Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 36
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 28
- Errors: 0
1 12:45:38.058639 lava-dispatcher, installed at version: 2023.05.1
2 12:45:38.058822 start: 0 validate
3 12:45:38.058946 Start time: 2023-06-14 12:45:38.058939+00:00 (UTC)
4 12:45:38.059065 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:45:38.059191 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 12:45:38.326060 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:45:38.326780 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:45:38.589625 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:45:38.590351 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:45:38.860109 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:45:38.860793 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:45:39.115018 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:45:39.115641 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:45:39.390335 validate duration: 1.33
16 12:45:39.391475 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:45:39.391958 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:45:39.392439 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:45:39.392993 Not decompressing ramdisk as can be used compressed.
20 12:45:39.393412 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230609.0/arm64/initrd.cpio.gz
21 12:45:39.393739 saving as /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/ramdisk/initrd.cpio.gz
22 12:45:39.394072 total size: 4665406 (4MB)
23 12:45:39.403664 progress 0% (0MB)
24 12:45:39.410761 progress 5% (0MB)
25 12:45:39.417229 progress 10% (0MB)
26 12:45:39.422422 progress 15% (0MB)
27 12:45:39.426226 progress 20% (0MB)
28 12:45:39.429598 progress 25% (1MB)
29 12:45:39.432274 progress 30% (1MB)
30 12:45:39.434892 progress 35% (1MB)
31 12:45:39.437206 progress 40% (1MB)
32 12:45:39.439689 progress 45% (2MB)
33 12:45:39.441594 progress 50% (2MB)
34 12:45:39.443491 progress 55% (2MB)
35 12:45:39.445283 progress 60% (2MB)
36 12:45:39.446948 progress 65% (2MB)
37 12:45:39.448619 progress 70% (3MB)
38 12:45:39.450182 progress 75% (3MB)
39 12:45:39.451664 progress 80% (3MB)
40 12:45:39.453351 progress 85% (3MB)
41 12:45:39.454809 progress 90% (4MB)
42 12:45:39.456163 progress 95% (4MB)
43 12:45:39.457522 progress 100% (4MB)
44 12:45:39.457690 4MB downloaded in 0.06s (69.93MB/s)
45 12:45:39.457853 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:45:39.458112 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:45:39.458207 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:45:39.458299 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:45:39.458439 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:45:39.458519 saving as /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/kernel/Image
52 12:45:39.458586 total size: 47581696 (45MB)
53 12:45:39.458651 No compression specified
54 12:45:39.459824 progress 0% (0MB)
55 12:45:39.471772 progress 5% (2MB)
56 12:45:39.483787 progress 10% (4MB)
57 12:45:39.495573 progress 15% (6MB)
58 12:45:39.507635 progress 20% (9MB)
59 12:45:39.519766 progress 25% (11MB)
60 12:45:39.531790 progress 30% (13MB)
61 12:45:39.544007 progress 35% (15MB)
62 12:45:39.555896 progress 40% (18MB)
63 12:45:39.568010 progress 45% (20MB)
64 12:45:39.580126 progress 50% (22MB)
65 12:45:39.592150 progress 55% (24MB)
66 12:45:39.604244 progress 60% (27MB)
67 12:45:39.616175 progress 65% (29MB)
68 12:45:39.628431 progress 70% (31MB)
69 12:45:39.640598 progress 75% (34MB)
70 12:45:39.652482 progress 80% (36MB)
71 12:45:39.664429 progress 85% (38MB)
72 12:45:39.676202 progress 90% (40MB)
73 12:45:39.687956 progress 95% (43MB)
74 12:45:39.699724 progress 100% (45MB)
75 12:45:39.699843 45MB downloaded in 0.24s (188.09MB/s)
76 12:45:39.699987 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:45:39.700261 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:45:39.700347 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:45:39.700435 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:45:39.700567 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:45:39.700636 saving as /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/dtb/mt8192-asurada-spherion-r0.dtb
83 12:45:39.700700 total size: 46924 (0MB)
84 12:45:39.700763 No compression specified
85 12:45:39.701864 progress 69% (0MB)
86 12:45:39.702134 progress 100% (0MB)
87 12:45:39.702285 0MB downloaded in 0.00s (28.28MB/s)
88 12:45:39.702402 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:45:39.702618 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:45:39.702701 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:45:39.702781 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:45:39.702888 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230609.0/arm64/full.rootfs.tar.xz
94 12:45:39.702953 saving as /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/nfsrootfs/full.rootfs.tar
95 12:45:39.703013 total size: 89385828 (85MB)
96 12:45:39.703075 Using unxz to decompress xz
97 12:45:39.707169 progress 0% (0MB)
98 12:45:39.917077 progress 5% (4MB)
99 12:45:40.135261 progress 10% (8MB)
100 12:45:40.390525 progress 15% (12MB)
101 12:45:40.584744 progress 20% (17MB)
102 12:45:40.679629 progress 25% (21MB)
103 12:45:40.931578 progress 30% (25MB)
104 12:45:41.215862 progress 35% (29MB)
105 12:45:41.481685 progress 40% (34MB)
106 12:45:41.742320 progress 45% (38MB)
107 12:45:41.991753 progress 50% (42MB)
108 12:45:42.255586 progress 55% (46MB)
109 12:45:42.511300 progress 60% (51MB)
110 12:45:42.783251 progress 65% (55MB)
111 12:45:43.083426 progress 70% (59MB)
112 12:45:43.389937 progress 75% (63MB)
113 12:45:43.688207 progress 80% (68MB)
114 12:45:43.943943 progress 85% (72MB)
115 12:45:44.175010 progress 90% (76MB)
116 12:45:44.433101 progress 95% (81MB)
117 12:45:44.697203 progress 100% (85MB)
118 12:45:44.703426 85MB downloaded in 5.00s (17.05MB/s)
119 12:45:44.703715 end: 1.4.1 http-download (duration 00:00:05) [common]
121 12:45:44.703976 end: 1.4 download-retry (duration 00:00:05) [common]
122 12:45:44.704071 start: 1.5 download-retry (timeout 00:09:55) [common]
123 12:45:44.704161 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 12:45:44.704347 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:45:44.704417 saving as /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/modules/modules.tar
126 12:45:44.704478 total size: 8536768 (8MB)
127 12:45:44.704540 Using unxz to decompress xz
128 12:45:44.707973 progress 0% (0MB)
129 12:45:44.728799 progress 5% (0MB)
130 12:45:44.755290 progress 10% (0MB)
131 12:45:44.785303 progress 15% (1MB)
132 12:45:44.808788 progress 20% (1MB)
133 12:45:44.831988 progress 25% (2MB)
134 12:45:44.856484 progress 30% (2MB)
135 12:45:44.880393 progress 35% (2MB)
136 12:45:44.906890 progress 40% (3MB)
137 12:45:44.931154 progress 45% (3MB)
138 12:45:44.956884 progress 50% (4MB)
139 12:45:44.981231 progress 55% (4MB)
140 12:45:45.005913 progress 60% (4MB)
141 12:45:45.030654 progress 65% (5MB)
142 12:45:45.055126 progress 70% (5MB)
143 12:45:45.078906 progress 75% (6MB)
144 12:45:45.102350 progress 80% (6MB)
145 12:45:45.125724 progress 85% (6MB)
146 12:45:45.150615 progress 90% (7MB)
147 12:45:45.174917 progress 95% (7MB)
148 12:45:45.197013 progress 100% (8MB)
149 12:45:45.203473 8MB downloaded in 0.50s (16.32MB/s)
150 12:45:45.203732 end: 1.5.1 http-download (duration 00:00:00) [common]
152 12:45:45.203995 end: 1.5 download-retry (duration 00:00:00) [common]
153 12:45:45.204097 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 12:45:45.204189 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 12:45:46.811339 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10724911/extract-nfsrootfs-0ljjj21m
156 12:45:46.811522 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:45:46.811623 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 12:45:46.811806 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n
159 12:45:46.811970 makedir: /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin
160 12:45:46.812247 makedir: /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/tests
161 12:45:46.812353 makedir: /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/results
162 12:45:46.812485 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-add-keys
163 12:45:46.812627 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-add-sources
164 12:45:46.812754 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-background-process-start
165 12:45:46.812879 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-background-process-stop
166 12:45:46.813001 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-common-functions
167 12:45:46.813131 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-echo-ipv4
168 12:45:46.813302 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-install-packages
169 12:45:46.813453 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-installed-packages
170 12:45:46.813578 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-os-build
171 12:45:46.813699 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-probe-channel
172 12:45:46.813819 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-probe-ip
173 12:45:46.813940 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-target-ip
174 12:45:46.814058 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-target-mac
175 12:45:46.814189 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-target-storage
176 12:45:46.814331 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-test-case
177 12:45:46.814472 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-test-event
178 12:45:46.814594 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-test-feedback
179 12:45:46.814715 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-test-raise
180 12:45:46.814834 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-test-reference
181 12:45:46.814954 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-test-runner
182 12:45:46.815084 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-test-set
183 12:45:46.815218 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-test-shell
184 12:45:46.815342 Updating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-install-packages (oe)
185 12:45:46.815489 Updating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/bin/lava-installed-packages (oe)
186 12:45:46.815608 Creating /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/environment
187 12:45:46.815702 LAVA metadata
188 12:45:46.815771 - LAVA_JOB_ID=10724911
189 12:45:46.815833 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:45:46.815931 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 12:45:46.815997 skipped lava-vland-overlay
192 12:45:46.816109 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:45:46.816188 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 12:45:46.816249 skipped lava-multinode-overlay
195 12:45:46.816321 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:45:46.816397 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 12:45:46.816468 Loading test definitions
198 12:45:46.816559 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 12:45:46.816629 Using /lava-10724911 at stage 0
200 12:45:46.816923 uuid=10724911_1.6.2.3.1 testdef=None
201 12:45:46.817030 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:45:46.817118 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 12:45:46.817586 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:45:46.817807 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 12:45:46.818404 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:45:46.818629 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 12:45:46.819242 runner path: /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/0/tests/0_lc-compliance test_uuid 10724911_1.6.2.3.1
210 12:45:46.819393 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:45:46.819595 Creating lava-test-runner.conf files
213 12:45:46.819658 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724911/lava-overlay-0zoqa06n/lava-10724911/0 for stage 0
214 12:45:46.819745 - 0_lc-compliance
215 12:45:46.819840 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 12:45:46.819924 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 12:45:46.825804 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 12:45:46.825905 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 12:45:46.825998 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 12:45:46.826084 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 12:45:46.826168 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 12:45:46.940488 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 12:45:46.940851 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 12:45:46.941010 extracting modules file /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724911/extract-nfsrootfs-0ljjj21m
225 12:45:47.149382 extracting modules file /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724911/extract-overlay-ramdisk-323b4m2u/ramdisk
226 12:45:47.366881 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 12:45:47.367049 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 12:45:47.367143 [common] Applying overlay to NFS
229 12:45:47.367216 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724911/compress-overlay-5txrji8d/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724911/extract-nfsrootfs-0ljjj21m
230 12:45:47.373950 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 12:45:47.374063 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 12:45:47.374154 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 12:45:47.374259 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 12:45:47.374347 Building ramdisk /var/lib/lava/dispatcher/tmp/10724911/extract-overlay-ramdisk-323b4m2u/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724911/extract-overlay-ramdisk-323b4m2u/ramdisk
235 12:45:47.683488 >> 117806 blocks
236 12:45:49.590997 rename /var/lib/lava/dispatcher/tmp/10724911/extract-overlay-ramdisk-323b4m2u/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/ramdisk/ramdisk.cpio.gz
237 12:45:49.591407 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 12:45:49.591577 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 12:45:49.591698 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 12:45:49.591807 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/kernel/Image'
241 12:46:01.480723 Returned 0 in 11 seconds
242 12:46:01.581300 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/kernel/image.itb
243 12:46:01.915707 output: FIT description: Kernel Image image with one or more FDT blobs
244 12:46:01.916095 output: Created: Wed Jun 14 13:46:01 2023
245 12:46:01.916207 output: Image 0 (kernel-1)
246 12:46:01.916303 output: Description:
247 12:46:01.916398 output: Created: Wed Jun 14 13:46:01 2023
248 12:46:01.916479 output: Type: Kernel Image
249 12:46:01.916544 output: Compression: lzma compressed
250 12:46:01.916604 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
251 12:46:01.916664 output: Architecture: AArch64
252 12:46:01.916724 output: OS: Linux
253 12:46:01.916782 output: Load Address: 0x00000000
254 12:46:01.916838 output: Entry Point: 0x00000000
255 12:46:01.916895 output: Hash algo: crc32
256 12:46:01.916950 output: Hash value: ced21bfe
257 12:46:01.917003 output: Image 1 (fdt-1)
258 12:46:01.917057 output: Description: mt8192-asurada-spherion-r0
259 12:46:01.917118 output: Created: Wed Jun 14 13:46:01 2023
260 12:46:01.917172 output: Type: Flat Device Tree
261 12:46:01.917224 output: Compression: uncompressed
262 12:46:01.917277 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 12:46:01.917330 output: Architecture: AArch64
264 12:46:01.917383 output: Hash algo: crc32
265 12:46:01.917435 output: Hash value: 1df858fa
266 12:46:01.917487 output: Image 2 (ramdisk-1)
267 12:46:01.917540 output: Description: unavailable
268 12:46:01.917593 output: Created: Wed Jun 14 13:46:01 2023
269 12:46:01.917646 output: Type: RAMDisk Image
270 12:46:01.917699 output: Compression: Unknown Compression
271 12:46:01.917751 output: Data Size: 17639001 Bytes = 17225.59 KiB = 16.82 MiB
272 12:46:01.917805 output: Architecture: AArch64
273 12:46:01.917857 output: OS: Linux
274 12:46:01.917909 output: Load Address: unavailable
275 12:46:01.917962 output: Entry Point: unavailable
276 12:46:01.918014 output: Hash algo: crc32
277 12:46:01.918066 output: Hash value: b0a694e3
278 12:46:01.918118 output: Default Configuration: 'conf-1'
279 12:46:01.918170 output: Configuration 0 (conf-1)
280 12:46:01.918223 output: Description: mt8192-asurada-spherion-r0
281 12:46:01.918275 output: Kernel: kernel-1
282 12:46:01.918327 output: Init Ramdisk: ramdisk-1
283 12:46:01.918379 output: FDT: fdt-1
284 12:46:01.918431 output: Loadables: kernel-1
285 12:46:01.918483 output:
286 12:46:01.918679 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
287 12:46:01.918783 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
288 12:46:01.918889 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
289 12:46:01.918981 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 12:46:01.919060 No LXC device requested
291 12:46:01.919138 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 12:46:01.919223 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 12:46:01.919300 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 12:46:01.919369 Checking files for TFTP limit of 4294967296 bytes.
295 12:46:01.919854 end: 1 tftp-deploy (duration 00:00:23) [common]
296 12:46:01.919958 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 12:46:01.920079 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 12:46:01.920222 substitutions:
299 12:46:01.920291 - {DTB}: 10724911/tftp-deploy-q4vik08t/dtb/mt8192-asurada-spherion-r0.dtb
300 12:46:01.920358 - {INITRD}: 10724911/tftp-deploy-q4vik08t/ramdisk/ramdisk.cpio.gz
301 12:46:01.920418 - {KERNEL}: 10724911/tftp-deploy-q4vik08t/kernel/Image
302 12:46:01.920476 - {LAVA_MAC}: None
303 12:46:01.920533 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10724911/extract-nfsrootfs-0ljjj21m
304 12:46:01.920589 - {NFS_SERVER_IP}: 192.168.201.1
305 12:46:01.920644 - {PRESEED_CONFIG}: None
306 12:46:01.920699 - {PRESEED_LOCAL}: None
307 12:46:01.920754 - {RAMDISK}: 10724911/tftp-deploy-q4vik08t/ramdisk/ramdisk.cpio.gz
308 12:46:01.920809 - {ROOT_PART}: None
309 12:46:01.920863 - {ROOT}: None
310 12:46:01.920916 - {SERVER_IP}: 192.168.201.1
311 12:46:01.920970 - {TEE}: None
312 12:46:01.921023 Parsed boot commands:
313 12:46:01.921077 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 12:46:01.921253 Parsed boot commands: tftpboot 192.168.201.1 10724911/tftp-deploy-q4vik08t/kernel/image.itb 10724911/tftp-deploy-q4vik08t/kernel/cmdline
315 12:46:01.921342 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 12:46:01.921433 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 12:46:01.921527 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 12:46:01.921614 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 12:46:01.921683 Not connected, no need to disconnect.
320 12:46:01.921756 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 12:46:01.921837 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 12:46:01.921906 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
323 12:46:01.925218 Setting prompt string to ['lava-test: # ']
324 12:46:01.925563 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 12:46:01.925671 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 12:46:01.925767 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 12:46:01.925860 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 12:46:01.926053 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
329 12:46:07.073886 >> Command sent successfully.
330 12:46:07.083963 Returned 0 in 5 seconds
331 12:46:07.185190 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 12:46:07.186685 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 12:46:07.187246 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 12:46:07.187730 Setting prompt string to 'Starting depthcharge on Spherion...'
336 12:46:07.188267 Changing prompt to 'Starting depthcharge on Spherion...'
337 12:46:07.188723 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 12:46:07.190046 [Enter `^Ec?' for help]
339 12:46:07.352810
340 12:46:07.353340
341 12:46:07.353703 F0: 102B 0000
342 12:46:07.354026
343 12:46:07.354332 F3: 1001 0000 [0200]
344 12:46:07.354635
345 12:46:07.356360 F3: 1001 0000
346 12:46:07.356831
347 12:46:07.357358 F7: 102D 0000
348 12:46:07.357751
349 12:46:07.359739 F1: 0000 0000
350 12:46:07.360308
351 12:46:07.360671 V0: 0000 0000 [0001]
352 12:46:07.361072
353 12:46:07.361388 00: 0007 8000
354 12:46:07.363972
355 12:46:07.364552 01: 0000 0000
356 12:46:07.365087
357 12:46:07.365588 BP: 0C00 0209 [0000]
358 12:46:07.366068
359 12:46:07.367624 G0: 1182 0000
360 12:46:07.368266
361 12:46:07.368706 EC: 0000 0021 [4000]
362 12:46:07.369079
363 12:46:07.371352 S7: 0000 0000 [0000]
364 12:46:07.371903
365 12:46:07.372411 CC: 0000 0000 [0001]
366 12:46:07.372797
367 12:46:07.374029 T0: 0000 0040 [010F]
368 12:46:07.374693
369 12:46:07.375090 Jump to BL
370 12:46:07.375461
371 12:46:07.400207
372 12:46:07.400711
373 12:46:07.401082
374 12:46:07.408015 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 12:46:07.411179 ARM64: Exception handlers installed.
376 12:46:07.414837 ARM64: Testing exception
377 12:46:07.418676 ARM64: Done test exception
378 12:46:07.426211 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 12:46:07.433093 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 12:46:07.439873 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 12:46:07.450826 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 12:46:07.457230 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 12:46:07.467224 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 12:46:07.477995 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 12:46:07.484471 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 12:46:07.503083 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 12:46:07.505908 WDT: Last reset was cold boot
388 12:46:07.509701 SPI1(PAD0) initialized at 2873684 Hz
389 12:46:07.512944 SPI5(PAD0) initialized at 992727 Hz
390 12:46:07.516027 VBOOT: Loading verstage.
391 12:46:07.522035 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 12:46:07.526149 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 12:46:07.528976 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 12:46:07.532551 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 12:46:07.540188 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 12:46:07.546899 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 12:46:07.557561 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 12:46:07.557997
399 12:46:07.558335
400 12:46:07.567409 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 12:46:07.571062 ARM64: Exception handlers installed.
402 12:46:07.574343 ARM64: Testing exception
403 12:46:07.574772 ARM64: Done test exception
404 12:46:07.581659 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 12:46:07.584915 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 12:46:07.599177 Probing TPM: . done!
407 12:46:07.599640 TPM ready after 0 ms
408 12:46:07.606093 Connected to device vid:did:rid of 1ae0:0028:00
409 12:46:07.612788 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
410 12:46:07.670882 Initialized TPM device CR50 revision 0
411 12:46:07.682666 tlcl_send_startup: Startup return code is 0
412 12:46:07.683158 TPM: setup succeeded
413 12:46:07.694541 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 12:46:07.702997 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 12:46:07.716819 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 12:46:07.724006 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 12:46:07.727449 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 12:46:07.733186 in-header: 03 07 00 00 08 00 00 00
419 12:46:07.737252 in-data: aa e4 47 04 13 02 00 00
420 12:46:07.741195 Chrome EC: UHEPI supported
421 12:46:07.748344 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 12:46:07.752409 in-header: 03 95 00 00 08 00 00 00
423 12:46:07.752862 in-data: 18 20 20 08 00 00 00 00
424 12:46:07.755909 Phase 1
425 12:46:07.759237 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 12:46:07.762833 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 12:46:07.769917 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 12:46:07.773483 Recovery requested (1009000e)
429 12:46:07.781798 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 12:46:07.787210 tlcl_extend: response is 0
431 12:46:07.796586 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 12:46:07.802597 tlcl_extend: response is 0
433 12:46:07.809282 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 12:46:07.828963 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 12:46:07.835534 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 12:46:07.835962
437 12:46:07.836331
438 12:46:07.845632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 12:46:07.848779 ARM64: Exception handlers installed.
440 12:46:07.852115 ARM64: Testing exception
441 12:46:07.852547 ARM64: Done test exception
442 12:46:07.874379 pmic_efuse_setting: Set efuses in 11 msecs
443 12:46:07.877724 pmwrap_interface_init: Select PMIF_VLD_RDY
444 12:46:07.884179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 12:46:07.887693 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 12:46:07.894288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 12:46:07.897808 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 12:46:07.901143 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 12:46:07.908451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 12:46:07.911887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 12:46:07.915697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 12:46:07.922904 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 12:46:07.926455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 12:46:07.930756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 12:46:07.933662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 12:46:07.941418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 12:46:07.945080 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 12:46:07.952928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 12:46:07.960340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 12:46:07.963387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 12:46:07.970860 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 12:46:07.974496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 12:46:07.982465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 12:46:07.985672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 12:46:07.993050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 12:46:07.996921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 12:46:08.004298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 12:46:08.007962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 12:46:08.014882 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 12:46:08.019167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 12:46:08.022222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 12:46:08.029727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 12:46:08.033344 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 12:46:08.037142 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 12:46:08.044373 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 12:46:08.047895 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 12:46:08.055384 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 12:46:08.058405 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 12:46:08.062255 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 12:46:08.069833 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 12:46:08.073913 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 12:46:08.077296 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 12:46:08.081228 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 12:46:08.088615 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 12:46:08.091913 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 12:46:08.095793 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 12:46:08.099206 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 12:46:08.103265 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 12:46:08.110477 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 12:46:08.114098 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 12:46:08.117637 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 12:46:08.121409 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 12:46:08.125055 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 12:46:08.128471 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 12:46:08.135789 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 12:46:08.147248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 12:46:08.150733 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 12:46:08.157735 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 12:46:08.165223 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 12:46:08.173194 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 12:46:08.176516 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 12:46:08.180168 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 12:46:08.187646 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
504 12:46:08.191166 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 12:46:08.199208 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
506 12:46:08.202104 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 12:46:08.211808 [RTC]rtc_get_frequency_meter,154: input=15, output=852
508 12:46:08.221492 [RTC]rtc_get_frequency_meter,154: input=7, output=723
509 12:46:08.230620 [RTC]rtc_get_frequency_meter,154: input=11, output=789
510 12:46:08.240321 [RTC]rtc_get_frequency_meter,154: input=13, output=820
511 12:46:08.249654 [RTC]rtc_get_frequency_meter,154: input=12, output=804
512 12:46:08.259390 [RTC]rtc_get_frequency_meter,154: input=11, output=788
513 12:46:08.269603 [RTC]rtc_get_frequency_meter,154: input=12, output=804
514 12:46:08.272762 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
515 12:46:08.276906 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
516 12:46:08.283766 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 12:46:08.287394 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 12:46:08.291266 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 12:46:08.294681 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 12:46:08.298153 ADC[4]: Raw value=904433 ID=7
521 12:46:08.302321 ADC[3]: Raw value=213546 ID=1
522 12:46:08.302799 RAM Code: 0x71
523 12:46:08.305957 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 12:46:08.313668 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 12:46:08.320760 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 12:46:08.327549 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 12:46:08.331329 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 12:46:08.334641 in-header: 03 07 00 00 08 00 00 00
529 12:46:08.335124 in-data: aa e4 47 04 13 02 00 00
530 12:46:08.338843 Chrome EC: UHEPI supported
531 12:46:08.346325 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 12:46:08.349917 in-header: 03 95 00 00 08 00 00 00
533 12:46:08.353025 in-data: 18 20 20 08 00 00 00 00
534 12:46:08.356941 MRC: failed to locate region type 0.
535 12:46:08.364684 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 12:46:08.365113 DRAM-K: Running full calibration
537 12:46:08.371576 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 12:46:08.375663 header.status = 0x0
539 12:46:08.376169 header.version = 0x6 (expected: 0x6)
540 12:46:08.379475 header.size = 0xd00 (expected: 0xd00)
541 12:46:08.382763 header.flags = 0x0
542 12:46:08.389704 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 12:46:08.406167 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
544 12:46:08.413941 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 12:46:08.414372 dram_init: ddr_geometry: 2
546 12:46:08.417533 [EMI] MDL number = 2
547 12:46:08.421385 [EMI] Get MDL freq = 0
548 12:46:08.421885 dram_init: ddr_type: 0
549 12:46:08.425172 is_discrete_lpddr4: 1
550 12:46:08.425649 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 12:46:08.428634
552 12:46:08.429064
553 12:46:08.429408 [Bian_co] ETT version 0.0.0.1
554 12:46:08.435942 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 12:46:08.436455
556 12:46:08.439815 dramc_set_vcore_voltage set vcore to 650000
557 12:46:08.440353 Read voltage for 800, 4
558 12:46:08.443600 Vio18 = 0
559 12:46:08.444187 Vcore = 650000
560 12:46:08.444599 Vdram = 0
561 12:46:08.444933 Vddq = 0
562 12:46:08.447111 Vmddr = 0
563 12:46:08.447567 dram_init: config_dvfs: 1
564 12:46:08.454155 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 12:46:08.457285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 12:46:08.460662 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 12:46:08.464119 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 12:46:08.471327 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 12:46:08.475022 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 12:46:08.475494 MEM_TYPE=3, freq_sel=18
571 12:46:08.478404 sv_algorithm_assistance_LP4_1600
572 12:46:08.482259 ============ PULL DRAM RESETB DOWN ============
573 12:46:08.486074 ========== PULL DRAM RESETB DOWN end =========
574 12:46:08.492984 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 12:46:08.496688 ===================================
576 12:46:08.497117 LPDDR4 DRAM CONFIGURATION
577 12:46:08.499607 ===================================
578 12:46:08.503438 EX_ROW_EN[0] = 0x0
579 12:46:08.503863 EX_ROW_EN[1] = 0x0
580 12:46:08.506699 LP4Y_EN = 0x0
581 12:46:08.507124 WORK_FSP = 0x0
582 12:46:08.509716 WL = 0x2
583 12:46:08.513203 RL = 0x2
584 12:46:08.513632 BL = 0x2
585 12:46:08.516192 RPST = 0x0
586 12:46:08.516621 RD_PRE = 0x0
587 12:46:08.519556 WR_PRE = 0x1
588 12:46:08.519983 WR_PST = 0x0
589 12:46:08.523108 DBI_WR = 0x0
590 12:46:08.523534 DBI_RD = 0x0
591 12:46:08.526296 OTF = 0x1
592 12:46:08.529500 ===================================
593 12:46:08.533146 ===================================
594 12:46:08.533571 ANA top config
595 12:46:08.536187 ===================================
596 12:46:08.539470 DLL_ASYNC_EN = 0
597 12:46:08.542973 ALL_SLAVE_EN = 1
598 12:46:08.543401 NEW_RANK_MODE = 1
599 12:46:08.546161 DLL_IDLE_MODE = 1
600 12:46:08.549738 LP45_APHY_COMB_EN = 1
601 12:46:08.552978 TX_ODT_DIS = 1
602 12:46:08.553404 NEW_8X_MODE = 1
603 12:46:08.556550 ===================================
604 12:46:08.559487 ===================================
605 12:46:08.563180 data_rate = 1600
606 12:46:08.566444 CKR = 1
607 12:46:08.569534 DQ_P2S_RATIO = 8
608 12:46:08.573055 ===================================
609 12:46:08.577189 CA_P2S_RATIO = 8
610 12:46:08.577614 DQ_CA_OPEN = 0
611 12:46:08.580516 DQ_SEMI_OPEN = 0
612 12:46:08.583754 CA_SEMI_OPEN = 0
613 12:46:08.587193 CA_FULL_RATE = 0
614 12:46:08.590604 DQ_CKDIV4_EN = 1
615 12:46:08.591031 CA_CKDIV4_EN = 1
616 12:46:08.593823 CA_PREDIV_EN = 0
617 12:46:08.597603 PH8_DLY = 0
618 12:46:08.600429 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 12:46:08.603798 DQ_AAMCK_DIV = 4
620 12:46:08.607235 CA_AAMCK_DIV = 4
621 12:46:08.607666 CA_ADMCK_DIV = 4
622 12:46:08.610734 DQ_TRACK_CA_EN = 0
623 12:46:08.613836 CA_PICK = 800
624 12:46:08.617526 CA_MCKIO = 800
625 12:46:08.620140 MCKIO_SEMI = 0
626 12:46:08.624012 PLL_FREQ = 3068
627 12:46:08.627995 DQ_UI_PI_RATIO = 32
628 12:46:08.628468 CA_UI_PI_RATIO = 0
629 12:46:08.631389 ===================================
630 12:46:08.635162 ===================================
631 12:46:08.638765 memory_type:LPDDR4
632 12:46:08.639256 GP_NUM : 10
633 12:46:08.642329 SRAM_EN : 1
634 12:46:08.642758 MD32_EN : 0
635 12:46:08.646087 ===================================
636 12:46:08.649728 [ANA_INIT] >>>>>>>>>>>>>>
637 12:46:08.653033 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 12:46:08.656992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 12:46:08.660682 ===================================
640 12:46:08.661115 data_rate = 1600,PCW = 0X7600
641 12:46:08.663726 ===================================
642 12:46:08.667326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 12:46:08.674141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 12:46:08.680547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 12:46:08.683797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 12:46:08.687084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 12:46:08.690430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 12:46:08.694092 [ANA_INIT] flow start
649 12:46:08.694706 [ANA_INIT] PLL >>>>>>>>
650 12:46:08.697529 [ANA_INIT] PLL <<<<<<<<
651 12:46:08.700824 [ANA_INIT] MIDPI >>>>>>>>
652 12:46:08.704400 [ANA_INIT] MIDPI <<<<<<<<
653 12:46:08.704853 [ANA_INIT] DLL >>>>>>>>
654 12:46:08.707078 [ANA_INIT] flow end
655 12:46:08.710376 ============ LP4 DIFF to SE enter ============
656 12:46:08.713867 ============ LP4 DIFF to SE exit ============
657 12:46:08.717131 [ANA_INIT] <<<<<<<<<<<<<
658 12:46:08.720714 [Flow] Enable top DCM control >>>>>
659 12:46:08.723607 [Flow] Enable top DCM control <<<<<
660 12:46:08.726990 Enable DLL master slave shuffle
661 12:46:08.733883 ==============================================================
662 12:46:08.734344 Gating Mode config
663 12:46:08.740512 ==============================================================
664 12:46:08.740965 Config description:
665 12:46:08.750178 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 12:46:08.756448 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 12:46:08.763023 SELPH_MODE 0: By rank 1: By Phase
668 12:46:08.766605 ==============================================================
669 12:46:08.769765 GAT_TRACK_EN = 1
670 12:46:08.773234 RX_GATING_MODE = 2
671 12:46:08.776359 RX_GATING_TRACK_MODE = 2
672 12:46:08.779680 SELPH_MODE = 1
673 12:46:08.782782 PICG_EARLY_EN = 1
674 12:46:08.786382 VALID_LAT_VALUE = 1
675 12:46:08.793387 ==============================================================
676 12:46:08.796386 Enter into Gating configuration >>>>
677 12:46:08.799540 Exit from Gating configuration <<<<
678 12:46:08.802735 Enter into DVFS_PRE_config >>>>>
679 12:46:08.813166 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 12:46:08.816470 Exit from DVFS_PRE_config <<<<<
681 12:46:08.819900 Enter into PICG configuration >>>>
682 12:46:08.822820 Exit from PICG configuration <<<<
683 12:46:08.826577 [RX_INPUT] configuration >>>>>
684 12:46:08.827013 [RX_INPUT] configuration <<<<<
685 12:46:08.833341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 12:46:08.839163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 12:46:08.843374 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 12:46:08.849198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 12:46:08.855985 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 12:46:08.862273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 12:46:08.865884 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 12:46:08.869219 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 12:46:08.875876 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 12:46:08.879010 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 12:46:08.882424 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 12:46:08.888888 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:46:08.892440 ===================================
698 12:46:08.892932 LPDDR4 DRAM CONFIGURATION
699 12:46:08.895670 ===================================
700 12:46:08.898731 EX_ROW_EN[0] = 0x0
701 12:46:08.899293 EX_ROW_EN[1] = 0x0
702 12:46:08.902522 LP4Y_EN = 0x0
703 12:46:08.905377 WORK_FSP = 0x0
704 12:46:08.905853 WL = 0x2
705 12:46:08.909029 RL = 0x2
706 12:46:08.909517 BL = 0x2
707 12:46:08.911992 RPST = 0x0
708 12:46:08.912521 RD_PRE = 0x0
709 12:46:08.915131 WR_PRE = 0x1
710 12:46:08.915582 WR_PST = 0x0
711 12:46:08.919318 DBI_WR = 0x0
712 12:46:08.919782 DBI_RD = 0x0
713 12:46:08.921816 OTF = 0x1
714 12:46:08.925318 ===================================
715 12:46:08.928689 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 12:46:08.931912 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 12:46:08.935901 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 12:46:08.938942 ===================================
719 12:46:08.942549 LPDDR4 DRAM CONFIGURATION
720 12:46:08.945731 ===================================
721 12:46:08.948822 EX_ROW_EN[0] = 0x10
722 12:46:08.949290 EX_ROW_EN[1] = 0x0
723 12:46:08.952553 LP4Y_EN = 0x0
724 12:46:08.953047 WORK_FSP = 0x0
725 12:46:08.955353 WL = 0x2
726 12:46:08.955904 RL = 0x2
727 12:46:08.958409 BL = 0x2
728 12:46:08.962134 RPST = 0x0
729 12:46:08.962722 RD_PRE = 0x0
730 12:46:08.965166 WR_PRE = 0x1
731 12:46:08.965657 WR_PST = 0x0
732 12:46:08.968222 DBI_WR = 0x0
733 12:46:08.968654 DBI_RD = 0x0
734 12:46:08.972094 OTF = 0x1
735 12:46:08.975193 ===================================
736 12:46:08.978419 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 12:46:08.983883 nWR fixed to 40
738 12:46:08.987369 [ModeRegInit_LP4] CH0 RK0
739 12:46:08.987830 [ModeRegInit_LP4] CH0 RK1
740 12:46:08.990303 [ModeRegInit_LP4] CH1 RK0
741 12:46:08.993719 [ModeRegInit_LP4] CH1 RK1
742 12:46:08.994143 match AC timing 13
743 12:46:09.000388 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 12:46:09.003755 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 12:46:09.006983 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 12:46:09.014037 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 12:46:09.017239 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 12:46:09.020528 [EMI DOE] emi_dcm 0
749 12:46:09.023759 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 12:46:09.024183 ==
751 12:46:09.027317 Dram Type= 6, Freq= 0, CH_0, rank 0
752 12:46:09.030324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 12:46:09.030711 ==
754 12:46:09.036882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 12:46:09.043281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 12:46:09.051616 [CA 0] Center 37 (7~68) winsize 62
757 12:46:09.055233 [CA 1] Center 37 (6~68) winsize 63
758 12:46:09.057729 [CA 2] Center 34 (4~65) winsize 62
759 12:46:09.061537 [CA 3] Center 35 (4~66) winsize 63
760 12:46:09.064647 [CA 4] Center 33 (3~64) winsize 62
761 12:46:09.067816 [CA 5] Center 33 (3~64) winsize 62
762 12:46:09.068230
763 12:46:09.071166 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 12:46:09.071549
765 12:46:09.074309 [CATrainingPosCal] consider 1 rank data
766 12:46:09.078322 u2DelayCellTimex100 = 270/100 ps
767 12:46:09.081521 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 12:46:09.087717 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
769 12:46:09.091176 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 12:46:09.094697 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
771 12:46:09.098243 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 12:46:09.101162 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 12:46:09.101776
774 12:46:09.104560 CA PerBit enable=1, Macro0, CA PI delay=33
775 12:46:09.105031
776 12:46:09.108101 [CBTSetCACLKResult] CA Dly = 33
777 12:46:09.108569 CS Dly: 5 (0~36)
778 12:46:09.111233 ==
779 12:46:09.114400 Dram Type= 6, Freq= 0, CH_0, rank 1
780 12:46:09.117703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 12:46:09.118204 ==
782 12:46:09.120968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 12:46:09.127941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 12:46:09.138028 [CA 0] Center 38 (7~69) winsize 63
785 12:46:09.140817 [CA 1] Center 37 (7~68) winsize 62
786 12:46:09.144437 [CA 2] Center 35 (4~66) winsize 63
787 12:46:09.147554 [CA 3] Center 35 (4~66) winsize 63
788 12:46:09.150861 [CA 4] Center 34 (3~65) winsize 63
789 12:46:09.154895 [CA 5] Center 33 (3~64) winsize 62
790 12:46:09.155453
791 12:46:09.157480 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 12:46:09.157977
793 12:46:09.160661 [CATrainingPosCal] consider 2 rank data
794 12:46:09.164443 u2DelayCellTimex100 = 270/100 ps
795 12:46:09.167690 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 12:46:09.174241 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 12:46:09.177622 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 12:46:09.180763 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
799 12:46:09.183999 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 12:46:09.187270 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 12:46:09.187869
802 12:46:09.190691 CA PerBit enable=1, Macro0, CA PI delay=33
803 12:46:09.191264
804 12:46:09.194478 [CBTSetCACLKResult] CA Dly = 33
805 12:46:09.197593 CS Dly: 5 (0~37)
806 12:46:09.198082
807 12:46:09.200318 ----->DramcWriteLeveling(PI) begin...
808 12:46:09.200819 ==
809 12:46:09.203823 Dram Type= 6, Freq= 0, CH_0, rank 0
810 12:46:09.207425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:46:09.207989 ==
812 12:46:09.211334 Write leveling (Byte 0): 34 => 34
813 12:46:09.214868 Write leveling (Byte 1): 28 => 28
814 12:46:09.215178 DramcWriteLeveling(PI) end<-----
815 12:46:09.215388
816 12:46:09.218141 ==
817 12:46:09.218441 Dram Type= 6, Freq= 0, CH_0, rank 0
818 12:46:09.225096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 12:46:09.225311 ==
820 12:46:09.228056 [Gating] SW mode calibration
821 12:46:09.235244 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 12:46:09.238636 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 12:46:09.242286 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 12:46:09.248837 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 12:46:09.251608 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 12:46:09.255003 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:46:09.262209 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:46:09.264849 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:46:09.268761 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:46:09.274948 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:46:09.278696 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 12:46:09.281479 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 12:46:09.288332 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 12:46:09.291821 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 12:46:09.295139 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 12:46:09.301617 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 12:46:09.304770 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 12:46:09.308122 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:46:09.315235 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 12:46:09.318587 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
841 12:46:09.321466 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 12:46:09.328285 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:46:09.331873 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:46:09.334899 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:46:09.342020 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 12:46:09.344772 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 12:46:09.348694 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 12:46:09.352175 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 12:46:09.358657 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
850 12:46:09.361781 0 9 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
851 12:46:09.365564 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 12:46:09.371789 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 12:46:09.375016 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 12:46:09.378080 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 12:46:09.384798 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 12:46:09.388319 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
857 12:46:09.391665 0 10 8 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 0)
858 12:46:09.398451 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
859 12:46:09.401611 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:46:09.405058 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:46:09.411406 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:46:09.415094 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:46:09.417912 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:46:09.424713 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
865 12:46:09.427736 0 11 8 | B1->B0 | 2929 3f3f | 1 0 | (0 0) (0 0)
866 12:46:09.431367 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
867 12:46:09.438119 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 12:46:09.441212 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 12:46:09.444375 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 12:46:09.450651 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 12:46:09.454097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 12:46:09.457415 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 12:46:09.464386 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 12:46:09.467622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 12:46:09.471033 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 12:46:09.477781 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 12:46:09.481320 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 12:46:09.484403 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 12:46:09.491057 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 12:46:09.493980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 12:46:09.497911 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 12:46:09.504447 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 12:46:09.507516 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 12:46:09.510566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 12:46:09.517225 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 12:46:09.520335 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 12:46:09.524346 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 12:46:09.530771 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 12:46:09.533655 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
890 12:46:09.536818 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 12:46:09.540538 Total UI for P1: 0, mck2ui 16
892 12:46:09.543307 best dqsien dly found for B0: ( 0, 14, 8)
893 12:46:09.547178 Total UI for P1: 0, mck2ui 16
894 12:46:09.550361 best dqsien dly found for B1: ( 0, 14, 8)
895 12:46:09.553449 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
896 12:46:09.556759 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
897 12:46:09.556896
898 12:46:09.560290 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 12:46:09.566808 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
900 12:46:09.566906 [Gating] SW calibration Done
901 12:46:09.566980 ==
902 12:46:09.570008 Dram Type= 6, Freq= 0, CH_0, rank 0
903 12:46:09.577531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 12:46:09.577609 ==
905 12:46:09.577674 RX Vref Scan: 0
906 12:46:09.577736
907 12:46:09.580212 RX Vref 0 -> 0, step: 1
908 12:46:09.580285
909 12:46:09.583839 RX Delay -130 -> 252, step: 16
910 12:46:09.587354 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 12:46:09.590389 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 12:46:09.593678 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 12:46:09.596949 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 12:46:09.604385 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
915 12:46:09.607332 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
916 12:46:09.610406 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 12:46:09.613644 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
918 12:46:09.617408 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
919 12:46:09.623597 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
920 12:46:09.627707 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 12:46:09.630436 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 12:46:09.634108 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
923 12:46:09.637001 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
924 12:46:09.643560 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 12:46:09.648091 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 12:46:09.648332 ==
927 12:46:09.650269 Dram Type= 6, Freq= 0, CH_0, rank 0
928 12:46:09.653647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 12:46:09.653960 ==
930 12:46:09.657061 DQS Delay:
931 12:46:09.657461 DQS0 = 0, DQS1 = 0
932 12:46:09.657796 DQM Delay:
933 12:46:09.660746 DQM0 = 88, DQM1 = 74
934 12:46:09.661138 DQ Delay:
935 12:46:09.663587 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 12:46:09.667027 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
937 12:46:09.670209 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
938 12:46:09.673733 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
939 12:46:09.674124
940 12:46:09.674481
941 12:46:09.674790 ==
942 12:46:09.676787 Dram Type= 6, Freq= 0, CH_0, rank 0
943 12:46:09.683771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 12:46:09.684230 ==
945 12:46:09.684562
946 12:46:09.684909
947 12:46:09.685208 TX Vref Scan disable
948 12:46:09.687282 == TX Byte 0 ==
949 12:46:09.690701 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
950 12:46:09.698049 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
951 12:46:09.698483 == TX Byte 1 ==
952 12:46:09.701271 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
953 12:46:09.707102 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
954 12:46:09.707601 ==
955 12:46:09.710960 Dram Type= 6, Freq= 0, CH_0, rank 0
956 12:46:09.713794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 12:46:09.714487 ==
958 12:46:09.727014 TX Vref=22, minBit 1, minWin=27, winSum=440
959 12:46:09.730454 TX Vref=24, minBit 0, minWin=27, winSum=442
960 12:46:09.733839 TX Vref=26, minBit 4, minWin=27, winSum=446
961 12:46:09.737301 TX Vref=28, minBit 5, minWin=27, winSum=451
962 12:46:09.740756 TX Vref=30, minBit 4, minWin=27, winSum=450
963 12:46:09.743483 TX Vref=32, minBit 8, minWin=27, winSum=448
964 12:46:09.750194 [TxChooseVref] Worse bit 5, Min win 27, Win sum 451, Final Vref 28
965 12:46:09.750625
966 12:46:09.753674 Final TX Range 1 Vref 28
967 12:46:09.754099
968 12:46:09.754434 ==
969 12:46:09.757684 Dram Type= 6, Freq= 0, CH_0, rank 0
970 12:46:09.760078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 12:46:09.760511 ==
972 12:46:09.760849
973 12:46:09.763768
974 12:46:09.764359 TX Vref Scan disable
975 12:46:09.767294 == TX Byte 0 ==
976 12:46:09.770846 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
977 12:46:09.776916 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
978 12:46:09.777331 == TX Byte 1 ==
979 12:46:09.780357 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
980 12:46:09.787314 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
981 12:46:09.787620
982 12:46:09.787857 [DATLAT]
983 12:46:09.788100 Freq=800, CH0 RK0
984 12:46:09.788318
985 12:46:09.789976 DATLAT Default: 0xa
986 12:46:09.790389 0, 0xFFFF, sum = 0
987 12:46:09.793830 1, 0xFFFF, sum = 0
988 12:46:09.796889 2, 0xFFFF, sum = 0
989 12:46:09.797201 3, 0xFFFF, sum = 0
990 12:46:09.800412 4, 0xFFFF, sum = 0
991 12:46:09.800718 5, 0xFFFF, sum = 0
992 12:46:09.803498 6, 0xFFFF, sum = 0
993 12:46:09.803803 7, 0xFFFF, sum = 0
994 12:46:09.806574 8, 0xFFFF, sum = 0
995 12:46:09.806658 9, 0x0, sum = 1
996 12:46:09.810255 10, 0x0, sum = 2
997 12:46:09.810339 11, 0x0, sum = 3
998 12:46:09.810406 12, 0x0, sum = 4
999 12:46:09.813227 best_step = 10
1000 12:46:09.813309
1001 12:46:09.813404 ==
1002 12:46:09.816853 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 12:46:09.819786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 12:46:09.819872 ==
1005 12:46:09.823272 RX Vref Scan: 1
1006 12:46:09.823384
1007 12:46:09.826727 Set Vref Range= 32 -> 127
1008 12:46:09.826831
1009 12:46:09.826925 RX Vref 32 -> 127, step: 1
1010 12:46:09.827014
1011 12:46:09.829991 RX Delay -111 -> 252, step: 8
1012 12:46:09.830088
1013 12:46:09.833583 Set Vref, RX VrefLevel [Byte0]: 32
1014 12:46:09.836621 [Byte1]: 32
1015 12:46:09.839875
1016 12:46:09.839973 Set Vref, RX VrefLevel [Byte0]: 33
1017 12:46:09.843338 [Byte1]: 33
1018 12:46:09.847903
1019 12:46:09.848010 Set Vref, RX VrefLevel [Byte0]: 34
1020 12:46:09.851037 [Byte1]: 34
1021 12:46:09.855622
1022 12:46:09.855713 Set Vref, RX VrefLevel [Byte0]: 35
1023 12:46:09.858249 [Byte1]: 35
1024 12:46:09.862588
1025 12:46:09.862732 Set Vref, RX VrefLevel [Byte0]: 36
1026 12:46:09.866084 [Byte1]: 36
1027 12:46:09.871121
1028 12:46:09.871281 Set Vref, RX VrefLevel [Byte0]: 37
1029 12:46:09.874007 [Byte1]: 37
1030 12:46:09.878123
1031 12:46:09.878265 Set Vref, RX VrefLevel [Byte0]: 38
1032 12:46:09.881563 [Byte1]: 38
1033 12:46:09.886328
1034 12:46:09.886508 Set Vref, RX VrefLevel [Byte0]: 39
1035 12:46:09.889553 [Byte1]: 39
1036 12:46:09.893222
1037 12:46:09.893555 Set Vref, RX VrefLevel [Byte0]: 40
1038 12:46:09.896892 [Byte1]: 40
1039 12:46:09.901196
1040 12:46:09.901698 Set Vref, RX VrefLevel [Byte0]: 41
1041 12:46:09.904334 [Byte1]: 41
1042 12:46:09.908755
1043 12:46:09.909302 Set Vref, RX VrefLevel [Byte0]: 42
1044 12:46:09.911890 [Byte1]: 42
1045 12:46:09.917038
1046 12:46:09.917541 Set Vref, RX VrefLevel [Byte0]: 43
1047 12:46:09.919563 [Byte1]: 43
1048 12:46:09.924333
1049 12:46:09.924763 Set Vref, RX VrefLevel [Byte0]: 44
1050 12:46:09.927290 [Byte1]: 44
1051 12:46:09.931485
1052 12:46:09.931920 Set Vref, RX VrefLevel [Byte0]: 45
1053 12:46:09.935243 [Byte1]: 45
1054 12:46:09.939681
1055 12:46:09.940311 Set Vref, RX VrefLevel [Byte0]: 46
1056 12:46:09.942926 [Byte1]: 46
1057 12:46:09.947426
1058 12:46:09.947901 Set Vref, RX VrefLevel [Byte0]: 47
1059 12:46:09.950434 [Byte1]: 47
1060 12:46:09.954111
1061 12:46:09.954194 Set Vref, RX VrefLevel [Byte0]: 48
1062 12:46:09.957805 [Byte1]: 48
1063 12:46:09.962077
1064 12:46:09.962160 Set Vref, RX VrefLevel [Byte0]: 49
1065 12:46:09.965034 [Byte1]: 49
1066 12:46:09.969645
1067 12:46:09.969755 Set Vref, RX VrefLevel [Byte0]: 50
1068 12:46:09.972840 [Byte1]: 50
1069 12:46:09.976962
1070 12:46:09.977070 Set Vref, RX VrefLevel [Byte0]: 51
1071 12:46:09.980824 [Byte1]: 51
1072 12:46:09.984602
1073 12:46:09.984707 Set Vref, RX VrefLevel [Byte0]: 52
1074 12:46:09.988296 [Byte1]: 52
1075 12:46:09.992898
1076 12:46:09.992979 Set Vref, RX VrefLevel [Byte0]: 53
1077 12:46:09.995816 [Byte1]: 53
1078 12:46:10.000652
1079 12:46:10.000733 Set Vref, RX VrefLevel [Byte0]: 54
1080 12:46:10.003190 [Byte1]: 54
1081 12:46:10.007890
1082 12:46:10.007972 Set Vref, RX VrefLevel [Byte0]: 55
1083 12:46:10.011108 [Byte1]: 55
1084 12:46:10.015687
1085 12:46:10.015765 Set Vref, RX VrefLevel [Byte0]: 56
1086 12:46:10.018890 [Byte1]: 56
1087 12:46:10.022994
1088 12:46:10.023100 Set Vref, RX VrefLevel [Byte0]: 57
1089 12:46:10.026284 [Byte1]: 57
1090 12:46:10.030604
1091 12:46:10.030685 Set Vref, RX VrefLevel [Byte0]: 58
1092 12:46:10.033925 [Byte1]: 58
1093 12:46:10.038208
1094 12:46:10.038290 Set Vref, RX VrefLevel [Byte0]: 59
1095 12:46:10.041653 [Byte1]: 59
1096 12:46:10.045884
1097 12:46:10.045965 Set Vref, RX VrefLevel [Byte0]: 60
1098 12:46:10.049459 [Byte1]: 60
1099 12:46:10.053772
1100 12:46:10.053853 Set Vref, RX VrefLevel [Byte0]: 61
1101 12:46:10.056809 [Byte1]: 61
1102 12:46:10.061198
1103 12:46:10.061322 Set Vref, RX VrefLevel [Byte0]: 62
1104 12:46:10.064625 [Byte1]: 62
1105 12:46:10.068898
1106 12:46:10.068975 Set Vref, RX VrefLevel [Byte0]: 63
1107 12:46:10.072455 [Byte1]: 63
1108 12:46:10.076875
1109 12:46:10.076978 Set Vref, RX VrefLevel [Byte0]: 64
1110 12:46:10.080160 [Byte1]: 64
1111 12:46:10.084606
1112 12:46:10.084687 Set Vref, RX VrefLevel [Byte0]: 65
1113 12:46:10.087588 [Byte1]: 65
1114 12:46:10.091706
1115 12:46:10.091792 Set Vref, RX VrefLevel [Byte0]: 66
1116 12:46:10.094955 [Byte1]: 66
1117 12:46:10.100265
1118 12:46:10.100347 Set Vref, RX VrefLevel [Byte0]: 67
1119 12:46:10.103141 [Byte1]: 67
1120 12:46:10.107557
1121 12:46:10.107639 Set Vref, RX VrefLevel [Byte0]: 68
1122 12:46:10.110958 [Byte1]: 68
1123 12:46:10.115011
1124 12:46:10.115116 Set Vref, RX VrefLevel [Byte0]: 69
1125 12:46:10.118421 [Byte1]: 69
1126 12:46:10.122539
1127 12:46:10.122620 Set Vref, RX VrefLevel [Byte0]: 70
1128 12:46:10.126081 [Byte1]: 70
1129 12:46:10.130235
1130 12:46:10.130316 Set Vref, RX VrefLevel [Byte0]: 71
1131 12:46:10.133624 [Byte1]: 71
1132 12:46:10.137818
1133 12:46:10.137899 Set Vref, RX VrefLevel [Byte0]: 72
1134 12:46:10.141367 [Byte1]: 72
1135 12:46:10.145225
1136 12:46:10.145307 Set Vref, RX VrefLevel [Byte0]: 73
1137 12:46:10.148728 [Byte1]: 73
1138 12:46:10.153102
1139 12:46:10.153184 Set Vref, RX VrefLevel [Byte0]: 74
1140 12:46:10.156284 [Byte1]: 74
1141 12:46:10.161087
1142 12:46:10.161231 Set Vref, RX VrefLevel [Byte0]: 75
1143 12:46:10.164175 [Byte1]: 75
1144 12:46:10.168256
1145 12:46:10.168339 Final RX Vref Byte 0 = 52 to rank0
1146 12:46:10.171976 Final RX Vref Byte 1 = 60 to rank0
1147 12:46:10.175482 Final RX Vref Byte 0 = 52 to rank1
1148 12:46:10.178103 Final RX Vref Byte 1 = 60 to rank1==
1149 12:46:10.181617 Dram Type= 6, Freq= 0, CH_0, rank 0
1150 12:46:10.188307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 12:46:10.188391 ==
1152 12:46:10.188457 DQS Delay:
1153 12:46:10.188517 DQS0 = 0, DQS1 = 0
1154 12:46:10.191710 DQM Delay:
1155 12:46:10.191816 DQM0 = 88, DQM1 = 76
1156 12:46:10.195504 DQ Delay:
1157 12:46:10.198411 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1158 12:46:10.201562 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1159 12:46:10.204906 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1160 12:46:10.208354 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1161 12:46:10.208436
1162 12:46:10.208505
1163 12:46:10.214998 [DQSOSCAuto] RK0, (LSB)MR18= 0x2822, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1164 12:46:10.218689 CH0 RK0: MR19=606, MR18=2822
1165 12:46:10.224852 CH0_RK0: MR19=0x606, MR18=0x2822, DQSOSC=399, MR23=63, INC=92, DEC=61
1166 12:46:10.224955
1167 12:46:10.227951 ----->DramcWriteLeveling(PI) begin...
1168 12:46:10.228088 ==
1169 12:46:10.231506 Dram Type= 6, Freq= 0, CH_0, rank 1
1170 12:46:10.234877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1171 12:46:10.235003 ==
1172 12:46:10.238240 Write leveling (Byte 0): 32 => 32
1173 12:46:10.241158 Write leveling (Byte 1): 29 => 29
1174 12:46:10.245037 DramcWriteLeveling(PI) end<-----
1175 12:46:10.245190
1176 12:46:10.245309 ==
1177 12:46:10.247675 Dram Type= 6, Freq= 0, CH_0, rank 1
1178 12:46:10.251303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 12:46:10.251519 ==
1180 12:46:10.254758 [Gating] SW mode calibration
1181 12:46:10.261106 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1182 12:46:10.309246 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1183 12:46:10.310389 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1184 12:46:10.311064 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1185 12:46:10.311779 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1186 12:46:10.312442 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:46:10.313048 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:46:10.313642 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:46:10.314229 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:46:10.314804 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:46:10.315216 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:46:10.353107 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:46:10.353526 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:46:10.354201 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:46:10.354558 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:46:10.354902 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:46:10.355296 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 12:46:10.355650 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 12:46:10.355981 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1200 12:46:10.356435 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1201 12:46:10.356799 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1202 12:46:10.373743 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:46:10.374200 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:46:10.374873 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:46:10.375364 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:46:10.377516 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:46:10.380462 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:46:10.380879 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1209 12:46:10.387272 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1210 12:46:10.390336 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1211 12:46:10.394083 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 12:46:10.400318 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 12:46:10.404069 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 12:46:10.407290 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 12:46:10.413494 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1216 12:46:10.417727 0 10 4 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
1217 12:46:10.420019 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1218 12:46:10.426911 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1219 12:46:10.429909 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:46:10.433734 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:46:10.440127 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:46:10.443059 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:46:10.446484 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:46:10.453981 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1225 12:46:10.457572 0 11 8 | B1->B0 | 3030 4545 | 1 0 | (0 0) (0 0)
1226 12:46:10.460921 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1227 12:46:10.465069 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 12:46:10.467997 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 12:46:10.474945 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 12:46:10.478081 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 12:46:10.482788 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 12:46:10.488510 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1233 12:46:10.492283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1234 12:46:10.495230 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 12:46:10.501945 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 12:46:10.505275 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 12:46:10.509035 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 12:46:10.515306 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 12:46:10.518481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 12:46:10.521576 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 12:46:10.528562 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 12:46:10.531708 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 12:46:10.534969 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 12:46:10.541550 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 12:46:10.544983 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 12:46:10.548821 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 12:46:10.554766 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 12:46:10.558174 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 12:46:10.561991 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1250 12:46:10.565198 Total UI for P1: 0, mck2ui 16
1251 12:46:10.568280 best dqsien dly found for B0: ( 0, 14, 6)
1252 12:46:10.571790 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 12:46:10.575394 Total UI for P1: 0, mck2ui 16
1254 12:46:10.578361 best dqsien dly found for B1: ( 0, 14, 8)
1255 12:46:10.581581 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1256 12:46:10.588273 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1257 12:46:10.588691
1258 12:46:10.591483 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1259 12:46:10.594802 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1260 12:46:10.598388 [Gating] SW calibration Done
1261 12:46:10.598806 ==
1262 12:46:10.601522 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 12:46:10.604438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 12:46:10.604860 ==
1265 12:46:10.605196 RX Vref Scan: 0
1266 12:46:10.608523
1267 12:46:10.608942 RX Vref 0 -> 0, step: 1
1268 12:46:10.609273
1269 12:46:10.611058 RX Delay -130 -> 252, step: 16
1270 12:46:10.614489 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1271 12:46:10.618014 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1272 12:46:10.624914 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1273 12:46:10.627699 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1274 12:46:10.631087 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1275 12:46:10.634780 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1276 12:46:10.637834 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1277 12:46:10.644624 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1278 12:46:10.647773 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1279 12:46:10.650978 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1280 12:46:10.654523 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1281 12:46:10.657382 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1282 12:46:10.664334 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1283 12:46:10.667914 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1284 12:46:10.671014 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1285 12:46:10.674259 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1286 12:46:10.674677 ==
1287 12:46:10.677735 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 12:46:10.684286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 12:46:10.684710 ==
1290 12:46:10.685041 DQS Delay:
1291 12:46:10.687518 DQS0 = 0, DQS1 = 0
1292 12:46:10.687988 DQM Delay:
1293 12:46:10.691103 DQM0 = 86, DQM1 = 77
1294 12:46:10.691523 DQ Delay:
1295 12:46:10.693818 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1296 12:46:10.697548 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1297 12:46:10.700647 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1298 12:46:10.703964 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1299 12:46:10.704430
1300 12:46:10.704763
1301 12:46:10.705069 ==
1302 12:46:10.707086 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 12:46:10.710542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 12:46:10.710993 ==
1305 12:46:10.711414
1306 12:46:10.711750
1307 12:46:10.715022 TX Vref Scan disable
1308 12:46:10.717165 == TX Byte 0 ==
1309 12:46:10.720404 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1310 12:46:10.723643 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1311 12:46:10.727320 == TX Byte 1 ==
1312 12:46:10.730444 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1313 12:46:10.733842 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1314 12:46:10.734337 ==
1315 12:46:10.737565 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 12:46:10.740829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 12:46:10.743388 ==
1318 12:46:10.755139 TX Vref=22, minBit 1, minWin=27, winSum=442
1319 12:46:10.758419 TX Vref=24, minBit 1, minWin=27, winSum=445
1320 12:46:10.762256 TX Vref=26, minBit 1, minWin=27, winSum=447
1321 12:46:10.764871 TX Vref=28, minBit 1, minWin=27, winSum=450
1322 12:46:10.768339 TX Vref=30, minBit 0, minWin=28, winSum=454
1323 12:46:10.774715 TX Vref=32, minBit 1, minWin=27, winSum=449
1324 12:46:10.778418 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1325 12:46:10.778840
1326 12:46:10.781731 Final TX Range 1 Vref 30
1327 12:46:10.782154
1328 12:46:10.782480 ==
1329 12:46:10.784637 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 12:46:10.788160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 12:46:10.791134 ==
1332 12:46:10.791615
1333 12:46:10.791996
1334 12:46:10.792359 TX Vref Scan disable
1335 12:46:10.795532 == TX Byte 0 ==
1336 12:46:10.798934 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1337 12:46:10.804783 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1338 12:46:10.805194 == TX Byte 1 ==
1339 12:46:10.808461 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1340 12:46:10.814988 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1341 12:46:10.815472
1342 12:46:10.815796 [DATLAT]
1343 12:46:10.816262 Freq=800, CH0 RK1
1344 12:46:10.816632
1345 12:46:10.818303 DATLAT Default: 0xa
1346 12:46:10.818803 0, 0xFFFF, sum = 0
1347 12:46:10.821620 1, 0xFFFF, sum = 0
1348 12:46:10.822110 2, 0xFFFF, sum = 0
1349 12:46:10.824731 3, 0xFFFF, sum = 0
1350 12:46:10.828107 4, 0xFFFF, sum = 0
1351 12:46:10.828524 5, 0xFFFF, sum = 0
1352 12:46:10.832020 6, 0xFFFF, sum = 0
1353 12:46:10.832473 7, 0xFFFF, sum = 0
1354 12:46:10.835114 8, 0xFFFF, sum = 0
1355 12:46:10.835603 9, 0x0, sum = 1
1356 12:46:10.835936 10, 0x0, sum = 2
1357 12:46:10.838118 11, 0x0, sum = 3
1358 12:46:10.838533 12, 0x0, sum = 4
1359 12:46:10.842023 best_step = 10
1360 12:46:10.842482
1361 12:46:10.842863 ==
1362 12:46:10.844926 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 12:46:10.848270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 12:46:10.848682 ==
1365 12:46:10.851685 RX Vref Scan: 0
1366 12:46:10.852126
1367 12:46:10.852506 RX Vref 0 -> 0, step: 1
1368 12:46:10.854870
1369 12:46:10.855278 RX Delay -95 -> 252, step: 8
1370 12:46:10.861700 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1371 12:46:10.865229 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1372 12:46:10.868469 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1373 12:46:10.872268 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1374 12:46:10.875030 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1375 12:46:10.881562 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1376 12:46:10.885153 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1377 12:46:10.888620 iDelay=209, Bit 7, Center 92 (-15 ~ 200) 216
1378 12:46:10.891586 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1379 12:46:10.894746 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1380 12:46:10.901451 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1381 12:46:10.904645 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1382 12:46:10.907753 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1383 12:46:10.911616 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1384 12:46:10.918217 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1385 12:46:10.921157 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1386 12:46:10.921564 ==
1387 12:46:10.924479 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 12:46:10.927952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 12:46:10.928407 ==
1390 12:46:10.931326 DQS Delay:
1391 12:46:10.931729 DQS0 = 0, DQS1 = 0
1392 12:46:10.932096 DQM Delay:
1393 12:46:10.934480 DQM0 = 85, DQM1 = 77
1394 12:46:10.934886 DQ Delay:
1395 12:46:10.938358 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1396 12:46:10.941454 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1397 12:46:10.945014 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1398 12:46:10.947822 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1399 12:46:10.948275
1400 12:46:10.948596
1401 12:46:10.957783 [DQSOSCAuto] RK1, (LSB)MR18= 0x2623, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1402 12:46:10.958190 CH0 RK1: MR19=606, MR18=2623
1403 12:46:10.964424 CH0_RK1: MR19=0x606, MR18=0x2623, DQSOSC=400, MR23=63, INC=92, DEC=61
1404 12:46:10.967815 [RxdqsGatingPostProcess] freq 800
1405 12:46:10.974657 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1406 12:46:10.978013 Pre-setting of DQS Precalculation
1407 12:46:10.980953 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1408 12:46:10.981363 ==
1409 12:46:10.984128 Dram Type= 6, Freq= 0, CH_1, rank 0
1410 12:46:10.990933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 12:46:10.991340 ==
1412 12:46:10.994912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 12:46:11.000737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 12:46:11.010089 [CA 0] Center 36 (6~67) winsize 62
1415 12:46:11.013962 [CA 1] Center 37 (6~68) winsize 63
1416 12:46:11.016703 [CA 2] Center 35 (5~65) winsize 61
1417 12:46:11.020481 [CA 3] Center 34 (4~65) winsize 62
1418 12:46:11.023464 [CA 4] Center 34 (4~65) winsize 62
1419 12:46:11.026972 [CA 5] Center 33 (3~64) winsize 62
1420 12:46:11.027378
1421 12:46:11.029904 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 12:46:11.030310
1423 12:46:11.033363 [CATrainingPosCal] consider 1 rank data
1424 12:46:11.036598 u2DelayCellTimex100 = 270/100 ps
1425 12:46:11.040452 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1426 12:46:11.043354 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1427 12:46:11.050133 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1428 12:46:11.053494 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1429 12:46:11.056566 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1430 12:46:11.060371 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 12:46:11.060775
1432 12:46:11.063374 CA PerBit enable=1, Macro0, CA PI delay=33
1433 12:46:11.063780
1434 12:46:11.066755 [CBTSetCACLKResult] CA Dly = 33
1435 12:46:11.067157 CS Dly: 4 (0~35)
1436 12:46:11.069846 ==
1437 12:46:11.073320 Dram Type= 6, Freq= 0, CH_1, rank 1
1438 12:46:11.076137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 12:46:11.076547 ==
1440 12:46:11.080564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1441 12:46:11.086437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1442 12:46:11.096110 [CA 0] Center 36 (6~67) winsize 62
1443 12:46:11.099297 [CA 1] Center 36 (6~67) winsize 62
1444 12:46:11.102812 [CA 2] Center 34 (4~65) winsize 62
1445 12:46:11.106051 [CA 3] Center 34 (3~65) winsize 63
1446 12:46:11.109186 [CA 4] Center 34 (4~65) winsize 62
1447 12:46:11.112622 [CA 5] Center 34 (3~65) winsize 63
1448 12:46:11.113051
1449 12:46:11.116210 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1450 12:46:11.116641
1451 12:46:11.119713 [CATrainingPosCal] consider 2 rank data
1452 12:46:11.123332 u2DelayCellTimex100 = 270/100 ps
1453 12:46:11.127163 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1454 12:46:11.130224 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1455 12:46:11.134230 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1456 12:46:11.137766 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1457 12:46:11.141139 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1458 12:46:11.144202 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1459 12:46:11.144618
1460 12:46:11.148115 CA PerBit enable=1, Macro0, CA PI delay=33
1461 12:46:11.151826
1462 12:46:11.152328 [CBTSetCACLKResult] CA Dly = 33
1463 12:46:11.154842 CS Dly: 5 (0~37)
1464 12:46:11.155267
1465 12:46:11.158443 ----->DramcWriteLeveling(PI) begin...
1466 12:46:11.158866 ==
1467 12:46:11.161815 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 12:46:11.165582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 12:46:11.165997 ==
1470 12:46:11.168370 Write leveling (Byte 0): 26 => 26
1471 12:46:11.171813 Write leveling (Byte 1): 28 => 28
1472 12:46:11.174964 DramcWriteLeveling(PI) end<-----
1473 12:46:11.175375
1474 12:46:11.175701 ==
1475 12:46:11.178329 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 12:46:11.181258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 12:46:11.181674 ==
1478 12:46:11.185138 [Gating] SW mode calibration
1479 12:46:11.191333 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1480 12:46:11.198089 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1481 12:46:11.201418 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1482 12:46:11.208253 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1483 12:46:11.211407 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:46:11.214749 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:46:11.221725 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:46:11.225036 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:46:11.228137 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:46:11.234708 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:46:11.237789 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:46:11.241230 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:46:11.248097 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:46:11.251089 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:46:11.254465 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:46:11.257873 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:46:11.264393 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 12:46:11.267417 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 12:46:11.270885 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:46:11.277439 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1499 12:46:11.280928 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1500 12:46:11.284065 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:46:11.290870 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:46:11.293580 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:46:11.300521 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:46:11.304155 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:46:11.307223 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:46:11.310369 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1507 12:46:11.317207 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1508 12:46:11.320645 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 12:46:11.323697 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 12:46:11.330424 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 12:46:11.333915 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 12:46:11.337185 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1513 12:46:11.344086 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1514 12:46:11.346939 0 10 4 | B1->B0 | 3333 2f2f | 0 1 | (0 0) (0 0)
1515 12:46:11.350191 0 10 8 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1516 12:46:11.356976 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:46:11.360026 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:46:11.363304 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:46:11.370179 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:46:11.373329 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:46:11.376888 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:46:11.383311 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1523 12:46:11.386612 0 11 8 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)
1524 12:46:11.389678 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 12:46:11.396383 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 12:46:11.400103 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 12:46:11.403081 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 12:46:11.409765 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 12:46:11.413077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 12:46:11.416110 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1531 12:46:11.422922 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 12:46:11.426324 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 12:46:11.429375 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 12:46:11.436234 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 12:46:11.439497 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 12:46:11.442770 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 12:46:11.449559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 12:46:11.452959 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 12:46:11.456335 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 12:46:11.462510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 12:46:11.465987 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 12:46:11.469538 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 12:46:11.475851 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 12:46:11.479231 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 12:46:11.482379 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 12:46:11.489508 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1547 12:46:11.492814 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 12:46:11.495761 Total UI for P1: 0, mck2ui 16
1549 12:46:11.499516 best dqsien dly found for B0: ( 0, 14, 4)
1550 12:46:11.502614 Total UI for P1: 0, mck2ui 16
1551 12:46:11.506040 best dqsien dly found for B1: ( 0, 14, 4)
1552 12:46:11.509109 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1553 12:46:11.512855 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1554 12:46:11.513316
1555 12:46:11.515752 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1556 12:46:11.519008 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1557 12:46:11.522344 [Gating] SW calibration Done
1558 12:46:11.522812 ==
1559 12:46:11.525916 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 12:46:11.529046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 12:46:11.529465 ==
1562 12:46:11.533183 RX Vref Scan: 0
1563 12:46:11.533601
1564 12:46:11.535670 RX Vref 0 -> 0, step: 1
1565 12:46:11.536127
1566 12:46:11.536469 RX Delay -130 -> 252, step: 16
1567 12:46:11.542326 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1568 12:46:11.545484 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1569 12:46:11.549028 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1570 12:46:11.552498 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1571 12:46:11.555400 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1572 12:46:11.562244 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1573 12:46:11.565324 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1574 12:46:11.569089 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1575 12:46:11.572104 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1576 12:46:11.575278 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1577 12:46:11.582292 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1578 12:46:11.585357 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1579 12:46:11.588627 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1580 12:46:11.592102 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1581 12:46:11.598426 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1582 12:46:11.602605 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1583 12:46:11.603213 ==
1584 12:46:11.605211 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:46:11.608514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:46:11.608966 ==
1587 12:46:11.612073 DQS Delay:
1588 12:46:11.612499 DQS0 = 0, DQS1 = 0
1589 12:46:11.612833 DQM Delay:
1590 12:46:11.615409 DQM0 = 86, DQM1 = 79
1591 12:46:11.615831 DQ Delay:
1592 12:46:11.619090 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1593 12:46:11.621894 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =85
1594 12:46:11.625166 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1595 12:46:11.628684 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1596 12:46:11.629108
1597 12:46:11.629499
1598 12:46:11.629817 ==
1599 12:46:11.632192 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 12:46:11.638860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 12:46:11.639285 ==
1602 12:46:11.639623
1603 12:46:11.639933
1604 12:46:11.640263 TX Vref Scan disable
1605 12:46:11.641883 == TX Byte 0 ==
1606 12:46:11.645110 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1607 12:46:11.652297 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1608 12:46:11.652799 == TX Byte 1 ==
1609 12:46:11.655362 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1610 12:46:11.662074 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1611 12:46:11.662503 ==
1612 12:46:11.664981 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 12:46:11.668834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 12:46:11.669344 ==
1615 12:46:11.681851 TX Vref=22, minBit 4, minWin=27, winSum=444
1616 12:46:11.684263 TX Vref=24, minBit 2, minWin=27, winSum=446
1617 12:46:11.687536 TX Vref=26, minBit 2, minWin=27, winSum=450
1618 12:46:11.691095 TX Vref=28, minBit 2, minWin=27, winSum=453
1619 12:46:11.694180 TX Vref=30, minBit 5, minWin=27, winSum=457
1620 12:46:11.698082 TX Vref=32, minBit 0, minWin=27, winSum=451
1621 12:46:11.705351 [TxChooseVref] Worse bit 5, Min win 27, Win sum 457, Final Vref 30
1622 12:46:11.705783
1623 12:46:11.708096 Final TX Range 1 Vref 30
1624 12:46:11.708522
1625 12:46:11.708858 ==
1626 12:46:11.711269 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 12:46:11.715156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 12:46:11.715574 ==
1629 12:46:11.715904
1630 12:46:11.716253
1631 12:46:11.718211 TX Vref Scan disable
1632 12:46:11.721584 == TX Byte 0 ==
1633 12:46:11.724763 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1634 12:46:11.727926 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1635 12:46:11.731426 == TX Byte 1 ==
1636 12:46:11.734764 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1637 12:46:11.737722 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1638 12:46:11.738133
1639 12:46:11.741466 [DATLAT]
1640 12:46:11.741878 Freq=800, CH1 RK0
1641 12:46:11.742207
1642 12:46:11.744499 DATLAT Default: 0xa
1643 12:46:11.744913 0, 0xFFFF, sum = 0
1644 12:46:11.747659 1, 0xFFFF, sum = 0
1645 12:46:11.748107 2, 0xFFFF, sum = 0
1646 12:46:11.751191 3, 0xFFFF, sum = 0
1647 12:46:11.751627 4, 0xFFFF, sum = 0
1648 12:46:11.754631 5, 0xFFFF, sum = 0
1649 12:46:11.755053 6, 0xFFFF, sum = 0
1650 12:46:11.757777 7, 0xFFFF, sum = 0
1651 12:46:11.758210 8, 0xFFFF, sum = 0
1652 12:46:11.760920 9, 0x0, sum = 1
1653 12:46:11.761352 10, 0x0, sum = 2
1654 12:46:11.764456 11, 0x0, sum = 3
1655 12:46:11.764886 12, 0x0, sum = 4
1656 12:46:11.767423 best_step = 10
1657 12:46:11.767845
1658 12:46:11.768314 ==
1659 12:46:11.770901 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 12:46:11.774662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 12:46:11.775089 ==
1662 12:46:11.777873 RX Vref Scan: 1
1663 12:46:11.778295
1664 12:46:11.778735 Set Vref Range= 32 -> 127
1665 12:46:11.779134
1666 12:46:11.781087 RX Vref 32 -> 127, step: 1
1667 12:46:11.781510
1668 12:46:11.784132 RX Delay -95 -> 252, step: 8
1669 12:46:11.784552
1670 12:46:11.788252 Set Vref, RX VrefLevel [Byte0]: 32
1671 12:46:11.790804 [Byte1]: 32
1672 12:46:11.791218
1673 12:46:11.794666 Set Vref, RX VrefLevel [Byte0]: 33
1674 12:46:11.797324 [Byte1]: 33
1675 12:46:11.801096
1676 12:46:11.801477 Set Vref, RX VrefLevel [Byte0]: 34
1677 12:46:11.804792 [Byte1]: 34
1678 12:46:11.808887
1679 12:46:11.809314 Set Vref, RX VrefLevel [Byte0]: 35
1680 12:46:11.812552 [Byte1]: 35
1681 12:46:11.816343
1682 12:46:11.816761 Set Vref, RX VrefLevel [Byte0]: 36
1683 12:46:11.822800 [Byte1]: 36
1684 12:46:11.823223
1685 12:46:11.826085 Set Vref, RX VrefLevel [Byte0]: 37
1686 12:46:11.829580 [Byte1]: 37
1687 12:46:11.830048
1688 12:46:11.832560 Set Vref, RX VrefLevel [Byte0]: 38
1689 12:46:11.836159 [Byte1]: 38
1690 12:46:11.836583
1691 12:46:11.839886 Set Vref, RX VrefLevel [Byte0]: 39
1692 12:46:11.842708 [Byte1]: 39
1693 12:46:11.847060
1694 12:46:11.847483 Set Vref, RX VrefLevel [Byte0]: 40
1695 12:46:11.850434 [Byte1]: 40
1696 12:46:11.854428
1697 12:46:11.854848 Set Vref, RX VrefLevel [Byte0]: 41
1698 12:46:11.857985 [Byte1]: 41
1699 12:46:11.862248
1700 12:46:11.862671 Set Vref, RX VrefLevel [Byte0]: 42
1701 12:46:11.865382 [Byte1]: 42
1702 12:46:11.869372
1703 12:46:11.869793 Set Vref, RX VrefLevel [Byte0]: 43
1704 12:46:11.872944 [Byte1]: 43
1705 12:46:11.877414
1706 12:46:11.877833 Set Vref, RX VrefLevel [Byte0]: 44
1707 12:46:11.880756 [Byte1]: 44
1708 12:46:11.884937
1709 12:46:11.885356 Set Vref, RX VrefLevel [Byte0]: 45
1710 12:46:11.888142 [Byte1]: 45
1711 12:46:11.892181
1712 12:46:11.892670 Set Vref, RX VrefLevel [Byte0]: 46
1713 12:46:11.896220 [Byte1]: 46
1714 12:46:11.899769
1715 12:46:11.900206 Set Vref, RX VrefLevel [Byte0]: 47
1716 12:46:11.903159 [Byte1]: 47
1717 12:46:11.907684
1718 12:46:11.908134 Set Vref, RX VrefLevel [Byte0]: 48
1719 12:46:11.910868 [Byte1]: 48
1720 12:46:11.914884
1721 12:46:11.915299 Set Vref, RX VrefLevel [Byte0]: 49
1722 12:46:11.918482 [Byte1]: 49
1723 12:46:11.922895
1724 12:46:11.923380 Set Vref, RX VrefLevel [Byte0]: 50
1725 12:46:11.925918 [Byte1]: 50
1726 12:46:11.930672
1727 12:46:11.931117 Set Vref, RX VrefLevel [Byte0]: 51
1728 12:46:11.934104 [Byte1]: 51
1729 12:46:11.938044
1730 12:46:11.938494 Set Vref, RX VrefLevel [Byte0]: 52
1731 12:46:11.941313 [Byte1]: 52
1732 12:46:11.945626
1733 12:46:11.946088 Set Vref, RX VrefLevel [Byte0]: 53
1734 12:46:11.948781 [Byte1]: 53
1735 12:46:11.953052
1736 12:46:11.953507 Set Vref, RX VrefLevel [Byte0]: 54
1737 12:46:11.956377 [Byte1]: 54
1738 12:46:11.960920
1739 12:46:11.961341 Set Vref, RX VrefLevel [Byte0]: 55
1740 12:46:11.964132 [Byte1]: 55
1741 12:46:11.968507
1742 12:46:11.968920 Set Vref, RX VrefLevel [Byte0]: 56
1743 12:46:11.971714 [Byte1]: 56
1744 12:46:11.975919
1745 12:46:11.976376 Set Vref, RX VrefLevel [Byte0]: 57
1746 12:46:11.979256 [Byte1]: 57
1747 12:46:11.983515
1748 12:46:11.983932 Set Vref, RX VrefLevel [Byte0]: 58
1749 12:46:11.987324 [Byte1]: 58
1750 12:46:11.990950
1751 12:46:11.991366 Set Vref, RX VrefLevel [Byte0]: 59
1752 12:46:11.995056 [Byte1]: 59
1753 12:46:11.998986
1754 12:46:11.999403 Set Vref, RX VrefLevel [Byte0]: 60
1755 12:46:12.002450 [Byte1]: 60
1756 12:46:12.006201
1757 12:46:12.006619 Set Vref, RX VrefLevel [Byte0]: 61
1758 12:46:12.009735 [Byte1]: 61
1759 12:46:12.013771
1760 12:46:12.014187 Set Vref, RX VrefLevel [Byte0]: 62
1761 12:46:12.017359 [Byte1]: 62
1762 12:46:12.021636
1763 12:46:12.022089 Set Vref, RX VrefLevel [Byte0]: 63
1764 12:46:12.025111 [Byte1]: 63
1765 12:46:12.029008
1766 12:46:12.029422 Set Vref, RX VrefLevel [Byte0]: 64
1767 12:46:12.032522 [Byte1]: 64
1768 12:46:12.036944
1769 12:46:12.037363 Set Vref, RX VrefLevel [Byte0]: 65
1770 12:46:12.040170 [Byte1]: 65
1771 12:46:12.044198
1772 12:46:12.044665 Set Vref, RX VrefLevel [Byte0]: 66
1773 12:46:12.047927 [Byte1]: 66
1774 12:46:12.052014
1775 12:46:12.052502 Set Vref, RX VrefLevel [Byte0]: 67
1776 12:46:12.055362 [Byte1]: 67
1777 12:46:12.059695
1778 12:46:12.060229 Set Vref, RX VrefLevel [Byte0]: 68
1779 12:46:12.062737 [Byte1]: 68
1780 12:46:12.066819
1781 12:46:12.067232 Set Vref, RX VrefLevel [Byte0]: 69
1782 12:46:12.070157 [Byte1]: 69
1783 12:46:12.075079
1784 12:46:12.075555 Set Vref, RX VrefLevel [Byte0]: 70
1785 12:46:12.077898 [Byte1]: 70
1786 12:46:12.082189
1787 12:46:12.082601 Set Vref, RX VrefLevel [Byte0]: 71
1788 12:46:12.085534 [Byte1]: 71
1789 12:46:12.089760
1790 12:46:12.090197 Set Vref, RX VrefLevel [Byte0]: 72
1791 12:46:12.093694 [Byte1]: 72
1792 12:46:12.097660
1793 12:46:12.098076 Set Vref, RX VrefLevel [Byte0]: 73
1794 12:46:12.100963 [Byte1]: 73
1795 12:46:12.105437
1796 12:46:12.105924 Set Vref, RX VrefLevel [Byte0]: 74
1797 12:46:12.108372 [Byte1]: 74
1798 12:46:12.112826
1799 12:46:12.113242 Set Vref, RX VrefLevel [Byte0]: 75
1800 12:46:12.115957 [Byte1]: 75
1801 12:46:12.120101
1802 12:46:12.120517 Final RX Vref Byte 0 = 58 to rank0
1803 12:46:12.123866 Final RX Vref Byte 1 = 54 to rank0
1804 12:46:12.126979 Final RX Vref Byte 0 = 58 to rank1
1805 12:46:12.130305 Final RX Vref Byte 1 = 54 to rank1==
1806 12:46:12.133625 Dram Type= 6, Freq= 0, CH_1, rank 0
1807 12:46:12.140336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 12:46:12.140822 ==
1809 12:46:12.141162 DQS Delay:
1810 12:46:12.141581 DQS0 = 0, DQS1 = 0
1811 12:46:12.143539 DQM Delay:
1812 12:46:12.143963 DQM0 = 86, DQM1 = 80
1813 12:46:12.146811 DQ Delay:
1814 12:46:12.150235 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1815 12:46:12.153822 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1816 12:46:12.157075 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1817 12:46:12.160115 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1818 12:46:12.160689
1819 12:46:12.161178
1820 12:46:12.166983 [DQSOSCAuto] RK0, (LSB)MR18= 0x1629, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1821 12:46:12.170425 CH1 RK0: MR19=606, MR18=1629
1822 12:46:12.176616 CH1_RK0: MR19=0x606, MR18=0x1629, DQSOSC=399, MR23=63, INC=92, DEC=61
1823 12:46:12.177054
1824 12:46:12.180266 ----->DramcWriteLeveling(PI) begin...
1825 12:46:12.180711 ==
1826 12:46:12.183619 Dram Type= 6, Freq= 0, CH_1, rank 1
1827 12:46:12.186520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 12:46:12.187055 ==
1829 12:46:12.190108 Write leveling (Byte 0): 26 => 26
1830 12:46:12.193655 Write leveling (Byte 1): 26 => 26
1831 12:46:12.196756 DramcWriteLeveling(PI) end<-----
1832 12:46:12.197201
1833 12:46:12.197682 ==
1834 12:46:12.199703 Dram Type= 6, Freq= 0, CH_1, rank 1
1835 12:46:12.203530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 12:46:12.204225 ==
1837 12:46:12.206668 [Gating] SW mode calibration
1838 12:46:12.213134 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1839 12:46:12.219924 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1840 12:46:12.222951 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1841 12:46:12.229456 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1842 12:46:12.232691 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1843 12:46:12.236104 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:46:12.239378 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:46:12.246313 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:46:12.250465 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:46:12.252769 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:46:12.259808 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:46:12.263002 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:46:12.266082 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:46:12.272434 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:46:12.276093 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:46:12.279781 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:46:12.286237 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:46:12.289615 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:46:12.293145 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1857 12:46:12.299300 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1858 12:46:12.302478 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:46:12.305780 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:46:12.312653 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:46:12.316093 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:46:12.319502 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:46:12.326097 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:46:12.329580 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:46:12.332840 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1866 12:46:12.338905 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1867 12:46:12.342487 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 12:46:12.345907 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 12:46:12.352201 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 12:46:12.355983 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 12:46:12.358855 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 12:46:12.365685 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1873 12:46:12.369432 0 10 4 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (1 0)
1874 12:46:12.372799 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1875 12:46:12.379241 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:46:12.382575 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:46:12.385496 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:46:12.391992 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:46:12.395671 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:46:12.398535 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:46:12.402458 0 11 4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
1882 12:46:12.408323 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1883 12:46:12.411704 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 12:46:12.415697 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 12:46:12.421827 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 12:46:12.425394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 12:46:12.428480 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 12:46:12.435377 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1889 12:46:12.438302 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1890 12:46:12.441667 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1891 12:46:12.448282 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 12:46:12.451724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 12:46:12.455032 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 12:46:12.461657 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 12:46:12.465481 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 12:46:12.468671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 12:46:12.475062 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 12:46:12.478066 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 12:46:12.481746 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 12:46:12.488552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 12:46:12.491435 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 12:46:12.494841 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 12:46:12.501195 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 12:46:12.504898 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 12:46:12.508156 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1906 12:46:12.514320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 12:46:12.514744 Total UI for P1: 0, mck2ui 16
1908 12:46:12.521094 best dqsien dly found for B0: ( 0, 14, 4)
1909 12:46:12.521572 Total UI for P1: 0, mck2ui 16
1910 12:46:12.527769 best dqsien dly found for B1: ( 0, 14, 4)
1911 12:46:12.530910 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1912 12:46:12.534365 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1913 12:46:12.534793
1914 12:46:12.537977 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1915 12:46:12.541173 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1916 12:46:12.544062 [Gating] SW calibration Done
1917 12:46:12.544476 ==
1918 12:46:12.547581 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 12:46:12.551179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 12:46:12.551641 ==
1921 12:46:12.554094 RX Vref Scan: 0
1922 12:46:12.554556
1923 12:46:12.554927 RX Vref 0 -> 0, step: 1
1924 12:46:12.555243
1925 12:46:12.557436 RX Delay -130 -> 252, step: 16
1926 12:46:12.564205 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1927 12:46:12.567322 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1928 12:46:12.570629 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1929 12:46:12.574218 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1930 12:46:12.577563 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1931 12:46:12.583786 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1932 12:46:12.586926 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1933 12:46:12.591100 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1934 12:46:12.593848 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1935 12:46:12.597350 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1936 12:46:12.603946 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1937 12:46:12.607376 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1938 12:46:12.610655 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1939 12:46:12.613747 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1940 12:46:12.617226 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1941 12:46:12.624158 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1942 12:46:12.624611 ==
1943 12:46:12.627125 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 12:46:12.629895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 12:46:12.630350 ==
1946 12:46:12.630682 DQS Delay:
1947 12:46:12.633260 DQS0 = 0, DQS1 = 0
1948 12:46:12.633675 DQM Delay:
1949 12:46:12.636766 DQM0 = 82, DQM1 = 80
1950 12:46:12.637184 DQ Delay:
1951 12:46:12.640684 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1952 12:46:12.643718 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1953 12:46:12.647173 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1954 12:46:12.649903 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1955 12:46:12.649983
1956 12:46:12.650046
1957 12:46:12.650103 ==
1958 12:46:12.653040 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 12:46:12.657101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 12:46:12.657183 ==
1961 12:46:12.660004
1962 12:46:12.660120
1963 12:46:12.660184 TX Vref Scan disable
1964 12:46:12.663025 == TX Byte 0 ==
1965 12:46:12.666441 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 12:46:12.669788 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 12:46:12.673371 == TX Byte 1 ==
1968 12:46:12.676482 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1969 12:46:12.679539 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1970 12:46:12.682922 ==
1971 12:46:12.682998 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 12:46:12.689645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 12:46:12.689725 ==
1974 12:46:12.701333 TX Vref=22, minBit 1, minWin=27, winSum=445
1975 12:46:12.705075 TX Vref=24, minBit 1, minWin=27, winSum=451
1976 12:46:12.708398 TX Vref=26, minBit 3, minWin=27, winSum=453
1977 12:46:12.711350 TX Vref=28, minBit 6, minWin=27, winSum=453
1978 12:46:12.714938 TX Vref=30, minBit 6, minWin=27, winSum=453
1979 12:46:12.721233 TX Vref=32, minBit 1, minWin=28, winSum=458
1980 12:46:12.724860 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 32
1981 12:46:12.724939
1982 12:46:12.728472 Final TX Range 1 Vref 32
1983 12:46:12.728545
1984 12:46:12.728606 ==
1985 12:46:12.731353 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 12:46:12.734660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 12:46:12.734758 ==
1988 12:46:12.738020
1989 12:46:12.738093
1990 12:46:12.738152 TX Vref Scan disable
1991 12:46:12.741523 == TX Byte 0 ==
1992 12:46:12.745071 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1993 12:46:12.748293 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1994 12:46:12.751604 == TX Byte 1 ==
1995 12:46:12.754758 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1996 12:46:12.761286 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1997 12:46:12.761379
1998 12:46:12.761453 [DATLAT]
1999 12:46:12.761523 Freq=800, CH1 RK1
2000 12:46:12.761590
2001 12:46:12.764731 DATLAT Default: 0xa
2002 12:46:12.764831 0, 0xFFFF, sum = 0
2003 12:46:12.768130 1, 0xFFFF, sum = 0
2004 12:46:12.768233 2, 0xFFFF, sum = 0
2005 12:46:12.771864 3, 0xFFFF, sum = 0
2006 12:46:12.775681 4, 0xFFFF, sum = 0
2007 12:46:12.775804 5, 0xFFFF, sum = 0
2008 12:46:12.778551 6, 0xFFFF, sum = 0
2009 12:46:12.778674 7, 0xFFFF, sum = 0
2010 12:46:12.781558 8, 0xFFFF, sum = 0
2011 12:46:12.781694 9, 0x0, sum = 1
2012 12:46:12.781802 10, 0x0, sum = 2
2013 12:46:12.784474 11, 0x0, sum = 3
2014 12:46:12.784626 12, 0x0, sum = 4
2015 12:46:12.788166 best_step = 10
2016 12:46:12.788318
2017 12:46:12.788438 ==
2018 12:46:12.791748 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 12:46:12.795109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 12:46:12.795309 ==
2021 12:46:12.797934 RX Vref Scan: 0
2022 12:46:12.798133
2023 12:46:12.798291 RX Vref 0 -> 0, step: 1
2024 12:46:12.798439
2025 12:46:12.801268 RX Delay -95 -> 252, step: 8
2026 12:46:12.808484 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2027 12:46:12.811651 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2028 12:46:12.814781 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2029 12:46:12.818382 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2030 12:46:12.821793 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2031 12:46:12.828155 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2032 12:46:12.831776 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2033 12:46:12.834852 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2034 12:46:12.838421 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2035 12:46:12.841988 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2036 12:46:12.848373 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2037 12:46:12.852439 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2038 12:46:12.854902 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2039 12:46:12.858090 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2040 12:46:12.865091 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2041 12:46:12.868116 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2042 12:46:12.868535 ==
2043 12:46:12.871673 Dram Type= 6, Freq= 0, CH_1, rank 1
2044 12:46:12.876291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2045 12:46:12.876714 ==
2046 12:46:12.877778 DQS Delay:
2047 12:46:12.878192 DQS0 = 0, DQS1 = 0
2048 12:46:12.878524 DQM Delay:
2049 12:46:12.881665 DQM0 = 87, DQM1 = 81
2050 12:46:12.882082 DQ Delay:
2051 12:46:12.884612 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2052 12:46:12.888401 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2053 12:46:12.891342 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2054 12:46:12.894764 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2055 12:46:12.895183
2056 12:46:12.895514
2057 12:46:12.904314 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2058 12:46:12.904774 CH1 RK1: MR19=606, MR18=1E39
2059 12:46:12.911123 CH1_RK1: MR19=0x606, MR18=0x1E39, DQSOSC=395, MR23=63, INC=94, DEC=63
2060 12:46:12.914303 [RxdqsGatingPostProcess] freq 800
2061 12:46:12.920840 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2062 12:46:12.924183 Pre-setting of DQS Precalculation
2063 12:46:12.927941 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2064 12:46:12.934191 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2065 12:46:12.944112 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2066 12:46:12.944540
2067 12:46:12.944866
2068 12:46:12.947571 [Calibration Summary] 1600 Mbps
2069 12:46:12.947987 CH 0, Rank 0
2070 12:46:12.950975 SW Impedance : PASS
2071 12:46:12.951387 DUTY Scan : NO K
2072 12:46:12.954409 ZQ Calibration : PASS
2073 12:46:12.957631 Jitter Meter : NO K
2074 12:46:12.958105 CBT Training : PASS
2075 12:46:12.960764 Write leveling : PASS
2076 12:46:12.964491 RX DQS gating : PASS
2077 12:46:12.964906 RX DQ/DQS(RDDQC) : PASS
2078 12:46:12.967462 TX DQ/DQS : PASS
2079 12:46:12.968022 RX DATLAT : PASS
2080 12:46:12.970701 RX DQ/DQS(Engine): PASS
2081 12:46:12.974078 TX OE : NO K
2082 12:46:12.974493 All Pass.
2083 12:46:12.974819
2084 12:46:12.975122 CH 0, Rank 1
2085 12:46:12.977319 SW Impedance : PASS
2086 12:46:12.980329 DUTY Scan : NO K
2087 12:46:12.980743 ZQ Calibration : PASS
2088 12:46:12.983944 Jitter Meter : NO K
2089 12:46:12.987272 CBT Training : PASS
2090 12:46:12.987687 Write leveling : PASS
2091 12:46:12.990419 RX DQS gating : PASS
2092 12:46:12.993717 RX DQ/DQS(RDDQC) : PASS
2093 12:46:12.994131 TX DQ/DQS : PASS
2094 12:46:12.996892 RX DATLAT : PASS
2095 12:46:13.000490 RX DQ/DQS(Engine): PASS
2096 12:46:13.000914 TX OE : NO K
2097 12:46:13.004244 All Pass.
2098 12:46:13.004666
2099 12:46:13.005049 CH 1, Rank 0
2100 12:46:13.007114 SW Impedance : PASS
2101 12:46:13.007551 DUTY Scan : NO K
2102 12:46:13.010286 ZQ Calibration : PASS
2103 12:46:13.013976 Jitter Meter : NO K
2104 12:46:13.014409 CBT Training : PASS
2105 12:46:13.016748 Write leveling : PASS
2106 12:46:13.020361 RX DQS gating : PASS
2107 12:46:13.020743 RX DQ/DQS(RDDQC) : PASS
2108 12:46:13.023525 TX DQ/DQS : PASS
2109 12:46:13.027022 RX DATLAT : PASS
2110 12:46:13.027440 RX DQ/DQS(Engine): PASS
2111 12:46:13.030406 TX OE : NO K
2112 12:46:13.030894 All Pass.
2113 12:46:13.031217
2114 12:46:13.033595 CH 1, Rank 1
2115 12:46:13.033979 SW Impedance : PASS
2116 12:46:13.037120 DUTY Scan : NO K
2117 12:46:13.037538 ZQ Calibration : PASS
2118 12:46:13.040554 Jitter Meter : NO K
2119 12:46:13.043528 CBT Training : PASS
2120 12:46:13.044015 Write leveling : PASS
2121 12:46:13.046780 RX DQS gating : PASS
2122 12:46:13.049861 RX DQ/DQS(RDDQC) : PASS
2123 12:46:13.050335 TX DQ/DQS : PASS
2124 12:46:13.053540 RX DATLAT : PASS
2125 12:46:13.056911 RX DQ/DQS(Engine): PASS
2126 12:46:13.057439 TX OE : NO K
2127 12:46:13.060133 All Pass.
2128 12:46:13.060700
2129 12:46:13.061191 DramC Write-DBI off
2130 12:46:13.063200 PER_BANK_REFRESH: Hybrid Mode
2131 12:46:13.063668 TX_TRACKING: ON
2132 12:46:13.066659 [GetDramInforAfterCalByMRR] Vendor 6.
2133 12:46:13.073890 [GetDramInforAfterCalByMRR] Revision 606.
2134 12:46:13.076391 [GetDramInforAfterCalByMRR] Revision 2 0.
2135 12:46:13.076852 MR0 0x3b3b
2136 12:46:13.077196 MR8 0x5151
2137 12:46:13.080598 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2138 12:46:13.083087
2139 12:46:13.083517 MR0 0x3b3b
2140 12:46:13.083898 MR8 0x5151
2141 12:46:13.086391 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2142 12:46:13.086853
2143 12:46:13.096523 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2144 12:46:13.100286 [FAST_K] Save calibration result to emmc
2145 12:46:13.103191 [FAST_K] Save calibration result to emmc
2146 12:46:13.106425 dram_init: config_dvfs: 1
2147 12:46:13.110058 dramc_set_vcore_voltage set vcore to 662500
2148 12:46:13.113114 Read voltage for 1200, 2
2149 12:46:13.113546 Vio18 = 0
2150 12:46:13.113918 Vcore = 662500
2151 12:46:13.116421 Vdram = 0
2152 12:46:13.116852 Vddq = 0
2153 12:46:13.117232 Vmddr = 0
2154 12:46:13.123128 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2155 12:46:13.126369 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2156 12:46:13.129635 MEM_TYPE=3, freq_sel=15
2157 12:46:13.133467 sv_algorithm_assistance_LP4_1600
2158 12:46:13.136455 ============ PULL DRAM RESETB DOWN ============
2159 12:46:13.139554 ========== PULL DRAM RESETB DOWN end =========
2160 12:46:13.146865 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2161 12:46:13.149774 ===================================
2162 12:46:13.152967 LPDDR4 DRAM CONFIGURATION
2163 12:46:13.156437 ===================================
2164 12:46:13.156872 EX_ROW_EN[0] = 0x0
2165 12:46:13.159957 EX_ROW_EN[1] = 0x0
2166 12:46:13.160422 LP4Y_EN = 0x0
2167 12:46:13.162786 WORK_FSP = 0x0
2168 12:46:13.163348 WL = 0x4
2169 12:46:13.166287 RL = 0x4
2170 12:46:13.166851 BL = 0x2
2171 12:46:13.169597 RPST = 0x0
2172 12:46:13.170057 RD_PRE = 0x0
2173 12:46:13.173182 WR_PRE = 0x1
2174 12:46:13.173616 WR_PST = 0x0
2175 12:46:13.175897 DBI_WR = 0x0
2176 12:46:13.176395 DBI_RD = 0x0
2177 12:46:13.179761 OTF = 0x1
2178 12:46:13.182353 ===================================
2179 12:46:13.185819 ===================================
2180 12:46:13.186236 ANA top config
2181 12:46:13.189338 ===================================
2182 12:46:13.192793 DLL_ASYNC_EN = 0
2183 12:46:13.195954 ALL_SLAVE_EN = 0
2184 12:46:13.199030 NEW_RANK_MODE = 1
2185 12:46:13.202862 DLL_IDLE_MODE = 1
2186 12:46:13.203279 LP45_APHY_COMB_EN = 1
2187 12:46:13.205677 TX_ODT_DIS = 1
2188 12:46:13.208965 NEW_8X_MODE = 1
2189 12:46:13.213151 ===================================
2190 12:46:13.215500 ===================================
2191 12:46:13.218606 data_rate = 2400
2192 12:46:13.222222 CKR = 1
2193 12:46:13.222614 DQ_P2S_RATIO = 8
2194 12:46:13.225425 ===================================
2195 12:46:13.228923 CA_P2S_RATIO = 8
2196 12:46:13.232086 DQ_CA_OPEN = 0
2197 12:46:13.236024 DQ_SEMI_OPEN = 0
2198 12:46:13.238657 CA_SEMI_OPEN = 0
2199 12:46:13.242128 CA_FULL_RATE = 0
2200 12:46:13.242543 DQ_CKDIV4_EN = 0
2201 12:46:13.245498 CA_CKDIV4_EN = 0
2202 12:46:13.248509 CA_PREDIV_EN = 0
2203 12:46:13.252121 PH8_DLY = 17
2204 12:46:13.255695 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2205 12:46:13.258820 DQ_AAMCK_DIV = 4
2206 12:46:13.259235 CA_AAMCK_DIV = 4
2207 12:46:13.261867 CA_ADMCK_DIV = 4
2208 12:46:13.265458 DQ_TRACK_CA_EN = 0
2209 12:46:13.268678 CA_PICK = 1200
2210 12:46:13.271682 CA_MCKIO = 1200
2211 12:46:13.275131 MCKIO_SEMI = 0
2212 12:46:13.278582 PLL_FREQ = 2366
2213 12:46:13.281629 DQ_UI_PI_RATIO = 32
2214 12:46:13.282050 CA_UI_PI_RATIO = 0
2215 12:46:13.285784 ===================================
2216 12:46:13.288419 ===================================
2217 12:46:13.291591 memory_type:LPDDR4
2218 12:46:13.294854 GP_NUM : 10
2219 12:46:13.295270 SRAM_EN : 1
2220 12:46:13.298327 MD32_EN : 0
2221 12:46:13.301921 ===================================
2222 12:46:13.305039 [ANA_INIT] >>>>>>>>>>>>>>
2223 12:46:13.308090 <<<<<< [CONFIGURE PHASE]: ANA_TX
2224 12:46:13.311517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2225 12:46:13.314999 ===================================
2226 12:46:13.315419 data_rate = 2400,PCW = 0X5b00
2227 12:46:13.318409 ===================================
2228 12:46:13.321594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2229 12:46:13.328152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2230 12:46:13.334755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2231 12:46:13.338426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2232 12:46:13.341234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2233 12:46:13.344531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2234 12:46:13.347860 [ANA_INIT] flow start
2235 12:46:13.348312 [ANA_INIT] PLL >>>>>>>>
2236 12:46:13.351625 [ANA_INIT] PLL <<<<<<<<
2237 12:46:13.355162 [ANA_INIT] MIDPI >>>>>>>>
2238 12:46:13.357800 [ANA_INIT] MIDPI <<<<<<<<
2239 12:46:13.358216 [ANA_INIT] DLL >>>>>>>>
2240 12:46:13.362010 [ANA_INIT] DLL <<<<<<<<
2241 12:46:13.364123 [ANA_INIT] flow end
2242 12:46:13.367734 ============ LP4 DIFF to SE enter ============
2243 12:46:13.371001 ============ LP4 DIFF to SE exit ============
2244 12:46:13.374885 [ANA_INIT] <<<<<<<<<<<<<
2245 12:46:13.377740 [Flow] Enable top DCM control >>>>>
2246 12:46:13.381197 [Flow] Enable top DCM control <<<<<
2247 12:46:13.384642 Enable DLL master slave shuffle
2248 12:46:13.387896 ==============================================================
2249 12:46:13.390955 Gating Mode config
2250 12:46:13.397814 ==============================================================
2251 12:46:13.398231 Config description:
2252 12:46:13.407444 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2253 12:46:13.414354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2254 12:46:13.417686 SELPH_MODE 0: By rank 1: By Phase
2255 12:46:13.424078 ==============================================================
2256 12:46:13.427267 GAT_TRACK_EN = 1
2257 12:46:13.431014 RX_GATING_MODE = 2
2258 12:46:13.434031 RX_GATING_TRACK_MODE = 2
2259 12:46:13.437402 SELPH_MODE = 1
2260 12:46:13.440717 PICG_EARLY_EN = 1
2261 12:46:13.443647 VALID_LAT_VALUE = 1
2262 12:46:13.447216 ==============================================================
2263 12:46:13.450644 Enter into Gating configuration >>>>
2264 12:46:13.453625 Exit from Gating configuration <<<<
2265 12:46:13.456920 Enter into DVFS_PRE_config >>>>>
2266 12:46:13.470408 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2267 12:46:13.470828 Exit from DVFS_PRE_config <<<<<
2268 12:46:13.474003 Enter into PICG configuration >>>>
2269 12:46:13.477119 Exit from PICG configuration <<<<
2270 12:46:13.480107 [RX_INPUT] configuration >>>>>
2271 12:46:13.483874 [RX_INPUT] configuration <<<<<
2272 12:46:13.490392 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2273 12:46:13.494255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2274 12:46:13.500557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2275 12:46:13.506625 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2276 12:46:13.513562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2277 12:46:13.520209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2278 12:46:13.523200 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2279 12:46:13.526723 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2280 12:46:13.530098 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2281 12:46:13.536440 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2282 12:46:13.540131 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2283 12:46:13.542990 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 12:46:13.546454 ===================================
2285 12:46:13.549506 LPDDR4 DRAM CONFIGURATION
2286 12:46:13.552941 ===================================
2287 12:46:13.556089 EX_ROW_EN[0] = 0x0
2288 12:46:13.556501 EX_ROW_EN[1] = 0x0
2289 12:46:13.559363 LP4Y_EN = 0x0
2290 12:46:13.559761 WORK_FSP = 0x0
2291 12:46:13.563358 WL = 0x4
2292 12:46:13.563814 RL = 0x4
2293 12:46:13.566417 BL = 0x2
2294 12:46:13.566893 RPST = 0x0
2295 12:46:13.569507 RD_PRE = 0x0
2296 12:46:13.569947 WR_PRE = 0x1
2297 12:46:13.573269 WR_PST = 0x0
2298 12:46:13.573734 DBI_WR = 0x0
2299 12:46:13.576066 DBI_RD = 0x0
2300 12:46:13.576543 OTF = 0x1
2301 12:46:13.579497 ===================================
2302 12:46:13.586191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2303 12:46:13.590244 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2304 12:46:13.593545 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2305 12:46:13.595952 ===================================
2306 12:46:13.599668 LPDDR4 DRAM CONFIGURATION
2307 12:46:13.602888 ===================================
2308 12:46:13.606125 EX_ROW_EN[0] = 0x10
2309 12:46:13.606597 EX_ROW_EN[1] = 0x0
2310 12:46:13.609186 LP4Y_EN = 0x0
2311 12:46:13.609661 WORK_FSP = 0x0
2312 12:46:13.612693 WL = 0x4
2313 12:46:13.613159 RL = 0x4
2314 12:46:13.615959 BL = 0x2
2315 12:46:13.616444 RPST = 0x0
2316 12:46:13.619095 RD_PRE = 0x0
2317 12:46:13.619564 WR_PRE = 0x1
2318 12:46:13.622815 WR_PST = 0x0
2319 12:46:13.623239 DBI_WR = 0x0
2320 12:46:13.626246 DBI_RD = 0x0
2321 12:46:13.626667 OTF = 0x1
2322 12:46:13.629266 ===================================
2323 12:46:13.636494 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2324 12:46:13.636934 ==
2325 12:46:13.639527 Dram Type= 6, Freq= 0, CH_0, rank 0
2326 12:46:13.645956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2327 12:46:13.646443 ==
2328 12:46:13.646783 [Duty_Offset_Calibration]
2329 12:46:13.649372 B0:2 B1:0 CA:4
2330 12:46:13.649791
2331 12:46:13.652184 [DutyScan_Calibration_Flow] k_type=0
2332 12:46:13.660623
2333 12:46:13.661098 ==CLK 0==
2334 12:46:13.664247 Final CLK duty delay cell = -4
2335 12:46:13.667563 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2336 12:46:13.671053 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2337 12:46:13.673948 [-4] AVG Duty = 4953%(X100)
2338 12:46:13.674480
2339 12:46:13.677314 CH0 CLK Duty spec in!! Max-Min= 218%
2340 12:46:13.680883 [DutyScan_Calibration_Flow] ====Done====
2341 12:46:13.681355
2342 12:46:13.683831 [DutyScan_Calibration_Flow] k_type=1
2343 12:46:13.700250
2344 12:46:13.700725 ==DQS 0 ==
2345 12:46:13.703223 Final DQS duty delay cell = 0
2346 12:46:13.707112 [0] MAX Duty = 5156%(X100), DQS PI = 18
2347 12:46:13.709864 [0] MIN Duty = 5093%(X100), DQS PI = 0
2348 12:46:13.710298 [0] AVG Duty = 5124%(X100)
2349 12:46:13.713336
2350 12:46:13.713811 ==DQS 1 ==
2351 12:46:13.716585 Final DQS duty delay cell = 0
2352 12:46:13.719947 [0] MAX Duty = 5125%(X100), DQS PI = 48
2353 12:46:13.723172 [0] MIN Duty = 5000%(X100), DQS PI = 0
2354 12:46:13.723603 [0] AVG Duty = 5062%(X100)
2355 12:46:13.726490
2356 12:46:13.729715 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2357 12:46:13.730171
2358 12:46:13.733109 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2359 12:46:13.736667 [DutyScan_Calibration_Flow] ====Done====
2360 12:46:13.737130
2361 12:46:13.740160 [DutyScan_Calibration_Flow] k_type=3
2362 12:46:13.756517
2363 12:46:13.756967 ==DQM 0 ==
2364 12:46:13.759779 Final DQM duty delay cell = 0
2365 12:46:13.762657 [0] MAX Duty = 5125%(X100), DQS PI = 20
2366 12:46:13.766192 [0] MIN Duty = 4844%(X100), DQS PI = 54
2367 12:46:13.769855 [0] AVG Duty = 4984%(X100)
2368 12:46:13.770303
2369 12:46:13.770651 ==DQM 1 ==
2370 12:46:13.772997 Final DQM duty delay cell = 0
2371 12:46:13.776020 [0] MAX Duty = 4969%(X100), DQS PI = 2
2372 12:46:13.779450 [0] MIN Duty = 4876%(X100), DQS PI = 20
2373 12:46:13.782780 [0] AVG Duty = 4922%(X100)
2374 12:46:13.783254
2375 12:46:13.786158 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2376 12:46:13.786612
2377 12:46:13.789505 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2378 12:46:13.793054 [DutyScan_Calibration_Flow] ====Done====
2379 12:46:13.793484
2380 12:46:13.796273 [DutyScan_Calibration_Flow] k_type=2
2381 12:46:13.812679
2382 12:46:13.813106 ==DQ 0 ==
2383 12:46:13.816577 Final DQ duty delay cell = 0
2384 12:46:13.819127 [0] MAX Duty = 5125%(X100), DQS PI = 18
2385 12:46:13.822550 [0] MIN Duty = 4969%(X100), DQS PI = 52
2386 12:46:13.822964 [0] AVG Duty = 5047%(X100)
2387 12:46:13.825983
2388 12:46:13.826412 ==DQ 1 ==
2389 12:46:13.829647 Final DQ duty delay cell = 0
2390 12:46:13.832629 [0] MAX Duty = 5156%(X100), DQS PI = 6
2391 12:46:13.835982 [0] MIN Duty = 4938%(X100), DQS PI = 16
2392 12:46:13.836516 [0] AVG Duty = 5047%(X100)
2393 12:46:13.836880
2394 12:46:13.839491 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2395 12:46:13.842899
2396 12:46:13.846403 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2397 12:46:13.849283 [DutyScan_Calibration_Flow] ====Done====
2398 12:46:13.849807 ==
2399 12:46:13.852887 Dram Type= 6, Freq= 0, CH_1, rank 0
2400 12:46:13.856194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2401 12:46:13.856795 ==
2402 12:46:13.859239 [Duty_Offset_Calibration]
2403 12:46:13.859668 B0:0 B1:-1 CA:3
2404 12:46:13.860092
2405 12:46:13.862787 [DutyScan_Calibration_Flow] k_type=0
2406 12:46:13.871735
2407 12:46:13.872320 ==CLK 0==
2408 12:46:13.875090 Final CLK duty delay cell = -4
2409 12:46:13.879014 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2410 12:46:13.882024 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2411 12:46:13.885152 [-4] AVG Duty = 4938%(X100)
2412 12:46:13.885584
2413 12:46:13.888754 CH1 CLK Duty spec in!! Max-Min= 124%
2414 12:46:13.891626 [DutyScan_Calibration_Flow] ====Done====
2415 12:46:13.892092
2416 12:46:13.895224 [DutyScan_Calibration_Flow] k_type=1
2417 12:46:13.911597
2418 12:46:13.912018 ==DQS 0 ==
2419 12:46:13.915005 Final DQS duty delay cell = 0
2420 12:46:13.918333 [0] MAX Duty = 5187%(X100), DQS PI = 18
2421 12:46:13.921979 [0] MIN Duty = 4907%(X100), DQS PI = 38
2422 12:46:13.924784 [0] AVG Duty = 5047%(X100)
2423 12:46:13.925205
2424 12:46:13.925544 ==DQS 1 ==
2425 12:46:13.928427 Final DQS duty delay cell = 0
2426 12:46:13.931487 [0] MAX Duty = 5156%(X100), DQS PI = 6
2427 12:46:13.934702 [0] MIN Duty = 5031%(X100), DQS PI = 2
2428 12:46:13.937927 [0] AVG Duty = 5093%(X100)
2429 12:46:13.938350
2430 12:46:13.941416 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2431 12:46:13.941840
2432 12:46:13.944586 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2433 12:46:13.948147 [DutyScan_Calibration_Flow] ====Done====
2434 12:46:13.948569
2435 12:46:13.951450 [DutyScan_Calibration_Flow] k_type=3
2436 12:46:13.967732
2437 12:46:13.968288 ==DQM 0 ==
2438 12:46:13.971172 Final DQM duty delay cell = 0
2439 12:46:13.974948 [0] MAX Duty = 5031%(X100), DQS PI = 28
2440 12:46:13.977537 [0] MIN Duty = 4813%(X100), DQS PI = 38
2441 12:46:13.981304 [0] AVG Duty = 4922%(X100)
2442 12:46:13.981725
2443 12:46:13.982056 ==DQM 1 ==
2444 12:46:13.984178 Final DQM duty delay cell = 0
2445 12:46:13.987838 [0] MAX Duty = 4969%(X100), DQS PI = 32
2446 12:46:13.991448 [0] MIN Duty = 4844%(X100), DQS PI = 0
2447 12:46:13.994371 [0] AVG Duty = 4906%(X100)
2448 12:46:13.994795
2449 12:46:13.997794 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2450 12:46:13.998216
2451 12:46:14.001291 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2452 12:46:14.004376 [DutyScan_Calibration_Flow] ====Done====
2453 12:46:14.004800
2454 12:46:14.007831 [DutyScan_Calibration_Flow] k_type=2
2455 12:46:14.023931
2456 12:46:14.024469 ==DQ 0 ==
2457 12:46:14.026788 Final DQ duty delay cell = -4
2458 12:46:14.030223 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2459 12:46:14.033682 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2460 12:46:14.037112 [-4] AVG Duty = 4937%(X100)
2461 12:46:14.037594
2462 12:46:14.037990 ==DQ 1 ==
2463 12:46:14.040322 Final DQ duty delay cell = 0
2464 12:46:14.043455 [0] MAX Duty = 5031%(X100), DQS PI = 34
2465 12:46:14.047036 [0] MIN Duty = 4844%(X100), DQS PI = 62
2466 12:46:14.050339 [0] AVG Duty = 4937%(X100)
2467 12:46:14.050767
2468 12:46:14.054107 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2469 12:46:14.054586
2470 12:46:14.057189 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2471 12:46:14.060214 [DutyScan_Calibration_Flow] ====Done====
2472 12:46:14.063539 nWR fixed to 30
2473 12:46:14.063958 [ModeRegInit_LP4] CH0 RK0
2474 12:46:14.066916 [ModeRegInit_LP4] CH0 RK1
2475 12:46:14.070427 [ModeRegInit_LP4] CH1 RK0
2476 12:46:14.073445 [ModeRegInit_LP4] CH1 RK1
2477 12:46:14.073909 match AC timing 7
2478 12:46:14.080349 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2479 12:46:14.083851 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2480 12:46:14.086540 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2481 12:46:14.093249 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2482 12:46:14.096883 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2483 12:46:14.097303 ==
2484 12:46:14.099863 Dram Type= 6, Freq= 0, CH_0, rank 0
2485 12:46:14.103052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 12:46:14.103472 ==
2487 12:46:14.109574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 12:46:14.116162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2489 12:46:14.124065 [CA 0] Center 39 (9~70) winsize 62
2490 12:46:14.127323 [CA 1] Center 39 (9~70) winsize 62
2491 12:46:14.130379 [CA 2] Center 35 (5~66) winsize 62
2492 12:46:14.133863 [CA 3] Center 35 (5~66) winsize 62
2493 12:46:14.136940 [CA 4] Center 33 (3~64) winsize 62
2494 12:46:14.140738 [CA 5] Center 33 (3~63) winsize 61
2495 12:46:14.141204
2496 12:46:14.144014 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2497 12:46:14.144563
2498 12:46:14.147333 [CATrainingPosCal] consider 1 rank data
2499 12:46:14.150641 u2DelayCellTimex100 = 270/100 ps
2500 12:46:14.153891 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 12:46:14.160238 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2502 12:46:14.164024 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 12:46:14.166748 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 12:46:14.170086 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2505 12:46:14.173437 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2506 12:46:14.173861
2507 12:46:14.176969 CA PerBit enable=1, Macro0, CA PI delay=33
2508 12:46:14.177393
2509 12:46:14.180170 [CBTSetCACLKResult] CA Dly = 33
2510 12:46:14.183100 CS Dly: 7 (0~38)
2511 12:46:14.183557 ==
2512 12:46:14.186774 Dram Type= 6, Freq= 0, CH_0, rank 1
2513 12:46:14.190227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 12:46:14.190646 ==
2515 12:46:14.196636 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 12:46:14.199623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 12:46:14.209553 [CA 0] Center 39 (9~70) winsize 62
2518 12:46:14.213067 [CA 1] Center 39 (9~70) winsize 62
2519 12:46:14.216121 [CA 2] Center 35 (5~66) winsize 62
2520 12:46:14.219552 [CA 3] Center 35 (5~66) winsize 62
2521 12:46:14.223156 [CA 4] Center 34 (4~65) winsize 62
2522 12:46:14.226165 [CA 5] Center 33 (3~64) winsize 62
2523 12:46:14.226736
2524 12:46:14.229434 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2525 12:46:14.229893
2526 12:46:14.233283 [CATrainingPosCal] consider 2 rank data
2527 12:46:14.236324 u2DelayCellTimex100 = 270/100 ps
2528 12:46:14.239144 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 12:46:14.245914 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2530 12:46:14.249425 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2531 12:46:14.252739 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 12:46:14.256133 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2533 12:46:14.259283 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2534 12:46:14.259758
2535 12:46:14.262252 CA PerBit enable=1, Macro0, CA PI delay=33
2536 12:46:14.262664
2537 12:46:14.265727 [CBTSetCACLKResult] CA Dly = 33
2538 12:46:14.269449 CS Dly: 8 (0~41)
2539 12:46:14.269862
2540 12:46:14.272370 ----->DramcWriteLeveling(PI) begin...
2541 12:46:14.272787 ==
2542 12:46:14.276059 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 12:46:14.279013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2544 12:46:14.279428 ==
2545 12:46:14.282197 Write leveling (Byte 0): 33 => 33
2546 12:46:14.285567 Write leveling (Byte 1): 26 => 26
2547 12:46:14.288630 DramcWriteLeveling(PI) end<-----
2548 12:46:14.289048
2549 12:46:14.289375 ==
2550 12:46:14.292329 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 12:46:14.295728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 12:46:14.296228 ==
2553 12:46:14.298917 [Gating] SW mode calibration
2554 12:46:14.305506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2555 12:46:14.312263 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2556 12:46:14.315195 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2557 12:46:14.318587 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2558 12:46:14.325438 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 12:46:14.328681 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 12:46:14.332336 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 12:46:14.338357 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 12:46:14.341920 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2563 12:46:14.344885 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2564 12:46:14.352079 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2565 12:46:14.355771 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2566 12:46:14.358404 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 12:46:14.365200 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 12:46:14.368286 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 12:46:14.371399 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 12:46:14.378246 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2571 12:46:14.381545 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2572 12:46:14.384557 1 1 0 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
2573 12:46:14.391630 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2574 12:46:14.395095 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 12:46:14.398269 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 12:46:14.404797 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 12:46:14.407696 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 12:46:14.410990 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2579 12:46:14.417773 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2580 12:46:14.421413 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2581 12:46:14.424511 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2582 12:46:14.431102 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 12:46:14.434127 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 12:46:14.438001 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 12:46:14.444251 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 12:46:14.447895 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 12:46:14.451190 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 12:46:14.457915 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 12:46:14.461060 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 12:46:14.464094 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 12:46:14.467731 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 12:46:14.474117 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 12:46:14.478176 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 12:46:14.481291 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2595 12:46:14.487535 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2596 12:46:14.490726 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2597 12:46:14.494409 Total UI for P1: 0, mck2ui 16
2598 12:46:14.497634 best dqsien dly found for B0: ( 1, 3, 26)
2599 12:46:14.501697 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2600 12:46:14.507547 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 12:46:14.510662 Total UI for P1: 0, mck2ui 16
2602 12:46:14.514266 best dqsien dly found for B1: ( 1, 4, 2)
2603 12:46:14.517375 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2604 12:46:14.520707 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2605 12:46:14.521130
2606 12:46:14.524020 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2607 12:46:14.527463 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2608 12:46:14.530457 [Gating] SW calibration Done
2609 12:46:14.530871 ==
2610 12:46:14.534314 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 12:46:14.537643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 12:46:14.538056 ==
2613 12:46:14.540796 RX Vref Scan: 0
2614 12:46:14.541228
2615 12:46:14.541558 RX Vref 0 -> 0, step: 1
2616 12:46:14.541862
2617 12:46:14.543986 RX Delay -40 -> 252, step: 8
2618 12:46:14.550606 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2619 12:46:14.554414 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2620 12:46:14.557544 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2621 12:46:14.560627 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2622 12:46:14.564075 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2623 12:46:14.570644 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2624 12:46:14.573996 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2625 12:46:14.577454 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2626 12:46:14.580462 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2627 12:46:14.583687 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2628 12:46:14.587014 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2629 12:46:14.593549 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2630 12:46:14.596965 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2631 12:46:14.600163 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2632 12:46:14.603225 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2633 12:46:14.610225 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2634 12:46:14.610644 ==
2635 12:46:14.613276 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 12:46:14.616787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 12:46:14.617204 ==
2638 12:46:14.617531 DQS Delay:
2639 12:46:14.619771 DQS0 = 0, DQS1 = 0
2640 12:46:14.620262 DQM Delay:
2641 12:46:14.623434 DQM0 = 118, DQM1 = 107
2642 12:46:14.623851 DQ Delay:
2643 12:46:14.627283 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2644 12:46:14.630482 DQ4 =123, DQ5 =111, DQ6 =123, DQ7 =123
2645 12:46:14.633439 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2646 12:46:14.636542 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2647 12:46:14.637012
2648 12:46:14.637350
2649 12:46:14.640062 ==
2650 12:46:14.643500 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 12:46:14.646784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 12:46:14.647248 ==
2653 12:46:14.647634
2654 12:46:14.647954
2655 12:46:14.649773 TX Vref Scan disable
2656 12:46:14.650228 == TX Byte 0 ==
2657 12:46:14.653067 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2658 12:46:14.659856 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2659 12:46:14.660339 == TX Byte 1 ==
2660 12:46:14.663098 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2661 12:46:14.670232 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2662 12:46:14.670716 ==
2663 12:46:14.672970 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 12:46:14.676286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 12:46:14.676786 ==
2666 12:46:14.688556 TX Vref=22, minBit 0, minWin=25, winSum=412
2667 12:46:14.692695 TX Vref=24, minBit 5, minWin=25, winSum=417
2668 12:46:14.695754 TX Vref=26, minBit 13, minWin=25, winSum=423
2669 12:46:14.698773 TX Vref=28, minBit 4, minWin=26, winSum=429
2670 12:46:14.702224 TX Vref=30, minBit 1, minWin=26, winSum=431
2671 12:46:14.708654 TX Vref=32, minBit 2, minWin=26, winSum=428
2672 12:46:14.712127 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
2673 12:46:14.712711
2674 12:46:14.715842 Final TX Range 1 Vref 30
2675 12:46:14.716375
2676 12:46:14.716710 ==
2677 12:46:14.719378 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 12:46:14.722384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 12:46:14.722802 ==
2680 12:46:14.725720
2681 12:46:14.726134
2682 12:46:14.726464 TX Vref Scan disable
2683 12:46:14.728769 == TX Byte 0 ==
2684 12:46:14.731931 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2685 12:46:14.738620 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2686 12:46:14.739086 == TX Byte 1 ==
2687 12:46:14.741646 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2688 12:46:14.748531 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2689 12:46:14.748990
2690 12:46:14.749320 [DATLAT]
2691 12:46:14.749676 Freq=1200, CH0 RK0
2692 12:46:14.749981
2693 12:46:14.751859 DATLAT Default: 0xd
2694 12:46:14.755246 0, 0xFFFF, sum = 0
2695 12:46:14.755689 1, 0xFFFF, sum = 0
2696 12:46:14.758383 2, 0xFFFF, sum = 0
2697 12:46:14.758785 3, 0xFFFF, sum = 0
2698 12:46:14.761823 4, 0xFFFF, sum = 0
2699 12:46:14.762222 5, 0xFFFF, sum = 0
2700 12:46:14.765004 6, 0xFFFF, sum = 0
2701 12:46:14.765371 7, 0xFFFF, sum = 0
2702 12:46:14.768892 8, 0xFFFF, sum = 0
2703 12:46:14.769280 9, 0xFFFF, sum = 0
2704 12:46:14.771756 10, 0xFFFF, sum = 0
2705 12:46:14.772159 11, 0xFFFF, sum = 0
2706 12:46:14.775397 12, 0x0, sum = 1
2707 12:46:14.775798 13, 0x0, sum = 2
2708 12:46:14.778564 14, 0x0, sum = 3
2709 12:46:14.778938 15, 0x0, sum = 4
2710 12:46:14.781408 best_step = 13
2711 12:46:14.781783
2712 12:46:14.782100 ==
2713 12:46:14.784670 Dram Type= 6, Freq= 0, CH_0, rank 0
2714 12:46:14.788155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2715 12:46:14.788608 ==
2716 12:46:14.791492 RX Vref Scan: 1
2717 12:46:14.792166
2718 12:46:14.792706 Set Vref Range= 32 -> 127
2719 12:46:14.793266
2720 12:46:14.794634 RX Vref 32 -> 127, step: 1
2721 12:46:14.795240
2722 12:46:14.798221 RX Delay -21 -> 252, step: 4
2723 12:46:14.798830
2724 12:46:14.801132 Set Vref, RX VrefLevel [Byte0]: 32
2725 12:46:14.805017 [Byte1]: 32
2726 12:46:14.805474
2727 12:46:14.808542 Set Vref, RX VrefLevel [Byte0]: 33
2728 12:46:14.811083 [Byte1]: 33
2729 12:46:14.815410
2730 12:46:14.815822 Set Vref, RX VrefLevel [Byte0]: 34
2731 12:46:14.819205 [Byte1]: 34
2732 12:46:14.823201
2733 12:46:14.823610 Set Vref, RX VrefLevel [Byte0]: 35
2734 12:46:14.826659 [Byte1]: 35
2735 12:46:14.830862
2736 12:46:14.831273 Set Vref, RX VrefLevel [Byte0]: 36
2737 12:46:14.834253 [Byte1]: 36
2738 12:46:14.838984
2739 12:46:14.839536 Set Vref, RX VrefLevel [Byte0]: 37
2740 12:46:14.842339 [Byte1]: 37
2741 12:46:14.846972
2742 12:46:14.847383 Set Vref, RX VrefLevel [Byte0]: 38
2743 12:46:14.850278 [Byte1]: 38
2744 12:46:14.855158
2745 12:46:14.855570 Set Vref, RX VrefLevel [Byte0]: 39
2746 12:46:14.858196 [Byte1]: 39
2747 12:46:14.863227
2748 12:46:14.863636 Set Vref, RX VrefLevel [Byte0]: 40
2749 12:46:14.866168 [Byte1]: 40
2750 12:46:14.870729
2751 12:46:14.871138 Set Vref, RX VrefLevel [Byte0]: 41
2752 12:46:14.873911 [Byte1]: 41
2753 12:46:14.879022
2754 12:46:14.879434 Set Vref, RX VrefLevel [Byte0]: 42
2755 12:46:14.881996 [Byte1]: 42
2756 12:46:14.886680
2757 12:46:14.887089 Set Vref, RX VrefLevel [Byte0]: 43
2758 12:46:14.889912 [Byte1]: 43
2759 12:46:14.894569
2760 12:46:14.894980 Set Vref, RX VrefLevel [Byte0]: 44
2761 12:46:14.897617 [Byte1]: 44
2762 12:46:14.902409
2763 12:46:14.902820 Set Vref, RX VrefLevel [Byte0]: 45
2764 12:46:14.905897 [Byte1]: 45
2765 12:46:14.910733
2766 12:46:14.911144 Set Vref, RX VrefLevel [Byte0]: 46
2767 12:46:14.913505 [Byte1]: 46
2768 12:46:14.918535
2769 12:46:14.918946 Set Vref, RX VrefLevel [Byte0]: 47
2770 12:46:14.921445 [Byte1]: 47
2771 12:46:14.926623
2772 12:46:14.927032 Set Vref, RX VrefLevel [Byte0]: 48
2773 12:46:14.929765 [Byte1]: 48
2774 12:46:14.934019
2775 12:46:14.934508 Set Vref, RX VrefLevel [Byte0]: 49
2776 12:46:14.937580 [Byte1]: 49
2777 12:46:14.942117
2778 12:46:14.942560 Set Vref, RX VrefLevel [Byte0]: 50
2779 12:46:14.945329 [Byte1]: 50
2780 12:46:14.950011
2781 12:46:14.950471 Set Vref, RX VrefLevel [Byte0]: 51
2782 12:46:14.953040 [Byte1]: 51
2783 12:46:14.957975
2784 12:46:14.958366 Set Vref, RX VrefLevel [Byte0]: 52
2785 12:46:14.961006 [Byte1]: 52
2786 12:46:14.965557
2787 12:46:14.965976 Set Vref, RX VrefLevel [Byte0]: 53
2788 12:46:14.968890 [Byte1]: 53
2789 12:46:14.973305
2790 12:46:14.973692 Set Vref, RX VrefLevel [Byte0]: 54
2791 12:46:14.977124 [Byte1]: 54
2792 12:46:14.981428
2793 12:46:14.981867 Set Vref, RX VrefLevel [Byte0]: 55
2794 12:46:14.985103 [Byte1]: 55
2795 12:46:14.989314
2796 12:46:14.989730 Set Vref, RX VrefLevel [Byte0]: 56
2797 12:46:14.992852 [Byte1]: 56
2798 12:46:14.997370
2799 12:46:14.997772 Set Vref, RX VrefLevel [Byte0]: 57
2800 12:46:15.000811 [Byte1]: 57
2801 12:46:15.005430
2802 12:46:15.005861 Set Vref, RX VrefLevel [Byte0]: 58
2803 12:46:15.008709 [Byte1]: 58
2804 12:46:15.013693
2805 12:46:15.014131 Set Vref, RX VrefLevel [Byte0]: 59
2806 12:46:15.016292 [Byte1]: 59
2807 12:46:15.021512
2808 12:46:15.021909 Set Vref, RX VrefLevel [Byte0]: 60
2809 12:46:15.024506 [Byte1]: 60
2810 12:46:15.029252
2811 12:46:15.029674 Set Vref, RX VrefLevel [Byte0]: 61
2812 12:46:15.032933 [Byte1]: 61
2813 12:46:15.036968
2814 12:46:15.037555 Set Vref, RX VrefLevel [Byte0]: 62
2815 12:46:15.040463 [Byte1]: 62
2816 12:46:15.044798
2817 12:46:15.045256 Set Vref, RX VrefLevel [Byte0]: 63
2818 12:46:15.048592 [Byte1]: 63
2819 12:46:15.052743
2820 12:46:15.052823 Set Vref, RX VrefLevel [Byte0]: 64
2821 12:46:15.056025 [Byte1]: 64
2822 12:46:15.060627
2823 12:46:15.060707 Set Vref, RX VrefLevel [Byte0]: 65
2824 12:46:15.063591 [Byte1]: 65
2825 12:46:15.068944
2826 12:46:15.069024 Set Vref, RX VrefLevel [Byte0]: 66
2827 12:46:15.071660 [Byte1]: 66
2828 12:46:15.076345
2829 12:46:15.076455 Set Vref, RX VrefLevel [Byte0]: 67
2830 12:46:15.079796 [Byte1]: 67
2831 12:46:15.084149
2832 12:46:15.084229 Set Vref, RX VrefLevel [Byte0]: 68
2833 12:46:15.087608 [Byte1]: 68
2834 12:46:15.092083
2835 12:46:15.092163 Final RX Vref Byte 0 = 52 to rank0
2836 12:46:15.096024 Final RX Vref Byte 1 = 59 to rank0
2837 12:46:15.098608 Final RX Vref Byte 0 = 52 to rank1
2838 12:46:15.101807 Final RX Vref Byte 1 = 59 to rank1==
2839 12:46:15.105451 Dram Type= 6, Freq= 0, CH_0, rank 0
2840 12:46:15.112296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 12:46:15.112378 ==
2842 12:46:15.112442 DQS Delay:
2843 12:46:15.112501 DQS0 = 0, DQS1 = 0
2844 12:46:15.116196 DQM Delay:
2845 12:46:15.116277 DQM0 = 116, DQM1 = 105
2846 12:46:15.118686 DQ Delay:
2847 12:46:15.122007 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2848 12:46:15.125611 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =120
2849 12:46:15.128809 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2850 12:46:15.132006 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2851 12:46:15.132111
2852 12:46:15.132174
2853 12:46:15.139012 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
2854 12:46:15.141980 CH0 RK0: MR19=403, MR18=FC
2855 12:46:15.148863 CH0_RK0: MR19=0x403, MR18=0xFC, DQSOSC=410, MR23=63, INC=39, DEC=26
2856 12:46:15.148944
2857 12:46:15.152151 ----->DramcWriteLeveling(PI) begin...
2858 12:46:15.152262 ==
2859 12:46:15.155560 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 12:46:15.159248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 12:46:15.159329 ==
2862 12:46:15.162190 Write leveling (Byte 0): 30 => 30
2863 12:46:15.165756 Write leveling (Byte 1): 25 => 25
2864 12:46:15.169078 DramcWriteLeveling(PI) end<-----
2865 12:46:15.169158
2866 12:46:15.169221 ==
2867 12:46:15.172212 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 12:46:15.175345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 12:46:15.178810 ==
2870 12:46:15.178916 [Gating] SW mode calibration
2871 12:46:15.188831 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2872 12:46:15.191906 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2873 12:46:15.195453 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2874 12:46:15.201722 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2875 12:46:15.205092 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 12:46:15.208448 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 12:46:15.214839 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 12:46:15.218468 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 12:46:15.221663 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2880 12:46:15.228184 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 1) (0 0)
2881 12:46:15.231591 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2882 12:46:15.234662 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 12:46:15.241007 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 12:46:15.244834 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 12:46:15.247599 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 12:46:15.254188 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 12:46:15.257992 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2888 12:46:15.261466 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
2889 12:46:15.267755 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2890 12:46:15.270889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 12:46:15.274239 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 12:46:15.280920 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 12:46:15.284329 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 12:46:15.287595 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 12:46:15.293975 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2896 12:46:15.297184 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2897 12:46:15.300417 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 12:46:15.307150 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 12:46:15.310596 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 12:46:15.313440 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 12:46:15.320376 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 12:46:15.323896 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 12:46:15.326983 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 12:46:15.333622 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 12:46:15.336735 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 12:46:15.340346 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 12:46:15.346921 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 12:46:15.350578 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 12:46:15.353974 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 12:46:15.359943 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 12:46:15.363228 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2912 12:46:15.366725 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2913 12:46:15.373468 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2914 12:46:15.373570 Total UI for P1: 0, mck2ui 16
2915 12:46:15.380207 best dqsien dly found for B0: ( 1, 3, 26)
2916 12:46:15.383238 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 12:46:15.386881 Total UI for P1: 0, mck2ui 16
2918 12:46:15.389783 best dqsien dly found for B1: ( 1, 4, 0)
2919 12:46:15.393392 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2920 12:46:15.396423 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2921 12:46:15.396503
2922 12:46:15.399968 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2923 12:46:15.402891 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2924 12:46:15.406275 [Gating] SW calibration Done
2925 12:46:15.406348 ==
2926 12:46:15.409744 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 12:46:15.412841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 12:46:15.416388 ==
2929 12:46:15.416488 RX Vref Scan: 0
2930 12:46:15.416578
2931 12:46:15.419649 RX Vref 0 -> 0, step: 1
2932 12:46:15.419747
2933 12:46:15.422740 RX Delay -40 -> 252, step: 8
2934 12:46:15.426290 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2935 12:46:15.429755 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2936 12:46:15.432980 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2937 12:46:15.436733 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2938 12:46:15.442713 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2939 12:46:15.446263 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2940 12:46:15.449521 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2941 12:46:15.452993 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2942 12:46:15.456414 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2943 12:46:15.459282 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2944 12:46:15.466443 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2945 12:46:15.469150 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2946 12:46:15.472466 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2947 12:46:15.475964 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2948 12:46:15.482525 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2949 12:46:15.485798 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2950 12:46:15.485880 ==
2951 12:46:15.489135 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 12:46:15.492556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 12:46:15.492638 ==
2954 12:46:15.495805 DQS Delay:
2955 12:46:15.495890 DQS0 = 0, DQS1 = 0
2956 12:46:15.495973 DQM Delay:
2957 12:46:15.499279 DQM0 = 117, DQM1 = 110
2958 12:46:15.499355 DQ Delay:
2959 12:46:15.502354 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =115
2960 12:46:15.505470 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =119
2961 12:46:15.509031 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2962 12:46:15.515844 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2963 12:46:15.515927
2964 12:46:15.516027
2965 12:46:15.516147 ==
2966 12:46:15.518813 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 12:46:15.522413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 12:46:15.522489 ==
2969 12:46:15.522569
2970 12:46:15.522651
2971 12:46:15.525450 TX Vref Scan disable
2972 12:46:15.525525 == TX Byte 0 ==
2973 12:46:15.531844 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2974 12:46:15.535547 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2975 12:46:15.535624 == TX Byte 1 ==
2976 12:46:15.542277 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2977 12:46:15.545521 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2978 12:46:15.545599 ==
2979 12:46:15.548818 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 12:46:15.552100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 12:46:15.552175 ==
2982 12:46:15.565377 TX Vref=22, minBit 4, minWin=25, winSum=414
2983 12:46:15.568581 TX Vref=24, minBit 2, minWin=25, winSum=415
2984 12:46:15.572438 TX Vref=26, minBit 0, minWin=26, winSum=423
2985 12:46:15.575402 TX Vref=28, minBit 1, minWin=26, winSum=425
2986 12:46:15.578824 TX Vref=30, minBit 0, minWin=26, winSum=426
2987 12:46:15.582004 TX Vref=32, minBit 0, minWin=26, winSum=422
2988 12:46:15.588500 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2989 12:46:15.588588
2990 12:46:15.591700 Final TX Range 1 Vref 30
2991 12:46:15.591779
2992 12:46:15.591860 ==
2993 12:46:15.595437 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 12:46:15.598273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 12:46:15.598351 ==
2996 12:46:15.601762
2997 12:46:15.601837
2998 12:46:15.601916 TX Vref Scan disable
2999 12:46:15.604931 == TX Byte 0 ==
3000 12:46:15.608213 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3001 12:46:15.615641 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3002 12:46:15.615723 == TX Byte 1 ==
3003 12:46:15.618103 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3004 12:46:15.624810 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3005 12:46:15.624891
3006 12:46:15.624973 [DATLAT]
3007 12:46:15.625050 Freq=1200, CH0 RK1
3008 12:46:15.625126
3009 12:46:15.627981 DATLAT Default: 0xd
3010 12:46:15.631319 0, 0xFFFF, sum = 0
3011 12:46:15.631398 1, 0xFFFF, sum = 0
3012 12:46:15.634904 2, 0xFFFF, sum = 0
3013 12:46:15.634980 3, 0xFFFF, sum = 0
3014 12:46:15.637996 4, 0xFFFF, sum = 0
3015 12:46:15.638073 5, 0xFFFF, sum = 0
3016 12:46:15.641341 6, 0xFFFF, sum = 0
3017 12:46:15.641417 7, 0xFFFF, sum = 0
3018 12:46:15.644320 8, 0xFFFF, sum = 0
3019 12:46:15.644397 9, 0xFFFF, sum = 0
3020 12:46:15.648172 10, 0xFFFF, sum = 0
3021 12:46:15.648245 11, 0xFFFF, sum = 0
3022 12:46:15.651475 12, 0x0, sum = 1
3023 12:46:15.651549 13, 0x0, sum = 2
3024 12:46:15.654598 14, 0x0, sum = 3
3025 12:46:15.654674 15, 0x0, sum = 4
3026 12:46:15.657758 best_step = 13
3027 12:46:15.657831
3028 12:46:15.657909 ==
3029 12:46:15.661119 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 12:46:15.664474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 12:46:15.664552 ==
3032 12:46:15.664631 RX Vref Scan: 0
3033 12:46:15.667954
3034 12:46:15.668061 RX Vref 0 -> 0, step: 1
3035 12:46:15.668153
3036 12:46:15.671241 RX Delay -21 -> 252, step: 4
3037 12:46:15.677849 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3038 12:46:15.681245 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3039 12:46:15.684589 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3040 12:46:15.688350 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3041 12:46:15.691302 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3042 12:46:15.697557 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3043 12:46:15.701474 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3044 12:46:15.704629 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3045 12:46:15.707596 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3046 12:46:15.711001 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3047 12:46:15.717286 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3048 12:46:15.720904 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3049 12:46:15.724146 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3050 12:46:15.727438 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3051 12:46:15.730594 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3052 12:46:15.737589 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3053 12:46:15.737668 ==
3054 12:46:15.740945 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 12:46:15.743803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 12:46:15.743880 ==
3057 12:46:15.743965 DQS Delay:
3058 12:46:15.747384 DQS0 = 0, DQS1 = 0
3059 12:46:15.747459 DQM Delay:
3060 12:46:15.750544 DQM0 = 115, DQM1 = 106
3061 12:46:15.750619 DQ Delay:
3062 12:46:15.754274 DQ0 =112, DQ1 =116, DQ2 =110, DQ3 =112
3063 12:46:15.757021 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3064 12:46:15.760817 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3065 12:46:15.763801 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =112
3066 12:46:15.763881
3067 12:46:15.763980
3068 12:46:15.773864 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3069 12:46:15.777148 CH0 RK1: MR19=303, MR18=FFFD
3070 12:46:15.783860 CH0_RK1: MR19=0x303, MR18=0xFFFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3071 12:46:15.783944 [RxdqsGatingPostProcess] freq 1200
3072 12:46:15.790531 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3073 12:46:15.793533 best DQS0 dly(2T, 0.5T) = (0, 11)
3074 12:46:15.796976 best DQS1 dly(2T, 0.5T) = (0, 12)
3075 12:46:15.800338 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3076 12:46:15.803233 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3077 12:46:15.806678 best DQS0 dly(2T, 0.5T) = (0, 11)
3078 12:46:15.810192 best DQS1 dly(2T, 0.5T) = (0, 12)
3079 12:46:15.813601 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3080 12:46:15.816538 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3081 12:46:15.820003 Pre-setting of DQS Precalculation
3082 12:46:15.823621 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3083 12:46:15.823708 ==
3084 12:46:15.826940 Dram Type= 6, Freq= 0, CH_1, rank 0
3085 12:46:15.833407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 12:46:15.833491 ==
3087 12:46:15.837066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3088 12:46:15.843170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3089 12:46:15.851309 [CA 0] Center 38 (8~68) winsize 61
3090 12:46:15.854764 [CA 1] Center 37 (7~68) winsize 62
3091 12:46:15.857960 [CA 2] Center 35 (6~65) winsize 60
3092 12:46:15.861547 [CA 3] Center 34 (4~64) winsize 61
3093 12:46:15.864536 [CA 4] Center 35 (5~65) winsize 61
3094 12:46:15.867606 [CA 5] Center 33 (3~63) winsize 61
3095 12:46:15.867681
3096 12:46:15.871034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3097 12:46:15.871109
3098 12:46:15.874692 [CATrainingPosCal] consider 1 rank data
3099 12:46:15.877924 u2DelayCellTimex100 = 270/100 ps
3100 12:46:15.880990 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3101 12:46:15.887882 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3102 12:46:15.890907 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3103 12:46:15.894264 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 12:46:15.897808 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3105 12:46:15.901271 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3106 12:46:15.901347
3107 12:46:15.904823 CA PerBit enable=1, Macro0, CA PI delay=33
3108 12:46:15.904900
3109 12:46:15.907560 [CBTSetCACLKResult] CA Dly = 33
3110 12:46:15.907638 CS Dly: 4 (0~35)
3111 12:46:15.911390 ==
3112 12:46:15.914422 Dram Type= 6, Freq= 0, CH_1, rank 1
3113 12:46:15.917462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 12:46:15.917551 ==
3115 12:46:15.920779 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 12:46:15.927634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3117 12:46:15.936977 [CA 0] Center 38 (8~68) winsize 61
3118 12:46:15.940076 [CA 1] Center 37 (7~68) winsize 62
3119 12:46:15.943763 [CA 2] Center 35 (5~65) winsize 61
3120 12:46:15.947320 [CA 3] Center 33 (3~64) winsize 62
3121 12:46:15.950342 [CA 4] Center 34 (4~64) winsize 61
3122 12:46:15.954673 [CA 5] Center 33 (3~64) winsize 62
3123 12:46:15.954756
3124 12:46:15.957195 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3125 12:46:15.957276
3126 12:46:15.960738 [CATrainingPosCal] consider 2 rank data
3127 12:46:15.963822 u2DelayCellTimex100 = 270/100 ps
3128 12:46:15.966670 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3129 12:46:15.973176 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 12:46:15.977219 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3131 12:46:15.980415 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 12:46:15.983622 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3133 12:46:15.986903 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3134 12:46:15.986988
3135 12:46:15.990053 CA PerBit enable=1, Macro0, CA PI delay=33
3136 12:46:15.990134
3137 12:46:15.993905 [CBTSetCACLKResult] CA Dly = 33
3138 12:46:15.993985 CS Dly: 6 (0~39)
3139 12:46:15.996620
3140 12:46:15.999948 ----->DramcWriteLeveling(PI) begin...
3141 12:46:16.000047 ==
3142 12:46:16.003284 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 12:46:16.006523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 12:46:16.006601 ==
3145 12:46:16.009970 Write leveling (Byte 0): 24 => 24
3146 12:46:16.013633 Write leveling (Byte 1): 27 => 27
3147 12:46:16.016912 DramcWriteLeveling(PI) end<-----
3148 12:46:16.016992
3149 12:46:16.017074 ==
3150 12:46:16.019695 Dram Type= 6, Freq= 0, CH_1, rank 0
3151 12:46:16.023185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 12:46:16.023262 ==
3153 12:46:16.026182 [Gating] SW mode calibration
3154 12:46:16.033015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3155 12:46:16.039569 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3156 12:46:16.042869 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (0 0)
3157 12:46:16.046285 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 12:46:16.052762 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 12:46:16.056160 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 12:46:16.059553 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 12:46:16.066192 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 12:46:16.069953 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3163 12:46:16.073064 0 15 28 | B1->B0 | 2d2d 2727 | 0 0 | (0 1) (0 0)
3164 12:46:16.079303 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 12:46:16.082965 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 12:46:16.086061 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 12:46:16.089359 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 12:46:16.096145 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 12:46:16.099987 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 12:46:16.106277 1 0 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
3171 12:46:16.109330 1 0 28 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
3172 12:46:16.112845 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 12:46:16.115847 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 12:46:16.122448 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 12:46:16.125946 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 12:46:16.129033 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 12:46:16.135809 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 12:46:16.138964 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 12:46:16.142732 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3180 12:46:16.148869 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3181 12:46:16.152283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 12:46:16.155510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 12:46:16.162324 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 12:46:16.165943 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 12:46:16.169076 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 12:46:16.175411 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 12:46:16.178743 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 12:46:16.182150 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 12:46:16.188463 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 12:46:16.191951 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 12:46:16.195172 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 12:46:16.202014 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 12:46:16.205464 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 12:46:16.208212 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 12:46:16.215347 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3196 12:46:16.218980 Total UI for P1: 0, mck2ui 16
3197 12:46:16.222219 best dqsien dly found for B0: ( 1, 3, 26)
3198 12:46:16.225127 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 12:46:16.228730 Total UI for P1: 0, mck2ui 16
3200 12:46:16.231622 best dqsien dly found for B1: ( 1, 3, 28)
3201 12:46:16.234981 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3202 12:46:16.238763 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3203 12:46:16.238841
3204 12:46:16.241922 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3205 12:46:16.244819 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3206 12:46:16.248117 [Gating] SW calibration Done
3207 12:46:16.248194 ==
3208 12:46:16.251699 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 12:46:16.258196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 12:46:16.258275 ==
3211 12:46:16.258357 RX Vref Scan: 0
3212 12:46:16.258435
3213 12:46:16.261430 RX Vref 0 -> 0, step: 1
3214 12:46:16.261505
3215 12:46:16.264744 RX Delay -40 -> 252, step: 8
3216 12:46:16.267773 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3217 12:46:16.271413 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3218 12:46:16.275398 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3219 12:46:16.278024 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3220 12:46:16.284705 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3221 12:46:16.287762 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3222 12:46:16.291583 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3223 12:46:16.294529 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3224 12:46:16.298051 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3225 12:46:16.304402 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3226 12:46:16.308209 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3227 12:46:16.311325 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3228 12:46:16.314780 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3229 12:46:16.320934 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3230 12:46:16.324304 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3231 12:46:16.327866 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3232 12:46:16.327947 ==
3233 12:46:16.330965 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 12:46:16.334236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 12:46:16.334339 ==
3236 12:46:16.337810 DQS Delay:
3237 12:46:16.337890 DQS0 = 0, DQS1 = 0
3238 12:46:16.340970 DQM Delay:
3239 12:46:16.341051 DQM0 = 116, DQM1 = 112
3240 12:46:16.341115 DQ Delay:
3241 12:46:16.347620 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3242 12:46:16.350701 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3243 12:46:16.354299 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3244 12:46:16.357547 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3245 12:46:16.357628
3246 12:46:16.357691
3247 12:46:16.357750 ==
3248 12:46:16.360299 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 12:46:16.363808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 12:46:16.363889 ==
3251 12:46:16.363952
3252 12:46:16.364010
3253 12:46:16.367163 TX Vref Scan disable
3254 12:46:16.370604 == TX Byte 0 ==
3255 12:46:16.374005 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3256 12:46:16.377218 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3257 12:46:16.380703 == TX Byte 1 ==
3258 12:46:16.383471 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3259 12:46:16.387086 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3260 12:46:16.387167 ==
3261 12:46:16.391422 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 12:46:16.393895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 12:46:16.396915 ==
3264 12:46:16.407153 TX Vref=22, minBit 3, minWin=24, winSum=408
3265 12:46:16.410394 TX Vref=24, minBit 9, minWin=24, winSum=411
3266 12:46:16.413794 TX Vref=26, minBit 3, minWin=25, winSum=419
3267 12:46:16.417213 TX Vref=28, minBit 9, minWin=24, winSum=422
3268 12:46:16.420328 TX Vref=30, minBit 9, minWin=25, winSum=428
3269 12:46:16.426767 TX Vref=32, minBit 9, minWin=25, winSum=426
3270 12:46:16.430429 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 30
3271 12:46:16.430505
3272 12:46:16.433344 Final TX Range 1 Vref 30
3273 12:46:16.433414
3274 12:46:16.433483 ==
3275 12:46:16.436881 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 12:46:16.440268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 12:46:16.443530 ==
3278 12:46:16.443627
3279 12:46:16.443715
3280 12:46:16.443801 TX Vref Scan disable
3281 12:46:16.447000 == TX Byte 0 ==
3282 12:46:16.450154 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3283 12:46:16.456939 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3284 12:46:16.457014 == TX Byte 1 ==
3285 12:46:16.460038 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3286 12:46:16.466661 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3287 12:46:16.466763
3288 12:46:16.466854 [DATLAT]
3289 12:46:16.466941 Freq=1200, CH1 RK0
3290 12:46:16.467027
3291 12:46:16.469800 DATLAT Default: 0xd
3292 12:46:16.469894 0, 0xFFFF, sum = 0
3293 12:46:16.473425 1, 0xFFFF, sum = 0
3294 12:46:16.476703 2, 0xFFFF, sum = 0
3295 12:46:16.476777 3, 0xFFFF, sum = 0
3296 12:46:16.479978 4, 0xFFFF, sum = 0
3297 12:46:16.480075 5, 0xFFFF, sum = 0
3298 12:46:16.483345 6, 0xFFFF, sum = 0
3299 12:46:16.483417 7, 0xFFFF, sum = 0
3300 12:46:16.486953 8, 0xFFFF, sum = 0
3301 12:46:16.487031 9, 0xFFFF, sum = 0
3302 12:46:16.490369 10, 0xFFFF, sum = 0
3303 12:46:16.490467 11, 0xFFFF, sum = 0
3304 12:46:16.493447 12, 0x0, sum = 1
3305 12:46:16.493547 13, 0x0, sum = 2
3306 12:46:16.496797 14, 0x0, sum = 3
3307 12:46:16.496868 15, 0x0, sum = 4
3308 12:46:16.496940 best_step = 13
3309 12:46:16.500574
3310 12:46:16.500668 ==
3311 12:46:16.503289 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 12:46:16.506951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 12:46:16.507047 ==
3314 12:46:16.507138 RX Vref Scan: 1
3315 12:46:16.507226
3316 12:46:16.510484 Set Vref Range= 32 -> 127
3317 12:46:16.510578
3318 12:46:16.513640 RX Vref 32 -> 127, step: 1
3319 12:46:16.513734
3320 12:46:16.517228 RX Delay -13 -> 252, step: 4
3321 12:46:16.517303
3322 12:46:16.519903 Set Vref, RX VrefLevel [Byte0]: 32
3323 12:46:16.523165 [Byte1]: 32
3324 12:46:16.523236
3325 12:46:16.526294 Set Vref, RX VrefLevel [Byte0]: 33
3326 12:46:16.529984 [Byte1]: 33
3327 12:46:16.533560
3328 12:46:16.533656 Set Vref, RX VrefLevel [Byte0]: 34
3329 12:46:16.536280 [Byte1]: 34
3330 12:46:16.541462
3331 12:46:16.541534 Set Vref, RX VrefLevel [Byte0]: 35
3332 12:46:16.544479 [Byte1]: 35
3333 12:46:16.548868
3334 12:46:16.548942 Set Vref, RX VrefLevel [Byte0]: 36
3335 12:46:16.552761 [Byte1]: 36
3336 12:46:16.557052
3337 12:46:16.557148 Set Vref, RX VrefLevel [Byte0]: 37
3338 12:46:16.560474 [Byte1]: 37
3339 12:46:16.564629
3340 12:46:16.564702 Set Vref, RX VrefLevel [Byte0]: 38
3341 12:46:16.568254 [Byte1]: 38
3342 12:46:16.572384
3343 12:46:16.572471 Set Vref, RX VrefLevel [Byte0]: 39
3344 12:46:16.575847 [Byte1]: 39
3345 12:46:16.580862
3346 12:46:16.580934 Set Vref, RX VrefLevel [Byte0]: 40
3347 12:46:16.583914 [Byte1]: 40
3348 12:46:16.588441
3349 12:46:16.588515 Set Vref, RX VrefLevel [Byte0]: 41
3350 12:46:16.591602 [Byte1]: 41
3351 12:46:16.596672
3352 12:46:16.596745 Set Vref, RX VrefLevel [Byte0]: 42
3353 12:46:16.599769 [Byte1]: 42
3354 12:46:16.604346
3355 12:46:16.604415 Set Vref, RX VrefLevel [Byte0]: 43
3356 12:46:16.607498 [Byte1]: 43
3357 12:46:16.612252
3358 12:46:16.612347 Set Vref, RX VrefLevel [Byte0]: 44
3359 12:46:16.615866 [Byte1]: 44
3360 12:46:16.619927
3361 12:46:16.620022 Set Vref, RX VrefLevel [Byte0]: 45
3362 12:46:16.623052 [Byte1]: 45
3363 12:46:16.627641
3364 12:46:16.627708 Set Vref, RX VrefLevel [Byte0]: 46
3365 12:46:16.631284 [Byte1]: 46
3366 12:46:16.635965
3367 12:46:16.636098 Set Vref, RX VrefLevel [Byte0]: 47
3368 12:46:16.639320 [Byte1]: 47
3369 12:46:16.644633
3370 12:46:16.644701 Set Vref, RX VrefLevel [Byte0]: 48
3371 12:46:16.646957 [Byte1]: 48
3372 12:46:16.651293
3373 12:46:16.651360 Set Vref, RX VrefLevel [Byte0]: 49
3374 12:46:16.655015 [Byte1]: 49
3375 12:46:16.659527
3376 12:46:16.659619 Set Vref, RX VrefLevel [Byte0]: 50
3377 12:46:16.662865 [Byte1]: 50
3378 12:46:16.667272
3379 12:46:16.667365 Set Vref, RX VrefLevel [Byte0]: 51
3380 12:46:16.670489 [Byte1]: 51
3381 12:46:16.675034
3382 12:46:16.675129 Set Vref, RX VrefLevel [Byte0]: 52
3383 12:46:16.678340 [Byte1]: 52
3384 12:46:16.683079
3385 12:46:16.683152 Set Vref, RX VrefLevel [Byte0]: 53
3386 12:46:16.686251 [Byte1]: 53
3387 12:46:16.691685
3388 12:46:16.691777 Set Vref, RX VrefLevel [Byte0]: 54
3389 12:46:16.694286 [Byte1]: 54
3390 12:46:16.698680
3391 12:46:16.698745 Set Vref, RX VrefLevel [Byte0]: 55
3392 12:46:16.701903 [Byte1]: 55
3393 12:46:16.706661
3394 12:46:16.706732 Set Vref, RX VrefLevel [Byte0]: 56
3395 12:46:16.710067 [Byte1]: 56
3396 12:46:16.714503
3397 12:46:16.714571 Set Vref, RX VrefLevel [Byte0]: 57
3398 12:46:16.718086 [Byte1]: 57
3399 12:46:16.722594
3400 12:46:16.722688 Set Vref, RX VrefLevel [Byte0]: 58
3401 12:46:16.726082 [Byte1]: 58
3402 12:46:16.730380
3403 12:46:16.730448 Set Vref, RX VrefLevel [Byte0]: 59
3404 12:46:16.733980 [Byte1]: 59
3405 12:46:16.738403
3406 12:46:16.738497 Set Vref, RX VrefLevel [Byte0]: 60
3407 12:46:16.741190 [Byte1]: 60
3408 12:46:16.746167
3409 12:46:16.746236 Set Vref, RX VrefLevel [Byte0]: 61
3410 12:46:16.749441 [Byte1]: 61
3411 12:46:16.754273
3412 12:46:16.754341 Set Vref, RX VrefLevel [Byte0]: 62
3413 12:46:16.757161 [Byte1]: 62
3414 12:46:16.762058
3415 12:46:16.762124 Set Vref, RX VrefLevel [Byte0]: 63
3416 12:46:16.764904 [Byte1]: 63
3417 12:46:16.769933
3418 12:46:16.770029 Set Vref, RX VrefLevel [Byte0]: 64
3419 12:46:16.773011 [Byte1]: 64
3420 12:46:16.777701
3421 12:46:16.777798 Final RX Vref Byte 0 = 52 to rank0
3422 12:46:16.780951 Final RX Vref Byte 1 = 48 to rank0
3423 12:46:16.784306 Final RX Vref Byte 0 = 52 to rank1
3424 12:46:16.787482 Final RX Vref Byte 1 = 48 to rank1==
3425 12:46:16.790806 Dram Type= 6, Freq= 0, CH_1, rank 0
3426 12:46:16.797608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 12:46:16.797680 ==
3428 12:46:16.797742 DQS Delay:
3429 12:46:16.797804 DQS0 = 0, DQS1 = 0
3430 12:46:16.800877 DQM Delay:
3431 12:46:16.800971 DQM0 = 115, DQM1 = 112
3432 12:46:16.804285 DQ Delay:
3433 12:46:16.807237 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3434 12:46:16.810704 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3435 12:46:16.814318 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
3436 12:46:16.817534 DQ12 =120, DQ13 =120, DQ14 =116, DQ15 =120
3437 12:46:16.817634
3438 12:46:16.817724
3439 12:46:16.827778 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3440 12:46:16.827876 CH1 RK0: MR19=303, MR18=F3FF
3441 12:46:16.833792 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3442 12:46:16.833863
3443 12:46:16.837033 ----->DramcWriteLeveling(PI) begin...
3444 12:46:16.837131 ==
3445 12:46:16.840744 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 12:46:16.846932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 12:46:16.847029 ==
3448 12:46:16.850872 Write leveling (Byte 0): 26 => 26
3449 12:46:16.853560 Write leveling (Byte 1): 29 => 29
3450 12:46:16.853628 DramcWriteLeveling(PI) end<-----
3451 12:46:16.853687
3452 12:46:16.856939 ==
3453 12:46:16.860365 Dram Type= 6, Freq= 0, CH_1, rank 1
3454 12:46:16.863622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 12:46:16.863689 ==
3456 12:46:16.866846 [Gating] SW mode calibration
3457 12:46:16.873645 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3458 12:46:16.876841 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3459 12:46:16.883249 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3460 12:46:16.886528 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 12:46:16.890574 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 12:46:16.897161 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 12:46:16.900136 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 12:46:16.903181 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 12:46:16.909901 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
3466 12:46:16.913283 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
3467 12:46:16.916359 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 12:46:16.923627 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 12:46:16.926467 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 12:46:16.929720 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 12:46:16.937003 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 12:46:16.940372 1 0 20 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
3473 12:46:16.943206 1 0 24 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
3474 12:46:16.950253 1 0 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3475 12:46:16.953267 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 12:46:16.956390 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 12:46:16.963036 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 12:46:16.966199 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 12:46:16.969927 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 12:46:16.976172 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3481 12:46:16.979833 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3482 12:46:16.983521 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3483 12:46:16.989287 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:46:16.992795 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:46:16.995762 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:46:17.002365 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:46:17.005503 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:46:17.009229 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:46:17.015841 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:46:17.019028 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:46:17.022098 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:46:17.028712 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:46:17.032297 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:46:17.035577 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:46:17.041924 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:46:17.045724 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3497 12:46:17.048552 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3498 12:46:17.055186 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3499 12:46:17.055287 Total UI for P1: 0, mck2ui 16
3500 12:46:17.062446 best dqsien dly found for B0: ( 1, 3, 22)
3501 12:46:17.065420 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 12:46:17.068388 Total UI for P1: 0, mck2ui 16
3503 12:46:17.071773 best dqsien dly found for B1: ( 1, 3, 28)
3504 12:46:17.074898 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3505 12:46:17.078809 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3506 12:46:17.078891
3507 12:46:17.081588 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3508 12:46:17.085108 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3509 12:46:17.088286 [Gating] SW calibration Done
3510 12:46:17.088368 ==
3511 12:46:17.091594 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 12:46:17.095148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 12:46:17.097917 ==
3514 12:46:17.097999 RX Vref Scan: 0
3515 12:46:17.098081
3516 12:46:17.101414 RX Vref 0 -> 0, step: 1
3517 12:46:17.101496
3518 12:46:17.104627 RX Delay -40 -> 252, step: 8
3519 12:46:17.107554 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3520 12:46:17.111215 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3521 12:46:17.114369 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3522 12:46:17.117748 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3523 12:46:17.124370 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3524 12:46:17.128128 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3525 12:46:17.130683 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3526 12:46:17.133973 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3527 12:46:17.137618 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3528 12:46:17.144929 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3529 12:46:17.147124 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3530 12:46:17.150464 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3531 12:46:17.153762 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3532 12:46:17.160282 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3533 12:46:17.163706 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3534 12:46:17.167228 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3535 12:46:17.167311 ==
3536 12:46:17.170374 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 12:46:17.173714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 12:46:17.173802 ==
3539 12:46:17.177180 DQS Delay:
3540 12:46:17.177262 DQS0 = 0, DQS1 = 0
3541 12:46:17.180585 DQM Delay:
3542 12:46:17.180667 DQM0 = 114, DQM1 = 111
3543 12:46:17.183379 DQ Delay:
3544 12:46:17.186655 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3545 12:46:17.189850 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3546 12:46:17.193735 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3547 12:46:17.196319 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3548 12:46:17.196400
3549 12:46:17.196464
3550 12:46:17.196523 ==
3551 12:46:17.199697 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 12:46:17.202913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 12:46:17.202995 ==
3554 12:46:17.203060
3555 12:46:17.203120
3556 12:46:17.206151 TX Vref Scan disable
3557 12:46:17.209837 == TX Byte 0 ==
3558 12:46:17.213018 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3559 12:46:17.216279 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3560 12:46:17.219470 == TX Byte 1 ==
3561 12:46:17.223230 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3562 12:46:17.226486 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3563 12:46:17.226569 ==
3564 12:46:17.229664 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 12:46:17.235996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 12:46:17.236124 ==
3567 12:46:17.246549 TX Vref=22, minBit 7, minWin=25, winSum=422
3568 12:46:17.249891 TX Vref=24, minBit 3, minWin=25, winSum=424
3569 12:46:17.253388 TX Vref=26, minBit 9, minWin=25, winSum=426
3570 12:46:17.256485 TX Vref=28, minBit 1, minWin=26, winSum=431
3571 12:46:17.259900 TX Vref=30, minBit 9, minWin=26, winSum=433
3572 12:46:17.266350 TX Vref=32, minBit 9, minWin=26, winSum=432
3573 12:46:17.270068 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3574 12:46:17.270151
3575 12:46:17.272751 Final TX Range 1 Vref 30
3576 12:46:17.272832
3577 12:46:17.272897 ==
3578 12:46:17.275965 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 12:46:17.279501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 12:46:17.283059 ==
3581 12:46:17.283142
3582 12:46:17.283207
3583 12:46:17.283268 TX Vref Scan disable
3584 12:46:17.286264 == TX Byte 0 ==
3585 12:46:17.289830 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3586 12:46:17.296743 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3587 12:46:17.296825 == TX Byte 1 ==
3588 12:46:17.299353 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3589 12:46:17.306264 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3590 12:46:17.306346
3591 12:46:17.306440 [DATLAT]
3592 12:46:17.306499 Freq=1200, CH1 RK1
3593 12:46:17.306558
3594 12:46:17.309530 DATLAT Default: 0xd
3595 12:46:17.312834 0, 0xFFFF, sum = 0
3596 12:46:17.312918 1, 0xFFFF, sum = 0
3597 12:46:17.316002 2, 0xFFFF, sum = 0
3598 12:46:17.316139 3, 0xFFFF, sum = 0
3599 12:46:17.319223 4, 0xFFFF, sum = 0
3600 12:46:17.319307 5, 0xFFFF, sum = 0
3601 12:46:17.322478 6, 0xFFFF, sum = 0
3602 12:46:17.322561 7, 0xFFFF, sum = 0
3603 12:46:17.326115 8, 0xFFFF, sum = 0
3604 12:46:17.326198 9, 0xFFFF, sum = 0
3605 12:46:17.329238 10, 0xFFFF, sum = 0
3606 12:46:17.329321 11, 0xFFFF, sum = 0
3607 12:46:17.332334 12, 0x0, sum = 1
3608 12:46:17.332417 13, 0x0, sum = 2
3609 12:46:17.336130 14, 0x0, sum = 3
3610 12:46:17.336240 15, 0x0, sum = 4
3611 12:46:17.339593 best_step = 13
3612 12:46:17.339675
3613 12:46:17.339739 ==
3614 12:46:17.342499 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 12:46:17.346004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 12:46:17.346086 ==
3617 12:46:17.349278 RX Vref Scan: 0
3618 12:46:17.349360
3619 12:46:17.349425 RX Vref 0 -> 0, step: 1
3620 12:46:17.349486
3621 12:46:17.353571 RX Delay -13 -> 252, step: 4
3622 12:46:17.358784 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3623 12:46:17.361998 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3624 12:46:17.365512 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3625 12:46:17.368522 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3626 12:46:17.371734 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3627 12:46:17.378623 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3628 12:46:17.381883 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3629 12:46:17.385096 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3630 12:46:17.388970 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3631 12:46:17.391691 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3632 12:46:17.398304 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3633 12:46:17.401941 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3634 12:46:17.404902 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3635 12:46:17.408438 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3636 12:46:17.415412 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3637 12:46:17.418833 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3638 12:46:17.418915 ==
3639 12:46:17.421470 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 12:46:17.425034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 12:46:17.425116 ==
3642 12:46:17.427899 DQS Delay:
3643 12:46:17.428008 DQS0 = 0, DQS1 = 0
3644 12:46:17.428130 DQM Delay:
3645 12:46:17.431622 DQM0 = 114, DQM1 = 111
3646 12:46:17.431705 DQ Delay:
3647 12:46:17.434776 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3648 12:46:17.437779 DQ4 =112, DQ5 =124, DQ6 =120, DQ7 =112
3649 12:46:17.441040 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3650 12:46:17.447973 DQ12 =120, DQ13 =116, DQ14 =118, DQ15 =122
3651 12:46:17.448118
3652 12:46:17.448256
3653 12:46:17.454330 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3654 12:46:17.457682 CH1 RK1: MR19=304, MR18=F709
3655 12:46:17.463968 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3656 12:46:17.467263 [RxdqsGatingPostProcess] freq 1200
3657 12:46:17.470373 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3658 12:46:17.473912 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 12:46:17.477155 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 12:46:17.480624 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 12:46:17.484107 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 12:46:17.487217 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 12:46:17.490448 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 12:46:17.494170 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 12:46:17.496932 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 12:46:17.500306 Pre-setting of DQS Precalculation
3667 12:46:17.507429 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3668 12:46:17.513507 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3669 12:46:17.520302 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3670 12:46:17.520386
3671 12:46:17.520463
3672 12:46:17.523511 [Calibration Summary] 2400 Mbps
3673 12:46:17.523618 CH 0, Rank 0
3674 12:46:17.526464 SW Impedance : PASS
3675 12:46:17.530558 DUTY Scan : NO K
3676 12:46:17.530653 ZQ Calibration : PASS
3677 12:46:17.533988 Jitter Meter : NO K
3678 12:46:17.536633 CBT Training : PASS
3679 12:46:17.536725 Write leveling : PASS
3680 12:46:17.539625 RX DQS gating : PASS
3681 12:46:17.539705 RX DQ/DQS(RDDQC) : PASS
3682 12:46:17.543467 TX DQ/DQS : PASS
3683 12:46:17.546571 RX DATLAT : PASS
3684 12:46:17.546652 RX DQ/DQS(Engine): PASS
3685 12:46:17.549547 TX OE : NO K
3686 12:46:17.549629 All Pass.
3687 12:46:17.549693
3688 12:46:17.552962 CH 0, Rank 1
3689 12:46:17.553042 SW Impedance : PASS
3690 12:46:17.556257 DUTY Scan : NO K
3691 12:46:17.559418 ZQ Calibration : PASS
3692 12:46:17.559500 Jitter Meter : NO K
3693 12:46:17.563300 CBT Training : PASS
3694 12:46:17.565973 Write leveling : PASS
3695 12:46:17.566046 RX DQS gating : PASS
3696 12:46:17.569521 RX DQ/DQS(RDDQC) : PASS
3697 12:46:17.572612 TX DQ/DQS : PASS
3698 12:46:17.572691 RX DATLAT : PASS
3699 12:46:17.576025 RX DQ/DQS(Engine): PASS
3700 12:46:17.579417 TX OE : NO K
3701 12:46:17.579495 All Pass.
3702 12:46:17.579560
3703 12:46:17.579620 CH 1, Rank 0
3704 12:46:17.582718 SW Impedance : PASS
3705 12:46:17.585870 DUTY Scan : NO K
3706 12:46:17.585945 ZQ Calibration : PASS
3707 12:46:17.590000 Jitter Meter : NO K
3708 12:46:17.592803 CBT Training : PASS
3709 12:46:17.592877 Write leveling : PASS
3710 12:46:17.596143 RX DQS gating : PASS
3711 12:46:17.599187 RX DQ/DQS(RDDQC) : PASS
3712 12:46:17.599263 TX DQ/DQS : PASS
3713 12:46:17.602179 RX DATLAT : PASS
3714 12:46:17.605848 RX DQ/DQS(Engine): PASS
3715 12:46:17.605920 TX OE : NO K
3716 12:46:17.609115 All Pass.
3717 12:46:17.609189
3718 12:46:17.609255 CH 1, Rank 1
3719 12:46:17.611923 SW Impedance : PASS
3720 12:46:17.611999 DUTY Scan : NO K
3721 12:46:17.615568 ZQ Calibration : PASS
3722 12:46:17.618692 Jitter Meter : NO K
3723 12:46:17.618769 CBT Training : PASS
3724 12:46:17.621936 Write leveling : PASS
3725 12:46:17.625544 RX DQS gating : PASS
3726 12:46:17.625658 RX DQ/DQS(RDDQC) : PASS
3727 12:46:17.628528 TX DQ/DQS : PASS
3728 12:46:17.632016 RX DATLAT : PASS
3729 12:46:17.632133 RX DQ/DQS(Engine): PASS
3730 12:46:17.635479 TX OE : NO K
3731 12:46:17.635564 All Pass.
3732 12:46:17.635648
3733 12:46:17.638384 DramC Write-DBI off
3734 12:46:17.641507 PER_BANK_REFRESH: Hybrid Mode
3735 12:46:17.641591 TX_TRACKING: ON
3736 12:46:17.651461 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3737 12:46:17.654963 [FAST_K] Save calibration result to emmc
3738 12:46:17.658511 dramc_set_vcore_voltage set vcore to 650000
3739 12:46:17.661448 Read voltage for 600, 5
3740 12:46:17.661532 Vio18 = 0
3741 12:46:17.661617 Vcore = 650000
3742 12:46:17.665431 Vdram = 0
3743 12:46:17.665515 Vddq = 0
3744 12:46:17.665605 Vmddr = 0
3745 12:46:17.671407 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3746 12:46:17.674820 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3747 12:46:17.678052 MEM_TYPE=3, freq_sel=19
3748 12:46:17.681044 sv_algorithm_assistance_LP4_1600
3749 12:46:17.684798 ============ PULL DRAM RESETB DOWN ============
3750 12:46:17.687964 ========== PULL DRAM RESETB DOWN end =========
3751 12:46:17.694721 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 12:46:17.697688 ===================================
3753 12:46:17.701078 LPDDR4 DRAM CONFIGURATION
3754 12:46:17.704199 ===================================
3755 12:46:17.704280 EX_ROW_EN[0] = 0x0
3756 12:46:17.708156 EX_ROW_EN[1] = 0x0
3757 12:46:17.708236 LP4Y_EN = 0x0
3758 12:46:17.710777 WORK_FSP = 0x0
3759 12:46:17.710858 WL = 0x2
3760 12:46:17.713876 RL = 0x2
3761 12:46:17.713956 BL = 0x2
3762 12:46:17.717306 RPST = 0x0
3763 12:46:17.717387 RD_PRE = 0x0
3764 12:46:17.721105 WR_PRE = 0x1
3765 12:46:17.721211 WR_PST = 0x0
3766 12:46:17.724411 DBI_WR = 0x0
3767 12:46:17.727746 DBI_RD = 0x0
3768 12:46:17.727826 OTF = 0x1
3769 12:46:17.730448 ===================================
3770 12:46:17.733590 ===================================
3771 12:46:17.733671 ANA top config
3772 12:46:17.737140 ===================================
3773 12:46:17.740824 DLL_ASYNC_EN = 0
3774 12:46:17.743916 ALL_SLAVE_EN = 1
3775 12:46:17.747049 NEW_RANK_MODE = 1
3776 12:46:17.750162 DLL_IDLE_MODE = 1
3777 12:46:17.750267 LP45_APHY_COMB_EN = 1
3778 12:46:17.753347 TX_ODT_DIS = 1
3779 12:46:17.756605 NEW_8X_MODE = 1
3780 12:46:17.760330 ===================================
3781 12:46:17.763599 ===================================
3782 12:46:17.766790 data_rate = 1200
3783 12:46:17.770269 CKR = 1
3784 12:46:17.773308 DQ_P2S_RATIO = 8
3785 12:46:17.776508 ===================================
3786 12:46:17.776612 CA_P2S_RATIO = 8
3787 12:46:17.779997 DQ_CA_OPEN = 0
3788 12:46:17.783552 DQ_SEMI_OPEN = 0
3789 12:46:17.786496 CA_SEMI_OPEN = 0
3790 12:46:17.789551 CA_FULL_RATE = 0
3791 12:46:17.793175 DQ_CKDIV4_EN = 1
3792 12:46:17.793272 CA_CKDIV4_EN = 1
3793 12:46:17.796110 CA_PREDIV_EN = 0
3794 12:46:17.799282 PH8_DLY = 0
3795 12:46:17.802964 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3796 12:46:17.806333 DQ_AAMCK_DIV = 4
3797 12:46:17.809558 CA_AAMCK_DIV = 4
3798 12:46:17.809630 CA_ADMCK_DIV = 4
3799 12:46:17.812902 DQ_TRACK_CA_EN = 0
3800 12:46:17.815939 CA_PICK = 600
3801 12:46:17.819387 CA_MCKIO = 600
3802 12:46:17.822273 MCKIO_SEMI = 0
3803 12:46:17.826444 PLL_FREQ = 2288
3804 12:46:17.829401 DQ_UI_PI_RATIO = 32
3805 12:46:17.832529 CA_UI_PI_RATIO = 0
3806 12:46:17.835832 ===================================
3807 12:46:17.838758 ===================================
3808 12:46:17.838835 memory_type:LPDDR4
3809 12:46:17.842064 GP_NUM : 10
3810 12:46:17.845691 SRAM_EN : 1
3811 12:46:17.845790 MD32_EN : 0
3812 12:46:17.849355 ===================================
3813 12:46:17.852358 [ANA_INIT] >>>>>>>>>>>>>>
3814 12:46:17.855162 <<<<<< [CONFIGURE PHASE]: ANA_TX
3815 12:46:17.858977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3816 12:46:17.862182 ===================================
3817 12:46:17.865237 data_rate = 1200,PCW = 0X5800
3818 12:46:17.868742 ===================================
3819 12:46:17.871853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3820 12:46:17.875415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 12:46:17.882449 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 12:46:17.885372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3823 12:46:17.889513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3824 12:46:17.891749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3825 12:46:17.895010 [ANA_INIT] flow start
3826 12:46:17.899037 [ANA_INIT] PLL >>>>>>>>
3827 12:46:17.899117 [ANA_INIT] PLL <<<<<<<<
3828 12:46:17.901846 [ANA_INIT] MIDPI >>>>>>>>
3829 12:46:17.905030 [ANA_INIT] MIDPI <<<<<<<<
3830 12:46:17.908357 [ANA_INIT] DLL >>>>>>>>
3831 12:46:17.908438 [ANA_INIT] flow end
3832 12:46:17.911857 ============ LP4 DIFF to SE enter ============
3833 12:46:17.918295 ============ LP4 DIFF to SE exit ============
3834 12:46:17.918377 [ANA_INIT] <<<<<<<<<<<<<
3835 12:46:17.921363 [Flow] Enable top DCM control >>>>>
3836 12:46:17.925075 [Flow] Enable top DCM control <<<<<
3837 12:46:17.927977 Enable DLL master slave shuffle
3838 12:46:17.934535 ==============================================================
3839 12:46:17.934617 Gating Mode config
3840 12:46:17.941364 ==============================================================
3841 12:46:17.944425 Config description:
3842 12:46:17.954448 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3843 12:46:17.960738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3844 12:46:17.963970 SELPH_MODE 0: By rank 1: By Phase
3845 12:46:17.971018 ==============================================================
3846 12:46:17.974078 GAT_TRACK_EN = 1
3847 12:46:17.977626 RX_GATING_MODE = 2
3848 12:46:17.980718 RX_GATING_TRACK_MODE = 2
3849 12:46:17.980792 SELPH_MODE = 1
3850 12:46:17.983991 PICG_EARLY_EN = 1
3851 12:46:17.987276 VALID_LAT_VALUE = 1
3852 12:46:17.994120 ==============================================================
3853 12:46:17.997056 Enter into Gating configuration >>>>
3854 12:46:18.000004 Exit from Gating configuration <<<<
3855 12:46:18.003912 Enter into DVFS_PRE_config >>>>>
3856 12:46:18.013297 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3857 12:46:18.017356 Exit from DVFS_PRE_config <<<<<
3858 12:46:18.019994 Enter into PICG configuration >>>>
3859 12:46:18.023184 Exit from PICG configuration <<<<
3860 12:46:18.026343 [RX_INPUT] configuration >>>>>
3861 12:46:18.029679 [RX_INPUT] configuration <<<<<
3862 12:46:18.036694 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3863 12:46:18.039885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3864 12:46:18.046456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 12:46:18.053047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 12:46:18.059405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 12:46:18.066186 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 12:46:18.069592 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3869 12:46:18.072559 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3870 12:46:18.075630 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3871 12:46:18.082211 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3872 12:46:18.085488 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3873 12:46:18.088898 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 12:46:18.092309 ===================================
3875 12:46:18.095692 LPDDR4 DRAM CONFIGURATION
3876 12:46:18.099215 ===================================
3877 12:46:18.102917 EX_ROW_EN[0] = 0x0
3878 12:46:18.102998 EX_ROW_EN[1] = 0x0
3879 12:46:18.105312 LP4Y_EN = 0x0
3880 12:46:18.105393 WORK_FSP = 0x0
3881 12:46:18.108940 WL = 0x2
3882 12:46:18.109020 RL = 0x2
3883 12:46:18.112171 BL = 0x2
3884 12:46:18.112251 RPST = 0x0
3885 12:46:18.115289 RD_PRE = 0x0
3886 12:46:18.115370 WR_PRE = 0x1
3887 12:46:18.118929 WR_PST = 0x0
3888 12:46:18.119010 DBI_WR = 0x0
3889 12:46:18.122194 DBI_RD = 0x0
3890 12:46:18.122275 OTF = 0x1
3891 12:46:18.125619 ===================================
3892 12:46:18.131698 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3893 12:46:18.135080 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3894 12:46:18.138460 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 12:46:18.141691 ===================================
3896 12:46:18.144798 LPDDR4 DRAM CONFIGURATION
3897 12:46:18.147931 ===================================
3898 12:46:18.151391 EX_ROW_EN[0] = 0x10
3899 12:46:18.151472 EX_ROW_EN[1] = 0x0
3900 12:46:18.154608 LP4Y_EN = 0x0
3901 12:46:18.154689 WORK_FSP = 0x0
3902 12:46:18.157608 WL = 0x2
3903 12:46:18.157690 RL = 0x2
3904 12:46:18.161521 BL = 0x2
3905 12:46:18.161602 RPST = 0x0
3906 12:46:18.164827 RD_PRE = 0x0
3907 12:46:18.164908 WR_PRE = 0x1
3908 12:46:18.167732 WR_PST = 0x0
3909 12:46:18.171128 DBI_WR = 0x0
3910 12:46:18.171209 DBI_RD = 0x0
3911 12:46:18.174498 OTF = 0x1
3912 12:46:18.177646 ===================================
3913 12:46:18.180926 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3914 12:46:18.186065 nWR fixed to 30
3915 12:46:18.189557 [ModeRegInit_LP4] CH0 RK0
3916 12:46:18.189637 [ModeRegInit_LP4] CH0 RK1
3917 12:46:18.192850 [ModeRegInit_LP4] CH1 RK0
3918 12:46:18.196527 [ModeRegInit_LP4] CH1 RK1
3919 12:46:18.196607 match AC timing 17
3920 12:46:18.202970 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3921 12:46:18.205818 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3922 12:46:18.210122 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3923 12:46:18.215772 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3924 12:46:18.218904 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3925 12:46:18.218985 ==
3926 12:46:18.222136 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 12:46:18.225469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 12:46:18.225549 ==
3929 12:46:18.232410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 12:46:18.239036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3931 12:46:18.242294 [CA 0] Center 36 (6~67) winsize 62
3932 12:46:18.245470 [CA 1] Center 36 (6~66) winsize 61
3933 12:46:18.249023 [CA 2] Center 34 (4~65) winsize 62
3934 12:46:18.252076 [CA 3] Center 34 (4~65) winsize 62
3935 12:46:18.255218 [CA 4] Center 33 (3~64) winsize 62
3936 12:46:18.259114 [CA 5] Center 33 (3~64) winsize 62
3937 12:46:18.259194
3938 12:46:18.262052 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3939 12:46:18.262132
3940 12:46:18.264921 [CATrainingPosCal] consider 1 rank data
3941 12:46:18.268528 u2DelayCellTimex100 = 270/100 ps
3942 12:46:18.272404 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3943 12:46:18.274910 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3944 12:46:18.278775 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3945 12:46:18.285015 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 12:46:18.288457 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3947 12:46:18.291542 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 12:46:18.291622
3949 12:46:18.294554 CA PerBit enable=1, Macro0, CA PI delay=33
3950 12:46:18.294637
3951 12:46:18.298010 [CBTSetCACLKResult] CA Dly = 33
3952 12:46:18.298091 CS Dly: 5 (0~36)
3953 12:46:18.298155 ==
3954 12:46:18.301384 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 12:46:18.308514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 12:46:18.308596 ==
3957 12:46:18.311759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 12:46:18.318100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3959 12:46:18.321504 [CA 0] Center 36 (6~67) winsize 62
3960 12:46:18.324682 [CA 1] Center 36 (6~67) winsize 62
3961 12:46:18.328249 [CA 2] Center 34 (4~65) winsize 62
3962 12:46:18.331416 [CA 3] Center 34 (4~65) winsize 62
3963 12:46:18.334937 [CA 4] Center 33 (3~64) winsize 62
3964 12:46:18.337910 [CA 5] Center 33 (3~64) winsize 62
3965 12:46:18.337991
3966 12:46:18.341162 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3967 12:46:18.341243
3968 12:46:18.344299 [CATrainingPosCal] consider 2 rank data
3969 12:46:18.348147 u2DelayCellTimex100 = 270/100 ps
3970 12:46:18.354519 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3971 12:46:18.357493 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3972 12:46:18.360851 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3973 12:46:18.364224 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3974 12:46:18.367334 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 12:46:18.370670 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3976 12:46:18.370751
3977 12:46:18.373852 CA PerBit enable=1, Macro0, CA PI delay=33
3978 12:46:18.373932
3979 12:46:18.376974 [CBTSetCACLKResult] CA Dly = 33
3980 12:46:18.380366 CS Dly: 6 (0~38)
3981 12:46:18.380446
3982 12:46:18.383961 ----->DramcWriteLeveling(PI) begin...
3983 12:46:18.384050 ==
3984 12:46:18.387132 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 12:46:18.390215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 12:46:18.390296 ==
3987 12:46:18.393606 Write leveling (Byte 0): 34 => 34
3988 12:46:18.396890 Write leveling (Byte 1): 28 => 28
3989 12:46:18.400255 DramcWriteLeveling(PI) end<-----
3990 12:46:18.400335
3991 12:46:18.400400 ==
3992 12:46:18.403593 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 12:46:18.406606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 12:46:18.406688 ==
3995 12:46:18.409708 [Gating] SW mode calibration
3996 12:46:18.416346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3997 12:46:18.423086 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3998 12:46:18.426163 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 12:46:18.433004 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 12:46:18.436363 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 12:46:18.439440 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4002 12:46:18.446350 0 9 16 | B1->B0 | 2d2d 2828 | 1 0 | (1 0) (0 0)
4003 12:46:18.449156 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 12:46:18.452457 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 12:46:18.459327 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 12:46:18.462480 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 12:46:18.465812 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 12:46:18.473009 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 12:46:18.475553 0 10 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 1)
4010 12:46:18.479441 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4011 12:46:18.485666 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 12:46:18.489061 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 12:46:18.492061 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 12:46:18.498680 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 12:46:18.502235 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 12:46:18.505253 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4017 12:46:18.511827 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 12:46:18.515001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4019 12:46:18.517962 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:46:18.524849 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:46:18.528251 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:46:18.531383 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:46:18.538276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:46:18.541232 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:46:18.544589 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:46:18.551508 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:46:18.554438 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:46:18.557934 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:46:18.564315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:46:18.568008 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:46:18.570711 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:46:18.578147 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:46:18.580611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4034 12:46:18.584353 Total UI for P1: 0, mck2ui 16
4035 12:46:18.587559 best dqsien dly found for B0: ( 0, 13, 10)
4036 12:46:18.590834 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4037 12:46:18.597913 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 12:46:18.597994 Total UI for P1: 0, mck2ui 16
4039 12:46:18.604235 best dqsien dly found for B1: ( 0, 13, 18)
4040 12:46:18.607464 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4041 12:46:18.610774 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4042 12:46:18.610855
4043 12:46:18.614097 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4044 12:46:18.617350 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4045 12:46:18.620526 [Gating] SW calibration Done
4046 12:46:18.620608 ==
4047 12:46:18.623738 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 12:46:18.627342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 12:46:18.627424 ==
4050 12:46:18.630456 RX Vref Scan: 0
4051 12:46:18.630537
4052 12:46:18.633706 RX Vref 0 -> 0, step: 1
4053 12:46:18.633787
4054 12:46:18.633852 RX Delay -230 -> 252, step: 16
4055 12:46:18.640004 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4056 12:46:18.643432 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4057 12:46:18.646597 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4058 12:46:18.649895 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4059 12:46:18.656600 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4060 12:46:18.660177 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4061 12:46:18.663354 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4062 12:46:18.666530 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4063 12:46:18.672855 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4064 12:46:18.676076 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4065 12:46:18.680365 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4066 12:46:18.682889 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4067 12:46:18.689279 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4068 12:46:18.692843 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4069 12:46:18.696191 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4070 12:46:18.699298 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4071 12:46:18.699382 ==
4072 12:46:18.703129 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 12:46:18.709529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 12:46:18.709610 ==
4075 12:46:18.709675 DQS Delay:
4076 12:46:18.712888 DQS0 = 0, DQS1 = 0
4077 12:46:18.712969 DQM Delay:
4078 12:46:18.715880 DQM0 = 40, DQM1 = 34
4079 12:46:18.715961 DQ Delay:
4080 12:46:18.718966 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4081 12:46:18.722617 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4082 12:46:18.725699 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4083 12:46:18.728865 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4084 12:46:18.728947
4085 12:46:18.729011
4086 12:46:18.729070 ==
4087 12:46:18.732631 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 12:46:18.735382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 12:46:18.735463 ==
4090 12:46:18.735527
4091 12:46:18.735585
4092 12:46:18.738662 TX Vref Scan disable
4093 12:46:18.742525 == TX Byte 0 ==
4094 12:46:18.745978 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4095 12:46:18.748365 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4096 12:46:18.751738 == TX Byte 1 ==
4097 12:46:18.755596 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4098 12:46:18.759143 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4099 12:46:18.759219 ==
4100 12:46:18.762014 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 12:46:18.768613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 12:46:18.768690 ==
4103 12:46:18.768753
4104 12:46:18.768813
4105 12:46:18.768872 TX Vref Scan disable
4106 12:46:18.773162 == TX Byte 0 ==
4107 12:46:18.776368 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4108 12:46:18.782864 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4109 12:46:18.782964 == TX Byte 1 ==
4110 12:46:18.785975 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4111 12:46:18.793396 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4112 12:46:18.793494
4113 12:46:18.793584 [DATLAT]
4114 12:46:18.793670 Freq=600, CH0 RK0
4115 12:46:18.793755
4116 12:46:18.795755 DATLAT Default: 0x9
4117 12:46:18.799242 0, 0xFFFF, sum = 0
4118 12:46:18.799313 1, 0xFFFF, sum = 0
4119 12:46:18.802370 2, 0xFFFF, sum = 0
4120 12:46:18.802440 3, 0xFFFF, sum = 0
4121 12:46:18.805616 4, 0xFFFF, sum = 0
4122 12:46:18.805686 5, 0xFFFF, sum = 0
4123 12:46:18.809395 6, 0xFFFF, sum = 0
4124 12:46:18.809466 7, 0xFFFF, sum = 0
4125 12:46:18.812363 8, 0x0, sum = 1
4126 12:46:18.812437 9, 0x0, sum = 2
4127 12:46:18.815741 10, 0x0, sum = 3
4128 12:46:18.815839 11, 0x0, sum = 4
4129 12:46:18.815928 best_step = 9
4130 12:46:18.816013
4131 12:46:18.819767 ==
4132 12:46:18.822600 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 12:46:18.825459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 12:46:18.825559 ==
4135 12:46:18.825624 RX Vref Scan: 1
4136 12:46:18.825685
4137 12:46:18.828997 RX Vref 0 -> 0, step: 1
4138 12:46:18.829096
4139 12:46:18.832459 RX Delay -195 -> 252, step: 8
4140 12:46:18.832530
4141 12:46:18.835612 Set Vref, RX VrefLevel [Byte0]: 52
4142 12:46:18.838661 [Byte1]: 59
4143 12:46:18.842148
4144 12:46:18.842224 Final RX Vref Byte 0 = 52 to rank0
4145 12:46:18.845326 Final RX Vref Byte 1 = 59 to rank0
4146 12:46:18.848424 Final RX Vref Byte 0 = 52 to rank1
4147 12:46:18.851808 Final RX Vref Byte 1 = 59 to rank1==
4148 12:46:18.855364 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 12:46:18.861840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 12:46:18.861913 ==
4151 12:46:18.861975 DQS Delay:
4152 12:46:18.862033 DQS0 = 0, DQS1 = 0
4153 12:46:18.865198 DQM Delay:
4154 12:46:18.865267 DQM0 = 41, DQM1 = 32
4155 12:46:18.868787 DQ Delay:
4156 12:46:18.872255 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4157 12:46:18.874687 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4158 12:46:18.878468 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4159 12:46:18.881554 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4160 12:46:18.881663
4161 12:46:18.881728
4162 12:46:18.888041 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4163 12:46:18.891961 CH0 RK0: MR19=808, MR18=4C44
4164 12:46:18.897902 CH0_RK0: MR19=0x808, MR18=0x4C44, DQSOSC=395, MR23=63, INC=168, DEC=112
4165 12:46:18.897974
4166 12:46:18.901200 ----->DramcWriteLeveling(PI) begin...
4167 12:46:18.901271 ==
4168 12:46:18.904476 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 12:46:18.907529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 12:46:18.907624 ==
4171 12:46:18.911174 Write leveling (Byte 0): 33 => 33
4172 12:46:18.914685 Write leveling (Byte 1): 29 => 29
4173 12:46:18.917649 DramcWriteLeveling(PI) end<-----
4174 12:46:18.917743
4175 12:46:18.917831 ==
4176 12:46:18.920697 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 12:46:18.924356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 12:46:18.927531 ==
4179 12:46:18.927626 [Gating] SW mode calibration
4180 12:46:18.937677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 12:46:18.940602 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 12:46:18.943829 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 12:46:18.950794 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 12:46:18.954187 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 12:46:18.957463 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4186 12:46:18.963726 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4187 12:46:18.967014 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 12:46:18.970261 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 12:46:18.977062 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 12:46:18.980106 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 12:46:18.983395 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 12:46:18.989980 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4193 12:46:18.993350 0 10 12 | B1->B0 | 2626 3434 | 0 1 | (1 1) (0 0)
4194 12:46:19.000021 0 10 16 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
4195 12:46:19.003020 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 12:46:19.006969 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 12:46:19.012508 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 12:46:19.016295 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 12:46:19.019205 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 12:46:19.025925 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 12:46:19.029055 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4202 12:46:19.032399 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:46:19.039918 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:46:19.042626 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:46:19.045935 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:46:19.052126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:46:19.055428 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:46:19.058974 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:46:19.065566 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:46:19.069292 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:46:19.072155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:46:19.078611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:46:19.082540 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:46:19.085293 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:46:19.091982 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:46:19.095307 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:46:19.098472 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4218 12:46:19.104725 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4219 12:46:19.104808 Total UI for P1: 0, mck2ui 16
4220 12:46:19.111343 best dqsien dly found for B0: ( 0, 13, 12)
4221 12:46:19.115067 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 12:46:19.118262 Total UI for P1: 0, mck2ui 16
4223 12:46:19.121358 best dqsien dly found for B1: ( 0, 13, 14)
4224 12:46:19.124568 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4225 12:46:19.127707 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4226 12:46:19.127790
4227 12:46:19.131238 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4228 12:46:19.134231 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4229 12:46:19.137528 [Gating] SW calibration Done
4230 12:46:19.137610 ==
4231 12:46:19.140861 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 12:46:19.147442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 12:46:19.147525 ==
4234 12:46:19.147608 RX Vref Scan: 0
4235 12:46:19.147709
4236 12:46:19.150786 RX Vref 0 -> 0, step: 1
4237 12:46:19.150868
4238 12:46:19.154157 RX Delay -230 -> 252, step: 16
4239 12:46:19.157552 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4240 12:46:19.161134 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4241 12:46:19.163826 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4242 12:46:19.170846 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4243 12:46:19.174516 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4244 12:46:19.177369 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4245 12:46:19.180323 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4246 12:46:19.187165 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4247 12:46:19.190969 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4248 12:46:19.193391 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4249 12:46:19.196871 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4250 12:46:19.203401 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4251 12:46:19.206991 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4252 12:46:19.210048 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4253 12:46:19.213203 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4254 12:46:19.219884 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4255 12:46:19.219969 ==
4256 12:46:19.223350 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 12:46:19.226308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 12:46:19.226385 ==
4259 12:46:19.226448 DQS Delay:
4260 12:46:19.229311 DQS0 = 0, DQS1 = 0
4261 12:46:19.229388 DQM Delay:
4262 12:46:19.232931 DQM0 = 42, DQM1 = 31
4263 12:46:19.233001 DQ Delay:
4264 12:46:19.236139 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4265 12:46:19.239938 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4266 12:46:19.242925 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4267 12:46:19.246167 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4268 12:46:19.246238
4269 12:46:19.246299
4270 12:46:19.246356 ==
4271 12:46:19.249273 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 12:46:19.256003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 12:46:19.256100 ==
4274 12:46:19.256168
4275 12:46:19.256228
4276 12:46:19.256284 TX Vref Scan disable
4277 12:46:19.259407 == TX Byte 0 ==
4278 12:46:19.262713 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4279 12:46:19.269418 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4280 12:46:19.269507 == TX Byte 1 ==
4281 12:46:19.272235 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4282 12:46:19.279306 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4283 12:46:19.279388 ==
4284 12:46:19.282133 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 12:46:19.285480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 12:46:19.285589 ==
4287 12:46:19.285727
4288 12:46:19.285798
4289 12:46:19.288993 TX Vref Scan disable
4290 12:46:19.292345 == TX Byte 0 ==
4291 12:46:19.295811 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4292 12:46:19.299479 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4293 12:46:19.301933 == TX Byte 1 ==
4294 12:46:19.305509 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4295 12:46:19.308690 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4296 12:46:19.308772
4297 12:46:19.312306 [DATLAT]
4298 12:46:19.312388 Freq=600, CH0 RK1
4299 12:46:19.312454
4300 12:46:19.315500 DATLAT Default: 0x9
4301 12:46:19.315582 0, 0xFFFF, sum = 0
4302 12:46:19.319127 1, 0xFFFF, sum = 0
4303 12:46:19.319211 2, 0xFFFF, sum = 0
4304 12:46:19.322033 3, 0xFFFF, sum = 0
4305 12:46:19.322117 4, 0xFFFF, sum = 0
4306 12:46:19.325534 5, 0xFFFF, sum = 0
4307 12:46:19.325618 6, 0xFFFF, sum = 0
4308 12:46:19.328888 7, 0xFFFF, sum = 0
4309 12:46:19.328970 8, 0x0, sum = 1
4310 12:46:19.331847 9, 0x0, sum = 2
4311 12:46:19.331956 10, 0x0, sum = 3
4312 12:46:19.335172 11, 0x0, sum = 4
4313 12:46:19.335256 best_step = 9
4314 12:46:19.335321
4315 12:46:19.335380 ==
4316 12:46:19.338212 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 12:46:19.341748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 12:46:19.344713 ==
4319 12:46:19.344799 RX Vref Scan: 0
4320 12:46:19.344865
4321 12:46:19.348549 RX Vref 0 -> 0, step: 1
4322 12:46:19.348631
4323 12:46:19.351716 RX Delay -195 -> 252, step: 8
4324 12:46:19.354934 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4325 12:46:19.357891 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4326 12:46:19.364393 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4327 12:46:19.367578 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4328 12:46:19.371155 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4329 12:46:19.374342 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4330 12:46:19.381619 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4331 12:46:19.384293 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4332 12:46:19.388271 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4333 12:46:19.391013 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4334 12:46:19.397591 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4335 12:46:19.400882 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4336 12:46:19.404146 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4337 12:46:19.407940 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4338 12:46:19.414570 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4339 12:46:19.417591 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4340 12:46:19.417671 ==
4341 12:46:19.420420 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 12:46:19.424221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 12:46:19.424301 ==
4344 12:46:19.427768 DQS Delay:
4345 12:46:19.427847 DQS0 = 0, DQS1 = 0
4346 12:46:19.427909 DQM Delay:
4347 12:46:19.430343 DQM0 = 40, DQM1 = 33
4348 12:46:19.430422 DQ Delay:
4349 12:46:19.433966 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4350 12:46:19.437063 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4351 12:46:19.440646 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4352 12:46:19.444542 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4353 12:46:19.444621
4354 12:46:19.444683
4355 12:46:19.453473 [DQSOSCAuto] RK1, (LSB)MR18= 0x423c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4356 12:46:19.456833 CH0 RK1: MR19=808, MR18=423C
4357 12:46:19.460002 CH0_RK1: MR19=0x808, MR18=0x423C, DQSOSC=397, MR23=63, INC=166, DEC=110
4358 12:46:19.463719 [RxdqsGatingPostProcess] freq 600
4359 12:46:19.470148 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4360 12:46:19.473331 Pre-setting of DQS Precalculation
4361 12:46:19.476577 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4362 12:46:19.479544 ==
4363 12:46:19.479623 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 12:46:19.486392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 12:46:19.486471 ==
4366 12:46:19.489707 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 12:46:19.496392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4368 12:46:19.499824 [CA 0] Center 36 (6~66) winsize 61
4369 12:46:19.503563 [CA 1] Center 35 (5~66) winsize 62
4370 12:46:19.506496 [CA 2] Center 34 (4~65) winsize 62
4371 12:46:19.509647 [CA 3] Center 34 (4~65) winsize 62
4372 12:46:19.513193 [CA 4] Center 34 (4~65) winsize 62
4373 12:46:19.516818 [CA 5] Center 34 (3~65) winsize 63
4374 12:46:19.516897
4375 12:46:19.519909 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4376 12:46:19.520027
4377 12:46:19.523341 [CATrainingPosCal] consider 1 rank data
4378 12:46:19.526125 u2DelayCellTimex100 = 270/100 ps
4379 12:46:19.533243 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4380 12:46:19.535923 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4381 12:46:19.539272 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 12:46:19.542283 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 12:46:19.546141 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 12:46:19.549282 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4385 12:46:19.549361
4386 12:46:19.552535 CA PerBit enable=1, Macro0, CA PI delay=34
4387 12:46:19.552614
4388 12:46:19.556192 [CBTSetCACLKResult] CA Dly = 34
4389 12:46:19.559475 CS Dly: 4 (0~35)
4390 12:46:19.559553 ==
4391 12:46:19.562547 Dram Type= 6, Freq= 0, CH_1, rank 1
4392 12:46:19.565756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 12:46:19.565836 ==
4394 12:46:19.572417 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4395 12:46:19.575674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4396 12:46:19.580648 [CA 0] Center 36 (6~66) winsize 61
4397 12:46:19.583516 [CA 1] Center 35 (5~66) winsize 62
4398 12:46:19.586697 [CA 2] Center 34 (4~65) winsize 62
4399 12:46:19.589748 [CA 3] Center 33 (3~64) winsize 62
4400 12:46:19.593291 [CA 4] Center 34 (4~64) winsize 61
4401 12:46:19.597263 [CA 5] Center 33 (3~64) winsize 62
4402 12:46:19.597342
4403 12:46:19.600302 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4404 12:46:19.600394
4405 12:46:19.602798 [CATrainingPosCal] consider 2 rank data
4406 12:46:19.606665 u2DelayCellTimex100 = 270/100 ps
4407 12:46:19.609769 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4408 12:46:19.616177 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4409 12:46:19.619668 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 12:46:19.623070 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4411 12:46:19.626209 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4412 12:46:19.629567 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 12:46:19.629645
4414 12:46:19.632668 CA PerBit enable=1, Macro0, CA PI delay=33
4415 12:46:19.632747
4416 12:46:19.635988 [CBTSetCACLKResult] CA Dly = 33
4417 12:46:19.639084 CS Dly: 5 (0~37)
4418 12:46:19.639163
4419 12:46:19.643171 ----->DramcWriteLeveling(PI) begin...
4420 12:46:19.643251 ==
4421 12:46:19.646153 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 12:46:19.649411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 12:46:19.649489 ==
4424 12:46:19.652334 Write leveling (Byte 0): 28 => 28
4425 12:46:19.655773 Write leveling (Byte 1): 29 => 29
4426 12:46:19.658980 DramcWriteLeveling(PI) end<-----
4427 12:46:19.659061
4428 12:46:19.659124 ==
4429 12:46:19.662517 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 12:46:19.665425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 12:46:19.665506 ==
4432 12:46:19.669011 [Gating] SW mode calibration
4433 12:46:19.675543 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4434 12:46:19.682027 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4435 12:46:19.685595 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 12:46:19.689038 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 12:46:19.695168 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 12:46:19.698390 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
4439 12:46:19.702121 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 12:46:19.708344 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 12:46:19.711606 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 12:46:19.714946 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 12:46:19.721470 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 12:46:19.725152 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 12:46:19.728362 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 12:46:19.735104 0 10 12 | B1->B0 | 2f2f 3636 | 0 0 | (1 1) (0 0)
4447 12:46:19.737906 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 12:46:19.741649 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 12:46:19.747922 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 12:46:19.751273 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 12:46:19.754353 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 12:46:19.761035 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 12:46:19.764170 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 12:46:19.767733 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4455 12:46:19.774494 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:46:19.777424 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:46:19.784985 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:46:19.787221 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:46:19.791018 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:46:19.793852 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:46:19.800781 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:46:19.804088 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:46:19.810336 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:46:19.813687 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:46:19.816817 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:46:19.823297 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:46:19.827086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:46:19.830316 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:46:19.836780 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:46:19.840642 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4471 12:46:19.843831 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4472 12:46:19.846684 Total UI for P1: 0, mck2ui 16
4473 12:46:19.849971 best dqsien dly found for B0: ( 0, 13, 12)
4474 12:46:19.856901 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 12:46:19.856977 Total UI for P1: 0, mck2ui 16
4476 12:46:19.860063 best dqsien dly found for B1: ( 0, 13, 14)
4477 12:46:19.866295 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4478 12:46:19.869925 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4479 12:46:19.869995
4480 12:46:19.872863 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4481 12:46:19.875973 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4482 12:46:19.879178 [Gating] SW calibration Done
4483 12:46:19.879274 ==
4484 12:46:19.883302 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 12:46:19.886015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 12:46:19.886116 ==
4487 12:46:19.889290 RX Vref Scan: 0
4488 12:46:19.889369
4489 12:46:19.889435 RX Vref 0 -> 0, step: 1
4490 12:46:19.889498
4491 12:46:19.892345 RX Delay -230 -> 252, step: 16
4492 12:46:19.899138 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4493 12:46:19.902644 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4494 12:46:19.905976 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4495 12:46:19.909079 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4496 12:46:19.915775 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4497 12:46:19.918955 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4498 12:46:19.922033 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4499 12:46:19.925244 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4500 12:46:19.929018 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4501 12:46:19.935616 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4502 12:46:19.938339 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4503 12:46:19.941892 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4504 12:46:19.945394 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4505 12:46:19.952122 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4506 12:46:19.954781 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4507 12:46:19.958057 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4508 12:46:19.958127 ==
4509 12:46:19.961832 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 12:46:19.968262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 12:46:19.968335 ==
4512 12:46:19.968397 DQS Delay:
4513 12:46:19.971541 DQS0 = 0, DQS1 = 0
4514 12:46:19.971640 DQM Delay:
4515 12:46:19.971713 DQM0 = 44, DQM1 = 38
4516 12:46:19.975448 DQ Delay:
4517 12:46:19.977996 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4518 12:46:19.981718 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4519 12:46:19.984520 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4520 12:46:19.987753 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4521 12:46:19.987852
4522 12:46:19.987942
4523 12:46:19.988027 ==
4524 12:46:19.990982 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 12:46:19.994602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 12:46:19.994704 ==
4527 12:46:19.994795
4528 12:46:19.994902
4529 12:46:19.997758 TX Vref Scan disable
4530 12:46:20.001218 == TX Byte 0 ==
4531 12:46:20.004337 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4532 12:46:20.007983 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4533 12:46:20.010921 == TX Byte 1 ==
4534 12:46:20.014026 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4535 12:46:20.017387 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4536 12:46:20.017485 ==
4537 12:46:20.021183 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 12:46:20.023805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 12:46:20.027179 ==
4540 12:46:20.027255
4541 12:46:20.027318
4542 12:46:20.027377 TX Vref Scan disable
4543 12:46:20.031055 == TX Byte 0 ==
4544 12:46:20.034528 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4545 12:46:20.040987 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4546 12:46:20.041090 == TX Byte 1 ==
4547 12:46:20.044212 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4548 12:46:20.051162 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4549 12:46:20.051238
4550 12:46:20.051303 [DATLAT]
4551 12:46:20.051368 Freq=600, CH1 RK0
4552 12:46:20.051431
4553 12:46:20.054384 DATLAT Default: 0x9
4554 12:46:20.054481 0, 0xFFFF, sum = 0
4555 12:46:20.058106 1, 0xFFFF, sum = 0
4556 12:46:20.060709 2, 0xFFFF, sum = 0
4557 12:46:20.060808 3, 0xFFFF, sum = 0
4558 12:46:20.064582 4, 0xFFFF, sum = 0
4559 12:46:20.064651 5, 0xFFFF, sum = 0
4560 12:46:20.067975 6, 0xFFFF, sum = 0
4561 12:46:20.068106 7, 0xFFFF, sum = 0
4562 12:46:20.071030 8, 0x0, sum = 1
4563 12:46:20.071127 9, 0x0, sum = 2
4564 12:46:20.074019 10, 0x0, sum = 3
4565 12:46:20.074092 11, 0x0, sum = 4
4566 12:46:20.074161 best_step = 9
4567 12:46:20.074222
4568 12:46:20.077443 ==
4569 12:46:20.080286 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 12:46:20.084020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 12:46:20.084158 ==
4572 12:46:20.084247 RX Vref Scan: 1
4573 12:46:20.084334
4574 12:46:20.087341 RX Vref 0 -> 0, step: 1
4575 12:46:20.087427
4576 12:46:20.090581 RX Delay -179 -> 252, step: 8
4577 12:46:20.090683
4578 12:46:20.093716 Set Vref, RX VrefLevel [Byte0]: 52
4579 12:46:20.096761 [Byte1]: 48
4580 12:46:20.096860
4581 12:46:20.100214 Final RX Vref Byte 0 = 52 to rank0
4582 12:46:20.103476 Final RX Vref Byte 1 = 48 to rank0
4583 12:46:20.106960 Final RX Vref Byte 0 = 52 to rank1
4584 12:46:20.110163 Final RX Vref Byte 1 = 48 to rank1==
4585 12:46:20.113417 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 12:46:20.119964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 12:46:20.120084 ==
4588 12:46:20.120166 DQS Delay:
4589 12:46:20.120243 DQS0 = 0, DQS1 = 0
4590 12:46:20.123036 DQM Delay:
4591 12:46:20.123111 DQM0 = 42, DQM1 = 34
4592 12:46:20.126291 DQ Delay:
4593 12:46:20.129760 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4594 12:46:20.133407 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4595 12:46:20.136699 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4596 12:46:20.139567 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4597 12:46:20.139662
4598 12:46:20.139729
4599 12:46:20.146091 [DQSOSCAuto] RK0, (LSB)MR18= 0x3049, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 400 ps
4600 12:46:20.149475 CH1 RK0: MR19=808, MR18=3049
4601 12:46:20.156067 CH1_RK0: MR19=0x808, MR18=0x3049, DQSOSC=396, MR23=63, INC=167, DEC=111
4602 12:46:20.156148
4603 12:46:20.160044 ----->DramcWriteLeveling(PI) begin...
4604 12:46:20.160126 ==
4605 12:46:20.162741 Dram Type= 6, Freq= 0, CH_1, rank 1
4606 12:46:20.165948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 12:46:20.166031 ==
4608 12:46:20.169061 Write leveling (Byte 0): 29 => 29
4609 12:46:20.172489 Write leveling (Byte 1): 28 => 28
4610 12:46:20.175999 DramcWriteLeveling(PI) end<-----
4611 12:46:20.176090
4612 12:46:20.176156 ==
4613 12:46:20.179149 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 12:46:20.182129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 12:46:20.185432 ==
4616 12:46:20.185513 [Gating] SW mode calibration
4617 12:46:20.195686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4618 12:46:20.198634 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4619 12:46:20.202603 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 12:46:20.209348 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 12:46:20.212086 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 12:46:20.215721 0 9 12 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (1 1)
4623 12:46:20.221810 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4624 12:46:20.224898 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 12:46:20.228590 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 12:46:20.234987 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 12:46:20.238135 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 12:46:20.241169 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 12:46:20.248429 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4630 12:46:20.251511 0 10 12 | B1->B0 | 3030 3f3f | 1 0 | (0 0) (0 0)
4631 12:46:20.257657 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:46:20.261142 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 12:46:20.264535 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 12:46:20.270866 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 12:46:20.274401 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 12:46:20.277732 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 12:46:20.284128 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4638 12:46:20.287386 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4639 12:46:20.290826 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:46:20.297155 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:46:20.300309 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:46:20.304373 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:46:20.310218 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:46:20.313510 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:46:20.317037 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:46:20.323649 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:46:20.326877 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:46:20.329913 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:46:20.336637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:46:20.339976 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:46:20.343196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:46:20.349607 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:46:20.352993 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4654 12:46:20.356165 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4655 12:46:20.362634 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 12:46:20.362742 Total UI for P1: 0, mck2ui 16
4657 12:46:20.369655 best dqsien dly found for B0: ( 0, 13, 10)
4658 12:46:20.369736 Total UI for P1: 0, mck2ui 16
4659 12:46:20.376171 best dqsien dly found for B1: ( 0, 13, 10)
4660 12:46:20.379892 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4661 12:46:20.382541 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4662 12:46:20.382622
4663 12:46:20.386467 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4664 12:46:20.389517 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4665 12:46:20.393180 [Gating] SW calibration Done
4666 12:46:20.393261 ==
4667 12:46:20.396295 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 12:46:20.398886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 12:46:20.398967 ==
4670 12:46:20.402770 RX Vref Scan: 0
4671 12:46:20.402850
4672 12:46:20.402914 RX Vref 0 -> 0, step: 1
4673 12:46:20.406043
4674 12:46:20.406123 RX Delay -230 -> 252, step: 16
4675 12:46:20.412735 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4676 12:46:20.415535 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4677 12:46:20.418889 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4678 12:46:20.422010 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4679 12:46:20.429278 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4680 12:46:20.431808 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4681 12:46:20.435891 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4682 12:46:20.438466 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4683 12:46:20.445126 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4684 12:46:20.448590 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4685 12:46:20.452140 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4686 12:46:20.455102 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4687 12:46:20.458590 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4688 12:46:20.465491 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4689 12:46:20.469029 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4690 12:46:20.471491 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4691 12:46:20.471572 ==
4692 12:46:20.474919 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 12:46:20.481592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 12:46:20.481673 ==
4695 12:46:20.481736 DQS Delay:
4696 12:46:20.484472 DQS0 = 0, DQS1 = 0
4697 12:46:20.484552 DQM Delay:
4698 12:46:20.484615 DQM0 = 42, DQM1 = 39
4699 12:46:20.488127 DQ Delay:
4700 12:46:20.490942 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4701 12:46:20.494562 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4702 12:46:20.498433 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4703 12:46:20.501204 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4704 12:46:20.501285
4705 12:46:20.501349
4706 12:46:20.501407 ==
4707 12:46:20.504292 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 12:46:20.507577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 12:46:20.507657 ==
4710 12:46:20.507722
4711 12:46:20.507779
4712 12:46:20.511330 TX Vref Scan disable
4713 12:46:20.514635 == TX Byte 0 ==
4714 12:46:20.517238 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4715 12:46:20.520953 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4716 12:46:20.523902 == TX Byte 1 ==
4717 12:46:20.527373 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4718 12:46:20.530494 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4719 12:46:20.530584 ==
4720 12:46:20.533830 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 12:46:20.540364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 12:46:20.540452 ==
4723 12:46:20.540517
4724 12:46:20.540578
4725 12:46:20.540634 TX Vref Scan disable
4726 12:46:20.544724 == TX Byte 0 ==
4727 12:46:20.547833 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4728 12:46:20.554483 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4729 12:46:20.554597 == TX Byte 1 ==
4730 12:46:20.557794 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4731 12:46:20.564385 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4732 12:46:20.564539
4733 12:46:20.564663 [DATLAT]
4734 12:46:20.564776 Freq=600, CH1 RK1
4735 12:46:20.564868
4736 12:46:20.567805 DATLAT Default: 0x9
4737 12:46:20.567919 0, 0xFFFF, sum = 0
4738 12:46:20.571237 1, 0xFFFF, sum = 0
4739 12:46:20.574251 2, 0xFFFF, sum = 0
4740 12:46:20.574396 3, 0xFFFF, sum = 0
4741 12:46:20.577804 4, 0xFFFF, sum = 0
4742 12:46:20.577938 5, 0xFFFF, sum = 0
4743 12:46:20.580805 6, 0xFFFF, sum = 0
4744 12:46:20.580930 7, 0xFFFF, sum = 0
4745 12:46:20.584604 8, 0x0, sum = 1
4746 12:46:20.584710 9, 0x0, sum = 2
4747 12:46:20.587213 10, 0x0, sum = 3
4748 12:46:20.587358 11, 0x0, sum = 4
4749 12:46:20.587486 best_step = 9
4750 12:46:20.587598
4751 12:46:20.590624 ==
4752 12:46:20.594138 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 12:46:20.597521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 12:46:20.597617 ==
4755 12:46:20.597696 RX Vref Scan: 0
4756 12:46:20.597771
4757 12:46:20.600833 RX Vref 0 -> 0, step: 1
4758 12:46:20.600947
4759 12:46:20.603860 RX Delay -179 -> 252, step: 8
4760 12:46:20.610566 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4761 12:46:20.613894 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4762 12:46:20.617288 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4763 12:46:20.620719 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4764 12:46:20.623477 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4765 12:46:20.630267 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4766 12:46:20.634199 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4767 12:46:20.637277 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4768 12:46:20.639949 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4769 12:46:20.646812 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4770 12:46:20.650132 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4771 12:46:20.653286 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4772 12:46:20.656859 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4773 12:46:20.663029 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4774 12:46:20.666373 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4775 12:46:20.669875 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4776 12:46:20.670098 ==
4777 12:46:20.672972 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 12:46:20.679389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 12:46:20.679610 ==
4780 12:46:20.679852 DQS Delay:
4781 12:46:20.680121 DQS0 = 0, DQS1 = 0
4782 12:46:20.682638 DQM Delay:
4783 12:46:20.682850 DQM0 = 37, DQM1 = 34
4784 12:46:20.686968 DQ Delay:
4785 12:46:20.689412 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4786 12:46:20.692995 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4787 12:46:20.696161 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4788 12:46:20.699556 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =44
4789 12:46:20.699835
4790 12:46:20.700091
4791 12:46:20.705639 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f53, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4792 12:46:20.709548 CH1 RK1: MR19=808, MR18=2F53
4793 12:46:20.715956 CH1_RK1: MR19=0x808, MR18=0x2F53, DQSOSC=394, MR23=63, INC=168, DEC=112
4794 12:46:20.719547 [RxdqsGatingPostProcess] freq 600
4795 12:46:20.722431 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4796 12:46:20.725839 Pre-setting of DQS Precalculation
4797 12:46:20.732318 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4798 12:46:20.738635 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4799 12:46:20.745291 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4800 12:46:20.745516
4801 12:46:20.745687
4802 12:46:20.748743 [Calibration Summary] 1200 Mbps
4803 12:46:20.748955 CH 0, Rank 0
4804 12:46:20.752429 SW Impedance : PASS
4805 12:46:20.755411 DUTY Scan : NO K
4806 12:46:20.755622 ZQ Calibration : PASS
4807 12:46:20.758718 Jitter Meter : NO K
4808 12:46:20.762228 CBT Training : PASS
4809 12:46:20.762487 Write leveling : PASS
4810 12:46:20.765055 RX DQS gating : PASS
4811 12:46:20.768496 RX DQ/DQS(RDDQC) : PASS
4812 12:46:20.768707 TX DQ/DQS : PASS
4813 12:46:20.771893 RX DATLAT : PASS
4814 12:46:20.775235 RX DQ/DQS(Engine): PASS
4815 12:46:20.775447 TX OE : NO K
4816 12:46:20.778104 All Pass.
4817 12:46:20.778346
4818 12:46:20.778518 CH 0, Rank 1
4819 12:46:20.781584 SW Impedance : PASS
4820 12:46:20.781797 DUTY Scan : NO K
4821 12:46:20.784871 ZQ Calibration : PASS
4822 12:46:20.788276 Jitter Meter : NO K
4823 12:46:20.788563 CBT Training : PASS
4824 12:46:20.791219 Write leveling : PASS
4825 12:46:20.794531 RX DQS gating : PASS
4826 12:46:20.794755 RX DQ/DQS(RDDQC) : PASS
4827 12:46:20.798214 TX DQ/DQS : PASS
4828 12:46:20.801366 RX DATLAT : PASS
4829 12:46:20.801577 RX DQ/DQS(Engine): PASS
4830 12:46:20.804845 TX OE : NO K
4831 12:46:20.805055 All Pass.
4832 12:46:20.805220
4833 12:46:20.807915 CH 1, Rank 0
4834 12:46:20.808150 SW Impedance : PASS
4835 12:46:20.811411 DUTY Scan : NO K
4836 12:46:20.814637 ZQ Calibration : PASS
4837 12:46:20.814845 Jitter Meter : NO K
4838 12:46:20.817734 CBT Training : PASS
4839 12:46:20.820699 Write leveling : PASS
4840 12:46:20.820908 RX DQS gating : PASS
4841 12:46:20.824780 RX DQ/DQS(RDDQC) : PASS
4842 12:46:20.827640 TX DQ/DQS : PASS
4843 12:46:20.827851 RX DATLAT : PASS
4844 12:46:20.830963 RX DQ/DQS(Engine): PASS
4845 12:46:20.834159 TX OE : NO K
4846 12:46:20.834369 All Pass.
4847 12:46:20.834541
4848 12:46:20.834735 CH 1, Rank 1
4849 12:46:20.837328 SW Impedance : PASS
4850 12:46:20.841049 DUTY Scan : NO K
4851 12:46:20.841259 ZQ Calibration : PASS
4852 12:46:20.844100 Jitter Meter : NO K
4853 12:46:20.847016 CBT Training : PASS
4854 12:46:20.847226 Write leveling : PASS
4855 12:46:20.850464 RX DQS gating : PASS
4856 12:46:20.850675 RX DQ/DQS(RDDQC) : PASS
4857 12:46:20.853810 TX DQ/DQS : PASS
4858 12:46:20.856881 RX DATLAT : PASS
4859 12:46:20.857092 RX DQ/DQS(Engine): PASS
4860 12:46:20.860331 TX OE : NO K
4861 12:46:20.860504 All Pass.
4862 12:46:20.860642
4863 12:46:20.863432 DramC Write-DBI off
4864 12:46:20.866750 PER_BANK_REFRESH: Hybrid Mode
4865 12:46:20.866896 TX_TRACKING: ON
4866 12:46:20.877197 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4867 12:46:20.880117 [FAST_K] Save calibration result to emmc
4868 12:46:20.883394 dramc_set_vcore_voltage set vcore to 662500
4869 12:46:20.886536 Read voltage for 933, 3
4870 12:46:20.886672 Vio18 = 0
4871 12:46:20.889964 Vcore = 662500
4872 12:46:20.890047 Vdram = 0
4873 12:46:20.890111 Vddq = 0
4874 12:46:20.890171 Vmddr = 0
4875 12:46:20.896586 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4876 12:46:20.902940 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4877 12:46:20.903024 MEM_TYPE=3, freq_sel=17
4878 12:46:20.906223 sv_algorithm_assistance_LP4_1600
4879 12:46:20.909517 ============ PULL DRAM RESETB DOWN ============
4880 12:46:20.916461 ========== PULL DRAM RESETB DOWN end =========
4881 12:46:20.919823 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4882 12:46:20.922763 ===================================
4883 12:46:20.926059 LPDDR4 DRAM CONFIGURATION
4884 12:46:20.929215 ===================================
4885 12:46:20.929297 EX_ROW_EN[0] = 0x0
4886 12:46:20.932429 EX_ROW_EN[1] = 0x0
4887 12:46:20.935967 LP4Y_EN = 0x0
4888 12:46:20.936071 WORK_FSP = 0x0
4889 12:46:20.939929 WL = 0x3
4890 12:46:20.940010 RL = 0x3
4891 12:46:20.942291 BL = 0x2
4892 12:46:20.942372 RPST = 0x0
4893 12:46:20.945488 RD_PRE = 0x0
4894 12:46:20.945569 WR_PRE = 0x1
4895 12:46:20.949112 WR_PST = 0x0
4896 12:46:20.949193 DBI_WR = 0x0
4897 12:46:20.952259 DBI_RD = 0x0
4898 12:46:20.952340 OTF = 0x1
4899 12:46:20.955779 ===================================
4900 12:46:20.959163 ===================================
4901 12:46:20.961938 ANA top config
4902 12:46:20.965330 ===================================
4903 12:46:20.968845 DLL_ASYNC_EN = 0
4904 12:46:20.968926 ALL_SLAVE_EN = 1
4905 12:46:20.971649 NEW_RANK_MODE = 1
4906 12:46:20.975262 DLL_IDLE_MODE = 1
4907 12:46:20.978273 LP45_APHY_COMB_EN = 1
4908 12:46:20.978355 TX_ODT_DIS = 1
4909 12:46:20.981692 NEW_8X_MODE = 1
4910 12:46:20.985376 ===================================
4911 12:46:20.988778 ===================================
4912 12:46:20.991652 data_rate = 1866
4913 12:46:20.995068 CKR = 1
4914 12:46:20.998672 DQ_P2S_RATIO = 8
4915 12:46:21.001773 ===================================
4916 12:46:21.004824 CA_P2S_RATIO = 8
4917 12:46:21.004905 DQ_CA_OPEN = 0
4918 12:46:21.008383 DQ_SEMI_OPEN = 0
4919 12:46:21.011608 CA_SEMI_OPEN = 0
4920 12:46:21.014970 CA_FULL_RATE = 0
4921 12:46:21.017824 DQ_CKDIV4_EN = 1
4922 12:46:21.021599 CA_CKDIV4_EN = 1
4923 12:46:21.024658 CA_PREDIV_EN = 0
4924 12:46:21.024739 PH8_DLY = 0
4925 12:46:21.028247 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4926 12:46:21.030909 DQ_AAMCK_DIV = 4
4927 12:46:21.034718 CA_AAMCK_DIV = 4
4928 12:46:21.038021 CA_ADMCK_DIV = 4
4929 12:46:21.040941 DQ_TRACK_CA_EN = 0
4930 12:46:21.041023 CA_PICK = 933
4931 12:46:21.044269 CA_MCKIO = 933
4932 12:46:21.047901 MCKIO_SEMI = 0
4933 12:46:21.051078 PLL_FREQ = 3732
4934 12:46:21.054330 DQ_UI_PI_RATIO = 32
4935 12:46:21.057362 CA_UI_PI_RATIO = 0
4936 12:46:21.061053 ===================================
4937 12:46:21.064084 ===================================
4938 12:46:21.067344 memory_type:LPDDR4
4939 12:46:21.067425 GP_NUM : 10
4940 12:46:21.070804 SRAM_EN : 1
4941 12:46:21.070886 MD32_EN : 0
4942 12:46:21.073563 ===================================
4943 12:46:21.077395 [ANA_INIT] >>>>>>>>>>>>>>
4944 12:46:21.080608 <<<<<< [CONFIGURE PHASE]: ANA_TX
4945 12:46:21.083727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4946 12:46:21.087418 ===================================
4947 12:46:21.090243 data_rate = 1866,PCW = 0X8f00
4948 12:46:21.093495 ===================================
4949 12:46:21.097031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4950 12:46:21.104027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 12:46:21.106576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4952 12:46:21.113276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4953 12:46:21.117013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4954 12:46:21.119754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4955 12:46:21.119835 [ANA_INIT] flow start
4956 12:46:21.123189 [ANA_INIT] PLL >>>>>>>>
4957 12:46:21.126383 [ANA_INIT] PLL <<<<<<<<
4958 12:46:21.126465 [ANA_INIT] MIDPI >>>>>>>>
4959 12:46:21.129932 [ANA_INIT] MIDPI <<<<<<<<
4960 12:46:21.133042 [ANA_INIT] DLL >>>>>>>>
4961 12:46:21.133123 [ANA_INIT] flow end
4962 12:46:21.140010 ============ LP4 DIFF to SE enter ============
4963 12:46:21.142918 ============ LP4 DIFF to SE exit ============
4964 12:46:21.146457 [ANA_INIT] <<<<<<<<<<<<<
4965 12:46:21.149453 [Flow] Enable top DCM control >>>>>
4966 12:46:21.152633 [Flow] Enable top DCM control <<<<<
4967 12:46:21.156038 Enable DLL master slave shuffle
4968 12:46:21.159567 ==============================================================
4969 12:46:21.162594 Gating Mode config
4970 12:46:21.169101 ==============================================================
4971 12:46:21.169183 Config description:
4972 12:46:21.179019 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4973 12:46:21.185775 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4974 12:46:21.189145 SELPH_MODE 0: By rank 1: By Phase
4975 12:46:21.196267 ==============================================================
4976 12:46:21.198759 GAT_TRACK_EN = 1
4977 12:46:21.203113 RX_GATING_MODE = 2
4978 12:46:21.205628 RX_GATING_TRACK_MODE = 2
4979 12:46:21.208906 SELPH_MODE = 1
4980 12:46:21.212707 PICG_EARLY_EN = 1
4981 12:46:21.215898 VALID_LAT_VALUE = 1
4982 12:46:21.218695 ==============================================================
4983 12:46:21.222122 Enter into Gating configuration >>>>
4984 12:46:21.225248 Exit from Gating configuration <<<<
4985 12:46:21.228367 Enter into DVFS_PRE_config >>>>>
4986 12:46:21.241679 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4987 12:46:21.244768 Exit from DVFS_PRE_config <<<<<
4988 12:46:21.248849 Enter into PICG configuration >>>>
4989 12:46:21.248930 Exit from PICG configuration <<<<
4990 12:46:21.251688 [RX_INPUT] configuration >>>>>
4991 12:46:21.254981 [RX_INPUT] configuration <<<<<
4992 12:46:21.262060 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4993 12:46:21.264785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4994 12:46:21.271642 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 12:46:21.277696 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 12:46:21.284513 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4997 12:46:21.291258 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4998 12:46:21.294470 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4999 12:46:21.297390 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5000 12:46:21.304354 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5001 12:46:21.307427 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5002 12:46:21.310928 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5003 12:46:21.317074 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5004 12:46:21.320192 ===================================
5005 12:46:21.320274 LPDDR4 DRAM CONFIGURATION
5006 12:46:21.323886 ===================================
5007 12:46:21.327375 EX_ROW_EN[0] = 0x0
5008 12:46:21.327458 EX_ROW_EN[1] = 0x0
5009 12:46:21.330249 LP4Y_EN = 0x0
5010 12:46:21.333708 WORK_FSP = 0x0
5011 12:46:21.333790 WL = 0x3
5012 12:46:21.336815 RL = 0x3
5013 12:46:21.336896 BL = 0x2
5014 12:46:21.340445 RPST = 0x0
5015 12:46:21.340527 RD_PRE = 0x0
5016 12:46:21.343662 WR_PRE = 0x1
5017 12:46:21.343743 WR_PST = 0x0
5018 12:46:21.347017 DBI_WR = 0x0
5019 12:46:21.347098 DBI_RD = 0x0
5020 12:46:21.350517 OTF = 0x1
5021 12:46:21.353880 ===================================
5022 12:46:21.356821 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5023 12:46:21.360155 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5024 12:46:21.366899 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5025 12:46:21.369945 ===================================
5026 12:46:21.370027 LPDDR4 DRAM CONFIGURATION
5027 12:46:21.373476 ===================================
5028 12:46:21.376320 EX_ROW_EN[0] = 0x10
5029 12:46:21.376401 EX_ROW_EN[1] = 0x0
5030 12:46:21.379887 LP4Y_EN = 0x0
5031 12:46:21.383497 WORK_FSP = 0x0
5032 12:46:21.383578 WL = 0x3
5033 12:46:21.386161 RL = 0x3
5034 12:46:21.386242 BL = 0x2
5035 12:46:21.389789 RPST = 0x0
5036 12:46:21.389871 RD_PRE = 0x0
5037 12:46:21.393084 WR_PRE = 0x1
5038 12:46:21.393166 WR_PST = 0x0
5039 12:46:21.396347 DBI_WR = 0x0
5040 12:46:21.396428 DBI_RD = 0x0
5041 12:46:21.399422 OTF = 0x1
5042 12:46:21.402781 ===================================
5043 12:46:21.409202 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5044 12:46:21.412776 nWR fixed to 30
5045 12:46:21.412857 [ModeRegInit_LP4] CH0 RK0
5046 12:46:21.415996 [ModeRegInit_LP4] CH0 RK1
5047 12:46:21.419377 [ModeRegInit_LP4] CH1 RK0
5048 12:46:21.422522 [ModeRegInit_LP4] CH1 RK1
5049 12:46:21.422602 match AC timing 9
5050 12:46:21.429279 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5051 12:46:21.433029 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5052 12:46:21.436315 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5053 12:46:21.442133 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5054 12:46:21.445676 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5055 12:46:21.445757 ==
5056 12:46:21.448793 Dram Type= 6, Freq= 0, CH_0, rank 0
5057 12:46:21.451961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5058 12:46:21.452068 ==
5059 12:46:21.458756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5060 12:46:21.465341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5061 12:46:21.468865 [CA 0] Center 37 (7~68) winsize 62
5062 12:46:21.471953 [CA 1] Center 37 (7~68) winsize 62
5063 12:46:21.475691 [CA 2] Center 34 (4~64) winsize 61
5064 12:46:21.478870 [CA 3] Center 34 (4~65) winsize 62
5065 12:46:21.482310 [CA 4] Center 33 (3~63) winsize 61
5066 12:46:21.485002 [CA 5] Center 32 (2~63) winsize 62
5067 12:46:21.485083
5068 12:46:21.488679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5069 12:46:21.488760
5070 12:46:21.491723 [CATrainingPosCal] consider 1 rank data
5071 12:46:21.494884 u2DelayCellTimex100 = 270/100 ps
5072 12:46:21.498307 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5073 12:46:21.501689 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5074 12:46:21.504940 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5075 12:46:21.507877 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 12:46:21.514648 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5077 12:46:21.518122 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5078 12:46:21.518202
5079 12:46:21.521635 CA PerBit enable=1, Macro0, CA PI delay=32
5080 12:46:21.521715
5081 12:46:21.524742 [CBTSetCACLKResult] CA Dly = 32
5082 12:46:21.524823 CS Dly: 5 (0~36)
5083 12:46:21.524887 ==
5084 12:46:21.527646 Dram Type= 6, Freq= 0, CH_0, rank 1
5085 12:46:21.535314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 12:46:21.535396 ==
5087 12:46:21.537676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5088 12:46:21.544390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5089 12:46:21.547925 [CA 0] Center 38 (8~68) winsize 61
5090 12:46:21.550795 [CA 1] Center 37 (7~68) winsize 62
5091 12:46:21.554383 [CA 2] Center 34 (4~65) winsize 62
5092 12:46:21.557190 [CA 3] Center 34 (4~65) winsize 62
5093 12:46:21.560918 [CA 4] Center 33 (2~64) winsize 63
5094 12:46:21.564329 [CA 5] Center 32 (2~63) winsize 62
5095 12:46:21.564410
5096 12:46:21.567206 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5097 12:46:21.567288
5098 12:46:21.571060 [CATrainingPosCal] consider 2 rank data
5099 12:46:21.574342 u2DelayCellTimex100 = 270/100 ps
5100 12:46:21.577506 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5101 12:46:21.580380 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5102 12:46:21.587180 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5103 12:46:21.590457 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5104 12:46:21.593675 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5105 12:46:21.597264 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5106 12:46:21.597346
5107 12:46:21.600427 CA PerBit enable=1, Macro0, CA PI delay=32
5108 12:46:21.600508
5109 12:46:21.603581 [CBTSetCACLKResult] CA Dly = 32
5110 12:46:21.607157 CS Dly: 6 (0~39)
5111 12:46:21.607239
5112 12:46:21.610587 ----->DramcWriteLeveling(PI) begin...
5113 12:46:21.610670 ==
5114 12:46:21.613735 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 12:46:21.616656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 12:46:21.616738 ==
5117 12:46:21.620215 Write leveling (Byte 0): 29 => 29
5118 12:46:21.623277 Write leveling (Byte 1): 28 => 28
5119 12:46:21.626393 DramcWriteLeveling(PI) end<-----
5120 12:46:21.626474
5121 12:46:21.626538 ==
5122 12:46:21.629988 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 12:46:21.633469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 12:46:21.633551 ==
5125 12:46:21.636530 [Gating] SW mode calibration
5126 12:46:21.643053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5127 12:46:21.649846 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5128 12:46:21.652962 0 14 0 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
5129 12:46:21.655913 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5130 12:46:21.662935 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 12:46:21.665966 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 12:46:21.669165 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 12:46:21.676796 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 12:46:21.679102 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 12:46:21.685774 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 1)
5136 12:46:21.688946 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5137 12:46:21.692203 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 12:46:21.699029 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 12:46:21.701917 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 12:46:21.705182 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 12:46:21.712047 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 12:46:21.715299 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
5143 12:46:21.718335 0 15 28 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
5144 12:46:21.724853 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5145 12:46:21.728340 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 12:46:21.732189 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 12:46:21.738499 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 12:46:21.741863 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 12:46:21.745344 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 12:46:21.751162 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5151 12:46:21.754611 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5152 12:46:21.757800 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5153 12:46:21.764803 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5154 12:46:21.767669 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:46:21.771446 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:46:21.777615 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:46:21.780811 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:46:21.784041 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:46:21.790863 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:46:21.794295 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:46:21.797626 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:46:21.803924 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:46:21.807343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:46:21.810669 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:46:21.817379 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:46:21.820486 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:46:21.824332 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5168 12:46:21.830545 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5169 12:46:21.830627 Total UI for P1: 0, mck2ui 16
5170 12:46:21.837323 best dqsien dly found for B0: ( 1, 2, 28)
5171 12:46:21.840743 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5172 12:46:21.844150 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 12:46:21.847312 Total UI for P1: 0, mck2ui 16
5174 12:46:21.850542 best dqsien dly found for B1: ( 1, 3, 0)
5175 12:46:21.853796 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5176 12:46:21.856853 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5177 12:46:21.856934
5178 12:46:21.860037 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5179 12:46:21.867053 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5180 12:46:21.867135 [Gating] SW calibration Done
5181 12:46:21.867200 ==
5182 12:46:21.870171 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 12:46:21.876568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 12:46:21.876651 ==
5185 12:46:21.876715 RX Vref Scan: 0
5186 12:46:21.876776
5187 12:46:21.879754 RX Vref 0 -> 0, step: 1
5188 12:46:21.879858
5189 12:46:21.883167 RX Delay -80 -> 252, step: 8
5190 12:46:21.886341 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5191 12:46:21.889892 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5192 12:46:21.892822 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5193 12:46:21.899695 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5194 12:46:21.902768 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5195 12:46:21.906519 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5196 12:46:21.909310 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5197 12:46:21.912751 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5198 12:46:21.916269 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5199 12:46:21.922864 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5200 12:46:21.926140 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5201 12:46:21.928985 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5202 12:46:21.932306 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5203 12:46:21.935663 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5204 12:46:21.942219 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5205 12:46:21.945906 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5206 12:46:21.945999 ==
5207 12:46:21.948627 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 12:46:21.952266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 12:46:21.952347 ==
5210 12:46:21.955508 DQS Delay:
5211 12:46:21.955587 DQS0 = 0, DQS1 = 0
5212 12:46:21.955650 DQM Delay:
5213 12:46:21.958571 DQM0 = 99, DQM1 = 88
5214 12:46:21.958650 DQ Delay:
5215 12:46:21.962654 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5216 12:46:21.965025 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5217 12:46:21.968763 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5218 12:46:21.971564 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5219 12:46:21.971644
5220 12:46:21.971706
5221 12:46:21.974979 ==
5222 12:46:21.975059 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 12:46:21.981811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 12:46:21.981892 ==
5225 12:46:21.981993
5226 12:46:21.982074
5227 12:46:21.985046 TX Vref Scan disable
5228 12:46:21.985125 == TX Byte 0 ==
5229 12:46:21.988251 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5230 12:46:21.994570 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5231 12:46:21.994650 == TX Byte 1 ==
5232 12:46:22.001211 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5233 12:46:22.004297 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5234 12:46:22.004377 ==
5235 12:46:22.007934 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 12:46:22.011477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 12:46:22.011556 ==
5238 12:46:22.011661
5239 12:46:22.011744
5240 12:46:22.014287 TX Vref Scan disable
5241 12:46:22.017897 == TX Byte 0 ==
5242 12:46:22.021238 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5243 12:46:22.024277 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5244 12:46:22.027744 == TX Byte 1 ==
5245 12:46:22.030994 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5246 12:46:22.034625 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5247 12:46:22.034705
5248 12:46:22.037110 [DATLAT]
5249 12:46:22.037190 Freq=933, CH0 RK0
5250 12:46:22.037253
5251 12:46:22.040823 DATLAT Default: 0xd
5252 12:46:22.040903 0, 0xFFFF, sum = 0
5253 12:46:22.043947 1, 0xFFFF, sum = 0
5254 12:46:22.044029 2, 0xFFFF, sum = 0
5255 12:46:22.047098 3, 0xFFFF, sum = 0
5256 12:46:22.047181 4, 0xFFFF, sum = 0
5257 12:46:22.050018 5, 0xFFFF, sum = 0
5258 12:46:22.050100 6, 0xFFFF, sum = 0
5259 12:46:22.053876 7, 0xFFFF, sum = 0
5260 12:46:22.057668 8, 0xFFFF, sum = 0
5261 12:46:22.057751 9, 0xFFFF, sum = 0
5262 12:46:22.060104 10, 0x0, sum = 1
5263 12:46:22.060187 11, 0x0, sum = 2
5264 12:46:22.060253 12, 0x0, sum = 3
5265 12:46:22.063648 13, 0x0, sum = 4
5266 12:46:22.063730 best_step = 11
5267 12:46:22.063794
5268 12:46:22.066847 ==
5269 12:46:22.066929 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 12:46:22.073515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 12:46:22.073622 ==
5272 12:46:22.073715 RX Vref Scan: 1
5273 12:46:22.073805
5274 12:46:22.076777 RX Vref 0 -> 0, step: 1
5275 12:46:22.076859
5276 12:46:22.079779 RX Delay -61 -> 252, step: 4
5277 12:46:22.079861
5278 12:46:22.083639 Set Vref, RX VrefLevel [Byte0]: 52
5279 12:46:22.087127 [Byte1]: 59
5280 12:46:22.087208
5281 12:46:22.090270 Final RX Vref Byte 0 = 52 to rank0
5282 12:46:22.093242 Final RX Vref Byte 1 = 59 to rank0
5283 12:46:22.096914 Final RX Vref Byte 0 = 52 to rank1
5284 12:46:22.100126 Final RX Vref Byte 1 = 59 to rank1==
5285 12:46:22.103487 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 12:46:22.106602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 12:46:22.109419 ==
5288 12:46:22.109501 DQS Delay:
5289 12:46:22.109565 DQS0 = 0, DQS1 = 0
5290 12:46:22.113693 DQM Delay:
5291 12:46:22.113773 DQM0 = 99, DQM1 = 87
5292 12:46:22.116857 DQ Delay:
5293 12:46:22.116939 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5294 12:46:22.122952 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5295 12:46:22.126250 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5296 12:46:22.129624 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5297 12:46:22.129705
5298 12:46:22.129769
5299 12:46:22.136406 [DQSOSCAuto] RK0, (LSB)MR18= 0x1913, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5300 12:46:22.139752 CH0 RK0: MR19=505, MR18=1913
5301 12:46:22.145648 CH0_RK0: MR19=0x505, MR18=0x1913, DQSOSC=413, MR23=63, INC=63, DEC=42
5302 12:46:22.145730
5303 12:46:22.149314 ----->DramcWriteLeveling(PI) begin...
5304 12:46:22.149397 ==
5305 12:46:22.152804 Dram Type= 6, Freq= 0, CH_0, rank 1
5306 12:46:22.155908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 12:46:22.156015 ==
5308 12:46:22.159404 Write leveling (Byte 0): 30 => 30
5309 12:46:22.162387 Write leveling (Byte 1): 26 => 26
5310 12:46:22.166462 DramcWriteLeveling(PI) end<-----
5311 12:46:22.166543
5312 12:46:22.166608 ==
5313 12:46:22.169961 Dram Type= 6, Freq= 0, CH_0, rank 1
5314 12:46:22.172222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 12:46:22.175779 ==
5316 12:46:22.175860 [Gating] SW mode calibration
5317 12:46:22.185765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5318 12:46:22.188835 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5319 12:46:22.191730 0 14 0 | B1->B0 | 2828 3333 | 1 1 | (1 1) (1 1)
5320 12:46:22.198798 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5321 12:46:22.202052 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 12:46:22.205301 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 12:46:22.211577 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 12:46:22.215254 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 12:46:22.218512 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5326 12:46:22.225135 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5327 12:46:22.228307 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5328 12:46:22.231469 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5329 12:46:22.238232 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 12:46:22.241666 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 12:46:22.245040 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 12:46:22.251504 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 12:46:22.255050 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5334 12:46:22.257932 0 15 28 | B1->B0 | 2727 3b3b | 1 0 | (0 0) (0 0)
5335 12:46:22.264707 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5336 12:46:22.268136 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 12:46:22.271484 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 12:46:22.277879 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 12:46:22.281378 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 12:46:22.284757 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 12:46:22.291477 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5342 12:46:22.294561 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5343 12:46:22.298078 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:46:22.304499 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:46:22.308018 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:46:22.310930 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 12:46:22.317621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 12:46:22.320615 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 12:46:22.324079 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 12:46:22.330633 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 12:46:22.334255 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:46:22.337524 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:46:22.343407 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:46:22.346991 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:46:22.350406 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:46:22.357018 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:46:22.360153 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5358 12:46:22.363361 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5359 12:46:22.366676 Total UI for P1: 0, mck2ui 16
5360 12:46:22.370460 best dqsien dly found for B0: ( 1, 2, 24)
5361 12:46:22.376549 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 12:46:22.379878 Total UI for P1: 0, mck2ui 16
5363 12:46:22.383563 best dqsien dly found for B1: ( 1, 2, 28)
5364 12:46:22.386633 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5365 12:46:22.390229 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5366 12:46:22.390644
5367 12:46:22.392595 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5368 12:46:22.396314 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5369 12:46:22.399991 [Gating] SW calibration Done
5370 12:46:22.400442 ==
5371 12:46:22.402601 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 12:46:22.406012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 12:46:22.406435 ==
5374 12:46:22.409587 RX Vref Scan: 0
5375 12:46:22.410006
5376 12:46:22.412631 RX Vref 0 -> 0, step: 1
5377 12:46:22.413347
5378 12:46:22.413979 RX Delay -80 -> 252, step: 8
5379 12:46:22.419572 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5380 12:46:22.422850 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5381 12:46:22.426523 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5382 12:46:22.429508 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5383 12:46:22.432747 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5384 12:46:22.435719 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5385 12:46:22.443027 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5386 12:46:22.445945 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5387 12:46:22.449567 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5388 12:46:22.452612 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5389 12:46:22.455984 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5390 12:46:22.462384 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5391 12:46:22.465701 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5392 12:46:22.468715 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5393 12:46:22.471986 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5394 12:46:22.475475 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5395 12:46:22.475934 ==
5396 12:46:22.478800 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 12:46:22.485154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 12:46:22.485570 ==
5399 12:46:22.485898 DQS Delay:
5400 12:46:22.488780 DQS0 = 0, DQS1 = 0
5401 12:46:22.489192 DQM Delay:
5402 12:46:22.489517 DQM0 = 98, DQM1 = 90
5403 12:46:22.491878 DQ Delay:
5404 12:46:22.496307 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5405 12:46:22.498466 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5406 12:46:22.502022 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5407 12:46:22.505959 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5408 12:46:22.506372
5409 12:46:22.506697
5410 12:46:22.506999 ==
5411 12:46:22.508189 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 12:46:22.511372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 12:46:22.511789 ==
5414 12:46:22.512163
5415 12:46:22.512475
5416 12:46:22.514956 TX Vref Scan disable
5417 12:46:22.518065 == TX Byte 0 ==
5418 12:46:22.521275 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5419 12:46:22.524755 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5420 12:46:22.528085 == TX Byte 1 ==
5421 12:46:22.531102 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5422 12:46:22.534549 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5423 12:46:22.534971 ==
5424 12:46:22.537802 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 12:46:22.545096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 12:46:22.545519 ==
5427 12:46:22.545942
5428 12:46:22.546423
5429 12:46:22.546751 TX Vref Scan disable
5430 12:46:22.548605 == TX Byte 0 ==
5431 12:46:22.552082 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5432 12:46:22.558488 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5433 12:46:22.558909 == TX Byte 1 ==
5434 12:46:22.561441 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5435 12:46:22.568424 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5436 12:46:22.568845
5437 12:46:22.569177 [DATLAT]
5438 12:46:22.569486 Freq=933, CH0 RK1
5439 12:46:22.569787
5440 12:46:22.571698 DATLAT Default: 0xb
5441 12:46:22.574917 0, 0xFFFF, sum = 0
5442 12:46:22.575344 1, 0xFFFF, sum = 0
5443 12:46:22.578640 2, 0xFFFF, sum = 0
5444 12:46:22.579064 3, 0xFFFF, sum = 0
5445 12:46:22.581399 4, 0xFFFF, sum = 0
5446 12:46:22.581825 5, 0xFFFF, sum = 0
5447 12:46:22.584554 6, 0xFFFF, sum = 0
5448 12:46:22.585130 7, 0xFFFF, sum = 0
5449 12:46:22.588066 8, 0xFFFF, sum = 0
5450 12:46:22.588492 9, 0xFFFF, sum = 0
5451 12:46:22.591056 10, 0x0, sum = 1
5452 12:46:22.591480 11, 0x0, sum = 2
5453 12:46:22.594493 12, 0x0, sum = 3
5454 12:46:22.595026 13, 0x0, sum = 4
5455 12:46:22.597832 best_step = 11
5456 12:46:22.598328
5457 12:46:22.598781 ==
5458 12:46:22.601227 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 12:46:22.604355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 12:46:22.604776 ==
5461 12:46:22.605108 RX Vref Scan: 0
5462 12:46:22.608128
5463 12:46:22.608546 RX Vref 0 -> 0, step: 1
5464 12:46:22.608884
5465 12:46:22.610958 RX Delay -53 -> 252, step: 4
5466 12:46:22.617723 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5467 12:46:22.621371 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5468 12:46:22.624405 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5469 12:46:22.627441 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5470 12:46:22.630536 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5471 12:46:22.634344 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5472 12:46:22.640699 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5473 12:46:22.644011 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5474 12:46:22.647107 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5475 12:46:22.650490 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5476 12:46:22.653912 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5477 12:46:22.660700 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5478 12:46:22.663671 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5479 12:46:22.666728 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5480 12:46:22.670314 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5481 12:46:22.673491 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5482 12:46:22.674012 ==
5483 12:46:22.677156 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 12:46:22.683359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 12:46:22.683814 ==
5486 12:46:22.684209 DQS Delay:
5487 12:46:22.686735 DQS0 = 0, DQS1 = 0
5488 12:46:22.687195 DQM Delay:
5489 12:46:22.690107 DQM0 = 97, DQM1 = 88
5490 12:46:22.690526 DQ Delay:
5491 12:46:22.693382 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =96
5492 12:46:22.696177 DQ4 =102, DQ5 =86, DQ6 =106, DQ7 =104
5493 12:46:22.699836 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5494 12:46:22.702785 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =94
5495 12:46:22.703205
5496 12:46:22.703539
5497 12:46:22.709545 [DQSOSCAuto] RK1, (LSB)MR18= 0x100e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5498 12:46:22.712819 CH0 RK1: MR19=505, MR18=100E
5499 12:46:22.719367 CH0_RK1: MR19=0x505, MR18=0x100E, DQSOSC=416, MR23=63, INC=62, DEC=41
5500 12:46:22.723033 [RxdqsGatingPostProcess] freq 933
5501 12:46:22.729716 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5502 12:46:22.732526 best DQS0 dly(2T, 0.5T) = (0, 10)
5503 12:46:22.732624 best DQS1 dly(2T, 0.5T) = (0, 11)
5504 12:46:22.735887 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5505 12:46:22.739197 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5506 12:46:22.742238 best DQS0 dly(2T, 0.5T) = (0, 10)
5507 12:46:22.745690 best DQS1 dly(2T, 0.5T) = (0, 10)
5508 12:46:22.749408 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5509 12:46:22.752272 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5510 12:46:22.755576 Pre-setting of DQS Precalculation
5511 12:46:22.762325 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5512 12:46:22.762410 ==
5513 12:46:22.765689 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 12:46:22.768782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 12:46:22.768864 ==
5516 12:46:22.775021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 12:46:22.781945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5518 12:46:22.784898 [CA 0] Center 36 (6~67) winsize 62
5519 12:46:22.788200 [CA 1] Center 36 (6~67) winsize 62
5520 12:46:22.792199 [CA 2] Center 34 (4~65) winsize 62
5521 12:46:22.794835 [CA 3] Center 34 (4~64) winsize 61
5522 12:46:22.798282 [CA 4] Center 34 (4~65) winsize 62
5523 12:46:22.801775 [CA 5] Center 33 (3~64) winsize 62
5524 12:46:22.801847
5525 12:46:22.804783 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5526 12:46:22.804860
5527 12:46:22.808101 [CATrainingPosCal] consider 1 rank data
5528 12:46:22.811185 u2DelayCellTimex100 = 270/100 ps
5529 12:46:22.814824 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 12:46:22.817721 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5531 12:46:22.821247 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5532 12:46:22.824952 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 12:46:22.827942 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5534 12:46:22.831480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 12:46:22.831557
5536 12:46:22.837520 CA PerBit enable=1, Macro0, CA PI delay=33
5537 12:46:22.837602
5538 12:46:22.840815 [CBTSetCACLKResult] CA Dly = 33
5539 12:46:22.840898 CS Dly: 5 (0~36)
5540 12:46:22.840963 ==
5541 12:46:22.844229 Dram Type= 6, Freq= 0, CH_1, rank 1
5542 12:46:22.847408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 12:46:22.847489 ==
5544 12:46:22.854439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5545 12:46:22.860881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5546 12:46:22.864254 [CA 0] Center 36 (6~67) winsize 62
5547 12:46:22.867044 [CA 1] Center 36 (6~67) winsize 62
5548 12:46:22.870843 [CA 2] Center 34 (4~65) winsize 62
5549 12:46:22.873835 [CA 3] Center 33 (3~64) winsize 62
5550 12:46:22.877283 [CA 4] Center 34 (4~64) winsize 61
5551 12:46:22.880397 [CA 5] Center 33 (3~64) winsize 62
5552 12:46:22.880470
5553 12:46:22.883928 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5554 12:46:22.884000
5555 12:46:22.887164 [CATrainingPosCal] consider 2 rank data
5556 12:46:22.890645 u2DelayCellTimex100 = 270/100 ps
5557 12:46:22.894000 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5558 12:46:22.897132 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 12:46:22.900249 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5560 12:46:22.903791 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 12:46:22.910373 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5562 12:46:22.913805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5563 12:46:22.913888
5564 12:46:22.916485 CA PerBit enable=1, Macro0, CA PI delay=33
5565 12:46:22.916566
5566 12:46:22.919974 [CBTSetCACLKResult] CA Dly = 33
5567 12:46:22.920078 CS Dly: 6 (0~38)
5568 12:46:22.920143
5569 12:46:22.923553 ----->DramcWriteLeveling(PI) begin...
5570 12:46:22.923636 ==
5571 12:46:22.926408 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 12:46:22.933200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 12:46:22.933282 ==
5574 12:46:22.936402 Write leveling (Byte 0): 27 => 27
5575 12:46:22.939595 Write leveling (Byte 1): 27 => 27
5576 12:46:22.942689 DramcWriteLeveling(PI) end<-----
5577 12:46:22.942795
5578 12:46:22.942887 ==
5579 12:46:22.946313 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 12:46:22.949614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 12:46:22.949726 ==
5582 12:46:22.952498 [Gating] SW mode calibration
5583 12:46:22.959123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5584 12:46:22.965828 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5585 12:46:22.968943 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 12:46:22.972483 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 12:46:22.979386 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 12:46:22.982355 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 12:46:22.985657 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 12:46:22.991982 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 12:46:22.995346 0 14 24 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
5592 12:46:22.998404 0 14 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5593 12:46:23.004997 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5594 12:46:23.008937 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 12:46:23.011708 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 12:46:23.018190 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 12:46:23.021787 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 12:46:23.025107 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 12:46:23.031762 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5600 12:46:23.035761 0 15 28 | B1->B0 | 3535 3e3e | 0 0 | (0 0) (0 0)
5601 12:46:23.038158 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 12:46:23.044592 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 12:46:23.047878 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 12:46:23.051377 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 12:46:23.058251 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 12:46:23.061176 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 12:46:23.064767 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 12:46:23.071271 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 12:46:23.074582 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5610 12:46:23.078004 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:46:23.084340 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:46:23.087741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 12:46:23.090905 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 12:46:23.097540 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 12:46:23.101082 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:46:23.103983 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:46:23.110413 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:46:23.114168 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:46:23.117002 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:46:23.124208 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:46:23.127075 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:46:23.130172 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:46:23.137003 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:46:23.139861 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 12:46:23.144021 Total UI for P1: 0, mck2ui 16
5626 12:46:23.146644 best dqsien dly found for B0: ( 1, 2, 26)
5627 12:46:23.149838 Total UI for P1: 0, mck2ui 16
5628 12:46:23.153119 best dqsien dly found for B1: ( 1, 2, 26)
5629 12:46:23.156796 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5630 12:46:23.159970 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5631 12:46:23.160088
5632 12:46:23.162792 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5633 12:46:23.169868 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5634 12:46:23.169951 [Gating] SW calibration Done
5635 12:46:23.170016 ==
5636 12:46:23.173214 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 12:46:23.179500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 12:46:23.179595 ==
5639 12:46:23.179661 RX Vref Scan: 0
5640 12:46:23.179722
5641 12:46:23.183048 RX Vref 0 -> 0, step: 1
5642 12:46:23.183131
5643 12:46:23.186091 RX Delay -80 -> 252, step: 8
5644 12:46:23.189732 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5645 12:46:23.193026 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5646 12:46:23.195789 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5647 12:46:23.199328 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5648 12:46:23.205731 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5649 12:46:23.209544 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5650 12:46:23.212659 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5651 12:46:23.216316 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5652 12:46:23.219119 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5653 12:46:23.225384 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5654 12:46:23.228947 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5655 12:46:23.231964 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5656 12:46:23.235506 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5657 12:46:23.238840 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5658 12:46:23.245576 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5659 12:46:23.248485 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5660 12:46:23.248566 ==
5661 12:46:23.251787 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 12:46:23.255129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 12:46:23.255211 ==
5664 12:46:23.255276 DQS Delay:
5665 12:46:23.258162 DQS0 = 0, DQS1 = 0
5666 12:46:23.258244 DQM Delay:
5667 12:46:23.261587 DQM0 = 99, DQM1 = 95
5668 12:46:23.261668 DQ Delay:
5669 12:46:23.265162 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5670 12:46:23.268181 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5671 12:46:23.271850 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5672 12:46:23.275202 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5673 12:46:23.275284
5674 12:46:23.275348
5675 12:46:23.278061 ==
5676 12:46:23.278142 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 12:46:23.284951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 12:46:23.285033 ==
5679 12:46:23.285098
5680 12:46:23.285156
5681 12:46:23.287984 TX Vref Scan disable
5682 12:46:23.288077 == TX Byte 0 ==
5683 12:46:23.291187 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5684 12:46:23.298028 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5685 12:46:23.298109 == TX Byte 1 ==
5686 12:46:23.304511 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5687 12:46:23.307876 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5688 12:46:23.307983 ==
5689 12:46:23.311196 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 12:46:23.314602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 12:46:23.314684 ==
5692 12:46:23.314748
5693 12:46:23.314806
5694 12:46:23.318016 TX Vref Scan disable
5695 12:46:23.321238 == TX Byte 0 ==
5696 12:46:23.324918 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5697 12:46:23.327218 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5698 12:46:23.330640 == TX Byte 1 ==
5699 12:46:23.333880 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5700 12:46:23.338248 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5701 12:46:23.338355
5702 12:46:23.340665 [DATLAT]
5703 12:46:23.340748 Freq=933, CH1 RK0
5704 12:46:23.340830
5705 12:46:23.343967 DATLAT Default: 0xd
5706 12:46:23.344106 0, 0xFFFF, sum = 0
5707 12:46:23.347398 1, 0xFFFF, sum = 0
5708 12:46:23.347500 2, 0xFFFF, sum = 0
5709 12:46:23.350507 3, 0xFFFF, sum = 0
5710 12:46:23.350611 4, 0xFFFF, sum = 0
5711 12:46:23.353379 5, 0xFFFF, sum = 0
5712 12:46:23.353477 6, 0xFFFF, sum = 0
5713 12:46:23.356903 7, 0xFFFF, sum = 0
5714 12:46:23.356981 8, 0xFFFF, sum = 0
5715 12:46:23.360300 9, 0xFFFF, sum = 0
5716 12:46:23.360371 10, 0x0, sum = 1
5717 12:46:23.363742 11, 0x0, sum = 2
5718 12:46:23.363840 12, 0x0, sum = 3
5719 12:46:23.367687 13, 0x0, sum = 4
5720 12:46:23.367783 best_step = 11
5721 12:46:23.367870
5722 12:46:23.367955 ==
5723 12:46:23.370482 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 12:46:23.377380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 12:46:23.377452 ==
5726 12:46:23.377513 RX Vref Scan: 1
5727 12:46:23.377571
5728 12:46:23.380020 RX Vref 0 -> 0, step: 1
5729 12:46:23.380120
5730 12:46:23.383134 RX Delay -53 -> 252, step: 4
5731 12:46:23.383230
5732 12:46:23.386507 Set Vref, RX VrefLevel [Byte0]: 52
5733 12:46:23.390325 [Byte1]: 48
5734 12:46:23.390395
5735 12:46:23.393265 Final RX Vref Byte 0 = 52 to rank0
5736 12:46:23.396444 Final RX Vref Byte 1 = 48 to rank0
5737 12:46:23.399982 Final RX Vref Byte 0 = 52 to rank1
5738 12:46:23.402877 Final RX Vref Byte 1 = 48 to rank1==
5739 12:46:23.406331 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 12:46:23.409691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 12:46:23.413030 ==
5742 12:46:23.413103 DQS Delay:
5743 12:46:23.413165 DQS0 = 0, DQS1 = 0
5744 12:46:23.416352 DQM Delay:
5745 12:46:23.416422 DQM0 = 98, DQM1 = 93
5746 12:46:23.419616 DQ Delay:
5747 12:46:23.423037 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =100
5748 12:46:23.426202 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5749 12:46:23.429129 DQ8 =78, DQ9 =84, DQ10 =94, DQ11 =86
5750 12:46:23.432696 DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =100
5751 12:46:23.432771
5752 12:46:23.432852
5753 12:46:23.439777 [DQSOSCAuto] RK0, (LSB)MR18= 0x716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5754 12:46:23.443378 CH1 RK0: MR19=505, MR18=716
5755 12:46:23.449558 CH1_RK0: MR19=0x505, MR18=0x716, DQSOSC=414, MR23=63, INC=63, DEC=42
5756 12:46:23.449663
5757 12:46:23.452557 ----->DramcWriteLeveling(PI) begin...
5758 12:46:23.452658 ==
5759 12:46:23.455911 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 12:46:23.459375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 12:46:23.459445 ==
5762 12:46:23.461949 Write leveling (Byte 0): 28 => 28
5763 12:46:23.465956 Write leveling (Byte 1): 29 => 29
5764 12:46:23.468462 DramcWriteLeveling(PI) end<-----
5765 12:46:23.468530
5766 12:46:23.468596 ==
5767 12:46:23.471921 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 12:46:23.475420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 12:46:23.478816 ==
5770 12:46:23.478913 [Gating] SW mode calibration
5771 12:46:23.488131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5772 12:46:23.491894 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5773 12:46:23.495702 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 12:46:23.502149 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 12:46:23.504924 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 12:46:23.508128 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 12:46:23.514953 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 12:46:23.517968 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 12:46:23.521649 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5780 12:46:23.528194 0 14 28 | B1->B0 | 2727 2323 | 1 0 | (1 1) (1 0)
5781 12:46:23.531292 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5782 12:46:23.534912 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 12:46:23.541076 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 12:46:23.544420 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 12:46:23.547976 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 12:46:23.554229 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 12:46:23.557456 0 15 24 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
5788 12:46:23.561319 0 15 28 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
5789 12:46:23.567810 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 12:46:23.571017 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 12:46:23.574230 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 12:46:23.580737 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 12:46:23.584262 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 12:46:23.587183 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 12:46:23.594108 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5796 12:46:23.597631 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5797 12:46:23.600409 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:46:23.606856 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:46:23.610507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 12:46:23.613768 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 12:46:23.620217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 12:46:23.623394 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 12:46:23.626945 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 12:46:23.633592 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 12:46:23.636741 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:46:23.640210 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 12:46:23.646768 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:46:23.649461 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:46:23.656212 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:46:23.659509 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:46:23.662797 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5812 12:46:23.669134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5813 12:46:23.669215 Total UI for P1: 0, mck2ui 16
5814 12:46:23.672493 best dqsien dly found for B0: ( 1, 2, 24)
5815 12:46:23.679360 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 12:46:23.682425 Total UI for P1: 0, mck2ui 16
5817 12:46:23.686132 best dqsien dly found for B1: ( 1, 2, 28)
5818 12:46:23.689053 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5819 12:46:23.692238 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5820 12:46:23.692318
5821 12:46:23.695851 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5822 12:46:23.698903 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5823 12:46:23.702746 [Gating] SW calibration Done
5824 12:46:23.702827 ==
5825 12:46:23.705478 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 12:46:23.709036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 12:46:23.712313 ==
5828 12:46:23.712393 RX Vref Scan: 0
5829 12:46:23.712456
5830 12:46:23.715496 RX Vref 0 -> 0, step: 1
5831 12:46:23.715576
5832 12:46:23.718605 RX Delay -80 -> 252, step: 8
5833 12:46:23.722264 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5834 12:46:23.725465 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5835 12:46:23.728391 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5836 12:46:23.731734 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5837 12:46:23.734964 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5838 12:46:23.741715 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5839 12:46:23.745529 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5840 12:46:23.748412 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5841 12:46:23.752179 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5842 12:46:23.754566 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5843 12:46:23.758586 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5844 12:46:23.764534 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5845 12:46:23.768377 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5846 12:46:23.771250 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5847 12:46:23.774566 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5848 12:46:23.778063 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5849 12:46:23.781068 ==
5850 12:46:23.784253 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 12:46:23.787734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 12:46:23.787813 ==
5853 12:46:23.787915 DQS Delay:
5854 12:46:23.791044 DQS0 = 0, DQS1 = 0
5855 12:46:23.791148 DQM Delay:
5856 12:46:23.793967 DQM0 = 97, DQM1 = 94
5857 12:46:23.794043 DQ Delay:
5858 12:46:23.797623 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5859 12:46:23.800743 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5860 12:46:23.804102 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5861 12:46:23.807406 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5862 12:46:23.807481
5863 12:46:23.807561
5864 12:46:23.807638 ==
5865 12:46:23.810463 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 12:46:23.813751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 12:46:23.817485 ==
5868 12:46:23.817563
5869 12:46:23.817645
5870 12:46:23.817722 TX Vref Scan disable
5871 12:46:23.820302 == TX Byte 0 ==
5872 12:46:23.823983 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5873 12:46:23.827022 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5874 12:46:23.830166 == TX Byte 1 ==
5875 12:46:23.833701 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5876 12:46:23.836772 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5877 12:46:23.840616 ==
5878 12:46:23.843491 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 12:46:23.847244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 12:46:23.847326 ==
5881 12:46:23.847410
5882 12:46:23.847486
5883 12:46:23.849954 TX Vref Scan disable
5884 12:46:23.850032 == TX Byte 0 ==
5885 12:46:23.856623 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5886 12:46:23.860390 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5887 12:46:23.860475 == TX Byte 1 ==
5888 12:46:23.866438 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5889 12:46:23.869936 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5890 12:46:23.870016
5891 12:46:23.870099 [DATLAT]
5892 12:46:23.873296 Freq=933, CH1 RK1
5893 12:46:23.873370
5894 12:46:23.873448 DATLAT Default: 0xb
5895 12:46:23.876687 0, 0xFFFF, sum = 0
5896 12:46:23.876761 1, 0xFFFF, sum = 0
5897 12:46:23.880205 2, 0xFFFF, sum = 0
5898 12:46:23.880282 3, 0xFFFF, sum = 0
5899 12:46:23.882958 4, 0xFFFF, sum = 0
5900 12:46:23.886536 5, 0xFFFF, sum = 0
5901 12:46:23.886612 6, 0xFFFF, sum = 0
5902 12:46:23.889551 7, 0xFFFF, sum = 0
5903 12:46:23.889629 8, 0xFFFF, sum = 0
5904 12:46:23.893046 9, 0xFFFF, sum = 0
5905 12:46:23.893128 10, 0x0, sum = 1
5906 12:46:23.896283 11, 0x0, sum = 2
5907 12:46:23.896360 12, 0x0, sum = 3
5908 12:46:23.900105 13, 0x0, sum = 4
5909 12:46:23.900182 best_step = 11
5910 12:46:23.900262
5911 12:46:23.900338 ==
5912 12:46:23.902917 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 12:46:23.906002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 12:46:23.906075 ==
5915 12:46:23.909640 RX Vref Scan: 0
5916 12:46:23.909715
5917 12:46:23.912576 RX Vref 0 -> 0, step: 1
5918 12:46:23.912658
5919 12:46:23.912733 RX Delay -53 -> 252, step: 4
5920 12:46:23.920711 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5921 12:46:23.924195 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5922 12:46:23.927234 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5923 12:46:23.930044 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5924 12:46:23.933865 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5925 12:46:23.940154 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5926 12:46:23.943847 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5927 12:46:23.946506 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5928 12:46:23.950077 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5929 12:46:23.953391 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5930 12:46:23.959968 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5931 12:46:23.963258 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5932 12:46:23.966619 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5933 12:46:23.969866 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5934 12:46:23.973174 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5935 12:46:23.979895 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5936 12:46:23.979975 ==
5937 12:46:23.982846 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 12:46:23.985971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 12:46:23.986051 ==
5940 12:46:23.986114 DQS Delay:
5941 12:46:23.989617 DQS0 = 0, DQS1 = 0
5942 12:46:23.989697 DQM Delay:
5943 12:46:23.992529 DQM0 = 97, DQM1 = 91
5944 12:46:23.992608 DQ Delay:
5945 12:46:23.996199 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5946 12:46:23.999448 DQ4 =96, DQ5 =106, DQ6 =106, DQ7 =94
5947 12:46:24.003406 DQ8 =78, DQ9 =80, DQ10 =90, DQ11 =84
5948 12:46:24.006405 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
5949 12:46:24.006485
5950 12:46:24.006549
5951 12:46:24.016001 [DQSOSCAuto] RK1, (LSB)MR18= 0x820, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 419 ps
5952 12:46:24.016102 CH1 RK1: MR19=505, MR18=820
5953 12:46:24.022608 CH1_RK1: MR19=0x505, MR18=0x820, DQSOSC=411, MR23=63, INC=64, DEC=42
5954 12:46:24.025572 [RxdqsGatingPostProcess] freq 933
5955 12:46:24.032349 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5956 12:46:24.035710 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 12:46:24.038982 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 12:46:24.042542 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 12:46:24.045664 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 12:46:24.049198 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 12:46:24.052417 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 12:46:24.055528 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 12:46:24.058708 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 12:46:24.058790 Pre-setting of DQS Precalculation
5965 12:46:24.065506 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5966 12:46:24.071806 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5967 12:46:24.078479 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5968 12:46:24.078561
5969 12:46:24.078625
5970 12:46:24.081955 [Calibration Summary] 1866 Mbps
5971 12:46:24.085093 CH 0, Rank 0
5972 12:46:24.085174 SW Impedance : PASS
5973 12:46:24.088498 DUTY Scan : NO K
5974 12:46:24.091746 ZQ Calibration : PASS
5975 12:46:24.091836 Jitter Meter : NO K
5976 12:46:24.094882 CBT Training : PASS
5977 12:46:24.098435 Write leveling : PASS
5978 12:46:24.098517 RX DQS gating : PASS
5979 12:46:24.101916 RX DQ/DQS(RDDQC) : PASS
5980 12:46:24.104897 TX DQ/DQS : PASS
5981 12:46:24.104979 RX DATLAT : PASS
5982 12:46:24.108361 RX DQ/DQS(Engine): PASS
5983 12:46:24.111564 TX OE : NO K
5984 12:46:24.111646 All Pass.
5985 12:46:24.111710
5986 12:46:24.111768 CH 0, Rank 1
5987 12:46:24.114578 SW Impedance : PASS
5988 12:46:24.117982 DUTY Scan : NO K
5989 12:46:24.118062 ZQ Calibration : PASS
5990 12:46:24.121354 Jitter Meter : NO K
5991 12:46:24.124389 CBT Training : PASS
5992 12:46:24.124469 Write leveling : PASS
5993 12:46:24.127629 RX DQS gating : PASS
5994 12:46:24.131028 RX DQ/DQS(RDDQC) : PASS
5995 12:46:24.131109 TX DQ/DQS : PASS
5996 12:46:24.134490 RX DATLAT : PASS
5997 12:46:24.134572 RX DQ/DQS(Engine): PASS
5998 12:46:24.139071 TX OE : NO K
5999 12:46:24.139153 All Pass.
6000 12:46:24.139217
6001 12:46:24.140684 CH 1, Rank 0
6002 12:46:24.140765 SW Impedance : PASS
6003 12:46:24.144555 DUTY Scan : NO K
6004 12:46:24.147683 ZQ Calibration : PASS
6005 12:46:24.147765 Jitter Meter : NO K
6006 12:46:24.150828 CBT Training : PASS
6007 12:46:24.153866 Write leveling : PASS
6008 12:46:24.153947 RX DQS gating : PASS
6009 12:46:24.157711 RX DQ/DQS(RDDQC) : PASS
6010 12:46:24.160643 TX DQ/DQS : PASS
6011 12:46:24.160724 RX DATLAT : PASS
6012 12:46:24.163937 RX DQ/DQS(Engine): PASS
6013 12:46:24.167707 TX OE : NO K
6014 12:46:24.167788 All Pass.
6015 12:46:24.167853
6016 12:46:24.167912 CH 1, Rank 1
6017 12:46:24.171019 SW Impedance : PASS
6018 12:46:24.173456 DUTY Scan : NO K
6019 12:46:24.173537 ZQ Calibration : PASS
6020 12:46:24.177636 Jitter Meter : NO K
6021 12:46:24.180149 CBT Training : PASS
6022 12:46:24.180229 Write leveling : PASS
6023 12:46:24.183999 RX DQS gating : PASS
6024 12:46:24.186911 RX DQ/DQS(RDDQC) : PASS
6025 12:46:24.186991 TX DQ/DQS : PASS
6026 12:46:24.190168 RX DATLAT : PASS
6027 12:46:24.193295 RX DQ/DQS(Engine): PASS
6028 12:46:24.193375 TX OE : NO K
6029 12:46:24.197348 All Pass.
6030 12:46:24.197428
6031 12:46:24.197491 DramC Write-DBI off
6032 12:46:24.200224 PER_BANK_REFRESH: Hybrid Mode
6033 12:46:24.200305 TX_TRACKING: ON
6034 12:46:24.210104 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6035 12:46:24.213188 [FAST_K] Save calibration result to emmc
6036 12:46:24.216446 dramc_set_vcore_voltage set vcore to 650000
6037 12:46:24.220002 Read voltage for 400, 6
6038 12:46:24.220118 Vio18 = 0
6039 12:46:24.222946 Vcore = 650000
6040 12:46:24.223026 Vdram = 0
6041 12:46:24.223090 Vddq = 0
6042 12:46:24.226531 Vmddr = 0
6043 12:46:24.229923 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6044 12:46:24.236453 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6045 12:46:24.236534 MEM_TYPE=3, freq_sel=20
6046 12:46:24.239924 sv_algorithm_assistance_LP4_800
6047 12:46:24.246026 ============ PULL DRAM RESETB DOWN ============
6048 12:46:24.249604 ========== PULL DRAM RESETB DOWN end =========
6049 12:46:24.253362 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6050 12:46:24.256962 ===================================
6051 12:46:24.259438 LPDDR4 DRAM CONFIGURATION
6052 12:46:24.263268 ===================================
6053 12:46:24.266305 EX_ROW_EN[0] = 0x0
6054 12:46:24.266386 EX_ROW_EN[1] = 0x0
6055 12:46:24.269162 LP4Y_EN = 0x0
6056 12:46:24.269242 WORK_FSP = 0x0
6057 12:46:24.272949 WL = 0x2
6058 12:46:24.273030 RL = 0x2
6059 12:46:24.275956 BL = 0x2
6060 12:46:24.276093 RPST = 0x0
6061 12:46:24.279370 RD_PRE = 0x0
6062 12:46:24.279450 WR_PRE = 0x1
6063 12:46:24.282422 WR_PST = 0x0
6064 12:46:24.282502 DBI_WR = 0x0
6065 12:46:24.285509 DBI_RD = 0x0
6066 12:46:24.285590 OTF = 0x1
6067 12:46:24.289040 ===================================
6068 12:46:24.292433 ===================================
6069 12:46:24.295299 ANA top config
6070 12:46:24.298766 ===================================
6071 12:46:24.301930 DLL_ASYNC_EN = 0
6072 12:46:24.302010 ALL_SLAVE_EN = 1
6073 12:46:24.305810 NEW_RANK_MODE = 1
6074 12:46:24.308750 DLL_IDLE_MODE = 1
6075 12:46:24.312176 LP45_APHY_COMB_EN = 1
6076 12:46:24.315593 TX_ODT_DIS = 1
6077 12:46:24.315673 NEW_8X_MODE = 1
6078 12:46:24.318952 ===================================
6079 12:46:24.322036 ===================================
6080 12:46:24.325274 data_rate = 800
6081 12:46:24.328307 CKR = 1
6082 12:46:24.331677 DQ_P2S_RATIO = 4
6083 12:46:24.335441 ===================================
6084 12:46:24.338604 CA_P2S_RATIO = 4
6085 12:46:24.341410 DQ_CA_OPEN = 0
6086 12:46:24.341490 DQ_SEMI_OPEN = 1
6087 12:46:24.344797 CA_SEMI_OPEN = 1
6088 12:46:24.348502 CA_FULL_RATE = 0
6089 12:46:24.351484 DQ_CKDIV4_EN = 0
6090 12:46:24.355113 CA_CKDIV4_EN = 1
6091 12:46:24.358276 CA_PREDIV_EN = 0
6092 12:46:24.358357 PH8_DLY = 0
6093 12:46:24.361699 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6094 12:46:24.364784 DQ_AAMCK_DIV = 0
6095 12:46:24.367877 CA_AAMCK_DIV = 0
6096 12:46:24.371087 CA_ADMCK_DIV = 4
6097 12:46:24.374716 DQ_TRACK_CA_EN = 0
6098 12:46:24.377834 CA_PICK = 800
6099 12:46:24.377914 CA_MCKIO = 400
6100 12:46:24.381030 MCKIO_SEMI = 400
6101 12:46:24.384413 PLL_FREQ = 3016
6102 12:46:24.387383 DQ_UI_PI_RATIO = 32
6103 12:46:24.391025 CA_UI_PI_RATIO = 32
6104 12:46:24.394123 ===================================
6105 12:46:24.397285 ===================================
6106 12:46:24.401294 memory_type:LPDDR4
6107 12:46:24.401375 GP_NUM : 10
6108 12:46:24.404192 SRAM_EN : 1
6109 12:46:24.407586 MD32_EN : 0
6110 12:46:24.410355 ===================================
6111 12:46:24.410437 [ANA_INIT] >>>>>>>>>>>>>>
6112 12:46:24.414016 <<<<<< [CONFIGURE PHASE]: ANA_TX
6113 12:46:24.417427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6114 12:46:24.420405 ===================================
6115 12:46:24.424232 data_rate = 800,PCW = 0X7400
6116 12:46:24.427033 ===================================
6117 12:46:24.430051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6118 12:46:24.436844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 12:46:24.446824 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 12:46:24.453632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6121 12:46:24.456914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6122 12:46:24.459670 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6123 12:46:24.459752 [ANA_INIT] flow start
6124 12:46:24.463414 [ANA_INIT] PLL >>>>>>>>
6125 12:46:24.466411 [ANA_INIT] PLL <<<<<<<<
6126 12:46:24.469874 [ANA_INIT] MIDPI >>>>>>>>
6127 12:46:24.469955 [ANA_INIT] MIDPI <<<<<<<<
6128 12:46:24.472830 [ANA_INIT] DLL >>>>>>>>
6129 12:46:24.476215 [ANA_INIT] flow end
6130 12:46:24.479722 ============ LP4 DIFF to SE enter ============
6131 12:46:24.482819 ============ LP4 DIFF to SE exit ============
6132 12:46:24.485875 [ANA_INIT] <<<<<<<<<<<<<
6133 12:46:24.489091 [Flow] Enable top DCM control >>>>>
6134 12:46:24.492280 [Flow] Enable top DCM control <<<<<
6135 12:46:24.496154 Enable DLL master slave shuffle
6136 12:46:24.499575 ==============================================================
6137 12:46:24.502396 Gating Mode config
6138 12:46:24.509013 ==============================================================
6139 12:46:24.509095 Config description:
6140 12:46:24.518624 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6141 12:46:24.525453 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6142 12:46:24.528701 SELPH_MODE 0: By rank 1: By Phase
6143 12:46:24.535013 ==============================================================
6144 12:46:24.538869 GAT_TRACK_EN = 0
6145 12:46:24.542558 RX_GATING_MODE = 2
6146 12:46:24.545222 RX_GATING_TRACK_MODE = 2
6147 12:46:24.548248 SELPH_MODE = 1
6148 12:46:24.551806 PICG_EARLY_EN = 1
6149 12:46:24.554934 VALID_LAT_VALUE = 1
6150 12:46:24.558430 ==============================================================
6151 12:46:24.561563 Enter into Gating configuration >>>>
6152 12:46:24.565134 Exit from Gating configuration <<<<
6153 12:46:24.568433 Enter into DVFS_PRE_config >>>>>
6154 12:46:24.581602 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6155 12:46:24.584611 Exit from DVFS_PRE_config <<<<<
6156 12:46:24.588414 Enter into PICG configuration >>>>
6157 12:46:24.588496 Exit from PICG configuration <<<<
6158 12:46:24.591246 [RX_INPUT] configuration >>>>>
6159 12:46:24.595035 [RX_INPUT] configuration <<<<<
6160 12:46:24.601686 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6161 12:46:24.604549 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6162 12:46:24.611184 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 12:46:24.618804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 12:46:24.624456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 12:46:24.631041 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 12:46:24.634392 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6167 12:46:24.637530 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6168 12:46:24.644284 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6169 12:46:24.647362 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6170 12:46:24.650521 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6171 12:46:24.657457 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 12:46:24.660176 ===================================
6173 12:46:24.660258 LPDDR4 DRAM CONFIGURATION
6174 12:46:24.663885 ===================================
6175 12:46:24.667028 EX_ROW_EN[0] = 0x0
6176 12:46:24.667109 EX_ROW_EN[1] = 0x0
6177 12:46:24.670326 LP4Y_EN = 0x0
6178 12:46:24.670408 WORK_FSP = 0x0
6179 12:46:24.673515 WL = 0x2
6180 12:46:24.676682 RL = 0x2
6181 12:46:24.676763 BL = 0x2
6182 12:46:24.680370 RPST = 0x0
6183 12:46:24.680477 RD_PRE = 0x0
6184 12:46:24.683630 WR_PRE = 0x1
6185 12:46:24.683711 WR_PST = 0x0
6186 12:46:24.686557 DBI_WR = 0x0
6187 12:46:24.686638 DBI_RD = 0x0
6188 12:46:24.689805 OTF = 0x1
6189 12:46:24.693442 ===================================
6190 12:46:24.696900 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6191 12:46:24.699994 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6192 12:46:24.706245 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6193 12:46:24.709718 ===================================
6194 12:46:24.709799 LPDDR4 DRAM CONFIGURATION
6195 12:46:24.713044 ===================================
6196 12:46:24.716312 EX_ROW_EN[0] = 0x10
6197 12:46:24.719648 EX_ROW_EN[1] = 0x0
6198 12:46:24.719729 LP4Y_EN = 0x0
6199 12:46:24.723025 WORK_FSP = 0x0
6200 12:46:24.723106 WL = 0x2
6201 12:46:24.726065 RL = 0x2
6202 12:46:24.726147 BL = 0x2
6203 12:46:24.729565 RPST = 0x0
6204 12:46:24.729646 RD_PRE = 0x0
6205 12:46:24.732677 WR_PRE = 0x1
6206 12:46:24.732758 WR_PST = 0x0
6207 12:46:24.735925 DBI_WR = 0x0
6208 12:46:24.736006 DBI_RD = 0x0
6209 12:46:24.739553 OTF = 0x1
6210 12:46:24.742789 ===================================
6211 12:46:24.749595 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6212 12:46:24.752465 nWR fixed to 30
6213 12:46:24.755416 [ModeRegInit_LP4] CH0 RK0
6214 12:46:24.755497 [ModeRegInit_LP4] CH0 RK1
6215 12:46:24.759443 [ModeRegInit_LP4] CH1 RK0
6216 12:46:24.762559 [ModeRegInit_LP4] CH1 RK1
6217 12:46:24.762640 match AC timing 19
6218 12:46:24.768616 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6219 12:46:24.771960 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6220 12:46:24.775866 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6221 12:46:24.781849 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6222 12:46:24.785633 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6223 12:46:24.785715 ==
6224 12:46:24.788853 Dram Type= 6, Freq= 0, CH_0, rank 0
6225 12:46:24.791975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 12:46:24.792093 ==
6227 12:46:24.799046 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 12:46:24.804959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6229 12:46:24.809000 [CA 0] Center 36 (8~64) winsize 57
6230 12:46:24.811616 [CA 1] Center 36 (8~64) winsize 57
6231 12:46:24.815089 [CA 2] Center 36 (8~64) winsize 57
6232 12:46:24.815170 [CA 3] Center 36 (8~64) winsize 57
6233 12:46:24.818468 [CA 4] Center 36 (8~64) winsize 57
6234 12:46:24.821634 [CA 5] Center 36 (8~64) winsize 57
6235 12:46:24.821715
6236 12:46:24.828475 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6237 12:46:24.828556
6238 12:46:24.831301 [CATrainingPosCal] consider 1 rank data
6239 12:46:24.834767 u2DelayCellTimex100 = 270/100 ps
6240 12:46:24.838040 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:46:24.841606 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 12:46:24.845015 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 12:46:24.848035 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:46:24.851868 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:46:24.854678 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:46:24.854759
6247 12:46:24.858769 CA PerBit enable=1, Macro0, CA PI delay=36
6248 12:46:24.858850
6249 12:46:24.861324 [CBTSetCACLKResult] CA Dly = 36
6250 12:46:24.864297 CS Dly: 1 (0~32)
6251 12:46:24.864379 ==
6252 12:46:24.867986 Dram Type= 6, Freq= 0, CH_0, rank 1
6253 12:46:24.870845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 12:46:24.870927 ==
6255 12:46:24.877875 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 12:46:24.884308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6257 12:46:24.887966 [CA 0] Center 36 (8~64) winsize 57
6258 12:46:24.888084 [CA 1] Center 36 (8~64) winsize 57
6259 12:46:24.891072 [CA 2] Center 36 (8~64) winsize 57
6260 12:46:24.894804 [CA 3] Center 36 (8~64) winsize 57
6261 12:46:24.897394 [CA 4] Center 36 (8~64) winsize 57
6262 12:46:24.901082 [CA 5] Center 36 (8~64) winsize 57
6263 12:46:24.901163
6264 12:46:24.904306 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6265 12:46:24.904387
6266 12:46:24.910815 [CATrainingPosCal] consider 2 rank data
6267 12:46:24.910896 u2DelayCellTimex100 = 270/100 ps
6268 12:46:24.917532 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:46:24.920438 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:46:24.923928 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 12:46:24.927141 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 12:46:24.930258 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 12:46:24.933671 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 12:46:24.933753
6275 12:46:24.937541 CA PerBit enable=1, Macro0, CA PI delay=36
6276 12:46:24.937623
6277 12:46:24.940316 [CBTSetCACLKResult] CA Dly = 36
6278 12:46:24.943383 CS Dly: 1 (0~32)
6279 12:46:24.943464
6280 12:46:24.947122 ----->DramcWriteLeveling(PI) begin...
6281 12:46:24.947205 ==
6282 12:46:24.950224 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 12:46:24.953661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 12:46:24.953743 ==
6285 12:46:24.956953 Write leveling (Byte 0): 40 => 8
6286 12:46:24.960017 Write leveling (Byte 1): 40 => 8
6287 12:46:24.963204 DramcWriteLeveling(PI) end<-----
6288 12:46:24.963285
6289 12:46:24.963349 ==
6290 12:46:24.967038 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 12:46:24.970194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 12:46:24.970276 ==
6293 12:46:24.973395 [Gating] SW mode calibration
6294 12:46:24.980409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6295 12:46:24.986303 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6296 12:46:24.990605 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 12:46:24.992962 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 12:46:24.999419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 12:46:25.003205 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 12:46:25.006275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 12:46:25.013229 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 12:46:25.015864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 12:46:25.019590 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 12:46:25.026518 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 12:46:25.029161 Total UI for P1: 0, mck2ui 16
6306 12:46:25.032425 best dqsien dly found for B0: ( 0, 14, 24)
6307 12:46:25.035921 Total UI for P1: 0, mck2ui 16
6308 12:46:25.039027 best dqsien dly found for B1: ( 0, 14, 24)
6309 12:46:25.042047 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6310 12:46:25.045713 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6311 12:46:25.045794
6312 12:46:25.048888 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 12:46:25.052227 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 12:46:25.055420 [Gating] SW calibration Done
6315 12:46:25.055501 ==
6316 12:46:25.058721 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 12:46:25.062529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 12:46:25.065344 ==
6319 12:46:25.065425 RX Vref Scan: 0
6320 12:46:25.065490
6321 12:46:25.068596 RX Vref 0 -> 0, step: 1
6322 12:46:25.068676
6323 12:46:25.071641 RX Delay -410 -> 252, step: 16
6324 12:46:25.075455 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6325 12:46:25.078508 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6326 12:46:25.081471 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6327 12:46:25.088010 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6328 12:46:25.091516 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6329 12:46:25.094868 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6330 12:46:25.098181 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6331 12:46:25.104740 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6332 12:46:25.107973 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6333 12:46:25.111876 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6334 12:46:25.118097 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6335 12:46:25.122144 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6336 12:46:25.124828 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6337 12:46:25.127989 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6338 12:46:25.134716 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6339 12:46:25.139376 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6340 12:46:25.139788 ==
6341 12:46:25.141157 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 12:46:25.144406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 12:46:25.144816 ==
6344 12:46:25.147870 DQS Delay:
6345 12:46:25.148317 DQS0 = 35, DQS1 = 51
6346 12:46:25.151122 DQM Delay:
6347 12:46:25.151599 DQM0 = 4, DQM1 = 10
6348 12:46:25.152135 DQ Delay:
6349 12:46:25.154941 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6350 12:46:25.157861 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6351 12:46:25.160874 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6352 12:46:25.164514 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6353 12:46:25.164921
6354 12:46:25.165240
6355 12:46:25.165532 ==
6356 12:46:25.167354 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 12:46:25.174387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 12:46:25.174800 ==
6359 12:46:25.175124
6360 12:46:25.175421
6361 12:46:25.175703 TX Vref Scan disable
6362 12:46:25.177703 == TX Byte 0 ==
6363 12:46:25.180718 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 12:46:25.184073 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 12:46:25.187763 == TX Byte 1 ==
6366 12:46:25.190742 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 12:46:25.194060 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 12:46:25.194495 ==
6369 12:46:25.198064 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 12:46:25.203944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 12:46:25.204399 ==
6372 12:46:25.204727
6373 12:46:25.205025
6374 12:46:25.205307 TX Vref Scan disable
6375 12:46:25.207085 == TX Byte 0 ==
6376 12:46:25.210556 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 12:46:25.214089 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 12:46:25.217013 == TX Byte 1 ==
6379 12:46:25.220398 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6380 12:46:25.223782 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6381 12:46:25.227430
6382 12:46:25.227834 [DATLAT]
6383 12:46:25.228196 Freq=400, CH0 RK0
6384 12:46:25.228507
6385 12:46:25.230133 DATLAT Default: 0xf
6386 12:46:25.230556 0, 0xFFFF, sum = 0
6387 12:46:25.233666 1, 0xFFFF, sum = 0
6388 12:46:25.234149 2, 0xFFFF, sum = 0
6389 12:46:25.236552 3, 0xFFFF, sum = 0
6390 12:46:25.239960 4, 0xFFFF, sum = 0
6391 12:46:25.240410 5, 0xFFFF, sum = 0
6392 12:46:25.243150 6, 0xFFFF, sum = 0
6393 12:46:25.243562 7, 0xFFFF, sum = 0
6394 12:46:25.246427 8, 0xFFFF, sum = 0
6395 12:46:25.246841 9, 0xFFFF, sum = 0
6396 12:46:25.249993 10, 0xFFFF, sum = 0
6397 12:46:25.250405 11, 0xFFFF, sum = 0
6398 12:46:25.253306 12, 0xFFFF, sum = 0
6399 12:46:25.253720 13, 0x0, sum = 1
6400 12:46:25.256018 14, 0x0, sum = 2
6401 12:46:25.256484 15, 0x0, sum = 3
6402 12:46:25.259291 16, 0x0, sum = 4
6403 12:46:25.259702 best_step = 14
6404 12:46:25.260020
6405 12:46:25.260377 ==
6406 12:46:25.263321 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 12:46:25.266328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 12:46:25.269947 ==
6409 12:46:25.270383 RX Vref Scan: 1
6410 12:46:25.270700
6411 12:46:25.273472 RX Vref 0 -> 0, step: 1
6412 12:46:25.273877
6413 12:46:25.276141 RX Delay -343 -> 252, step: 8
6414 12:46:25.276546
6415 12:46:25.279643 Set Vref, RX VrefLevel [Byte0]: 52
6416 12:46:25.282632 [Byte1]: 59
6417 12:46:25.283062
6418 12:46:25.286226 Final RX Vref Byte 0 = 52 to rank0
6419 12:46:25.289490 Final RX Vref Byte 1 = 59 to rank0
6420 12:46:25.292520 Final RX Vref Byte 0 = 52 to rank1
6421 12:46:25.296146 Final RX Vref Byte 1 = 59 to rank1==
6422 12:46:25.299472 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 12:46:25.302144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 12:46:25.305688 ==
6425 12:46:25.306160 DQS Delay:
6426 12:46:25.306509 DQS0 = 40, DQS1 = 60
6427 12:46:25.308955 DQM Delay:
6428 12:46:25.309397 DQM0 = 6, DQM1 = 16
6429 12:46:25.311907 DQ Delay:
6430 12:46:25.312412 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6431 12:46:25.315396 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6432 12:46:25.319093 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6433 12:46:25.322231 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6434 12:46:25.322697
6435 12:46:25.323033
6436 12:46:25.332131 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6437 12:46:25.335048 CH0 RK0: MR19=C0C, MR18=8D81
6438 12:46:25.341643 CH0_RK0: MR19=0xC0C, MR18=0x8D81, DQSOSC=392, MR23=63, INC=384, DEC=256
6439 12:46:25.342104 ==
6440 12:46:25.345132 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 12:46:25.348328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 12:46:25.348758 ==
6443 12:46:25.351649 [Gating] SW mode calibration
6444 12:46:25.357829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6445 12:46:25.364616 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6446 12:46:25.367879 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 12:46:25.371118 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 12:46:25.377933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 12:46:25.381150 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 12:46:25.385047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 12:46:25.391057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 12:46:25.394481 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 12:46:25.397561 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 12:46:25.404170 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 12:46:25.404722 Total UI for P1: 0, mck2ui 16
6456 12:46:25.410558 best dqsien dly found for B0: ( 0, 14, 24)
6457 12:46:25.411074 Total UI for P1: 0, mck2ui 16
6458 12:46:25.417241 best dqsien dly found for B1: ( 0, 14, 24)
6459 12:46:25.420718 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6460 12:46:25.423862 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6461 12:46:25.424316
6462 12:46:25.427227 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 12:46:25.430899 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 12:46:25.434208 [Gating] SW calibration Done
6465 12:46:25.434629 ==
6466 12:46:25.437441 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 12:46:25.440268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 12:46:25.440686 ==
6469 12:46:25.443700 RX Vref Scan: 0
6470 12:46:25.444156
6471 12:46:25.444492 RX Vref 0 -> 0, step: 1
6472 12:46:25.444798
6473 12:46:25.447727 RX Delay -410 -> 252, step: 16
6474 12:46:25.454146 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6475 12:46:25.457037 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6476 12:46:25.460662 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6477 12:46:25.463746 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6478 12:46:25.469969 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6479 12:46:25.473335 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6480 12:46:25.476354 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6481 12:46:25.479751 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6482 12:46:25.486321 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6483 12:46:25.489656 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6484 12:46:25.493080 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6485 12:46:25.496661 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6486 12:46:25.503074 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6487 12:46:25.507062 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6488 12:46:25.509440 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6489 12:46:25.516706 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6490 12:46:25.517156 ==
6491 12:46:25.519671 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 12:46:25.522598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 12:46:25.523161 ==
6494 12:46:25.523639 DQS Delay:
6495 12:46:25.526152 DQS0 = 35, DQS1 = 59
6496 12:46:25.526551 DQM Delay:
6497 12:46:25.529170 DQM0 = 6, DQM1 = 16
6498 12:46:25.529592 DQ Delay:
6499 12:46:25.532482 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6500 12:46:25.535864 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6501 12:46:25.539715 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6502 12:46:25.542341 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6503 12:46:25.542759
6504 12:46:25.543084
6505 12:46:25.543401 ==
6506 12:46:25.546201 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 12:46:25.549187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 12:46:25.549800 ==
6509 12:46:25.550325
6510 12:46:25.550833
6511 12:46:25.552191 TX Vref Scan disable
6512 12:46:25.555897 == TX Byte 0 ==
6513 12:46:25.559059 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6514 12:46:25.562265 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6515 12:46:25.565315 == TX Byte 1 ==
6516 12:46:25.569236 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6517 12:46:25.571916 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6518 12:46:25.572362 ==
6519 12:46:25.575190 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 12:46:25.578713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 12:46:25.581982 ==
6522 12:46:25.582397
6523 12:46:25.582726
6524 12:46:25.583031 TX Vref Scan disable
6525 12:46:25.585202 == TX Byte 0 ==
6526 12:46:25.588423 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6527 12:46:25.592090 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6528 12:46:25.594935 == TX Byte 1 ==
6529 12:46:25.598452 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6530 12:46:25.601550 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6531 12:46:25.601974
6532 12:46:25.604845 [DATLAT]
6533 12:46:25.605264 Freq=400, CH0 RK1
6534 12:46:25.605595
6535 12:46:25.608133 DATLAT Default: 0xe
6536 12:46:25.608550 0, 0xFFFF, sum = 0
6537 12:46:25.611262 1, 0xFFFF, sum = 0
6538 12:46:25.611687 2, 0xFFFF, sum = 0
6539 12:46:25.614927 3, 0xFFFF, sum = 0
6540 12:46:25.615353 4, 0xFFFF, sum = 0
6541 12:46:25.618243 5, 0xFFFF, sum = 0
6542 12:46:25.618669 6, 0xFFFF, sum = 0
6543 12:46:25.621362 7, 0xFFFF, sum = 0
6544 12:46:25.621812 8, 0xFFFF, sum = 0
6545 12:46:25.625032 9, 0xFFFF, sum = 0
6546 12:46:25.625469 10, 0xFFFF, sum = 0
6547 12:46:25.627785 11, 0xFFFF, sum = 0
6548 12:46:25.628248 12, 0xFFFF, sum = 0
6549 12:46:25.631260 13, 0x0, sum = 1
6550 12:46:25.631684 14, 0x0, sum = 2
6551 12:46:25.634371 15, 0x0, sum = 3
6552 12:46:25.634799 16, 0x0, sum = 4
6553 12:46:25.637849 best_step = 14
6554 12:46:25.638458
6555 12:46:25.638888 ==
6556 12:46:25.640966 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 12:46:25.644645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 12:46:25.645100 ==
6559 12:46:25.647575 RX Vref Scan: 0
6560 12:46:25.648200
6561 12:46:25.648673 RX Vref 0 -> 0, step: 1
6562 12:46:25.649004
6563 12:46:25.651210 RX Delay -359 -> 252, step: 8
6564 12:46:25.659259 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6565 12:46:25.662974 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6566 12:46:25.665761 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6567 12:46:25.672346 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6568 12:46:25.675875 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6569 12:46:25.678735 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6570 12:46:25.682839 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6571 12:46:25.689295 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6572 12:46:25.692344 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6573 12:46:25.695445 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6574 12:46:25.698964 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6575 12:46:25.705568 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6576 12:46:25.708782 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6577 12:46:25.711690 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6578 12:46:25.715722 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6579 12:46:25.721811 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6580 12:46:25.722225 ==
6581 12:46:25.725043 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 12:46:25.728441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 12:46:25.728860 ==
6584 12:46:25.731642 DQS Delay:
6585 12:46:25.732070 DQS0 = 44, DQS1 = 60
6586 12:46:25.732405 DQM Delay:
6587 12:46:25.734500 DQM0 = 9, DQM1 = 16
6588 12:46:25.734915 DQ Delay:
6589 12:46:25.737990 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6590 12:46:25.741839 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6591 12:46:25.745098 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6592 12:46:25.748188 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6593 12:46:25.748604
6594 12:46:25.748937
6595 12:46:25.757495 [DQSOSCAuto] RK1, (LSB)MR18= 0x7d77, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
6596 12:46:25.757922 CH0 RK1: MR19=C0C, MR18=7D77
6597 12:46:25.764575 CH0_RK1: MR19=0xC0C, MR18=0x7D77, DQSOSC=394, MR23=63, INC=380, DEC=253
6598 12:46:25.767823 [RxdqsGatingPostProcess] freq 400
6599 12:46:25.774806 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6600 12:46:25.778274 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 12:46:25.780988 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 12:46:25.784260 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 12:46:25.787850 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 12:46:25.790738 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 12:46:25.793818 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 12:46:25.797142 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 12:46:25.801022 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 12:46:25.801632 Pre-setting of DQS Precalculation
6609 12:46:25.806968 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6610 12:46:25.807437 ==
6611 12:46:25.810792 Dram Type= 6, Freq= 0, CH_1, rank 0
6612 12:46:25.813926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 12:46:25.814469 ==
6614 12:46:25.820440 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 12:46:25.827659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6616 12:46:25.830472 [CA 0] Center 36 (8~64) winsize 57
6617 12:46:25.833734 [CA 1] Center 36 (8~64) winsize 57
6618 12:46:25.836372 [CA 2] Center 36 (8~64) winsize 57
6619 12:46:25.839843 [CA 3] Center 36 (8~64) winsize 57
6620 12:46:25.843157 [CA 4] Center 36 (8~64) winsize 57
6621 12:46:25.843265 [CA 5] Center 36 (8~64) winsize 57
6622 12:46:25.846421
6623 12:46:25.849563 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6624 12:46:25.849671
6625 12:46:25.852629 [CATrainingPosCal] consider 1 rank data
6626 12:46:25.855961 u2DelayCellTimex100 = 270/100 ps
6627 12:46:25.859588 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:46:25.862762 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 12:46:25.865845 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 12:46:25.869249 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:46:25.872295 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:46:25.875728 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:46:25.875809
6634 12:46:25.882574 CA PerBit enable=1, Macro0, CA PI delay=36
6635 12:46:25.882654
6636 12:46:25.882718 [CBTSetCACLKResult] CA Dly = 36
6637 12:46:25.885877 CS Dly: 1 (0~32)
6638 12:46:25.885958 ==
6639 12:46:25.889525 Dram Type= 6, Freq= 0, CH_1, rank 1
6640 12:46:25.892117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 12:46:25.892200 ==
6642 12:46:25.898686 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 12:46:25.905487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6644 12:46:25.908485 [CA 0] Center 36 (8~64) winsize 57
6645 12:46:25.911877 [CA 1] Center 36 (8~64) winsize 57
6646 12:46:25.915119 [CA 2] Center 36 (8~64) winsize 57
6647 12:46:25.918944 [CA 3] Center 36 (8~64) winsize 57
6648 12:46:25.922015 [CA 4] Center 36 (8~64) winsize 57
6649 12:46:25.922096 [CA 5] Center 36 (8~64) winsize 57
6650 12:46:25.922160
6651 12:46:25.928817 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6652 12:46:25.928898
6653 12:46:25.932405 [CATrainingPosCal] consider 2 rank data
6654 12:46:25.935139 u2DelayCellTimex100 = 270/100 ps
6655 12:46:25.938704 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:46:25.941959 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:46:25.944940 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 12:46:25.948405 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 12:46:25.951671 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 12:46:25.954743 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 12:46:25.954823
6662 12:46:25.958334 CA PerBit enable=1, Macro0, CA PI delay=36
6663 12:46:25.958415
6664 12:46:25.961839 [CBTSetCACLKResult] CA Dly = 36
6665 12:46:25.964971 CS Dly: 1 (0~32)
6666 12:46:25.965051
6667 12:46:25.968027 ----->DramcWriteLeveling(PI) begin...
6668 12:46:25.968152 ==
6669 12:46:25.971492 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 12:46:25.974778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 12:46:25.974877 ==
6672 12:46:25.978226 Write leveling (Byte 0): 40 => 8
6673 12:46:25.981246 Write leveling (Byte 1): 40 => 8
6674 12:46:25.984509 DramcWriteLeveling(PI) end<-----
6675 12:46:25.984606
6676 12:46:25.984669 ==
6677 12:46:25.987760 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 12:46:25.991049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 12:46:25.991130 ==
6680 12:46:25.994954 [Gating] SW mode calibration
6681 12:46:26.000991 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6682 12:46:26.007557 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6683 12:46:26.010977 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6684 12:46:26.017859 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 12:46:26.021093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 12:46:26.024173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 12:46:26.030367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 12:46:26.033678 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 12:46:26.037338 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 12:46:26.043422 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 12:46:26.047320 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 12:46:26.050235 Total UI for P1: 0, mck2ui 16
6693 12:46:26.054141 best dqsien dly found for B0: ( 0, 14, 24)
6694 12:46:26.056694 Total UI for P1: 0, mck2ui 16
6695 12:46:26.060386 best dqsien dly found for B1: ( 0, 14, 24)
6696 12:46:26.063224 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6697 12:46:26.066942 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6698 12:46:26.067022
6699 12:46:26.070151 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 12:46:26.076707 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 12:46:26.076788 [Gating] SW calibration Done
6702 12:46:26.076854 ==
6703 12:46:26.079988 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 12:46:26.086536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 12:46:26.086650 ==
6706 12:46:26.086743 RX Vref Scan: 0
6707 12:46:26.086834
6708 12:46:26.089965 RX Vref 0 -> 0, step: 1
6709 12:46:26.090052
6710 12:46:26.093175 RX Delay -410 -> 252, step: 16
6711 12:46:26.096390 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6712 12:46:26.100382 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6713 12:46:26.106161 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6714 12:46:26.110034 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6715 12:46:26.112918 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6716 12:46:26.115924 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6717 12:46:26.122679 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6718 12:46:26.126214 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6719 12:46:26.129402 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6720 12:46:26.132318 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6721 12:46:26.138941 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6722 12:46:26.142355 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6723 12:46:26.145585 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6724 12:46:26.152514 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6725 12:46:26.155878 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6726 12:46:26.159025 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6727 12:46:26.159101 ==
6728 12:46:26.162976 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 12:46:26.165585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 12:46:26.168812 ==
6731 12:46:26.168892 DQS Delay:
6732 12:46:26.168955 DQS0 = 43, DQS1 = 51
6733 12:46:26.171965 DQM Delay:
6734 12:46:26.172084 DQM0 = 13, DQM1 = 14
6735 12:46:26.175486 DQ Delay:
6736 12:46:26.175566 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6737 12:46:26.178997 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6738 12:46:26.182137 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6739 12:46:26.185537 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6740 12:46:26.185617
6741 12:46:26.185680
6742 12:46:26.188963 ==
6743 12:46:26.189043 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 12:46:26.195043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 12:46:26.195123 ==
6746 12:46:26.195187
6747 12:46:26.195245
6748 12:46:26.198478 TX Vref Scan disable
6749 12:46:26.198559 == TX Byte 0 ==
6750 12:46:26.201700 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 12:46:26.208399 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 12:46:26.208479 == TX Byte 1 ==
6753 12:46:26.211579 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 12:46:26.218158 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 12:46:26.218248 ==
6756 12:46:26.221552 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 12:46:26.224564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 12:46:26.224664 ==
6759 12:46:26.224754
6760 12:46:26.224844
6761 12:46:26.228337 TX Vref Scan disable
6762 12:46:26.228432 == TX Byte 0 ==
6763 12:46:26.232170 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 12:46:26.237902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 12:46:26.237984 == TX Byte 1 ==
6766 12:46:26.240929 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 12:46:26.247855 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 12:46:26.247943
6769 12:46:26.248007 [DATLAT]
6770 12:46:26.250909 Freq=400, CH1 RK0
6771 12:46:26.250991
6772 12:46:26.251055 DATLAT Default: 0xf
6773 12:46:26.254272 0, 0xFFFF, sum = 0
6774 12:46:26.254355 1, 0xFFFF, sum = 0
6775 12:46:26.257458 2, 0xFFFF, sum = 0
6776 12:46:26.257541 3, 0xFFFF, sum = 0
6777 12:46:26.261007 4, 0xFFFF, sum = 0
6778 12:46:26.261141 5, 0xFFFF, sum = 0
6779 12:46:26.264075 6, 0xFFFF, sum = 0
6780 12:46:26.264171 7, 0xFFFF, sum = 0
6781 12:46:26.267568 8, 0xFFFF, sum = 0
6782 12:46:26.267651 9, 0xFFFF, sum = 0
6783 12:46:26.271284 10, 0xFFFF, sum = 0
6784 12:46:26.271387 11, 0xFFFF, sum = 0
6785 12:46:26.273885 12, 0xFFFF, sum = 0
6786 12:46:26.273967 13, 0x0, sum = 1
6787 12:46:26.277790 14, 0x0, sum = 2
6788 12:46:26.277873 15, 0x0, sum = 3
6789 12:46:26.280881 16, 0x0, sum = 4
6790 12:46:26.280964 best_step = 14
6791 12:46:26.281028
6792 12:46:26.281088 ==
6793 12:46:26.284277 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 12:46:26.290556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 12:46:26.290651 ==
6796 12:46:26.290715 RX Vref Scan: 1
6797 12:46:26.290775
6798 12:46:26.294215 RX Vref 0 -> 0, step: 1
6799 12:46:26.294296
6800 12:46:26.297104 RX Delay -343 -> 252, step: 8
6801 12:46:26.297200
6802 12:46:26.300762 Set Vref, RX VrefLevel [Byte0]: 52
6803 12:46:26.304214 [Byte1]: 48
6804 12:46:26.307095
6805 12:46:26.307192 Final RX Vref Byte 0 = 52 to rank0
6806 12:46:26.310619 Final RX Vref Byte 1 = 48 to rank0
6807 12:46:26.313983 Final RX Vref Byte 0 = 52 to rank1
6808 12:46:26.316953 Final RX Vref Byte 1 = 48 to rank1==
6809 12:46:26.320645 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 12:46:26.327029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 12:46:26.327111 ==
6812 12:46:26.327175 DQS Delay:
6813 12:46:26.331011 DQS0 = 44, DQS1 = 56
6814 12:46:26.331149 DQM Delay:
6815 12:46:26.331215 DQM0 = 10, DQM1 = 14
6816 12:46:26.333698 DQ Delay:
6817 12:46:26.336870 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6818 12:46:26.336971 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6819 12:46:26.340622 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6820 12:46:26.343450 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6821 12:46:26.343552
6822 12:46:26.347189
6823 12:46:26.353493 [DQSOSCAuto] RK0, (LSB)MR18= 0x6187, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6824 12:46:26.356761 CH1 RK0: MR19=C0C, MR18=6187
6825 12:46:26.363454 CH1_RK0: MR19=0xC0C, MR18=0x6187, DQSOSC=392, MR23=63, INC=384, DEC=256
6826 12:46:26.363536 ==
6827 12:46:26.366664 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 12:46:26.370016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 12:46:26.370098 ==
6830 12:46:26.374068 [Gating] SW mode calibration
6831 12:46:26.379831 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6832 12:46:26.386853 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6833 12:46:26.390026 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 12:46:26.393082 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 12:46:26.399694 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 12:46:26.402979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 12:46:26.406468 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 12:46:26.412915 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 12:46:26.416624 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 12:46:26.419389 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 12:46:26.426553 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 12:46:26.426634 Total UI for P1: 0, mck2ui 16
6843 12:46:26.432856 best dqsien dly found for B0: ( 0, 14, 24)
6844 12:46:26.432937 Total UI for P1: 0, mck2ui 16
6845 12:46:26.435874 best dqsien dly found for B1: ( 0, 14, 24)
6846 12:46:26.443020 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6847 12:46:26.445737 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6848 12:46:26.445818
6849 12:46:26.449034 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 12:46:26.452687 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 12:46:26.455950 [Gating] SW calibration Done
6852 12:46:26.456035 ==
6853 12:46:26.458969 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 12:46:26.462261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 12:46:26.462347 ==
6856 12:46:26.465683 RX Vref Scan: 0
6857 12:46:26.465776
6858 12:46:26.465849 RX Vref 0 -> 0, step: 1
6859 12:46:26.468946
6860 12:46:26.469038 RX Delay -410 -> 252, step: 16
6861 12:46:26.475912 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6862 12:46:26.479001 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6863 12:46:26.482235 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6864 12:46:26.485559 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6865 12:46:26.491910 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6866 12:46:26.495587 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6867 12:46:26.498814 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6868 12:46:26.505104 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6869 12:46:26.508878 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6870 12:46:26.511569 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6871 12:46:26.514904 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6872 12:46:26.521815 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6873 12:46:26.524766 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6874 12:46:26.528565 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6875 12:46:26.531630 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6876 12:46:26.537994 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6877 12:46:26.538534 ==
6878 12:46:26.541397 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 12:46:26.544535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 12:46:26.544976 ==
6881 12:46:26.547771 DQS Delay:
6882 12:46:26.548266 DQS0 = 43, DQS1 = 51
6883 12:46:26.548698 DQM Delay:
6884 12:46:26.551236 DQM0 = 10, DQM1 = 14
6885 12:46:26.551613 DQ Delay:
6886 12:46:26.554486 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6887 12:46:26.557806 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6888 12:46:26.561078 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6889 12:46:26.564353 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6890 12:46:26.564785
6891 12:46:26.565219
6892 12:46:26.565632 ==
6893 12:46:26.567770 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 12:46:26.571098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 12:46:26.574305 ==
6896 12:46:26.574734
6897 12:46:26.575170
6898 12:46:26.575582 TX Vref Scan disable
6899 12:46:26.577944 == TX Byte 0 ==
6900 12:46:26.580760 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6901 12:46:26.584466 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6902 12:46:26.587419 == TX Byte 1 ==
6903 12:46:26.591019 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6904 12:46:26.594321 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6905 12:46:26.594929 ==
6906 12:46:26.597826 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 12:46:26.601397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 12:46:26.603914 ==
6909 12:46:26.604375
6910 12:46:26.604705
6911 12:46:26.605010 TX Vref Scan disable
6912 12:46:26.607595 == TX Byte 0 ==
6913 12:46:26.610554 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6914 12:46:26.613932 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6915 12:46:26.617468 == TX Byte 1 ==
6916 12:46:26.621180 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6917 12:46:26.624001 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6918 12:46:26.624481
6919 12:46:26.626942 [DATLAT]
6920 12:46:26.627359 Freq=400, CH1 RK1
6921 12:46:26.627720
6922 12:46:26.630659 DATLAT Default: 0xe
6923 12:46:26.631075 0, 0xFFFF, sum = 0
6924 12:46:26.633547 1, 0xFFFF, sum = 0
6925 12:46:26.633970 2, 0xFFFF, sum = 0
6926 12:46:26.637502 3, 0xFFFF, sum = 0
6927 12:46:26.638041 4, 0xFFFF, sum = 0
6928 12:46:26.640578 5, 0xFFFF, sum = 0
6929 12:46:26.641003 6, 0xFFFF, sum = 0
6930 12:46:26.643395 7, 0xFFFF, sum = 0
6931 12:46:26.643816 8, 0xFFFF, sum = 0
6932 12:46:26.646712 9, 0xFFFF, sum = 0
6933 12:46:26.650177 10, 0xFFFF, sum = 0
6934 12:46:26.650600 11, 0xFFFF, sum = 0
6935 12:46:26.653302 12, 0xFFFF, sum = 0
6936 12:46:26.653726 13, 0x0, sum = 1
6937 12:46:26.656504 14, 0x0, sum = 2
6938 12:46:26.656929 15, 0x0, sum = 3
6939 12:46:26.657270 16, 0x0, sum = 4
6940 12:46:26.659987 best_step = 14
6941 12:46:26.660459
6942 12:46:26.660794 ==
6943 12:46:26.663097 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 12:46:26.666275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 12:46:26.666697 ==
6946 12:46:26.669942 RX Vref Scan: 0
6947 12:46:26.670406
6948 12:46:26.672792 RX Vref 0 -> 0, step: 1
6949 12:46:26.673211
6950 12:46:26.673545 RX Delay -343 -> 252, step: 8
6951 12:46:26.681981 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6952 12:46:26.684832 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6953 12:46:26.688204 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6954 12:46:26.694836 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6955 12:46:26.698470 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6956 12:46:26.701599 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6957 12:46:26.705184 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6958 12:46:26.711378 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6959 12:46:26.714509 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6960 12:46:26.717726 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6961 12:46:26.721506 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6962 12:46:26.727479 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6963 12:46:26.730908 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6964 12:46:26.734707 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6965 12:46:26.737473 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6966 12:46:26.744385 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6967 12:46:26.744467 ==
6968 12:46:26.747528 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 12:46:26.750798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 12:46:26.750880 ==
6971 12:46:26.750945 DQS Delay:
6972 12:46:26.753716 DQS0 = 48, DQS1 = 56
6973 12:46:26.753796 DQM Delay:
6974 12:46:26.757355 DQM0 = 12, DQM1 = 15
6975 12:46:26.757436 DQ Delay:
6976 12:46:26.760417 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6977 12:46:26.764247 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6978 12:46:26.766808 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6979 12:46:26.771178 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6980 12:46:26.771260
6981 12:46:26.771324
6982 12:46:26.780376 [DQSOSCAuto] RK1, (LSB)MR18= 0x6da4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6983 12:46:26.780458 CH1 RK1: MR19=C0C, MR18=6DA4
6984 12:46:26.786672 CH1_RK1: MR19=0xC0C, MR18=0x6DA4, DQSOSC=389, MR23=63, INC=390, DEC=260
6985 12:46:26.789843 [RxdqsGatingPostProcess] freq 400
6986 12:46:26.796574 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6987 12:46:26.800505 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 12:46:26.803075 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 12:46:26.806752 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 12:46:26.809899 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 12:46:26.813329 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 12:46:26.816524 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 12:46:26.819864 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 12:46:26.823207 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 12:46:26.823300 Pre-setting of DQS Precalculation
6996 12:46:26.829819 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6997 12:46:26.836181 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6998 12:46:26.843238 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6999 12:46:26.843373
7000 12:46:26.843480
7001 12:46:26.846087 [Calibration Summary] 800 Mbps
7002 12:46:26.849532 CH 0, Rank 0
7003 12:46:26.849703 SW Impedance : PASS
7004 12:46:26.852569 DUTY Scan : NO K
7005 12:46:26.855946 ZQ Calibration : PASS
7006 12:46:26.856159 Jitter Meter : NO K
7007 12:46:26.859487 CBT Training : PASS
7008 12:46:26.862671 Write leveling : PASS
7009 12:46:26.862919 RX DQS gating : PASS
7010 12:46:26.866024 RX DQ/DQS(RDDQC) : PASS
7011 12:46:26.869418 TX DQ/DQS : PASS
7012 12:46:26.869877 RX DATLAT : PASS
7013 12:46:26.872629 RX DQ/DQS(Engine): PASS
7014 12:46:26.875690 TX OE : NO K
7015 12:46:26.876270 All Pass.
7016 12:46:26.876609
7017 12:46:26.876915 CH 0, Rank 1
7018 12:46:26.879274 SW Impedance : PASS
7019 12:46:26.882234 DUTY Scan : NO K
7020 12:46:26.882674 ZQ Calibration : PASS
7021 12:46:26.885840 Jitter Meter : NO K
7022 12:46:26.888965 CBT Training : PASS
7023 12:46:26.889381 Write leveling : NO K
7024 12:46:26.892348 RX DQS gating : PASS
7025 12:46:26.895522 RX DQ/DQS(RDDQC) : PASS
7026 12:46:26.895937 TX DQ/DQS : PASS
7027 12:46:26.898660 RX DATLAT : PASS
7028 12:46:26.899073 RX DQ/DQS(Engine): PASS
7029 12:46:26.902427 TX OE : NO K
7030 12:46:26.902844 All Pass.
7031 12:46:26.903176
7032 12:46:26.905648 CH 1, Rank 0
7033 12:46:26.908889 SW Impedance : PASS
7034 12:46:26.909303 DUTY Scan : NO K
7035 12:46:26.912608 ZQ Calibration : PASS
7036 12:46:26.913022 Jitter Meter : NO K
7037 12:46:26.915333 CBT Training : PASS
7038 12:46:26.918995 Write leveling : PASS
7039 12:46:26.919409 RX DQS gating : PASS
7040 12:46:26.921705 RX DQ/DQS(RDDQC) : PASS
7041 12:46:26.925159 TX DQ/DQS : PASS
7042 12:46:26.925575 RX DATLAT : PASS
7043 12:46:26.928647 RX DQ/DQS(Engine): PASS
7044 12:46:26.931620 TX OE : NO K
7045 12:46:26.932059 All Pass.
7046 12:46:26.932394
7047 12:46:26.932695 CH 1, Rank 1
7048 12:46:26.934989 SW Impedance : PASS
7049 12:46:26.938047 DUTY Scan : NO K
7050 12:46:26.938462 ZQ Calibration : PASS
7051 12:46:26.941631 Jitter Meter : NO K
7052 12:46:26.944937 CBT Training : PASS
7053 12:46:26.945352 Write leveling : NO K
7054 12:46:26.948155 RX DQS gating : PASS
7055 12:46:26.951218 RX DQ/DQS(RDDQC) : PASS
7056 12:46:26.951631 TX DQ/DQS : PASS
7057 12:46:26.954576 RX DATLAT : PASS
7058 12:46:26.957884 RX DQ/DQS(Engine): PASS
7059 12:46:26.958299 TX OE : NO K
7060 12:46:26.961329 All Pass.
7061 12:46:26.961742
7062 12:46:26.962068 DramC Write-DBI off
7063 12:46:26.964675 PER_BANK_REFRESH: Hybrid Mode
7064 12:46:26.967948 TX_TRACKING: ON
7065 12:46:26.974026 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7066 12:46:26.977672 [FAST_K] Save calibration result to emmc
7067 12:46:26.980727 dramc_set_vcore_voltage set vcore to 725000
7068 12:46:26.984094 Read voltage for 1600, 0
7069 12:46:26.984509 Vio18 = 0
7070 12:46:26.987561 Vcore = 725000
7071 12:46:26.987973 Vdram = 0
7072 12:46:26.988358 Vddq = 0
7073 12:46:26.990544 Vmddr = 0
7074 12:46:26.994717 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7075 12:46:27.000401 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7076 12:46:27.003674 MEM_TYPE=3, freq_sel=13
7077 12:46:27.004119 sv_algorithm_assistance_LP4_3733
7078 12:46:27.010020 ============ PULL DRAM RESETB DOWN ============
7079 12:46:27.013608 ========== PULL DRAM RESETB DOWN end =========
7080 12:46:27.016941 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7081 12:46:27.019957 ===================================
7082 12:46:27.023482 LPDDR4 DRAM CONFIGURATION
7083 12:46:27.026558 ===================================
7084 12:46:27.030085 EX_ROW_EN[0] = 0x0
7085 12:46:27.030495 EX_ROW_EN[1] = 0x0
7086 12:46:27.033610 LP4Y_EN = 0x0
7087 12:46:27.034024 WORK_FSP = 0x1
7088 12:46:27.036324 WL = 0x5
7089 12:46:27.036736 RL = 0x5
7090 12:46:27.040174 BL = 0x2
7091 12:46:27.042951 RPST = 0x0
7092 12:46:27.043363 RD_PRE = 0x0
7093 12:46:27.046372 WR_PRE = 0x1
7094 12:46:27.046786 WR_PST = 0x1
7095 12:46:27.049795 DBI_WR = 0x0
7096 12:46:27.050337 DBI_RD = 0x0
7097 12:46:27.052906 OTF = 0x1
7098 12:46:27.056363 ===================================
7099 12:46:27.059696 ===================================
7100 12:46:27.060148 ANA top config
7101 12:46:27.062997 ===================================
7102 12:46:27.066493 DLL_ASYNC_EN = 0
7103 12:46:27.069479 ALL_SLAVE_EN = 0
7104 12:46:27.069948 NEW_RANK_MODE = 1
7105 12:46:27.072711 DLL_IDLE_MODE = 1
7106 12:46:27.075766 LP45_APHY_COMB_EN = 1
7107 12:46:27.079261 TX_ODT_DIS = 0
7108 12:46:27.082509 NEW_8X_MODE = 1
7109 12:46:27.086107 ===================================
7110 12:46:27.089173 ===================================
7111 12:46:27.089587 data_rate = 3200
7112 12:46:27.092696 CKR = 1
7113 12:46:27.095758 DQ_P2S_RATIO = 8
7114 12:46:27.098949 ===================================
7115 12:46:27.103018 CA_P2S_RATIO = 8
7116 12:46:27.105560 DQ_CA_OPEN = 0
7117 12:46:27.109315 DQ_SEMI_OPEN = 0
7118 12:46:27.109732 CA_SEMI_OPEN = 0
7119 12:46:27.112172 CA_FULL_RATE = 0
7120 12:46:27.115463 DQ_CKDIV4_EN = 0
7121 12:46:27.119104 CA_CKDIV4_EN = 0
7122 12:46:27.122348 CA_PREDIV_EN = 0
7123 12:46:27.125348 PH8_DLY = 12
7124 12:46:27.128799 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7125 12:46:27.129211 DQ_AAMCK_DIV = 4
7126 12:46:27.132581 CA_AAMCK_DIV = 4
7127 12:46:27.135964 CA_ADMCK_DIV = 4
7128 12:46:27.138335 DQ_TRACK_CA_EN = 0
7129 12:46:27.141793 CA_PICK = 1600
7130 12:46:27.144902 CA_MCKIO = 1600
7131 12:46:27.148479 MCKIO_SEMI = 0
7132 12:46:27.148896 PLL_FREQ = 3068
7133 12:46:27.151894 DQ_UI_PI_RATIO = 32
7134 12:46:27.155142 CA_UI_PI_RATIO = 0
7135 12:46:27.158702 ===================================
7136 12:46:27.161499 ===================================
7137 12:46:27.165013 memory_type:LPDDR4
7138 12:46:27.168183 GP_NUM : 10
7139 12:46:27.168675 SRAM_EN : 1
7140 12:46:27.171274 MD32_EN : 0
7141 12:46:27.174630 ===================================
7142 12:46:27.178077 [ANA_INIT] >>>>>>>>>>>>>>
7143 12:46:27.178511 <<<<<< [CONFIGURE PHASE]: ANA_TX
7144 12:46:27.181570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7145 12:46:27.184366 ===================================
7146 12:46:27.187617 data_rate = 3200,PCW = 0X7600
7147 12:46:27.191300 ===================================
7148 12:46:27.194168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7149 12:46:27.201162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 12:46:27.207308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 12:46:27.210804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7152 12:46:27.214238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7153 12:46:27.217167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7154 12:46:27.220547 [ANA_INIT] flow start
7155 12:46:27.220967 [ANA_INIT] PLL >>>>>>>>
7156 12:46:27.223787 [ANA_INIT] PLL <<<<<<<<
7157 12:46:27.227105 [ANA_INIT] MIDPI >>>>>>>>
7158 12:46:27.230681 [ANA_INIT] MIDPI <<<<<<<<
7159 12:46:27.231098 [ANA_INIT] DLL >>>>>>>>
7160 12:46:27.234085 [ANA_INIT] DLL <<<<<<<<
7161 12:46:27.237158 [ANA_INIT] flow end
7162 12:46:27.240157 ============ LP4 DIFF to SE enter ============
7163 12:46:27.243837 ============ LP4 DIFF to SE exit ============
7164 12:46:27.247040 [ANA_INIT] <<<<<<<<<<<<<
7165 12:46:27.250318 [Flow] Enable top DCM control >>>>>
7166 12:46:27.254074 [Flow] Enable top DCM control <<<<<
7167 12:46:27.256547 Enable DLL master slave shuffle
7168 12:46:27.259826 ==============================================================
7169 12:46:27.263300 Gating Mode config
7170 12:46:27.269657 ==============================================================
7171 12:46:27.270079 Config description:
7172 12:46:27.279620 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7173 12:46:27.286061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7174 12:46:27.292693 SELPH_MODE 0: By rank 1: By Phase
7175 12:46:27.296459 ==============================================================
7176 12:46:27.300007 GAT_TRACK_EN = 1
7177 12:46:27.302468 RX_GATING_MODE = 2
7178 12:46:27.306186 RX_GATING_TRACK_MODE = 2
7179 12:46:27.309750 SELPH_MODE = 1
7180 12:46:27.312579 PICG_EARLY_EN = 1
7181 12:46:27.315845 VALID_LAT_VALUE = 1
7182 12:46:27.319542 ==============================================================
7183 12:46:27.322465 Enter into Gating configuration >>>>
7184 12:46:27.326033 Exit from Gating configuration <<<<
7185 12:46:27.328844 Enter into DVFS_PRE_config >>>>>
7186 12:46:27.342439 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7187 12:46:27.345660 Exit from DVFS_PRE_config <<<<<
7188 12:46:27.348935 Enter into PICG configuration >>>>
7189 12:46:27.352605 Exit from PICG configuration <<<<
7190 12:46:27.353017 [RX_INPUT] configuration >>>>>
7191 12:46:27.355449 [RX_INPUT] configuration <<<<<
7192 12:46:27.362179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7193 12:46:27.365372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7194 12:46:27.371871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 12:46:27.378582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 12:46:27.385231 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 12:46:27.391646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 12:46:27.395183 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7199 12:46:27.398619 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7200 12:46:27.404850 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7201 12:46:27.408490 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7202 12:46:27.411211 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7203 12:46:27.417993 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 12:46:27.421140 ===================================
7205 12:46:27.421574 LPDDR4 DRAM CONFIGURATION
7206 12:46:27.424575 ===================================
7207 12:46:27.428478 EX_ROW_EN[0] = 0x0
7208 12:46:27.428860 EX_ROW_EN[1] = 0x0
7209 12:46:27.431311 LP4Y_EN = 0x0
7210 12:46:27.434307 WORK_FSP = 0x1
7211 12:46:27.434730 WL = 0x5
7212 12:46:27.437731 RL = 0x5
7213 12:46:27.438169 BL = 0x2
7214 12:46:27.441124 RPST = 0x0
7215 12:46:27.441588 RD_PRE = 0x0
7216 12:46:27.444640 WR_PRE = 0x1
7217 12:46:27.445115 WR_PST = 0x1
7218 12:46:27.447848 DBI_WR = 0x0
7219 12:46:27.448411 DBI_RD = 0x0
7220 12:46:27.451263 OTF = 0x1
7221 12:46:27.454532 ===================================
7222 12:46:27.457398 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7223 12:46:27.460995 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7224 12:46:27.467635 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7225 12:46:27.470900 ===================================
7226 12:46:27.471389 LPDDR4 DRAM CONFIGURATION
7227 12:46:27.473874 ===================================
7228 12:46:27.477597 EX_ROW_EN[0] = 0x10
7229 12:46:27.481188 EX_ROW_EN[1] = 0x0
7230 12:46:27.481646 LP4Y_EN = 0x0
7231 12:46:27.483830 WORK_FSP = 0x1
7232 12:46:27.484375 WL = 0x5
7233 12:46:27.487113 RL = 0x5
7234 12:46:27.487546 BL = 0x2
7235 12:46:27.490890 RPST = 0x0
7236 12:46:27.491359 RD_PRE = 0x0
7237 12:46:27.493947 WR_PRE = 0x1
7238 12:46:27.494412 WR_PST = 0x1
7239 12:46:27.496695 DBI_WR = 0x0
7240 12:46:27.497152 DBI_RD = 0x0
7241 12:46:27.500137 OTF = 0x1
7242 12:46:27.503501 ===================================
7243 12:46:27.510212 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7244 12:46:27.510658 ==
7245 12:46:27.513538 Dram Type= 6, Freq= 0, CH_0, rank 0
7246 12:46:27.516698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7247 12:46:27.517142 ==
7248 12:46:27.520158 [Duty_Offset_Calibration]
7249 12:46:27.520592 B0:2 B1:0 CA:4
7250 12:46:27.521088
7251 12:46:27.523271 [DutyScan_Calibration_Flow] k_type=0
7252 12:46:27.533965
7253 12:46:27.534461 ==CLK 0==
7254 12:46:27.536481 Final CLK duty delay cell = -4
7255 12:46:27.539962 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7256 12:46:27.543017 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7257 12:46:27.546873 [-4] AVG Duty = 4906%(X100)
7258 12:46:27.547294
7259 12:46:27.549788 CH0 CLK Duty spec in!! Max-Min= 187%
7260 12:46:27.553099 [DutyScan_Calibration_Flow] ====Done====
7261 12:46:27.553524
7262 12:46:27.556151 [DutyScan_Calibration_Flow] k_type=1
7263 12:46:27.573939
7264 12:46:27.574359 ==DQS 0 ==
7265 12:46:27.576853 Final DQS duty delay cell = 0
7266 12:46:27.580019 [0] MAX Duty = 5218%(X100), DQS PI = 24
7267 12:46:27.583401 [0] MIN Duty = 5093%(X100), DQS PI = 6
7268 12:46:27.586956 [0] AVG Duty = 5155%(X100)
7269 12:46:27.587381
7270 12:46:27.587751 ==DQS 1 ==
7271 12:46:27.589886 Final DQS duty delay cell = 0
7272 12:46:27.593033 [0] MAX Duty = 5187%(X100), DQS PI = 0
7273 12:46:27.596465 [0] MIN Duty = 4969%(X100), DQS PI = 10
7274 12:46:27.599856 [0] AVG Duty = 5078%(X100)
7275 12:46:27.600309
7276 12:46:27.603084 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7277 12:46:27.603555
7278 12:46:27.606548 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7279 12:46:27.609615 [DutyScan_Calibration_Flow] ====Done====
7280 12:46:27.610094
7281 12:46:27.613263 [DutyScan_Calibration_Flow] k_type=3
7282 12:46:27.630381
7283 12:46:27.630850 ==DQM 0 ==
7284 12:46:27.634696 Final DQM duty delay cell = 0
7285 12:46:27.637446 [0] MAX Duty = 5124%(X100), DQS PI = 22
7286 12:46:27.641458 [0] MIN Duty = 4875%(X100), DQS PI = 56
7287 12:46:27.644024 [0] AVG Duty = 4999%(X100)
7288 12:46:27.644492
7289 12:46:27.644911 ==DQM 1 ==
7290 12:46:27.647006 Final DQM duty delay cell = 0
7291 12:46:27.650117 [0] MAX Duty = 4969%(X100), DQS PI = 2
7292 12:46:27.653766 [0] MIN Duty = 4844%(X100), DQS PI = 16
7293 12:46:27.656718 [0] AVG Duty = 4906%(X100)
7294 12:46:27.657194
7295 12:46:27.660614 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7296 12:46:27.661112
7297 12:46:27.663925 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7298 12:46:27.666969 [DutyScan_Calibration_Flow] ====Done====
7299 12:46:27.667391
7300 12:46:27.669865 [DutyScan_Calibration_Flow] k_type=2
7301 12:46:27.687410
7302 12:46:27.687820 ==DQ 0 ==
7303 12:46:27.691391 Final DQ duty delay cell = 0
7304 12:46:27.694398 [0] MAX Duty = 5125%(X100), DQS PI = 22
7305 12:46:27.698180 [0] MIN Duty = 4969%(X100), DQS PI = 10
7306 12:46:27.698598 [0] AVG Duty = 5047%(X100)
7307 12:46:27.700992
7308 12:46:27.701421 ==DQ 1 ==
7309 12:46:27.704159 Final DQ duty delay cell = 0
7310 12:46:27.707504 [0] MAX Duty = 5187%(X100), DQS PI = 2
7311 12:46:27.711473 [0] MIN Duty = 4907%(X100), DQS PI = 34
7312 12:46:27.711922 [0] AVG Duty = 5047%(X100)
7313 12:46:27.713846
7314 12:46:27.717207 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7315 12:46:27.717675
7316 12:46:27.720484 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7317 12:46:27.724161 [DutyScan_Calibration_Flow] ====Done====
7318 12:46:27.724580 ==
7319 12:46:27.726894 Dram Type= 6, Freq= 0, CH_1, rank 0
7320 12:46:27.730902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7321 12:46:27.731328 ==
7322 12:46:27.733400 [Duty_Offset_Calibration]
7323 12:46:27.733884 B0:0 B1:-1 CA:3
7324 12:46:27.734272
7325 12:46:27.736748 [DutyScan_Calibration_Flow] k_type=0
7326 12:46:27.746972
7327 12:46:27.747439 ==CLK 0==
7328 12:46:27.750562 Final CLK duty delay cell = -4
7329 12:46:27.753968 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7330 12:46:27.757195 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7331 12:46:27.759999 [-4] AVG Duty = 4922%(X100)
7332 12:46:27.760448
7333 12:46:27.763776 CH1 CLK Duty spec in!! Max-Min= 156%
7334 12:46:27.767006 [DutyScan_Calibration_Flow] ====Done====
7335 12:46:27.767485
7336 12:46:27.770003 [DutyScan_Calibration_Flow] k_type=1
7337 12:46:27.786381
7338 12:46:27.786807 ==DQS 0 ==
7339 12:46:27.789349 Final DQS duty delay cell = 0
7340 12:46:27.793330 [0] MAX Duty = 5250%(X100), DQS PI = 30
7341 12:46:27.795996 [0] MIN Duty = 4907%(X100), DQS PI = 56
7342 12:46:27.799572 [0] AVG Duty = 5078%(X100)
7343 12:46:27.799974
7344 12:46:27.800428 ==DQS 1 ==
7345 12:46:27.802929 Final DQS duty delay cell = -4
7346 12:46:27.806493 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7347 12:46:27.809739 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7348 12:46:27.812639 [-4] AVG Duty = 4922%(X100)
7349 12:46:27.813043
7350 12:46:27.816486 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7351 12:46:27.816893
7352 12:46:27.819789 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7353 12:46:27.822440 [DutyScan_Calibration_Flow] ====Done====
7354 12:46:27.822843
7355 12:46:27.825732 [DutyScan_Calibration_Flow] k_type=3
7356 12:46:27.843765
7357 12:46:27.844194 ==DQM 0 ==
7358 12:46:27.846876 Final DQM duty delay cell = 0
7359 12:46:27.850395 [0] MAX Duty = 5062%(X100), DQS PI = 30
7360 12:46:27.853230 [0] MIN Duty = 4750%(X100), DQS PI = 40
7361 12:46:27.856575 [0] AVG Duty = 4906%(X100)
7362 12:46:27.856980
7363 12:46:27.857298 ==DQM 1 ==
7364 12:46:27.859987 Final DQM duty delay cell = 0
7365 12:46:27.863450 [0] MAX Duty = 5000%(X100), DQS PI = 30
7366 12:46:27.866573 [0] MIN Duty = 4813%(X100), DQS PI = 0
7367 12:46:27.870030 [0] AVG Duty = 4906%(X100)
7368 12:46:27.870438
7369 12:46:27.873251 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7370 12:46:27.873659
7371 12:46:27.876998 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7372 12:46:27.879714 [DutyScan_Calibration_Flow] ====Done====
7373 12:46:27.880161
7374 12:46:27.883084 [DutyScan_Calibration_Flow] k_type=2
7375 12:46:27.899382
7376 12:46:27.899786 ==DQ 0 ==
7377 12:46:27.902999 Final DQ duty delay cell = -4
7378 12:46:27.906002 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7379 12:46:27.909224 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7380 12:46:27.912855 [-4] AVG Duty = 4875%(X100)
7381 12:46:27.913257
7382 12:46:27.913574 ==DQ 1 ==
7383 12:46:27.916364 Final DQ duty delay cell = 0
7384 12:46:27.919715 [0] MAX Duty = 5031%(X100), DQS PI = 32
7385 12:46:27.922410 [0] MIN Duty = 4875%(X100), DQS PI = 0
7386 12:46:27.925961 [0] AVG Duty = 4953%(X100)
7387 12:46:27.926373
7388 12:46:27.929352 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7389 12:46:27.929766
7390 12:46:27.932709 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7391 12:46:27.935602 [DutyScan_Calibration_Flow] ====Done====
7392 12:46:27.939135 nWR fixed to 30
7393 12:46:27.942216 [ModeRegInit_LP4] CH0 RK0
7394 12:46:27.942630 [ModeRegInit_LP4] CH0 RK1
7395 12:46:27.945704 [ModeRegInit_LP4] CH1 RK0
7396 12:46:27.948957 [ModeRegInit_LP4] CH1 RK1
7397 12:46:27.949408 match AC timing 5
7398 12:46:27.955412 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7399 12:46:27.958764 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7400 12:46:27.962166 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7401 12:46:27.968870 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7402 12:46:27.972124 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7403 12:46:27.972541 [MiockJmeterHQA]
7404 12:46:27.975592
7405 12:46:27.978225 [DramcMiockJmeter] u1RxGatingPI = 0
7406 12:46:27.978665 0 : 4254, 4027
7407 12:46:27.979004 4 : 4252, 4026
7408 12:46:27.981739 8 : 4252, 4027
7409 12:46:27.982323 12 : 4252, 4026
7410 12:46:27.985150 16 : 4252, 4027
7411 12:46:27.985630 20 : 4253, 4026
7412 12:46:27.988608 24 : 4255, 4029
7413 12:46:27.989048 28 : 4363, 4137
7414 12:46:27.989382 32 : 4252, 4027
7415 12:46:27.991694 36 : 4252, 4027
7416 12:46:27.992107 40 : 4253, 4026
7417 12:46:27.995036 44 : 4254, 4029
7418 12:46:27.995419 48 : 4252, 4027
7419 12:46:27.998706 52 : 4363, 4138
7420 12:46:27.999173 56 : 4363, 4137
7421 12:46:28.001643 60 : 4252, 4029
7422 12:46:28.002135 64 : 4252, 4027
7423 12:46:28.002481 68 : 4253, 4026
7424 12:46:28.005648 72 : 4250, 4026
7425 12:46:28.006110 76 : 4252, 4030
7426 12:46:28.008390 80 : 4361, 4137
7427 12:46:28.008861 84 : 4253, 4029
7428 12:46:28.011767 88 : 4250, 4026
7429 12:46:28.012241 92 : 4250, 4026
7430 12:46:28.015128 96 : 4252, 2956
7431 12:46:28.015574 100 : 4250, 0
7432 12:46:28.015984 104 : 4249, 0
7433 12:46:28.017927 108 : 4363, 0
7434 12:46:28.018353 112 : 4363, 0
7435 12:46:28.021093 116 : 4363, 0
7436 12:46:28.021583 120 : 4250, 0
7437 12:46:28.021962 124 : 4361, 0
7438 12:46:28.024929 128 : 4250, 0
7439 12:46:28.025396 132 : 4250, 0
7440 12:46:28.027718 136 : 4250, 0
7441 12:46:28.028292 140 : 4250, 0
7442 12:46:28.028816 144 : 4253, 0
7443 12:46:28.031245 148 : 4252, 0
7444 12:46:28.031731 152 : 4252, 0
7445 12:46:28.034056 156 : 4252, 0
7446 12:46:28.034546 160 : 4363, 0
7447 12:46:28.034914 164 : 4360, 0
7448 12:46:28.037778 168 : 4362, 0
7449 12:46:28.038224 172 : 4250, 0
7450 12:46:28.038645 176 : 4360, 0
7451 12:46:28.040649 180 : 4250, 0
7452 12:46:28.041108 184 : 4250, 0
7453 12:46:28.044307 188 : 4250, 0
7454 12:46:28.044823 192 : 4360, 0
7455 12:46:28.045167 196 : 4249, 0
7456 12:46:28.047053 200 : 4252, 0
7457 12:46:28.047476 204 : 4250, 0
7458 12:46:28.050689 208 : 4252, 0
7459 12:46:28.051161 212 : 4250, 0
7460 12:46:28.051507 216 : 4250, 0
7461 12:46:28.053932 220 : 4250, 518
7462 12:46:28.054356 224 : 4250, 3965
7463 12:46:28.057297 228 : 4361, 4137
7464 12:46:28.057719 232 : 4250, 4027
7465 12:46:28.060477 236 : 4360, 4138
7466 12:46:28.060898 240 : 4361, 4137
7467 12:46:28.063954 244 : 4250, 4026
7468 12:46:28.064424 248 : 4250, 4027
7469 12:46:28.067607 252 : 4363, 4140
7470 12:46:28.068062 256 : 4250, 4027
7471 12:46:28.070632 260 : 4253, 4026
7472 12:46:28.071051 264 : 4250, 4027
7473 12:46:28.073607 268 : 4252, 4030
7474 12:46:28.074026 272 : 4250, 4027
7475 12:46:28.074361 276 : 4250, 4026
7476 12:46:28.077146 280 : 4361, 4137
7477 12:46:28.077564 284 : 4250, 4027
7478 12:46:28.080328 288 : 4250, 4027
7479 12:46:28.080746 292 : 4360, 4137
7480 12:46:28.083517 296 : 4250, 4026
7481 12:46:28.083936 300 : 4250, 4027
7482 12:46:28.086787 304 : 4363, 4140
7483 12:46:28.087208 308 : 4249, 4027
7484 12:46:28.090240 312 : 4250, 4026
7485 12:46:28.090660 316 : 4250, 4027
7486 12:46:28.093481 320 : 4252, 4030
7487 12:46:28.093899 324 : 4249, 4027
7488 12:46:28.096976 328 : 4250, 4026
7489 12:46:28.097397 332 : 4363, 4081
7490 12:46:28.100012 336 : 4250, 1954
7491 12:46:28.100464
7492 12:46:28.100792 MIOCK jitter meter ch=0
7493 12:46:28.101097
7494 12:46:28.103864 1T = (336-100) = 236 dly cells
7495 12:46:28.110514 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7496 12:46:28.110930 ==
7497 12:46:28.113222 Dram Type= 6, Freq= 0, CH_0, rank 0
7498 12:46:28.117130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 12:46:28.117548 ==
7500 12:46:28.123703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 12:46:28.126424 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 12:46:28.129675 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 12:46:28.136563 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 12:46:28.146267 [CA 0] Center 43 (13~73) winsize 61
7505 12:46:28.149618 [CA 1] Center 42 (12~73) winsize 62
7506 12:46:28.152727 [CA 2] Center 37 (8~67) winsize 60
7507 12:46:28.156179 [CA 3] Center 37 (8~67) winsize 60
7508 12:46:28.159252 [CA 4] Center 36 (6~66) winsize 61
7509 12:46:28.162776 [CA 5] Center 35 (5~66) winsize 62
7510 12:46:28.163197
7511 12:46:28.165718 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7512 12:46:28.166131
7513 12:46:28.172195 [CATrainingPosCal] consider 1 rank data
7514 12:46:28.172614 u2DelayCellTimex100 = 275/100 ps
7515 12:46:28.179252 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7516 12:46:28.182502 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7517 12:46:28.185807 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7518 12:46:28.189118 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7519 12:46:28.192345 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7520 12:46:28.195508 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7521 12:46:28.196109
7522 12:46:28.198727 CA PerBit enable=1, Macro0, CA PI delay=35
7523 12:46:28.199147
7524 12:46:28.202014 [CBTSetCACLKResult] CA Dly = 35
7525 12:46:28.205367 CS Dly: 11 (0~42)
7526 12:46:28.208930 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 12:46:28.212071 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 12:46:28.212488 ==
7529 12:46:28.215355 Dram Type= 6, Freq= 0, CH_0, rank 1
7530 12:46:28.221937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 12:46:28.222357 ==
7532 12:46:28.224614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 12:46:28.231601 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 12:46:28.234671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 12:46:28.241577 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 12:46:28.249735 [CA 0] Center 43 (13~74) winsize 62
7537 12:46:28.253171 [CA 1] Center 43 (13~73) winsize 61
7538 12:46:28.256102 [CA 2] Center 38 (9~68) winsize 60
7539 12:46:28.259302 [CA 3] Center 38 (9~68) winsize 60
7540 12:46:28.262755 [CA 4] Center 36 (6~67) winsize 62
7541 12:46:28.266050 [CA 5] Center 36 (6~66) winsize 61
7542 12:46:28.266469
7543 12:46:28.269481 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7544 12:46:28.269900
7545 12:46:28.272737 [CATrainingPosCal] consider 2 rank data
7546 12:46:28.275919 u2DelayCellTimex100 = 275/100 ps
7547 12:46:28.282232 CA0 delay=43 (13~73),Diff = 7 PI (24 cell)
7548 12:46:28.285640 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7549 12:46:28.289220 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7550 12:46:28.292646 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7551 12:46:28.295571 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7552 12:46:28.298732 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7553 12:46:28.299151
7554 12:46:28.301964 CA PerBit enable=1, Macro0, CA PI delay=36
7555 12:46:28.302413
7556 12:46:28.305582 [CBTSetCACLKResult] CA Dly = 36
7557 12:46:28.308808 CS Dly: 11 (0~43)
7558 12:46:28.312356 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 12:46:28.315301 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 12:46:28.315849
7561 12:46:28.318968 ----->DramcWriteLeveling(PI) begin...
7562 12:46:28.319391 ==
7563 12:46:28.322627 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 12:46:28.328698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 12:46:28.329119 ==
7566 12:46:28.331849 Write leveling (Byte 0): 34 => 34
7567 12:46:28.334858 Write leveling (Byte 1): 25 => 25
7568 12:46:28.338122 DramcWriteLeveling(PI) end<-----
7569 12:46:28.338536
7570 12:46:28.338862 ==
7571 12:46:28.341847 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 12:46:28.344824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 12:46:28.345246 ==
7574 12:46:28.349024 [Gating] SW mode calibration
7575 12:46:28.354738 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7576 12:46:28.361495 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7577 12:46:28.364778 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 12:46:28.367980 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 12:46:28.374420 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7580 12:46:28.377766 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7581 12:46:28.381010 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7582 12:46:28.388015 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7583 12:46:28.390878 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 12:46:28.394243 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 12:46:28.400777 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 12:46:28.403934 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7587 12:46:28.407124 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7588 12:46:28.413847 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7589 12:46:28.417401 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7590 12:46:28.420840 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7591 12:46:28.427433 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 12:46:28.429915 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 12:46:28.433725 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 12:46:28.440363 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 12:46:28.443154 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7596 12:46:28.446930 1 6 12 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
7597 12:46:28.453473 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7598 12:46:28.456118 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
7599 12:46:28.459576 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 12:46:28.466358 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 12:46:28.469968 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 12:46:28.472662 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 12:46:28.479597 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 12:46:28.483080 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7605 12:46:28.485606 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7606 12:46:28.492352 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7607 12:46:28.495707 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7608 12:46:28.498996 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 12:46:28.505929 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 12:46:28.509026 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 12:46:28.512433 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 12:46:28.518438 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 12:46:28.522023 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 12:46:28.525787 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 12:46:28.532190 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 12:46:28.535247 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 12:46:28.538385 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 12:46:28.545242 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 12:46:28.548388 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7620 12:46:28.551714 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7621 12:46:28.554766 Total UI for P1: 0, mck2ui 16
7622 12:46:28.558435 best dqsien dly found for B0: ( 1, 9, 8)
7623 12:46:28.564791 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7624 12:46:28.568473 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7625 12:46:28.571342 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7626 12:46:28.577687 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 12:46:28.580955 Total UI for P1: 0, mck2ui 16
7628 12:46:28.584600 best dqsien dly found for B1: ( 1, 9, 22)
7629 12:46:28.587535 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7630 12:46:28.591057 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7631 12:46:28.591475
7632 12:46:28.594276 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7633 12:46:28.597601 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7634 12:46:28.601143 [Gating] SW calibration Done
7635 12:46:28.601560 ==
7636 12:46:28.604299 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 12:46:28.607541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 12:46:28.608138 ==
7639 12:46:28.610622 RX Vref Scan: 0
7640 12:46:28.611026
7641 12:46:28.614039 RX Vref 0 -> 0, step: 1
7642 12:46:28.614419
7643 12:46:28.614781 RX Delay 0 -> 252, step: 8
7644 12:46:28.620506 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7645 12:46:28.624428 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7646 12:46:28.627236 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7647 12:46:28.630578 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7648 12:46:28.634365 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7649 12:46:28.640301 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7650 12:46:28.643554 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7651 12:46:28.646785 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7652 12:46:28.650208 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7653 12:46:28.656710 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7654 12:46:28.660074 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7655 12:46:28.663112 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7656 12:46:28.666986 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7657 12:46:28.670161 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7658 12:46:28.676535 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7659 12:46:28.680077 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7660 12:46:28.680497 ==
7661 12:46:28.683551 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 12:46:28.686637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 12:46:28.687059 ==
7664 12:46:28.690169 DQS Delay:
7665 12:46:28.690584 DQS0 = 0, DQS1 = 0
7666 12:46:28.690913 DQM Delay:
7667 12:46:28.692929 DQM0 = 131, DQM1 = 126
7668 12:46:28.693346 DQ Delay:
7669 12:46:28.696609 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
7670 12:46:28.699605 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7671 12:46:28.706444 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7672 12:46:28.709924 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7673 12:46:28.710371
7674 12:46:28.710693
7675 12:46:28.711044 ==
7676 12:46:28.712845 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 12:46:28.716453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 12:46:28.716818 ==
7679 12:46:28.717176
7680 12:46:28.717471
7681 12:46:28.719630 TX Vref Scan disable
7682 12:46:28.722673 == TX Byte 0 ==
7683 12:46:28.726252 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7684 12:46:28.729587 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7685 12:46:28.732289 == TX Byte 1 ==
7686 12:46:28.735963 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7687 12:46:28.739199 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7688 12:46:28.739610 ==
7689 12:46:28.742197 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 12:46:28.746459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 12:46:28.749117 ==
7692 12:46:28.761011
7693 12:46:28.764454 TX Vref early break, caculate TX vref
7694 12:46:28.767869 TX Vref=16, minBit 8, minWin=22, winSum=369
7695 12:46:28.770880 TX Vref=18, minBit 7, minWin=22, winSum=380
7696 12:46:28.774378 TX Vref=20, minBit 7, minWin=23, winSum=386
7697 12:46:28.777500 TX Vref=22, minBit 1, minWin=24, winSum=394
7698 12:46:28.781004 TX Vref=24, minBit 8, minWin=24, winSum=408
7699 12:46:28.787169 TX Vref=26, minBit 1, minWin=25, winSum=415
7700 12:46:28.790688 TX Vref=28, minBit 1, minWin=25, winSum=417
7701 12:46:28.793852 TX Vref=30, minBit 0, minWin=25, winSum=413
7702 12:46:28.797223 TX Vref=32, minBit 7, minWin=24, winSum=409
7703 12:46:28.800322 TX Vref=34, minBit 1, minWin=24, winSum=393
7704 12:46:28.806848 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 28
7705 12:46:28.807286
7706 12:46:28.810572 Final TX Range 0 Vref 28
7707 12:46:28.810997
7708 12:46:28.811396 ==
7709 12:46:28.813935 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 12:46:28.817615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 12:46:28.818177 ==
7712 12:46:28.818575
7713 12:46:28.818891
7714 12:46:28.820002 TX Vref Scan disable
7715 12:46:28.827351 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7716 12:46:28.827837 == TX Byte 0 ==
7717 12:46:28.830389 u2DelayCellOfst[0]=10 cells (3 PI)
7718 12:46:28.833740 u2DelayCellOfst[1]=14 cells (4 PI)
7719 12:46:28.837204 u2DelayCellOfst[2]=10 cells (3 PI)
7720 12:46:28.840403 u2DelayCellOfst[3]=10 cells (3 PI)
7721 12:46:28.843356 u2DelayCellOfst[4]=7 cells (2 PI)
7722 12:46:28.846932 u2DelayCellOfst[5]=0 cells (0 PI)
7723 12:46:28.850517 u2DelayCellOfst[6]=14 cells (4 PI)
7724 12:46:28.853276 u2DelayCellOfst[7]=14 cells (4 PI)
7725 12:46:28.856608 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7726 12:46:28.859692 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7727 12:46:28.863174 == TX Byte 1 ==
7728 12:46:28.866276 u2DelayCellOfst[8]=0 cells (0 PI)
7729 12:46:28.869870 u2DelayCellOfst[9]=0 cells (0 PI)
7730 12:46:28.873075 u2DelayCellOfst[10]=3 cells (1 PI)
7731 12:46:28.876518 u2DelayCellOfst[11]=0 cells (0 PI)
7732 12:46:28.877001 u2DelayCellOfst[12]=7 cells (2 PI)
7733 12:46:28.879754 u2DelayCellOfst[13]=7 cells (2 PI)
7734 12:46:28.882755 u2DelayCellOfst[14]=14 cells (4 PI)
7735 12:46:28.886351 u2DelayCellOfst[15]=10 cells (3 PI)
7736 12:46:28.892541 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7737 12:46:28.896180 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7738 12:46:28.896641 DramC Write-DBI on
7739 12:46:28.899869 ==
7740 12:46:28.902709 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 12:46:28.906152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 12:46:28.906606 ==
7743 12:46:28.907041
7744 12:46:28.907451
7745 12:46:28.909575 TX Vref Scan disable
7746 12:46:28.909995 == TX Byte 0 ==
7747 12:46:28.915505 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7748 12:46:28.915924 == TX Byte 1 ==
7749 12:46:28.918960 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7750 12:46:28.922189 DramC Write-DBI off
7751 12:46:28.922604
7752 12:46:28.922934 [DATLAT]
7753 12:46:28.925498 Freq=1600, CH0 RK0
7754 12:46:28.925921
7755 12:46:28.926253 DATLAT Default: 0xf
7756 12:46:28.928603 0, 0xFFFF, sum = 0
7757 12:46:28.929026 1, 0xFFFF, sum = 0
7758 12:46:28.931853 2, 0xFFFF, sum = 0
7759 12:46:28.935509 3, 0xFFFF, sum = 0
7760 12:46:28.935931 4, 0xFFFF, sum = 0
7761 12:46:28.938417 5, 0xFFFF, sum = 0
7762 12:46:28.938843 6, 0xFFFF, sum = 0
7763 12:46:28.941925 7, 0xFFFF, sum = 0
7764 12:46:28.942350 8, 0xFFFF, sum = 0
7765 12:46:28.945351 9, 0xFFFF, sum = 0
7766 12:46:28.945778 10, 0xFFFF, sum = 0
7767 12:46:28.948651 11, 0xFFFF, sum = 0
7768 12:46:28.949077 12, 0xFFFF, sum = 0
7769 12:46:28.952363 13, 0xFFFF, sum = 0
7770 12:46:28.952789 14, 0x0, sum = 1
7771 12:46:28.955149 15, 0x0, sum = 2
7772 12:46:28.955575 16, 0x0, sum = 3
7773 12:46:28.958273 17, 0x0, sum = 4
7774 12:46:28.958704 best_step = 15
7775 12:46:28.959093
7776 12:46:28.959432 ==
7777 12:46:28.961715 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 12:46:28.967996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 12:46:28.968533 ==
7780 12:46:28.968870 RX Vref Scan: 1
7781 12:46:28.969227
7782 12:46:28.971391 Set Vref Range= 24 -> 127
7783 12:46:28.971786
7784 12:46:28.975403 RX Vref 24 -> 127, step: 1
7785 12:46:28.975874
7786 12:46:28.976262 RX Delay 11 -> 252, step: 4
7787 12:46:28.978393
7788 12:46:28.978876 Set Vref, RX VrefLevel [Byte0]: 24
7789 12:46:28.981787 [Byte1]: 24
7790 12:46:28.985788
7791 12:46:28.986234 Set Vref, RX VrefLevel [Byte0]: 25
7792 12:46:28.988842 [Byte1]: 25
7793 12:46:28.993075
7794 12:46:28.993492 Set Vref, RX VrefLevel [Byte0]: 26
7795 12:46:28.996642 [Byte1]: 26
7796 12:46:29.000587
7797 12:46:29.001002 Set Vref, RX VrefLevel [Byte0]: 27
7798 12:46:29.004183 [Byte1]: 27
7799 12:46:29.008237
7800 12:46:29.008775 Set Vref, RX VrefLevel [Byte0]: 28
7801 12:46:29.011846 [Byte1]: 28
7802 12:46:29.016190
7803 12:46:29.016601 Set Vref, RX VrefLevel [Byte0]: 29
7804 12:46:29.019369 [Byte1]: 29
7805 12:46:29.023696
7806 12:46:29.024139 Set Vref, RX VrefLevel [Byte0]: 30
7807 12:46:29.026922 [Byte1]: 30
7808 12:46:29.031139
7809 12:46:29.031549 Set Vref, RX VrefLevel [Byte0]: 31
7810 12:46:29.034538 [Byte1]: 31
7811 12:46:29.039157
7812 12:46:29.039569 Set Vref, RX VrefLevel [Byte0]: 32
7813 12:46:29.042642 [Byte1]: 32
7814 12:46:29.046409
7815 12:46:29.046966 Set Vref, RX VrefLevel [Byte0]: 33
7816 12:46:29.050260 [Byte1]: 33
7817 12:46:29.054371
7818 12:46:29.054781 Set Vref, RX VrefLevel [Byte0]: 34
7819 12:46:29.057724 [Byte1]: 34
7820 12:46:29.062164
7821 12:46:29.062577 Set Vref, RX VrefLevel [Byte0]: 35
7822 12:46:29.065084 [Byte1]: 35
7823 12:46:29.069451
7824 12:46:29.069865 Set Vref, RX VrefLevel [Byte0]: 36
7825 12:46:29.073002 [Byte1]: 36
7826 12:46:29.077013
7827 12:46:29.077427 Set Vref, RX VrefLevel [Byte0]: 37
7828 12:46:29.080201 [Byte1]: 37
7829 12:46:29.084777
7830 12:46:29.085189 Set Vref, RX VrefLevel [Byte0]: 38
7831 12:46:29.088115 [Byte1]: 38
7832 12:46:29.092204
7833 12:46:29.092619 Set Vref, RX VrefLevel [Byte0]: 39
7834 12:46:29.095249 [Byte1]: 39
7835 12:46:29.099983
7836 12:46:29.100449 Set Vref, RX VrefLevel [Byte0]: 40
7837 12:46:29.103093 [Byte1]: 40
7838 12:46:29.107359
7839 12:46:29.107770 Set Vref, RX VrefLevel [Byte0]: 41
7840 12:46:29.111201 [Byte1]: 41
7841 12:46:29.115311
7842 12:46:29.115724 Set Vref, RX VrefLevel [Byte0]: 42
7843 12:46:29.118506 [Byte1]: 42
7844 12:46:29.123014
7845 12:46:29.123427 Set Vref, RX VrefLevel [Byte0]: 43
7846 12:46:29.125941 [Byte1]: 43
7847 12:46:29.130347
7848 12:46:29.130764 Set Vref, RX VrefLevel [Byte0]: 44
7849 12:46:29.133413 [Byte1]: 44
7850 12:46:29.138110
7851 12:46:29.138529 Set Vref, RX VrefLevel [Byte0]: 45
7852 12:46:29.141141 [Byte1]: 45
7853 12:46:29.145364
7854 12:46:29.145838 Set Vref, RX VrefLevel [Byte0]: 46
7855 12:46:29.148920 [Byte1]: 46
7856 12:46:29.153878
7857 12:46:29.154296 Set Vref, RX VrefLevel [Byte0]: 47
7858 12:46:29.156921 [Byte1]: 47
7859 12:46:29.160937
7860 12:46:29.161353 Set Vref, RX VrefLevel [Byte0]: 48
7861 12:46:29.163839 [Byte1]: 48
7862 12:46:29.168629
7863 12:46:29.169044 Set Vref, RX VrefLevel [Byte0]: 49
7864 12:46:29.171817 [Byte1]: 49
7865 12:46:29.175773
7866 12:46:29.179342 Set Vref, RX VrefLevel [Byte0]: 50
7867 12:46:29.182477 [Byte1]: 50
7868 12:46:29.182899
7869 12:46:29.186206 Set Vref, RX VrefLevel [Byte0]: 51
7870 12:46:29.189186 [Byte1]: 51
7871 12:46:29.189636
7872 12:46:29.192397 Set Vref, RX VrefLevel [Byte0]: 52
7873 12:46:29.195491 [Byte1]: 52
7874 12:46:29.198801
7875 12:46:29.199262 Set Vref, RX VrefLevel [Byte0]: 53
7876 12:46:29.202105 [Byte1]: 53
7877 12:46:29.206656
7878 12:46:29.207071 Set Vref, RX VrefLevel [Byte0]: 54
7879 12:46:29.209562 [Byte1]: 54
7880 12:46:29.214182
7881 12:46:29.214597 Set Vref, RX VrefLevel [Byte0]: 55
7882 12:46:29.217248 [Byte1]: 55
7883 12:46:29.221686
7884 12:46:29.222103 Set Vref, RX VrefLevel [Byte0]: 56
7885 12:46:29.225291 [Byte1]: 56
7886 12:46:29.229106
7887 12:46:29.229524 Set Vref, RX VrefLevel [Byte0]: 57
7888 12:46:29.233079 [Byte1]: 57
7889 12:46:29.236537
7890 12:46:29.236954 Set Vref, RX VrefLevel [Byte0]: 58
7891 12:46:29.240097 [Byte1]: 58
7892 12:46:29.244599
7893 12:46:29.245023 Set Vref, RX VrefLevel [Byte0]: 59
7894 12:46:29.247539 [Byte1]: 59
7895 12:46:29.252131
7896 12:46:29.252684 Set Vref, RX VrefLevel [Byte0]: 60
7897 12:46:29.255972 [Byte1]: 60
7898 12:46:29.260069
7899 12:46:29.260492 Set Vref, RX VrefLevel [Byte0]: 61
7900 12:46:29.263530 [Byte1]: 61
7901 12:46:29.267510
7902 12:46:29.267928 Set Vref, RX VrefLevel [Byte0]: 62
7903 12:46:29.270916 [Byte1]: 62
7904 12:46:29.274852
7905 12:46:29.275271 Set Vref, RX VrefLevel [Byte0]: 63
7906 12:46:29.278742 [Byte1]: 63
7907 12:46:29.282387
7908 12:46:29.282808 Set Vref, RX VrefLevel [Byte0]: 64
7909 12:46:29.285706 [Byte1]: 64
7910 12:46:29.290415
7911 12:46:29.290836 Set Vref, RX VrefLevel [Byte0]: 65
7912 12:46:29.293467 [Byte1]: 65
7913 12:46:29.297692
7914 12:46:29.298114 Set Vref, RX VrefLevel [Byte0]: 66
7915 12:46:29.300808 [Byte1]: 66
7916 12:46:29.305446
7917 12:46:29.305891 Set Vref, RX VrefLevel [Byte0]: 67
7918 12:46:29.308822 [Byte1]: 67
7919 12:46:29.313372
7920 12:46:29.313794 Set Vref, RX VrefLevel [Byte0]: 68
7921 12:46:29.316476 [Byte1]: 68
7922 12:46:29.320597
7923 12:46:29.321018 Set Vref, RX VrefLevel [Byte0]: 69
7924 12:46:29.323740 [Byte1]: 69
7925 12:46:29.328228
7926 12:46:29.328648 Set Vref, RX VrefLevel [Byte0]: 70
7927 12:46:29.331535 [Byte1]: 70
7928 12:46:29.336324
7929 12:46:29.336753 Set Vref, RX VrefLevel [Byte0]: 71
7930 12:46:29.339243 [Byte1]: 71
7931 12:46:29.343481
7932 12:46:29.343902 Set Vref, RX VrefLevel [Byte0]: 72
7933 12:46:29.347082 [Byte1]: 72
7934 12:46:29.351500
7935 12:46:29.351922 Set Vref, RX VrefLevel [Byte0]: 73
7936 12:46:29.354187 [Byte1]: 73
7937 12:46:29.358684
7938 12:46:29.359125 Final RX Vref Byte 0 = 53 to rank0
7939 12:46:29.361729 Final RX Vref Byte 1 = 59 to rank0
7940 12:46:29.365146 Final RX Vref Byte 0 = 53 to rank1
7941 12:46:29.368548 Final RX Vref Byte 1 = 59 to rank1==
7942 12:46:29.371677 Dram Type= 6, Freq= 0, CH_0, rank 0
7943 12:46:29.378202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 12:46:29.378631 ==
7945 12:46:29.378964 DQS Delay:
7946 12:46:29.381830 DQS0 = 0, DQS1 = 0
7947 12:46:29.382251 DQM Delay:
7948 12:46:29.382587 DQM0 = 128, DQM1 = 124
7949 12:46:29.384839 DQ Delay:
7950 12:46:29.388405 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7951 12:46:29.391383 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7952 12:46:29.395277 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7953 12:46:29.398430 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7954 12:46:29.398847
7955 12:46:29.399316
7956 12:46:29.399710
7957 12:46:29.401522 [DramC_TX_OE_Calibration] TA2
7958 12:46:29.405475 Original DQ_B0 (3 6) =30, OEN = 27
7959 12:46:29.408621 Original DQ_B1 (3 6) =30, OEN = 27
7960 12:46:29.411513 24, 0x0, End_B0=24 End_B1=24
7961 12:46:29.414557 25, 0x0, End_B0=25 End_B1=25
7962 12:46:29.414987 26, 0x0, End_B0=26 End_B1=26
7963 12:46:29.418009 27, 0x0, End_B0=27 End_B1=27
7964 12:46:29.421055 28, 0x0, End_B0=28 End_B1=28
7965 12:46:29.424509 29, 0x0, End_B0=29 End_B1=29
7966 12:46:29.428006 30, 0x0, End_B0=30 End_B1=30
7967 12:46:29.428496 31, 0x4141, End_B0=30 End_B1=30
7968 12:46:29.431061 Byte0 end_step=30 best_step=27
7969 12:46:29.434776 Byte1 end_step=30 best_step=27
7970 12:46:29.437780 Byte0 TX OE(2T, 0.5T) = (3, 3)
7971 12:46:29.441174 Byte1 TX OE(2T, 0.5T) = (3, 3)
7972 12:46:29.441597
7973 12:46:29.441930
7974 12:46:29.447538 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7975 12:46:29.450718 CH0 RK0: MR19=303, MR18=1714
7976 12:46:29.457131 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
7977 12:46:29.457553
7978 12:46:29.460527 ----->DramcWriteLeveling(PI) begin...
7979 12:46:29.460953 ==
7980 12:46:29.463415 Dram Type= 6, Freq= 0, CH_0, rank 1
7981 12:46:29.466890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 12:46:29.469974 ==
7983 12:46:29.470386 Write leveling (Byte 0): 34 => 34
7984 12:46:29.473815 Write leveling (Byte 1): 27 => 27
7985 12:46:29.477026 DramcWriteLeveling(PI) end<-----
7986 12:46:29.477440
7987 12:46:29.477767 ==
7988 12:46:29.480487 Dram Type= 6, Freq= 0, CH_0, rank 1
7989 12:46:29.486725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 12:46:29.487141 ==
7991 12:46:29.490416 [Gating] SW mode calibration
7992 12:46:29.497136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7993 12:46:29.499962 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7994 12:46:29.507247 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 12:46:29.509929 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 12:46:29.513049 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7997 12:46:29.519730 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7998 12:46:29.523092 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7999 12:46:29.526272 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8000 12:46:29.533059 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 12:46:29.536525 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 12:46:29.539762 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 12:46:29.546094 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8004 12:46:29.549423 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
8005 12:46:29.552769 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
8006 12:46:29.559893 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8007 12:46:29.562301 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8008 12:46:29.565944 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 12:46:29.572838 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 12:46:29.575745 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 12:46:29.579201 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 12:46:29.585403 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8013 12:46:29.589234 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8014 12:46:29.592112 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8015 12:46:29.598756 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 12:46:29.601813 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 12:46:29.605471 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 12:46:29.611615 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 12:46:29.615048 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8020 12:46:29.618662 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8021 12:46:29.624610 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8022 12:46:29.628008 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8023 12:46:29.631818 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8024 12:46:29.638277 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8025 12:46:29.641360 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 12:46:29.644661 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 12:46:29.650974 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 12:46:29.654438 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 12:46:29.657622 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 12:46:29.664165 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 12:46:29.667499 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 12:46:29.670833 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 12:46:29.677867 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 12:46:29.681075 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 12:46:29.684949 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 12:46:29.690317 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8037 12:46:29.693922 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8038 12:46:29.697066 Total UI for P1: 0, mck2ui 16
8039 12:46:29.700148 best dqsien dly found for B0: ( 1, 9, 8)
8040 12:46:29.703687 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8041 12:46:29.710121 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8042 12:46:29.713675 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 12:46:29.716954 Total UI for P1: 0, mck2ui 16
8044 12:46:29.720026 best dqsien dly found for B1: ( 1, 9, 18)
8045 12:46:29.723552 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8046 12:46:29.726468 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8047 12:46:29.726884
8048 12:46:29.729979 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8049 12:46:29.737115 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8050 12:46:29.737528 [Gating] SW calibration Done
8051 12:46:29.737857 ==
8052 12:46:29.739841 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 12:46:29.746604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 12:46:29.747132 ==
8055 12:46:29.747470 RX Vref Scan: 0
8056 12:46:29.747776
8057 12:46:29.749732 RX Vref 0 -> 0, step: 1
8058 12:46:29.750144
8059 12:46:29.753064 RX Delay 0 -> 252, step: 8
8060 12:46:29.756356 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8061 12:46:29.759499 iDelay=192, Bit 1, Center 131 (72 ~ 191) 120
8062 12:46:29.762760 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8063 12:46:29.769628 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8064 12:46:29.772817 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8065 12:46:29.775872 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8066 12:46:29.779060 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8067 12:46:29.782339 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8068 12:46:29.788902 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8069 12:46:29.792266 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
8070 12:46:29.795569 iDelay=192, Bit 10, Center 127 (72 ~ 183) 112
8071 12:46:29.799025 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8072 12:46:29.802674 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
8073 12:46:29.809141 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8074 12:46:29.812236 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8075 12:46:29.815480 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8076 12:46:29.815909 ==
8077 12:46:29.818592 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 12:46:29.825558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 12:46:29.825959 ==
8080 12:46:29.826420 DQS Delay:
8081 12:46:29.826940 DQS0 = 0, DQS1 = 0
8082 12:46:29.828715 DQM Delay:
8083 12:46:29.829208 DQM0 = 130, DQM1 = 127
8084 12:46:29.832140 DQ Delay:
8085 12:46:29.835188 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8086 12:46:29.838299 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8087 12:46:29.842113 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8088 12:46:29.845139 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8089 12:46:29.845556
8090 12:46:29.845883
8091 12:46:29.846189 ==
8092 12:46:29.848518 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 12:46:29.851790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 12:46:29.855118 ==
8095 12:46:29.855536
8096 12:46:29.855902
8097 12:46:29.856442 TX Vref Scan disable
8098 12:46:29.858429 == TX Byte 0 ==
8099 12:46:29.861639 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8100 12:46:29.864858 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8101 12:46:29.868575 == TX Byte 1 ==
8102 12:46:29.871769 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8103 12:46:29.874775 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8104 12:46:29.878323 ==
8105 12:46:29.881626 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 12:46:29.884610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 12:46:29.885031 ==
8108 12:46:29.898817
8109 12:46:29.902229 TX Vref early break, caculate TX vref
8110 12:46:29.905470 TX Vref=16, minBit 9, minWin=23, winSum=384
8111 12:46:29.908494 TX Vref=18, minBit 1, minWin=23, winSum=388
8112 12:46:29.911819 TX Vref=20, minBit 2, minWin=24, winSum=401
8113 12:46:29.915712 TX Vref=22, minBit 9, minWin=24, winSum=404
8114 12:46:29.918464 TX Vref=24, minBit 2, minWin=25, winSum=415
8115 12:46:29.925307 TX Vref=26, minBit 3, minWin=25, winSum=420
8116 12:46:29.928379 TX Vref=28, minBit 0, minWin=26, winSum=426
8117 12:46:29.932332 TX Vref=30, minBit 2, minWin=25, winSum=420
8118 12:46:29.934864 TX Vref=32, minBit 1, minWin=24, winSum=407
8119 12:46:29.938186 TX Vref=34, minBit 1, minWin=24, winSum=404
8120 12:46:29.944958 TX Vref=36, minBit 0, minWin=23, winSum=392
8121 12:46:29.948277 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8122 12:46:29.948692
8123 12:46:29.951620 Final TX Range 0 Vref 28
8124 12:46:29.952227
8125 12:46:29.952570 ==
8126 12:46:29.954819 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 12:46:29.958056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 12:46:29.958479 ==
8129 12:46:29.961254
8130 12:46:29.961668
8131 12:46:29.961999 TX Vref Scan disable
8132 12:46:29.967979 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8133 12:46:29.968425 == TX Byte 0 ==
8134 12:46:29.971135 u2DelayCellOfst[0]=10 cells (3 PI)
8135 12:46:29.974549 u2DelayCellOfst[1]=14 cells (4 PI)
8136 12:46:29.977895 u2DelayCellOfst[2]=7 cells (2 PI)
8137 12:46:29.981241 u2DelayCellOfst[3]=10 cells (3 PI)
8138 12:46:29.984646 u2DelayCellOfst[4]=7 cells (2 PI)
8139 12:46:29.988228 u2DelayCellOfst[5]=0 cells (0 PI)
8140 12:46:29.991096 u2DelayCellOfst[6]=14 cells (4 PI)
8141 12:46:29.994591 u2DelayCellOfst[7]=14 cells (4 PI)
8142 12:46:29.997441 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8143 12:46:30.001037 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8144 12:46:30.004456 == TX Byte 1 ==
8145 12:46:30.007150 u2DelayCellOfst[8]=3 cells (1 PI)
8146 12:46:30.010580 u2DelayCellOfst[9]=0 cells (0 PI)
8147 12:46:30.013830 u2DelayCellOfst[10]=3 cells (1 PI)
8148 12:46:30.017292 u2DelayCellOfst[11]=3 cells (1 PI)
8149 12:46:30.021256 u2DelayCellOfst[12]=10 cells (3 PI)
8150 12:46:30.023864 u2DelayCellOfst[13]=10 cells (3 PI)
8151 12:46:30.027219 u2DelayCellOfst[14]=14 cells (4 PI)
8152 12:46:30.030867 u2DelayCellOfst[15]=14 cells (4 PI)
8153 12:46:30.033654 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8154 12:46:30.037206 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8155 12:46:30.040522 DramC Write-DBI on
8156 12:46:30.041102 ==
8157 12:46:30.043469 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 12:46:30.046609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 12:46:30.047193 ==
8160 12:46:30.047664
8161 12:46:30.048221
8162 12:46:30.049993 TX Vref Scan disable
8163 12:46:30.053488 == TX Byte 0 ==
8164 12:46:30.056519 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8165 12:46:30.056978 == TX Byte 1 ==
8166 12:46:30.063700 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8167 12:46:30.064240 DramC Write-DBI off
8168 12:46:30.064606
8169 12:46:30.064948 [DATLAT]
8170 12:46:30.066844 Freq=1600, CH0 RK1
8171 12:46:30.067404
8172 12:46:30.069991 DATLAT Default: 0xf
8173 12:46:30.070519 0, 0xFFFF, sum = 0
8174 12:46:30.073396 1, 0xFFFF, sum = 0
8175 12:46:30.073874 2, 0xFFFF, sum = 0
8176 12:46:30.076633 3, 0xFFFF, sum = 0
8177 12:46:30.077080 4, 0xFFFF, sum = 0
8178 12:46:30.079942 5, 0xFFFF, sum = 0
8179 12:46:30.080453 6, 0xFFFF, sum = 0
8180 12:46:30.083659 7, 0xFFFF, sum = 0
8181 12:46:30.084157 8, 0xFFFF, sum = 0
8182 12:46:30.086672 9, 0xFFFF, sum = 0
8183 12:46:30.087149 10, 0xFFFF, sum = 0
8184 12:46:30.089672 11, 0xFFFF, sum = 0
8185 12:46:30.090268 12, 0xFFFF, sum = 0
8186 12:46:30.093249 13, 0xFFFF, sum = 0
8187 12:46:30.093710 14, 0x0, sum = 1
8188 12:46:30.096489 15, 0x0, sum = 2
8189 12:46:30.096950 16, 0x0, sum = 3
8190 12:46:30.100239 17, 0x0, sum = 4
8191 12:46:30.100855 best_step = 15
8192 12:46:30.101298
8193 12:46:30.101810 ==
8194 12:46:30.103106 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 12:46:30.109178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 12:46:30.109698 ==
8197 12:46:30.110147 RX Vref Scan: 0
8198 12:46:30.110604
8199 12:46:30.112538 RX Vref 0 -> 0, step: 1
8200 12:46:30.112985
8201 12:46:30.115641 RX Delay 19 -> 252, step: 4
8202 12:46:30.119243 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8203 12:46:30.122332 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8204 12:46:30.129044 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8205 12:46:30.132317 iDelay=191, Bit 3, Center 124 (71 ~ 178) 108
8206 12:46:30.135954 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8207 12:46:30.138731 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8208 12:46:30.142669 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8209 12:46:30.148504 iDelay=191, Bit 7, Center 136 (87 ~ 186) 100
8210 12:46:30.152534 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8211 12:46:30.155541 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8212 12:46:30.158602 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8213 12:46:30.162415 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8214 12:46:30.168878 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8215 12:46:30.171556 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8216 12:46:30.175094 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8217 12:46:30.178498 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8218 12:46:30.181996 ==
8219 12:46:30.182468 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 12:46:30.188486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 12:46:30.189037 ==
8222 12:46:30.189592 DQS Delay:
8223 12:46:30.191600 DQS0 = 0, DQS1 = 0
8224 12:46:30.192164 DQM Delay:
8225 12:46:30.194647 DQM0 = 128, DQM1 = 124
8226 12:46:30.195121 DQ Delay:
8227 12:46:30.198044 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =124
8228 12:46:30.201210 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =136
8229 12:46:30.204662 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8230 12:46:30.207885 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8231 12:46:30.208439
8232 12:46:30.208817
8233 12:46:30.209186
8234 12:46:30.211418 [DramC_TX_OE_Calibration] TA2
8235 12:46:30.214575 Original DQ_B0 (3 6) =30, OEN = 27
8236 12:46:30.218018 Original DQ_B1 (3 6) =30, OEN = 27
8237 12:46:30.221178 24, 0x0, End_B0=24 End_B1=24
8238 12:46:30.224872 25, 0x0, End_B0=25 End_B1=25
8239 12:46:30.225359 26, 0x0, End_B0=26 End_B1=26
8240 12:46:30.228387 27, 0x0, End_B0=27 End_B1=27
8241 12:46:30.230866 28, 0x0, End_B0=28 End_B1=28
8242 12:46:30.234340 29, 0x0, End_B0=29 End_B1=29
8243 12:46:30.237715 30, 0x0, End_B0=30 End_B1=30
8244 12:46:30.238335 31, 0x4141, End_B0=30 End_B1=30
8245 12:46:30.241395 Byte0 end_step=30 best_step=27
8246 12:46:30.244228 Byte1 end_step=30 best_step=27
8247 12:46:30.247420 Byte0 TX OE(2T, 0.5T) = (3, 3)
8248 12:46:30.250591 Byte1 TX OE(2T, 0.5T) = (3, 3)
8249 12:46:30.251139
8250 12:46:30.251652
8251 12:46:30.257174 [DQSOSCAuto] RK1, (LSB)MR18= 0x110f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8252 12:46:30.260338 CH0 RK1: MR19=303, MR18=110F
8253 12:46:30.267228 CH0_RK1: MR19=0x303, MR18=0x110F, DQSOSC=401, MR23=63, INC=22, DEC=15
8254 12:46:30.270248 [RxdqsGatingPostProcess] freq 1600
8255 12:46:30.277167 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8256 12:46:30.279994 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 12:46:30.284019 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 12:46:30.286977 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 12:46:30.287399 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 12:46:30.290307 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 12:46:30.293527 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 12:46:30.297614 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 12:46:30.300379 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 12:46:30.303584 Pre-setting of DQS Precalculation
8265 12:46:30.310293 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8266 12:46:30.310843 ==
8267 12:46:30.313671 Dram Type= 6, Freq= 0, CH_1, rank 0
8268 12:46:30.316447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 12:46:30.316933 ==
8270 12:46:30.323798 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 12:46:30.326214 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 12:46:30.329671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 12:46:30.336014 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 12:46:30.345115 [CA 0] Center 42 (13~72) winsize 60
8275 12:46:30.348334 [CA 1] Center 42 (13~72) winsize 60
8276 12:46:30.351836 [CA 2] Center 38 (9~68) winsize 60
8277 12:46:30.355069 [CA 3] Center 37 (8~67) winsize 60
8278 12:46:30.358397 [CA 4] Center 38 (9~68) winsize 60
8279 12:46:30.361288 [CA 5] Center 37 (8~67) winsize 60
8280 12:46:30.361713
8281 12:46:30.364782 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8282 12:46:30.365227
8283 12:46:30.368109 [CATrainingPosCal] consider 1 rank data
8284 12:46:30.371245 u2DelayCellTimex100 = 275/100 ps
8285 12:46:30.378090 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8286 12:46:30.381546 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8287 12:46:30.384769 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8288 12:46:30.387720 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8289 12:46:30.391308 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8290 12:46:30.394687 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8291 12:46:30.395242
8292 12:46:30.397722 CA PerBit enable=1, Macro0, CA PI delay=37
8293 12:46:30.398194
8294 12:46:30.401287 [CBTSetCACLKResult] CA Dly = 37
8295 12:46:30.404717 CS Dly: 8 (0~39)
8296 12:46:30.408235 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 12:46:30.411761 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 12:46:30.412371 ==
8299 12:46:30.414186 Dram Type= 6, Freq= 0, CH_1, rank 1
8300 12:46:30.421039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 12:46:30.421479 ==
8302 12:46:30.424163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 12:46:30.430988 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 12:46:30.434398 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 12:46:30.440468 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 12:46:30.448025 [CA 0] Center 41 (12~71) winsize 60
8307 12:46:30.451874 [CA 1] Center 42 (13~71) winsize 59
8308 12:46:30.454997 [CA 2] Center 37 (8~67) winsize 60
8309 12:46:30.458242 [CA 3] Center 36 (7~66) winsize 60
8310 12:46:30.460805 [CA 4] Center 36 (7~66) winsize 60
8311 12:46:30.464438 [CA 5] Center 36 (7~66) winsize 60
8312 12:46:30.464885
8313 12:46:30.467845 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8314 12:46:30.468370
8315 12:46:30.474457 [CATrainingPosCal] consider 2 rank data
8316 12:46:30.474915 u2DelayCellTimex100 = 275/100 ps
8317 12:46:30.481383 CA0 delay=42 (13~71),Diff = 5 PI (17 cell)
8318 12:46:30.484288 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8319 12:46:30.487677 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8320 12:46:30.491097 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8321 12:46:30.494122 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8322 12:46:30.497141 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8323 12:46:30.497573
8324 12:46:30.500538 CA PerBit enable=1, Macro0, CA PI delay=37
8325 12:46:30.501100
8326 12:46:30.503997 [CBTSetCACLKResult] CA Dly = 37
8327 12:46:30.507230 CS Dly: 10 (0~43)
8328 12:46:30.510518 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 12:46:30.513365 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 12:46:30.513780
8331 12:46:30.516829 ----->DramcWriteLeveling(PI) begin...
8332 12:46:30.520442 ==
8333 12:46:30.523813 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 12:46:30.526461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 12:46:30.526938 ==
8336 12:46:30.529754 Write leveling (Byte 0): 23 => 23
8337 12:46:30.533797 Write leveling (Byte 1): 27 => 27
8338 12:46:30.536594 DramcWriteLeveling(PI) end<-----
8339 12:46:30.537008
8340 12:46:30.537327 ==
8341 12:46:30.539708 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 12:46:30.543045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 12:46:30.543577 ==
8344 12:46:30.546493 [Gating] SW mode calibration
8345 12:46:30.553005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8346 12:46:30.559717 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8347 12:46:30.563076 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 12:46:30.565684 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 12:46:30.572808 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 12:46:30.576542 1 4 12 | B1->B0 | 2322 2d2d | 1 0 | (0 0) (0 0)
8351 12:46:30.579221 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 12:46:30.585965 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 12:46:30.589043 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 12:46:30.592719 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 12:46:30.599052 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 12:46:30.602348 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 12:46:30.605484 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 12:46:30.611803 1 5 12 | B1->B0 | 3333 2727 | 0 0 | (0 0) (1 0)
8359 12:46:30.616144 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 12:46:30.618739 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 12:46:30.625476 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 12:46:30.628894 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 12:46:30.631798 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 12:46:30.638410 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 12:46:30.641345 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8366 12:46:30.644651 1 6 12 | B1->B0 | 2f2f 4343 | 0 0 | (0 0) (0 0)
8367 12:46:30.651241 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 12:46:30.654767 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 12:46:30.657956 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 12:46:30.664189 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 12:46:30.667951 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 12:46:30.671783 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 12:46:30.677614 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 12:46:30.681008 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8375 12:46:30.684371 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8376 12:46:30.691524 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 12:46:30.694092 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 12:46:30.700606 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 12:46:30.704218 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 12:46:30.707300 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 12:46:30.714122 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 12:46:30.717214 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 12:46:30.720364 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 12:46:30.727299 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 12:46:30.730640 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 12:46:30.733824 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 12:46:30.740539 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 12:46:30.743509 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 12:46:30.746542 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 12:46:30.753180 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8391 12:46:30.756548 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:46:30.759912 Total UI for P1: 0, mck2ui 16
8393 12:46:30.763413 best dqsien dly found for B0: ( 1, 9, 12)
8394 12:46:30.766158 Total UI for P1: 0, mck2ui 16
8395 12:46:30.769725 best dqsien dly found for B1: ( 1, 9, 12)
8396 12:46:30.772870 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8397 12:46:30.776149 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8398 12:46:30.776559
8399 12:46:30.779152 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8400 12:46:30.783010 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8401 12:46:30.786278 [Gating] SW calibration Done
8402 12:46:30.786690 ==
8403 12:46:30.789354 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 12:46:30.795788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 12:46:30.796255 ==
8406 12:46:30.796585 RX Vref Scan: 0
8407 12:46:30.796887
8408 12:46:30.799128 RX Vref 0 -> 0, step: 1
8409 12:46:30.799549
8410 12:46:30.802292 RX Delay 0 -> 252, step: 8
8411 12:46:30.806039 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8412 12:46:30.808703 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8413 12:46:30.812248 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8414 12:46:30.815497 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8415 12:46:30.822569 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8416 12:46:30.825256 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8417 12:46:30.828764 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8418 12:46:30.832720 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8419 12:46:30.835172 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8420 12:46:30.841928 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8421 12:46:30.845194 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8422 12:46:30.848567 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8423 12:46:30.852322 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8424 12:46:30.859052 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8425 12:46:30.861578 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8426 12:46:30.864889 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8427 12:46:30.865305 ==
8428 12:46:30.868150 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 12:46:30.871621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 12:46:30.872074 ==
8431 12:46:30.875146 DQS Delay:
8432 12:46:30.875558 DQS0 = 0, DQS1 = 0
8433 12:46:30.878104 DQM Delay:
8434 12:46:30.878520 DQM0 = 135, DQM1 = 129
8435 12:46:30.881338 DQ Delay:
8436 12:46:30.884797 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8437 12:46:30.888063 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8438 12:46:30.891644 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8439 12:46:30.895117 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8440 12:46:30.895536
8441 12:46:30.895864
8442 12:46:30.896214 ==
8443 12:46:30.898581 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 12:46:30.901134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 12:46:30.901560 ==
8446 12:46:30.901898
8447 12:46:30.902208
8448 12:46:30.904665 TX Vref Scan disable
8449 12:46:30.908068 == TX Byte 0 ==
8450 12:46:30.911359 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8451 12:46:30.914847 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8452 12:46:30.917639 == TX Byte 1 ==
8453 12:46:30.920722 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8454 12:46:30.924378 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8455 12:46:30.924803 ==
8456 12:46:30.927408 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 12:46:30.933783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 12:46:30.934208 ==
8459 12:46:30.946127
8460 12:46:30.950059 TX Vref early break, caculate TX vref
8461 12:46:30.952389 TX Vref=16, minBit 8, minWin=21, winSum=365
8462 12:46:30.955841 TX Vref=18, minBit 11, minWin=22, winSum=379
8463 12:46:30.959170 TX Vref=20, minBit 8, minWin=22, winSum=386
8464 12:46:30.962932 TX Vref=22, minBit 8, minWin=23, winSum=396
8465 12:46:30.965828 TX Vref=24, minBit 8, minWin=24, winSum=405
8466 12:46:30.972140 TX Vref=26, minBit 8, minWin=24, winSum=414
8467 12:46:30.975460 TX Vref=28, minBit 0, minWin=25, winSum=418
8468 12:46:30.978949 TX Vref=30, minBit 9, minWin=24, winSum=414
8469 12:46:30.982441 TX Vref=32, minBit 0, minWin=24, winSum=405
8470 12:46:30.985583 TX Vref=34, minBit 0, minWin=23, winSum=395
8471 12:46:30.992207 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8472 12:46:30.992694
8473 12:46:30.995620 Final TX Range 0 Vref 28
8474 12:46:30.996151
8475 12:46:30.996572 ==
8476 12:46:30.998819 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 12:46:31.001911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 12:46:31.002332 ==
8479 12:46:31.002734
8480 12:46:31.005030
8481 12:46:31.005500 TX Vref Scan disable
8482 12:46:31.011678 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8483 12:46:31.012246 == TX Byte 0 ==
8484 12:46:31.015268 u2DelayCellOfst[0]=14 cells (4 PI)
8485 12:46:31.018818 u2DelayCellOfst[1]=10 cells (3 PI)
8486 12:46:31.021446 u2DelayCellOfst[2]=0 cells (0 PI)
8487 12:46:31.024975 u2DelayCellOfst[3]=7 cells (2 PI)
8488 12:46:31.028160 u2DelayCellOfst[4]=10 cells (3 PI)
8489 12:46:31.031485 u2DelayCellOfst[5]=17 cells (5 PI)
8490 12:46:31.035317 u2DelayCellOfst[6]=17 cells (5 PI)
8491 12:46:31.038274 u2DelayCellOfst[7]=7 cells (2 PI)
8492 12:46:31.041358 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8493 12:46:31.044768 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8494 12:46:31.047709 == TX Byte 1 ==
8495 12:46:31.051698 u2DelayCellOfst[8]=0 cells (0 PI)
8496 12:46:31.054300 u2DelayCellOfst[9]=3 cells (1 PI)
8497 12:46:31.057695 u2DelayCellOfst[10]=10 cells (3 PI)
8498 12:46:31.061274 u2DelayCellOfst[11]=7 cells (2 PI)
8499 12:46:31.064505 u2DelayCellOfst[12]=14 cells (4 PI)
8500 12:46:31.067851 u2DelayCellOfst[13]=14 cells (4 PI)
8501 12:46:31.068330 u2DelayCellOfst[14]=17 cells (5 PI)
8502 12:46:31.071013 u2DelayCellOfst[15]=17 cells (5 PI)
8503 12:46:31.078438 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8504 12:46:31.080887 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8505 12:46:31.084090 DramC Write-DBI on
8506 12:46:31.084521 ==
8507 12:46:31.087612 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 12:46:31.090763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 12:46:31.091181 ==
8510 12:46:31.091507
8511 12:46:31.091808
8512 12:46:31.093769 TX Vref Scan disable
8513 12:46:31.094184 == TX Byte 0 ==
8514 12:46:31.100409 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8515 12:46:31.100823 == TX Byte 1 ==
8516 12:46:31.104322 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8517 12:46:31.107237 DramC Write-DBI off
8518 12:46:31.107649
8519 12:46:31.107983 [DATLAT]
8520 12:46:31.110691 Freq=1600, CH1 RK0
8521 12:46:31.111105
8522 12:46:31.111429 DATLAT Default: 0xf
8523 12:46:31.113770 0, 0xFFFF, sum = 0
8524 12:46:31.116835 1, 0xFFFF, sum = 0
8525 12:46:31.117253 2, 0xFFFF, sum = 0
8526 12:46:31.120345 3, 0xFFFF, sum = 0
8527 12:46:31.120764 4, 0xFFFF, sum = 0
8528 12:46:31.123427 5, 0xFFFF, sum = 0
8529 12:46:31.123842 6, 0xFFFF, sum = 0
8530 12:46:31.127071 7, 0xFFFF, sum = 0
8531 12:46:31.127492 8, 0xFFFF, sum = 0
8532 12:46:31.130081 9, 0xFFFF, sum = 0
8533 12:46:31.130500 10, 0xFFFF, sum = 0
8534 12:46:31.133618 11, 0xFFFF, sum = 0
8535 12:46:31.134039 12, 0xFFFF, sum = 0
8536 12:46:31.136572 13, 0xFFFF, sum = 0
8537 12:46:31.136994 14, 0x0, sum = 1
8538 12:46:31.140224 15, 0x0, sum = 2
8539 12:46:31.140641 16, 0x0, sum = 3
8540 12:46:31.143397 17, 0x0, sum = 4
8541 12:46:31.143815 best_step = 15
8542 12:46:31.144184
8543 12:46:31.144497 ==
8544 12:46:31.147185 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 12:46:31.153374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 12:46:31.153791 ==
8547 12:46:31.154118 RX Vref Scan: 1
8548 12:46:31.154424
8549 12:46:31.156293 Set Vref Range= 24 -> 127
8550 12:46:31.156708
8551 12:46:31.160101 RX Vref 24 -> 127, step: 1
8552 12:46:31.160577
8553 12:46:31.160912 RX Delay 11 -> 252, step: 4
8554 12:46:31.163217
8555 12:46:31.163630 Set Vref, RX VrefLevel [Byte0]: 24
8556 12:46:31.166955 [Byte1]: 24
8557 12:46:31.170794
8558 12:46:31.171153 Set Vref, RX VrefLevel [Byte0]: 25
8559 12:46:31.173920 [Byte1]: 25
8560 12:46:31.178074
8561 12:46:31.178512 Set Vref, RX VrefLevel [Byte0]: 26
8562 12:46:31.181400 [Byte1]: 26
8563 12:46:31.186288
8564 12:46:31.186771 Set Vref, RX VrefLevel [Byte0]: 27
8565 12:46:31.189145 [Byte1]: 27
8566 12:46:31.193632
8567 12:46:31.194074 Set Vref, RX VrefLevel [Byte0]: 28
8568 12:46:31.196634 [Byte1]: 28
8569 12:46:31.201148
8570 12:46:31.201630 Set Vref, RX VrefLevel [Byte0]: 29
8571 12:46:31.204615 [Byte1]: 29
8572 12:46:31.208491
8573 12:46:31.208912 Set Vref, RX VrefLevel [Byte0]: 30
8574 12:46:31.211869 [Byte1]: 30
8575 12:46:31.216493
8576 12:46:31.216917 Set Vref, RX VrefLevel [Byte0]: 31
8577 12:46:31.219627 [Byte1]: 31
8578 12:46:31.223763
8579 12:46:31.224225 Set Vref, RX VrefLevel [Byte0]: 32
8580 12:46:31.227581 [Byte1]: 32
8581 12:46:31.231926
8582 12:46:31.232488 Set Vref, RX VrefLevel [Byte0]: 33
8583 12:46:31.235328 [Byte1]: 33
8584 12:46:31.239202
8585 12:46:31.239626 Set Vref, RX VrefLevel [Byte0]: 34
8586 12:46:31.242506 [Byte1]: 34
8587 12:46:31.246532
8588 12:46:31.246949 Set Vref, RX VrefLevel [Byte0]: 35
8589 12:46:31.250014 [Byte1]: 35
8590 12:46:31.254424
8591 12:46:31.254842 Set Vref, RX VrefLevel [Byte0]: 36
8592 12:46:31.257549 [Byte1]: 36
8593 12:46:31.262196
8594 12:46:31.262616 Set Vref, RX VrefLevel [Byte0]: 37
8595 12:46:31.265489 [Byte1]: 37
8596 12:46:31.269805
8597 12:46:31.270222 Set Vref, RX VrefLevel [Byte0]: 38
8598 12:46:31.273089 [Byte1]: 38
8599 12:46:31.277501
8600 12:46:31.277932 Set Vref, RX VrefLevel [Byte0]: 39
8601 12:46:31.280995 [Byte1]: 39
8602 12:46:31.284694
8603 12:46:31.285109 Set Vref, RX VrefLevel [Byte0]: 40
8604 12:46:31.288025 [Byte1]: 40
8605 12:46:31.292888
8606 12:46:31.293321 Set Vref, RX VrefLevel [Byte0]: 41
8607 12:46:31.295669 [Byte1]: 41
8608 12:46:31.300210
8609 12:46:31.300627 Set Vref, RX VrefLevel [Byte0]: 42
8610 12:46:31.303473 [Byte1]: 42
8611 12:46:31.307680
8612 12:46:31.308138 Set Vref, RX VrefLevel [Byte0]: 43
8613 12:46:31.311088 [Byte1]: 43
8614 12:46:31.315419
8615 12:46:31.315829 Set Vref, RX VrefLevel [Byte0]: 44
8616 12:46:31.318548 [Byte1]: 44
8617 12:46:31.322761
8618 12:46:31.323173 Set Vref, RX VrefLevel [Byte0]: 45
8619 12:46:31.326081 [Byte1]: 45
8620 12:46:31.330411
8621 12:46:31.330821 Set Vref, RX VrefLevel [Byte0]: 46
8622 12:46:31.333820 [Byte1]: 46
8623 12:46:31.338144
8624 12:46:31.338551 Set Vref, RX VrefLevel [Byte0]: 47
8625 12:46:31.341551 [Byte1]: 47
8626 12:46:31.345766
8627 12:46:31.346182 Set Vref, RX VrefLevel [Byte0]: 48
8628 12:46:31.349024 [Byte1]: 48
8629 12:46:31.353391
8630 12:46:31.353804 Set Vref, RX VrefLevel [Byte0]: 49
8631 12:46:31.356510 [Byte1]: 49
8632 12:46:31.361091
8633 12:46:31.361544 Set Vref, RX VrefLevel [Byte0]: 50
8634 12:46:31.364414 [Byte1]: 50
8635 12:46:31.368392
8636 12:46:31.369010 Set Vref, RX VrefLevel [Byte0]: 51
8637 12:46:31.371796 [Byte1]: 51
8638 12:46:31.376144
8639 12:46:31.376566 Set Vref, RX VrefLevel [Byte0]: 52
8640 12:46:31.379426 [Byte1]: 52
8641 12:46:31.383716
8642 12:46:31.384194 Set Vref, RX VrefLevel [Byte0]: 53
8643 12:46:31.387885 [Byte1]: 53
8644 12:46:31.391607
8645 12:46:31.392026 Set Vref, RX VrefLevel [Byte0]: 54
8646 12:46:31.394576 [Byte1]: 54
8647 12:46:31.399064
8648 12:46:31.399485 Set Vref, RX VrefLevel [Byte0]: 55
8649 12:46:31.402402 [Byte1]: 55
8650 12:46:31.407415
8651 12:46:31.407835 Set Vref, RX VrefLevel [Byte0]: 56
8652 12:46:31.410283 [Byte1]: 56
8653 12:46:31.414350
8654 12:46:31.414801 Set Vref, RX VrefLevel [Byte0]: 57
8655 12:46:31.417583 [Byte1]: 57
8656 12:46:31.421682
8657 12:46:31.422102 Set Vref, RX VrefLevel [Byte0]: 58
8658 12:46:31.425142 [Byte1]: 58
8659 12:46:31.429228
8660 12:46:31.429650 Set Vref, RX VrefLevel [Byte0]: 59
8661 12:46:31.432950 [Byte1]: 59
8662 12:46:31.437147
8663 12:46:31.437568 Set Vref, RX VrefLevel [Byte0]: 60
8664 12:46:31.440738 [Byte1]: 60
8665 12:46:31.444652
8666 12:46:31.445072 Set Vref, RX VrefLevel [Byte0]: 61
8667 12:46:31.447965 [Byte1]: 61
8668 12:46:31.452122
8669 12:46:31.452543 Set Vref, RX VrefLevel [Byte0]: 62
8670 12:46:31.455616 [Byte1]: 62
8671 12:46:31.459741
8672 12:46:31.460240 Set Vref, RX VrefLevel [Byte0]: 63
8673 12:46:31.463599 [Byte1]: 63
8674 12:46:31.467675
8675 12:46:31.468168 Set Vref, RX VrefLevel [Byte0]: 64
8676 12:46:31.470787 [Byte1]: 64
8677 12:46:31.475049
8678 12:46:31.475473 Set Vref, RX VrefLevel [Byte0]: 65
8679 12:46:31.478767 [Byte1]: 65
8680 12:46:31.482655
8681 12:46:31.483078 Set Vref, RX VrefLevel [Byte0]: 66
8682 12:46:31.486236 [Byte1]: 66
8683 12:46:31.490287
8684 12:46:31.490749 Set Vref, RX VrefLevel [Byte0]: 67
8685 12:46:31.493680 [Byte1]: 67
8686 12:46:31.498961
8687 12:46:31.499381 Set Vref, RX VrefLevel [Byte0]: 68
8688 12:46:31.501359 [Byte1]: 68
8689 12:46:31.505403
8690 12:46:31.505823 Set Vref, RX VrefLevel [Byte0]: 69
8691 12:46:31.508926 [Byte1]: 69
8692 12:46:31.513307
8693 12:46:31.513730 Set Vref, RX VrefLevel [Byte0]: 70
8694 12:46:31.516842 [Byte1]: 70
8695 12:46:31.521072
8696 12:46:31.521530 Set Vref, RX VrefLevel [Byte0]: 71
8697 12:46:31.524377 [Byte1]: 71
8698 12:46:31.528588
8699 12:46:31.529010 Final RX Vref Byte 0 = 59 to rank0
8700 12:46:31.531746 Final RX Vref Byte 1 = 62 to rank0
8701 12:46:31.535118 Final RX Vref Byte 0 = 59 to rank1
8702 12:46:31.538345 Final RX Vref Byte 1 = 62 to rank1==
8703 12:46:31.541647 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 12:46:31.548140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 12:46:31.548565 ==
8706 12:46:31.548901 DQS Delay:
8707 12:46:31.551031 DQS0 = 0, DQS1 = 0
8708 12:46:31.551490 DQM Delay:
8709 12:46:31.554656 DQM0 = 132, DQM1 = 128
8710 12:46:31.555078 DQ Delay:
8711 12:46:31.558368 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8712 12:46:31.561018 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8713 12:46:31.564222 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8714 12:46:31.567906 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8715 12:46:31.568361
8716 12:46:31.568690
8717 12:46:31.568990
8718 12:46:31.570616 [DramC_TX_OE_Calibration] TA2
8719 12:46:31.574279 Original DQ_B0 (3 6) =30, OEN = 27
8720 12:46:31.577649 Original DQ_B1 (3 6) =30, OEN = 27
8721 12:46:31.580679 24, 0x0, End_B0=24 End_B1=24
8722 12:46:31.584141 25, 0x0, End_B0=25 End_B1=25
8723 12:46:31.584565 26, 0x0, End_B0=26 End_B1=26
8724 12:46:31.587971 27, 0x0, End_B0=27 End_B1=27
8725 12:46:31.591106 28, 0x0, End_B0=28 End_B1=28
8726 12:46:31.594190 29, 0x0, End_B0=29 End_B1=29
8727 12:46:31.594616 30, 0x0, End_B0=30 End_B1=30
8728 12:46:31.597385 31, 0x4545, End_B0=30 End_B1=30
8729 12:46:31.600689 Byte0 end_step=30 best_step=27
8730 12:46:31.604437 Byte1 end_step=30 best_step=27
8731 12:46:31.607331 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 12:46:31.611022 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 12:46:31.611437
8734 12:46:31.611766
8735 12:46:31.617210 [DQSOSCAuto] RK0, (LSB)MR18= 0xa12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
8736 12:46:31.620457 CH1 RK0: MR19=303, MR18=A12
8737 12:46:31.626982 CH1_RK0: MR19=0x303, MR18=0xA12, DQSOSC=400, MR23=63, INC=23, DEC=15
8738 12:46:31.627401
8739 12:46:31.630536 ----->DramcWriteLeveling(PI) begin...
8740 12:46:31.630960 ==
8741 12:46:31.633631 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 12:46:31.636951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 12:46:31.637373 ==
8744 12:46:31.640431 Write leveling (Byte 0): 24 => 24
8745 12:46:31.643507 Write leveling (Byte 1): 26 => 26
8746 12:46:31.646799 DramcWriteLeveling(PI) end<-----
8747 12:46:31.647217
8748 12:46:31.647545 ==
8749 12:46:31.650057 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 12:46:31.656522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 12:46:31.656943 ==
8752 12:46:31.657277 [Gating] SW mode calibration
8753 12:46:31.667007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 12:46:31.670141 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 12:46:31.673634 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 12:46:31.680139 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 12:46:31.683726 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8758 12:46:31.686708 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8759 12:46:31.692857 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 12:46:31.696373 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 12:46:31.699772 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 12:46:31.706464 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 12:46:31.709672 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 12:46:31.712609 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8765 12:46:31.719487 1 5 8 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
8766 12:46:31.722392 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8767 12:46:31.726004 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8768 12:46:31.732658 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 12:46:31.735877 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 12:46:31.739050 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 12:46:31.745795 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 12:46:31.748975 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8773 12:46:31.755284 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8774 12:46:31.758538 1 6 12 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8775 12:46:31.761693 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 12:46:31.768340 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 12:46:31.771505 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 12:46:31.774926 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 12:46:31.781437 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 12:46:31.785143 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8781 12:46:31.788203 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8782 12:46:31.794382 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8783 12:46:31.797814 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:46:31.801505 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:46:31.807972 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:46:31.811288 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:46:31.814348 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:46:31.821187 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:46:31.824111 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 12:46:31.827190 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 12:46:31.833975 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 12:46:31.837715 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:46:31.841035 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:46:31.847251 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 12:46:31.850253 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 12:46:31.853680 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8797 12:46:31.860109 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8798 12:46:31.863617 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8799 12:46:31.867011 Total UI for P1: 0, mck2ui 16
8800 12:46:31.870254 best dqsien dly found for B0: ( 1, 9, 6)
8801 12:46:31.873500 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 12:46:31.876751 Total UI for P1: 0, mck2ui 16
8803 12:46:31.879826 best dqsien dly found for B1: ( 1, 9, 12)
8804 12:46:31.883133 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8805 12:46:31.887121 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8806 12:46:31.887543
8807 12:46:31.894257 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8808 12:46:31.896994 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8809 12:46:31.900129 [Gating] SW calibration Done
8810 12:46:31.900552 ==
8811 12:46:31.902848 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 12:46:31.906521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 12:46:31.906947 ==
8814 12:46:31.907283 RX Vref Scan: 0
8815 12:46:31.907593
8816 12:46:31.909790 RX Vref 0 -> 0, step: 1
8817 12:46:31.910211
8818 12:46:31.912921 RX Delay 0 -> 252, step: 8
8819 12:46:31.916496 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8820 12:46:31.919497 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8821 12:46:31.926094 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8822 12:46:31.929518 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8823 12:46:31.932576 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8824 12:46:31.935793 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8825 12:46:31.939371 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8826 12:46:31.946284 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8827 12:46:31.948780 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8828 12:46:31.952315 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8829 12:46:31.955853 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8830 12:46:31.962414 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8831 12:46:31.965773 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8832 12:46:31.968943 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8833 12:46:31.972023 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8834 12:46:31.975345 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8835 12:46:31.978519 ==
8836 12:46:31.982116 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 12:46:31.984964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 12:46:31.985393 ==
8839 12:46:31.985730 DQS Delay:
8840 12:46:31.988453 DQS0 = 0, DQS1 = 0
8841 12:46:31.988963 DQM Delay:
8842 12:46:31.992180 DQM0 = 133, DQM1 = 131
8843 12:46:31.992645 DQ Delay:
8844 12:46:31.994924 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8845 12:46:31.998020 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8846 12:46:32.001876 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8847 12:46:32.004846 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8848 12:46:32.005276
8849 12:46:32.005685
8850 12:46:32.008593 ==
8851 12:46:32.009015 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 12:46:32.014883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 12:46:32.015308 ==
8854 12:46:32.015655
8855 12:46:32.016062
8856 12:46:32.018335 TX Vref Scan disable
8857 12:46:32.018757 == TX Byte 0 ==
8858 12:46:32.022280 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8859 12:46:32.027856 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8860 12:46:32.028355 == TX Byte 1 ==
8861 12:46:32.034625 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8862 12:46:32.037840 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8863 12:46:32.038334 ==
8864 12:46:32.041334 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 12:46:32.044310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 12:46:32.044761 ==
8867 12:46:32.058572
8868 12:46:32.062297 TX Vref early break, caculate TX vref
8869 12:46:32.065031 TX Vref=16, minBit 9, minWin=21, winSum=376
8870 12:46:32.068309 TX Vref=18, minBit 9, minWin=22, winSum=386
8871 12:46:32.071902 TX Vref=20, minBit 9, minWin=22, winSum=393
8872 12:46:32.074879 TX Vref=22, minBit 9, minWin=24, winSum=403
8873 12:46:32.078516 TX Vref=24, minBit 9, minWin=24, winSum=412
8874 12:46:32.085019 TX Vref=26, minBit 9, minWin=24, winSum=416
8875 12:46:32.088377 TX Vref=28, minBit 9, minWin=24, winSum=418
8876 12:46:32.091328 TX Vref=30, minBit 13, minWin=25, winSum=420
8877 12:46:32.094775 TX Vref=32, minBit 8, minWin=24, winSum=407
8878 12:46:32.098286 TX Vref=34, minBit 8, minWin=24, winSum=402
8879 12:46:32.104670 TX Vref=36, minBit 9, minWin=22, winSum=395
8880 12:46:32.107728 [TxChooseVref] Worse bit 13, Min win 25, Win sum 420, Final Vref 30
8881 12:46:32.108202
8882 12:46:32.111061 Final TX Range 0 Vref 30
8883 12:46:32.111485
8884 12:46:32.111818 ==
8885 12:46:32.114809 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 12:46:32.117686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 12:46:32.121303 ==
8888 12:46:32.121723
8889 12:46:32.122051
8890 12:46:32.122432 TX Vref Scan disable
8891 12:46:32.128484 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8892 12:46:32.128907 == TX Byte 0 ==
8893 12:46:32.131700 u2DelayCellOfst[0]=17 cells (5 PI)
8894 12:46:32.134535 u2DelayCellOfst[1]=10 cells (3 PI)
8895 12:46:32.138199 u2DelayCellOfst[2]=0 cells (0 PI)
8896 12:46:32.142112 u2DelayCellOfst[3]=7 cells (2 PI)
8897 12:46:32.144546 u2DelayCellOfst[4]=7 cells (2 PI)
8898 12:46:32.147863 u2DelayCellOfst[5]=14 cells (4 PI)
8899 12:46:32.151020 u2DelayCellOfst[6]=17 cells (5 PI)
8900 12:46:32.154811 u2DelayCellOfst[7]=7 cells (2 PI)
8901 12:46:32.157562 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8902 12:46:32.160552 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8903 12:46:32.163965 == TX Byte 1 ==
8904 12:46:32.167711 u2DelayCellOfst[8]=0 cells (0 PI)
8905 12:46:32.170790 u2DelayCellOfst[9]=3 cells (1 PI)
8906 12:46:32.174236 u2DelayCellOfst[10]=10 cells (3 PI)
8907 12:46:32.177387 u2DelayCellOfst[11]=7 cells (2 PI)
8908 12:46:32.180482 u2DelayCellOfst[12]=14 cells (4 PI)
8909 12:46:32.184099 u2DelayCellOfst[13]=17 cells (5 PI)
8910 12:46:32.187420 u2DelayCellOfst[14]=17 cells (5 PI)
8911 12:46:32.190194 u2DelayCellOfst[15]=17 cells (5 PI)
8912 12:46:32.193669 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8913 12:46:32.196665 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8914 12:46:32.200515 DramC Write-DBI on
8915 12:46:32.201017 ==
8916 12:46:32.203386 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 12:46:32.206919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 12:46:32.207337 ==
8919 12:46:32.207663
8920 12:46:32.207968
8921 12:46:32.210139 TX Vref Scan disable
8922 12:46:32.210566 == TX Byte 0 ==
8923 12:46:32.216994 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8924 12:46:32.217409 == TX Byte 1 ==
8925 12:46:32.223585 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8926 12:46:32.224002 DramC Write-DBI off
8927 12:46:32.224375
8928 12:46:32.224680 [DATLAT]
8929 12:46:32.226650 Freq=1600, CH1 RK1
8930 12:46:32.227067
8931 12:46:32.230393 DATLAT Default: 0xf
8932 12:46:32.230806 0, 0xFFFF, sum = 0
8933 12:46:32.233745 1, 0xFFFF, sum = 0
8934 12:46:32.234163 2, 0xFFFF, sum = 0
8935 12:46:32.236220 3, 0xFFFF, sum = 0
8936 12:46:32.236639 4, 0xFFFF, sum = 0
8937 12:46:32.239826 5, 0xFFFF, sum = 0
8938 12:46:32.240274 6, 0xFFFF, sum = 0
8939 12:46:32.242975 7, 0xFFFF, sum = 0
8940 12:46:32.243393 8, 0xFFFF, sum = 0
8941 12:46:32.246448 9, 0xFFFF, sum = 0
8942 12:46:32.246868 10, 0xFFFF, sum = 0
8943 12:46:32.249199 11, 0xFFFF, sum = 0
8944 12:46:32.249623 12, 0xFFFF, sum = 0
8945 12:46:32.252685 13, 0xFFFF, sum = 0
8946 12:46:32.253105 14, 0x0, sum = 1
8947 12:46:32.256110 15, 0x0, sum = 2
8948 12:46:32.256487 16, 0x0, sum = 3
8949 12:46:32.259860 17, 0x0, sum = 4
8950 12:46:32.260357 best_step = 15
8951 12:46:32.260758
8952 12:46:32.261272 ==
8953 12:46:32.262652 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 12:46:32.268850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 12:46:32.269265 ==
8956 12:46:32.269594 RX Vref Scan: 0
8957 12:46:32.269897
8958 12:46:32.272399 RX Vref 0 -> 0, step: 1
8959 12:46:32.272812
8960 12:46:32.275904 RX Delay 19 -> 252, step: 4
8961 12:46:32.279207 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8962 12:46:32.282114 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8963 12:46:32.289226 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8964 12:46:32.292005 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8965 12:46:32.295253 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8966 12:46:32.298774 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8967 12:46:32.301595 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8968 12:46:32.308393 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8969 12:46:32.311738 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8970 12:46:32.315109 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8971 12:46:32.318561 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8972 12:46:32.325261 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8973 12:46:32.329005 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8974 12:46:32.331803 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8975 12:46:32.334744 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8976 12:46:32.337987 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8977 12:46:32.341771 ==
8978 12:46:32.344837 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 12:46:32.347974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 12:46:32.348419 ==
8981 12:46:32.348748 DQS Delay:
8982 12:46:32.351195 DQS0 = 0, DQS1 = 0
8983 12:46:32.351607 DQM Delay:
8984 12:46:32.354516 DQM0 = 131, DQM1 = 128
8985 12:46:32.354929 DQ Delay:
8986 12:46:32.357767 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8987 12:46:32.361235 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =130
8988 12:46:32.365099 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8989 12:46:32.367651 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8990 12:46:32.368100
8991 12:46:32.368438
8992 12:46:32.368739
8993 12:46:32.371237 [DramC_TX_OE_Calibration] TA2
8994 12:46:32.374239 Original DQ_B0 (3 6) =30, OEN = 27
8995 12:46:32.377692 Original DQ_B1 (3 6) =30, OEN = 27
8996 12:46:32.380959 24, 0x0, End_B0=24 End_B1=24
8997 12:46:32.384145 25, 0x0, End_B0=25 End_B1=25
8998 12:46:32.387220 26, 0x0, End_B0=26 End_B1=26
8999 12:46:32.387641 27, 0x0, End_B0=27 End_B1=27
9000 12:46:32.390861 28, 0x0, End_B0=28 End_B1=28
9001 12:46:32.394018 29, 0x0, End_B0=29 End_B1=29
9002 12:46:32.397656 30, 0x0, End_B0=30 End_B1=30
9003 12:46:32.400516 31, 0x4141, End_B0=30 End_B1=30
9004 12:46:32.400951 Byte0 end_step=30 best_step=27
9005 12:46:32.403913 Byte1 end_step=30 best_step=27
9006 12:46:32.407109 Byte0 TX OE(2T, 0.5T) = (3, 3)
9007 12:46:32.410641 Byte1 TX OE(2T, 0.5T) = (3, 3)
9008 12:46:32.411060
9009 12:46:32.411389
9010 12:46:32.420157 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9011 12:46:32.420583 CH1 RK1: MR19=303, MR18=E1C
9012 12:46:32.426871 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9013 12:46:32.430955 [RxdqsGatingPostProcess] freq 1600
9014 12:46:32.436942 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9015 12:46:32.439794 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 12:46:32.443440 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 12:46:32.446726 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 12:46:32.447141 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 12:46:32.449804 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 12:46:32.452781 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 12:46:32.456289 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 12:46:32.459773 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 12:46:32.462649 Pre-setting of DQS Precalculation
9024 12:46:32.469458 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9025 12:46:32.476185 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9026 12:46:32.482887 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9027 12:46:32.483323
9028 12:46:32.483727
9029 12:46:32.485769 [Calibration Summary] 3200 Mbps
9030 12:46:32.486246 CH 0, Rank 0
9031 12:46:32.490034 SW Impedance : PASS
9032 12:46:32.492635 DUTY Scan : NO K
9033 12:46:32.493047 ZQ Calibration : PASS
9034 12:46:32.496112 Jitter Meter : NO K
9035 12:46:32.499149 CBT Training : PASS
9036 12:46:32.499561 Write leveling : PASS
9037 12:46:32.502343 RX DQS gating : PASS
9038 12:46:32.505620 RX DQ/DQS(RDDQC) : PASS
9039 12:46:32.506091 TX DQ/DQS : PASS
9040 12:46:32.509406 RX DATLAT : PASS
9041 12:46:32.512136 RX DQ/DQS(Engine): PASS
9042 12:46:32.512657 TX OE : PASS
9043 12:46:32.515748 All Pass.
9044 12:46:32.516297
9045 12:46:32.516818 CH 0, Rank 1
9046 12:46:32.518970 SW Impedance : PASS
9047 12:46:32.519385 DUTY Scan : NO K
9048 12:46:32.522022 ZQ Calibration : PASS
9049 12:46:32.525178 Jitter Meter : NO K
9050 12:46:32.525594 CBT Training : PASS
9051 12:46:32.528815 Write leveling : PASS
9052 12:46:32.532142 RX DQS gating : PASS
9053 12:46:32.532566 RX DQ/DQS(RDDQC) : PASS
9054 12:46:32.534988 TX DQ/DQS : PASS
9055 12:46:32.538503 RX DATLAT : PASS
9056 12:46:32.538987 RX DQ/DQS(Engine): PASS
9057 12:46:32.541843 TX OE : PASS
9058 12:46:32.542322 All Pass.
9059 12:46:32.542655
9060 12:46:32.545333 CH 1, Rank 0
9061 12:46:32.545822 SW Impedance : PASS
9062 12:46:32.548255 DUTY Scan : NO K
9063 12:46:32.548670 ZQ Calibration : PASS
9064 12:46:32.551921 Jitter Meter : NO K
9065 12:46:32.555167 CBT Training : PASS
9066 12:46:32.555583 Write leveling : PASS
9067 12:46:32.558552 RX DQS gating : PASS
9068 12:46:32.561294 RX DQ/DQS(RDDQC) : PASS
9069 12:46:32.561707 TX DQ/DQS : PASS
9070 12:46:32.564710 RX DATLAT : PASS
9071 12:46:32.568129 RX DQ/DQS(Engine): PASS
9072 12:46:32.568542 TX OE : PASS
9073 12:46:32.571703 All Pass.
9074 12:46:32.572148
9075 12:46:32.572509 CH 1, Rank 1
9076 12:46:32.574508 SW Impedance : PASS
9077 12:46:32.575041 DUTY Scan : NO K
9078 12:46:32.578174 ZQ Calibration : PASS
9079 12:46:32.581705 Jitter Meter : NO K
9080 12:46:32.582118 CBT Training : PASS
9081 12:46:32.584868 Write leveling : PASS
9082 12:46:32.587961 RX DQS gating : PASS
9083 12:46:32.588485 RX DQ/DQS(RDDQC) : PASS
9084 12:46:32.591729 TX DQ/DQS : PASS
9085 12:46:32.594524 RX DATLAT : PASS
9086 12:46:32.594938 RX DQ/DQS(Engine): PASS
9087 12:46:32.598018 TX OE : PASS
9088 12:46:32.598435 All Pass.
9089 12:46:32.598786
9090 12:46:32.602109 DramC Write-DBI on
9091 12:46:32.604586 PER_BANK_REFRESH: Hybrid Mode
9092 12:46:32.605072 TX_TRACKING: ON
9093 12:46:32.614165 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9094 12:46:32.620887 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9095 12:46:32.627572 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9096 12:46:32.630948 [FAST_K] Save calibration result to emmc
9097 12:46:32.634203 sync common calibartion params.
9098 12:46:32.637622 sync cbt_mode0:1, 1:1
9099 12:46:32.640675 dram_init: ddr_geometry: 2
9100 12:46:32.641089 dram_init: ddr_geometry: 2
9101 12:46:32.643953 dram_init: ddr_geometry: 2
9102 12:46:32.647520 0:dram_rank_size:100000000
9103 12:46:32.650913 1:dram_rank_size:100000000
9104 12:46:32.654557 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9105 12:46:32.657412 DFS_SHUFFLE_HW_MODE: ON
9106 12:46:32.660735 dramc_set_vcore_voltage set vcore to 725000
9107 12:46:32.664096 Read voltage for 1600, 0
9108 12:46:32.664511 Vio18 = 0
9109 12:46:32.664839 Vcore = 725000
9110 12:46:32.667211 Vdram = 0
9111 12:46:32.667626 Vddq = 0
9112 12:46:32.667954 Vmddr = 0
9113 12:46:32.670275 switch to 3200 Mbps bootup
9114 12:46:32.673928 [DramcRunTimeConfig]
9115 12:46:32.674340 PHYPLL
9116 12:46:32.674668 DPM_CONTROL_AFTERK: ON
9117 12:46:32.677025 PER_BANK_REFRESH: ON
9118 12:46:32.680092 REFRESH_OVERHEAD_REDUCTION: ON
9119 12:46:32.683829 CMD_PICG_NEW_MODE: OFF
9120 12:46:32.684289 XRTWTW_NEW_MODE: ON
9121 12:46:32.687016 XRTRTR_NEW_MODE: ON
9122 12:46:32.687460 TX_TRACKING: ON
9123 12:46:32.690156 RDSEL_TRACKING: OFF
9124 12:46:32.690626 DQS Precalculation for DVFS: ON
9125 12:46:32.693271 RX_TRACKING: OFF
9126 12:46:32.693763 HW_GATING DBG: ON
9127 12:46:32.696694 ZQCS_ENABLE_LP4: ON
9128 12:46:32.699794 RX_PICG_NEW_MODE: ON
9129 12:46:32.700236 TX_PICG_NEW_MODE: ON
9130 12:46:32.703623 ENABLE_RX_DCM_DPHY: ON
9131 12:46:32.706446 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9132 12:46:32.709679 DUMMY_READ_FOR_TRACKING: OFF
9133 12:46:32.710091 !!! SPM_CONTROL_AFTERK: OFF
9134 12:46:32.713369 !!! SPM could not control APHY
9135 12:46:32.716903 IMPEDANCE_TRACKING: ON
9136 12:46:32.717318 TEMP_SENSOR: ON
9137 12:46:32.719959 HW_SAVE_FOR_SR: OFF
9138 12:46:32.722863 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9139 12:46:32.726394 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9140 12:46:32.726809 Read ODT Tracking: ON
9141 12:46:32.729842 Refresh Rate DeBounce: ON
9142 12:46:32.732727 DFS_NO_QUEUE_FLUSH: ON
9143 12:46:32.736107 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9144 12:46:32.736653 ENABLE_DFS_RUNTIME_MRW: OFF
9145 12:46:32.739364 DDR_RESERVE_NEW_MODE: ON
9146 12:46:32.742591 MR_CBT_SWITCH_FREQ: ON
9147 12:46:32.743003 =========================
9148 12:46:32.763226 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9149 12:46:32.766151 dram_init: ddr_geometry: 2
9150 12:46:32.784539 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9151 12:46:32.788011 dram_init: dram init end (result: 0)
9152 12:46:32.794598 DRAM-K: Full calibration passed in 24417 msecs
9153 12:46:32.797985 MRC: failed to locate region type 0.
9154 12:46:32.798467 DRAM rank0 size:0x100000000,
9155 12:46:32.801280 DRAM rank1 size=0x100000000
9156 12:46:32.810895 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9157 12:46:32.817571 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9158 12:46:32.827214 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9159 12:46:32.834171 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9160 12:46:32.834589 DRAM rank0 size:0x100000000,
9161 12:46:32.836975 DRAM rank1 size=0x100000000
9162 12:46:32.837390 CBMEM:
9163 12:46:32.840770 IMD: root @ 0xfffff000 254 entries.
9164 12:46:32.843772 IMD: root @ 0xffffec00 62 entries.
9165 12:46:32.850540 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9166 12:46:32.853568 WARNING: RO_VPD is uninitialized or empty.
9167 12:46:32.857190 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9168 12:46:32.865100 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9169 12:46:32.877667 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9170 12:46:32.888875 BS: romstage times (exec / console): total (unknown) / 23946 ms
9171 12:46:32.889352
9172 12:46:32.889683
9173 12:46:32.899164 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9174 12:46:32.902426 ARM64: Exception handlers installed.
9175 12:46:32.905370 ARM64: Testing exception
9176 12:46:32.908738 ARM64: Done test exception
9177 12:46:32.909302 Enumerating buses...
9178 12:46:32.912132 Show all devs... Before device enumeration.
9179 12:46:32.914873 Root Device: enabled 1
9180 12:46:32.918867 CPU_CLUSTER: 0: enabled 1
9181 12:46:32.919282 CPU: 00: enabled 1
9182 12:46:32.921781 Compare with tree...
9183 12:46:32.922194 Root Device: enabled 1
9184 12:46:32.925085 CPU_CLUSTER: 0: enabled 1
9185 12:46:32.928363 CPU: 00: enabled 1
9186 12:46:32.928778 Root Device scanning...
9187 12:46:32.931790 scan_static_bus for Root Device
9188 12:46:32.934959 CPU_CLUSTER: 0 enabled
9189 12:46:32.938096 scan_static_bus for Root Device done
9190 12:46:32.941424 scan_bus: bus Root Device finished in 8 msecs
9191 12:46:32.941840 done
9192 12:46:32.948087 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9193 12:46:32.951889 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9194 12:46:32.957702 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9195 12:46:32.965032 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9196 12:46:32.965451 Allocating resources...
9197 12:46:32.967705 Reading resources...
9198 12:46:32.970947 Root Device read_resources bus 0 link: 0
9199 12:46:32.974797 DRAM rank0 size:0x100000000,
9200 12:46:32.975216 DRAM rank1 size=0x100000000
9201 12:46:32.981031 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9202 12:46:32.981451 CPU: 00 missing read_resources
9203 12:46:32.987567 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9204 12:46:32.990631 Root Device read_resources bus 0 link: 0 done
9205 12:46:32.994388 Done reading resources.
9206 12:46:32.997334 Show resources in subtree (Root Device)...After reading.
9207 12:46:33.000550 Root Device child on link 0 CPU_CLUSTER: 0
9208 12:46:33.004349 CPU_CLUSTER: 0 child on link 0 CPU: 00
9209 12:46:33.013680 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9210 12:46:33.014155 CPU: 00
9211 12:46:33.020512 Root Device assign_resources, bus 0 link: 0
9212 12:46:33.023697 CPU_CLUSTER: 0 missing set_resources
9213 12:46:33.026950 Root Device assign_resources, bus 0 link: 0 done
9214 12:46:33.030040 Done setting resources.
9215 12:46:33.033479 Show resources in subtree (Root Device)...After assigning values.
9216 12:46:33.036995 Root Device child on link 0 CPU_CLUSTER: 0
9217 12:46:33.043326 CPU_CLUSTER: 0 child on link 0 CPU: 00
9218 12:46:33.050522 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9219 12:46:33.053231 CPU: 00
9220 12:46:33.053641 Done allocating resources.
9221 12:46:33.059722 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9222 12:46:33.060156 Enabling resources...
9223 12:46:33.063275 done.
9224 12:46:33.066227 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9225 12:46:33.069751 Initializing devices...
9226 12:46:33.070226 Root Device init
9227 12:46:33.073142 init hardware done!
9228 12:46:33.073567 0x00000018: ctrlr->caps
9229 12:46:33.076335 52.000 MHz: ctrlr->f_max
9230 12:46:33.079310 0.400 MHz: ctrlr->f_min
9231 12:46:33.082976 0x40ff8080: ctrlr->voltages
9232 12:46:33.083402 sclk: 390625
9233 12:46:33.083728 Bus Width = 1
9234 12:46:33.086085 sclk: 390625
9235 12:46:33.086501 Bus Width = 1
9236 12:46:33.090114 Early init status = 3
9237 12:46:33.092505 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9238 12:46:33.096660 in-header: 03 fc 00 00 01 00 00 00
9239 12:46:33.099482 in-data: 00
9240 12:46:33.102848 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9241 12:46:33.107432 in-header: 03 fd 00 00 00 00 00 00
9242 12:46:33.111404 in-data:
9243 12:46:33.114475 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9244 12:46:33.117956 in-header: 03 fc 00 00 01 00 00 00
9245 12:46:33.121026 in-data: 00
9246 12:46:33.124263 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9247 12:46:33.129117 in-header: 03 fd 00 00 00 00 00 00
9248 12:46:33.132284 in-data:
9249 12:46:33.135285 [SSUSB] Setting up USB HOST controller...
9250 12:46:33.139113 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9251 12:46:33.142183 [SSUSB] phy power-on done.
9252 12:46:33.145347 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9253 12:46:33.151712 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9254 12:46:33.155647 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9255 12:46:33.161966 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9256 12:46:33.170175 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9257 12:46:33.174869 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9258 12:46:33.181247 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9259 12:46:33.188635 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9260 12:46:33.191465 SPM: binary array size = 0x9dc
9261 12:46:33.194827 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9262 12:46:33.201245 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9263 12:46:33.207983 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9264 12:46:33.214694 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9265 12:46:33.217851 configure_display: Starting display init
9266 12:46:33.252164 anx7625_power_on_init: Init interface.
9267 12:46:33.255442 anx7625_disable_pd_protocol: Disabled PD feature.
9268 12:46:33.258683 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9269 12:46:33.286618 anx7625_start_dp_work: Secure OCM version=00
9270 12:46:33.289759 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9271 12:46:33.304706 sp_tx_get_edid_block: EDID Block = 1
9272 12:46:33.407080 Extracted contents:
9273 12:46:33.411060 header: 00 ff ff ff ff ff ff 00
9274 12:46:33.413794 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9275 12:46:33.417038 version: 01 04
9276 12:46:33.420554 basic params: 95 1f 11 78 0a
9277 12:46:33.423485 chroma info: 76 90 94 55 54 90 27 21 50 54
9278 12:46:33.427108 established: 00 00 00
9279 12:46:33.433283 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9280 12:46:33.436619 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9281 12:46:33.443447 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9282 12:46:33.450532 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9283 12:46:33.456544 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9284 12:46:33.459889 extensions: 00
9285 12:46:33.460373 checksum: fb
9286 12:46:33.460708
9287 12:46:33.466437 Manufacturer: IVO Model 57d Serial Number 0
9288 12:46:33.466854 Made week 0 of 2020
9289 12:46:33.469847 EDID version: 1.4
9290 12:46:33.470264 Digital display
9291 12:46:33.473194 6 bits per primary color channel
9292 12:46:33.476072 DisplayPort interface
9293 12:46:33.476502 Maximum image size: 31 cm x 17 cm
9294 12:46:33.479207 Gamma: 220%
9295 12:46:33.479623 Check DPMS levels
9296 12:46:33.486062 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9297 12:46:33.489161 First detailed timing is preferred timing
9298 12:46:33.492711 Established timings supported:
9299 12:46:33.493127 Standard timings supported:
9300 12:46:33.496006 Detailed timings
9301 12:46:33.499783 Hex of detail: 383680a07038204018303c0035ae10000019
9302 12:46:33.505643 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9303 12:46:33.508949 0780 0798 07c8 0820 hborder 0
9304 12:46:33.512225 0438 043b 0447 0458 vborder 0
9305 12:46:33.515610 -hsync -vsync
9306 12:46:33.516027 Did detailed timing
9307 12:46:33.522200 Hex of detail: 000000000000000000000000000000000000
9308 12:46:33.525456 Manufacturer-specified data, tag 0
9309 12:46:33.528983 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9310 12:46:33.532205 ASCII string: InfoVision
9311 12:46:33.535310 Hex of detail: 000000fe00523134304e574635205248200a
9312 12:46:33.538863 ASCII string: R140NWF5 RH
9313 12:46:33.539280 Checksum
9314 12:46:33.542097 Checksum: 0xfb (valid)
9315 12:46:33.545282 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9316 12:46:33.548985 DSI data_rate: 832800000 bps
9317 12:46:33.555104 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9318 12:46:33.558871 anx7625_parse_edid: pixelclock(138800).
9319 12:46:33.562056 hactive(1920), hsync(48), hfp(24), hbp(88)
9320 12:46:33.565349 vactive(1080), vsync(12), vfp(3), vbp(17)
9321 12:46:33.568022 anx7625_dsi_config: config dsi.
9322 12:46:33.574975 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9323 12:46:33.589662 anx7625_dsi_config: success to config DSI
9324 12:46:33.592687 anx7625_dp_start: MIPI phy setup OK.
9325 12:46:33.595754 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9326 12:46:33.599268 mtk_ddp_mode_set invalid vrefresh 60
9327 12:46:33.602368 main_disp_path_setup
9328 12:46:33.602787 ovl_layer_smi_id_en
9329 12:46:33.605981 ovl_layer_smi_id_en
9330 12:46:33.606388 ccorr_config
9331 12:46:33.606704 aal_config
9332 12:46:33.608853 gamma_config
9333 12:46:33.609257 postmask_config
9334 12:46:33.612078 dither_config
9335 12:46:33.615594 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9336 12:46:33.622073 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9337 12:46:33.625849 Root Device init finished in 551 msecs
9338 12:46:33.629097 CPU_CLUSTER: 0 init
9339 12:46:33.635433 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9340 12:46:33.641989 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9341 12:46:33.642397 APU_MBOX 0x190000b0 = 0x10001
9342 12:46:33.645646 APU_MBOX 0x190001b0 = 0x10001
9343 12:46:33.648588 APU_MBOX 0x190005b0 = 0x10001
9344 12:46:33.652149 APU_MBOX 0x190006b0 = 0x10001
9345 12:46:33.658778 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9346 12:46:33.668563 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9347 12:46:33.680693 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9348 12:46:33.686945 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9349 12:46:33.699060 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9350 12:46:33.708180 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9351 12:46:33.711298 CPU_CLUSTER: 0 init finished in 81 msecs
9352 12:46:33.714489 Devices initialized
9353 12:46:33.717870 Show all devs... After init.
9354 12:46:33.718278 Root Device: enabled 1
9355 12:46:33.721071 CPU_CLUSTER: 0: enabled 1
9356 12:46:33.724243 CPU: 00: enabled 1
9357 12:46:33.727554 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9358 12:46:33.731612 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9359 12:46:33.734183 ELOG: NV offset 0x57f000 size 0x1000
9360 12:46:33.741313 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9361 12:46:33.747447 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9362 12:46:33.750854 ELOG: Event(17) added with size 13 at 2023-06-14 12:46:34 UTC
9363 12:46:33.757888 out: cmd=0x121: 03 db 21 01 00 00 00 00
9364 12:46:33.760533 in-header: 03 32 00 00 2c 00 00 00
9365 12:46:33.770570 in-data: 2d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9366 12:46:33.777163 ELOG: Event(A1) added with size 10 at 2023-06-14 12:46:34 UTC
9367 12:46:33.783820 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9368 12:46:33.790387 ELOG: Event(A0) added with size 9 at 2023-06-14 12:46:34 UTC
9369 12:46:33.794185 elog_add_boot_reason: Logged dev mode boot
9370 12:46:33.800460 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9371 12:46:33.800872 Finalize devices...
9372 12:46:33.803639 Devices finalized
9373 12:46:33.806717 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9374 12:46:33.810296 Writing coreboot table at 0xffe64000
9375 12:46:33.814019 0. 000000000010a000-0000000000113fff: RAMSTAGE
9376 12:46:33.820078 1. 0000000040000000-00000000400fffff: RAM
9377 12:46:33.823588 2. 0000000040100000-000000004032afff: RAMSTAGE
9378 12:46:33.826480 3. 000000004032b000-00000000545fffff: RAM
9379 12:46:33.830609 4. 0000000054600000-000000005465ffff: BL31
9380 12:46:33.833074 5. 0000000054660000-00000000ffe63fff: RAM
9381 12:46:33.839715 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9382 12:46:33.842962 7. 0000000100000000-000000023fffffff: RAM
9383 12:46:33.846352 Passing 5 GPIOs to payload:
9384 12:46:33.849623 NAME | PORT | POLARITY | VALUE
9385 12:46:33.856096 EC in RW | 0x000000aa | low | undefined
9386 12:46:33.859577 EC interrupt | 0x00000005 | low | undefined
9387 12:46:33.866347 TPM interrupt | 0x000000ab | high | undefined
9388 12:46:33.869190 SD card detect | 0x00000011 | high | undefined
9389 12:46:33.872487 speaker enable | 0x00000093 | high | undefined
9390 12:46:33.875618 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9391 12:46:33.879819 in-header: 03 f9 00 00 02 00 00 00
9392 12:46:33.882569 in-data: 02 00
9393 12:46:33.886331 ADC[4]: Raw value=902216 ID=7
9394 12:46:33.889289 ADC[3]: Raw value=213916 ID=1
9395 12:46:33.889713 RAM Code: 0x71
9396 12:46:33.892567 ADC[6]: Raw value=75000 ID=0
9397 12:46:33.896420 ADC[5]: Raw value=213916 ID=1
9398 12:46:33.896820 SKU Code: 0x1
9399 12:46:33.902690 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 951a
9400 12:46:33.903135 coreboot table: 964 bytes.
9401 12:46:33.906102 IMD ROOT 0. 0xfffff000 0x00001000
9402 12:46:33.909652 IMD SMALL 1. 0xffffe000 0x00001000
9403 12:46:33.912323 RO MCACHE 2. 0xffffc000 0x00001104
9404 12:46:33.915652 CONSOLE 3. 0xfff7c000 0x00080000
9405 12:46:33.919151 FMAP 4. 0xfff7b000 0x00000452
9406 12:46:33.922194 TIME STAMP 5. 0xfff7a000 0x00000910
9407 12:46:33.925908 VBOOT WORK 6. 0xfff66000 0x00014000
9408 12:46:33.928817 RAMOOPS 7. 0xffe66000 0x00100000
9409 12:46:33.932700 COREBOOT 8. 0xffe64000 0x00002000
9410 12:46:33.935534 IMD small region:
9411 12:46:33.938757 IMD ROOT 0. 0xffffec00 0x00000400
9412 12:46:33.941968 VPD 1. 0xffffeba0 0x0000004c
9413 12:46:33.945254 MMC STATUS 2. 0xffffeb80 0x00000004
9414 12:46:33.952567 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9415 12:46:33.952989 Probing TPM: done!
9416 12:46:33.958744 Connected to device vid:did:rid of 1ae0:0028:00
9417 12:46:33.965405 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9418 12:46:33.968523 Initialized TPM device CR50 revision 0
9419 12:46:33.972249 Checking cr50 for pending updates
9420 12:46:33.978249 Reading cr50 TPM mode
9421 12:46:33.986741 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9422 12:46:33.992641 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9423 12:46:34.033339 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9424 12:46:34.036136 Checking segment from ROM address 0x40100000
9425 12:46:34.039624 Checking segment from ROM address 0x4010001c
9426 12:46:34.046127 Loading segment from ROM address 0x40100000
9427 12:46:34.046545 code (compression=0)
9428 12:46:34.056137 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9429 12:46:34.063112 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9430 12:46:34.063531 it's not compressed!
9431 12:46:34.069650 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9432 12:46:34.075789 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9433 12:46:34.093242 Loading segment from ROM address 0x4010001c
9434 12:46:34.093661 Entry Point 0x80000000
9435 12:46:34.097217 Loaded segments
9436 12:46:34.099961 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9437 12:46:34.106789 Jumping to boot code at 0x80000000(0xffe64000)
9438 12:46:34.113599 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9439 12:46:34.120007 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9440 12:46:34.128149 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9441 12:46:34.131375 Checking segment from ROM address 0x40100000
9442 12:46:34.134465 Checking segment from ROM address 0x4010001c
9443 12:46:34.141285 Loading segment from ROM address 0x40100000
9444 12:46:34.141701 code (compression=1)
9445 12:46:34.147798 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9446 12:46:34.158146 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9447 12:46:34.158561 using LZMA
9448 12:46:34.166216 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9449 12:46:34.172644 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9450 12:46:34.175962 Loading segment from ROM address 0x4010001c
9451 12:46:34.176421 Entry Point 0x54601000
9452 12:46:34.179387 Loaded segments
9453 12:46:34.182917 NOTICE: MT8192 bl31_setup
9454 12:46:34.189784 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9455 12:46:34.193010 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9456 12:46:34.196345 WARNING: region 0:
9457 12:46:34.199914 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9458 12:46:34.200374 WARNING: region 1:
9459 12:46:34.206368 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9460 12:46:34.209802 WARNING: region 2:
9461 12:46:34.213076 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9462 12:46:34.216351 WARNING: region 3:
9463 12:46:34.219891 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 12:46:34.223508 WARNING: region 4:
9465 12:46:34.229542 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9466 12:46:34.229961 WARNING: region 5:
9467 12:46:34.233446 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 12:46:34.236802 WARNING: region 6:
9469 12:46:34.239754 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 12:46:34.242763 WARNING: region 7:
9471 12:46:34.246581 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 12:46:34.252963 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9473 12:46:34.256583 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9474 12:46:34.259405 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9475 12:46:34.266656 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9476 12:46:34.269764 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9477 12:46:34.273087 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9478 12:46:34.279820 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9479 12:46:34.282597 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9480 12:46:34.289138 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9481 12:46:34.292668 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9482 12:46:34.296119 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9483 12:46:34.302691 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9484 12:46:34.306034 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9485 12:46:34.312438 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9486 12:46:34.316003 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9487 12:46:34.319209 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9488 12:46:34.325903 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9489 12:46:34.329282 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9490 12:46:34.335849 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9491 12:46:34.338785 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9492 12:46:34.342680 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9493 12:46:34.348841 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9494 12:46:34.352939 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9495 12:46:34.355468 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9496 12:46:34.362196 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9497 12:46:34.365576 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9498 12:46:34.372062 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9499 12:46:34.375517 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9500 12:46:34.381767 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9501 12:46:34.384973 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9502 12:46:34.388499 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9503 12:46:34.395220 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9504 12:46:34.398776 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9505 12:46:34.401766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9506 12:46:34.405224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9507 12:46:34.411988 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9508 12:46:34.415599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9509 12:46:34.418633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9510 12:46:34.421747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9511 12:46:34.428834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9512 12:46:34.432024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9513 12:46:34.434843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9514 12:46:34.438673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9515 12:46:34.444960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9516 12:46:34.448148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9517 12:46:34.451634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9518 12:46:34.455031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9519 12:46:34.461564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9520 12:46:34.464981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9521 12:46:34.471830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9522 12:46:34.474805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9523 12:46:34.478477 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9524 12:46:34.484691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9525 12:46:34.488297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9526 12:46:34.495436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9527 12:46:34.498208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9528 12:46:34.504599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9529 12:46:34.509188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9530 12:46:34.511526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9531 12:46:34.517981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9532 12:46:34.521579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9533 12:46:34.527901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9534 12:46:34.531473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9535 12:46:34.537915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9536 12:46:34.541791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9537 12:46:34.548253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9538 12:46:34.551140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9539 12:46:34.554811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9540 12:46:34.561108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9541 12:46:34.564602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9542 12:46:34.571273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9543 12:46:34.574683 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9544 12:46:34.580997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9545 12:46:34.584211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9546 12:46:34.591627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9547 12:46:34.594436 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9548 12:46:34.597615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9549 12:46:34.604434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9550 12:46:34.607427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9551 12:46:34.614534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9552 12:46:34.617980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9553 12:46:34.624188 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9554 12:46:34.627413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9555 12:46:34.634267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9556 12:46:34.637435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9557 12:46:34.640764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9558 12:46:34.647711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9559 12:46:34.651140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9560 12:46:34.657831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9561 12:46:34.660593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9562 12:46:34.667332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9563 12:46:34.670494 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9564 12:46:34.674270 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9565 12:46:34.680563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9566 12:46:34.683837 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9567 12:46:34.690605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9568 12:46:34.694865 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9569 12:46:34.697199 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9570 12:46:34.703866 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9571 12:46:34.707016 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9572 12:46:34.710485 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9573 12:46:34.714030 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9574 12:46:34.720203 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9575 12:46:34.724072 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9576 12:46:34.730298 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9577 12:46:34.734028 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9578 12:46:34.740100 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9579 12:46:34.743215 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9580 12:46:34.747166 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9581 12:46:34.753575 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9582 12:46:34.757106 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9583 12:46:34.763296 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9584 12:46:34.766138 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9585 12:46:34.769774 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9586 12:46:34.776654 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9587 12:46:34.779828 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9588 12:46:34.783150 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9589 12:46:34.789730 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9590 12:46:34.793003 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9591 12:46:34.796412 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9592 12:46:34.803383 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9593 12:46:34.806483 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9594 12:46:34.809540 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9595 12:46:34.813019 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9596 12:46:34.820026 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9597 12:46:34.823085 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9598 12:46:34.829762 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9599 12:46:34.832549 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9600 12:46:34.836403 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9601 12:46:34.842677 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9602 12:46:34.846218 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9603 12:46:34.852996 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9604 12:46:34.856176 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9605 12:46:34.859676 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9606 12:46:34.866199 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9607 12:46:34.869601 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9608 12:46:34.875986 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9609 12:46:34.879408 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9610 12:46:34.882731 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9611 12:46:34.889036 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9612 12:46:34.892455 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9613 12:46:34.895674 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9614 12:46:34.902565 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9615 12:46:34.905569 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9616 12:46:34.912276 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9617 12:46:34.915406 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9618 12:46:34.918759 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9619 12:46:34.926077 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9620 12:46:34.929248 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9621 12:46:34.935766 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9622 12:46:34.939106 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9623 12:46:34.942312 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9624 12:46:34.948728 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9625 12:46:34.952677 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9626 12:46:34.958942 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9627 12:46:34.962005 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9628 12:46:34.965292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9629 12:46:34.972686 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9630 12:46:34.975488 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9631 12:46:34.979072 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9632 12:46:34.985086 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9633 12:46:34.988547 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9634 12:46:34.996201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9635 12:46:34.998702 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9636 12:46:35.005294 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9637 12:46:35.009064 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9638 12:46:35.011764 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9639 12:46:35.018347 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9640 12:46:35.021471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9641 12:46:35.025576 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9642 12:46:35.031302 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9643 12:46:35.035306 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9644 12:46:35.041633 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9645 12:46:35.044597 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9646 12:46:35.048273 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9647 12:46:35.054610 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9648 12:46:35.057761 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9649 12:46:35.064513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9650 12:46:35.068293 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9651 12:46:35.070713 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9652 12:46:35.077623 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9653 12:46:35.081003 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9654 12:46:35.087705 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9655 12:46:35.090486 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9656 12:46:35.096928 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9657 12:46:35.100460 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9658 12:46:35.104469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9659 12:46:35.110374 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9660 12:46:35.114672 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9661 12:46:35.120486 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9662 12:46:35.123759 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9663 12:46:35.130587 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9664 12:46:35.133443 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9665 12:46:35.136814 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9666 12:46:35.143183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9667 12:46:35.146827 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9668 12:46:35.153267 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9669 12:46:35.156394 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9670 12:46:35.163248 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9671 12:46:35.166540 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9672 12:46:35.169508 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9673 12:46:35.176239 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9674 12:46:35.179315 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9675 12:46:35.185888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9676 12:46:35.189378 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9677 12:46:35.196017 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9678 12:46:35.198954 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9679 12:46:35.202767 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9680 12:46:35.208936 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9681 12:46:35.212434 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9682 12:46:35.218911 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9683 12:46:35.222273 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9684 12:46:35.228643 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9685 12:46:35.231927 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9686 12:46:35.235900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9687 12:46:35.242332 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9688 12:46:35.245376 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9689 12:46:35.252128 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9690 12:46:35.255061 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9691 12:46:35.261343 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9692 12:46:35.264890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9693 12:46:35.268154 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9694 12:46:35.274448 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9695 12:46:35.278173 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9696 12:46:35.284275 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9697 12:46:35.287805 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9698 12:46:35.295002 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9699 12:46:35.297940 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9700 12:46:35.300521 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9701 12:46:35.307300 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9702 12:46:35.311048 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9703 12:46:35.314122 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9704 12:46:35.317344 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9705 12:46:35.323830 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9706 12:46:35.327181 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9707 12:46:35.330566 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9708 12:46:35.336921 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9709 12:46:35.340286 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9710 12:46:35.343314 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9711 12:46:35.350406 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9712 12:46:35.353732 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9713 12:46:35.360107 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9714 12:46:35.363838 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9715 12:46:35.366933 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9716 12:46:35.373021 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9717 12:46:35.376612 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9718 12:46:35.383166 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9719 12:46:35.386454 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9720 12:46:35.389396 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9721 12:46:35.396243 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9722 12:46:35.399697 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9723 12:46:35.402771 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9724 12:46:35.409685 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9725 12:46:35.412542 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9726 12:46:35.419290 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9727 12:46:35.422627 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9728 12:46:35.426114 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9729 12:46:35.432570 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9730 12:46:35.436618 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9731 12:46:35.438911 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9732 12:46:35.445362 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9733 12:46:35.448916 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9734 12:46:35.455713 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9735 12:46:35.458459 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9736 12:46:35.462121 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9737 12:46:35.468830 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9738 12:46:35.472381 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9739 12:46:35.478563 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9740 12:46:35.481963 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9741 12:46:35.485663 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9742 12:46:35.488432 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9743 12:46:35.491685 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9744 12:46:35.498849 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9745 12:46:35.502003 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9746 12:46:35.505048 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9747 12:46:35.508114 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9748 12:46:35.514650 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9749 12:46:35.518156 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9750 12:46:35.521646 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9751 12:46:35.525133 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9752 12:46:35.531342 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9753 12:46:35.534694 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9754 12:46:35.541151 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9755 12:46:35.544665 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9756 12:46:35.547801 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9757 12:46:35.554062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9758 12:46:35.557813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9759 12:46:35.564109 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9760 12:46:35.567497 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9761 12:46:35.574016 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9762 12:46:35.577029 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9763 12:46:35.580291 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9764 12:46:35.587167 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9765 12:46:35.590447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9766 12:46:35.597049 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9767 12:46:35.600183 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9768 12:46:35.606751 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9769 12:46:35.610195 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9770 12:46:35.613629 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9771 12:46:35.620205 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9772 12:46:35.623274 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9773 12:46:35.629792 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9774 12:46:35.633075 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9775 12:46:35.640080 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9776 12:46:35.643154 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9777 12:46:35.646565 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9778 12:46:35.652619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9779 12:46:35.656388 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9780 12:46:35.662585 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9781 12:46:35.665992 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9782 12:46:35.669401 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9783 12:46:35.675787 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9784 12:46:35.678923 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9785 12:46:35.685735 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9786 12:46:35.689020 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9787 12:46:35.692269 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9788 12:46:35.699322 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9789 12:46:35.702068 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9790 12:46:35.708857 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9791 12:46:35.712422 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9792 12:46:35.718581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9793 12:46:35.722096 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9794 12:46:35.725712 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9795 12:46:35.732178 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9796 12:46:35.735199 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9797 12:46:35.741964 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9798 12:46:35.745152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9799 12:46:35.751550 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9800 12:46:35.754879 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9801 12:46:35.758225 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9802 12:46:35.764833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9803 12:46:35.768138 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9804 12:46:35.774937 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9805 12:46:35.778285 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9806 12:46:35.784486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9807 12:46:35.787482 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9808 12:46:35.790777 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9809 12:46:35.797666 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9810 12:46:35.800967 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9811 12:46:35.807426 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9812 12:46:35.810868 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9813 12:46:35.814537 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9814 12:46:35.820726 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9815 12:46:35.824695 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9816 12:46:35.830362 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9817 12:46:35.834382 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9818 12:46:35.840521 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9819 12:46:35.844011 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9820 12:46:35.847225 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9821 12:46:35.853890 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9822 12:46:35.856680 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9823 12:46:35.863513 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9824 12:46:35.867080 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9825 12:46:35.870297 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9826 12:46:35.876594 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9827 12:46:35.879876 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9828 12:46:35.886199 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9829 12:46:35.889825 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9830 12:46:35.896118 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9831 12:46:35.899161 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9832 12:46:35.906082 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9833 12:46:35.908991 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9834 12:46:35.915636 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9835 12:46:35.919155 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9836 12:46:35.922635 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9837 12:46:35.928855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9838 12:46:35.932478 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9839 12:46:35.939015 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9840 12:46:35.942248 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9841 12:46:35.949304 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9842 12:46:35.951821 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9843 12:46:35.958426 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9844 12:46:35.962201 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9845 12:46:35.968873 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9846 12:46:35.971950 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9847 12:46:35.975169 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9848 12:46:35.981720 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9849 12:46:35.985194 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9850 12:46:35.991306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9851 12:46:35.994756 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9852 12:46:36.001628 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9853 12:46:36.005666 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9854 12:46:36.011611 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9855 12:46:36.014950 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9856 12:46:36.021300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9857 12:46:36.024415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9858 12:46:36.028187 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9859 12:46:36.034422 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9860 12:46:36.037595 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9861 12:46:36.044149 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9862 12:46:36.047356 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9863 12:46:36.054631 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9864 12:46:36.057291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9865 12:46:36.060901 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9866 12:46:36.067078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9867 12:46:36.070416 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9868 12:46:36.077293 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9869 12:46:36.080306 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9870 12:46:36.087058 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9871 12:46:36.090333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9872 12:46:36.097431 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9873 12:46:36.100093 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9874 12:46:36.103625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9875 12:46:36.110271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9876 12:46:36.113457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9877 12:46:36.119998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9878 12:46:36.123198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9879 12:46:36.129776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9880 12:46:36.132999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9881 12:46:36.139357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9882 12:46:36.142528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9883 12:46:36.149650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9884 12:46:36.152775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9885 12:46:36.159060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9886 12:46:36.162774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9887 12:46:36.169225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9888 12:46:36.172538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9889 12:46:36.179176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9890 12:46:36.182071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9891 12:46:36.188949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9892 12:46:36.192238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9893 12:46:36.198736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9894 12:46:36.202745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9895 12:46:36.209050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9896 12:46:36.211940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9897 12:46:36.218351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9898 12:46:36.221850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9899 12:46:36.228286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9900 12:46:36.231410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9901 12:46:36.238150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9902 12:46:36.241581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9903 12:46:36.247919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9904 12:46:36.251625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9905 12:46:36.258226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9906 12:46:36.261001 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9907 12:46:36.264662 INFO: [APUAPC] vio 0
9908 12:46:36.268105 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9909 12:46:36.275296 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9910 12:46:36.278073 INFO: [APUAPC] D0_APC_0: 0x400510
9911 12:46:36.281014 INFO: [APUAPC] D0_APC_1: 0x0
9912 12:46:36.284494 INFO: [APUAPC] D0_APC_2: 0x1540
9913 12:46:36.284913 INFO: [APUAPC] D0_APC_3: 0x0
9914 12:46:36.287548 INFO: [APUAPC] D1_APC_0: 0xffffffff
9915 12:46:36.290991 INFO: [APUAPC] D1_APC_1: 0xffffffff
9916 12:46:36.294602 INFO: [APUAPC] D1_APC_2: 0x3fffff
9917 12:46:36.297549 INFO: [APUAPC] D1_APC_3: 0x0
9918 12:46:36.300888 INFO: [APUAPC] D2_APC_0: 0xffffffff
9919 12:46:36.304097 INFO: [APUAPC] D2_APC_1: 0xffffffff
9920 12:46:36.307152 INFO: [APUAPC] D2_APC_2: 0x3fffff
9921 12:46:36.311018 INFO: [APUAPC] D2_APC_3: 0x0
9922 12:46:36.314159 INFO: [APUAPC] D3_APC_0: 0xffffffff
9923 12:46:36.317351 INFO: [APUAPC] D3_APC_1: 0xffffffff
9924 12:46:36.320270 INFO: [APUAPC] D3_APC_2: 0x3fffff
9925 12:46:36.323854 INFO: [APUAPC] D3_APC_3: 0x0
9926 12:46:36.326900 INFO: [APUAPC] D4_APC_0: 0xffffffff
9927 12:46:36.330135 INFO: [APUAPC] D4_APC_1: 0xffffffff
9928 12:46:36.333591 INFO: [APUAPC] D4_APC_2: 0x3fffff
9929 12:46:36.336900 INFO: [APUAPC] D4_APC_3: 0x0
9930 12:46:36.340023 INFO: [APUAPC] D5_APC_0: 0xffffffff
9931 12:46:36.343470 INFO: [APUAPC] D5_APC_1: 0xffffffff
9932 12:46:36.346755 INFO: [APUAPC] D5_APC_2: 0x3fffff
9933 12:46:36.350824 INFO: [APUAPC] D5_APC_3: 0x0
9934 12:46:36.353226 INFO: [APUAPC] D6_APC_0: 0xffffffff
9935 12:46:36.356685 INFO: [APUAPC] D6_APC_1: 0xffffffff
9936 12:46:36.359880 INFO: [APUAPC] D6_APC_2: 0x3fffff
9937 12:46:36.362841 INFO: [APUAPC] D6_APC_3: 0x0
9938 12:46:36.366349 INFO: [APUAPC] D7_APC_0: 0xffffffff
9939 12:46:36.369504 INFO: [APUAPC] D7_APC_1: 0xffffffff
9940 12:46:36.373350 INFO: [APUAPC] D7_APC_2: 0x3fffff
9941 12:46:36.376616 INFO: [APUAPC] D7_APC_3: 0x0
9942 12:46:36.379701 INFO: [APUAPC] D8_APC_0: 0xffffffff
9943 12:46:36.383307 INFO: [APUAPC] D8_APC_1: 0xffffffff
9944 12:46:36.386164 INFO: [APUAPC] D8_APC_2: 0x3fffff
9945 12:46:36.389407 INFO: [APUAPC] D8_APC_3: 0x0
9946 12:46:36.392850 INFO: [APUAPC] D9_APC_0: 0xffffffff
9947 12:46:36.396159 INFO: [APUAPC] D9_APC_1: 0xffffffff
9948 12:46:36.399769 INFO: [APUAPC] D9_APC_2: 0x3fffff
9949 12:46:36.403244 INFO: [APUAPC] D9_APC_3: 0x0
9950 12:46:36.405927 INFO: [APUAPC] D10_APC_0: 0xffffffff
9951 12:46:36.409110 INFO: [APUAPC] D10_APC_1: 0xffffffff
9952 12:46:36.412748 INFO: [APUAPC] D10_APC_2: 0x3fffff
9953 12:46:36.416019 INFO: [APUAPC] D10_APC_3: 0x0
9954 12:46:36.419358 INFO: [APUAPC] D11_APC_0: 0xffffffff
9955 12:46:36.422588 INFO: [APUAPC] D11_APC_1: 0xffffffff
9956 12:46:36.425655 INFO: [APUAPC] D11_APC_2: 0x3fffff
9957 12:46:36.429076 INFO: [APUAPC] D11_APC_3: 0x0
9958 12:46:36.432131 INFO: [APUAPC] D12_APC_0: 0xffffffff
9959 12:46:36.435853 INFO: [APUAPC] D12_APC_1: 0xffffffff
9960 12:46:36.438749 INFO: [APUAPC] D12_APC_2: 0x3fffff
9961 12:46:36.442081 INFO: [APUAPC] D12_APC_3: 0x0
9962 12:46:36.445584 INFO: [APUAPC] D13_APC_0: 0xffffffff
9963 12:46:36.448939 INFO: [APUAPC] D13_APC_1: 0xffffffff
9964 12:46:36.452204 INFO: [APUAPC] D13_APC_2: 0x3fffff
9965 12:46:36.455150 INFO: [APUAPC] D13_APC_3: 0x0
9966 12:46:36.458637 INFO: [APUAPC] D14_APC_0: 0xffffffff
9967 12:46:36.461993 INFO: [APUAPC] D14_APC_1: 0xffffffff
9968 12:46:36.465386 INFO: [APUAPC] D14_APC_2: 0x3fffff
9969 12:46:36.468987 INFO: [APUAPC] D14_APC_3: 0x0
9970 12:46:36.471532 INFO: [APUAPC] D15_APC_0: 0xffffffff
9971 12:46:36.475095 INFO: [APUAPC] D15_APC_1: 0xffffffff
9972 12:46:36.478268 INFO: [APUAPC] D15_APC_2: 0x3fffff
9973 12:46:36.481956 INFO: [APUAPC] D15_APC_3: 0x0
9974 12:46:36.484952 INFO: [APUAPC] APC_CON: 0x4
9975 12:46:36.488451 INFO: [NOCDAPC] D0_APC_0: 0x0
9976 12:46:36.491672 INFO: [NOCDAPC] D0_APC_1: 0x0
9977 12:46:36.494820 INFO: [NOCDAPC] D1_APC_0: 0x0
9978 12:46:36.498297 INFO: [NOCDAPC] D1_APC_1: 0xfff
9979 12:46:36.501270 INFO: [NOCDAPC] D2_APC_0: 0x0
9980 12:46:36.504755 INFO: [NOCDAPC] D2_APC_1: 0xfff
9981 12:46:36.507765 INFO: [NOCDAPC] D3_APC_0: 0x0
9982 12:46:36.508220 INFO: [NOCDAPC] D3_APC_1: 0xfff
9983 12:46:36.510954 INFO: [NOCDAPC] D4_APC_0: 0x0
9984 12:46:36.514244 INFO: [NOCDAPC] D4_APC_1: 0xfff
9985 12:46:36.517948 INFO: [NOCDAPC] D5_APC_0: 0x0
9986 12:46:36.521159 INFO: [NOCDAPC] D5_APC_1: 0xfff
9987 12:46:36.524559 INFO: [NOCDAPC] D6_APC_0: 0x0
9988 12:46:36.527467 INFO: [NOCDAPC] D6_APC_1: 0xfff
9989 12:46:36.530667 INFO: [NOCDAPC] D7_APC_0: 0x0
9990 12:46:36.534051 INFO: [NOCDAPC] D7_APC_1: 0xfff
9991 12:46:36.537148 INFO: [NOCDAPC] D8_APC_0: 0x0
9992 12:46:36.540770 INFO: [NOCDAPC] D8_APC_1: 0xfff
9993 12:46:36.544572 INFO: [NOCDAPC] D9_APC_0: 0x0
9994 12:46:36.547203 INFO: [NOCDAPC] D9_APC_1: 0xfff
9995 12:46:36.547620 INFO: [NOCDAPC] D10_APC_0: 0x0
9996 12:46:36.550652 INFO: [NOCDAPC] D10_APC_1: 0xfff
9997 12:46:36.554041 INFO: [NOCDAPC] D11_APC_0: 0x0
9998 12:46:36.556975 INFO: [NOCDAPC] D11_APC_1: 0xfff
9999 12:46:36.560367 INFO: [NOCDAPC] D12_APC_0: 0x0
10000 12:46:36.563692 INFO: [NOCDAPC] D12_APC_1: 0xfff
10001 12:46:36.567033 INFO: [NOCDAPC] D13_APC_0: 0x0
10002 12:46:36.569988 INFO: [NOCDAPC] D13_APC_1: 0xfff
10003 12:46:36.573933 INFO: [NOCDAPC] D14_APC_0: 0x0
10004 12:46:36.576784 INFO: [NOCDAPC] D14_APC_1: 0xfff
10005 12:46:36.580130 INFO: [NOCDAPC] D15_APC_0: 0x0
10006 12:46:36.583610 INFO: [NOCDAPC] D15_APC_1: 0xfff
10007 12:46:36.586570 INFO: [NOCDAPC] APC_CON: 0x4
10008 12:46:36.590203 INFO: [APUAPC] set_apusys_apc done
10009 12:46:36.593273 INFO: [DEVAPC] devapc_init done
10010 12:46:36.596295 INFO: GICv3 without legacy support detected.
10011 12:46:36.599852 INFO: ARM GICv3 driver initialized in EL3
10012 12:46:36.602947 INFO: Maximum SPI INTID supported: 639
10013 12:46:36.606478 INFO: BL31: Initializing runtime services
10014 12:46:36.612796 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10015 12:46:36.616551 INFO: SPM: enable CPC mode
10016 12:46:36.622929 INFO: mcdi ready for mcusys-off-idle and system suspend
10017 12:46:36.625988 INFO: BL31: Preparing for EL3 exit to normal world
10018 12:46:36.629212 INFO: Entry point address = 0x80000000
10019 12:46:36.632897 INFO: SPSR = 0x8
10020 12:46:36.638063
10021 12:46:36.638478
10022 12:46:36.638810
10023 12:46:36.641518 Starting depthcharge on Spherion...
10024 12:46:36.641941
10025 12:46:36.642272 Wipe memory regions:
10026 12:46:36.642581
10027 12:46:36.644843 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10028 12:46:36.645332 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10029 12:46:36.645759 Setting prompt string to ['asurada:']
10030 12:46:36.646154 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10031 12:46:36.646813 [0x00000040000000, 0x00000054600000)
10032 12:46:36.767010
10033 12:46:36.767472 [0x00000054660000, 0x00000080000000)
10034 12:46:37.027684
10035 12:46:37.028226 [0x000000821a7280, 0x000000ffe64000)
10036 12:46:37.772435
10037 12:46:37.772939 [0x00000100000000, 0x00000240000000)
10038 12:46:39.662359
10039 12:46:39.666153 Initializing XHCI USB controller at 0x11200000.
10040 12:46:40.703763
10041 12:46:40.706501 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10042 12:46:40.706598
10043 12:46:40.706663
10044 12:46:40.706727
10045 12:46:40.707039 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 12:46:40.807425 asurada: tftpboot 192.168.201.1 10724911/tftp-deploy-q4vik08t/kernel/image.itb 10724911/tftp-deploy-q4vik08t/kernel/cmdline
10048 12:46:40.807601 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10049 12:46:40.807690 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10050 12:46:40.812234 tftpboot 192.168.201.1 10724911/tftp-deploy-q4vik08t/kernel/image.ittp-deploy-q4vik08t/kernel/cmdline
10051 12:46:40.812320
10052 12:46:40.812385 Waiting for link
10053 12:46:40.972170
10054 12:46:40.972321 R8152: Initializing
10055 12:46:40.972391
10056 12:46:40.975800 Version 6 (ocp_data = 5c30)
10057 12:46:40.975883
10058 12:46:40.979093 R8152: Done initializing
10059 12:46:40.979176
10060 12:46:40.979241 Adding net device
10061 12:46:43.007934
10062 12:46:43.008096 done.
10063 12:46:43.008249
10064 12:46:43.008348 MAC: 00:24:32:30:7c:7b
10065 12:46:43.008410
10066 12:46:43.010747 Sending DHCP discover... done.
10067 12:46:43.010829
10068 12:46:43.014068 Waiting for reply... done.
10069 12:46:43.014195
10070 12:46:43.017131 Sending DHCP request... done.
10071 12:46:43.017216
10072 12:46:43.017295 Waiting for reply... done.
10073 12:46:43.017368
10074 12:46:43.021184 My ip is 192.168.201.14
10075 12:46:43.021266
10076 12:46:43.023836 The DHCP server ip is 192.168.201.1
10077 12:46:43.023949
10078 12:46:43.027258 TFTP server IP predefined by user: 192.168.201.1
10079 12:46:43.027339
10080 12:46:43.034382 Bootfile predefined by user: 10724911/tftp-deploy-q4vik08t/kernel/image.itb
10081 12:46:43.034548
10082 12:46:43.036918 Sending tftp read request... done.
10083 12:46:43.037025
10084 12:46:43.040601 Waiting for the transfer...
10085 12:46:43.043495
10086 12:46:43.577340 00000000 ################################################################
10087 12:46:43.577488
10088 12:46:44.125479 00080000 ################################################################
10089 12:46:44.125629
10090 12:46:44.683318 00100000 ################################################################
10091 12:46:44.683467
10092 12:46:45.233654 00180000 ################################################################
10093 12:46:45.233807
10094 12:46:45.793630 00200000 ################################################################
10095 12:46:45.793778
10096 12:46:46.337397 00280000 ################################################################
10097 12:46:46.337545
10098 12:46:46.894715 00300000 ################################################################
10099 12:46:46.894861
10100 12:46:47.464521 00380000 ################################################################
10101 12:46:47.464668
10102 12:46:48.014103 00400000 ################################################################
10103 12:46:48.014237
10104 12:46:48.540537 00480000 ################################################################
10105 12:46:48.540680
10106 12:46:49.109809 00500000 ################################################################
10107 12:46:49.109950
10108 12:46:49.668441 00580000 ################################################################
10109 12:46:49.668598
10110 12:46:50.217295 00600000 ################################################################
10111 12:46:50.217451
10112 12:46:50.748555 00680000 ################################################################
10113 12:46:50.748711
10114 12:46:51.322645 00700000 ################################################################
10115 12:46:51.322800
10116 12:46:51.899394 00780000 ################################################################
10117 12:46:51.899548
10118 12:46:52.472073 00800000 ################################################################
10119 12:46:52.472226
10120 12:46:53.040018 00880000 ################################################################
10121 12:46:53.040223
10122 12:46:53.602154 00900000 ################################################################
10123 12:46:53.602312
10124 12:46:54.150919 00980000 ################################################################
10125 12:46:54.151076
10126 12:46:54.707516 00a00000 ################################################################
10127 12:46:54.707701
10128 12:46:55.260677 00a80000 ################################################################
10129 12:46:55.260833
10130 12:46:55.821971 00b00000 ################################################################
10131 12:46:55.822125
10132 12:46:56.386393 00b80000 ################################################################
10133 12:46:56.386545
10134 12:46:56.937174 00c00000 ################################################################
10135 12:46:56.937327
10136 12:46:57.494657 00c80000 ################################################################
10137 12:46:57.494805
10138 12:46:58.052749 00d00000 ################################################################
10139 12:46:58.052898
10140 12:46:58.625410 00d80000 ################################################################
10141 12:46:58.625562
10142 12:46:59.193040 00e00000 ################################################################
10143 12:46:59.193192
10144 12:46:59.746767 00e80000 ################################################################
10145 12:46:59.746923
10146 12:47:00.278866 00f00000 ################################################################
10147 12:47:00.279018
10148 12:47:00.809947 00f80000 ################################################################
10149 12:47:00.810088
10150 12:47:01.363257 01000000 ################################################################
10151 12:47:01.363384
10152 12:47:01.913001 01080000 ################################################################
10153 12:47:01.913136
10154 12:47:02.458466 01100000 ################################################################
10155 12:47:02.458601
10156 12:47:03.009387 01180000 ################################################################
10157 12:47:03.009546
10158 12:47:03.572288 01200000 ################################################################
10159 12:47:03.572424
10160 12:47:04.109644 01280000 ################################################################
10161 12:47:04.109800
10162 12:47:04.661881 01300000 ################################################################
10163 12:47:04.662016
10164 12:47:05.197998 01380000 ################################################################
10165 12:47:05.198133
10166 12:47:05.739569 01400000 ################################################################
10167 12:47:05.739736
10168 12:47:06.279899 01480000 ################################################################
10169 12:47:06.280033
10170 12:47:06.832252 01500000 ################################################################
10171 12:47:06.832388
10172 12:47:07.383463 01580000 ################################################################
10173 12:47:07.383600
10174 12:47:07.931400 01600000 ################################################################
10175 12:47:07.931536
10176 12:47:08.492131 01680000 ################################################################
10177 12:47:08.492286
10178 12:47:09.042321 01700000 ################################################################
10179 12:47:09.042466
10180 12:47:09.588616 01780000 ################################################################
10181 12:47:09.588752
10182 12:47:10.163991 01800000 ################################################################
10183 12:47:10.164148
10184 12:47:10.705491 01880000 ################################################################
10185 12:47:10.705667
10186 12:47:11.222968 01900000 ################################################################
10187 12:47:11.223102
10188 12:47:11.741791 01980000 ################################################################
10189 12:47:11.741931
10190 12:47:12.252592 01a00000 ################################################################
10191 12:47:12.252754
10192 12:47:12.599788 01a80000 ########################################## done.
10193 12:47:12.599922
10194 12:47:12.603352 The bootfile was 28130338 bytes long.
10195 12:47:12.603446
10196 12:47:12.606461 Sending tftp read request... done.
10197 12:47:12.606549
10198 12:47:12.606637 Waiting for the transfer...
10199 12:47:12.606718
10200 12:47:12.609567 00000000 # done.
10201 12:47:12.609665
10202 12:47:12.616111 Command line loaded dynamically from TFTP file: 10724911/tftp-deploy-q4vik08t/kernel/cmdline
10203 12:47:12.616197
10204 12:47:12.635463 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724911/extract-nfsrootfs-0ljjj21m,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10205 12:47:12.635579
10206 12:47:12.639139 Loading FIT.
10207 12:47:12.639247
10208 12:47:12.642282 Image ramdisk-1 has 17639001 bytes.
10209 12:47:12.642386
10210 12:47:12.642479 Image fdt-1 has 46924 bytes.
10211 12:47:12.642564
10212 12:47:12.645661 Image kernel-1 has 10442380 bytes.
10213 12:47:12.645770
10214 12:47:12.655282 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10215 12:47:12.655380
10216 12:47:12.671986 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10217 12:47:12.675148
10218 12:47:12.678290 Choosing best match conf-1 for compat google,spherion-rev2.
10219 12:47:12.682406
10220 12:47:12.687464 Connected to device vid:did:rid of 1ae0:0028:00
10221 12:47:12.694157
10222 12:47:12.697659 tpm_get_response: command 0x17b, return code 0x0
10223 12:47:12.697767
10224 12:47:12.704071 ec_init: CrosEC protocol v3 supported (256, 248)
10225 12:47:12.704172
10226 12:47:12.707262 tpm_cleanup: add release locality here.
10227 12:47:12.707343
10228 12:47:12.710865 Shutting down all USB controllers.
10229 12:47:12.710952
10230 12:47:12.714103 Removing current net device
10231 12:47:12.714202
10232 12:47:12.718111 Exiting depthcharge with code 4 at timestamp: 65315778
10233 12:47:12.718193
10234 12:47:12.720556 LZMA decompressing kernel-1 to 0x821a6718
10235 12:47:12.720633
10236 12:47:12.723787 LZMA decompressing kernel-1 to 0x40000000
10237 12:47:14.035969
10238 12:47:14.036128 jumping to kernel
10239 12:47:14.036765 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10240 12:47:14.036898 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10241 12:47:14.037002 Setting prompt string to ['Linux version [0-9]']
10242 12:47:14.037105 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10243 12:47:14.037278 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10244 12:47:14.118314
10245 12:47:14.121267 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10246 12:47:14.124639 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10247 12:47:14.124730 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10248 12:47:14.124818 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10249 12:47:14.124897 Using line separator: #'\n'#
10250 12:47:14.124958 No login prompt set.
10251 12:47:14.125022 Parsing kernel messages
10252 12:47:14.125078 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10253 12:47:14.125186 [login-action] Waiting for messages, (timeout 00:03:48)
10254 12:47:14.144573 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10255 12:47:14.147577 [ 0.000000] random: crng init done
10256 12:47:14.151206 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10257 12:47:14.154885 [ 0.000000] efi: UEFI not found.
10258 12:47:14.164808 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10259 12:47:14.170674 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10260 12:47:14.180558 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10261 12:47:14.190485 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10262 12:47:14.196741 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10263 12:47:14.204361 [ 0.000000] printk: bootconsole [mtk8250] enabled
10264 12:47:14.210298 [ 0.000000] NUMA: No NUMA configuration found
10265 12:47:14.216532 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10266 12:47:14.220046 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10267 12:47:14.223330 [ 0.000000] Zone ranges:
10268 12:47:14.229779 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10269 12:47:14.233014 [ 0.000000] DMA32 empty
10270 12:47:14.239548 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10271 12:47:14.243459 [ 0.000000] Movable zone start for each node
10272 12:47:14.246431 [ 0.000000] Early memory node ranges
10273 12:47:14.252679 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10274 12:47:14.259724 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10275 12:47:14.266214 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10276 12:47:14.272630 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10277 12:47:14.279442 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10278 12:47:14.285932 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10279 12:47:14.341057 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10280 12:47:14.347784 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10281 12:47:14.354875 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10282 12:47:14.358013 [ 0.000000] psci: probing for conduit method from DT.
10283 12:47:14.364968 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10284 12:47:14.367752 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10285 12:47:14.374121 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10286 12:47:14.377451 [ 0.000000] psci: SMC Calling Convention v1.2
10287 12:47:14.384197 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10288 12:47:14.387809 [ 0.000000] Detected VIPT I-cache on CPU0
10289 12:47:14.394543 [ 0.000000] CPU features: detected: GIC system register CPU interface
10290 12:47:14.400752 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10291 12:47:14.407445 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10292 12:47:14.413907 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10293 12:47:14.423619 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10294 12:47:14.430687 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10295 12:47:14.434051 [ 0.000000] alternatives: applying boot alternatives
10296 12:47:14.440317 [ 0.000000] Fallback order for Node 0: 0
10297 12:47:14.447074 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10298 12:47:14.450006 [ 0.000000] Policy zone: Normal
10299 12:47:14.470352 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10724911/extract-nfsrootfs-0ljjj21m,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10300 12:47:14.480157 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10301 12:47:14.492015 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10302 12:47:14.501910 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10303 12:47:14.508201 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10304 12:47:14.512053 <6>[ 0.000000] software IO TLB: area num 8.
10305 12:47:14.569233 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10306 12:47:14.718813 <6>[ 0.000000] Memory: 7953936K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398832K reserved, 32768K cma-reserved)
10307 12:47:14.724561 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10308 12:47:14.731577 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10309 12:47:14.734632 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10310 12:47:14.740927 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10311 12:47:14.747969 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10312 12:47:14.754400 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10313 12:47:14.760722 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10314 12:47:14.766890 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10315 12:47:14.774237 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10316 12:47:14.780739 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10317 12:47:14.783461 <6>[ 0.000000] GICv3: 608 SPIs implemented
10318 12:47:14.787289 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10319 12:47:14.793501 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10320 12:47:14.796941 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10321 12:47:14.803723 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10322 12:47:14.816630 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10323 12:47:14.830046 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10324 12:47:14.836270 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10325 12:47:14.844655 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10326 12:47:14.857910 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10327 12:47:14.864642 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10328 12:47:14.871534 <6>[ 0.009178] Console: colour dummy device 80x25
10329 12:47:14.881257 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10330 12:47:14.887694 <6>[ 0.024376] pid_max: default: 32768 minimum: 301
10331 12:47:14.891274 <6>[ 0.029279] LSM: Security Framework initializing
10332 12:47:14.897965 <6>[ 0.034218] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10333 12:47:14.907973 <6>[ 0.042033] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10334 12:47:14.917514 <6>[ 0.051453] cblist_init_generic: Setting adjustable number of callback queues.
10335 12:47:14.920576 <6>[ 0.058951] cblist_init_generic: Setting shift to 3 and lim to 1.
10336 12:47:14.927675 <6>[ 0.065291] cblist_init_generic: Setting shift to 3 and lim to 1.
10337 12:47:14.933991 <6>[ 0.071699] rcu: Hierarchical SRCU implementation.
10338 12:47:14.940510 <6>[ 0.076713] rcu: Max phase no-delay instances is 1000.
10339 12:47:14.946960 <6>[ 0.083727] EFI services will not be available.
10340 12:47:14.950495 <6>[ 0.088702] smp: Bringing up secondary CPUs ...
10341 12:47:14.958023 <6>[ 0.093752] Detected VIPT I-cache on CPU1
10342 12:47:14.964535 <6>[ 0.093823] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10343 12:47:14.971387 <6>[ 0.093856] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10344 12:47:14.974796 <6>[ 0.094190] Detected VIPT I-cache on CPU2
10345 12:47:14.981161 <6>[ 0.094246] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10346 12:47:14.991361 <6>[ 0.094264] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10347 12:47:14.995119 <6>[ 0.094526] Detected VIPT I-cache on CPU3
10348 12:47:15.000940 <6>[ 0.094575] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10349 12:47:15.008061 <6>[ 0.094590] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10350 12:47:15.010942 <6>[ 0.094894] CPU features: detected: Spectre-v4
10351 12:47:15.017530 <6>[ 0.094903] CPU features: detected: Spectre-BHB
10352 12:47:15.020701 <6>[ 0.094910] Detected PIPT I-cache on CPU4
10353 12:47:15.027177 <6>[ 0.094968] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10354 12:47:15.034463 <6>[ 0.094985] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10355 12:47:15.040426 <6>[ 0.095278] Detected PIPT I-cache on CPU5
10356 12:47:15.047372 <6>[ 0.095340] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10357 12:47:15.054530 <6>[ 0.095356] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10358 12:47:15.057441 <6>[ 0.095640] Detected PIPT I-cache on CPU6
10359 12:47:15.063475 <6>[ 0.095705] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10360 12:47:15.073774 <6>[ 0.095721] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10361 12:47:15.076960 <6>[ 0.096017] Detected PIPT I-cache on CPU7
10362 12:47:15.083547 <6>[ 0.096080] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10363 12:47:15.089473 <6>[ 0.096097] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10364 12:47:15.092983 <6>[ 0.096143] smp: Brought up 1 node, 8 CPUs
10365 12:47:15.099534 <6>[ 0.237377] SMP: Total of 8 processors activated.
10366 12:47:15.102964 <6>[ 0.242298] CPU features: detected: 32-bit EL0 Support
10367 12:47:15.112821 <6>[ 0.247695] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10368 12:47:15.119507 <6>[ 0.256495] CPU features: detected: Common not Private translations
10369 12:47:15.126266 <6>[ 0.262971] CPU features: detected: CRC32 instructions
10370 12:47:15.133074 <6>[ 0.268356] CPU features: detected: RCpc load-acquire (LDAPR)
10371 12:47:15.136006 <6>[ 0.274352] CPU features: detected: LSE atomic instructions
10372 12:47:15.142697 <6>[ 0.280133] CPU features: detected: Privileged Access Never
10373 12:47:15.149149 <6>[ 0.285949] CPU features: detected: RAS Extension Support
10374 12:47:15.155562 <6>[ 0.291557] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10375 12:47:15.159222 <6>[ 0.298776] CPU: All CPU(s) started at EL2
10376 12:47:15.165930 <6>[ 0.303120] alternatives: applying system-wide alternatives
10377 12:47:15.175841 <6>[ 0.313867] devtmpfs: initialized
10378 12:47:15.191231 <6>[ 0.322723] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10379 12:47:15.198057 <6>[ 0.332688] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10380 12:47:15.204476 <6>[ 0.340920] pinctrl core: initialized pinctrl subsystem
10381 12:47:15.208085 <6>[ 0.347583] DMI not present or invalid.
10382 12:47:15.214101 <6>[ 0.351991] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10383 12:47:15.224531 <6>[ 0.358871] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10384 12:47:15.230890 <6>[ 0.366444] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10385 12:47:15.240577 <6>[ 0.374668] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10386 12:47:15.243962 <6>[ 0.382906] audit: initializing netlink subsys (disabled)
10387 12:47:15.254588 <5>[ 0.388601] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10388 12:47:15.260420 <6>[ 0.389297] thermal_sys: Registered thermal governor 'step_wise'
10389 12:47:15.267270 <6>[ 0.396570] thermal_sys: Registered thermal governor 'power_allocator'
10390 12:47:15.270654 <6>[ 0.402829] cpuidle: using governor menu
10391 12:47:15.277191 <6>[ 0.413785] NET: Registered PF_QIPCRTR protocol family
10392 12:47:15.283696 <6>[ 0.419273] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10393 12:47:15.289999 <6>[ 0.426376] ASID allocator initialised with 32768 entries
10394 12:47:15.293198 <6>[ 0.432939] Serial: AMBA PL011 UART driver
10395 12:47:15.303652 <4>[ 0.441597] Trying to register duplicate clock ID: 134
10396 12:47:15.358478 <6>[ 0.498999] KASLR enabled
10397 12:47:15.372028 <6>[ 0.506735] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10398 12:47:15.378665 <6>[ 0.513749] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10399 12:47:15.385711 <6>[ 0.520240] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10400 12:47:15.391901 <6>[ 0.527249] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10401 12:47:15.398488 <6>[ 0.533737] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10402 12:47:15.404939 <6>[ 0.540738] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10403 12:47:15.411414 <6>[ 0.547226] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10404 12:47:15.417654 <6>[ 0.554231] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10405 12:47:15.421793 <6>[ 0.561741] ACPI: Interpreter disabled.
10406 12:47:15.430158 <6>[ 0.568069] iommu: Default domain type: Translated
10407 12:47:15.436661 <6>[ 0.573179] iommu: DMA domain TLB invalidation policy: strict mode
10408 12:47:15.440071 <5>[ 0.579832] SCSI subsystem initialized
10409 12:47:15.449350 <6>[ 0.583994] usbcore: registered new interface driver usbfs
10410 12:47:15.452889 <6>[ 0.589729] usbcore: registered new interface driver hub
10411 12:47:15.457026 <6>[ 0.595276] usbcore: registered new device driver usb
10412 12:47:15.463279 <6>[ 0.601361] pps_core: LinuxPPS API ver. 1 registered
10413 12:47:15.473163 <6>[ 0.606551] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10414 12:47:15.476910 <6>[ 0.615895] PTP clock support registered
10415 12:47:15.480024 <6>[ 0.620138] EDAC MC: Ver: 3.0.0
10416 12:47:15.487359 <6>[ 0.625286] FPGA manager framework
10417 12:47:15.493966 <6>[ 0.628965] Advanced Linux Sound Architecture Driver Initialized.
10418 12:47:15.497104 <6>[ 0.635737] vgaarb: loaded
10419 12:47:15.503477 <6>[ 0.638911] clocksource: Switched to clocksource arch_sys_counter
10420 12:47:15.507010 <5>[ 0.645350] VFS: Disk quotas dquot_6.6.0
10421 12:47:15.513633 <6>[ 0.649539] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10422 12:47:15.516641 <6>[ 0.656729] pnp: PnP ACPI: disabled
10423 12:47:15.525735 <6>[ 0.663448] NET: Registered PF_INET protocol family
10424 12:47:15.535207 <6>[ 0.669045] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10425 12:47:15.546426 <6>[ 0.681335] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10426 12:47:15.556874 <6>[ 0.690151] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10427 12:47:15.562898 <6>[ 0.698122] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10428 12:47:15.572908 <6>[ 0.706817] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10429 12:47:15.579929 <6>[ 0.716562] TCP: Hash tables configured (established 65536 bind 65536)
10430 12:47:15.585910 <6>[ 0.723416] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10431 12:47:15.595900 <6>[ 0.730617] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10432 12:47:15.602728 <6>[ 0.738311] NET: Registered PF_UNIX/PF_LOCAL protocol family
10433 12:47:15.609252 <6>[ 0.744464] RPC: Registered named UNIX socket transport module.
10434 12:47:15.612466 <6>[ 0.750618] RPC: Registered udp transport module.
10435 12:47:15.618891 <6>[ 0.755550] RPC: Registered tcp transport module.
10436 12:47:15.625555 <6>[ 0.760483] RPC: Registered tcp NFSv4.1 backchannel transport module.
10437 12:47:15.628959 <6>[ 0.767147] PCI: CLS 0 bytes, default 64
10438 12:47:15.632767 <6>[ 0.771444] Unpacking initramfs...
10439 12:47:15.642703 <6>[ 0.775505] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10440 12:47:15.648727 <6>[ 0.784148] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10441 12:47:15.655362 <6>[ 0.792964] kvm [1]: IPA Size Limit: 40 bits
10442 12:47:15.658706 <6>[ 0.797488] kvm [1]: GICv3: no GICV resource entry
10443 12:47:15.665489 <6>[ 0.802504] kvm [1]: disabling GICv2 emulation
10444 12:47:15.671771 <6>[ 0.807192] kvm [1]: GIC system register CPU interface enabled
10445 12:47:15.674798 <6>[ 0.813354] kvm [1]: vgic interrupt IRQ18
10446 12:47:15.681487 <6>[ 0.817728] kvm [1]: VHE mode initialized successfully
10447 12:47:15.685388 <5>[ 0.824213] Initialise system trusted keyrings
10448 12:47:15.691388 <6>[ 0.828995] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10449 12:47:15.701092 <6>[ 0.839271] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10450 12:47:15.708293 <5>[ 0.845678] NFS: Registering the id_resolver key type
10451 12:47:15.710983 <5>[ 0.850980] Key type id_resolver registered
10452 12:47:15.717651 <5>[ 0.855394] Key type id_legacy registered
10453 12:47:15.724511 <6>[ 0.859679] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10454 12:47:15.730671 <6>[ 0.866599] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10455 12:47:15.737552 <6>[ 0.874311] 9p: Installing v9fs 9p2000 file system support
10456 12:47:15.773767 <5>[ 0.911855] Key type asymmetric registered
10457 12:47:15.777180 <5>[ 0.916189] Asymmetric key parser 'x509' registered
10458 12:47:15.787035 <6>[ 0.921339] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10459 12:47:15.790582 <6>[ 0.928949] io scheduler mq-deadline registered
10460 12:47:15.793457 <6>[ 0.933707] io scheduler kyber registered
10461 12:47:15.812838 <6>[ 0.950541] EINJ: ACPI disabled.
10462 12:47:15.844463 <4>[ 0.976093] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10463 12:47:15.854516 <4>[ 0.986703] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10464 12:47:15.869959 <6>[ 1.007390] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10465 12:47:15.877915 <6>[ 1.015455] printk: console [ttyS0] disabled
10466 12:47:15.905276 <6>[ 1.040090] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10467 12:47:15.911809 <6>[ 1.049567] printk: console [ttyS0] enabled
10468 12:47:15.915430 <6>[ 1.049567] printk: console [ttyS0] enabled
10469 12:47:15.922183 <6>[ 1.058467] printk: bootconsole [mtk8250] disabled
10470 12:47:15.924887 <6>[ 1.058467] printk: bootconsole [mtk8250] disabled
10471 12:47:15.931500 <6>[ 1.069693] SuperH (H)SCI(F) driver initialized
10472 12:47:15.934673 <6>[ 1.074970] msm_serial: driver initialized
10473 12:47:15.949106 <6>[ 1.083886] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10474 12:47:15.959439 <6>[ 1.092432] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10475 12:47:15.965886 <6>[ 1.100973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10476 12:47:15.975573 <6>[ 1.109601] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10477 12:47:15.985610 <6>[ 1.118307] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10478 12:47:15.991881 <6>[ 1.127027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10479 12:47:16.001846 <6>[ 1.135568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10480 12:47:16.008843 <6>[ 1.144373] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10481 12:47:16.018315 <6>[ 1.152916] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10482 12:47:16.030837 <6>[ 1.168484] loop: module loaded
10483 12:47:16.037283 <6>[ 1.174550] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10484 12:47:16.060567 <4>[ 1.198033] mtk-pmic-keys: Failed to locate of_node [id: -1]
10485 12:47:16.066809 <6>[ 1.204749] megasas: 07.719.03.00-rc1
10486 12:47:16.076159 <6>[ 1.214413] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10487 12:47:16.084269 <6>[ 1.222296] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10488 12:47:16.100929 <6>[ 1.238924] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10489 12:47:16.156924 <6>[ 1.288640] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10490 12:47:16.407349 <6>[ 1.545395] Freeing initrd memory: 17220K
10491 12:47:16.417439 <6>[ 1.555683] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10492 12:47:16.428395 <6>[ 1.566610] tun: Universal TUN/TAP device driver, 1.6
10493 12:47:16.432570 <6>[ 1.572662] thunder_xcv, ver 1.0
10494 12:47:16.434812 <6>[ 1.576166] thunder_bgx, ver 1.0
10495 12:47:16.438526 <6>[ 1.579658] nicpf, ver 1.0
10496 12:47:16.448726 <6>[ 1.583667] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10497 12:47:16.452148 <6>[ 1.591143] hns3: Copyright (c) 2017 Huawei Corporation.
10498 12:47:16.455893 <6>[ 1.596731] hclge is initializing
10499 12:47:16.462105 <6>[ 1.600314] e1000: Intel(R) PRO/1000 Network Driver
10500 12:47:16.468890 <6>[ 1.605443] e1000: Copyright (c) 1999-2006 Intel Corporation.
10501 12:47:16.472017 <6>[ 1.611456] e1000e: Intel(R) PRO/1000 Network Driver
10502 12:47:16.479233 <6>[ 1.616671] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10503 12:47:16.485677 <6>[ 1.622859] igb: Intel(R) Gigabit Ethernet Network Driver
10504 12:47:16.491828 <6>[ 1.628508] igb: Copyright (c) 2007-2014 Intel Corporation.
10505 12:47:16.499726 <6>[ 1.634343] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10506 12:47:16.505458 <6>[ 1.640861] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10507 12:47:16.508934 <6>[ 1.647319] sky2: driver version 1.30
10508 12:47:16.515263 <6>[ 1.652287] VFIO - User Level meta-driver version: 0.3
10509 12:47:16.522676 <6>[ 1.660467] usbcore: registered new interface driver usb-storage
10510 12:47:16.528818 <6>[ 1.666917] usbcore: registered new device driver onboard-usb-hub
10511 12:47:16.537818 <6>[ 1.676009] mt6397-rtc mt6359-rtc: registered as rtc0
10512 12:47:16.547918 <6>[ 1.681474] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:47:17 UTC (1686746837)
10513 12:47:16.550951 <6>[ 1.691035] i2c_dev: i2c /dev entries driver
10514 12:47:16.567857 <6>[ 1.702643] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10515 12:47:16.574663 <6>[ 1.712849] sdhci: Secure Digital Host Controller Interface driver
10516 12:47:16.581295 <6>[ 1.719288] sdhci: Copyright(c) Pierre Ossman
10517 12:47:16.587801 <6>[ 1.724668] Synopsys Designware Multimedia Card Interface Driver
10518 12:47:16.591189 <6>[ 1.731263] mmc0: CQHCI version 5.10
10519 12:47:16.597634 <6>[ 1.731815] sdhci-pltfm: SDHCI platform and OF driver helper
10520 12:47:16.604805 <6>[ 1.743121] ledtrig-cpu: registered to indicate activity on CPUs
10521 12:47:16.615773 <6>[ 1.750466] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10522 12:47:16.619581 <6>[ 1.757836] usbcore: registered new interface driver usbhid
10523 12:47:16.626046 <6>[ 1.763670] usbhid: USB HID core driver
10524 12:47:16.632062 <6>[ 1.767910] spi_master spi0: will run message pump with realtime priority
10525 12:47:16.674732 <6>[ 1.805847] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10526 12:47:16.692920 <6>[ 1.820811] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10527 12:47:16.696184 <6>[ 1.834367] mmc0: Command Queue Engine enabled
10528 12:47:16.703030 <6>[ 1.839115] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10529 12:47:16.709650 <6>[ 1.846051] cros-ec-spi spi0.0: Chrome EC device registered
10530 12:47:16.712630 <6>[ 1.846315] mmcblk0: mmc0:0001 DA4128 116 GiB
10531 12:47:16.723234 <6>[ 1.861120] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10532 12:47:16.730716 <6>[ 1.868270] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10533 12:47:16.737118 <6>[ 1.874140] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10534 12:47:16.743365 <6>[ 1.880084] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10535 12:47:16.760621 <6>[ 1.895083] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10536 12:47:16.768734 <6>[ 1.906520] NET: Registered PF_PACKET protocol family
10537 12:47:16.772715 <6>[ 1.911994] 9pnet: Installing 9P2000 support
10538 12:47:16.778305 <5>[ 1.916568] Key type dns_resolver registered
10539 12:47:16.782072 <6>[ 1.921606] registered taskstats version 1
10540 12:47:16.788206 <5>[ 1.926009] Loading compiled-in X.509 certificates
10541 12:47:16.822164 <4>[ 1.953617] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10542 12:47:16.832224 <4>[ 1.964312] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10543 12:47:16.842178 <3>[ 1.976861] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10544 12:47:16.854566 <6>[ 1.992340] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10545 12:47:16.860924 <6>[ 1.999201] xhci-mtk 11200000.usb: xHCI Host Controller
10546 12:47:16.867876 <6>[ 2.004703] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10547 12:47:16.877799 <6>[ 2.012569] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10548 12:47:16.885520 <6>[ 2.022031] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10549 12:47:16.890781 <6>[ 2.028136] xhci-mtk 11200000.usb: xHCI Host Controller
10550 12:47:16.897355 <6>[ 2.033726] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10551 12:47:16.903936 <6>[ 2.041399] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10552 12:47:16.910960 <6>[ 2.049295] hub 1-0:1.0: USB hub found
10553 12:47:16.914548 <6>[ 2.053344] hub 1-0:1.0: 1 port detected
10554 12:47:16.924332 <6>[ 2.057697] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10555 12:47:16.928049 <6>[ 2.066555] hub 2-0:1.0: USB hub found
10556 12:47:16.931505 <6>[ 2.070606] hub 2-0:1.0: 1 port detected
10557 12:47:16.939611 <6>[ 2.077477] mtk-msdc 11f70000.mmc: Got CD GPIO
10558 12:47:16.957261 <6>[ 2.091753] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10559 12:47:16.963760 <6>[ 2.099780] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10560 12:47:16.974007 <4>[ 2.107751] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10561 12:47:16.983440 <6>[ 2.117414] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10562 12:47:16.990432 <6>[ 2.125502] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10563 12:47:16.996861 <6>[ 2.133540] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10564 12:47:17.007134 <6>[ 2.141459] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10565 12:47:17.013220 <6>[ 2.149280] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10566 12:47:17.023366 <6>[ 2.157115] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10567 12:47:17.033177 <6>[ 2.167904] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10568 12:47:17.039792 <6>[ 2.176277] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10569 12:47:17.049626 <6>[ 2.184623] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10570 12:47:17.060022 <6>[ 2.192966] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10571 12:47:17.066914 <6>[ 2.201309] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10572 12:47:17.076403 <6>[ 2.209652] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10573 12:47:17.082986 <6>[ 2.217995] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10574 12:47:17.092858 <6>[ 2.226338] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10575 12:47:17.100080 <6>[ 2.234682] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10576 12:47:17.109214 <6>[ 2.243024] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10577 12:47:17.116002 <6>[ 2.251372] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10578 12:47:17.125883 <6>[ 2.259715] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10579 12:47:17.132454 <6>[ 2.268059] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10580 12:47:17.142858 <6>[ 2.276403] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10581 12:47:17.149206 <6>[ 2.284751] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10582 12:47:17.156082 <6>[ 2.293640] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10583 12:47:17.162864 <6>[ 2.301085] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10584 12:47:17.170242 <6>[ 2.308100] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10585 12:47:17.180535 <6>[ 2.315191] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10586 12:47:17.186866 <6>[ 2.322454] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10587 12:47:17.196851 <6>[ 2.329391] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10588 12:47:17.203698 <6>[ 2.338546] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10589 12:47:17.213592 <6>[ 2.347673] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10590 12:47:17.223487 <6>[ 2.356974] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10591 12:47:17.233455 <6>[ 2.366450] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10592 12:47:17.243428 <6>[ 2.375924] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10593 12:47:17.249491 <6>[ 2.385051] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10594 12:47:17.259506 <6>[ 2.394526] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10595 12:47:17.269591 <6>[ 2.403653] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10596 12:47:17.279453 <6>[ 2.412977] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10597 12:47:17.289292 <6>[ 2.423144] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10598 12:47:17.299733 <6>[ 2.434688] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10599 12:47:17.306270 <6>[ 2.444656] Trying to probe devices needed for running init ...
10600 12:47:17.324448 <6>[ 2.459358] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10601 12:47:17.353549 <6>[ 2.491419] hub 2-1:1.0: USB hub found
10602 12:47:17.356859 <6>[ 2.495920] hub 2-1:1.0: 3 ports detected
10603 12:47:17.476457 <6>[ 2.611158] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10604 12:47:17.629808 <6>[ 2.767446] hub 1-1:1.0: USB hub found
10605 12:47:17.632451 <6>[ 2.771807] hub 1-1:1.0: 4 ports detected
10606 12:47:17.708885 <6>[ 2.843435] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10607 12:47:17.952295 <6>[ 3.087054] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10608 12:47:18.084901 <6>[ 3.223439] hub 1-1.4:1.0: USB hub found
10609 12:47:18.088089 <6>[ 3.228126] hub 1-1.4:1.0: 2 ports detected
10610 12:47:18.388245 <6>[ 3.523184] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10611 12:47:18.580037 <6>[ 3.715183] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10612 12:47:29.588939 <6>[ 14.731732] ALSA device list:
10613 12:47:29.595307 <6>[ 14.734989] No soundcards found.
10614 12:47:29.607814 <6>[ 14.747388] Freeing unused kernel memory: 8384K
10615 12:47:29.611404 <6>[ 14.752313] Run /init as init process
10616 12:47:29.621695 Loading, please wait...
10617 12:47:29.640703 Starting version 247.3-7+deb11u2
10618 12:47:29.962182 <6>[ 15.098541] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10619 12:47:29.975861 <6>[ 15.115413] remoteproc remoteproc0: scp is available
10620 12:47:29.985745 <4>[ 15.120902] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10621 12:47:29.992348 <6>[ 15.130766] remoteproc remoteproc0: powering up scp
10622 12:47:30.002710 <4>[ 15.135948] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10623 12:47:30.009170 <3>[ 15.140776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 12:47:30.015493 <3>[ 15.145776] remoteproc remoteproc0: request_firmware failed: -2
10625 12:47:30.021907 <3>[ 15.160118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 12:47:30.032114 <6>[ 15.163786] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10627 12:47:30.038529 <3>[ 15.168278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 12:47:30.048505 <6>[ 15.175921] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10629 12:47:30.051650 <6>[ 15.177558] mc: Linux media interface: v0.10
10630 12:47:30.058546 <4>[ 15.191132] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10631 12:47:30.068013 <6>[ 15.191555] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10632 12:47:30.074746 <6>[ 15.192699] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10633 12:47:30.084593 <3>[ 15.192913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10634 12:47:30.091091 <3>[ 15.192941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10635 12:47:30.101014 <3>[ 15.192952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 12:47:30.107952 <3>[ 15.192974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 12:47:30.117693 <3>[ 15.192988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10638 12:47:30.124405 <4>[ 15.199240] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10639 12:47:30.131199 <3>[ 15.200066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10640 12:47:30.140972 <3>[ 15.200149] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 12:47:30.147496 <3>[ 15.200157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 12:47:30.157255 <3>[ 15.200165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 12:47:30.164168 <3>[ 15.202437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 12:47:30.173775 <3>[ 15.202470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10645 12:47:30.180206 <3>[ 15.202479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 12:47:30.187264 <3>[ 15.202488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10647 12:47:30.198154 <3>[ 15.202497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10648 12:47:30.204250 <3>[ 15.202571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10649 12:47:30.211015 <6>[ 15.207214] usbcore: registered new interface driver r8152
10650 12:47:30.217361 <6>[ 15.213009] videodev: Linux video capture interface: v2.00
10651 12:47:30.224408 <4>[ 15.228294] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10652 12:47:30.230906 <4>[ 15.228294] Fallback method does not support PEC.
10653 12:47:30.237903 <6>[ 15.311699] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10654 12:47:30.248361 <6>[ 15.320089] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10655 12:47:30.257565 <6>[ 15.322876] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10656 12:47:30.264337 <6>[ 15.330546] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10657 12:47:30.271668 <6>[ 15.333680] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10658 12:47:30.280905 <3>[ 15.335932] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 12:47:30.287412 <6>[ 15.341486] pci_bus 0000:00: root bus resource [bus 00-ff]
10660 12:47:30.297525 <4>[ 15.362154] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10661 12:47:30.304897 <6>[ 15.374693] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10662 12:47:30.314306 <6>[ 15.374702] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10663 12:47:30.321002 <4>[ 15.381984] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10664 12:47:30.327441 <6>[ 15.383077] usbcore: registered new interface driver cdc_ether
10665 12:47:30.336852 <3>[ 15.385544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 12:47:30.343789 <6>[ 15.392024] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10667 12:47:30.347263 <6>[ 15.392331] usbcore: registered new interface driver r8153_ecm
10668 12:47:30.354421 <6>[ 15.402292] Bluetooth: Core ver 2.22
10669 12:47:30.360332 <6>[ 15.408203] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10670 12:47:30.366673 <6>[ 15.409107] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10671 12:47:30.379984 <6>[ 15.410413] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10672 12:47:30.386670 <6>[ 15.410560] usbcore: registered new interface driver uvcvideo
10673 12:47:30.390114 <6>[ 15.417298] NET: Registered PF_BLUETOOTH protocol family
10674 12:47:30.396411 <6>[ 15.426096] pci 0000:00:00.0: supports D1 D2
10675 12:47:30.402878 <6>[ 15.431844] Bluetooth: HCI device and connection manager initialized
10676 12:47:30.409516 <6>[ 15.432452] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10677 12:47:30.416372 <6>[ 15.440787] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10678 12:47:30.422904 <6>[ 15.442528] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10679 12:47:30.429572 <6>[ 15.447936] Bluetooth: HCI socket layer initialized
10680 12:47:30.432489 <6>[ 15.451222] r8152 2-1.3:1.0 eth0: v1.12.13
10681 12:47:30.439400 <6>[ 15.457996] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10682 12:47:30.446721 <6>[ 15.459025] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10683 12:47:30.449119 <6>[ 15.465922] Bluetooth: L2CAP socket layer initialized
10684 12:47:30.459029 <6>[ 15.472029] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10685 12:47:30.462328 <6>[ 15.480789] Bluetooth: SCO socket layer initialized
10686 12:47:30.469149 <6>[ 15.487046] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10687 12:47:30.475556 <6>[ 15.530698] usbcore: registered new interface driver btusb
10688 12:47:30.485559 <4>[ 15.531494] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10689 12:47:30.492343 <3>[ 15.531505] Bluetooth: hci0: Failed to load firmware file (-2)
10690 12:47:30.498857 <3>[ 15.531508] Bluetooth: hci0: Failed to set up firmware (-2)
10691 12:47:30.508769 <4>[ 15.531512] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10692 12:47:30.515635 <6>[ 15.535485] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10693 12:47:30.521996 <6>[ 15.661573] pci 0000:01:00.0: supports D1 D2
10694 12:47:30.528633 <6>[ 15.666099] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10695 12:47:30.546300 <6>[ 15.682952] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10696 12:47:30.553053 <6>[ 15.689858] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10697 12:47:30.559702 <6>[ 15.697948] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10698 12:47:30.569444 <6>[ 15.705952] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10699 12:47:30.576160 <6>[ 15.713960] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10700 12:47:30.586018 <6>[ 15.721968] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10701 12:47:30.589330 <6>[ 15.729975] pci 0000:00:00.0: PCI bridge to [bus 01]
10702 12:47:30.599839 <6>[ 15.735196] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10703 12:47:30.606035 <6>[ 15.743333] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10704 12:47:30.612360 <6>[ 15.750503] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10705 12:47:30.619011 <6>[ 15.757200] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10706 12:47:30.637662 <5>[ 15.773720] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10707 12:47:30.657466 <5>[ 15.793722] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10708 12:47:30.663984 <4>[ 15.800612] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10709 12:47:30.670539 <6>[ 15.809492] cfg80211: failed to load regulatory.db
10710 12:47:30.720008 <6>[ 15.856649] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10711 12:47:30.726814 <6>[ 15.864165] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10712 12:47:30.751006 <6>[ 15.890856] mt7921e 0000:01:00.0: ASIC revision: 79610010
10713 12:47:30.857767 <4>[ 15.990848] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10714 12:47:30.871642 Begin: Loading essential drivers ... done.
10715 12:47:30.877701 Begin: Running /scripts/init-premount ... done.
10716 12:47:30.884875 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10717 12:47:30.891568 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10718 12:47:30.894566 Device /sys/class/net/enx002432307c7b found
10719 12:47:30.897742 done.
10720 12:47:30.977838 IP-Config: enx002432307c7b hardw<4>[ 16.109596] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10721 12:47:30.981504 are address 00:24:32:30:7c:7b mtu 1500 DHCP
10722 12:47:31.096055 <4>[ 16.229103] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10723 12:47:31.216028 <4>[ 16.348984] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10724 12:47:31.331674 <4>[ 16.464928] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10725 12:47:31.447779 <4>[ 16.580942] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10726 12:47:31.563264 <4>[ 16.696809] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10727 12:47:31.679193 <4>[ 16.812722] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10728 12:47:31.795353 <4>[ 16.928660] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10729 12:47:31.911549 <4>[ 17.044597] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10730 12:47:32.017483 <6>[ 17.157260] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10731 12:47:32.023862 <3>[ 17.158615] mt7921e 0000:01:00.0: hardware init failed
10732 12:47:32.041875 IP-Config: no response after 2 secs - giving up
10733 12:47:32.074875 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10734 12:47:33.179526 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10735 12:47:33.186179 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10736 12:47:33.192978 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10737 12:47:33.199835 host : mt8192-asurada-spherion-r0-cbg-2
10738 12:47:33.205942 domain : lava-rack
10739 12:47:33.212545 rootserver: 192.168.201.1 rootpath:
10740 12:47:33.212641 filename :
10741 12:47:33.239159 done.
10742 12:47:33.246892 Begin: Running /scripts/nfs-bottom ... done.
10743 12:47:33.265552 Begin: Running /scripts/init-bottom ... done.
10744 12:47:34.411125 <6>[ 19.550931] NET: Registered PF_INET6 protocol family
10745 12:47:34.418581 <6>[ 19.558080] Segment Routing with IPv6
10746 12:47:34.421133 <6>[ 19.562078] In-situ OAM (IOAM) with IPv6
10747 12:47:34.540551 <30>[ 19.660311] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10748 12:47:34.543373 <30>[ 19.684130] systemd[1]: Detected architecture arm64.
10749 12:47:34.564124
10750 12:47:34.567348 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10751 12:47:34.567430
10752 12:47:34.585679 <30>[ 19.725651] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10753 12:47:35.177989 <30>[ 20.314487] systemd[1]: Queued start job for default target Graphical Interface.
10754 12:47:35.212300 <30>[ 20.352190] systemd[1]: Created slice system-getty.slice.
10755 12:47:35.218789 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10756 12:47:35.235816 <30>[ 20.375809] systemd[1]: Created slice system-modprobe.slice.
10757 12:47:35.242166 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10758 12:47:35.259964 <30>[ 20.399775] systemd[1]: Created slice system-serial\x2dgetty.slice.
10759 12:47:35.269601 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10760 12:47:35.283783 <30>[ 20.423654] systemd[1]: Created slice User and Session Slice.
10761 12:47:35.290281 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10762 12:47:35.310788 <30>[ 20.447732] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10763 12:47:35.320750 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10764 12:47:35.338419 <30>[ 20.475369] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10765 12:47:35.344868 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10766 12:47:35.366400 <30>[ 20.499336] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10767 12:47:35.372248 <30>[ 20.511361] systemd[1]: Reached target Local Encrypted Volumes.
10768 12:47:35.379387 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10769 12:47:35.394804 <30>[ 20.535278] systemd[1]: Reached target Paths.
10770 12:47:35.399120 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10771 12:47:35.415474 <30>[ 20.555215] systemd[1]: Reached target Remote File Systems.
10772 12:47:35.421264 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10773 12:47:35.439080 <30>[ 20.579499] systemd[1]: Reached target Slices.
10774 12:47:35.445868 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10775 12:47:35.459011 <30>[ 20.599244] systemd[1]: Reached target Swap.
10776 12:47:35.462355 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10777 12:47:35.482416 <30>[ 20.619547] systemd[1]: Listening on initctl Compatibility Named Pipe.
10778 12:47:35.489311 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10779 12:47:35.495742 <30>[ 20.635187] systemd[1]: Listening on Journal Audit Socket.
10780 12:47:35.502516 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10781 12:47:35.516290 <30>[ 20.656271] systemd[1]: Listening on Journal Socket (/dev/log).
10782 12:47:35.522772 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10783 12:47:35.539020 <30>[ 20.679480] systemd[1]: Listening on Journal Socket.
10784 12:47:35.546516 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10785 12:47:35.560162 <30>[ 20.700377] systemd[1]: Listening on Network Service Netlink Socket.
10786 12:47:35.570294 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10787 12:47:35.585805 <30>[ 20.725866] systemd[1]: Listening on udev Control Socket.
10788 12:47:35.592459 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10789 12:47:35.607011 <30>[ 20.747505] systemd[1]: Listening on udev Kernel Socket.
10790 12:47:35.613727 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10791 12:47:35.664183 <30>[ 20.803493] systemd[1]: Mounting Huge Pages File System...
10792 12:47:35.670077 Mounting [0;1;39mHuge Pages File System[0m...
10793 12:47:35.685470 <30>[ 20.825577] systemd[1]: Mounting POSIX Message Queue File System...
10794 12:47:35.691980 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10795 12:47:35.709502 <30>[ 20.849687] systemd[1]: Mounting Kernel Debug File System...
10796 12:47:35.716148 Mounting [0;1;39mKernel Debug File System[0m...
10797 12:47:35.734245 <30>[ 20.871447] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10798 12:47:35.746832 <30>[ 20.883778] systemd[1]: Starting Create list of static device nodes for the current kernel...
10799 12:47:35.754089 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10800 12:47:35.788013 <30>[ 20.927669] systemd[1]: Starting Load Kernel Module configfs...
10801 12:47:35.793819 Starting [0;1;39mLoad Kernel Module configfs[0m...
10802 12:47:35.809427 <30>[ 20.949711] systemd[1]: Starting Load Kernel Module drm...
10803 12:47:35.815868 Starting [0;1;39mLoad Kernel Module drm[0m...
10804 12:47:35.833842 <30>[ 20.974111] systemd[1]: Starting Load Kernel Module fuse...
10805 12:47:35.840224 Starting [0;1;39mLoad Kernel Module fuse[0m...
10806 12:47:35.876251 <6>[ 21.016295] fuse: init (API version 7.37)
10807 12:47:35.885829 <30>[ 21.016447] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10808 12:47:35.911927 <30>[ 21.051924] systemd[1]: Starting Journal Service...
10809 12:47:35.914992 Starting [0;1;39mJournal Service[0m...
10810 12:47:35.939258 <30>[ 21.079414] systemd[1]: Starting Load Kernel Modules...
10811 12:47:35.945921 Starting [0;1;39mLoad Kernel Modules[0m...
10812 12:47:35.965483 <30>[ 21.101907] systemd[1]: Starting Remount Root and Kernel File Systems...
10813 12:47:35.971309 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10814 12:47:35.986489 <30>[ 21.126896] systemd[1]: Starting Coldplug All udev Devices...
10815 12:47:35.993743 Starting [0;1;39mColdplug All udev Devices[0m...
10816 12:47:36.010017 <30>[ 21.150121] systemd[1]: Mounted Huge Pages File System.
10817 12:47:36.016494 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10818 12:47:36.031487 <30>[ 21.171559] systemd[1]: Mounted POSIX Message Queue File System.
10819 12:47:36.037579 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10820 12:47:36.059453 <30>[ 21.199569] systemd[1]: Mounted Kernel Debug File System.
10821 12:47:36.069712 <3>[ 21.202792] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10822 12:47:36.075886 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10823 12:47:36.095521 <30>[ 21.232223] systemd[1]: Finished Create list of static device nodes for the current kernel.
10824 12:47:36.105798 <3>[ 21.236748] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10825 12:47:36.112522 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10826 12:47:36.128012 <30>[ 21.268120] systemd[1]: modprobe@configfs.service: Succeeded.
10827 12:47:36.134682 <30>[ 21.274801] systemd[1]: Finished Load Kernel Module configfs.
10828 12:47:36.148478 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.284920] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10829 12:47:36.151654 l Module configfs[0m.
10830 12:47:36.168552 <30>[ 21.308036] systemd[1]: modprobe@drm.service: Succeeded.
10831 12:47:36.175634 <30>[ 21.314258] systemd[1]: Finished Load Kernel Module drm.
10832 12:47:36.185205 <3>[ 21.314747] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10833 12:47:36.188276 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10834 12:47:36.204527 <30>[ 21.344077] systemd[1]: modprobe@fuse.service: Succeeded.
10835 12:47:36.210693 <30>[ 21.350483] systemd[1]: Finished Load Kernel Module fuse.
10836 12:47:36.220801 <3>[ 21.350517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 12:47:36.227407 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10838 12:47:36.244744 <30>[ 21.384613] systemd[1]: Finished Load Kernel Modules.
10839 12:47:36.254516 <3>[ 21.385507] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 12:47:36.258089 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10841 12:47:36.277002 <30>[ 21.416426] systemd[1]: Finished Remount Root and Kernel File Systems.
10842 12:47:36.287385 <3>[ 21.420722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 12:47:36.293673 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10844 12:47:36.317908 <3>[ 21.454858] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10845 12:47:36.342552 <30>[ 21.483008] systemd[1]: Mounting FUSE Control File System...
10846 12:47:36.352708 <3>[ 21.484118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 12:47:36.359440 Mounting [0;1;39mFUSE Control File System[0m...
10848 12:47:36.374114 <30>[ 21.513887] systemd[1]: Mounting Kernel Configuration File System...
10849 12:47:36.383824 <3>[ 21.517948] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 12:47:36.390373 Mounting [0;1;39mKernel Configuration File System[0m...
10851 12:47:36.415646 <30>[ 21.552722] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10852 12:47:36.425674 <30>[ 21.561870] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10853 12:47:36.447302 <30>[ 21.587725] systemd[1]: Starting Load/Save Random Seed...
10854 12:47:36.453720 Starting [0;1;39mLoad/Save Random Seed[0m...
10855 12:47:36.469402 <30>[ 21.609915] systemd[1]: Starting Apply Kernel Variables...
10856 12:47:36.476204 Starting [0;1;39mApply Kernel Variables[0m...
10857 12:47:36.495606 <30>[ 21.635734] systemd[1]: Starting Create System Users...
10858 12:47:36.502025 Starting [0;1;39mCreate System Users[0m...
10859 12:47:36.516211 <30>[ 21.656729] systemd[1]: Started Journal Service.
10860 12:47:36.523232 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10861 12:47:36.550773 [[0;32m OK [0m] Mounted [0;1;39mFUSE Contro<4>[ 21.681024] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10862 12:47:36.560461 l File System[0<3>[ 21.697601] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10863 12:47:36.560543 m.
10864 12:47:36.575698 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10865 12:47:36.596199 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10866 12:47:36.607324 See 'systemctl status systemd-udev-trigger.service' for details.
10867 12:47:36.628060 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10868 12:47:36.643855 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10869 12:47:36.659506 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10870 12:47:36.704211 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10871 12:47:36.725081 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10872 12:47:36.767914 <46>[ 21.904997] systemd-journald[290]: Received client request to flush runtime journal.
10873 12:47:37.426440 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10874 12:47:37.439894 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10875 12:47:37.455521 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10876 12:47:37.519751 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10877 12:47:38.160507 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10878 12:47:38.191385 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10879 12:47:38.257048 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10880 12:47:38.315570 Starting [0;1;39mNetwork Service[0m...
10881 12:47:38.505916 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10882 12:47:38.690878 Starting [0;1;39mNetwork Time Synchronization[0m...
10883 12:47:38.713850 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10884 12:47:38.837537 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10885 12:47:38.905275 <6>[ 24.045869] remoteproc remoteproc0: powering up scp
10886 12:47:38.945053 <4>[ 24.082606] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10887 12:47:38.952066 <3>[ 24.092479] remoteproc remoteproc0: request_firmware failed: -2
10888 12:47:38.961955 <3>[ 24.098670] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10889 12:47:39.052537 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10890 12:47:39.071492 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10891 12:47:39.139716 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10892 12:47:39.158971 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10893 12:47:39.178086 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10894 12:47:39.218479 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10895 12:47:39.243368 Starting [0;1;39mNetwork Name Resolution[0m...
10896 12:47:39.259295 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10897 12:47:39.279945 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10898 12:47:39.295691 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10899 12:47:39.314333 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10900 12:47:39.326821 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10901 12:47:39.347812 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10902 12:47:40.010569 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10903 12:47:40.036234 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10904 12:47:40.359638 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10905 12:47:40.392308 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10906 12:47:40.406522 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10907 12:47:40.428193 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10908 12:47:40.442397 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10909 12:47:40.462309 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10910 12:47:40.499296 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10911 12:47:40.574978 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10912 12:47:40.783755 Starting [0;1;39mUser Login Management[0m...
10913 12:47:40.805812 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10914 12:47:41.007672 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10915 12:47:41.026832 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10916 12:47:41.045672 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10917 12:47:41.095596 Starting [0;1;39mPermit User Sessions[0m...
10918 12:47:41.111170 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10919 12:47:41.131565 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10920 12:47:41.149357 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10921 12:47:41.191417 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10922 12:47:41.209260 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10923 12:47:41.226807 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10924 12:47:41.242813 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10925 12:47:41.259949 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10926 12:47:41.279024 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10927 12:47:41.338637 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10928 12:47:41.380212 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10929 12:47:41.462771
10930 12:47:41.462913
10931 12:47:41.466749 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10932 12:47:41.466858
10933 12:47:41.469596 debian-bullseye-arm64 login: root (automatic login)
10934 12:47:41.469669
10935 12:47:41.469745
10936 12:47:41.779407 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
10937 12:47:41.779569
10938 12:47:41.785987 The programs included with the Debian GNU/Linux system are free software;
10939 12:47:41.792488 the exact distribution terms for each program are described in the
10940 12:47:41.796286 individual files in /usr/share/doc/*/copyright.
10941 12:47:41.796367
10942 12:47:41.802800 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10943 12:47:41.805443 permitted by applicable law.
10944 12:47:41.873316 Matched prompt #10: / #
10946 12:47:41.873646 Setting prompt string to ['/ #']
10947 12:47:41.873774 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10949 12:47:41.874084 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10950 12:47:41.874197 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
10951 12:47:41.874303 Setting prompt string to ['/ #']
10952 12:47:41.874391 Forcing a shell prompt, looking for ['/ #']
10954 12:47:41.924638 / #
10955 12:47:41.924738 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10956 12:47:41.924825 Waiting using forced prompt support (timeout 00:02:30)
10957 12:47:41.930678
10958 12:47:41.930975 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10959 12:47:41.931090 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
10961 12:47:42.031438 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724911/extract-nfsrootfs-0ljjj21m'
10962 12:47:42.037639 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10724911/extract-nfsrootfs-0ljjj21m'
10964 12:47:42.138150 / # export NFS_SERVER_IP='192.168.201.1'
10965 12:47:42.144176 export NFS_SERVER_IP='192.168.201.1'
10966 12:47:42.144455 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10967 12:47:42.144553 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
10968 12:47:42.144634 end: 2 depthcharge-action (duration 00:01:40) [common]
10969 12:47:42.144718 start: 3 lava-test-retry (timeout 00:30:00) [common]
10970 12:47:42.144801 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10971 12:47:42.144873 Using namespace: common
10973 12:47:42.245166 / # #
10974 12:47:42.245291 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10975 12:47:42.250841 #
10976 12:47:42.251125 Using /lava-10724911
10978 12:47:42.351452 / # export SHELL=/bin/sh
10979 12:47:42.356263 export SHELL=/bin/sh
10981 12:47:42.456720 / # . /lava-10724911/environment
10982 12:47:42.462384 . /lava-10724911/environment
10984 12:47:42.567738 / # /lava-10724911/bin/lava-test-runner /lava-10724911/0
10985 12:47:42.567883 Test shell timeout: 10s (minimum of the action and connection timeout)
10986 12:47:42.572725 /lava-10724911/bin/lava-test-runner /lava-10724911/0
10987 12:47:42.822124 + export TESTRUN_ID=0_lc-compliance
10988 12:47:42.828414 + cd /lava-10724911/0/tests/0_lc-compliance
10989 12:47:42.828506 + cat uuid
10990 12:47:42.833944 + UUID=10724911_1.6.2.3.1
10991 12:47:42.834045 + set +x
10992 12:47:42.840313 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10724911_1.6.2.3.1>
10993 12:47:42.840566 Received signal: <STARTRUN> 0_lc-compliance 10724911_1.6.2.3.1
10994 12:47:42.840640 Starting test lava.0_lc-compliance (10724911_1.6.2.3.1)
10995 12:47:42.840746 Skipping test definition patterns.
10996 12:47:42.843534 + /usr/bin/lc-compliance-parser.sh
10997 12:47:44.008616 [0:00:29.031966693] [401] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-0ee93393
10998 12:47:44.011752 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10999 12:47:44.021835 [0:00:29.046503231] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11000 12:47:44.076185 [0:00:29.099992693] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11001 12:47:44.104461 [==========] Running 120 tests from 1 test suite.
11002 12:47:44.127432 [0:00:29.151181385] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11003 12:47:44.178771 [0:00:29.202617000] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11004 12:47:44.194964 [----------] Global test environment set-up.
11005 12:47:44.299855 [----------] 120 tests from CaptureTests/SingleStream
11006 12:47:44.408818 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11007 12:47:44.482475 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11008 12:47:44.483276 Received signal: <TESTSET> START CaptureTests/SingleStream
11009 12:47:44.483660 Starting test_set CaptureTests/SingleStream
11010 12:47:44.486059 Camera needs 4 requests, can't test only 1
11011 12:47:44.540756 [0:00:29.564186693] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11012 12:47:44.585006 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11013 12:47:44.686194
11014 12:47:44.794755 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (54 ms)
11015 12:47:44.918402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11016 12:47:44.919161 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11018 12:47:44.939656 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11019 12:47:45.004349 Camera needs 4 requests, can't test only 2
11020 12:47:45.031703 [0:00:30.054730847] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11021 12:47:45.103451 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11022 12:47:45.197344
11023 12:47:45.299081 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (51 ms)
11024 12:47:45.396165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11025 12:47:45.396949 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11027 12:47:45.417027 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11028 12:47:45.470867 Camera needs 4 requests, can't test only 3
11029 12:47:45.560614 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11030 12:47:45.652949
11031 12:47:45.743887 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
11032 12:47:45.759660 [0:00:30.782683385] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11033 12:47:45.858426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11034 12:47:45.859187 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11036 12:47:45.879325 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11037 12:47:45.942932 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (361 ms)
11038 12:47:46.051284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11039 12:47:46.052139 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11041 12:47:46.072888 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11042 12:47:46.139495 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (490 ms)
11043 12:47:46.248963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11044 12:47:46.249689 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11046 12:47:46.269075 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11047 12:47:46.329723 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (727 ms)
11048 12:47:46.450719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11049 12:47:46.451542 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11051 12:47:46.473433 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11052 12:47:46.645515 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (894 ms)
11053 12:47:46.654643 [0:00:31.678284462] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11054 12:47:46.771491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11055 12:47:46.772273 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11057 12:47:46.789880 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11058 12:47:48.038527 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1394 ms)
11059 12:47:48.048591 [0:00:33.070529385] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11060 12:47:48.162031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11061 12:47:48.162816 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11063 12:47:48.182595 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11064 12:47:50.130416 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2092 ms)
11065 12:47:50.140785 [0:00:35.162594924] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11066 12:47:50.252023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11067 12:47:50.252819 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11069 12:47:50.272526 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11070 12:47:53.354183 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3223 ms)
11071 12:47:53.363901 [0:00:38.386615693] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11072 12:47:53.413730 [0:00:38.438060001] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11073 12:47:53.464256 [0:00:38.488497693] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11074 12:47:53.487439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11075 12:47:53.488212 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11077 12:47:53.514747 [0:00:38.539218386] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11078 12:47:53.518120 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11079 12:47:53.581403 Camera needs 4 requests, can't test only 1
11080 12:47:53.689406 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11081 12:47:53.806520
11082 12:47:53.876775 [0:00:38.901175078] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11083 12:47:53.914441 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (52 ms)
11084 12:47:54.029741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11085 12:47:54.030488 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11087 12:47:54.050346 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11088 12:47:54.117980 Camera needs 4 requests, can't test only 2
11089 12:47:54.214693 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11090 12:47:54.310927
11091 12:47:54.339526 [0:00:39.363581001] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11092 12:47:54.416336 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (51 ms)
11093 12:47:54.525418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11094 12:47:54.526180 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11096 12:47:54.548397 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11097 12:47:54.615291 Camera needs 4 requests, can't test only 3
11098 12:47:54.719381 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11099 12:47:54.822773
11100 12:47:54.926074 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (51 ms)
11101 12:47:55.032452 [0:00:40.056041001] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11102 12:47:55.040648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11103 12:47:55.041351 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11105 12:47:55.059149 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11106 12:47:55.124889 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (361 ms)
11107 12:47:55.233683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11108 12:47:55.234430 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11110 12:47:55.251672 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11111 12:47:55.314872 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (463 ms)
11112 12:47:55.426667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11113 12:47:55.427489 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11115 12:47:55.446257 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11116 12:47:55.509995 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (692 ms)
11117 12:47:55.615825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11118 12:47:55.616582 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11120 12:47:55.635286 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11121 12:47:55.917417 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (894 ms)
11122 12:47:55.931029 [0:00:40.951437463] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11123 12:47:56.026635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11124 12:47:56.027389 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11126 12:47:56.047251 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11127 12:47:57.311687 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1394 ms)
11128 12:47:57.324230 [0:00:42.346292232] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 12:47:57.427653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11130 12:47:57.428461 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11132 12:47:57.447631 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11133 12:47:59.405419 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2094 ms)
11134 12:47:59.417872 [0:00:44.438820078] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11135 12:47:59.519555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11136 12:47:59.520333 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11138 12:47:59.538796 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11139 12:48:01.009159 <6>[ 46.155119] vpu: disabling
11140 12:48:01.012662 <6>[ 46.158168] vproc2: disabling
11141 12:48:01.015889 <6>[ 46.161442] vproc1: disabling
11142 12:48:01.019071 <6>[ 46.164701] vaud18: disabling
11143 12:48:01.025131 <6>[ 46.168106] vsram_others: disabling
11144 12:48:01.025227 <6>[ 46.171980] va09: disabling
11145 12:48:01.031949 <6>[ 46.175083] vsram_md: disabling
11146 12:48:01.032045 <6>[ 46.178567] Vgpu: disabling
11147 12:48:02.631199 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3226 ms)
11148 12:48:02.643660 [0:00:47.665519848] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 12:48:02.691491 [0:00:47.716583155] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11150 12:48:02.742555 [0:00:47.767912078] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11151 12:48:02.749571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11152 12:48:02.750281 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11154 12:48:02.770160 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11155 12:48:02.794115 [0:00:47.819632155] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11156 12:48:02.828520 Camera needs 4 requests, can't test only 1
11157 12:48:02.910804 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11158 12:48:02.992515
11159 12:48:03.097440 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (53 ms)
11160 12:48:03.157589 [0:00:48.183044079] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11161 12:48:03.214462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11162 12:48:03.215221 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11164 12:48:03.236987 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11165 12:48:03.302256 Camera needs 4 requests, can't test only 2
11166 12:48:03.409293 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11167 12:48:03.512634
11168 12:48:03.620645 [0:00:48.646406309] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11169 12:48:03.627245 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (50 ms)
11170 12:48:03.741313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11171 12:48:03.741960 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11173 12:48:03.760473 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11174 12:48:03.826075 Camera needs 4 requests, can't test only 3
11175 12:48:03.933117 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11176 12:48:04.035468
11177 12:48:04.142286 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (52 ms)
11178 12:48:04.260482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11179 12:48:04.261262 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11181 12:48:04.278868 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11182 12:48:04.314002 [0:00:49.339810156] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11183 12:48:04.349188 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (363 ms)
11184 12:48:04.463768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11185 12:48:04.464519 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11187 12:48:04.481022 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11188 12:48:04.540802 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (462 ms)
11189 12:48:04.651872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11190 12:48:04.652736 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11192 12:48:04.672504 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11193 12:48:04.739539 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (695 ms)
11194 12:48:04.852555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11195 12:48:04.853354 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11197 12:48:04.873328 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11198 12:48:05.200954 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (896 ms)
11199 12:48:05.214584 [0:00:50.236851771] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11200 12:48:05.323619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11201 12:48:05.324390 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11203 12:48:05.341135 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11204 12:48:06.602399 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1401 ms)
11205 12:48:06.615250 [0:00:51.636177463] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11206 12:48:06.718065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11207 12:48:06.718813 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11209 12:48:06.738432 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11210 12:48:08.733420 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2131 ms)
11211 12:48:08.746486 [0:00:53.767952233] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11212 12:48:08.848677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11213 12:48:08.849401 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11215 12:48:08.869043 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11216 12:48:11.964973 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3232 ms)
11217 12:48:11.977774 [0:00:56.999407925] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11218 12:48:12.028759 [0:00:57.055123041] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11219 12:48:12.073998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11220 12:48:12.074335 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11222 12:48:12.087146 [0:00:57.112070736] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 12:48:12.102032 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11224 12:48:12.143279 [0:00:57.169004895] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11225 12:48:12.173338 Camera needs 4 requests, can't test only 1
11226 12:48:12.268126 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11227 12:48:12.356481
11228 12:48:12.458050 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (56 ms)
11229 12:48:12.510488 [0:00:57.536401293] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11230 12:48:12.578334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11231 12:48:12.579059 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11233 12:48:12.598032 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11234 12:48:12.660556 Camera needs 4 requests, can't test only 2
11235 12:48:12.751443 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11236 12:48:12.838358
11237 12:48:12.933214 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (57 ms)
11238 12:48:12.978165 [0:00:58.004228902] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11239 12:48:13.040695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11240 12:48:13.041410 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11242 12:48:13.059243 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11243 12:48:13.116701 Camera needs 4 requests, can't test only 3
11244 12:48:13.210511 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11245 12:48:13.297866
11246 12:48:13.387576 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (57 ms)
11247 12:48:13.490005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11248 12:48:13.490817 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11250 12:48:13.508334 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11251 12:48:13.570139 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (368 ms)
11252 12:48:13.676489 [0:00:58.702818990] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11253 12:48:13.680017 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11255 12:48:13.682718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11256 12:48:13.697842 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11257 12:48:13.760464 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (467 ms)
11258 12:48:13.877949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11259 12:48:13.878745 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11261 12:48:13.897634 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11262 12:48:13.958838 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (698 ms)
11263 12:48:14.071412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11264 12:48:14.072131 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11266 12:48:14.090277 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11267 12:48:14.568706 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (900 ms)
11268 12:48:14.582282 [0:00:59.603765573] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11269 12:48:14.690362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11270 12:48:14.691163 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11272 12:48:14.710968 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11273 12:48:15.968448 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1400 ms)
11274 12:48:15.981412 [0:01:01.003685758] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11275 12:48:16.106217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11276 12:48:16.107018 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11278 12:48:16.125232 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11279 12:48:18.039409 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2071 ms)
11280 12:48:18.052240 [0:01:03.073908000] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11281 12:48:18.155968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11282 12:48:18.156932 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11284 12:48:18.173126 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11285 12:48:21.270646 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3231 ms)
11286 12:48:21.283554 [0:01:06.304571533] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11287 12:48:21.338844 [0:01:06.363902222] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11288 12:48:21.395449 [0:01:06.420794446] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 12:48:21.403768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11290 12:48:21.404061 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11292 12:48:21.420880 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11293 12:48:21.454539 [0:01:06.479340796] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11294 12:48:21.481585 Camera needs 4 requests, can't test only 1
11295 12:48:21.571606 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11296 12:48:21.659677
11297 12:48:21.760840 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (59 ms)
11298 12:48:21.892124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11299 12:48:21.893040 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11301 12:48:21.913280 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11302 12:48:21.976652 Camera needs 4 requests, can't test only 2
11303 12:48:22.065269 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11304 12:48:22.163077
11305 12:48:22.275489 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (58 ms)
11306 12:48:22.378736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11307 12:48:22.379514 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11309 12:48:22.398432 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11310 12:48:22.461950 Camera needs 4 requests, can't test only 3
11311 12:48:22.555774 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11312 12:48:22.584166 [0:01:07.609922931] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11313 12:48:22.656443
11314 12:48:22.751771 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (58 ms)
11315 12:48:22.861057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11316 12:48:22.861800 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11318 12:48:22.877099 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11319 12:48:22.937628 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1131 ms)
11320 12:48:23.054462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11321 12:48:23.055252 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11323 12:48:23.073934 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11324 12:48:23.971172 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1395 ms)
11325 12:48:23.984612 [0:01:09.005376065] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11326 12:48:24.076909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11327 12:48:24.077252 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11329 12:48:24.094799 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11330 12:48:26.092758 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2122 ms)
11331 12:48:26.106259 [0:01:11.128970142] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 12:48:26.193843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11333 12:48:26.194170 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11335 12:48:26.208021 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11336 12:48:28.788607 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2695 ms)
11337 12:48:28.802005 [0:01:13.823921464] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11338 12:48:28.884230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11339 12:48:28.884546 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11341 12:48:28.897086 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11342 12:48:32.979174 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4190 ms)
11343 12:48:32.991940 [0:01:18.015164773] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11344 12:48:33.071362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11345 12:48:33.071651 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11347 12:48:33.087052 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11348 12:48:39.365409 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6386 ms)
11349 12:48:39.378280 [0:01:24.400556816] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11350 12:48:39.493607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11351 12:48:39.493919 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11353 12:48:39.511704 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11354 12:48:49.115286 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9751 ms)
11355 12:48:49.128350 [0:01:34.152073525] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11356 12:48:49.185715 [0:01:34.211983379] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11357 12:48:49.226548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11358 12:48:49.226808 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11360 12:48:49.243842 [0:01:34.269430681] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 12:48:49.249058 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11362 12:48:49.299785 [0:01:34.326920598] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11363 12:48:49.307221 Camera needs 4 requests, can't test only 1
11364 12:48:49.388947 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11365 12:48:49.466745
11366 12:48:49.554512 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (62 ms)
11367 12:48:49.648253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11368 12:48:49.648559 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11370 12:48:49.663183 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11371 12:48:49.712654 Camera needs 4 requests, can't test only 2
11372 12:48:49.800477 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11373 12:48:49.879106
11374 12:48:49.964268 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (57 ms)
11375 12:48:50.060928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11376 12:48:50.061218 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11378 12:48:50.073706 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11379 12:48:50.133444 Camera needs 4 requests, can't test only 3
11380 12:48:50.211147 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11381 12:48:50.294676
11382 12:48:50.385320 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (57 ms)
11383 12:48:50.479973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11384 12:48:50.480310 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11386 12:48:50.493953 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11387 12:48:50.650825 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1357 ms)
11388 12:48:50.660918 [0:01:35.684268498] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11389 12:48:50.750255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11390 12:48:50.750614 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11392 12:48:50.763995 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11393 12:48:52.047032 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1396 ms)
11394 12:48:52.056568 [0:01:37.079832080] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11395 12:48:52.149805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11396 12:48:52.150092 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11398 12:48:52.163724 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11399 12:48:54.167789 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2121 ms)
11400 12:48:54.177814 [0:01:39.201090248] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11401 12:48:54.267665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11402 12:48:54.267999 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11404 12:48:54.281508 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11405 12:48:56.862642 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2694 ms)
11406 12:48:56.872836 [0:01:41.895823635] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11407 12:48:56.968922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11408 12:48:56.969256 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11410 12:48:56.979705 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11411 12:49:00.986556 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4125 ms)
11412 12:49:00.996616 [0:01:46.020587130] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11413 12:49:01.087977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11414 12:49:01.088334 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11416 12:49:01.099215 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11417 12:49:07.275732 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6289 ms)
11418 12:49:07.284832 [0:01:52.308831109] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11419 12:49:07.409159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11420 12:49:07.409926 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11422 12:49:07.426690 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11423 12:49:16.962579 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9689 ms)
11424 12:49:16.972286 [0:02:01.996447351] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11425 12:49:17.024478 [0:02:02.053930683] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 12:49:17.082240 [0:02:02.111442528] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 12:49:17.101437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11428 12:49:17.102110 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11430 12:49:17.117907 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11431 12:49:17.139136 [0:02:02.168513629] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11432 12:49:17.189479 Camera needs 4 requests, can't test only 1
11433 12:49:17.280548 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11434 12:49:17.369975
11435 12:49:17.473833 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (57 ms)
11436 12:49:17.576770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11437 12:49:17.577551 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11439 12:49:17.590461 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11440 12:49:17.659559 Camera needs 4 requests, can't test only 2
11441 12:49:17.752763 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11442 12:49:17.832239
11443 12:49:17.928339 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (58 ms)
11444 12:49:18.020314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11445 12:49:18.020612 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11447 12:49:18.031829 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11448 12:49:18.085220 Camera needs 4 requests, can't test only 3
11449 12:49:18.166190 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11450 12:49:18.247254
11451 12:49:18.338606 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11452 12:49:18.399730 [0:02:03.429292207] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11453 12:49:18.434584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11454 12:49:18.434847 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11456 12:49:18.449346 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11457 12:49:18.504725 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1260 ms)
11458 12:49:18.591046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11459 12:49:18.591362 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11461 12:49:18.604643 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11462 12:49:19.786781 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1392 ms)
11463 12:49:19.797297 [0:02:04.820743590] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11464 12:49:19.893462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11465 12:49:19.893748 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11467 12:49:19.906678 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11468 12:49:21.906359 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2118 ms)
11469 12:49:21.915763 [0:02:06.939251762] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11470 12:49:22.028203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11471 12:49:22.028967 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11473 12:49:22.044081 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11474 12:49:24.633091 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2726 ms)
11475 12:49:24.642806 [0:02:09.666278075] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11476 12:49:24.738746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11477 12:49:24.739040 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11479 12:49:24.750450 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11480 12:49:28.885623 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4253 ms)
11481 12:49:28.895213 [0:02:13.918425318] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11482 12:49:29.003103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11483 12:49:29.003817 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11485 12:49:29.022104 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11486 12:49:35.171499 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6285 ms)
11487 12:49:35.181106 [0:02:20.203806571] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11488 12:49:35.305408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11489 12:49:35.306196 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11491 12:49:35.325501 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11492 12:49:44.888976 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9718 ms)
11493 12:49:44.898993 [0:02:29.921844266] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11494 12:49:44.951756 [0:02:29.979404276] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 12:49:45.008588 [0:02:30.035971323] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 12:49:45.014820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11497 12:49:45.015616 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11499 12:49:45.032151 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11500 12:49:45.066207 [0:02:30.094331554] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11501 12:49:45.104728 Camera needs 4 requests, can't test only 1
11502 12:49:45.200015 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11503 12:49:45.281714
11504 12:49:45.380092 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (58 ms)
11505 12:49:45.491368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11506 12:49:45.492154 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11508 12:49:45.517135 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11509 12:49:45.575989 Camera needs 4 requests, can't test only 2
11510 12:49:45.652645 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11511 12:49:45.728545
11512 12:49:45.816877 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (56 ms)
11513 12:49:45.930454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11514 12:49:45.931289 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11516 12:49:45.947860 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11517 12:49:46.016132 Camera needs 4 requests, can't test only 3
11518 12:49:46.117828 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11519 12:49:46.214825
11520 12:49:46.294544 [0:02:31.322784483] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11521 12:49:46.325527 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11522 12:49:46.439154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11523 12:49:46.439900 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11525 12:49:46.453005 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11526 12:49:46.524090 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1227 ms)
11527 12:49:46.637424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11528 12:49:46.638196 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11530 12:49:46.654183 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11531 12:49:47.717599 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1427 ms)
11532 12:49:47.726937 [0:02:32.751639524] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11533 12:49:47.839073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11534 12:49:47.839820 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11536 12:49:47.853067 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11537 12:49:49.840102 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2124 ms)
11538 12:49:49.850057 [0:02:34.874818126] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11539 12:49:49.963978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11540 12:49:49.964927 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11542 12:49:49.978236 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11543 12:49:52.533995 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2694 ms)
11544 12:49:52.543704 [0:02:37.569075110] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11545 12:49:52.658049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11546 12:49:52.658829 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11548 12:49:52.673660 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11549 12:49:56.660506 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4126 ms)
11550 12:49:56.670440 [0:02:41.694284010] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11551 12:49:56.784373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11552 12:49:56.785136 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11554 12:49:56.802616 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11555 12:50:02.979985 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6320 ms)
11556 12:50:02.989889 [0:02:48.014816952] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11557 12:50:03.103536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11558 12:50:03.104335 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11560 12:50:03.119315 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11561 12:50:12.699473 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9720 ms)
11562 12:50:12.709545 [0:02:57.733261898] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11563 12:50:12.823154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11564 12:50:12.823903 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11566 12:50:12.837315 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11567 12:50:12.995580 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (300 ms)
11568 12:50:13.008845 [0:02:58.033944737] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11569 12:50:13.129433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11570 12:50:13.130184 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11572 12:50:13.150373 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11573 12:50:13.266516 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (270 ms)
11574 12:50:13.279488 [0:02:58.303702408] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11575 12:50:13.390078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11576 12:50:13.390854 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11578 12:50:13.410292 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11579 12:50:13.568589 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (302 ms)
11580 12:50:13.581926 [0:02:58.607158875] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11581 12:50:13.711245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11582 12:50:13.712019 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11584 12:50:13.729528 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11585 12:50:14.003217 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (434 ms)
11586 12:50:14.015810 [0:02:59.041734413] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11587 12:50:14.131866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11588 12:50:14.132692 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11590 12:50:14.151421 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11591 12:50:14.506260 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (504 ms)
11592 12:50:14.519294 [0:02:59.544340876] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11593 12:50:14.627542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11594 12:50:14.628315 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11596 12:50:14.646012 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11597 12:50:15.208939 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (702 ms)
11598 12:50:15.222299 [0:03:00.245686173] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11599 12:50:15.354560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11600 12:50:15.355342 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11602 12:50:15.372804 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11603 12:50:16.109907 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (902 ms)
11604 12:50:16.122801 [0:03:01.146636718] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11605 12:50:16.237436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11606 12:50:16.238218 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11608 12:50:16.260801 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11609 12:50:17.444898 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1335 ms)
11610 12:50:17.458171 [0:03:02.481530209] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11611 12:50:17.601694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11612 12:50:17.602466 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11614 12:50:17.622904 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11615 12:50:19.575599 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2131 ms)
11616 12:50:19.588951 [0:03:04.613704824] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11617 12:50:19.691585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11618 12:50:19.692347 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11620 12:50:19.712531 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11621 12:50:22.809373 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3233 ms)
11622 12:50:22.823124 [0:03:07.847799875] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11623 12:50:22.926205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11624 12:50:22.927009 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11626 12:50:22.945787 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11627 12:50:23.083166 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (271 ms)
11628 12:50:23.092336 [0:03:08.117127422] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11629 12:50:23.211853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11630 12:50:23.212182 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11632 12:50:23.225938 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11633 12:50:23.345735 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (263 ms)
11634 12:50:23.355024 [0:03:08.379473948] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11635 12:50:23.446229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11636 12:50:23.446545 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11638 12:50:23.460568 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11639 12:50:23.645563 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (300 ms)
11640 12:50:23.654999 [0:03:08.679337690] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11641 12:50:23.779845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11642 12:50:23.780612 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11644 12:50:23.797759 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11645 12:50:24.013213 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (366 ms)
11646 12:50:24.022288 [0:03:09.046461117] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11647 12:50:24.140704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11648 12:50:24.141543 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11650 12:50:24.157773 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11651 12:50:24.480480 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (468 ms)
11652 12:50:24.490746 [0:03:09.514406392] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11653 12:50:24.620678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11654 12:50:24.621667 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11656 12:50:24.636588 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11657 12:50:25.212940 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (732 ms)
11658 12:50:25.223144 [0:03:10.246583923] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11659 12:50:25.343700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11660 12:50:25.344596 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11662 12:50:25.362065 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11663 12:50:26.111649 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (899 ms)
11664 12:50:26.121490 [0:03:11.146017630] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11665 12:50:26.233683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11666 12:50:26.234439 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11668 12:50:26.251898 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11669 12:50:27.510047 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1398 ms)
11670 12:50:27.519806 [0:03:12.545725053] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11671 12:50:27.627177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11672 12:50:27.627945 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11674 12:50:27.641964 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11675 12:50:29.611174 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2101 ms)
11676 12:50:29.620435 [0:03:14.646952285] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11677 12:50:29.743308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11678 12:50:29.744148 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11680 12:50:29.761172 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11681 12:50:32.811107 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3201 ms)
11682 12:50:32.820768 [0:03:17.845741815] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11683 12:50:32.942623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11684 12:50:32.943375 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11686 12:50:32.960691 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11687 12:50:33.109413 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (298 ms)
11688 12:50:33.119368 [0:03:18.143868499] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11689 12:50:33.252665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11690 12:50:33.253448 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11692 12:50:33.272115 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11693 12:50:33.377637 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (268 ms)
11694 12:50:33.386520 [0:03:18.412262092] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11695 12:50:33.515653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11696 12:50:33.516548 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11698 12:50:33.533595 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11699 12:50:33.672397 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (295 ms)
11700 12:50:33.683268 [0:03:18.708228296] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11701 12:50:33.797084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11702 12:50:33.797830 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11704 12:50:33.814353 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11705 12:50:34.100177 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (428 ms)
11706 12:50:34.110797 [0:03:19.136043801] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11707 12:50:34.228739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11708 12:50:34.229478 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11710 12:50:34.247666 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11711 12:50:34.563775 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (464 ms)
11712 12:50:34.573460 [0:03:19.599820831] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11713 12:50:34.692578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11714 12:50:34.693318 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11716 12:50:34.707330 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11717 12:50:35.258704 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (694 ms)
11718 12:50:35.268514 [0:03:20.294874466] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11719 12:50:35.379702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11720 12:50:35.380474 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11722 12:50:35.398865 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11723 12:50:36.154594 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (896 ms)
11724 12:50:36.164157 [0:03:21.191857842] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11725 12:50:36.283243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11726 12:50:36.284080 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11728 12:50:36.302349 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11729 12:50:37.549336 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1395 ms)
11730 12:50:37.559197 [0:03:22.584445760] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11731 12:50:37.677849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11732 12:50:37.678573 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11734 12:50:37.693290 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11735 12:50:39.610862 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2062 ms)
11736 12:50:39.621069 [0:03:24.647403204] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11737 12:50:39.745589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11738 12:50:39.746333 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11740 12:50:39.759824 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11741 12:50:42.836900 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3227 ms)
11742 12:50:42.846771 [0:03:27.872494176] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11743 12:50:42.932392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11744 12:50:42.932706 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11746 12:50:42.943184 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11747 12:50:43.098976 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (262 ms)
11748 12:50:43.108637 [0:03:28.135757933] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11749 12:50:43.203195 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11751 12:50:43.206205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11752 12:50:43.218028 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11753 12:50:43.362273 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (263 ms)
11754 12:50:43.371893 [0:03:28.399393901] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11755 12:50:43.467498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11756 12:50:43.467814 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11758 12:50:43.482961 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11759 12:50:43.658762 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (296 ms)
11760 12:50:43.668232 [0:03:28.695614188] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11761 12:50:43.762684 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11763 12:50:43.765619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11764 12:50:43.777855 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11765 12:50:44.022009 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (364 ms)
11766 12:50:44.031748 [0:03:29.058913582] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11767 12:50:44.118953 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11769 12:50:44.122455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11770 12:50:44.137539 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11771 12:50:44.485520 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (463 ms)
11772 12:50:44.495159 [0:03:29.520512633] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11773 12:50:44.618713 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11775 12:50:44.621880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11776 12:50:44.636850 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11777 12:50:45.113980 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (628 ms)
11778 12:50:45.123255 [0:03:30.148771087] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11779 12:50:45.233567 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11781 12:50:45.236318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11782 12:50:45.253487 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11783 12:50:46.007670 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (895 ms)
11784 12:50:46.017526 [0:03:31.044436253] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11785 12:50:46.106736 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11787 12:50:46.109760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11788 12:50:46.126809 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11789 12:50:47.400872 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1393 ms)
11790 12:50:47.410737 [0:03:32.437914248] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11791 12:50:47.506634 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11793 12:50:47.509766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11794 12:50:47.524426 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11795 12:50:49.494281 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2094 ms)
11796 12:50:49.504241 [0:03:34.531727817] [401] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11797 12:50:49.594908 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11799 12:50:49.598091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11800 12:50:49.611715 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11801 12:50:52.754058 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3260 ms)
11802 12:50:52.856324 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11804 12:50:52.859922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11805 12:50:52.872563 [----------] 120 tests from CaptureTests/SingleStream (188745 ms total)
11806 12:50:52.953250
11807 12:50:53.050284 [----------] Global test environment tear-down
11808 12:50:53.137783 [==========] 120 tests from 1 test suite ran. (188745 ms total)
11809 12:50:53.236087 <LAVA_SIGNAL_TESTSET STOP>
11810 12:50:53.236418 Received signal: <TESTSET> STOP
11811 12:50:53.236500 Closing test_set CaptureTests/SingleStream
11812 12:50:53.247426 + set +x
11813 12:50:53.250531 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10724911_1.6.2.3.1>
11814 12:50:53.250804 Received signal: <ENDRUN> 0_lc-compliance 10724911_1.6.2.3.1
11815 12:50:53.250886 Ending use of test pattern.
11816 12:50:53.250949 Ending test lava.0_lc-compliance (10724911_1.6.2.3.1), duration 190.41
11818 12:50:53.253491 <LAVA_TEST_RUNNER EXIT>
11819 12:50:53.253759 ok: lava_test_shell seems to have completed
11820 12:50:53.255578 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11821 12:50:53.255803 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11822 12:50:53.255904 end: 3 lava-test-retry (duration 00:03:11) [common]
11823 12:50:53.256052 start: 4 finalize (timeout 00:10:00) [common]
11824 12:50:53.256168 start: 4.1 power-off (timeout 00:00:30) [common]
11825 12:50:53.256331 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11826 12:50:53.331655 >> Command sent successfully.
11827 12:50:53.334000 Returned 0 in 0 seconds
11828 12:50:53.434463 end: 4.1 power-off (duration 00:00:00) [common]
11830 12:50:53.434855 start: 4.2 read-feedback (timeout 00:10:00) [common]
11831 12:50:53.435199 Listened to connection for namespace 'common' for up to 1s
11832 12:50:54.436141 Finalising connection for namespace 'common'
11833 12:50:54.436332 Disconnecting from shell: Finalise
11834 12:50:54.436437 / #
11835 12:50:54.536814 end: 4.2 read-feedback (duration 00:00:01) [common]
11836 12:50:54.537003 end: 4 finalize (duration 00:00:01) [common]
11837 12:50:54.537171 Cleaning after the job
11838 12:50:54.537310 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/ramdisk
11839 12:50:54.540041 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/kernel
11840 12:50:54.549207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/dtb
11841 12:50:54.549466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/nfsrootfs
11842 12:50:54.592366 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724911/tftp-deploy-q4vik08t/modules
11843 12:50:54.597802 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724911
11844 12:50:54.858479 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724911
11845 12:50:54.858662 Job finished correctly