Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 175
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
1 12:43:30.367843 lava-dispatcher, installed at version: 2023.05.1
2 12:43:30.368045 start: 0 validate
3 12:43:30.368182 Start time: 2023-06-14 12:43:30.368172+00:00 (UTC)
4 12:43:30.368301 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:43:30.368434 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 12:43:30.631320 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:43:30.632115 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:43:30.894167 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:43:30.894954 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:43:31.165031 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:43:31.165826 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:43:31.428847 validate duration: 1.06
14 12:43:31.429120 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:43:31.429222 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:43:31.429318 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:43:31.429444 Not decompressing ramdisk as can be used compressed.
18 12:43:31.429539 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230609.0/arm64/rootfs.cpio.gz
19 12:43:31.429612 saving as /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/ramdisk/rootfs.cpio.gz
20 12:43:31.429683 total size: 84920281 (80MB)
21 12:43:31.431468 progress 0% (0MB)
22 12:43:31.452785 progress 5% (4MB)
23 12:43:31.474392 progress 10% (8MB)
24 12:43:31.495612 progress 15% (12MB)
25 12:43:31.517080 progress 20% (16MB)
26 12:43:31.538337 progress 25% (20MB)
27 12:43:31.559739 progress 30% (24MB)
28 12:43:31.581104 progress 35% (28MB)
29 12:43:31.602236 progress 40% (32MB)
30 12:43:31.623505 progress 45% (36MB)
31 12:43:31.644798 progress 50% (40MB)
32 12:43:31.666071 progress 55% (44MB)
33 12:43:31.687085 progress 60% (48MB)
34 12:43:31.708285 progress 65% (52MB)
35 12:43:31.729640 progress 70% (56MB)
36 12:43:31.750976 progress 75% (60MB)
37 12:43:31.772252 progress 80% (64MB)
38 12:43:31.793476 progress 85% (68MB)
39 12:43:31.814809 progress 90% (72MB)
40 12:43:31.836141 progress 95% (76MB)
41 12:43:31.857251 progress 100% (80MB)
42 12:43:31.857471 80MB downloaded in 0.43s (189.32MB/s)
43 12:43:31.857632 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:43:31.857875 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:43:31.857965 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:43:31.858051 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:43:31.858190 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:43:31.858266 saving as /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/kernel/Image
50 12:43:31.858330 total size: 47581696 (45MB)
51 12:43:31.858392 No compression specified
52 12:43:31.859520 progress 0% (0MB)
53 12:43:31.871414 progress 5% (2MB)
54 12:43:31.883379 progress 10% (4MB)
55 12:43:31.895165 progress 15% (6MB)
56 12:43:31.907194 progress 20% (9MB)
57 12:43:31.919439 progress 25% (11MB)
58 12:43:31.931466 progress 30% (13MB)
59 12:43:31.943548 progress 35% (15MB)
60 12:43:31.955424 progress 40% (18MB)
61 12:43:31.967413 progress 45% (20MB)
62 12:43:31.979360 progress 50% (22MB)
63 12:43:31.991077 progress 55% (24MB)
64 12:43:32.002947 progress 60% (27MB)
65 12:43:32.014648 progress 65% (29MB)
66 12:43:32.026654 progress 70% (31MB)
67 12:43:32.038737 progress 75% (34MB)
68 12:43:32.050720 progress 80% (36MB)
69 12:43:32.062760 progress 85% (38MB)
70 12:43:32.074625 progress 90% (40MB)
71 12:43:32.086870 progress 95% (43MB)
72 12:43:32.099417 progress 100% (45MB)
73 12:43:32.099593 45MB downloaded in 0.24s (188.09MB/s)
74 12:43:32.099750 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:43:32.099987 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:43:32.100077 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:43:32.100166 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:43:32.100311 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:43:32.100387 saving as /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/dtb/mt8192-asurada-spherion-r0.dtb
81 12:43:32.100451 total size: 46924 (0MB)
82 12:43:32.100512 No compression specified
83 12:43:32.101755 progress 69% (0MB)
84 12:43:32.102045 progress 100% (0MB)
85 12:43:32.102202 0MB downloaded in 0.00s (25.60MB/s)
86 12:43:32.102333 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:43:32.102560 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:43:32.102648 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:43:32.102733 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:43:32.102852 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:43:32.102921 saving as /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/modules/modules.tar
93 12:43:32.102983 total size: 8536768 (8MB)
94 12:43:32.103044 Using unxz to decompress xz
95 12:43:32.106791 progress 0% (0MB)
96 12:43:32.128690 progress 5% (0MB)
97 12:43:32.156703 progress 10% (0MB)
98 12:43:32.189350 progress 15% (1MB)
99 12:43:32.214841 progress 20% (1MB)
100 12:43:32.239809 progress 25% (2MB)
101 12:43:32.265040 progress 30% (2MB)
102 12:43:32.289579 progress 35% (2MB)
103 12:43:32.317062 progress 40% (3MB)
104 12:43:32.342691 progress 45% (3MB)
105 12:43:32.369277 progress 50% (4MB)
106 12:43:32.394799 progress 55% (4MB)
107 12:43:32.421103 progress 60% (4MB)
108 12:43:32.447621 progress 65% (5MB)
109 12:43:32.473294 progress 70% (5MB)
110 12:43:32.498671 progress 75% (6MB)
111 12:43:32.523395 progress 80% (6MB)
112 12:43:32.547821 progress 85% (6MB)
113 12:43:32.572961 progress 90% (7MB)
114 12:43:32.597626 progress 95% (7MB)
115 12:43:32.620238 progress 100% (8MB)
116 12:43:32.626968 8MB downloaded in 0.52s (15.54MB/s)
117 12:43:32.627253 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:43:32.627525 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:43:32.627620 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:43:32.627717 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:43:32.627799 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:43:32.627890 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:43:32.628109 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu
125 12:43:32.628236 makedir: /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin
126 12:43:32.628336 makedir: /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/tests
127 12:43:32.628431 makedir: /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/results
128 12:43:32.628545 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-add-keys
129 12:43:32.628686 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-add-sources
130 12:43:32.628812 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-background-process-start
131 12:43:32.628939 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-background-process-stop
132 12:43:32.629098 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-common-functions
133 12:43:32.629220 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-echo-ipv4
134 12:43:32.629342 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-install-packages
135 12:43:32.629462 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-installed-packages
136 12:43:32.629581 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-os-build
137 12:43:32.629700 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-probe-channel
138 12:43:32.629818 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-probe-ip
139 12:43:32.629936 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-target-ip
140 12:43:32.630055 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-target-mac
141 12:43:32.630173 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-target-storage
142 12:43:32.630299 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-test-case
143 12:43:32.630419 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-test-event
144 12:43:32.630538 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-test-feedback
145 12:43:32.630657 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-test-raise
146 12:43:32.630777 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-test-reference
147 12:43:32.630895 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-test-runner
148 12:43:32.631015 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-test-set
149 12:43:32.631135 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-test-shell
150 12:43:32.631257 Updating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-install-packages (oe)
151 12:43:32.631404 Updating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/bin/lava-installed-packages (oe)
152 12:43:32.631530 Creating /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/environment
153 12:43:32.631628 LAVA metadata
154 12:43:32.631709 - LAVA_JOB_ID=10724891
155 12:43:32.631776 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:43:32.631904 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:43:32.631974 skipped lava-vland-overlay
158 12:43:32.632051 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:43:32.632133 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:43:32.632196 skipped lava-multinode-overlay
161 12:43:32.632273 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:43:32.632357 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:43:32.632432 Loading test definitions
164 12:43:32.632524 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 12:43:32.632600 Using /lava-10724891 at stage 0
166 12:43:32.632698 Fetching tests from https://github.com/kernelci/kernelci-core
167 12:43:32.632781 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/0/tests/0_sleep'
168 12:43:33.320056 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/0/tests/0_sleep
169 12:43:33.321231 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 12:43:33.321621 uuid=10724891_1.5.2.3.1 testdef=None
171 12:43:33.321769 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 12:43:33.322028 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 12:43:33.322612 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 12:43:33.322847 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 12:43:33.323538 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 12:43:33.323783 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 12:43:33.324440 runner path: /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/0/tests/0_sleep test_uuid 10724891_1.5.2.3.1
181 12:43:33.324528 sleep_params='mem freeze'
182 12:43:33.324669 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 12:43:33.324878 Creating lava-test-runner.conf files
185 12:43:33.324945 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724891/lava-overlay-6xjcp_gu/lava-10724891/0 for stage 0
186 12:43:33.325073 - 0_sleep
187 12:43:33.325179 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 12:43:33.325268 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 12:43:33.444091 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 12:43:33.444246 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 12:43:33.444344 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 12:43:33.444442 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 12:43:33.444530 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 12:43:35.741206 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 12:43:35.741556 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
196 12:43:35.741674 extracting modules file /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724891/extract-overlay-ramdisk-k6yhhbgr/ramdisk
197 12:43:35.945703 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 12:43:35.945879 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 12:43:35.945975 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724891/compress-overlay-ipfv20lp/overlay-1.5.2.4.tar.gz to ramdisk
200 12:43:35.946053 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724891/compress-overlay-ipfv20lp/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724891/extract-overlay-ramdisk-k6yhhbgr/ramdisk
201 12:43:36.033521 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 12:43:36.033669 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 12:43:36.033768 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 12:43:36.033859 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 12:43:36.033944 Building ramdisk /var/lib/lava/dispatcher/tmp/10724891/extract-overlay-ramdisk-k6yhhbgr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724891/extract-overlay-ramdisk-k6yhhbgr/ramdisk
206 12:43:37.516075 >> 561605 blocks
207 12:43:46.921016 rename /var/lib/lava/dispatcher/tmp/10724891/extract-overlay-ramdisk-k6yhhbgr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/ramdisk/ramdisk.cpio.gz
208 12:43:46.921500 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 12:43:46.921614 start: 1.5.8 prepare-kernel (timeout 00:09:45) [common]
210 12:43:46.921747 start: 1.5.8.1 prepare-fit (timeout 00:09:45) [common]
211 12:43:46.921872 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/kernel/Image'
212 12:43:58.560031 Returned 0 in 11 seconds
213 12:43:58.660714 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/kernel/image.itb
214 12:44:00.325324 output: FIT description: Kernel Image image with one or more FDT blobs
215 12:44:00.325681 output: Created: Wed Jun 14 13:44:00 2023
216 12:44:00.325757 output: Image 0 (kernel-1)
217 12:44:00.325822 output: Description:
218 12:44:00.325884 output: Created: Wed Jun 14 13:44:00 2023
219 12:44:00.325941 output: Type: Kernel Image
220 12:44:00.326002 output: Compression: lzma compressed
221 12:44:00.326060 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
222 12:44:00.326118 output: Architecture: AArch64
223 12:44:00.326177 output: OS: Linux
224 12:44:00.326236 output: Load Address: 0x00000000
225 12:44:00.326297 output: Entry Point: 0x00000000
226 12:44:00.326353 output: Hash algo: crc32
227 12:44:00.326406 output: Hash value: ced21bfe
228 12:44:00.326459 output: Image 1 (fdt-1)
229 12:44:00.326513 output: Description: mt8192-asurada-spherion-r0
230 12:44:00.326567 output: Created: Wed Jun 14 13:44:00 2023
231 12:44:00.326620 output: Type: Flat Device Tree
232 12:44:00.326673 output: Compression: uncompressed
233 12:44:00.326726 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 12:44:00.326778 output: Architecture: AArch64
235 12:44:00.326831 output: Hash algo: crc32
236 12:44:00.326884 output: Hash value: 1df858fa
237 12:44:00.326936 output: Image 2 (ramdisk-1)
238 12:44:00.326988 output: Description: unavailable
239 12:44:00.327041 output: Created: Wed Jun 14 13:44:00 2023
240 12:44:00.327094 output: Type: RAMDisk Image
241 12:44:00.327147 output: Compression: Unknown Compression
242 12:44:00.327199 output: Data Size: 98154185 Bytes = 95853.70 KiB = 93.61 MiB
243 12:44:00.327252 output: Architecture: AArch64
244 12:44:00.327305 output: OS: Linux
245 12:44:00.327358 output: Load Address: unavailable
246 12:44:00.327411 output: Entry Point: unavailable
247 12:44:00.327463 output: Hash algo: crc32
248 12:44:00.327516 output: Hash value: ed5a89b0
249 12:44:00.327568 output: Default Configuration: 'conf-1'
250 12:44:00.327620 output: Configuration 0 (conf-1)
251 12:44:00.327673 output: Description: mt8192-asurada-spherion-r0
252 12:44:00.327726 output: Kernel: kernel-1
253 12:44:00.327778 output: Init Ramdisk: ramdisk-1
254 12:44:00.327830 output: FDT: fdt-1
255 12:44:00.327883 output: Loadables: kernel-1
256 12:44:00.327935 output:
257 12:44:00.328124 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
258 12:44:00.328219 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
259 12:44:00.328325 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 12:44:00.328418 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
261 12:44:00.328501 No LXC device requested
262 12:44:00.328577 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 12:44:00.328662 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
264 12:44:00.328740 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 12:44:00.328807 Checking files for TFTP limit of 4294967296 bytes.
266 12:44:00.329349 end: 1 tftp-deploy (duration 00:00:29) [common]
267 12:44:00.329460 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 12:44:00.329554 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 12:44:00.329672 substitutions:
270 12:44:00.329739 - {DTB}: 10724891/tftp-deploy-y3xahij0/dtb/mt8192-asurada-spherion-r0.dtb
271 12:44:00.329804 - {INITRD}: 10724891/tftp-deploy-y3xahij0/ramdisk/ramdisk.cpio.gz
272 12:44:00.329864 - {KERNEL}: 10724891/tftp-deploy-y3xahij0/kernel/Image
273 12:44:00.329922 - {LAVA_MAC}: None
274 12:44:00.329978 - {PRESEED_CONFIG}: None
275 12:44:00.330033 - {PRESEED_LOCAL}: None
276 12:44:00.330087 - {RAMDISK}: 10724891/tftp-deploy-y3xahij0/ramdisk/ramdisk.cpio.gz
277 12:44:00.330143 - {ROOT_PART}: None
278 12:44:00.330196 - {ROOT}: None
279 12:44:00.330253 - {SERVER_IP}: 192.168.201.1
280 12:44:00.330307 - {TEE}: None
281 12:44:00.330361 Parsed boot commands:
282 12:44:00.330415 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 12:44:00.330590 Parsed boot commands: tftpboot 192.168.201.1 10724891/tftp-deploy-y3xahij0/kernel/image.itb 10724891/tftp-deploy-y3xahij0/kernel/cmdline
284 12:44:00.330681 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 12:44:00.330767 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 12:44:00.330858 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 12:44:00.330944 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 12:44:00.331014 Not connected, no need to disconnect.
289 12:44:00.331088 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 12:44:00.331168 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 12:44:00.331235 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
292 12:44:00.334475 Setting prompt string to ['lava-test: # ']
293 12:44:00.334821 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 12:44:00.334940 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 12:44:00.335073 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 12:44:00.335195 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 12:44:00.335429 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
298 12:44:05.467226 >> Command sent successfully.
299 12:44:05.469726 Returned 0 in 5 seconds
300 12:44:05.570104 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 12:44:05.570441 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 12:44:05.570554 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 12:44:05.570651 Setting prompt string to 'Starting depthcharge on Spherion...'
305 12:44:05.570725 Changing prompt to 'Starting depthcharge on Spherion...'
306 12:44:05.570798 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 12:44:05.571080 [Enter `^Ec?' for help]
308 12:44:05.744671
309 12:44:05.745243
310 12:44:05.745606 F0: 102B 0000
311 12:44:05.746005
312 12:44:05.746359 F3: 1001 0000 [0200]
313 12:44:05.746710
314 12:44:05.747727 F3: 1001 0000
315 12:44:05.748159
316 12:44:05.748575 F7: 102D 0000
317 12:44:05.749018
318 12:44:05.751202 F1: 0000 0000
319 12:44:05.751804
320 12:44:05.752319 V0: 0000 0000 [0001]
321 12:44:05.752757
322 12:44:05.754370 00: 0007 8000
323 12:44:05.754839
324 12:44:05.755357 01: 0000 0000
325 12:44:05.755803
326 12:44:05.758287 BP: 0C00 0209 [0000]
327 12:44:05.758731
328 12:44:05.759127 G0: 1182 0000
329 12:44:05.759491
330 12:44:05.761288 EC: 0000 0021 [4000]
331 12:44:05.761751
332 12:44:05.762139 S7: 0000 0000 [0000]
333 12:44:05.762554
334 12:44:05.764480 CC: 0000 0000 [0001]
335 12:44:05.764829
336 12:44:05.765129 T0: 0000 0040 [010F]
337 12:44:05.765410
338 12:44:05.767754 Jump to BL
339 12:44:05.768119
340 12:44:05.790733
341 12:44:05.790851
342 12:44:05.790923
343 12:44:05.797596 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 12:44:05.801300 ARM64: Exception handlers installed.
345 12:44:05.804938 ARM64: Testing exception
346 12:44:05.808500 ARM64: Done test exception
347 12:44:05.815202 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 12:44:05.824940 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 12:44:05.831684 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 12:44:05.841959 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 12:44:05.848300 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 12:44:05.858822 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 12:44:05.869433 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 12:44:05.875858 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 12:44:05.893769 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 12:44:05.896846 WDT: Last reset was cold boot
357 12:44:05.900695 SPI1(PAD0) initialized at 2873684 Hz
358 12:44:05.903523 SPI5(PAD0) initialized at 992727 Hz
359 12:44:05.906716 VBOOT: Loading verstage.
360 12:44:05.913233 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 12:44:05.916730 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 12:44:05.919911 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 12:44:05.923672 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 12:44:05.931294 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 12:44:05.937758 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 12:44:05.948648 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
367 12:44:05.948759
368 12:44:05.948861
369 12:44:05.958866 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 12:44:05.961848 ARM64: Exception handlers installed.
371 12:44:05.965441 ARM64: Testing exception
372 12:44:05.965547 ARM64: Done test exception
373 12:44:05.971863 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 12:44:05.975553 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 12:44:05.989513 Probing TPM: . done!
376 12:44:05.989607 TPM ready after 0 ms
377 12:44:05.996230 Connected to device vid:did:rid of 1ae0:0028:00
378 12:44:06.006733 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 12:44:06.062387 Initialized TPM device CR50 revision 0
380 12:44:06.073477 tlcl_send_startup: Startup return code is 0
381 12:44:06.073604 TPM: setup succeeded
382 12:44:06.084895 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 12:44:06.093857 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 12:44:06.104154 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 12:44:06.113370 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 12:44:06.117135 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 12:44:06.124477 in-header: 03 07 00 00 08 00 00 00
388 12:44:06.128187 in-data: aa e4 47 04 13 02 00 00
389 12:44:06.131929 Chrome EC: UHEPI supported
390 12:44:06.138974 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 12:44:06.142188 in-header: 03 ad 00 00 08 00 00 00
392 12:44:06.145983 in-data: 00 20 20 08 00 00 00 00
393 12:44:06.146082 Phase 1
394 12:44:06.149796 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 12:44:06.156850 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 12:44:06.160659 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 12:44:06.164539 Recovery requested (1009000e)
398 12:44:06.174415 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 12:44:06.180972 tlcl_extend: response is 0
400 12:44:06.190708 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 12:44:06.196440 tlcl_extend: response is 0
402 12:44:06.203785 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 12:44:06.224152 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 12:44:06.230769 BS: bootblock times (exec / console): total (unknown) / 149 ms
405 12:44:06.230863
406 12:44:06.230935
407 12:44:06.240478 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 12:44:06.244019 ARM64: Exception handlers installed.
409 12:44:06.244105 ARM64: Testing exception
410 12:44:06.247361 ARM64: Done test exception
411 12:44:06.268951 pmic_efuse_setting: Set efuses in 11 msecs
412 12:44:06.272556 pmwrap_interface_init: Select PMIF_VLD_RDY
413 12:44:06.279807 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 12:44:06.282862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 12:44:06.289692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 12:44:06.292706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 12:44:06.299726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 12:44:06.302985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 12:44:06.306749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 12:44:06.314078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 12:44:06.317312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 12:44:06.321055 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 12:44:06.324926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 12:44:06.331224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 12:44:06.334746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 12:44:06.340939 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 12:44:06.348341 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 12:44:06.351511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 12:44:06.358844 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 12:44:06.365834 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 12:44:06.369086 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 12:44:06.375690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 12:44:06.379628 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 12:44:06.386754 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 12:44:06.393265 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 12:44:06.396675 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 12:44:06.403353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 12:44:06.410468 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 12:44:06.413320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 12:44:06.419805 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 12:44:06.423509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 12:44:06.426746 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 12:44:06.433314 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 12:44:06.436233 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 12:44:06.443266 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 12:44:06.449849 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 12:44:06.453004 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 12:44:06.459607 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 12:44:06.463029 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 12:44:06.469603 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 12:44:06.473262 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 12:44:06.476926 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 12:44:06.480855 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 12:44:06.484023 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 12:44:06.490627 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 12:44:06.494411 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 12:44:06.497278 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 12:44:06.504153 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 12:44:06.507292 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 12:44:06.510633 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 12:44:06.517192 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 12:44:06.520460 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 12:44:06.524276 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 12:44:06.530494 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 12:44:06.540647 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 12:44:06.543791 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 12:44:06.553626 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 12:44:06.560182 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 12:44:06.567242 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 12:44:06.570363 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 12:44:06.573649 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 12:44:06.581796 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x4
473 12:44:06.588452 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 12:44:06.591646 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 12:44:06.595320 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 12:44:06.606642 [RTC]rtc_get_frequency_meter,154: input=15, output=772
477 12:44:06.615792 [RTC]rtc_get_frequency_meter,154: input=23, output=957
478 12:44:06.624974 [RTC]rtc_get_frequency_meter,154: input=19, output=865
479 12:44:06.634655 [RTC]rtc_get_frequency_meter,154: input=17, output=819
480 12:44:06.645181 [RTC]rtc_get_frequency_meter,154: input=16, output=795
481 12:44:06.648375 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
482 12:44:06.652247 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
483 12:44:06.659004 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
484 12:44:06.663347 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
485 12:44:06.666546 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
486 12:44:06.670088 ADC[4]: Raw value=902139 ID=7
487 12:44:06.670176 ADC[3]: Raw value=213179 ID=1
488 12:44:06.673264 RAM Code: 0x71
489 12:44:06.676870 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
490 12:44:06.684658 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
491 12:44:06.692477 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
492 12:44:06.699205 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 12:44:06.699329 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
494 12:44:06.702583 in-header: 03 07 00 00 08 00 00 00
495 12:44:06.706315 in-data: aa e4 47 04 13 02 00 00
496 12:44:06.709711 Chrome EC: UHEPI supported
497 12:44:06.716011 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
498 12:44:06.719308 in-header: 03 ed 00 00 08 00 00 00
499 12:44:06.722774 in-data: 80 20 60 08 00 00 00 00
500 12:44:06.725884 MRC: failed to locate region type 0.
501 12:44:06.732596 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
502 12:44:06.735880 DRAM-K: Running full calibration
503 12:44:06.742510 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
504 12:44:06.742597 header.status = 0x0
505 12:44:06.745753 header.version = 0x6 (expected: 0x6)
506 12:44:06.749386 header.size = 0xd00 (expected: 0xd00)
507 12:44:06.752692 header.flags = 0x0
508 12:44:06.759485 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
509 12:44:06.777418 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
510 12:44:06.784375 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
511 12:44:06.787323 dram_init: ddr_geometry: 2
512 12:44:06.787408 [EMI] MDL number = 2
513 12:44:06.791165 [EMI] Get MDL freq = 0
514 12:44:06.791250 dram_init: ddr_type: 0
515 12:44:06.794095 is_discrete_lpddr4: 1
516 12:44:06.797418 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
517 12:44:06.797503
518 12:44:06.797571
519 12:44:06.800614 [Bian_co] ETT version 0.0.0.1
520 12:44:06.804254 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
521 12:44:06.804339
522 12:44:06.807526 dramc_set_vcore_voltage set vcore to 650000
523 12:44:06.810526 Read voltage for 800, 4
524 12:44:06.810611 Vio18 = 0
525 12:44:06.814093 Vcore = 650000
526 12:44:06.814181 Vdram = 0
527 12:44:06.814249 Vddq = 0
528 12:44:06.817274 Vmddr = 0
529 12:44:06.817359 dram_init: config_dvfs: 1
530 12:44:06.824175 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
531 12:44:06.827650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
532 12:44:06.834551 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
533 12:44:06.837263 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
534 12:44:06.840543 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
535 12:44:06.843759 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
536 12:44:06.847461 MEM_TYPE=3, freq_sel=18
537 12:44:06.850961 sv_algorithm_assistance_LP4_1600
538 12:44:06.854007 ============ PULL DRAM RESETB DOWN ============
539 12:44:06.857599 ========== PULL DRAM RESETB DOWN end =========
540 12:44:06.864161 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
541 12:44:06.867139 ===================================
542 12:44:06.867224 LPDDR4 DRAM CONFIGURATION
543 12:44:06.870361 ===================================
544 12:44:06.874027 EX_ROW_EN[0] = 0x0
545 12:44:06.874112 EX_ROW_EN[1] = 0x0
546 12:44:06.877263 LP4Y_EN = 0x0
547 12:44:06.877348 WORK_FSP = 0x0
548 12:44:06.880600 WL = 0x2
549 12:44:06.880685 RL = 0x2
550 12:44:06.884081 BL = 0x2
551 12:44:06.887406 RPST = 0x0
552 12:44:06.887491 RD_PRE = 0x0
553 12:44:06.890699 WR_PRE = 0x1
554 12:44:06.890783 WR_PST = 0x0
555 12:44:06.893738 DBI_WR = 0x0
556 12:44:06.893823 DBI_RD = 0x0
557 12:44:06.897262 OTF = 0x1
558 12:44:06.900391 ===================================
559 12:44:06.903806 ===================================
560 12:44:06.903891 ANA top config
561 12:44:06.907175 ===================================
562 12:44:06.910919 DLL_ASYNC_EN = 0
563 12:44:06.913705 ALL_SLAVE_EN = 1
564 12:44:06.913790 NEW_RANK_MODE = 1
565 12:44:06.916924 DLL_IDLE_MODE = 1
566 12:44:06.920475 LP45_APHY_COMB_EN = 1
567 12:44:06.923685 TX_ODT_DIS = 1
568 12:44:06.923770 NEW_8X_MODE = 1
569 12:44:06.927199 ===================================
570 12:44:06.930477 ===================================
571 12:44:06.933658 data_rate = 1600
572 12:44:06.936967 CKR = 1
573 12:44:06.940725 DQ_P2S_RATIO = 8
574 12:44:06.944222 ===================================
575 12:44:06.947118 CA_P2S_RATIO = 8
576 12:44:06.950621 DQ_CA_OPEN = 0
577 12:44:06.950706 DQ_SEMI_OPEN = 0
578 12:44:06.953588 CA_SEMI_OPEN = 0
579 12:44:06.957511 CA_FULL_RATE = 0
580 12:44:06.960300 DQ_CKDIV4_EN = 1
581 12:44:06.963774 CA_CKDIV4_EN = 1
582 12:44:06.967459 CA_PREDIV_EN = 0
583 12:44:06.967544 PH8_DLY = 0
584 12:44:06.970746 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
585 12:44:06.973594 DQ_AAMCK_DIV = 4
586 12:44:06.977280 CA_AAMCK_DIV = 4
587 12:44:06.980339 CA_ADMCK_DIV = 4
588 12:44:06.983876 DQ_TRACK_CA_EN = 0
589 12:44:06.983961 CA_PICK = 800
590 12:44:06.987009 CA_MCKIO = 800
591 12:44:06.990371 MCKIO_SEMI = 0
592 12:44:06.993595 PLL_FREQ = 3068
593 12:44:06.997095 DQ_UI_PI_RATIO = 32
594 12:44:07.000064 CA_UI_PI_RATIO = 0
595 12:44:07.003425 ===================================
596 12:44:07.006857 ===================================
597 12:44:07.010018 memory_type:LPDDR4
598 12:44:07.010102 GP_NUM : 10
599 12:44:07.013432 SRAM_EN : 1
600 12:44:07.013516 MD32_EN : 0
601 12:44:07.016867 ===================================
602 12:44:07.020822 [ANA_INIT] >>>>>>>>>>>>>>
603 12:44:07.024375 <<<<<< [CONFIGURE PHASE]: ANA_TX
604 12:44:07.027902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
605 12:44:07.031502 ===================================
606 12:44:07.031593 data_rate = 1600,PCW = 0X7600
607 12:44:07.035257 ===================================
608 12:44:07.038434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
609 12:44:07.045370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
610 12:44:07.048889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
611 12:44:07.056086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
612 12:44:07.059411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
613 12:44:07.062517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
614 12:44:07.062606 [ANA_INIT] flow start
615 12:44:07.066411 [ANA_INIT] PLL >>>>>>>>
616 12:44:07.069419 [ANA_INIT] PLL <<<<<<<<
617 12:44:07.069507 [ANA_INIT] MIDPI >>>>>>>>
618 12:44:07.072645 [ANA_INIT] MIDPI <<<<<<<<
619 12:44:07.076296 [ANA_INIT] DLL >>>>>>>>
620 12:44:07.076384 [ANA_INIT] flow end
621 12:44:07.082920 ============ LP4 DIFF to SE enter ============
622 12:44:07.086165 ============ LP4 DIFF to SE exit ============
623 12:44:07.089183 [ANA_INIT] <<<<<<<<<<<<<
624 12:44:07.093196 [Flow] Enable top DCM control >>>>>
625 12:44:07.096225 [Flow] Enable top DCM control <<<<<
626 12:44:07.096330 Enable DLL master slave shuffle
627 12:44:07.102515 ==============================================================
628 12:44:07.105762 Gating Mode config
629 12:44:07.109087 ==============================================================
630 12:44:07.112474 Config description:
631 12:44:07.122827 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
632 12:44:07.129288 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
633 12:44:07.132702 SELPH_MODE 0: By rank 1: By Phase
634 12:44:07.139156 ==============================================================
635 12:44:07.143093 GAT_TRACK_EN = 1
636 12:44:07.145738 RX_GATING_MODE = 2
637 12:44:07.149357 RX_GATING_TRACK_MODE = 2
638 12:44:07.149430 SELPH_MODE = 1
639 12:44:07.152888 PICG_EARLY_EN = 1
640 12:44:07.155892 VALID_LAT_VALUE = 1
641 12:44:07.162646 ==============================================================
642 12:44:07.165948 Enter into Gating configuration >>>>
643 12:44:07.168991 Exit from Gating configuration <<<<
644 12:44:07.172586 Enter into DVFS_PRE_config >>>>>
645 12:44:07.182092 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
646 12:44:07.185911 Exit from DVFS_PRE_config <<<<<
647 12:44:07.189008 Enter into PICG configuration >>>>
648 12:44:07.192174 Exit from PICG configuration <<<<
649 12:44:07.195879 [RX_INPUT] configuration >>>>>
650 12:44:07.199062 [RX_INPUT] configuration <<<<<
651 12:44:07.202587 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
652 12:44:07.208949 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
653 12:44:07.215641 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
654 12:44:07.222554 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
655 12:44:07.225736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
656 12:44:07.232318 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
657 12:44:07.235644 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
658 12:44:07.242028 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
659 12:44:07.245905 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
660 12:44:07.249554 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
661 12:44:07.252825 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
662 12:44:07.260066 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
663 12:44:07.262650 ===================================
664 12:44:07.262728 LPDDR4 DRAM CONFIGURATION
665 12:44:07.266088 ===================================
666 12:44:07.269422 EX_ROW_EN[0] = 0x0
667 12:44:07.272954 EX_ROW_EN[1] = 0x0
668 12:44:07.273071 LP4Y_EN = 0x0
669 12:44:07.275790 WORK_FSP = 0x0
670 12:44:07.275889 WL = 0x2
671 12:44:07.279376 RL = 0x2
672 12:44:07.279452 BL = 0x2
673 12:44:07.282947 RPST = 0x0
674 12:44:07.283049 RD_PRE = 0x0
675 12:44:07.286033 WR_PRE = 0x1
676 12:44:07.286107 WR_PST = 0x0
677 12:44:07.289289 DBI_WR = 0x0
678 12:44:07.289361 DBI_RD = 0x0
679 12:44:07.292915 OTF = 0x1
680 12:44:07.296227 ===================================
681 12:44:07.299793 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
682 12:44:07.303496 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
683 12:44:07.306726 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
684 12:44:07.310113 ===================================
685 12:44:07.313358 LPDDR4 DRAM CONFIGURATION
686 12:44:07.317267 ===================================
687 12:44:07.320314 EX_ROW_EN[0] = 0x10
688 12:44:07.320390 EX_ROW_EN[1] = 0x0
689 12:44:07.323328 LP4Y_EN = 0x0
690 12:44:07.323406 WORK_FSP = 0x0
691 12:44:07.327174 WL = 0x2
692 12:44:07.327250 RL = 0x2
693 12:44:07.330477 BL = 0x2
694 12:44:07.330552 RPST = 0x0
695 12:44:07.334047 RD_PRE = 0x0
696 12:44:07.334127 WR_PRE = 0x1
697 12:44:07.337786 WR_PST = 0x0
698 12:44:07.337861 DBI_WR = 0x0
699 12:44:07.341254 DBI_RD = 0x0
700 12:44:07.341361 OTF = 0x1
701 12:44:07.344753 ===================================
702 12:44:07.352315 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
703 12:44:07.355681 nWR fixed to 40
704 12:44:07.355788 [ModeRegInit_LP4] CH0 RK0
705 12:44:07.359187 [ModeRegInit_LP4] CH0 RK1
706 12:44:07.363260 [ModeRegInit_LP4] CH1 RK0
707 12:44:07.363365 [ModeRegInit_LP4] CH1 RK1
708 12:44:07.366461 match AC timing 13
709 12:44:07.370157 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
710 12:44:07.374149 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
711 12:44:07.377835 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
712 12:44:07.385028 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
713 12:44:07.388616 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
714 12:44:07.388695 [EMI DOE] emi_dcm 0
715 12:44:07.392448 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
716 12:44:07.395937 ==
717 12:44:07.396022 Dram Type= 6, Freq= 0, CH_0, rank 0
718 12:44:07.403722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
719 12:44:07.403831 ==
720 12:44:07.407498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
721 12:44:07.414207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
722 12:44:07.422701 [CA 0] Center 38 (7~69) winsize 63
723 12:44:07.426210 [CA 1] Center 38 (7~69) winsize 63
724 12:44:07.429691 [CA 2] Center 35 (5~66) winsize 62
725 12:44:07.432901 [CA 3] Center 35 (5~66) winsize 62
726 12:44:07.436769 [CA 4] Center 34 (4~65) winsize 62
727 12:44:07.440300 [CA 5] Center 33 (3~64) winsize 62
728 12:44:07.440548
729 12:44:07.443583 [CmdBusTrainingLP45] Vref(ca) range 1: 34
730 12:44:07.443835
731 12:44:07.447011 [CATrainingPosCal] consider 1 rank data
732 12:44:07.451115 u2DelayCellTimex100 = 270/100 ps
733 12:44:07.454952 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
734 12:44:07.458314 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
735 12:44:07.462208 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
736 12:44:07.465556 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
737 12:44:07.469601 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
738 12:44:07.473011 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
739 12:44:07.473457
740 12:44:07.476633 CA PerBit enable=1, Macro0, CA PI delay=33
741 12:44:07.477354
742 12:44:07.480578 [CBTSetCACLKResult] CA Dly = 33
743 12:44:07.481293 CS Dly: 6 (0~37)
744 12:44:07.481927 ==
745 12:44:07.484136 Dram Type= 6, Freq= 0, CH_0, rank 1
746 12:44:07.487950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
747 12:44:07.488394 ==
748 12:44:07.495059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
749 12:44:07.498771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
750 12:44:07.509185 [CA 0] Center 38 (7~69) winsize 63
751 12:44:07.513036 [CA 1] Center 38 (8~69) winsize 62
752 12:44:07.516900 [CA 2] Center 36 (6~67) winsize 62
753 12:44:07.520672 [CA 3] Center 35 (5~66) winsize 62
754 12:44:07.524415 [CA 4] Center 35 (4~66) winsize 63
755 12:44:07.524877 [CA 5] Center 34 (4~65) winsize 62
756 12:44:07.528147
757 12:44:07.528740 [CmdBusTrainingLP45] Vref(ca) range 1: 32
758 12:44:07.532100
759 12:44:07.532548 [CATrainingPosCal] consider 2 rank data
760 12:44:07.535845 u2DelayCellTimex100 = 270/100 ps
761 12:44:07.539515 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
762 12:44:07.543720 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
763 12:44:07.547132 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
764 12:44:07.550738 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
765 12:44:07.554312 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
766 12:44:07.557704 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
767 12:44:07.558166
768 12:44:07.561463 CA PerBit enable=1, Macro0, CA PI delay=34
769 12:44:07.561948
770 12:44:07.564874 [CBTSetCACLKResult] CA Dly = 34
771 12:44:07.568971 CS Dly: 6 (0~38)
772 12:44:07.569436
773 12:44:07.572497 ----->DramcWriteLeveling(PI) begin...
774 12:44:07.572946 ==
775 12:44:07.573352 Dram Type= 6, Freq= 0, CH_0, rank 0
776 12:44:07.579943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
777 12:44:07.580390 ==
778 12:44:07.583738 Write leveling (Byte 0): 31 => 31
779 12:44:07.584206 Write leveling (Byte 1): 28 => 28
780 12:44:07.587422 DramcWriteLeveling(PI) end<-----
781 12:44:07.587865
782 12:44:07.588221 ==
783 12:44:07.591086 Dram Type= 6, Freq= 0, CH_0, rank 0
784 12:44:07.594944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
785 12:44:07.595386 ==
786 12:44:07.598358 [Gating] SW mode calibration
787 12:44:07.606709 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
788 12:44:07.609707 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
789 12:44:07.613526 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
790 12:44:07.621066 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
791 12:44:07.624501 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
792 12:44:07.628725 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:44:07.631949 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:44:07.635172 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:44:07.641893 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:44:07.645686 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:44:07.648571 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:44:07.655317 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:44:07.658536 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:44:07.661936 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:44:07.668377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:44:07.671603 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:44:07.675532 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:44:07.681643 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:44:07.684814 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
806 12:44:07.688323 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
807 12:44:07.694860 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
808 12:44:07.698342 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:44:07.701396 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:44:07.708538 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:44:07.712260 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:44:07.715230 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:44:07.721849 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:44:07.725163 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
815 12:44:07.728535 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
816 12:44:07.734976 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
817 12:44:07.738426 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:44:07.741411 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:44:07.748095 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:44:07.751509 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 12:44:07.755085 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 12:44:07.758494 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
823 12:44:07.764480 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
824 12:44:07.767970 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
825 12:44:07.771364 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:44:07.777967 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:44:07.781046 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:44:07.784383 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:44:07.791296 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:44:07.794290 0 11 4 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
831 12:44:07.797556 0 11 8 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
832 12:44:07.804290 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
833 12:44:07.807443 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:44:07.811268 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:44:07.817700 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:44:07.821148 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:44:07.824404 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:44:07.831179 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 12:44:07.834712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:44:07.837608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:44:07.844261 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:44:07.847749 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:44:07.851385 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:44:07.857749 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:44:07.860908 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:44:07.864266 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:44:07.870803 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:44:07.874348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:44:07.877623 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:44:07.884088 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:44:07.887574 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:44:07.890815 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:44:07.897444 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:44:07.900653 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
855 12:44:07.904216 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:44:07.907154 Total UI for P1: 0, mck2ui 16
857 12:44:07.910617 best dqsien dly found for B0: ( 0, 14, 4)
858 12:44:07.914008 Total UI for P1: 0, mck2ui 16
859 12:44:07.917516 best dqsien dly found for B1: ( 0, 14, 6)
860 12:44:07.920940 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
861 12:44:07.923701 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
862 12:44:07.923815
863 12:44:07.927323 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
864 12:44:07.930430 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
865 12:44:07.934052 [Gating] SW calibration Done
866 12:44:07.934167 ==
867 12:44:07.937606 Dram Type= 6, Freq= 0, CH_0, rank 0
868 12:44:07.944066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
869 12:44:07.944186 ==
870 12:44:07.944286 RX Vref Scan: 0
871 12:44:07.944382
872 12:44:07.946925 RX Vref 0 -> 0, step: 1
873 12:44:07.947035
874 12:44:07.950510 RX Delay -130 -> 252, step: 16
875 12:44:07.954027 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
876 12:44:07.956892 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
877 12:44:07.960394 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
878 12:44:07.966801 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
879 12:44:07.970248 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
880 12:44:07.973504 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
881 12:44:07.976868 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
882 12:44:07.980365 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
883 12:44:07.986902 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
884 12:44:07.990196 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
885 12:44:07.993401 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
886 12:44:07.996650 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
887 12:44:08.000002 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
888 12:44:08.006950 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
889 12:44:08.010119 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
890 12:44:08.013464 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
891 12:44:08.013576 ==
892 12:44:08.016809 Dram Type= 6, Freq= 0, CH_0, rank 0
893 12:44:08.020271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
894 12:44:08.020386 ==
895 12:44:08.023466 DQS Delay:
896 12:44:08.023577 DQS0 = 0, DQS1 = 0
897 12:44:08.026821 DQM Delay:
898 12:44:08.026934 DQM0 = 88, DQM1 = 78
899 12:44:08.027036 DQ Delay:
900 12:44:08.030015 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
901 12:44:08.033177 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
902 12:44:08.037225 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
903 12:44:08.040131 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
904 12:44:08.040244
905 12:44:08.043325
906 12:44:08.043437 ==
907 12:44:08.046696 Dram Type= 6, Freq= 0, CH_0, rank 0
908 12:44:08.050231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 12:44:08.050341 ==
910 12:44:08.050438
911 12:44:08.050532
912 12:44:08.053315 TX Vref Scan disable
913 12:44:08.053426 == TX Byte 0 ==
914 12:44:08.060403 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
915 12:44:08.063709 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
916 12:44:08.063828 == TX Byte 1 ==
917 12:44:08.070650 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
918 12:44:08.073290 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
919 12:44:08.073407 ==
920 12:44:08.076768 Dram Type= 6, Freq= 0, CH_0, rank 0
921 12:44:08.079847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 12:44:08.079963 ==
923 12:44:08.093646 TX Vref=22, minBit 8, minWin=26, winSum=440
924 12:44:08.096936 TX Vref=24, minBit 7, minWin=27, winSum=448
925 12:44:08.100239 TX Vref=26, minBit 8, minWin=27, winSum=450
926 12:44:08.103219 TX Vref=28, minBit 9, minWin=27, winSum=453
927 12:44:08.106511 TX Vref=30, minBit 6, minWin=28, winSum=457
928 12:44:08.113844 TX Vref=32, minBit 3, minWin=28, winSum=453
929 12:44:08.117092 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 30
930 12:44:08.117182
931 12:44:08.120114 Final TX Range 1 Vref 30
932 12:44:08.120200
933 12:44:08.120271 ==
934 12:44:08.123438 Dram Type= 6, Freq= 0, CH_0, rank 0
935 12:44:08.126588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 12:44:08.126678 ==
937 12:44:08.130261
938 12:44:08.130346
939 12:44:08.130413 TX Vref Scan disable
940 12:44:08.133414 == TX Byte 0 ==
941 12:44:08.136647 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
942 12:44:08.143541 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
943 12:44:08.143626 == TX Byte 1 ==
944 12:44:08.147263 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
945 12:44:08.153532 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
946 12:44:08.153617
947 12:44:08.153684 [DATLAT]
948 12:44:08.153746 Freq=800, CH0 RK0
949 12:44:08.153806
950 12:44:08.156564 DATLAT Default: 0xa
951 12:44:08.156647 0, 0xFFFF, sum = 0
952 12:44:08.160108 1, 0xFFFF, sum = 0
953 12:44:08.160194 2, 0xFFFF, sum = 0
954 12:44:08.163620 3, 0xFFFF, sum = 0
955 12:44:08.163706 4, 0xFFFF, sum = 0
956 12:44:08.167014 5, 0xFFFF, sum = 0
957 12:44:08.170340 6, 0xFFFF, sum = 0
958 12:44:08.170425 7, 0xFFFF, sum = 0
959 12:44:08.173293 8, 0xFFFF, sum = 0
960 12:44:08.173379 9, 0x0, sum = 1
961 12:44:08.173448 10, 0x0, sum = 2
962 12:44:08.177050 11, 0x0, sum = 3
963 12:44:08.177136 12, 0x0, sum = 4
964 12:44:08.180443 best_step = 10
965 12:44:08.180527
966 12:44:08.180593 ==
967 12:44:08.183607 Dram Type= 6, Freq= 0, CH_0, rank 0
968 12:44:08.187034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
969 12:44:08.187119 ==
970 12:44:08.189929 RX Vref Scan: 1
971 12:44:08.190012
972 12:44:08.190078 Set Vref Range= 32 -> 127
973 12:44:08.193900
974 12:44:08.193983 RX Vref 32 -> 127, step: 1
975 12:44:08.194050
976 12:44:08.196745 RX Delay -95 -> 252, step: 8
977 12:44:08.196859
978 12:44:08.200052 Set Vref, RX VrefLevel [Byte0]: 32
979 12:44:08.203396 [Byte1]: 32
980 12:44:08.203485
981 12:44:08.206888 Set Vref, RX VrefLevel [Byte0]: 33
982 12:44:08.210396 [Byte1]: 33
983 12:44:08.213997
984 12:44:08.214081 Set Vref, RX VrefLevel [Byte0]: 34
985 12:44:08.217237 [Byte1]: 34
986 12:44:08.221396
987 12:44:08.221484 Set Vref, RX VrefLevel [Byte0]: 35
988 12:44:08.224597 [Byte1]: 35
989 12:44:08.228893
990 12:44:08.228989 Set Vref, RX VrefLevel [Byte0]: 36
991 12:44:08.232245 [Byte1]: 36
992 12:44:08.236626
993 12:44:08.236713 Set Vref, RX VrefLevel [Byte0]: 37
994 12:44:08.240265 [Byte1]: 37
995 12:44:08.244698
996 12:44:08.244786 Set Vref, RX VrefLevel [Byte0]: 38
997 12:44:08.248104 [Byte1]: 38
998 12:44:08.251833
999 12:44:08.251923 Set Vref, RX VrefLevel [Byte0]: 39
1000 12:44:08.258358 [Byte1]: 39
1001 12:44:08.258445
1002 12:44:08.261572 Set Vref, RX VrefLevel [Byte0]: 40
1003 12:44:08.265348 [Byte1]: 40
1004 12:44:08.265436
1005 12:44:08.268772 Set Vref, RX VrefLevel [Byte0]: 41
1006 12:44:08.272578 [Byte1]: 41
1007 12:44:08.272667
1008 12:44:08.275675 Set Vref, RX VrefLevel [Byte0]: 42
1009 12:44:08.279262 [Byte1]: 42
1010 12:44:08.282558
1011 12:44:08.282645 Set Vref, RX VrefLevel [Byte0]: 43
1012 12:44:08.286016 [Byte1]: 43
1013 12:44:08.290149
1014 12:44:08.290236 Set Vref, RX VrefLevel [Byte0]: 44
1015 12:44:08.293320 [Byte1]: 44
1016 12:44:08.298106
1017 12:44:08.298207 Set Vref, RX VrefLevel [Byte0]: 45
1018 12:44:08.300925 [Byte1]: 45
1019 12:44:08.305104
1020 12:44:08.305258 Set Vref, RX VrefLevel [Byte0]: 46
1021 12:44:08.308443 [Byte1]: 46
1022 12:44:08.312421
1023 12:44:08.312509 Set Vref, RX VrefLevel [Byte0]: 47
1024 12:44:08.316218 [Byte1]: 47
1025 12:44:08.320272
1026 12:44:08.320359 Set Vref, RX VrefLevel [Byte0]: 48
1027 12:44:08.323454 [Byte1]: 48
1028 12:44:08.327650
1029 12:44:08.330945 Set Vref, RX VrefLevel [Byte0]: 49
1030 12:44:08.334142 [Byte1]: 49
1031 12:44:08.334217
1032 12:44:08.337438 Set Vref, RX VrefLevel [Byte0]: 50
1033 12:44:08.340831 [Byte1]: 50
1034 12:44:08.340911
1035 12:44:08.344214 Set Vref, RX VrefLevel [Byte0]: 51
1036 12:44:08.347435 [Byte1]: 51
1037 12:44:08.347509
1038 12:44:08.350659 Set Vref, RX VrefLevel [Byte0]: 52
1039 12:44:08.354387 [Byte1]: 52
1040 12:44:08.358111
1041 12:44:08.358193 Set Vref, RX VrefLevel [Byte0]: 53
1042 12:44:08.361609 [Byte1]: 53
1043 12:44:08.365596
1044 12:44:08.365680 Set Vref, RX VrefLevel [Byte0]: 54
1045 12:44:08.369251 [Byte1]: 54
1046 12:44:08.373221
1047 12:44:08.373304 Set Vref, RX VrefLevel [Byte0]: 55
1048 12:44:08.376719 [Byte1]: 55
1049 12:44:08.381221
1050 12:44:08.381296 Set Vref, RX VrefLevel [Byte0]: 56
1051 12:44:08.384169 [Byte1]: 56
1052 12:44:08.388605
1053 12:44:08.391601 Set Vref, RX VrefLevel [Byte0]: 57
1054 12:44:08.395024 [Byte1]: 57
1055 12:44:08.395097
1056 12:44:08.398350 Set Vref, RX VrefLevel [Byte0]: 58
1057 12:44:08.401663 [Byte1]: 58
1058 12:44:08.401758
1059 12:44:08.405182 Set Vref, RX VrefLevel [Byte0]: 59
1060 12:44:08.408580 [Byte1]: 59
1061 12:44:08.408659
1062 12:44:08.411727 Set Vref, RX VrefLevel [Byte0]: 60
1063 12:44:08.414768 [Byte1]: 60
1064 12:44:08.419059
1065 12:44:08.419134 Set Vref, RX VrefLevel [Byte0]: 61
1066 12:44:08.422171 [Byte1]: 61
1067 12:44:08.426614
1068 12:44:08.426691 Set Vref, RX VrefLevel [Byte0]: 62
1069 12:44:08.429890 [Byte1]: 62
1070 12:44:08.433908
1071 12:44:08.433982 Set Vref, RX VrefLevel [Byte0]: 63
1072 12:44:08.437441 [Byte1]: 63
1073 12:44:08.441696
1074 12:44:08.441790 Set Vref, RX VrefLevel [Byte0]: 64
1075 12:44:08.445246 [Byte1]: 64
1076 12:44:08.449554
1077 12:44:08.449673 Set Vref, RX VrefLevel [Byte0]: 65
1078 12:44:08.453008 [Byte1]: 65
1079 12:44:08.457003
1080 12:44:08.457115 Set Vref, RX VrefLevel [Byte0]: 66
1081 12:44:08.460204 [Byte1]: 66
1082 12:44:08.464593
1083 12:44:08.464679 Set Vref, RX VrefLevel [Byte0]: 67
1084 12:44:08.467861 [Byte1]: 67
1085 12:44:08.472027
1086 12:44:08.472101 Set Vref, RX VrefLevel [Byte0]: 68
1087 12:44:08.475450 [Byte1]: 68
1088 12:44:08.479586
1089 12:44:08.479659 Set Vref, RX VrefLevel [Byte0]: 69
1090 12:44:08.483144 [Byte1]: 69
1091 12:44:08.487271
1092 12:44:08.487350 Set Vref, RX VrefLevel [Byte0]: 70
1093 12:44:08.490528 [Byte1]: 70
1094 12:44:08.494945
1095 12:44:08.495028 Set Vref, RX VrefLevel [Byte0]: 71
1096 12:44:08.498289 [Byte1]: 71
1097 12:44:08.502382
1098 12:44:08.502461 Set Vref, RX VrefLevel [Byte0]: 72
1099 12:44:08.506040 [Byte1]: 72
1100 12:44:08.510103
1101 12:44:08.510226 Set Vref, RX VrefLevel [Byte0]: 73
1102 12:44:08.513936 [Byte1]: 73
1103 12:44:08.517778
1104 12:44:08.517861 Set Vref, RX VrefLevel [Byte0]: 74
1105 12:44:08.520788 [Byte1]: 74
1106 12:44:08.525468
1107 12:44:08.525543 Set Vref, RX VrefLevel [Byte0]: 75
1108 12:44:08.528582 [Byte1]: 75
1109 12:44:08.532707
1110 12:44:08.532795 Set Vref, RX VrefLevel [Byte0]: 76
1111 12:44:08.536066 [Byte1]: 76
1112 12:44:08.540990
1113 12:44:08.541078 Set Vref, RX VrefLevel [Byte0]: 77
1114 12:44:08.543977 [Byte1]: 77
1115 12:44:08.548213
1116 12:44:08.548288 Final RX Vref Byte 0 = 61 to rank0
1117 12:44:08.551653 Final RX Vref Byte 1 = 62 to rank0
1118 12:44:08.555064 Final RX Vref Byte 0 = 61 to rank1
1119 12:44:08.558300 Final RX Vref Byte 1 = 62 to rank1==
1120 12:44:08.561526 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 12:44:08.565211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 12:44:08.568350 ==
1123 12:44:08.568429 DQS Delay:
1124 12:44:08.568494 DQS0 = 0, DQS1 = 0
1125 12:44:08.571974 DQM Delay:
1126 12:44:08.572057 DQM0 = 93, DQM1 = 83
1127 12:44:08.574850 DQ Delay:
1128 12:44:08.578165 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1129 12:44:08.578246 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1130 12:44:08.581645 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1131 12:44:08.588031 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1132 12:44:08.588126
1133 12:44:08.588191
1134 12:44:08.595330 [DQSOSCAuto] RK0, (LSB)MR18= 0x3935, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1135 12:44:08.598141 CH0 RK0: MR19=606, MR18=3935
1136 12:44:08.604766 CH0_RK0: MR19=0x606, MR18=0x3935, DQSOSC=395, MR23=63, INC=94, DEC=63
1137 12:44:08.604851
1138 12:44:08.607892 ----->DramcWriteLeveling(PI) begin...
1139 12:44:08.607970 ==
1140 12:44:08.611284 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 12:44:08.614562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 12:44:08.614652 ==
1143 12:44:08.617745 Write leveling (Byte 0): 32 => 32
1144 12:44:08.621313 Write leveling (Byte 1): 32 => 32
1145 12:44:08.624528 DramcWriteLeveling(PI) end<-----
1146 12:44:08.624632
1147 12:44:08.624701 ==
1148 12:44:08.627838 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 12:44:08.631307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 12:44:08.631418 ==
1151 12:44:08.634922 [Gating] SW mode calibration
1152 12:44:08.641228 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 12:44:08.647576 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 12:44:08.651102 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 12:44:08.654574 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 12:44:08.660930 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:44:08.664738 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:44:08.667899 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:44:08.711681 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:44:08.712034 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:44:08.712146 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:44:08.712534 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:44:08.712639 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:44:08.712916 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:44:08.713047 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:44:08.713298 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:44:08.713757 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:44:08.713855 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:44:08.729809 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:44:08.730152 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1171 12:44:08.730414 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1172 12:44:08.733232 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:44:08.736776 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:44:08.740008 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:44:08.743101 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:44:08.749738 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:44:08.753270 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:44:08.756398 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:44:08.760081 0 9 4 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1180 12:44:08.766720 0 9 8 | B1->B0 | 3030 3333 | 1 1 | (0 0) (1 1)
1181 12:44:08.769817 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:44:08.773416 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:44:08.779975 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:44:08.783206 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:44:08.786403 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:44:08.792861 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:44:08.796729 0 10 4 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 1)
1188 12:44:08.799769 0 10 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
1189 12:44:08.806521 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:44:08.809690 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:44:08.813171 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:44:08.820179 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:44:08.823120 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:44:08.826288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:44:08.832806 0 11 4 | B1->B0 | 2727 3838 | 0 0 | (0 0) (0 0)
1196 12:44:08.836424 0 11 8 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
1197 12:44:08.839734 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:44:08.846758 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:44:08.849907 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:44:08.853279 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:44:08.856917 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:44:08.863963 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:44:08.867271 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 12:44:08.870602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1205 12:44:08.877546 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:44:08.881204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:44:08.884387 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:44:08.888115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:44:08.895243 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:44:08.897916 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:44:08.901277 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:44:08.908188 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:44:08.910936 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:44:08.914848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:44:08.921288 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:44:08.924371 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:44:08.927759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:44:08.934699 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:44:08.937907 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1220 12:44:08.941131 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1221 12:44:08.944503 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 12:44:08.947701 Total UI for P1: 0, mck2ui 16
1223 12:44:08.951049 best dqsien dly found for B0: ( 0, 14, 6)
1224 12:44:08.954255 Total UI for P1: 0, mck2ui 16
1225 12:44:08.957843 best dqsien dly found for B1: ( 0, 14, 6)
1226 12:44:08.961316 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1227 12:44:08.967796 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1228 12:44:08.967879
1229 12:44:08.970848 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1230 12:44:08.974203 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 12:44:08.978073 [Gating] SW calibration Done
1232 12:44:08.978157 ==
1233 12:44:08.981157 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 12:44:08.984407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 12:44:08.984491 ==
1236 12:44:08.984558 RX Vref Scan: 0
1237 12:44:08.984618
1238 12:44:08.987543 RX Vref 0 -> 0, step: 1
1239 12:44:08.987626
1240 12:44:08.990882 RX Delay -130 -> 252, step: 16
1241 12:44:08.994332 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1242 12:44:08.997492 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1243 12:44:09.003930 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1244 12:44:09.007506 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1245 12:44:09.010799 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1246 12:44:09.014014 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1247 12:44:09.017346 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1248 12:44:09.024460 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1249 12:44:09.027268 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1250 12:44:09.030704 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1251 12:44:09.033986 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1252 12:44:09.037770 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1253 12:44:09.043821 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1254 12:44:09.047392 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1255 12:44:09.050781 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1256 12:44:09.054095 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1257 12:44:09.054179 ==
1258 12:44:09.057526 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 12:44:09.063887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 12:44:09.063972 ==
1261 12:44:09.064038 DQS Delay:
1262 12:44:09.067254 DQS0 = 0, DQS1 = 0
1263 12:44:09.067338 DQM Delay:
1264 12:44:09.070240 DQM0 = 92, DQM1 = 81
1265 12:44:09.070324 DQ Delay:
1266 12:44:09.073714 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1267 12:44:09.077114 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1268 12:44:09.080322 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =85
1269 12:44:09.083761 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =85
1270 12:44:09.083844
1271 12:44:09.083909
1272 12:44:09.083970 ==
1273 12:44:09.087080 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 12:44:09.090567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 12:44:09.090651 ==
1276 12:44:09.090717
1277 12:44:09.090777
1278 12:44:09.093666 TX Vref Scan disable
1279 12:44:09.097189 == TX Byte 0 ==
1280 12:44:09.100145 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1281 12:44:09.103787 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1282 12:44:09.107527 == TX Byte 1 ==
1283 12:44:09.110271 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1284 12:44:09.113775 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1285 12:44:09.113858 ==
1286 12:44:09.116808 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:44:09.120175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:44:09.123430 ==
1289 12:44:09.134719 TX Vref=22, minBit 3, minWin=27, winSum=445
1290 12:44:09.138199 TX Vref=24, minBit 3, minWin=27, winSum=448
1291 12:44:09.141348 TX Vref=26, minBit 8, minWin=27, winSum=453
1292 12:44:09.145012 TX Vref=28, minBit 8, minWin=28, winSum=456
1293 12:44:09.147967 TX Vref=30, minBit 8, minWin=27, winSum=456
1294 12:44:09.154748 TX Vref=32, minBit 9, minWin=27, winSum=455
1295 12:44:09.158086 [TxChooseVref] Worse bit 8, Min win 28, Win sum 456, Final Vref 28
1296 12:44:09.158170
1297 12:44:09.161246 Final TX Range 1 Vref 28
1298 12:44:09.161330
1299 12:44:09.161395 ==
1300 12:44:09.164695 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 12:44:09.168140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 12:44:09.168223 ==
1303 12:44:09.171049
1304 12:44:09.171130
1305 12:44:09.171194 TX Vref Scan disable
1306 12:44:09.174893 == TX Byte 0 ==
1307 12:44:09.177886 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1308 12:44:09.184659 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1309 12:44:09.184741 == TX Byte 1 ==
1310 12:44:09.187992 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1311 12:44:09.194947 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1312 12:44:09.195029
1313 12:44:09.195093 [DATLAT]
1314 12:44:09.195154 Freq=800, CH0 RK1
1315 12:44:09.195212
1316 12:44:09.197753 DATLAT Default: 0xa
1317 12:44:09.197834 0, 0xFFFF, sum = 0
1318 12:44:09.201034 1, 0xFFFF, sum = 0
1319 12:44:09.201144 2, 0xFFFF, sum = 0
1320 12:44:09.204642 3, 0xFFFF, sum = 0
1321 12:44:09.207931 4, 0xFFFF, sum = 0
1322 12:44:09.208014 5, 0xFFFF, sum = 0
1323 12:44:09.211334 6, 0xFFFF, sum = 0
1324 12:44:09.211416 7, 0xFFFF, sum = 0
1325 12:44:09.214912 8, 0xFFFF, sum = 0
1326 12:44:09.214994 9, 0x0, sum = 1
1327 12:44:09.215060 10, 0x0, sum = 2
1328 12:44:09.218040 11, 0x0, sum = 3
1329 12:44:09.218122 12, 0x0, sum = 4
1330 12:44:09.221304 best_step = 10
1331 12:44:09.221386
1332 12:44:09.221452 ==
1333 12:44:09.224556 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 12:44:09.228113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 12:44:09.228196 ==
1336 12:44:09.231183 RX Vref Scan: 0
1337 12:44:09.231264
1338 12:44:09.231330 RX Vref 0 -> 0, step: 1
1339 12:44:09.231390
1340 12:44:09.234299 RX Delay -79 -> 252, step: 8
1341 12:44:09.241472 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1342 12:44:09.244636 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1343 12:44:09.248261 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 12:44:09.251496 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1345 12:44:09.255039 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1346 12:44:09.261157 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1347 12:44:09.264678 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 12:44:09.267941 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 12:44:09.271483 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1350 12:44:09.274740 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1351 12:44:09.281519 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1352 12:44:09.284699 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1353 12:44:09.288137 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1354 12:44:09.291501 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1355 12:44:09.294807 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 12:44:09.301174 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1357 12:44:09.301259 ==
1358 12:44:09.304515 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 12:44:09.307838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 12:44:09.307921 ==
1361 12:44:09.307986 DQS Delay:
1362 12:44:09.311363 DQS0 = 0, DQS1 = 0
1363 12:44:09.311445 DQM Delay:
1364 12:44:09.314731 DQM0 = 91, DQM1 = 81
1365 12:44:09.314813 DQ Delay:
1366 12:44:09.318164 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1367 12:44:09.321419 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1368 12:44:09.324876 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1369 12:44:09.328029 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1370 12:44:09.328110
1371 12:44:09.328176
1372 12:44:09.338029 [DQSOSCAuto] RK1, (LSB)MR18= 0x421c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1373 12:44:09.338112 CH0 RK1: MR19=606, MR18=421C
1374 12:44:09.344498 CH0_RK1: MR19=0x606, MR18=0x421C, DQSOSC=393, MR23=63, INC=95, DEC=63
1375 12:44:09.347658 [RxdqsGatingPostProcess] freq 800
1376 12:44:09.354391 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 12:44:09.357654 Pre-setting of DQS Precalculation
1378 12:44:09.360967 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 12:44:09.361092 ==
1380 12:44:09.364558 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 12:44:09.367615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 12:44:09.371103 ==
1383 12:44:09.374153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 12:44:09.380932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 12:44:09.389878 [CA 0] Center 36 (6~67) winsize 62
1386 12:44:09.393009 [CA 1] Center 36 (6~67) winsize 62
1387 12:44:09.396218 [CA 2] Center 35 (5~65) winsize 61
1388 12:44:09.399865 [CA 3] Center 34 (4~65) winsize 62
1389 12:44:09.403125 [CA 4] Center 34 (4~65) winsize 62
1390 12:44:09.406207 [CA 5] Center 34 (4~65) winsize 62
1391 12:44:09.406292
1392 12:44:09.409481 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1393 12:44:09.409565
1394 12:44:09.412729 [CATrainingPosCal] consider 1 rank data
1395 12:44:09.416555 u2DelayCellTimex100 = 270/100 ps
1396 12:44:09.419986 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 12:44:09.426208 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 12:44:09.429782 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 12:44:09.433064 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 12:44:09.436275 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 12:44:09.439527 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 12:44:09.439611
1403 12:44:09.442691 CA PerBit enable=1, Macro0, CA PI delay=34
1404 12:44:09.442775
1405 12:44:09.446163 [CBTSetCACLKResult] CA Dly = 34
1406 12:44:09.446247 CS Dly: 5 (0~36)
1407 12:44:09.449820 ==
1408 12:44:09.453241 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 12:44:09.456121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 12:44:09.456206 ==
1411 12:44:09.459499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 12:44:09.465990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 12:44:09.476129 [CA 0] Center 37 (7~67) winsize 61
1414 12:44:09.479419 [CA 1] Center 37 (6~68) winsize 63
1415 12:44:09.482497 [CA 2] Center 35 (5~66) winsize 62
1416 12:44:09.485699 [CA 3] Center 34 (4~65) winsize 62
1417 12:44:09.489282 [CA 4] Center 35 (5~65) winsize 61
1418 12:44:09.492415 [CA 5] Center 34 (4~64) winsize 61
1419 12:44:09.492500
1420 12:44:09.495696 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1421 12:44:09.495780
1422 12:44:09.499225 [CATrainingPosCal] consider 2 rank data
1423 12:44:09.502413 u2DelayCellTimex100 = 270/100 ps
1424 12:44:09.505737 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1425 12:44:09.508962 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 12:44:09.515989 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 12:44:09.519510 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 12:44:09.523571 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1429 12:44:09.527022 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 12:44:09.527106
1431 12:44:09.530663 CA PerBit enable=1, Macro0, CA PI delay=34
1432 12:44:09.530747
1433 12:44:09.530813 [CBTSetCACLKResult] CA Dly = 34
1434 12:44:09.535402 CS Dly: 6 (0~38)
1435 12:44:09.535486
1436 12:44:09.538584 ----->DramcWriteLeveling(PI) begin...
1437 12:44:09.538669 ==
1438 12:44:09.541791 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 12:44:09.545399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 12:44:09.545483 ==
1441 12:44:09.549133 Write leveling (Byte 0): 26 => 26
1442 12:44:09.552748 Write leveling (Byte 1): 30 => 30
1443 12:44:09.555660 DramcWriteLeveling(PI) end<-----
1444 12:44:09.555744
1445 12:44:09.555811 ==
1446 12:44:09.559254 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 12:44:09.562741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 12:44:09.562824 ==
1449 12:44:09.565745 [Gating] SW mode calibration
1450 12:44:09.572225 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 12:44:09.575705 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 12:44:09.582358 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 12:44:09.585751 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1454 12:44:09.589474 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1455 12:44:09.595829 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:44:09.598966 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:44:09.602489 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:44:09.609070 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:44:09.612140 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:44:09.615815 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:44:09.622602 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:44:09.625797 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:44:09.629115 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:44:09.635434 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:44:09.639123 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:44:09.642293 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:44:09.648915 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:44:09.652122 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1469 12:44:09.655865 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1470 12:44:09.662202 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:44:09.665458 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:44:09.668735 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:44:09.675318 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:44:09.678386 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:44:09.681954 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:44:09.688590 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:44:09.692076 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1478 12:44:09.695789 0 9 8 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
1479 12:44:09.701583 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:44:09.704915 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:44:09.708655 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:44:09.715012 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:44:09.718258 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:44:09.721685 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1485 12:44:09.725305 0 10 4 | B1->B0 | 2f2f 2c2c | 0 0 | (1 0) (0 0)
1486 12:44:09.732004 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:44:09.735254 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:44:09.738257 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:44:09.745404 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:44:09.748392 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:44:09.751647 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:44:09.758404 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:44:09.761870 0 11 4 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
1494 12:44:09.764964 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1495 12:44:09.771632 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:44:09.775242 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:44:09.778253 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:44:09.784726 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:44:09.787917 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:44:09.791200 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:44:09.798129 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 12:44:09.801514 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:44:09.804608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:44:09.811659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:44:09.814609 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:44:09.817711 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:44:09.824720 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:44:09.827966 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:44:09.831121 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:44:09.838031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:44:09.841134 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:44:09.844329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:44:09.851057 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:44:09.854609 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:44:09.857430 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:44:09.864321 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:44:09.867451 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 12:44:09.870799 Total UI for P1: 0, mck2ui 16
1519 12:44:09.874679 best dqsien dly found for B0: ( 0, 14, 2)
1520 12:44:09.877792 Total UI for P1: 0, mck2ui 16
1521 12:44:09.881026 best dqsien dly found for B1: ( 0, 14, 2)
1522 12:44:09.884027 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1523 12:44:09.887282 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1524 12:44:09.887359
1525 12:44:09.891061 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1526 12:44:09.894003 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1527 12:44:09.897667 [Gating] SW calibration Done
1528 12:44:09.897742 ==
1529 12:44:09.901379 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 12:44:09.904496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 12:44:09.904596 ==
1532 12:44:09.907338 RX Vref Scan: 0
1533 12:44:09.907412
1534 12:44:09.910776 RX Vref 0 -> 0, step: 1
1535 12:44:09.910880
1536 12:44:09.910975 RX Delay -130 -> 252, step: 16
1537 12:44:09.917554 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1538 12:44:09.920433 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1539 12:44:09.924326 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1540 12:44:09.927121 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1541 12:44:09.930490 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1542 12:44:09.937212 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1543 12:44:09.940540 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1544 12:44:09.943874 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1545 12:44:09.947449 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1546 12:44:09.951171 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1547 12:44:09.957156 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1548 12:44:09.960653 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1549 12:44:09.963807 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1550 12:44:09.967133 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1551 12:44:09.973739 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1552 12:44:09.977561 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1553 12:44:09.977662 ==
1554 12:44:09.981063 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 12:44:09.983842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 12:44:09.983943 ==
1557 12:44:09.984034 DQS Delay:
1558 12:44:09.986854 DQS0 = 0, DQS1 = 0
1559 12:44:09.986924 DQM Delay:
1560 12:44:09.990581 DQM0 = 94, DQM1 = 81
1561 12:44:09.990679 DQ Delay:
1562 12:44:09.993436 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1563 12:44:09.996845 DQ4 =93, DQ5 =101, DQ6 =109, DQ7 =93
1564 12:44:10.000490 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1565 12:44:10.003698 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1566 12:44:10.003796
1567 12:44:10.003886
1568 12:44:10.003976 ==
1569 12:44:10.007012 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 12:44:10.013688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 12:44:10.013764 ==
1572 12:44:10.013827
1573 12:44:10.013886
1574 12:44:10.013943 TX Vref Scan disable
1575 12:44:10.016856 == TX Byte 0 ==
1576 12:44:10.020536 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1577 12:44:10.024210 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1578 12:44:10.026947 == TX Byte 1 ==
1579 12:44:10.030269 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 12:44:10.037011 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 12:44:10.037107 ==
1582 12:44:10.040445 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 12:44:10.043332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 12:44:10.043409 ==
1585 12:44:10.056436 TX Vref=22, minBit 8, minWin=27, winSum=447
1586 12:44:10.060122 TX Vref=24, minBit 15, minWin=26, winSum=447
1587 12:44:10.062996 TX Vref=26, minBit 8, minWin=27, winSum=452
1588 12:44:10.066608 TX Vref=28, minBit 15, minWin=27, winSum=458
1589 12:44:10.069473 TX Vref=30, minBit 9, minWin=27, winSum=457
1590 12:44:10.076255 TX Vref=32, minBit 8, minWin=27, winSum=457
1591 12:44:10.079838 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 28
1592 12:44:10.079911
1593 12:44:10.082937 Final TX Range 1 Vref 28
1594 12:44:10.083009
1595 12:44:10.083070 ==
1596 12:44:10.086557 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 12:44:10.089571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 12:44:10.093086 ==
1599 12:44:10.093164
1600 12:44:10.093226
1601 12:44:10.093284 TX Vref Scan disable
1602 12:44:10.096955 == TX Byte 0 ==
1603 12:44:10.100724 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 12:44:10.103957 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 12:44:10.107420 == TX Byte 1 ==
1606 12:44:10.110484 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1607 12:44:10.113947 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1608 12:44:10.114018
1609 12:44:10.116896 [DATLAT]
1610 12:44:10.117033 Freq=800, CH1 RK0
1611 12:44:10.117100
1612 12:44:10.120407 DATLAT Default: 0xa
1613 12:44:10.120508 0, 0xFFFF, sum = 0
1614 12:44:10.123872 1, 0xFFFF, sum = 0
1615 12:44:10.123979 2, 0xFFFF, sum = 0
1616 12:44:10.126937 3, 0xFFFF, sum = 0
1617 12:44:10.127037 4, 0xFFFF, sum = 0
1618 12:44:10.130529 5, 0xFFFF, sum = 0
1619 12:44:10.130630 6, 0xFFFF, sum = 0
1620 12:44:10.133884 7, 0xFFFF, sum = 0
1621 12:44:10.133988 8, 0x0, sum = 1
1622 12:44:10.137247 9, 0x0, sum = 2
1623 12:44:10.137319 10, 0x0, sum = 3
1624 12:44:10.140702 11, 0x0, sum = 4
1625 12:44:10.140801 best_step = 9
1626 12:44:10.140890
1627 12:44:10.140986 ==
1628 12:44:10.143862 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 12:44:10.147061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 12:44:10.150579 ==
1631 12:44:10.150652 RX Vref Scan: 1
1632 12:44:10.150714
1633 12:44:10.153722 Set Vref Range= 32 -> 127
1634 12:44:10.153796
1635 12:44:10.153865 RX Vref 32 -> 127, step: 1
1636 12:44:10.157255
1637 12:44:10.157341 RX Delay -95 -> 252, step: 8
1638 12:44:10.157408
1639 12:44:10.160466 Set Vref, RX VrefLevel [Byte0]: 32
1640 12:44:10.163504 [Byte1]: 32
1641 12:44:10.167106
1642 12:44:10.167182 Set Vref, RX VrefLevel [Byte0]: 33
1643 12:44:10.170614 [Byte1]: 33
1644 12:44:10.174951
1645 12:44:10.175028 Set Vref, RX VrefLevel [Byte0]: 34
1646 12:44:10.178208 [Byte1]: 34
1647 12:44:10.182367
1648 12:44:10.182442 Set Vref, RX VrefLevel [Byte0]: 35
1649 12:44:10.185660 [Byte1]: 35
1650 12:44:10.190134
1651 12:44:10.190206 Set Vref, RX VrefLevel [Byte0]: 36
1652 12:44:10.193364 [Byte1]: 36
1653 12:44:10.197715
1654 12:44:10.197789 Set Vref, RX VrefLevel [Byte0]: 37
1655 12:44:10.201096 [Byte1]: 37
1656 12:44:10.205332
1657 12:44:10.205408 Set Vref, RX VrefLevel [Byte0]: 38
1658 12:44:10.208552 [Byte1]: 38
1659 12:44:10.212906
1660 12:44:10.212982 Set Vref, RX VrefLevel [Byte0]: 39
1661 12:44:10.215963 [Byte1]: 39
1662 12:44:10.220374
1663 12:44:10.220448 Set Vref, RX VrefLevel [Byte0]: 40
1664 12:44:10.224194 [Byte1]: 40
1665 12:44:10.228186
1666 12:44:10.228261 Set Vref, RX VrefLevel [Byte0]: 41
1667 12:44:10.231306 [Byte1]: 41
1668 12:44:10.235885
1669 12:44:10.235957 Set Vref, RX VrefLevel [Byte0]: 42
1670 12:44:10.238860 [Byte1]: 42
1671 12:44:10.243456
1672 12:44:10.243538 Set Vref, RX VrefLevel [Byte0]: 43
1673 12:44:10.246615 [Byte1]: 43
1674 12:44:10.251048
1675 12:44:10.251157 Set Vref, RX VrefLevel [Byte0]: 44
1676 12:44:10.254240 [Byte1]: 44
1677 12:44:10.259030
1678 12:44:10.259111 Set Vref, RX VrefLevel [Byte0]: 45
1679 12:44:10.262096 [Byte1]: 45
1680 12:44:10.266141
1681 12:44:10.266215 Set Vref, RX VrefLevel [Byte0]: 46
1682 12:44:10.269205 [Byte1]: 46
1683 12:44:10.273720
1684 12:44:10.273794 Set Vref, RX VrefLevel [Byte0]: 47
1685 12:44:10.277030 [Byte1]: 47
1686 12:44:10.281110
1687 12:44:10.281183 Set Vref, RX VrefLevel [Byte0]: 48
1688 12:44:10.284477 [Byte1]: 48
1689 12:44:10.288907
1690 12:44:10.288982 Set Vref, RX VrefLevel [Byte0]: 49
1691 12:44:10.292519 [Byte1]: 49
1692 12:44:10.296755
1693 12:44:10.296838 Set Vref, RX VrefLevel [Byte0]: 50
1694 12:44:10.299657 [Byte1]: 50
1695 12:44:10.305383
1696 12:44:10.305466 Set Vref, RX VrefLevel [Byte0]: 51
1697 12:44:10.307394 [Byte1]: 51
1698 12:44:10.311844
1699 12:44:10.311927 Set Vref, RX VrefLevel [Byte0]: 52
1700 12:44:10.314745 [Byte1]: 52
1701 12:44:10.319167
1702 12:44:10.319240 Set Vref, RX VrefLevel [Byte0]: 53
1703 12:44:10.322939 [Byte1]: 53
1704 12:44:10.326943
1705 12:44:10.327025 Set Vref, RX VrefLevel [Byte0]: 54
1706 12:44:10.330085 [Byte1]: 54
1707 12:44:10.334441
1708 12:44:10.334524 Set Vref, RX VrefLevel [Byte0]: 55
1709 12:44:10.337819 [Byte1]: 55
1710 12:44:10.342404
1711 12:44:10.342486 Set Vref, RX VrefLevel [Byte0]: 56
1712 12:44:10.345748 [Byte1]: 56
1713 12:44:10.349987
1714 12:44:10.350070 Set Vref, RX VrefLevel [Byte0]: 57
1715 12:44:10.353095 [Byte1]: 57
1716 12:44:10.357289
1717 12:44:10.357402 Set Vref, RX VrefLevel [Byte0]: 58
1718 12:44:10.360695 [Byte1]: 58
1719 12:44:10.364654
1720 12:44:10.364766 Set Vref, RX VrefLevel [Byte0]: 59
1721 12:44:10.367924 [Byte1]: 59
1722 12:44:10.372798
1723 12:44:10.372908 Set Vref, RX VrefLevel [Byte0]: 60
1724 12:44:10.375674 [Byte1]: 60
1725 12:44:10.379831
1726 12:44:10.379913 Set Vref, RX VrefLevel [Byte0]: 61
1727 12:44:10.383682 [Byte1]: 61
1728 12:44:10.387910
1729 12:44:10.387987 Set Vref, RX VrefLevel [Byte0]: 62
1730 12:44:10.390730 [Byte1]: 62
1731 12:44:10.395145
1732 12:44:10.395227 Set Vref, RX VrefLevel [Byte0]: 63
1733 12:44:10.398633 [Byte1]: 63
1734 12:44:10.403206
1735 12:44:10.403289 Set Vref, RX VrefLevel [Byte0]: 64
1736 12:44:10.405977 [Byte1]: 64
1737 12:44:10.410754
1738 12:44:10.410842 Set Vref, RX VrefLevel [Byte0]: 65
1739 12:44:10.413627 [Byte1]: 65
1740 12:44:10.417819
1741 12:44:10.421196 Set Vref, RX VrefLevel [Byte0]: 66
1742 12:44:10.424463 [Byte1]: 66
1743 12:44:10.424546
1744 12:44:10.428016 Set Vref, RX VrefLevel [Byte0]: 67
1745 12:44:10.431228 [Byte1]: 67
1746 12:44:10.431332
1747 12:44:10.434704 Set Vref, RX VrefLevel [Byte0]: 68
1748 12:44:10.437897 [Byte1]: 68
1749 12:44:10.437980
1750 12:44:10.441265 Set Vref, RX VrefLevel [Byte0]: 69
1751 12:44:10.444266 [Byte1]: 69
1752 12:44:10.448491
1753 12:44:10.448574 Set Vref, RX VrefLevel [Byte0]: 70
1754 12:44:10.451912 [Byte1]: 70
1755 12:44:10.456026
1756 12:44:10.456135 Set Vref, RX VrefLevel [Byte0]: 71
1757 12:44:10.459301 [Byte1]: 71
1758 12:44:10.463431
1759 12:44:10.463504 Set Vref, RX VrefLevel [Byte0]: 72
1760 12:44:10.466934 [Byte1]: 72
1761 12:44:10.471063
1762 12:44:10.471148 Set Vref, RX VrefLevel [Byte0]: 73
1763 12:44:10.474678 [Byte1]: 73
1764 12:44:10.478867
1765 12:44:10.478969 Set Vref, RX VrefLevel [Byte0]: 74
1766 12:44:10.481963 [Byte1]: 74
1767 12:44:10.486774
1768 12:44:10.486875 Set Vref, RX VrefLevel [Byte0]: 75
1769 12:44:10.490506 [Byte1]: 75
1770 12:44:10.494255
1771 12:44:10.494364 Set Vref, RX VrefLevel [Byte0]: 76
1772 12:44:10.497268 [Byte1]: 76
1773 12:44:10.501583
1774 12:44:10.501672 Final RX Vref Byte 0 = 50 to rank0
1775 12:44:10.504840 Final RX Vref Byte 1 = 63 to rank0
1776 12:44:10.508354 Final RX Vref Byte 0 = 50 to rank1
1777 12:44:10.511618 Final RX Vref Byte 1 = 63 to rank1==
1778 12:44:10.514696 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 12:44:10.521394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 12:44:10.521477 ==
1781 12:44:10.521544 DQS Delay:
1782 12:44:10.521607 DQS0 = 0, DQS1 = 0
1783 12:44:10.524889 DQM Delay:
1784 12:44:10.524971 DQM0 = 92, DQM1 = 83
1785 12:44:10.528437 DQ Delay:
1786 12:44:10.531348 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1787 12:44:10.534754 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1788 12:44:10.538230 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1789 12:44:10.541501 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1790 12:44:10.541603
1791 12:44:10.541695
1792 12:44:10.548229 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1793 12:44:10.551470 CH1 RK0: MR19=606, MR18=2F4B
1794 12:44:10.558360 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1795 12:44:10.558443
1796 12:44:10.561583 ----->DramcWriteLeveling(PI) begin...
1797 12:44:10.561668 ==
1798 12:44:10.564963 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 12:44:10.568329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 12:44:10.568441 ==
1801 12:44:10.571310 Write leveling (Byte 0): 30 => 30
1802 12:44:10.574720 Write leveling (Byte 1): 30 => 30
1803 12:44:10.578080 DramcWriteLeveling(PI) end<-----
1804 12:44:10.578194
1805 12:44:10.578293 ==
1806 12:44:10.581651 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 12:44:10.585215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 12:44:10.585298 ==
1809 12:44:10.587907 [Gating] SW mode calibration
1810 12:44:10.594865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 12:44:10.601094 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 12:44:10.604752 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1813 12:44:10.607971 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1814 12:44:10.614955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:44:10.617885 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:44:10.621173 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:44:10.628090 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:44:10.631112 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:44:10.634693 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:44:10.641268 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:44:10.644628 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:44:10.647751 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:44:10.654501 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:44:10.658283 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:44:10.661530 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:44:10.667492 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:44:10.670861 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:44:10.674322 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:44:10.680792 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1830 12:44:10.684467 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:44:10.687448 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:44:10.693962 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:44:10.697717 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:44:10.701387 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:44:10.707320 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:44:10.710762 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:44:10.714040 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 12:44:10.720760 0 9 8 | B1->B0 | 3434 3333 | 0 1 | (0 0) (0 0)
1839 12:44:10.724134 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 12:44:10.727287 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 12:44:10.734493 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 12:44:10.737105 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 12:44:10.740794 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 12:44:10.747506 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 12:44:10.750414 0 10 4 | B1->B0 | 2e2e 2f2f | 0 0 | (1 1) (0 0)
1846 12:44:10.753630 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1847 12:44:10.760623 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:44:10.763619 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:44:10.767142 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:44:10.770367 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:44:10.776944 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:44:10.780649 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:44:10.784048 0 11 4 | B1->B0 | 2d2d 2929 | 1 0 | (0 0) (0 0)
1854 12:44:10.790630 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1855 12:44:10.793674 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 12:44:10.797121 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 12:44:10.803616 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 12:44:10.807320 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 12:44:10.810589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 12:44:10.817277 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 12:44:10.820724 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1862 12:44:10.823736 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1863 12:44:10.830297 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:44:10.833987 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:44:10.836880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:44:10.843426 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:44:10.847162 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:44:10.850166 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:44:10.856877 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:44:10.860141 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:44:10.863646 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:44:10.870153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:44:10.873622 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:44:10.876597 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:44:10.883335 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:44:10.886926 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:44:10.890211 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1878 12:44:10.896666 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1879 12:44:10.896749 Total UI for P1: 0, mck2ui 16
1880 12:44:10.900421 best dqsien dly found for B1: ( 0, 14, 4)
1881 12:44:10.906681 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 12:44:10.909815 Total UI for P1: 0, mck2ui 16
1883 12:44:10.913256 best dqsien dly found for B0: ( 0, 14, 8)
1884 12:44:10.916469 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1885 12:44:10.920216 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1886 12:44:10.920298
1887 12:44:10.923650 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1888 12:44:10.926540 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 12:44:10.930296 [Gating] SW calibration Done
1890 12:44:10.930377 ==
1891 12:44:10.933187 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 12:44:10.936375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 12:44:10.936458 ==
1894 12:44:10.939850 RX Vref Scan: 0
1895 12:44:10.939933
1896 12:44:10.943217 RX Vref 0 -> 0, step: 1
1897 12:44:10.943299
1898 12:44:10.943364 RX Delay -130 -> 252, step: 16
1899 12:44:10.949726 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1900 12:44:10.952957 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1901 12:44:10.956734 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1902 12:44:10.959713 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1903 12:44:10.963263 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1904 12:44:10.969655 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1905 12:44:10.972943 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1906 12:44:10.976296 iDelay=222, Bit 7, Center 85 (-18 ~ 189) 208
1907 12:44:10.979984 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1908 12:44:10.983224 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1909 12:44:10.989423 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1910 12:44:10.992810 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1911 12:44:10.996140 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1912 12:44:10.999559 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1913 12:44:11.002739 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1914 12:44:11.009317 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1915 12:44:11.009400 ==
1916 12:44:11.012683 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 12:44:11.015865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 12:44:11.015947 ==
1919 12:44:11.016013 DQS Delay:
1920 12:44:11.019152 DQS0 = 0, DQS1 = 0
1921 12:44:11.019234 DQM Delay:
1922 12:44:11.022751 DQM0 = 90, DQM1 = 83
1923 12:44:11.022834 DQ Delay:
1924 12:44:11.026064 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1925 12:44:11.029676 DQ4 =85, DQ5 =109, DQ6 =93, DQ7 =85
1926 12:44:11.032838 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1927 12:44:11.035922 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1928 12:44:11.036004
1929 12:44:11.036069
1930 12:44:11.036129 ==
1931 12:44:11.039229 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 12:44:11.042660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 12:44:11.045902 ==
1934 12:44:11.045984
1935 12:44:11.046049
1936 12:44:11.046108 TX Vref Scan disable
1937 12:44:11.049326 == TX Byte 0 ==
1938 12:44:11.052382 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1939 12:44:11.055846 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1940 12:44:11.059089 == TX Byte 1 ==
1941 12:44:11.062648 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 12:44:11.065995 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 12:44:11.069254 ==
1944 12:44:11.069336 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 12:44:11.075772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 12:44:11.075854 ==
1947 12:44:11.087985 TX Vref=22, minBit 8, minWin=27, winSum=450
1948 12:44:11.091542 TX Vref=24, minBit 8, minWin=27, winSum=454
1949 12:44:11.095395 TX Vref=26, minBit 13, minWin=27, winSum=456
1950 12:44:11.098347 TX Vref=28, minBit 9, minWin=27, winSum=458
1951 12:44:11.101547 TX Vref=30, minBit 8, minWin=28, winSum=460
1952 12:44:11.108119 TX Vref=32, minBit 8, minWin=28, winSum=460
1953 12:44:11.111397 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1954 12:44:11.111480
1955 12:44:11.114605 Final TX Range 1 Vref 30
1956 12:44:11.114688
1957 12:44:11.114753 ==
1958 12:44:11.117781 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 12:44:11.121251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 12:44:11.121333 ==
1961 12:44:11.124792
1962 12:44:11.124874
1963 12:44:11.124939 TX Vref Scan disable
1964 12:44:11.127999 == TX Byte 0 ==
1965 12:44:11.131455 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1966 12:44:11.137877 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1967 12:44:11.137960 == TX Byte 1 ==
1968 12:44:11.141391 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1969 12:44:11.147689 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1970 12:44:11.147771
1971 12:44:11.147836 [DATLAT]
1972 12:44:11.147897 Freq=800, CH1 RK1
1973 12:44:11.147955
1974 12:44:11.151151 DATLAT Default: 0x9
1975 12:44:11.151233 0, 0xFFFF, sum = 0
1976 12:44:11.154405 1, 0xFFFF, sum = 0
1977 12:44:11.157817 2, 0xFFFF, sum = 0
1978 12:44:11.157900 3, 0xFFFF, sum = 0
1979 12:44:11.161091 4, 0xFFFF, sum = 0
1980 12:44:11.161175 5, 0xFFFF, sum = 0
1981 12:44:11.164367 6, 0xFFFF, sum = 0
1982 12:44:11.164449 7, 0xFFFF, sum = 0
1983 12:44:11.168152 8, 0xFFFF, sum = 0
1984 12:44:11.168255 9, 0x0, sum = 1
1985 12:44:11.171114 10, 0x0, sum = 2
1986 12:44:11.171197 11, 0x0, sum = 3
1987 12:44:11.171264 12, 0x0, sum = 4
1988 12:44:11.174422 best_step = 10
1989 12:44:11.174504
1990 12:44:11.174568 ==
1991 12:44:11.177933 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 12:44:11.181465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 12:44:11.181548 ==
1994 12:44:11.184778 RX Vref Scan: 0
1995 12:44:11.184860
1996 12:44:11.184925 RX Vref 0 -> 0, step: 1
1997 12:44:11.184992
1998 12:44:11.187803 RX Delay -95 -> 252, step: 8
1999 12:44:11.194822 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
2000 12:44:11.198021 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2001 12:44:11.201422 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2002 12:44:11.205104 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2003 12:44:11.207902 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2004 12:44:11.214761 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2005 12:44:11.218387 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2006 12:44:11.221165 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2007 12:44:11.224406 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2008 12:44:11.227821 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2009 12:44:11.234461 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2010 12:44:11.237731 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2011 12:44:11.241445 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2012 12:44:11.244476 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2013 12:44:11.247729 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2014 12:44:11.254288 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2015 12:44:11.254371 ==
2016 12:44:11.257738 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 12:44:11.261545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 12:44:11.261627 ==
2019 12:44:11.261692 DQS Delay:
2020 12:44:11.264563 DQS0 = 0, DQS1 = 0
2021 12:44:11.264644 DQM Delay:
2022 12:44:11.267767 DQM0 = 91, DQM1 = 84
2023 12:44:11.267849 DQ Delay:
2024 12:44:11.271000 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2025 12:44:11.274303 DQ4 =96, DQ5 =104, DQ6 =96, DQ7 =88
2026 12:44:11.277568 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2027 12:44:11.280888 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2028 12:44:11.281001
2029 12:44:11.281068
2030 12:44:11.287710 [DQSOSCAuto] RK1, (LSB)MR18= 0x370d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2031 12:44:11.291115 CH1 RK1: MR19=606, MR18=370D
2032 12:44:11.297663 CH1_RK1: MR19=0x606, MR18=0x370D, DQSOSC=395, MR23=63, INC=94, DEC=63
2033 12:44:11.300878 [RxdqsGatingPostProcess] freq 800
2034 12:44:11.307749 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 12:44:11.311105 Pre-setting of DQS Precalculation
2036 12:44:11.314394 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
2037 12:44:11.320875 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 12:44:11.327680 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 12:44:11.327762
2040 12:44:11.327826
2041 12:44:11.331124 [Calibration Summary] 1600 Mbps
2042 12:44:11.334252 CH 0, Rank 0
2043 12:44:11.334332 SW Impedance : PASS
2044 12:44:11.337790 DUTY Scan : NO K
2045 12:44:11.340738 ZQ Calibration : PASS
2046 12:44:11.340819 Jitter Meter : NO K
2047 12:44:11.344109 CBT Training : PASS
2048 12:44:11.347505 Write leveling : PASS
2049 12:44:11.347586 RX DQS gating : PASS
2050 12:44:11.350695 RX DQ/DQS(RDDQC) : PASS
2051 12:44:11.353892 TX DQ/DQS : PASS
2052 12:44:11.353974 RX DATLAT : PASS
2053 12:44:11.356967 RX DQ/DQS(Engine): PASS
2054 12:44:11.360413 TX OE : NO K
2055 12:44:11.360493 All Pass.
2056 12:44:11.360558
2057 12:44:11.360616 CH 0, Rank 1
2058 12:44:11.363882 SW Impedance : PASS
2059 12:44:11.367219 DUTY Scan : NO K
2060 12:44:11.367299 ZQ Calibration : PASS
2061 12:44:11.370649 Jitter Meter : NO K
2062 12:44:11.370729 CBT Training : PASS
2063 12:44:11.373777 Write leveling : PASS
2064 12:44:11.377499 RX DQS gating : PASS
2065 12:44:11.377580 RX DQ/DQS(RDDQC) : PASS
2066 12:44:11.380463 TX DQ/DQS : PASS
2067 12:44:11.383818 RX DATLAT : PASS
2068 12:44:11.383898 RX DQ/DQS(Engine): PASS
2069 12:44:11.387349 TX OE : NO K
2070 12:44:11.387444 All Pass.
2071 12:44:11.387509
2072 12:44:11.390351 CH 1, Rank 0
2073 12:44:11.390433 SW Impedance : PASS
2074 12:44:11.393636 DUTY Scan : NO K
2075 12:44:11.397202 ZQ Calibration : PASS
2076 12:44:11.397284 Jitter Meter : NO K
2077 12:44:11.400250 CBT Training : PASS
2078 12:44:11.403793 Write leveling : PASS
2079 12:44:11.403876 RX DQS gating : PASS
2080 12:44:11.407450 RX DQ/DQS(RDDQC) : PASS
2081 12:44:11.410220 TX DQ/DQS : PASS
2082 12:44:11.410303 RX DATLAT : PASS
2083 12:44:11.413748 RX DQ/DQS(Engine): PASS
2084 12:44:11.413830 TX OE : NO K
2085 12:44:11.416879 All Pass.
2086 12:44:11.417008
2087 12:44:11.417090 CH 1, Rank 1
2088 12:44:11.420635 SW Impedance : PASS
2089 12:44:11.420717 DUTY Scan : NO K
2090 12:44:11.424012 ZQ Calibration : PASS
2091 12:44:11.427597 Jitter Meter : NO K
2092 12:44:11.427679 CBT Training : PASS
2093 12:44:11.430848 Write leveling : PASS
2094 12:44:11.434209 RX DQS gating : PASS
2095 12:44:11.434292 RX DQ/DQS(RDDQC) : PASS
2096 12:44:11.437164 TX DQ/DQS : PASS
2097 12:44:11.440133 RX DATLAT : PASS
2098 12:44:11.440215 RX DQ/DQS(Engine): PASS
2099 12:44:11.443468 TX OE : NO K
2100 12:44:11.443551 All Pass.
2101 12:44:11.443616
2102 12:44:11.446848 DramC Write-DBI off
2103 12:44:11.450374 PER_BANK_REFRESH: Hybrid Mode
2104 12:44:11.450459 TX_TRACKING: ON
2105 12:44:11.453411 [GetDramInforAfterCalByMRR] Vendor 6.
2106 12:44:11.457146 [GetDramInforAfterCalByMRR] Revision 606.
2107 12:44:11.460283 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 12:44:11.463833 MR0 0x3b3b
2109 12:44:11.463915 MR8 0x5151
2110 12:44:11.466645 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 12:44:11.466728
2112 12:44:11.466793 MR0 0x3b3b
2113 12:44:11.470538 MR8 0x5151
2114 12:44:11.473384 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 12:44:11.473467
2116 12:44:11.483374 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 12:44:11.486740 [FAST_K] Save calibration result to emmc
2118 12:44:11.490014 [FAST_K] Save calibration result to emmc
2119 12:44:11.490097 dram_init: config_dvfs: 1
2120 12:44:11.496960 dramc_set_vcore_voltage set vcore to 662500
2121 12:44:11.497052 Read voltage for 1200, 2
2122 12:44:11.500315 Vio18 = 0
2123 12:44:11.500397 Vcore = 662500
2124 12:44:11.500463 Vdram = 0
2125 12:44:11.503499 Vddq = 0
2126 12:44:11.503581 Vmddr = 0
2127 12:44:11.506674 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 12:44:11.513622 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 12:44:11.516707 MEM_TYPE=3, freq_sel=15
2130 12:44:11.519884 sv_algorithm_assistance_LP4_1600
2131 12:44:11.523352 ============ PULL DRAM RESETB DOWN ============
2132 12:44:11.526674 ========== PULL DRAM RESETB DOWN end =========
2133 12:44:11.530048 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 12:44:11.533229 ===================================
2135 12:44:11.536613 LPDDR4 DRAM CONFIGURATION
2136 12:44:11.540022 ===================================
2137 12:44:11.542963 EX_ROW_EN[0] = 0x0
2138 12:44:11.543045 EX_ROW_EN[1] = 0x0
2139 12:44:11.546266 LP4Y_EN = 0x0
2140 12:44:11.546374 WORK_FSP = 0x0
2141 12:44:11.549714 WL = 0x4
2142 12:44:11.549796 RL = 0x4
2143 12:44:11.552940 BL = 0x2
2144 12:44:11.556119 RPST = 0x0
2145 12:44:11.556201 RD_PRE = 0x0
2146 12:44:11.559519 WR_PRE = 0x1
2147 12:44:11.559601 WR_PST = 0x0
2148 12:44:11.562987 DBI_WR = 0x0
2149 12:44:11.563069 DBI_RD = 0x0
2150 12:44:11.566145 OTF = 0x1
2151 12:44:11.569663 ===================================
2152 12:44:11.573058 ===================================
2153 12:44:11.573140 ANA top config
2154 12:44:11.576388 ===================================
2155 12:44:11.579551 DLL_ASYNC_EN = 0
2156 12:44:11.582881 ALL_SLAVE_EN = 0
2157 12:44:11.582964 NEW_RANK_MODE = 1
2158 12:44:11.586265 DLL_IDLE_MODE = 1
2159 12:44:11.589728 LP45_APHY_COMB_EN = 1
2160 12:44:11.592872 TX_ODT_DIS = 1
2161 12:44:11.592954 NEW_8X_MODE = 1
2162 12:44:11.596165 ===================================
2163 12:44:11.599968 ===================================
2164 12:44:11.602921 data_rate = 2400
2165 12:44:11.606071 CKR = 1
2166 12:44:11.609383 DQ_P2S_RATIO = 8
2167 12:44:11.612944 ===================================
2168 12:44:11.616368 CA_P2S_RATIO = 8
2169 12:44:11.619618 DQ_CA_OPEN = 0
2170 12:44:11.619700 DQ_SEMI_OPEN = 0
2171 12:44:11.622942 CA_SEMI_OPEN = 0
2172 12:44:11.625775 CA_FULL_RATE = 0
2173 12:44:11.629271 DQ_CKDIV4_EN = 0
2174 12:44:11.632445 CA_CKDIV4_EN = 0
2175 12:44:11.636034 CA_PREDIV_EN = 0
2176 12:44:11.636117 PH8_DLY = 17
2177 12:44:11.639407 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 12:44:11.642618 DQ_AAMCK_DIV = 4
2179 12:44:11.646092 CA_AAMCK_DIV = 4
2180 12:44:11.649176 CA_ADMCK_DIV = 4
2181 12:44:11.652636 DQ_TRACK_CA_EN = 0
2182 12:44:11.656363 CA_PICK = 1200
2183 12:44:11.656446 CA_MCKIO = 1200
2184 12:44:11.659218 MCKIO_SEMI = 0
2185 12:44:11.662474 PLL_FREQ = 2366
2186 12:44:11.666186 DQ_UI_PI_RATIO = 32
2187 12:44:11.669175 CA_UI_PI_RATIO = 0
2188 12:44:11.672707 ===================================
2189 12:44:11.675851 ===================================
2190 12:44:11.679244 memory_type:LPDDR4
2191 12:44:11.679326 GP_NUM : 10
2192 12:44:11.682983 SRAM_EN : 1
2193 12:44:11.683065 MD32_EN : 0
2194 12:44:11.685882 ===================================
2195 12:44:11.689398 [ANA_INIT] >>>>>>>>>>>>>>
2196 12:44:11.692789 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 12:44:11.695908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 12:44:11.699091 ===================================
2199 12:44:11.702892 data_rate = 2400,PCW = 0X5b00
2200 12:44:11.705793 ===================================
2201 12:44:11.709305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 12:44:11.715716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 12:44:11.718838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 12:44:11.725545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 12:44:11.728922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 12:44:11.732311 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 12:44:11.732421 [ANA_INIT] flow start
2208 12:44:11.735725 [ANA_INIT] PLL >>>>>>>>
2209 12:44:11.738888 [ANA_INIT] PLL <<<<<<<<
2210 12:44:11.738969 [ANA_INIT] MIDPI >>>>>>>>
2211 12:44:11.742815 [ANA_INIT] MIDPI <<<<<<<<
2212 12:44:11.745856 [ANA_INIT] DLL >>>>>>>>
2213 12:44:11.745938 [ANA_INIT] DLL <<<<<<<<
2214 12:44:11.749057 [ANA_INIT] flow end
2215 12:44:11.752275 ============ LP4 DIFF to SE enter ============
2216 12:44:11.755402 ============ LP4 DIFF to SE exit ============
2217 12:44:11.759365 [ANA_INIT] <<<<<<<<<<<<<
2218 12:44:11.762246 [Flow] Enable top DCM control >>>>>
2219 12:44:11.765342 [Flow] Enable top DCM control <<<<<
2220 12:44:11.769040 Enable DLL master slave shuffle
2221 12:44:11.775355 ==============================================================
2222 12:44:11.775438 Gating Mode config
2223 12:44:11.782187 ==============================================================
2224 12:44:11.782269 Config description:
2225 12:44:11.791907 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 12:44:11.798610 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 12:44:11.805477 SELPH_MODE 0: By rank 1: By Phase
2228 12:44:11.808689 ==============================================================
2229 12:44:11.811938 GAT_TRACK_EN = 1
2230 12:44:11.815083 RX_GATING_MODE = 2
2231 12:44:11.818658 RX_GATING_TRACK_MODE = 2
2232 12:44:11.821978 SELPH_MODE = 1
2233 12:44:11.825008 PICG_EARLY_EN = 1
2234 12:44:11.828498 VALID_LAT_VALUE = 1
2235 12:44:11.835322 ==============================================================
2236 12:44:11.838475 Enter into Gating configuration >>>>
2237 12:44:11.841875 Exit from Gating configuration <<<<
2238 12:44:11.845342 Enter into DVFS_PRE_config >>>>>
2239 12:44:11.855381 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 12:44:11.858614 Exit from DVFS_PRE_config <<<<<
2241 12:44:11.862007 Enter into PICG configuration >>>>
2242 12:44:11.865158 Exit from PICG configuration <<<<
2243 12:44:11.868296 [RX_INPUT] configuration >>>>>
2244 12:44:11.868379 [RX_INPUT] configuration <<<<<
2245 12:44:11.875053 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 12:44:11.881517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 12:44:11.884832 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 12:44:11.891783 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 12:44:11.898286 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 12:44:11.905115 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 12:44:11.908253 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 12:44:11.911450 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 12:44:11.918009 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 12:44:11.921400 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 12:44:11.924861 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 12:44:11.931646 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 12:44:11.934776 ===================================
2258 12:44:11.934860 LPDDR4 DRAM CONFIGURATION
2259 12:44:11.938290 ===================================
2260 12:44:11.941406 EX_ROW_EN[0] = 0x0
2261 12:44:11.941489 EX_ROW_EN[1] = 0x0
2262 12:44:11.944969 LP4Y_EN = 0x0
2263 12:44:11.945118 WORK_FSP = 0x0
2264 12:44:11.947941 WL = 0x4
2265 12:44:11.948024 RL = 0x4
2266 12:44:11.951795 BL = 0x2
2267 12:44:11.954660 RPST = 0x0
2268 12:44:11.954744 RD_PRE = 0x0
2269 12:44:11.958117 WR_PRE = 0x1
2270 12:44:11.958201 WR_PST = 0x0
2271 12:44:11.961270 DBI_WR = 0x0
2272 12:44:11.961354 DBI_RD = 0x0
2273 12:44:11.964771 OTF = 0x1
2274 12:44:11.968313 ===================================
2275 12:44:11.971475 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 12:44:11.974764 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 12:44:11.977818 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 12:44:11.981002 ===================================
2279 12:44:11.984596 LPDDR4 DRAM CONFIGURATION
2280 12:44:11.988025 ===================================
2281 12:44:11.991123 EX_ROW_EN[0] = 0x10
2282 12:44:11.991226 EX_ROW_EN[1] = 0x0
2283 12:44:11.994158 LP4Y_EN = 0x0
2284 12:44:11.994242 WORK_FSP = 0x0
2285 12:44:11.997711 WL = 0x4
2286 12:44:11.997794 RL = 0x4
2287 12:44:12.000989 BL = 0x2
2288 12:44:12.001085 RPST = 0x0
2289 12:44:12.004178 RD_PRE = 0x0
2290 12:44:12.008133 WR_PRE = 0x1
2291 12:44:12.008216 WR_PST = 0x0
2292 12:44:12.010877 DBI_WR = 0x0
2293 12:44:12.010960 DBI_RD = 0x0
2294 12:44:12.014558 OTF = 0x1
2295 12:44:12.017432 ===================================
2296 12:44:12.020958 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 12:44:12.024457 ==
2298 12:44:12.024540 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 12:44:12.030970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 12:44:12.031053 ==
2301 12:44:12.034339 [Duty_Offset_Calibration]
2302 12:44:12.034419 B0:2 B1:0 CA:1
2303 12:44:12.034484
2304 12:44:12.037707 [DutyScan_Calibration_Flow] k_type=0
2305 12:44:12.046161
2306 12:44:12.046242 ==CLK 0==
2307 12:44:12.049518 Final CLK duty delay cell = -4
2308 12:44:12.052982 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2309 12:44:12.056194 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2310 12:44:12.059841 [-4] AVG Duty = 4953%(X100)
2311 12:44:12.059922
2312 12:44:12.062894 CH0 CLK Duty spec in!! Max-Min= 156%
2313 12:44:12.066116 [DutyScan_Calibration_Flow] ====Done====
2314 12:44:12.066197
2315 12:44:12.069474 [DutyScan_Calibration_Flow] k_type=1
2316 12:44:12.085079
2317 12:44:12.085192 ==DQS 0 ==
2318 12:44:12.088360 Final DQS duty delay cell = 0
2319 12:44:12.091536 [0] MAX Duty = 5187%(X100), DQS PI = 30
2320 12:44:12.094988 [0] MIN Duty = 4938%(X100), DQS PI = 0
2321 12:44:12.095068 [0] AVG Duty = 5062%(X100)
2322 12:44:12.098248
2323 12:44:12.098327 ==DQS 1 ==
2324 12:44:12.101641 Final DQS duty delay cell = -4
2325 12:44:12.104846 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2326 12:44:12.108087 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2327 12:44:12.111512 [-4] AVG Duty = 5031%(X100)
2328 12:44:12.111592
2329 12:44:12.115216 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2330 12:44:12.115295
2331 12:44:12.118365 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2332 12:44:12.121721 [DutyScan_Calibration_Flow] ====Done====
2333 12:44:12.121801
2334 12:44:12.124837 [DutyScan_Calibration_Flow] k_type=3
2335 12:44:12.140852
2336 12:44:12.140931 ==DQM 0 ==
2337 12:44:12.144182 Final DQM duty delay cell = 0
2338 12:44:12.147872 [0] MAX Duty = 5062%(X100), DQS PI = 24
2339 12:44:12.151329 [0] MIN Duty = 4844%(X100), DQS PI = 0
2340 12:44:12.151408 [0] AVG Duty = 4953%(X100)
2341 12:44:12.154934
2342 12:44:12.155012 ==DQM 1 ==
2343 12:44:12.157941 Final DQM duty delay cell = -4
2344 12:44:12.160748 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2345 12:44:12.164409 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2346 12:44:12.168293 [-4] AVG Duty = 4906%(X100)
2347 12:44:12.168372
2348 12:44:12.170766 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2349 12:44:12.170846
2350 12:44:12.174165 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2351 12:44:12.177643 [DutyScan_Calibration_Flow] ====Done====
2352 12:44:12.177722
2353 12:44:12.180855 [DutyScan_Calibration_Flow] k_type=2
2354 12:44:12.197320
2355 12:44:12.197449 ==DQ 0 ==
2356 12:44:12.200377 Final DQ duty delay cell = -4
2357 12:44:12.203560 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2358 12:44:12.206982 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2359 12:44:12.210193 [-4] AVG Duty = 4953%(X100)
2360 12:44:12.210275
2361 12:44:12.210340 ==DQ 1 ==
2362 12:44:12.213453 Final DQ duty delay cell = 0
2363 12:44:12.216917 [0] MAX Duty = 4969%(X100), DQS PI = 56
2364 12:44:12.220519 [0] MIN Duty = 4907%(X100), DQS PI = 0
2365 12:44:12.223933 [0] AVG Duty = 4938%(X100)
2366 12:44:12.224015
2367 12:44:12.226848 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2368 12:44:12.226930
2369 12:44:12.229948 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2370 12:44:12.233478 [DutyScan_Calibration_Flow] ====Done====
2371 12:44:12.233560 ==
2372 12:44:12.236816 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 12:44:12.240150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 12:44:12.240233 ==
2375 12:44:12.243808 [Duty_Offset_Calibration]
2376 12:44:12.243890 B0:0 B1:-1 CA:2
2377 12:44:12.243955
2378 12:44:12.246762 [DutyScan_Calibration_Flow] k_type=0
2379 12:44:12.257129
2380 12:44:12.257210 ==CLK 0==
2381 12:44:12.260630 Final CLK duty delay cell = 0
2382 12:44:12.263791 [0] MAX Duty = 5156%(X100), DQS PI = 16
2383 12:44:12.267395 [0] MIN Duty = 4938%(X100), DQS PI = 44
2384 12:44:12.270427 [0] AVG Duty = 5047%(X100)
2385 12:44:12.270509
2386 12:44:12.273659 CH1 CLK Duty spec in!! Max-Min= 218%
2387 12:44:12.276928 [DutyScan_Calibration_Flow] ====Done====
2388 12:44:12.277057
2389 12:44:12.280209 [DutyScan_Calibration_Flow] k_type=1
2390 12:44:12.296735
2391 12:44:12.296817 ==DQS 0 ==
2392 12:44:12.299947 Final DQS duty delay cell = 0
2393 12:44:12.303117 [0] MAX Duty = 5093%(X100), DQS PI = 24
2394 12:44:12.306470 [0] MIN Duty = 4969%(X100), DQS PI = 0
2395 12:44:12.309746 [0] AVG Duty = 5031%(X100)
2396 12:44:12.309828
2397 12:44:12.309893 ==DQS 1 ==
2398 12:44:12.313330 Final DQS duty delay cell = 0
2399 12:44:12.316518 [0] MAX Duty = 5156%(X100), DQS PI = 0
2400 12:44:12.319661 [0] MIN Duty = 4844%(X100), DQS PI = 36
2401 12:44:12.322904 [0] AVG Duty = 5000%(X100)
2402 12:44:12.322986
2403 12:44:12.326529 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2404 12:44:12.326611
2405 12:44:12.329747 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2406 12:44:12.332944 [DutyScan_Calibration_Flow] ====Done====
2407 12:44:12.333086
2408 12:44:12.336244 [DutyScan_Calibration_Flow] k_type=3
2409 12:44:12.352916
2410 12:44:12.353058 ==DQM 0 ==
2411 12:44:12.356645 Final DQM duty delay cell = 4
2412 12:44:12.359733 [4] MAX Duty = 5093%(X100), DQS PI = 6
2413 12:44:12.363577 [4] MIN Duty = 4969%(X100), DQS PI = 28
2414 12:44:12.363658 [4] AVG Duty = 5031%(X100)
2415 12:44:12.366518
2416 12:44:12.366600 ==DQM 1 ==
2417 12:44:12.370021 Final DQM duty delay cell = -4
2418 12:44:12.373265 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2419 12:44:12.376417 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2420 12:44:12.380135 [-4] AVG Duty = 4875%(X100)
2421 12:44:12.380217
2422 12:44:12.383145 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2423 12:44:12.383227
2424 12:44:12.386560 CH1 DQM 1 Duty spec in!! Max-Min= 311%
2425 12:44:12.389461 [DutyScan_Calibration_Flow] ====Done====
2426 12:44:12.389544
2427 12:44:12.392760 [DutyScan_Calibration_Flow] k_type=2
2428 12:44:12.409836
2429 12:44:12.409928 ==DQ 0 ==
2430 12:44:12.413007 Final DQ duty delay cell = 0
2431 12:44:12.416667 [0] MAX Duty = 5062%(X100), DQS PI = 18
2432 12:44:12.419945 [0] MIN Duty = 4938%(X100), DQS PI = 0
2433 12:44:12.420049 [0] AVG Duty = 5000%(X100)
2434 12:44:12.423353
2435 12:44:12.423453 ==DQ 1 ==
2436 12:44:12.426727 Final DQ duty delay cell = 0
2437 12:44:12.429651 [0] MAX Duty = 5031%(X100), DQS PI = 2
2438 12:44:12.433318 [0] MIN Duty = 4813%(X100), DQS PI = 34
2439 12:44:12.433392 [0] AVG Duty = 4922%(X100)
2440 12:44:12.433455
2441 12:44:12.439737 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 12:44:12.439821
2443 12:44:12.443001 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2444 12:44:12.446605 [DutyScan_Calibration_Flow] ====Done====
2445 12:44:12.449589 nWR fixed to 30
2446 12:44:12.449673 [ModeRegInit_LP4] CH0 RK0
2447 12:44:12.452746 [ModeRegInit_LP4] CH0 RK1
2448 12:44:12.456016 [ModeRegInit_LP4] CH1 RK0
2449 12:44:12.459669 [ModeRegInit_LP4] CH1 RK1
2450 12:44:12.459752 match AC timing 7
2451 12:44:12.462789 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 12:44:12.469776 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 12:44:12.472925 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 12:44:12.479659 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 12:44:12.482784 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 12:44:12.482867 ==
2457 12:44:12.486552 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 12:44:12.490015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 12:44:12.490099 ==
2460 12:44:12.496188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 12:44:12.502561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 12:44:12.510099 [CA 0] Center 38 (8~69) winsize 62
2463 12:44:12.513176 [CA 1] Center 38 (8~69) winsize 62
2464 12:44:12.516239 [CA 2] Center 35 (5~66) winsize 62
2465 12:44:12.519799 [CA 3] Center 35 (4~66) winsize 63
2466 12:44:12.523057 [CA 4] Center 34 (4~65) winsize 62
2467 12:44:12.526703 [CA 5] Center 33 (3~63) winsize 61
2468 12:44:12.526786
2469 12:44:12.529773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2470 12:44:12.529856
2471 12:44:12.533116 [CATrainingPosCal] consider 1 rank data
2472 12:44:12.536656 u2DelayCellTimex100 = 270/100 ps
2473 12:44:12.539669 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2474 12:44:12.546028 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2475 12:44:12.549311 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 12:44:12.552821 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2477 12:44:12.556444 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2478 12:44:12.559338 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 12:44:12.559422
2480 12:44:12.562981 CA PerBit enable=1, Macro0, CA PI delay=33
2481 12:44:12.563065
2482 12:44:12.566545 [CBTSetCACLKResult] CA Dly = 33
2483 12:44:12.566627 CS Dly: 6 (0~37)
2484 12:44:12.569313 ==
2485 12:44:12.573217 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 12:44:12.576158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 12:44:12.576242 ==
2488 12:44:12.579473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 12:44:12.586000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2490 12:44:12.595267 [CA 0] Center 39 (8~70) winsize 63
2491 12:44:12.598644 [CA 1] Center 38 (8~69) winsize 62
2492 12:44:12.602019 [CA 2] Center 35 (5~66) winsize 62
2493 12:44:12.605264 [CA 3] Center 35 (5~66) winsize 62
2494 12:44:12.608571 [CA 4] Center 34 (4~65) winsize 62
2495 12:44:12.612310 [CA 5] Center 34 (4~64) winsize 61
2496 12:44:12.612392
2497 12:44:12.615236 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2498 12:44:12.615318
2499 12:44:12.618577 [CATrainingPosCal] consider 2 rank data
2500 12:44:12.622134 u2DelayCellTimex100 = 270/100 ps
2501 12:44:12.625862 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2502 12:44:12.629167 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2503 12:44:12.635610 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 12:44:12.638975 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 12:44:12.642189 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2506 12:44:12.645514 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2507 12:44:12.645596
2508 12:44:12.648827 CA PerBit enable=1, Macro0, CA PI delay=33
2509 12:44:12.648909
2510 12:44:12.652228 [CBTSetCACLKResult] CA Dly = 33
2511 12:44:12.652310 CS Dly: 7 (0~39)
2512 12:44:12.652375
2513 12:44:12.655518 ----->DramcWriteLeveling(PI) begin...
2514 12:44:12.659209 ==
2515 12:44:12.659291 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 12:44:12.665588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 12:44:12.665671 ==
2518 12:44:12.668578 Write leveling (Byte 0): 34 => 34
2519 12:44:12.671816 Write leveling (Byte 1): 32 => 32
2520 12:44:12.675399 DramcWriteLeveling(PI) end<-----
2521 12:44:12.675481
2522 12:44:12.675545 ==
2523 12:44:12.678532 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 12:44:12.681869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 12:44:12.681951 ==
2526 12:44:12.685586 [Gating] SW mode calibration
2527 12:44:12.691998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 12:44:12.695293 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 12:44:12.701927 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2530 12:44:12.705125 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2531 12:44:12.708820 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 12:44:12.715414 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 12:44:12.718767 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 12:44:12.721794 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 12:44:12.728397 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2536 12:44:12.731823 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2537 12:44:12.735216 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2538 12:44:12.741732 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2539 12:44:12.745529 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 12:44:12.748392 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 12:44:12.755080 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 12:44:12.758207 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 12:44:12.761716 1 0 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
2544 12:44:12.768317 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2545 12:44:12.771551 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
2546 12:44:12.774843 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 12:44:12.781383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 12:44:12.784753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 12:44:12.788514 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 12:44:12.794938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 12:44:12.797982 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 12:44:12.801511 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 12:44:12.807989 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 12:44:12.811220 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:44:12.814728 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:44:12.821599 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:44:12.824957 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:44:12.828418 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:44:12.834634 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:44:12.838235 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:44:12.841446 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:44:12.844546 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:44:12.851756 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:44:12.854581 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:44:12.857751 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:44:12.864504 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:44:12.867958 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 12:44:12.871041 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 12:44:12.877513 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 12:44:12.881214 Total UI for P1: 0, mck2ui 16
2571 12:44:12.884402 best dqsien dly found for B0: ( 1, 3, 26)
2572 12:44:12.887807 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 12:44:12.890893 Total UI for P1: 0, mck2ui 16
2574 12:44:12.894305 best dqsien dly found for B1: ( 1, 4, 0)
2575 12:44:12.897665 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2576 12:44:12.900918 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2577 12:44:12.901069
2578 12:44:12.904400 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2579 12:44:12.907682 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 12:44:12.911253 [Gating] SW calibration Done
2581 12:44:12.911359 ==
2582 12:44:12.914331 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 12:44:12.920666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 12:44:12.920754 ==
2585 12:44:12.920825 RX Vref Scan: 0
2586 12:44:12.920890
2587 12:44:12.924247 RX Vref 0 -> 0, step: 1
2588 12:44:12.924333
2589 12:44:12.927676 RX Delay -40 -> 252, step: 8
2590 12:44:12.931059 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2591 12:44:12.934836 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2592 12:44:12.937852 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2593 12:44:12.940943 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2594 12:44:12.948033 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2595 12:44:12.950685 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2596 12:44:12.954178 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2597 12:44:12.957575 iDelay=208, Bit 7, Center 131 (56 ~ 207) 152
2598 12:44:12.961026 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2599 12:44:12.967463 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2600 12:44:12.970614 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2601 12:44:12.974154 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2602 12:44:12.977198 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2603 12:44:12.980703 iDelay=208, Bit 13, Center 111 (48 ~ 175) 128
2604 12:44:12.987208 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2605 12:44:12.990557 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2606 12:44:12.990639 ==
2607 12:44:12.993976 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 12:44:12.997650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 12:44:12.997735 ==
2610 12:44:13.000417 DQS Delay:
2611 12:44:13.000500 DQS0 = 0, DQS1 = 0
2612 12:44:13.000566 DQM Delay:
2613 12:44:13.003871 DQM0 = 123, DQM1 = 109
2614 12:44:13.003954 DQ Delay:
2615 12:44:13.007109 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2616 12:44:13.010603 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =131
2617 12:44:13.013745 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2618 12:44:13.020464 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2619 12:44:13.020548
2620 12:44:13.020614
2621 12:44:13.020674 ==
2622 12:44:13.023651 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 12:44:13.027167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 12:44:13.027250 ==
2625 12:44:13.027317
2626 12:44:13.027378
2627 12:44:13.030486 TX Vref Scan disable
2628 12:44:13.030569 == TX Byte 0 ==
2629 12:44:13.036811 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2630 12:44:13.040293 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2631 12:44:13.040379 == TX Byte 1 ==
2632 12:44:13.046678 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2633 12:44:13.050131 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2634 12:44:13.050215 ==
2635 12:44:13.053427 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 12:44:13.056654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 12:44:13.056737 ==
2638 12:44:13.069940 TX Vref=22, minBit 0, minWin=24, winSum=400
2639 12:44:13.073103 TX Vref=24, minBit 1, minWin=24, winSum=408
2640 12:44:13.076563 TX Vref=26, minBit 0, minWin=24, winSum=413
2641 12:44:13.080025 TX Vref=28, minBit 1, minWin=25, winSum=414
2642 12:44:13.083366 TX Vref=30, minBit 5, minWin=25, winSum=418
2643 12:44:13.089542 TX Vref=32, minBit 0, minWin=25, winSum=412
2644 12:44:13.092889 [TxChooseVref] Worse bit 5, Min win 25, Win sum 418, Final Vref 30
2645 12:44:13.092974
2646 12:44:13.096679 Final TX Range 1 Vref 30
2647 12:44:13.096763
2648 12:44:13.096829 ==
2649 12:44:13.099440 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 12:44:13.102927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 12:44:13.103011 ==
2652 12:44:13.106290
2653 12:44:13.106373
2654 12:44:13.106438 TX Vref Scan disable
2655 12:44:13.109304 == TX Byte 0 ==
2656 12:44:13.112783 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2657 12:44:13.119355 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2658 12:44:13.119439 == TX Byte 1 ==
2659 12:44:13.122794 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2660 12:44:13.129255 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2661 12:44:13.129338
2662 12:44:13.129404 [DATLAT]
2663 12:44:13.129464 Freq=1200, CH0 RK0
2664 12:44:13.129524
2665 12:44:13.133351 DATLAT Default: 0xd
2666 12:44:13.133433 0, 0xFFFF, sum = 0
2667 12:44:13.136005 1, 0xFFFF, sum = 0
2668 12:44:13.139468 2, 0xFFFF, sum = 0
2669 12:44:13.139552 3, 0xFFFF, sum = 0
2670 12:44:13.142873 4, 0xFFFF, sum = 0
2671 12:44:13.142957 5, 0xFFFF, sum = 0
2672 12:44:13.145973 6, 0xFFFF, sum = 0
2673 12:44:13.146057 7, 0xFFFF, sum = 0
2674 12:44:13.149320 8, 0xFFFF, sum = 0
2675 12:44:13.149405 9, 0xFFFF, sum = 0
2676 12:44:13.152595 10, 0xFFFF, sum = 0
2677 12:44:13.152680 11, 0xFFFF, sum = 0
2678 12:44:13.155775 12, 0x0, sum = 1
2679 12:44:13.155872 13, 0x0, sum = 2
2680 12:44:13.159239 14, 0x0, sum = 3
2681 12:44:13.159324 15, 0x0, sum = 4
2682 12:44:13.162673 best_step = 13
2683 12:44:13.162756
2684 12:44:13.162822 ==
2685 12:44:13.165734 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 12:44:13.168936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 12:44:13.169055 ==
2688 12:44:13.169122 RX Vref Scan: 1
2689 12:44:13.172302
2690 12:44:13.172385 Set Vref Range= 32 -> 127
2691 12:44:13.172452
2692 12:44:13.175763 RX Vref 32 -> 127, step: 1
2693 12:44:13.175847
2694 12:44:13.179269 RX Delay -13 -> 252, step: 4
2695 12:44:13.179352
2696 12:44:13.182203 Set Vref, RX VrefLevel [Byte0]: 32
2697 12:44:13.185748 [Byte1]: 32
2698 12:44:13.185831
2699 12:44:13.189412 Set Vref, RX VrefLevel [Byte0]: 33
2700 12:44:13.192173 [Byte1]: 33
2701 12:44:13.195916
2702 12:44:13.196001 Set Vref, RX VrefLevel [Byte0]: 34
2703 12:44:13.202325 [Byte1]: 34
2704 12:44:13.202408
2705 12:44:13.205687 Set Vref, RX VrefLevel [Byte0]: 35
2706 12:44:13.208972 [Byte1]: 35
2707 12:44:13.209078
2708 12:44:13.212083 Set Vref, RX VrefLevel [Byte0]: 36
2709 12:44:13.215833 [Byte1]: 36
2710 12:44:13.219484
2711 12:44:13.219566 Set Vref, RX VrefLevel [Byte0]: 37
2712 12:44:13.223082 [Byte1]: 37
2713 12:44:13.227412
2714 12:44:13.227494 Set Vref, RX VrefLevel [Byte0]: 38
2715 12:44:13.230842 [Byte1]: 38
2716 12:44:13.235286
2717 12:44:13.235368 Set Vref, RX VrefLevel [Byte0]: 39
2718 12:44:13.238465 [Byte1]: 39
2719 12:44:13.243246
2720 12:44:13.243328 Set Vref, RX VrefLevel [Byte0]: 40
2721 12:44:13.246336 [Byte1]: 40
2722 12:44:13.251331
2723 12:44:13.251413 Set Vref, RX VrefLevel [Byte0]: 41
2724 12:44:13.254529 [Byte1]: 41
2725 12:44:13.258809
2726 12:44:13.258897 Set Vref, RX VrefLevel [Byte0]: 42
2727 12:44:13.262428 [Byte1]: 42
2728 12:44:13.266634
2729 12:44:13.266717 Set Vref, RX VrefLevel [Byte0]: 43
2730 12:44:13.270237 [Byte1]: 43
2731 12:44:13.274560
2732 12:44:13.274641 Set Vref, RX VrefLevel [Byte0]: 44
2733 12:44:13.277908 [Byte1]: 44
2734 12:44:13.282586
2735 12:44:13.282682 Set Vref, RX VrefLevel [Byte0]: 45
2736 12:44:13.285713 [Byte1]: 45
2737 12:44:13.290317
2738 12:44:13.293912 Set Vref, RX VrefLevel [Byte0]: 46
2739 12:44:13.296881 [Byte1]: 46
2740 12:44:13.296963
2741 12:44:13.300352 Set Vref, RX VrefLevel [Byte0]: 47
2742 12:44:13.303625 [Byte1]: 47
2743 12:44:13.303707
2744 12:44:13.307081 Set Vref, RX VrefLevel [Byte0]: 48
2745 12:44:13.310160 [Byte1]: 48
2746 12:44:13.314216
2747 12:44:13.314299 Set Vref, RX VrefLevel [Byte0]: 49
2748 12:44:13.317653 [Byte1]: 49
2749 12:44:13.322076
2750 12:44:13.322158 Set Vref, RX VrefLevel [Byte0]: 50
2751 12:44:13.325363 [Byte1]: 50
2752 12:44:13.330128
2753 12:44:13.330210 Set Vref, RX VrefLevel [Byte0]: 51
2754 12:44:13.332945 [Byte1]: 51
2755 12:44:13.337646
2756 12:44:13.337727 Set Vref, RX VrefLevel [Byte0]: 52
2757 12:44:13.341397 [Byte1]: 52
2758 12:44:13.345698
2759 12:44:13.345780 Set Vref, RX VrefLevel [Byte0]: 53
2760 12:44:13.349189 [Byte1]: 53
2761 12:44:13.353631
2762 12:44:13.353713 Set Vref, RX VrefLevel [Byte0]: 54
2763 12:44:13.357090 [Byte1]: 54
2764 12:44:13.361511
2765 12:44:13.361593 Set Vref, RX VrefLevel [Byte0]: 55
2766 12:44:13.368055 [Byte1]: 55
2767 12:44:13.368137
2768 12:44:13.371406 Set Vref, RX VrefLevel [Byte0]: 56
2769 12:44:13.374789 [Byte1]: 56
2770 12:44:13.374872
2771 12:44:13.378098 Set Vref, RX VrefLevel [Byte0]: 57
2772 12:44:13.381161 [Byte1]: 57
2773 12:44:13.385029
2774 12:44:13.385113 Set Vref, RX VrefLevel [Byte0]: 58
2775 12:44:13.388325 [Byte1]: 58
2776 12:44:13.392871
2777 12:44:13.393001 Set Vref, RX VrefLevel [Byte0]: 59
2778 12:44:13.396390 [Byte1]: 59
2779 12:44:13.401156
2780 12:44:13.401238 Set Vref, RX VrefLevel [Byte0]: 60
2781 12:44:13.403973 [Byte1]: 60
2782 12:44:13.409023
2783 12:44:13.409106 Set Vref, RX VrefLevel [Byte0]: 61
2784 12:44:13.412395 [Byte1]: 61
2785 12:44:13.417126
2786 12:44:13.417208 Set Vref, RX VrefLevel [Byte0]: 62
2787 12:44:13.419925 [Byte1]: 62
2788 12:44:13.424552
2789 12:44:13.424636 Set Vref, RX VrefLevel [Byte0]: 63
2790 12:44:13.428105 [Byte1]: 63
2791 12:44:13.432659
2792 12:44:13.432742 Set Vref, RX VrefLevel [Byte0]: 64
2793 12:44:13.436004 [Byte1]: 64
2794 12:44:13.440437
2795 12:44:13.440520 Set Vref, RX VrefLevel [Byte0]: 65
2796 12:44:13.443913 [Byte1]: 65
2797 12:44:13.448246
2798 12:44:13.448328 Set Vref, RX VrefLevel [Byte0]: 66
2799 12:44:13.451700 [Byte1]: 66
2800 12:44:13.456226
2801 12:44:13.456313 Set Vref, RX VrefLevel [Byte0]: 67
2802 12:44:13.459542 [Byte1]: 67
2803 12:44:13.464838
2804 12:44:13.464920 Set Vref, RX VrefLevel [Byte0]: 68
2805 12:44:13.467701 [Byte1]: 68
2806 12:44:13.472061
2807 12:44:13.472143 Final RX Vref Byte 0 = 56 to rank0
2808 12:44:13.475311 Final RX Vref Byte 1 = 48 to rank0
2809 12:44:13.478467 Final RX Vref Byte 0 = 56 to rank1
2810 12:44:13.481997 Final RX Vref Byte 1 = 48 to rank1==
2811 12:44:13.485141 Dram Type= 6, Freq= 0, CH_0, rank 0
2812 12:44:13.491899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2813 12:44:13.491983 ==
2814 12:44:13.492049 DQS Delay:
2815 12:44:13.492110 DQS0 = 0, DQS1 = 0
2816 12:44:13.495468 DQM Delay:
2817 12:44:13.495551 DQM0 = 122, DQM1 = 109
2818 12:44:13.498454 DQ Delay:
2819 12:44:13.501721 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2820 12:44:13.504967 DQ4 =124, DQ5 =116, DQ6 =130, DQ7 =128
2821 12:44:13.508781 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2822 12:44:13.511775 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2823 12:44:13.511859
2824 12:44:13.511924
2825 12:44:13.518860 [DQSOSCAuto] RK0, (LSB)MR18= 0x805, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2826 12:44:13.521705 CH0 RK0: MR19=404, MR18=805
2827 12:44:13.528870 CH0_RK0: MR19=0x404, MR18=0x805, DQSOSC=406, MR23=63, INC=39, DEC=26
2828 12:44:13.528986
2829 12:44:13.531829 ----->DramcWriteLeveling(PI) begin...
2830 12:44:13.531913 ==
2831 12:44:13.535216 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 12:44:13.538900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 12:44:13.541657 ==
2834 12:44:13.541739 Write leveling (Byte 0): 35 => 35
2835 12:44:13.545080 Write leveling (Byte 1): 29 => 29
2836 12:44:13.548281 DramcWriteLeveling(PI) end<-----
2837 12:44:13.548364
2838 12:44:13.548430 ==
2839 12:44:13.551855 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 12:44:13.558159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 12:44:13.558243 ==
2842 12:44:13.558310 [Gating] SW mode calibration
2843 12:44:13.568011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2844 12:44:13.571327 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2845 12:44:13.578146 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2846 12:44:13.581580 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 12:44:13.584702 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 12:44:13.591488 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 12:44:13.594617 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 12:44:13.598128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 12:44:13.601489 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2852 12:44:13.608033 0 15 28 | B1->B0 | 3030 2f2f | 0 0 | (1 0) (1 0)
2853 12:44:13.611526 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 12:44:13.614774 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 12:44:13.621612 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 12:44:13.624786 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 12:44:13.628031 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 12:44:13.634804 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 12:44:13.637801 1 0 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
2860 12:44:13.641166 1 0 28 | B1->B0 | 3737 3c3c | 1 1 | (0 0) (0 0)
2861 12:44:13.648126 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 12:44:13.651115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 12:44:13.654903 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 12:44:13.661564 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 12:44:13.664550 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 12:44:13.667710 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 12:44:13.674407 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 12:44:13.677876 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2869 12:44:13.680890 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2870 12:44:13.687677 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:44:13.690960 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:44:13.694401 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:44:13.700785 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:44:13.704952 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:44:13.707742 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:44:13.714581 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:44:13.717708 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:44:13.720925 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:44:13.727796 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:44:13.731209 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:44:13.734394 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:44:13.737794 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:44:13.744366 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:44:13.747340 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2885 12:44:13.750947 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 12:44:13.754740 Total UI for P1: 0, mck2ui 16
2887 12:44:13.757465 best dqsien dly found for B0: ( 1, 3, 28)
2888 12:44:13.760829 Total UI for P1: 0, mck2ui 16
2889 12:44:13.764039 best dqsien dly found for B1: ( 1, 3, 28)
2890 12:44:13.767451 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2891 12:44:13.770752 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2892 12:44:13.770836
2893 12:44:13.777362 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2894 12:44:13.780909 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2895 12:44:13.784330 [Gating] SW calibration Done
2896 12:44:13.784413 ==
2897 12:44:13.787760 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 12:44:13.790699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 12:44:13.790781 ==
2900 12:44:13.790846 RX Vref Scan: 0
2901 12:44:13.790906
2902 12:44:13.794143 RX Vref 0 -> 0, step: 1
2903 12:44:13.794225
2904 12:44:13.797262 RX Delay -40 -> 252, step: 8
2905 12:44:13.800632 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2906 12:44:13.804027 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2907 12:44:13.810782 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2908 12:44:13.813906 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2909 12:44:13.817848 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2910 12:44:13.820867 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2911 12:44:13.824162 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2912 12:44:13.830512 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2913 12:44:13.833850 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2914 12:44:13.837272 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2915 12:44:13.840613 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2916 12:44:13.843823 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2917 12:44:13.850543 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2918 12:44:13.854279 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2919 12:44:13.857324 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2920 12:44:13.860471 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2921 12:44:13.860566 ==
2922 12:44:13.864185 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 12:44:13.870616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 12:44:13.870698 ==
2925 12:44:13.870763 DQS Delay:
2926 12:44:13.870822 DQS0 = 0, DQS1 = 0
2927 12:44:13.874090 DQM Delay:
2928 12:44:13.874171 DQM0 = 120, DQM1 = 108
2929 12:44:13.876796 DQ Delay:
2930 12:44:13.880484 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2931 12:44:13.883555 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2932 12:44:13.887057 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2933 12:44:13.890112 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2934 12:44:13.890193
2935 12:44:13.890258
2936 12:44:13.890317 ==
2937 12:44:13.893415 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 12:44:13.896758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 12:44:13.896840 ==
2940 12:44:13.900332
2941 12:44:13.900413
2942 12:44:13.900477 TX Vref Scan disable
2943 12:44:13.903775 == TX Byte 0 ==
2944 12:44:13.906796 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2945 12:44:13.910219 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2946 12:44:13.913717 == TX Byte 1 ==
2947 12:44:13.917105 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2948 12:44:13.920420 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2949 12:44:13.920502 ==
2950 12:44:13.923416 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 12:44:13.930204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 12:44:13.930287 ==
2953 12:44:13.941517 TX Vref=22, minBit 0, minWin=24, winSum=406
2954 12:44:13.944696 TX Vref=24, minBit 1, minWin=24, winSum=408
2955 12:44:13.948192 TX Vref=26, minBit 0, minWin=25, winSum=416
2956 12:44:13.951065 TX Vref=28, minBit 2, minWin=25, winSum=417
2957 12:44:13.954726 TX Vref=30, minBit 3, minWin=25, winSum=421
2958 12:44:13.961244 TX Vref=32, minBit 3, minWin=25, winSum=420
2959 12:44:13.964323 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 30
2960 12:44:13.964404
2961 12:44:13.967880 Final TX Range 1 Vref 30
2962 12:44:13.967960
2963 12:44:13.968024 ==
2964 12:44:13.971123 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 12:44:13.974682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 12:44:13.974763 ==
2967 12:44:13.978219
2968 12:44:13.978299
2969 12:44:13.978362 TX Vref Scan disable
2970 12:44:13.981324 == TX Byte 0 ==
2971 12:44:13.984441 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2972 12:44:13.987879 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2973 12:44:13.991037 == TX Byte 1 ==
2974 12:44:13.994314 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2975 12:44:14.000819 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2976 12:44:14.000928
2977 12:44:14.001019 [DATLAT]
2978 12:44:14.001119 Freq=1200, CH0 RK1
2979 12:44:14.001179
2980 12:44:14.004504 DATLAT Default: 0xd
2981 12:44:14.004586 0, 0xFFFF, sum = 0
2982 12:44:14.007641 1, 0xFFFF, sum = 0
2983 12:44:14.007766 2, 0xFFFF, sum = 0
2984 12:44:14.010990 3, 0xFFFF, sum = 0
2985 12:44:14.014543 4, 0xFFFF, sum = 0
2986 12:44:14.014626 5, 0xFFFF, sum = 0
2987 12:44:14.017818 6, 0xFFFF, sum = 0
2988 12:44:14.017901 7, 0xFFFF, sum = 0
2989 12:44:14.021234 8, 0xFFFF, sum = 0
2990 12:44:14.021317 9, 0xFFFF, sum = 0
2991 12:44:14.024418 10, 0xFFFF, sum = 0
2992 12:44:14.024501 11, 0xFFFF, sum = 0
2993 12:44:14.027468 12, 0x0, sum = 1
2994 12:44:14.027551 13, 0x0, sum = 2
2995 12:44:14.030901 14, 0x0, sum = 3
2996 12:44:14.030984 15, 0x0, sum = 4
2997 12:44:14.031051 best_step = 13
2998 12:44:14.034233
2999 12:44:14.034315 ==
3000 12:44:14.037491 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 12:44:14.041243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 12:44:14.041325 ==
3003 12:44:14.041391 RX Vref Scan: 0
3004 12:44:14.041451
3005 12:44:14.044216 RX Vref 0 -> 0, step: 1
3006 12:44:14.044299
3007 12:44:14.047624 RX Delay -21 -> 252, step: 4
3008 12:44:14.051079 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3009 12:44:14.057433 iDelay=195, Bit 1, Center 124 (59 ~ 190) 132
3010 12:44:14.060863 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3011 12:44:14.064056 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3012 12:44:14.067394 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3013 12:44:14.070741 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3014 12:44:14.077652 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3015 12:44:14.080660 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3016 12:44:14.084150 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3017 12:44:14.087331 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3018 12:44:14.090671 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3019 12:44:14.097448 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3020 12:44:14.100806 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3021 12:44:14.103846 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3022 12:44:14.107050 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3023 12:44:14.113749 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3024 12:44:14.113830 ==
3025 12:44:14.116916 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 12:44:14.120737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 12:44:14.120818 ==
3028 12:44:14.120883 DQS Delay:
3029 12:44:14.123920 DQS0 = 0, DQS1 = 0
3030 12:44:14.124001 DQM Delay:
3031 12:44:14.126993 DQM0 = 119, DQM1 = 107
3032 12:44:14.127073 DQ Delay:
3033 12:44:14.130840 DQ0 =116, DQ1 =124, DQ2 =116, DQ3 =114
3034 12:44:14.134105 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3035 12:44:14.136957 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3036 12:44:14.140323 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3037 12:44:14.140404
3038 12:44:14.140468
3039 12:44:14.150186 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3040 12:44:14.150268 CH0 RK1: MR19=403, MR18=CF3
3041 12:44:14.156993 CH0_RK1: MR19=0x403, MR18=0xCF3, DQSOSC=405, MR23=63, INC=39, DEC=26
3042 12:44:14.160156 [RxdqsGatingPostProcess] freq 1200
3043 12:44:14.166888 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3044 12:44:14.170358 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 12:44:14.173399 best DQS1 dly(2T, 0.5T) = (0, 12)
3046 12:44:14.176717 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 12:44:14.180193 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3048 12:44:14.183294 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 12:44:14.187217 best DQS1 dly(2T, 0.5T) = (0, 11)
3050 12:44:14.189981 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 12:44:14.190062 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3052 12:44:14.193534 Pre-setting of DQS Precalculation
3053 12:44:14.200106 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3054 12:44:14.200202 ==
3055 12:44:14.203936 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 12:44:14.206846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 12:44:14.206927 ==
3058 12:44:14.213608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3059 12:44:14.219675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3060 12:44:14.227146 [CA 0] Center 37 (7~68) winsize 62
3061 12:44:14.230420 [CA 1] Center 37 (7~68) winsize 62
3062 12:44:14.233788 [CA 2] Center 35 (5~65) winsize 61
3063 12:44:14.237427 [CA 3] Center 34 (3~65) winsize 63
3064 12:44:14.240901 [CA 4] Center 33 (3~64) winsize 62
3065 12:44:14.244023 [CA 5] Center 33 (3~64) winsize 62
3066 12:44:14.244103
3067 12:44:14.247039 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3068 12:44:14.247120
3069 12:44:14.250595 [CATrainingPosCal] consider 1 rank data
3070 12:44:14.253771 u2DelayCellTimex100 = 270/100 ps
3071 12:44:14.256893 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3072 12:44:14.263671 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3073 12:44:14.267199 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3074 12:44:14.270452 CA3 delay=34 (3~65),Diff = 1 PI (4 cell)
3075 12:44:14.273861 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3076 12:44:14.277235 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3077 12:44:14.277316
3078 12:44:14.280351 CA PerBit enable=1, Macro0, CA PI delay=33
3079 12:44:14.280432
3080 12:44:14.283603 [CBTSetCACLKResult] CA Dly = 33
3081 12:44:14.283684 CS Dly: 5 (0~36)
3082 12:44:14.283763 ==
3083 12:44:14.287554 Dram Type= 6, Freq= 0, CH_1, rank 1
3084 12:44:14.293736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 12:44:14.293823 ==
3086 12:44:14.296884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 12:44:14.303597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3088 12:44:14.313055 [CA 0] Center 38 (8~68) winsize 61
3089 12:44:14.316202 [CA 1] Center 38 (7~69) winsize 63
3090 12:44:14.319424 [CA 2] Center 35 (5~66) winsize 62
3091 12:44:14.322600 [CA 3] Center 35 (5~65) winsize 61
3092 12:44:14.326009 [CA 4] Center 34 (4~64) winsize 61
3093 12:44:14.329635 [CA 5] Center 34 (4~64) winsize 61
3094 12:44:14.329715
3095 12:44:14.332559 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3096 12:44:14.332655
3097 12:44:14.335858 [CATrainingPosCal] consider 2 rank data
3098 12:44:14.339218 u2DelayCellTimex100 = 270/100 ps
3099 12:44:14.343125 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3100 12:44:14.346170 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3101 12:44:14.352641 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3102 12:44:14.356203 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3103 12:44:14.359500 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3104 12:44:14.362646 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3105 12:44:14.362728
3106 12:44:14.366334 CA PerBit enable=1, Macro0, CA PI delay=34
3107 12:44:14.366415
3108 12:44:14.369329 [CBTSetCACLKResult] CA Dly = 34
3109 12:44:14.369410 CS Dly: 6 (0~39)
3110 12:44:14.369474
3111 12:44:14.373182 ----->DramcWriteLeveling(PI) begin...
3112 12:44:14.376319 ==
3113 12:44:14.379367 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 12:44:14.382890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 12:44:14.382972 ==
3116 12:44:14.385871 Write leveling (Byte 0): 24 => 24
3117 12:44:14.389434 Write leveling (Byte 1): 26 => 26
3118 12:44:14.392605 DramcWriteLeveling(PI) end<-----
3119 12:44:14.392686
3120 12:44:14.392749 ==
3121 12:44:14.396109 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 12:44:14.399406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 12:44:14.399487 ==
3124 12:44:14.402651 [Gating] SW mode calibration
3125 12:44:14.409493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3126 12:44:14.416179 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3127 12:44:14.419465 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 12:44:14.422959 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 12:44:14.426443 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 12:44:14.432408 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 12:44:14.435741 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 12:44:14.439034 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3133 12:44:14.445700 0 15 24 | B1->B0 | 2b2b 2828 | 1 0 | (1 0) (0 1)
3134 12:44:14.449275 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3135 12:44:14.452954 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 12:44:14.459098 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 12:44:14.462472 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 12:44:14.465815 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 12:44:14.472606 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 12:44:14.475909 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 12:44:14.478997 1 0 24 | B1->B0 | 3939 4343 | 1 0 | (0 0) (0 0)
3142 12:44:14.486074 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 12:44:14.488965 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 12:44:14.492254 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 12:44:14.499156 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 12:44:14.502058 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 12:44:14.505873 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 12:44:14.512326 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 12:44:14.515530 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3150 12:44:14.518740 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:44:14.525292 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:44:14.528950 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:44:14.532156 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:44:14.538606 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:44:14.541917 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:44:14.545582 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:44:14.551813 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:44:14.555650 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:44:14.558423 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:44:14.565417 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:44:14.568464 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:44:14.571901 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:44:14.578564 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:44:14.581710 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3165 12:44:14.585490 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3166 12:44:14.592012 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3167 12:44:14.592093 Total UI for P1: 0, mck2ui 16
3168 12:44:14.595065 best dqsien dly found for B0: ( 1, 3, 22)
3169 12:44:14.601715 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 12:44:14.605147 Total UI for P1: 0, mck2ui 16
3171 12:44:14.608357 best dqsien dly found for B1: ( 1, 3, 26)
3172 12:44:14.611349 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3173 12:44:14.614990 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3174 12:44:14.615071
3175 12:44:14.618042 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3176 12:44:14.621513 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3177 12:44:14.624799 [Gating] SW calibration Done
3178 12:44:14.624879 ==
3179 12:44:14.628320 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 12:44:14.631579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 12:44:14.631660 ==
3182 12:44:14.635142 RX Vref Scan: 0
3183 12:44:14.635223
3184 12:44:14.637974 RX Vref 0 -> 0, step: 1
3185 12:44:14.638069
3186 12:44:14.638135 RX Delay -40 -> 252, step: 8
3187 12:44:14.644818 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3188 12:44:14.648014 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3189 12:44:14.651232 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3190 12:44:14.654850 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3191 12:44:14.658000 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3192 12:44:14.664924 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3193 12:44:14.668105 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3194 12:44:14.671293 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3195 12:44:14.674265 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3196 12:44:14.677867 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3197 12:44:14.684340 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3198 12:44:14.687855 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3199 12:44:14.691279 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3200 12:44:14.694948 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3201 12:44:14.697856 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3202 12:44:14.704417 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3203 12:44:14.704498 ==
3204 12:44:14.707753 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 12:44:14.711017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 12:44:14.711098 ==
3207 12:44:14.711163 DQS Delay:
3208 12:44:14.714125 DQS0 = 0, DQS1 = 0
3209 12:44:14.714206 DQM Delay:
3210 12:44:14.717711 DQM0 = 120, DQM1 = 112
3211 12:44:14.717791 DQ Delay:
3212 12:44:14.720875 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3213 12:44:14.724280 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3214 12:44:14.728397 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3215 12:44:14.731174 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3216 12:44:14.731270
3217 12:44:14.731363
3218 12:44:14.734488 ==
3219 12:44:14.737710 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 12:44:14.741026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 12:44:14.741120 ==
3222 12:44:14.741184
3223 12:44:14.741243
3224 12:44:14.744109 TX Vref Scan disable
3225 12:44:14.744190 == TX Byte 0 ==
3226 12:44:14.751075 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3227 12:44:14.754209 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3228 12:44:14.754290 == TX Byte 1 ==
3229 12:44:14.760767 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3230 12:44:14.763893 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3231 12:44:14.763975 ==
3232 12:44:14.767297 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 12:44:14.770731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 12:44:14.770813 ==
3235 12:44:14.782824 TX Vref=22, minBit 1, minWin=24, winSum=404
3236 12:44:14.786239 TX Vref=24, minBit 1, minWin=25, winSum=412
3237 12:44:14.789818 TX Vref=26, minBit 3, minWin=25, winSum=418
3238 12:44:14.792750 TX Vref=28, minBit 10, minWin=25, winSum=421
3239 12:44:14.796132 TX Vref=30, minBit 11, minWin=25, winSum=420
3240 12:44:14.803198 TX Vref=32, minBit 11, minWin=25, winSum=423
3241 12:44:14.806117 [TxChooseVref] Worse bit 11, Min win 25, Win sum 423, Final Vref 32
3242 12:44:14.806223
3243 12:44:14.809645 Final TX Range 1 Vref 32
3244 12:44:14.809726
3245 12:44:14.809790 ==
3246 12:44:14.812881 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 12:44:14.816103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 12:44:14.819467 ==
3249 12:44:14.819548
3250 12:44:14.819612
3251 12:44:14.819670 TX Vref Scan disable
3252 12:44:14.822699 == TX Byte 0 ==
3253 12:44:14.826023 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3254 12:44:14.829591 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3255 12:44:14.832769 == TX Byte 1 ==
3256 12:44:14.836263 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3257 12:44:14.839493 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3258 12:44:14.842736
3259 12:44:14.842816 [DATLAT]
3260 12:44:14.842879 Freq=1200, CH1 RK0
3261 12:44:14.842938
3262 12:44:14.846282 DATLAT Default: 0xd
3263 12:44:14.846362 0, 0xFFFF, sum = 0
3264 12:44:14.849403 1, 0xFFFF, sum = 0
3265 12:44:14.849486 2, 0xFFFF, sum = 0
3266 12:44:14.852722 3, 0xFFFF, sum = 0
3267 12:44:14.856187 4, 0xFFFF, sum = 0
3268 12:44:14.856270 5, 0xFFFF, sum = 0
3269 12:44:14.859113 6, 0xFFFF, sum = 0
3270 12:44:14.859195 7, 0xFFFF, sum = 0
3271 12:44:14.862675 8, 0xFFFF, sum = 0
3272 12:44:14.862757 9, 0xFFFF, sum = 0
3273 12:44:14.865957 10, 0xFFFF, sum = 0
3274 12:44:14.866039 11, 0xFFFF, sum = 0
3275 12:44:14.869646 12, 0x0, sum = 1
3276 12:44:14.869728 13, 0x0, sum = 2
3277 12:44:14.872626 14, 0x0, sum = 3
3278 12:44:14.872708 15, 0x0, sum = 4
3279 12:44:14.872773 best_step = 13
3280 12:44:14.875647
3281 12:44:14.875728 ==
3282 12:44:14.879201 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 12:44:14.882718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 12:44:14.882799 ==
3285 12:44:14.882865 RX Vref Scan: 1
3286 12:44:14.882924
3287 12:44:14.885872 Set Vref Range= 32 -> 127
3288 12:44:14.885953
3289 12:44:14.889302 RX Vref 32 -> 127, step: 1
3290 12:44:14.889382
3291 12:44:14.892255 RX Delay -13 -> 252, step: 4
3292 12:44:14.892335
3293 12:44:14.895867 Set Vref, RX VrefLevel [Byte0]: 32
3294 12:44:14.899023 [Byte1]: 32
3295 12:44:14.899104
3296 12:44:14.902419 Set Vref, RX VrefLevel [Byte0]: 33
3297 12:44:14.905623 [Byte1]: 33
3298 12:44:14.909268
3299 12:44:14.909347 Set Vref, RX VrefLevel [Byte0]: 34
3300 12:44:14.912485 [Byte1]: 34
3301 12:44:14.917679
3302 12:44:14.917758 Set Vref, RX VrefLevel [Byte0]: 35
3303 12:44:14.923486 [Byte1]: 35
3304 12:44:14.923564
3305 12:44:14.926888 Set Vref, RX VrefLevel [Byte0]: 36
3306 12:44:14.929962 [Byte1]: 36
3307 12:44:14.930041
3308 12:44:14.934066 Set Vref, RX VrefLevel [Byte0]: 37
3309 12:44:14.936886 [Byte1]: 37
3310 12:44:14.940654
3311 12:44:14.940732 Set Vref, RX VrefLevel [Byte0]: 38
3312 12:44:14.944202 [Byte1]: 38
3313 12:44:14.948610
3314 12:44:14.948689 Set Vref, RX VrefLevel [Byte0]: 39
3315 12:44:14.952329 [Byte1]: 39
3316 12:44:14.956937
3317 12:44:14.957041 Set Vref, RX VrefLevel [Byte0]: 40
3318 12:44:14.959763 [Byte1]: 40
3319 12:44:14.964418
3320 12:44:14.964497 Set Vref, RX VrefLevel [Byte0]: 41
3321 12:44:14.967512 [Byte1]: 41
3322 12:44:14.972292
3323 12:44:14.972370 Set Vref, RX VrefLevel [Byte0]: 42
3324 12:44:14.975538 [Byte1]: 42
3325 12:44:14.980394
3326 12:44:14.980472 Set Vref, RX VrefLevel [Byte0]: 43
3327 12:44:14.983896 [Byte1]: 43
3328 12:44:14.988023
3329 12:44:14.988102 Set Vref, RX VrefLevel [Byte0]: 44
3330 12:44:14.991271 [Byte1]: 44
3331 12:44:14.995811
3332 12:44:14.995890 Set Vref, RX VrefLevel [Byte0]: 45
3333 12:44:14.998944 [Byte1]: 45
3334 12:44:15.003900
3335 12:44:15.003981 Set Vref, RX VrefLevel [Byte0]: 46
3336 12:44:15.007107 [Byte1]: 46
3337 12:44:15.011916
3338 12:44:15.012007 Set Vref, RX VrefLevel [Byte0]: 47
3339 12:44:15.014985 [Byte1]: 47
3340 12:44:15.019414
3341 12:44:15.022870 Set Vref, RX VrefLevel [Byte0]: 48
3342 12:44:15.026130 [Byte1]: 48
3343 12:44:15.026210
3344 12:44:15.029321 Set Vref, RX VrefLevel [Byte0]: 49
3345 12:44:15.032584 [Byte1]: 49
3346 12:44:15.032663
3347 12:44:15.035883 Set Vref, RX VrefLevel [Byte0]: 50
3348 12:44:15.039077 [Byte1]: 50
3349 12:44:15.043041
3350 12:44:15.043119 Set Vref, RX VrefLevel [Byte0]: 51
3351 12:44:15.046663 [Byte1]: 51
3352 12:44:15.051371
3353 12:44:15.051449 Set Vref, RX VrefLevel [Byte0]: 52
3354 12:44:15.054454 [Byte1]: 52
3355 12:44:15.058986
3356 12:44:15.059064 Set Vref, RX VrefLevel [Byte0]: 53
3357 12:44:15.062328 [Byte1]: 53
3358 12:44:15.066936
3359 12:44:15.067017 Set Vref, RX VrefLevel [Byte0]: 54
3360 12:44:15.069986 [Byte1]: 54
3361 12:44:15.074613
3362 12:44:15.074694 Set Vref, RX VrefLevel [Byte0]: 55
3363 12:44:15.078014 [Byte1]: 55
3364 12:44:15.082652
3365 12:44:15.082732 Set Vref, RX VrefLevel [Byte0]: 56
3366 12:44:15.089179 [Byte1]: 56
3367 12:44:15.089261
3368 12:44:15.092489 Set Vref, RX VrefLevel [Byte0]: 57
3369 12:44:15.095623 [Byte1]: 57
3370 12:44:15.095706
3371 12:44:15.099080 Set Vref, RX VrefLevel [Byte0]: 58
3372 12:44:15.102391 [Byte1]: 58
3373 12:44:15.106345
3374 12:44:15.106427 Set Vref, RX VrefLevel [Byte0]: 59
3375 12:44:15.109653 [Byte1]: 59
3376 12:44:15.114114
3377 12:44:15.114196 Set Vref, RX VrefLevel [Byte0]: 60
3378 12:44:15.117724 [Byte1]: 60
3379 12:44:15.122087
3380 12:44:15.122169 Set Vref, RX VrefLevel [Byte0]: 61
3381 12:44:15.125406 [Byte1]: 61
3382 12:44:15.129858
3383 12:44:15.129940 Set Vref, RX VrefLevel [Byte0]: 62
3384 12:44:15.133228 [Byte1]: 62
3385 12:44:15.137961
3386 12:44:15.138043 Set Vref, RX VrefLevel [Byte0]: 63
3387 12:44:15.141300 [Byte1]: 63
3388 12:44:15.145790
3389 12:44:15.145872 Set Vref, RX VrefLevel [Byte0]: 64
3390 12:44:15.148889 [Byte1]: 64
3391 12:44:15.154086
3392 12:44:15.154167 Set Vref, RX VrefLevel [Byte0]: 65
3393 12:44:15.156919 [Byte1]: 65
3394 12:44:15.161629
3395 12:44:15.161711 Set Vref, RX VrefLevel [Byte0]: 66
3396 12:44:15.164913 [Byte1]: 66
3397 12:44:15.169511
3398 12:44:15.169592 Set Vref, RX VrefLevel [Byte0]: 67
3399 12:44:15.172824 [Byte1]: 67
3400 12:44:15.177425
3401 12:44:15.177507 Final RX Vref Byte 0 = 51 to rank0
3402 12:44:15.180573 Final RX Vref Byte 1 = 52 to rank0
3403 12:44:15.184591 Final RX Vref Byte 0 = 51 to rank1
3404 12:44:15.187379 Final RX Vref Byte 1 = 52 to rank1==
3405 12:44:15.190528 Dram Type= 6, Freq= 0, CH_1, rank 0
3406 12:44:15.197356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3407 12:44:15.197439 ==
3408 12:44:15.197505 DQS Delay:
3409 12:44:15.197565 DQS0 = 0, DQS1 = 0
3410 12:44:15.200610 DQM Delay:
3411 12:44:15.200692 DQM0 = 119, DQM1 = 112
3412 12:44:15.203760 DQ Delay:
3413 12:44:15.207108 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =118
3414 12:44:15.210465 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3415 12:44:15.214096 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3416 12:44:15.217522 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3417 12:44:15.217605
3418 12:44:15.217670
3419 12:44:15.223724 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3420 12:44:15.227648 CH1 RK0: MR19=404, MR18=13
3421 12:44:15.233680 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3422 12:44:15.233763
3423 12:44:15.237337 ----->DramcWriteLeveling(PI) begin...
3424 12:44:15.237421 ==
3425 12:44:15.240667 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 12:44:15.243702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 12:44:15.243785 ==
3428 12:44:15.246933 Write leveling (Byte 0): 25 => 25
3429 12:44:15.250646 Write leveling (Byte 1): 29 => 29
3430 12:44:15.253755 DramcWriteLeveling(PI) end<-----
3431 12:44:15.253837
3432 12:44:15.253902 ==
3433 12:44:15.256943 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 12:44:15.263855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 12:44:15.263937 ==
3436 12:44:15.264003 [Gating] SW mode calibration
3437 12:44:15.273880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3438 12:44:15.276890 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3439 12:44:15.280920 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 12:44:15.287023 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 12:44:15.290268 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 12:44:15.293621 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 12:44:15.300444 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 12:44:15.303725 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 12:44:15.307148 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 1)
3446 12:44:15.313431 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 0)
3447 12:44:15.316886 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 12:44:15.320310 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 12:44:15.326582 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 12:44:15.330093 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 12:44:15.333862 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 12:44:15.340013 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3453 12:44:15.343886 1 0 24 | B1->B0 | 3d3d 2626 | 0 0 | (0 0) (0 0)
3454 12:44:15.346942 1 0 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
3455 12:44:15.353750 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 12:44:15.356707 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 12:44:15.360063 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 12:44:15.366643 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 12:44:15.369925 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 12:44:15.373449 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 12:44:15.379799 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3462 12:44:15.383347 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3463 12:44:15.386647 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:44:15.393254 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:44:15.396409 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:44:15.399531 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:44:15.406480 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:44:15.409595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:44:15.413214 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:44:15.419651 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:44:15.422971 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:44:15.426235 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:44:15.432903 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:44:15.435973 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:44:15.439365 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:44:15.446244 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:44:15.449566 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3478 12:44:15.452495 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3479 12:44:15.455733 Total UI for P1: 0, mck2ui 16
3480 12:44:15.459029 best dqsien dly found for B0: ( 1, 3, 24)
3481 12:44:15.462514 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 12:44:15.466047 Total UI for P1: 0, mck2ui 16
3483 12:44:15.469173 best dqsien dly found for B1: ( 1, 3, 26)
3484 12:44:15.472612 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3485 12:44:15.479069 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3486 12:44:15.479150
3487 12:44:15.482984 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3488 12:44:15.485872 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3489 12:44:15.488790 [Gating] SW calibration Done
3490 12:44:15.488873 ==
3491 12:44:15.492330 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 12:44:15.495635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 12:44:15.495718 ==
3494 12:44:15.499069 RX Vref Scan: 0
3495 12:44:15.499152
3496 12:44:15.499217 RX Vref 0 -> 0, step: 1
3497 12:44:15.499277
3498 12:44:15.502164 RX Delay -40 -> 252, step: 8
3499 12:44:15.505814 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3500 12:44:15.512071 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3501 12:44:15.515370 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3502 12:44:15.519003 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3503 12:44:15.521889 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3504 12:44:15.525741 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3505 12:44:15.532452 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3506 12:44:15.535646 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3507 12:44:15.538517 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3508 12:44:15.542144 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3509 12:44:15.545109 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3510 12:44:15.551908 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3511 12:44:15.555147 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3512 12:44:15.558257 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3513 12:44:15.561635 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3514 12:44:15.564872 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3515 12:44:15.568259 ==
3516 12:44:15.571460 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 12:44:15.575093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 12:44:15.575176 ==
3519 12:44:15.575243 DQS Delay:
3520 12:44:15.578377 DQS0 = 0, DQS1 = 0
3521 12:44:15.578460 DQM Delay:
3522 12:44:15.581618 DQM0 = 119, DQM1 = 113
3523 12:44:15.581701 DQ Delay:
3524 12:44:15.584879 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3525 12:44:15.588354 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3526 12:44:15.591572 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3527 12:44:15.594834 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3528 12:44:15.594916
3529 12:44:15.594981
3530 12:44:15.595041 ==
3531 12:44:15.598235 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 12:44:15.604955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 12:44:15.605100 ==
3534 12:44:15.605165
3535 12:44:15.605224
3536 12:44:15.605281 TX Vref Scan disable
3537 12:44:15.608244 == TX Byte 0 ==
3538 12:44:15.611926 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3539 12:44:15.618040 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3540 12:44:15.618122 == TX Byte 1 ==
3541 12:44:15.621414 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3542 12:44:15.628255 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3543 12:44:15.628336 ==
3544 12:44:15.631136 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 12:44:15.634335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 12:44:15.634417 ==
3547 12:44:15.646081 TX Vref=22, minBit 1, minWin=25, winSum=417
3548 12:44:15.649892 TX Vref=24, minBit 1, minWin=25, winSum=421
3549 12:44:15.652838 TX Vref=26, minBit 1, minWin=26, winSum=427
3550 12:44:15.655963 TX Vref=28, minBit 1, minWin=26, winSum=429
3551 12:44:15.659529 TX Vref=30, minBit 1, minWin=26, winSum=428
3552 12:44:15.666482 TX Vref=32, minBit 1, minWin=26, winSum=426
3553 12:44:15.669565 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3554 12:44:15.669648
3555 12:44:15.672906 Final TX Range 1 Vref 28
3556 12:44:15.672994
3557 12:44:15.673110 ==
3558 12:44:15.675923 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 12:44:15.679405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 12:44:15.679487 ==
3561 12:44:15.682371
3562 12:44:15.682452
3563 12:44:15.682517 TX Vref Scan disable
3564 12:44:15.685941 == TX Byte 0 ==
3565 12:44:15.689095 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3566 12:44:15.696034 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3567 12:44:15.696116 == TX Byte 1 ==
3568 12:44:15.699276 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3569 12:44:15.705570 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3570 12:44:15.705652
3571 12:44:15.705716 [DATLAT]
3572 12:44:15.705776 Freq=1200, CH1 RK1
3573 12:44:15.705834
3574 12:44:15.708837 DATLAT Default: 0xd
3575 12:44:15.712154 0, 0xFFFF, sum = 0
3576 12:44:15.712237 1, 0xFFFF, sum = 0
3577 12:44:15.715627 2, 0xFFFF, sum = 0
3578 12:44:15.715710 3, 0xFFFF, sum = 0
3579 12:44:15.718762 4, 0xFFFF, sum = 0
3580 12:44:15.718845 5, 0xFFFF, sum = 0
3581 12:44:15.722348 6, 0xFFFF, sum = 0
3582 12:44:15.722431 7, 0xFFFF, sum = 0
3583 12:44:15.725349 8, 0xFFFF, sum = 0
3584 12:44:15.725432 9, 0xFFFF, sum = 0
3585 12:44:15.728838 10, 0xFFFF, sum = 0
3586 12:44:15.728920 11, 0xFFFF, sum = 0
3587 12:44:15.732235 12, 0x0, sum = 1
3588 12:44:15.732317 13, 0x0, sum = 2
3589 12:44:15.735476 14, 0x0, sum = 3
3590 12:44:15.735558 15, 0x0, sum = 4
3591 12:44:15.738745 best_step = 13
3592 12:44:15.738826
3593 12:44:15.738891 ==
3594 12:44:15.741901 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 12:44:15.745307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 12:44:15.745391 ==
3597 12:44:15.748376 RX Vref Scan: 0
3598 12:44:15.748457
3599 12:44:15.748523 RX Vref 0 -> 0, step: 1
3600 12:44:15.748582
3601 12:44:15.751937 RX Delay -13 -> 252, step: 4
3602 12:44:15.758356 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3603 12:44:15.762275 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3604 12:44:15.765255 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3605 12:44:15.768281 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3606 12:44:15.771657 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3607 12:44:15.777973 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3608 12:44:15.781624 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3609 12:44:15.784833 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3610 12:44:15.788317 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3611 12:44:15.791219 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3612 12:44:15.798174 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3613 12:44:15.801505 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3614 12:44:15.804329 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3615 12:44:15.807934 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3616 12:44:15.814470 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3617 12:44:15.817722 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3618 12:44:15.817809 ==
3619 12:44:15.821278 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 12:44:15.824530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 12:44:15.824613 ==
3622 12:44:15.824678 DQS Delay:
3623 12:44:15.827562 DQS0 = 0, DQS1 = 0
3624 12:44:15.827644 DQM Delay:
3625 12:44:15.830937 DQM0 = 119, DQM1 = 113
3626 12:44:15.831019 DQ Delay:
3627 12:44:15.834313 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3628 12:44:15.837634 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3629 12:44:15.840987 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3630 12:44:15.847563 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3631 12:44:15.847645
3632 12:44:15.847710
3633 12:44:15.854139 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3634 12:44:15.857648 CH1 RK1: MR19=403, MR18=7EC
3635 12:44:15.863846 CH1_RK1: MR19=0x403, MR18=0x7EC, DQSOSC=407, MR23=63, INC=39, DEC=26
3636 12:44:15.867243 [RxdqsGatingPostProcess] freq 1200
3637 12:44:15.870875 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3638 12:44:15.873665 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 12:44:15.877701 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 12:44:15.880502 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 12:44:15.883716 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 12:44:15.887048 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 12:44:15.890254 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 12:44:15.893956 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 12:44:15.896740 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 12:44:15.900565 Pre-setting of DQS Precalculation
3647 12:44:15.903381 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3648 12:44:15.913876 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3649 12:44:15.920001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3650 12:44:15.920089
3651 12:44:15.920155
3652 12:44:15.923301 [Calibration Summary] 2400 Mbps
3653 12:44:15.923384 CH 0, Rank 0
3654 12:44:15.926899 SW Impedance : PASS
3655 12:44:15.926982 DUTY Scan : NO K
3656 12:44:15.930083 ZQ Calibration : PASS
3657 12:44:15.933298 Jitter Meter : NO K
3658 12:44:15.933379 CBT Training : PASS
3659 12:44:15.936891 Write leveling : PASS
3660 12:44:15.940184 RX DQS gating : PASS
3661 12:44:15.940265 RX DQ/DQS(RDDQC) : PASS
3662 12:44:15.944168 TX DQ/DQS : PASS
3663 12:44:15.946396 RX DATLAT : PASS
3664 12:44:15.946477 RX DQ/DQS(Engine): PASS
3665 12:44:15.950202 TX OE : NO K
3666 12:44:15.950335 All Pass.
3667 12:44:15.950400
3668 12:44:15.953460 CH 0, Rank 1
3669 12:44:15.953541 SW Impedance : PASS
3670 12:44:15.956698 DUTY Scan : NO K
3671 12:44:15.959703 ZQ Calibration : PASS
3672 12:44:15.959785 Jitter Meter : NO K
3673 12:44:15.963206 CBT Training : PASS
3674 12:44:15.966445 Write leveling : PASS
3675 12:44:15.966526 RX DQS gating : PASS
3676 12:44:15.969819 RX DQ/DQS(RDDQC) : PASS
3677 12:44:15.969901 TX DQ/DQS : PASS
3678 12:44:15.973019 RX DATLAT : PASS
3679 12:44:15.976510 RX DQ/DQS(Engine): PASS
3680 12:44:15.976592 TX OE : NO K
3681 12:44:15.979551 All Pass.
3682 12:44:15.979632
3683 12:44:15.979697 CH 1, Rank 0
3684 12:44:15.982901 SW Impedance : PASS
3685 12:44:15.982983 DUTY Scan : NO K
3686 12:44:15.986730 ZQ Calibration : PASS
3687 12:44:15.989804 Jitter Meter : NO K
3688 12:44:15.989886 CBT Training : PASS
3689 12:44:15.992607 Write leveling : PASS
3690 12:44:15.996210 RX DQS gating : PASS
3691 12:44:15.996293 RX DQ/DQS(RDDQC) : PASS
3692 12:44:15.999228 TX DQ/DQS : PASS
3693 12:44:16.002541 RX DATLAT : PASS
3694 12:44:16.002624 RX DQ/DQS(Engine): PASS
3695 12:44:16.005881 TX OE : NO K
3696 12:44:16.005964 All Pass.
3697 12:44:16.006030
3698 12:44:16.009336 CH 1, Rank 1
3699 12:44:16.009419 SW Impedance : PASS
3700 12:44:16.012717 DUTY Scan : NO K
3701 12:44:16.015665 ZQ Calibration : PASS
3702 12:44:16.015748 Jitter Meter : NO K
3703 12:44:16.019212 CBT Training : PASS
3704 12:44:16.022489 Write leveling : PASS
3705 12:44:16.022572 RX DQS gating : PASS
3706 12:44:16.025851 RX DQ/DQS(RDDQC) : PASS
3707 12:44:16.029312 TX DQ/DQS : PASS
3708 12:44:16.029395 RX DATLAT : PASS
3709 12:44:16.032565 RX DQ/DQS(Engine): PASS
3710 12:44:16.032648 TX OE : NO K
3711 12:44:16.035877 All Pass.
3712 12:44:16.035959
3713 12:44:16.036025 DramC Write-DBI off
3714 12:44:16.039066 PER_BANK_REFRESH: Hybrid Mode
3715 12:44:16.042129 TX_TRACKING: ON
3716 12:44:16.049093 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3717 12:44:16.052052 [FAST_K] Save calibration result to emmc
3718 12:44:16.058660 dramc_set_vcore_voltage set vcore to 650000
3719 12:44:16.058743 Read voltage for 600, 5
3720 12:44:16.062831 Vio18 = 0
3721 12:44:16.062914 Vcore = 650000
3722 12:44:16.062979 Vdram = 0
3723 12:44:16.065485 Vddq = 0
3724 12:44:16.065567 Vmddr = 0
3725 12:44:16.068666 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3726 12:44:16.076048 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3727 12:44:16.078438 MEM_TYPE=3, freq_sel=19
3728 12:44:16.081899 sv_algorithm_assistance_LP4_1600
3729 12:44:16.084985 ============ PULL DRAM RESETB DOWN ============
3730 12:44:16.088374 ========== PULL DRAM RESETB DOWN end =========
3731 12:44:16.095112 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3732 12:44:16.095192 ===================================
3733 12:44:16.098566 LPDDR4 DRAM CONFIGURATION
3734 12:44:16.101791 ===================================
3735 12:44:16.104729 EX_ROW_EN[0] = 0x0
3736 12:44:16.104809 EX_ROW_EN[1] = 0x0
3737 12:44:16.108277 LP4Y_EN = 0x0
3738 12:44:16.108358 WORK_FSP = 0x0
3739 12:44:16.111880 WL = 0x2
3740 12:44:16.111960 RL = 0x2
3741 12:44:16.114598 BL = 0x2
3742 12:44:16.118061 RPST = 0x0
3743 12:44:16.118142 RD_PRE = 0x0
3744 12:44:16.121436 WR_PRE = 0x1
3745 12:44:16.121517 WR_PST = 0x0
3746 12:44:16.124913 DBI_WR = 0x0
3747 12:44:16.125065 DBI_RD = 0x0
3748 12:44:16.127877 OTF = 0x1
3749 12:44:16.131093 ===================================
3750 12:44:16.134563 ===================================
3751 12:44:16.134643 ANA top config
3752 12:44:16.137936 ===================================
3753 12:44:16.141012 DLL_ASYNC_EN = 0
3754 12:44:16.144647 ALL_SLAVE_EN = 1
3755 12:44:16.144728 NEW_RANK_MODE = 1
3756 12:44:16.148099 DLL_IDLE_MODE = 1
3757 12:44:16.151149 LP45_APHY_COMB_EN = 1
3758 12:44:16.154345 TX_ODT_DIS = 1
3759 12:44:16.157626 NEW_8X_MODE = 1
3760 12:44:16.160983 ===================================
3761 12:44:16.164937 ===================================
3762 12:44:16.165073 data_rate = 1200
3763 12:44:16.167661 CKR = 1
3764 12:44:16.171304 DQ_P2S_RATIO = 8
3765 12:44:16.174116 ===================================
3766 12:44:16.177863 CA_P2S_RATIO = 8
3767 12:44:16.181139 DQ_CA_OPEN = 0
3768 12:44:16.184113 DQ_SEMI_OPEN = 0
3769 12:44:16.184194 CA_SEMI_OPEN = 0
3770 12:44:16.187727 CA_FULL_RATE = 0
3771 12:44:16.190870 DQ_CKDIV4_EN = 1
3772 12:44:16.194443 CA_CKDIV4_EN = 1
3773 12:44:16.197868 CA_PREDIV_EN = 0
3774 12:44:16.201089 PH8_DLY = 0
3775 12:44:16.201184 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3776 12:44:16.203991 DQ_AAMCK_DIV = 4
3777 12:44:16.207541 CA_AAMCK_DIV = 4
3778 12:44:16.210892 CA_ADMCK_DIV = 4
3779 12:44:16.214351 DQ_TRACK_CA_EN = 0
3780 12:44:16.217196 CA_PICK = 600
3781 12:44:16.217277 CA_MCKIO = 600
3782 12:44:16.220938 MCKIO_SEMI = 0
3783 12:44:16.224273 PLL_FREQ = 2288
3784 12:44:16.227347 DQ_UI_PI_RATIO = 32
3785 12:44:16.230734 CA_UI_PI_RATIO = 0
3786 12:44:16.233824 ===================================
3787 12:44:16.237826 ===================================
3788 12:44:16.240645 memory_type:LPDDR4
3789 12:44:16.240726 GP_NUM : 10
3790 12:44:16.243765 SRAM_EN : 1
3791 12:44:16.246742 MD32_EN : 0
3792 12:44:16.250224 ===================================
3793 12:44:16.250305 [ANA_INIT] >>>>>>>>>>>>>>
3794 12:44:16.253943 <<<<<< [CONFIGURE PHASE]: ANA_TX
3795 12:44:16.256913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3796 12:44:16.260455 ===================================
3797 12:44:16.263402 data_rate = 1200,PCW = 0X5800
3798 12:44:16.266997 ===================================
3799 12:44:16.269949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3800 12:44:16.276446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 12:44:16.280081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 12:44:16.286390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3803 12:44:16.289932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3804 12:44:16.292963 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3805 12:44:16.293097 [ANA_INIT] flow start
3806 12:44:16.296559 [ANA_INIT] PLL >>>>>>>>
3807 12:44:16.299920 [ANA_INIT] PLL <<<<<<<<
3808 12:44:16.303199 [ANA_INIT] MIDPI >>>>>>>>
3809 12:44:16.303299 [ANA_INIT] MIDPI <<<<<<<<
3810 12:44:16.306371 [ANA_INIT] DLL >>>>>>>>
3811 12:44:16.306452 [ANA_INIT] flow end
3812 12:44:16.313384 ============ LP4 DIFF to SE enter ============
3813 12:44:16.316219 ============ LP4 DIFF to SE exit ============
3814 12:44:16.319683 [ANA_INIT] <<<<<<<<<<<<<
3815 12:44:16.322927 [Flow] Enable top DCM control >>>>>
3816 12:44:16.326559 [Flow] Enable top DCM control <<<<<
3817 12:44:16.329432 Enable DLL master slave shuffle
3818 12:44:16.333243 ==============================================================
3819 12:44:16.336083 Gating Mode config
3820 12:44:16.339590 ==============================================================
3821 12:44:16.342798 Config description:
3822 12:44:16.352620 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3823 12:44:16.359501 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3824 12:44:16.362710 SELPH_MODE 0: By rank 1: By Phase
3825 12:44:16.369351 ==============================================================
3826 12:44:16.372970 GAT_TRACK_EN = 1
3827 12:44:16.376558 RX_GATING_MODE = 2
3828 12:44:16.379238 RX_GATING_TRACK_MODE = 2
3829 12:44:16.382945 SELPH_MODE = 1
3830 12:44:16.385698 PICG_EARLY_EN = 1
3831 12:44:16.389279 VALID_LAT_VALUE = 1
3832 12:44:16.392268 ==============================================================
3833 12:44:16.395712 Enter into Gating configuration >>>>
3834 12:44:16.399319 Exit from Gating configuration <<<<
3835 12:44:16.402313 Enter into DVFS_PRE_config >>>>>
3836 12:44:16.415247 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3837 12:44:16.415350 Exit from DVFS_PRE_config <<<<<
3838 12:44:16.418575 Enter into PICG configuration >>>>
3839 12:44:16.421958 Exit from PICG configuration <<<<
3840 12:44:16.425333 [RX_INPUT] configuration >>>>>
3841 12:44:16.428842 [RX_INPUT] configuration <<<<<
3842 12:44:16.435874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3843 12:44:16.438808 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3844 12:44:16.445344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 12:44:16.452177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 12:44:16.458729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 12:44:16.465140 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 12:44:16.468248 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3849 12:44:16.471724 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3850 12:44:16.475412 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3851 12:44:16.481692 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3852 12:44:16.484798 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3853 12:44:16.488526 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3854 12:44:16.491743 ===================================
3855 12:44:16.494612 LPDDR4 DRAM CONFIGURATION
3856 12:44:16.498493 ===================================
3857 12:44:16.501371 EX_ROW_EN[0] = 0x0
3858 12:44:16.501488 EX_ROW_EN[1] = 0x0
3859 12:44:16.504479 LP4Y_EN = 0x0
3860 12:44:16.504560 WORK_FSP = 0x0
3861 12:44:16.507948 WL = 0x2
3862 12:44:16.508030 RL = 0x2
3863 12:44:16.511208 BL = 0x2
3864 12:44:16.511290 RPST = 0x0
3865 12:44:16.514484 RD_PRE = 0x0
3866 12:44:16.514581 WR_PRE = 0x1
3867 12:44:16.517722 WR_PST = 0x0
3868 12:44:16.517804 DBI_WR = 0x0
3869 12:44:16.521723 DBI_RD = 0x0
3870 12:44:16.521805 OTF = 0x1
3871 12:44:16.524783 ===================================
3872 12:44:16.531087 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3873 12:44:16.534254 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3874 12:44:16.537709 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 12:44:16.540583 ===================================
3876 12:44:16.544128 LPDDR4 DRAM CONFIGURATION
3877 12:44:16.547651 ===================================
3878 12:44:16.550729 EX_ROW_EN[0] = 0x10
3879 12:44:16.550811 EX_ROW_EN[1] = 0x0
3880 12:44:16.554398 LP4Y_EN = 0x0
3881 12:44:16.554481 WORK_FSP = 0x0
3882 12:44:16.557229 WL = 0x2
3883 12:44:16.557311 RL = 0x2
3884 12:44:16.560496 BL = 0x2
3885 12:44:16.560578 RPST = 0x0
3886 12:44:16.563652 RD_PRE = 0x0
3887 12:44:16.563734 WR_PRE = 0x1
3888 12:44:16.567327 WR_PST = 0x0
3889 12:44:16.570519 DBI_WR = 0x0
3890 12:44:16.570600 DBI_RD = 0x0
3891 12:44:16.573652 OTF = 0x1
3892 12:44:16.577056 ===================================
3893 12:44:16.580011 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3894 12:44:16.585555 nWR fixed to 30
3895 12:44:16.588963 [ModeRegInit_LP4] CH0 RK0
3896 12:44:16.589084 [ModeRegInit_LP4] CH0 RK1
3897 12:44:16.592736 [ModeRegInit_LP4] CH1 RK0
3898 12:44:16.595273 [ModeRegInit_LP4] CH1 RK1
3899 12:44:16.595357 match AC timing 17
3900 12:44:16.602052 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3901 12:44:16.605560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3902 12:44:16.608944 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3903 12:44:16.615397 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3904 12:44:16.618511 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3905 12:44:16.618596 ==
3906 12:44:16.622141 Dram Type= 6, Freq= 0, CH_0, rank 0
3907 12:44:16.625290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3908 12:44:16.625375 ==
3909 12:44:16.631771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3910 12:44:16.638521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3911 12:44:16.641620 [CA 0] Center 36 (5~67) winsize 63
3912 12:44:16.645259 [CA 1] Center 36 (6~67) winsize 62
3913 12:44:16.648373 [CA 2] Center 34 (4~65) winsize 62
3914 12:44:16.651784 [CA 3] Center 34 (4~65) winsize 62
3915 12:44:16.654855 [CA 4] Center 33 (3~64) winsize 62
3916 12:44:16.658196 [CA 5] Center 33 (2~64) winsize 63
3917 12:44:16.658280
3918 12:44:16.661523 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3919 12:44:16.661607
3920 12:44:16.664949 [CATrainingPosCal] consider 1 rank data
3921 12:44:16.668458 u2DelayCellTimex100 = 270/100 ps
3922 12:44:16.671328 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3923 12:44:16.674903 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3924 12:44:16.677893 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3925 12:44:16.681365 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3926 12:44:16.688165 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3927 12:44:16.691237 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3928 12:44:16.691396
3929 12:44:16.694889 CA PerBit enable=1, Macro0, CA PI delay=33
3930 12:44:16.694971
3931 12:44:16.697820 [CBTSetCACLKResult] CA Dly = 33
3932 12:44:16.697903 CS Dly: 5 (0~36)
3933 12:44:16.697969 ==
3934 12:44:16.701308 Dram Type= 6, Freq= 0, CH_0, rank 1
3935 12:44:16.707615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 12:44:16.707700 ==
3937 12:44:16.710800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 12:44:16.717626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3939 12:44:16.720849 [CA 0] Center 36 (6~67) winsize 62
3940 12:44:16.724346 [CA 1] Center 36 (6~67) winsize 62
3941 12:44:16.727632 [CA 2] Center 35 (5~66) winsize 62
3942 12:44:16.730882 [CA 3] Center 35 (4~66) winsize 63
3943 12:44:16.734265 [CA 4] Center 34 (3~65) winsize 63
3944 12:44:16.737467 [CA 5] Center 34 (3~65) winsize 63
3945 12:44:16.737551
3946 12:44:16.741135 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3947 12:44:16.741248
3948 12:44:16.744111 [CATrainingPosCal] consider 2 rank data
3949 12:44:16.747263 u2DelayCellTimex100 = 270/100 ps
3950 12:44:16.750849 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3951 12:44:16.757340 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3952 12:44:16.760720 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3953 12:44:16.763728 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3954 12:44:16.766962 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3955 12:44:16.770763 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3956 12:44:16.770846
3957 12:44:16.773924 CA PerBit enable=1, Macro0, CA PI delay=33
3958 12:44:16.774006
3959 12:44:16.777168 [CBTSetCACLKResult] CA Dly = 33
3960 12:44:16.780276 CS Dly: 6 (0~38)
3961 12:44:16.780360
3962 12:44:16.783933 ----->DramcWriteLeveling(PI) begin...
3963 12:44:16.784017 ==
3964 12:44:16.787224 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 12:44:16.790120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 12:44:16.790205 ==
3967 12:44:16.793541 Write leveling (Byte 0): 31 => 31
3968 12:44:16.797170 Write leveling (Byte 1): 29 => 29
3969 12:44:16.800271 DramcWriteLeveling(PI) end<-----
3970 12:44:16.800354
3971 12:44:16.800421 ==
3972 12:44:16.803574 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 12:44:16.807133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 12:44:16.807224 ==
3975 12:44:16.810711 [Gating] SW mode calibration
3976 12:44:16.816944 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3977 12:44:16.823235 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3978 12:44:16.826625 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 12:44:16.829926 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 12:44:16.836337 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3981 12:44:16.839930 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
3982 12:44:16.842959 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3983 12:44:16.849868 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 12:44:16.853017 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 12:44:16.856574 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:44:16.863002 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 12:44:16.866096 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 12:44:16.869423 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 12:44:16.876647 0 10 12 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
3990 12:44:16.880077 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3991 12:44:16.883403 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 12:44:16.890313 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 12:44:16.892885 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:44:16.896367 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 12:44:16.902911 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 12:44:16.906058 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 12:44:16.909516 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 12:44:16.916173 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3999 12:44:16.919574 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:44:16.922906 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:44:16.929253 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:44:16.932843 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:44:16.935938 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:44:16.942618 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:44:16.945826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:44:16.949109 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:44:16.955589 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:44:16.959105 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:44:16.962738 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:44:16.969195 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:44:16.972298 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:44:16.975805 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4013 12:44:16.978774 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4014 12:44:16.985803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 12:44:16.989043 Total UI for P1: 0, mck2ui 16
4016 12:44:16.992162 best dqsien dly found for B0: ( 0, 13, 10)
4017 12:44:16.995770 Total UI for P1: 0, mck2ui 16
4018 12:44:16.998770 best dqsien dly found for B1: ( 0, 13, 12)
4019 12:44:17.002404 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4020 12:44:17.005681 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4021 12:44:17.005765
4022 12:44:17.009173 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4023 12:44:17.012194 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4024 12:44:17.015291 [Gating] SW calibration Done
4025 12:44:17.015374 ==
4026 12:44:17.018984 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 12:44:17.022025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 12:44:17.022108 ==
4029 12:44:17.025428 RX Vref Scan: 0
4030 12:44:17.025511
4031 12:44:17.028782 RX Vref 0 -> 0, step: 1
4032 12:44:17.028864
4033 12:44:17.028931 RX Delay -230 -> 252, step: 16
4034 12:44:17.036063 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4035 12:44:17.038688 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4036 12:44:17.041901 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4037 12:44:17.045307 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4038 12:44:17.051917 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4039 12:44:17.055089 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4040 12:44:17.058532 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4041 12:44:17.061818 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4042 12:44:17.065213 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4043 12:44:17.071765 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4044 12:44:17.074917 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4045 12:44:17.078467 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4046 12:44:17.081636 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4047 12:44:17.088452 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4048 12:44:17.091541 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4049 12:44:17.094924 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4050 12:44:17.095006 ==
4051 12:44:17.098254 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 12:44:17.101871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 12:44:17.104906 ==
4054 12:44:17.105063 DQS Delay:
4055 12:44:17.105160 DQS0 = 0, DQS1 = 0
4056 12:44:17.108073 DQM Delay:
4057 12:44:17.108175 DQM0 = 53, DQM1 = 41
4058 12:44:17.111552 DQ Delay:
4059 12:44:17.115392 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4060 12:44:17.115475 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4061 12:44:17.117972 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4062 12:44:17.124746 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4063 12:44:17.124829
4064 12:44:17.124894
4065 12:44:17.124955 ==
4066 12:44:17.128084 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 12:44:17.131138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 12:44:17.131221 ==
4069 12:44:17.131286
4070 12:44:17.131346
4071 12:44:17.134894 TX Vref Scan disable
4072 12:44:17.134976 == TX Byte 0 ==
4073 12:44:17.141367 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4074 12:44:17.144598 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4075 12:44:17.144680 == TX Byte 1 ==
4076 12:44:17.151588 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4077 12:44:17.154388 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4078 12:44:17.154470 ==
4079 12:44:17.157704 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 12:44:17.160955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 12:44:17.161089 ==
4082 12:44:17.161155
4083 12:44:17.164592
4084 12:44:17.164673 TX Vref Scan disable
4085 12:44:17.167527 == TX Byte 0 ==
4086 12:44:17.171151 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4087 12:44:17.177590 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4088 12:44:17.177673 == TX Byte 1 ==
4089 12:44:17.181124 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4090 12:44:17.187530 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4091 12:44:17.187612
4092 12:44:17.187678 [DATLAT]
4093 12:44:17.187754 Freq=600, CH0 RK0
4094 12:44:17.187827
4095 12:44:17.190690 DATLAT Default: 0x9
4096 12:44:17.190772 0, 0xFFFF, sum = 0
4097 12:44:17.194118 1, 0xFFFF, sum = 0
4098 12:44:17.197307 2, 0xFFFF, sum = 0
4099 12:44:17.197391 3, 0xFFFF, sum = 0
4100 12:44:17.200904 4, 0xFFFF, sum = 0
4101 12:44:17.200996 5, 0xFFFF, sum = 0
4102 12:44:17.204099 6, 0xFFFF, sum = 0
4103 12:44:17.204182 7, 0xFFFF, sum = 0
4104 12:44:17.207434 8, 0x0, sum = 1
4105 12:44:17.207518 9, 0x0, sum = 2
4106 12:44:17.207584 10, 0x0, sum = 3
4107 12:44:17.210898 11, 0x0, sum = 4
4108 12:44:17.210982 best_step = 9
4109 12:44:17.211047
4110 12:44:17.211110 ==
4111 12:44:17.214105 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 12:44:17.221082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 12:44:17.221165 ==
4114 12:44:17.221231 RX Vref Scan: 1
4115 12:44:17.221294
4116 12:44:17.224271 RX Vref 0 -> 0, step: 1
4117 12:44:17.224353
4118 12:44:17.227271 RX Delay -179 -> 252, step: 8
4119 12:44:17.227354
4120 12:44:17.230949 Set Vref, RX VrefLevel [Byte0]: 56
4121 12:44:17.233903 [Byte1]: 48
4122 12:44:17.233985
4123 12:44:17.237199 Final RX Vref Byte 0 = 56 to rank0
4124 12:44:17.240360 Final RX Vref Byte 1 = 48 to rank0
4125 12:44:17.244026 Final RX Vref Byte 0 = 56 to rank1
4126 12:44:17.247073 Final RX Vref Byte 1 = 48 to rank1==
4127 12:44:17.250390 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 12:44:17.253847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 12:44:17.253930 ==
4130 12:44:17.257333 DQS Delay:
4131 12:44:17.257415 DQS0 = 0, DQS1 = 0
4132 12:44:17.260374 DQM Delay:
4133 12:44:17.260456 DQM0 = 49, DQM1 = 39
4134 12:44:17.260521 DQ Delay:
4135 12:44:17.263491 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4136 12:44:17.267159 DQ4 =44, DQ5 =40, DQ6 =60, DQ7 =56
4137 12:44:17.270313 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4138 12:44:17.273649 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4139 12:44:17.273731
4140 12:44:17.273796
4141 12:44:17.283302 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4142 12:44:17.286655 CH0 RK0: MR19=808, MR18=5D57
4143 12:44:17.293080 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4144 12:44:17.293164
4145 12:44:17.296709 ----->DramcWriteLeveling(PI) begin...
4146 12:44:17.296793 ==
4147 12:44:17.300213 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 12:44:17.303421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 12:44:17.303504 ==
4150 12:44:17.306564 Write leveling (Byte 0): 34 => 34
4151 12:44:17.309631 Write leveling (Byte 1): 30 => 30
4152 12:44:17.312945 DramcWriteLeveling(PI) end<-----
4153 12:44:17.313089
4154 12:44:17.313155 ==
4155 12:44:17.316242 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 12:44:17.319556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 12:44:17.319639 ==
4158 12:44:17.323303 [Gating] SW mode calibration
4159 12:44:17.329743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4160 12:44:17.336571 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4161 12:44:17.339655 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 12:44:17.343029 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 12:44:17.349783 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 12:44:17.352770 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
4165 12:44:17.356260 0 9 16 | B1->B0 | 2a2a 2727 | 1 0 | (1 0) (1 0)
4166 12:44:17.362795 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 12:44:17.365727 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 12:44:17.369146 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 12:44:17.376212 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 12:44:17.378824 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 12:44:17.382463 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 12:44:17.389073 0 10 12 | B1->B0 | 2f2f 3333 | 0 0 | (0 0) (0 0)
4173 12:44:17.392234 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4174 12:44:17.398524 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 12:44:17.401898 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 12:44:17.405170 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 12:44:17.412225 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 12:44:17.415434 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 12:44:17.418542 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 12:44:17.421990 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 12:44:17.428242 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:44:17.431623 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:44:17.435107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:44:17.441640 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:44:17.444801 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:44:17.448292 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:44:17.454898 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:44:17.458137 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:44:17.461558 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:44:17.468391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:44:17.471507 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:44:17.474954 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:44:17.481508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:44:17.484555 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:44:17.488447 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4196 12:44:17.494428 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:44:17.497785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 12:44:17.501256 Total UI for P1: 0, mck2ui 16
4199 12:44:17.504515 best dqsien dly found for B0: ( 0, 13, 14)
4200 12:44:17.507715 Total UI for P1: 0, mck2ui 16
4201 12:44:17.511010 best dqsien dly found for B1: ( 0, 13, 14)
4202 12:44:17.514089 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4203 12:44:17.517525 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4204 12:44:17.517610
4205 12:44:17.520913 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 12:44:17.527412 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4207 12:44:17.527557 [Gating] SW calibration Done
4208 12:44:17.527659 ==
4209 12:44:17.530719 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 12:44:17.537463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 12:44:17.537559 ==
4212 12:44:17.537647 RX Vref Scan: 0
4213 12:44:17.537729
4214 12:44:17.540866 RX Vref 0 -> 0, step: 1
4215 12:44:17.540954
4216 12:44:17.543950 RX Delay -230 -> 252, step: 16
4217 12:44:17.547496 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4218 12:44:17.550446 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4219 12:44:17.557604 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4220 12:44:17.561102 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4221 12:44:17.564271 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4222 12:44:17.567679 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4223 12:44:17.570777 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4224 12:44:17.577560 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4225 12:44:17.580496 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4226 12:44:17.584245 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4227 12:44:17.587218 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4228 12:44:17.593878 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4229 12:44:17.597124 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4230 12:44:17.600483 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4231 12:44:17.603733 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4232 12:44:17.610660 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4233 12:44:17.610961 ==
4234 12:44:17.614028 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 12:44:17.617239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 12:44:17.617628 ==
4237 12:44:17.617935 DQS Delay:
4238 12:44:17.621139 DQS0 = 0, DQS1 = 0
4239 12:44:17.621649 DQM Delay:
4240 12:44:17.624677 DQM0 = 46, DQM1 = 41
4241 12:44:17.625201 DQ Delay:
4242 12:44:17.627782 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4243 12:44:17.630823 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4244 12:44:17.633997 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4245 12:44:17.637686 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4246 12:44:17.638211
4247 12:44:17.638550
4248 12:44:17.638859 ==
4249 12:44:17.640679 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 12:44:17.644498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 12:44:17.645133 ==
4252 12:44:17.645488
4253 12:44:17.647516
4254 12:44:17.647935 TX Vref Scan disable
4255 12:44:17.650972 == TX Byte 0 ==
4256 12:44:17.653809 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4257 12:44:17.657331 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4258 12:44:17.660585 == TX Byte 1 ==
4259 12:44:17.663947 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4260 12:44:17.666779 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4261 12:44:17.667247 ==
4262 12:44:17.670269 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 12:44:17.677339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 12:44:17.677931 ==
4265 12:44:17.678273
4266 12:44:17.678585
4267 12:44:17.680029 TX Vref Scan disable
4268 12:44:17.680447 == TX Byte 0 ==
4269 12:44:17.686806 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4270 12:44:17.690108 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4271 12:44:17.690635 == TX Byte 1 ==
4272 12:44:17.696883 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4273 12:44:17.699867 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4274 12:44:17.700290
4275 12:44:17.700625 [DATLAT]
4276 12:44:17.703223 Freq=600, CH0 RK1
4277 12:44:17.703739
4278 12:44:17.704083 DATLAT Default: 0x9
4279 12:44:17.706633 0, 0xFFFF, sum = 0
4280 12:44:17.707060 1, 0xFFFF, sum = 0
4281 12:44:17.709781 2, 0xFFFF, sum = 0
4282 12:44:17.713272 3, 0xFFFF, sum = 0
4283 12:44:17.713804 4, 0xFFFF, sum = 0
4284 12:44:17.716546 5, 0xFFFF, sum = 0
4285 12:44:17.717132 6, 0xFFFF, sum = 0
4286 12:44:17.719850 7, 0xFFFF, sum = 0
4287 12:44:17.720376 8, 0x0, sum = 1
4288 12:44:17.723532 9, 0x0, sum = 2
4289 12:44:17.724062 10, 0x0, sum = 3
4290 12:44:17.724416 11, 0x0, sum = 4
4291 12:44:17.726324 best_step = 9
4292 12:44:17.726845
4293 12:44:17.727192 ==
4294 12:44:17.729643 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 12:44:17.732874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 12:44:17.733439 ==
4297 12:44:17.736482 RX Vref Scan: 0
4298 12:44:17.737058
4299 12:44:17.737423 RX Vref 0 -> 0, step: 1
4300 12:44:17.739270
4301 12:44:17.739689 RX Delay -179 -> 252, step: 8
4302 12:44:17.747011 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4303 12:44:17.750100 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4304 12:44:17.753447 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4305 12:44:17.756935 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4306 12:44:17.763596 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4307 12:44:17.767234 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4308 12:44:17.770032 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4309 12:44:17.773381 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4310 12:44:17.776868 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4311 12:44:17.783651 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4312 12:44:17.786723 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4313 12:44:17.789964 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4314 12:44:17.793325 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4315 12:44:17.800216 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4316 12:44:17.803088 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4317 12:44:17.806286 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4318 12:44:17.806708 ==
4319 12:44:17.809446 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 12:44:17.813045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 12:44:17.813489 ==
4322 12:44:17.816389 DQS Delay:
4323 12:44:17.816810 DQS0 = 0, DQS1 = 0
4324 12:44:17.819905 DQM Delay:
4325 12:44:17.820417 DQM0 = 48, DQM1 = 40
4326 12:44:17.820750 DQ Delay:
4327 12:44:17.823091 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4328 12:44:17.826726 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4329 12:44:17.829654 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4330 12:44:17.832754 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =44
4331 12:44:17.833352
4332 12:44:17.833695
4333 12:44:17.842734 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4334 12:44:17.846542 CH0 RK1: MR19=808, MR18=5F2E
4335 12:44:17.852900 CH0_RK1: MR19=0x808, MR18=0x5F2E, DQSOSC=391, MR23=63, INC=171, DEC=114
4336 12:44:17.853470 [RxdqsGatingPostProcess] freq 600
4337 12:44:17.859580 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 12:44:17.862761 Pre-setting of DQS Precalculation
4339 12:44:17.866439 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 12:44:17.869559 ==
4341 12:44:17.872821 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 12:44:17.876141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 12:44:17.876668 ==
4344 12:44:17.882708 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 12:44:17.885836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4346 12:44:17.890178 [CA 0] Center 35 (5~66) winsize 62
4347 12:44:17.893217 [CA 1] Center 35 (5~66) winsize 62
4348 12:44:17.896581 [CA 2] Center 34 (4~65) winsize 62
4349 12:44:17.899960 [CA 3] Center 33 (3~64) winsize 62
4350 12:44:17.902747 [CA 4] Center 34 (3~65) winsize 63
4351 12:44:17.905997 [CA 5] Center 33 (3~64) winsize 62
4352 12:44:17.906430
4353 12:44:17.909644 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4354 12:44:17.910162
4355 12:44:17.912951 [CATrainingPosCal] consider 1 rank data
4356 12:44:17.916215 u2DelayCellTimex100 = 270/100 ps
4357 12:44:17.919922 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4358 12:44:17.925950 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4359 12:44:17.929217 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4360 12:44:17.932890 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 12:44:17.936384 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4362 12:44:17.939413 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4363 12:44:17.939925
4364 12:44:17.942751 CA PerBit enable=1, Macro0, CA PI delay=33
4365 12:44:17.943271
4366 12:44:17.945705 [CBTSetCACLKResult] CA Dly = 33
4367 12:44:17.949190 CS Dly: 5 (0~36)
4368 12:44:17.949740 ==
4369 12:44:17.952675 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 12:44:17.955637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 12:44:17.956153 ==
4372 12:44:17.962257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 12:44:17.965838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4374 12:44:17.969853 [CA 0] Center 35 (5~66) winsize 62
4375 12:44:17.973451 [CA 1] Center 35 (5~66) winsize 62
4376 12:44:17.976789 [CA 2] Center 34 (4~65) winsize 62
4377 12:44:17.979848 [CA 3] Center 34 (4~65) winsize 62
4378 12:44:17.983140 [CA 4] Center 34 (3~65) winsize 63
4379 12:44:17.986478 [CA 5] Center 33 (3~64) winsize 62
4380 12:44:17.986993
4381 12:44:17.990037 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4382 12:44:17.990581
4383 12:44:17.993380 [CATrainingPosCal] consider 2 rank data
4384 12:44:17.996568 u2DelayCellTimex100 = 270/100 ps
4385 12:44:17.999889 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 12:44:18.006118 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4387 12:44:18.009740 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 12:44:18.013006 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4389 12:44:18.016345 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4390 12:44:18.019840 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 12:44:18.020357
4392 12:44:18.022694 CA PerBit enable=1, Macro0, CA PI delay=33
4393 12:44:18.023146
4394 12:44:18.026056 [CBTSetCACLKResult] CA Dly = 33
4395 12:44:18.026571 CS Dly: 5 (0~37)
4396 12:44:18.029877
4397 12:44:18.032674 ----->DramcWriteLeveling(PI) begin...
4398 12:44:18.033261 ==
4399 12:44:18.035852 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 12:44:18.039191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:44:18.039711 ==
4402 12:44:18.042394 Write leveling (Byte 0): 30 => 30
4403 12:44:18.046046 Write leveling (Byte 1): 30 => 30
4404 12:44:18.049133 DramcWriteLeveling(PI) end<-----
4405 12:44:18.049666
4406 12:44:18.050013 ==
4407 12:44:18.052864 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 12:44:18.056009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 12:44:18.056534 ==
4410 12:44:18.059271 [Gating] SW mode calibration
4411 12:44:18.066218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 12:44:18.072348 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 12:44:18.076047 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 12:44:18.078953 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 12:44:18.085813 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4416 12:44:18.088747 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
4417 12:44:18.092492 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 12:44:18.098823 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 12:44:18.102526 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 12:44:18.105514 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 12:44:18.112145 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 12:44:18.115468 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 12:44:18.118929 0 10 8 | B1->B0 | 2525 2a2a | 1 1 | (0 0) (0 0)
4424 12:44:18.125484 0 10 12 | B1->B0 | 3939 3b3b | 0 1 | (0 0) (0 0)
4425 12:44:18.128445 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 12:44:18.132099 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 12:44:18.138366 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 12:44:18.142009 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 12:44:18.145092 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 12:44:18.151669 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 12:44:18.155008 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 12:44:18.158306 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:44:18.165132 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:44:18.168283 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:44:18.171500 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:44:18.178353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:44:18.181682 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:44:18.184861 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:44:18.191192 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:44:18.194933 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:44:18.197878 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:44:18.204970 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:44:18.208091 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:44:18.211082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:44:18.217805 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:44:18.221234 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:44:18.225115 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:44:18.231659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4449 12:44:18.234351 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 12:44:18.237567 Total UI for P1: 0, mck2ui 16
4451 12:44:18.240875 best dqsien dly found for B0: ( 0, 13, 12)
4452 12:44:18.244265 Total UI for P1: 0, mck2ui 16
4453 12:44:18.247693 best dqsien dly found for B1: ( 0, 13, 12)
4454 12:44:18.250606 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4455 12:44:18.254314 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4456 12:44:18.254843
4457 12:44:18.257648 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 12:44:18.260493 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 12:44:18.264233 [Gating] SW calibration Done
4460 12:44:18.264763 ==
4461 12:44:18.267303 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 12:44:18.270476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 12:44:18.274148 ==
4464 12:44:18.274673 RX Vref Scan: 0
4465 12:44:18.275016
4466 12:44:18.276961 RX Vref 0 -> 0, step: 1
4467 12:44:18.277423
4468 12:44:18.280502 RX Delay -230 -> 252, step: 16
4469 12:44:18.283674 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4470 12:44:18.287086 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4471 12:44:18.290440 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4472 12:44:18.296887 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4473 12:44:18.300757 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4474 12:44:18.303637 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4475 12:44:18.306614 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4476 12:44:18.310096 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4477 12:44:18.317282 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4478 12:44:18.320163 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4479 12:44:18.323599 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4480 12:44:18.327104 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4481 12:44:18.333695 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4482 12:44:18.336583 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4483 12:44:18.340226 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4484 12:44:18.343310 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4485 12:44:18.343855 ==
4486 12:44:18.346496 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 12:44:18.353553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 12:44:18.354089 ==
4489 12:44:18.354435 DQS Delay:
4490 12:44:18.356523 DQS0 = 0, DQS1 = 0
4491 12:44:18.357081 DQM Delay:
4492 12:44:18.357434 DQM0 = 50, DQM1 = 41
4493 12:44:18.359957 DQ Delay:
4494 12:44:18.363486 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4495 12:44:18.366780 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4496 12:44:18.369815 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4497 12:44:18.373263 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4498 12:44:18.373788
4499 12:44:18.374186
4500 12:44:18.374512 ==
4501 12:44:18.376481 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 12:44:18.379733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 12:44:18.380269 ==
4504 12:44:18.380619
4505 12:44:18.380934
4506 12:44:18.383214 TX Vref Scan disable
4507 12:44:18.386418 == TX Byte 0 ==
4508 12:44:18.389848 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4509 12:44:18.392952 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4510 12:44:18.396546 == TX Byte 1 ==
4511 12:44:18.399586 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 12:44:18.402945 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 12:44:18.403476 ==
4514 12:44:18.406174 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 12:44:18.409154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 12:44:18.412937 ==
4517 12:44:18.413493
4518 12:44:18.413835
4519 12:44:18.414153 TX Vref Scan disable
4520 12:44:18.416396 == TX Byte 0 ==
4521 12:44:18.420039 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 12:44:18.423341 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 12:44:18.426604 == TX Byte 1 ==
4524 12:44:18.430117 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 12:44:18.433418 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 12:44:18.436284
4527 12:44:18.436705 [DATLAT]
4528 12:44:18.437067 Freq=600, CH1 RK0
4529 12:44:18.437391
4530 12:44:18.440529 DATLAT Default: 0x9
4531 12:44:18.441106 0, 0xFFFF, sum = 0
4532 12:44:18.443165 1, 0xFFFF, sum = 0
4533 12:44:18.443615 2, 0xFFFF, sum = 0
4534 12:44:18.446949 3, 0xFFFF, sum = 0
4535 12:44:18.447377 4, 0xFFFF, sum = 0
4536 12:44:18.449863 5, 0xFFFF, sum = 0
4537 12:44:18.453665 6, 0xFFFF, sum = 0
4538 12:44:18.454114 7, 0xFFFF, sum = 0
4539 12:44:18.454458 8, 0x0, sum = 1
4540 12:44:18.456497 9, 0x0, sum = 2
4541 12:44:18.456924 10, 0x0, sum = 3
4542 12:44:18.459668 11, 0x0, sum = 4
4543 12:44:18.460093 best_step = 9
4544 12:44:18.460424
4545 12:44:18.460735 ==
4546 12:44:18.463534 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 12:44:18.469742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 12:44:18.470262 ==
4549 12:44:18.470606 RX Vref Scan: 1
4550 12:44:18.470916
4551 12:44:18.472942 RX Vref 0 -> 0, step: 1
4552 12:44:18.473407
4553 12:44:18.476139 RX Delay -179 -> 252, step: 8
4554 12:44:18.476594
4555 12:44:18.479644 Set Vref, RX VrefLevel [Byte0]: 51
4556 12:44:18.482910 [Byte1]: 52
4557 12:44:18.483439
4558 12:44:18.486458 Final RX Vref Byte 0 = 51 to rank0
4559 12:44:18.489286 Final RX Vref Byte 1 = 52 to rank0
4560 12:44:18.492817 Final RX Vref Byte 0 = 51 to rank1
4561 12:44:18.496000 Final RX Vref Byte 1 = 52 to rank1==
4562 12:44:18.499164 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 12:44:18.502819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 12:44:18.503344 ==
4565 12:44:18.505965 DQS Delay:
4566 12:44:18.506491 DQS0 = 0, DQS1 = 0
4567 12:44:18.508830 DQM Delay:
4568 12:44:18.509343 DQM0 = 49, DQM1 = 41
4569 12:44:18.509688 DQ Delay:
4570 12:44:18.512203 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4571 12:44:18.515445 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4572 12:44:18.519054 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4573 12:44:18.522148 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4574 12:44:18.522670
4575 12:44:18.525323
4576 12:44:18.532052 [DQSOSCAuto] RK0, (LSB)MR18= 0x476d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4577 12:44:18.535545 CH1 RK0: MR19=808, MR18=476D
4578 12:44:18.542451 CH1_RK0: MR19=0x808, MR18=0x476D, DQSOSC=389, MR23=63, INC=173, DEC=115
4579 12:44:18.542977
4580 12:44:18.545344 ----->DramcWriteLeveling(PI) begin...
4581 12:44:18.545772 ==
4582 12:44:18.549158 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 12:44:18.552269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 12:44:18.552797 ==
4585 12:44:18.555377 Write leveling (Byte 0): 29 => 29
4586 12:44:18.558951 Write leveling (Byte 1): 33 => 33
4587 12:44:18.562033 DramcWriteLeveling(PI) end<-----
4588 12:44:18.562538
4589 12:44:18.563019 ==
4590 12:44:18.565403 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 12:44:18.569055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 12:44:18.569605 ==
4593 12:44:18.572089 [Gating] SW mode calibration
4594 12:44:18.578615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 12:44:18.585529 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 12:44:18.588852 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 12:44:18.592138 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 12:44:18.598681 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
4599 12:44:18.602119 0 9 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
4600 12:44:18.605554 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4601 12:44:18.611636 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 12:44:18.614974 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 12:44:18.618584 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 12:44:18.624800 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 12:44:18.628530 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 12:44:18.631460 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4607 12:44:18.638360 0 10 12 | B1->B0 | 3e3e 2f2f | 0 0 | (0 0) (0 0)
4608 12:44:18.641338 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 12:44:18.645261 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 12:44:18.651456 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 12:44:18.654809 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 12:44:18.658297 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 12:44:18.664615 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 12:44:18.667797 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 12:44:18.671294 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4616 12:44:18.677855 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:44:18.681297 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:44:18.684793 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:44:18.690959 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:44:18.694716 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:44:18.698093 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:44:18.704524 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:44:18.708033 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:44:18.710802 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:44:18.717656 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:44:18.720936 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:44:18.724331 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:44:18.730903 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:44:18.734226 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:44:18.737962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:44:18.744256 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:44:18.744774 Total UI for P1: 0, mck2ui 16
4633 12:44:18.747341 best dqsien dly found for B0: ( 0, 13, 10)
4634 12:44:18.750933 Total UI for P1: 0, mck2ui 16
4635 12:44:18.754239 best dqsien dly found for B1: ( 0, 13, 10)
4636 12:44:18.761319 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4637 12:44:18.764185 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4638 12:44:18.764704
4639 12:44:18.767154 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4640 12:44:18.770354 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4641 12:44:18.773933 [Gating] SW calibration Done
4642 12:44:18.774451 ==
4643 12:44:18.777331 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 12:44:18.780437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 12:44:18.780868 ==
4646 12:44:18.783646 RX Vref Scan: 0
4647 12:44:18.784072
4648 12:44:18.784408 RX Vref 0 -> 0, step: 1
4649 12:44:18.784719
4650 12:44:18.787411 RX Delay -230 -> 252, step: 16
4651 12:44:18.790050 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4652 12:44:18.797094 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4653 12:44:18.800080 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4654 12:44:18.803469 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4655 12:44:18.806740 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4656 12:44:18.813277 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4657 12:44:18.817010 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4658 12:44:18.820134 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4659 12:44:18.823436 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4660 12:44:18.826797 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4661 12:44:18.833232 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4662 12:44:18.836314 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4663 12:44:18.840040 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4664 12:44:18.843129 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4665 12:44:18.850065 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4666 12:44:18.853136 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4667 12:44:18.853653 ==
4668 12:44:18.856520 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 12:44:18.859361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 12:44:18.859786 ==
4671 12:44:18.863092 DQS Delay:
4672 12:44:18.863601 DQS0 = 0, DQS1 = 0
4673 12:44:18.866486 DQM Delay:
4674 12:44:18.867006 DQM0 = 51, DQM1 = 44
4675 12:44:18.867348 DQ Delay:
4676 12:44:18.870295 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4677 12:44:18.872698 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4678 12:44:18.876343 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4679 12:44:18.879367 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4680 12:44:18.879789
4681 12:44:18.880162
4682 12:44:18.882945 ==
4683 12:44:18.883478 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 12:44:18.889392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 12:44:18.889909 ==
4686 12:44:18.890295
4687 12:44:18.890616
4688 12:44:18.892687 TX Vref Scan disable
4689 12:44:18.893144 == TX Byte 0 ==
4690 12:44:18.899281 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4691 12:44:18.902752 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4692 12:44:18.903281 == TX Byte 1 ==
4693 12:44:18.909569 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4694 12:44:18.912286 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4695 12:44:18.912715 ==
4696 12:44:18.915774 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 12:44:18.919190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 12:44:18.919720 ==
4699 12:44:18.920066
4700 12:44:18.920378
4701 12:44:18.922496 TX Vref Scan disable
4702 12:44:18.925851 == TX Byte 0 ==
4703 12:44:18.929260 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 12:44:18.932249 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 12:44:18.935817 == TX Byte 1 ==
4706 12:44:18.939090 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4707 12:44:18.942358 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4708 12:44:18.945698
4709 12:44:18.946277 [DATLAT]
4710 12:44:18.946623 Freq=600, CH1 RK1
4711 12:44:18.946939
4712 12:44:18.949170 DATLAT Default: 0x9
4713 12:44:18.949690 0, 0xFFFF, sum = 0
4714 12:44:18.952033 1, 0xFFFF, sum = 0
4715 12:44:18.952493 2, 0xFFFF, sum = 0
4716 12:44:18.955968 3, 0xFFFF, sum = 0
4717 12:44:18.958942 4, 0xFFFF, sum = 0
4718 12:44:18.959472 5, 0xFFFF, sum = 0
4719 12:44:18.961903 6, 0xFFFF, sum = 0
4720 12:44:18.962433 7, 0xFFFF, sum = 0
4721 12:44:18.965535 8, 0x0, sum = 1
4722 12:44:18.965962 9, 0x0, sum = 2
4723 12:44:18.966307 10, 0x0, sum = 3
4724 12:44:18.969079 11, 0x0, sum = 4
4725 12:44:18.969614 best_step = 9
4726 12:44:18.970042
4727 12:44:18.970363 ==
4728 12:44:18.972426 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 12:44:18.978734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 12:44:18.979264 ==
4731 12:44:18.979609 RX Vref Scan: 0
4732 12:44:18.979920
4733 12:44:18.981849 RX Vref 0 -> 0, step: 1
4734 12:44:18.982270
4735 12:44:18.985423 RX Delay -163 -> 252, step: 8
4736 12:44:18.988969 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4737 12:44:18.995169 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4738 12:44:18.998791 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4739 12:44:19.001419 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4740 12:44:19.005019 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4741 12:44:19.008283 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4742 12:44:19.014981 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4743 12:44:19.018174 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4744 12:44:19.021778 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4745 12:44:19.025006 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4746 12:44:19.028411 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4747 12:44:19.034623 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4748 12:44:19.038237 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4749 12:44:19.041722 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4750 12:44:19.045070 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4751 12:44:19.051731 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4752 12:44:19.052283 ==
4753 12:44:19.055069 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 12:44:19.057965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 12:44:19.058496 ==
4756 12:44:19.058836 DQS Delay:
4757 12:44:19.061169 DQS0 = 0, DQS1 = 0
4758 12:44:19.061591 DQM Delay:
4759 12:44:19.064793 DQM0 = 49, DQM1 = 43
4760 12:44:19.065331 DQ Delay:
4761 12:44:19.067737 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4762 12:44:19.071416 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4763 12:44:19.074584 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4764 12:44:19.077997 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4765 12:44:19.078420
4766 12:44:19.078757
4767 12:44:19.084660 [DQSOSCAuto] RK1, (LSB)MR18= 0x581e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4768 12:44:19.088202 CH1 RK1: MR19=808, MR18=581E
4769 12:44:19.094819 CH1_RK1: MR19=0x808, MR18=0x581E, DQSOSC=393, MR23=63, INC=169, DEC=113
4770 12:44:19.097888 [RxdqsGatingPostProcess] freq 600
4771 12:44:19.104427 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 12:44:19.107661 Pre-setting of DQS Precalculation
4773 12:44:19.110788 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 12:44:19.117673 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 12:44:19.124282 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 12:44:19.124794
4777 12:44:19.128435
4778 12:44:19.128948 [Calibration Summary] 1200 Mbps
4779 12:44:19.130508 CH 0, Rank 0
4780 12:44:19.130930 SW Impedance : PASS
4781 12:44:19.134205 DUTY Scan : NO K
4782 12:44:19.137396 ZQ Calibration : PASS
4783 12:44:19.137815 Jitter Meter : NO K
4784 12:44:19.140801 CBT Training : PASS
4785 12:44:19.144258 Write leveling : PASS
4786 12:44:19.144780 RX DQS gating : PASS
4787 12:44:19.147088 RX DQ/DQS(RDDQC) : PASS
4788 12:44:19.150912 TX DQ/DQS : PASS
4789 12:44:19.151437 RX DATLAT : PASS
4790 12:44:19.153561 RX DQ/DQS(Engine): PASS
4791 12:44:19.157443 TX OE : NO K
4792 12:44:19.157964 All Pass.
4793 12:44:19.158308
4794 12:44:19.158621 CH 0, Rank 1
4795 12:44:19.160407 SW Impedance : PASS
4796 12:44:19.163865 DUTY Scan : NO K
4797 12:44:19.164384 ZQ Calibration : PASS
4798 12:44:19.167017 Jitter Meter : NO K
4799 12:44:19.170807 CBT Training : PASS
4800 12:44:19.171336 Write leveling : PASS
4801 12:44:19.173997 RX DQS gating : PASS
4802 12:44:19.174416 RX DQ/DQS(RDDQC) : PASS
4803 12:44:19.177049 TX DQ/DQS : PASS
4804 12:44:19.180913 RX DATLAT : PASS
4805 12:44:19.181483 RX DQ/DQS(Engine): PASS
4806 12:44:19.184105 TX OE : NO K
4807 12:44:19.184632 All Pass.
4808 12:44:19.184973
4809 12:44:19.187447 CH 1, Rank 0
4810 12:44:19.187865 SW Impedance : PASS
4811 12:44:19.190419 DUTY Scan : NO K
4812 12:44:19.193539 ZQ Calibration : PASS
4813 12:44:19.193959 Jitter Meter : NO K
4814 12:44:19.196862 CBT Training : PASS
4815 12:44:19.200598 Write leveling : PASS
4816 12:44:19.201041 RX DQS gating : PASS
4817 12:44:19.203644 RX DQ/DQS(RDDQC) : PASS
4818 12:44:19.207499 TX DQ/DQS : PASS
4819 12:44:19.208028 RX DATLAT : PASS
4820 12:44:19.210370 RX DQ/DQS(Engine): PASS
4821 12:44:19.210801 TX OE : NO K
4822 12:44:19.213829 All Pass.
4823 12:44:19.214247
4824 12:44:19.214638 CH 1, Rank 1
4825 12:44:19.217138 SW Impedance : PASS
4826 12:44:19.220792 DUTY Scan : NO K
4827 12:44:19.221362 ZQ Calibration : PASS
4828 12:44:19.224013 Jitter Meter : NO K
4829 12:44:19.224447 CBT Training : PASS
4830 12:44:19.226956 Write leveling : PASS
4831 12:44:19.229925 RX DQS gating : PASS
4832 12:44:19.230352 RX DQ/DQS(RDDQC) : PASS
4833 12:44:19.233292 TX DQ/DQS : PASS
4834 12:44:19.236951 RX DATLAT : PASS
4835 12:44:19.237527 RX DQ/DQS(Engine): PASS
4836 12:44:19.240280 TX OE : NO K
4837 12:44:19.240807 All Pass.
4838 12:44:19.241201
4839 12:44:19.243445 DramC Write-DBI off
4840 12:44:19.246663 PER_BANK_REFRESH: Hybrid Mode
4841 12:44:19.247088 TX_TRACKING: ON
4842 12:44:19.256857 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 12:44:19.259717 [FAST_K] Save calibration result to emmc
4844 12:44:19.263395 dramc_set_vcore_voltage set vcore to 662500
4845 12:44:19.266760 Read voltage for 933, 3
4846 12:44:19.267286 Vio18 = 0
4847 12:44:19.267629 Vcore = 662500
4848 12:44:19.269790 Vdram = 0
4849 12:44:19.270212 Vddq = 0
4850 12:44:19.270601 Vmddr = 0
4851 12:44:19.276599 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 12:44:19.279506 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 12:44:19.283443 MEM_TYPE=3, freq_sel=17
4854 12:44:19.286388 sv_algorithm_assistance_LP4_1600
4855 12:44:19.289418 ============ PULL DRAM RESETB DOWN ============
4856 12:44:19.296557 ========== PULL DRAM RESETB DOWN end =========
4857 12:44:19.299635 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 12:44:19.302423 ===================================
4859 12:44:19.306098 LPDDR4 DRAM CONFIGURATION
4860 12:44:19.309404 ===================================
4861 12:44:19.309934 EX_ROW_EN[0] = 0x0
4862 12:44:19.312392 EX_ROW_EN[1] = 0x0
4863 12:44:19.312834 LP4Y_EN = 0x0
4864 12:44:19.316110 WORK_FSP = 0x0
4865 12:44:19.316635 WL = 0x3
4866 12:44:19.319149 RL = 0x3
4867 12:44:19.322595 BL = 0x2
4868 12:44:19.323152 RPST = 0x0
4869 12:44:19.325688 RD_PRE = 0x0
4870 12:44:19.326109 WR_PRE = 0x1
4871 12:44:19.329126 WR_PST = 0x0
4872 12:44:19.329662 DBI_WR = 0x0
4873 12:44:19.332816 DBI_RD = 0x0
4874 12:44:19.333409 OTF = 0x1
4875 12:44:19.335450 ===================================
4876 12:44:19.338732 ===================================
4877 12:44:19.342026 ANA top config
4878 12:44:19.345941 ===================================
4879 12:44:19.346495 DLL_ASYNC_EN = 0
4880 12:44:19.348759 ALL_SLAVE_EN = 1
4881 12:44:19.352129 NEW_RANK_MODE = 1
4882 12:44:19.355558 DLL_IDLE_MODE = 1
4883 12:44:19.356089 LP45_APHY_COMB_EN = 1
4884 12:44:19.358983 TX_ODT_DIS = 1
4885 12:44:19.362390 NEW_8X_MODE = 1
4886 12:44:19.365425 ===================================
4887 12:44:19.368682 ===================================
4888 12:44:19.372356 data_rate = 1866
4889 12:44:19.375292 CKR = 1
4890 12:44:19.378885 DQ_P2S_RATIO = 8
4891 12:44:19.381834 ===================================
4892 12:44:19.382332 CA_P2S_RATIO = 8
4893 12:44:19.385289 DQ_CA_OPEN = 0
4894 12:44:19.388796 DQ_SEMI_OPEN = 0
4895 12:44:19.392041 CA_SEMI_OPEN = 0
4896 12:44:19.395512 CA_FULL_RATE = 0
4897 12:44:19.398581 DQ_CKDIV4_EN = 1
4898 12:44:19.399008 CA_CKDIV4_EN = 1
4899 12:44:19.401924 CA_PREDIV_EN = 0
4900 12:44:19.405407 PH8_DLY = 0
4901 12:44:19.408535 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 12:44:19.411982 DQ_AAMCK_DIV = 4
4903 12:44:19.415118 CA_AAMCK_DIV = 4
4904 12:44:19.415544 CA_ADMCK_DIV = 4
4905 12:44:19.418214 DQ_TRACK_CA_EN = 0
4906 12:44:19.421812 CA_PICK = 933
4907 12:44:19.424858 CA_MCKIO = 933
4908 12:44:19.428321 MCKIO_SEMI = 0
4909 12:44:19.431780 PLL_FREQ = 3732
4910 12:44:19.435205 DQ_UI_PI_RATIO = 32
4911 12:44:19.435741 CA_UI_PI_RATIO = 0
4912 12:44:19.437915 ===================================
4913 12:44:19.441403 ===================================
4914 12:44:19.444769 memory_type:LPDDR4
4915 12:44:19.448250 GP_NUM : 10
4916 12:44:19.448677 SRAM_EN : 1
4917 12:44:19.451374 MD32_EN : 0
4918 12:44:19.454549 ===================================
4919 12:44:19.458133 [ANA_INIT] >>>>>>>>>>>>>>
4920 12:44:19.461339 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 12:44:19.465002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 12:44:19.467988 ===================================
4923 12:44:19.468516 data_rate = 1866,PCW = 0X8f00
4924 12:44:19.471054 ===================================
4925 12:44:19.478151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 12:44:19.481137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 12:44:19.487881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 12:44:19.491232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 12:44:19.494351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 12:44:19.497869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 12:44:19.501168 [ANA_INIT] flow start
4932 12:44:19.504596 [ANA_INIT] PLL >>>>>>>>
4933 12:44:19.505148 [ANA_INIT] PLL <<<<<<<<
4934 12:44:19.507630 [ANA_INIT] MIDPI >>>>>>>>
4935 12:44:19.511004 [ANA_INIT] MIDPI <<<<<<<<
4936 12:44:19.511575 [ANA_INIT] DLL >>>>>>>>
4937 12:44:19.514288 [ANA_INIT] flow end
4938 12:44:19.517501 ============ LP4 DIFF to SE enter ============
4939 12:44:19.524067 ============ LP4 DIFF to SE exit ============
4940 12:44:19.524612 [ANA_INIT] <<<<<<<<<<<<<
4941 12:44:19.527320 [Flow] Enable top DCM control >>>>>
4942 12:44:19.530751 [Flow] Enable top DCM control <<<<<
4943 12:44:19.533807 Enable DLL master slave shuffle
4944 12:44:19.540682 ==============================================================
4945 12:44:19.541239 Gating Mode config
4946 12:44:19.547437 ==============================================================
4947 12:44:19.550354 Config description:
4948 12:44:19.560544 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 12:44:19.566898 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 12:44:19.570277 SELPH_MODE 0: By rank 1: By Phase
4951 12:44:19.576947 ==============================================================
4952 12:44:19.580064 GAT_TRACK_EN = 1
4953 12:44:19.580558 RX_GATING_MODE = 2
4954 12:44:19.583343 RX_GATING_TRACK_MODE = 2
4955 12:44:19.586982 SELPH_MODE = 1
4956 12:44:19.590126 PICG_EARLY_EN = 1
4957 12:44:19.593276 VALID_LAT_VALUE = 1
4958 12:44:19.599838 ==============================================================
4959 12:44:19.603177 Enter into Gating configuration >>>>
4960 12:44:19.606557 Exit from Gating configuration <<<<
4961 12:44:19.609844 Enter into DVFS_PRE_config >>>>>
4962 12:44:19.619930 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 12:44:19.623051 Exit from DVFS_PRE_config <<<<<
4964 12:44:19.626364 Enter into PICG configuration >>>>
4965 12:44:19.629620 Exit from PICG configuration <<<<
4966 12:44:19.632886 [RX_INPUT] configuration >>>>>
4967 12:44:19.636148 [RX_INPUT] configuration <<<<<
4968 12:44:19.639808 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 12:44:19.646231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 12:44:19.653388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 12:44:19.659361 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 12:44:19.666084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 12:44:19.669220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 12:44:19.675864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 12:44:19.679773 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 12:44:19.682593 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 12:44:19.685597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 12:44:19.692454 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 12:44:19.695586 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 12:44:19.698800 ===================================
4981 12:44:19.701915 LPDDR4 DRAM CONFIGURATION
4982 12:44:19.705705 ===================================
4983 12:44:19.706233 EX_ROW_EN[0] = 0x0
4984 12:44:19.708769 EX_ROW_EN[1] = 0x0
4985 12:44:19.709373 LP4Y_EN = 0x0
4986 12:44:19.712390 WORK_FSP = 0x0
4987 12:44:19.712956 WL = 0x3
4988 12:44:19.715197 RL = 0x3
4989 12:44:19.715664 BL = 0x2
4990 12:44:19.718769 RPST = 0x0
4991 12:44:19.719235 RD_PRE = 0x0
4992 12:44:19.721873 WR_PRE = 0x1
4993 12:44:19.722327 WR_PST = 0x0
4994 12:44:19.725218 DBI_WR = 0x0
4995 12:44:19.728843 DBI_RD = 0x0
4996 12:44:19.729417 OTF = 0x1
4997 12:44:19.732052 ===================================
4998 12:44:19.735442 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 12:44:19.738806 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 12:44:19.745519 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 12:44:19.748392 ===================================
5002 12:44:19.752236 LPDDR4 DRAM CONFIGURATION
5003 12:44:19.754887 ===================================
5004 12:44:19.755364 EX_ROW_EN[0] = 0x10
5005 12:44:19.758680 EX_ROW_EN[1] = 0x0
5006 12:44:19.759211 LP4Y_EN = 0x0
5007 12:44:19.761804 WORK_FSP = 0x0
5008 12:44:19.762364 WL = 0x3
5009 12:44:19.765163 RL = 0x3
5010 12:44:19.765742 BL = 0x2
5011 12:44:19.768680 RPST = 0x0
5012 12:44:19.769305 RD_PRE = 0x0
5013 12:44:19.771584 WR_PRE = 0x1
5014 12:44:19.772053 WR_PST = 0x0
5015 12:44:19.775163 DBI_WR = 0x0
5016 12:44:19.775789 DBI_RD = 0x0
5017 12:44:19.778636 OTF = 0x1
5018 12:44:19.781442 ===================================
5019 12:44:19.788365 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 12:44:19.791880 nWR fixed to 30
5021 12:44:19.795259 [ModeRegInit_LP4] CH0 RK0
5022 12:44:19.795799 [ModeRegInit_LP4] CH0 RK1
5023 12:44:19.798427 [ModeRegInit_LP4] CH1 RK0
5024 12:44:19.801340 [ModeRegInit_LP4] CH1 RK1
5025 12:44:19.801772 match AC timing 9
5026 12:44:19.808203 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 12:44:19.812102 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 12:44:19.815065 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 12:44:19.822582 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 12:44:19.824478 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 12:44:19.824915 ==
5032 12:44:19.828323 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 12:44:19.831797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 12:44:19.832383 ==
5035 12:44:19.838084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 12:44:19.844634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5037 12:44:19.847839 [CA 0] Center 38 (7~69) winsize 63
5038 12:44:19.851344 [CA 1] Center 38 (8~69) winsize 62
5039 12:44:19.854450 [CA 2] Center 35 (5~66) winsize 62
5040 12:44:19.858237 [CA 3] Center 34 (4~65) winsize 62
5041 12:44:19.861188 [CA 4] Center 34 (4~65) winsize 62
5042 12:44:19.864757 [CA 5] Center 33 (3~64) winsize 62
5043 12:44:19.865410
5044 12:44:19.867826 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5045 12:44:19.868401
5046 12:44:19.871262 [CATrainingPosCal] consider 1 rank data
5047 12:44:19.874412 u2DelayCellTimex100 = 270/100 ps
5048 12:44:19.877876 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5049 12:44:19.881112 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5050 12:44:19.884099 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5051 12:44:19.887675 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5052 12:44:19.891135 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5053 12:44:19.897450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5054 12:44:19.897972
5055 12:44:19.901156 CA PerBit enable=1, Macro0, CA PI delay=33
5056 12:44:19.901730
5057 12:44:19.904113 [CBTSetCACLKResult] CA Dly = 33
5058 12:44:19.904590 CS Dly: 6 (0~37)
5059 12:44:19.904966 ==
5060 12:44:19.908106 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 12:44:19.911020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 12:44:19.914084 ==
5063 12:44:19.917695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 12:44:19.924169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5065 12:44:19.927312 [CA 0] Center 38 (8~69) winsize 62
5066 12:44:19.930933 [CA 1] Center 38 (8~69) winsize 62
5067 12:44:19.933826 [CA 2] Center 36 (6~66) winsize 61
5068 12:44:19.937362 [CA 3] Center 35 (5~66) winsize 62
5069 12:44:19.940835 [CA 4] Center 34 (4~65) winsize 62
5070 12:44:19.944041 [CA 5] Center 34 (4~65) winsize 62
5071 12:44:19.944600
5072 12:44:19.947351 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5073 12:44:19.947881
5074 12:44:19.950886 [CATrainingPosCal] consider 2 rank data
5075 12:44:19.954006 u2DelayCellTimex100 = 270/100 ps
5076 12:44:19.957372 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5077 12:44:19.960951 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5078 12:44:19.964188 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5079 12:44:19.970710 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5080 12:44:19.973552 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5081 12:44:19.977309 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5082 12:44:19.977840
5083 12:44:19.980028 CA PerBit enable=1, Macro0, CA PI delay=34
5084 12:44:19.980556
5085 12:44:19.983907 [CBTSetCACLKResult] CA Dly = 34
5086 12:44:19.984435 CS Dly: 7 (0~39)
5087 12:44:19.984784
5088 12:44:19.987190 ----->DramcWriteLeveling(PI) begin...
5089 12:44:19.990679 ==
5090 12:44:19.993517 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 12:44:19.996776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 12:44:19.997473 ==
5093 12:44:19.999986 Write leveling (Byte 0): 30 => 30
5094 12:44:20.003382 Write leveling (Byte 1): 29 => 29
5095 12:44:20.006214 DramcWriteLeveling(PI) end<-----
5096 12:44:20.006638
5097 12:44:20.006977 ==
5098 12:44:20.009626 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 12:44:20.013219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 12:44:20.013756 ==
5101 12:44:20.016674 [Gating] SW mode calibration
5102 12:44:20.023086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 12:44:20.029819 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 12:44:20.033296 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5105 12:44:20.036566 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:44:20.043105 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 12:44:20.046324 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 12:44:20.049429 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 12:44:20.056208 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 12:44:20.059744 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
5111 12:44:20.062759 0 14 28 | B1->B0 | 3131 2323 | 0 0 | (0 0) (1 0)
5112 12:44:20.069512 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
5113 12:44:20.072687 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:44:20.075548 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 12:44:20.082640 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 12:44:20.086003 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 12:44:20.088881 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 12:44:20.095509 0 15 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5119 12:44:20.099176 0 15 28 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
5120 12:44:20.102503 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5121 12:44:20.109143 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:44:20.112452 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 12:44:20.115240 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 12:44:20.122182 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 12:44:20.125479 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 12:44:20.128833 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 12:44:20.135526 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5128 12:44:20.138798 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5129 12:44:20.142275 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:44:20.145392 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:44:20.152565 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:44:20.155674 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:44:20.158954 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:44:20.165605 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:44:20.169009 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:44:20.172182 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:44:20.178593 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:44:20.181846 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:44:20.185519 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:44:20.191710 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:44:20.195263 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:44:20.198342 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:44:20.205077 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 12:44:20.208413 Total UI for P1: 0, mck2ui 16
5145 12:44:20.211731 best dqsien dly found for B0: ( 1, 2, 26)
5146 12:44:20.214552 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 12:44:20.217838 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 12:44:20.221180 Total UI for P1: 0, mck2ui 16
5149 12:44:20.224624 best dqsien dly found for B1: ( 1, 2, 30)
5150 12:44:20.227837 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5151 12:44:20.234472 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5152 12:44:20.234941
5153 12:44:20.237703 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5154 12:44:20.240772 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5155 12:44:20.244463 [Gating] SW calibration Done
5156 12:44:20.245079 ==
5157 12:44:20.247762 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 12:44:20.251194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 12:44:20.251784 ==
5160 12:44:20.254489 RX Vref Scan: 0
5161 12:44:20.255036
5162 12:44:20.255385 RX Vref 0 -> 0, step: 1
5163 12:44:20.255707
5164 12:44:20.257465 RX Delay -80 -> 252, step: 8
5165 12:44:20.261124 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5166 12:44:20.267802 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5167 12:44:20.270976 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5168 12:44:20.274464 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5169 12:44:20.277542 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5170 12:44:20.281054 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5171 12:44:20.283839 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5172 12:44:20.290800 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5173 12:44:20.294023 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5174 12:44:20.296831 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5175 12:44:20.300523 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5176 12:44:20.303904 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5177 12:44:20.310925 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5178 12:44:20.313461 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5179 12:44:20.317026 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5180 12:44:20.320161 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5181 12:44:20.320640 ==
5182 12:44:20.324419 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 12:44:20.326807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 12:44:20.330007 ==
5185 12:44:20.330476 DQS Delay:
5186 12:44:20.330845 DQS0 = 0, DQS1 = 0
5187 12:44:20.333450 DQM Delay:
5188 12:44:20.333921 DQM0 = 106, DQM1 = 90
5189 12:44:20.336617 DQ Delay:
5190 12:44:20.340206 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5191 12:44:20.343272 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5192 12:44:20.346706 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5193 12:44:20.349900 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5194 12:44:20.350433
5195 12:44:20.350960
5196 12:44:20.351340 ==
5197 12:44:20.353417 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 12:44:20.356319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 12:44:20.356854 ==
5200 12:44:20.357239
5201 12:44:20.357587
5202 12:44:20.360214 TX Vref Scan disable
5203 12:44:20.363073 == TX Byte 0 ==
5204 12:44:20.366567 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5205 12:44:20.369461 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5206 12:44:20.372836 == TX Byte 1 ==
5207 12:44:20.376337 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5208 12:44:20.379374 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5209 12:44:20.379906 ==
5210 12:44:20.382334 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 12:44:20.389202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 12:44:20.389782 ==
5213 12:44:20.390163
5214 12:44:20.390514
5215 12:44:20.390848 TX Vref Scan disable
5216 12:44:20.393021 == TX Byte 0 ==
5217 12:44:20.395965 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5218 12:44:20.403030 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5219 12:44:20.403588 == TX Byte 1 ==
5220 12:44:20.406222 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5221 12:44:20.412736 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5222 12:44:20.413354
5223 12:44:20.413739 [DATLAT]
5224 12:44:20.414093 Freq=933, CH0 RK0
5225 12:44:20.414437
5226 12:44:20.416275 DATLAT Default: 0xd
5227 12:44:20.416834 0, 0xFFFF, sum = 0
5228 12:44:20.419299 1, 0xFFFF, sum = 0
5229 12:44:20.422639 2, 0xFFFF, sum = 0
5230 12:44:20.423204 3, 0xFFFF, sum = 0
5231 12:44:20.426347 4, 0xFFFF, sum = 0
5232 12:44:20.426917 5, 0xFFFF, sum = 0
5233 12:44:20.429292 6, 0xFFFF, sum = 0
5234 12:44:20.429770 7, 0xFFFF, sum = 0
5235 12:44:20.432695 8, 0xFFFF, sum = 0
5236 12:44:20.433302 9, 0xFFFF, sum = 0
5237 12:44:20.436015 10, 0x0, sum = 1
5238 12:44:20.436585 11, 0x0, sum = 2
5239 12:44:20.439113 12, 0x0, sum = 3
5240 12:44:20.439592 13, 0x0, sum = 4
5241 12:44:20.440029 best_step = 11
5242 12:44:20.442183
5243 12:44:20.442652 ==
5244 12:44:20.445486 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 12:44:20.449046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 12:44:20.449495 ==
5247 12:44:20.449936 RX Vref Scan: 1
5248 12:44:20.450351
5249 12:44:20.452551 RX Vref 0 -> 0, step: 1
5250 12:44:20.453141
5251 12:44:20.456001 RX Delay -53 -> 252, step: 4
5252 12:44:20.456555
5253 12:44:20.459109 Set Vref, RX VrefLevel [Byte0]: 56
5254 12:44:20.462138 [Byte1]: 48
5255 12:44:20.465854
5256 12:44:20.466394 Final RX Vref Byte 0 = 56 to rank0
5257 12:44:20.469265 Final RX Vref Byte 1 = 48 to rank0
5258 12:44:20.472198 Final RX Vref Byte 0 = 56 to rank1
5259 12:44:20.475551 Final RX Vref Byte 1 = 48 to rank1==
5260 12:44:20.478805 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 12:44:20.485583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 12:44:20.486174 ==
5263 12:44:20.486557 DQS Delay:
5264 12:44:20.486910 DQS0 = 0, DQS1 = 0
5265 12:44:20.488484 DQM Delay:
5266 12:44:20.489103 DQM0 = 108, DQM1 = 92
5267 12:44:20.492193 DQ Delay:
5268 12:44:20.495179 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5269 12:44:20.498527 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =116
5270 12:44:20.501953 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =90
5271 12:44:20.505135 DQ12 =96, DQ13 =96, DQ14 =104, DQ15 =100
5272 12:44:20.505739
5273 12:44:20.506119
5274 12:44:20.512029 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5275 12:44:20.515091 CH0 RK0: MR19=505, MR18=2622
5276 12:44:20.521610 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5277 12:44:20.522182
5278 12:44:20.524950 ----->DramcWriteLeveling(PI) begin...
5279 12:44:20.525568 ==
5280 12:44:20.528133 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 12:44:20.531614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 12:44:20.534913 ==
5283 12:44:20.535411 Write leveling (Byte 0): 32 => 32
5284 12:44:20.538176 Write leveling (Byte 1): 31 => 31
5285 12:44:20.541449 DramcWriteLeveling(PI) end<-----
5286 12:44:20.542038
5287 12:44:20.542421 ==
5288 12:44:20.544506 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 12:44:20.551464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 12:44:20.552047 ==
5291 12:44:20.552430 [Gating] SW mode calibration
5292 12:44:20.561308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 12:44:20.564925 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 12:44:20.571440 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 12:44:20.574211 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 12:44:20.578620 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 12:44:20.584469 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 12:44:20.587830 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 12:44:20.590763 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 12:44:20.597571 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5301 12:44:20.600898 0 14 28 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (1 0)
5302 12:44:20.604037 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 12:44:20.610793 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 12:44:20.613937 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 12:44:20.617361 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 12:44:20.623896 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 12:44:20.628063 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 12:44:20.630389 0 15 24 | B1->B0 | 2727 2b2b | 0 1 | (0 0) (1 1)
5309 12:44:20.637162 0 15 28 | B1->B0 | 3c3c 4241 | 0 1 | (0 0) (0 0)
5310 12:44:20.640131 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 12:44:20.643471 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:44:20.650232 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 12:44:20.653166 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 12:44:20.656433 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 12:44:20.663640 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 12:44:20.666934 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 12:44:20.670241 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5318 12:44:20.677053 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:44:20.680065 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:44:20.683273 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:44:20.689910 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:44:20.693307 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:44:20.696590 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:44:20.703419 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:44:20.706344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:44:20.709501 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:44:20.716371 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:44:20.719254 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:44:20.722763 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:44:20.729434 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:44:20.732307 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:44:20.735758 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:44:20.742405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 12:44:20.742826 Total UI for P1: 0, mck2ui 16
5335 12:44:20.749647 best dqsien dly found for B0: ( 1, 2, 26)
5336 12:44:20.750220 Total UI for P1: 0, mck2ui 16
5337 12:44:20.752707 best dqsien dly found for B1: ( 1, 2, 26)
5338 12:44:20.759248 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5339 12:44:20.762205 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5340 12:44:20.762670
5341 12:44:20.765678 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5342 12:44:20.769583 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5343 12:44:20.772486 [Gating] SW calibration Done
5344 12:44:20.773032 ==
5345 12:44:20.775154 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 12:44:20.778314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 12:44:20.778755 ==
5348 12:44:20.782147 RX Vref Scan: 0
5349 12:44:20.782579
5350 12:44:20.782940 RX Vref 0 -> 0, step: 1
5351 12:44:20.783264
5352 12:44:20.785156 RX Delay -80 -> 252, step: 8
5353 12:44:20.788660 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5354 12:44:20.795251 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5355 12:44:20.798549 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5356 12:44:20.801883 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5357 12:44:20.805595 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5358 12:44:20.808383 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5359 12:44:20.815469 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5360 12:44:20.818134 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5361 12:44:20.821593 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5362 12:44:20.825185 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5363 12:44:20.828109 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5364 12:44:20.831470 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5365 12:44:20.838428 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5366 12:44:20.841594 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5367 12:44:20.844669 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5368 12:44:20.848083 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5369 12:44:20.848556 ==
5370 12:44:20.851591 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 12:44:20.854756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 12:44:20.858051 ==
5373 12:44:20.858613 DQS Delay:
5374 12:44:20.858991 DQS0 = 0, DQS1 = 0
5375 12:44:20.861422 DQM Delay:
5376 12:44:20.861888 DQM0 = 104, DQM1 = 90
5377 12:44:20.864683 DQ Delay:
5378 12:44:20.867810 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5379 12:44:20.870963 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5380 12:44:20.874826 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5381 12:44:20.877876 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5382 12:44:20.878346
5383 12:44:20.878719
5384 12:44:20.879066 ==
5385 12:44:20.881013 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 12:44:20.884141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 12:44:20.884567 ==
5388 12:44:20.884904
5389 12:44:20.885287
5390 12:44:20.888011 TX Vref Scan disable
5391 12:44:20.888530 == TX Byte 0 ==
5392 12:44:20.894281 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5393 12:44:20.897419 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5394 12:44:20.901090 == TX Byte 1 ==
5395 12:44:20.904045 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5396 12:44:20.907496 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5397 12:44:20.907986 ==
5398 12:44:20.910713 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 12:44:20.914113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 12:44:20.917356 ==
5401 12:44:20.917978
5402 12:44:20.918357
5403 12:44:20.918708 TX Vref Scan disable
5404 12:44:20.920468 == TX Byte 0 ==
5405 12:44:20.924009 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5406 12:44:20.931271 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5407 12:44:20.932054 == TX Byte 1 ==
5408 12:44:20.934245 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5409 12:44:20.940646 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5410 12:44:20.941245
5411 12:44:20.941628 [DATLAT]
5412 12:44:20.941978 Freq=933, CH0 RK1
5413 12:44:20.942316
5414 12:44:20.943634 DATLAT Default: 0xb
5415 12:44:20.944103 0, 0xFFFF, sum = 0
5416 12:44:20.947063 1, 0xFFFF, sum = 0
5417 12:44:20.950400 2, 0xFFFF, sum = 0
5418 12:44:20.950851 3, 0xFFFF, sum = 0
5419 12:44:20.953997 4, 0xFFFF, sum = 0
5420 12:44:20.954528 5, 0xFFFF, sum = 0
5421 12:44:20.956946 6, 0xFFFF, sum = 0
5422 12:44:20.957401 7, 0xFFFF, sum = 0
5423 12:44:20.960203 8, 0xFFFF, sum = 0
5424 12:44:20.960726 9, 0xFFFF, sum = 0
5425 12:44:20.963624 10, 0x0, sum = 1
5426 12:44:20.964054 11, 0x0, sum = 2
5427 12:44:20.967028 12, 0x0, sum = 3
5428 12:44:20.967559 13, 0x0, sum = 4
5429 12:44:20.967911 best_step = 11
5430 12:44:20.970176
5431 12:44:20.970701 ==
5432 12:44:20.973650 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 12:44:20.977100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 12:44:20.977636 ==
5435 12:44:20.977982 RX Vref Scan: 0
5436 12:44:20.978300
5437 12:44:20.980314 RX Vref 0 -> 0, step: 1
5438 12:44:20.980833
5439 12:44:20.983377 RX Delay -53 -> 252, step: 4
5440 12:44:20.990107 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5441 12:44:20.993852 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5442 12:44:20.996595 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5443 12:44:20.999823 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5444 12:44:21.003201 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5445 12:44:21.009876 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5446 12:44:21.013070 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5447 12:44:21.016373 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5448 12:44:21.020138 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5449 12:44:21.022978 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5450 12:44:21.029260 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5451 12:44:21.032888 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5452 12:44:21.036066 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5453 12:44:21.039551 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5454 12:44:21.042687 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5455 12:44:21.049614 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5456 12:44:21.050142 ==
5457 12:44:21.052306 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 12:44:21.055843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 12:44:21.056275 ==
5460 12:44:21.056615 DQS Delay:
5461 12:44:21.059489 DQS0 = 0, DQS1 = 0
5462 12:44:21.060015 DQM Delay:
5463 12:44:21.062746 DQM0 = 104, DQM1 = 92
5464 12:44:21.063262 DQ Delay:
5465 12:44:21.066127 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5466 12:44:21.069345 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5467 12:44:21.072398 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90
5468 12:44:21.075797 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5469 12:44:21.076323
5470 12:44:21.076666
5471 12:44:21.085593 [DQSOSCAuto] RK1, (LSB)MR18= 0x2608, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5472 12:44:21.086155 CH0 RK1: MR19=505, MR18=2608
5473 12:44:21.092623 CH0_RK1: MR19=0x505, MR18=0x2608, DQSOSC=409, MR23=63, INC=64, DEC=43
5474 12:44:21.095633 [RxdqsGatingPostProcess] freq 933
5475 12:44:21.102417 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5476 12:44:21.105333 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 12:44:21.108655 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 12:44:21.112559 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 12:44:21.115604 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 12:44:21.118787 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 12:44:21.121849 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 12:44:21.122682 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 12:44:21.125355 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 12:44:21.128668 Pre-setting of DQS Precalculation
5485 12:44:21.135459 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5486 12:44:21.136027 ==
5487 12:44:21.138542 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 12:44:21.141608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 12:44:21.142084 ==
5490 12:44:21.148633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5491 12:44:21.155049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5492 12:44:21.158782 [CA 0] Center 37 (7~68) winsize 62
5493 12:44:21.161628 [CA 1] Center 37 (7~68) winsize 62
5494 12:44:21.165255 [CA 2] Center 35 (5~66) winsize 62
5495 12:44:21.168241 [CA 3] Center 35 (5~65) winsize 61
5496 12:44:21.171783 [CA 4] Center 35 (5~66) winsize 62
5497 12:44:21.174894 [CA 5] Center 34 (4~65) winsize 62
5498 12:44:21.175469
5499 12:44:21.178418 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5500 12:44:21.178988
5501 12:44:21.181748 [CATrainingPosCal] consider 1 rank data
5502 12:44:21.184790 u2DelayCellTimex100 = 270/100 ps
5503 12:44:21.187992 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5504 12:44:21.191050 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5505 12:44:21.194735 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5506 12:44:21.198066 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5507 12:44:21.201389 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5508 12:44:21.207875 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5509 12:44:21.208437
5510 12:44:21.211128 CA PerBit enable=1, Macro0, CA PI delay=34
5511 12:44:21.211706
5512 12:44:21.214677 [CBTSetCACLKResult] CA Dly = 34
5513 12:44:21.215146 CS Dly: 6 (0~37)
5514 12:44:21.215519 ==
5515 12:44:21.217465 Dram Type= 6, Freq= 0, CH_1, rank 1
5516 12:44:21.221370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 12:44:21.224333 ==
5518 12:44:21.227650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 12:44:21.234006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5520 12:44:21.237413 [CA 0] Center 38 (7~69) winsize 63
5521 12:44:21.240670 [CA 1] Center 38 (8~69) winsize 62
5522 12:44:21.244331 [CA 2] Center 35 (5~66) winsize 62
5523 12:44:21.247536 [CA 3] Center 35 (5~65) winsize 61
5524 12:44:21.250759 [CA 4] Center 35 (5~65) winsize 61
5525 12:44:21.254396 [CA 5] Center 35 (5~65) winsize 61
5526 12:44:21.254966
5527 12:44:21.257483 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5528 12:44:21.258120
5529 12:44:21.260352 [CATrainingPosCal] consider 2 rank data
5530 12:44:21.264025 u2DelayCellTimex100 = 270/100 ps
5531 12:44:21.268045 CA0 delay=37 (7~68),Diff = 2 PI (12 cell)
5532 12:44:21.270846 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5533 12:44:21.273756 CA2 delay=35 (5~66),Diff = 0 PI (0 cell)
5534 12:44:21.280523 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5535 12:44:21.283780 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5536 12:44:21.287396 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5537 12:44:21.287970
5538 12:44:21.290607 CA PerBit enable=1, Macro0, CA PI delay=35
5539 12:44:21.291079
5540 12:44:21.293792 [CBTSetCACLKResult] CA Dly = 35
5541 12:44:21.294363 CS Dly: 7 (0~39)
5542 12:44:21.294743
5543 12:44:21.296910 ----->DramcWriteLeveling(PI) begin...
5544 12:44:21.297409 ==
5545 12:44:21.300285 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 12:44:21.306982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 12:44:21.307571 ==
5548 12:44:21.310202 Write leveling (Byte 0): 29 => 29
5549 12:44:21.313282 Write leveling (Byte 1): 31 => 31
5550 12:44:21.316904 DramcWriteLeveling(PI) end<-----
5551 12:44:21.317552
5552 12:44:21.317995 ==
5553 12:44:21.320043 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 12:44:21.322990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 12:44:21.323650 ==
5556 12:44:21.326438 [Gating] SW mode calibration
5557 12:44:21.333349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5558 12:44:21.339562 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5559 12:44:21.343183 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 12:44:21.346377 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:44:21.352712 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 12:44:21.356185 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 12:44:21.359668 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 12:44:21.365961 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 12:44:21.369438 0 14 24 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 1)
5566 12:44:21.372905 0 14 28 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
5567 12:44:21.379769 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 12:44:21.382819 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:44:21.385909 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 12:44:21.389231 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 12:44:21.396098 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 12:44:21.399531 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 12:44:21.402486 0 15 24 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (0 0)
5574 12:44:21.409145 0 15 28 | B1->B0 | 3c3c 3e3e | 1 1 | (0 0) (0 0)
5575 12:44:21.412605 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 12:44:21.415864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 12:44:21.422256 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 12:44:21.425559 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 12:44:21.429187 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 12:44:21.435570 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 12:44:21.439440 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5582 12:44:21.442574 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:44:21.448896 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:44:21.452255 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:44:21.455272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:44:21.462072 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:44:21.465513 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:44:21.469136 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:44:21.475332 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:44:21.479024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:44:21.481850 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:44:21.488699 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:44:21.491825 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:44:21.495486 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:44:21.501843 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:44:21.505132 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5597 12:44:21.508204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5598 12:44:21.514951 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5599 12:44:21.518121 Total UI for P1: 0, mck2ui 16
5600 12:44:21.521508 best dqsien dly found for B0: ( 1, 2, 22)
5601 12:44:21.524586 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 12:44:21.528213 Total UI for P1: 0, mck2ui 16
5603 12:44:21.531543 best dqsien dly found for B1: ( 1, 2, 28)
5604 12:44:21.534419 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5605 12:44:21.537951 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5606 12:44:21.538419
5607 12:44:21.541076 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5608 12:44:21.544705 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5609 12:44:21.547481 [Gating] SW calibration Done
5610 12:44:21.547961 ==
5611 12:44:21.551100 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 12:44:21.557679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 12:44:21.558151 ==
5614 12:44:21.558546 RX Vref Scan: 0
5615 12:44:21.558900
5616 12:44:21.560697 RX Vref 0 -> 0, step: 1
5617 12:44:21.561182
5618 12:44:21.564109 RX Delay -80 -> 252, step: 8
5619 12:44:21.567903 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5620 12:44:21.571061 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5621 12:44:21.573946 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5622 12:44:21.577419 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5623 12:44:21.584533 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5624 12:44:21.587351 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5625 12:44:21.590803 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5626 12:44:21.594154 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5627 12:44:21.597120 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5628 12:44:21.600717 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5629 12:44:21.607241 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5630 12:44:21.610296 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5631 12:44:21.613474 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5632 12:44:21.617151 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5633 12:44:21.620410 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5634 12:44:21.627206 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5635 12:44:21.627791 ==
5636 12:44:21.630477 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 12:44:21.633794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 12:44:21.634377 ==
5639 12:44:21.634763 DQS Delay:
5640 12:44:21.636948 DQS0 = 0, DQS1 = 0
5641 12:44:21.637490 DQM Delay:
5642 12:44:21.640480 DQM0 = 101, DQM1 = 95
5643 12:44:21.641017 DQ Delay:
5644 12:44:21.643328 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5645 12:44:21.646847 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5646 12:44:21.650263 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5647 12:44:21.653544 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5648 12:44:21.654128
5649 12:44:21.654517
5650 12:44:21.654868 ==
5651 12:44:21.657117 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 12:44:21.663103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 12:44:21.663586 ==
5654 12:44:21.663965
5655 12:44:21.664319
5656 12:44:21.664654 TX Vref Scan disable
5657 12:44:21.666638 == TX Byte 0 ==
5658 12:44:21.669848 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5659 12:44:21.676652 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5660 12:44:21.677249 == TX Byte 1 ==
5661 12:44:21.680149 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5662 12:44:21.686489 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5663 12:44:21.687056 ==
5664 12:44:21.689917 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 12:44:21.692847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 12:44:21.693347 ==
5667 12:44:21.693728
5668 12:44:21.694083
5669 12:44:21.696514 TX Vref Scan disable
5670 12:44:21.697012 == TX Byte 0 ==
5671 12:44:21.703025 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5672 12:44:21.706255 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5673 12:44:21.709293 == TX Byte 1 ==
5674 12:44:21.713062 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5675 12:44:21.716521 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5676 12:44:21.717131
5677 12:44:21.717514 [DATLAT]
5678 12:44:21.719620 Freq=933, CH1 RK0
5679 12:44:21.720206
5680 12:44:21.720587 DATLAT Default: 0xd
5681 12:44:21.722847 0, 0xFFFF, sum = 0
5682 12:44:21.726157 1, 0xFFFF, sum = 0
5683 12:44:21.726638 2, 0xFFFF, sum = 0
5684 12:44:21.729185 3, 0xFFFF, sum = 0
5685 12:44:21.729682 4, 0xFFFF, sum = 0
5686 12:44:21.733046 5, 0xFFFF, sum = 0
5687 12:44:21.733630 6, 0xFFFF, sum = 0
5688 12:44:21.736272 7, 0xFFFF, sum = 0
5689 12:44:21.736879 8, 0xFFFF, sum = 0
5690 12:44:21.739444 9, 0xFFFF, sum = 0
5691 12:44:21.740033 10, 0x0, sum = 1
5692 12:44:21.742943 11, 0x0, sum = 2
5693 12:44:21.743525 12, 0x0, sum = 3
5694 12:44:21.745970 13, 0x0, sum = 4
5695 12:44:21.746454 best_step = 11
5696 12:44:21.746829
5697 12:44:21.747183 ==
5698 12:44:21.749356 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 12:44:21.752419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 12:44:21.752899 ==
5701 12:44:21.756060 RX Vref Scan: 1
5702 12:44:21.756632
5703 12:44:21.759362 RX Vref 0 -> 0, step: 1
5704 12:44:21.759849
5705 12:44:21.760230 RX Delay -53 -> 252, step: 4
5706 12:44:21.760586
5707 12:44:21.762547 Set Vref, RX VrefLevel [Byte0]: 51
5708 12:44:21.765519 [Byte1]: 52
5709 12:44:21.771019
5710 12:44:21.771584 Final RX Vref Byte 0 = 51 to rank0
5711 12:44:21.773573 Final RX Vref Byte 1 = 52 to rank0
5712 12:44:21.777232 Final RX Vref Byte 0 = 51 to rank1
5713 12:44:21.780483 Final RX Vref Byte 1 = 52 to rank1==
5714 12:44:21.783867 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 12:44:21.790254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 12:44:21.790888 ==
5717 12:44:21.791448 DQS Delay:
5718 12:44:21.793498 DQS0 = 0, DQS1 = 0
5719 12:44:21.793973 DQM Delay:
5720 12:44:21.794350 DQM0 = 104, DQM1 = 96
5721 12:44:21.797108 DQ Delay:
5722 12:44:21.800303 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5723 12:44:21.803781 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =100
5724 12:44:21.806854 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =92
5725 12:44:21.810005 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5726 12:44:21.810496
5727 12:44:21.810872
5728 12:44:21.820506 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5729 12:44:21.821139 CH1 RK0: MR19=505, MR18=1A33
5730 12:44:21.826445 CH1_RK0: MR19=0x505, MR18=0x1A33, DQSOSC=405, MR23=63, INC=66, DEC=44
5731 12:44:21.827022
5732 12:44:21.829665 ----->DramcWriteLeveling(PI) begin...
5733 12:44:21.830150 ==
5734 12:44:21.833488 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 12:44:21.840517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:44:21.841161 ==
5737 12:44:21.843208 Write leveling (Byte 0): 29 => 29
5738 12:44:21.843775 Write leveling (Byte 1): 30 => 30
5739 12:44:21.846332 DramcWriteLeveling(PI) end<-----
5740 12:44:21.846811
5741 12:44:21.847194 ==
5742 12:44:21.849822 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 12:44:21.856377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 12:44:21.856945 ==
5745 12:44:21.859803 [Gating] SW mode calibration
5746 12:44:21.866057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5747 12:44:21.869490 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5748 12:44:21.876163 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5749 12:44:21.879430 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 12:44:21.882475 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 12:44:21.889544 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 12:44:21.892376 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 12:44:21.896120 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 12:44:21.902740 0 14 24 | B1->B0 | 2f2f 3434 | 0 1 | (1 0) (1 0)
5755 12:44:21.905872 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5756 12:44:21.909575 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5757 12:44:21.915817 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 12:44:21.918816 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 12:44:21.922357 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 12:44:21.928814 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 12:44:21.932367 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 12:44:21.935877 0 15 24 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
5763 12:44:21.942115 0 15 28 | B1->B0 | 4040 3737 | 0 1 | (0 0) (0 0)
5764 12:44:21.945756 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 12:44:21.948461 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:44:21.955977 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 12:44:21.958393 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 12:44:21.961658 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 12:44:21.968622 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 12:44:21.972108 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5771 12:44:21.975235 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5772 12:44:21.982147 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:44:21.984733 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:44:21.988679 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:44:21.994885 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:44:21.998203 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:44:22.001579 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:44:22.008412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:44:22.011406 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:44:22.015092 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:44:22.021359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:44:22.024962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:44:22.027809 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:44:22.035028 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:44:22.037564 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:44:22.041254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:44:22.047997 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5788 12:44:22.048577 Total UI for P1: 0, mck2ui 16
5789 12:44:22.054344 best dqsien dly found for B1: ( 1, 2, 26)
5790 12:44:22.057919 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 12:44:22.061033 Total UI for P1: 0, mck2ui 16
5792 12:44:22.064197 best dqsien dly found for B0: ( 1, 2, 28)
5793 12:44:22.067575 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5794 12:44:22.071214 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5795 12:44:22.071785
5796 12:44:22.074559 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5797 12:44:22.077522 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5798 12:44:22.080793 [Gating] SW calibration Done
5799 12:44:22.081421 ==
5800 12:44:22.084458 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 12:44:22.087314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 12:44:22.091007 ==
5803 12:44:22.091581 RX Vref Scan: 0
5804 12:44:22.091965
5805 12:44:22.093565 RX Vref 0 -> 0, step: 1
5806 12:44:22.094038
5807 12:44:22.097439 RX Delay -80 -> 252, step: 8
5808 12:44:22.100766 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5809 12:44:22.103686 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5810 12:44:22.107321 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5811 12:44:22.110498 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5812 12:44:22.117312 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5813 12:44:22.119972 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5814 12:44:22.123693 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5815 12:44:22.126754 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5816 12:44:22.130270 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5817 12:44:22.133865 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5818 12:44:22.140254 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5819 12:44:22.143781 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5820 12:44:22.147067 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5821 12:44:22.150183 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5822 12:44:22.153537 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5823 12:44:22.160013 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5824 12:44:22.160666 ==
5825 12:44:22.163390 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 12:44:22.166658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 12:44:22.167265 ==
5828 12:44:22.167695 DQS Delay:
5829 12:44:22.170158 DQS0 = 0, DQS1 = 0
5830 12:44:22.170729 DQM Delay:
5831 12:44:22.173380 DQM0 = 103, DQM1 = 96
5832 12:44:22.173954 DQ Delay:
5833 12:44:22.176837 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5834 12:44:22.179885 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5835 12:44:22.183516 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5836 12:44:22.186122 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =107
5837 12:44:22.186601
5838 12:44:22.186979
5839 12:44:22.187329 ==
5840 12:44:22.189676 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 12:44:22.196504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 12:44:22.197152 ==
5843 12:44:22.197551
5844 12:44:22.197905
5845 12:44:22.198243 TX Vref Scan disable
5846 12:44:22.199885 == TX Byte 0 ==
5847 12:44:22.203176 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5848 12:44:22.209818 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5849 12:44:22.210404 == TX Byte 1 ==
5850 12:44:22.213613 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5851 12:44:22.219709 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5852 12:44:22.220313 ==
5853 12:44:22.223425 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 12:44:22.226677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 12:44:22.227260 ==
5856 12:44:22.227644
5857 12:44:22.228001
5858 12:44:22.229259 TX Vref Scan disable
5859 12:44:22.229738 == TX Byte 0 ==
5860 12:44:22.236514 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5861 12:44:22.239530 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5862 12:44:22.240009 == TX Byte 1 ==
5863 12:44:22.245970 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5864 12:44:22.249172 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5865 12:44:22.249654
5866 12:44:22.250037 [DATLAT]
5867 12:44:22.253007 Freq=933, CH1 RK1
5868 12:44:22.253661
5869 12:44:22.254053 DATLAT Default: 0xb
5870 12:44:22.255897 0, 0xFFFF, sum = 0
5871 12:44:22.256489 1, 0xFFFF, sum = 0
5872 12:44:22.259550 2, 0xFFFF, sum = 0
5873 12:44:22.262813 3, 0xFFFF, sum = 0
5874 12:44:22.263402 4, 0xFFFF, sum = 0
5875 12:44:22.266125 5, 0xFFFF, sum = 0
5876 12:44:22.266712 6, 0xFFFF, sum = 0
5877 12:44:22.269618 7, 0xFFFF, sum = 0
5878 12:44:22.270201 8, 0xFFFF, sum = 0
5879 12:44:22.272571 9, 0xFFFF, sum = 0
5880 12:44:22.273186 10, 0x0, sum = 1
5881 12:44:22.275911 11, 0x0, sum = 2
5882 12:44:22.276500 12, 0x0, sum = 3
5883 12:44:22.279421 13, 0x0, sum = 4
5884 12:44:22.280004 best_step = 11
5885 12:44:22.280384
5886 12:44:22.280739 ==
5887 12:44:22.282462 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 12:44:22.285639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 12:44:22.286181 ==
5890 12:44:22.289083 RX Vref Scan: 0
5891 12:44:22.289732
5892 12:44:22.292439 RX Vref 0 -> 0, step: 1
5893 12:44:22.293048
5894 12:44:22.293433 RX Delay -53 -> 252, step: 4
5895 12:44:22.300126 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5896 12:44:22.303645 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5897 12:44:22.307015 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5898 12:44:22.310287 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5899 12:44:22.313764 iDelay=199, Bit 4, Center 104 (23 ~ 186) 164
5900 12:44:22.319825 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5901 12:44:22.323460 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5902 12:44:22.326788 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5903 12:44:22.330308 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5904 12:44:22.333648 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5905 12:44:22.339825 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5906 12:44:22.343100 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5907 12:44:22.346399 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5908 12:44:22.349849 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5909 12:44:22.353251 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5910 12:44:22.359663 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5911 12:44:22.360249 ==
5912 12:44:22.362988 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 12:44:22.366820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 12:44:22.367412 ==
5915 12:44:22.367794 DQS Delay:
5916 12:44:22.369785 DQS0 = 0, DQS1 = 0
5917 12:44:22.370259 DQM Delay:
5918 12:44:22.373157 DQM0 = 104, DQM1 = 97
5919 12:44:22.373735 DQ Delay:
5920 12:44:22.376163 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =106
5921 12:44:22.379484 DQ4 =104, DQ5 =114, DQ6 =112, DQ7 =102
5922 12:44:22.382820 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5923 12:44:22.386266 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =108
5924 12:44:22.386845
5925 12:44:22.387227
5926 12:44:22.395771 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5927 12:44:22.399215 CH1 RK1: MR19=504, MR18=22FF
5928 12:44:22.402860 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
5929 12:44:22.405873 [RxdqsGatingPostProcess] freq 933
5930 12:44:22.412548 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5931 12:44:22.416252 best DQS0 dly(2T, 0.5T) = (0, 10)
5932 12:44:22.419112 best DQS1 dly(2T, 0.5T) = (0, 10)
5933 12:44:22.422127 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5934 12:44:22.425752 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5935 12:44:22.428941 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 12:44:22.432017 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 12:44:22.435695 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 12:44:22.438867 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 12:44:22.442363 Pre-setting of DQS Precalculation
5940 12:44:22.445257 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5941 12:44:22.451989 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5942 12:44:22.462220 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5943 12:44:22.462799
5944 12:44:22.463179
5945 12:44:22.463532 [Calibration Summary] 1866 Mbps
5946 12:44:22.464899 CH 0, Rank 0
5947 12:44:22.465427 SW Impedance : PASS
5948 12:44:22.469024 DUTY Scan : NO K
5949 12:44:22.472267 ZQ Calibration : PASS
5950 12:44:22.472834 Jitter Meter : NO K
5951 12:44:22.475403 CBT Training : PASS
5952 12:44:22.478923 Write leveling : PASS
5953 12:44:22.479496 RX DQS gating : PASS
5954 12:44:22.482095 RX DQ/DQS(RDDQC) : PASS
5955 12:44:22.485275 TX DQ/DQS : PASS
5956 12:44:22.485858 RX DATLAT : PASS
5957 12:44:22.488788 RX DQ/DQS(Engine): PASS
5958 12:44:22.492425 TX OE : NO K
5959 12:44:22.493035 All Pass.
5960 12:44:22.493422
5961 12:44:22.493779 CH 0, Rank 1
5962 12:44:22.495052 SW Impedance : PASS
5963 12:44:22.498375 DUTY Scan : NO K
5964 12:44:22.499109 ZQ Calibration : PASS
5965 12:44:22.501863 Jitter Meter : NO K
5966 12:44:22.505208 CBT Training : PASS
5967 12:44:22.505787 Write leveling : PASS
5968 12:44:22.509124 RX DQS gating : PASS
5969 12:44:22.509915 RX DQ/DQS(RDDQC) : PASS
5970 12:44:22.511882 TX DQ/DQS : PASS
5971 12:44:22.515310 RX DATLAT : PASS
5972 12:44:22.515891 RX DQ/DQS(Engine): PASS
5973 12:44:22.518556 TX OE : NO K
5974 12:44:22.519137 All Pass.
5975 12:44:22.519518
5976 12:44:22.521522 CH 1, Rank 0
5977 12:44:22.521998 SW Impedance : PASS
5978 12:44:22.525099 DUTY Scan : NO K
5979 12:44:22.528592 ZQ Calibration : PASS
5980 12:44:22.529118 Jitter Meter : NO K
5981 12:44:22.531367 CBT Training : PASS
5982 12:44:22.535231 Write leveling : PASS
5983 12:44:22.535704 RX DQS gating : PASS
5984 12:44:22.538082 RX DQ/DQS(RDDQC) : PASS
5985 12:44:22.541266 TX DQ/DQS : PASS
5986 12:44:22.541743 RX DATLAT : PASS
5987 12:44:22.544972 RX DQ/DQS(Engine): PASS
5988 12:44:22.548408 TX OE : NO K
5989 12:44:22.548952 All Pass.
5990 12:44:22.549347
5991 12:44:22.549668 CH 1, Rank 1
5992 12:44:22.551801 SW Impedance : PASS
5993 12:44:22.554828 DUTY Scan : NO K
5994 12:44:22.555260 ZQ Calibration : PASS
5995 12:44:22.558133 Jitter Meter : NO K
5996 12:44:22.561547 CBT Training : PASS
5997 12:44:22.562074 Write leveling : PASS
5998 12:44:22.565202 RX DQS gating : PASS
5999 12:44:22.567779 RX DQ/DQS(RDDQC) : PASS
6000 12:44:22.568211 TX DQ/DQS : PASS
6001 12:44:22.571727 RX DATLAT : PASS
6002 12:44:22.572270 RX DQ/DQS(Engine): PASS
6003 12:44:22.574591 TX OE : NO K
6004 12:44:22.575134 All Pass.
6005 12:44:22.575483
6006 12:44:22.578072 DramC Write-DBI off
6007 12:44:22.581435 PER_BANK_REFRESH: Hybrid Mode
6008 12:44:22.581976 TX_TRACKING: ON
6009 12:44:22.591232 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6010 12:44:22.594298 [FAST_K] Save calibration result to emmc
6011 12:44:22.597614 dramc_set_vcore_voltage set vcore to 650000
6012 12:44:22.600904 Read voltage for 400, 6
6013 12:44:22.601524 Vio18 = 0
6014 12:44:22.604369 Vcore = 650000
6015 12:44:22.605021 Vdram = 0
6016 12:44:22.605426 Vddq = 0
6017 12:44:22.605780 Vmddr = 0
6018 12:44:22.610557 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6019 12:44:22.617155 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6020 12:44:22.617632 MEM_TYPE=3, freq_sel=20
6021 12:44:22.620705 sv_algorithm_assistance_LP4_800
6022 12:44:22.624247 ============ PULL DRAM RESETB DOWN ============
6023 12:44:22.630309 ========== PULL DRAM RESETB DOWN end =========
6024 12:44:22.633583 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6025 12:44:22.637183 ===================================
6026 12:44:22.640567 LPDDR4 DRAM CONFIGURATION
6027 12:44:22.643741 ===================================
6028 12:44:22.644173 EX_ROW_EN[0] = 0x0
6029 12:44:22.647101 EX_ROW_EN[1] = 0x0
6030 12:44:22.650173 LP4Y_EN = 0x0
6031 12:44:22.650649 WORK_FSP = 0x0
6032 12:44:22.653643 WL = 0x2
6033 12:44:22.654063 RL = 0x2
6034 12:44:22.656821 BL = 0x2
6035 12:44:22.657287 RPST = 0x0
6036 12:44:22.660540 RD_PRE = 0x0
6037 12:44:22.661110 WR_PRE = 0x1
6038 12:44:22.663500 WR_PST = 0x0
6039 12:44:22.663922 DBI_WR = 0x0
6040 12:44:22.666831 DBI_RD = 0x0
6041 12:44:22.667252 OTF = 0x1
6042 12:44:22.669870 ===================================
6043 12:44:22.673287 ===================================
6044 12:44:22.676707 ANA top config
6045 12:44:22.679985 ===================================
6046 12:44:22.680413 DLL_ASYNC_EN = 0
6047 12:44:22.683117 ALL_SLAVE_EN = 1
6048 12:44:22.686732 NEW_RANK_MODE = 1
6049 12:44:22.690406 DLL_IDLE_MODE = 1
6050 12:44:22.693363 LP45_APHY_COMB_EN = 1
6051 12:44:22.693897 TX_ODT_DIS = 1
6052 12:44:22.696617 NEW_8X_MODE = 1
6053 12:44:22.699930 ===================================
6054 12:44:22.703278 ===================================
6055 12:44:22.706389 data_rate = 800
6056 12:44:22.709627 CKR = 1
6057 12:44:22.713179 DQ_P2S_RATIO = 4
6058 12:44:22.716471 ===================================
6059 12:44:22.719545 CA_P2S_RATIO = 4
6060 12:44:22.720015 DQ_CA_OPEN = 0
6061 12:44:22.723667 DQ_SEMI_OPEN = 1
6062 12:44:22.726357 CA_SEMI_OPEN = 1
6063 12:44:22.729719 CA_FULL_RATE = 0
6064 12:44:22.732904 DQ_CKDIV4_EN = 0
6065 12:44:22.736348 CA_CKDIV4_EN = 1
6066 12:44:22.736881 CA_PREDIV_EN = 0
6067 12:44:22.739507 PH8_DLY = 0
6068 12:44:22.742810 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6069 12:44:22.746248 DQ_AAMCK_DIV = 0
6070 12:44:22.749102 CA_AAMCK_DIV = 0
6071 12:44:22.752747 CA_ADMCK_DIV = 4
6072 12:44:22.753218 DQ_TRACK_CA_EN = 0
6073 12:44:22.755907 CA_PICK = 800
6074 12:44:22.759564 CA_MCKIO = 400
6075 12:44:22.762554 MCKIO_SEMI = 400
6076 12:44:22.765568 PLL_FREQ = 3016
6077 12:44:22.769789 DQ_UI_PI_RATIO = 32
6078 12:44:22.772527 CA_UI_PI_RATIO = 32
6079 12:44:22.775758 ===================================
6080 12:44:22.778882 ===================================
6081 12:44:22.779329 memory_type:LPDDR4
6082 12:44:22.782211 GP_NUM : 10
6083 12:44:22.785302 SRAM_EN : 1
6084 12:44:22.785728 MD32_EN : 0
6085 12:44:22.788906 ===================================
6086 12:44:22.792013 [ANA_INIT] >>>>>>>>>>>>>>
6087 12:44:22.795769 <<<<<< [CONFIGURE PHASE]: ANA_TX
6088 12:44:22.798512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6089 12:44:22.802162 ===================================
6090 12:44:22.805328 data_rate = 800,PCW = 0X7400
6091 12:44:22.808431 ===================================
6092 12:44:22.811915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6093 12:44:22.815373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 12:44:22.828525 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 12:44:22.831987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6096 12:44:22.835689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6097 12:44:22.838457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6098 12:44:22.841803 [ANA_INIT] flow start
6099 12:44:22.845431 [ANA_INIT] PLL >>>>>>>>
6100 12:44:22.846024 [ANA_INIT] PLL <<<<<<<<
6101 12:44:22.848403 [ANA_INIT] MIDPI >>>>>>>>
6102 12:44:22.851682 [ANA_INIT] MIDPI <<<<<<<<
6103 12:44:22.852305 [ANA_INIT] DLL >>>>>>>>
6104 12:44:22.854804 [ANA_INIT] flow end
6105 12:44:22.858187 ============ LP4 DIFF to SE enter ============
6106 12:44:22.864475 ============ LP4 DIFF to SE exit ============
6107 12:44:22.865147 [ANA_INIT] <<<<<<<<<<<<<
6108 12:44:22.867923 [Flow] Enable top DCM control >>>>>
6109 12:44:22.871168 [Flow] Enable top DCM control <<<<<
6110 12:44:22.874891 Enable DLL master slave shuffle
6111 12:44:22.881418 ==============================================================
6112 12:44:22.881861 Gating Mode config
6113 12:44:22.887827 ==============================================================
6114 12:44:22.891466 Config description:
6115 12:44:22.901253 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6116 12:44:22.907957 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6117 12:44:22.910877 SELPH_MODE 0: By rank 1: By Phase
6118 12:44:22.917520 ==============================================================
6119 12:44:22.920884 GAT_TRACK_EN = 0
6120 12:44:22.924304 RX_GATING_MODE = 2
6121 12:44:22.924839 RX_GATING_TRACK_MODE = 2
6122 12:44:22.927262 SELPH_MODE = 1
6123 12:44:22.930514 PICG_EARLY_EN = 1
6124 12:44:22.934210 VALID_LAT_VALUE = 1
6125 12:44:22.940813 ==============================================================
6126 12:44:22.943994 Enter into Gating configuration >>>>
6127 12:44:22.947294 Exit from Gating configuration <<<<
6128 12:44:22.950348 Enter into DVFS_PRE_config >>>>>
6129 12:44:22.960292 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6130 12:44:22.963706 Exit from DVFS_PRE_config <<<<<
6131 12:44:22.967330 Enter into PICG configuration >>>>
6132 12:44:22.970430 Exit from PICG configuration <<<<
6133 12:44:22.973476 [RX_INPUT] configuration >>>>>
6134 12:44:22.977266 [RX_INPUT] configuration <<<<<
6135 12:44:22.980170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6136 12:44:22.987078 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6137 12:44:22.993603 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 12:44:22.999994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 12:44:23.007032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 12:44:23.009864 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 12:44:23.016284 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6142 12:44:23.019710 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6143 12:44:23.023405 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6144 12:44:23.026175 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6145 12:44:23.033403 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6146 12:44:23.036343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6147 12:44:23.039256 ===================================
6148 12:44:23.042692 LPDDR4 DRAM CONFIGURATION
6149 12:44:23.046172 ===================================
6150 12:44:23.046704 EX_ROW_EN[0] = 0x0
6151 12:44:23.049233 EX_ROW_EN[1] = 0x0
6152 12:44:23.049895 LP4Y_EN = 0x0
6153 12:44:23.052665 WORK_FSP = 0x0
6154 12:44:23.053201 WL = 0x2
6155 12:44:23.056214 RL = 0x2
6156 12:44:23.059584 BL = 0x2
6157 12:44:23.060158 RPST = 0x0
6158 12:44:23.062716 RD_PRE = 0x0
6159 12:44:23.063170 WR_PRE = 0x1
6160 12:44:23.065684 WR_PST = 0x0
6161 12:44:23.066113 DBI_WR = 0x0
6162 12:44:23.069358 DBI_RD = 0x0
6163 12:44:23.069894 OTF = 0x1
6164 12:44:23.072735 ===================================
6165 12:44:23.076037 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6166 12:44:23.082095 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6167 12:44:23.085550 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 12:44:23.088932 ===================================
6169 12:44:23.092350 LPDDR4 DRAM CONFIGURATION
6170 12:44:23.095489 ===================================
6171 12:44:23.096032 EX_ROW_EN[0] = 0x10
6172 12:44:23.099509 EX_ROW_EN[1] = 0x0
6173 12:44:23.100152 LP4Y_EN = 0x0
6174 12:44:23.102112 WORK_FSP = 0x0
6175 12:44:23.102645 WL = 0x2
6176 12:44:23.105647 RL = 0x2
6177 12:44:23.108751 BL = 0x2
6178 12:44:23.109350 RPST = 0x0
6179 12:44:23.111769 RD_PRE = 0x0
6180 12:44:23.112201 WR_PRE = 0x1
6181 12:44:23.115582 WR_PST = 0x0
6182 12:44:23.116116 DBI_WR = 0x0
6183 12:44:23.118745 DBI_RD = 0x0
6184 12:44:23.119263 OTF = 0x1
6185 12:44:23.121916 ===================================
6186 12:44:23.128711 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6187 12:44:23.133012 nWR fixed to 30
6188 12:44:23.136075 [ModeRegInit_LP4] CH0 RK0
6189 12:44:23.136597 [ModeRegInit_LP4] CH0 RK1
6190 12:44:23.139471 [ModeRegInit_LP4] CH1 RK0
6191 12:44:23.142421 [ModeRegInit_LP4] CH1 RK1
6192 12:44:23.142987 match AC timing 19
6193 12:44:23.149213 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6194 12:44:23.152665 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6195 12:44:23.156146 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6196 12:44:23.162661 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6197 12:44:23.165804 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6198 12:44:23.166370 ==
6199 12:44:23.169407 Dram Type= 6, Freq= 0, CH_0, rank 0
6200 12:44:23.172135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6201 12:44:23.172631 ==
6202 12:44:23.178757 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6203 12:44:23.185351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6204 12:44:23.188790 [CA 0] Center 36 (8~64) winsize 57
6205 12:44:23.192003 [CA 1] Center 36 (8~64) winsize 57
6206 12:44:23.195421 [CA 2] Center 36 (8~64) winsize 57
6207 12:44:23.198507 [CA 3] Center 36 (8~64) winsize 57
6208 12:44:23.198997 [CA 4] Center 36 (8~64) winsize 57
6209 12:44:23.202247 [CA 5] Center 36 (8~64) winsize 57
6210 12:44:23.202830
6211 12:44:23.208615 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6212 12:44:23.209085
6213 12:44:23.211949 [CATrainingPosCal] consider 1 rank data
6214 12:44:23.215227 u2DelayCellTimex100 = 270/100 ps
6215 12:44:23.219308 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 12:44:23.221778 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 12:44:23.225488 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 12:44:23.228667 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 12:44:23.232197 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 12:44:23.235591 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 12:44:23.236159
6222 12:44:23.238277 CA PerBit enable=1, Macro0, CA PI delay=36
6223 12:44:23.238749
6224 12:44:23.241572 [CBTSetCACLKResult] CA Dly = 36
6225 12:44:23.245202 CS Dly: 1 (0~32)
6226 12:44:23.245748 ==
6227 12:44:23.248416 Dram Type= 6, Freq= 0, CH_0, rank 1
6228 12:44:23.251843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6229 12:44:23.252424 ==
6230 12:44:23.258339 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6231 12:44:23.264891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6232 12:44:23.268628 [CA 0] Center 36 (8~64) winsize 57
6233 12:44:23.269239 [CA 1] Center 36 (8~64) winsize 57
6234 12:44:23.271747 [CA 2] Center 36 (8~64) winsize 57
6235 12:44:23.274740 [CA 3] Center 36 (8~64) winsize 57
6236 12:44:23.278254 [CA 4] Center 36 (8~64) winsize 57
6237 12:44:23.281753 [CA 5] Center 36 (8~64) winsize 57
6238 12:44:23.282222
6239 12:44:23.284735 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6240 12:44:23.285296
6241 12:44:23.292047 [CATrainingPosCal] consider 2 rank data
6242 12:44:23.292631 u2DelayCellTimex100 = 270/100 ps
6243 12:44:23.298053 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:44:23.301570 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:44:23.304350 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:44:23.307762 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:44:23.311339 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:44:23.314432 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:44:23.314860
6250 12:44:23.317825 CA PerBit enable=1, Macro0, CA PI delay=36
6251 12:44:23.318299
6252 12:44:23.321107 [CBTSetCACLKResult] CA Dly = 36
6253 12:44:23.324337 CS Dly: 1 (0~32)
6254 12:44:23.324859
6255 12:44:23.327393 ----->DramcWriteLeveling(PI) begin...
6256 12:44:23.327819 ==
6257 12:44:23.331184 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 12:44:23.333934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 12:44:23.334526 ==
6260 12:44:23.337417 Write leveling (Byte 0): 40 => 8
6261 12:44:23.340966 Write leveling (Byte 1): 32 => 0
6262 12:44:23.343884 DramcWriteLeveling(PI) end<-----
6263 12:44:23.344311
6264 12:44:23.344650 ==
6265 12:44:23.347512 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 12:44:23.350761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 12:44:23.351242 ==
6268 12:44:23.353757 [Gating] SW mode calibration
6269 12:44:23.360660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6270 12:44:23.367068 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6271 12:44:23.370491 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 12:44:23.373465 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 12:44:23.380534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 12:44:23.383233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 12:44:23.389603 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 12:44:23.393142 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 12:44:23.397280 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 12:44:23.403100 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 12:44:23.406438 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 12:44:23.409435 Total UI for P1: 0, mck2ui 16
6281 12:44:23.412679 best dqsien dly found for B0: ( 0, 14, 24)
6282 12:44:23.416228 Total UI for P1: 0, mck2ui 16
6283 12:44:23.419833 best dqsien dly found for B1: ( 0, 14, 24)
6284 12:44:23.422725 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6285 12:44:23.425986 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6286 12:44:23.426462
6287 12:44:23.429542 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 12:44:23.432729 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 12:44:23.436447 [Gating] SW calibration Done
6290 12:44:23.436918 ==
6291 12:44:23.439280 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 12:44:23.442472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 12:44:23.445973 ==
6294 12:44:23.446447 RX Vref Scan: 0
6295 12:44:23.446826
6296 12:44:23.449125 RX Vref 0 -> 0, step: 1
6297 12:44:23.449599
6298 12:44:23.452393 RX Delay -410 -> 252, step: 16
6299 12:44:23.455700 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6300 12:44:23.459145 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6301 12:44:23.462198 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6302 12:44:23.469121 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6303 12:44:23.472119 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6304 12:44:23.476000 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6305 12:44:23.479034 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6306 12:44:23.485530 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6307 12:44:23.488759 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6308 12:44:23.492240 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6309 12:44:23.495356 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6310 12:44:23.502043 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6311 12:44:23.505216 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6312 12:44:23.508634 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6313 12:44:23.515269 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6314 12:44:23.518689 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6315 12:44:23.519153 ==
6316 12:44:23.521839 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 12:44:23.525157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 12:44:23.525719 ==
6319 12:44:23.528442 DQS Delay:
6320 12:44:23.528860 DQS0 = 27, DQS1 = 43
6321 12:44:23.529246 DQM Delay:
6322 12:44:23.531861 DQM0 = 13, DQM1 = 11
6323 12:44:23.532371 DQ Delay:
6324 12:44:23.535244 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6325 12:44:23.538959 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6326 12:44:23.542042 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6327 12:44:23.544839 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6328 12:44:23.545486
6329 12:44:23.545850
6330 12:44:23.546165 ==
6331 12:44:23.548582 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 12:44:23.551866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 12:44:23.555061 ==
6334 12:44:23.555572
6335 12:44:23.555965
6336 12:44:23.556481 TX Vref Scan disable
6337 12:44:23.558380 == TX Byte 0 ==
6338 12:44:23.561534 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 12:44:23.564885 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 12:44:23.568839 == TX Byte 1 ==
6341 12:44:23.571780 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6342 12:44:23.575230 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6343 12:44:23.575746 ==
6344 12:44:23.578736 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 12:44:23.584835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 12:44:23.585479 ==
6347 12:44:23.585827
6348 12:44:23.586141
6349 12:44:23.586467 TX Vref Scan disable
6350 12:44:23.587941 == TX Byte 0 ==
6351 12:44:23.591667 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 12:44:23.595036 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 12:44:23.598441 == TX Byte 1 ==
6354 12:44:23.601503 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6355 12:44:23.605072 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6356 12:44:23.605590
6357 12:44:23.607950 [DATLAT]
6358 12:44:23.608462 Freq=400, CH0 RK0
6359 12:44:23.608801
6360 12:44:23.611686 DATLAT Default: 0xf
6361 12:44:23.612360 0, 0xFFFF, sum = 0
6362 12:44:23.614777 1, 0xFFFF, sum = 0
6363 12:44:23.615213 2, 0xFFFF, sum = 0
6364 12:44:23.618037 3, 0xFFFF, sum = 0
6365 12:44:23.618560 4, 0xFFFF, sum = 0
6366 12:44:23.621213 5, 0xFFFF, sum = 0
6367 12:44:23.621794 6, 0xFFFF, sum = 0
6368 12:44:23.624454 7, 0xFFFF, sum = 0
6369 12:44:23.625006 8, 0xFFFF, sum = 0
6370 12:44:23.627931 9, 0xFFFF, sum = 0
6371 12:44:23.631502 10, 0xFFFF, sum = 0
6372 12:44:23.632040 11, 0xFFFF, sum = 0
6373 12:44:23.634326 12, 0xFFFF, sum = 0
6374 12:44:23.634888 13, 0x0, sum = 1
6375 12:44:23.638392 14, 0x0, sum = 2
6376 12:44:23.638923 15, 0x0, sum = 3
6377 12:44:23.639278 16, 0x0, sum = 4
6378 12:44:23.641092 best_step = 14
6379 12:44:23.641521
6380 12:44:23.641864 ==
6381 12:44:23.644186 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 12:44:23.648163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 12:44:23.648695 ==
6384 12:44:23.651067 RX Vref Scan: 1
6385 12:44:23.651498
6386 12:44:23.654344 RX Vref 0 -> 0, step: 1
6387 12:44:23.654796
6388 12:44:23.655141 RX Delay -327 -> 252, step: 8
6389 12:44:23.655467
6390 12:44:23.657628 Set Vref, RX VrefLevel [Byte0]: 56
6391 12:44:23.661210 [Byte1]: 48
6392 12:44:23.666551
6393 12:44:23.667113 Final RX Vref Byte 0 = 56 to rank0
6394 12:44:23.669599 Final RX Vref Byte 1 = 48 to rank0
6395 12:44:23.673492 Final RX Vref Byte 0 = 56 to rank1
6396 12:44:23.676566 Final RX Vref Byte 1 = 48 to rank1==
6397 12:44:23.679624 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 12:44:23.686371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 12:44:23.686914 ==
6400 12:44:23.687265 DQS Delay:
6401 12:44:23.689355 DQS0 = 28, DQS1 = 48
6402 12:44:23.689785 DQM Delay:
6403 12:44:23.690128 DQM0 = 12, DQM1 = 15
6404 12:44:23.693225 DQ Delay:
6405 12:44:23.696256 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6406 12:44:23.699385 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6407 12:44:23.699914 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6408 12:44:23.705906 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6409 12:44:23.706434
6410 12:44:23.706778
6411 12:44:23.713157 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6412 12:44:23.716173 CH0 RK0: MR19=C0C, MR18=ACA4
6413 12:44:23.722701 CH0_RK0: MR19=0xC0C, MR18=0xACA4, DQSOSC=388, MR23=63, INC=392, DEC=261
6414 12:44:23.723231 ==
6415 12:44:23.726274 Dram Type= 6, Freq= 0, CH_0, rank 1
6416 12:44:23.729080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 12:44:23.729517 ==
6418 12:44:23.732728 [Gating] SW mode calibration
6419 12:44:23.738946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6420 12:44:23.745450 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6421 12:44:23.748973 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 12:44:23.752364 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 12:44:23.758565 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 12:44:23.762533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 12:44:23.765156 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 12:44:23.771964 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 12:44:23.775544 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 12:44:23.778985 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 12:44:23.785242 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 12:44:23.788812 Total UI for P1: 0, mck2ui 16
6431 12:44:23.791722 best dqsien dly found for B0: ( 0, 14, 24)
6432 12:44:23.792252 Total UI for P1: 0, mck2ui 16
6433 12:44:23.798321 best dqsien dly found for B1: ( 0, 14, 24)
6434 12:44:23.801841 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6435 12:44:23.804945 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6436 12:44:23.805548
6437 12:44:23.808405 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 12:44:23.811859 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 12:44:23.814838 [Gating] SW calibration Done
6440 12:44:23.815419 ==
6441 12:44:23.818611 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 12:44:23.821533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 12:44:23.822064 ==
6444 12:44:23.825115 RX Vref Scan: 0
6445 12:44:23.825637
6446 12:44:23.825977 RX Vref 0 -> 0, step: 1
6447 12:44:23.828327
6448 12:44:23.828865 RX Delay -410 -> 252, step: 16
6449 12:44:23.835122 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6450 12:44:23.838089 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6451 12:44:23.841726 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6452 12:44:23.844662 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6453 12:44:23.851764 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6454 12:44:23.854523 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6455 12:44:23.858331 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6456 12:44:23.861272 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6457 12:44:23.867943 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6458 12:44:23.871401 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6459 12:44:23.874642 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6460 12:44:23.881238 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6461 12:44:23.884543 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6462 12:44:23.888006 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6463 12:44:23.891493 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6464 12:44:23.897861 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6465 12:44:23.898435 ==
6466 12:44:23.901318 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 12:44:23.904415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 12:44:23.905020 ==
6469 12:44:23.905404 DQS Delay:
6470 12:44:23.907748 DQS0 = 27, DQS1 = 43
6471 12:44:23.908317 DQM Delay:
6472 12:44:23.911294 DQM0 = 9, DQM1 = 16
6473 12:44:23.911860 DQ Delay:
6474 12:44:23.914192 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6475 12:44:23.917651 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6476 12:44:23.920875 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6477 12:44:23.924272 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6478 12:44:23.924836
6479 12:44:23.925245
6480 12:44:23.925589 ==
6481 12:44:23.927777 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 12:44:23.930909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 12:44:23.931480 ==
6484 12:44:23.931857
6485 12:44:23.932204
6486 12:44:23.934234 TX Vref Scan disable
6487 12:44:23.934802 == TX Byte 0 ==
6488 12:44:23.940827 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6489 12:44:23.944028 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6490 12:44:23.944493 == TX Byte 1 ==
6491 12:44:23.950392 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6492 12:44:23.953622 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6493 12:44:23.954089 ==
6494 12:44:23.956833 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 12:44:23.960270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 12:44:23.960741 ==
6497 12:44:23.961142
6498 12:44:23.963450
6499 12:44:23.964016 TX Vref Scan disable
6500 12:44:23.967495 == TX Byte 0 ==
6501 12:44:23.970482 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6502 12:44:23.973393 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6503 12:44:23.976673 == TX Byte 1 ==
6504 12:44:23.980189 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6505 12:44:23.983465 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6506 12:44:23.984028
6507 12:44:23.984398 [DATLAT]
6508 12:44:23.986623 Freq=400, CH0 RK1
6509 12:44:23.987090
6510 12:44:23.987459 DATLAT Default: 0xe
6511 12:44:23.989722 0, 0xFFFF, sum = 0
6512 12:44:23.993329 1, 0xFFFF, sum = 0
6513 12:44:23.993872 2, 0xFFFF, sum = 0
6514 12:44:23.996805 3, 0xFFFF, sum = 0
6515 12:44:23.997416 4, 0xFFFF, sum = 0
6516 12:44:24.000187 5, 0xFFFF, sum = 0
6517 12:44:24.000761 6, 0xFFFF, sum = 0
6518 12:44:24.003179 7, 0xFFFF, sum = 0
6519 12:44:24.003651 8, 0xFFFF, sum = 0
6520 12:44:24.006591 9, 0xFFFF, sum = 0
6521 12:44:24.007065 10, 0xFFFF, sum = 0
6522 12:44:24.010053 11, 0xFFFF, sum = 0
6523 12:44:24.010633 12, 0xFFFF, sum = 0
6524 12:44:24.013193 13, 0x0, sum = 1
6525 12:44:24.013772 14, 0x0, sum = 2
6526 12:44:24.016577 15, 0x0, sum = 3
6527 12:44:24.017183 16, 0x0, sum = 4
6528 12:44:24.019896 best_step = 14
6529 12:44:24.020437
6530 12:44:24.020807 ==
6531 12:44:24.023187 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 12:44:24.026424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 12:44:24.026895 ==
6534 12:44:24.029420 RX Vref Scan: 0
6535 12:44:24.029883
6536 12:44:24.030254 RX Vref 0 -> 0, step: 1
6537 12:44:24.030602
6538 12:44:24.032804 RX Delay -327 -> 252, step: 8
6539 12:44:24.040666 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6540 12:44:24.043981 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6541 12:44:24.047364 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6542 12:44:24.050306 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6543 12:44:24.057220 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6544 12:44:24.060500 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6545 12:44:24.063898 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6546 12:44:24.067301 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6547 12:44:24.073871 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6548 12:44:24.077129 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6549 12:44:24.080524 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6550 12:44:24.086773 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6551 12:44:24.090009 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6552 12:44:24.093421 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6553 12:44:24.096900 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6554 12:44:24.103417 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6555 12:44:24.103982 ==
6556 12:44:24.106944 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 12:44:24.110067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 12:44:24.110604 ==
6559 12:44:24.110976 DQS Delay:
6560 12:44:24.113662 DQS0 = 28, DQS1 = 40
6561 12:44:24.114240 DQM Delay:
6562 12:44:24.116801 DQM0 = 10, DQM1 = 12
6563 12:44:24.117403 DQ Delay:
6564 12:44:24.119864 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6565 12:44:24.123199 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6566 12:44:24.126538 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6567 12:44:24.129662 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6568 12:44:24.130436
6569 12:44:24.131057
6570 12:44:24.136306 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6571 12:44:24.139369 CH0 RK1: MR19=C0C, MR18=BB6F
6572 12:44:24.145994 CH0_RK1: MR19=0xC0C, MR18=0xBB6F, DQSOSC=386, MR23=63, INC=396, DEC=264
6573 12:44:24.149483 [RxdqsGatingPostProcess] freq 400
6574 12:44:24.156036 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6575 12:44:24.159095 best DQS0 dly(2T, 0.5T) = (0, 10)
6576 12:44:24.162778 best DQS1 dly(2T, 0.5T) = (0, 10)
6577 12:44:24.166048 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6578 12:44:24.169467 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6579 12:44:24.172713 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 12:44:24.173221 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 12:44:24.175708 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 12:44:24.179397 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 12:44:24.182258 Pre-setting of DQS Precalculation
6584 12:44:24.189108 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6585 12:44:24.189696 ==
6586 12:44:24.192482 Dram Type= 6, Freq= 0, CH_1, rank 0
6587 12:44:24.195503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 12:44:24.196070 ==
6589 12:44:24.202391 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6590 12:44:24.209190 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6591 12:44:24.212415 [CA 0] Center 36 (8~64) winsize 57
6592 12:44:24.215487 [CA 1] Center 36 (8~64) winsize 57
6593 12:44:24.216091 [CA 2] Center 36 (8~64) winsize 57
6594 12:44:24.218855 [CA 3] Center 36 (8~64) winsize 57
6595 12:44:24.222088 [CA 4] Center 36 (8~64) winsize 57
6596 12:44:24.225932 [CA 5] Center 36 (8~64) winsize 57
6597 12:44:24.226498
6598 12:44:24.228839 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6599 12:44:24.232240
6600 12:44:24.235770 [CATrainingPosCal] consider 1 rank data
6601 12:44:24.236337 u2DelayCellTimex100 = 270/100 ps
6602 12:44:24.242112 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 12:44:24.245015 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 12:44:24.248378 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 12:44:24.251619 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 12:44:24.255069 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 12:44:24.258399 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 12:44:24.258865
6609 12:44:24.261638 CA PerBit enable=1, Macro0, CA PI delay=36
6610 12:44:24.262238
6611 12:44:24.265085 [CBTSetCACLKResult] CA Dly = 36
6612 12:44:24.268175 CS Dly: 1 (0~32)
6613 12:44:24.268641 ==
6614 12:44:24.271462 Dram Type= 6, Freq= 0, CH_1, rank 1
6615 12:44:24.275177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 12:44:24.275645 ==
6617 12:44:24.281422 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6618 12:44:24.287822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6619 12:44:24.288304 [CA 0] Center 36 (8~64) winsize 57
6620 12:44:24.291217 [CA 1] Center 36 (8~64) winsize 57
6621 12:44:24.294382 [CA 2] Center 36 (8~64) winsize 57
6622 12:44:24.298300 [CA 3] Center 36 (8~64) winsize 57
6623 12:44:24.301443 [CA 4] Center 36 (8~64) winsize 57
6624 12:44:24.304909 [CA 5] Center 36 (8~64) winsize 57
6625 12:44:24.305526
6626 12:44:24.308363 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6627 12:44:24.308941
6628 12:44:24.311202 [CATrainingPosCal] consider 2 rank data
6629 12:44:24.314498 u2DelayCellTimex100 = 270/100 ps
6630 12:44:24.317714 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:44:24.321162 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:44:24.327897 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:44:24.330866 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:44:24.334438 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:44:24.337762 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:44:24.338098
6637 12:44:24.340827 CA PerBit enable=1, Macro0, CA PI delay=36
6638 12:44:24.341095
6639 12:44:24.344008 [CBTSetCACLKResult] CA Dly = 36
6640 12:44:24.344253 CS Dly: 1 (0~32)
6641 12:44:24.344453
6642 12:44:24.347440 ----->DramcWriteLeveling(PI) begin...
6643 12:44:24.350647 ==
6644 12:44:24.354009 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 12:44:24.357407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 12:44:24.357654 ==
6647 12:44:24.360705 Write leveling (Byte 0): 40 => 8
6648 12:44:24.363979 Write leveling (Byte 1): 32 => 0
6649 12:44:24.367544 DramcWriteLeveling(PI) end<-----
6650 12:44:24.367975
6651 12:44:24.368320 ==
6652 12:44:24.370929 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 12:44:24.373884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 12:44:24.374318 ==
6655 12:44:24.377489 [Gating] SW mode calibration
6656 12:44:24.383876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6657 12:44:24.390844 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6658 12:44:24.393632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 12:44:24.397196 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 12:44:24.403807 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 12:44:24.406829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 12:44:24.410496 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 12:44:24.416652 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 12:44:24.420277 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 12:44:24.423604 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 12:44:24.430142 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 12:44:24.430567 Total UI for P1: 0, mck2ui 16
6668 12:44:24.436412 best dqsien dly found for B0: ( 0, 14, 24)
6669 12:44:24.436840 Total UI for P1: 0, mck2ui 16
6670 12:44:24.440146 best dqsien dly found for B1: ( 0, 14, 24)
6671 12:44:24.446868 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6672 12:44:24.449882 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6673 12:44:24.450306
6674 12:44:24.453150 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 12:44:24.456472 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 12:44:24.459792 [Gating] SW calibration Done
6677 12:44:24.460219 ==
6678 12:44:24.463188 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 12:44:24.466197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 12:44:24.466656 ==
6681 12:44:24.469919 RX Vref Scan: 0
6682 12:44:24.470360
6683 12:44:24.470798 RX Vref 0 -> 0, step: 1
6684 12:44:24.471211
6685 12:44:24.473150 RX Delay -410 -> 252, step: 16
6686 12:44:24.480021 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6687 12:44:24.483015 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6688 12:44:24.486194 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6689 12:44:24.489667 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6690 12:44:24.496098 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6691 12:44:24.500174 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6692 12:44:24.502918 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6693 12:44:24.505998 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6694 12:44:24.512479 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6695 12:44:24.515643 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6696 12:44:24.519039 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6697 12:44:24.522710 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6698 12:44:24.528889 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6699 12:44:24.532579 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6700 12:44:24.535861 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6701 12:44:24.542271 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6702 12:44:24.542711 ==
6703 12:44:24.545847 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 12:44:24.548740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 12:44:24.549220 ==
6706 12:44:24.549658 DQS Delay:
6707 12:44:24.552091 DQS0 = 27, DQS1 = 43
6708 12:44:24.552521 DQM Delay:
6709 12:44:24.555254 DQM0 = 7, DQM1 = 16
6710 12:44:24.555689 DQ Delay:
6711 12:44:24.558607 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6712 12:44:24.561896 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =0
6713 12:44:24.565290 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6714 12:44:24.568813 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6715 12:44:24.569305
6716 12:44:24.569736
6717 12:44:24.570151 ==
6718 12:44:24.571803 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 12:44:24.575482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 12:44:24.576024 ==
6721 12:44:24.576470
6722 12:44:24.576880
6723 12:44:24.578788 TX Vref Scan disable
6724 12:44:24.579322 == TX Byte 0 ==
6725 12:44:24.585062 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 12:44:24.588504 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 12:44:24.589099 == TX Byte 1 ==
6728 12:44:24.595135 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6729 12:44:24.598183 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6730 12:44:24.598625 ==
6731 12:44:24.601622 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 12:44:24.604877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 12:44:24.605342 ==
6734 12:44:24.608778
6735 12:44:24.609248
6736 12:44:24.609589 TX Vref Scan disable
6737 12:44:24.611873 == TX Byte 0 ==
6738 12:44:24.614838 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 12:44:24.618296 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 12:44:24.621355 == TX Byte 1 ==
6741 12:44:24.624660 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6742 12:44:24.628050 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6743 12:44:24.628476
6744 12:44:24.631631 [DATLAT]
6745 12:44:24.632058 Freq=400, CH1 RK0
6746 12:44:24.632399
6747 12:44:24.634801 DATLAT Default: 0xf
6748 12:44:24.635228 0, 0xFFFF, sum = 0
6749 12:44:24.638425 1, 0xFFFF, sum = 0
6750 12:44:24.638856 2, 0xFFFF, sum = 0
6751 12:44:24.641458 3, 0xFFFF, sum = 0
6752 12:44:24.641892 4, 0xFFFF, sum = 0
6753 12:44:24.644458 5, 0xFFFF, sum = 0
6754 12:44:24.644892 6, 0xFFFF, sum = 0
6755 12:44:24.648267 7, 0xFFFF, sum = 0
6756 12:44:24.648698 8, 0xFFFF, sum = 0
6757 12:44:24.651399 9, 0xFFFF, sum = 0
6758 12:44:24.651828 10, 0xFFFF, sum = 0
6759 12:44:24.654675 11, 0xFFFF, sum = 0
6760 12:44:24.655109 12, 0xFFFF, sum = 0
6761 12:44:24.657818 13, 0x0, sum = 1
6762 12:44:24.658123 14, 0x0, sum = 2
6763 12:44:24.661132 15, 0x0, sum = 3
6764 12:44:24.661443 16, 0x0, sum = 4
6765 12:44:24.664334 best_step = 14
6766 12:44:24.664638
6767 12:44:24.664884 ==
6768 12:44:24.668094 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 12:44:24.671098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 12:44:24.671406 ==
6771 12:44:24.674466 RX Vref Scan: 1
6772 12:44:24.674871
6773 12:44:24.675120 RX Vref 0 -> 0, step: 1
6774 12:44:24.675353
6775 12:44:24.677695 RX Delay -327 -> 252, step: 8
6776 12:44:24.678107
6777 12:44:24.681023 Set Vref, RX VrefLevel [Byte0]: 51
6778 12:44:24.684095 [Byte1]: 52
6779 12:44:24.688895
6780 12:44:24.689329 Final RX Vref Byte 0 = 51 to rank0
6781 12:44:24.692563 Final RX Vref Byte 1 = 52 to rank0
6782 12:44:24.695526 Final RX Vref Byte 0 = 51 to rank1
6783 12:44:24.699162 Final RX Vref Byte 1 = 52 to rank1==
6784 12:44:24.702346 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 12:44:24.708727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 12:44:24.709203 ==
6787 12:44:24.709548 DQS Delay:
6788 12:44:24.712154 DQS0 = 32, DQS1 = 40
6789 12:44:24.712579 DQM Delay:
6790 12:44:24.712919 DQM0 = 12, DQM1 = 12
6791 12:44:24.715321 DQ Delay:
6792 12:44:24.718762 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6793 12:44:24.719188 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6794 12:44:24.722271 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6795 12:44:24.725561 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6796 12:44:24.728815
6797 12:44:24.729327
6798 12:44:24.735280 [DQSOSCAuto] RK0, (LSB)MR18= 0x91cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6799 12:44:24.738630 CH1 RK0: MR19=C0C, MR18=91CC
6800 12:44:24.745071 CH1_RK0: MR19=0xC0C, MR18=0x91CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6801 12:44:24.745579 ==
6802 12:44:24.748284 Dram Type= 6, Freq= 0, CH_1, rank 1
6803 12:44:24.751657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 12:44:24.752127 ==
6805 12:44:24.754822 [Gating] SW mode calibration
6806 12:44:24.761614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6807 12:44:24.768016 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6808 12:44:24.771474 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 12:44:24.774744 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 12:44:24.781527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 12:44:24.784807 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 12:44:24.787926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 12:44:24.794727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 12:44:24.797755 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 12:44:24.801076 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 12:44:24.807736 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 12:44:24.808165 Total UI for P1: 0, mck2ui 16
6818 12:44:24.814453 best dqsien dly found for B0: ( 0, 14, 24)
6819 12:44:24.814904 Total UI for P1: 0, mck2ui 16
6820 12:44:24.820636 best dqsien dly found for B1: ( 0, 14, 24)
6821 12:44:24.823868 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6822 12:44:24.827127 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6823 12:44:24.827356
6824 12:44:24.830752 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 12:44:24.834004 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 12:44:24.837123 [Gating] SW calibration Done
6827 12:44:24.837277 ==
6828 12:44:24.840842 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 12:44:24.844232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 12:44:24.844563 ==
6831 12:44:24.847252 RX Vref Scan: 0
6832 12:44:24.847498
6833 12:44:24.847694 RX Vref 0 -> 0, step: 1
6834 12:44:24.850951
6835 12:44:24.851325 RX Delay -410 -> 252, step: 16
6836 12:44:24.857093 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6837 12:44:24.860649 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6838 12:44:24.864173 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6839 12:44:24.866993 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6840 12:44:24.873637 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6841 12:44:24.876738 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6842 12:44:24.880356 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6843 12:44:24.883615 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6844 12:44:24.889890 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6845 12:44:24.893448 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6846 12:44:24.897081 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6847 12:44:24.903309 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6848 12:44:24.906565 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6849 12:44:24.909968 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6850 12:44:24.913134 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6851 12:44:24.919486 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6852 12:44:24.919734 ==
6853 12:44:24.922957 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 12:44:24.926239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 12:44:24.926486 ==
6856 12:44:24.926682 DQS Delay:
6857 12:44:24.929674 DQS0 = 35, DQS1 = 43
6858 12:44:24.929917 DQM Delay:
6859 12:44:24.932929 DQM0 = 16, DQM1 = 19
6860 12:44:24.933134 DQ Delay:
6861 12:44:24.936099 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6862 12:44:24.939902 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6863 12:44:24.942865 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6864 12:44:24.946017 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6865 12:44:24.946189
6866 12:44:24.946330
6867 12:44:24.946451 ==
6868 12:44:24.949244 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 12:44:24.952655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 12:44:24.956118 ==
6871 12:44:24.956279
6872 12:44:24.956405
6873 12:44:24.956524 TX Vref Scan disable
6874 12:44:24.959139 == TX Byte 0 ==
6875 12:44:24.962597 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6876 12:44:24.965954 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6877 12:44:24.969650 == TX Byte 1 ==
6878 12:44:24.972722 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6879 12:44:24.975982 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6880 12:44:24.976493 ==
6881 12:44:24.979215 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 12:44:24.982911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 12:44:24.985796 ==
6884 12:44:24.986223
6885 12:44:24.986567
6886 12:44:24.986884 TX Vref Scan disable
6887 12:44:24.989393 == TX Byte 0 ==
6888 12:44:24.992931 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6889 12:44:24.996050 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6890 12:44:24.999128 == TX Byte 1 ==
6891 12:44:25.002800 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6892 12:44:25.005752 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6893 12:44:25.006187
6894 12:44:25.009257 [DATLAT]
6895 12:44:25.009730 Freq=400, CH1 RK1
6896 12:44:25.010077
6897 12:44:25.012597 DATLAT Default: 0xe
6898 12:44:25.013042 0, 0xFFFF, sum = 0
6899 12:44:25.015604 1, 0xFFFF, sum = 0
6900 12:44:25.016041 2, 0xFFFF, sum = 0
6901 12:44:25.019124 3, 0xFFFF, sum = 0
6902 12:44:25.019559 4, 0xFFFF, sum = 0
6903 12:44:25.022071 5, 0xFFFF, sum = 0
6904 12:44:25.022508 6, 0xFFFF, sum = 0
6905 12:44:25.025595 7, 0xFFFF, sum = 0
6906 12:44:25.026031 8, 0xFFFF, sum = 0
6907 12:44:25.028850 9, 0xFFFF, sum = 0
6908 12:44:25.029388 10, 0xFFFF, sum = 0
6909 12:44:25.031990 11, 0xFFFF, sum = 0
6910 12:44:25.035309 12, 0xFFFF, sum = 0
6911 12:44:25.035750 13, 0x0, sum = 1
6912 12:44:25.036102 14, 0x0, sum = 2
6913 12:44:25.039040 15, 0x0, sum = 3
6914 12:44:25.039553 16, 0x0, sum = 4
6915 12:44:25.041898 best_step = 14
6916 12:44:25.042326
6917 12:44:25.042666 ==
6918 12:44:25.045391 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 12:44:25.049638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 12:44:25.050069 ==
6921 12:44:25.052184 RX Vref Scan: 0
6922 12:44:25.052613
6923 12:44:25.052958 RX Vref 0 -> 0, step: 1
6924 12:44:25.055492
6925 12:44:25.055927 RX Delay -327 -> 252, step: 8
6926 12:44:25.063716 iDelay=217, Bit 0, Center -20 (-239 ~ 200) 440
6927 12:44:25.067397 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6928 12:44:25.069949 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6929 12:44:25.077063 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6930 12:44:25.079941 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6931 12:44:25.083895 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6932 12:44:25.086919 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6933 12:44:25.093529 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6934 12:44:25.096838 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6935 12:44:25.100113 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6936 12:44:25.103257 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6937 12:44:25.109844 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6938 12:44:25.113086 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6939 12:44:25.116584 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6940 12:44:25.119515 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6941 12:44:25.126315 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6942 12:44:25.126809 ==
6943 12:44:25.129326 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 12:44:25.132973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 12:44:25.133442 ==
6946 12:44:25.133791 DQS Delay:
6947 12:44:25.136225 DQS0 = 32, DQS1 = 36
6948 12:44:25.136654 DQM Delay:
6949 12:44:25.139354 DQM0 = 11, DQM1 = 11
6950 12:44:25.139851 DQ Delay:
6951 12:44:25.142662 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6952 12:44:25.146005 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6953 12:44:25.149240 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6954 12:44:25.152725 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6955 12:44:25.153206
6956 12:44:25.153554
6957 12:44:25.159464 [DQSOSCAuto] RK1, (LSB)MR18= 0xa44e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6958 12:44:25.162955 CH1 RK1: MR19=C0C, MR18=A44E
6959 12:44:25.169296 CH1_RK1: MR19=0xC0C, MR18=0xA44E, DQSOSC=389, MR23=63, INC=390, DEC=260
6960 12:44:25.172492 [RxdqsGatingPostProcess] freq 400
6961 12:44:25.178929 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6962 12:44:25.182497 best DQS0 dly(2T, 0.5T) = (0, 10)
6963 12:44:25.185384 best DQS1 dly(2T, 0.5T) = (0, 10)
6964 12:44:25.189152 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6965 12:44:25.192169 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6966 12:44:25.195643 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 12:44:25.196133 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 12:44:25.198683 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 12:44:25.202133 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 12:44:25.205509 Pre-setting of DQS Precalculation
6971 12:44:25.212167 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6972 12:44:25.218860 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6973 12:44:25.225327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6974 12:44:25.225756
6975 12:44:25.226095
6976 12:44:25.228772 [Calibration Summary] 800 Mbps
6977 12:44:25.231875 CH 0, Rank 0
6978 12:44:25.232366 SW Impedance : PASS
6979 12:44:25.235067 DUTY Scan : NO K
6980 12:44:25.235565 ZQ Calibration : PASS
6981 12:44:25.238572 Jitter Meter : NO K
6982 12:44:25.241977 CBT Training : PASS
6983 12:44:25.242403 Write leveling : PASS
6984 12:44:25.245290 RX DQS gating : PASS
6985 12:44:25.248297 RX DQ/DQS(RDDQC) : PASS
6986 12:44:25.248724 TX DQ/DQS : PASS
6987 12:44:25.251933 RX DATLAT : PASS
6988 12:44:25.255099 RX DQ/DQS(Engine): PASS
6989 12:44:25.255529 TX OE : NO K
6990 12:44:25.258175 All Pass.
6991 12:44:25.258602
6992 12:44:25.258939 CH 0, Rank 1
6993 12:44:25.262062 SW Impedance : PASS
6994 12:44:25.262488 DUTY Scan : NO K
6995 12:44:25.264951 ZQ Calibration : PASS
6996 12:44:25.268219 Jitter Meter : NO K
6997 12:44:25.268647 CBT Training : PASS
6998 12:44:25.271897 Write leveling : NO K
6999 12:44:25.275150 RX DQS gating : PASS
7000 12:44:25.275659 RX DQ/DQS(RDDQC) : PASS
7001 12:44:25.278375 TX DQ/DQS : PASS
7002 12:44:25.281709 RX DATLAT : PASS
7003 12:44:25.282134 RX DQ/DQS(Engine): PASS
7004 12:44:25.284833 TX OE : NO K
7005 12:44:25.285294 All Pass.
7006 12:44:25.285638
7007 12:44:25.288318 CH 1, Rank 0
7008 12:44:25.288742 SW Impedance : PASS
7009 12:44:25.291673 DUTY Scan : NO K
7010 12:44:25.292218 ZQ Calibration : PASS
7011 12:44:25.294920 Jitter Meter : NO K
7012 12:44:25.298168 CBT Training : PASS
7013 12:44:25.298702 Write leveling : PASS
7014 12:44:25.301533 RX DQS gating : PASS
7015 12:44:25.304419 RX DQ/DQS(RDDQC) : PASS
7016 12:44:25.304848 TX DQ/DQS : PASS
7017 12:44:25.307925 RX DATLAT : PASS
7018 12:44:25.311228 RX DQ/DQS(Engine): PASS
7019 12:44:25.311765 TX OE : NO K
7020 12:44:25.314352 All Pass.
7021 12:44:25.314788
7022 12:44:25.315126 CH 1, Rank 1
7023 12:44:25.317700 SW Impedance : PASS
7024 12:44:25.318302 DUTY Scan : NO K
7025 12:44:25.321167 ZQ Calibration : PASS
7026 12:44:25.324414 Jitter Meter : NO K
7027 12:44:25.324840 CBT Training : PASS
7028 12:44:25.327783 Write leveling : NO K
7029 12:44:25.331411 RX DQS gating : PASS
7030 12:44:25.331945 RX DQ/DQS(RDDQC) : PASS
7031 12:44:25.334577 TX DQ/DQS : PASS
7032 12:44:25.337720 RX DATLAT : PASS
7033 12:44:25.338151 RX DQ/DQS(Engine): PASS
7034 12:44:25.341181 TX OE : NO K
7035 12:44:25.341718 All Pass.
7036 12:44:25.342070
7037 12:44:25.344296 DramC Write-DBI off
7038 12:44:25.347332 PER_BANK_REFRESH: Hybrid Mode
7039 12:44:25.347759 TX_TRACKING: ON
7040 12:44:25.357452 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7041 12:44:25.360872 [FAST_K] Save calibration result to emmc
7042 12:44:25.364520 dramc_set_vcore_voltage set vcore to 725000
7043 12:44:25.367476 Read voltage for 1600, 0
7044 12:44:25.367904 Vio18 = 0
7045 12:44:25.368246 Vcore = 725000
7046 12:44:25.370468 Vdram = 0
7047 12:44:25.370894 Vddq = 0
7048 12:44:25.371237 Vmddr = 0
7049 12:44:25.377059 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7050 12:44:25.380387 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7051 12:44:25.383845 MEM_TYPE=3, freq_sel=13
7052 12:44:25.387106 sv_algorithm_assistance_LP4_3733
7053 12:44:25.390171 ============ PULL DRAM RESETB DOWN ============
7054 12:44:25.393937 ========== PULL DRAM RESETB DOWN end =========
7055 12:44:25.400406 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7056 12:44:25.403760 ===================================
7057 12:44:25.407447 LPDDR4 DRAM CONFIGURATION
7058 12:44:25.410628 ===================================
7059 12:44:25.411178 EX_ROW_EN[0] = 0x0
7060 12:44:25.414258 EX_ROW_EN[1] = 0x0
7061 12:44:25.414798 LP4Y_EN = 0x0
7062 12:44:25.417034 WORK_FSP = 0x1
7063 12:44:25.417464 WL = 0x5
7064 12:44:25.420293 RL = 0x5
7065 12:44:25.420719 BL = 0x2
7066 12:44:25.423498 RPST = 0x0
7067 12:44:25.423919 RD_PRE = 0x0
7068 12:44:25.426936 WR_PRE = 0x1
7069 12:44:25.427363 WR_PST = 0x1
7070 12:44:25.431205 DBI_WR = 0x0
7071 12:44:25.431737 DBI_RD = 0x0
7072 12:44:25.433575 OTF = 0x1
7073 12:44:25.436934 ===================================
7074 12:44:25.440707 ===================================
7075 12:44:25.441309 ANA top config
7076 12:44:25.443615 ===================================
7077 12:44:25.446634 DLL_ASYNC_EN = 0
7078 12:44:25.450345 ALL_SLAVE_EN = 0
7079 12:44:25.453832 NEW_RANK_MODE = 1
7080 12:44:25.454510 DLL_IDLE_MODE = 1
7081 12:44:25.456924 LP45_APHY_COMB_EN = 1
7082 12:44:25.460205 TX_ODT_DIS = 0
7083 12:44:25.463482 NEW_8X_MODE = 1
7084 12:44:25.466862 ===================================
7085 12:44:25.469962 ===================================
7086 12:44:25.473769 data_rate = 3200
7087 12:44:25.476746 CKR = 1
7088 12:44:25.477226 DQ_P2S_RATIO = 8
7089 12:44:25.479963 ===================================
7090 12:44:25.483048 CA_P2S_RATIO = 8
7091 12:44:25.486665 DQ_CA_OPEN = 0
7092 12:44:25.489922 DQ_SEMI_OPEN = 0
7093 12:44:25.493059 CA_SEMI_OPEN = 0
7094 12:44:25.496229 CA_FULL_RATE = 0
7095 12:44:25.496658 DQ_CKDIV4_EN = 0
7096 12:44:25.499811 CA_CKDIV4_EN = 0
7097 12:44:25.503047 CA_PREDIV_EN = 0
7098 12:44:25.506483 PH8_DLY = 12
7099 12:44:25.509425 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7100 12:44:25.513053 DQ_AAMCK_DIV = 4
7101 12:44:25.513549 CA_AAMCK_DIV = 4
7102 12:44:25.516258 CA_ADMCK_DIV = 4
7103 12:44:25.519341 DQ_TRACK_CA_EN = 0
7104 12:44:25.523124 CA_PICK = 1600
7105 12:44:25.526089 CA_MCKIO = 1600
7106 12:44:25.529105 MCKIO_SEMI = 0
7107 12:44:25.532503 PLL_FREQ = 3068
7108 12:44:25.535868 DQ_UI_PI_RATIO = 32
7109 12:44:25.536369 CA_UI_PI_RATIO = 0
7110 12:44:25.539556 ===================================
7111 12:44:25.542358 ===================================
7112 12:44:25.545615 memory_type:LPDDR4
7113 12:44:25.548961 GP_NUM : 10
7114 12:44:25.549415 SRAM_EN : 1
7115 12:44:25.552292 MD32_EN : 0
7116 12:44:25.555621 ===================================
7117 12:44:25.558866 [ANA_INIT] >>>>>>>>>>>>>>
7118 12:44:25.562153 <<<<<< [CONFIGURE PHASE]: ANA_TX
7119 12:44:25.565432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7120 12:44:25.568728 ===================================
7121 12:44:25.569194 data_rate = 3200,PCW = 0X7600
7122 12:44:25.572131 ===================================
7123 12:44:25.578879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7124 12:44:25.581982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 12:44:25.588663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 12:44:25.592206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7127 12:44:25.595254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7128 12:44:25.598709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7129 12:44:25.601910 [ANA_INIT] flow start
7130 12:44:25.605086 [ANA_INIT] PLL >>>>>>>>
7131 12:44:25.605585 [ANA_INIT] PLL <<<<<<<<
7132 12:44:25.608351 [ANA_INIT] MIDPI >>>>>>>>
7133 12:44:25.611913 [ANA_INIT] MIDPI <<<<<<<<
7134 12:44:25.612416 [ANA_INIT] DLL >>>>>>>>
7135 12:44:25.615352 [ANA_INIT] DLL <<<<<<<<
7136 12:44:25.618458 [ANA_INIT] flow end
7137 12:44:25.621941 ============ LP4 DIFF to SE enter ============
7138 12:44:25.624936 ============ LP4 DIFF to SE exit ============
7139 12:44:25.628176 [ANA_INIT] <<<<<<<<<<<<<
7140 12:44:25.631591 [Flow] Enable top DCM control >>>>>
7141 12:44:25.634928 [Flow] Enable top DCM control <<<<<
7142 12:44:25.638472 Enable DLL master slave shuffle
7143 12:44:25.641444 ==============================================================
7144 12:44:25.644896 Gating Mode config
7145 12:44:25.651472 ==============================================================
7146 12:44:25.652004 Config description:
7147 12:44:25.661147 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7148 12:44:25.668152 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7149 12:44:25.674710 SELPH_MODE 0: By rank 1: By Phase
7150 12:44:25.677966 ==============================================================
7151 12:44:25.681402 GAT_TRACK_EN = 1
7152 12:44:25.684507 RX_GATING_MODE = 2
7153 12:44:25.687941 RX_GATING_TRACK_MODE = 2
7154 12:44:25.691215 SELPH_MODE = 1
7155 12:44:25.694994 PICG_EARLY_EN = 1
7156 12:44:25.697914 VALID_LAT_VALUE = 1
7157 12:44:25.701357 ==============================================================
7158 12:44:25.704472 Enter into Gating configuration >>>>
7159 12:44:25.708252 Exit from Gating configuration <<<<
7160 12:44:25.710927 Enter into DVFS_PRE_config >>>>>
7161 12:44:25.725033 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7162 12:44:25.727924 Exit from DVFS_PRE_config <<<<<
7163 12:44:25.731523 Enter into PICG configuration >>>>
7164 12:44:25.732108 Exit from PICG configuration <<<<
7165 12:44:25.734778 [RX_INPUT] configuration >>>>>
7166 12:44:25.738049 [RX_INPUT] configuration <<<<<
7167 12:44:25.744886 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7168 12:44:25.747546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7169 12:44:25.754575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 12:44:25.761098 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 12:44:25.767790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 12:44:25.773972 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 12:44:25.777369 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7174 12:44:25.781114 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7175 12:44:25.784583 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7176 12:44:25.790942 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7177 12:44:25.793676 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7178 12:44:25.797363 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7179 12:44:25.800676 ===================================
7180 12:44:25.804371 LPDDR4 DRAM CONFIGURATION
7181 12:44:25.807380 ===================================
7182 12:44:25.810390 EX_ROW_EN[0] = 0x0
7183 12:44:25.810866 EX_ROW_EN[1] = 0x0
7184 12:44:25.813672 LP4Y_EN = 0x0
7185 12:44:25.814149 WORK_FSP = 0x1
7186 12:44:25.817295 WL = 0x5
7187 12:44:25.817768 RL = 0x5
7188 12:44:25.820363 BL = 0x2
7189 12:44:25.820836 RPST = 0x0
7190 12:44:25.823812 RD_PRE = 0x0
7191 12:44:25.824400 WR_PRE = 0x1
7192 12:44:25.826733 WR_PST = 0x1
7193 12:44:25.827211 DBI_WR = 0x0
7194 12:44:25.830498 DBI_RD = 0x0
7195 12:44:25.833557 OTF = 0x1
7196 12:44:25.837096 ===================================
7197 12:44:25.840216 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7198 12:44:25.844096 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7199 12:44:25.846693 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 12:44:25.850377 ===================================
7201 12:44:25.853325 LPDDR4 DRAM CONFIGURATION
7202 12:44:25.856721 ===================================
7203 12:44:25.860018 EX_ROW_EN[0] = 0x10
7204 12:44:25.860488 EX_ROW_EN[1] = 0x0
7205 12:44:25.863583 LP4Y_EN = 0x0
7206 12:44:25.864163 WORK_FSP = 0x1
7207 12:44:25.867000 WL = 0x5
7208 12:44:25.867572 RL = 0x5
7209 12:44:25.869748 BL = 0x2
7210 12:44:25.870226 RPST = 0x0
7211 12:44:25.873545 RD_PRE = 0x0
7212 12:44:25.874018 WR_PRE = 0x1
7213 12:44:25.876429 WR_PST = 0x1
7214 12:44:25.876902 DBI_WR = 0x0
7215 12:44:25.880592 DBI_RD = 0x0
7216 12:44:25.883525 OTF = 0x1
7217 12:44:25.884106 ===================================
7218 12:44:25.890110 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7219 12:44:25.890693 ==
7220 12:44:25.892733 Dram Type= 6, Freq= 0, CH_0, rank 0
7221 12:44:25.900142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7222 12:44:25.900731 ==
7223 12:44:25.902907 [Duty_Offset_Calibration]
7224 12:44:25.903485 B0:2 B1:0 CA:1
7225 12:44:25.903868
7226 12:44:25.906255 [DutyScan_Calibration_Flow] k_type=0
7227 12:44:25.915059
7228 12:44:25.915626 ==CLK 0==
7229 12:44:25.918223 Final CLK duty delay cell = -4
7230 12:44:25.921472 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7231 12:44:25.925010 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7232 12:44:25.927956 [-4] AVG Duty = 4922%(X100)
7233 12:44:25.928537
7234 12:44:25.931635 CH0 CLK Duty spec in!! Max-Min= 218%
7235 12:44:25.935218 [DutyScan_Calibration_Flow] ====Done====
7236 12:44:25.935693
7237 12:44:25.937677 [DutyScan_Calibration_Flow] k_type=1
7238 12:44:25.954790
7239 12:44:25.955353 ==DQS 0 ==
7240 12:44:25.957928 Final DQS duty delay cell = 0
7241 12:44:25.961190 [0] MAX Duty = 5249%(X100), DQS PI = 32
7242 12:44:25.964705 [0] MIN Duty = 4969%(X100), DQS PI = 0
7243 12:44:25.965327 [0] AVG Duty = 5109%(X100)
7244 12:44:25.967967
7245 12:44:25.968531 ==DQS 1 ==
7246 12:44:25.971221 Final DQS duty delay cell = -4
7247 12:44:25.974440 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7248 12:44:25.983282 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7249 12:44:25.983942 [-4] AVG Duty = 5000%(X100)
7250 12:44:25.984501
7251 12:44:25.985391 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7252 12:44:25.985837
7253 12:44:25.987619 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7254 12:44:25.991288 [DutyScan_Calibration_Flow] ====Done====
7255 12:44:25.991861
7256 12:44:25.994331 [DutyScan_Calibration_Flow] k_type=3
7257 12:44:26.011927
7258 12:44:26.012460 ==DQM 0 ==
7259 12:44:26.015461 Final DQM duty delay cell = 0
7260 12:44:26.018633 [0] MAX Duty = 5124%(X100), DQS PI = 26
7261 12:44:26.021962 [0] MIN Duty = 4813%(X100), DQS PI = 52
7262 12:44:26.025136 [0] AVG Duty = 4968%(X100)
7263 12:44:26.025610
7264 12:44:26.025990 ==DQM 1 ==
7265 12:44:26.028348 Final DQM duty delay cell = 0
7266 12:44:26.032082 [0] MAX Duty = 5249%(X100), DQS PI = 30
7267 12:44:26.034898 [0] MIN Duty = 5031%(X100), DQS PI = 18
7268 12:44:26.038320 [0] AVG Duty = 5140%(X100)
7269 12:44:26.038841
7270 12:44:26.041799 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7271 12:44:26.042434
7272 12:44:26.045292 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7273 12:44:26.048398 [DutyScan_Calibration_Flow] ====Done====
7274 12:44:26.048929
7275 12:44:26.051453 [DutyScan_Calibration_Flow] k_type=2
7276 12:44:26.069076
7277 12:44:26.069612 ==DQ 0 ==
7278 12:44:26.072345 Final DQ duty delay cell = 0
7279 12:44:26.076044 [0] MAX Duty = 5124%(X100), DQS PI = 32
7280 12:44:26.079065 [0] MIN Duty = 5000%(X100), DQS PI = 0
7281 12:44:26.079532 [0] AVG Duty = 5062%(X100)
7282 12:44:26.079902
7283 12:44:26.082301 ==DQ 1 ==
7284 12:44:26.085522 Final DQ duty delay cell = 0
7285 12:44:26.088928 [0] MAX Duty = 4969%(X100), DQS PI = 50
7286 12:44:26.092205 [0] MIN Duty = 4875%(X100), DQS PI = 12
7287 12:44:26.092742 [0] AVG Duty = 4922%(X100)
7288 12:44:26.093165
7289 12:44:26.099072 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7290 12:44:26.099537
7291 12:44:26.102791 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7292 12:44:26.105806 [DutyScan_Calibration_Flow] ====Done====
7293 12:44:26.106346 ==
7294 12:44:26.108795 Dram Type= 6, Freq= 0, CH_1, rank 0
7295 12:44:26.112204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7296 12:44:26.112678 ==
7297 12:44:26.115434 [Duty_Offset_Calibration]
7298 12:44:26.115974 B0:0 B1:-1 CA:2
7299 12:44:26.116370
7300 12:44:26.118724 [DutyScan_Calibration_Flow] k_type=0
7301 12:44:26.129209
7302 12:44:26.129666 ==CLK 0==
7303 12:44:26.132298 Final CLK duty delay cell = 0
7304 12:44:26.135810 [0] MAX Duty = 5156%(X100), DQS PI = 10
7305 12:44:26.139132 [0] MIN Duty = 4938%(X100), DQS PI = 44
7306 12:44:26.142387 [0] AVG Duty = 5047%(X100)
7307 12:44:26.142683
7308 12:44:26.145661 CH1 CLK Duty spec in!! Max-Min= 218%
7309 12:44:26.149160 [DutyScan_Calibration_Flow] ====Done====
7310 12:44:26.149461
7311 12:44:26.152138 [DutyScan_Calibration_Flow] k_type=1
7312 12:44:26.169084
7313 12:44:26.169448 ==DQS 0 ==
7314 12:44:26.172393 Final DQS duty delay cell = 0
7315 12:44:26.175732 [0] MAX Duty = 5124%(X100), DQS PI = 26
7316 12:44:26.178734 [0] MIN Duty = 4969%(X100), DQS PI = 0
7317 12:44:26.182039 [0] AVG Duty = 5046%(X100)
7318 12:44:26.182582
7319 12:44:26.182952 ==DQS 1 ==
7320 12:44:26.185437 Final DQS duty delay cell = 0
7321 12:44:26.188647 [0] MAX Duty = 5187%(X100), DQS PI = 0
7322 12:44:26.191992 [0] MIN Duty = 4844%(X100), DQS PI = 34
7323 12:44:26.195247 [0] AVG Duty = 5015%(X100)
7324 12:44:26.195710
7325 12:44:26.198763 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7326 12:44:26.199224
7327 12:44:26.201913 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7328 12:44:26.205458 [DutyScan_Calibration_Flow] ====Done====
7329 12:44:26.205986
7330 12:44:26.208565 [DutyScan_Calibration_Flow] k_type=3
7331 12:44:26.226535
7332 12:44:26.227060 ==DQM 0 ==
7333 12:44:26.229984 Final DQM duty delay cell = 4
7334 12:44:26.233226 [4] MAX Duty = 5125%(X100), DQS PI = 8
7335 12:44:26.236574 [4] MIN Duty = 5000%(X100), DQS PI = 30
7336 12:44:26.239703 [4] AVG Duty = 5062%(X100)
7337 12:44:26.240171
7338 12:44:26.240538 ==DQM 1 ==
7339 12:44:26.243553 Final DQM duty delay cell = 0
7340 12:44:26.246399 [0] MAX Duty = 5249%(X100), DQS PI = 60
7341 12:44:26.249949 [0] MIN Duty = 4876%(X100), DQS PI = 34
7342 12:44:26.253263 [0] AVG Duty = 5062%(X100)
7343 12:44:26.253719
7344 12:44:26.256556 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7345 12:44:26.257047
7346 12:44:26.259881 CH1 DQM 1 Duty spec in!! Max-Min= 373%
7347 12:44:26.263022 [DutyScan_Calibration_Flow] ====Done====
7348 12:44:26.263475
7349 12:44:26.266265 [DutyScan_Calibration_Flow] k_type=2
7350 12:44:26.283592
7351 12:44:26.284266 ==DQ 0 ==
7352 12:44:26.286687 Final DQ duty delay cell = 0
7353 12:44:26.290228 [0] MAX Duty = 5093%(X100), DQS PI = 18
7354 12:44:26.293102 [0] MIN Duty = 4969%(X100), DQS PI = 46
7355 12:44:26.296360 [0] AVG Duty = 5031%(X100)
7356 12:44:26.296813
7357 12:44:26.297252 ==DQ 1 ==
7358 12:44:26.299935 Final DQ duty delay cell = 0
7359 12:44:26.302947 [0] MAX Duty = 5062%(X100), DQS PI = 4
7360 12:44:26.306667 [0] MIN Duty = 4813%(X100), DQS PI = 34
7361 12:44:26.307124 [0] AVG Duty = 4937%(X100)
7362 12:44:26.310097
7363 12:44:26.313089 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7364 12:44:26.313551
7365 12:44:26.316412 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7366 12:44:26.319832 [DutyScan_Calibration_Flow] ====Done====
7367 12:44:26.323033 nWR fixed to 30
7368 12:44:26.323590 [ModeRegInit_LP4] CH0 RK0
7369 12:44:26.326223 [ModeRegInit_LP4] CH0 RK1
7370 12:44:26.329540 [ModeRegInit_LP4] CH1 RK0
7371 12:44:26.333594 [ModeRegInit_LP4] CH1 RK1
7372 12:44:26.334161 match AC timing 5
7373 12:44:26.339397 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7374 12:44:26.343120 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7375 12:44:26.346012 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7376 12:44:26.352777 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7377 12:44:26.355943 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7378 12:44:26.356424 [MiockJmeterHQA]
7379 12:44:26.356806
7380 12:44:26.359070 [DramcMiockJmeter] u1RxGatingPI = 0
7381 12:44:26.362685 0 : 4255, 4026
7382 12:44:26.363273 4 : 4253, 4027
7383 12:44:26.365706 8 : 4252, 4027
7384 12:44:26.366168 12 : 4252, 4027
7385 12:44:26.369290 16 : 4365, 4140
7386 12:44:26.369750 20 : 4363, 4138
7387 12:44:26.370114 24 : 4365, 4140
7388 12:44:26.372370 28 : 4250, 4027
7389 12:44:26.372830 32 : 4363, 4137
7390 12:44:26.375847 36 : 4250, 4027
7391 12:44:26.376315 40 : 4255, 4029
7392 12:44:26.379050 44 : 4253, 4027
7393 12:44:26.379510 48 : 4252, 4027
7394 12:44:26.382154 52 : 4250, 4027
7395 12:44:26.382615 56 : 4252, 4030
7396 12:44:26.382983 60 : 4250, 4027
7397 12:44:26.385856 64 : 4250, 4026
7398 12:44:26.386298 68 : 4363, 4140
7399 12:44:26.388749 72 : 4252, 4027
7400 12:44:26.389274 76 : 4253, 4029
7401 12:44:26.392262 80 : 4250, 4027
7402 12:44:26.392696 84 : 4360, 4137
7403 12:44:26.395836 88 : 4250, 3642
7404 12:44:26.396270 92 : 4252, 0
7405 12:44:26.396604 96 : 4250, 0
7406 12:44:26.398874 100 : 4252, 0
7407 12:44:26.399292 104 : 4249, 0
7408 12:44:26.399624 108 : 4360, 0
7409 12:44:26.402388 112 : 4361, 0
7410 12:44:26.402808 116 : 4363, 0
7411 12:44:26.405754 120 : 4249, 0
7412 12:44:26.406168 124 : 4250, 0
7413 12:44:26.406505 128 : 4250, 0
7414 12:44:26.408671 132 : 4250, 0
7415 12:44:26.409134 136 : 4250, 0
7416 12:44:26.412322 140 : 4250, 0
7417 12:44:26.412747 144 : 4252, 0
7418 12:44:26.413127 148 : 4250, 0
7419 12:44:26.415200 152 : 4361, 0
7420 12:44:26.415626 156 : 4250, 0
7421 12:44:26.419070 160 : 4360, 0
7422 12:44:26.419606 164 : 4361, 0
7423 12:44:26.419951 168 : 4247, 0
7424 12:44:26.421982 172 : 4361, 0
7425 12:44:26.422424 176 : 4250, 0
7426 12:44:26.422761 180 : 4250, 0
7427 12:44:26.425235 184 : 4360, 0
7428 12:44:26.425662 188 : 4250, 0
7429 12:44:26.428722 192 : 4250, 0
7430 12:44:26.429301 196 : 4250, 0
7431 12:44:26.429657 200 : 4250, 5
7432 12:44:26.431921 204 : 4250, 2305
7433 12:44:26.432310 208 : 4250, 4027
7434 12:44:26.434934 212 : 4250, 4027
7435 12:44:26.435361 216 : 4250, 4027
7436 12:44:26.438670 220 : 4250, 4027
7437 12:44:26.439195 224 : 4249, 4027
7438 12:44:26.441930 228 : 4360, 4138
7439 12:44:26.442462 232 : 4250, 4027
7440 12:44:26.444922 236 : 4250, 4027
7441 12:44:26.445374 240 : 4249, 4027
7442 12:44:26.448586 244 : 4250, 4027
7443 12:44:26.449233 248 : 4363, 4138
7444 12:44:26.451521 252 : 4250, 4027
7445 12:44:26.451954 256 : 4363, 4137
7446 12:44:26.452301 260 : 4250, 4027
7447 12:44:26.455150 264 : 4250, 4027
7448 12:44:26.455578 268 : 4252, 4029
7449 12:44:26.458246 272 : 4250, 4026
7450 12:44:26.458680 276 : 4250, 4027
7451 12:44:26.461888 280 : 4361, 4138
7452 12:44:26.462316 284 : 4250, 4027
7453 12:44:26.464608 288 : 4250, 4026
7454 12:44:26.465061 292 : 4250, 4027
7455 12:44:26.468198 296 : 4250, 4027
7456 12:44:26.468629 300 : 4360, 4137
7457 12:44:26.471395 304 : 4252, 4030
7458 12:44:26.471828 308 : 4361, 4137
7459 12:44:26.474874 312 : 4250, 3933
7460 12:44:26.475306 316 : 4250, 2049
7461 12:44:26.475654
7462 12:44:26.478471 MIOCK jitter meter ch=0
7463 12:44:26.478897
7464 12:44:26.481231 1T = (316-92) = 224 dly cells
7465 12:44:26.484737 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7466 12:44:26.485339 ==
7467 12:44:26.488112 Dram Type= 6, Freq= 0, CH_0, rank 0
7468 12:44:26.494599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7469 12:44:26.495026 ==
7470 12:44:26.498165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7471 12:44:26.504811 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7472 12:44:26.508075 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7473 12:44:26.514573 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7474 12:44:26.522317 [CA 0] Center 42 (12~72) winsize 61
7475 12:44:26.525616 [CA 1] Center 42 (12~72) winsize 61
7476 12:44:26.528958 [CA 2] Center 37 (7~67) winsize 61
7477 12:44:26.531999 [CA 3] Center 37 (7~67) winsize 61
7478 12:44:26.535486 [CA 4] Center 36 (6~66) winsize 61
7479 12:44:26.538426 [CA 5] Center 35 (5~65) winsize 61
7480 12:44:26.538893
7481 12:44:26.542115 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7482 12:44:26.542584
7483 12:44:26.545289 [CATrainingPosCal] consider 1 rank data
7484 12:44:26.548554 u2DelayCellTimex100 = 290/100 ps
7485 12:44:26.555241 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7486 12:44:26.558643 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7487 12:44:26.561999 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7488 12:44:26.565196 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7489 12:44:26.568412 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7490 12:44:26.571700 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7491 12:44:26.572174
7492 12:44:26.574941 CA PerBit enable=1, Macro0, CA PI delay=35
7493 12:44:26.575410
7494 12:44:26.578618 [CBTSetCACLKResult] CA Dly = 35
7495 12:44:26.581562 CS Dly: 9 (0~40)
7496 12:44:26.585140 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7497 12:44:26.588346 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7498 12:44:26.588818 ==
7499 12:44:26.591575 Dram Type= 6, Freq= 0, CH_0, rank 1
7500 12:44:26.598115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 12:44:26.598593 ==
7502 12:44:26.601699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 12:44:26.604723 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 12:44:26.611860 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 12:44:26.618179 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 12:44:26.625553 [CA 0] Center 43 (13~73) winsize 61
7507 12:44:26.628944 [CA 1] Center 43 (13~73) winsize 61
7508 12:44:26.631900 [CA 2] Center 38 (8~68) winsize 61
7509 12:44:26.635371 [CA 3] Center 38 (8~68) winsize 61
7510 12:44:26.638783 [CA 4] Center 36 (6~66) winsize 61
7511 12:44:26.642014 [CA 5] Center 36 (6~66) winsize 61
7512 12:44:26.642575
7513 12:44:26.645378 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 12:44:26.645914
7515 12:44:26.651870 [CATrainingPosCal] consider 2 rank data
7516 12:44:26.652350 u2DelayCellTimex100 = 290/100 ps
7517 12:44:26.658427 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7518 12:44:26.661829 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7519 12:44:26.664805 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7520 12:44:26.668534 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7521 12:44:26.671519 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7522 12:44:26.674806 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7523 12:44:26.675282
7524 12:44:26.678017 CA PerBit enable=1, Macro0, CA PI delay=35
7525 12:44:26.678495
7526 12:44:26.681298 [CBTSetCACLKResult] CA Dly = 35
7527 12:44:26.684941 CS Dly: 10 (0~43)
7528 12:44:26.688001 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 12:44:26.691391 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 12:44:26.691871
7531 12:44:26.694410 ----->DramcWriteLeveling(PI) begin...
7532 12:44:26.694911 ==
7533 12:44:26.697826 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 12:44:26.704576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 12:44:26.705207 ==
7536 12:44:26.707777 Write leveling (Byte 0): 37 => 37
7537 12:44:26.711394 Write leveling (Byte 1): 32 => 32
7538 12:44:26.714006 DramcWriteLeveling(PI) end<-----
7539 12:44:26.714488
7540 12:44:26.714868 ==
7541 12:44:26.717523 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 12:44:26.720922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 12:44:26.721436 ==
7544 12:44:26.724188 [Gating] SW mode calibration
7545 12:44:26.730782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7546 12:44:26.737722 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7547 12:44:26.741085 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 12:44:26.744368 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 12:44:26.750508 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7550 12:44:26.754179 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7551 12:44:26.757355 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7552 12:44:26.763792 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
7553 12:44:26.767339 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 12:44:26.770746 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 12:44:26.773750 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 12:44:26.780517 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 12:44:26.783558 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7558 12:44:26.786783 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7559 12:44:26.793912 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7560 12:44:26.797178 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7561 12:44:26.800512 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 12:44:26.807066 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 12:44:26.810494 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 12:44:26.813288 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 12:44:26.820322 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (1 1)
7566 12:44:26.823893 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7567 12:44:26.827106 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7568 12:44:26.833401 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7569 12:44:26.836640 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 12:44:26.840233 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 12:44:26.846474 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 12:44:26.849826 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 12:44:26.853108 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7574 12:44:26.859788 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 12:44:26.862875 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7576 12:44:26.865981 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7577 12:44:26.873026 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 12:44:26.876068 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:44:26.879444 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:44:26.886332 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:44:26.889360 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:44:26.892582 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:44:26.899335 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:44:26.902437 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:44:26.906343 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 12:44:26.912811 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 12:44:26.916477 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 12:44:26.918906 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 12:44:26.925886 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 12:44:26.929122 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 12:44:26.932346 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7592 12:44:26.935701 Total UI for P1: 0, mck2ui 16
7593 12:44:26.938887 best dqsien dly found for B0: ( 1, 9, 8)
7594 12:44:26.945467 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 12:44:26.948955 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 12:44:26.951840 Total UI for P1: 0, mck2ui 16
7597 12:44:26.955445 best dqsien dly found for B1: ( 1, 9, 20)
7598 12:44:26.958897 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7599 12:44:26.962056 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7600 12:44:26.962607
7601 12:44:26.965588 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7602 12:44:26.968634 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7603 12:44:26.972443 [Gating] SW calibration Done
7604 12:44:26.973063 ==
7605 12:44:26.975372 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 12:44:26.982365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 12:44:26.983036 ==
7608 12:44:26.983425 RX Vref Scan: 0
7609 12:44:26.983776
7610 12:44:26.984950 RX Vref 0 -> 0, step: 1
7611 12:44:26.985449
7612 12:44:26.988228 RX Delay 0 -> 252, step: 8
7613 12:44:26.991644 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7614 12:44:26.995172 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7615 12:44:26.998652 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7616 12:44:27.001546 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7617 12:44:27.008174 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7618 12:44:27.011864 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7619 12:44:27.014655 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7620 12:44:27.018236 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7621 12:44:27.021311 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7622 12:44:27.027982 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7623 12:44:27.031235 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7624 12:44:27.034547 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7625 12:44:27.038323 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7626 12:44:27.041532 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7627 12:44:27.047816 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7628 12:44:27.051480 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7629 12:44:27.051947 ==
7630 12:44:27.054364 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 12:44:27.057469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 12:44:27.057927 ==
7633 12:44:27.061219 DQS Delay:
7634 12:44:27.061680 DQS0 = 0, DQS1 = 0
7635 12:44:27.062051 DQM Delay:
7636 12:44:27.064403 DQM0 = 138, DQM1 = 126
7637 12:44:27.064868 DQ Delay:
7638 12:44:27.067573 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7639 12:44:27.071088 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7640 12:44:27.077416 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7641 12:44:27.081180 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7642 12:44:27.081742
7643 12:44:27.082114
7644 12:44:27.082456 ==
7645 12:44:27.084355 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 12:44:27.087797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 12:44:27.088338 ==
7648 12:44:27.088713
7649 12:44:27.089115
7650 12:44:27.090827 TX Vref Scan disable
7651 12:44:27.094312 == TX Byte 0 ==
7652 12:44:27.097576 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7653 12:44:27.100713 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7654 12:44:27.103926 == TX Byte 1 ==
7655 12:44:27.107298 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7656 12:44:27.110551 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7657 12:44:27.111021 ==
7658 12:44:27.113855 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 12:44:27.117083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 12:44:27.120171 ==
7661 12:44:27.133328
7662 12:44:27.136535 TX Vref early break, caculate TX vref
7663 12:44:27.139748 TX Vref=16, minBit 7, minWin=22, winSum=377
7664 12:44:27.142994 TX Vref=18, minBit 8, minWin=23, winSum=389
7665 12:44:27.146516 TX Vref=20, minBit 6, minWin=23, winSum=395
7666 12:44:27.149350 TX Vref=22, minBit 7, minWin=24, winSum=405
7667 12:44:27.153126 TX Vref=24, minBit 2, minWin=25, winSum=415
7668 12:44:27.159723 TX Vref=26, minBit 4, minWin=25, winSum=419
7669 12:44:27.162494 TX Vref=28, minBit 2, minWin=25, winSum=429
7670 12:44:27.165887 TX Vref=30, minBit 0, minWin=26, winSum=426
7671 12:44:27.169184 TX Vref=32, minBit 0, minWin=25, winSum=416
7672 12:44:27.172255 TX Vref=34, minBit 7, minWin=24, winSum=409
7673 12:44:27.179146 TX Vref=36, minBit 1, minWin=24, winSum=396
7674 12:44:27.182671 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
7675 12:44:27.183235
7676 12:44:27.185500 Final TX Range 0 Vref 30
7677 12:44:27.185970
7678 12:44:27.186337 ==
7679 12:44:27.188867 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 12:44:27.192269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 12:44:27.195502 ==
7682 12:44:27.195966
7683 12:44:27.196335
7684 12:44:27.196678 TX Vref Scan disable
7685 12:44:27.202167 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7686 12:44:27.202635 == TX Byte 0 ==
7687 12:44:27.205282 u2DelayCellOfst[0]=13 cells (4 PI)
7688 12:44:27.209142 u2DelayCellOfst[1]=16 cells (5 PI)
7689 12:44:27.212642 u2DelayCellOfst[2]=10 cells (3 PI)
7690 12:44:27.215711 u2DelayCellOfst[3]=10 cells (3 PI)
7691 12:44:27.218758 u2DelayCellOfst[4]=6 cells (2 PI)
7692 12:44:27.222369 u2DelayCellOfst[5]=0 cells (0 PI)
7693 12:44:27.225633 u2DelayCellOfst[6]=16 cells (5 PI)
7694 12:44:27.228669 u2DelayCellOfst[7]=13 cells (4 PI)
7695 12:44:27.232193 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7696 12:44:27.235527 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7697 12:44:27.238758 == TX Byte 1 ==
7698 12:44:27.242052 u2DelayCellOfst[8]=0 cells (0 PI)
7699 12:44:27.245426 u2DelayCellOfst[9]=0 cells (0 PI)
7700 12:44:27.248617 u2DelayCellOfst[10]=6 cells (2 PI)
7701 12:44:27.251603 u2DelayCellOfst[11]=3 cells (1 PI)
7702 12:44:27.255145 u2DelayCellOfst[12]=13 cells (4 PI)
7703 12:44:27.258019 u2DelayCellOfst[13]=10 cells (3 PI)
7704 12:44:27.261369 u2DelayCellOfst[14]=13 cells (4 PI)
7705 12:44:27.261837 u2DelayCellOfst[15]=10 cells (3 PI)
7706 12:44:27.268426 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7707 12:44:27.271807 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7708 12:44:27.274729 DramC Write-DBI on
7709 12:44:27.275192 ==
7710 12:44:27.278057 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 12:44:27.281576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 12:44:27.282043 ==
7713 12:44:27.282417
7714 12:44:27.282763
7715 12:44:27.284419 TX Vref Scan disable
7716 12:44:27.284880 == TX Byte 0 ==
7717 12:44:27.291351 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7718 12:44:27.291881 == TX Byte 1 ==
7719 12:44:27.297677 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7720 12:44:27.298227 DramC Write-DBI off
7721 12:44:27.298598
7722 12:44:27.298941 [DATLAT]
7723 12:44:27.301036 Freq=1600, CH0 RK0
7724 12:44:27.301505
7725 12:44:27.301877 DATLAT Default: 0xf
7726 12:44:27.304595 0, 0xFFFF, sum = 0
7727 12:44:27.307674 1, 0xFFFF, sum = 0
7728 12:44:27.308146 2, 0xFFFF, sum = 0
7729 12:44:27.311190 3, 0xFFFF, sum = 0
7730 12:44:27.311908 4, 0xFFFF, sum = 0
7731 12:44:27.314329 5, 0xFFFF, sum = 0
7732 12:44:27.314798 6, 0xFFFF, sum = 0
7733 12:44:27.317856 7, 0xFFFF, sum = 0
7734 12:44:27.318329 8, 0xFFFF, sum = 0
7735 12:44:27.321257 9, 0xFFFF, sum = 0
7736 12:44:27.321827 10, 0xFFFF, sum = 0
7737 12:44:27.325025 11, 0xFFFF, sum = 0
7738 12:44:27.325607 12, 0xFFFF, sum = 0
7739 12:44:27.327598 13, 0xFFFF, sum = 0
7740 12:44:27.328067 14, 0x0, sum = 1
7741 12:44:27.330739 15, 0x0, sum = 2
7742 12:44:27.331210 16, 0x0, sum = 3
7743 12:44:27.334102 17, 0x0, sum = 4
7744 12:44:27.334717 best_step = 15
7745 12:44:27.335105
7746 12:44:27.335455 ==
7747 12:44:27.337244 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 12:44:27.344188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 12:44:27.344730 ==
7750 12:44:27.345142 RX Vref Scan: 1
7751 12:44:27.345499
7752 12:44:27.347709 Set Vref Range= 24 -> 127
7753 12:44:27.348171
7754 12:44:27.350479 RX Vref 24 -> 127, step: 1
7755 12:44:27.350945
7756 12:44:27.354082 RX Delay 19 -> 252, step: 4
7757 12:44:27.354551
7758 12:44:27.357260 Set Vref, RX VrefLevel [Byte0]: 24
7759 12:44:27.360200 [Byte1]: 24
7760 12:44:27.360659
7761 12:44:27.363575 Set Vref, RX VrefLevel [Byte0]: 25
7762 12:44:27.366711 [Byte1]: 25
7763 12:44:27.367176
7764 12:44:27.370013 Set Vref, RX VrefLevel [Byte0]: 26
7765 12:44:27.373270 [Byte1]: 26
7766 12:44:27.373769
7767 12:44:27.376675 Set Vref, RX VrefLevel [Byte0]: 27
7768 12:44:27.380274 [Byte1]: 27
7769 12:44:27.384429
7770 12:44:27.387493 Set Vref, RX VrefLevel [Byte0]: 28
7771 12:44:27.390792 [Byte1]: 28
7772 12:44:27.391281
7773 12:44:27.393708 Set Vref, RX VrefLevel [Byte0]: 29
7774 12:44:27.397044 [Byte1]: 29
7775 12:44:27.397512
7776 12:44:27.400603 Set Vref, RX VrefLevel [Byte0]: 30
7777 12:44:27.403589 [Byte1]: 30
7778 12:44:27.404052
7779 12:44:27.406798 Set Vref, RX VrefLevel [Byte0]: 31
7780 12:44:27.410522 [Byte1]: 31
7781 12:44:27.414519
7782 12:44:27.414986 Set Vref, RX VrefLevel [Byte0]: 32
7783 12:44:27.417455 [Byte1]: 32
7784 12:44:27.422047
7785 12:44:27.422541 Set Vref, RX VrefLevel [Byte0]: 33
7786 12:44:27.425426 [Byte1]: 33
7787 12:44:27.429649
7788 12:44:27.430224 Set Vref, RX VrefLevel [Byte0]: 34
7789 12:44:27.433025 [Byte1]: 34
7790 12:44:27.437484
7791 12:44:27.438107 Set Vref, RX VrefLevel [Byte0]: 35
7792 12:44:27.440572 [Byte1]: 35
7793 12:44:27.444679
7794 12:44:27.445396 Set Vref, RX VrefLevel [Byte0]: 36
7795 12:44:27.448121 [Byte1]: 36
7796 12:44:27.452140
7797 12:44:27.452608 Set Vref, RX VrefLevel [Byte0]: 37
7798 12:44:27.455467 [Byte1]: 37
7799 12:44:27.459636
7800 12:44:27.460101 Set Vref, RX VrefLevel [Byte0]: 38
7801 12:44:27.463028 [Byte1]: 38
7802 12:44:27.467651
7803 12:44:27.468119 Set Vref, RX VrefLevel [Byte0]: 39
7804 12:44:27.470659 [Byte1]: 39
7805 12:44:27.474843
7806 12:44:27.475313 Set Vref, RX VrefLevel [Byte0]: 40
7807 12:44:27.478148 [Byte1]: 40
7808 12:44:27.482525
7809 12:44:27.482993 Set Vref, RX VrefLevel [Byte0]: 41
7810 12:44:27.486162 [Byte1]: 41
7811 12:44:27.490254
7812 12:44:27.490748 Set Vref, RX VrefLevel [Byte0]: 42
7813 12:44:27.493279 [Byte1]: 42
7814 12:44:27.497718
7815 12:44:27.498288 Set Vref, RX VrefLevel [Byte0]: 43
7816 12:44:27.501430 [Byte1]: 43
7817 12:44:27.505452
7818 12:44:27.505918 Set Vref, RX VrefLevel [Byte0]: 44
7819 12:44:27.508346 [Byte1]: 44
7820 12:44:27.513016
7821 12:44:27.513605 Set Vref, RX VrefLevel [Byte0]: 45
7822 12:44:27.519168 [Byte1]: 45
7823 12:44:27.519659
7824 12:44:27.522841 Set Vref, RX VrefLevel [Byte0]: 46
7825 12:44:27.526318 [Byte1]: 46
7826 12:44:27.526890
7827 12:44:27.529326 Set Vref, RX VrefLevel [Byte0]: 47
7828 12:44:27.532614 [Byte1]: 47
7829 12:44:27.533113
7830 12:44:27.535730 Set Vref, RX VrefLevel [Byte0]: 48
7831 12:44:27.539207 [Byte1]: 48
7832 12:44:27.543002
7833 12:44:27.543473 Set Vref, RX VrefLevel [Byte0]: 49
7834 12:44:27.546428 [Byte1]: 49
7835 12:44:27.550434
7836 12:44:27.550902 Set Vref, RX VrefLevel [Byte0]: 50
7837 12:44:27.554012 [Byte1]: 50
7838 12:44:27.558126
7839 12:44:27.558461 Set Vref, RX VrefLevel [Byte0]: 51
7840 12:44:27.561425 [Byte1]: 51
7841 12:44:27.565540
7842 12:44:27.565875 Set Vref, RX VrefLevel [Byte0]: 52
7843 12:44:27.568880 [Byte1]: 52
7844 12:44:27.573434
7845 12:44:27.573865 Set Vref, RX VrefLevel [Byte0]: 53
7846 12:44:27.576470 [Byte1]: 53
7847 12:44:27.580913
7848 12:44:27.581350 Set Vref, RX VrefLevel [Byte0]: 54
7849 12:44:27.584150 [Byte1]: 54
7850 12:44:27.588199
7851 12:44:27.588528 Set Vref, RX VrefLevel [Byte0]: 55
7852 12:44:27.591511 [Byte1]: 55
7853 12:44:27.595856
7854 12:44:27.596186 Set Vref, RX VrefLevel [Byte0]: 56
7855 12:44:27.599629 [Byte1]: 56
7856 12:44:27.603536
7857 12:44:27.604062 Set Vref, RX VrefLevel [Byte0]: 57
7858 12:44:27.607424 [Byte1]: 57
7859 12:44:27.611450
7860 12:44:27.611877 Set Vref, RX VrefLevel [Byte0]: 58
7861 12:44:27.614470 [Byte1]: 58
7862 12:44:27.618770
7863 12:44:27.619267 Set Vref, RX VrefLevel [Byte0]: 59
7864 12:44:27.622133 [Byte1]: 59
7865 12:44:27.626581
7866 12:44:27.627139 Set Vref, RX VrefLevel [Byte0]: 60
7867 12:44:27.629651 [Byte1]: 60
7868 12:44:27.633940
7869 12:44:27.634468 Set Vref, RX VrefLevel [Byte0]: 61
7870 12:44:27.637109 [Byte1]: 61
7871 12:44:27.642119
7872 12:44:27.642615 Set Vref, RX VrefLevel [Byte0]: 62
7873 12:44:27.645007 [Byte1]: 62
7874 12:44:27.649162
7875 12:44:27.649596 Set Vref, RX VrefLevel [Byte0]: 63
7876 12:44:27.652547 [Byte1]: 63
7877 12:44:27.656889
7878 12:44:27.657375 Set Vref, RX VrefLevel [Byte0]: 64
7879 12:44:27.659756 [Byte1]: 64
7880 12:44:27.664147
7881 12:44:27.664578 Set Vref, RX VrefLevel [Byte0]: 65
7882 12:44:27.667820 [Byte1]: 65
7883 12:44:27.671828
7884 12:44:27.672366 Set Vref, RX VrefLevel [Byte0]: 66
7885 12:44:27.675143 [Byte1]: 66
7886 12:44:27.679304
7887 12:44:27.679806 Set Vref, RX VrefLevel [Byte0]: 67
7888 12:44:27.682813 [Byte1]: 67
7889 12:44:27.686789
7890 12:44:27.687287 Set Vref, RX VrefLevel [Byte0]: 68
7891 12:44:27.690529 [Byte1]: 68
7892 12:44:27.694781
7893 12:44:27.695255 Set Vref, RX VrefLevel [Byte0]: 69
7894 12:44:27.697684 [Byte1]: 69
7895 12:44:27.702111
7896 12:44:27.702667 Set Vref, RX VrefLevel [Byte0]: 70
7897 12:44:27.705648 [Byte1]: 70
7898 12:44:27.709564
7899 12:44:27.710181 Set Vref, RX VrefLevel [Byte0]: 71
7900 12:44:27.713314 [Byte1]: 71
7901 12:44:27.717838
7902 12:44:27.718404 Set Vref, RX VrefLevel [Byte0]: 72
7903 12:44:27.720613 [Byte1]: 72
7904 12:44:27.724950
7905 12:44:27.725453 Set Vref, RX VrefLevel [Byte0]: 73
7906 12:44:27.728362 [Byte1]: 73
7907 12:44:27.732630
7908 12:44:27.733396 Set Vref, RX VrefLevel [Byte0]: 74
7909 12:44:27.735769 [Byte1]: 74
7910 12:44:27.739845
7911 12:44:27.740316 Set Vref, RX VrefLevel [Byte0]: 75
7912 12:44:27.743499 [Byte1]: 75
7913 12:44:27.748091
7914 12:44:27.748667 Set Vref, RX VrefLevel [Byte0]: 76
7915 12:44:27.751181 [Byte1]: 76
7916 12:44:27.755381
7917 12:44:27.755982 Set Vref, RX VrefLevel [Byte0]: 77
7918 12:44:27.758491 [Byte1]: 77
7919 12:44:27.762971
7920 12:44:27.763550 Final RX Vref Byte 0 = 63 to rank0
7921 12:44:27.765970 Final RX Vref Byte 1 = 62 to rank0
7922 12:44:27.769052 Final RX Vref Byte 0 = 63 to rank1
7923 12:44:27.772905 Final RX Vref Byte 1 = 62 to rank1==
7924 12:44:27.775867 Dram Type= 6, Freq= 0, CH_0, rank 0
7925 12:44:27.782496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7926 12:44:27.783060 ==
7927 12:44:27.783442 DQS Delay:
7928 12:44:27.783789 DQS0 = 0, DQS1 = 0
7929 12:44:27.786104 DQM Delay:
7930 12:44:27.786572 DQM0 = 135, DQM1 = 124
7931 12:44:27.789237 DQ Delay:
7932 12:44:27.792354 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7933 12:44:27.795936 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
7934 12:44:27.799553 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7935 12:44:27.802772 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7936 12:44:27.803273
7937 12:44:27.803652
7938 12:44:27.804041
7939 12:44:27.805785 [DramC_TX_OE_Calibration] TA2
7940 12:44:27.809290 Original DQ_B0 (3 6) =30, OEN = 27
7941 12:44:27.812605 Original DQ_B1 (3 6) =30, OEN = 27
7942 12:44:27.815909 24, 0x0, End_B0=24 End_B1=24
7943 12:44:27.816588 25, 0x0, End_B0=25 End_B1=25
7944 12:44:27.819230 26, 0x0, End_B0=26 End_B1=26
7945 12:44:27.822645 27, 0x0, End_B0=27 End_B1=27
7946 12:44:27.825651 28, 0x0, End_B0=28 End_B1=28
7947 12:44:27.828940 29, 0x0, End_B0=29 End_B1=29
7948 12:44:27.829465 30, 0x0, End_B0=30 End_B1=30
7949 12:44:27.832484 31, 0x4141, End_B0=30 End_B1=30
7950 12:44:27.835996 Byte0 end_step=30 best_step=27
7951 12:44:27.838981 Byte1 end_step=30 best_step=27
7952 12:44:27.842456 Byte0 TX OE(2T, 0.5T) = (3, 3)
7953 12:44:27.845734 Byte1 TX OE(2T, 0.5T) = (3, 3)
7954 12:44:27.846204
7955 12:44:27.846574
7956 12:44:27.852359 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7957 12:44:27.855968 CH0 RK0: MR19=303, MR18=1F1D
7958 12:44:27.862346 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
7959 12:44:27.862823
7960 12:44:27.865289 ----->DramcWriteLeveling(PI) begin...
7961 12:44:27.865764 ==
7962 12:44:27.868611 Dram Type= 6, Freq= 0, CH_0, rank 1
7963 12:44:27.871985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 12:44:27.872472 ==
7965 12:44:27.875340 Write leveling (Byte 0): 40 => 40
7966 12:44:27.879159 Write leveling (Byte 1): 30 => 30
7967 12:44:27.882386 DramcWriteLeveling(PI) end<-----
7968 12:44:27.882965
7969 12:44:27.883336 ==
7970 12:44:27.885388 Dram Type= 6, Freq= 0, CH_0, rank 1
7971 12:44:27.888854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 12:44:27.889358 ==
7973 12:44:27.891956 [Gating] SW mode calibration
7974 12:44:27.898850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7975 12:44:27.905046 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7976 12:44:27.908249 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 12:44:27.914867 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 12:44:27.918365 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 12:44:27.921707 1 4 12 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7980 12:44:27.928409 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7981 12:44:27.931883 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7982 12:44:27.934688 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7983 12:44:27.941401 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 12:44:27.945140 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 12:44:27.948592 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 12:44:27.955276 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7987 12:44:27.957624 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7988 12:44:27.961117 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7989 12:44:27.968095 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 12:44:27.971121 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 12:44:27.974819 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 12:44:27.981113 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 12:44:27.984732 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 12:44:27.988020 1 6 8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7995 12:44:27.994511 1 6 12 | B1->B0 | 2e2e 4545 | 0 0 | (0 0) (0 0)
7996 12:44:27.997771 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 12:44:28.001029 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 12:44:28.007818 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 12:44:28.010665 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 12:44:28.014112 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 12:44:28.020770 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 12:44:28.024320 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 12:44:28.027575 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8004 12:44:28.034261 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8005 12:44:28.037180 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:44:28.040780 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:44:28.047116 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:44:28.050405 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:44:28.053565 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:44:28.060074 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:44:28.063569 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:44:28.066997 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:44:28.073350 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 12:44:28.077283 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 12:44:28.080261 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 12:44:28.086457 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 12:44:28.089951 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 12:44:28.093320 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8019 12:44:28.096596 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8020 12:44:28.103689 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8021 12:44:28.106556 Total UI for P1: 0, mck2ui 16
8022 12:44:28.109980 best dqsien dly found for B0: ( 1, 9, 10)
8023 12:44:28.113172 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 12:44:28.116396 Total UI for P1: 0, mck2ui 16
8025 12:44:28.119604 best dqsien dly found for B1: ( 1, 9, 14)
8026 12:44:28.123082 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8027 12:44:28.126238 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8028 12:44:28.126704
8029 12:44:28.129774 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8030 12:44:28.136302 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8031 12:44:28.136882 [Gating] SW calibration Done
8032 12:44:28.137300 ==
8033 12:44:28.139808 Dram Type= 6, Freq= 0, CH_0, rank 1
8034 12:44:28.146302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8035 12:44:28.146772 ==
8036 12:44:28.147141 RX Vref Scan: 0
8037 12:44:28.147489
8038 12:44:28.149304 RX Vref 0 -> 0, step: 1
8039 12:44:28.149770
8040 12:44:28.152557 RX Delay 0 -> 252, step: 8
8041 12:44:28.156232 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8042 12:44:28.159194 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8043 12:44:28.162740 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8044 12:44:28.168949 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8045 12:44:28.172685 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8046 12:44:28.176014 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8047 12:44:28.179202 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8048 12:44:28.182265 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8049 12:44:28.189148 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8050 12:44:28.192638 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8051 12:44:28.195924 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8052 12:44:28.198980 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8053 12:44:28.202236 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8054 12:44:28.209228 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8055 12:44:28.212240 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8056 12:44:28.215490 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8057 12:44:28.216059 ==
8058 12:44:28.218575 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 12:44:28.222090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 12:44:28.222656 ==
8061 12:44:28.225670 DQS Delay:
8062 12:44:28.226138 DQS0 = 0, DQS1 = 0
8063 12:44:28.228762 DQM Delay:
8064 12:44:28.229275 DQM0 = 136, DQM1 = 125
8065 12:44:28.232099 DQ Delay:
8066 12:44:28.235391 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8067 12:44:28.238699 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8068 12:44:28.242386 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8069 12:44:28.245257 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8070 12:44:28.245734
8071 12:44:28.246113
8072 12:44:28.246459 ==
8073 12:44:28.248541 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 12:44:28.251955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 12:44:28.252431 ==
8076 12:44:28.252813
8077 12:44:28.255173
8078 12:44:28.255738 TX Vref Scan disable
8079 12:44:28.258332 == TX Byte 0 ==
8080 12:44:28.261707 Update DQ dly =996 (3 ,6, 36) DQ OEN =(3 ,3)
8081 12:44:28.265285 Update DQM dly =996 (3 ,6, 36) DQM OEN =(3 ,3)
8082 12:44:28.268309 == TX Byte 1 ==
8083 12:44:28.271480 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8084 12:44:28.274989 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8085 12:44:28.275467 ==
8086 12:44:28.278538 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 12:44:28.285076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 12:44:28.285611 ==
8089 12:44:28.298043
8090 12:44:28.301197 TX Vref early break, caculate TX vref
8091 12:44:28.304698 TX Vref=16, minBit 8, minWin=23, winSum=388
8092 12:44:28.307801 TX Vref=18, minBit 0, minWin=24, winSum=397
8093 12:44:28.310997 TX Vref=20, minBit 8, minWin=24, winSum=409
8094 12:44:28.314691 TX Vref=22, minBit 0, minWin=25, winSum=416
8095 12:44:28.317762 TX Vref=24, minBit 0, minWin=25, winSum=426
8096 12:44:28.324453 TX Vref=26, minBit 8, minWin=26, winSum=433
8097 12:44:28.327772 TX Vref=28, minBit 4, minWin=26, winSum=435
8098 12:44:28.330899 TX Vref=30, minBit 0, minWin=26, winSum=424
8099 12:44:28.334239 TX Vref=32, minBit 0, minWin=26, winSum=419
8100 12:44:28.337834 TX Vref=34, minBit 0, minWin=25, winSum=411
8101 12:44:28.344325 [TxChooseVref] Worse bit 4, Min win 26, Win sum 435, Final Vref 28
8102 12:44:28.344819
8103 12:44:28.347743 Final TX Range 0 Vref 28
8104 12:44:28.348298
8105 12:44:28.348682 ==
8106 12:44:28.350458 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 12:44:28.354302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 12:44:28.354776 ==
8109 12:44:28.355157
8110 12:44:28.355512
8111 12:44:28.357088 TX Vref Scan disable
8112 12:44:28.363902 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8113 12:44:28.364526 == TX Byte 0 ==
8114 12:44:28.367193 u2DelayCellOfst[0]=13 cells (4 PI)
8115 12:44:28.370518 u2DelayCellOfst[1]=16 cells (5 PI)
8116 12:44:28.374095 u2DelayCellOfst[2]=13 cells (4 PI)
8117 12:44:28.376933 u2DelayCellOfst[3]=13 cells (4 PI)
8118 12:44:28.380915 u2DelayCellOfst[4]=10 cells (3 PI)
8119 12:44:28.383604 u2DelayCellOfst[5]=0 cells (0 PI)
8120 12:44:28.387381 u2DelayCellOfst[6]=20 cells (6 PI)
8121 12:44:28.390558 u2DelayCellOfst[7]=20 cells (6 PI)
8122 12:44:28.393575 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8123 12:44:28.397276 Update DQM dly =996 (3 ,6, 36) DQM OEN =(3 ,3)
8124 12:44:28.400290 == TX Byte 1 ==
8125 12:44:28.403672 u2DelayCellOfst[8]=0 cells (0 PI)
8126 12:44:28.407320 u2DelayCellOfst[9]=0 cells (0 PI)
8127 12:44:28.409956 u2DelayCellOfst[10]=6 cells (2 PI)
8128 12:44:28.410441 u2DelayCellOfst[11]=3 cells (1 PI)
8129 12:44:28.413278 u2DelayCellOfst[12]=13 cells (4 PI)
8130 12:44:28.416957 u2DelayCellOfst[13]=13 cells (4 PI)
8131 12:44:28.420333 u2DelayCellOfst[14]=16 cells (5 PI)
8132 12:44:28.423575 u2DelayCellOfst[15]=10 cells (3 PI)
8133 12:44:28.429820 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8134 12:44:28.433204 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8135 12:44:28.433775 DramC Write-DBI on
8136 12:44:28.436906 ==
8137 12:44:28.437526 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 12:44:28.442838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 12:44:28.443374 ==
8140 12:44:28.443745
8141 12:44:28.444097
8142 12:44:28.446025 TX Vref Scan disable
8143 12:44:28.446490 == TX Byte 0 ==
8144 12:44:28.452721 Update DQM dly =739 (2 ,6, 35) DQM OEN =(3 ,3)
8145 12:44:28.453219 == TX Byte 1 ==
8146 12:44:28.456137 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8147 12:44:28.459403 DramC Write-DBI off
8148 12:44:28.459876
8149 12:44:28.460440 [DATLAT]
8150 12:44:28.462777 Freq=1600, CH0 RK1
8151 12:44:28.463251
8152 12:44:28.463621 DATLAT Default: 0xf
8153 12:44:28.465980 0, 0xFFFF, sum = 0
8154 12:44:28.466539 1, 0xFFFF, sum = 0
8155 12:44:28.469090 2, 0xFFFF, sum = 0
8156 12:44:28.469562 3, 0xFFFF, sum = 0
8157 12:44:28.472532 4, 0xFFFF, sum = 0
8158 12:44:28.476222 5, 0xFFFF, sum = 0
8159 12:44:28.476696 6, 0xFFFF, sum = 0
8160 12:44:28.479429 7, 0xFFFF, sum = 0
8161 12:44:28.480005 8, 0xFFFF, sum = 0
8162 12:44:28.482458 9, 0xFFFF, sum = 0
8163 12:44:28.482932 10, 0xFFFF, sum = 0
8164 12:44:28.485704 11, 0xFFFF, sum = 0
8165 12:44:28.486176 12, 0xFFFF, sum = 0
8166 12:44:28.489002 13, 0xFFFF, sum = 0
8167 12:44:28.489466 14, 0x0, sum = 1
8168 12:44:28.492160 15, 0x0, sum = 2
8169 12:44:28.492589 16, 0x0, sum = 3
8170 12:44:28.495522 17, 0x0, sum = 4
8171 12:44:28.495948 best_step = 15
8172 12:44:28.496283
8173 12:44:28.496597 ==
8174 12:44:28.499054 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 12:44:28.502345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 12:44:28.505905 ==
8177 12:44:28.506330 RX Vref Scan: 0
8178 12:44:28.506668
8179 12:44:28.509466 RX Vref 0 -> 0, step: 1
8180 12:44:28.509883
8181 12:44:28.512256 RX Delay 11 -> 252, step: 4
8182 12:44:28.515387 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8183 12:44:28.518692 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8184 12:44:28.522180 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8185 12:44:28.528723 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8186 12:44:28.531807 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8187 12:44:28.535295 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8188 12:44:28.538712 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8189 12:44:28.541792 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8190 12:44:28.548385 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8191 12:44:28.552325 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8192 12:44:28.555056 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8193 12:44:28.558359 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8194 12:44:28.561789 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8195 12:44:28.568318 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8196 12:44:28.571544 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8197 12:44:28.574921 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8198 12:44:28.575347 ==
8199 12:44:28.578101 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 12:44:28.581427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 12:44:28.584667 ==
8202 12:44:28.585211 DQS Delay:
8203 12:44:28.585563 DQS0 = 0, DQS1 = 0
8204 12:44:28.587782 DQM Delay:
8205 12:44:28.588260 DQM0 = 133, DQM1 = 123
8206 12:44:28.591249 DQ Delay:
8207 12:44:28.594667 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8208 12:44:28.597710 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8209 12:44:28.601073 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8210 12:44:28.604608 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8211 12:44:28.605150
8212 12:44:28.605499
8213 12:44:28.605816
8214 12:44:28.607606 [DramC_TX_OE_Calibration] TA2
8215 12:44:28.610848 Original DQ_B0 (3 6) =30, OEN = 27
8216 12:44:28.614478 Original DQ_B1 (3 6) =30, OEN = 27
8217 12:44:28.617456 24, 0x0, End_B0=24 End_B1=24
8218 12:44:28.617884 25, 0x0, End_B0=25 End_B1=25
8219 12:44:28.621091 26, 0x0, End_B0=26 End_B1=26
8220 12:44:28.624615 27, 0x0, End_B0=27 End_B1=27
8221 12:44:28.627508 28, 0x0, End_B0=28 End_B1=28
8222 12:44:28.627955 29, 0x0, End_B0=29 End_B1=29
8223 12:44:28.631002 30, 0x0, End_B0=30 End_B1=30
8224 12:44:28.634613 31, 0x4545, End_B0=30 End_B1=30
8225 12:44:28.637675 Byte0 end_step=30 best_step=27
8226 12:44:28.641027 Byte1 end_step=30 best_step=27
8227 12:44:28.644513 Byte0 TX OE(2T, 0.5T) = (3, 3)
8228 12:44:28.647608 Byte1 TX OE(2T, 0.5T) = (3, 3)
8229 12:44:28.648149
8230 12:44:28.648524
8231 12:44:28.653938 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8232 12:44:28.657325 CH0 RK1: MR19=303, MR18=1E0C
8233 12:44:28.663952 CH0_RK1: MR19=0x303, MR18=0x1E0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8234 12:44:28.667367 [RxdqsGatingPostProcess] freq 1600
8235 12:44:28.670774 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8236 12:44:28.673941 best DQS0 dly(2T, 0.5T) = (1, 1)
8237 12:44:28.677479 best DQS1 dly(2T, 0.5T) = (1, 1)
8238 12:44:28.680831 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8239 12:44:28.683665 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8240 12:44:28.687018 best DQS0 dly(2T, 0.5T) = (1, 1)
8241 12:44:28.690248 best DQS1 dly(2T, 0.5T) = (1, 1)
8242 12:44:28.693807 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8243 12:44:28.697107 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8244 12:44:28.700728 Pre-setting of DQS Precalculation
8245 12:44:28.703519 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8246 12:44:28.704084 ==
8247 12:44:28.706837 Dram Type= 6, Freq= 0, CH_1, rank 0
8248 12:44:28.713678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 12:44:28.714251 ==
8250 12:44:28.717013 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8251 12:44:28.720348 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8252 12:44:28.726512 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8253 12:44:28.733168 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8254 12:44:28.740839 [CA 0] Center 41 (12~71) winsize 60
8255 12:44:28.744312 [CA 1] Center 42 (12~72) winsize 61
8256 12:44:28.747441 [CA 2] Center 38 (9~67) winsize 59
8257 12:44:28.750190 [CA 3] Center 36 (7~66) winsize 60
8258 12:44:28.753627 [CA 4] Center 37 (7~68) winsize 62
8259 12:44:28.757360 [CA 5] Center 36 (7~66) winsize 60
8260 12:44:28.757940
8261 12:44:28.761085 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8262 12:44:28.761674
8263 12:44:28.763904 [CATrainingPosCal] consider 1 rank data
8264 12:44:28.767093 u2DelayCellTimex100 = 290/100 ps
8265 12:44:28.773471 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8266 12:44:28.777103 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8267 12:44:28.780314 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8268 12:44:28.783522 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8269 12:44:28.786973 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8270 12:44:28.790037 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8271 12:44:28.790465
8272 12:44:28.793435 CA PerBit enable=1, Macro0, CA PI delay=36
8273 12:44:28.793877
8274 12:44:28.796844 [CBTSetCACLKResult] CA Dly = 36
8275 12:44:28.800177 CS Dly: 9 (0~40)
8276 12:44:28.803234 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8277 12:44:28.806493 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8278 12:44:28.806920 ==
8279 12:44:28.810358 Dram Type= 6, Freq= 0, CH_1, rank 1
8280 12:44:28.813457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 12:44:28.816669 ==
8282 12:44:28.820001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8283 12:44:28.823138 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8284 12:44:28.829547 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8285 12:44:28.836065 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8286 12:44:28.843865 [CA 0] Center 42 (13~72) winsize 60
8287 12:44:28.846711 [CA 1] Center 42 (12~72) winsize 61
8288 12:44:28.850294 [CA 2] Center 38 (9~68) winsize 60
8289 12:44:28.853397 [CA 3] Center 37 (8~67) winsize 60
8290 12:44:28.856949 [CA 4] Center 38 (9~67) winsize 59
8291 12:44:28.860644 [CA 5] Center 37 (8~67) winsize 60
8292 12:44:28.861266
8293 12:44:28.863592 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8294 12:44:28.864091
8295 12:44:28.866989 [CATrainingPosCal] consider 2 rank data
8296 12:44:28.870111 u2DelayCellTimex100 = 290/100 ps
8297 12:44:28.873437 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8298 12:44:28.879944 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8299 12:44:28.883143 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8300 12:44:28.886451 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8301 12:44:28.889684 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8302 12:44:28.893380 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8303 12:44:28.893928
8304 12:44:28.896333 CA PerBit enable=1, Macro0, CA PI delay=37
8305 12:44:28.896641
8306 12:44:28.899715 [CBTSetCACLKResult] CA Dly = 37
8307 12:44:28.902757 CS Dly: 10 (0~42)
8308 12:44:28.905861 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8309 12:44:28.909531 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8310 12:44:28.909828
8311 12:44:28.912781 ----->DramcWriteLeveling(PI) begin...
8312 12:44:28.913029 ==
8313 12:44:28.916384 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 12:44:28.922687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 12:44:28.923119 ==
8316 12:44:28.926996 Write leveling (Byte 0): 24 => 24
8317 12:44:28.929309 Write leveling (Byte 1): 30 => 30
8318 12:44:28.929805 DramcWriteLeveling(PI) end<-----
8319 12:44:28.930188
8320 12:44:28.932672 ==
8321 12:44:28.936296 Dram Type= 6, Freq= 0, CH_1, rank 0
8322 12:44:28.939373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 12:44:28.939903 ==
8324 12:44:28.942803 [Gating] SW mode calibration
8325 12:44:28.949313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8326 12:44:28.952634 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8327 12:44:28.959113 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 12:44:28.962356 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 12:44:28.965918 1 4 8 | B1->B0 | 2929 2c2c | 1 0 | (1 1) (0 0)
8330 12:44:28.972268 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 12:44:28.975560 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 12:44:28.979011 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 12:44:28.986005 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 12:44:28.988944 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 12:44:28.991983 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 12:44:28.999161 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8337 12:44:29.002107 1 5 8 | B1->B0 | 2929 2929 | 0 1 | (0 0) (1 0)
8338 12:44:29.005250 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8339 12:44:29.011971 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 12:44:29.015362 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 12:44:29.018874 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 12:44:29.025284 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 12:44:29.028681 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 12:44:29.031847 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8345 12:44:29.038078 1 6 8 | B1->B0 | 3c3c 4444 | 1 0 | (0 0) (0 0)
8346 12:44:29.041385 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 12:44:29.045083 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 12:44:29.051879 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 12:44:29.054912 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 12:44:29.058144 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 12:44:29.064769 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:44:29.067967 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 12:44:29.071586 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8354 12:44:29.077829 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8355 12:44:29.081352 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:44:29.084464 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:44:29.091496 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:44:29.094368 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:44:29.097821 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:44:29.104277 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:44:29.107694 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:44:29.110995 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:44:29.117743 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:44:29.121494 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:44:29.124416 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 12:44:29.130746 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 12:44:29.134139 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 12:44:29.137194 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8369 12:44:29.143820 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8370 12:44:29.147629 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8371 12:44:29.150570 Total UI for P1: 0, mck2ui 16
8372 12:44:29.153859 best dqsien dly found for B0: ( 1, 9, 6)
8373 12:44:29.157669 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 12:44:29.160642 Total UI for P1: 0, mck2ui 16
8375 12:44:29.163713 best dqsien dly found for B1: ( 1, 9, 10)
8376 12:44:29.167304 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8377 12:44:29.171110 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8378 12:44:29.171687
8379 12:44:29.177222 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8380 12:44:29.180544 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8381 12:44:29.181080 [Gating] SW calibration Done
8382 12:44:29.183758 ==
8383 12:44:29.187392 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 12:44:29.190621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 12:44:29.191198 ==
8386 12:44:29.191578 RX Vref Scan: 0
8387 12:44:29.191931
8388 12:44:29.193680 RX Vref 0 -> 0, step: 1
8389 12:44:29.194151
8390 12:44:29.197073 RX Delay 0 -> 252, step: 8
8391 12:44:29.200301 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8392 12:44:29.203567 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8393 12:44:29.207100 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8394 12:44:29.213760 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8395 12:44:29.216630 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8396 12:44:29.220139 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8397 12:44:29.223678 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8398 12:44:29.226932 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8399 12:44:29.233371 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8400 12:44:29.236768 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8401 12:44:29.240159 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8402 12:44:29.243625 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8403 12:44:29.247069 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8404 12:44:29.253385 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8405 12:44:29.256453 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8406 12:44:29.259874 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8407 12:44:29.260447 ==
8408 12:44:29.263406 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 12:44:29.266582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 12:44:29.269648 ==
8411 12:44:29.270126 DQS Delay:
8412 12:44:29.270503 DQS0 = 0, DQS1 = 0
8413 12:44:29.273167 DQM Delay:
8414 12:44:29.273640 DQM0 = 137, DQM1 = 130
8415 12:44:29.276404 DQ Delay:
8416 12:44:29.279514 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8417 12:44:29.282959 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8418 12:44:29.286379 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8419 12:44:29.289585 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8420 12:44:29.290245
8421 12:44:29.290803
8422 12:44:29.291345 ==
8423 12:44:29.292924 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 12:44:29.295902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 12:44:29.296334 ==
8426 12:44:29.296680
8427 12:44:29.299335
8428 12:44:29.299763 TX Vref Scan disable
8429 12:44:29.302876 == TX Byte 0 ==
8430 12:44:29.305963 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8431 12:44:29.309268 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8432 12:44:29.312931 == TX Byte 1 ==
8433 12:44:29.315984 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8434 12:44:29.319208 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8435 12:44:29.319637 ==
8436 12:44:29.322813 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 12:44:29.329477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 12:44:29.329910 ==
8439 12:44:29.341715
8440 12:44:29.344392 TX Vref early break, caculate TX vref
8441 12:44:29.347860 TX Vref=16, minBit 10, minWin=21, winSum=367
8442 12:44:29.351101 TX Vref=18, minBit 10, minWin=22, winSum=378
8443 12:44:29.354409 TX Vref=20, minBit 10, minWin=22, winSum=383
8444 12:44:29.357737 TX Vref=22, minBit 8, minWin=23, winSum=392
8445 12:44:29.364530 TX Vref=24, minBit 8, minWin=24, winSum=402
8446 12:44:29.367230 TX Vref=26, minBit 11, minWin=24, winSum=410
8447 12:44:29.370519 TX Vref=28, minBit 9, minWin=24, winSum=416
8448 12:44:29.374313 TX Vref=30, minBit 9, minWin=24, winSum=408
8449 12:44:29.377596 TX Vref=32, minBit 8, minWin=23, winSum=401
8450 12:44:29.380610 TX Vref=34, minBit 13, minWin=22, winSum=394
8451 12:44:29.387896 [TxChooseVref] Worse bit 9, Min win 24, Win sum 416, Final Vref 28
8452 12:44:29.388466
8453 12:44:29.390701 Final TX Range 0 Vref 28
8454 12:44:29.391285
8455 12:44:29.391659 ==
8456 12:44:29.393930 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 12:44:29.397169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 12:44:29.397639 ==
8459 12:44:29.400366
8460 12:44:29.400931
8461 12:44:29.401359 TX Vref Scan disable
8462 12:44:29.406719 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8463 12:44:29.407190 == TX Byte 0 ==
8464 12:44:29.410560 u2DelayCellOfst[0]=16 cells (5 PI)
8465 12:44:29.413573 u2DelayCellOfst[1]=10 cells (3 PI)
8466 12:44:29.417064 u2DelayCellOfst[2]=0 cells (0 PI)
8467 12:44:29.420095 u2DelayCellOfst[3]=6 cells (2 PI)
8468 12:44:29.423563 u2DelayCellOfst[4]=6 cells (2 PI)
8469 12:44:29.426613 u2DelayCellOfst[5]=16 cells (5 PI)
8470 12:44:29.430056 u2DelayCellOfst[6]=16 cells (5 PI)
8471 12:44:29.433364 u2DelayCellOfst[7]=6 cells (2 PI)
8472 12:44:29.436345 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8473 12:44:29.439990 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8474 12:44:29.443068 == TX Byte 1 ==
8475 12:44:29.446269 u2DelayCellOfst[8]=0 cells (0 PI)
8476 12:44:29.450040 u2DelayCellOfst[9]=3 cells (1 PI)
8477 12:44:29.453082 u2DelayCellOfst[10]=10 cells (3 PI)
8478 12:44:29.456709 u2DelayCellOfst[11]=3 cells (1 PI)
8479 12:44:29.459834 u2DelayCellOfst[12]=13 cells (4 PI)
8480 12:44:29.463145 u2DelayCellOfst[13]=16 cells (5 PI)
8481 12:44:29.463748 u2DelayCellOfst[14]=16 cells (5 PI)
8482 12:44:29.466524 u2DelayCellOfst[15]=16 cells (5 PI)
8483 12:44:29.472939 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8484 12:44:29.476241 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8485 12:44:29.479852 DramC Write-DBI on
8486 12:44:29.480433 ==
8487 12:44:29.483079 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 12:44:29.486404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 12:44:29.486988 ==
8490 12:44:29.487477
8491 12:44:29.487933
8492 12:44:29.489543 TX Vref Scan disable
8493 12:44:29.490028 == TX Byte 0 ==
8494 12:44:29.496388 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8495 12:44:29.496875 == TX Byte 1 ==
8496 12:44:29.499768 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8497 12:44:29.502806 DramC Write-DBI off
8498 12:44:29.503382
8499 12:44:29.503877 [DATLAT]
8500 12:44:29.506433 Freq=1600, CH1 RK0
8501 12:44:29.507013
8502 12:44:29.507505 DATLAT Default: 0xf
8503 12:44:29.509194 0, 0xFFFF, sum = 0
8504 12:44:29.509684 1, 0xFFFF, sum = 0
8505 12:44:29.512594 2, 0xFFFF, sum = 0
8506 12:44:29.513219 3, 0xFFFF, sum = 0
8507 12:44:29.516047 4, 0xFFFF, sum = 0
8508 12:44:29.519301 5, 0xFFFF, sum = 0
8509 12:44:29.519896 6, 0xFFFF, sum = 0
8510 12:44:29.522567 7, 0xFFFF, sum = 0
8511 12:44:29.523154 8, 0xFFFF, sum = 0
8512 12:44:29.525639 9, 0xFFFF, sum = 0
8513 12:44:29.526130 10, 0xFFFF, sum = 0
8514 12:44:29.528922 11, 0xFFFF, sum = 0
8515 12:44:29.529436 12, 0xFFFF, sum = 0
8516 12:44:29.532686 13, 0xFFFF, sum = 0
8517 12:44:29.533303 14, 0x0, sum = 1
8518 12:44:29.536032 15, 0x0, sum = 2
8519 12:44:29.536614 16, 0x0, sum = 3
8520 12:44:29.539391 17, 0x0, sum = 4
8521 12:44:29.539964 best_step = 15
8522 12:44:29.540335
8523 12:44:29.540681 ==
8524 12:44:29.542295 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 12:44:29.545891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 12:44:29.549222 ==
8527 12:44:29.549788 RX Vref Scan: 1
8528 12:44:29.550178
8529 12:44:29.552445 Set Vref Range= 24 -> 127
8530 12:44:29.552957
8531 12:44:29.555483 RX Vref 24 -> 127, step: 1
8532 12:44:29.556050
8533 12:44:29.556421 RX Delay 19 -> 252, step: 4
8534 12:44:29.556768
8535 12:44:29.559121 Set Vref, RX VrefLevel [Byte0]: 24
8536 12:44:29.562388 [Byte1]: 24
8537 12:44:29.565956
8538 12:44:29.566519 Set Vref, RX VrefLevel [Byte0]: 25
8539 12:44:29.569190 [Byte1]: 25
8540 12:44:29.573519
8541 12:44:29.573985 Set Vref, RX VrefLevel [Byte0]: 26
8542 12:44:29.577153 [Byte1]: 26
8543 12:44:29.581768
8544 12:44:29.582340 Set Vref, RX VrefLevel [Byte0]: 27
8545 12:44:29.584388 [Byte1]: 27
8546 12:44:29.588898
8547 12:44:29.589510 Set Vref, RX VrefLevel [Byte0]: 28
8548 12:44:29.592401 [Byte1]: 28
8549 12:44:29.596319
8550 12:44:29.596784 Set Vref, RX VrefLevel [Byte0]: 29
8551 12:44:29.599964 [Byte1]: 29
8552 12:44:29.604090
8553 12:44:29.604653 Set Vref, RX VrefLevel [Byte0]: 30
8554 12:44:29.607621 [Byte1]: 30
8555 12:44:29.611714
8556 12:44:29.612291 Set Vref, RX VrefLevel [Byte0]: 31
8557 12:44:29.614927 [Byte1]: 31
8558 12:44:29.619150
8559 12:44:29.619718 Set Vref, RX VrefLevel [Byte0]: 32
8560 12:44:29.622514 [Byte1]: 32
8561 12:44:29.626731
8562 12:44:29.627333 Set Vref, RX VrefLevel [Byte0]: 33
8563 12:44:29.630004 [Byte1]: 33
8564 12:44:29.634156
8565 12:44:29.634754 Set Vref, RX VrefLevel [Byte0]: 34
8566 12:44:29.637473 [Byte1]: 34
8567 12:44:29.641896
8568 12:44:29.642474 Set Vref, RX VrefLevel [Byte0]: 35
8569 12:44:29.645146 [Byte1]: 35
8570 12:44:29.649519
8571 12:44:29.650099 Set Vref, RX VrefLevel [Byte0]: 36
8572 12:44:29.652802 [Byte1]: 36
8573 12:44:29.657708
8574 12:44:29.658278 Set Vref, RX VrefLevel [Byte0]: 37
8575 12:44:29.660184 [Byte1]: 37
8576 12:44:29.664383
8577 12:44:29.664970 Set Vref, RX VrefLevel [Byte0]: 38
8578 12:44:29.668023 [Byte1]: 38
8579 12:44:29.672138
8580 12:44:29.672715 Set Vref, RX VrefLevel [Byte0]: 39
8581 12:44:29.675636 [Byte1]: 39
8582 12:44:29.679690
8583 12:44:29.680166 Set Vref, RX VrefLevel [Byte0]: 40
8584 12:44:29.682737 [Byte1]: 40
8585 12:44:29.687556
8586 12:44:29.688136 Set Vref, RX VrefLevel [Byte0]: 41
8587 12:44:29.690518 [Byte1]: 41
8588 12:44:29.694962
8589 12:44:29.695540 Set Vref, RX VrefLevel [Byte0]: 42
8590 12:44:29.698139 [Byte1]: 42
8591 12:44:29.702298
8592 12:44:29.702912 Set Vref, RX VrefLevel [Byte0]: 43
8593 12:44:29.705642 [Byte1]: 43
8594 12:44:29.710251
8595 12:44:29.710832 Set Vref, RX VrefLevel [Byte0]: 44
8596 12:44:29.713425 [Byte1]: 44
8597 12:44:29.717608
8598 12:44:29.718186 Set Vref, RX VrefLevel [Byte0]: 45
8599 12:44:29.720877 [Byte1]: 45
8600 12:44:29.725362
8601 12:44:29.725945 Set Vref, RX VrefLevel [Byte0]: 46
8602 12:44:29.728725 [Byte1]: 46
8603 12:44:29.732618
8604 12:44:29.733233 Set Vref, RX VrefLevel [Byte0]: 47
8605 12:44:29.735943 [Byte1]: 47
8606 12:44:29.740439
8607 12:44:29.741124 Set Vref, RX VrefLevel [Byte0]: 48
8608 12:44:29.743719 [Byte1]: 48
8609 12:44:29.748000
8610 12:44:29.748601 Set Vref, RX VrefLevel [Byte0]: 49
8611 12:44:29.751218 [Byte1]: 49
8612 12:44:29.755443
8613 12:44:29.755956 Set Vref, RX VrefLevel [Byte0]: 50
8614 12:44:29.758728 [Byte1]: 50
8615 12:44:29.762977
8616 12:44:29.766361 Set Vref, RX VrefLevel [Byte0]: 51
8617 12:44:29.766948 [Byte1]: 51
8618 12:44:29.770583
8619 12:44:29.771167 Set Vref, RX VrefLevel [Byte0]: 52
8620 12:44:29.773898 [Byte1]: 52
8621 12:44:29.778463
8622 12:44:29.779109 Set Vref, RX VrefLevel [Byte0]: 53
8623 12:44:29.781420 [Byte1]: 53
8624 12:44:29.785630
8625 12:44:29.786208 Set Vref, RX VrefLevel [Byte0]: 54
8626 12:44:29.789069 [Byte1]: 54
8627 12:44:29.793585
8628 12:44:29.794168 Set Vref, RX VrefLevel [Byte0]: 55
8629 12:44:29.796809 [Byte1]: 55
8630 12:44:29.800830
8631 12:44:29.801444 Set Vref, RX VrefLevel [Byte0]: 56
8632 12:44:29.804190 [Byte1]: 56
8633 12:44:29.808688
8634 12:44:29.809385 Set Vref, RX VrefLevel [Byte0]: 57
8635 12:44:29.811718 [Byte1]: 57
8636 12:44:29.816169
8637 12:44:29.816742 Set Vref, RX VrefLevel [Byte0]: 58
8638 12:44:29.819382 [Byte1]: 58
8639 12:44:29.823762
8640 12:44:29.824332 Set Vref, RX VrefLevel [Byte0]: 59
8641 12:44:29.826955 [Byte1]: 59
8642 12:44:29.831340
8643 12:44:29.831908 Set Vref, RX VrefLevel [Byte0]: 60
8644 12:44:29.834387 [Byte1]: 60
8645 12:44:29.838996
8646 12:44:29.839596 Set Vref, RX VrefLevel [Byte0]: 61
8647 12:44:29.841981 [Byte1]: 61
8648 12:44:29.846283
8649 12:44:29.846857 Set Vref, RX VrefLevel [Byte0]: 62
8650 12:44:29.849569 [Byte1]: 62
8651 12:44:29.854066
8652 12:44:29.854633 Set Vref, RX VrefLevel [Byte0]: 63
8653 12:44:29.857395 [Byte1]: 63
8654 12:44:29.861500
8655 12:44:29.862081 Set Vref, RX VrefLevel [Byte0]: 64
8656 12:44:29.864561 [Byte1]: 64
8657 12:44:29.869363
8658 12:44:29.869981 Set Vref, RX VrefLevel [Byte0]: 65
8659 12:44:29.872283 [Byte1]: 65
8660 12:44:29.876729
8661 12:44:29.877361 Set Vref, RX VrefLevel [Byte0]: 66
8662 12:44:29.879712 [Byte1]: 66
8663 12:44:29.883848
8664 12:44:29.884396 Set Vref, RX VrefLevel [Byte0]: 67
8665 12:44:29.887243 [Byte1]: 67
8666 12:44:29.891486
8667 12:44:29.892035 Set Vref, RX VrefLevel [Byte0]: 68
8668 12:44:29.894567 [Byte1]: 68
8669 12:44:29.899228
8670 12:44:29.899834 Set Vref, RX VrefLevel [Byte0]: 69
8671 12:44:29.902306 [Byte1]: 69
8672 12:44:29.906815
8673 12:44:29.907384 Set Vref, RX VrefLevel [Byte0]: 70
8674 12:44:29.909993 [Byte1]: 70
8675 12:44:29.914523
8676 12:44:29.915102 Set Vref, RX VrefLevel [Byte0]: 71
8677 12:44:29.917738 [Byte1]: 71
8678 12:44:29.922096
8679 12:44:29.922724 Set Vref, RX VrefLevel [Byte0]: 72
8680 12:44:29.924927 [Byte1]: 72
8681 12:44:29.929458
8682 12:44:29.929988 Set Vref, RX VrefLevel [Byte0]: 73
8683 12:44:29.932842 [Byte1]: 73
8684 12:44:29.937063
8685 12:44:29.937573 Set Vref, RX VrefLevel [Byte0]: 74
8686 12:44:29.940502 [Byte1]: 74
8687 12:44:29.944680
8688 12:44:29.945314 Final RX Vref Byte 0 = 52 to rank0
8689 12:44:29.947812 Final RX Vref Byte 1 = 62 to rank0
8690 12:44:29.951027 Final RX Vref Byte 0 = 52 to rank1
8691 12:44:29.954500 Final RX Vref Byte 1 = 62 to rank1==
8692 12:44:29.957741 Dram Type= 6, Freq= 0, CH_1, rank 0
8693 12:44:29.964545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8694 12:44:29.965169 ==
8695 12:44:29.965745 DQS Delay:
8696 12:44:29.967488 DQS0 = 0, DQS1 = 0
8697 12:44:29.968148 DQM Delay:
8698 12:44:29.968722 DQM0 = 133, DQM1 = 129
8699 12:44:29.970648 DQ Delay:
8700 12:44:29.974028 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8701 12:44:29.977385 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8702 12:44:29.980551 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8703 12:44:29.984397 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =136
8704 12:44:29.984877
8705 12:44:29.985298
8706 12:44:29.985672
8707 12:44:29.987472 [DramC_TX_OE_Calibration] TA2
8708 12:44:29.991032 Original DQ_B0 (3 6) =30, OEN = 27
8709 12:44:29.993822 Original DQ_B1 (3 6) =30, OEN = 27
8710 12:44:29.996871 24, 0x0, End_B0=24 End_B1=24
8711 12:44:30.000344 25, 0x0, End_B0=25 End_B1=25
8712 12:44:30.000819 26, 0x0, End_B0=26 End_B1=26
8713 12:44:30.004027 27, 0x0, End_B0=27 End_B1=27
8714 12:44:30.006851 28, 0x0, End_B0=28 End_B1=28
8715 12:44:30.010230 29, 0x0, End_B0=29 End_B1=29
8716 12:44:30.010697 30, 0x0, End_B0=30 End_B1=30
8717 12:44:30.013707 31, 0x5151, End_B0=30 End_B1=30
8718 12:44:30.016757 Byte0 end_step=30 best_step=27
8719 12:44:30.019990 Byte1 end_step=30 best_step=27
8720 12:44:30.023864 Byte0 TX OE(2T, 0.5T) = (3, 3)
8721 12:44:30.026786 Byte1 TX OE(2T, 0.5T) = (3, 3)
8722 12:44:30.027375
8723 12:44:30.027773
8724 12:44:30.033451 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a28, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
8725 12:44:30.036457 CH1 RK0: MR19=303, MR18=1A28
8726 12:44:30.043544 CH1_RK0: MR19=0x303, MR18=0x1A28, DQSOSC=389, MR23=63, INC=24, DEC=16
8727 12:44:30.044188
8728 12:44:30.046857 ----->DramcWriteLeveling(PI) begin...
8729 12:44:30.047458 ==
8730 12:44:30.050325 Dram Type= 6, Freq= 0, CH_1, rank 1
8731 12:44:30.053238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 12:44:30.053827 ==
8733 12:44:30.056764 Write leveling (Byte 0): 24 => 24
8734 12:44:30.059792 Write leveling (Byte 1): 30 => 30
8735 12:44:30.062952 DramcWriteLeveling(PI) end<-----
8736 12:44:30.063520
8737 12:44:30.063958 ==
8738 12:44:30.066126 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 12:44:30.072707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 12:44:30.073221 ==
8741 12:44:30.073692 [Gating] SW mode calibration
8742 12:44:30.082654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8743 12:44:30.086370 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8744 12:44:30.089552 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 12:44:30.095781 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 12:44:30.099165 1 4 8 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
8747 12:44:30.102474 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8748 12:44:30.109065 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 12:44:30.112193 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 12:44:30.115672 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 12:44:30.122405 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 12:44:30.125895 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 12:44:30.128945 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 12:44:30.135459 1 5 8 | B1->B0 | 2929 3434 | 0 1 | (1 0) (1 0)
8755 12:44:30.138998 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (0 1)
8756 12:44:30.142515 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 12:44:30.148510 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 12:44:30.152087 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 12:44:30.155499 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 12:44:30.161736 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 12:44:30.165163 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8762 12:44:30.168701 1 6 8 | B1->B0 | 4646 2727 | 0 0 | (0 0) (0 0)
8763 12:44:30.175110 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8764 12:44:30.178149 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 12:44:30.184958 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 12:44:30.188773 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 12:44:30.191518 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 12:44:30.194789 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 12:44:30.201425 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 12:44:30.204954 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8771 12:44:30.207954 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8772 12:44:30.214923 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8773 12:44:30.217583 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 12:44:30.221093 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 12:44:30.227399 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 12:44:30.230695 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 12:44:30.234035 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 12:44:30.240618 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 12:44:30.244209 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 12:44:30.247191 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 12:44:30.253853 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:44:30.257190 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 12:44:30.260459 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:44:30.267075 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:44:30.270657 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:44:30.273638 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8787 12:44:30.280662 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8788 12:44:30.284197 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 12:44:30.287306 Total UI for P1: 0, mck2ui 16
8790 12:44:30.290128 best dqsien dly found for B0: ( 1, 9, 10)
8791 12:44:30.293442 Total UI for P1: 0, mck2ui 16
8792 12:44:30.296921 best dqsien dly found for B1: ( 1, 9, 10)
8793 12:44:30.300103 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8794 12:44:30.303486 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8795 12:44:30.303593
8796 12:44:30.306784 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8797 12:44:30.313573 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8798 12:44:30.313667 [Gating] SW calibration Done
8799 12:44:30.313736 ==
8800 12:44:30.316895 Dram Type= 6, Freq= 0, CH_1, rank 1
8801 12:44:30.323254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 12:44:30.323350 ==
8803 12:44:30.323419 RX Vref Scan: 0
8804 12:44:30.323481
8805 12:44:30.326889 RX Vref 0 -> 0, step: 1
8806 12:44:30.326964
8807 12:44:30.330212 RX Delay 0 -> 252, step: 8
8808 12:44:30.333249 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8809 12:44:30.336727 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8810 12:44:30.340160 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8811 12:44:30.343121 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8812 12:44:30.349852 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8813 12:44:30.352892 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8814 12:44:30.356484 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8815 12:44:30.359554 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8816 12:44:30.362891 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8817 12:44:30.369727 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8818 12:44:30.372842 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8819 12:44:30.376094 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8820 12:44:30.379710 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8821 12:44:30.386084 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8822 12:44:30.389467 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8823 12:44:30.393067 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8824 12:44:30.393152 ==
8825 12:44:30.395847 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 12:44:30.399724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 12:44:30.399811 ==
8828 12:44:30.402435 DQS Delay:
8829 12:44:30.402521 DQS0 = 0, DQS1 = 0
8830 12:44:30.406013 DQM Delay:
8831 12:44:30.406102 DQM0 = 136, DQM1 = 133
8832 12:44:30.409242 DQ Delay:
8833 12:44:30.412491 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8834 12:44:30.416046 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =139
8835 12:44:30.419082 DQ8 =115, DQ9 =123, DQ10 =135, DQ11 =127
8836 12:44:30.422524 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8837 12:44:30.422619
8838 12:44:30.422692
8839 12:44:30.422757 ==
8840 12:44:30.425826 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 12:44:30.428818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 12:44:30.428906 ==
8843 12:44:30.428987
8844 12:44:30.429051
8845 12:44:30.432238 TX Vref Scan disable
8846 12:44:30.436078 == TX Byte 0 ==
8847 12:44:30.439276 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8848 12:44:30.442162 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8849 12:44:30.445573 == TX Byte 1 ==
8850 12:44:30.448946 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8851 12:44:30.452209 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8852 12:44:30.452342 ==
8853 12:44:30.455265 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 12:44:30.461986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 12:44:30.462073 ==
8856 12:44:30.474750
8857 12:44:30.478404 TX Vref early break, caculate TX vref
8858 12:44:30.481415 TX Vref=16, minBit 9, minWin=21, winSum=376
8859 12:44:30.484600 TX Vref=18, minBit 9, minWin=22, winSum=389
8860 12:44:30.488289 TX Vref=20, minBit 9, minWin=22, winSum=392
8861 12:44:30.491400 TX Vref=22, minBit 9, minWin=23, winSum=404
8862 12:44:30.494845 TX Vref=24, minBit 8, minWin=24, winSum=411
8863 12:44:30.501252 TX Vref=26, minBit 8, minWin=24, winSum=417
8864 12:44:30.505234 TX Vref=28, minBit 8, minWin=24, winSum=417
8865 12:44:30.507959 TX Vref=30, minBit 8, minWin=24, winSum=410
8866 12:44:30.511387 TX Vref=32, minBit 8, minWin=24, winSum=403
8867 12:44:30.514512 TX Vref=34, minBit 10, minWin=23, winSum=398
8868 12:44:30.521295 TX Vref=36, minBit 9, minWin=22, winSum=385
8869 12:44:30.524521 [TxChooseVref] Worse bit 8, Min win 24, Win sum 417, Final Vref 26
8870 12:44:30.524603
8871 12:44:30.527694 Final TX Range 0 Vref 26
8872 12:44:30.527776
8873 12:44:30.527841 ==
8874 12:44:30.531238 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 12:44:30.534165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 12:44:30.537567 ==
8877 12:44:30.537650
8878 12:44:30.537715
8879 12:44:30.537775 TX Vref Scan disable
8880 12:44:30.544332 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8881 12:44:30.544414 == TX Byte 0 ==
8882 12:44:30.547804 u2DelayCellOfst[0]=13 cells (4 PI)
8883 12:44:30.551015 u2DelayCellOfst[1]=10 cells (3 PI)
8884 12:44:30.554251 u2DelayCellOfst[2]=0 cells (0 PI)
8885 12:44:30.557425 u2DelayCellOfst[3]=3 cells (1 PI)
8886 12:44:30.561072 u2DelayCellOfst[4]=6 cells (2 PI)
8887 12:44:30.564072 u2DelayCellOfst[5]=16 cells (5 PI)
8888 12:44:30.568004 u2DelayCellOfst[6]=16 cells (5 PI)
8889 12:44:30.571334 u2DelayCellOfst[7]=3 cells (1 PI)
8890 12:44:30.574396 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8891 12:44:30.577748 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8892 12:44:30.580708 == TX Byte 1 ==
8893 12:44:30.584137 u2DelayCellOfst[8]=0 cells (0 PI)
8894 12:44:30.587642 u2DelayCellOfst[9]=3 cells (1 PI)
8895 12:44:30.590737 u2DelayCellOfst[10]=10 cells (3 PI)
8896 12:44:30.594017 u2DelayCellOfst[11]=3 cells (1 PI)
8897 12:44:30.594099 u2DelayCellOfst[12]=13 cells (4 PI)
8898 12:44:30.597548 u2DelayCellOfst[13]=16 cells (5 PI)
8899 12:44:30.600513 u2DelayCellOfst[14]=16 cells (5 PI)
8900 12:44:30.604150 u2DelayCellOfst[15]=16 cells (5 PI)
8901 12:44:30.610406 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8902 12:44:30.614028 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8903 12:44:30.614110 DramC Write-DBI on
8904 12:44:30.617216 ==
8905 12:44:30.620833 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 12:44:30.623582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 12:44:30.623665 ==
8908 12:44:30.623731
8909 12:44:30.623792
8910 12:44:30.627034 TX Vref Scan disable
8911 12:44:30.627116 == TX Byte 0 ==
8912 12:44:30.633745 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8913 12:44:30.633828 == TX Byte 1 ==
8914 12:44:30.636928 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8915 12:44:30.640565 DramC Write-DBI off
8916 12:44:30.640647
8917 12:44:30.640712 [DATLAT]
8918 12:44:30.643775 Freq=1600, CH1 RK1
8919 12:44:30.643859
8920 12:44:30.643924 DATLAT Default: 0xf
8921 12:44:30.647447 0, 0xFFFF, sum = 0
8922 12:44:30.647530 1, 0xFFFF, sum = 0
8923 12:44:30.650268 2, 0xFFFF, sum = 0
8924 12:44:30.650350 3, 0xFFFF, sum = 0
8925 12:44:30.653672 4, 0xFFFF, sum = 0
8926 12:44:30.653756 5, 0xFFFF, sum = 0
8927 12:44:30.656901 6, 0xFFFF, sum = 0
8928 12:44:30.657021 7, 0xFFFF, sum = 0
8929 12:44:30.660152 8, 0xFFFF, sum = 0
8930 12:44:30.663485 9, 0xFFFF, sum = 0
8931 12:44:30.663568 10, 0xFFFF, sum = 0
8932 12:44:30.666716 11, 0xFFFF, sum = 0
8933 12:44:30.666800 12, 0xFFFF, sum = 0
8934 12:44:30.670084 13, 0xFFFF, sum = 0
8935 12:44:30.670168 14, 0x0, sum = 1
8936 12:44:30.673291 15, 0x0, sum = 2
8937 12:44:30.673374 16, 0x0, sum = 3
8938 12:44:30.676835 17, 0x0, sum = 4
8939 12:44:30.676918 best_step = 15
8940 12:44:30.677003
8941 12:44:30.677079 ==
8942 12:44:30.679856 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 12:44:30.683250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 12:44:30.683333 ==
8945 12:44:30.686661 RX Vref Scan: 0
8946 12:44:30.686743
8947 12:44:30.689733 RX Vref 0 -> 0, step: 1
8948 12:44:30.689814
8949 12:44:30.689880 RX Delay 19 -> 252, step: 4
8950 12:44:30.697091 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8951 12:44:30.700261 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
8952 12:44:30.703775 iDelay=195, Bit 2, Center 122 (75 ~ 170) 96
8953 12:44:30.707146 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8954 12:44:30.710168 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8955 12:44:30.716838 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8956 12:44:30.720193 iDelay=195, Bit 6, Center 140 (95 ~ 186) 92
8957 12:44:30.723387 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8958 12:44:30.727523 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8959 12:44:30.730471 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8960 12:44:30.736448 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8961 12:44:30.739953 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8962 12:44:30.743766 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8963 12:44:30.746466 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8964 12:44:30.750032 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8965 12:44:30.756548 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8966 12:44:30.756631 ==
8967 12:44:30.759563 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 12:44:30.763088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 12:44:30.763171 ==
8970 12:44:30.763236 DQS Delay:
8971 12:44:30.766718 DQS0 = 0, DQS1 = 0
8972 12:44:30.766800 DQM Delay:
8973 12:44:30.769482 DQM0 = 133, DQM1 = 130
8974 12:44:30.769564 DQ Delay:
8975 12:44:30.772936 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =130
8976 12:44:30.776038 DQ4 =134, DQ5 =146, DQ6 =140, DQ7 =130
8977 12:44:30.779502 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
8978 12:44:30.786158 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8979 12:44:30.786240
8980 12:44:30.786306
8981 12:44:30.786367
8982 12:44:30.786425 [DramC_TX_OE_Calibration] TA2
8983 12:44:30.789101 Original DQ_B0 (3 6) =30, OEN = 27
8984 12:44:30.793228 Original DQ_B1 (3 6) =30, OEN = 27
8985 12:44:30.796137 24, 0x0, End_B0=24 End_B1=24
8986 12:44:30.799653 25, 0x0, End_B0=25 End_B1=25
8987 12:44:30.802497 26, 0x0, End_B0=26 End_B1=26
8988 12:44:30.802580 27, 0x0, End_B0=27 End_B1=27
8989 12:44:30.805947 28, 0x0, End_B0=28 End_B1=28
8990 12:44:30.809115 29, 0x0, End_B0=29 End_B1=29
8991 12:44:30.812271 30, 0x0, End_B0=30 End_B1=30
8992 12:44:30.815725 31, 0x4545, End_B0=30 End_B1=30
8993 12:44:30.818896 Byte0 end_step=30 best_step=27
8994 12:44:30.818979 Byte1 end_step=30 best_step=27
8995 12:44:30.822406 Byte0 TX OE(2T, 0.5T) = (3, 3)
8996 12:44:30.825679 Byte1 TX OE(2T, 0.5T) = (3, 3)
8997 12:44:30.825762
8998 12:44:30.825827
8999 12:44:30.835743 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9000 12:44:30.835827 CH1 RK1: MR19=303, MR18=1D08
9001 12:44:30.842232 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9002 12:44:30.845465 [RxdqsGatingPostProcess] freq 1600
9003 12:44:30.852670 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9004 12:44:30.855214 best DQS0 dly(2T, 0.5T) = (1, 1)
9005 12:44:30.858819 best DQS1 dly(2T, 0.5T) = (1, 1)
9006 12:44:30.861880 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9007 12:44:30.865765 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9008 12:44:30.868416 best DQS0 dly(2T, 0.5T) = (1, 1)
9009 12:44:30.868499 best DQS1 dly(2T, 0.5T) = (1, 1)
9010 12:44:30.871941 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9011 12:44:30.875137 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9012 12:44:30.878360 Pre-setting of DQS Precalculation
9013 12:44:30.885360 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9014 12:44:30.891642 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9015 12:44:30.898317 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9016 12:44:30.898400
9017 12:44:30.898465
9018 12:44:30.901662 [Calibration Summary] 3200 Mbps
9019 12:44:30.904855 CH 0, Rank 0
9020 12:44:30.904963 SW Impedance : PASS
9021 12:44:30.908255 DUTY Scan : NO K
9022 12:44:30.908337 ZQ Calibration : PASS
9023 12:44:30.911106 Jitter Meter : NO K
9024 12:44:30.914582 CBT Training : PASS
9025 12:44:30.914665 Write leveling : PASS
9026 12:44:30.917764 RX DQS gating : PASS
9027 12:44:30.921202 RX DQ/DQS(RDDQC) : PASS
9028 12:44:30.921284 TX DQ/DQS : PASS
9029 12:44:30.924768 RX DATLAT : PASS
9030 12:44:30.927819 RX DQ/DQS(Engine): PASS
9031 12:44:30.927902 TX OE : PASS
9032 12:44:30.931148 All Pass.
9033 12:44:30.931231
9034 12:44:30.931296 CH 0, Rank 1
9035 12:44:30.934276 SW Impedance : PASS
9036 12:44:30.934358 DUTY Scan : NO K
9037 12:44:30.937941 ZQ Calibration : PASS
9038 12:44:30.941317 Jitter Meter : NO K
9039 12:44:30.941400 CBT Training : PASS
9040 12:44:30.944340 Write leveling : PASS
9041 12:44:30.947477 RX DQS gating : PASS
9042 12:44:30.947560 RX DQ/DQS(RDDQC) : PASS
9043 12:44:30.951015 TX DQ/DQS : PASS
9044 12:44:30.954422 RX DATLAT : PASS
9045 12:44:30.954504 RX DQ/DQS(Engine): PASS
9046 12:44:30.957770 TX OE : PASS
9047 12:44:30.957852 All Pass.
9048 12:44:30.957917
9049 12:44:30.960762 CH 1, Rank 0
9050 12:44:30.960843 SW Impedance : PASS
9051 12:44:30.964410 DUTY Scan : NO K
9052 12:44:30.967402 ZQ Calibration : PASS
9053 12:44:30.967485 Jitter Meter : NO K
9054 12:44:30.970797 CBT Training : PASS
9055 12:44:30.970879 Write leveling : PASS
9056 12:44:30.973963 RX DQS gating : PASS
9057 12:44:30.977561 RX DQ/DQS(RDDQC) : PASS
9058 12:44:30.977644 TX DQ/DQS : PASS
9059 12:44:30.980589 RX DATLAT : PASS
9060 12:44:30.984130 RX DQ/DQS(Engine): PASS
9061 12:44:30.984212 TX OE : PASS
9062 12:44:30.987480 All Pass.
9063 12:44:30.987563
9064 12:44:30.987628 CH 1, Rank 1
9065 12:44:30.990643 SW Impedance : PASS
9066 12:44:30.990726 DUTY Scan : NO K
9067 12:44:30.994663 ZQ Calibration : PASS
9068 12:44:30.997577 Jitter Meter : NO K
9069 12:44:30.997659 CBT Training : PASS
9070 12:44:31.000814 Write leveling : PASS
9071 12:44:31.003892 RX DQS gating : PASS
9072 12:44:31.003974 RX DQ/DQS(RDDQC) : PASS
9073 12:44:31.007484 TX DQ/DQS : PASS
9074 12:44:31.010669 RX DATLAT : PASS
9075 12:44:31.010752 RX DQ/DQS(Engine): PASS
9076 12:44:31.014098 TX OE : PASS
9077 12:44:31.014180 All Pass.
9078 12:44:31.014246
9079 12:44:31.016923 DramC Write-DBI on
9080 12:44:31.020533 PER_BANK_REFRESH: Hybrid Mode
9081 12:44:31.020615 TX_TRACKING: ON
9082 12:44:31.030566 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9083 12:44:31.036940 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9084 12:44:31.043545 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9085 12:44:31.046561 [FAST_K] Save calibration result to emmc
9086 12:44:31.050410 sync common calibartion params.
9087 12:44:31.053347 sync cbt_mode0:1, 1:1
9088 12:44:31.056891 dram_init: ddr_geometry: 2
9089 12:44:31.056973 dram_init: ddr_geometry: 2
9090 12:44:31.059948 dram_init: ddr_geometry: 2
9091 12:44:31.063410 0:dram_rank_size:100000000
9092 12:44:31.066910 1:dram_rank_size:100000000
9093 12:44:31.069997 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9094 12:44:31.073508 DFS_SHUFFLE_HW_MODE: ON
9095 12:44:31.076508 dramc_set_vcore_voltage set vcore to 725000
9096 12:44:31.080159 Read voltage for 1600, 0
9097 12:44:31.080241 Vio18 = 0
9098 12:44:31.080322 Vcore = 725000
9099 12:44:31.083385 Vdram = 0
9100 12:44:31.083467 Vddq = 0
9101 12:44:31.083533 Vmddr = 0
9102 12:44:31.086488 switch to 3200 Mbps bootup
9103 12:44:31.089920 [DramcRunTimeConfig]
9104 12:44:31.090001 PHYPLL
9105 12:44:31.090067 DPM_CONTROL_AFTERK: ON
9106 12:44:31.093437 PER_BANK_REFRESH: ON
9107 12:44:31.096397 REFRESH_OVERHEAD_REDUCTION: ON
9108 12:44:31.096480 CMD_PICG_NEW_MODE: OFF
9109 12:44:31.099871 XRTWTW_NEW_MODE: ON
9110 12:44:31.103273 XRTRTR_NEW_MODE: ON
9111 12:44:31.103355 TX_TRACKING: ON
9112 12:44:31.106246 RDSEL_TRACKING: OFF
9113 12:44:31.106328 DQS Precalculation for DVFS: ON
9114 12:44:31.109596 RX_TRACKING: OFF
9115 12:44:31.109678 HW_GATING DBG: ON
9116 12:44:31.112898 ZQCS_ENABLE_LP4: ON
9117 12:44:31.112984 RX_PICG_NEW_MODE: ON
9118 12:44:31.116487 TX_PICG_NEW_MODE: ON
9119 12:44:31.119489 ENABLE_RX_DCM_DPHY: ON
9120 12:44:31.122955 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9121 12:44:31.123038 DUMMY_READ_FOR_TRACKING: OFF
9122 12:44:31.126169 !!! SPM_CONTROL_AFTERK: OFF
9123 12:44:31.129298 !!! SPM could not control APHY
9124 12:44:31.132527 IMPEDANCE_TRACKING: ON
9125 12:44:31.132609 TEMP_SENSOR: ON
9126 12:44:31.136136 HW_SAVE_FOR_SR: OFF
9127 12:44:31.139191 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9128 12:44:31.142601 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9129 12:44:31.142684 Read ODT Tracking: ON
9130 12:44:31.146096 Refresh Rate DeBounce: ON
9131 12:44:31.149253 DFS_NO_QUEUE_FLUSH: ON
9132 12:44:31.152251 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9133 12:44:31.152333 ENABLE_DFS_RUNTIME_MRW: OFF
9134 12:44:31.155431 DDR_RESERVE_NEW_MODE: ON
9135 12:44:31.159117 MR_CBT_SWITCH_FREQ: ON
9136 12:44:31.159202 =========================
9137 12:44:31.178829 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9138 12:44:31.182451 dram_init: ddr_geometry: 2
9139 12:44:31.200506 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9140 12:44:31.203865 dram_init: dram init end (result: 0)
9141 12:44:31.210598 DRAM-K: Full calibration passed in 24462 msecs
9142 12:44:31.213615 MRC: failed to locate region type 0.
9143 12:44:31.213698 DRAM rank0 size:0x100000000,
9144 12:44:31.217093 DRAM rank1 size=0x100000000
9145 12:44:31.226863 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9146 12:44:31.233815 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9147 12:44:31.240808 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9148 12:44:31.246915 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9149 12:44:31.250118 DRAM rank0 size:0x100000000,
9150 12:44:31.253612 DRAM rank1 size=0x100000000
9151 12:44:31.253694 CBMEM:
9152 12:44:31.256961 IMD: root @ 0xfffff000 254 entries.
9153 12:44:31.260197 IMD: root @ 0xffffec00 62 entries.
9154 12:44:31.263695 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9155 12:44:31.269934 WARNING: RO_VPD is uninitialized or empty.
9156 12:44:31.273263 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9157 12:44:31.280473 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9158 12:44:31.293686 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9159 12:44:31.304824 BS: romstage times (exec / console): total (unknown) / 23967 ms
9160 12:44:31.304911
9161 12:44:31.305009
9162 12:44:31.314745 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9163 12:44:31.318037 ARM64: Exception handlers installed.
9164 12:44:31.321058 ARM64: Testing exception
9165 12:44:31.324335 ARM64: Done test exception
9166 12:44:31.324413 Enumerating buses...
9167 12:44:31.327720 Show all devs... Before device enumeration.
9168 12:44:31.330994 Root Device: enabled 1
9169 12:44:31.334331 CPU_CLUSTER: 0: enabled 1
9170 12:44:31.334412 CPU: 00: enabled 1
9171 12:44:31.337564 Compare with tree...
9172 12:44:31.337637 Root Device: enabled 1
9173 12:44:31.340879 CPU_CLUSTER: 0: enabled 1
9174 12:44:31.344290 CPU: 00: enabled 1
9175 12:44:31.344371 Root Device scanning...
9176 12:44:31.347365 scan_static_bus for Root Device
9177 12:44:31.350688 CPU_CLUSTER: 0 enabled
9178 12:44:31.354124 scan_static_bus for Root Device done
9179 12:44:31.357467 scan_bus: bus Root Device finished in 8 msecs
9180 12:44:31.357569 done
9181 12:44:31.364049 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9182 12:44:31.367421 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9183 12:44:31.374187 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9184 12:44:31.380414 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9185 12:44:31.380499 Allocating resources...
9186 12:44:31.383708 Reading resources...
9187 12:44:31.387170 Root Device read_resources bus 0 link: 0
9188 12:44:31.390384 DRAM rank0 size:0x100000000,
9189 12:44:31.390461 DRAM rank1 size=0x100000000
9190 12:44:31.397134 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9191 12:44:31.397211 CPU: 00 missing read_resources
9192 12:44:31.403584 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9193 12:44:31.406842 Root Device read_resources bus 0 link: 0 done
9194 12:44:31.409959 Done reading resources.
9195 12:44:31.413229 Show resources in subtree (Root Device)...After reading.
9196 12:44:31.416637 Root Device child on link 0 CPU_CLUSTER: 0
9197 12:44:31.420256 CPU_CLUSTER: 0 child on link 0 CPU: 00
9198 12:44:31.430090 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9199 12:44:31.430174 CPU: 00
9200 12:44:31.436751 Root Device assign_resources, bus 0 link: 0
9201 12:44:31.439997 CPU_CLUSTER: 0 missing set_resources
9202 12:44:31.442968 Root Device assign_resources, bus 0 link: 0 done
9203 12:44:31.443046 Done setting resources.
9204 12:44:31.449986 Show resources in subtree (Root Device)...After assigning values.
9205 12:44:31.453025 Root Device child on link 0 CPU_CLUSTER: 0
9206 12:44:31.456312 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 12:44:31.466061 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 12:44:31.466157 CPU: 00
9209 12:44:31.469338 Done allocating resources.
9210 12:44:31.476335 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9211 12:44:31.476426 Enabling resources...
9212 12:44:31.479638 done.
9213 12:44:31.482772 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9214 12:44:31.486500 Initializing devices...
9215 12:44:31.486588 Root Device init
9216 12:44:31.489703 init hardware done!
9217 12:44:31.489793 0x00000018: ctrlr->caps
9218 12:44:31.492698 52.000 MHz: ctrlr->f_max
9219 12:44:31.495879 0.400 MHz: ctrlr->f_min
9220 12:44:31.495966 0x40ff8080: ctrlr->voltages
9221 12:44:31.499484 sclk: 390625
9222 12:44:31.499569 Bus Width = 1
9223 12:44:31.502662 sclk: 390625
9224 12:44:31.502746 Bus Width = 1
9225 12:44:31.506318 Early init status = 3
9226 12:44:31.509304 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9227 12:44:31.512453 in-header: 03 fc 00 00 01 00 00 00
9228 12:44:31.516032 in-data: 00
9229 12:44:31.519287 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9230 12:44:31.524037 in-header: 03 fd 00 00 00 00 00 00
9231 12:44:31.527590 in-data:
9232 12:44:31.530710 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9233 12:44:31.534975 in-header: 03 fc 00 00 01 00 00 00
9234 12:44:31.538124 in-data: 00
9235 12:44:31.541663 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9236 12:44:31.547509 in-header: 03 fd 00 00 00 00 00 00
9237 12:44:31.550722 in-data:
9238 12:44:31.554068 [SSUSB] Setting up USB HOST controller...
9239 12:44:31.557105 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9240 12:44:31.560334 [SSUSB] phy power-on done.
9241 12:44:31.563615 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9242 12:44:31.570393 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9243 12:44:31.574003 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9244 12:44:31.580155 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9245 12:44:31.586635 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9246 12:44:31.593501 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9247 12:44:31.599974 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9248 12:44:31.606536 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9249 12:44:31.609798 SPM: binary array size = 0x9dc
9250 12:44:31.613009 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9251 12:44:31.619418 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9252 12:44:31.625990 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9253 12:44:31.632731 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9254 12:44:31.635749 configure_display: Starting display init
9255 12:44:31.670851 anx7625_power_on_init: Init interface.
9256 12:44:31.673766 anx7625_disable_pd_protocol: Disabled PD feature.
9257 12:44:31.676866 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9258 12:44:31.704717 anx7625_start_dp_work: Secure OCM version=00
9259 12:44:31.707779 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9260 12:44:31.722776 sp_tx_get_edid_block: EDID Block = 1
9261 12:44:31.825293 Extracted contents:
9262 12:44:31.828742 header: 00 ff ff ff ff ff ff 00
9263 12:44:31.832249 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9264 12:44:31.835389 version: 01 04
9265 12:44:31.838669 basic params: 95 1f 11 78 0a
9266 12:44:31.842445 chroma info: 76 90 94 55 54 90 27 21 50 54
9267 12:44:31.845173 established: 00 00 00
9268 12:44:31.852085 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9269 12:44:31.855299 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9270 12:44:31.861926 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9271 12:44:31.868499 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9272 12:44:31.875166 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9273 12:44:31.878923 extensions: 00
9274 12:44:31.879008 checksum: fb
9275 12:44:31.879075
9276 12:44:31.882149 Manufacturer: IVO Model 57d Serial Number 0
9277 12:44:31.885028 Made week 0 of 2020
9278 12:44:31.885112 EDID version: 1.4
9279 12:44:31.888532 Digital display
9280 12:44:31.891615 6 bits per primary color channel
9281 12:44:31.891702 DisplayPort interface
9282 12:44:31.894934 Maximum image size: 31 cm x 17 cm
9283 12:44:31.898123 Gamma: 220%
9284 12:44:31.898207 Check DPMS levels
9285 12:44:31.901305 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9286 12:44:31.907768 First detailed timing is preferred timing
9287 12:44:31.907853 Established timings supported:
9288 12:44:31.911125 Standard timings supported:
9289 12:44:31.914334 Detailed timings
9290 12:44:31.918033 Hex of detail: 383680a07038204018303c0035ae10000019
9291 12:44:31.924296 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9292 12:44:31.927782 0780 0798 07c8 0820 hborder 0
9293 12:44:31.930853 0438 043b 0447 0458 vborder 0
9294 12:44:31.933984 -hsync -vsync
9295 12:44:31.934068 Did detailed timing
9296 12:44:31.940922 Hex of detail: 000000000000000000000000000000000000
9297 12:44:31.944226 Manufacturer-specified data, tag 0
9298 12:44:31.947753 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9299 12:44:31.950886 ASCII string: InfoVision
9300 12:44:31.953826 Hex of detail: 000000fe00523134304e574635205248200a
9301 12:44:31.957422 ASCII string: R140NWF5 RH
9302 12:44:31.957508 Checksum
9303 12:44:31.960441 Checksum: 0xfb (valid)
9304 12:44:31.964201 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9305 12:44:31.967372 DSI data_rate: 832800000 bps
9306 12:44:31.973791 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9307 12:44:31.977315 anx7625_parse_edid: pixelclock(138800).
9308 12:44:31.980484 hactive(1920), hsync(48), hfp(24), hbp(88)
9309 12:44:31.983402 vactive(1080), vsync(12), vfp(3), vbp(17)
9310 12:44:31.986779 anx7625_dsi_config: config dsi.
9311 12:44:31.993873 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9312 12:44:32.007798 anx7625_dsi_config: success to config DSI
9313 12:44:32.010743 anx7625_dp_start: MIPI phy setup OK.
9314 12:44:32.014189 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9315 12:44:32.017304 mtk_ddp_mode_set invalid vrefresh 60
9316 12:44:32.020654 main_disp_path_setup
9317 12:44:32.020735 ovl_layer_smi_id_en
9318 12:44:32.023940 ovl_layer_smi_id_en
9319 12:44:32.024021 ccorr_config
9320 12:44:32.024085 aal_config
9321 12:44:32.027176 gamma_config
9322 12:44:32.027256 postmask_config
9323 12:44:32.030421 dither_config
9324 12:44:32.033823 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9325 12:44:32.040293 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9326 12:44:32.043940 Root Device init finished in 553 msecs
9327 12:44:32.047278 CPU_CLUSTER: 0 init
9328 12:44:32.053877 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9329 12:44:32.060301 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9330 12:44:32.060387 APU_MBOX 0x190000b0 = 0x10001
9331 12:44:32.063386 APU_MBOX 0x190001b0 = 0x10001
9332 12:44:32.067011 APU_MBOX 0x190005b0 = 0x10001
9333 12:44:32.070024 APU_MBOX 0x190006b0 = 0x10001
9334 12:44:32.076599 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9335 12:44:32.086475 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9336 12:44:32.098879 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9337 12:44:32.105373 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9338 12:44:32.116901 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9339 12:44:32.126360 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9340 12:44:32.129758 CPU_CLUSTER: 0 init finished in 81 msecs
9341 12:44:32.132796 Devices initialized
9342 12:44:32.135891 Show all devs... After init.
9343 12:44:32.135977 Root Device: enabled 1
9344 12:44:32.139342 CPU_CLUSTER: 0: enabled 1
9345 12:44:32.142468 CPU: 00: enabled 1
9346 12:44:32.146080 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9347 12:44:32.149162 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9348 12:44:32.152784 ELOG: NV offset 0x57f000 size 0x1000
9349 12:44:32.159537 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9350 12:44:32.165741 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9351 12:44:32.169333 ELOG: Event(17) added with size 13 at 2023-06-14 12:44:27 UTC
9352 12:44:32.175744 out: cmd=0x121: 03 db 21 01 00 00 00 00
9353 12:44:32.179191 in-header: 03 54 00 00 2c 00 00 00
9354 12:44:32.189027 in-data: 0b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9355 12:44:32.195652 ELOG: Event(A1) added with size 10 at 2023-06-14 12:44:27 UTC
9356 12:44:32.202224 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9357 12:44:32.208758 ELOG: Event(A0) added with size 9 at 2023-06-14 12:44:27 UTC
9358 12:44:32.212556 elog_add_boot_reason: Logged dev mode boot
9359 12:44:32.218590 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9360 12:44:32.218706 Finalize devices...
9361 12:44:32.221812 Devices finalized
9362 12:44:32.225318 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9363 12:44:32.228485 Writing coreboot table at 0xffe64000
9364 12:44:32.232143 0. 000000000010a000-0000000000113fff: RAMSTAGE
9365 12:44:32.238435 1. 0000000040000000-00000000400fffff: RAM
9366 12:44:32.242093 2. 0000000040100000-000000004032afff: RAMSTAGE
9367 12:44:32.245154 3. 000000004032b000-00000000545fffff: RAM
9368 12:44:32.248988 4. 0000000054600000-000000005465ffff: BL31
9369 12:44:32.251735 5. 0000000054660000-00000000ffe63fff: RAM
9370 12:44:32.258609 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9371 12:44:32.261797 7. 0000000100000000-000000023fffffff: RAM
9372 12:44:32.265226 Passing 5 GPIOs to payload:
9373 12:44:32.268168 NAME | PORT | POLARITY | VALUE
9374 12:44:32.274759 EC in RW | 0x000000aa | low | undefined
9375 12:44:32.278224 EC interrupt | 0x00000005 | low | undefined
9376 12:44:32.281553 TPM interrupt | 0x000000ab | high | undefined
9377 12:44:32.288124 SD card detect | 0x00000011 | high | undefined
9378 12:44:32.291259 speaker enable | 0x00000093 | high | undefined
9379 12:44:32.294826 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9380 12:44:32.297827 in-header: 03 f9 00 00 02 00 00 00
9381 12:44:32.301597 in-data: 02 00
9382 12:44:32.304591 ADC[4]: Raw value=901032 ID=7
9383 12:44:32.304676 ADC[3]: Raw value=213179 ID=1
9384 12:44:32.308105 RAM Code: 0x71
9385 12:44:32.311177 ADC[6]: Raw value=74502 ID=0
9386 12:44:32.311268 ADC[5]: Raw value=212072 ID=1
9387 12:44:32.314580 SKU Code: 0x1
9388 12:44:32.321204 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9389 12:44:32.321314 coreboot table: 964 bytes.
9390 12:44:32.324452 IMD ROOT 0. 0xfffff000 0x00001000
9391 12:44:32.327636 IMD SMALL 1. 0xffffe000 0x00001000
9392 12:44:32.331174 RO MCACHE 2. 0xffffc000 0x00001104
9393 12:44:32.334165 CONSOLE 3. 0xfff7c000 0x00080000
9394 12:44:32.337625 FMAP 4. 0xfff7b000 0x00000452
9395 12:44:32.340863 TIME STAMP 5. 0xfff7a000 0x00000910
9396 12:44:32.344433 VBOOT WORK 6. 0xfff66000 0x00014000
9397 12:44:32.347515 RAMOOPS 7. 0xffe66000 0x00100000
9398 12:44:32.350640 COREBOOT 8. 0xffe64000 0x00002000
9399 12:44:32.354131 IMD small region:
9400 12:44:32.357631 IMD ROOT 0. 0xffffec00 0x00000400
9401 12:44:32.360839 VPD 1. 0xffffeba0 0x0000004c
9402 12:44:32.364049 MMC STATUS 2. 0xffffeb80 0x00000004
9403 12:44:32.367598 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9404 12:44:32.370935 Probing TPM: done!
9405 12:44:32.374207 Connected to device vid:did:rid of 1ae0:0028:00
9406 12:44:32.385105 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9407 12:44:32.388808 Initialized TPM device CR50 revision 0
9408 12:44:32.392431 Checking cr50 for pending updates
9409 12:44:32.396115 Reading cr50 TPM mode
9410 12:44:32.404140 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9411 12:44:32.410902 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9412 12:44:32.451023 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9413 12:44:32.454679 Checking segment from ROM address 0x40100000
9414 12:44:32.458114 Checking segment from ROM address 0x4010001c
9415 12:44:32.464415 Loading segment from ROM address 0x40100000
9416 12:44:32.464500 code (compression=0)
9417 12:44:32.474527 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9418 12:44:32.480959 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9419 12:44:32.481092 it's not compressed!
9420 12:44:32.487661 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9421 12:44:32.494270 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9422 12:44:32.511757 Loading segment from ROM address 0x4010001c
9423 12:44:32.511853 Entry Point 0x80000000
9424 12:44:32.514845 Loaded segments
9425 12:44:32.518402 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9426 12:44:32.524818 Jumping to boot code at 0x80000000(0xffe64000)
9427 12:44:32.531472 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9428 12:44:32.537908 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9429 12:44:32.546069 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9430 12:44:32.549343 Checking segment from ROM address 0x40100000
9431 12:44:32.552664 Checking segment from ROM address 0x4010001c
9432 12:44:32.559535 Loading segment from ROM address 0x40100000
9433 12:44:32.559625 code (compression=1)
9434 12:44:32.565803 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9435 12:44:32.576041 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9436 12:44:32.576159 using LZMA
9437 12:44:32.584271 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9438 12:44:32.591155 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9439 12:44:32.594199 Loading segment from ROM address 0x4010001c
9440 12:44:32.594284 Entry Point 0x54601000
9441 12:44:32.597630 Loaded segments
9442 12:44:32.601056 NOTICE: MT8192 bl31_setup
9443 12:44:32.608039 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9444 12:44:32.611258 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9445 12:44:32.615111 WARNING: region 0:
9446 12:44:32.618222 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 12:44:32.618309 WARNING: region 1:
9448 12:44:32.625343 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9449 12:44:32.628263 WARNING: region 2:
9450 12:44:32.631577 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9451 12:44:32.634697 WARNING: region 3:
9452 12:44:32.638152 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9453 12:44:32.641136 WARNING: region 4:
9454 12:44:32.647980 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9455 12:44:32.648088 WARNING: region 5:
9456 12:44:32.651432 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 12:44:32.654583 WARNING: region 6:
9458 12:44:32.657791 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 12:44:32.661225 WARNING: region 7:
9460 12:44:32.664606 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 12:44:32.671204 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9462 12:44:32.674759 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9463 12:44:32.678263 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9464 12:44:32.684769 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9465 12:44:32.687810 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9466 12:44:32.691220 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9467 12:44:32.697815 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9468 12:44:32.701288 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9469 12:44:32.707662 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9470 12:44:32.710899 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9471 12:44:32.714366 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9472 12:44:32.721149 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9473 12:44:32.724201 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9474 12:44:32.727773 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9475 12:44:32.734223 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9476 12:44:32.737650 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9477 12:44:32.744094 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9478 12:44:32.747394 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9479 12:44:32.750950 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9480 12:44:32.757588 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9481 12:44:32.760745 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9482 12:44:32.764397 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9483 12:44:32.770665 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9484 12:44:32.774023 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9485 12:44:32.780603 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9486 12:44:32.784146 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9487 12:44:32.790672 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9488 12:44:32.794122 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9489 12:44:32.797890 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9490 12:44:32.804351 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9491 12:44:32.807460 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9492 12:44:32.810640 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9493 12:44:32.817518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9494 12:44:32.820838 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9495 12:44:32.823951 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9496 12:44:32.827410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9497 12:44:32.834298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9498 12:44:32.837525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9499 12:44:32.840719 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9500 12:44:32.843961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9501 12:44:32.850856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9502 12:44:32.854027 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9503 12:44:32.857192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9504 12:44:32.860540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9505 12:44:32.867418 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9506 12:44:32.870382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9507 12:44:32.873977 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9508 12:44:32.881138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9509 12:44:32.883924 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9510 12:44:32.887158 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9511 12:44:32.894303 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9512 12:44:32.897417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9513 12:44:32.903549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9514 12:44:32.907018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9515 12:44:32.914098 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9516 12:44:32.917365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9517 12:44:32.920315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9518 12:44:32.927039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9519 12:44:32.930298 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9520 12:44:32.936959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9521 12:44:32.940741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9522 12:44:32.947113 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9523 12:44:32.950188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9524 12:44:32.957240 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9525 12:44:32.960452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9526 12:44:32.963581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9527 12:44:32.970214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9528 12:44:32.973515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9529 12:44:32.980386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9530 12:44:32.983671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9531 12:44:32.986898 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9532 12:44:32.993539 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9533 12:44:32.996837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9534 12:44:33.003481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9535 12:44:33.006827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9536 12:44:33.013630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9537 12:44:33.016773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9538 12:44:33.023668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9539 12:44:33.026819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9540 12:44:33.029962 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9541 12:44:33.036793 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9542 12:44:33.040240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9543 12:44:33.046545 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9544 12:44:33.050214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9545 12:44:33.056651 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9546 12:44:33.060256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9547 12:44:33.063606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9548 12:44:33.070017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9549 12:44:33.073347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9550 12:44:33.080544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9551 12:44:33.083086 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9552 12:44:33.089890 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9553 12:44:33.093378 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9554 12:44:33.099685 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9555 12:44:33.103196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9556 12:44:33.106760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9557 12:44:33.113398 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9558 12:44:33.116814 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9559 12:44:33.119933 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9560 12:44:33.123339 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9561 12:44:33.129776 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9562 12:44:33.133364 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9563 12:44:33.140163 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9564 12:44:33.143385 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9565 12:44:33.146319 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9566 12:44:33.153069 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9567 12:44:33.156346 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9568 12:44:33.162844 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9569 12:44:33.166614 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9570 12:44:33.169493 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9571 12:44:33.176215 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9572 12:44:33.179538 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9573 12:44:33.186186 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9574 12:44:33.189773 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9575 12:44:33.192730 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9576 12:44:33.199491 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9577 12:44:33.202810 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9578 12:44:33.206469 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9579 12:44:33.212931 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9580 12:44:33.216000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9581 12:44:33.219510 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9582 12:44:33.222525 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9583 12:44:33.229462 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9584 12:44:33.232747 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9585 12:44:33.236069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9586 12:44:33.242851 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9587 12:44:33.246060 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9588 12:44:33.249253 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9589 12:44:33.255644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9590 12:44:33.259188 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9591 12:44:33.265759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9592 12:44:33.269171 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9593 12:44:33.272296 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9594 12:44:33.279112 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9595 12:44:33.282554 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9596 12:44:33.288996 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9597 12:44:33.292471 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9598 12:44:33.295543 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9599 12:44:33.302252 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9600 12:44:33.305680 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9601 12:44:33.312331 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9602 12:44:33.315373 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9603 12:44:33.319127 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9604 12:44:33.325557 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9605 12:44:33.328873 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9606 12:44:33.331986 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9607 12:44:33.338570 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9608 12:44:33.342084 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9609 12:44:33.348644 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9610 12:44:33.352043 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9611 12:44:33.358822 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9612 12:44:33.362040 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9613 12:44:33.365703 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9614 12:44:33.371973 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9615 12:44:33.375339 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9616 12:44:33.378671 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9617 12:44:33.385504 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9618 12:44:33.388582 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9619 12:44:33.391897 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9620 12:44:33.398902 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9621 12:44:33.401936 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9622 12:44:33.408482 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9623 12:44:33.411611 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9624 12:44:33.418416 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9625 12:44:33.421722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9626 12:44:33.425112 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9627 12:44:33.431839 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9628 12:44:33.434903 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9629 12:44:33.438274 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9630 12:44:33.444994 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9631 12:44:33.448177 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9632 12:44:33.455037 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9633 12:44:33.458147 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9634 12:44:33.461498 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9635 12:44:33.468103 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9636 12:44:33.471197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9637 12:44:33.478049 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9638 12:44:33.481537 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9639 12:44:33.484800 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9640 12:44:33.491109 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9641 12:44:33.494573 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9642 12:44:33.501330 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9643 12:44:33.504488 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9644 12:44:33.507870 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9645 12:44:33.514243 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9646 12:44:33.517816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9647 12:44:33.524178 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9648 12:44:33.527609 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9649 12:44:33.530717 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9650 12:44:33.537366 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9651 12:44:33.540790 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9652 12:44:33.547686 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9653 12:44:33.550772 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9654 12:44:33.557363 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9655 12:44:33.560730 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9656 12:44:33.564563 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9657 12:44:33.570911 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9658 12:44:33.574035 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9659 12:44:33.580485 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9660 12:44:33.584010 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9661 12:44:33.587210 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9662 12:44:33.593600 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9663 12:44:33.597200 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9664 12:44:33.603744 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9665 12:44:33.607248 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9666 12:44:33.613919 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9667 12:44:33.617187 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9668 12:44:33.620258 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9669 12:44:33.627015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9670 12:44:33.630285 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9671 12:44:33.637174 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9672 12:44:33.640317 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9673 12:44:33.646962 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9674 12:44:33.650137 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9675 12:44:33.653627 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9676 12:44:33.659948 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9677 12:44:33.663243 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9678 12:44:33.669808 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9679 12:44:33.673282 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9680 12:44:33.679569 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9681 12:44:33.683435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9682 12:44:33.686560 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9683 12:44:33.692964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9684 12:44:33.696237 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9685 12:44:33.703036 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9686 12:44:33.706447 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9687 12:44:33.712986 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9688 12:44:33.716115 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9689 12:44:33.719488 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9690 12:44:33.726398 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9691 12:44:33.729392 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9692 12:44:33.732464 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9693 12:44:33.736272 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9694 12:44:33.739419 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9695 12:44:33.745902 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9696 12:44:33.749272 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9697 12:44:33.756155 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9698 12:44:33.759170 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9699 12:44:33.762272 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9700 12:44:33.768869 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9701 12:44:33.772383 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9702 12:44:33.778816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9703 12:44:33.782392 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9704 12:44:33.785799 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9705 12:44:33.792521 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9706 12:44:33.795380 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9707 12:44:33.798822 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9708 12:44:33.805478 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9709 12:44:33.808513 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9710 12:44:33.811978 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9711 12:44:33.818754 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9712 12:44:33.821897 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9713 12:44:33.828378 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9714 12:44:33.832019 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9715 12:44:33.835262 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9716 12:44:33.841986 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9717 12:44:33.845267 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9718 12:44:33.848759 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9719 12:44:33.855120 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9720 12:44:33.858657 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9721 12:44:33.861978 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9722 12:44:33.868113 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9723 12:44:33.871639 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9724 12:44:33.878087 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9725 12:44:33.881904 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9726 12:44:33.884765 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9727 12:44:33.891776 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9728 12:44:33.894672 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9729 12:44:33.898342 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9730 12:44:33.904899 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9731 12:44:33.908074 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9732 12:44:33.911512 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9733 12:44:33.914649 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9734 12:44:33.917795 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9735 12:44:33.924539 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9736 12:44:33.928012 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9737 12:44:33.930845 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9738 12:44:33.937849 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9739 12:44:33.940854 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9740 12:44:33.944104 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9741 12:44:33.947746 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9742 12:44:33.954589 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9743 12:44:33.957299 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9744 12:44:33.964034 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9745 12:44:33.967659 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9746 12:44:33.970781 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9747 12:44:33.977534 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9748 12:44:33.980771 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9749 12:44:33.987716 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9750 12:44:33.990779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9751 12:44:33.993880 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9752 12:44:34.000370 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9753 12:44:34.003881 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9754 12:44:34.010373 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9755 12:44:34.013649 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9756 12:44:34.020310 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9757 12:44:34.023657 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9758 12:44:34.027526 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9759 12:44:34.033748 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9760 12:44:34.036938 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9761 12:44:34.043623 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9762 12:44:34.046943 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9763 12:44:34.050741 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9764 12:44:34.056919 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9765 12:44:34.059970 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9766 12:44:34.066779 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9767 12:44:34.069973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9768 12:44:34.073284 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9769 12:44:34.079935 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9770 12:44:34.083377 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9771 12:44:34.089816 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9772 12:44:34.092856 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9773 12:44:34.099433 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9774 12:44:34.103134 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9775 12:44:34.106141 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9776 12:44:34.112982 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9777 12:44:34.116358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9778 12:44:34.123350 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9779 12:44:34.126138 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9780 12:44:34.132997 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9781 12:44:34.136444 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9782 12:44:34.139370 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9783 12:44:34.146222 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9784 12:44:34.148985 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9785 12:44:34.155653 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9786 12:44:34.159162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9787 12:44:34.162257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9788 12:44:34.169118 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9789 12:44:34.172273 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9790 12:44:34.178938 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9791 12:44:34.182113 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9792 12:44:34.185595 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9793 12:44:34.192395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9794 12:44:34.195622 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9795 12:44:34.202366 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9796 12:44:34.205312 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9797 12:44:34.211863 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9798 12:44:34.215457 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9799 12:44:34.218803 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9800 12:44:34.225013 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9801 12:44:34.228712 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9802 12:44:34.235015 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9803 12:44:34.238155 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9804 12:44:34.244995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9805 12:44:34.248142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9806 12:44:34.251732 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9807 12:44:34.258346 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9808 12:44:34.261271 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9809 12:44:34.268626 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9810 12:44:34.271688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9811 12:44:34.274890 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9812 12:44:34.281353 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9813 12:44:34.284705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9814 12:44:34.291119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9815 12:44:34.294869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9816 12:44:34.297592 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9817 12:44:34.304925 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9818 12:44:34.307718 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9819 12:44:34.314255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9820 12:44:34.317919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9821 12:44:34.324148 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9822 12:44:34.327644 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9823 12:44:34.334230 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9824 12:44:34.337590 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9825 12:44:34.340747 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9826 12:44:34.347487 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9827 12:44:34.350600 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9828 12:44:34.357127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9829 12:44:34.360546 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9830 12:44:34.367501 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9831 12:44:34.370811 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9832 12:44:34.374080 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9833 12:44:34.380749 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9834 12:44:34.383651 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9835 12:44:34.390274 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9836 12:44:34.393674 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9837 12:44:34.400612 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9838 12:44:34.403637 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9839 12:44:34.410105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9840 12:44:34.413774 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9841 12:44:34.416624 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9842 12:44:34.423473 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9843 12:44:34.426988 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9844 12:44:34.433588 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9845 12:44:34.436596 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9846 12:44:34.443170 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9847 12:44:34.446643 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9848 12:44:34.453019 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9849 12:44:34.456400 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9850 12:44:34.462821 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9851 12:44:34.466130 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9852 12:44:34.469625 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9853 12:44:34.476171 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9854 12:44:34.479356 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9855 12:44:34.485944 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9856 12:44:34.489415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9857 12:44:34.496057 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9858 12:44:34.499192 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9859 12:44:34.505746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9860 12:44:34.508874 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9861 12:44:34.512550 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9862 12:44:34.519078 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9863 12:44:34.522182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9864 12:44:34.529112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9865 12:44:34.532420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9866 12:44:34.538964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9867 12:44:34.542120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9868 12:44:34.545562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9869 12:44:34.552262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9870 12:44:34.555523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9871 12:44:34.562321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9872 12:44:34.565594 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9873 12:44:34.571855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9874 12:44:34.575253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9875 12:44:34.582063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9876 12:44:34.585237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9877 12:44:34.591752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9878 12:44:34.595246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9879 12:44:34.601666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9880 12:44:34.605151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9881 12:44:34.611683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9882 12:44:34.614942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9883 12:44:34.621678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9884 12:44:34.625140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9885 12:44:34.631590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9886 12:44:34.634707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9887 12:44:34.641546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9888 12:44:34.644434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9889 12:44:34.651337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9890 12:44:34.654445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9891 12:44:34.661141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9892 12:44:34.664761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9893 12:44:34.671053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9894 12:44:34.674355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9895 12:44:34.680880 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9896 12:44:34.681009 INFO: [APUAPC] vio 0
9897 12:44:34.688001 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9898 12:44:34.691363 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9899 12:44:34.694510 INFO: [APUAPC] D0_APC_0: 0x400510
9900 12:44:34.697992 INFO: [APUAPC] D0_APC_1: 0x0
9901 12:44:34.701423 INFO: [APUAPC] D0_APC_2: 0x1540
9902 12:44:34.704708 INFO: [APUAPC] D0_APC_3: 0x0
9903 12:44:34.708051 INFO: [APUAPC] D1_APC_0: 0xffffffff
9904 12:44:34.710934 INFO: [APUAPC] D1_APC_1: 0xffffffff
9905 12:44:34.714780 INFO: [APUAPC] D1_APC_2: 0x3fffff
9906 12:44:34.717839 INFO: [APUAPC] D1_APC_3: 0x0
9907 12:44:34.721319 INFO: [APUAPC] D2_APC_0: 0xffffffff
9908 12:44:34.724363 INFO: [APUAPC] D2_APC_1: 0xffffffff
9909 12:44:34.727558 INFO: [APUAPC] D2_APC_2: 0x3fffff
9910 12:44:34.730889 INFO: [APUAPC] D2_APC_3: 0x0
9911 12:44:34.734444 INFO: [APUAPC] D3_APC_0: 0xffffffff
9912 12:44:34.737773 INFO: [APUAPC] D3_APC_1: 0xffffffff
9913 12:44:34.740738 INFO: [APUAPC] D3_APC_2: 0x3fffff
9914 12:44:34.743930 INFO: [APUAPC] D3_APC_3: 0x0
9915 12:44:34.747527 INFO: [APUAPC] D4_APC_0: 0xffffffff
9916 12:44:34.750611 INFO: [APUAPC] D4_APC_1: 0xffffffff
9917 12:44:34.754120 INFO: [APUAPC] D4_APC_2: 0x3fffff
9918 12:44:34.757564 INFO: [APUAPC] D4_APC_3: 0x0
9919 12:44:34.760732 INFO: [APUAPC] D5_APC_0: 0xffffffff
9920 12:44:34.763753 INFO: [APUAPC] D5_APC_1: 0xffffffff
9921 12:44:34.767170 INFO: [APUAPC] D5_APC_2: 0x3fffff
9922 12:44:34.767253 INFO: [APUAPC] D5_APC_3: 0x0
9923 12:44:34.773742 INFO: [APUAPC] D6_APC_0: 0xffffffff
9924 12:44:34.777305 INFO: [APUAPC] D6_APC_1: 0xffffffff
9925 12:44:34.780520 INFO: [APUAPC] D6_APC_2: 0x3fffff
9926 12:44:34.780603 INFO: [APUAPC] D6_APC_3: 0x0
9927 12:44:34.783474 INFO: [APUAPC] D7_APC_0: 0xffffffff
9928 12:44:34.790271 INFO: [APUAPC] D7_APC_1: 0xffffffff
9929 12:44:34.793515 INFO: [APUAPC] D7_APC_2: 0x3fffff
9930 12:44:34.793598 INFO: [APUAPC] D7_APC_3: 0x0
9931 12:44:34.796876 INFO: [APUAPC] D8_APC_0: 0xffffffff
9932 12:44:34.800333 INFO: [APUAPC] D8_APC_1: 0xffffffff
9933 12:44:34.803688 INFO: [APUAPC] D8_APC_2: 0x3fffff
9934 12:44:34.806658 INFO: [APUAPC] D8_APC_3: 0x0
9935 12:44:34.809935 INFO: [APUAPC] D9_APC_0: 0xffffffff
9936 12:44:34.813398 INFO: [APUAPC] D9_APC_1: 0xffffffff
9937 12:44:34.817216 INFO: [APUAPC] D9_APC_2: 0x3fffff
9938 12:44:34.819836 INFO: [APUAPC] D9_APC_3: 0x0
9939 12:44:34.823588 INFO: [APUAPC] D10_APC_0: 0xffffffff
9940 12:44:34.826671 INFO: [APUAPC] D10_APC_1: 0xffffffff
9941 12:44:34.829909 INFO: [APUAPC] D10_APC_2: 0x3fffff
9942 12:44:34.833243 INFO: [APUAPC] D10_APC_3: 0x0
9943 12:44:34.836720 INFO: [APUAPC] D11_APC_0: 0xffffffff
9944 12:44:34.839630 INFO: [APUAPC] D11_APC_1: 0xffffffff
9945 12:44:34.843280 INFO: [APUAPC] D11_APC_2: 0x3fffff
9946 12:44:34.846162 INFO: [APUAPC] D11_APC_3: 0x0
9947 12:44:34.849553 INFO: [APUAPC] D12_APC_0: 0xffffffff
9948 12:44:34.852889 INFO: [APUAPC] D12_APC_1: 0xffffffff
9949 12:44:34.859712 INFO: [APUAPC] D12_APC_2: 0x3fffff
9950 12:44:34.859795 INFO: [APUAPC] D12_APC_3: 0x0
9951 12:44:34.862869 INFO: [APUAPC] D13_APC_0: 0xffffffff
9952 12:44:34.869392 INFO: [APUAPC] D13_APC_1: 0xffffffff
9953 12:44:34.872986 INFO: [APUAPC] D13_APC_2: 0x3fffff
9954 12:44:34.873069 INFO: [APUAPC] D13_APC_3: 0x0
9955 12:44:34.879412 INFO: [APUAPC] D14_APC_0: 0xffffffff
9956 12:44:34.882874 INFO: [APUAPC] D14_APC_1: 0xffffffff
9957 12:44:34.885789 INFO: [APUAPC] D14_APC_2: 0x3fffff
9958 12:44:34.885872 INFO: [APUAPC] D14_APC_3: 0x0
9959 12:44:34.892529 INFO: [APUAPC] D15_APC_0: 0xffffffff
9960 12:44:34.895941 INFO: [APUAPC] D15_APC_1: 0xffffffff
9961 12:44:34.899496 INFO: [APUAPC] D15_APC_2: 0x3fffff
9962 12:44:34.902470 INFO: [APUAPC] D15_APC_3: 0x0
9963 12:44:34.902557 INFO: [APUAPC] APC_CON: 0x4
9964 12:44:34.905717 INFO: [NOCDAPC] D0_APC_0: 0x0
9965 12:44:34.909176 INFO: [NOCDAPC] D0_APC_1: 0x0
9966 12:44:34.912373 INFO: [NOCDAPC] D1_APC_0: 0x0
9967 12:44:34.915690 INFO: [NOCDAPC] D1_APC_1: 0xfff
9968 12:44:34.919174 INFO: [NOCDAPC] D2_APC_0: 0x0
9969 12:44:34.922397 INFO: [NOCDAPC] D2_APC_1: 0xfff
9970 12:44:34.925549 INFO: [NOCDAPC] D3_APC_0: 0x0
9971 12:44:34.929209 INFO: [NOCDAPC] D3_APC_1: 0xfff
9972 12:44:34.932542 INFO: [NOCDAPC] D4_APC_0: 0x0
9973 12:44:34.932624 INFO: [NOCDAPC] D4_APC_1: 0xfff
9974 12:44:34.935313 INFO: [NOCDAPC] D5_APC_0: 0x0
9975 12:44:34.938759 INFO: [NOCDAPC] D5_APC_1: 0xfff
9976 12:44:34.941997 INFO: [NOCDAPC] D6_APC_0: 0x0
9977 12:44:34.945573 INFO: [NOCDAPC] D6_APC_1: 0xfff
9978 12:44:34.948488 INFO: [NOCDAPC] D7_APC_0: 0x0
9979 12:44:34.952057 INFO: [NOCDAPC] D7_APC_1: 0xfff
9980 12:44:34.955381 INFO: [NOCDAPC] D8_APC_0: 0x0
9981 12:44:34.958580 INFO: [NOCDAPC] D8_APC_1: 0xfff
9982 12:44:34.962033 INFO: [NOCDAPC] D9_APC_0: 0x0
9983 12:44:34.965394 INFO: [NOCDAPC] D9_APC_1: 0xfff
9984 12:44:34.968709 INFO: [NOCDAPC] D10_APC_0: 0x0
9985 12:44:34.968792 INFO: [NOCDAPC] D10_APC_1: 0xfff
9986 12:44:34.971919 INFO: [NOCDAPC] D11_APC_0: 0x0
9987 12:44:34.975507 INFO: [NOCDAPC] D11_APC_1: 0xfff
9988 12:44:34.978737 INFO: [NOCDAPC] D12_APC_0: 0x0
9989 12:44:34.982089 INFO: [NOCDAPC] D12_APC_1: 0xfff
9990 12:44:34.984940 INFO: [NOCDAPC] D13_APC_0: 0x0
9991 12:44:34.988453 INFO: [NOCDAPC] D13_APC_1: 0xfff
9992 12:44:34.991470 INFO: [NOCDAPC] D14_APC_0: 0x0
9993 12:44:34.995167 INFO: [NOCDAPC] D14_APC_1: 0xfff
9994 12:44:34.998258 INFO: [NOCDAPC] D15_APC_0: 0x0
9995 12:44:35.001748 INFO: [NOCDAPC] D15_APC_1: 0xfff
9996 12:44:35.004877 INFO: [NOCDAPC] APC_CON: 0x4
9997 12:44:35.008207 INFO: [APUAPC] set_apusys_apc done
9998 12:44:35.011456 INFO: [DEVAPC] devapc_init done
9999 12:44:35.015048 INFO: GICv3 without legacy support detected.
10000 12:44:35.018037 INFO: ARM GICv3 driver initialized in EL3
10001 12:44:35.021430 INFO: Maximum SPI INTID supported: 639
10002 12:44:35.024618 INFO: BL31: Initializing runtime services
10003 12:44:35.031434 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10004 12:44:35.034674 INFO: SPM: enable CPC mode
10005 12:44:35.041214 INFO: mcdi ready for mcusys-off-idle and system suspend
10006 12:44:35.044665 INFO: BL31: Preparing for EL3 exit to normal world
10007 12:44:35.047691 INFO: Entry point address = 0x80000000
10008 12:44:35.051393 INFO: SPSR = 0x8
10009 12:44:35.055813
10010 12:44:35.055905
10011 12:44:35.055974
10012 12:44:35.059415 Starting depthcharge on Spherion...
10013 12:44:35.059500
10014 12:44:35.059567 Wipe memory regions:
10015 12:44:35.059631
10016 12:44:35.060237 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10017 12:44:35.060339 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10018 12:44:35.060425 Setting prompt string to ['asurada:']
10019 12:44:35.060514 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10020 12:44:35.062612 [0x00000040000000, 0x00000054600000)
10021 12:44:35.185276
10022 12:44:35.185411 [0x00000054660000, 0x00000080000000)
10023 12:44:35.445867
10024 12:44:35.446051 [0x000000821a7280, 0x000000ffe64000)
10025 12:44:36.190595
10026 12:44:36.190751 [0x00000100000000, 0x00000240000000)
10027 12:44:38.080880
10028 12:44:38.084454 Initializing XHCI USB controller at 0x11200000.
10029 12:44:39.121946
10030 12:44:39.125031 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10031 12:44:39.125127
10032 12:44:39.125195
10033 12:44:39.125258
10034 12:44:39.125539 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10036 12:44:39.225898 asurada: tftpboot 192.168.201.1 10724891/tftp-deploy-y3xahij0/kernel/image.itb 10724891/tftp-deploy-y3xahij0/kernel/cmdline
10037 12:44:39.226027 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10038 12:44:39.226114 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10039 12:44:39.229777 tftpboot 192.168.201.1 10724891/tftp-deploy-y3xahij0/kernel/image.itp-deploy-y3xahij0/kernel/cmdline
10040 12:44:39.229865
10041 12:44:39.229933 Waiting for link
10042 12:44:39.390626
10043 12:44:39.390774 R8152: Initializing
10044 12:44:39.390845
10045 12:44:39.393814 Version 9 (ocp_data = 6010)
10046 12:44:39.393899
10047 12:44:39.397046 R8152: Done initializing
10048 12:44:39.397131
10049 12:44:39.397198 Adding net device
10050 12:44:41.269715
10051 12:44:41.269867 done.
10052 12:44:41.269939
10053 12:44:41.270002 MAC: 00:e0:4c:72:2d:d6
10054 12:44:41.270064
10055 12:44:41.273150 Sending DHCP discover... done.
10056 12:44:41.273236
10057 12:44:48.621940 Waiting for reply... done.
10058 12:44:48.622452
10059 12:44:48.622837 Sending DHCP request... done.
10060 12:44:48.625529
10061 12:44:48.626012 Waiting for reply... done.
10062 12:44:48.626369
10063 12:44:48.628870 My ip is 192.168.201.21
10064 12:44:48.629360
10065 12:44:48.632106 The DHCP server ip is 192.168.201.1
10066 12:44:48.632535
10067 12:44:48.635296 TFTP server IP predefined by user: 192.168.201.1
10068 12:44:48.635727
10069 12:44:48.641947 Bootfile predefined by user: 10724891/tftp-deploy-y3xahij0/kernel/image.itb
10070 12:44:48.642421
10071 12:44:48.645381 Sending tftp read request... done.
10072 12:44:48.645854
10073 12:44:48.648555 Waiting for the transfer...
10074 12:44:48.649060
10075 12:44:48.928889 00000000 ################################################################
10076 12:44:48.929059
10077 12:44:49.187469 00080000 ################################################################
10078 12:44:49.187603
10079 12:44:49.438263 00100000 ################################################################
10080 12:44:49.438400
10081 12:44:49.699361 00180000 ################################################################
10082 12:44:49.699497
10083 12:44:49.953241 00200000 ################################################################
10084 12:44:49.953394
10085 12:44:50.211164 00280000 ################################################################
10086 12:44:50.211299
10087 12:44:50.482363 00300000 ################################################################
10088 12:44:50.482495
10089 12:44:50.744885 00380000 ################################################################
10090 12:44:50.745054
10091 12:44:51.016497 00400000 ################################################################
10092 12:44:51.016629
10093 12:44:51.279479 00480000 ################################################################
10094 12:44:51.279617
10095 12:44:51.527934 00500000 ################################################################
10096 12:44:51.528066
10097 12:44:51.793254 00580000 ################################################################
10098 12:44:51.793396
10099 12:44:52.044237 00600000 ################################################################
10100 12:44:52.044367
10101 12:44:52.295821 00680000 ################################################################
10102 12:44:52.295957
10103 12:44:52.548283 00700000 ################################################################
10104 12:44:52.548413
10105 12:44:52.804447 00780000 ################################################################
10106 12:44:52.804582
10107 12:44:53.053606 00800000 ################################################################
10108 12:44:53.053742
10109 12:44:53.301895 00880000 ################################################################
10110 12:44:53.302032
10111 12:44:53.566112 00900000 ################################################################
10112 12:44:53.566247
10113 12:44:53.823563 00980000 ################################################################
10114 12:44:53.823768
10115 12:44:54.081406 00a00000 ################################################################
10116 12:44:54.081542
10117 12:44:54.327117 00a80000 ################################################################
10118 12:44:54.327274
10119 12:44:54.573714 00b00000 ################################################################
10120 12:44:54.573855
10121 12:44:54.820017 00b80000 ################################################################
10122 12:44:54.820169
10123 12:44:55.082784 00c00000 ################################################################
10124 12:44:55.082930
10125 12:44:55.348594 00c80000 ################################################################
10126 12:44:55.348762
10127 12:44:55.622879 00d00000 ################################################################
10128 12:44:55.623054
10129 12:44:55.873796 00d80000 ################################################################
10130 12:44:55.873968
10131 12:44:56.126087 00e00000 ################################################################
10132 12:44:56.126222
10133 12:44:56.378861 00e80000 ################################################################
10134 12:44:56.379021
10135 12:44:56.638297 00f00000 ################################################################
10136 12:44:56.638438
10137 12:44:56.893877 00f80000 ################################################################
10138 12:44:56.894020
10139 12:44:57.148292 01000000 ################################################################
10140 12:44:57.148446
10141 12:44:57.400514 01080000 ################################################################
10142 12:44:57.400660
10143 12:44:57.651791 01100000 ################################################################
10144 12:44:57.651943
10145 12:44:57.900952 01180000 ################################################################
10146 12:44:57.901129
10147 12:44:58.156085 01200000 ################################################################
10148 12:44:58.156221
10149 12:44:58.408598 01280000 ################################################################
10150 12:44:58.408762
10151 12:44:58.671362 01300000 ################################################################
10152 12:44:58.671506
10153 12:44:58.957199 01380000 ################################################################
10154 12:44:58.957340
10155 12:44:59.240932 01400000 ################################################################
10156 12:44:59.241098
10157 12:44:59.511857 01480000 ################################################################
10158 12:44:59.511990
10159 12:44:59.786263 01500000 ################################################################
10160 12:44:59.786403
10161 12:45:00.056268 01580000 ################################################################
10162 12:45:00.056410
10163 12:45:00.326834 01600000 ################################################################
10164 12:45:00.326969
10165 12:45:00.601238 01680000 ################################################################
10166 12:45:00.601417
10167 12:45:00.874531 01700000 ################################################################
10168 12:45:00.874690
10169 12:45:01.167737 01780000 ################################################################
10170 12:45:01.167919
10171 12:45:01.452888 01800000 ################################################################
10172 12:45:01.453091
10173 12:45:01.733551 01880000 ################################################################
10174 12:45:01.733730
10175 12:45:02.038362 01900000 ################################################################
10176 12:45:02.038532
10177 12:45:02.340519 01980000 ################################################################
10178 12:45:02.340688
10179 12:45:02.612996 01a00000 ################################################################
10180 12:45:02.613164
10181 12:45:02.865575 01a80000 ################################################################
10182 12:45:02.865755
10183 12:45:03.116861 01b00000 ################################################################
10184 12:45:03.117057
10185 12:45:03.367226 01b80000 ################################################################
10186 12:45:03.367396
10187 12:45:03.622509 01c00000 ################################################################
10188 12:45:03.622647
10189 12:45:03.875460 01c80000 ################################################################
10190 12:45:03.875613
10191 12:45:04.123301 01d00000 ################################################################
10192 12:45:04.123434
10193 12:45:04.375183 01d80000 ################################################################
10194 12:45:04.375336
10195 12:45:04.626985 01e00000 ################################################################
10196 12:45:04.627126
10197 12:45:04.879496 01e80000 ################################################################
10198 12:45:04.879646
10199 12:45:05.131695 01f00000 ################################################################
10200 12:45:05.131849
10201 12:45:05.380105 01f80000 ################################################################
10202 12:45:05.380254
10203 12:45:05.629022 02000000 ################################################################
10204 12:45:05.629185
10205 12:45:05.879978 02080000 ################################################################
10206 12:45:05.880158
10207 12:45:06.130696 02100000 ################################################################
10208 12:45:06.130848
10209 12:45:06.381083 02180000 ################################################################
10210 12:45:06.381238
10211 12:45:06.644480 02200000 ################################################################
10212 12:45:06.644636
10213 12:45:06.892595 02280000 ################################################################
10214 12:45:06.892765
10215 12:45:07.141587 02300000 ################################################################
10216 12:45:07.141753
10217 12:45:07.382959 02380000 ################################################################
10218 12:45:07.383136
10219 12:45:07.634236 02400000 ################################################################
10220 12:45:07.634395
10221 12:45:07.892334 02480000 ################################################################
10222 12:45:07.892480
10223 12:45:08.157293 02500000 ################################################################
10224 12:45:08.157438
10225 12:45:08.405587 02580000 ################################################################
10226 12:45:08.405745
10227 12:45:08.648686 02600000 ################################################################
10228 12:45:08.648869
10229 12:45:08.899749 02680000 ################################################################
10230 12:45:08.899911
10231 12:45:09.149641 02700000 ################################################################
10232 12:45:09.149825
10233 12:45:09.399952 02780000 ################################################################
10234 12:45:09.400120
10235 12:45:09.647799 02800000 ################################################################
10236 12:45:09.647961
10237 12:45:09.898798 02880000 ################################################################
10238 12:45:09.898987
10239 12:45:10.148081 02900000 ################################################################
10240 12:45:10.148215
10241 12:45:10.393609 02980000 ################################################################
10242 12:45:10.393749
10243 12:45:10.639706 02a00000 ################################################################
10244 12:45:10.639843
10245 12:45:10.883897 02a80000 ################################################################
10246 12:45:10.884060
10247 12:45:11.128271 02b00000 ################################################################
10248 12:45:11.128431
10249 12:45:11.371812 02b80000 ################################################################
10250 12:45:11.371950
10251 12:45:11.616166 02c00000 ################################################################
10252 12:45:11.616326
10253 12:45:11.861668 02c80000 ################################################################
10254 12:45:11.861802
10255 12:45:12.106745 02d00000 ################################################################
10256 12:45:12.106881
10257 12:45:12.352192 02d80000 ################################################################
10258 12:45:12.352328
10259 12:45:12.599018 02e00000 ################################################################
10260 12:45:12.599206
10261 12:45:12.841620 02e80000 ################################################################
10262 12:45:12.841762
10263 12:45:13.086592 02f00000 ################################################################
10264 12:45:13.086734
10265 12:45:13.337430 02f80000 ################################################################
10266 12:45:13.337569
10267 12:45:13.581978 03000000 ################################################################
10268 12:45:13.582118
10269 12:45:13.826620 03080000 ################################################################
10270 12:45:13.826761
10271 12:45:14.071954 03100000 ################################################################
10272 12:45:14.072114
10273 12:45:14.325531 03180000 ################################################################
10274 12:45:14.325672
10275 12:45:14.579716 03200000 ################################################################
10276 12:45:14.579873
10277 12:45:14.830014 03280000 ################################################################
10278 12:45:14.830169
10279 12:45:15.079929 03300000 ################################################################
10280 12:45:15.080087
10281 12:45:15.333646 03380000 ################################################################
10282 12:45:15.333782
10283 12:45:15.584518 03400000 ################################################################
10284 12:45:15.584652
10285 12:45:15.835318 03480000 ################################################################
10286 12:45:15.835451
10287 12:45:16.095881 03500000 ################################################################
10288 12:45:16.096008
10289 12:45:16.345545 03580000 ################################################################
10290 12:45:16.345688
10291 12:45:16.594298 03600000 ################################################################
10292 12:45:16.594451
10293 12:45:16.967366 03680000 ################################################################
10294 12:45:16.967970
10295 12:45:17.276273 03700000 ################################################################
10296 12:45:17.276434
10297 12:45:17.574786 03780000 ################################################################
10298 12:45:17.574927
10299 12:45:17.867042 03800000 ################################################################
10300 12:45:17.867208
10301 12:45:18.146257 03880000 ################################################################
10302 12:45:18.146398
10303 12:45:18.420907 03900000 ################################################################
10304 12:45:18.421092
10305 12:45:18.673406 03980000 ################################################################
10306 12:45:18.673554
10307 12:45:18.926195 03a00000 ################################################################
10308 12:45:18.926334
10309 12:45:19.178817 03a80000 ################################################################
10310 12:45:19.178949
10311 12:45:19.428125 03b00000 ################################################################
10312 12:45:19.428264
10313 12:45:19.680791 03b80000 ################################################################
10314 12:45:19.680934
10315 12:45:19.928431 03c00000 ################################################################
10316 12:45:19.928564
10317 12:45:20.191069 03c80000 ################################################################
10318 12:45:20.191239
10319 12:45:20.456204 03d00000 ################################################################
10320 12:45:20.456340
10321 12:45:20.730647 03d80000 ################################################################
10322 12:45:20.730855
10323 12:45:21.002032 03e00000 ################################################################
10324 12:45:21.002188
10325 12:45:21.261496 03e80000 ################################################################
10326 12:45:21.261639
10327 12:45:21.516858 03f00000 ################################################################
10328 12:45:21.517016
10329 12:45:21.763007 03f80000 ################################################################
10330 12:45:21.763158
10331 12:45:22.010697 04000000 ################################################################
10332 12:45:22.010843
10333 12:45:22.258122 04080000 ################################################################
10334 12:45:22.258256
10335 12:45:22.519527 04100000 ################################################################
10336 12:45:22.519689
10337 12:45:22.779042 04180000 ################################################################
10338 12:45:22.779182
10339 12:45:23.031146 04200000 ################################################################
10340 12:45:23.031277
10341 12:45:23.282588 04280000 ################################################################
10342 12:45:23.282736
10343 12:45:23.538323 04300000 ################################################################
10344 12:45:23.538477
10345 12:45:23.790427 04380000 ################################################################
10346 12:45:23.790569
10347 12:45:24.039700 04400000 ################################################################
10348 12:45:24.039845
10349 12:45:24.299060 04480000 ################################################################
10350 12:45:24.299198
10351 12:45:24.559400 04500000 ################################################################
10352 12:45:24.559566
10353 12:45:24.828811 04580000 ################################################################
10354 12:45:24.828973
10355 12:45:25.097603 04600000 ################################################################
10356 12:45:25.097764
10357 12:45:25.361288 04680000 ################################################################
10358 12:45:25.361422
10359 12:45:25.630513 04700000 ################################################################
10360 12:45:25.630649
10361 12:45:25.901849 04780000 ################################################################
10362 12:45:25.901995
10363 12:45:26.152884 04800000 ################################################################
10364 12:45:26.153085
10365 12:45:26.397071 04880000 ################################################################
10366 12:45:26.397222
10367 12:45:26.640860 04900000 ################################################################
10368 12:45:26.641016
10369 12:45:26.896816 04980000 ################################################################
10370 12:45:26.897020
10371 12:45:27.178814 04a00000 ################################################################
10372 12:45:27.178950
10373 12:45:27.458335 04a80000 ################################################################
10374 12:45:27.458475
10375 12:45:27.716346 04b00000 ################################################################
10376 12:45:27.716480
10377 12:45:27.967350 04b80000 ################################################################
10378 12:45:27.967496
10379 12:45:28.219790 04c00000 ################################################################
10380 12:45:28.219929
10381 12:45:28.469058 04c80000 ################################################################
10382 12:45:28.469196
10383 12:45:28.719708 04d00000 ################################################################
10384 12:45:28.719877
10385 12:45:28.968328 04d80000 ################################################################
10386 12:45:28.968513
10387 12:45:29.218238 04e00000 ################################################################
10388 12:45:29.218415
10389 12:45:29.498940 04e80000 ################################################################
10390 12:45:29.499076
10391 12:45:29.796097 04f00000 ################################################################
10392 12:45:29.796224
10393 12:45:30.055422 04f80000 ################################################################
10394 12:45:30.055554
10395 12:45:30.314428 05000000 ################################################################
10396 12:45:30.314582
10397 12:45:30.609750 05080000 ################################################################
10398 12:45:30.609883
10399 12:45:30.882304 05100000 ################################################################
10400 12:45:30.882438
10401 12:45:31.140179 05180000 ################################################################
10402 12:45:31.140316
10403 12:45:31.392562 05200000 ################################################################
10404 12:45:31.392696
10405 12:45:31.644186 05280000 ################################################################
10406 12:45:31.644322
10407 12:45:31.926505 05300000 ################################################################
10408 12:45:31.927051
10409 12:45:32.212588 05380000 ################################################################
10410 12:45:32.212747
10411 12:45:32.494863 05400000 ################################################################
10412 12:45:32.495024
10413 12:45:32.793515 05480000 ################################################################
10414 12:45:32.793669
10415 12:45:33.089768 05500000 ################################################################
10416 12:45:33.089908
10417 12:45:33.352536 05580000 ################################################################
10418 12:45:33.352689
10419 12:45:33.640258 05600000 ################################################################
10420 12:45:33.640407
10421 12:45:33.932067 05680000 ################################################################
10422 12:45:33.932195
10423 12:45:34.226524 05700000 ################################################################
10424 12:45:34.226660
10425 12:45:34.519992 05780000 ################################################################
10426 12:45:34.520127
10427 12:45:34.796249 05800000 ################################################################
10428 12:45:34.796373
10429 12:45:35.093856 05880000 ################################################################
10430 12:45:35.094016
10431 12:45:35.380956 05900000 ################################################################
10432 12:45:35.381146
10433 12:45:35.660329 05980000 ################################################################
10434 12:45:35.660491
10435 12:45:35.924794 05a00000 ################################################################
10436 12:45:35.924949
10437 12:45:36.206812 05a80000 ################################################################
10438 12:45:36.206986
10439 12:45:36.494595 05b00000 ################################################################
10440 12:45:36.494747
10441 12:45:36.785010 05b80000 ################################################################
10442 12:45:36.785178
10443 12:45:37.062969 05c00000 ################################################################
10444 12:45:37.063093
10445 12:45:37.362096 05c80000 ################################################################
10446 12:45:37.362248
10447 12:45:37.660791 05d00000 ################################################################
10448 12:45:37.660927
10449 12:45:37.956871 05d80000 ################################################################
10450 12:45:37.957094
10451 12:45:38.251105 05e00000 ################################################################
10452 12:45:38.251265
10453 12:45:38.539014 05e80000 ################################################################
10454 12:45:38.539156
10455 12:45:38.820372 05f00000 ################################################################
10456 12:45:38.820525
10457 12:45:39.095865 05f80000 ################################################################
10458 12:45:39.096016
10459 12:45:39.391394 06000000 ################################################################
10460 12:45:39.391525
10461 12:45:39.678387 06080000 ################################################################
10462 12:45:39.678514
10463 12:45:39.949626 06100000 ################################################################
10464 12:45:39.949749
10465 12:45:40.223063 06180000 ################################################################
10466 12:45:40.223184
10467 12:45:40.500706 06200000 ################################################################
10468 12:45:40.500864
10469 12:45:40.776441 06280000 ################################################################
10470 12:45:40.776578
10471 12:45:41.053291 06300000 ################################################################
10472 12:45:41.053417
10473 12:45:41.301657 06380000 ################################################################
10474 12:45:41.301776
10475 12:45:41.553024 06400000 ################################################################
10476 12:45:41.553185
10477 12:45:41.805333 06480000 ################################################################
10478 12:45:41.805449
10479 12:45:42.061042 06500000 ################################################################
10480 12:45:42.061157
10481 12:45:42.325559 06580000 ################################################################
10482 12:45:42.325680
10483 12:45:42.573402 06600000 ################################################################
10484 12:45:42.573531
10485 12:45:42.860098 06680000 ################################################################
10486 12:45:42.860264
10487 12:45:43.133605 06700000 ################################################################
10488 12:45:43.133729
10489 12:45:43.192226 06780000 ############### done.
10490 12:45:43.192317
10491 12:45:43.195354 The bootfile was 108645522 bytes long.
10492 12:45:43.195779
10493 12:45:43.198875 Sending tftp read request... done.
10494 12:45:43.199340
10495 12:45:43.202577 Waiting for the transfer...
10496 12:45:43.203043
10497 12:45:43.203413 00000000 # done.
10498 12:45:43.205532
10499 12:45:43.212364 Command line loaded dynamically from TFTP file: 10724891/tftp-deploy-y3xahij0/kernel/cmdline
10500 12:45:43.212945
10501 12:45:43.222016 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10502 12:45:43.222494
10503 12:45:43.225066 Loading FIT.
10504 12:45:43.225532
10505 12:45:43.228782 Image ramdisk-1 has 98154185 bytes.
10506 12:45:43.229280
10507 12:45:43.229649 Image fdt-1 has 46924 bytes.
10508 12:45:43.231665
10509 12:45:43.232130 Image kernel-1 has 10442380 bytes.
10510 12:45:43.232499
10511 12:45:43.241611 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10512 12:45:43.242198
10513 12:45:43.258421 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10514 12:45:43.261380
10515 12:45:43.264331 Choosing best match conf-1 for compat google,spherion-rev2.
10516 12:45:43.269397
10517 12:45:43.273187 Connected to device vid:did:rid of 1ae0:0028:00
10518 12:45:43.280654
10519 12:45:43.284029 tpm_get_response: command 0x17b, return code 0x0
10520 12:45:43.284600
10521 12:45:43.290506 ec_init: CrosEC protocol v3 supported (256, 248)
10522 12:45:43.291080
10523 12:45:43.293580 tpm_cleanup: add release locality here.
10524 12:45:43.294191
10525 12:45:43.296936 Shutting down all USB controllers.
10526 12:45:43.297451
10527 12:45:43.300489 Removing current net device
10528 12:45:43.301089
10529 12:45:43.303613 Exiting depthcharge with code 4 at timestamp: 97511598
10530 12:45:43.307303
10531 12:45:43.310262 LZMA decompressing kernel-1 to 0x821a6718
10532 12:45:43.310729
10533 12:45:43.313351 LZMA decompressing kernel-1 to 0x40000000
10534 12:45:44.623731
10535 12:45:44.624297 jumping to kernel
10536 12:45:44.626141 end: 2.2.4 bootloader-commands (duration 00:01:10) [common]
10537 12:45:44.626703 start: 2.2.5 auto-login-action (timeout 00:03:16) [common]
10538 12:45:44.627115 Setting prompt string to ['Linux version [0-9]']
10539 12:45:44.627496 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10540 12:45:44.627889 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10541 12:45:44.707032
10542 12:45:44.709964 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10543 12:45:44.713687 start: 2.2.5.1 login-action (timeout 00:03:16) [common]
10544 12:45:44.714283 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10545 12:45:44.714756 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10546 12:45:44.715193 Using line separator: #'\n'#
10547 12:45:44.715540 No login prompt set.
10548 12:45:44.715892 Parsing kernel messages
10549 12:45:44.716296 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10550 12:45:44.716876 [login-action] Waiting for messages, (timeout 00:03:16)
10551 12:45:44.733258 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10552 12:45:44.736138 [ 0.000000] random: crng init done
10553 12:45:44.740094 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10554 12:45:44.742715 [ 0.000000] efi: UEFI not found.
10555 12:45:44.752733 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10556 12:45:44.759520 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10557 12:45:44.769760 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10558 12:45:44.779353 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10559 12:45:44.786020 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10560 12:45:44.789463 [ 0.000000] printk: bootconsole [mtk8250] enabled
10561 12:45:44.797793 [ 0.000000] NUMA: No NUMA configuration found
10562 12:45:44.804015 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10563 12:45:44.810903 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10564 12:45:44.811472 [ 0.000000] Zone ranges:
10565 12:45:44.817132 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10566 12:45:44.820897 [ 0.000000] DMA32 empty
10567 12:45:44.827061 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10568 12:45:44.830240 [ 0.000000] Movable zone start for each node
10569 12:45:44.834142 [ 0.000000] Early memory node ranges
10570 12:45:44.840741 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10571 12:45:44.847033 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10572 12:45:44.854034 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10573 12:45:44.860284 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10574 12:45:44.866897 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10575 12:45:44.873873 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10576 12:45:44.930030 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10577 12:45:44.936558 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10578 12:45:44.942999 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10579 12:45:44.946654 [ 0.000000] psci: probing for conduit method from DT.
10580 12:45:44.953168 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10581 12:45:44.956252 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10582 12:45:44.962745 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10583 12:45:44.966235 [ 0.000000] psci: SMC Calling Convention v1.2
10584 12:45:44.973266 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10585 12:45:44.976301 [ 0.000000] Detected VIPT I-cache on CPU0
10586 12:45:44.982991 [ 0.000000] CPU features: detected: GIC system register CPU interface
10587 12:45:44.989134 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10588 12:45:44.995792 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10589 12:45:45.002951 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10590 12:45:45.012097 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10591 12:45:45.019139 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10592 12:45:45.022037 [ 0.000000] alternatives: applying boot alternatives
10593 12:45:45.029100 [ 0.000000] Fallback order for Node 0: 0
10594 12:45:45.035789 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10595 12:45:45.038734 [ 0.000000] Policy zone: Normal
10596 12:45:45.048512 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10597 12:45:45.061784 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10598 12:45:45.072070 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10599 12:45:45.081954 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10600 12:45:45.088253 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10601 12:45:45.091530 <6>[ 0.000000] software IO TLB: area num 8.
10602 12:45:45.147669 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10603 12:45:45.296527 <6>[ 0.000000] Memory: 7875304K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 477464K reserved, 32768K cma-reserved)
10604 12:45:45.303270 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10605 12:45:45.309701 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10606 12:45:45.312896 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10607 12:45:45.319500 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10608 12:45:45.326109 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10609 12:45:45.329134 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10610 12:45:45.339441 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10611 12:45:45.345938 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10612 12:45:45.352668 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10613 12:45:45.358864 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10614 12:45:45.362706 <6>[ 0.000000] GICv3: 608 SPIs implemented
10615 12:45:45.365766 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10616 12:45:45.372186 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10617 12:45:45.375424 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10618 12:45:45.382022 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10619 12:45:45.395383 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10620 12:45:45.408731 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10621 12:45:45.414783 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10622 12:45:45.422957 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10623 12:45:45.436400 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10624 12:45:45.442993 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10625 12:45:45.449532 <6>[ 0.009224] Console: colour dummy device 80x25
10626 12:45:45.459186 <6>[ 0.013949] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10627 12:45:45.466414 <6>[ 0.024457] pid_max: default: 32768 minimum: 301
10628 12:45:45.469286 <6>[ 0.029331] LSM: Security Framework initializing
10629 12:45:45.476114 <6>[ 0.034301] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10630 12:45:45.485863 <6>[ 0.042163] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10631 12:45:45.495504 <6>[ 0.051641] cblist_init_generic: Setting adjustable number of callback queues.
10632 12:45:45.502276 <6>[ 0.059093] cblist_init_generic: Setting shift to 3 and lim to 1.
10633 12:45:45.505903 <6>[ 0.065432] cblist_init_generic: Setting shift to 3 and lim to 1.
10634 12:45:45.512192 <6>[ 0.071879] rcu: Hierarchical SRCU implementation.
10635 12:45:45.518694 <6>[ 0.076892] rcu: Max phase no-delay instances is 1000.
10636 12:45:45.525361 <6>[ 0.083907] EFI services will not be available.
10637 12:45:45.528568 <6>[ 0.088906] smp: Bringing up secondary CPUs ...
10638 12:45:45.536635 <6>[ 0.093959] Detected VIPT I-cache on CPU1
10639 12:45:45.543259 <6>[ 0.094030] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10640 12:45:45.550326 <6>[ 0.094060] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10641 12:45:45.553042 <6>[ 0.094397] Detected VIPT I-cache on CPU2
10642 12:45:45.559825 <6>[ 0.094448] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10643 12:45:45.569505 <6>[ 0.094463] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10644 12:45:45.572868 <6>[ 0.094721] Detected VIPT I-cache on CPU3
10645 12:45:45.579659 <6>[ 0.094770] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10646 12:45:45.585996 <6>[ 0.094785] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10647 12:45:45.589553 <6>[ 0.095090] CPU features: detected: Spectre-v4
10648 12:45:45.595779 <6>[ 0.095097] CPU features: detected: Spectre-BHB
10649 12:45:45.598955 <6>[ 0.095103] Detected PIPT I-cache on CPU4
10650 12:45:45.605576 <6>[ 0.095162] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10651 12:45:45.612360 <6>[ 0.095179] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10652 12:45:45.619089 <6>[ 0.095469] Detected PIPT I-cache on CPU5
10653 12:45:45.625422 <6>[ 0.095524] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10654 12:45:45.632255 <6>[ 0.095540] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10655 12:45:45.635801 <6>[ 0.095810] Detected PIPT I-cache on CPU6
10656 12:45:45.642741 <6>[ 0.095874] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10657 12:45:45.649038 <6>[ 0.095890] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10658 12:45:45.655290 <6>[ 0.096188] Detected PIPT I-cache on CPU7
10659 12:45:45.661777 <6>[ 0.096254] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10660 12:45:45.668585 <6>[ 0.096269] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10661 12:45:45.672347 <6>[ 0.096316] smp: Brought up 1 node, 8 CPUs
10662 12:45:45.678989 <6>[ 0.237531] SMP: Total of 8 processors activated.
10663 12:45:45.681547 <6>[ 0.242483] CPU features: detected: 32-bit EL0 Support
10664 12:45:45.691776 <6>[ 0.247846] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10665 12:45:45.697873 <6>[ 0.256701] CPU features: detected: Common not Private translations
10666 12:45:45.704739 <6>[ 0.263217] CPU features: detected: CRC32 instructions
10667 12:45:45.711161 <6>[ 0.268591] CPU features: detected: RCpc load-acquire (LDAPR)
10668 12:45:45.714630 <6>[ 0.274588] CPU features: detected: LSE atomic instructions
10669 12:45:45.721174 <6>[ 0.280369] CPU features: detected: Privileged Access Never
10670 12:45:45.728196 <6>[ 0.286148] CPU features: detected: RAS Extension Support
10671 12:45:45.734292 <6>[ 0.291757] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10672 12:45:45.737890 <6>[ 0.298977] CPU: All CPU(s) started at EL2
10673 12:45:45.744083 <6>[ 0.303318] alternatives: applying system-wide alternatives
10674 12:45:45.754338 <6>[ 0.314070] devtmpfs: initialized
10675 12:45:45.769776 <6>[ 0.323002] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10676 12:45:45.776895 <6>[ 0.332966] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10677 12:45:45.782853 <6>[ 0.341116] pinctrl core: initialized pinctrl subsystem
10678 12:45:45.786167 <6>[ 0.347774] DMI not present or invalid.
10679 12:45:45.793007 <6>[ 0.352181] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10680 12:45:45.802735 <6>[ 0.359043] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10681 12:45:45.809545 <6>[ 0.366622] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10682 12:45:45.819599 <6>[ 0.374840] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10683 12:45:45.822400 <6>[ 0.383082] audit: initializing netlink subsys (disabled)
10684 12:45:45.832256 <5>[ 0.388774] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10685 12:45:45.838758 <6>[ 0.389474] thermal_sys: Registered thermal governor 'step_wise'
10686 12:45:45.845878 <6>[ 0.396739] thermal_sys: Registered thermal governor 'power_allocator'
10687 12:45:45.849619 <6>[ 0.402993] cpuidle: using governor menu
10688 12:45:45.855302 <6>[ 0.413945] NET: Registered PF_QIPCRTR protocol family
10689 12:45:45.861983 <6>[ 0.419423] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10690 12:45:45.869238 <6>[ 0.426526] ASID allocator initialised with 32768 entries
10691 12:45:45.871696 <6>[ 0.433110] Serial: AMBA PL011 UART driver
10692 12:45:45.882271 <4>[ 0.441832] Trying to register duplicate clock ID: 134
10693 12:45:45.936229 <6>[ 0.499448] KASLR enabled
10694 12:45:45.950546 <6>[ 0.507154] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10695 12:45:45.957133 <6>[ 0.514168] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10696 12:45:45.963916 <6>[ 0.520657] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10697 12:45:45.970275 <6>[ 0.527663] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10698 12:45:45.977214 <6>[ 0.534149] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10699 12:45:45.983710 <6>[ 0.541156] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10700 12:45:45.990358 <6>[ 0.547642] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10701 12:45:45.996831 <6>[ 0.554646] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10702 12:45:46.000199 <6>[ 0.562157] ACPI: Interpreter disabled.
10703 12:45:46.008571 <6>[ 0.568549] iommu: Default domain type: Translated
10704 12:45:46.015565 <6>[ 0.573657] iommu: DMA domain TLB invalidation policy: strict mode
10705 12:45:46.018748 <5>[ 0.580313] SCSI subsystem initialized
10706 12:45:46.025117 <6>[ 0.584480] usbcore: registered new interface driver usbfs
10707 12:45:46.032125 <6>[ 0.590212] usbcore: registered new interface driver hub
10708 12:45:46.034912 <6>[ 0.595762] usbcore: registered new device driver usb
10709 12:45:46.041840 <6>[ 0.601844] pps_core: LinuxPPS API ver. 1 registered
10710 12:45:46.051858 <6>[ 0.607035] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10711 12:45:46.055583 <6>[ 0.616380] PTP clock support registered
10712 12:45:46.058946 <6>[ 0.620623] EDAC MC: Ver: 3.0.0
10713 12:45:46.066158 <6>[ 0.625771] FPGA manager framework
10714 12:45:46.072714 <6>[ 0.629454] Advanced Linux Sound Architecture Driver Initialized.
10715 12:45:46.076484 <6>[ 0.636233] vgaarb: loaded
10716 12:45:46.082105 <6>[ 0.639392] clocksource: Switched to clocksource arch_sys_counter
10717 12:45:46.086092 <5>[ 0.645831] VFS: Disk quotas dquot_6.6.0
10718 12:45:46.092968 <6>[ 0.650014] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10719 12:45:46.095364 <6>[ 0.657204] pnp: PnP ACPI: disabled
10720 12:45:46.104410 <6>[ 0.663951] NET: Registered PF_INET protocol family
10721 12:45:46.113886 <6>[ 0.669555] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10722 12:45:46.125365 <6>[ 0.681868] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10723 12:45:46.135153 <6>[ 0.690683] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10724 12:45:46.141780 <6>[ 0.698654] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10725 12:45:46.151797 <6>[ 0.707351] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10726 12:45:46.158015 <6>[ 0.717075] TCP: Hash tables configured (established 65536 bind 65536)
10727 12:45:46.164626 <6>[ 0.723932] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10728 12:45:46.174841 <6>[ 0.731130] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10729 12:45:46.181437 <6>[ 0.738832] NET: Registered PF_UNIX/PF_LOCAL protocol family
10730 12:45:46.184390 <6>[ 0.744908] RPC: Registered named UNIX socket transport module.
10731 12:45:46.191481 <6>[ 0.751056] RPC: Registered udp transport module.
10732 12:45:46.194805 <6>[ 0.755988] RPC: Registered tcp transport module.
10733 12:45:46.200895 <6>[ 0.760920] RPC: Registered tcp NFSv4.1 backchannel transport module.
10734 12:45:46.207836 <6>[ 0.767584] PCI: CLS 0 bytes, default 64
10735 12:45:46.211377 <6>[ 0.771902] Unpacking initramfs...
10736 12:45:46.227103 <6>[ 0.783932] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10737 12:45:46.237221 <6>[ 0.792599] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10738 12:45:46.240514 <6>[ 0.801438] kvm [1]: IPA Size Limit: 40 bits
10739 12:45:46.247300 <6>[ 0.805967] kvm [1]: GICv3: no GICV resource entry
10740 12:45:46.250539 <6>[ 0.810986] kvm [1]: disabling GICv2 emulation
10741 12:45:46.256953 <6>[ 0.815675] kvm [1]: GIC system register CPU interface enabled
10742 12:45:46.260371 <6>[ 0.821831] kvm [1]: vgic interrupt IRQ18
10743 12:45:46.266869 <6>[ 0.826208] kvm [1]: VHE mode initialized successfully
10744 12:45:46.273556 <5>[ 0.832625] Initialise system trusted keyrings
10745 12:45:46.279992 <6>[ 0.837447] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10746 12:45:46.288044 <6>[ 0.847493] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10747 12:45:46.294000 <5>[ 0.853885] NFS: Registering the id_resolver key type
10748 12:45:46.297818 <5>[ 0.859189] Key type id_resolver registered
10749 12:45:46.304036 <5>[ 0.863603] Key type id_legacy registered
10750 12:45:46.310524 <6>[ 0.867891] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10751 12:45:46.317708 <6>[ 0.874813] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10752 12:45:46.323872 <6>[ 0.882525] 9p: Installing v9fs 9p2000 file system support
10753 12:45:46.360891 <5>[ 0.920812] Key type asymmetric registered
10754 12:45:46.363938 <5>[ 0.925142] Asymmetric key parser 'x509' registered
10755 12:45:46.374006 <6>[ 0.930276] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10756 12:45:46.377714 <6>[ 0.937888] io scheduler mq-deadline registered
10757 12:45:46.381030 <6>[ 0.942647] io scheduler kyber registered
10758 12:45:46.399906 <6>[ 0.959612] EINJ: ACPI disabled.
10759 12:45:46.431969 <4>[ 0.984667] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10760 12:45:46.441064 <4>[ 0.995315] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10761 12:45:46.455839 <6>[ 1.015924] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10762 12:45:46.464366 <6>[ 1.023844] printk: console [ttyS0] disabled
10763 12:45:46.491532 <6>[ 1.048485] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10764 12:45:46.499193 <6>[ 1.057957] printk: console [ttyS0] enabled
10765 12:45:46.501656 <6>[ 1.057957] printk: console [ttyS0] enabled
10766 12:45:46.508643 <6>[ 1.066852] printk: bootconsole [mtk8250] disabled
10767 12:45:46.511765 <6>[ 1.066852] printk: bootconsole [mtk8250] disabled
10768 12:45:46.518095 <6>[ 1.077822] SuperH (H)SCI(F) driver initialized
10769 12:45:46.521633 <6>[ 1.083082] msm_serial: driver initialized
10770 12:45:46.535398 <6>[ 1.091899] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10771 12:45:46.545454 <6>[ 1.100441] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10772 12:45:46.551775 <6>[ 1.108985] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10773 12:45:46.561621 <6>[ 1.117613] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10774 12:45:46.571604 <6>[ 1.126318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10775 12:45:46.578464 <6>[ 1.135037] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10776 12:45:46.587906 <6>[ 1.143576] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10777 12:45:46.594462 <6>[ 1.152368] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10778 12:45:46.604351 <6>[ 1.160910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10779 12:45:46.616472 <6>[ 1.176266] loop: module loaded
10780 12:45:46.622706 <6>[ 1.182251] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10781 12:45:46.645820 <4>[ 1.205348] mtk-pmic-keys: Failed to locate of_node [id: -1]
10782 12:45:46.652204 <6>[ 1.211978] megasas: 07.719.03.00-rc1
10783 12:45:46.661399 <6>[ 1.221347] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10784 12:45:46.671388 <6>[ 1.230757] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10785 12:45:46.687448 <6>[ 1.247230] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10786 12:45:46.746741 <6>[ 1.300211] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10787 12:45:50.197822 <6>[ 4.758300] Freeing initrd memory: 95848K
10788 12:45:50.208435 <6>[ 4.768888] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10789 12:45:50.219388 <6>[ 4.780055] tun: Universal TUN/TAP device driver, 1.6
10790 12:45:50.222458 <6>[ 4.786127] thunder_xcv, ver 1.0
10791 12:45:50.226155 <6>[ 4.789634] thunder_bgx, ver 1.0
10792 12:45:50.229225 <6>[ 4.793130] nicpf, ver 1.0
10793 12:45:50.239908 <6>[ 4.797170] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10794 12:45:50.243283 <6>[ 4.804646] hns3: Copyright (c) 2017 Huawei Corporation.
10795 12:45:50.249744 <6>[ 4.810232] hclge is initializing
10796 12:45:50.253319 <6>[ 4.813817] e1000: Intel(R) PRO/1000 Network Driver
10797 12:45:50.259739 <6>[ 4.818947] e1000: Copyright (c) 1999-2006 Intel Corporation.
10798 12:45:50.263425 <6>[ 4.824963] e1000e: Intel(R) PRO/1000 Network Driver
10799 12:45:50.269737 <6>[ 4.830178] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10800 12:45:50.276820 <6>[ 4.836364] igb: Intel(R) Gigabit Ethernet Network Driver
10801 12:45:50.282971 <6>[ 4.842013] igb: Copyright (c) 2007-2014 Intel Corporation.
10802 12:45:50.289575 <6>[ 4.847850] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10803 12:45:50.296117 <6>[ 4.854368] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10804 12:45:50.299821 <6>[ 4.860830] sky2: driver version 1.30
10805 12:45:50.306076 <6>[ 4.865820] VFIO - User Level meta-driver version: 0.3
10806 12:45:50.313336 <6>[ 4.874012] usbcore: registered new interface driver usb-storage
10807 12:45:50.320025 <6>[ 4.880457] usbcore: registered new device driver onboard-usb-hub
10808 12:45:50.329169 <6>[ 4.889542] mt6397-rtc mt6359-rtc: registered as rtc0
10809 12:45:50.338905 <6>[ 4.895006] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:45:45 UTC (1686746745)
10810 12:45:50.342788 <6>[ 4.904590] i2c_dev: i2c /dev entries driver
10811 12:45:50.359274 <6>[ 4.916324] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10812 12:45:50.366002 <6>[ 4.926552] sdhci: Secure Digital Host Controller Interface driver
10813 12:45:50.373356 <6>[ 4.932991] sdhci: Copyright(c) Pierre Ossman
10814 12:45:50.379539 <6>[ 4.938383] Synopsys Designware Multimedia Card Interface Driver
10815 12:45:50.382374 <6>[ 4.945016] mmc0: CQHCI version 5.10
10816 12:45:50.389389 <6>[ 4.945533] sdhci-pltfm: SDHCI platform and OF driver helper
10817 12:45:50.397109 <6>[ 4.957239] ledtrig-cpu: registered to indicate activity on CPUs
10818 12:45:50.407787 <6>[ 4.964614] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10819 12:45:50.414137 <6>[ 4.972022] usbcore: registered new interface driver usbhid
10820 12:45:50.417165 <6>[ 4.977855] usbhid: USB HID core driver
10821 12:45:50.424237 <6>[ 4.982096] spi_master spi0: will run message pump with realtime priority
10822 12:45:50.468585 <6>[ 5.022168] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10823 12:45:50.487477 <6>[ 5.037335] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10824 12:45:50.491128 <6>[ 5.050917] mmc0: Command Queue Engine enabled
10825 12:45:50.497387 <6>[ 5.053284] cros-ec-spi spi0.0: Chrome EC device registered
10826 12:45:50.503884 <6>[ 5.055651] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10827 12:45:50.507189 <6>[ 5.068753] mmcblk0: mmc0:0001 DA4128 116 GiB
10828 12:45:50.518526 <6>[ 5.078844] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10829 12:45:50.528410 <6>[ 5.079207] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10830 12:45:50.535097 <6>[ 5.086275] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10831 12:45:50.538533 <6>[ 5.096195] NET: Registered PF_PACKET protocol family
10832 12:45:50.544960 <6>[ 5.099948] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10833 12:45:50.548615 <6>[ 5.104721] 9pnet: Installing 9P2000 support
10834 12:45:50.554684 <6>[ 5.110497] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10835 12:45:50.561602 <5>[ 5.114397] Key type dns_resolver registered
10836 12:45:50.564744 <6>[ 5.125914] registered taskstats version 1
10837 12:45:50.571602 <5>[ 5.130303] Loading compiled-in X.509 certificates
10838 12:45:50.604648 <4>[ 5.158463] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10839 12:45:50.614574 <4>[ 5.169200] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10840 12:45:50.624955 <3>[ 5.182212] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10841 12:45:50.637405 <6>[ 5.197835] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10842 12:45:50.644149 <6>[ 5.204613] xhci-mtk 11200000.usb: xHCI Host Controller
10843 12:45:50.650707 <6>[ 5.210119] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10844 12:45:50.660653 <6>[ 5.217965] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10845 12:45:50.667317 <6>[ 5.227405] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10846 12:45:50.673578 <6>[ 5.233597] xhci-mtk 11200000.usb: xHCI Host Controller
10847 12:45:50.680409 <6>[ 5.239101] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10848 12:45:50.686961 <6>[ 5.246768] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10849 12:45:50.694276 <6>[ 5.254669] hub 1-0:1.0: USB hub found
10850 12:45:50.697352 <6>[ 5.258713] hub 1-0:1.0: 1 port detected
10851 12:45:50.707417 <6>[ 5.263077] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10852 12:45:50.710504 <6>[ 5.271889] hub 2-0:1.0: USB hub found
10853 12:45:50.713601 <6>[ 5.275931] hub 2-0:1.0: 1 port detected
10854 12:45:50.723252 <6>[ 5.282972] mtk-msdc 11f70000.mmc: Got CD GPIO
10855 12:45:50.739731 <6>[ 5.296388] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10856 12:45:50.745903 <6>[ 5.304513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10857 12:45:50.755828 <4>[ 5.312507] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10858 12:45:50.765959 <6>[ 5.322216] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10859 12:45:50.773210 <6>[ 5.330305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10860 12:45:50.782335 <6>[ 5.338376] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10861 12:45:50.789169 <6>[ 5.346301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10862 12:45:50.795716 <6>[ 5.354161] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10863 12:45:50.805368 <6>[ 5.361986] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10864 12:45:50.816212 <6>[ 5.372667] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10865 12:45:50.825707 <6>[ 5.381030] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10866 12:45:50.832162 <6>[ 5.389459] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10867 12:45:50.841610 <6>[ 5.397807] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10868 12:45:50.848467 <6>[ 5.406180] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10869 12:45:50.858436 <6>[ 5.414525] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10870 12:45:50.865418 <6>[ 5.422896] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10871 12:45:50.875133 <6>[ 5.431241] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10872 12:45:50.881678 <6>[ 5.439606] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10873 12:45:50.891549 <6>[ 5.447952] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10874 12:45:50.898299 <6>[ 5.456295] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10875 12:45:50.908066 <6>[ 5.464638] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10876 12:45:50.914422 <6>[ 5.472995] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10877 12:45:50.923956 <6>[ 5.481341] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10878 12:45:50.933884 <6>[ 5.489685] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10879 12:45:50.940515 <6>[ 5.498586] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10880 12:45:50.947131 <6>[ 5.506063] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10881 12:45:50.953888 <6>[ 5.513161] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10882 12:45:50.960118 <6>[ 5.520354] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10883 12:45:50.970143 <6>[ 5.527693] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10884 12:45:50.977057 <6>[ 5.534614] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10885 12:45:50.986831 <6>[ 5.543755] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10886 12:45:50.997316 <6>[ 5.552962] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10887 12:45:51.006433 <6>[ 5.562404] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10888 12:45:51.016864 <6>[ 5.571884] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10889 12:45:51.026635 <6>[ 5.581358] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10890 12:45:51.036182 <6>[ 5.590486] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10891 12:45:51.042995 <6>[ 5.599960] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10892 12:45:51.052368 <6>[ 5.609087] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10893 12:45:51.062472 <6>[ 5.618389] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10894 12:45:51.072256 <6>[ 5.628587] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10895 12:45:51.082782 <6>[ 5.640120] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10896 12:45:51.130501 <6>[ 5.687667] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10897 12:45:51.284721 <6>[ 5.845020] hub 1-1:1.0: USB hub found
10898 12:45:51.287815 <6>[ 5.849510] hub 1-1:1.0: 4 ports detected
10899 12:45:51.410748 <6>[ 5.967894] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10900 12:45:51.437504 <6>[ 5.997655] hub 2-1:1.0: USB hub found
10901 12:45:51.440605 <6>[ 6.002143] hub 2-1:1.0: 3 ports detected
10902 12:45:51.610084 <6>[ 6.167671] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10903 12:45:51.743642 <6>[ 6.303958] hub 1-1.4:1.0: USB hub found
10904 12:45:51.746754 <6>[ 6.308637] hub 1-1.4:1.0: 2 ports detected
10905 12:45:51.822380 <6>[ 6.379896] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10906 12:45:52.046343 <6>[ 6.603664] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10907 12:45:52.238274 <6>[ 6.795665] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10908 12:46:03.367615 <6>[ 17.932311] ALSA device list:
10909 12:46:03.373313 <6>[ 17.935565] No soundcards found.
10910 12:46:03.385785 <6>[ 17.947956] Freeing unused kernel memory: 8384K
10911 12:46:03.389622 <6>[ 17.952860] Run /init as init process
10912 12:46:03.419798 <6>[ 17.981606] NET: Registered PF_INET6 protocol family
10913 12:46:03.426602 <6>[ 17.988022] Segment Routing with IPv6
10914 12:46:03.429377 <6>[ 17.991970] In-situ OAM (IOAM) with IPv6
10915 12:46:03.464551 <30>[ 18.006666] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10916 12:46:03.467903 <30>[ 18.030589] systemd[1]: Detected architecture arm64.
10917 12:46:03.471138
10918 12:46:03.474411 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10919 12:46:03.474888
10920 12:46:03.490384 <30>[ 18.051780] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10921 12:46:03.643914 <30>[ 18.202826] systemd[1]: Queued start job for default target Graphical Interface.
10922 12:46:03.687087 <30>[ 18.248980] systemd[1]: Created slice system-getty.slice.
10923 12:46:03.693541 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10924 12:46:03.710741 <30>[ 18.272352] systemd[1]: Created slice system-modprobe.slice.
10925 12:46:03.716907 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10926 12:46:03.734649 <30>[ 18.296776] systemd[1]: Created slice system-serial\x2dgetty.slice.
10927 12:46:03.744572 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10928 12:46:03.758018 <30>[ 18.320174] systemd[1]: Created slice User and Session Slice.
10929 12:46:03.764710 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10930 12:46:03.785688 <30>[ 18.344230] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10931 12:46:03.795382 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10932 12:46:03.813566 <30>[ 18.371828] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10933 12:46:03.819858 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10934 12:46:03.840440 <30>[ 18.395780] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10935 12:46:03.846974 <30>[ 18.407811] systemd[1]: Reached target Local Encrypted Volumes.
10936 12:46:03.853321 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10937 12:46:03.870503 <30>[ 18.432017] systemd[1]: Reached target Paths.
10938 12:46:03.873697 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10939 12:46:03.889996 <30>[ 18.451800] systemd[1]: Reached target Remote File Systems.
10940 12:46:03.896519 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10941 12:46:03.914320 <30>[ 18.475937] systemd[1]: Reached target Slices.
10942 12:46:03.920428 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10943 12:46:03.933996 <30>[ 18.495740] systemd[1]: Reached target Swap.
10944 12:46:03.936727 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10945 12:46:03.957319 <30>[ 18.516030] systemd[1]: Listening on initctl Compatibility Named Pipe.
10946 12:46:03.963933 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10947 12:46:03.970344 <30>[ 18.530753] systemd[1]: Listening on Journal Audit Socket.
10948 12:46:03.976819 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10949 12:46:03.990096 <30>[ 18.551999] systemd[1]: Listening on Journal Socket (/dev/log).
10950 12:46:03.996710 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10951 12:46:04.014315 <30>[ 18.576449] systemd[1]: Listening on Journal Socket.
10952 12:46:04.020920 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10953 12:46:04.034406 <30>[ 18.596015] systemd[1]: Listening on udev Control Socket.
10954 12:46:04.040776 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10955 12:46:04.058709 <30>[ 18.620334] systemd[1]: Listening on udev Kernel Socket.
10956 12:46:04.065312 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10957 12:46:04.102213 <30>[ 18.664111] systemd[1]: Mounting Huge Pages File System...
10958 12:46:04.108434 Mounting [0;1;39mHuge Pages File System[0m...
10959 12:46:04.123573 <30>[ 18.685709] systemd[1]: Mounting POSIX Message Queue File System...
10960 12:46:04.130410 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10961 12:46:04.148242 <30>[ 18.709908] systemd[1]: Mounting Kernel Debug File System...
10962 12:46:04.154428 Mounting [0;1;39mKernel Debug File System[0m...
10963 12:46:04.173213 <30>[ 18.732145] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10964 12:46:04.184638 <30>[ 18.743151] systemd[1]: Starting Create list of static device nodes for the current kernel...
10965 12:46:04.190880 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10966 12:46:04.208312 <30>[ 18.769955] systemd[1]: Starting Load Kernel Module configfs...
10967 12:46:04.214335 Starting [0;1;39mLoad Kernel Module configfs[0m...
10968 12:46:04.232197 <30>[ 18.794140] systemd[1]: Starting Load Kernel Module drm...
10969 12:46:04.238818 Starting [0;1;39mLoad Kernel Module drm[0m...
10970 12:46:04.257241 <30>[ 18.815885] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10971 12:46:04.310414 <30>[ 18.872370] systemd[1]: Starting Journal Service...
10972 12:46:04.313623 Starting [0;1;39mJournal Service[0m...
10973 12:46:04.332351 <30>[ 18.894494] systemd[1]: Starting Load Kernel Modules...
10974 12:46:04.338873 Starting [0;1;39mLoad Kernel Modules[0m...
10975 12:46:04.359530 <30>[ 18.918210] systemd[1]: Starting Remount Root and Kernel File Systems...
10976 12:46:04.366408 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10977 12:46:04.380377 <30>[ 18.942095] systemd[1]: Starting Coldplug All udev Devices...
10978 12:46:04.386533 Starting [0;1;39mColdplug All udev Devices[0m...
10979 12:46:04.404334 <30>[ 18.966375] systemd[1]: Mounted Huge Pages File System.
10980 12:46:04.410730 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10981 12:46:04.426037 <30>[ 18.988266] systemd[1]: Started Journal Service.
10982 12:46:04.432802 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10983 12:46:04.447314 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10984 12:46:04.462993 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10985 12:46:04.482792 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10986 12:46:04.499072 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10987 12:46:04.515143 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10988 12:46:04.531248 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10989 12:46:04.550561 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10990 12:46:04.566342 See 'systemctl status systemd-remount-fs.service' for details.
10991 12:46:04.618462 Mounting [0;1;39mKernel Configuration File System[0m...
10992 12:46:04.636942 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10993 12:46:04.653370 <46>[ 19.212181] systemd-journald[173]: Received client request to flush runtime journal.
10994 12:46:04.662261 Starting [0;1;39mLoad/Save Random Seed[0m...
10995 12:46:04.680902 Starting [0;1;39mApply Kernel Variables[0m...
10996 12:46:04.700313 Starting [0;1;39mCreate System Users[0m...
10997 12:46:04.716440 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10998 12:46:04.738327 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10999 12:46:04.755192 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11000 12:46:04.771089 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11001 12:46:04.787061 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11002 12:46:04.802892 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11003 12:46:04.846170 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11004 12:46:04.870693 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11005 12:46:04.882061 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11006 12:46:04.898126 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11007 12:46:04.942418 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11008 12:46:04.965478 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11009 12:46:04.986520 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11010 12:46:05.006441 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11011 12:46:05.046958 Starting [0;1;39mNetwork Time Synchronization[0m...
11012 12:46:05.065516 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11013 12:46:05.106264 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11014 12:46:05.161008 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11015 12:46:05.193377 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11016 12:46:05.213114 [[0;32m OK [0m] Reached targ<6>[ 19.769904] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11017 12:46:05.213704 et [0;1;39mSystem Time Set[0m.
11018 12:46:05.224307 <6>[ 19.785911] remoteproc remoteproc0: scp is available
11019 12:46:05.233875 <4>[ 19.791530] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11020 12:46:05.240516 <6>[ 19.801433] remoteproc remoteproc0: powering up scp
11021 12:46:05.247297 <6>[ 19.805987] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11022 12:46:05.257229 <4>[ 19.807498] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11023 12:46:05.266527 <6>[ 19.814355] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11024 12:46:05.273478 <4>[ 19.816083] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11025 12:46:05.280034 <4>[ 19.816298] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11026 12:46:05.286567 <3>[ 19.825505] remoteproc remoteproc0: request_firmware failed: -2
11027 12:46:05.296861 <6>[ 19.832705] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11028 12:46:05.300071 <6>[ 19.835957] mc: Linux media interface: v0.10
11029 12:46:05.306645 <6>[ 19.839259] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11030 12:46:05.316312 <3>[ 19.846541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11031 12:46:05.319742 <6>[ 19.863481] usbcore: registered new interface driver r8152
11032 12:46:05.329650 <3>[ 19.867201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11033 12:46:05.336453 <6>[ 19.881181] videodev: Linux video capture interface: v2.00
11034 12:46:05.342569 <3>[ 19.882870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11035 12:46:05.353282 [[0;32m OK [<3>[ 19.912220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11036 12:46:05.362809 0m] Reached targ<3>[ 19.915815] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11037 12:46:05.369341 <3>[ 19.920583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11038 12:46:05.379219 et [0;1;39mSyst<6>[ 19.931178] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11039 12:46:05.389252 em Time Synchron<3>[ 19.936577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11040 12:46:05.392493 ized[0m.
11041 12:46:05.399229 <6>[ 19.953314] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11042 12:46:05.408800 <3>[ 19.957748] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11043 12:46:05.415632 <6>[ 19.969735] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11044 12:46:05.422152 <3>[ 19.975549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11045 12:46:05.431858 <3>[ 19.982151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11046 12:46:05.438749 <6>[ 19.982788] pci_bus 0000:00: root bus resource [bus 00-ff]
11047 12:46:05.445342 <6>[ 19.987796] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11048 12:46:05.451839 <3>[ 20.001966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11049 12:46:05.458795 <6>[ 20.005283] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11050 12:46:05.468633 <3>[ 20.011676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11051 12:46:05.478427 <6>[ 20.019732] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11052 12:46:05.485174 <6>[ 20.020097] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11053 12:46:05.491586 <4>[ 20.022410] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11054 12:46:05.501635 <4>[ 20.022423] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11055 12:46:05.508314 <3>[ 20.026924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11056 12:46:05.515053 <3>[ 20.028386] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11057 12:46:05.524854 <6>[ 20.035062] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11058 12:46:05.527995 <6>[ 20.035170] pci 0000:00:00.0: supports D1 D2
11059 12:46:05.534799 <3>[ 20.045114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11060 12:46:05.541535 <6>[ 20.051258] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11061 12:46:05.551940 <3>[ 20.060276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11062 12:46:05.558188 <4>[ 20.069430] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11063 12:46:05.564917 <4>[ 20.069430] Fallback method does not support PEC.
11064 12:46:05.568275 <6>[ 20.071681] r8152 2-1.3:1.0 eth0: v1.12.13
11065 12:46:05.577974 <6>[ 20.073174] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11066 12:46:05.584944 <6>[ 20.073311] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11067 12:46:05.591123 <6>[ 20.073343] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11068 12:46:05.598268 <6>[ 20.073364] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11069 12:46:05.604535 <6>[ 20.073381] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11070 12:46:05.611295 <6>[ 20.073502] pci 0000:01:00.0: supports D1 D2
11071 12:46:05.618104 <6>[ 20.073506] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11072 12:46:05.624491 <3>[ 20.076444] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11073 12:46:05.634837 <3>[ 20.076455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11074 12:46:05.640912 <3>[ 20.076461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11075 12:46:05.647784 <3>[ 20.076505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11076 12:46:05.655072 <6>[ 20.083557] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11077 12:46:05.665037 <3>[ 20.109445] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11078 12:46:05.675075 <6>[ 20.110024] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11079 12:46:05.678725 <3>[ 20.131689] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11080 12:46:05.688495 <6>[ 20.135998] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11081 12:46:05.694803 <6>[ 20.136012] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11082 12:46:05.702042 <3>[ 20.144803] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
11083 12:46:05.709010 <6>[ 20.150527] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11084 12:46:05.719225 <6>[ 20.158176] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11085 12:46:05.729611 <6>[ 20.165478] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11086 12:46:05.732771 <6>[ 20.201614] Bluetooth: Core ver 2.22
11087 12:46:05.739499 <6>[ 20.201669] usbcore: registered new interface driver cdc_ether
11088 12:46:05.742451 <6>[ 20.208666] pci 0000:00:00.0: PCI bridge to [bus 01]
11089 12:46:05.749345 <6>[ 20.209040] usbcore: registered new interface driver r8153_ecm
11090 12:46:05.755639 <6>[ 20.216836] NET: Registered PF_BLUETOOTH protocol family
11091 12:46:05.762324 <6>[ 20.223645] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11092 12:46:05.769231 <6>[ 20.225399] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
11093 12:46:05.776614 <3>[ 20.228918] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11094 12:46:05.786104 <3>[ 20.229523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11095 12:46:05.792667 <6>[ 20.232494] Bluetooth: HCI device and connection manager initialized
11096 12:46:05.799457 <6>[ 20.233773] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11097 12:46:05.812917 <6>[ 20.235103] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11098 12:46:05.819480 <6>[ 20.235256] usbcore: registered new interface driver uvcvideo
11099 12:46:05.826336 <6>[ 20.240859] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11100 12:46:05.829632 <6>[ 20.246981] Bluetooth: HCI socket layer initialized
11101 12:46:05.836757 <6>[ 20.255892] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11102 12:46:05.843343 <3>[ 20.257517] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11103 12:46:05.853240 <3>[ 20.258321] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11104 12:46:05.856493 <6>[ 20.262981] Bluetooth: L2CAP socket layer initialized
11105 12:46:05.862975 <6>[ 20.263010] Bluetooth: SCO socket layer initialized
11106 12:46:05.869499 <6>[ 20.263723] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11107 12:46:05.873074 <6>[ 20.267663] remoteproc remoteproc0: powering up scp
11108 12:46:05.883083 <4>[ 20.267713] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11109 12:46:05.889869 <3>[ 20.267722] remoteproc remoteproc0: request_firmware failed: -2
11110 12:46:05.899469 <3>[ 20.267725] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11111 12:46:05.902639 <6>[ 20.270069] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11112 12:46:05.912609 <3>[ 20.272260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11113 12:46:05.922689 <3>[ 20.295171] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11114 12:46:05.929515 <5>[ 20.319901] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11115 12:46:05.936201 <6>[ 20.330674] usbcore: registered new interface driver btusb
11116 12:46:05.946412 <4>[ 20.331219] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11117 12:46:05.953481 <3>[ 20.331231] Bluetooth: hci0: Failed to load firmware file (-2)
11118 12:46:05.956425 <3>[ 20.331235] Bluetooth: hci0: Failed to set up firmware (-2)
11119 12:46:05.966620 <4>[ 20.331238] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11120 12:46:05.976944 <3>[ 20.344823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11121 12:46:05.983575 <5>[ 20.349000] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11122 12:46:05.993698 <3>[ 20.374719] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11123 12:46:05.999928 <4>[ 20.379830] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11124 12:46:06.010490 <3>[ 20.409797] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11125 12:46:06.013648 <6>[ 20.412124] cfg80211: failed to load regulatory.db
11126 12:46:06.024381 <6>[ 20.484776] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11127 12:46:06.028071 <6>[ 20.589993] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11128 12:46:06.037378 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11129 12:46:06.054108 [[0;32m OK [0m] Finished [0<6>[ 20.615575] mt7921e 0000:01:00.0: ASIC revision: 79610010
11130 12:46:06.060813 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11131 12:46:06.080433 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11132 12:46:06.159201 <4>[ 20.715199] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11133 12:46:06.256187 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11134 12:46:06.280546 [[0;32m OK [0m] Reached targ<4>[ 20.834168] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11135 12:46:06.283474 et [0;1;39mSystem Initialization[0m.
11136 12:46:06.302363 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11137 12:46:06.316722 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11138 12:46:06.329938 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11139 12:46:06.349477 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11140 12:46:06.361705 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11141 12:46:06.377675 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11142 12:46:06.398638 <4>[ 20.953951] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11143 12:46:06.408787 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11144 12:46:06.449889 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11145 12:46:06.477116 Starting [0;1;39mUser Login Management[0m...
11146 12:46:06.492178 Starting [0;1;39mPermit User Sessions[0m...
11147 12:46:06.521778 Startin<4>[ 21.078412] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11148 12:46:06.528495 g [0;1;39mLoad/Save RF Kill Switch Status[0m...
11149 12:46:06.544036 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11150 12:46:06.563502 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11151 12:46:06.582892 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11152 12:46:06.628148 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11153 12:46:06.646752 <4>[ 21.202556] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11154 12:46:06.686815 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11155 12:46:06.702281 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11156 12:46:06.717916 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11157 12:46:06.733687 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11158 12:46:06.767237 <4>[ 21.322798] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11159 12:46:06.779669 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11160 12:46:06.808315 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11161 12:46:06.824116
11162 12:46:06.824686
11163 12:46:06.827627 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11164 12:46:06.828194
11165 12:46:06.830732 debian-bullseye-arm64 login: root (automatic login)
11166 12:46:06.831298
11167 12:46:06.831666
11168 12:46:06.847408 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11169 12:46:06.848005
11170 12:46:06.853668 The programs included with the Debian GNU/Linux system are free software;
11171 12:46:06.861148 the exact distribution terms for each program are described in the
11172 12:46:06.863564 individual files in /usr/share/doc/*/copyright.
11173 12:46:06.864030
11174 12:46:06.870361 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11175 12:46:06.873412 permitted by applicable law.
11176 12:46:06.874580 Matched prompt #10: / #
11178 12:46:06.875673 Setting prompt string to ['/ #']
11179 12:46:06.876155 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11181 12:46:06.877278 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11182 12:46:06.877767 start: 2.2.6 expect-shell-connection (timeout 00:02:53) [common]
11183 12:46:06.878170 Setting prompt string to ['/ #']
11184 12:46:06.878556 Forcing a shell prompt, looking for ['/ #']
11186 12:46:06.929447 / # <4>[
11187 12:46:06.930100 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11188 12:46:06.930572 Waiting using forced prompt support (timeout 00:02:30)
11189 12:46:06.931088 21.441978] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11190 12:46:06.936017
11191 12:46:06.937001 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11192 12:46:06.937537 start: 2.2.7 export-device-env (timeout 00:02:53) [common]
11193 12:46:06.938059 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11194 12:46:06.938557 end: 2.2 depthcharge-retry (duration 00:02:07) [common]
11195 12:46:06.939047 end: 2 depthcharge-action (duration 00:02:07) [common]
11196 12:46:06.939533 start: 3 lava-test-retry (timeout 00:05:00) [common]
11197 12:46:06.940015 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11198 12:46:06.940429 Using namespace: common
11200 12:46:07.041626 / # #
11201 12:46:07.042282 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11202 12:46:07.042867 <4>[ 21.561704] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11203 12:46:07.047546 #
11204 12:46:07.048429 Using /lava-10724891
11206 12:46:07.149616 / # export SHELL=/bin/sh
11207 12:46:07.150397 export SHELL=/bin/sh<4>[ 21.682035] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11208 12:46:07.155839
11210 12:46:07.257502 / # . /lava-10724891/environment
11211 12:46:07.258309 . /lava-10724891/environment<4>[ 21.801343] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11212 12:46:07.263655
11214 12:46:07.365529 / # /lava-10724891/bin/lava-test-runner /lava-10724891/0
11215 12:46:07.366169 Test shell timeout: 10s (minimum of the action and connection timeout)
11216 12:46:07.367753 /lava-10724891/bin/lava-test-runner /lava-10724891/0<3>[ 21.915289] mt7921e 0000:01:00.0: hardware init failed
11217 12:46:07.371775
11218 12:46:07.413438 + export TESTRUN_ID=0_sleep
11219 12:46:07.414020 + cd /lava-10724891/0/tests/0_sleep
11220 12:46:07.414400 + cat uuid
11221 12:46:07.414749 + UUID=10724891_1.5.2.3.1
11222 12:46:07.415151 + set +x
11223 12:46:07.415487 <LAVA_SIGNAL_STARTRUN 0_sleep 10724891_1.5.2.3.1>
11224 12:46:07.415814 + ./config/lava/sleep/sleep.sh mem freeze
11225 12:46:07.416437 Received signal: <STARTRUN> 0_sleep 10724891_1.5.2.3.1
11226 12:46:07.416813 Starting test lava.0_sleep (10724891_1.5.2.3.1)
11227 12:46:07.417275 Skipping test definition patterns.
11228 12:46:07.417859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11229 12:46:07.418319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11230 12:46:07.418949 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11232 12:46:07.420023 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11234 12:46:07.421285 rtcwake: assuming RTC uses UTC ...
11235 12:46:07.431113 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:08<6>[ 21.993555] PM: suspend entry (deep)
11236 12:46:07.431690 2023
11237 12:46:07.437711 <6>[ 21.998728] Filesystems sync: 0.000 seconds
11238 12:46:07.444571 <6>[ 22.006394] Freezing user space processes
11239 12:46:07.450922 <6>[ 22.012278] Freezing user space processes completed (elapsed 0.001 seconds)
11240 12:46:07.454247 <6>[ 22.019548] OOM killer disabled.
11241 12:46:07.460847 <6>[ 22.023029] Freezing remaining freezable tasks
11242 12:46:07.471316 <6>[ 22.029051] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11243 12:46:07.477576 <6>[ 22.036729] printk: Suspending console(s) (use no_console_suspend to debug)
11244 12:46:10.609092 <3>[ 22.045019] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11245 12:46:10.615720 <3>[ 22.045051] elants_i2c 4-0010: PM: failed to suspend async: error -16
11246 12:46:10.622645 <3>[ 25.163677] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11247 12:46:10.631981 <3>[ 25.163706] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11248 12:46:10.638482 <3>[ 25.163736] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11249 12:46:10.644836 <3>[ 25.163761] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11250 12:46:10.655063 <3>[ 25.164023] PM: Some devices failed to suspend, or early wake event detected
11251 12:46:10.658057 <6>[ 25.221714] OOM killer enabled.
11252 12:46:10.661666 <6>[ 25.225112] Restarting tasks ... done.
11253 12:46:10.667983 <5>[ 25.230337] random: crng reseeded on system resumption
11254 12:46:10.671590 <6>[ 25.236774] PM: suspend exit
11255 12:46:10.674644 rtcwake: write error
11256 12:46:10.682374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11257 12:46:10.683047 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11259 12:46:10.685448 rtcwake: assuming RTC uses UTC ...
11260 12:46:10.692541 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:11 2023
11261 12:46:10.705351 <6>[ 25.267994] PM: suspend entry (deep)
11262 12:46:10.708549 <6>[ 25.271912] Filesystems sync: 0.000 seconds
11263 12:46:10.715286 <6>[ 25.277030] Freezing user space processes
11264 12:46:10.721588 <6>[ 25.283073] Freezing user space processes completed (elapsed 0.001 seconds)
11265 12:46:10.725083 <6>[ 25.290314] OOM killer disabled.
11266 12:46:10.731931 <6>[ 25.293802] Freezing remaining freezable tasks
11267 12:46:10.737985 <6>[ 25.299435] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11268 12:46:10.748261 <6>[ 25.307090] printk: Suspending console(s) (use no_console_suspend to debug)
11269 12:46:13.936157 <3>[ 25.315152] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11270 12:46:13.942871 <3>[ 25.315184] elants_i2c 4-0010: PM: failed to suspend async: error -16
11271 12:46:13.950343 <3>[ 28.491640] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11272 12:46:13.959164 <3>[ 28.491663] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11273 12:46:13.966289 <3>[ 28.491689] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11274 12:46:13.972762 <3>[ 28.491712] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11275 12:46:13.982382 <3>[ 28.491917] PM: Some devices failed to suspend, or early wake event detected
11276 12:46:13.985937 <6>[ 28.549874] OOM killer enabled.
11277 12:46:13.988896 <6>[ 28.553287] Restarting tasks ... done.
11278 12:46:13.995871 <5>[ 28.558473] random: crng reseeded on system resumption
11279 12:46:13.998974 <6>[ 28.565856] PM: suspend exit
11280 12:46:14.002504 rtcwake: write error
11281 12:46:14.010127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11282 12:46:14.010386 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11284 12:46:14.013415 rtcwake: assuming RTC uses UTC ...
11285 12:46:14.019981 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:15 2023
11286 12:46:14.033083 <6>[ 28.596717] PM: suspend entry (deep)
11287 12:46:14.036174 <6>[ 28.600641] Filesystems sync: 0.000 seconds
11288 12:46:14.039558 <6>[ 28.605674] Freezing user space processes
11289 12:46:14.051274 <6>[ 28.611491] Freezing user space processes completed (elapsed 0.001 seconds)
11290 12:46:14.054408 <6>[ 28.618718] OOM killer disabled.
11291 12:46:14.057783 <6>[ 28.622201] Freezing remaining freezable tasks
11292 12:46:14.067680 <6>[ 28.628090] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11293 12:46:14.074330 <6>[ 28.635749] printk: Suspending console(s) (use no_console_suspend to debug)
11294 12:46:17.264309 <3>[ 28.643748] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11295 12:46:17.270482 <3>[ 28.643781] elants_i2c 4-0010: PM: failed to suspend async: error -16
11296 12:46:17.277596 <3>[ 31.819670] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11297 12:46:17.287175 <3>[ 31.819702] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11298 12:46:17.293778 <3>[ 31.819733] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11299 12:46:17.300390 <3>[ 31.819756] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11300 12:46:17.310424 <3>[ 31.820013] PM: Some devices failed to suspend, or early wake event detected
11301 12:46:17.313427 <6>[ 31.877683] OOM killer enabled.
11302 12:46:17.317548 <6>[ 31.881081] Restarting tasks ... done.
11303 12:46:17.323614 <5>[ 31.886402] random: crng reseeded on system resumption
11304 12:46:17.326761 <6>[ 31.892867] PM: suspend exit
11305 12:46:17.330137 rtcwake: write error
11306 12:46:17.337490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11307 12:46:17.338331 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11309 12:46:17.340789 rtcwake: assuming RTC uses UTC ...
11310 12:46:17.347545 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:18 2023
11311 12:46:17.360865 <6>[ 31.924217] PM: suspend entry (deep)
11312 12:46:17.364385 <6>[ 31.928119] Filesystems sync: 0.000 seconds
11313 12:46:17.367224 <6>[ 31.933117] Freezing user space processes
11314 12:46:17.379117 <6>[ 31.939035] Freezing user space processes completed (elapsed 0.001 seconds)
11315 12:46:17.381860 <6>[ 31.946365] OOM killer disabled.
11316 12:46:17.385258 <6>[ 31.949865] Freezing remaining freezable tasks
11317 12:46:17.395378 <6>[ 31.955423] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11318 12:46:17.401701 <6>[ 31.963075] printk: Suspending console(s) (use no_console_suspend to debug)
11319 12:46:20.592398 <3>[ 31.971025] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11320 12:46:20.599047 <3>[ 31.971053] elants_i2c 4-0010: PM: failed to suspend async: error -16
11321 12:46:20.605470 <3>[ 35.147770] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11322 12:46:20.615365 <3>[ 35.147857] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11323 12:46:20.622096 <3>[ 35.147945] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11324 12:46:20.628240 <3>[ 35.147989] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11325 12:46:20.638531 <3>[ 35.148272] PM: Some devices failed to suspend, or early wake event detected
11326 12:46:20.641650 <6>[ 35.206012] OOM killer enabled.
11327 12:46:20.645204 <6>[ 35.209410] Restarting tasks ... done.
11328 12:46:20.651685 <5>[ 35.214665] random: crng reseeded on system resumption
11329 12:46:20.655242 <6>[ 35.221106] PM: suspend exit
11330 12:46:20.658496 rtcwake: write error
11331 12:46:20.665370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11332 12:46:20.666228 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11334 12:46:20.668415 rtcwake: assuming RTC uses UTC ...
11335 12:46:20.674945 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:21 2023
11336 12:46:20.688792 <6>[ 35.251896] PM: suspend entry (deep)
11337 12:46:20.691230 <6>[ 35.255790] Filesystems sync: 0.000 seconds
11338 12:46:20.694710 <6>[ 35.260759] Freezing user space processes
11339 12:46:20.706213 <6>[ 35.266539] Freezing user space processes completed (elapsed 0.001 seconds)
11340 12:46:20.709195 <6>[ 35.273879] OOM killer disabled.
11341 12:46:20.712232 <6>[ 35.277364] Freezing remaining freezable tasks
11342 12:46:20.722917 <6>[ 35.283400] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11343 12:46:20.729141 <6>[ 35.291065] printk: Suspending console(s) (use no_console_suspend to debug)
11344 12:46:23.921637 <3>[ 35.299056] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11345 12:46:23.928396 <3>[ 35.299091] elants_i2c 4-0010: PM: failed to suspend async: error -16
11346 12:46:23.935138 <3>[ 38.475711] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11347 12:46:23.944922 <3>[ 38.475740] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11348 12:46:23.951174 <3>[ 38.475775] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11349 12:46:23.957984 <3>[ 38.475799] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11350 12:46:23.968045 <3>[ 38.476187] PM: Some devices failed to suspend, or early wake event detected
11351 12:46:23.971074 <6>[ 38.536214] OOM killer enabled.
11352 12:46:23.974265 <6>[ 38.539612] Restarting tasks ... done.
11353 12:46:23.981494 <5>[ 38.544936] random: crng reseeded on system resumption
11354 12:46:23.984363 <6>[ 38.551280] PM: suspend exit
11355 12:46:23.987544 rtcwake: write error
11356 12:46:23.994369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11357 12:46:23.995205 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11359 12:46:23.997558 rtcwake: assuming RTC uses UTC ...
11360 12:46:24.004930 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:25 2023
11361 12:46:24.017357 <6>[ 38.581801] PM: suspend entry (deep)
11362 12:46:24.020799 <6>[ 38.585701] Filesystems sync: 0.000 seconds
11363 12:46:24.023959 <6>[ 38.590777] Freezing user space processes
11364 12:46:24.035825 <6>[ 38.596817] Freezing user space processes completed (elapsed 0.001 seconds)
11365 12:46:24.038843 <6>[ 38.604129] OOM killer disabled.
11366 12:46:24.042001 <6>[ 38.607622] Freezing remaining freezable tasks
11367 12:46:24.053164 <6>[ 38.613661] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11368 12:46:24.059244 <6>[ 38.621336] printk: Suspending console(s) (use no_console_suspend to debug)
11369 12:46:27.247220 <3>[ 38.629383] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11370 12:46:27.253676 <3>[ 38.629413] elants_i2c 4-0010: PM: failed to suspend async: error -16
11371 12:46:27.259874 <3>[ 41.803650] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11372 12:46:27.270063 <3>[ 41.803674] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11373 12:46:27.276840 <3>[ 41.803700] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11374 12:46:27.283296 <3>[ 41.803723] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11375 12:46:27.293022 <3>[ 41.804045] PM: Some devices failed to suspend, or early wake event detected
11376 12:46:27.296645 <6>[ 41.861786] OOM killer enabled.
11377 12:46:27.299863 <6>[ 41.865183] Restarting tasks ... done.
11378 12:46:27.306386 <5>[ 41.870530] random: crng reseeded on system resumption
11379 12:46:27.309488 <6>[ 41.877515] PM: suspend exit
11380 12:46:27.312468 rtcwake: write error
11381 12:46:27.320945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11382 12:46:27.321789 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11384 12:46:27.323866 rtcwake: assuming RTC uses UTC ...
11385 12:46:27.330706 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:28 2023
11386 12:46:27.344137 <6>[ 41.908701] PM: suspend entry (deep)
11387 12:46:27.347364 <6>[ 41.912608] Filesystems sync: 0.000 seconds
11388 12:46:27.354041 <6>[ 41.917685] Freezing user space processes
11389 12:46:27.359991 <6>[ 41.923465] Freezing user space processes completed (elapsed 0.001 seconds)
11390 12:46:27.363413 <6>[ 41.930766] OOM killer disabled.
11391 12:46:27.370349 <6>[ 41.934257] Freezing remaining freezable tasks
11392 12:46:27.376839 <6>[ 41.940137] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11393 12:46:27.386568 <6>[ 41.947792] printk: Suspending console(s) (use no_console_suspend to debug)
11394 12:46:30.574632 <3>[ 41.955881] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11395 12:46:30.581092 <3>[ 41.955912] elants_i2c 4-0010: PM: failed to suspend async: error -16
11396 12:46:30.587610 <3>[ 45.131696] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11397 12:46:30.597701 <3>[ 45.131751] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11398 12:46:30.604315 <3>[ 45.131821] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11399 12:46:30.610588 <3>[ 45.131906] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11400 12:46:30.620612 <3>[ 45.132343] PM: Some devices failed to suspend, or early wake event detected
11401 12:46:30.623929 <6>[ 45.190175] OOM killer enabled.
11402 12:46:30.627313 <6>[ 45.193573] Restarting tasks ... done.
11403 12:46:30.633738 <5>[ 45.199085] random: crng reseeded on system resumption
11404 12:46:30.637606 <6>[ 45.206559] PM: suspend exit
11405 12:46:30.640906 rtcwake: write error
11406 12:46:30.648938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11407 12:46:30.649249 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11409 12:46:30.652146 rtcwake: assuming RTC uses UTC ...
11410 12:46:30.658569 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:31 2023
11411 12:46:30.671548 <6>[ 45.237270] PM: suspend entry (deep)
11412 12:46:30.674804 <6>[ 45.241193] Filesystems sync: 0.000 seconds
11413 12:46:30.681566 <6>[ 45.246381] Freezing user space processes
11414 12:46:30.688147 <6>[ 45.252309] Freezing user space processes completed (elapsed 0.001 seconds)
11415 12:46:30.691275 <6>[ 45.259536] OOM killer disabled.
11416 12:46:30.698072 <6>[ 45.263014] Freezing remaining freezable tasks
11417 12:46:30.704457 <6>[ 45.268984] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11418 12:46:30.714328 <6>[ 45.276646] printk: Suspending console(s) (use no_console_suspend to debug)
11419 12:46:33.901969 <3>[ 45.284824] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11420 12:46:33.908540 <3>[ 45.284861] elants_i2c 4-0010: PM: failed to suspend async: error -16
11421 12:46:33.908637 <6>[ 48.203767] vpu: disabling
11422 12:46:33.912020 <6>[ 48.203879] vproc2: disabling
11423 12:46:33.915214 <6>[ 48.203921] vproc1: disabling
11424 12:46:33.918380 <6>[ 48.203962] vaud18: disabling
11425 12:46:33.925108 <6>[ 48.204149] vsram_others: disabling
11426 12:46:33.925193 <6>[ 48.204278] va09: disabling
11427 12:46:33.928762 <6>[ 48.204333] vsram_md: disabling
11428 12:46:33.931820 <6>[ 48.204429] Vgpu: disabling
11429 12:46:33.938316 <3>[ 48.459681] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11430 12:46:33.948388 <3>[ 48.459711] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11431 12:46:33.958264 <3>[ 48.459741] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11432 12:46:33.964921 <3>[ 48.459764] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11433 12:46:33.971461 <3>[ 48.460050] PM: Some devices failed to suspend, or early wake event detected
11434 12:46:33.974959 <6>[ 48.543937] OOM killer enabled.
11435 12:46:33.982427 <6>[ 48.547329] Restarting tasks ... done.
11436 12:46:33.985971 <5>[ 48.552659] random: crng reseeded on system resumption
11437 12:46:33.990909 <6>[ 48.560345] PM: suspend exit
11438 12:46:33.994659 rtcwake: write error
11439 12:46:34.002725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11440 12:46:34.003019 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11442 12:46:34.005708 rtcwake: assuming RTC uses UTC ...
11443 12:46:34.012317 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:35 2023
11444 12:46:34.025735 <6>[ 48.591443] PM: suspend entry (deep)
11445 12:46:34.028732 <6>[ 48.595315] Filesystems sync: 0.000 seconds
11446 12:46:34.035216 <6>[ 48.600476] Freezing user space processes
11447 12:46:34.041817 <6>[ 48.606481] Freezing user space processes completed (elapsed 0.001 seconds)
11448 12:46:34.045380 <6>[ 48.613706] OOM killer disabled.
11449 12:46:34.052248 <6>[ 48.617189] Freezing remaining freezable tasks
11450 12:46:34.058434 <6>[ 48.623053] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11451 12:46:34.068207 <6>[ 48.630711] printk: Suspending console(s) (use no_console_suspend to debug)
11452 12:46:37.229372 <3>[ 48.638762] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11453 12:46:37.236021 <3>[ 48.638790] elants_i2c 4-0010: PM: failed to suspend async: error -16
11454 12:46:37.242786 <3>[ 51.787669] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11455 12:46:37.252460 <3>[ 51.787695] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11456 12:46:37.259132 <3>[ 51.787726] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11457 12:46:37.265661 <3>[ 51.787747] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11458 12:46:37.275334 <3>[ 51.788184] PM: Some devices failed to suspend, or early wake event detected
11459 12:46:37.278665 <6>[ 51.846050] OOM killer enabled.
11460 12:46:37.282113 <6>[ 51.849448] Restarting tasks ... done.
11461 12:46:37.288460 <5>[ 51.854967] random: crng reseeded on system resumption
11462 12:46:37.291973 <6>[ 51.861901] PM: suspend exit
11463 12:46:37.295536 rtcwake: write error
11464 12:46:37.303506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11465 12:46:37.303758 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11467 12:46:37.306929 rtcwake: assuming RTC uses UTC ...
11468 12:46:37.313493 rtcwake: wakeup from "mem" using rtc0 at Wed Jun 14 12:46:38 2023
11469 12:46:37.326408 <6>[ 51.892905] PM: suspend entry (deep)
11470 12:46:37.329824 <6>[ 51.896805] Filesystems sync: 0.000 seconds
11471 12:46:37.336571 <6>[ 51.901990] Freezing user space processes
11472 12:46:37.342921 <6>[ 51.907988] Freezing user space processes completed (elapsed 0.001 seconds)
11473 12:46:37.346333 <6>[ 51.915229] OOM killer disabled.
11474 12:46:37.352747 <6>[ 51.918715] Freezing remaining freezable tasks
11475 12:46:37.362790 <6>[ 51.924858] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11476 12:46:37.369287 <6>[ 51.932532] printk: Suspending console(s) (use no_console_suspend to debug)
11477 12:46:40.557074 <3>[ 51.940757] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11478 12:46:40.563525 <3>[ 51.940785] elants_i2c 4-0010: PM: failed to suspend async: error -16
11479 12:46:40.570376 <3>[ 55.115666] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11480 12:46:40.580195 <3>[ 55.115691] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11481 12:46:40.586881 <3>[ 55.115725] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11482 12:46:40.593493 <3>[ 55.115745] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11483 12:46:40.603515 <3>[ 55.116143] PM: Some devices failed to suspend, or early wake event detected
11484 12:46:40.606603 <6>[ 55.173992] OOM killer enabled.
11485 12:46:40.610016 <6>[ 55.177390] Restarting tasks ... done.
11486 12:46:40.616358 <5>[ 55.182958] random: crng reseeded on system resumption
11487 12:46:40.620000 <6>[ 55.189440] PM: suspend exit
11488 12:46:40.622863 rtcwake: write error
11489 12:46:40.630605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11490 12:46:40.630866 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11492 12:46:40.633931 rtcwake: assuming RTC uses UTC ...
11493 12:46:40.640131 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:46:41 2023
11494 12:46:40.654631 <6>[ 55.221395] PM: suspend entry (s2idle)
11495 12:46:40.657699 <6>[ 55.225481] Filesystems sync: 0.000 seconds
11496 12:46:40.664081 <6>[ 55.230655] Freezing user space processes
11497 12:46:40.671044 <6>[ 55.236729] Freezing user space processes completed (elapsed 0.001 seconds)
11498 12:46:40.674058 <6>[ 55.244005] OOM killer disabled.
11499 12:46:40.681003 <6>[ 55.247491] Freezing remaining freezable tasks
11500 12:46:40.690670 <6>[ 55.253468] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11501 12:46:40.697266 <6>[ 55.261138] printk: Suspending console(s) (use no_console_suspend to debug)
11502 12:46:43.884676 <3>[ 55.269377] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11503 12:46:43.890857 <3>[ 55.269405] elants_i2c 4-0010: PM: failed to suspend async: error -16
11504 12:46:43.897517 <3>[ 58.443696] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11505 12:46:43.907670 <3>[ 58.443721] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11506 12:46:43.914021 <3>[ 58.443755] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11507 12:46:43.920519 <3>[ 58.443776] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11508 12:46:43.930557 <3>[ 58.444113] PM: Some devices failed to suspend, or early wake event detected
11509 12:46:43.933569 <6>[ 58.501687] OOM killer enabled.
11510 12:46:43.937157 <6>[ 58.505083] Restarting tasks ... done.
11511 12:46:43.943742 <5>[ 58.510384] random: crng reseeded on system resumption
11512 12:46:43.946750 <6>[ 58.516856] PM: suspend exit
11513 12:46:43.949975 rtcwake: write error
11514 12:46:43.957785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11515 12:46:43.958063 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11517 12:46:43.961333 rtcwake: assuming RTC uses UTC ...
11518 12:46:43.967880 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:46:45 2023
11519 12:46:43.980613 <6>[ 58.547979] PM: suspend entry (s2idle)
11520 12:46:43.984042 <6>[ 58.552130] Filesystems sync: 0.000 seconds
11521 12:46:43.990782 <6>[ 58.557235] Freezing user space processes
11522 12:46:43.996933 <6>[ 58.563260] Freezing user space processes completed (elapsed 0.001 seconds)
11523 12:46:44.000374 <6>[ 58.570590] OOM killer disabled.
11524 12:46:44.007030 <6>[ 58.574076] Freezing remaining freezable tasks
11525 12:46:44.016917 <6>[ 58.579976] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11526 12:46:44.023279 <6>[ 58.587635] printk: Suspending console(s) (use no_console_suspend to debug)
11527 12:46:47.212214 <3>[ 58.595770] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11528 12:46:47.218799 <3>[ 58.595800] elants_i2c 4-0010: PM: failed to suspend async: error -16
11529 12:46:47.225480 <3>[ 61.771642] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11530 12:46:47.235700 <3>[ 61.771665] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11531 12:46:47.241842 <3>[ 61.771691] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11532 12:46:47.248535 <3>[ 61.771713] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11533 12:46:47.258239 <3>[ 61.772117] PM: Some devices failed to suspend, or early wake event detected
11534 12:46:47.261762 <6>[ 61.829830] OOM killer enabled.
11535 12:46:47.264952 <6>[ 61.833227] Restarting tasks ... done.
11536 12:46:47.271632 <5>[ 61.838550] random: crng reseeded on system resumption
11537 12:46:47.275102 <6>[ 61.846081] PM: suspend exit
11538 12:46:47.278437 rtcwake: write error
11539 12:46:47.286445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11540 12:46:47.286705 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11542 12:46:47.290040 rtcwake: assuming RTC uses UTC ...
11543 12:46:47.296409 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:46:48 2023
11544 12:46:47.309663 <6>[ 61.877397] PM: suspend entry (s2idle)
11545 12:46:47.313140 <6>[ 61.881470] Filesystems sync: 0.000 seconds
11546 12:46:47.319775 <6>[ 61.886663] Freezing user space processes
11547 12:46:47.326335 <6>[ 61.892356] Freezing user space processes completed (elapsed 0.001 seconds)
11548 12:46:47.329553 <6>[ 61.899653] OOM killer disabled.
11549 12:46:47.336356 <6>[ 61.903132] Freezing remaining freezable tasks
11550 12:46:47.343146 <6>[ 61.909164] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11551 12:46:47.352575 <6>[ 61.916838] printk: Suspending console(s) (use no_console_suspend to debug)
11552 12:46:50.540098 <3>[ 61.924943] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11553 12:46:50.546255 <3>[ 61.924974] elants_i2c 4-0010: PM: failed to suspend async: error -16
11554 12:46:50.553080 <3>[ 65.099741] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11555 12:46:50.562785 <3>[ 65.099776] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11556 12:46:50.569728 <3>[ 65.099810] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11557 12:46:50.576169 <3>[ 65.099835] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11558 12:46:50.585915 <3>[ 65.100257] PM: Some devices failed to suspend, or early wake event detected
11559 12:46:50.589410 <6>[ 65.157973] OOM killer enabled.
11560 12:46:50.592620 <6>[ 65.161372] Restarting tasks ... done.
11561 12:46:50.598911 <5>[ 65.166293] random: crng reseeded on system resumption
11562 12:46:50.602389 <6>[ 65.172956] PM: suspend exit
11563 12:46:50.605516 rtcwake: write error
11564 12:46:50.612860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11565 12:46:50.613121 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11567 12:46:50.615961 rtcwake: assuming RTC uses UTC ...
11568 12:46:50.622491 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:46:51 2023
11569 12:46:50.635463 <6>[ 65.203649] PM: suspend entry (s2idle)
11570 12:46:50.639374 <6>[ 65.207718] Filesystems sync: 0.000 seconds
11571 12:46:50.645592 <6>[ 65.212829] Freezing user space processes
11572 12:46:50.651904 <6>[ 65.218510] Freezing user space processes completed (elapsed 0.001 seconds)
11573 12:46:50.655740 <6>[ 65.225758] OOM killer disabled.
11574 12:46:50.662108 <6>[ 65.229241] Freezing remaining freezable tasks
11575 12:46:50.668563 <6>[ 65.235249] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11576 12:46:50.678228 <6>[ 65.242933] printk: Suspending console(s) (use no_console_suspend to debug)
11577 12:46:53.869178 <3>[ 65.250907] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11578 12:46:53.875520 <3>[ 65.250959] elants_i2c 4-0010: PM: failed to suspend async: error -16
11579 12:46:53.882053 <3>[ 68.427772] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11580 12:46:53.891977 <3>[ 68.427817] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11581 12:46:53.898546 <3>[ 68.427850] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11582 12:46:53.905392 <3>[ 68.427873] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11583 12:46:53.915490 <3>[ 68.428120] PM: Some devices failed to suspend, or early wake event detected
11584 12:46:53.918629 <6>[ 68.487298] OOM killer enabled.
11585 12:46:53.921638 <6>[ 68.490693] Restarting tasks ... done.
11586 12:46:53.928308 <5>[ 68.495516] random: crng reseeded on system resumption
11587 12:46:53.931531 <6>[ 68.502028] PM: suspend exit
11588 12:46:53.934785 rtcwake: write error
11589 12:46:53.942474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11590 12:46:53.942734 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11592 12:46:53.945003 rtcwake: assuming RTC uses UTC ...
11593 12:46:53.951854 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:46:55 2023
11594 12:46:53.964484 <6>[ 68.533021] PM: suspend entry (s2idle)
11595 12:46:53.967868 <6>[ 68.537080] Filesystems sync: 0.000 seconds
11596 12:46:53.974615 <6>[ 68.542181] Freezing user space processes
11597 12:46:53.981199 <6>[ 68.547455] Freezing user space processes completed (elapsed 0.000 seconds)
11598 12:46:53.984513 <6>[ 68.554676] OOM killer disabled.
11599 12:46:53.991020 <6>[ 68.558159] Freezing remaining freezable tasks
11600 12:46:53.997733 <6>[ 68.564017] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11601 12:46:54.004939 <6>[ 68.571679] printk: Suspending console(s) (use no_console_suspend to debug)
11602 12:46:57.195481 <3>[ 68.579802] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11603 12:46:57.201776 <3>[ 68.579826] elants_i2c 4-0010: PM: failed to suspend async: error -16
11604 12:46:57.208286 <3>[ 71.755882] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11605 12:46:57.218381 <3>[ 71.756007] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11606 12:46:57.225173 <3>[ 71.756052] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11607 12:46:57.231756 <3>[ 71.756072] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11608 12:46:57.241727 <3>[ 71.756290] PM: Some devices failed to suspend, or early wake event detected
11609 12:46:57.244937 <6>[ 71.814207] OOM killer enabled.
11610 12:46:57.248074 <6>[ 71.817618] Restarting tasks ... done.
11611 12:46:57.254654 <5>[ 71.822407] random: crng reseeded on system resumption
11612 12:46:57.258345 <6>[ 71.828876] PM: suspend exit
11613 12:46:57.261412 rtcwake: write error
11614 12:46:57.268196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11615 12:46:57.268456 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11617 12:46:57.271524 rtcwake: assuming RTC uses UTC ...
11618 12:46:57.278178 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:46:58 2023
11619 12:46:57.291218 <6>[ 71.859781] PM: suspend entry (s2idle)
11620 12:46:57.294189 <6>[ 71.863845] Filesystems sync: 0.000 seconds
11621 12:46:57.300791 <6>[ 71.869021] Freezing user space processes
11622 12:46:57.307608 <6>[ 71.874720] Freezing user space processes completed (elapsed 0.001 seconds)
11623 12:46:57.310536 <6>[ 71.881953] OOM killer disabled.
11624 12:46:57.317703 <6>[ 71.885438] Freezing remaining freezable tasks
11625 12:46:57.324123 <6>[ 71.891362] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11626 12:46:57.333505 <6>[ 71.899026] printk: Suspending console(s) (use no_console_suspend to debug)
11627 12:47:00.523384 <3>[ 71.907166] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11628 12:47:00.529861 <3>[ 71.907195] elants_i2c 4-0010: PM: failed to suspend async: error -16
11629 12:47:00.536324 <3>[ 75.083690] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11630 12:47:00.546698 <3>[ 75.083717] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11631 12:47:00.552855 <3>[ 75.083755] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11632 12:47:00.559855 <3>[ 75.083788] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11633 12:47:00.569618 <3>[ 75.084183] PM: Some devices failed to suspend, or early wake event detected
11634 12:47:00.572928 <6>[ 75.142148] OOM killer enabled.
11635 12:47:00.576118 <6>[ 75.145570] Restarting tasks ... done.
11636 12:47:00.582850 <5>[ 75.150367] random: crng reseeded on system resumption
11637 12:47:00.586136 <6>[ 75.157351] PM: suspend exit
11638 12:47:00.589121 rtcwake: write error
11639 12:47:00.596667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11640 12:47:00.597514 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11642 12:47:00.600142 rtcwake: assuming RTC uses UTC ...
11643 12:47:00.607036 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:47:01 2023
11644 12:47:00.619365 <6>[ 75.188312] PM: suspend entry (s2idle)
11645 12:47:00.622899 <6>[ 75.192464] Filesystems sync: 0.000 seconds
11646 12:47:00.629426 <6>[ 75.197637] Freezing user space processes
11647 12:47:00.635818 <6>[ 75.203211] Freezing user space processes completed (elapsed 0.001 seconds)
11648 12:47:00.639155 <6>[ 75.210442] OOM killer disabled.
11649 12:47:00.646316 <6>[ 75.213925] Freezing remaining freezable tasks
11650 12:47:00.652279 <6>[ 75.219422] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11651 12:47:00.659301 <6>[ 75.227076] printk: Suspending console(s) (use no_console_suspend to debug)
11652 12:47:03.850558 <3>[ 75.235042] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11653 12:47:03.857509 <3>[ 75.235083] elants_i2c 4-0010: PM: failed to suspend async: error -16
11654 12:47:03.864184 <3>[ 78.411676] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11655 12:47:03.874099 <3>[ 78.411700] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11656 12:47:03.880927 <3>[ 78.411726] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11657 12:47:03.887334 <3>[ 78.411748] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11658 12:47:03.897346 <3>[ 78.412069] PM: Some devices failed to suspend, or early wake event detected
11659 12:47:03.900393 <6>[ 78.469753] OOM killer enabled.
11660 12:47:03.903423 <6>[ 78.473151] Restarting tasks ... done.
11661 12:47:03.910164 <5>[ 78.477878] random: crng reseeded on system resumption
11662 12:47:03.913784 <6>[ 78.484499] PM: suspend exit
11663 12:47:03.917124 rtcwake: write error
11664 12:47:03.923769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11665 12:47:03.924639 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11667 12:47:03.927174 rtcwake: assuming RTC uses UTC ...
11668 12:47:03.933707 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:47:05 2023
11669 12:47:03.947335 <6>[ 78.515638] PM: suspend entry (s2idle)
11670 12:47:03.949513 <6>[ 78.519695] Filesystems sync: 0.000 seconds
11671 12:47:03.956471 <6>[ 78.524811] Freezing user space processes
11672 12:47:03.963393 <6>[ 78.530464] Freezing user space processes completed (elapsed 0.001 seconds)
11673 12:47:03.966299 <6>[ 78.537690] OOM killer disabled.
11674 12:47:03.973492 <6>[ 78.541171] Freezing remaining freezable tasks
11675 12:47:03.979926 <6>[ 78.547028] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11676 12:47:03.986375 <6>[ 78.554682] printk: Suspending console(s) (use no_console_suspend to debug)
11677 12:47:07.178394 <3>[ 78.562708] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11678 12:47:07.185064 <3>[ 78.562734] elants_i2c 4-0010: PM: failed to suspend async: error -16
11679 12:47:07.191681 <3>[ 81.739682] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11680 12:47:07.201574 <3>[ 81.739718] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11681 12:47:07.208149 <3>[ 81.739757] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11682 12:47:07.214624 <3>[ 81.739786] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11683 12:47:07.224620 <3>[ 81.740175] PM: Some devices failed to suspend, or early wake event detected
11684 12:47:07.227729 <6>[ 81.797862] OOM killer enabled.
11685 12:47:07.231423 <6>[ 81.801261] Restarting tasks ... done.
11686 12:47:07.237734 <5>[ 81.806024] random: crng reseeded on system resumption
11687 12:47:07.241287 <6>[ 81.812752] PM: suspend exit
11688 12:47:07.244236 rtcwake: write error
11689 12:47:07.251687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11690 12:47:07.252672 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11692 12:47:07.254762 rtcwake: assuming RTC uses UTC ...
11693 12:47:07.261539 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:47:08 2023
11694 12:47:07.274218 <6>[ 81.843721] PM: suspend entry (s2idle)
11695 12:47:07.277338 <6>[ 81.847786] Filesystems sync: 0.000 seconds
11696 12:47:07.284089 <6>[ 81.852944] Freezing user space processes
11697 12:47:07.290762 <6>[ 81.858567] Freezing user space processes completed (elapsed 0.001 seconds)
11698 12:47:07.294035 <6>[ 81.865797] OOM killer disabled.
11699 12:47:07.301045 <6>[ 81.869278] Freezing remaining freezable tasks
11700 12:47:07.307579 <6>[ 81.875151] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11701 12:47:07.317016 <6>[ 81.882814] printk: Suspending console(s) (use no_console_suspend to debug)
11702 12:47:10.506104 <3>[ 81.890895] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11703 12:47:10.512292 <3>[ 81.890922] elants_i2c 4-0010: PM: failed to suspend async: error -16
11704 12:47:10.519344 <3>[ 85.067642] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11705 12:47:10.529379 <3>[ 85.067665] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11706 12:47:10.535827 <3>[ 85.067691] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11707 12:47:10.542575 <3>[ 85.067714] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11708 12:47:10.552108 <3>[ 85.068104] PM: Some devices failed to suspend, or early wake event detected
11709 12:47:10.555596 <6>[ 85.125682] OOM killer enabled.
11710 12:47:10.558902 <6>[ 85.129077] Restarting tasks ... done.
11711 12:47:10.565172 <5>[ 85.133955] random: crng reseeded on system resumption
11712 12:47:10.568512 <6>[ 85.140529] PM: suspend exit
11713 12:47:10.571796 rtcwake: write error
11714 12:47:10.579135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11715 12:47:10.580117 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
11717 12:47:10.581988 rtcwake: assuming RTC uses UTC ...
11718 12:47:10.588836 rtcwake: wakeup from "freeze" using rtc0 at Wed Jun 14 12:47:11 2023
11719 12:47:10.602230 <6>[ 85.171636] PM: suspend entry (s2idle)
11720 12:47:10.605367 <6>[ 85.175725] Filesystems sync: 0.000 seconds
11721 12:47:10.611539 <6>[ 85.180944] Freezing user space processes
11722 12:47:10.618775 <6>[ 85.186596] Freezing user space processes completed (elapsed 0.001 seconds)
11723 12:47:10.622307 <6>[ 85.193835] OOM killer disabled.
11724 12:47:10.628609 <6>[ 85.197317] Freezing remaining freezable tasks
11725 12:47:10.635535 <6>[ 85.203199] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11726 12:47:10.644874 <6>[ 85.210865] printk: Suspending console(s) (use no_console_suspend to debug)
11727 12:47:13.833830 <3>[ 85.218918] elants_i2c 4-0010: PM: dpm_run_callback(): elants_i2c_suspend+0x0/0x180 [elants_i2c] returns -16
11728 12:47:13.840492 <3>[ 85.218946] elants_i2c 4-0010: PM: failed to suspend async: error -16
11729 12:47:13.846799 <3>[ 88.395714] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11730 12:47:13.856836 <3>[ 88.395751] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11731 12:47:13.863517 <3>[ 88.395791] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11732 12:47:13.869937 <3>[ 88.395820] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11733 12:47:13.880033 <3>[ 88.396190] PM: Some devices failed to suspend, or early wake event detected
11734 12:47:13.882899 <6>[ 88.454001] OOM killer enabled.
11735 12:47:13.886231 <6>[ 88.457400] Restarting tasks ... done.
11736 12:47:13.893585 <5>[ 88.462209] random: crng reseeded on system resumption
11737 12:47:13.896479 <6>[ 88.469621] PM: suspend exit
11738 12:47:13.900289 rtcwake: write error
11739 12:47:13.907932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11740 12:47:13.908804 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
11742 12:47:13.910959 + set +x
11743 12:47:13.914607 <LAVA_SIGNAL_ENDRUN 0_sleep 10724891_1.5.2.3.1>
11744 12:47:13.915187 <LAVA_TEST_RUNNER EXIT>
11745 12:47:13.915834 Received signal: <ENDRUN> 0_sleep 10724891_1.5.2.3.1
11746 12:47:13.916270 Ending use of test pattern.
11747 12:47:13.916618 Ending test lava.0_sleep (10724891_1.5.2.3.1), duration 66.50
11749 12:47:13.918754 ok: lava_test_shell seems to have completed
11750 12:47:13.919807 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11751 12:47:13.920324 end: 3.1 lava-test-shell (duration 00:01:07) [common]
11752 12:47:13.920789 end: 3 lava-test-retry (duration 00:01:07) [common]
11753 12:47:13.921019 start: 4 finalize (timeout 00:06:18) [common]
11754 12:47:13.921123 start: 4.1 power-off (timeout 00:00:30) [common]
11755 12:47:13.921272 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11756 12:47:13.999393 >> Command sent successfully.
11757 12:47:14.005099 Returned 0 in 0 seconds
11758 12:47:14.106146 end: 4.1 power-off (duration 00:00:00) [common]
11760 12:47:14.107631 start: 4.2 read-feedback (timeout 00:06:17) [common]
11761 12:47:14.108877 Listened to connection for namespace 'common' for up to 1s
11762 12:47:14.109755 Listened to connection for namespace 'common' for up to 1s
11763 12:47:15.109274 Finalising connection for namespace 'common'
11764 12:47:15.109996 Disconnecting from shell: Finalise
11765 12:47:15.110447 / #
11766 12:47:15.211580 end: 4.2 read-feedback (duration 00:00:01) [common]
11767 12:47:15.212302 end: 4 finalize (duration 00:00:01) [common]
11768 12:47:15.213144 Cleaning after the job
11769 12:47:15.213704 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/ramdisk
11770 12:47:15.252082 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/kernel
11771 12:47:15.275822 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/dtb
11772 12:47:15.276041 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724891/tftp-deploy-y3xahij0/modules
11773 12:47:15.281581 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724891
11774 12:47:15.414207 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724891
11775 12:47:15.414387 Job finished correctly