Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 70
- Errors: 2
1 12:44:56.659885 lava-dispatcher, installed at version: 2023.05.1
2 12:44:56.660122 start: 0 validate
3 12:44:56.660270 Start time: 2023-06-14 12:44:56.660262+00:00 (UTC)
4 12:44:56.660425 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:44:56.660578 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 12:44:56.915001 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:44:56.915208 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:44:57.174702 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:44:57.174898 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:44:57.442219 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:44:57.442407 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:44:57.702477 validate duration: 1.04
14 12:44:57.702827 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:44:57.702966 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:44:57.703092 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:44:57.703274 Not decompressing ramdisk as can be used compressed.
18 12:44:57.703402 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230609.0/arm64/rootfs.cpio.gz
19 12:44:57.703505 saving as /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/ramdisk/rootfs.cpio.gz
20 12:44:57.703603 total size: 27153005 (25MB)
21 12:44:57.705095 progress 0% (0MB)
22 12:44:57.712628 progress 5% (1MB)
23 12:44:57.719740 progress 10% (2MB)
24 12:44:57.726914 progress 15% (3MB)
25 12:44:57.733960 progress 20% (5MB)
26 12:44:57.741246 progress 25% (6MB)
27 12:44:57.748424 progress 30% (7MB)
28 12:44:57.755485 progress 35% (9MB)
29 12:44:57.762610 progress 40% (10MB)
30 12:44:57.769629 progress 45% (11MB)
31 12:44:57.776855 progress 50% (12MB)
32 12:44:57.783985 progress 55% (14MB)
33 12:44:57.791438 progress 60% (15MB)
34 12:44:57.798564 progress 65% (16MB)
35 12:44:57.805743 progress 70% (18MB)
36 12:44:57.812745 progress 75% (19MB)
37 12:44:57.819739 progress 80% (20MB)
38 12:44:57.826924 progress 85% (22MB)
39 12:44:57.833800 progress 90% (23MB)
40 12:44:57.840986 progress 95% (24MB)
41 12:44:57.848268 progress 100% (25MB)
42 12:44:57.848557 25MB downloaded in 0.14s (178.65MB/s)
43 12:44:57.848723 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:44:57.848970 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:44:57.849060 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:44:57.849144 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:44:57.849280 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:44:57.849354 saving as /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/kernel/Image
50 12:44:57.849416 total size: 47581696 (45MB)
51 12:44:57.849482 No compression specified
52 12:44:57.850661 progress 0% (0MB)
53 12:44:57.862957 progress 5% (2MB)
54 12:44:57.875781 progress 10% (4MB)
55 12:44:57.888378 progress 15% (6MB)
56 12:44:57.901212 progress 20% (9MB)
57 12:44:57.913759 progress 25% (11MB)
58 12:44:57.926557 progress 30% (13MB)
59 12:44:57.939254 progress 35% (15MB)
60 12:44:57.951792 progress 40% (18MB)
61 12:44:57.964453 progress 45% (20MB)
62 12:44:57.977160 progress 50% (22MB)
63 12:44:57.989714 progress 55% (24MB)
64 12:44:58.002314 progress 60% (27MB)
65 12:44:58.014640 progress 65% (29MB)
66 12:44:58.027222 progress 70% (31MB)
67 12:44:58.039920 progress 75% (34MB)
68 12:44:58.052847 progress 80% (36MB)
69 12:44:58.065661 progress 85% (38MB)
70 12:44:58.077942 progress 90% (40MB)
71 12:44:58.090318 progress 95% (43MB)
72 12:44:58.102762 progress 100% (45MB)
73 12:44:58.102909 45MB downloaded in 0.25s (179.01MB/s)
74 12:44:58.103057 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:44:58.103292 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:44:58.103385 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:44:58.103472 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:44:58.103659 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:44:58.103742 saving as /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/dtb/mt8192-asurada-spherion-r0.dtb
81 12:44:58.103808 total size: 46924 (0MB)
82 12:44:58.103911 No compression specified
83 12:44:58.105297 progress 69% (0MB)
84 12:44:58.105573 progress 100% (0MB)
85 12:44:58.105730 0MB downloaded in 0.00s (23.31MB/s)
86 12:44:58.105861 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:44:58.106228 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:44:58.106343 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:44:58.106466 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:44:58.106581 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:44:58.106656 saving as /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/modules/modules.tar
93 12:44:58.106716 total size: 8536768 (8MB)
94 12:44:58.106776 Using unxz to decompress xz
95 12:44:58.110502 progress 0% (0MB)
96 12:44:58.131727 progress 5% (0MB)
97 12:44:58.160244 progress 10% (0MB)
98 12:44:58.193465 progress 15% (1MB)
99 12:44:58.218355 progress 20% (1MB)
100 12:44:58.242593 progress 25% (2MB)
101 12:44:58.267524 progress 30% (2MB)
102 12:44:58.291921 progress 35% (2MB)
103 12:44:58.319979 progress 40% (3MB)
104 12:44:58.345339 progress 45% (3MB)
105 12:44:58.371622 progress 50% (4MB)
106 12:44:58.396972 progress 55% (4MB)
107 12:44:58.423453 progress 60% (4MB)
108 12:44:58.449841 progress 65% (5MB)
109 12:44:58.475843 progress 70% (5MB)
110 12:44:58.501311 progress 75% (6MB)
111 12:44:58.526093 progress 80% (6MB)
112 12:44:58.550500 progress 85% (6MB)
113 12:44:58.576092 progress 90% (7MB)
114 12:44:58.601591 progress 95% (7MB)
115 12:44:58.624519 progress 100% (8MB)
116 12:44:58.631258 8MB downloaded in 0.52s (15.52MB/s)
117 12:44:58.631580 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:44:58.631912 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:44:58.632021 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:44:58.632117 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:44:58.632234 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:44:58.632326 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:44:58.632584 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow
125 12:44:58.632714 makedir: /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin
126 12:44:58.632817 makedir: /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/tests
127 12:44:58.632911 makedir: /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/results
128 12:44:58.633022 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-add-keys
129 12:44:58.633194 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-add-sources
130 12:44:58.633321 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-background-process-start
131 12:44:58.633448 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-background-process-stop
132 12:44:58.633601 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-common-functions
133 12:44:58.633721 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-echo-ipv4
134 12:44:58.633845 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-install-packages
135 12:44:58.633964 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-installed-packages
136 12:44:58.634082 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-os-build
137 12:44:58.634230 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-probe-channel
138 12:44:58.634350 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-probe-ip
139 12:44:58.634499 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-target-ip
140 12:44:58.634615 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-target-mac
141 12:44:58.634734 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-target-storage
142 12:44:58.634888 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-test-case
143 12:44:58.635055 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-test-event
144 12:44:58.635243 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-test-feedback
145 12:44:58.635399 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-test-raise
146 12:44:58.635525 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-test-reference
147 12:44:58.635675 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-test-runner
148 12:44:58.635796 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-test-set
149 12:44:58.635920 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-test-shell
150 12:44:58.636045 Updating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-install-packages (oe)
151 12:44:58.636222 Updating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/bin/lava-installed-packages (oe)
152 12:44:58.636357 Creating /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/environment
153 12:44:58.636466 LAVA metadata
154 12:44:58.636560 - LAVA_JOB_ID=10724910
155 12:44:58.636625 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:44:58.636728 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:44:58.636796 skipped lava-vland-overlay
158 12:44:58.636871 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:44:58.636952 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:44:58.637014 skipped lava-multinode-overlay
161 12:44:58.637089 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:44:58.637172 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:44:58.637245 Loading test definitions
164 12:44:58.637335 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:44:58.637407 Using /lava-10724910 at stage 0
166 12:44:58.637691 uuid=10724910_1.5.2.3.1 testdef=None
167 12:44:58.637778 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:44:58.637866 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:44:58.638369 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:44:58.638640 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:44:58.639356 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:44:58.639588 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:44:58.640162 runner path: /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10724910_1.5.2.3.1
176 12:44:58.640312 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:44:58.640521 Creating lava-test-runner.conf files
179 12:44:58.640622 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724910/lava-overlay-ogqrq0ow/lava-10724910/0 for stage 0
180 12:44:58.640736 - 0_v4l2-compliance-mtk-vcodec-enc
181 12:44:58.640831 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:44:58.640917 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:44:58.647614 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:44:58.647720 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:44:58.647837 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:44:58.647961 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:44:58.648068 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:44:59.360073 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:44:59.360426 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:44:59.360581 extracting modules file /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724910/extract-overlay-ramdisk-x8jm_tm0/ramdisk
191 12:44:59.574674 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:44:59.574837 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:44:59.574933 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724910/compress-overlay-xt53dz5z/overlay-1.5.2.4.tar.gz to ramdisk
194 12:44:59.575007 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724910/compress-overlay-xt53dz5z/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724910/extract-overlay-ramdisk-x8jm_tm0/ramdisk
195 12:44:59.581471 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:44:59.581583 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:44:59.581674 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:44:59.581763 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:44:59.581841 Building ramdisk /var/lib/lava/dispatcher/tmp/10724910/extract-overlay-ramdisk-x8jm_tm0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724910/extract-overlay-ramdisk-x8jm_tm0/ramdisk
200 12:45:00.110364 >> 230342 blocks
201 12:45:04.300513 rename /var/lib/lava/dispatcher/tmp/10724910/extract-overlay-ramdisk-x8jm_tm0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/ramdisk/ramdisk.cpio.gz
202 12:45:04.300928 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:45:04.301050 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:45:04.301152 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:45:04.301266 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/kernel/Image'
206 12:45:16.193224 Returned 0 in 11 seconds
207 12:45:16.294034 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/kernel/image.itb
208 12:45:16.871116 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:45:16.871467 output: Created: Wed Jun 14 13:45:16 2023
210 12:45:16.871546 output: Image 0 (kernel-1)
211 12:45:16.871612 output: Description:
212 12:45:16.871674 output: Created: Wed Jun 14 13:45:16 2023
213 12:45:16.871736 output: Type: Kernel Image
214 12:45:16.871796 output: Compression: lzma compressed
215 12:45:16.871855 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
216 12:45:16.871914 output: Architecture: AArch64
217 12:45:16.871968 output: OS: Linux
218 12:45:16.872029 output: Load Address: 0x00000000
219 12:45:16.872087 output: Entry Point: 0x00000000
220 12:45:16.872143 output: Hash algo: crc32
221 12:45:16.872198 output: Hash value: ced21bfe
222 12:45:16.872251 output: Image 1 (fdt-1)
223 12:45:16.872303 output: Description: mt8192-asurada-spherion-r0
224 12:45:16.872355 output: Created: Wed Jun 14 13:45:16 2023
225 12:45:16.872408 output: Type: Flat Device Tree
226 12:45:16.872461 output: Compression: uncompressed
227 12:45:16.872518 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:45:16.872584 output: Architecture: AArch64
229 12:45:16.872638 output: Hash algo: crc32
230 12:45:16.872690 output: Hash value: 1df858fa
231 12:45:16.872742 output: Image 2 (ramdisk-1)
232 12:45:16.872794 output: Description: unavailable
233 12:45:16.872846 output: Created: Wed Jun 14 13:45:16 2023
234 12:45:16.872899 output: Type: RAMDisk Image
235 12:45:16.872951 output: Compression: Unknown Compression
236 12:45:16.873005 output: Data Size: 40144210 Bytes = 39203.33 KiB = 38.28 MiB
237 12:45:16.873059 output: Architecture: AArch64
238 12:45:16.873111 output: OS: Linux
239 12:45:16.873163 output: Load Address: unavailable
240 12:45:16.873215 output: Entry Point: unavailable
241 12:45:16.873267 output: Hash algo: crc32
242 12:45:16.873319 output: Hash value: dd68c745
243 12:45:16.873371 output: Default Configuration: 'conf-1'
244 12:45:16.873423 output: Configuration 0 (conf-1)
245 12:45:16.873475 output: Description: mt8192-asurada-spherion-r0
246 12:45:16.873526 output: Kernel: kernel-1
247 12:45:16.873578 output: Init Ramdisk: ramdisk-1
248 12:45:16.873632 output: FDT: fdt-1
249 12:45:16.873686 output: Loadables: kernel-1
250 12:45:16.873737 output:
251 12:45:16.873928 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:45:16.874023 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:45:16.874130 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 12:45:16.874223 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 12:45:16.874305 No LXC device requested
256 12:45:16.874384 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:45:16.874471 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 12:45:16.874548 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:45:16.874617 Checking files for TFTP limit of 4294967296 bytes.
260 12:45:16.875108 end: 1 tftp-deploy (duration 00:00:19) [common]
261 12:45:16.875208 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:45:16.875305 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:45:16.875427 substitutions:
264 12:45:16.875495 - {DTB}: 10724910/tftp-deploy-h2rsz2y1/dtb/mt8192-asurada-spherion-r0.dtb
265 12:45:16.875558 - {INITRD}: 10724910/tftp-deploy-h2rsz2y1/ramdisk/ramdisk.cpio.gz
266 12:45:16.875616 - {KERNEL}: 10724910/tftp-deploy-h2rsz2y1/kernel/Image
267 12:45:16.875673 - {LAVA_MAC}: None
268 12:45:16.875728 - {PRESEED_CONFIG}: None
269 12:45:16.875786 - {PRESEED_LOCAL}: None
270 12:45:16.875841 - {RAMDISK}: 10724910/tftp-deploy-h2rsz2y1/ramdisk/ramdisk.cpio.gz
271 12:45:16.875896 - {ROOT_PART}: None
272 12:45:16.875949 - {ROOT}: None
273 12:45:16.876003 - {SERVER_IP}: 192.168.201.1
274 12:45:16.876055 - {TEE}: None
275 12:45:16.876109 Parsed boot commands:
276 12:45:16.876161 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:45:16.876329 Parsed boot commands: tftpboot 192.168.201.1 10724910/tftp-deploy-h2rsz2y1/kernel/image.itb 10724910/tftp-deploy-h2rsz2y1/kernel/cmdline
278 12:45:16.876416 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:45:16.876504 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:45:16.876644 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:45:16.876729 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:45:16.876798 Not connected, no need to disconnect.
283 12:45:16.876870 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:45:16.876946 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:45:16.877016 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
286 12:45:16.880344 Setting prompt string to ['lava-test: # ']
287 12:45:16.880721 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:45:16.880827 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:45:16.880929 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:45:16.881022 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:45:16.881220 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 12:45:22.021674 >> Command sent successfully.
293 12:45:22.031894 Returned 0 in 5 seconds
294 12:45:22.133089 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:45:22.135907 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:45:22.136677 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:45:22.137187 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:45:22.137570 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:45:22.138009 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:45:22.139274 [Enter `^Ec?' for help]
302 12:45:22.297515
303 12:45:22.298101
304 12:45:22.298475 F0: 102B 0000
305 12:45:22.298853
306 12:45:22.299195 F3: 1001 0000 [0200]
307 12:45:22.299717
308 12:45:22.300745 F3: 1001 0000
309 12:45:22.301216
310 12:45:22.301585 F7: 102D 0000
311 12:45:22.301933
312 12:45:22.304037 F1: 0000 0000
313 12:45:22.304503
314 12:45:22.304946 V0: 0000 0000 [0001]
315 12:45:22.305297
316 12:45:22.308061 00: 0007 8000
317 12:45:22.308583
318 12:45:22.308975 01: 0000 0000
319 12:45:22.309297
320 12:45:22.309597 BP: 0C00 0209 [0000]
321 12:45:22.311266
322 12:45:22.311685 G0: 1182 0000
323 12:45:22.312020
324 12:45:22.312332 EC: 0000 0021 [4000]
325 12:45:22.312692
326 12:45:22.314829 S7: 0000 0000 [0000]
327 12:45:22.315298
328 12:45:22.315648 CC: 0000 0000 [0001]
329 12:45:22.315965
330 12:45:22.317902 T0: 0000 0040 [010F]
331 12:45:22.318337
332 12:45:22.318710 Jump to BL
333 12:45:22.319054
334 12:45:22.343896
335 12:45:22.344451
336 12:45:22.344877
337 12:45:22.351242 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:45:22.355126 ARM64: Exception handlers installed.
339 12:45:22.359666 ARM64: Testing exception
340 12:45:22.362286 ARM64: Done test exception
341 12:45:22.369344 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:45:22.376896 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:45:22.384217 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:45:22.395057 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:45:22.402205 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:45:22.408876 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:45:22.420463 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:45:22.426911 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:45:22.447232 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:45:22.450236 WDT: Last reset was cold boot
351 12:45:22.453310 SPI1(PAD0) initialized at 2873684 Hz
352 12:45:22.456729 SPI5(PAD0) initialized at 992727 Hz
353 12:45:22.460090 VBOOT: Loading verstage.
354 12:45:22.466630 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:45:22.469831 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:45:22.473396 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:45:22.476480 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:45:22.483901 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:45:22.490772 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:45:22.502238 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:45:22.502723
362 12:45:22.503096
363 12:45:22.511598 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:45:22.515571 ARM64: Exception handlers installed.
365 12:45:22.518921 ARM64: Testing exception
366 12:45:22.519508 ARM64: Done test exception
367 12:45:22.525484 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:45:22.528397 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:45:22.543483 Probing TPM: . done!
370 12:45:22.544066 TPM ready after 0 ms
371 12:45:22.549469 Connected to device vid:did:rid of 1ae0:0028:00
372 12:45:22.559768 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:45:22.597781 Initialized TPM device CR50 revision 0
374 12:45:22.609979 tlcl_send_startup: Startup return code is 0
375 12:45:22.610471 TPM: setup succeeded
376 12:45:22.622699 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:45:22.631131 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:45:22.641426 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:45:22.649873 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:45:22.653043 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:45:22.656272 in-header: 03 07 00 00 08 00 00 00
382 12:45:22.659546 in-data: aa e4 47 04 13 02 00 00
383 12:45:22.663189 Chrome EC: UHEPI supported
384 12:45:22.669801 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:45:22.673092 in-header: 03 ad 00 00 08 00 00 00
386 12:45:22.676093 in-data: 00 20 20 08 00 00 00 00
387 12:45:22.676620 Phase 1
388 12:45:22.679418 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:45:22.686114 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:45:22.693002 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:45:22.696676 Recovery requested (1009000e)
392 12:45:22.700378 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:45:22.708790 tlcl_extend: response is 0
394 12:45:22.717062 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:45:22.721839 tlcl_extend: response is 0
396 12:45:22.728893 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:45:22.749289 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:45:22.756627 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:45:22.757202
400 12:45:22.757580
401 12:45:22.766907 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:45:22.770478 ARM64: Exception handlers installed.
403 12:45:22.771268 ARM64: Testing exception
404 12:45:22.773233 ARM64: Done test exception
405 12:45:22.795049 pmic_efuse_setting: Set efuses in 11 msecs
406 12:45:22.798295 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:45:22.805100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:45:22.808617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:45:22.812073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:45:22.818568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:45:22.822008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:45:22.828833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:45:22.832077 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:45:22.839005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:45:22.842124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:45:22.845812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:45:22.852260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:45:22.855160 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:45:22.862423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:45:22.868727 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:45:22.871623 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:45:22.878247 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:45:22.885008 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:45:22.888452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:45:22.894977 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:45:22.901344 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:45:22.905182 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:45:22.912508 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:45:22.919141 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:45:22.923301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:45:22.929710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:45:22.933208 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:45:22.939977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:45:22.943199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:45:22.950465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:45:22.953561 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:45:22.957258 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:45:22.963486 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:45:22.967065 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:45:22.973710 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:45:22.977146 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:45:22.984292 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:45:22.990575 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:45:22.994146 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:45:22.997398 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:45:23.004303 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:45:23.007707 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:45:23.010935 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:45:23.015039 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:45:23.021483 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:45:23.024988 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:45:23.027889 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:45:23.031288 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:45:23.038203 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:45:23.041434 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:45:23.044479 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:45:23.048270 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:45:23.058463 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:45:23.064708 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:45:23.071724 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:45:23.078237 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:45:23.088083 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:45:23.091824 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:45:23.097909 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:45:23.101171 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:45:23.108095 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1f
467 12:45:23.114119 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:45:23.118458 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 12:45:23.121055 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:45:23.131813 [RTC]rtc_get_frequency_meter,154: input=15, output=833
471 12:45:23.141693 [RTC]rtc_get_frequency_meter,154: input=7, output=707
472 12:45:23.150895 [RTC]rtc_get_frequency_meter,154: input=11, output=771
473 12:45:23.160646 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 12:45:23.170029 [RTC]rtc_get_frequency_meter,154: input=12, output=787
475 12:45:23.179591 [RTC]rtc_get_frequency_meter,154: input=12, output=787
476 12:45:23.188730 [RTC]rtc_get_frequency_meter,154: input=13, output=804
477 12:45:23.192510 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 12:45:23.199403 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 12:45:23.202647 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:45:23.206216 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:45:23.212672 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:45:23.216135 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:45:23.219744 ADC[4]: Raw value=903031 ID=7
484 12:45:23.220344 ADC[3]: Raw value=214021 ID=1
485 12:45:23.222702 RAM Code: 0x71
486 12:45:23.225897 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:45:23.232507 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:45:23.239520 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:45:23.246310 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:45:23.249438 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:45:23.252190 in-header: 03 07 00 00 08 00 00 00
492 12:45:23.255711 in-data: aa e4 47 04 13 02 00 00
493 12:45:23.259668 Chrome EC: UHEPI supported
494 12:45:23.265756 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:45:23.268764 in-header: 03 dd 00 00 08 00 00 00
496 12:45:23.272689 in-data: 90 20 60 08 00 00 00 00
497 12:45:23.275544 MRC: failed to locate region type 0.
498 12:45:23.282433 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:45:23.285430 DRAM-K: Running full calibration
500 12:45:23.292500 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:45:23.293114 header.status = 0x0
502 12:45:23.295184 header.version = 0x6 (expected: 0x6)
503 12:45:23.299034 header.size = 0xd00 (expected: 0xd00)
504 12:45:23.302128 header.flags = 0x0
505 12:45:23.308686 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:45:23.326152 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 12:45:23.332194 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:45:23.335692 dram_init: ddr_geometry: 2
509 12:45:23.338884 [EMI] MDL number = 2
510 12:45:23.339354 [EMI] Get MDL freq = 0
511 12:45:23.342026 dram_init: ddr_type: 0
512 12:45:23.342528 is_discrete_lpddr4: 1
513 12:45:23.345334 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:45:23.345807
515 12:45:23.346182
516 12:45:23.348915 [Bian_co] ETT version 0.0.0.1
517 12:45:23.355420 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:45:23.355912
519 12:45:23.358506 dramc_set_vcore_voltage set vcore to 650000
520 12:45:23.362474 Read voltage for 800, 4
521 12:45:23.363058 Vio18 = 0
522 12:45:23.363441 Vcore = 650000
523 12:45:23.365457 Vdram = 0
524 12:45:23.365930 Vddq = 0
525 12:45:23.366305 Vmddr = 0
526 12:45:23.369388 dram_init: config_dvfs: 1
527 12:45:23.372284 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:45:23.378840 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:45:23.382440 [SwImpedanceCal] DRVP=8, DRVN=15, ODTN=9
530 12:45:23.386262 freq_region=0, Reg: DRVP=8, DRVN=15, ODTN=9
531 12:45:23.389008 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 12:45:23.392184 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 12:45:23.395376 MEM_TYPE=3, freq_sel=18
534 12:45:23.398567 sv_algorithm_assistance_LP4_1600
535 12:45:23.402270 ============ PULL DRAM RESETB DOWN ============
536 12:45:23.408823 ========== PULL DRAM RESETB DOWN end =========
537 12:45:23.412098 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:45:23.415212 ===================================
539 12:45:23.418611 LPDDR4 DRAM CONFIGURATION
540 12:45:23.421758 ===================================
541 12:45:23.422238 EX_ROW_EN[0] = 0x0
542 12:45:23.425043 EX_ROW_EN[1] = 0x0
543 12:45:23.425615 LP4Y_EN = 0x0
544 12:45:23.428375 WORK_FSP = 0x0
545 12:45:23.428908 WL = 0x2
546 12:45:23.431650 RL = 0x2
547 12:45:23.432198 BL = 0x2
548 12:45:23.435848 RPST = 0x0
549 12:45:23.436394 RD_PRE = 0x0
550 12:45:23.438383 WR_PRE = 0x1
551 12:45:23.442287 WR_PST = 0x0
552 12:45:23.442756 DBI_WR = 0x0
553 12:45:23.445243 DBI_RD = 0x0
554 12:45:23.445815 OTF = 0x1
555 12:45:23.448416 ===================================
556 12:45:23.451491 ===================================
557 12:45:23.451981 ANA top config
558 12:45:23.454700 ===================================
559 12:45:23.458344 DLL_ASYNC_EN = 0
560 12:45:23.461449 ALL_SLAVE_EN = 1
561 12:45:23.464819 NEW_RANK_MODE = 1
562 12:45:23.468286 DLL_IDLE_MODE = 1
563 12:45:23.468817 LP45_APHY_COMB_EN = 1
564 12:45:23.471206 TX_ODT_DIS = 1
565 12:45:23.474779 NEW_8X_MODE = 1
566 12:45:23.478634 ===================================
567 12:45:23.481207 ===================================
568 12:45:23.485269 data_rate = 1600
569 12:45:23.488580 CKR = 1
570 12:45:23.489166 DQ_P2S_RATIO = 8
571 12:45:23.491422 ===================================
572 12:45:23.495035 CA_P2S_RATIO = 8
573 12:45:23.498283 DQ_CA_OPEN = 0
574 12:45:23.501437 DQ_SEMI_OPEN = 0
575 12:45:23.505312 CA_SEMI_OPEN = 0
576 12:45:23.507756 CA_FULL_RATE = 0
577 12:45:23.508227 DQ_CKDIV4_EN = 1
578 12:45:23.511731 CA_CKDIV4_EN = 1
579 12:45:23.515245 CA_PREDIV_EN = 0
580 12:45:23.518059 PH8_DLY = 0
581 12:45:23.521424 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:45:23.524692 DQ_AAMCK_DIV = 4
583 12:45:23.525253 CA_AAMCK_DIV = 4
584 12:45:23.527842 CA_ADMCK_DIV = 4
585 12:45:23.531382 DQ_TRACK_CA_EN = 0
586 12:45:23.534727 CA_PICK = 800
587 12:45:23.537722 CA_MCKIO = 800
588 12:45:23.541181 MCKIO_SEMI = 0
589 12:45:23.544192 PLL_FREQ = 3068
590 12:45:23.544702 DQ_UI_PI_RATIO = 32
591 12:45:23.548184 CA_UI_PI_RATIO = 0
592 12:45:23.551185 ===================================
593 12:45:23.554046 ===================================
594 12:45:23.557415 memory_type:LPDDR4
595 12:45:23.560658 GP_NUM : 10
596 12:45:23.561134 SRAM_EN : 1
597 12:45:23.564327 MD32_EN : 0
598 12:45:23.567606 ===================================
599 12:45:23.571342 [ANA_INIT] >>>>>>>>>>>>>>
600 12:45:23.571909 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:45:23.574271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:45:23.577832 ===================================
603 12:45:23.581152 data_rate = 1600,PCW = 0X7600
604 12:45:23.584604 ===================================
605 12:45:23.587601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:45:23.594402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:45:23.600630 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:45:23.604045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:45:23.608053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:45:23.610633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:45:23.613924 [ANA_INIT] flow start
612 12:45:23.614483 [ANA_INIT] PLL >>>>>>>>
613 12:45:23.617291 [ANA_INIT] PLL <<<<<<<<
614 12:45:23.620986 [ANA_INIT] MIDPI >>>>>>>>
615 12:45:23.624111 [ANA_INIT] MIDPI <<<<<<<<
616 12:45:23.624618 [ANA_INIT] DLL >>>>>>>>
617 12:45:23.627066 [ANA_INIT] flow end
618 12:45:23.630443 ============ LP4 DIFF to SE enter ============
619 12:45:23.633697 ============ LP4 DIFF to SE exit ============
620 12:45:23.637262 [ANA_INIT] <<<<<<<<<<<<<
621 12:45:23.640607 [Flow] Enable top DCM control >>>>>
622 12:45:23.643844 [Flow] Enable top DCM control <<<<<
623 12:45:23.647464 Enable DLL master slave shuffle
624 12:45:23.653905 ==============================================================
625 12:45:23.654467 Gating Mode config
626 12:45:23.660823 ==============================================================
627 12:45:23.661435 Config description:
628 12:45:23.670226 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:45:23.676895 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:45:23.683926 SELPH_MODE 0: By rank 1: By Phase
631 12:45:23.687158 ==============================================================
632 12:45:23.690608 GAT_TRACK_EN = 1
633 12:45:23.693955 RX_GATING_MODE = 2
634 12:45:23.697375 RX_GATING_TRACK_MODE = 2
635 12:45:23.700464 SELPH_MODE = 1
636 12:45:23.704101 PICG_EARLY_EN = 1
637 12:45:23.707060 VALID_LAT_VALUE = 1
638 12:45:23.710094 ==============================================================
639 12:45:23.713266 Enter into Gating configuration >>>>
640 12:45:23.716597 Exit from Gating configuration <<<<
641 12:45:23.720479 Enter into DVFS_PRE_config >>>>>
642 12:45:23.733438 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:45:23.736643 Exit from DVFS_PRE_config <<<<<
644 12:45:23.739671 Enter into PICG configuration >>>>
645 12:45:23.743450 Exit from PICG configuration <<<<
646 12:45:23.743922 [RX_INPUT] configuration >>>>>
647 12:45:23.746456 [RX_INPUT] configuration <<<<<
648 12:45:23.753157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:45:23.756633 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:45:23.763925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:45:23.771124 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:45:23.778622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:45:23.782403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:45:23.785902 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:45:23.789737 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:45:23.796340 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:45:23.800031 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:45:23.803723 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:45:23.807577 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:45:23.811027 ===================================
661 12:45:23.815028 LPDDR4 DRAM CONFIGURATION
662 12:45:23.815753 ===================================
663 12:45:23.818540 EX_ROW_EN[0] = 0x0
664 12:45:23.821919 EX_ROW_EN[1] = 0x0
665 12:45:23.822395 LP4Y_EN = 0x0
666 12:45:23.825234 WORK_FSP = 0x0
667 12:45:23.825708 WL = 0x2
668 12:45:23.828863 RL = 0x2
669 12:45:23.829337 BL = 0x2
670 12:45:23.832960 RPST = 0x0
671 12:45:23.833537 RD_PRE = 0x0
672 12:45:23.833916 WR_PRE = 0x1
673 12:45:23.836274 WR_PST = 0x0
674 12:45:23.836788 DBI_WR = 0x0
675 12:45:23.840376 DBI_RD = 0x0
676 12:45:23.840893 OTF = 0x1
677 12:45:23.844287 ===================================
678 12:45:23.847351 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:45:23.850971 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:45:23.858515 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:45:23.861990 ===================================
682 12:45:23.862586 LPDDR4 DRAM CONFIGURATION
683 12:45:23.865845 ===================================
684 12:45:23.869421 EX_ROW_EN[0] = 0x10
685 12:45:23.869922 EX_ROW_EN[1] = 0x0
686 12:45:23.872988 LP4Y_EN = 0x0
687 12:45:23.873459 WORK_FSP = 0x0
688 12:45:23.876508 WL = 0x2
689 12:45:23.876986 RL = 0x2
690 12:45:23.880504 BL = 0x2
691 12:45:23.881134 RPST = 0x0
692 12:45:23.883776 RD_PRE = 0x0
693 12:45:23.884290 WR_PRE = 0x1
694 12:45:23.884691 WR_PST = 0x0
695 12:45:23.887995 DBI_WR = 0x0
696 12:45:23.888420 DBI_RD = 0x0
697 12:45:23.891644 OTF = 0x1
698 12:45:23.895032 ===================================
699 12:45:23.898389 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:45:23.904129 nWR fixed to 40
701 12:45:23.907180 [ModeRegInit_LP4] CH0 RK0
702 12:45:23.907629 [ModeRegInit_LP4] CH0 RK1
703 12:45:23.910592 [ModeRegInit_LP4] CH1 RK0
704 12:45:23.914780 [ModeRegInit_LP4] CH1 RK1
705 12:45:23.915207 match AC timing 13
706 12:45:23.918129 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:45:23.921454 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:45:23.928212 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:45:23.931736 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:45:23.938203 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:45:23.938781 [EMI DOE] emi_dcm 0
712 12:45:23.941812 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:45:23.945182 ==
714 12:45:23.945660 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:45:23.953150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:45:23.953730 ==
717 12:45:23.956472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:45:23.963062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:45:23.971712 [CA 0] Center 37 (6~68) winsize 63
720 12:45:23.975157 [CA 1] Center 36 (6~67) winsize 62
721 12:45:23.978096 [CA 2] Center 34 (4~65) winsize 62
722 12:45:23.981190 [CA 3] Center 34 (4~65) winsize 62
723 12:45:23.985046 [CA 4] Center 33 (3~64) winsize 62
724 12:45:23.988408 [CA 5] Center 33 (3~64) winsize 62
725 12:45:23.988934
726 12:45:23.991646 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:45:23.992103
728 12:45:23.995313 [CATrainingPosCal] consider 1 rank data
729 12:45:23.998276 u2DelayCellTimex100 = 270/100 ps
730 12:45:24.001586 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 12:45:24.005100 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 12:45:24.009285 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 12:45:24.014992 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:45:24.019057 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 12:45:24.021772 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:45:24.022243
737 12:45:24.025378 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:45:24.025865
739 12:45:24.028416 [CBTSetCACLKResult] CA Dly = 33
740 12:45:24.028907 CS Dly: 6 (0~37)
741 12:45:24.029282 ==
742 12:45:24.031352 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:45:24.038034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:45:24.038627 ==
745 12:45:24.041815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:45:24.048363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:45:24.057695 [CA 0] Center 37 (6~68) winsize 63
748 12:45:24.061069 [CA 1] Center 37 (7~68) winsize 62
749 12:45:24.064168 [CA 2] Center 34 (4~65) winsize 62
750 12:45:24.067969 [CA 3] Center 34 (4~65) winsize 62
751 12:45:24.071210 [CA 4] Center 33 (3~64) winsize 62
752 12:45:24.074228 [CA 5] Center 33 (3~64) winsize 62
753 12:45:24.074797
754 12:45:24.077401 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:45:24.077869
756 12:45:24.080652 [CATrainingPosCal] consider 2 rank data
757 12:45:24.084698 u2DelayCellTimex100 = 270/100 ps
758 12:45:24.087296 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 12:45:24.091132 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 12:45:24.094516 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 12:45:24.098425 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:45:24.101847 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 12:45:24.106463 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:45:24.107068
765 12:45:24.112577 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:45:24.113052
767 12:45:24.113429 [CBTSetCACLKResult] CA Dly = 33
768 12:45:24.116489 CS Dly: 6 (0~38)
769 12:45:24.117183
770 12:45:24.119306 ----->DramcWriteLeveling(PI) begin...
771 12:45:24.119953 ==
772 12:45:24.122594 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:45:24.126769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:45:24.127301 ==
775 12:45:24.129845 Write leveling (Byte 0): 30 => 30
776 12:45:24.132767 Write leveling (Byte 1): 30 => 30
777 12:45:24.136021 DramcWriteLeveling(PI) end<-----
778 12:45:24.136450
779 12:45:24.136849 ==
780 12:45:24.139189 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:45:24.142502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:45:24.142963 ==
783 12:45:24.146216 [Gating] SW mode calibration
784 12:45:24.152698 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:45:24.159077 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:45:24.162238 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:45:24.168918 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:45:24.172523 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 12:45:24.175491 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:45:24.182204 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:45:24.185742 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:45:24.188624 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:45:24.195635 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:45:24.198507 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:45:24.202309 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:45:24.205246 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:45:24.211689 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:45:24.215158 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:45:24.219003 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:45:24.225231 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:45:24.228557 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:45:24.232593 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:45:24.238350 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 12:45:24.242122 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 12:45:24.245408 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
806 12:45:24.251591 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:45:24.255113 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:45:24.258337 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:45:24.265054 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:45:24.268736 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:45:24.272190 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:45:24.278615 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
813 12:45:24.282122 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
814 12:45:24.285466 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:45:24.292470 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:45:24.295500 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:45:24.298979 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:45:24.305239 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:45:24.308416 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:45:24.311824 0 10 8 | B1->B0 | 3333 2929 | 0 0 | (0 0) (1 0)
821 12:45:24.318220 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
822 12:45:24.321757 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:45:24.325204 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:45:24.331715 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:45:24.334936 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:45:24.338958 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:45:24.345154 0 11 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
828 12:45:24.348422 0 11 8 | B1->B0 | 2929 3838 | 0 0 | (0 0) (0 0)
829 12:45:24.351867 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
830 12:45:24.358490 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:45:24.361832 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:45:24.365601 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:45:24.368365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:45:24.375395 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:45:24.378640 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:45:24.381579 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 12:45:24.387980 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:45:24.391406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:45:24.394776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:45:24.401527 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:45:24.404449 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:45:24.408003 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:45:24.415064 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:45:24.417934 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:45:24.421621 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:45:24.427683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:45:24.431547 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:45:24.434382 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:45:24.442020 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:45:24.445781 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:45:24.449800 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:45:24.453159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 12:45:24.457066 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 12:45:24.460217 Total UI for P1: 0, mck2ui 16
855 12:45:24.464081 best dqsien dly found for B0: ( 0, 14, 8)
856 12:45:24.467639 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:45:24.471090 Total UI for P1: 0, mck2ui 16
858 12:45:24.474544 best dqsien dly found for B1: ( 0, 14, 12)
859 12:45:24.478131 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 12:45:24.482317 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 12:45:24.482909
862 12:45:24.485615 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:45:24.489582 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 12:45:24.492967 [Gating] SW calibration Done
865 12:45:24.493391 ==
866 12:45:24.496605 Dram Type= 6, Freq= 0, CH_0, rank 0
867 12:45:24.500219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 12:45:24.500691 ==
869 12:45:24.501061 RX Vref Scan: 0
870 12:45:24.504197
871 12:45:24.504663 RX Vref 0 -> 0, step: 1
872 12:45:24.505013
873 12:45:24.507510 RX Delay -130 -> 252, step: 16
874 12:45:24.511300 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 12:45:24.514593 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 12:45:24.517527 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 12:45:24.523823 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 12:45:24.527535 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 12:45:24.530689 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 12:45:24.534208 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
881 12:45:24.537430 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 12:45:24.543809 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
883 12:45:24.547752 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
884 12:45:24.550993 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 12:45:24.554958 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 12:45:24.557828 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
887 12:45:24.561468 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
888 12:45:24.568879 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 12:45:24.572705 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
890 12:45:24.573259 ==
891 12:45:24.576285 Dram Type= 6, Freq= 0, CH_0, rank 0
892 12:45:24.580059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 12:45:24.580487 ==
894 12:45:24.580871 DQS Delay:
895 12:45:24.583368 DQS0 = 0, DQS1 = 0
896 12:45:24.583802 DQM Delay:
897 12:45:24.586931 DQM0 = 84, DQM1 = 71
898 12:45:24.587356 DQ Delay:
899 12:45:24.590472 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 12:45:24.592920 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
901 12:45:24.596177 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
902 12:45:24.599375 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
903 12:45:24.599804
904 12:45:24.600143
905 12:45:24.600458 ==
906 12:45:24.602916 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:45:24.605821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:45:24.606253 ==
909 12:45:24.606676
910 12:45:24.607012
911 12:45:24.610180 TX Vref Scan disable
912 12:45:24.612815 == TX Byte 0 ==
913 12:45:24.616219 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
914 12:45:24.619247 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
915 12:45:24.622975 == TX Byte 1 ==
916 12:45:24.626570 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 12:45:24.629333 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 12:45:24.629764 ==
919 12:45:24.632635 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:45:24.636176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:45:24.639236 ==
922 12:45:24.650698 TX Vref=22, minBit 11, minWin=26, winSum=439
923 12:45:24.654091 TX Vref=24, minBit 4, minWin=27, winSum=442
924 12:45:24.657039 TX Vref=26, minBit 5, minWin=27, winSum=445
925 12:45:24.660153 TX Vref=28, minBit 5, minWin=27, winSum=445
926 12:45:24.664024 TX Vref=30, minBit 9, minWin=27, winSum=443
927 12:45:24.667192 TX Vref=32, minBit 4, minWin=27, winSum=442
928 12:45:24.674244 [TxChooseVref] Worse bit 5, Min win 27, Win sum 445, Final Vref 26
929 12:45:24.674674
930 12:45:24.677320 Final TX Range 1 Vref 26
931 12:45:24.677753
932 12:45:24.678093 ==
933 12:45:24.680462 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:45:24.684271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:45:24.684728 ==
936 12:45:24.685073
937 12:45:24.685388
938 12:45:24.687030 TX Vref Scan disable
939 12:45:24.690321 == TX Byte 0 ==
940 12:45:24.693863 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
941 12:45:24.696955 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
942 12:45:24.700406 == TX Byte 1 ==
943 12:45:24.703578 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 12:45:24.707154 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 12:45:24.710817
946 12:45:24.711241 [DATLAT]
947 12:45:24.711580 Freq=800, CH0 RK0
948 12:45:24.712037
949 12:45:24.713651 DATLAT Default: 0xa
950 12:45:24.714077 0, 0xFFFF, sum = 0
951 12:45:24.717573 1, 0xFFFF, sum = 0
952 12:45:24.718018 2, 0xFFFF, sum = 0
953 12:45:24.720540 3, 0xFFFF, sum = 0
954 12:45:24.720978 4, 0xFFFF, sum = 0
955 12:45:24.723590 5, 0xFFFF, sum = 0
956 12:45:24.724016 6, 0xFFFF, sum = 0
957 12:45:24.727028 7, 0xFFFF, sum = 0
958 12:45:24.730348 8, 0xFFFF, sum = 0
959 12:45:24.730776 9, 0x0, sum = 1
960 12:45:24.731121 10, 0x0, sum = 2
961 12:45:24.733925 11, 0x0, sum = 3
962 12:45:24.734355 12, 0x0, sum = 4
963 12:45:24.737256 best_step = 10
964 12:45:24.737678
965 12:45:24.738013 ==
966 12:45:24.740133 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:45:24.743506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:45:24.743933 ==
969 12:45:24.747099 RX Vref Scan: 1
970 12:45:24.747523
971 12:45:24.747858 Set Vref Range= 32 -> 127
972 12:45:24.748169
973 12:45:24.750260 RX Vref 32 -> 127, step: 1
974 12:45:24.750685
975 12:45:24.753487 RX Delay -111 -> 252, step: 8
976 12:45:24.753913
977 12:45:24.756578 Set Vref, RX VrefLevel [Byte0]: 32
978 12:45:24.760335 [Byte1]: 32
979 12:45:24.760802
980 12:45:24.764044 Set Vref, RX VrefLevel [Byte0]: 33
981 12:45:24.766930 [Byte1]: 33
982 12:45:24.771482
983 12:45:24.771904 Set Vref, RX VrefLevel [Byte0]: 34
984 12:45:24.774094 [Byte1]: 34
985 12:45:24.778597
986 12:45:24.779019 Set Vref, RX VrefLevel [Byte0]: 35
987 12:45:24.781445 [Byte1]: 35
988 12:45:24.786335
989 12:45:24.786761 Set Vref, RX VrefLevel [Byte0]: 36
990 12:45:24.789183 [Byte1]: 36
991 12:45:24.793492
992 12:45:24.793915 Set Vref, RX VrefLevel [Byte0]: 37
993 12:45:24.797289 [Byte1]: 37
994 12:45:24.801544
995 12:45:24.801964 Set Vref, RX VrefLevel [Byte0]: 38
996 12:45:24.804705 [Byte1]: 38
997 12:45:24.809087
998 12:45:24.809560 Set Vref, RX VrefLevel [Byte0]: 39
999 12:45:24.812310 [Byte1]: 39
1000 12:45:24.816307
1001 12:45:24.816774 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:45:24.822967 [Byte1]: 40
1003 12:45:24.823394
1004 12:45:24.826332 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:45:24.829793 [Byte1]: 41
1006 12:45:24.830220
1007 12:45:24.833362 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:45:24.836242 [Byte1]: 42
1009 12:45:24.839347
1010 12:45:24.839766 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:45:24.843053 [Byte1]: 43
1012 12:45:24.847315
1013 12:45:24.847736 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:45:24.851130 [Byte1]: 44
1015 12:45:24.854742
1016 12:45:24.855164 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:45:24.857907 [Byte1]: 45
1018 12:45:24.862742
1019 12:45:24.863187 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:45:24.865858 [Byte1]: 46
1021 12:45:24.870179
1022 12:45:24.870602 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:45:24.873730 [Byte1]: 47
1024 12:45:24.878001
1025 12:45:24.878453 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:45:24.880970 [Byte1]: 48
1027 12:45:24.885723
1028 12:45:24.886138 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:45:24.888781 [Byte1]: 49
1030 12:45:24.893105
1031 12:45:24.893559 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:45:24.896387 [Byte1]: 50
1033 12:45:24.900484
1034 12:45:24.900936 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:45:24.904136 [Byte1]: 51
1036 12:45:24.908567
1037 12:45:24.908985 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:45:24.911624 [Byte1]: 52
1039 12:45:24.916089
1040 12:45:24.916505 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:45:24.919267 [Byte1]: 53
1042 12:45:24.923967
1043 12:45:24.924382 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:45:24.927122 [Byte1]: 54
1045 12:45:24.931065
1046 12:45:24.931516 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:45:24.934684 [Byte1]: 55
1048 12:45:24.939253
1049 12:45:24.939667 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:45:24.942480 [Byte1]: 56
1051 12:45:24.946519
1052 12:45:24.946932 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:45:24.949821 [Byte1]: 57
1054 12:45:24.954092
1055 12:45:24.954507 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:45:24.957526 [Byte1]: 58
1057 12:45:24.961704
1058 12:45:24.962120 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:45:24.965376 [Byte1]: 59
1060 12:45:24.969903
1061 12:45:24.970320 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:45:24.973296 [Byte1]: 60
1063 12:45:24.977503
1064 12:45:24.977959 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:45:24.980932 [Byte1]: 61
1066 12:45:24.984749
1067 12:45:24.985164 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:45:24.988167 [Byte1]: 62
1069 12:45:24.992336
1070 12:45:24.995996 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:45:24.999191 [Byte1]: 63
1072 12:45:24.999613
1073 12:45:25.002831 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:45:25.006219 [Byte1]: 64
1075 12:45:25.006693
1076 12:45:25.009803 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:45:25.013472 [Byte1]: 65
1078 12:45:25.013887
1079 12:45:25.016770 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:45:25.019962 [Byte1]: 66
1081 12:45:25.020432
1082 12:45:25.023628 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:45:25.027231 [Byte1]: 67
1084 12:45:25.030911
1085 12:45:25.031324 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:45:25.034172 [Byte1]: 68
1087 12:45:25.038665
1088 12:45:25.039086 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:45:25.042235 [Byte1]: 69
1090 12:45:25.045622
1091 12:45:25.049295 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:45:25.049804 [Byte1]: 70
1093 12:45:25.053938
1094 12:45:25.054388 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:45:25.057244 [Byte1]: 71
1096 12:45:25.061699
1097 12:45:25.062169 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:45:25.065198 [Byte1]: 72
1099 12:45:25.069283
1100 12:45:25.069788 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:45:25.072383 [Byte1]: 73
1102 12:45:25.077579
1103 12:45:25.078094 Set Vref, RX VrefLevel [Byte0]: 74
1104 12:45:25.080376 [Byte1]: 74
1105 12:45:25.085006
1106 12:45:25.085493 Set Vref, RX VrefLevel [Byte0]: 75
1107 12:45:25.087659 [Byte1]: 75
1108 12:45:25.092084
1109 12:45:25.092714 Set Vref, RX VrefLevel [Byte0]: 76
1110 12:45:25.095466 [Byte1]: 76
1111 12:45:25.100056
1112 12:45:25.100684 Set Vref, RX VrefLevel [Byte0]: 77
1113 12:45:25.102976 [Byte1]: 77
1114 12:45:25.107453
1115 12:45:25.107895 Set Vref, RX VrefLevel [Byte0]: 78
1116 12:45:25.110860 [Byte1]: 78
1117 12:45:25.114985
1118 12:45:25.115544 Set Vref, RX VrefLevel [Byte0]: 79
1119 12:45:25.118432 [Byte1]: 79
1120 12:45:25.122125
1121 12:45:25.122586 Set Vref, RX VrefLevel [Byte0]: 80
1122 12:45:25.125539 [Byte1]: 80
1123 12:45:25.130266
1124 12:45:25.130803 Final RX Vref Byte 0 = 66 to rank0
1125 12:45:25.133360 Final RX Vref Byte 1 = 51 to rank0
1126 12:45:25.136593 Final RX Vref Byte 0 = 66 to rank1
1127 12:45:25.140049 Final RX Vref Byte 1 = 51 to rank1==
1128 12:45:25.143693 Dram Type= 6, Freq= 0, CH_0, rank 0
1129 12:45:25.150181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 12:45:25.150666 ==
1131 12:45:25.151030 DQS Delay:
1132 12:45:25.151382 DQS0 = 0, DQS1 = 0
1133 12:45:25.153680 DQM Delay:
1134 12:45:25.154135 DQM0 = 87, DQM1 = 76
1135 12:45:25.156819 DQ Delay:
1136 12:45:25.160111 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1137 12:45:25.163128 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1138 12:45:25.166645 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1139 12:45:25.169706 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1140 12:45:25.170241
1141 12:45:25.170732
1142 12:45:25.176507 [DQSOSCAuto] RK0, (LSB)MR18= 0x4223, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1143 12:45:25.179539 CH0 RK0: MR19=606, MR18=4223
1144 12:45:25.187132 CH0_RK0: MR19=0x606, MR18=0x4223, DQSOSC=393, MR23=63, INC=95, DEC=63
1145 12:45:25.187678
1146 12:45:25.189652 ----->DramcWriteLeveling(PI) begin...
1147 12:45:25.190212 ==
1148 12:45:25.193030 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 12:45:25.196277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 12:45:25.196782 ==
1151 12:45:25.199758 Write leveling (Byte 0): 34 => 34
1152 12:45:25.203249 Write leveling (Byte 1): 29 => 29
1153 12:45:25.206802 DramcWriteLeveling(PI) end<-----
1154 12:45:25.207182
1155 12:45:25.207497 ==
1156 12:45:25.209914 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 12:45:25.213280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 12:45:25.213763 ==
1159 12:45:25.216374 [Gating] SW mode calibration
1160 12:45:25.263621 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1161 12:45:25.264559 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1162 12:45:25.264984 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 12:45:25.265359 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1164 12:45:25.265780 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1165 12:45:25.266124 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:45:25.266667 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:45:25.267157 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:45:25.267633 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:45:25.268100 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:45:25.278342 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:45:25.279081 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:45:25.281505 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:45:25.281958 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:45:25.285074 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:45:25.291520 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:45:25.296120 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:45:25.298356 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:45:25.304877 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:45:25.308290 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1180 12:45:25.311851 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1181 12:45:25.318273 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:45:25.321908 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:45:25.324983 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:45:25.331487 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:45:25.335043 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:45:25.337792 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:45:25.345334 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:45:25.348075 0 9 8 | B1->B0 | 2424 3030 | 1 1 | (1 1) (1 1)
1189 12:45:25.351449 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1190 12:45:25.354819 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 12:45:25.361901 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 12:45:25.365180 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 12:45:25.368299 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 12:45:25.374991 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 12:45:25.378068 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1196 12:45:25.381245 0 10 8 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
1197 12:45:25.387906 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1198 12:45:25.391613 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 12:45:25.394260 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 12:45:25.400864 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:45:25.404886 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:45:25.408125 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:45:25.414866 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1204 12:45:25.417613 0 11 8 | B1->B0 | 2f2f 4242 | 0 1 | (0 0) (0 0)
1205 12:45:25.420881 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1206 12:45:25.427649 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 12:45:25.431261 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 12:45:25.434323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 12:45:25.440801 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:45:25.444661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 12:45:25.447681 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1212 12:45:25.454456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1213 12:45:25.458169 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1214 12:45:25.462027 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:45:25.465489 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:45:25.471493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:45:25.475075 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:45:25.479373 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:45:25.485692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:45:25.489221 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:45:25.493130 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:45:25.496393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:45:25.502961 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:45:25.507046 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:45:25.510444 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:45:25.514070 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:45:25.517570 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:45:25.525195 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1229 12:45:25.528760 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 12:45:25.532107 Total UI for P1: 0, mck2ui 16
1231 12:45:25.535913 best dqsien dly found for B0: ( 0, 14, 8)
1232 12:45:25.536332 Total UI for P1: 0, mck2ui 16
1233 12:45:25.539447 best dqsien dly found for B1: ( 0, 14, 8)
1234 12:45:25.543212 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1235 12:45:25.547204 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1236 12:45:25.547621
1237 12:45:25.550825 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1238 12:45:25.554446 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1239 12:45:25.557924 [Gating] SW calibration Done
1240 12:45:25.558345 ==
1241 12:45:25.561886 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 12:45:25.565210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 12:45:25.565630 ==
1244 12:45:25.568813 RX Vref Scan: 0
1245 12:45:25.569255
1246 12:45:25.569585 RX Vref 0 -> 0, step: 1
1247 12:45:25.569894
1248 12:45:25.572665 RX Delay -130 -> 252, step: 16
1249 12:45:25.576226 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1250 12:45:25.579676 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1251 12:45:25.583556 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1252 12:45:25.587184 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1253 12:45:25.593902 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1254 12:45:25.597830 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1255 12:45:25.601425 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1256 12:45:25.605474 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1257 12:45:25.608812 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1258 12:45:25.612913 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1259 12:45:25.616650 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1260 12:45:25.619389 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1261 12:45:25.623511 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1262 12:45:25.627206 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1263 12:45:25.634523 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1264 12:45:25.638149 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1265 12:45:25.638601 ==
1266 12:45:25.641543 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 12:45:25.645840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 12:45:25.646379 ==
1269 12:45:25.646736 DQS Delay:
1270 12:45:25.649926 DQS0 = 0, DQS1 = 0
1271 12:45:25.650466 DQM Delay:
1272 12:45:25.650880 DQM0 = 85, DQM1 = 77
1273 12:45:25.652880 DQ Delay:
1274 12:45:25.653452 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1275 12:45:25.656321 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1276 12:45:25.659965 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1277 12:45:25.663533 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1278 12:45:25.664146
1279 12:45:25.664493
1280 12:45:25.664839 ==
1281 12:45:25.667295 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 12:45:25.671286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 12:45:25.671888 ==
1284 12:45:25.672413
1285 12:45:25.674788
1286 12:45:25.675220 TX Vref Scan disable
1287 12:45:25.678912 == TX Byte 0 ==
1288 12:45:25.681925 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1289 12:45:25.685847 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1290 12:45:25.686275 == TX Byte 1 ==
1291 12:45:25.693130 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1292 12:45:25.697030 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1293 12:45:25.697453 ==
1294 12:45:25.700234 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 12:45:25.703799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 12:45:25.704208 ==
1297 12:45:25.716998 TX Vref=22, minBit 3, minWin=27, winSum=441
1298 12:45:25.720808 TX Vref=24, minBit 3, minWin=27, winSum=444
1299 12:45:25.724491 TX Vref=26, minBit 3, minWin=27, winSum=445
1300 12:45:25.728159 TX Vref=28, minBit 9, minWin=27, winSum=448
1301 12:45:25.731626 TX Vref=30, minBit 9, minWin=27, winSum=449
1302 12:45:25.735140 TX Vref=32, minBit 0, minWin=27, winSum=447
1303 12:45:25.742832 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 30
1304 12:45:25.743287
1305 12:45:25.743542 Final TX Range 1 Vref 30
1306 12:45:25.743762
1307 12:45:25.743970 ==
1308 12:45:25.746335 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 12:45:25.750474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 12:45:25.750852 ==
1311 12:45:25.751146
1312 12:45:25.754327
1313 12:45:25.754774 TX Vref Scan disable
1314 12:45:25.758028 == TX Byte 0 ==
1315 12:45:25.761783 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1316 12:45:25.765442 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1317 12:45:25.765899 == TX Byte 1 ==
1318 12:45:25.772192 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1319 12:45:25.775814 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1320 12:45:25.776224
1321 12:45:25.776640 [DATLAT]
1322 12:45:25.779492 Freq=800, CH0 RK1
1323 12:45:25.780002
1324 12:45:25.780332 DATLAT Default: 0xa
1325 12:45:25.783176 0, 0xFFFF, sum = 0
1326 12:45:25.783806 1, 0xFFFF, sum = 0
1327 12:45:25.786829 2, 0xFFFF, sum = 0
1328 12:45:25.787430 3, 0xFFFF, sum = 0
1329 12:45:25.787906 4, 0xFFFF, sum = 0
1330 12:45:25.790576 5, 0xFFFF, sum = 0
1331 12:45:25.791185 6, 0xFFFF, sum = 0
1332 12:45:25.793853 7, 0xFFFF, sum = 0
1333 12:45:25.794505 8, 0xFFFF, sum = 0
1334 12:45:25.797655 9, 0x0, sum = 1
1335 12:45:25.798216 10, 0x0, sum = 2
1336 12:45:25.801490 11, 0x0, sum = 3
1337 12:45:25.802030 12, 0x0, sum = 4
1338 12:45:25.802518 best_step = 10
1339 12:45:25.802955
1340 12:45:25.804379 ==
1341 12:45:25.808199 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 12:45:25.811346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 12:45:25.812009 ==
1344 12:45:25.812645 RX Vref Scan: 0
1345 12:45:25.812972
1346 12:45:25.814516 RX Vref 0 -> 0, step: 1
1347 12:45:25.815043
1348 12:45:25.817880 RX Delay -111 -> 252, step: 8
1349 12:45:25.821219 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1350 12:45:25.827672 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1351 12:45:25.831189 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1352 12:45:25.834571 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1353 12:45:25.837616 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1354 12:45:25.841080 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1355 12:45:25.847667 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1356 12:45:25.850851 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1357 12:45:25.854195 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1358 12:45:25.857964 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1359 12:45:25.861312 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1360 12:45:25.868275 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1361 12:45:25.870942 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1362 12:45:25.874287 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1363 12:45:25.877852 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1364 12:45:25.880924 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1365 12:45:25.883838 ==
1366 12:45:25.887786 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 12:45:25.890856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 12:45:25.891442 ==
1369 12:45:25.891784 DQS Delay:
1370 12:45:25.894175 DQS0 = 0, DQS1 = 0
1371 12:45:25.894588 DQM Delay:
1372 12:45:25.897422 DQM0 = 86, DQM1 = 77
1373 12:45:25.897833 DQ Delay:
1374 12:45:25.900665 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1375 12:45:25.904190 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1376 12:45:25.907383 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1377 12:45:25.910880 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1378 12:45:25.911419
1379 12:45:25.911826
1380 12:45:25.917590 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1381 12:45:25.921557 CH0 RK1: MR19=606, MR18=3D04
1382 12:45:25.927216 CH0_RK1: MR19=0x606, MR18=0x3D04, DQSOSC=394, MR23=63, INC=95, DEC=63
1383 12:45:25.931066 [RxdqsGatingPostProcess] freq 800
1384 12:45:25.937228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1385 12:45:25.937732 Pre-setting of DQS Precalculation
1386 12:45:25.944038 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1387 12:45:25.944479 ==
1388 12:45:25.947242 Dram Type= 6, Freq= 0, CH_1, rank 0
1389 12:45:25.950286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 12:45:25.950839 ==
1391 12:45:25.956771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 12:45:25.963698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 12:45:25.972634 [CA 0] Center 36 (6~67) winsize 62
1394 12:45:25.975554 [CA 1] Center 36 (6~67) winsize 62
1395 12:45:25.978393 [CA 2] Center 34 (4~65) winsize 62
1396 12:45:25.981488 [CA 3] Center 34 (3~65) winsize 63
1397 12:45:25.985060 [CA 4] Center 34 (4~65) winsize 62
1398 12:45:25.988916 [CA 5] Center 34 (3~65) winsize 63
1399 12:45:25.989340
1400 12:45:25.991609 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1401 12:45:25.992029
1402 12:45:25.995482 [CATrainingPosCal] consider 1 rank data
1403 12:45:25.998061 u2DelayCellTimex100 = 270/100 ps
1404 12:45:26.001654 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1405 12:45:26.008024 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1406 12:45:26.011820 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 12:45:26.015108 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1408 12:45:26.018572 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1409 12:45:26.021571 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1410 12:45:26.022111
1411 12:45:26.025060 CA PerBit enable=1, Macro0, CA PI delay=34
1412 12:45:26.025478
1413 12:45:26.027903 [CBTSetCACLKResult] CA Dly = 34
1414 12:45:26.031273 CS Dly: 4 (0~35)
1415 12:45:26.031776 ==
1416 12:45:26.035085 Dram Type= 6, Freq= 0, CH_1, rank 1
1417 12:45:26.038534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 12:45:26.038955 ==
1419 12:45:26.044604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 12:45:26.047775 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 12:45:26.058145 [CA 0] Center 36 (6~67) winsize 62
1422 12:45:26.061433 [CA 1] Center 37 (6~68) winsize 63
1423 12:45:26.064755 [CA 2] Center 34 (4~65) winsize 62
1424 12:45:26.067981 [CA 3] Center 34 (3~65) winsize 63
1425 12:45:26.071248 [CA 4] Center 34 (4~65) winsize 62
1426 12:45:26.074563 [CA 5] Center 34 (4~64) winsize 61
1427 12:45:26.075109
1428 12:45:26.078395 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1429 12:45:26.078813
1430 12:45:26.081081 [CATrainingPosCal] consider 2 rank data
1431 12:45:26.084387 u2DelayCellTimex100 = 270/100 ps
1432 12:45:26.087693 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 12:45:26.094189 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 12:45:26.097539 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 12:45:26.100781 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1436 12:45:26.104333 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 12:45:26.107599 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1438 12:45:26.108114
1439 12:45:26.110877 CA PerBit enable=1, Macro0, CA PI delay=34
1440 12:45:26.111322
1441 12:45:26.114108 [CBTSetCACLKResult] CA Dly = 34
1442 12:45:26.117603 CS Dly: 5 (0~38)
1443 12:45:26.118039
1444 12:45:26.120622 ----->DramcWriteLeveling(PI) begin...
1445 12:45:26.121066 ==
1446 12:45:26.124332 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 12:45:26.127732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 12:45:26.128170 ==
1449 12:45:26.130598 Write leveling (Byte 0): 29 => 29
1450 12:45:26.133817 Write leveling (Byte 1): 28 => 28
1451 12:45:26.137556 DramcWriteLeveling(PI) end<-----
1452 12:45:26.138137
1453 12:45:26.138490 ==
1454 12:45:26.141263 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 12:45:26.144148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 12:45:26.144636 ==
1457 12:45:26.147123 [Gating] SW mode calibration
1458 12:45:26.154326 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1459 12:45:26.160350 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1460 12:45:26.164022 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1461 12:45:26.167311 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1462 12:45:26.174009 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:45:26.177103 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:45:26.180301 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:45:26.187156 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:45:26.190650 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:45:26.193893 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:45:26.200350 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:45:26.203626 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:45:26.206746 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:45:26.213458 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:45:26.216689 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:45:26.220291 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:45:26.226985 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:45:26.230287 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:45:26.233490 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1477 12:45:26.240256 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1478 12:45:26.243416 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:45:26.246662 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:45:26.253636 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:45:26.256426 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:45:26.260104 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:45:26.263387 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:45:26.270005 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:45:26.273748 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:45:26.277177 0 9 8 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
1487 12:45:26.283301 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 12:45:26.286583 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 12:45:26.290206 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 12:45:26.296184 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 12:45:26.299748 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 12:45:26.303526 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 12:45:26.309504 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
1494 12:45:26.313417 0 10 8 | B1->B0 | 2828 2929 | 0 0 | (0 0) (0 0)
1495 12:45:26.316071 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 12:45:26.322967 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 12:45:26.326680 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:45:26.329541 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:45:26.336573 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:45:26.340247 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:45:26.342442 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
1502 12:45:26.349389 0 11 8 | B1->B0 | 3a3a 3d3d | 0 0 | (0 0) (0 0)
1503 12:45:26.352278 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 12:45:26.356053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 12:45:26.362470 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 12:45:26.365666 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 12:45:26.368894 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 12:45:26.375438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1509 12:45:26.379382 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1510 12:45:26.382192 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:45:26.388787 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:45:26.391848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:45:26.395184 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:45:26.402128 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:45:26.405626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:45:26.408576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:45:26.414956 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:45:26.418463 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:45:26.422109 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:45:26.428272 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:45:26.431701 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:45:26.434941 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:45:26.442028 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:45:26.445274 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:45:26.448633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1526 12:45:26.455535 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 12:45:26.455998 Total UI for P1: 0, mck2ui 16
1528 12:45:26.461579 best dqsien dly found for B0: ( 0, 14, 4)
1529 12:45:26.462154 Total UI for P1: 0, mck2ui 16
1530 12:45:26.468369 best dqsien dly found for B1: ( 0, 14, 4)
1531 12:45:26.472241 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1532 12:45:26.474927 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1533 12:45:26.475355
1534 12:45:26.478323 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1535 12:45:26.481505 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1536 12:45:26.485161 [Gating] SW calibration Done
1537 12:45:26.485593 ==
1538 12:45:26.488500 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 12:45:26.491730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1540 12:45:26.492173 ==
1541 12:45:26.495313 RX Vref Scan: 0
1542 12:45:26.495808
1543 12:45:26.496238 RX Vref 0 -> 0, step: 1
1544 12:45:26.496712
1545 12:45:26.498481 RX Delay -130 -> 252, step: 16
1546 12:45:26.501479 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1547 12:45:26.504995 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1548 12:45:26.511481 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1549 12:45:26.514773 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1550 12:45:26.517874 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1551 12:45:26.521442 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1552 12:45:26.527923 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1553 12:45:26.531083 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1554 12:45:26.534328 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1555 12:45:26.537319 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1556 12:45:26.541282 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1557 12:45:26.547155 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1558 12:45:26.550944 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1559 12:45:26.554101 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1560 12:45:26.557461 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1561 12:45:26.564021 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1562 12:45:26.564133 ==
1563 12:45:26.567363 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 12:45:26.570663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 12:45:26.570772 ==
1566 12:45:26.570865 DQS Delay:
1567 12:45:26.573933 DQS0 = 0, DQS1 = 0
1568 12:45:26.574015 DQM Delay:
1569 12:45:26.577530 DQM0 = 88, DQM1 = 79
1570 12:45:26.577613 DQ Delay:
1571 12:45:26.580931 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1572 12:45:26.584016 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1573 12:45:26.587694 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1574 12:45:26.590645 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1575 12:45:26.590729
1576 12:45:26.590794
1577 12:45:26.590856 ==
1578 12:45:26.593874 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 12:45:26.597019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 12:45:26.597127 ==
1581 12:45:26.600409
1582 12:45:26.600558
1583 12:45:26.600628 TX Vref Scan disable
1584 12:45:26.603809 == TX Byte 0 ==
1585 12:45:26.606981 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1586 12:45:26.610331 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1587 12:45:26.613999 == TX Byte 1 ==
1588 12:45:26.616694 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1589 12:45:26.620701 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1590 12:45:26.623615 ==
1591 12:45:26.623697 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 12:45:26.630660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 12:45:26.630764 ==
1594 12:45:26.642427 TX Vref=22, minBit 8, minWin=27, winSum=443
1595 12:45:26.645424 TX Vref=24, minBit 8, minWin=27, winSum=444
1596 12:45:26.648937 TX Vref=26, minBit 9, minWin=27, winSum=450
1597 12:45:26.652395 TX Vref=28, minBit 8, minWin=27, winSum=450
1598 12:45:26.655966 TX Vref=30, minBit 10, minWin=27, winSum=449
1599 12:45:26.662402 TX Vref=32, minBit 8, minWin=27, winSum=447
1600 12:45:26.665633 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 26
1601 12:45:26.665747
1602 12:45:26.669279 Final TX Range 1 Vref 26
1603 12:45:26.669363
1604 12:45:26.669428 ==
1605 12:45:26.672304 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 12:45:26.675730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 12:45:26.678585 ==
1608 12:45:26.678692
1609 12:45:26.678785
1610 12:45:26.678873 TX Vref Scan disable
1611 12:45:26.682473 == TX Byte 0 ==
1612 12:45:26.685937 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1613 12:45:26.688991 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1614 12:45:26.692339 == TX Byte 1 ==
1615 12:45:26.695628 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1616 12:45:26.702311 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1617 12:45:26.702389
1618 12:45:26.702452 [DATLAT]
1619 12:45:26.702511 Freq=800, CH1 RK0
1620 12:45:26.702569
1621 12:45:26.705745 DATLAT Default: 0xa
1622 12:45:26.705828 0, 0xFFFF, sum = 0
1623 12:45:26.709133 1, 0xFFFF, sum = 0
1624 12:45:26.709216 2, 0xFFFF, sum = 0
1625 12:45:26.712137 3, 0xFFFF, sum = 0
1626 12:45:26.715744 4, 0xFFFF, sum = 0
1627 12:45:26.715818 5, 0xFFFF, sum = 0
1628 12:45:26.719093 6, 0xFFFF, sum = 0
1629 12:45:26.719177 7, 0xFFFF, sum = 0
1630 12:45:26.722136 8, 0xFFFF, sum = 0
1631 12:45:26.722245 9, 0x0, sum = 1
1632 12:45:26.725707 10, 0x0, sum = 2
1633 12:45:26.725807 11, 0x0, sum = 3
1634 12:45:26.725898 12, 0x0, sum = 4
1635 12:45:26.728954 best_step = 10
1636 12:45:26.729025
1637 12:45:26.729086 ==
1638 12:45:26.732062 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 12:45:26.735296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 12:45:26.735370 ==
1641 12:45:26.739275 RX Vref Scan: 1
1642 12:45:26.739344
1643 12:45:26.742379 Set Vref Range= 32 -> 127
1644 12:45:26.742486
1645 12:45:26.742581 RX Vref 32 -> 127, step: 1
1646 12:45:26.742645
1647 12:45:26.745361 RX Delay -95 -> 252, step: 8
1648 12:45:26.745432
1649 12:45:26.748825 Set Vref, RX VrefLevel [Byte0]: 32
1650 12:45:26.752058 [Byte1]: 32
1651 12:45:26.752140
1652 12:45:26.755333 Set Vref, RX VrefLevel [Byte0]: 33
1653 12:45:26.758792 [Byte1]: 33
1654 12:45:26.762484
1655 12:45:26.762566 Set Vref, RX VrefLevel [Byte0]: 34
1656 12:45:26.765976 [Byte1]: 34
1657 12:45:26.770700
1658 12:45:26.770782 Set Vref, RX VrefLevel [Byte0]: 35
1659 12:45:26.773612 [Byte1]: 35
1660 12:45:26.777699
1661 12:45:26.777781 Set Vref, RX VrefLevel [Byte0]: 36
1662 12:45:26.781426 [Byte1]: 36
1663 12:45:26.785299
1664 12:45:26.785381 Set Vref, RX VrefLevel [Byte0]: 37
1665 12:45:26.789056 [Byte1]: 37
1666 12:45:26.793048
1667 12:45:26.793133 Set Vref, RX VrefLevel [Byte0]: 38
1668 12:45:26.796248 [Byte1]: 38
1669 12:45:26.800725
1670 12:45:26.800812 Set Vref, RX VrefLevel [Byte0]: 39
1671 12:45:26.803732 [Byte1]: 39
1672 12:45:26.808056
1673 12:45:26.808154 Set Vref, RX VrefLevel [Byte0]: 40
1674 12:45:26.811459 [Byte1]: 40
1675 12:45:26.815844
1676 12:45:26.815926 Set Vref, RX VrefLevel [Byte0]: 41
1677 12:45:26.819748 [Byte1]: 41
1678 12:45:26.823623
1679 12:45:26.823704 Set Vref, RX VrefLevel [Byte0]: 42
1680 12:45:26.826568 [Byte1]: 42
1681 12:45:26.830756
1682 12:45:26.830866 Set Vref, RX VrefLevel [Byte0]: 43
1683 12:45:26.834147 [Byte1]: 43
1684 12:45:26.838822
1685 12:45:26.841785 Set Vref, RX VrefLevel [Byte0]: 44
1686 12:45:26.841868 [Byte1]: 44
1687 12:45:26.846488
1688 12:45:26.846572 Set Vref, RX VrefLevel [Byte0]: 45
1689 12:45:26.849855 [Byte1]: 45
1690 12:45:26.853952
1691 12:45:26.854062 Set Vref, RX VrefLevel [Byte0]: 46
1692 12:45:26.857187 [Byte1]: 46
1693 12:45:26.861846
1694 12:45:26.861928 Set Vref, RX VrefLevel [Byte0]: 47
1695 12:45:26.864868 [Byte1]: 47
1696 12:45:26.869809
1697 12:45:26.869920 Set Vref, RX VrefLevel [Byte0]: 48
1698 12:45:26.872313 [Byte1]: 48
1699 12:45:26.876402
1700 12:45:26.876522 Set Vref, RX VrefLevel [Byte0]: 49
1701 12:45:26.879996 [Byte1]: 49
1702 12:45:26.884177
1703 12:45:26.884283 Set Vref, RX VrefLevel [Byte0]: 50
1704 12:45:26.887252 [Byte1]: 50
1705 12:45:26.891928
1706 12:45:26.892001 Set Vref, RX VrefLevel [Byte0]: 51
1707 12:45:26.895209 [Byte1]: 51
1708 12:45:26.899227
1709 12:45:26.899298 Set Vref, RX VrefLevel [Byte0]: 52
1710 12:45:26.903018 [Byte1]: 52
1711 12:45:26.906902
1712 12:45:26.906971 Set Vref, RX VrefLevel [Byte0]: 53
1713 12:45:26.910309 [Byte1]: 53
1714 12:45:26.914773
1715 12:45:26.914849 Set Vref, RX VrefLevel [Byte0]: 54
1716 12:45:26.917919 [Byte1]: 54
1717 12:45:26.922042
1718 12:45:26.922129 Set Vref, RX VrefLevel [Byte0]: 55
1719 12:45:26.925488 [Byte1]: 55
1720 12:45:26.929839
1721 12:45:26.929912 Set Vref, RX VrefLevel [Byte0]: 56
1722 12:45:26.933299 [Byte1]: 56
1723 12:45:26.937436
1724 12:45:26.941030 Set Vref, RX VrefLevel [Byte0]: 57
1725 12:45:26.943822 [Byte1]: 57
1726 12:45:26.943907
1727 12:45:26.947037 Set Vref, RX VrefLevel [Byte0]: 58
1728 12:45:26.950396 [Byte1]: 58
1729 12:45:26.950467
1730 12:45:26.953947 Set Vref, RX VrefLevel [Byte0]: 59
1731 12:45:26.957608 [Byte1]: 59
1732 12:45:26.957686
1733 12:45:26.960792 Set Vref, RX VrefLevel [Byte0]: 60
1734 12:45:26.963856 [Byte1]: 60
1735 12:45:26.968188
1736 12:45:26.968296 Set Vref, RX VrefLevel [Byte0]: 61
1737 12:45:26.971183 [Byte1]: 61
1738 12:45:26.975434
1739 12:45:26.975509 Set Vref, RX VrefLevel [Byte0]: 62
1740 12:45:26.978469 [Byte1]: 62
1741 12:45:26.982965
1742 12:45:26.983067 Set Vref, RX VrefLevel [Byte0]: 63
1743 12:45:26.986143 [Byte1]: 63
1744 12:45:26.990405
1745 12:45:26.990507 Set Vref, RX VrefLevel [Byte0]: 64
1746 12:45:26.993960 [Byte1]: 64
1747 12:45:26.997821
1748 12:45:26.997919 Set Vref, RX VrefLevel [Byte0]: 65
1749 12:45:27.001718 [Byte1]: 65
1750 12:45:27.005732
1751 12:45:27.005807 Set Vref, RX VrefLevel [Byte0]: 66
1752 12:45:27.008866 [Byte1]: 66
1753 12:45:27.013593
1754 12:45:27.013702 Set Vref, RX VrefLevel [Byte0]: 67
1755 12:45:27.016331 [Byte1]: 67
1756 12:45:27.021204
1757 12:45:27.021284 Set Vref, RX VrefLevel [Byte0]: 68
1758 12:45:27.024520 [Byte1]: 68
1759 12:45:27.028261
1760 12:45:27.028364 Set Vref, RX VrefLevel [Byte0]: 69
1761 12:45:27.032108 [Byte1]: 69
1762 12:45:27.036316
1763 12:45:27.039365 Set Vref, RX VrefLevel [Byte0]: 70
1764 12:45:27.043035 [Byte1]: 70
1765 12:45:27.043137
1766 12:45:27.045988 Set Vref, RX VrefLevel [Byte0]: 71
1767 12:45:27.049216 [Byte1]: 71
1768 12:45:27.049290
1769 12:45:27.052745 Set Vref, RX VrefLevel [Byte0]: 72
1770 12:45:27.055670 [Byte1]: 72
1771 12:45:27.055738
1772 12:45:27.059159 Set Vref, RX VrefLevel [Byte0]: 73
1773 12:45:27.062295 [Byte1]: 73
1774 12:45:27.066650
1775 12:45:27.066746 Set Vref, RX VrefLevel [Byte0]: 74
1776 12:45:27.069675 [Byte1]: 74
1777 12:45:27.074087
1778 12:45:27.074168 Set Vref, RX VrefLevel [Byte0]: 75
1779 12:45:27.077548 [Byte1]: 75
1780 12:45:27.081891
1781 12:45:27.081998 Final RX Vref Byte 0 = 56 to rank0
1782 12:45:27.084989 Final RX Vref Byte 1 = 63 to rank0
1783 12:45:27.088219 Final RX Vref Byte 0 = 56 to rank1
1784 12:45:27.091964 Final RX Vref Byte 1 = 63 to rank1==
1785 12:45:27.096402 Dram Type= 6, Freq= 0, CH_1, rank 0
1786 12:45:27.101873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 12:45:27.101962 ==
1788 12:45:27.102026 DQS Delay:
1789 12:45:27.102085 DQS0 = 0, DQS1 = 0
1790 12:45:27.105064 DQM Delay:
1791 12:45:27.105132 DQM0 = 86, DQM1 = 79
1792 12:45:27.108081 DQ Delay:
1793 12:45:27.111600 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1794 12:45:27.115052 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1795 12:45:27.118478 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1796 12:45:27.122293 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1797 12:45:27.122362
1798 12:45:27.122436
1799 12:45:27.128235 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1800 12:45:27.131542 CH1 RK0: MR19=606, MR18=2C18
1801 12:45:27.138572 CH1_RK0: MR19=0x606, MR18=0x2C18, DQSOSC=398, MR23=63, INC=93, DEC=62
1802 12:45:27.138645
1803 12:45:27.141292 ----->DramcWriteLeveling(PI) begin...
1804 12:45:27.141364 ==
1805 12:45:27.145201 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 12:45:27.148178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 12:45:27.148248 ==
1808 12:45:27.151446 Write leveling (Byte 0): 29 => 29
1809 12:45:27.154501 Write leveling (Byte 1): 30 => 30
1810 12:45:27.157980 DramcWriteLeveling(PI) end<-----
1811 12:45:27.158080
1812 12:45:27.158170 ==
1813 12:45:27.160945 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 12:45:27.164706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 12:45:27.164780 ==
1816 12:45:27.167576 [Gating] SW mode calibration
1817 12:45:27.174283 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1818 12:45:27.181272 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1819 12:45:27.184095 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1820 12:45:27.190856 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1821 12:45:27.194290 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:45:27.197490 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:45:27.204655 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:45:27.207252 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:45:27.210524 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:45:27.217257 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:45:27.220775 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:45:27.224194 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:45:27.230595 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:45:27.234518 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:45:27.237661 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:45:27.241549 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:45:27.247342 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:45:27.250822 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:45:27.254089 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:45:27.260415 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1837 12:45:27.263586 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:45:27.267032 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:45:27.273711 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:45:27.277274 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:45:27.280105 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:45:27.287291 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:45:27.290262 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:45:27.294203 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:45:27.300275 0 9 8 | B1->B0 | 2e2e 2626 | 1 1 | (1 1) (0 0)
1846 12:45:27.303367 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1847 12:45:27.306959 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 12:45:27.313393 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 12:45:27.316635 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 12:45:27.319861 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:45:27.327216 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 12:45:27.330330 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 12:45:27.333561 0 10 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 0)
1854 12:45:27.339768 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:45:27.342919 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:45:27.346263 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:45:27.353077 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:45:27.356441 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:45:27.359682 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:45:27.366178 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1861 12:45:27.369411 0 11 8 | B1->B0 | 4141 3838 | 0 1 | (1 1) (0 0)
1862 12:45:27.373016 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 12:45:27.379871 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 12:45:27.382984 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:45:27.386387 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:45:27.393208 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:45:27.396534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 12:45:27.399625 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1869 12:45:27.406364 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1870 12:45:27.409734 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:45:27.413107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:45:27.419667 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:45:27.422760 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:45:27.426430 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:45:27.429757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:45:27.436131 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:45:27.439805 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:45:27.443018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:45:27.450063 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:45:27.452779 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:45:27.456047 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:45:27.462929 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:45:27.466317 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:45:27.469560 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1885 12:45:27.475995 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1886 12:45:27.479545 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 12:45:27.482375 Total UI for P1: 0, mck2ui 16
1888 12:45:27.486338 best dqsien dly found for B0: ( 0, 14, 6)
1889 12:45:27.489209 Total UI for P1: 0, mck2ui 16
1890 12:45:27.492470 best dqsien dly found for B1: ( 0, 14, 6)
1891 12:45:27.495905 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1892 12:45:27.498845 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1893 12:45:27.498971
1894 12:45:27.502355 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1895 12:45:27.505568 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 12:45:27.508659 [Gating] SW calibration Done
1897 12:45:27.508820 ==
1898 12:45:27.512164 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 12:45:27.519243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 12:45:27.519420 ==
1901 12:45:27.519598 RX Vref Scan: 0
1902 12:45:27.519766
1903 12:45:27.522268 RX Vref 0 -> 0, step: 1
1904 12:45:27.522441
1905 12:45:27.525396 RX Delay -130 -> 252, step: 16
1906 12:45:27.528912 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1907 12:45:27.531868 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1908 12:45:27.535572 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1909 12:45:27.542553 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1910 12:45:27.545876 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1911 12:45:27.549160 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1912 12:45:27.552180 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1913 12:45:27.555199 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1914 12:45:27.562283 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1915 12:45:27.565317 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1916 12:45:27.568512 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1917 12:45:27.571999 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1918 12:45:27.578753 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1919 12:45:27.581457 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1920 12:45:27.585432 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1921 12:45:27.588471 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1922 12:45:27.589020 ==
1923 12:45:27.591793 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 12:45:27.594910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 12:45:27.598508 ==
1926 12:45:27.599086 DQS Delay:
1927 12:45:27.599430 DQS0 = 0, DQS1 = 0
1928 12:45:27.601753 DQM Delay:
1929 12:45:27.602246 DQM0 = 86, DQM1 = 78
1930 12:45:27.604795 DQ Delay:
1931 12:45:27.607991 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1932 12:45:27.611970 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1933 12:45:27.615166 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1934 12:45:27.618524 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1935 12:45:27.619011
1936 12:45:27.619474
1937 12:45:27.619920 ==
1938 12:45:27.621952 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 12:45:27.624982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 12:45:27.625424 ==
1941 12:45:27.625874
1942 12:45:27.626310
1943 12:45:27.628027 TX Vref Scan disable
1944 12:45:27.628475 == TX Byte 0 ==
1945 12:45:27.635046 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1946 12:45:27.638285 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1947 12:45:27.638713 == TX Byte 1 ==
1948 12:45:27.644892 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1949 12:45:27.647886 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1950 12:45:27.648302 ==
1951 12:45:27.651981 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 12:45:27.654833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 12:45:27.655252 ==
1954 12:45:27.668588 TX Vref=22, minBit 8, minWin=26, winSum=441
1955 12:45:27.672335 TX Vref=24, minBit 9, minWin=26, winSum=445
1956 12:45:27.675671 TX Vref=26, minBit 8, minWin=27, winSum=448
1957 12:45:27.678733 TX Vref=28, minBit 8, minWin=27, winSum=449
1958 12:45:27.681889 TX Vref=30, minBit 8, minWin=27, winSum=452
1959 12:45:27.688481 TX Vref=32, minBit 9, minWin=27, winSum=451
1960 12:45:27.692097 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 30
1961 12:45:27.692588
1962 12:45:27.695534 Final TX Range 1 Vref 30
1963 12:45:27.695950
1964 12:45:27.696273 ==
1965 12:45:27.698311 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 12:45:27.702020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 12:45:27.702445 ==
1968 12:45:27.705259
1969 12:45:27.705682
1970 12:45:27.706016 TX Vref Scan disable
1971 12:45:27.708679 == TX Byte 0 ==
1972 12:45:27.712014 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1973 12:45:27.715473 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1974 12:45:27.718474 == TX Byte 1 ==
1975 12:45:27.722074 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1976 12:45:27.728779 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1977 12:45:27.729346
1978 12:45:27.729839 [DATLAT]
1979 12:45:27.730169 Freq=800, CH1 RK1
1980 12:45:27.730477
1981 12:45:27.731969 DATLAT Default: 0xa
1982 12:45:27.732579 0, 0xFFFF, sum = 0
1983 12:45:27.735240 1, 0xFFFF, sum = 0
1984 12:45:27.735776 2, 0xFFFF, sum = 0
1985 12:45:27.738167 3, 0xFFFF, sum = 0
1986 12:45:27.741708 4, 0xFFFF, sum = 0
1987 12:45:27.742137 5, 0xFFFF, sum = 0
1988 12:45:27.744895 6, 0xFFFF, sum = 0
1989 12:45:27.745461 7, 0xFFFF, sum = 0
1990 12:45:27.748350 8, 0xFFFF, sum = 0
1991 12:45:27.748873 9, 0x0, sum = 1
1992 12:45:27.751644 10, 0x0, sum = 2
1993 12:45:27.752124 11, 0x0, sum = 3
1994 12:45:27.752719 12, 0x0, sum = 4
1995 12:45:27.755997 best_step = 10
1996 12:45:27.756577
1997 12:45:27.756932 ==
1998 12:45:27.758187 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 12:45:27.762067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 12:45:27.762632 ==
2001 12:45:27.765407 RX Vref Scan: 0
2002 12:45:27.765827
2003 12:45:27.766211 RX Vref 0 -> 0, step: 1
2004 12:45:27.768482
2005 12:45:27.769118 RX Delay -95 -> 252, step: 8
2006 12:45:27.775431 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2007 12:45:27.778635 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2008 12:45:27.782145 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2009 12:45:27.785575 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2010 12:45:27.788616 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2011 12:45:27.795669 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2012 12:45:27.798722 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2013 12:45:27.801940 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2014 12:45:27.805946 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2015 12:45:27.808835 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2016 12:45:27.815273 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2017 12:45:27.818859 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2018 12:45:27.821647 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2019 12:45:27.825018 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2020 12:45:27.831990 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2021 12:45:27.835133 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2022 12:45:27.835671 ==
2023 12:45:27.838255 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 12:45:27.841940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 12:45:27.842052 ==
2026 12:45:27.844665 DQS Delay:
2027 12:45:27.844736 DQS0 = 0, DQS1 = 0
2028 12:45:27.844797 DQM Delay:
2029 12:45:27.847738 DQM0 = 87, DQM1 = 78
2030 12:45:27.847826 DQ Delay:
2031 12:45:27.851325 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2032 12:45:27.854764 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2033 12:45:27.857849 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2034 12:45:27.861657 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2035 12:45:27.861738
2036 12:45:27.861800
2037 12:45:27.871282 [DQSOSCAuto] RK1, (LSB)MR18= 0x170f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2038 12:45:27.871372 CH1 RK1: MR19=606, MR18=170F
2039 12:45:27.877915 CH1_RK1: MR19=0x606, MR18=0x170F, DQSOSC=404, MR23=63, INC=90, DEC=60
2040 12:45:27.881075 [RxdqsGatingPostProcess] freq 800
2041 12:45:27.888066 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2042 12:45:27.891192 Pre-setting of DQS Precalculation
2043 12:45:27.894314 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2044 12:45:27.900967 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2045 12:45:27.911037 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2046 12:45:27.911120
2047 12:45:27.911184
2048 12:45:27.913993 [Calibration Summary] 1600 Mbps
2049 12:45:27.914074 CH 0, Rank 0
2050 12:45:27.917506 SW Impedance : PASS
2051 12:45:27.917588 DUTY Scan : NO K
2052 12:45:27.920694 ZQ Calibration : PASS
2053 12:45:27.923869 Jitter Meter : NO K
2054 12:45:27.923950 CBT Training : PASS
2055 12:45:27.927510 Write leveling : PASS
2056 12:45:27.931261 RX DQS gating : PASS
2057 12:45:27.931368 RX DQ/DQS(RDDQC) : PASS
2058 12:45:27.933875 TX DQ/DQS : PASS
2059 12:45:27.933957 RX DATLAT : PASS
2060 12:45:27.937228 RX DQ/DQS(Engine): PASS
2061 12:45:27.941114 TX OE : NO K
2062 12:45:27.941562 All Pass.
2063 12:45:27.941896
2064 12:45:27.944049 CH 0, Rank 1
2065 12:45:27.944587 SW Impedance : PASS
2066 12:45:27.947670 DUTY Scan : NO K
2067 12:45:27.948091 ZQ Calibration : PASS
2068 12:45:27.950935 Jitter Meter : NO K
2069 12:45:27.953971 CBT Training : PASS
2070 12:45:27.954542 Write leveling : PASS
2071 12:45:27.957635 RX DQS gating : PASS
2072 12:45:27.960822 RX DQ/DQS(RDDQC) : PASS
2073 12:45:27.961246 TX DQ/DQS : PASS
2074 12:45:27.964029 RX DATLAT : PASS
2075 12:45:27.966981 RX DQ/DQS(Engine): PASS
2076 12:45:27.967087 TX OE : NO K
2077 12:45:27.970656 All Pass.
2078 12:45:27.970736
2079 12:45:27.970800 CH 1, Rank 0
2080 12:45:27.973587 SW Impedance : PASS
2081 12:45:27.973667 DUTY Scan : NO K
2082 12:45:27.977086 ZQ Calibration : PASS
2083 12:45:27.980239 Jitter Meter : NO K
2084 12:45:27.980319 CBT Training : PASS
2085 12:45:27.983649 Write leveling : PASS
2086 12:45:27.987460 RX DQS gating : PASS
2087 12:45:27.987573 RX DQ/DQS(RDDQC) : PASS
2088 12:45:27.990717 TX DQ/DQS : PASS
2089 12:45:27.990823 RX DATLAT : PASS
2090 12:45:27.993666 RX DQ/DQS(Engine): PASS
2091 12:45:27.997159 TX OE : NO K
2092 12:45:27.997261 All Pass.
2093 12:45:27.997351
2094 12:45:27.997437 CH 1, Rank 1
2095 12:45:28.000630 SW Impedance : PASS
2096 12:45:28.003683 DUTY Scan : NO K
2097 12:45:28.003757 ZQ Calibration : PASS
2098 12:45:28.007204 Jitter Meter : NO K
2099 12:45:28.010382 CBT Training : PASS
2100 12:45:28.010463 Write leveling : PASS
2101 12:45:28.013815 RX DQS gating : PASS
2102 12:45:28.016908 RX DQ/DQS(RDDQC) : PASS
2103 12:45:28.016990 TX DQ/DQS : PASS
2104 12:45:28.020279 RX DATLAT : PASS
2105 12:45:28.023514 RX DQ/DQS(Engine): PASS
2106 12:45:28.023604 TX OE : NO K
2107 12:45:28.027658 All Pass.
2108 12:45:28.027738
2109 12:45:28.027827 DramC Write-DBI off
2110 12:45:28.030690 PER_BANK_REFRESH: Hybrid Mode
2111 12:45:28.030762 TX_TRACKING: ON
2112 12:45:28.033614 [GetDramInforAfterCalByMRR] Vendor 6.
2113 12:45:28.040373 [GetDramInforAfterCalByMRR] Revision 606.
2114 12:45:28.043565 [GetDramInforAfterCalByMRR] Revision 2 0.
2115 12:45:28.043670 MR0 0x3b3b
2116 12:45:28.043762 MR8 0x5151
2117 12:45:28.047166 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 12:45:28.047268
2119 12:45:28.050116 MR0 0x3b3b
2120 12:45:28.050196 MR8 0x5151
2121 12:45:28.053208 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 12:45:28.053290
2123 12:45:28.063400 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2124 12:45:28.066526 [FAST_K] Save calibration result to emmc
2125 12:45:28.069797 [FAST_K] Save calibration result to emmc
2126 12:45:28.073499 dram_init: config_dvfs: 1
2127 12:45:28.077006 dramc_set_vcore_voltage set vcore to 662500
2128 12:45:28.079984 Read voltage for 1200, 2
2129 12:45:28.080065 Vio18 = 0
2130 12:45:28.080165 Vcore = 662500
2131 12:45:28.083210 Vdram = 0
2132 12:45:28.083313 Vddq = 0
2133 12:45:28.083391 Vmddr = 0
2134 12:45:28.089640 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2135 12:45:28.093597 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2136 12:45:28.096563 MEM_TYPE=3, freq_sel=15
2137 12:45:28.100158 sv_algorithm_assistance_LP4_1600
2138 12:45:28.103355 ============ PULL DRAM RESETB DOWN ============
2139 12:45:28.106439 ========== PULL DRAM RESETB DOWN end =========
2140 12:45:28.113229 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 12:45:28.116628 ===================================
2142 12:45:28.116741 LPDDR4 DRAM CONFIGURATION
2143 12:45:28.120105 ===================================
2144 12:45:28.123161 EX_ROW_EN[0] = 0x0
2145 12:45:28.126872 EX_ROW_EN[1] = 0x0
2146 12:45:28.127011 LP4Y_EN = 0x0
2147 12:45:28.130399 WORK_FSP = 0x0
2148 12:45:28.130554 WL = 0x4
2149 12:45:28.133028 RL = 0x4
2150 12:45:28.133184 BL = 0x2
2151 12:45:28.136445 RPST = 0x0
2152 12:45:28.136654 RD_PRE = 0x0
2153 12:45:28.140288 WR_PRE = 0x1
2154 12:45:28.140493 WR_PST = 0x0
2155 12:45:28.143100 DBI_WR = 0x0
2156 12:45:28.143298 DBI_RD = 0x0
2157 12:45:28.146822 OTF = 0x1
2158 12:45:28.150246 ===================================
2159 12:45:28.153795 ===================================
2160 12:45:28.154092 ANA top config
2161 12:45:28.156993 ===================================
2162 12:45:28.159748 DLL_ASYNC_EN = 0
2163 12:45:28.163322 ALL_SLAVE_EN = 0
2164 12:45:28.167239 NEW_RANK_MODE = 1
2165 12:45:28.167783 DLL_IDLE_MODE = 1
2166 12:45:28.169782 LP45_APHY_COMB_EN = 1
2167 12:45:28.173742 TX_ODT_DIS = 1
2168 12:45:28.176895 NEW_8X_MODE = 1
2169 12:45:28.180165 ===================================
2170 12:45:28.183160 ===================================
2171 12:45:28.186673 data_rate = 2400
2172 12:45:28.187095 CKR = 1
2173 12:45:28.189564 DQ_P2S_RATIO = 8
2174 12:45:28.192969 ===================================
2175 12:45:28.196309 CA_P2S_RATIO = 8
2176 12:45:28.199809 DQ_CA_OPEN = 0
2177 12:45:28.203506 DQ_SEMI_OPEN = 0
2178 12:45:28.206471 CA_SEMI_OPEN = 0
2179 12:45:28.206890 CA_FULL_RATE = 0
2180 12:45:28.209828 DQ_CKDIV4_EN = 0
2181 12:45:28.213007 CA_CKDIV4_EN = 0
2182 12:45:28.216322 CA_PREDIV_EN = 0
2183 12:45:28.220298 PH8_DLY = 17
2184 12:45:28.223204 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2185 12:45:28.223627 DQ_AAMCK_DIV = 4
2186 12:45:28.226311 CA_AAMCK_DIV = 4
2187 12:45:28.229895 CA_ADMCK_DIV = 4
2188 12:45:28.232695 DQ_TRACK_CA_EN = 0
2189 12:45:28.236222 CA_PICK = 1200
2190 12:45:28.240199 CA_MCKIO = 1200
2191 12:45:28.242985 MCKIO_SEMI = 0
2192 12:45:28.246266 PLL_FREQ = 2366
2193 12:45:28.246683 DQ_UI_PI_RATIO = 32
2194 12:45:28.249526 CA_UI_PI_RATIO = 0
2195 12:45:28.252702 ===================================
2196 12:45:28.256118 ===================================
2197 12:45:28.259194 memory_type:LPDDR4
2198 12:45:28.262433 GP_NUM : 10
2199 12:45:28.262849 SRAM_EN : 1
2200 12:45:28.265706 MD32_EN : 0
2201 12:45:28.269415 ===================================
2202 12:45:28.269834 [ANA_INIT] >>>>>>>>>>>>>>
2203 12:45:28.272800 <<<<<< [CONFIGURE PHASE]: ANA_TX
2204 12:45:28.275703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2205 12:45:28.279549 ===================================
2206 12:45:28.282648 data_rate = 2400,PCW = 0X5b00
2207 12:45:28.285776 ===================================
2208 12:45:28.289238 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2209 12:45:28.295403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 12:45:28.301985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 12:45:28.305499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2212 12:45:28.309166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2213 12:45:28.312142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2214 12:45:28.316001 [ANA_INIT] flow start
2215 12:45:28.316419 [ANA_INIT] PLL >>>>>>>>
2216 12:45:28.319054 [ANA_INIT] PLL <<<<<<<<
2217 12:45:28.322173 [ANA_INIT] MIDPI >>>>>>>>
2218 12:45:28.322596 [ANA_INIT] MIDPI <<<<<<<<
2219 12:45:28.325561 [ANA_INIT] DLL >>>>>>>>
2220 12:45:28.328783 [ANA_INIT] DLL <<<<<<<<
2221 12:45:28.329210 [ANA_INIT] flow end
2222 12:45:28.335186 ============ LP4 DIFF to SE enter ============
2223 12:45:28.338598 ============ LP4 DIFF to SE exit ============
2224 12:45:28.342113 [ANA_INIT] <<<<<<<<<<<<<
2225 12:45:28.345047 [Flow] Enable top DCM control >>>>>
2226 12:45:28.348455 [Flow] Enable top DCM control <<<<<
2227 12:45:28.348931 Enable DLL master slave shuffle
2228 12:45:28.355276 ==============================================================
2229 12:45:28.358252 Gating Mode config
2230 12:45:28.361522 ==============================================================
2231 12:45:28.365347 Config description:
2232 12:45:28.374875 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2233 12:45:28.381439 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2234 12:45:28.384857 SELPH_MODE 0: By rank 1: By Phase
2235 12:45:28.391401 ==============================================================
2236 12:45:28.394684 GAT_TRACK_EN = 1
2237 12:45:28.398093 RX_GATING_MODE = 2
2238 12:45:28.401401 RX_GATING_TRACK_MODE = 2
2239 12:45:28.404814 SELPH_MODE = 1
2240 12:45:28.408040 PICG_EARLY_EN = 1
2241 12:45:28.411463 VALID_LAT_VALUE = 1
2242 12:45:28.414277 ==============================================================
2243 12:45:28.418805 Enter into Gating configuration >>>>
2244 12:45:28.421331 Exit from Gating configuration <<<<
2245 12:45:28.424404 Enter into DVFS_PRE_config >>>>>
2246 12:45:28.434257 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2247 12:45:28.438099 Exit from DVFS_PRE_config <<<<<
2248 12:45:28.440798 Enter into PICG configuration >>>>
2249 12:45:28.444160 Exit from PICG configuration <<<<
2250 12:45:28.448053 [RX_INPUT] configuration >>>>>
2251 12:45:28.450922 [RX_INPUT] configuration <<<<<
2252 12:45:28.457765 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2253 12:45:28.460994 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2254 12:45:28.466997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 12:45:28.474232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 12:45:28.480677 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 12:45:28.487374 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 12:45:28.490887 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2259 12:45:28.493852 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2260 12:45:28.497460 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2261 12:45:28.503530 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2262 12:45:28.507280 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2263 12:45:28.510548 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 12:45:28.514252 ===================================
2265 12:45:28.517246 LPDDR4 DRAM CONFIGURATION
2266 12:45:28.520367 ===================================
2267 12:45:28.521035 EX_ROW_EN[0] = 0x0
2268 12:45:28.523548 EX_ROW_EN[1] = 0x0
2269 12:45:28.527050 LP4Y_EN = 0x0
2270 12:45:28.527524 WORK_FSP = 0x0
2271 12:45:28.530744 WL = 0x4
2272 12:45:28.531352 RL = 0x4
2273 12:45:28.533229 BL = 0x2
2274 12:45:28.533772 RPST = 0x0
2275 12:45:28.536976 RD_PRE = 0x0
2276 12:45:28.537446 WR_PRE = 0x1
2277 12:45:28.540149 WR_PST = 0x0
2278 12:45:28.540669 DBI_WR = 0x0
2279 12:45:28.543216 DBI_RD = 0x0
2280 12:45:28.543909 OTF = 0x1
2281 12:45:28.546526 ===================================
2282 12:45:28.553578 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2283 12:45:28.556476 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2284 12:45:28.560382 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2285 12:45:28.563290 ===================================
2286 12:45:28.566725 LPDDR4 DRAM CONFIGURATION
2287 12:45:28.570459 ===================================
2288 12:45:28.571134 EX_ROW_EN[0] = 0x10
2289 12:45:28.573312 EX_ROW_EN[1] = 0x0
2290 12:45:28.576292 LP4Y_EN = 0x0
2291 12:45:28.576999 WORK_FSP = 0x0
2292 12:45:28.579777 WL = 0x4
2293 12:45:28.580465 RL = 0x4
2294 12:45:28.583392 BL = 0x2
2295 12:45:28.583967 RPST = 0x0
2296 12:45:28.586568 RD_PRE = 0x0
2297 12:45:28.587248 WR_PRE = 0x1
2298 12:45:28.589569 WR_PST = 0x0
2299 12:45:28.590233 DBI_WR = 0x0
2300 12:45:28.593154 DBI_RD = 0x0
2301 12:45:28.593472 OTF = 0x1
2302 12:45:28.596278 ===================================
2303 12:45:28.602863 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2304 12:45:28.603085 ==
2305 12:45:28.605795 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 12:45:28.612682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2307 12:45:28.612985 ==
2308 12:45:28.613254 [Duty_Offset_Calibration]
2309 12:45:28.615650 B0:1 B1:-1 CA:0
2310 12:45:28.615732
2311 12:45:28.619203 [DutyScan_Calibration_Flow] k_type=0
2312 12:45:28.628396
2313 12:45:28.628503 ==CLK 0==
2314 12:45:28.631206 Final CLK duty delay cell = 0
2315 12:45:28.634677 [0] MAX Duty = 5125%(X100), DQS PI = 24
2316 12:45:28.637612 [0] MIN Duty = 4907%(X100), DQS PI = 6
2317 12:45:28.637696 [0] AVG Duty = 5016%(X100)
2318 12:45:28.641337
2319 12:45:28.644319 CH0 CLK Duty spec in!! Max-Min= 218%
2320 12:45:28.648280 [DutyScan_Calibration_Flow] ====Done====
2321 12:45:28.648386
2322 12:45:28.650644 [DutyScan_Calibration_Flow] k_type=1
2323 12:45:28.665372
2324 12:45:28.665461 ==DQS 0 ==
2325 12:45:28.668702 Final DQS duty delay cell = -4
2326 12:45:28.672142 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2327 12:45:28.675546 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2328 12:45:28.678996 [-4] AVG Duty = 4968%(X100)
2329 12:45:28.679095
2330 12:45:28.679192 ==DQS 1 ==
2331 12:45:28.682245 Final DQS duty delay cell = -4
2332 12:45:28.685586 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2333 12:45:28.688850 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2334 12:45:28.692091 [-4] AVG Duty = 4938%(X100)
2335 12:45:28.692190
2336 12:45:28.695955 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2337 12:45:28.696063
2338 12:45:28.699071 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2339 12:45:28.701946 [DutyScan_Calibration_Flow] ====Done====
2340 12:45:28.702062
2341 12:45:28.705268 [DutyScan_Calibration_Flow] k_type=3
2342 12:45:28.723559
2343 12:45:28.723677 ==DQM 0 ==
2344 12:45:28.726700 Final DQM duty delay cell = 0
2345 12:45:28.730492 [0] MAX Duty = 5062%(X100), DQS PI = 22
2346 12:45:28.733729 [0] MIN Duty = 4875%(X100), DQS PI = 8
2347 12:45:28.733830 [0] AVG Duty = 4968%(X100)
2348 12:45:28.737171
2349 12:45:28.737245 ==DQM 1 ==
2350 12:45:28.739985 Final DQM duty delay cell = 4
2351 12:45:28.743715 [4] MAX Duty = 5187%(X100), DQS PI = 14
2352 12:45:28.746783 [4] MIN Duty = 5000%(X100), DQS PI = 24
2353 12:45:28.750609 [4] AVG Duty = 5093%(X100)
2354 12:45:28.750705
2355 12:45:28.753412 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2356 12:45:28.753506
2357 12:45:28.756763 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2358 12:45:28.760111 [DutyScan_Calibration_Flow] ====Done====
2359 12:45:28.760209
2360 12:45:28.763186 [DutyScan_Calibration_Flow] k_type=2
2361 12:45:28.779053
2362 12:45:28.779167 ==DQ 0 ==
2363 12:45:28.781759 Final DQ duty delay cell = -4
2364 12:45:28.785228 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2365 12:45:28.788598 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2366 12:45:28.791739 [-4] AVG Duty = 4969%(X100)
2367 12:45:28.791812
2368 12:45:28.791876 ==DQ 1 ==
2369 12:45:28.795035 Final DQ duty delay cell = -4
2370 12:45:28.798213 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2371 12:45:28.802188 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2372 12:45:28.804821 [-4] AVG Duty = 4922%(X100)
2373 12:45:28.804896
2374 12:45:28.808153 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2375 12:45:28.808250
2376 12:45:28.811480 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2377 12:45:28.814782 [DutyScan_Calibration_Flow] ====Done====
2378 12:45:28.814886 ==
2379 12:45:28.818128 Dram Type= 6, Freq= 0, CH_1, rank 0
2380 12:45:28.821541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 12:45:28.821619 ==
2382 12:45:28.825390 [Duty_Offset_Calibration]
2383 12:45:28.825466 B0:-1 B1:1 CA:1
2384 12:45:28.825528
2385 12:45:28.828582 [DutyScan_Calibration_Flow] k_type=0
2386 12:45:28.839018
2387 12:45:28.839096 ==CLK 0==
2388 12:45:28.842266 Final CLK duty delay cell = 0
2389 12:45:28.845645 [0] MAX Duty = 5156%(X100), DQS PI = 22
2390 12:45:28.849200 [0] MIN Duty = 4969%(X100), DQS PI = 60
2391 12:45:28.849308 [0] AVG Duty = 5062%(X100)
2392 12:45:28.852667
2393 12:45:28.855524 CH1 CLK Duty spec in!! Max-Min= 187%
2394 12:45:28.859218 [DutyScan_Calibration_Flow] ====Done====
2395 12:45:28.859323
2396 12:45:28.861911 [DutyScan_Calibration_Flow] k_type=1
2397 12:45:28.878649
2398 12:45:28.878786 ==DQS 0 ==
2399 12:45:28.881482 Final DQS duty delay cell = 0
2400 12:45:28.885128 [0] MAX Duty = 5156%(X100), DQS PI = 48
2401 12:45:28.888260 [0] MIN Duty = 4907%(X100), DQS PI = 6
2402 12:45:28.888362 [0] AVG Duty = 5031%(X100)
2403 12:45:28.892016
2404 12:45:28.892116 ==DQS 1 ==
2405 12:45:28.895016 Final DQS duty delay cell = 0
2406 12:45:28.898118 [0] MAX Duty = 5062%(X100), DQS PI = 10
2407 12:45:28.901646 [0] MIN Duty = 4969%(X100), DQS PI = 56
2408 12:45:28.904790 [0] AVG Duty = 5015%(X100)
2409 12:45:28.904879
2410 12:45:28.908330 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2411 12:45:28.908428
2412 12:45:28.911925 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2413 12:45:28.914875 [DutyScan_Calibration_Flow] ====Done====
2414 12:45:28.914949
2415 12:45:28.918080 [DutyScan_Calibration_Flow] k_type=3
2416 12:45:28.933809
2417 12:45:28.933900 ==DQM 0 ==
2418 12:45:28.937611 Final DQM duty delay cell = -4
2419 12:45:28.940705 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2420 12:45:28.943740 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2421 12:45:28.947271 [-4] AVG Duty = 4953%(X100)
2422 12:45:28.947375
2423 12:45:28.947466 ==DQM 1 ==
2424 12:45:28.950972 Final DQM duty delay cell = 0
2425 12:45:28.953645 [0] MAX Duty = 5156%(X100), DQS PI = 4
2426 12:45:28.957082 [0] MIN Duty = 5000%(X100), DQS PI = 26
2427 12:45:28.960874 [0] AVG Duty = 5078%(X100)
2428 12:45:28.960951
2429 12:45:28.963566 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2430 12:45:28.963661
2431 12:45:28.967119 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2432 12:45:28.970722 [DutyScan_Calibration_Flow] ====Done====
2433 12:45:28.970824
2434 12:45:28.973715 [DutyScan_Calibration_Flow] k_type=2
2435 12:45:28.990702
2436 12:45:28.990831 ==DQ 0 ==
2437 12:45:28.994243 Final DQ duty delay cell = 0
2438 12:45:28.997233 [0] MAX Duty = 5156%(X100), DQS PI = 28
2439 12:45:29.001031 [0] MIN Duty = 4907%(X100), DQS PI = 8
2440 12:45:29.001103 [0] AVG Duty = 5031%(X100)
2441 12:45:29.004284
2442 12:45:29.004380 ==DQ 1 ==
2443 12:45:29.007157 Final DQ duty delay cell = 0
2444 12:45:29.010777 [0] MAX Duty = 5124%(X100), DQS PI = 10
2445 12:45:29.013792 [0] MIN Duty = 4969%(X100), DQS PI = 0
2446 12:45:29.013872 [0] AVG Duty = 5046%(X100)
2447 12:45:29.013961
2448 12:45:29.016952 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2449 12:45:29.020203
2450 12:45:29.023647 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2451 12:45:29.027093 [DutyScan_Calibration_Flow] ====Done====
2452 12:45:29.030466 nWR fixed to 30
2453 12:45:29.030570 [ModeRegInit_LP4] CH0 RK0
2454 12:45:29.033776 [ModeRegInit_LP4] CH0 RK1
2455 12:45:29.037115 [ModeRegInit_LP4] CH1 RK0
2456 12:45:29.037211 [ModeRegInit_LP4] CH1 RK1
2457 12:45:29.040646 match AC timing 7
2458 12:45:29.043656 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2459 12:45:29.050366 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2460 12:45:29.053301 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2461 12:45:29.060175 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2462 12:45:29.063417 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2463 12:45:29.063515 ==
2464 12:45:29.066773 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 12:45:29.070525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 12:45:29.070638 ==
2467 12:45:29.076885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 12:45:29.083166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2469 12:45:29.090508 [CA 0] Center 39 (9~70) winsize 62
2470 12:45:29.093843 [CA 1] Center 39 (9~69) winsize 61
2471 12:45:29.096934 [CA 2] Center 35 (5~66) winsize 62
2472 12:45:29.100349 [CA 3] Center 34 (4~65) winsize 62
2473 12:45:29.103860 [CA 4] Center 33 (4~63) winsize 60
2474 12:45:29.106984 [CA 5] Center 33 (3~63) winsize 61
2475 12:45:29.107084
2476 12:45:29.110413 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2477 12:45:29.110514
2478 12:45:29.113459 [CATrainingPosCal] consider 1 rank data
2479 12:45:29.117246 u2DelayCellTimex100 = 270/100 ps
2480 12:45:29.120372 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2481 12:45:29.127123 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2482 12:45:29.130040 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2483 12:45:29.133312 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2484 12:45:29.136959 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2485 12:45:29.139660 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2486 12:45:29.139756
2487 12:45:29.143113 CA PerBit enable=1, Macro0, CA PI delay=33
2488 12:45:29.143209
2489 12:45:29.146503 [CBTSetCACLKResult] CA Dly = 33
2490 12:45:29.149996 CS Dly: 8 (0~39)
2491 12:45:29.150092 ==
2492 12:45:29.153371 Dram Type= 6, Freq= 0, CH_0, rank 1
2493 12:45:29.156168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 12:45:29.156267 ==
2495 12:45:29.163097 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 12:45:29.166421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2497 12:45:29.176148 [CA 0] Center 38 (8~69) winsize 62
2498 12:45:29.179309 [CA 1] Center 39 (9~70) winsize 62
2499 12:45:29.182811 [CA 2] Center 35 (5~66) winsize 62
2500 12:45:29.186386 [CA 3] Center 34 (4~65) winsize 62
2501 12:45:29.189401 [CA 4] Center 33 (3~64) winsize 62
2502 12:45:29.193021 [CA 5] Center 32 (2~62) winsize 61
2503 12:45:29.193095
2504 12:45:29.195798 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2505 12:45:29.195932
2506 12:45:29.199270 [CATrainingPosCal] consider 2 rank data
2507 12:45:29.202888 u2DelayCellTimex100 = 270/100 ps
2508 12:45:29.206033 CA0 delay=39 (9~69),Diff = 7 PI (33 cell)
2509 12:45:29.212720 CA1 delay=39 (9~69),Diff = 7 PI (33 cell)
2510 12:45:29.215765 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2511 12:45:29.219309 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2512 12:45:29.222580 CA4 delay=33 (4~63),Diff = 1 PI (4 cell)
2513 12:45:29.225820 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2514 12:45:29.225934
2515 12:45:29.229053 CA PerBit enable=1, Macro0, CA PI delay=32
2516 12:45:29.229153
2517 12:45:29.232071 [CBTSetCACLKResult] CA Dly = 32
2518 12:45:29.235542 CS Dly: 9 (0~41)
2519 12:45:29.235645
2520 12:45:29.238971 ----->DramcWriteLeveling(PI) begin...
2521 12:45:29.239074 ==
2522 12:45:29.242373 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 12:45:29.245689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 12:45:29.245788 ==
2525 12:45:29.249063 Write leveling (Byte 0): 33 => 33
2526 12:45:29.251787 Write leveling (Byte 1): 30 => 30
2527 12:45:29.255392 DramcWriteLeveling(PI) end<-----
2528 12:45:29.255499
2529 12:45:29.255590 ==
2530 12:45:29.258780 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 12:45:29.262154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 12:45:29.262257 ==
2533 12:45:29.265537 [Gating] SW mode calibration
2534 12:45:29.271576 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2535 12:45:29.278362 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2536 12:45:29.281867 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2537 12:45:29.285192 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2538 12:45:29.291555 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2539 12:45:29.294804 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 12:45:29.298234 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 12:45:29.305008 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 12:45:29.308239 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2543 12:45:29.311768 0 15 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2544 12:45:29.318379 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2545 12:45:29.321252 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 12:45:29.324842 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 12:45:29.331416 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 12:45:29.334825 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 12:45:29.338179 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 12:45:29.344777 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2551 12:45:29.347779 1 0 28 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
2552 12:45:29.351385 1 1 0 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2553 12:45:29.357904 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2554 12:45:29.360955 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 12:45:29.364638 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 12:45:29.370883 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:45:29.374442 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:45:29.377646 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:45:29.384237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2560 12:45:29.388050 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2561 12:45:29.390800 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 12:45:29.397575 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:45:29.401160 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:45:29.404071 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:45:29.410921 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:45:29.413900 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:45:29.417309 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:45:29.424418 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:45:29.427747 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:45:29.430551 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:45:29.437812 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:45:29.441151 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:45:29.444043 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:45:29.450655 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2575 12:45:29.453975 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2576 12:45:29.457205 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2577 12:45:29.461170 Total UI for P1: 0, mck2ui 16
2578 12:45:29.463880 best dqsien dly found for B0: ( 1, 3, 26)
2579 12:45:29.470254 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2580 12:45:29.474219 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 12:45:29.477225 Total UI for P1: 0, mck2ui 16
2582 12:45:29.480751 best dqsien dly found for B1: ( 1, 4, 2)
2583 12:45:29.483812 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2584 12:45:29.487457 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2585 12:45:29.487539
2586 12:45:29.490528 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2587 12:45:29.493785 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2588 12:45:29.496794 [Gating] SW calibration Done
2589 12:45:29.496875 ==
2590 12:45:29.500005 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 12:45:29.503909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 12:45:29.503992 ==
2593 12:45:29.506757 RX Vref Scan: 0
2594 12:45:29.506839
2595 12:45:29.510378 RX Vref 0 -> 0, step: 1
2596 12:45:29.510460
2597 12:45:29.510524 RX Delay -40 -> 252, step: 8
2598 12:45:29.516644 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2599 12:45:29.519942 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2600 12:45:29.523503 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2601 12:45:29.526996 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2602 12:45:29.530381 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2603 12:45:29.536580 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2604 12:45:29.539834 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2605 12:45:29.543099 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2606 12:45:29.546829 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2607 12:45:29.549725 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2608 12:45:29.556739 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2609 12:45:29.559691 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2610 12:45:29.563178 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2611 12:45:29.566591 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2612 12:45:29.569948 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2613 12:45:29.576426 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2614 12:45:29.576573 ==
2615 12:45:29.580115 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 12:45:29.583392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 12:45:29.583475 ==
2618 12:45:29.583540 DQS Delay:
2619 12:45:29.586616 DQS0 = 0, DQS1 = 0
2620 12:45:29.586692 DQM Delay:
2621 12:45:29.589751 DQM0 = 119, DQM1 = 107
2622 12:45:29.589833 DQ Delay:
2623 12:45:29.593078 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2624 12:45:29.596313 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2625 12:45:29.599747 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2626 12:45:29.602704 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2627 12:45:29.602786
2628 12:45:29.606461
2629 12:45:29.606539 ==
2630 12:45:29.609328 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 12:45:29.612837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 12:45:29.612915 ==
2633 12:45:29.612978
2634 12:45:29.613036
2635 12:45:29.616552 TX Vref Scan disable
2636 12:45:29.616637 == TX Byte 0 ==
2637 12:45:29.623066 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2638 12:45:29.625928 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2639 12:45:29.626002 == TX Byte 1 ==
2640 12:45:29.632921 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2641 12:45:29.636012 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2642 12:45:29.636090 ==
2643 12:45:29.639313 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 12:45:29.643016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 12:45:29.643093 ==
2646 12:45:29.655186 TX Vref=22, minBit 1, minWin=25, winSum=412
2647 12:45:29.658523 TX Vref=24, minBit 1, minWin=25, winSum=413
2648 12:45:29.661771 TX Vref=26, minBit 1, minWin=26, winSum=427
2649 12:45:29.665035 TX Vref=28, minBit 5, minWin=26, winSum=434
2650 12:45:29.668861 TX Vref=30, minBit 5, minWin=26, winSum=433
2651 12:45:29.674859 TX Vref=32, minBit 4, minWin=26, winSum=433
2652 12:45:29.678012 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 28
2653 12:45:29.678092
2654 12:45:29.682122 Final TX Range 1 Vref 28
2655 12:45:29.682194
2656 12:45:29.682256 ==
2657 12:45:29.685312 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 12:45:29.688290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 12:45:29.688390 ==
2660 12:45:29.691511
2661 12:45:29.691580
2662 12:45:29.691642 TX Vref Scan disable
2663 12:45:29.694677 == TX Byte 0 ==
2664 12:45:29.698510 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2665 12:45:29.701764 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2666 12:45:29.704788 == TX Byte 1 ==
2667 12:45:29.707993 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2668 12:45:29.714667 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2669 12:45:29.714747
2670 12:45:29.714815 [DATLAT]
2671 12:45:29.714875 Freq=1200, CH0 RK0
2672 12:45:29.714935
2673 12:45:29.718225 DATLAT Default: 0xd
2674 12:45:29.718318 0, 0xFFFF, sum = 0
2675 12:45:29.721699 1, 0xFFFF, sum = 0
2676 12:45:29.724618 2, 0xFFFF, sum = 0
2677 12:45:29.724690 3, 0xFFFF, sum = 0
2678 12:45:29.727814 4, 0xFFFF, sum = 0
2679 12:45:29.727894 5, 0xFFFF, sum = 0
2680 12:45:29.731252 6, 0xFFFF, sum = 0
2681 12:45:29.731325 7, 0xFFFF, sum = 0
2682 12:45:29.734500 8, 0xFFFF, sum = 0
2683 12:45:29.734572 9, 0xFFFF, sum = 0
2684 12:45:29.737688 10, 0xFFFF, sum = 0
2685 12:45:29.737772 11, 0xFFFF, sum = 0
2686 12:45:29.741320 12, 0x0, sum = 1
2687 12:45:29.741399 13, 0x0, sum = 2
2688 12:45:29.744636 14, 0x0, sum = 3
2689 12:45:29.744736 15, 0x0, sum = 4
2690 12:45:29.747831 best_step = 13
2691 12:45:29.747935
2692 12:45:29.748031 ==
2693 12:45:29.751410 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 12:45:29.754468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 12:45:29.754540 ==
2696 12:45:29.754612 RX Vref Scan: 1
2697 12:45:29.757934
2698 12:45:29.758005 Set Vref Range= 32 -> 127
2699 12:45:29.758074
2700 12:45:29.760984 RX Vref 32 -> 127, step: 1
2701 12:45:29.761052
2702 12:45:29.764630 RX Delay -21 -> 252, step: 4
2703 12:45:29.764698
2704 12:45:29.767865 Set Vref, RX VrefLevel [Byte0]: 32
2705 12:45:29.771118 [Byte1]: 32
2706 12:45:29.771233
2707 12:45:29.774224 Set Vref, RX VrefLevel [Byte0]: 33
2708 12:45:29.777373 [Byte1]: 33
2709 12:45:29.781276
2710 12:45:29.781357 Set Vref, RX VrefLevel [Byte0]: 34
2711 12:45:29.784478 [Byte1]: 34
2712 12:45:29.789159
2713 12:45:29.789240 Set Vref, RX VrefLevel [Byte0]: 35
2714 12:45:29.792682 [Byte1]: 35
2715 12:45:29.797036
2716 12:45:29.797117 Set Vref, RX VrefLevel [Byte0]: 36
2717 12:45:29.800853 [Byte1]: 36
2718 12:45:29.805458
2719 12:45:29.805541 Set Vref, RX VrefLevel [Byte0]: 37
2720 12:45:29.808256 [Byte1]: 37
2721 12:45:29.813316
2722 12:45:29.813402 Set Vref, RX VrefLevel [Byte0]: 38
2723 12:45:29.816604 [Byte1]: 38
2724 12:45:29.820926
2725 12:45:29.821029 Set Vref, RX VrefLevel [Byte0]: 39
2726 12:45:29.824365 [Byte1]: 39
2727 12:45:29.828744
2728 12:45:29.828828 Set Vref, RX VrefLevel [Byte0]: 40
2729 12:45:29.832254 [Byte1]: 40
2730 12:45:29.836838
2731 12:45:29.836921 Set Vref, RX VrefLevel [Byte0]: 41
2732 12:45:29.840087 [Byte1]: 41
2733 12:45:29.844580
2734 12:45:29.847869 Set Vref, RX VrefLevel [Byte0]: 42
2735 12:45:29.847953 [Byte1]: 42
2736 12:45:29.852407
2737 12:45:29.852493 Set Vref, RX VrefLevel [Byte0]: 43
2738 12:45:29.855991 [Byte1]: 43
2739 12:45:29.860430
2740 12:45:29.860536 Set Vref, RX VrefLevel [Byte0]: 44
2741 12:45:29.864249 [Byte1]: 44
2742 12:45:29.868301
2743 12:45:29.868389 Set Vref, RX VrefLevel [Byte0]: 45
2744 12:45:29.871653 [Byte1]: 45
2745 12:45:29.876508
2746 12:45:29.876632 Set Vref, RX VrefLevel [Byte0]: 46
2747 12:45:29.879778 [Byte1]: 46
2748 12:45:29.884220
2749 12:45:29.884304 Set Vref, RX VrefLevel [Byte0]: 47
2750 12:45:29.887474 [Byte1]: 47
2751 12:45:29.892164
2752 12:45:29.892247 Set Vref, RX VrefLevel [Byte0]: 48
2753 12:45:29.895384 [Byte1]: 48
2754 12:45:29.900057
2755 12:45:29.900154 Set Vref, RX VrefLevel [Byte0]: 49
2756 12:45:29.903360 [Byte1]: 49
2757 12:45:29.908367
2758 12:45:29.908451 Set Vref, RX VrefLevel [Byte0]: 50
2759 12:45:29.911317 [Byte1]: 50
2760 12:45:29.916408
2761 12:45:29.916491 Set Vref, RX VrefLevel [Byte0]: 51
2762 12:45:29.919259 [Byte1]: 51
2763 12:45:29.923700
2764 12:45:29.923783 Set Vref, RX VrefLevel [Byte0]: 52
2765 12:45:29.927264 [Byte1]: 52
2766 12:45:29.932192
2767 12:45:29.932276 Set Vref, RX VrefLevel [Byte0]: 53
2768 12:45:29.935129 [Byte1]: 53
2769 12:45:29.939844
2770 12:45:29.939928 Set Vref, RX VrefLevel [Byte0]: 54
2771 12:45:29.943483 [Byte1]: 54
2772 12:45:29.947575
2773 12:45:29.947658 Set Vref, RX VrefLevel [Byte0]: 55
2774 12:45:29.951239 [Byte1]: 55
2775 12:45:29.955549
2776 12:45:29.955632 Set Vref, RX VrefLevel [Byte0]: 56
2777 12:45:29.958879 [Byte1]: 56
2778 12:45:29.963674
2779 12:45:29.963758 Set Vref, RX VrefLevel [Byte0]: 57
2780 12:45:29.966777 [Byte1]: 57
2781 12:45:29.972136
2782 12:45:29.972219 Set Vref, RX VrefLevel [Byte0]: 58
2783 12:45:29.974781 [Byte1]: 58
2784 12:45:29.979400
2785 12:45:29.979484 Set Vref, RX VrefLevel [Byte0]: 59
2786 12:45:29.982886 [Byte1]: 59
2787 12:45:29.987335
2788 12:45:29.987419 Set Vref, RX VrefLevel [Byte0]: 60
2789 12:45:29.990871 [Byte1]: 60
2790 12:45:29.995137
2791 12:45:29.995220 Set Vref, RX VrefLevel [Byte0]: 61
2792 12:45:29.998860 [Byte1]: 61
2793 12:45:30.003035
2794 12:45:30.003118 Set Vref, RX VrefLevel [Byte0]: 62
2795 12:45:30.006518 [Byte1]: 62
2796 12:45:30.011513
2797 12:45:30.011596 Set Vref, RX VrefLevel [Byte0]: 63
2798 12:45:30.014314 [Byte1]: 63
2799 12:45:30.018807
2800 12:45:30.018891 Set Vref, RX VrefLevel [Byte0]: 64
2801 12:45:30.022227 [Byte1]: 64
2802 12:45:30.027047
2803 12:45:30.027132 Set Vref, RX VrefLevel [Byte0]: 65
2804 12:45:30.030417 [Byte1]: 65
2805 12:45:30.034689
2806 12:45:30.034793 Set Vref, RX VrefLevel [Byte0]: 66
2807 12:45:30.038183 [Byte1]: 66
2808 12:45:30.042629
2809 12:45:30.046155 Set Vref, RX VrefLevel [Byte0]: 67
2810 12:45:30.046242 [Byte1]: 67
2811 12:45:30.050929
2812 12:45:30.051036 Set Vref, RX VrefLevel [Byte0]: 68
2813 12:45:30.054263 [Byte1]: 68
2814 12:45:30.059296
2815 12:45:30.059380 Set Vref, RX VrefLevel [Byte0]: 69
2816 12:45:30.062093 [Byte1]: 69
2817 12:45:30.066575
2818 12:45:30.066660 Set Vref, RX VrefLevel [Byte0]: 70
2819 12:45:30.070397 [Byte1]: 70
2820 12:45:30.074544
2821 12:45:30.074627 Set Vref, RX VrefLevel [Byte0]: 71
2822 12:45:30.077769 [Byte1]: 71
2823 12:45:30.082608
2824 12:45:30.082692 Set Vref, RX VrefLevel [Byte0]: 72
2825 12:45:30.085559 [Byte1]: 72
2826 12:45:30.090319
2827 12:45:30.090402 Set Vref, RX VrefLevel [Byte0]: 73
2828 12:45:30.093763 [Byte1]: 73
2829 12:45:30.098083
2830 12:45:30.098167 Set Vref, RX VrefLevel [Byte0]: 74
2831 12:45:30.101935 [Byte1]: 74
2832 12:45:30.106313
2833 12:45:30.106396 Set Vref, RX VrefLevel [Byte0]: 75
2834 12:45:30.109315 [Byte1]: 75
2835 12:45:30.114026
2836 12:45:30.114110 Set Vref, RX VrefLevel [Byte0]: 76
2837 12:45:30.117629 [Byte1]: 76
2838 12:45:30.122116
2839 12:45:30.122203 Set Vref, RX VrefLevel [Byte0]: 77
2840 12:45:30.126035 [Byte1]: 77
2841 12:45:30.129971
2842 12:45:30.130054 Final RX Vref Byte 0 = 55 to rank0
2843 12:45:30.133448 Final RX Vref Byte 1 = 57 to rank0
2844 12:45:30.137217 Final RX Vref Byte 0 = 55 to rank1
2845 12:45:30.139745 Final RX Vref Byte 1 = 57 to rank1==
2846 12:45:30.143157 Dram Type= 6, Freq= 0, CH_0, rank 0
2847 12:45:30.149840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 12:45:30.149947 ==
2849 12:45:30.150031 DQS Delay:
2850 12:45:30.153363 DQS0 = 0, DQS1 = 0
2851 12:45:30.153447 DQM Delay:
2852 12:45:30.153530 DQM0 = 118, DQM1 = 107
2853 12:45:30.156848 DQ Delay:
2854 12:45:30.160240 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2855 12:45:30.163294 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2856 12:45:30.166282 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2857 12:45:30.169963 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2858 12:45:30.170047
2859 12:45:30.170131
2860 12:45:30.179604 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2861 12:45:30.179695 CH0 RK0: MR19=403, MR18=10FC
2862 12:45:30.186279 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2863 12:45:30.186354
2864 12:45:30.189337 ----->DramcWriteLeveling(PI) begin...
2865 12:45:30.189415 ==
2866 12:45:30.193279 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 12:45:30.199260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 12:45:30.199335 ==
2869 12:45:30.202893 Write leveling (Byte 0): 33 => 33
2870 12:45:30.202962 Write leveling (Byte 1): 31 => 31
2871 12:45:30.206185 DramcWriteLeveling(PI) end<-----
2872 12:45:30.206251
2873 12:45:30.209299 ==
2874 12:45:30.209367 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 12:45:30.215977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 12:45:30.216058 ==
2877 12:45:30.219227 [Gating] SW mode calibration
2878 12:45:30.226134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2879 12:45:30.229278 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2880 12:45:30.236073 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2881 12:45:30.239207 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2882 12:45:30.242498 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 12:45:30.249178 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 12:45:30.252343 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 12:45:30.255613 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 12:45:30.262442 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2887 12:45:30.265732 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2888 12:45:30.268921 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2889 12:45:30.275678 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 12:45:30.279013 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 12:45:30.282350 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 12:45:30.289208 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 12:45:30.292171 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 12:45:30.295334 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 12:45:30.302410 1 0 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2896 12:45:30.305553 1 1 0 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2897 12:45:30.308590 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 12:45:30.315262 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 12:45:30.318672 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 12:45:30.322170 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 12:45:30.328564 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 12:45:30.332093 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2903 12:45:30.335128 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2904 12:45:30.342402 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2905 12:45:30.345082 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 12:45:30.348830 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 12:45:30.351883 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 12:45:30.358923 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 12:45:30.361886 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 12:45:30.365206 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 12:45:30.372031 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 12:45:30.374874 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 12:45:30.378241 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 12:45:30.385461 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 12:45:30.388753 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 12:45:30.391753 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 12:45:30.398480 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 12:45:30.401783 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:45:30.404881 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2920 12:45:30.411551 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2921 12:45:30.411634 Total UI for P1: 0, mck2ui 16
2922 12:45:30.418427 best dqsien dly found for B0: ( 1, 3, 28)
2923 12:45:30.421745 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 12:45:30.425011 Total UI for P1: 0, mck2ui 16
2925 12:45:30.428128 best dqsien dly found for B1: ( 1, 4, 0)
2926 12:45:30.431759 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2927 12:45:30.435147 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2928 12:45:30.435242
2929 12:45:30.438043 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2930 12:45:30.441426 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2931 12:45:30.445121 [Gating] SW calibration Done
2932 12:45:30.445218 ==
2933 12:45:30.448214 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 12:45:30.451220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 12:45:30.455064 ==
2936 12:45:30.455145 RX Vref Scan: 0
2937 12:45:30.455209
2938 12:45:30.457819 RX Vref 0 -> 0, step: 1
2939 12:45:30.457899
2940 12:45:30.461798 RX Delay -40 -> 252, step: 8
2941 12:45:30.464424 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2942 12:45:30.468217 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2943 12:45:30.471442 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2944 12:45:30.474762 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2945 12:45:30.481855 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2946 12:45:30.484538 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2947 12:45:30.487909 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2948 12:45:30.491431 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2949 12:45:30.495003 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2950 12:45:30.498238 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2951 12:45:30.504733 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2952 12:45:30.508087 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2953 12:45:30.511156 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2954 12:45:30.514449 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2955 12:45:30.521170 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2956 12:45:30.524999 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2957 12:45:30.525080 ==
2958 12:45:30.527780 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 12:45:30.531177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 12:45:30.531261 ==
2961 12:45:30.534675 DQS Delay:
2962 12:45:30.534758 DQS0 = 0, DQS1 = 0
2963 12:45:30.534840 DQM Delay:
2964 12:45:30.537685 DQM0 = 118, DQM1 = 109
2965 12:45:30.537768 DQ Delay:
2966 12:45:30.540813 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2967 12:45:30.544346 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2968 12:45:30.547435 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =107
2969 12:45:30.554110 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2970 12:45:30.554193
2971 12:45:30.554275
2972 12:45:30.554352 ==
2973 12:45:30.557694 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 12:45:30.560993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 12:45:30.561076 ==
2976 12:45:30.561159
2977 12:45:30.561256
2978 12:45:30.564048 TX Vref Scan disable
2979 12:45:30.564130 == TX Byte 0 ==
2980 12:45:30.570616 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2981 12:45:30.574140 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2982 12:45:30.574223 == TX Byte 1 ==
2983 12:45:30.580998 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2984 12:45:30.584044 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2985 12:45:30.584127 ==
2986 12:45:30.587452 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 12:45:30.590559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 12:45:30.590643 ==
2989 12:45:30.603253 TX Vref=22, minBit 6, minWin=25, winSum=413
2990 12:45:30.606901 TX Vref=24, minBit 8, minWin=25, winSum=423
2991 12:45:30.610886 TX Vref=26, minBit 13, minWin=25, winSum=427
2992 12:45:30.613458 TX Vref=28, minBit 2, minWin=27, winSum=435
2993 12:45:30.617141 TX Vref=30, minBit 12, minWin=26, winSum=436
2994 12:45:30.623714 TX Vref=32, minBit 1, minWin=26, winSum=425
2995 12:45:30.627245 [TxChooseVref] Worse bit 2, Min win 27, Win sum 435, Final Vref 28
2996 12:45:30.627327
2997 12:45:30.630726 Final TX Range 1 Vref 28
2998 12:45:30.630808
2999 12:45:30.630872 ==
3000 12:45:30.633597 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 12:45:30.637040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 12:45:30.637122 ==
3003 12:45:30.640267
3004 12:45:30.640348
3005 12:45:30.640413 TX Vref Scan disable
3006 12:45:30.643344 == TX Byte 0 ==
3007 12:45:30.646733 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3008 12:45:30.653633 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3009 12:45:30.653716 == TX Byte 1 ==
3010 12:45:30.656619 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3011 12:45:30.663101 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3012 12:45:30.663182
3013 12:45:30.663246 [DATLAT]
3014 12:45:30.663305 Freq=1200, CH0 RK1
3015 12:45:30.663363
3016 12:45:30.666227 DATLAT Default: 0xd
3017 12:45:30.670102 0, 0xFFFF, sum = 0
3018 12:45:30.670184 1, 0xFFFF, sum = 0
3019 12:45:30.672899 2, 0xFFFF, sum = 0
3020 12:45:30.672982 3, 0xFFFF, sum = 0
3021 12:45:30.676495 4, 0xFFFF, sum = 0
3022 12:45:30.676614 5, 0xFFFF, sum = 0
3023 12:45:30.680073 6, 0xFFFF, sum = 0
3024 12:45:30.680155 7, 0xFFFF, sum = 0
3025 12:45:30.682718 8, 0xFFFF, sum = 0
3026 12:45:30.682801 9, 0xFFFF, sum = 0
3027 12:45:30.686168 10, 0xFFFF, sum = 0
3028 12:45:30.686251 11, 0xFFFF, sum = 0
3029 12:45:30.689387 12, 0x0, sum = 1
3030 12:45:30.689470 13, 0x0, sum = 2
3031 12:45:30.692986 14, 0x0, sum = 3
3032 12:45:30.693068 15, 0x0, sum = 4
3033 12:45:30.696179 best_step = 13
3034 12:45:30.696260
3035 12:45:30.696383 ==
3036 12:45:30.699524 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 12:45:30.702561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 12:45:30.702643 ==
3039 12:45:30.706115 RX Vref Scan: 0
3040 12:45:30.706196
3041 12:45:30.706261 RX Vref 0 -> 0, step: 1
3042 12:45:30.706320
3043 12:45:30.709711 RX Delay -21 -> 252, step: 4
3044 12:45:30.716411 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3045 12:45:30.719400 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3046 12:45:30.722751 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3047 12:45:30.725818 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3048 12:45:30.729270 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3049 12:45:30.735951 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3050 12:45:30.739100 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3051 12:45:30.742304 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3052 12:45:30.745591 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3053 12:45:30.749296 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3054 12:45:30.756082 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3055 12:45:30.759413 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3056 12:45:30.762138 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3057 12:45:30.765799 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3058 12:45:30.769328 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3059 12:45:30.775372 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3060 12:45:30.775454 ==
3061 12:45:30.779002 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 12:45:30.782039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 12:45:30.782146 ==
3064 12:45:30.782241 DQS Delay:
3065 12:45:30.785483 DQS0 = 0, DQS1 = 0
3066 12:45:30.785584 DQM Delay:
3067 12:45:30.789397 DQM0 = 116, DQM1 = 109
3068 12:45:30.789507 DQ Delay:
3069 12:45:30.791974 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3070 12:45:30.795506 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =126
3071 12:45:30.798880 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3072 12:45:30.802227 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =116
3073 12:45:30.802309
3074 12:45:30.802380
3075 12:45:30.811931 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3076 12:45:30.815449 CH0 RK1: MR19=403, MR18=BE6
3077 12:45:30.818339 CH0_RK1: MR19=0x403, MR18=0xBE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3078 12:45:30.821850 [RxdqsGatingPostProcess] freq 1200
3079 12:45:30.828837 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3080 12:45:30.831908 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 12:45:30.835178 best DQS1 dly(2T, 0.5T) = (0, 12)
3082 12:45:30.838620 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 12:45:30.841806 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3084 12:45:30.844834 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 12:45:30.848441 best DQS1 dly(2T, 0.5T) = (0, 12)
3086 12:45:30.851376 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 12:45:30.854895 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3088 12:45:30.858117 Pre-setting of DQS Precalculation
3089 12:45:30.861332 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3090 12:45:30.861439 ==
3091 12:45:30.864697 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 12:45:30.868397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 12:45:30.871811 ==
3094 12:45:30.875051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 12:45:30.881541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 12:45:30.889398 [CA 0] Center 37 (7~67) winsize 61
3097 12:45:30.892783 [CA 1] Center 38 (8~68) winsize 61
3098 12:45:30.896271 [CA 2] Center 34 (4~64) winsize 61
3099 12:45:30.899302 [CA 3] Center 33 (3~64) winsize 62
3100 12:45:30.902962 [CA 4] Center 34 (4~64) winsize 61
3101 12:45:30.905929 [CA 5] Center 33 (3~64) winsize 62
3102 12:45:30.906030
3103 12:45:30.909627 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 12:45:30.909726
3105 12:45:30.912658 [CATrainingPosCal] consider 1 rank data
3106 12:45:30.915816 u2DelayCellTimex100 = 270/100 ps
3107 12:45:30.919028 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3108 12:45:30.926153 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3109 12:45:30.929133 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 12:45:30.932957 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3111 12:45:30.935780 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 12:45:30.938983 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3113 12:45:30.939082
3114 12:45:30.942475 CA PerBit enable=1, Macro0, CA PI delay=33
3115 12:45:30.942574
3116 12:45:30.945691 [CBTSetCACLKResult] CA Dly = 33
3117 12:45:30.945790 CS Dly: 5 (0~36)
3118 12:45:30.949469 ==
3119 12:45:30.949565 Dram Type= 6, Freq= 0, CH_1, rank 1
3120 12:45:30.955688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 12:45:30.955763 ==
3122 12:45:30.959161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 12:45:30.965845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3124 12:45:30.975166 [CA 0] Center 37 (7~67) winsize 61
3125 12:45:30.978438 [CA 1] Center 38 (8~68) winsize 61
3126 12:45:30.981602 [CA 2] Center 34 (3~65) winsize 63
3127 12:45:30.985088 [CA 3] Center 33 (3~64) winsize 62
3128 12:45:30.988310 [CA 4] Center 33 (3~64) winsize 62
3129 12:45:30.991548 [CA 5] Center 33 (3~64) winsize 62
3130 12:45:30.991623
3131 12:45:30.995104 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3132 12:45:30.995203
3133 12:45:30.998291 [CATrainingPosCal] consider 2 rank data
3134 12:45:31.001403 u2DelayCellTimex100 = 270/100 ps
3135 12:45:31.005036 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3136 12:45:31.008277 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3137 12:45:31.014534 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3138 12:45:31.018023 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3139 12:45:31.021448 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 12:45:31.024383 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3141 12:45:31.024489
3142 12:45:31.027817 CA PerBit enable=1, Macro0, CA PI delay=33
3143 12:45:31.027917
3144 12:45:31.031672 [CBTSetCACLKResult] CA Dly = 33
3145 12:45:31.031747 CS Dly: 7 (0~40)
3146 12:45:31.035085
3147 12:45:31.037997 ----->DramcWriteLeveling(PI) begin...
3148 12:45:31.038102 ==
3149 12:45:31.041457 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 12:45:31.044581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 12:45:31.044678 ==
3152 12:45:31.048159 Write leveling (Byte 0): 26 => 26
3153 12:45:31.051159 Write leveling (Byte 1): 26 => 26
3154 12:45:31.054537 DramcWriteLeveling(PI) end<-----
3155 12:45:31.054632
3156 12:45:31.054721 ==
3157 12:45:31.057871 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 12:45:31.060985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 12:45:31.061091 ==
3160 12:45:31.064449 [Gating] SW mode calibration
3161 12:45:31.070945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3162 12:45:31.077659 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3163 12:45:31.081202 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3164 12:45:31.084443 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 12:45:31.091307 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 12:45:31.094113 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 12:45:31.097927 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 12:45:31.104489 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 12:45:31.107419 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
3170 12:45:31.111168 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3171 12:45:31.117505 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 12:45:31.120931 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 12:45:31.124162 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 12:45:31.131196 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 12:45:31.134303 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 12:45:31.137795 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 12:45:31.144433 1 0 24 | B1->B0 | 2a2a 3636 | 1 1 | (0 0) (0 0)
3178 12:45:31.147707 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3179 12:45:31.150916 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 12:45:31.157374 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 12:45:31.160109 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 12:45:31.163902 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 12:45:31.170321 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 12:45:31.174063 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 12:45:31.177134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3186 12:45:31.180372 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3187 12:45:31.186826 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 12:45:31.190545 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 12:45:31.193710 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 12:45:31.200239 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 12:45:31.203448 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 12:45:31.207079 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 12:45:31.213703 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 12:45:31.217574 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 12:45:31.219870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 12:45:31.227245 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 12:45:31.230075 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 12:45:31.233399 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 12:45:31.239755 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 12:45:31.243641 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:45:31.246978 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3202 12:45:31.253556 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3203 12:45:31.256724 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 12:45:31.260054 Total UI for P1: 0, mck2ui 16
3205 12:45:31.263115 best dqsien dly found for B0: ( 1, 3, 26)
3206 12:45:31.266608 Total UI for P1: 0, mck2ui 16
3207 12:45:31.270203 best dqsien dly found for B1: ( 1, 3, 26)
3208 12:45:31.272881 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3209 12:45:31.276316 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3210 12:45:31.276398
3211 12:45:31.279578 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3212 12:45:31.282817 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3213 12:45:31.286168 [Gating] SW calibration Done
3214 12:45:31.286249 ==
3215 12:45:31.289661 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 12:45:31.293186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 12:45:31.296156 ==
3218 12:45:31.296237 RX Vref Scan: 0
3219 12:45:31.296302
3220 12:45:31.299624 RX Vref 0 -> 0, step: 1
3221 12:45:31.299704
3222 12:45:31.303128 RX Delay -40 -> 252, step: 8
3223 12:45:31.306433 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3224 12:45:31.309401 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3225 12:45:31.312832 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3226 12:45:31.316158 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3227 12:45:31.322694 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3228 12:45:31.326298 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3229 12:45:31.329343 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3230 12:45:31.332446 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3231 12:45:31.335998 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3232 12:45:31.342392 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3233 12:45:31.346152 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3234 12:45:31.349597 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3235 12:45:31.352660 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3236 12:45:31.355889 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3237 12:45:31.362578 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3238 12:45:31.365587 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3239 12:45:31.365669 ==
3240 12:45:31.369139 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 12:45:31.372264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 12:45:31.372393 ==
3243 12:45:31.375619 DQS Delay:
3244 12:45:31.375722 DQS0 = 0, DQS1 = 0
3245 12:45:31.375826 DQM Delay:
3246 12:45:31.378923 DQM0 = 118, DQM1 = 109
3247 12:45:31.379055 DQ Delay:
3248 12:45:31.382240 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3249 12:45:31.385618 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3250 12:45:31.388957 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3251 12:45:31.395782 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3252 12:45:31.395895
3253 12:45:31.396002
3254 12:45:31.396098 ==
3255 12:45:31.399372 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 12:45:31.402198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 12:45:31.402353 ==
3258 12:45:31.402486
3259 12:45:31.402591
3260 12:45:31.405761 TX Vref Scan disable
3261 12:45:31.405844 == TX Byte 0 ==
3262 12:45:31.412364 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3263 12:45:31.415790 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3264 12:45:31.415871 == TX Byte 1 ==
3265 12:45:31.422465 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3266 12:45:31.425574 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3267 12:45:31.425656 ==
3268 12:45:31.428989 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 12:45:31.432426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 12:45:31.432509 ==
3271 12:45:31.444935 TX Vref=22, minBit 10, minWin=24, winSum=411
3272 12:45:31.448120 TX Vref=24, minBit 10, minWin=24, winSum=414
3273 12:45:31.451182 TX Vref=26, minBit 9, minWin=25, winSum=421
3274 12:45:31.454601 TX Vref=28, minBit 9, minWin=25, winSum=426
3275 12:45:31.457640 TX Vref=30, minBit 10, minWin=25, winSum=426
3276 12:45:31.465015 TX Vref=32, minBit 9, minWin=25, winSum=425
3277 12:45:31.467911 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 28
3278 12:45:31.467993
3279 12:45:31.471207 Final TX Range 1 Vref 28
3280 12:45:31.471312
3281 12:45:31.471412 ==
3282 12:45:31.474769 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 12:45:31.477851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 12:45:31.480884 ==
3285 12:45:31.480976
3286 12:45:31.481044
3287 12:45:31.481104 TX Vref Scan disable
3288 12:45:31.484766 == TX Byte 0 ==
3289 12:45:31.487754 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3290 12:45:31.494619 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3291 12:45:31.494695 == TX Byte 1 ==
3292 12:45:31.497811 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3293 12:45:31.504139 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3294 12:45:31.504249
3295 12:45:31.504340 [DATLAT]
3296 12:45:31.504447 Freq=1200, CH1 RK0
3297 12:45:31.504582
3298 12:45:31.507962 DATLAT Default: 0xd
3299 12:45:31.508058 0, 0xFFFF, sum = 0
3300 12:45:31.511361 1, 0xFFFF, sum = 0
3301 12:45:31.514335 2, 0xFFFF, sum = 0
3302 12:45:31.514415 3, 0xFFFF, sum = 0
3303 12:45:31.517673 4, 0xFFFF, sum = 0
3304 12:45:31.517772 5, 0xFFFF, sum = 0
3305 12:45:31.520838 6, 0xFFFF, sum = 0
3306 12:45:31.520913 7, 0xFFFF, sum = 0
3307 12:45:31.524238 8, 0xFFFF, sum = 0
3308 12:45:31.524321 9, 0xFFFF, sum = 0
3309 12:45:31.527481 10, 0xFFFF, sum = 0
3310 12:45:31.527562 11, 0xFFFF, sum = 0
3311 12:45:31.530814 12, 0x0, sum = 1
3312 12:45:31.530895 13, 0x0, sum = 2
3313 12:45:31.533895 14, 0x0, sum = 3
3314 12:45:31.533976 15, 0x0, sum = 4
3315 12:45:31.537654 best_step = 13
3316 12:45:31.537734
3317 12:45:31.537796 ==
3318 12:45:31.540690 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 12:45:31.543908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 12:45:31.543988 ==
3321 12:45:31.544051 RX Vref Scan: 1
3322 12:45:31.547410
3323 12:45:31.547490 Set Vref Range= 32 -> 127
3324 12:45:31.547553
3325 12:45:31.550793 RX Vref 32 -> 127, step: 1
3326 12:45:31.550873
3327 12:45:31.553954 RX Delay -21 -> 252, step: 4
3328 12:45:31.554034
3329 12:45:31.557120 Set Vref, RX VrefLevel [Byte0]: 32
3330 12:45:31.561046 [Byte1]: 32
3331 12:45:31.561125
3332 12:45:31.563757 Set Vref, RX VrefLevel [Byte0]: 33
3333 12:45:31.567388 [Byte1]: 33
3334 12:45:31.571018
3335 12:45:31.571098 Set Vref, RX VrefLevel [Byte0]: 34
3336 12:45:31.574424 [Byte1]: 34
3337 12:45:31.578729
3338 12:45:31.578841 Set Vref, RX VrefLevel [Byte0]: 35
3339 12:45:31.582161 [Byte1]: 35
3340 12:45:31.586645
3341 12:45:31.586724 Set Vref, RX VrefLevel [Byte0]: 36
3342 12:45:31.590679 [Byte1]: 36
3343 12:45:31.594791
3344 12:45:31.594870 Set Vref, RX VrefLevel [Byte0]: 37
3345 12:45:31.598179 [Byte1]: 37
3346 12:45:31.602809
3347 12:45:31.602888 Set Vref, RX VrefLevel [Byte0]: 38
3348 12:45:31.605870 [Byte1]: 38
3349 12:45:31.610452
3350 12:45:31.610532 Set Vref, RX VrefLevel [Byte0]: 39
3351 12:45:31.613801 [Byte1]: 39
3352 12:45:31.618468
3353 12:45:31.618547 Set Vref, RX VrefLevel [Byte0]: 40
3354 12:45:31.622022 [Byte1]: 40
3355 12:45:31.626407
3356 12:45:31.626487 Set Vref, RX VrefLevel [Byte0]: 41
3357 12:45:31.629873 [Byte1]: 41
3358 12:45:31.634488
3359 12:45:31.634567 Set Vref, RX VrefLevel [Byte0]: 42
3360 12:45:31.638153 [Byte1]: 42
3361 12:45:31.642511
3362 12:45:31.642591 Set Vref, RX VrefLevel [Byte0]: 43
3363 12:45:31.645782 [Byte1]: 43
3364 12:45:31.650151
3365 12:45:31.650231 Set Vref, RX VrefLevel [Byte0]: 44
3366 12:45:31.653742 [Byte1]: 44
3367 12:45:31.657911
3368 12:45:31.657990 Set Vref, RX VrefLevel [Byte0]: 45
3369 12:45:31.664333 [Byte1]: 45
3370 12:45:31.664438
3371 12:45:31.668167 Set Vref, RX VrefLevel [Byte0]: 46
3372 12:45:31.670999 [Byte1]: 46
3373 12:45:31.671079
3374 12:45:31.674291 Set Vref, RX VrefLevel [Byte0]: 47
3375 12:45:31.677533 [Byte1]: 47
3376 12:45:31.682178
3377 12:45:31.682257 Set Vref, RX VrefLevel [Byte0]: 48
3378 12:45:31.684980 [Byte1]: 48
3379 12:45:31.689634
3380 12:45:31.689714 Set Vref, RX VrefLevel [Byte0]: 49
3381 12:45:31.693512 [Byte1]: 49
3382 12:45:31.697498
3383 12:45:31.697577 Set Vref, RX VrefLevel [Byte0]: 50
3384 12:45:31.701417 [Byte1]: 50
3385 12:45:31.705538
3386 12:45:31.705616 Set Vref, RX VrefLevel [Byte0]: 51
3387 12:45:31.709216 [Byte1]: 51
3388 12:45:31.713549
3389 12:45:31.713628 Set Vref, RX VrefLevel [Byte0]: 52
3390 12:45:31.716936 [Byte1]: 52
3391 12:45:31.721461
3392 12:45:31.721556 Set Vref, RX VrefLevel [Byte0]: 53
3393 12:45:31.724760 [Byte1]: 53
3394 12:45:31.729457
3395 12:45:31.729530 Set Vref, RX VrefLevel [Byte0]: 54
3396 12:45:31.732781 [Byte1]: 54
3397 12:45:31.737099
3398 12:45:31.737173 Set Vref, RX VrefLevel [Byte0]: 55
3399 12:45:31.740397 [Byte1]: 55
3400 12:45:31.745188
3401 12:45:31.745260 Set Vref, RX VrefLevel [Byte0]: 56
3402 12:45:31.748634 [Byte1]: 56
3403 12:45:31.752835
3404 12:45:31.752908 Set Vref, RX VrefLevel [Byte0]: 57
3405 12:45:31.756834 [Byte1]: 57
3406 12:45:31.761365
3407 12:45:31.761469 Set Vref, RX VrefLevel [Byte0]: 58
3408 12:45:31.764296 [Byte1]: 58
3409 12:45:31.769101
3410 12:45:31.769174 Set Vref, RX VrefLevel [Byte0]: 59
3411 12:45:31.772054 [Byte1]: 59
3412 12:45:31.776970
3413 12:45:31.777041 Set Vref, RX VrefLevel [Byte0]: 60
3414 12:45:31.780740 [Byte1]: 60
3415 12:45:31.784441
3416 12:45:31.784541 Set Vref, RX VrefLevel [Byte0]: 61
3417 12:45:31.787958 [Byte1]: 61
3418 12:45:31.792948
3419 12:45:31.793026 Set Vref, RX VrefLevel [Byte0]: 62
3420 12:45:31.796142 [Byte1]: 62
3421 12:45:31.800757
3422 12:45:31.800838 Set Vref, RX VrefLevel [Byte0]: 63
3423 12:45:31.804470 [Byte1]: 63
3424 12:45:31.808495
3425 12:45:31.808611 Set Vref, RX VrefLevel [Byte0]: 64
3426 12:45:31.811668 [Byte1]: 64
3427 12:45:31.816706
3428 12:45:31.816806 Set Vref, RX VrefLevel [Byte0]: 65
3429 12:45:31.820296 [Byte1]: 65
3430 12:45:31.824780
3431 12:45:31.824861 Set Vref, RX VrefLevel [Byte0]: 66
3432 12:45:31.827599 [Byte1]: 66
3433 12:45:31.832694
3434 12:45:31.832775 Set Vref, RX VrefLevel [Byte0]: 67
3435 12:45:31.835888 [Byte1]: 67
3436 12:45:31.840367
3437 12:45:31.840474 Set Vref, RX VrefLevel [Byte0]: 68
3438 12:45:31.843638 [Byte1]: 68
3439 12:45:31.847994
3440 12:45:31.848142 Final RX Vref Byte 0 = 46 to rank0
3441 12:45:31.851340 Final RX Vref Byte 1 = 52 to rank0
3442 12:45:31.855034 Final RX Vref Byte 0 = 46 to rank1
3443 12:45:31.858143 Final RX Vref Byte 1 = 52 to rank1==
3444 12:45:31.861356 Dram Type= 6, Freq= 0, CH_1, rank 0
3445 12:45:31.868093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 12:45:31.868175 ==
3447 12:45:31.868239 DQS Delay:
3448 12:45:31.871248 DQS0 = 0, DQS1 = 0
3449 12:45:31.871329 DQM Delay:
3450 12:45:31.871393 DQM0 = 116, DQM1 = 109
3451 12:45:31.874707 DQ Delay:
3452 12:45:31.877774 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3453 12:45:31.881559 DQ4 =112, DQ5 =128, DQ6 =126, DQ7 =114
3454 12:45:31.884694 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =100
3455 12:45:31.888035 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =116
3456 12:45:31.888118
3457 12:45:31.888182
3458 12:45:31.897747 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3459 12:45:31.897829 CH1 RK0: MR19=403, MR18=3F7
3460 12:45:31.904763 CH1_RK0: MR19=0x403, MR18=0x3F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3461 12:45:31.904844
3462 12:45:31.907994 ----->DramcWriteLeveling(PI) begin...
3463 12:45:31.908075 ==
3464 12:45:31.911478 Dram Type= 6, Freq= 0, CH_1, rank 1
3465 12:45:31.914616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 12:45:31.917761 ==
3467 12:45:31.917841 Write leveling (Byte 0): 25 => 25
3468 12:45:31.921395 Write leveling (Byte 1): 28 => 28
3469 12:45:31.924386 DramcWriteLeveling(PI) end<-----
3470 12:45:31.924466
3471 12:45:31.924567 ==
3472 12:45:31.927685 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 12:45:31.934496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 12:45:31.934577 ==
3475 12:45:31.937354 [Gating] SW mode calibration
3476 12:45:31.944013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3477 12:45:31.947349 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3478 12:45:31.954230 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 12:45:31.957332 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 12:45:31.960566 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 12:45:31.967270 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 12:45:31.970400 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 12:45:31.974128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 12:45:31.980289 0 15 24 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
3485 12:45:31.983960 0 15 28 | B1->B0 | 2424 2828 | 0 0 | (1 0) (1 0)
3486 12:45:31.986683 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 12:45:31.993373 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 12:45:31.996944 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 12:45:32.000191 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 12:45:32.007482 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 12:45:32.010744 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 12:45:32.013461 1 0 24 | B1->B0 | 3535 2424 | 1 0 | (1 1) (0 0)
3493 12:45:32.019877 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3494 12:45:32.023459 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 12:45:32.026354 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 12:45:32.033308 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 12:45:32.037123 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 12:45:32.039760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 12:45:32.046735 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 12:45:32.049700 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3501 12:45:32.053575 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3502 12:45:32.060362 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 12:45:32.062788 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 12:45:32.066195 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 12:45:32.073066 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 12:45:32.076181 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 12:45:32.079286 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 12:45:32.085986 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 12:45:32.089283 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 12:45:32.092257 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 12:45:32.098932 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 12:45:32.102398 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 12:45:32.106112 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 12:45:32.112372 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 12:45:32.115930 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 12:45:32.119120 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3517 12:45:32.125412 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3518 12:45:32.125494 Total UI for P1: 0, mck2ui 16
3519 12:45:32.132354 best dqsien dly found for B1: ( 1, 3, 24)
3520 12:45:32.135376 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 12:45:32.138807 Total UI for P1: 0, mck2ui 16
3522 12:45:32.142352 best dqsien dly found for B0: ( 1, 3, 26)
3523 12:45:32.145284 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3524 12:45:32.148785 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3525 12:45:32.148865
3526 12:45:32.152448 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3527 12:45:32.155109 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3528 12:45:32.158922 [Gating] SW calibration Done
3529 12:45:32.159002 ==
3530 12:45:32.161600 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 12:45:32.165205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 12:45:32.168463 ==
3533 12:45:32.168551 RX Vref Scan: 0
3534 12:45:32.168669
3535 12:45:32.171785 RX Vref 0 -> 0, step: 1
3536 12:45:32.171889
3537 12:45:32.174867 RX Delay -40 -> 252, step: 8
3538 12:45:32.178607 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3539 12:45:32.181278 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3540 12:45:32.184715 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3541 12:45:32.188108 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3542 12:45:32.194680 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3543 12:45:32.197945 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3544 12:45:32.201165 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3545 12:45:32.204801 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3546 12:45:32.207654 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3547 12:45:32.214334 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3548 12:45:32.217654 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3549 12:45:32.220993 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3550 12:45:32.224068 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3551 12:45:32.227462 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3552 12:45:32.234052 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3553 12:45:32.237687 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3554 12:45:32.237768 ==
3555 12:45:32.240737 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 12:45:32.244243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 12:45:32.244341 ==
3558 12:45:32.247317 DQS Delay:
3559 12:45:32.247397 DQS0 = 0, DQS1 = 0
3560 12:45:32.250820 DQM Delay:
3561 12:45:32.250901 DQM0 = 116, DQM1 = 109
3562 12:45:32.250964 DQ Delay:
3563 12:45:32.254012 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3564 12:45:32.260729 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3565 12:45:32.263905 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3566 12:45:32.267852 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3567 12:45:32.267932
3568 12:45:32.267996
3569 12:45:32.268054 ==
3570 12:45:32.270065 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 12:45:32.273581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 12:45:32.273662 ==
3573 12:45:32.273734
3574 12:45:32.273795
3575 12:45:32.276829 TX Vref Scan disable
3576 12:45:32.280173 == TX Byte 0 ==
3577 12:45:32.283472 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3578 12:45:32.287109 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3579 12:45:32.289892 == TX Byte 1 ==
3580 12:45:32.293096 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3581 12:45:32.296685 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3582 12:45:32.296766 ==
3583 12:45:32.300241 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 12:45:32.306486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 12:45:32.306567 ==
3586 12:45:32.317046 TX Vref=22, minBit 9, minWin=24, winSum=418
3587 12:45:32.320315 TX Vref=24, minBit 9, minWin=25, winSum=425
3588 12:45:32.323259 TX Vref=26, minBit 9, minWin=25, winSum=430
3589 12:45:32.326779 TX Vref=28, minBit 11, minWin=26, winSum=437
3590 12:45:32.330156 TX Vref=30, minBit 9, minWin=26, winSum=437
3591 12:45:32.336471 TX Vref=32, minBit 8, minWin=26, winSum=433
3592 12:45:32.340001 [TxChooseVref] Worse bit 11, Min win 26, Win sum 437, Final Vref 28
3593 12:45:32.340083
3594 12:45:32.343307 Final TX Range 1 Vref 28
3595 12:45:32.343387
3596 12:45:32.343486 ==
3597 12:45:32.346629 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 12:45:32.353068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 12:45:32.353148 ==
3600 12:45:32.353213
3601 12:45:32.353272
3602 12:45:32.353329 TX Vref Scan disable
3603 12:45:32.356699 == TX Byte 0 ==
3604 12:45:32.360392 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3605 12:45:32.366469 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3606 12:45:32.366566 == TX Byte 1 ==
3607 12:45:32.370091 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3608 12:45:32.376335 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3609 12:45:32.376444
3610 12:45:32.376567 [DATLAT]
3611 12:45:32.376630 Freq=1200, CH1 RK1
3612 12:45:32.376687
3613 12:45:32.379593 DATLAT Default: 0xd
3614 12:45:32.383133 0, 0xFFFF, sum = 0
3615 12:45:32.383216 1, 0xFFFF, sum = 0
3616 12:45:32.386418 2, 0xFFFF, sum = 0
3617 12:45:32.386838 3, 0xFFFF, sum = 0
3618 12:45:32.390218 4, 0xFFFF, sum = 0
3619 12:45:32.390640 5, 0xFFFF, sum = 0
3620 12:45:32.393200 6, 0xFFFF, sum = 0
3621 12:45:32.393645 7, 0xFFFF, sum = 0
3622 12:45:32.396465 8, 0xFFFF, sum = 0
3623 12:45:32.396914 9, 0xFFFF, sum = 0
3624 12:45:32.400076 10, 0xFFFF, sum = 0
3625 12:45:32.400652 11, 0xFFFF, sum = 0
3626 12:45:32.403203 12, 0x0, sum = 1
3627 12:45:32.403626 13, 0x0, sum = 2
3628 12:45:32.406256 14, 0x0, sum = 3
3629 12:45:32.406674 15, 0x0, sum = 4
3630 12:45:32.409780 best_step = 13
3631 12:45:32.410245
3632 12:45:32.410576 ==
3633 12:45:32.413115 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 12:45:32.416754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 12:45:32.417291 ==
3636 12:45:32.419660 RX Vref Scan: 0
3637 12:45:32.420201
3638 12:45:32.420566 RX Vref 0 -> 0, step: 1
3639 12:45:32.420887
3640 12:45:32.423229 RX Delay -21 -> 252, step: 4
3641 12:45:32.429380 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3642 12:45:32.432850 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3643 12:45:32.435979 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3644 12:45:32.439249 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3645 12:45:32.442697 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3646 12:45:32.449599 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3647 12:45:32.452974 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3648 12:45:32.456033 iDelay=199, Bit 7, Center 112 (47 ~ 178) 132
3649 12:45:32.459405 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3650 12:45:32.463229 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3651 12:45:32.469118 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3652 12:45:32.472497 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3653 12:45:32.475288 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3654 12:45:32.478551 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3655 12:45:32.485776 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3656 12:45:32.488881 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3657 12:45:32.489438 ==
3658 12:45:32.492391 Dram Type= 6, Freq= 0, CH_1, rank 1
3659 12:45:32.495332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3660 12:45:32.495822 ==
3661 12:45:32.498596 DQS Delay:
3662 12:45:32.499247 DQS0 = 0, DQS1 = 0
3663 12:45:32.499726 DQM Delay:
3664 12:45:32.501780 DQM0 = 116, DQM1 = 109
3665 12:45:32.502311 DQ Delay:
3666 12:45:32.505152 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3667 12:45:32.508484 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =112
3668 12:45:32.512177 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3669 12:45:32.518783 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3670 12:45:32.519293
3671 12:45:32.519645
3672 12:45:32.525274 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3673 12:45:32.528388 CH1 RK1: MR19=303, MR18=F3ED
3674 12:45:32.534526 CH1_RK1: MR19=0x303, MR18=0xF3ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3675 12:45:32.537941 [RxdqsGatingPostProcess] freq 1200
3676 12:45:32.541515 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3677 12:45:32.544519 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 12:45:32.547766 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 12:45:32.551057 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 12:45:32.554552 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 12:45:32.558072 best DQS0 dly(2T, 0.5T) = (0, 11)
3682 12:45:32.560936 best DQS1 dly(2T, 0.5T) = (0, 11)
3683 12:45:32.564166 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3684 12:45:32.567871 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3685 12:45:32.570792 Pre-setting of DQS Precalculation
3686 12:45:32.577959 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3687 12:45:32.584663 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3688 12:45:32.591514 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3689 12:45:32.592057
3690 12:45:32.592403
3691 12:45:32.594567 [Calibration Summary] 2400 Mbps
3692 12:45:32.594992 CH 0, Rank 0
3693 12:45:32.597706 SW Impedance : PASS
3694 12:45:32.601398 DUTY Scan : NO K
3695 12:45:32.601822 ZQ Calibration : PASS
3696 12:45:32.604191 Jitter Meter : NO K
3697 12:45:32.604864 CBT Training : PASS
3698 12:45:32.607396 Write leveling : PASS
3699 12:45:32.610987 RX DQS gating : PASS
3700 12:45:32.611594 RX DQ/DQS(RDDQC) : PASS
3701 12:45:32.614599 TX DQ/DQS : PASS
3702 12:45:32.617386 RX DATLAT : PASS
3703 12:45:32.617805 RX DQ/DQS(Engine): PASS
3704 12:45:32.620937 TX OE : NO K
3705 12:45:32.621362 All Pass.
3706 12:45:32.621692
3707 12:45:32.624295 CH 0, Rank 1
3708 12:45:32.624756 SW Impedance : PASS
3709 12:45:32.627228 DUTY Scan : NO K
3710 12:45:32.630826 ZQ Calibration : PASS
3711 12:45:32.631249 Jitter Meter : NO K
3712 12:45:32.634168 CBT Training : PASS
3713 12:45:32.637670 Write leveling : PASS
3714 12:45:32.638092 RX DQS gating : PASS
3715 12:45:32.640937 RX DQ/DQS(RDDQC) : PASS
3716 12:45:32.644015 TX DQ/DQS : PASS
3717 12:45:32.644436 RX DATLAT : PASS
3718 12:45:32.647091 RX DQ/DQS(Engine): PASS
3719 12:45:32.650419 TX OE : NO K
3720 12:45:32.650502 All Pass.
3721 12:45:32.650567
3722 12:45:32.650626 CH 1, Rank 0
3723 12:45:32.653517 SW Impedance : PASS
3724 12:45:32.656671 DUTY Scan : NO K
3725 12:45:32.656753 ZQ Calibration : PASS
3726 12:45:32.660501 Jitter Meter : NO K
3727 12:45:32.663531 CBT Training : PASS
3728 12:45:32.663695 Write leveling : PASS
3729 12:45:32.666913 RX DQS gating : PASS
3730 12:45:32.669788 RX DQ/DQS(RDDQC) : PASS
3731 12:45:32.669883 TX DQ/DQS : PASS
3732 12:45:32.672978 RX DATLAT : PASS
3733 12:45:32.676398 RX DQ/DQS(Engine): PASS
3734 12:45:32.676549 TX OE : NO K
3735 12:45:32.676642 All Pass.
3736 12:45:32.680384
3737 12:45:32.680595 CH 1, Rank 1
3738 12:45:32.683228 SW Impedance : PASS
3739 12:45:32.683428 DUTY Scan : NO K
3740 12:45:32.687027 ZQ Calibration : PASS
3741 12:45:32.689784 Jitter Meter : NO K
3742 12:45:32.689974 CBT Training : PASS
3743 12:45:32.692971 Write leveling : PASS
3744 12:45:32.693166 RX DQS gating : PASS
3745 12:45:32.696735 RX DQ/DQS(RDDQC) : PASS
3746 12:45:32.700075 TX DQ/DQS : PASS
3747 12:45:32.700332 RX DATLAT : PASS
3748 12:45:32.703373 RX DQ/DQS(Engine): PASS
3749 12:45:32.706760 TX OE : NO K
3750 12:45:32.707088 All Pass.
3751 12:45:32.707292
3752 12:45:32.710262 DramC Write-DBI off
3753 12:45:32.710592 PER_BANK_REFRESH: Hybrid Mode
3754 12:45:32.713719 TX_TRACKING: ON
3755 12:45:32.723203 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3756 12:45:32.726311 [FAST_K] Save calibration result to emmc
3757 12:45:32.730015 dramc_set_vcore_voltage set vcore to 650000
3758 12:45:32.730483 Read voltage for 600, 5
3759 12:45:32.733416 Vio18 = 0
3760 12:45:32.733836 Vcore = 650000
3761 12:45:32.734168 Vdram = 0
3762 12:45:32.736653 Vddq = 0
3763 12:45:32.737070 Vmddr = 0
3764 12:45:32.743245 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3765 12:45:32.745874 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3766 12:45:32.749574 MEM_TYPE=3, freq_sel=19
3767 12:45:32.752824 sv_algorithm_assistance_LP4_1600
3768 12:45:32.755861 ============ PULL DRAM RESETB DOWN ============
3769 12:45:32.759323 ========== PULL DRAM RESETB DOWN end =========
3770 12:45:32.766365 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3771 12:45:32.769158 ===================================
3772 12:45:32.769604 LPDDR4 DRAM CONFIGURATION
3773 12:45:32.772263 ===================================
3774 12:45:32.775681 EX_ROW_EN[0] = 0x0
3775 12:45:32.779221 EX_ROW_EN[1] = 0x0
3776 12:45:32.779639 LP4Y_EN = 0x0
3777 12:45:32.782230 WORK_FSP = 0x0
3778 12:45:32.782651 WL = 0x2
3779 12:45:32.786129 RL = 0x2
3780 12:45:32.786548 BL = 0x2
3781 12:45:32.789116 RPST = 0x0
3782 12:45:32.789534 RD_PRE = 0x0
3783 12:45:32.792366 WR_PRE = 0x1
3784 12:45:32.792860 WR_PST = 0x0
3785 12:45:32.795785 DBI_WR = 0x0
3786 12:45:32.796304 DBI_RD = 0x0
3787 12:45:32.798922 OTF = 0x1
3788 12:45:32.802474 ===================================
3789 12:45:32.805830 ===================================
3790 12:45:32.806349 ANA top config
3791 12:45:32.808802 ===================================
3792 12:45:32.812173 DLL_ASYNC_EN = 0
3793 12:45:32.815882 ALL_SLAVE_EN = 1
3794 12:45:32.818745 NEW_RANK_MODE = 1
3795 12:45:32.819272 DLL_IDLE_MODE = 1
3796 12:45:32.821657 LP45_APHY_COMB_EN = 1
3797 12:45:32.825193 TX_ODT_DIS = 1
3798 12:45:32.828467 NEW_8X_MODE = 1
3799 12:45:32.831843 ===================================
3800 12:45:32.834932 ===================================
3801 12:45:32.838561 data_rate = 1200
3802 12:45:32.838982 CKR = 1
3803 12:45:32.841800 DQ_P2S_RATIO = 8
3804 12:45:32.845241 ===================================
3805 12:45:32.848250 CA_P2S_RATIO = 8
3806 12:45:32.851335 DQ_CA_OPEN = 0
3807 12:45:32.854693 DQ_SEMI_OPEN = 0
3808 12:45:32.857837 CA_SEMI_OPEN = 0
3809 12:45:32.858063 CA_FULL_RATE = 0
3810 12:45:32.861604 DQ_CKDIV4_EN = 1
3811 12:45:32.864654 CA_CKDIV4_EN = 1
3812 12:45:32.867970 CA_PREDIV_EN = 0
3813 12:45:32.871504 PH8_DLY = 0
3814 12:45:32.874663 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3815 12:45:32.877724 DQ_AAMCK_DIV = 4
3816 12:45:32.877841 CA_AAMCK_DIV = 4
3817 12:45:32.880700 CA_ADMCK_DIV = 4
3818 12:45:32.884055 DQ_TRACK_CA_EN = 0
3819 12:45:32.887466 CA_PICK = 600
3820 12:45:32.890883 CA_MCKIO = 600
3821 12:45:32.893793 MCKIO_SEMI = 0
3822 12:45:32.897547 PLL_FREQ = 2288
3823 12:45:32.897630 DQ_UI_PI_RATIO = 32
3824 12:45:32.901030 CA_UI_PI_RATIO = 0
3825 12:45:32.903779 ===================================
3826 12:45:32.907350 ===================================
3827 12:45:32.910765 memory_type:LPDDR4
3828 12:45:32.913678 GP_NUM : 10
3829 12:45:32.913760 SRAM_EN : 1
3830 12:45:32.917157 MD32_EN : 0
3831 12:45:32.920248 ===================================
3832 12:45:32.923577 [ANA_INIT] >>>>>>>>>>>>>>
3833 12:45:32.923660 <<<<<< [CONFIGURE PHASE]: ANA_TX
3834 12:45:32.930239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3835 12:45:32.934006 ===================================
3836 12:45:32.934094 data_rate = 1200,PCW = 0X5800
3837 12:45:32.936963 ===================================
3838 12:45:32.939964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3839 12:45:32.947377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3840 12:45:32.953436 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3841 12:45:32.957181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3842 12:45:32.960068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3843 12:45:32.963244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3844 12:45:32.966511 [ANA_INIT] flow start
3845 12:45:32.966724 [ANA_INIT] PLL >>>>>>>>
3846 12:45:32.969803 [ANA_INIT] PLL <<<<<<<<
3847 12:45:32.973972 [ANA_INIT] MIDPI >>>>>>>>
3848 12:45:32.976586 [ANA_INIT] MIDPI <<<<<<<<
3849 12:45:32.976838 [ANA_INIT] DLL >>>>>>>>
3850 12:45:32.980233 [ANA_INIT] flow end
3851 12:45:32.983150 ============ LP4 DIFF to SE enter ============
3852 12:45:32.987280 ============ LP4 DIFF to SE exit ============
3853 12:45:32.990341 [ANA_INIT] <<<<<<<<<<<<<
3854 12:45:32.994001 [Flow] Enable top DCM control >>>>>
3855 12:45:32.996912 [Flow] Enable top DCM control <<<<<
3856 12:45:32.999903 Enable DLL master slave shuffle
3857 12:45:33.006695 ==============================================================
3858 12:45:33.007261 Gating Mode config
3859 12:45:33.013098 ==============================================================
3860 12:45:33.013675 Config description:
3861 12:45:33.023081 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3862 12:45:33.029845 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3863 12:45:33.036207 SELPH_MODE 0: By rank 1: By Phase
3864 12:45:33.039258 ==============================================================
3865 12:45:33.042683 GAT_TRACK_EN = 1
3866 12:45:33.045810 RX_GATING_MODE = 2
3867 12:45:33.049228 RX_GATING_TRACK_MODE = 2
3868 12:45:33.052683 SELPH_MODE = 1
3869 12:45:33.056050 PICG_EARLY_EN = 1
3870 12:45:33.059601 VALID_LAT_VALUE = 1
3871 12:45:33.065842 ==============================================================
3872 12:45:33.069226 Enter into Gating configuration >>>>
3873 12:45:33.072510 Exit from Gating configuration <<<<
3874 12:45:33.076178 Enter into DVFS_PRE_config >>>>>
3875 12:45:33.085691 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3876 12:45:33.089305 Exit from DVFS_PRE_config <<<<<
3877 12:45:33.092508 Enter into PICG configuration >>>>
3878 12:45:33.095315 Exit from PICG configuration <<<<
3879 12:45:33.098738 [RX_INPUT] configuration >>>>>
3880 12:45:33.102247 [RX_INPUT] configuration <<<<<
3881 12:45:33.105655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3882 12:45:33.112416 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3883 12:45:33.118285 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3884 12:45:33.125125 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3885 12:45:33.128414 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3886 12:45:33.135259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3887 12:45:33.138532 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3888 12:45:33.144827 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3889 12:45:33.147913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3890 12:45:33.151156 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3891 12:45:33.155053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3892 12:45:33.161703 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3893 12:45:33.164754 ===================================
3894 12:45:33.168115 LPDDR4 DRAM CONFIGURATION
3895 12:45:33.171005 ===================================
3896 12:45:33.171470 EX_ROW_EN[0] = 0x0
3897 12:45:33.175004 EX_ROW_EN[1] = 0x0
3898 12:45:33.175565 LP4Y_EN = 0x0
3899 12:45:33.178157 WORK_FSP = 0x0
3900 12:45:33.178716 WL = 0x2
3901 12:45:33.181266 RL = 0x2
3902 12:45:33.181825 BL = 0x2
3903 12:45:33.184272 RPST = 0x0
3904 12:45:33.184773 RD_PRE = 0x0
3905 12:45:33.188223 WR_PRE = 0x1
3906 12:45:33.188817 WR_PST = 0x0
3907 12:45:33.190699 DBI_WR = 0x0
3908 12:45:33.194411 DBI_RD = 0x0
3909 12:45:33.194983 OTF = 0x1
3910 12:45:33.197415 ===================================
3911 12:45:33.201020 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3912 12:45:33.204172 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3913 12:45:33.211068 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3914 12:45:33.214080 ===================================
3915 12:45:33.217200 LPDDR4 DRAM CONFIGURATION
3916 12:45:33.220595 ===================================
3917 12:45:33.221059 EX_ROW_EN[0] = 0x10
3918 12:45:33.224385 EX_ROW_EN[1] = 0x0
3919 12:45:33.224875 LP4Y_EN = 0x0
3920 12:45:33.227088 WORK_FSP = 0x0
3921 12:45:33.227550 WL = 0x2
3922 12:45:33.230519 RL = 0x2
3923 12:45:33.231091 BL = 0x2
3924 12:45:33.233810 RPST = 0x0
3925 12:45:33.234375 RD_PRE = 0x0
3926 12:45:33.237470 WR_PRE = 0x1
3927 12:45:33.238027 WR_PST = 0x0
3928 12:45:33.240624 DBI_WR = 0x0
3929 12:45:33.244307 DBI_RD = 0x0
3930 12:45:33.244899 OTF = 0x1
3931 12:45:33.247281 ===================================
3932 12:45:33.253386 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3933 12:45:33.257199 nWR fixed to 30
3934 12:45:33.260671 [ModeRegInit_LP4] CH0 RK0
3935 12:45:33.261232 [ModeRegInit_LP4] CH0 RK1
3936 12:45:33.263923 [ModeRegInit_LP4] CH1 RK0
3937 12:45:33.267251 [ModeRegInit_LP4] CH1 RK1
3938 12:45:33.267823 match AC timing 17
3939 12:45:33.274209 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3940 12:45:33.277034 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3941 12:45:33.280642 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3942 12:45:33.287247 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3943 12:45:33.290506 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3944 12:45:33.291062 ==
3945 12:45:33.294288 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 12:45:33.297083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 12:45:33.297551 ==
3948 12:45:33.303877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3949 12:45:33.310364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3950 12:45:33.313409 [CA 0] Center 36 (6~66) winsize 61
3951 12:45:33.316625 [CA 1] Center 36 (6~66) winsize 61
3952 12:45:33.320059 [CA 2] Center 34 (3~65) winsize 63
3953 12:45:33.323765 [CA 3] Center 34 (4~65) winsize 62
3954 12:45:33.326769 [CA 4] Center 33 (3~64) winsize 62
3955 12:45:33.330190 [CA 5] Center 33 (3~64) winsize 62
3956 12:45:33.330757
3957 12:45:33.333035 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3958 12:45:33.333501
3959 12:45:33.336492 [CATrainingPosCal] consider 1 rank data
3960 12:45:33.339764 u2DelayCellTimex100 = 270/100 ps
3961 12:45:33.342651 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3962 12:45:33.346263 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 12:45:33.349686 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3964 12:45:33.356571 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3965 12:45:33.359255 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 12:45:33.362678 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 12:45:33.363392
3968 12:45:33.366599 CA PerBit enable=1, Macro0, CA PI delay=33
3969 12:45:33.367177
3970 12:45:33.369365 [CBTSetCACLKResult] CA Dly = 33
3971 12:45:33.369829 CS Dly: 5 (0~36)
3972 12:45:33.370198 ==
3973 12:45:33.372899 Dram Type= 6, Freq= 0, CH_0, rank 1
3974 12:45:33.379427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 12:45:33.379998 ==
3976 12:45:33.382961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 12:45:33.389109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3978 12:45:33.392579 [CA 0] Center 35 (5~66) winsize 62
3979 12:45:33.395569 [CA 1] Center 36 (6~66) winsize 61
3980 12:45:33.399045 [CA 2] Center 33 (3~64) winsize 62
3981 12:45:33.402644 [CA 3] Center 33 (3~64) winsize 62
3982 12:45:33.406073 [CA 4] Center 33 (3~64) winsize 62
3983 12:45:33.408972 [CA 5] Center 33 (2~64) winsize 63
3984 12:45:33.409535
3985 12:45:33.412056 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3986 12:45:33.412543
3987 12:45:33.415242 [CATrainingPosCal] consider 2 rank data
3988 12:45:33.418731 u2DelayCellTimex100 = 270/100 ps
3989 12:45:33.422032 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3990 12:45:33.428800 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 12:45:33.432133 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
3992 12:45:33.435559 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3993 12:45:33.439182 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 12:45:33.441694 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 12:45:33.442162
3996 12:45:33.445544 CA PerBit enable=1, Macro0, CA PI delay=33
3997 12:45:33.446173
3998 12:45:33.448915 [CBTSetCACLKResult] CA Dly = 33
3999 12:45:33.452059 CS Dly: 5 (0~37)
4000 12:45:33.452645
4001 12:45:33.455402 ----->DramcWriteLeveling(PI) begin...
4002 12:45:33.455966 ==
4003 12:45:33.458949 Dram Type= 6, Freq= 0, CH_0, rank 0
4004 12:45:33.461708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4005 12:45:33.462178 ==
4006 12:45:33.465495 Write leveling (Byte 0): 34 => 34
4007 12:45:33.468301 Write leveling (Byte 1): 28 => 28
4008 12:45:33.472049 DramcWriteLeveling(PI) end<-----
4009 12:45:33.472544
4010 12:45:33.472929 ==
4011 12:45:33.474544 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 12:45:33.478066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 12:45:33.478632 ==
4014 12:45:33.481468 [Gating] SW mode calibration
4015 12:45:33.488024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4016 12:45:33.494439 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4017 12:45:33.498019 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 12:45:33.501350 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 12:45:33.508076 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 12:45:33.510987 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4021 12:45:33.515758 0 9 16 | B1->B0 | 3131 2929 | 0 0 | (0 0) (0 0)
4022 12:45:33.520927 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 12:45:33.524421 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 12:45:33.527657 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 12:45:33.534295 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 12:45:33.537850 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 12:45:33.540566 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 12:45:33.547219 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
4029 12:45:33.550927 0 10 16 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
4030 12:45:33.554376 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4031 12:45:33.561437 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 12:45:33.564330 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 12:45:33.567136 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 12:45:33.573836 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 12:45:33.576964 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 12:45:33.580293 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 12:45:33.587274 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4038 12:45:33.590250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 12:45:33.593620 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:45:33.600243 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 12:45:33.603753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 12:45:33.606974 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 12:45:33.613104 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 12:45:33.617059 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 12:45:33.619838 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 12:45:33.626895 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:45:33.629538 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 12:45:33.633097 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 12:45:33.639803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 12:45:33.643103 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:45:33.646086 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:45:33.653053 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:45:33.656328 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4054 12:45:33.659491 Total UI for P1: 0, mck2ui 16
4055 12:45:33.662978 best dqsien dly found for B0: ( 0, 13, 14)
4056 12:45:33.665894 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 12:45:33.669632 Total UI for P1: 0, mck2ui 16
4058 12:45:33.673287 best dqsien dly found for B1: ( 0, 13, 16)
4059 12:45:33.676165 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4060 12:45:33.682628 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4061 12:45:33.683179
4062 12:45:33.685885 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4063 12:45:33.689177 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4064 12:45:33.692615 [Gating] SW calibration Done
4065 12:45:33.693100 ==
4066 12:45:33.696035 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 12:45:33.699184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 12:45:33.699651 ==
4069 12:45:33.702631 RX Vref Scan: 0
4070 12:45:33.703204
4071 12:45:33.703579 RX Vref 0 -> 0, step: 1
4072 12:45:33.703920
4073 12:45:33.706095 RX Delay -230 -> 252, step: 16
4074 12:45:33.709487 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4075 12:45:33.716870 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4076 12:45:33.719339 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4077 12:45:33.722597 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4078 12:45:33.726026 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4079 12:45:33.732148 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4080 12:45:33.735573 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4081 12:45:33.739058 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4082 12:45:33.741737 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4083 12:45:33.745678 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4084 12:45:33.752092 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4085 12:45:33.755440 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4086 12:45:33.758854 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4087 12:45:33.761448 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4088 12:45:33.768388 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4089 12:45:33.771414 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4090 12:45:33.772040 ==
4091 12:45:33.775014 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 12:45:33.778091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 12:45:33.778570 ==
4094 12:45:33.781670 DQS Delay:
4095 12:45:33.782207 DQS0 = 0, DQS1 = 0
4096 12:45:33.784504 DQM Delay:
4097 12:45:33.785009 DQM0 = 41, DQM1 = 31
4098 12:45:33.785379 DQ Delay:
4099 12:45:33.788060 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4100 12:45:33.791305 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4101 12:45:33.794336 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4102 12:45:33.797612 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4103 12:45:33.798077
4104 12:45:33.798447
4105 12:45:33.801443 ==
4106 12:45:33.804722 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 12:45:33.807679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 12:45:33.808099 ==
4109 12:45:33.808432
4110 12:45:33.808801
4111 12:45:33.810670 TX Vref Scan disable
4112 12:45:33.811088 == TX Byte 0 ==
4113 12:45:33.817298 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4114 12:45:33.821190 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4115 12:45:33.821611 == TX Byte 1 ==
4116 12:45:33.827271 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4117 12:45:33.830629 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4118 12:45:33.831050 ==
4119 12:45:33.833707 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 12:45:33.837264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 12:45:33.837816 ==
4122 12:45:33.838248
4123 12:45:33.838653
4124 12:45:33.840435 TX Vref Scan disable
4125 12:45:33.843667 == TX Byte 0 ==
4126 12:45:33.847138 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4127 12:45:33.854290 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4128 12:45:33.854713 == TX Byte 1 ==
4129 12:45:33.857033 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4130 12:45:33.863685 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4131 12:45:33.864106
4132 12:45:33.864439 [DATLAT]
4133 12:45:33.864928 Freq=600, CH0 RK0
4134 12:45:33.865254
4135 12:45:33.867226 DATLAT Default: 0x9
4136 12:45:33.867641 0, 0xFFFF, sum = 0
4137 12:45:33.870137 1, 0xFFFF, sum = 0
4138 12:45:33.874387 2, 0xFFFF, sum = 0
4139 12:45:33.874814 3, 0xFFFF, sum = 0
4140 12:45:33.876863 4, 0xFFFF, sum = 0
4141 12:45:33.877292 5, 0xFFFF, sum = 0
4142 12:45:33.880327 6, 0xFFFF, sum = 0
4143 12:45:33.880785 7, 0xFFFF, sum = 0
4144 12:45:33.883608 8, 0x0, sum = 1
4145 12:45:33.884052 9, 0x0, sum = 2
4146 12:45:33.884387 10, 0x0, sum = 3
4147 12:45:33.887017 11, 0x0, sum = 4
4148 12:45:33.887604 best_step = 9
4149 12:45:33.888147
4150 12:45:33.888679 ==
4151 12:45:33.890319 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 12:45:33.896943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 12:45:33.897366 ==
4154 12:45:33.897704 RX Vref Scan: 1
4155 12:45:33.898018
4156 12:45:33.899920 RX Vref 0 -> 0, step: 1
4157 12:45:33.900339
4158 12:45:33.903427 RX Delay -195 -> 252, step: 8
4159 12:45:33.903847
4160 12:45:33.907104 Set Vref, RX VrefLevel [Byte0]: 55
4161 12:45:33.910580 [Byte1]: 57
4162 12:45:33.911000
4163 12:45:33.912996 Final RX Vref Byte 0 = 55 to rank0
4164 12:45:33.916709 Final RX Vref Byte 1 = 57 to rank0
4165 12:45:33.919689 Final RX Vref Byte 0 = 55 to rank1
4166 12:45:33.923469 Final RX Vref Byte 1 = 57 to rank1==
4167 12:45:33.926504 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 12:45:33.929862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 12:45:33.930283 ==
4170 12:45:33.933293 DQS Delay:
4171 12:45:33.933713 DQS0 = 0, DQS1 = 0
4172 12:45:33.936500 DQM Delay:
4173 12:45:33.936945 DQM0 = 44, DQM1 = 32
4174 12:45:33.939852 DQ Delay:
4175 12:45:33.940270 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4176 12:45:33.942771 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4177 12:45:33.946451 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4178 12:45:33.949854 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4179 12:45:33.950274
4180 12:45:33.952730
4181 12:45:33.960078 [DQSOSCAuto] RK0, (LSB)MR18= 0x643c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4182 12:45:33.962949 CH0 RK0: MR19=808, MR18=643C
4183 12:45:33.969405 CH0_RK0: MR19=0x808, MR18=0x643C, DQSOSC=391, MR23=63, INC=171, DEC=114
4184 12:45:33.969862
4185 12:45:33.972490 ----->DramcWriteLeveling(PI) begin...
4186 12:45:33.972962 ==
4187 12:45:33.975866 Dram Type= 6, Freq= 0, CH_0, rank 1
4188 12:45:33.979444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 12:45:33.979526 ==
4190 12:45:33.982525 Write leveling (Byte 0): 32 => 32
4191 12:45:33.985950 Write leveling (Byte 1): 32 => 32
4192 12:45:33.988955 DramcWriteLeveling(PI) end<-----
4193 12:45:33.989037
4194 12:45:33.989101 ==
4195 12:45:33.992278 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 12:45:33.995738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 12:45:33.995820 ==
4198 12:45:33.998943 [Gating] SW mode calibration
4199 12:45:34.005926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4200 12:45:34.012124 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4201 12:45:34.015580 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 12:45:34.019336 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 12:45:34.025635 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 12:45:34.028733 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4205 12:45:34.032322 0 9 16 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
4206 12:45:34.038417 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 12:45:34.042437 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 12:45:34.045571 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 12:45:34.052351 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 12:45:34.055134 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 12:45:34.058489 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 12:45:34.065193 0 10 12 | B1->B0 | 2525 2626 | 0 0 | (0 0) (1 1)
4213 12:45:34.068467 0 10 16 | B1->B0 | 3838 3b3b | 0 0 | (0 0) (0 0)
4214 12:45:34.071816 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 12:45:34.078240 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 12:45:34.081839 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 12:45:34.085601 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 12:45:34.091636 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 12:45:34.094850 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 12:45:34.098269 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4221 12:45:34.105238 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4222 12:45:34.108387 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 12:45:34.112034 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 12:45:34.118640 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 12:45:34.121450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 12:45:34.124788 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 12:45:34.132058 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 12:45:34.134784 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 12:45:34.138330 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 12:45:34.144762 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 12:45:34.148468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 12:45:34.151519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 12:45:34.158206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 12:45:34.161584 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 12:45:34.164839 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 12:45:34.171570 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4237 12:45:34.174979 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4238 12:45:34.178003 Total UI for P1: 0, mck2ui 16
4239 12:45:34.180889 best dqsien dly found for B0: ( 0, 13, 12)
4240 12:45:34.184276 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 12:45:34.187368 Total UI for P1: 0, mck2ui 16
4242 12:45:34.191025 best dqsien dly found for B1: ( 0, 13, 14)
4243 12:45:34.194114 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4244 12:45:34.197673 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4245 12:45:34.200574
4246 12:45:34.204361 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4247 12:45:34.207152 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4248 12:45:34.210990 [Gating] SW calibration Done
4249 12:45:34.211409 ==
4250 12:45:34.214102 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 12:45:34.217519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 12:45:34.218036 ==
4253 12:45:34.218371 RX Vref Scan: 0
4254 12:45:34.220579
4255 12:45:34.220999 RX Vref 0 -> 0, step: 1
4256 12:45:34.221336
4257 12:45:34.224212 RX Delay -230 -> 252, step: 16
4258 12:45:34.227042 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4259 12:45:34.233902 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4260 12:45:34.237029 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4261 12:45:34.240790 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4262 12:45:34.243522 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4263 12:45:34.247134 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4264 12:45:34.253736 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4265 12:45:34.257080 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4266 12:45:34.260691 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4267 12:45:34.263366 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4268 12:45:34.270348 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4269 12:45:34.273639 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4270 12:45:34.276977 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4271 12:45:34.279930 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4272 12:45:34.286718 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4273 12:45:34.290342 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4274 12:45:34.290764 ==
4275 12:45:34.293364 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 12:45:34.296377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 12:45:34.296842 ==
4278 12:45:34.299530 DQS Delay:
4279 12:45:34.299947 DQS0 = 0, DQS1 = 0
4280 12:45:34.300279 DQM Delay:
4281 12:45:34.303050 DQM0 = 44, DQM1 = 36
4282 12:45:34.303500 DQ Delay:
4283 12:45:34.306844 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4284 12:45:34.309672 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4285 12:45:34.312677 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4286 12:45:34.316153 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4287 12:45:34.316599
4288 12:45:34.316941
4289 12:45:34.317249 ==
4290 12:45:34.319836 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 12:45:34.325941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 12:45:34.326365 ==
4293 12:45:34.326694
4294 12:45:34.326995
4295 12:45:34.327284 TX Vref Scan disable
4296 12:45:34.329861 == TX Byte 0 ==
4297 12:45:34.333455 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4298 12:45:34.340975 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4299 12:45:34.341399 == TX Byte 1 ==
4300 12:45:34.343259 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4301 12:45:34.350351 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4302 12:45:34.350762 ==
4303 12:45:34.353169 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 12:45:34.356283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 12:45:34.356605 ==
4306 12:45:34.356843
4307 12:45:34.357056
4308 12:45:34.359539 TX Vref Scan disable
4309 12:45:34.363215 == TX Byte 0 ==
4310 12:45:34.366582 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4311 12:45:34.369463 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4312 12:45:34.372806 == TX Byte 1 ==
4313 12:45:34.376564 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4314 12:45:34.379297 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4315 12:45:34.379587
4316 12:45:34.379813 [DATLAT]
4317 12:45:34.382782 Freq=600, CH0 RK1
4318 12:45:34.383073
4319 12:45:34.386286 DATLAT Default: 0x9
4320 12:45:34.386577 0, 0xFFFF, sum = 0
4321 12:45:34.389509 1, 0xFFFF, sum = 0
4322 12:45:34.389847 2, 0xFFFF, sum = 0
4323 12:45:34.392485 3, 0xFFFF, sum = 0
4324 12:45:34.392802 4, 0xFFFF, sum = 0
4325 12:45:34.396507 5, 0xFFFF, sum = 0
4326 12:45:34.396923 6, 0xFFFF, sum = 0
4327 12:45:34.399259 7, 0xFFFF, sum = 0
4328 12:45:34.399637 8, 0x0, sum = 1
4329 12:45:34.402602 9, 0x0, sum = 2
4330 12:45:34.402683 10, 0x0, sum = 3
4331 12:45:34.405850 11, 0x0, sum = 4
4332 12:45:34.405943 best_step = 9
4333 12:45:34.406010
4334 12:45:34.406073 ==
4335 12:45:34.408827 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 12:45:34.412232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 12:45:34.412326 ==
4338 12:45:34.415470 RX Vref Scan: 0
4339 12:45:34.415561
4340 12:45:34.418614 RX Vref 0 -> 0, step: 1
4341 12:45:34.418713
4342 12:45:34.418790 RX Delay -195 -> 252, step: 8
4343 12:45:34.426687 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4344 12:45:34.429968 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4345 12:45:34.433265 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4346 12:45:34.437050 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4347 12:45:34.443693 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4348 12:45:34.447011 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4349 12:45:34.450270 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4350 12:45:34.453552 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4351 12:45:34.459912 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4352 12:45:34.463804 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4353 12:45:34.466576 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4354 12:45:34.469993 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4355 12:45:34.476937 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4356 12:45:34.480101 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4357 12:45:34.483102 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4358 12:45:34.487101 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4359 12:45:34.487604 ==
4360 12:45:34.489748 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 12:45:34.496476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 12:45:34.497133 ==
4363 12:45:34.497500 DQS Delay:
4364 12:45:34.500159 DQS0 = 0, DQS1 = 0
4365 12:45:34.500746 DQM Delay:
4366 12:45:34.501199 DQM0 = 41, DQM1 = 36
4367 12:45:34.503602 DQ Delay:
4368 12:45:34.506974 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4369 12:45:34.509935 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4370 12:45:34.513102 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4371 12:45:34.516040 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =44
4372 12:45:34.516492
4373 12:45:34.516885
4374 12:45:34.522596 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a0d, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
4375 12:45:34.525865 CH0 RK1: MR19=808, MR18=5A0D
4376 12:45:34.532561 CH0_RK1: MR19=0x808, MR18=0x5A0D, DQSOSC=392, MR23=63, INC=170, DEC=113
4377 12:45:34.535925 [RxdqsGatingPostProcess] freq 600
4378 12:45:34.542713 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4379 12:45:34.543174 Pre-setting of DQS Precalculation
4380 12:45:34.549295 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4381 12:45:34.549716 ==
4382 12:45:34.552426 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 12:45:34.555658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 12:45:34.556080 ==
4385 12:45:34.562607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 12:45:34.569031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4387 12:45:34.571933 [CA 0] Center 35 (5~66) winsize 62
4388 12:45:34.575359 [CA 1] Center 35 (5~66) winsize 62
4389 12:45:34.578514 [CA 2] Center 34 (4~64) winsize 61
4390 12:45:34.582232 [CA 3] Center 33 (3~64) winsize 62
4391 12:45:34.585271 [CA 4] Center 34 (4~65) winsize 62
4392 12:45:34.588968 [CA 5] Center 33 (3~64) winsize 62
4393 12:45:34.589436
4394 12:45:34.592033 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4395 12:45:34.592481
4396 12:45:34.595303 [CATrainingPosCal] consider 1 rank data
4397 12:45:34.598534 u2DelayCellTimex100 = 270/100 ps
4398 12:45:34.601732 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 12:45:34.604955 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 12:45:34.608232 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4401 12:45:34.611856 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 12:45:34.615475 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 12:45:34.621767 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 12:45:34.622231
4405 12:45:34.624853 CA PerBit enable=1, Macro0, CA PI delay=33
4406 12:45:34.625235
4407 12:45:34.628143 [CBTSetCACLKResult] CA Dly = 33
4408 12:45:34.628690 CS Dly: 5 (0~36)
4409 12:45:34.629019 ==
4410 12:45:34.631263 Dram Type= 6, Freq= 0, CH_1, rank 1
4411 12:45:34.634742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 12:45:34.637885 ==
4413 12:45:34.641199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 12:45:34.647309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4415 12:45:34.651283 [CA 0] Center 35 (5~66) winsize 62
4416 12:45:34.654303 [CA 1] Center 36 (6~66) winsize 61
4417 12:45:34.657262 [CA 2] Center 34 (4~65) winsize 62
4418 12:45:34.661223 [CA 3] Center 33 (3~64) winsize 62
4419 12:45:34.664088 [CA 4] Center 34 (3~65) winsize 63
4420 12:45:34.667352 [CA 5] Center 33 (3~64) winsize 62
4421 12:45:34.667435
4422 12:45:34.670729 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4423 12:45:34.670811
4424 12:45:34.673934 [CATrainingPosCal] consider 2 rank data
4425 12:45:34.677333 u2DelayCellTimex100 = 270/100 ps
4426 12:45:34.680866 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 12:45:34.683611 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4428 12:45:34.690630 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4429 12:45:34.693828 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 12:45:34.697033 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 12:45:34.700264 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 12:45:34.700346
4433 12:45:34.703844 CA PerBit enable=1, Macro0, CA PI delay=33
4434 12:45:34.703926
4435 12:45:34.706790 [CBTSetCACLKResult] CA Dly = 33
4436 12:45:34.706872 CS Dly: 6 (0~38)
4437 12:45:34.706936
4438 12:45:34.713346 ----->DramcWriteLeveling(PI) begin...
4439 12:45:34.713429 ==
4440 12:45:34.716699 Dram Type= 6, Freq= 0, CH_1, rank 0
4441 12:45:34.720171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 12:45:34.720253 ==
4443 12:45:34.723329 Write leveling (Byte 0): 29 => 29
4444 12:45:34.727005 Write leveling (Byte 1): 31 => 31
4445 12:45:34.730084 DramcWriteLeveling(PI) end<-----
4446 12:45:34.730165
4447 12:45:34.730229 ==
4448 12:45:34.733442 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 12:45:34.736457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 12:45:34.736563 ==
4451 12:45:34.740102 [Gating] SW mode calibration
4452 12:45:34.746558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4453 12:45:34.753124 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4454 12:45:34.756545 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 12:45:34.760192 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 12:45:34.766519 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4457 12:45:34.769663 0 9 12 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 0)
4458 12:45:34.773094 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4459 12:45:34.779313 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 12:45:34.782680 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 12:45:34.786036 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 12:45:34.793171 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 12:45:34.795851 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 12:45:34.799370 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 12:45:34.805864 0 10 12 | B1->B0 | 2a2a 3b3b | 1 0 | (0 0) (0 0)
4466 12:45:34.809380 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4467 12:45:34.812737 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 12:45:34.819118 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 12:45:34.822775 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 12:45:34.826084 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 12:45:34.832478 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 12:45:34.835924 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 12:45:34.839093 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 12:45:34.845436 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4475 12:45:34.849015 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 12:45:34.852076 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:45:34.859206 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:45:34.862337 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:45:34.865489 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:45:34.872725 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 12:45:34.875212 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:45:34.878365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 12:45:34.885051 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:45:34.889005 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:45:34.891881 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 12:45:34.898139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:45:34.901695 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:45:34.905221 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:45:34.911862 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4490 12:45:34.915045 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:45:34.918581 Total UI for P1: 0, mck2ui 16
4492 12:45:34.921569 best dqsien dly found for B0: ( 0, 13, 12)
4493 12:45:34.925159 Total UI for P1: 0, mck2ui 16
4494 12:45:34.927935 best dqsien dly found for B1: ( 0, 13, 12)
4495 12:45:34.931374 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4496 12:45:34.934551 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4497 12:45:34.934633
4498 12:45:34.938235 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4499 12:45:34.941360 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4500 12:45:34.944448 [Gating] SW calibration Done
4501 12:45:34.944553 ==
4502 12:45:34.948202 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 12:45:34.951264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 12:45:34.951346 ==
4505 12:45:34.954838 RX Vref Scan: 0
4506 12:45:34.954920
4507 12:45:34.958211 RX Vref 0 -> 0, step: 1
4508 12:45:34.958292
4509 12:45:34.961221 RX Delay -230 -> 252, step: 16
4510 12:45:34.964544 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4511 12:45:34.967983 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4512 12:45:34.971265 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4513 12:45:34.974463 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4514 12:45:34.981118 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4515 12:45:34.984257 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4516 12:45:34.987559 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4517 12:45:34.991053 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4518 12:45:34.997459 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4519 12:45:35.000883 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4520 12:45:35.004164 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4521 12:45:35.007169 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4522 12:45:35.013765 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4523 12:45:35.017336 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4524 12:45:35.020777 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4525 12:45:35.023596 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4526 12:45:35.027184 ==
4527 12:45:35.030143 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 12:45:35.033895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 12:45:35.033978 ==
4530 12:45:35.034043 DQS Delay:
4531 12:45:35.037288 DQS0 = 0, DQS1 = 0
4532 12:45:35.037369 DQM Delay:
4533 12:45:35.040772 DQM0 = 43, DQM1 = 36
4534 12:45:35.040854 DQ Delay:
4535 12:45:35.043583 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4536 12:45:35.046901 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4537 12:45:35.050518 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4538 12:45:35.054086 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =49
4539 12:45:35.054170
4540 12:45:35.054234
4541 12:45:35.054295 ==
4542 12:45:35.056686 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 12:45:35.060413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 12:45:35.060495 ==
4545 12:45:35.060596
4546 12:45:35.060656
4547 12:45:35.064368 TX Vref Scan disable
4548 12:45:35.066719 == TX Byte 0 ==
4549 12:45:35.070059 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4550 12:45:35.073196 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4551 12:45:35.077101 == TX Byte 1 ==
4552 12:45:35.080308 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4553 12:45:35.083221 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4554 12:45:35.083297 ==
4555 12:45:35.086682 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 12:45:35.093156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 12:45:35.093241 ==
4558 12:45:35.093306
4559 12:45:35.093366
4560 12:45:35.093424 TX Vref Scan disable
4561 12:45:35.097139 == TX Byte 0 ==
4562 12:45:35.100683 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4563 12:45:35.107356 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4564 12:45:35.107438 == TX Byte 1 ==
4565 12:45:35.110667 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4566 12:45:35.117466 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4567 12:45:35.117555
4568 12:45:35.117635 [DATLAT]
4569 12:45:35.117721 Freq=600, CH1 RK0
4570 12:45:35.117784
4571 12:45:35.120772 DATLAT Default: 0x9
4572 12:45:35.120854 0, 0xFFFF, sum = 0
4573 12:45:35.124010 1, 0xFFFF, sum = 0
4574 12:45:35.127366 2, 0xFFFF, sum = 0
4575 12:45:35.127449 3, 0xFFFF, sum = 0
4576 12:45:35.130555 4, 0xFFFF, sum = 0
4577 12:45:35.130637 5, 0xFFFF, sum = 0
4578 12:45:35.133450 6, 0xFFFF, sum = 0
4579 12:45:35.133533 7, 0xFFFF, sum = 0
4580 12:45:35.136469 8, 0x0, sum = 1
4581 12:45:35.136578 9, 0x0, sum = 2
4582 12:45:35.139921 10, 0x0, sum = 3
4583 12:45:35.140008 11, 0x0, sum = 4
4584 12:45:35.140075 best_step = 9
4585 12:45:35.140135
4586 12:45:35.143528 ==
4587 12:45:35.146528 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 12:45:35.149895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 12:45:35.149977 ==
4590 12:45:35.150042 RX Vref Scan: 1
4591 12:45:35.150103
4592 12:45:35.153090 RX Vref 0 -> 0, step: 1
4593 12:45:35.153171
4594 12:45:35.156626 RX Delay -179 -> 252, step: 8
4595 12:45:35.156707
4596 12:45:35.159498 Set Vref, RX VrefLevel [Byte0]: 46
4597 12:45:35.162620 [Byte1]: 52
4598 12:45:35.166084
4599 12:45:35.166166 Final RX Vref Byte 0 = 46 to rank0
4600 12:45:35.169438 Final RX Vref Byte 1 = 52 to rank0
4601 12:45:35.172832 Final RX Vref Byte 0 = 46 to rank1
4602 12:45:35.176186 Final RX Vref Byte 1 = 52 to rank1==
4603 12:45:35.179461 Dram Type= 6, Freq= 0, CH_1, rank 0
4604 12:45:35.185939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 12:45:35.186026 ==
4606 12:45:35.186092 DQS Delay:
4607 12:45:35.186153 DQS0 = 0, DQS1 = 0
4608 12:45:35.190249 DQM Delay:
4609 12:45:35.190331 DQM0 = 44, DQM1 = 34
4610 12:45:35.192802 DQ Delay:
4611 12:45:35.195810 DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =40
4612 12:45:35.199023 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =36
4613 12:45:35.202515 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4614 12:45:35.205732 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4615 12:45:35.205814
4616 12:45:35.205879
4617 12:45:35.212463 [DQSOSCAuto] RK0, (LSB)MR18= 0x492e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4618 12:45:35.215967 CH1 RK0: MR19=808, MR18=492E
4619 12:45:35.222170 CH1_RK0: MR19=0x808, MR18=0x492E, DQSOSC=396, MR23=63, INC=167, DEC=111
4620 12:45:35.222253
4621 12:45:35.225818 ----->DramcWriteLeveling(PI) begin...
4622 12:45:35.225901 ==
4623 12:45:35.228810 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 12:45:35.231939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 12:45:35.232046 ==
4626 12:45:35.235746 Write leveling (Byte 0): 31 => 31
4627 12:45:35.238818 Write leveling (Byte 1): 29 => 29
4628 12:45:35.241710 DramcWriteLeveling(PI) end<-----
4629 12:45:35.241791
4630 12:45:35.241856 ==
4631 12:45:35.245035 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 12:45:35.251662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 12:45:35.251750 ==
4634 12:45:35.251817 [Gating] SW mode calibration
4635 12:45:35.261836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4636 12:45:35.265028 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4637 12:45:35.268437 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4638 12:45:35.274975 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4639 12:45:35.278288 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 12:45:35.281267 0 9 12 | B1->B0 | 3131 3333 | 1 1 | (1 1) (1 0)
4641 12:45:35.288142 0 9 16 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4642 12:45:35.291419 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 12:45:35.294455 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 12:45:35.301327 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 12:45:35.304933 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 12:45:35.308533 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 12:45:35.314480 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 12:45:35.317600 0 10 12 | B1->B0 | 3535 2828 | 0 0 | (0 0) (1 1)
4649 12:45:35.321046 0 10 16 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
4650 12:45:35.327766 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 12:45:35.331145 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 12:45:35.334548 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 12:45:35.341138 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 12:45:35.344629 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 12:45:35.347927 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 12:45:35.353893 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4657 12:45:35.357409 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 12:45:35.360429 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 12:45:35.366974 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:45:35.370416 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 12:45:35.374546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 12:45:35.380382 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 12:45:35.383919 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 12:45:35.386970 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:45:35.393708 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 12:45:35.396991 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 12:45:35.400287 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 12:45:35.406959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 12:45:35.409892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 12:45:35.413372 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 12:45:35.420078 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:45:35.423283 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:45:35.426549 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 12:45:35.429685 Total UI for P1: 0, mck2ui 16
4675 12:45:35.432994 best dqsien dly found for B0: ( 0, 13, 14)
4676 12:45:35.436227 Total UI for P1: 0, mck2ui 16
4677 12:45:35.439699 best dqsien dly found for B1: ( 0, 13, 14)
4678 12:45:35.443133 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4679 12:45:35.449840 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4680 12:45:35.449948
4681 12:45:35.453073 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4682 12:45:35.456176 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4683 12:45:35.459403 [Gating] SW calibration Done
4684 12:45:35.459499 ==
4685 12:45:35.462461 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 12:45:35.466027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 12:45:35.466102 ==
4688 12:45:35.469324 RX Vref Scan: 0
4689 12:45:35.469391
4690 12:45:35.469451 RX Vref 0 -> 0, step: 1
4691 12:45:35.469512
4692 12:45:35.472463 RX Delay -230 -> 252, step: 16
4693 12:45:35.476084 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4694 12:45:35.482866 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4695 12:45:35.486139 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4696 12:45:35.489205 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4697 12:45:35.492724 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4698 12:45:35.499149 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4699 12:45:35.502735 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4700 12:45:35.505656 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4701 12:45:35.508749 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4702 12:45:35.512580 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4703 12:45:35.518877 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4704 12:45:35.521902 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4705 12:45:35.526212 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4706 12:45:35.528493 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4707 12:45:35.535124 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4708 12:45:35.538694 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4709 12:45:35.538776 ==
4710 12:45:35.541657 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 12:45:35.545623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 12:45:35.545701 ==
4713 12:45:35.548754 DQS Delay:
4714 12:45:35.548823 DQS0 = 0, DQS1 = 0
4715 12:45:35.552102 DQM Delay:
4716 12:45:35.552200 DQM0 = 44, DQM1 = 36
4717 12:45:35.552290 DQ Delay:
4718 12:45:35.555191 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4719 12:45:35.559009 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4720 12:45:35.561910 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4721 12:45:35.565369 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4722 12:45:35.565445
4723 12:45:35.565514
4724 12:45:35.568591 ==
4725 12:45:35.568667 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 12:45:35.575216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 12:45:35.575318 ==
4728 12:45:35.575409
4729 12:45:35.575497
4730 12:45:35.578182 TX Vref Scan disable
4731 12:45:35.578252 == TX Byte 0 ==
4732 12:45:35.584704 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4733 12:45:35.587954 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4734 12:45:35.588051 == TX Byte 1 ==
4735 12:45:35.594740 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4736 12:45:35.598248 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4737 12:45:35.598352 ==
4738 12:45:35.601064 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 12:45:35.604631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 12:45:35.604715 ==
4741 12:45:35.604805
4742 12:45:35.604896
4743 12:45:35.608010 TX Vref Scan disable
4744 12:45:35.611156 == TX Byte 0 ==
4745 12:45:35.614881 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4746 12:45:35.617652 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4747 12:45:35.621397 == TX Byte 1 ==
4748 12:45:35.624925 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4749 12:45:35.627867 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4750 12:45:35.627948
4751 12:45:35.631323 [DATLAT]
4752 12:45:35.631422 Freq=600, CH1 RK1
4753 12:45:35.631511
4754 12:45:35.634270 DATLAT Default: 0x9
4755 12:45:35.634340 0, 0xFFFF, sum = 0
4756 12:45:35.637567 1, 0xFFFF, sum = 0
4757 12:45:35.637644 2, 0xFFFF, sum = 0
4758 12:45:35.641168 3, 0xFFFF, sum = 0
4759 12:45:35.641254 4, 0xFFFF, sum = 0
4760 12:45:35.644708 5, 0xFFFF, sum = 0
4761 12:45:35.644807 6, 0xFFFF, sum = 0
4762 12:45:35.647399 7, 0xFFFF, sum = 0
4763 12:45:35.647477 8, 0x0, sum = 1
4764 12:45:35.650729 9, 0x0, sum = 2
4765 12:45:35.650808 10, 0x0, sum = 3
4766 12:45:35.654038 11, 0x0, sum = 4
4767 12:45:35.654136 best_step = 9
4768 12:45:35.654228
4769 12:45:35.654315 ==
4770 12:45:35.657246 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 12:45:35.663950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 12:45:35.664053 ==
4773 12:45:35.664143 RX Vref Scan: 0
4774 12:45:35.664232
4775 12:45:35.667393 RX Vref 0 -> 0, step: 1
4776 12:45:35.667495
4777 12:45:35.670761 RX Delay -195 -> 252, step: 8
4778 12:45:35.673899 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4779 12:45:35.680350 iDelay=205, Bit 1, Center 36 (-115 ~ 188) 304
4780 12:45:35.684070 iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296
4781 12:45:35.687156 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4782 12:45:35.690365 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4783 12:45:35.696759 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4784 12:45:35.700400 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4785 12:45:35.703252 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4786 12:45:35.707015 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4787 12:45:35.710014 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4788 12:45:35.716778 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4789 12:45:35.719850 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4790 12:45:35.723504 iDelay=205, Bit 12, Center 44 (-115 ~ 204) 320
4791 12:45:35.726817 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4792 12:45:35.734006 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4793 12:45:35.736808 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4794 12:45:35.736922 ==
4795 12:45:35.739813 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 12:45:35.743380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 12:45:35.743484 ==
4798 12:45:35.746614 DQS Delay:
4799 12:45:35.746710 DQS0 = 0, DQS1 = 0
4800 12:45:35.749973 DQM Delay:
4801 12:45:35.750072 DQM0 = 43, DQM1 = 33
4802 12:45:35.750161 DQ Delay:
4803 12:45:35.753258 DQ0 =44, DQ1 =36, DQ2 =32, DQ3 =40
4804 12:45:35.756272 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =40
4805 12:45:35.759598 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4806 12:45:35.762987 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4807 12:45:35.763100
4808 12:45:35.763181
4809 12:45:35.772711 [DQSOSCAuto] RK1, (LSB)MR18= 0x291e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4810 12:45:35.775965 CH1 RK1: MR19=808, MR18=291E
4811 12:45:35.783357 CH1_RK1: MR19=0x808, MR18=0x291E, DQSOSC=402, MR23=63, INC=162, DEC=108
4812 12:45:35.783468 [RxdqsGatingPostProcess] freq 600
4813 12:45:35.789063 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4814 12:45:35.792326 Pre-setting of DQS Precalculation
4815 12:45:35.795719 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4816 12:45:35.805701 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4817 12:45:35.812133 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4818 12:45:35.812254
4819 12:45:35.812360
4820 12:45:35.815535 [Calibration Summary] 1200 Mbps
4821 12:45:35.815651 CH 0, Rank 0
4822 12:45:35.818651 SW Impedance : PASS
4823 12:45:35.822043 DUTY Scan : NO K
4824 12:45:35.822131 ZQ Calibration : PASS
4825 12:45:35.825595 Jitter Meter : NO K
4826 12:45:35.825710 CBT Training : PASS
4827 12:45:35.829096 Write leveling : PASS
4828 12:45:35.832094 RX DQS gating : PASS
4829 12:45:35.832175 RX DQ/DQS(RDDQC) : PASS
4830 12:45:35.835482 TX DQ/DQS : PASS
4831 12:45:35.839110 RX DATLAT : PASS
4832 12:45:35.839191 RX DQ/DQS(Engine): PASS
4833 12:45:35.842230 TX OE : NO K
4834 12:45:35.842313 All Pass.
4835 12:45:35.842377
4836 12:45:35.845225 CH 0, Rank 1
4837 12:45:35.845307 SW Impedance : PASS
4838 12:45:35.848434 DUTY Scan : NO K
4839 12:45:35.852349 ZQ Calibration : PASS
4840 12:45:35.852430 Jitter Meter : NO K
4841 12:45:35.855046 CBT Training : PASS
4842 12:45:35.858868 Write leveling : PASS
4843 12:45:35.858949 RX DQS gating : PASS
4844 12:45:35.862121 RX DQ/DQS(RDDQC) : PASS
4845 12:45:35.865165 TX DQ/DQS : PASS
4846 12:45:35.865246 RX DATLAT : PASS
4847 12:45:35.868281 RX DQ/DQS(Engine): PASS
4848 12:45:35.871670 TX OE : NO K
4849 12:45:35.871751 All Pass.
4850 12:45:35.871816
4851 12:45:35.871876 CH 1, Rank 0
4852 12:45:35.875571 SW Impedance : PASS
4853 12:45:35.878845 DUTY Scan : NO K
4854 12:45:35.878941 ZQ Calibration : PASS
4855 12:45:35.881724 Jitter Meter : NO K
4856 12:45:35.885065 CBT Training : PASS
4857 12:45:35.885147 Write leveling : PASS
4858 12:45:35.888271 RX DQS gating : PASS
4859 12:45:35.888352 RX DQ/DQS(RDDQC) : PASS
4860 12:45:35.891880 TX DQ/DQS : PASS
4861 12:45:35.895004 RX DATLAT : PASS
4862 12:45:35.895086 RX DQ/DQS(Engine): PASS
4863 12:45:35.898173 TX OE : NO K
4864 12:45:35.898256 All Pass.
4865 12:45:35.898321
4866 12:45:35.901745 CH 1, Rank 1
4867 12:45:35.901826 SW Impedance : PASS
4868 12:45:35.904917 DUTY Scan : NO K
4869 12:45:35.908191 ZQ Calibration : PASS
4870 12:45:35.908272 Jitter Meter : NO K
4871 12:45:35.911477 CBT Training : PASS
4872 12:45:35.915201 Write leveling : PASS
4873 12:45:35.915282 RX DQS gating : PASS
4874 12:45:35.918279 RX DQ/DQS(RDDQC) : PASS
4875 12:45:35.921282 TX DQ/DQS : PASS
4876 12:45:35.921377 RX DATLAT : PASS
4877 12:45:35.925049 RX DQ/DQS(Engine): PASS
4878 12:45:35.928052 TX OE : NO K
4879 12:45:35.928134 All Pass.
4880 12:45:35.928198
4881 12:45:35.930985 DramC Write-DBI off
4882 12:45:35.931066 PER_BANK_REFRESH: Hybrid Mode
4883 12:45:35.934394 TX_TRACKING: ON
4884 12:45:35.940945 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4885 12:45:35.947476 [FAST_K] Save calibration result to emmc
4886 12:45:35.951050 dramc_set_vcore_voltage set vcore to 662500
4887 12:45:35.951132 Read voltage for 933, 3
4888 12:45:35.954008 Vio18 = 0
4889 12:45:35.954124 Vcore = 662500
4890 12:45:35.954217 Vdram = 0
4891 12:45:35.957163 Vddq = 0
4892 12:45:35.957241 Vmddr = 0
4893 12:45:35.961410 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4894 12:45:35.967559 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4895 12:45:35.970594 MEM_TYPE=3, freq_sel=17
4896 12:45:35.974438 sv_algorithm_assistance_LP4_1600
4897 12:45:35.976893 ============ PULL DRAM RESETB DOWN ============
4898 12:45:35.980597 ========== PULL DRAM RESETB DOWN end =========
4899 12:45:35.987170 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4900 12:45:35.990578 ===================================
4901 12:45:35.990695 LPDDR4 DRAM CONFIGURATION
4902 12:45:35.993774 ===================================
4903 12:45:35.997164 EX_ROW_EN[0] = 0x0
4904 12:45:36.000120 EX_ROW_EN[1] = 0x0
4905 12:45:36.000201 LP4Y_EN = 0x0
4906 12:45:36.003506 WORK_FSP = 0x0
4907 12:45:36.003587 WL = 0x3
4908 12:45:36.006885 RL = 0x3
4909 12:45:36.006967 BL = 0x2
4910 12:45:36.010225 RPST = 0x0
4911 12:45:36.010306 RD_PRE = 0x0
4912 12:45:36.013382 WR_PRE = 0x1
4913 12:45:36.013464 WR_PST = 0x0
4914 12:45:36.016550 DBI_WR = 0x0
4915 12:45:36.016645 DBI_RD = 0x0
4916 12:45:36.020244 OTF = 0x1
4917 12:45:36.023582 ===================================
4918 12:45:36.026455 ===================================
4919 12:45:36.026537 ANA top config
4920 12:45:36.030084 ===================================
4921 12:45:36.034099 DLL_ASYNC_EN = 0
4922 12:45:36.036602 ALL_SLAVE_EN = 1
4923 12:45:36.039701 NEW_RANK_MODE = 1
4924 12:45:36.039784 DLL_IDLE_MODE = 1
4925 12:45:36.043028 LP45_APHY_COMB_EN = 1
4926 12:45:36.046538 TX_ODT_DIS = 1
4927 12:45:36.049578 NEW_8X_MODE = 1
4928 12:45:36.052787 ===================================
4929 12:45:36.056652 ===================================
4930 12:45:36.059303 data_rate = 1866
4931 12:45:36.059385 CKR = 1
4932 12:45:36.063928 DQ_P2S_RATIO = 8
4933 12:45:36.066165 ===================================
4934 12:45:36.069094 CA_P2S_RATIO = 8
4935 12:45:36.072885 DQ_CA_OPEN = 0
4936 12:45:36.076282 DQ_SEMI_OPEN = 0
4937 12:45:36.079327 CA_SEMI_OPEN = 0
4938 12:45:36.079409 CA_FULL_RATE = 0
4939 12:45:36.082898 DQ_CKDIV4_EN = 1
4940 12:45:36.086232 CA_CKDIV4_EN = 1
4941 12:45:36.089243 CA_PREDIV_EN = 0
4942 12:45:36.092527 PH8_DLY = 0
4943 12:45:36.096101 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4944 12:45:36.096183 DQ_AAMCK_DIV = 4
4945 12:45:36.099253 CA_AAMCK_DIV = 4
4946 12:45:36.102605 CA_ADMCK_DIV = 4
4947 12:45:36.105704 DQ_TRACK_CA_EN = 0
4948 12:45:36.109114 CA_PICK = 933
4949 12:45:36.112833 CA_MCKIO = 933
4950 12:45:36.115712 MCKIO_SEMI = 0
4951 12:45:36.118997 PLL_FREQ = 3732
4952 12:45:36.119078 DQ_UI_PI_RATIO = 32
4953 12:45:36.122192 CA_UI_PI_RATIO = 0
4954 12:45:36.125659 ===================================
4955 12:45:36.129128 ===================================
4956 12:45:36.132085 memory_type:LPDDR4
4957 12:45:36.135396 GP_NUM : 10
4958 12:45:36.135477 SRAM_EN : 1
4959 12:45:36.138961 MD32_EN : 0
4960 12:45:36.142207 ===================================
4961 12:45:36.142289 [ANA_INIT] >>>>>>>>>>>>>>
4962 12:45:36.145978 <<<<<< [CONFIGURE PHASE]: ANA_TX
4963 12:45:36.148419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4964 12:45:36.152321 ===================================
4965 12:45:36.155535 data_rate = 1866,PCW = 0X8f00
4966 12:45:36.158414 ===================================
4967 12:45:36.161997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4968 12:45:36.168983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4969 12:45:36.175303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4970 12:45:36.178446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4971 12:45:36.181988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4972 12:45:36.184729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4973 12:45:36.188028 [ANA_INIT] flow start
4974 12:45:36.188179 [ANA_INIT] PLL >>>>>>>>
4975 12:45:36.191369 [ANA_INIT] PLL <<<<<<<<
4976 12:45:36.195183 [ANA_INIT] MIDPI >>>>>>>>
4977 12:45:36.198421 [ANA_INIT] MIDPI <<<<<<<<
4978 12:45:36.198573 [ANA_INIT] DLL >>>>>>>>
4979 12:45:36.201294 [ANA_INIT] flow end
4980 12:45:36.204619 ============ LP4 DIFF to SE enter ============
4981 12:45:36.207815 ============ LP4 DIFF to SE exit ============
4982 12:45:36.211606 [ANA_INIT] <<<<<<<<<<<<<
4983 12:45:36.214760 [Flow] Enable top DCM control >>>>>
4984 12:45:36.217863 [Flow] Enable top DCM control <<<<<
4985 12:45:36.221118 Enable DLL master slave shuffle
4986 12:45:36.227561 ==============================================================
4987 12:45:36.227654 Gating Mode config
4988 12:45:36.235024 ==============================================================
4989 12:45:36.235221 Config description:
4990 12:45:36.244485 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4991 12:45:36.250804 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4992 12:45:36.257726 SELPH_MODE 0: By rank 1: By Phase
4993 12:45:36.260829 ==============================================================
4994 12:45:36.263928 GAT_TRACK_EN = 1
4995 12:45:36.267509 RX_GATING_MODE = 2
4996 12:45:36.270713 RX_GATING_TRACK_MODE = 2
4997 12:45:36.274083 SELPH_MODE = 1
4998 12:45:36.277110 PICG_EARLY_EN = 1
4999 12:45:36.280209 VALID_LAT_VALUE = 1
5000 12:45:36.287104 ==============================================================
5001 12:45:36.290264 Enter into Gating configuration >>>>
5002 12:45:36.293444 Exit from Gating configuration <<<<
5003 12:45:36.297543 Enter into DVFS_PRE_config >>>>>
5004 12:45:36.307258 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5005 12:45:36.311079 Exit from DVFS_PRE_config <<<<<
5006 12:45:36.314165 Enter into PICG configuration >>>>
5007 12:45:36.317326 Exit from PICG configuration <<<<
5008 12:45:36.320565 [RX_INPUT] configuration >>>>>
5009 12:45:36.321071 [RX_INPUT] configuration <<<<<
5010 12:45:36.327066 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5011 12:45:36.333777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5012 12:45:36.340557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 12:45:36.343507 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 12:45:36.350789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 12:45:36.356713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 12:45:36.360054 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5017 12:45:36.363652 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5018 12:45:36.369842 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5019 12:45:36.373190 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5020 12:45:36.376803 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5021 12:45:36.383643 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5022 12:45:36.386905 ===================================
5023 12:45:36.387369 LPDDR4 DRAM CONFIGURATION
5024 12:45:36.390678 ===================================
5025 12:45:36.393136 EX_ROW_EN[0] = 0x0
5026 12:45:36.396410 EX_ROW_EN[1] = 0x0
5027 12:45:36.396938 LP4Y_EN = 0x0
5028 12:45:36.400043 WORK_FSP = 0x0
5029 12:45:36.400676 WL = 0x3
5030 12:45:36.403457 RL = 0x3
5031 12:45:36.403920 BL = 0x2
5032 12:45:36.406582 RPST = 0x0
5033 12:45:36.407044 RD_PRE = 0x0
5034 12:45:36.409632 WR_PRE = 0x1
5035 12:45:36.410094 WR_PST = 0x0
5036 12:45:36.413066 DBI_WR = 0x0
5037 12:45:36.413530 DBI_RD = 0x0
5038 12:45:36.416167 OTF = 0x1
5039 12:45:36.419944 ===================================
5040 12:45:36.423083 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5041 12:45:36.426371 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5042 12:45:36.433083 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5043 12:45:36.436765 ===================================
5044 12:45:36.437334 LPDDR4 DRAM CONFIGURATION
5045 12:45:36.439372 ===================================
5046 12:45:36.442726 EX_ROW_EN[0] = 0x10
5047 12:45:36.445807 EX_ROW_EN[1] = 0x0
5048 12:45:36.446268 LP4Y_EN = 0x0
5049 12:45:36.449259 WORK_FSP = 0x0
5050 12:45:36.449721 WL = 0x3
5051 12:45:36.452661 RL = 0x3
5052 12:45:36.453214 BL = 0x2
5053 12:45:36.456280 RPST = 0x0
5054 12:45:36.456939 RD_PRE = 0x0
5055 12:45:36.458882 WR_PRE = 0x1
5056 12:45:36.459511 WR_PST = 0x0
5057 12:45:36.462186 DBI_WR = 0x0
5058 12:45:36.462798 DBI_RD = 0x0
5059 12:45:36.465961 OTF = 0x1
5060 12:45:36.468874 ===================================
5061 12:45:36.475706 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5062 12:45:36.478926 nWR fixed to 30
5063 12:45:36.482074 [ModeRegInit_LP4] CH0 RK0
5064 12:45:36.482493 [ModeRegInit_LP4] CH0 RK1
5065 12:45:36.486109 [ModeRegInit_LP4] CH1 RK0
5066 12:45:36.489114 [ModeRegInit_LP4] CH1 RK1
5067 12:45:36.489641 match AC timing 9
5068 12:45:36.495863 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5069 12:45:36.498685 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5070 12:45:36.502455 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5071 12:45:36.508968 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5072 12:45:36.512510 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5073 12:45:36.513082 ==
5074 12:45:36.515138 Dram Type= 6, Freq= 0, CH_0, rank 0
5075 12:45:36.518493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 12:45:36.518916 ==
5077 12:45:36.525195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 12:45:36.532036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5079 12:45:36.534944 [CA 0] Center 37 (7~68) winsize 62
5080 12:45:36.538221 [CA 1] Center 37 (7~68) winsize 62
5081 12:45:36.541633 [CA 2] Center 34 (4~65) winsize 62
5082 12:45:36.544731 [CA 3] Center 34 (4~65) winsize 62
5083 12:45:36.548226 [CA 4] Center 33 (3~64) winsize 62
5084 12:45:36.551818 [CA 5] Center 33 (3~63) winsize 61
5085 12:45:36.552466
5086 12:45:36.554430 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5087 12:45:36.554894
5088 12:45:36.558668 [CATrainingPosCal] consider 1 rank data
5089 12:45:36.561084 u2DelayCellTimex100 = 270/100 ps
5090 12:45:36.564883 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5091 12:45:36.568440 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5092 12:45:36.571481 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5093 12:45:36.574298 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5094 12:45:36.580854 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5095 12:45:36.584967 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5096 12:45:36.585620
5097 12:45:36.587986 CA PerBit enable=1, Macro0, CA PI delay=33
5098 12:45:36.588635
5099 12:45:36.590948 [CBTSetCACLKResult] CA Dly = 33
5100 12:45:36.591431 CS Dly: 7 (0~38)
5101 12:45:36.591804 ==
5102 12:45:36.594065 Dram Type= 6, Freq= 0, CH_0, rank 1
5103 12:45:36.601489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 12:45:36.602034 ==
5105 12:45:36.603953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 12:45:36.610665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5107 12:45:36.614303 [CA 0] Center 37 (7~68) winsize 62
5108 12:45:36.617253 [CA 1] Center 37 (7~68) winsize 62
5109 12:45:36.620339 [CA 2] Center 34 (4~65) winsize 62
5110 12:45:36.624644 [CA 3] Center 35 (5~65) winsize 61
5111 12:45:36.627658 [CA 4] Center 33 (3~64) winsize 62
5112 12:45:36.630374 [CA 5] Center 33 (3~63) winsize 61
5113 12:45:36.630845
5114 12:45:36.633634 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5115 12:45:36.634104
5116 12:45:36.637213 [CATrainingPosCal] consider 2 rank data
5117 12:45:36.640140 u2DelayCellTimex100 = 270/100 ps
5118 12:45:36.644369 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5119 12:45:36.646609 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5120 12:45:36.654000 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5121 12:45:36.656760 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5122 12:45:36.660118 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5123 12:45:36.663725 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5124 12:45:36.664292
5125 12:45:36.666602 CA PerBit enable=1, Macro0, CA PI delay=33
5126 12:45:36.667153
5127 12:45:36.670087 [CBTSetCACLKResult] CA Dly = 33
5128 12:45:36.670657 CS Dly: 7 (0~39)
5129 12:45:36.673254
5130 12:45:36.676657 ----->DramcWriteLeveling(PI) begin...
5131 12:45:36.677223 ==
5132 12:45:36.680058 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 12:45:36.683177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5134 12:45:36.683745 ==
5135 12:45:36.686221 Write leveling (Byte 0): 33 => 33
5136 12:45:36.690719 Write leveling (Byte 1): 29 => 29
5137 12:45:36.693060 DramcWriteLeveling(PI) end<-----
5138 12:45:36.693528
5139 12:45:36.694123 ==
5140 12:45:36.696428 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 12:45:36.700115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 12:45:36.700794 ==
5143 12:45:36.702882 [Gating] SW mode calibration
5144 12:45:36.709366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5145 12:45:36.716442 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5146 12:45:36.719513 0 14 0 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
5147 12:45:36.722451 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5148 12:45:36.729527 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 12:45:36.732619 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 12:45:36.736105 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 12:45:36.742316 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 12:45:36.745895 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 12:45:36.748864 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
5154 12:45:36.755950 0 15 0 | B1->B0 | 3030 2828 | 0 0 | (0 0) (0 0)
5155 12:45:36.758936 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 12:45:36.762455 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 12:45:36.769103 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 12:45:36.771884 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 12:45:36.775379 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 12:45:36.781823 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 12:45:36.785565 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5162 12:45:36.788671 1 0 0 | B1->B0 | 3030 4444 | 0 1 | (0 0) (0 0)
5163 12:45:36.795320 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5164 12:45:36.798894 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 12:45:36.802074 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 12:45:36.808494 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 12:45:36.812386 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 12:45:36.814925 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 12:45:36.821546 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5170 12:45:36.824988 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5171 12:45:36.828824 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 12:45:36.834784 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 12:45:36.838296 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 12:45:36.841384 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 12:45:36.848384 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 12:45:36.851265 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 12:45:36.855298 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 12:45:36.861280 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 12:45:36.864661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:45:36.868028 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 12:45:36.874709 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:45:36.877458 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:45:36.881302 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:45:36.888136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:45:36.891162 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5186 12:45:36.894009 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5187 12:45:36.900776 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 12:45:36.901205 Total UI for P1: 0, mck2ui 16
5189 12:45:36.907184 best dqsien dly found for B0: ( 1, 2, 30)
5190 12:45:36.907609 Total UI for P1: 0, mck2ui 16
5191 12:45:36.913937 best dqsien dly found for B1: ( 1, 3, 2)
5192 12:45:36.917629 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5193 12:45:36.920806 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5194 12:45:36.921259
5195 12:45:36.923687 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5196 12:45:36.927106 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5197 12:45:36.930472 [Gating] SW calibration Done
5198 12:45:36.930907 ==
5199 12:45:36.933922 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 12:45:36.937332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 12:45:36.937756 ==
5202 12:45:36.940786 RX Vref Scan: 0
5203 12:45:36.941216
5204 12:45:36.941556 RX Vref 0 -> 0, step: 1
5205 12:45:36.942015
5206 12:45:36.944129 RX Delay -80 -> 252, step: 8
5207 12:45:36.947045 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5208 12:45:36.954024 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5209 12:45:36.956957 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5210 12:45:36.960580 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5211 12:45:36.964122 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5212 12:45:36.967015 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5213 12:45:36.970176 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5214 12:45:36.977047 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5215 12:45:36.980035 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5216 12:45:36.983132 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5217 12:45:36.986677 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5218 12:45:36.992971 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5219 12:45:36.996612 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5220 12:45:36.999541 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5221 12:45:37.003248 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5222 12:45:37.006521 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5223 12:45:37.006972 ==
5224 12:45:37.009552 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 12:45:37.016467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 12:45:37.017024 ==
5227 12:45:37.017399 DQS Delay:
5228 12:45:37.019721 DQS0 = 0, DQS1 = 0
5229 12:45:37.020201 DQM Delay:
5230 12:45:37.020759 DQM0 = 97, DQM1 = 87
5231 12:45:37.022656 DQ Delay:
5232 12:45:37.026004 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5233 12:45:37.029341 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =111
5234 12:45:37.032595 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5235 12:45:37.035715 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5236 12:45:37.036154
5237 12:45:37.036546
5238 12:45:37.036900 ==
5239 12:45:37.039927 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 12:45:37.042482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 12:45:37.042910 ==
5242 12:45:37.043471
5243 12:45:37.043874
5244 12:45:37.045949 TX Vref Scan disable
5245 12:45:37.049060 == TX Byte 0 ==
5246 12:45:37.052581 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5247 12:45:37.055573 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5248 12:45:37.058804 == TX Byte 1 ==
5249 12:45:37.061894 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5250 12:45:37.065372 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5251 12:45:37.065794 ==
5252 12:45:37.068584 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 12:45:37.075400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 12:45:37.075933 ==
5255 12:45:37.076307
5256 12:45:37.076748
5257 12:45:37.077066 TX Vref Scan disable
5258 12:45:37.079395 == TX Byte 0 ==
5259 12:45:37.082378 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5260 12:45:37.089127 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5261 12:45:37.089590 == TX Byte 1 ==
5262 12:45:37.092007 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5263 12:45:37.098843 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5264 12:45:37.099369
5265 12:45:37.099789 [DATLAT]
5266 12:45:37.100107 Freq=933, CH0 RK0
5267 12:45:37.100489
5268 12:45:37.101915 DATLAT Default: 0xd
5269 12:45:37.105203 0, 0xFFFF, sum = 0
5270 12:45:37.105678 1, 0xFFFF, sum = 0
5271 12:45:37.108772 2, 0xFFFF, sum = 0
5272 12:45:37.109238 3, 0xFFFF, sum = 0
5273 12:45:37.111763 4, 0xFFFF, sum = 0
5274 12:45:37.112224 5, 0xFFFF, sum = 0
5275 12:45:37.115421 6, 0xFFFF, sum = 0
5276 12:45:37.115892 7, 0xFFFF, sum = 0
5277 12:45:37.118690 8, 0xFFFF, sum = 0
5278 12:45:37.119114 9, 0xFFFF, sum = 0
5279 12:45:37.121908 10, 0x0, sum = 1
5280 12:45:37.122328 11, 0x0, sum = 2
5281 12:45:37.125321 12, 0x0, sum = 3
5282 12:45:37.125758 13, 0x0, sum = 4
5283 12:45:37.128073 best_step = 11
5284 12:45:37.128581
5285 12:45:37.128925 ==
5286 12:45:37.131458 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 12:45:37.134967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 12:45:37.135386 ==
5289 12:45:37.135717 RX Vref Scan: 1
5290 12:45:37.138342
5291 12:45:37.138918 RX Vref 0 -> 0, step: 1
5292 12:45:37.139266
5293 12:45:37.141689 RX Delay -61 -> 252, step: 4
5294 12:45:37.142097
5295 12:45:37.144963 Set Vref, RX VrefLevel [Byte0]: 55
5296 12:45:37.148261 [Byte1]: 57
5297 12:45:37.151693
5298 12:45:37.152117 Final RX Vref Byte 0 = 55 to rank0
5299 12:45:37.155259 Final RX Vref Byte 1 = 57 to rank0
5300 12:45:37.158339 Final RX Vref Byte 0 = 55 to rank1
5301 12:45:37.161632 Final RX Vref Byte 1 = 57 to rank1==
5302 12:45:37.164871 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 12:45:37.171074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 12:45:37.171374 ==
5305 12:45:37.171613 DQS Delay:
5306 12:45:37.174215 DQS0 = 0, DQS1 = 0
5307 12:45:37.174294 DQM Delay:
5308 12:45:37.174357 DQM0 = 97, DQM1 = 87
5309 12:45:37.177408 DQ Delay:
5310 12:45:37.180736 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5311 12:45:37.184046 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5312 12:45:37.187508 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =84
5313 12:45:37.190469 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =94
5314 12:45:37.190566
5315 12:45:37.190654
5316 12:45:37.197454 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5317 12:45:37.200799 CH0 RK0: MR19=505, MR18=260D
5318 12:45:37.207221 CH0_RK0: MR19=0x505, MR18=0x260D, DQSOSC=409, MR23=63, INC=64, DEC=43
5319 12:45:37.207301
5320 12:45:37.210571 ----->DramcWriteLeveling(PI) begin...
5321 12:45:37.210652 ==
5322 12:45:37.213850 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 12:45:37.216903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 12:45:37.216983 ==
5325 12:45:37.220405 Write leveling (Byte 0): 32 => 32
5326 12:45:37.223697 Write leveling (Byte 1): 29 => 29
5327 12:45:37.226712 DramcWriteLeveling(PI) end<-----
5328 12:45:37.226790
5329 12:45:37.226851 ==
5330 12:45:37.230331 Dram Type= 6, Freq= 0, CH_0, rank 1
5331 12:45:37.237482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 12:45:37.237562 ==
5333 12:45:37.237624 [Gating] SW mode calibration
5334 12:45:37.246548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5335 12:45:37.250067 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5336 12:45:37.253417 0 14 0 | B1->B0 | 2c2c 3131 | 1 1 | (1 1) (1 1)
5337 12:45:37.259849 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 12:45:37.263187 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 12:45:37.270028 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 12:45:37.272980 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 12:45:37.276352 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 12:45:37.279806 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5343 12:45:37.286210 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
5344 12:45:37.289903 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5345 12:45:37.292660 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5346 12:45:37.299855 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 12:45:37.302760 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 12:45:37.306131 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 12:45:37.312469 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 12:45:37.315875 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 12:45:37.319158 0 15 28 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)
5352 12:45:37.325698 1 0 0 | B1->B0 | 3e3d 4545 | 1 0 | (0 0) (0 0)
5353 12:45:37.329450 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 12:45:37.332579 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 12:45:37.339438 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 12:45:37.342712 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 12:45:37.345571 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 12:45:37.352663 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 12:45:37.355795 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5360 12:45:37.362283 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5361 12:45:37.365526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 12:45:37.368768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 12:45:37.375447 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 12:45:37.378544 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 12:45:37.382421 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 12:45:37.388347 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 12:45:37.392476 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:45:37.395064 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 12:45:37.401670 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 12:45:37.404733 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 12:45:37.408057 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 12:45:37.414649 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 12:45:37.418248 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:45:37.421375 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:45:37.424464 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5376 12:45:37.431128 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5377 12:45:37.434494 Total UI for P1: 0, mck2ui 16
5378 12:45:37.438023 best dqsien dly found for B0: ( 1, 2, 28)
5379 12:45:37.441553 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 12:45:37.444535 Total UI for P1: 0, mck2ui 16
5381 12:45:37.447766 best dqsien dly found for B1: ( 1, 3, 0)
5382 12:45:37.451065 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5383 12:45:37.454570 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5384 12:45:37.454651
5385 12:45:37.457930 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5386 12:45:37.460979 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5387 12:45:37.464729 [Gating] SW calibration Done
5388 12:45:37.464810 ==
5389 12:45:37.467790 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 12:45:37.474358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 12:45:37.474441 ==
5392 12:45:37.474505 RX Vref Scan: 0
5393 12:45:37.474563
5394 12:45:37.477543 RX Vref 0 -> 0, step: 1
5395 12:45:37.477624
5396 12:45:37.480886 RX Delay -80 -> 252, step: 8
5397 12:45:37.484283 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5398 12:45:37.487270 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5399 12:45:37.491103 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5400 12:45:37.494190 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5401 12:45:37.500841 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5402 12:45:37.504255 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5403 12:45:37.507404 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5404 12:45:37.510466 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5405 12:45:37.514156 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5406 12:45:37.516991 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5407 12:45:37.523621 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5408 12:45:37.527261 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5409 12:45:37.530344 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5410 12:45:37.533593 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5411 12:45:37.536834 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5412 12:45:37.544122 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5413 12:45:37.544231 ==
5414 12:45:37.546566 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 12:45:37.550453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 12:45:37.550543 ==
5417 12:45:37.550626 DQS Delay:
5418 12:45:37.553097 DQS0 = 0, DQS1 = 0
5419 12:45:37.553216 DQM Delay:
5420 12:45:37.556447 DQM0 = 96, DQM1 = 89
5421 12:45:37.556565 DQ Delay:
5422 12:45:37.559821 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5423 12:45:37.563261 DQ4 =95, DQ5 =83, DQ6 =107, DQ7 =107
5424 12:45:37.566803 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5425 12:45:37.569959 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5426 12:45:37.570043
5427 12:45:37.570127
5428 12:45:37.570205 ==
5429 12:45:37.573478 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 12:45:37.576788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 12:45:37.579563 ==
5432 12:45:37.579647
5433 12:45:37.579731
5434 12:45:37.579810 TX Vref Scan disable
5435 12:45:37.583301 == TX Byte 0 ==
5436 12:45:37.586283 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5437 12:45:37.589331 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5438 12:45:37.592699 == TX Byte 1 ==
5439 12:45:37.596298 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 12:45:37.602904 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 12:45:37.602993 ==
5442 12:45:37.606342 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 12:45:37.609815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 12:45:37.609929 ==
5445 12:45:37.610057
5446 12:45:37.610187
5447 12:45:37.612918 TX Vref Scan disable
5448 12:45:37.613030 == TX Byte 0 ==
5449 12:45:37.619521 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5450 12:45:37.622709 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5451 12:45:37.622792 == TX Byte 1 ==
5452 12:45:37.629030 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5453 12:45:37.632915 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5454 12:45:37.632998
5455 12:45:37.633063 [DATLAT]
5456 12:45:37.635835 Freq=933, CH0 RK1
5457 12:45:37.635917
5458 12:45:37.635981 DATLAT Default: 0xb
5459 12:45:37.639268 0, 0xFFFF, sum = 0
5460 12:45:37.639351 1, 0xFFFF, sum = 0
5461 12:45:37.642857 2, 0xFFFF, sum = 0
5462 12:45:37.645818 3, 0xFFFF, sum = 0
5463 12:45:37.645901 4, 0xFFFF, sum = 0
5464 12:45:37.649226 5, 0xFFFF, sum = 0
5465 12:45:37.649310 6, 0xFFFF, sum = 0
5466 12:45:37.652700 7, 0xFFFF, sum = 0
5467 12:45:37.652783 8, 0xFFFF, sum = 0
5468 12:45:37.655575 9, 0xFFFF, sum = 0
5469 12:45:37.655657 10, 0x0, sum = 1
5470 12:45:37.658722 11, 0x0, sum = 2
5471 12:45:37.658805 12, 0x0, sum = 3
5472 12:45:37.662235 13, 0x0, sum = 4
5473 12:45:37.662318 best_step = 11
5474 12:45:37.662383
5475 12:45:37.662444 ==
5476 12:45:37.665242 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 12:45:37.668652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 12:45:37.668736 ==
5479 12:45:37.672036 RX Vref Scan: 0
5480 12:45:37.672127
5481 12:45:37.675069 RX Vref 0 -> 0, step: 1
5482 12:45:37.675153
5483 12:45:37.675236 RX Delay -61 -> 252, step: 4
5484 12:45:37.683454 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5485 12:45:37.686257 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5486 12:45:37.690102 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5487 12:45:37.693246 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5488 12:45:37.696579 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5489 12:45:37.703105 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5490 12:45:37.706246 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5491 12:45:37.709414 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5492 12:45:37.712669 iDelay=199, Bit 8, Center 82 (-9 ~ 174) 184
5493 12:45:37.715940 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5494 12:45:37.719249 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5495 12:45:37.726588 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5496 12:45:37.729448 iDelay=199, Bit 12, Center 94 (-1 ~ 190) 192
5497 12:45:37.732714 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5498 12:45:37.736527 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5499 12:45:37.742338 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5500 12:45:37.742448 ==
5501 12:45:37.746081 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 12:45:37.749291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 12:45:37.749386 ==
5504 12:45:37.749460 DQS Delay:
5505 12:45:37.752476 DQS0 = 0, DQS1 = 0
5506 12:45:37.752589 DQM Delay:
5507 12:45:37.755786 DQM0 = 95, DQM1 = 88
5508 12:45:37.755887 DQ Delay:
5509 12:45:37.759292 DQ0 =90, DQ1 =98, DQ2 =90, DQ3 =94
5510 12:45:37.762167 DQ4 =94, DQ5 =88, DQ6 =104, DQ7 =104
5511 12:45:37.765570 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =82
5512 12:45:37.769040 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =92
5513 12:45:37.769175
5514 12:45:37.769314
5515 12:45:37.778596 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5516 12:45:37.778774 CH0 RK1: MR19=504, MR18=28F8
5517 12:45:37.785060 CH0_RK1: MR19=0x504, MR18=0x28F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5518 12:45:37.788688 [RxdqsGatingPostProcess] freq 933
5519 12:45:37.795587 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5520 12:45:37.798633 best DQS0 dly(2T, 0.5T) = (0, 10)
5521 12:45:37.801865 best DQS1 dly(2T, 0.5T) = (0, 11)
5522 12:45:37.805262 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5523 12:45:37.808454 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5524 12:45:37.811535 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 12:45:37.815123 best DQS1 dly(2T, 0.5T) = (0, 11)
5526 12:45:37.818249 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 12:45:37.821896 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5528 12:45:37.822341 Pre-setting of DQS Precalculation
5529 12:45:37.828480 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5530 12:45:37.828940 ==
5531 12:45:37.831782 Dram Type= 6, Freq= 0, CH_1, rank 0
5532 12:45:37.835029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 12:45:37.835453 ==
5534 12:45:37.841436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 12:45:37.847978 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 12:45:37.851782 [CA 0] Center 37 (7~67) winsize 61
5537 12:45:37.854584 [CA 1] Center 37 (7~68) winsize 62
5538 12:45:37.858121 [CA 2] Center 34 (4~65) winsize 62
5539 12:45:37.861524 [CA 3] Center 33 (3~64) winsize 62
5540 12:45:37.864740 [CA 4] Center 34 (4~64) winsize 61
5541 12:45:37.867507 [CA 5] Center 33 (3~64) winsize 62
5542 12:45:37.867589
5543 12:45:37.870775 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 12:45:37.870858
5545 12:45:37.874146 [CATrainingPosCal] consider 1 rank data
5546 12:45:37.877395 u2DelayCellTimex100 = 270/100 ps
5547 12:45:37.880310 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5548 12:45:37.883904 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5549 12:45:37.887601 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5550 12:45:37.890618 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5551 12:45:37.893985 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5552 12:45:37.900324 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 12:45:37.900438
5554 12:45:37.903707 CA PerBit enable=1, Macro0, CA PI delay=33
5555 12:45:37.903788
5556 12:45:37.907035 [CBTSetCACLKResult] CA Dly = 33
5557 12:45:37.907122 CS Dly: 6 (0~37)
5558 12:45:37.907193 ==
5559 12:45:37.909921 Dram Type= 6, Freq= 0, CH_1, rank 1
5560 12:45:37.917126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 12:45:37.917208 ==
5562 12:45:37.920094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 12:45:37.926513 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5564 12:45:37.929778 [CA 0] Center 36 (6~67) winsize 62
5565 12:45:37.933394 [CA 1] Center 37 (7~67) winsize 61
5566 12:45:37.936384 [CA 2] Center 34 (4~65) winsize 62
5567 12:45:37.939751 [CA 3] Center 34 (3~65) winsize 63
5568 12:45:37.943491 [CA 4] Center 34 (3~65) winsize 63
5569 12:45:37.946686 [CA 5] Center 33 (3~64) winsize 62
5570 12:45:37.946769
5571 12:45:37.949404 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5572 12:45:37.949532
5573 12:45:37.953030 [CATrainingPosCal] consider 2 rank data
5574 12:45:37.955919 u2DelayCellTimex100 = 270/100 ps
5575 12:45:37.959385 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5576 12:45:37.965990 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5577 12:45:37.969427 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5578 12:45:37.972706 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5579 12:45:37.976332 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5580 12:45:37.979106 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5581 12:45:37.979189
5582 12:45:37.983025 CA PerBit enable=1, Macro0, CA PI delay=33
5583 12:45:37.983109
5584 12:45:37.985863 [CBTSetCACLKResult] CA Dly = 33
5585 12:45:37.985946 CS Dly: 7 (0~39)
5586 12:45:37.989321
5587 12:45:37.992282 ----->DramcWriteLeveling(PI) begin...
5588 12:45:37.992366 ==
5589 12:45:37.996294 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 12:45:37.999524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 12:45:37.999640 ==
5592 12:45:38.002489 Write leveling (Byte 0): 25 => 25
5593 12:45:38.005794 Write leveling (Byte 1): 25 => 25
5594 12:45:38.008644 DramcWriteLeveling(PI) end<-----
5595 12:45:38.008727
5596 12:45:38.008810 ==
5597 12:45:38.012319 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 12:45:38.015751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 12:45:38.015835 ==
5600 12:45:38.018876 [Gating] SW mode calibration
5601 12:45:38.026044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5602 12:45:38.032135 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5603 12:45:38.035334 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 12:45:38.038689 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 12:45:38.045564 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 12:45:38.048739 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 12:45:38.051841 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 12:45:38.058181 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 12:45:38.061860 0 14 24 | B1->B0 | 3333 3333 | 0 1 | (0 1) (1 0)
5610 12:45:38.064599 0 14 28 | B1->B0 | 2e2e 2a2a | 0 0 | (0 1) (1 1)
5611 12:45:38.071743 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 12:45:38.075086 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 12:45:38.078289 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 12:45:38.084764 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 12:45:38.088023 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 12:45:38.091140 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 12:45:38.097560 0 15 24 | B1->B0 | 2626 2727 | 0 1 | (0 0) (0 0)
5618 12:45:38.101175 0 15 28 | B1->B0 | 3737 3939 | 1 0 | (0 0) (0 0)
5619 12:45:38.104752 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 12:45:38.111178 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 12:45:38.114450 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 12:45:38.117919 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 12:45:38.124512 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 12:45:38.128004 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5625 12:45:38.130837 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5626 12:45:38.137955 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 12:45:38.141201 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 12:45:38.144733 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 12:45:38.151630 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:45:38.154119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:45:38.158094 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:45:38.164319 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:45:38.168047 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:45:38.171279 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:45:38.177449 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:45:38.181322 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:45:38.184624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:45:38.191363 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:45:38.194173 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:45:38.197706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:45:38.203805 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5642 12:45:38.207469 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 12:45:38.210832 Total UI for P1: 0, mck2ui 16
5644 12:45:38.213924 best dqsien dly found for B0: ( 1, 2, 24)
5645 12:45:38.217434 Total UI for P1: 0, mck2ui 16
5646 12:45:38.220605 best dqsien dly found for B1: ( 1, 2, 24)
5647 12:45:38.224372 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5648 12:45:38.227262 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5649 12:45:38.227684
5650 12:45:38.230388 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5651 12:45:38.233357 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5652 12:45:38.236924 [Gating] SW calibration Done
5653 12:45:38.237365 ==
5654 12:45:38.239920 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 12:45:38.246548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 12:45:38.247086 ==
5657 12:45:38.247434 RX Vref Scan: 0
5658 12:45:38.247754
5659 12:45:38.250360 RX Vref 0 -> 0, step: 1
5660 12:45:38.250788
5661 12:45:38.253365 RX Delay -80 -> 252, step: 8
5662 12:45:38.256575 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5663 12:45:38.260286 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5664 12:45:38.263014 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5665 12:45:38.266348 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5666 12:45:38.273543 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5667 12:45:38.276346 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5668 12:45:38.279605 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5669 12:45:38.282867 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5670 12:45:38.286329 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5671 12:45:38.289219 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5672 12:45:38.295946 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5673 12:45:38.299372 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5674 12:45:38.303017 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5675 12:45:38.305811 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5676 12:45:38.309248 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5677 12:45:38.316298 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5678 12:45:38.316564 ==
5679 12:45:38.319023 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 12:45:38.322544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 12:45:38.322749 ==
5682 12:45:38.322905 DQS Delay:
5683 12:45:38.325415 DQS0 = 0, DQS1 = 0
5684 12:45:38.325611 DQM Delay:
5685 12:45:38.328976 DQM0 = 102, DQM1 = 90
5686 12:45:38.329137 DQ Delay:
5687 12:45:38.331973 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =103
5688 12:45:38.335406 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5689 12:45:38.338914 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5690 12:45:38.342565 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =103
5691 12:45:38.342809
5692 12:45:38.342941
5693 12:45:38.343059 ==
5694 12:45:38.345758 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 12:45:38.352217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 12:45:38.352469 ==
5697 12:45:38.352672
5698 12:45:38.352830
5699 12:45:38.352983 TX Vref Scan disable
5700 12:45:38.355369 == TX Byte 0 ==
5701 12:45:38.359921 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 12:45:38.366037 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 12:45:38.366344 == TX Byte 1 ==
5704 12:45:38.368933 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5705 12:45:38.375630 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5706 12:45:38.376052 ==
5707 12:45:38.379257 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 12:45:38.382614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 12:45:38.383300 ==
5710 12:45:38.383657
5711 12:45:38.383970
5712 12:45:38.385479 TX Vref Scan disable
5713 12:45:38.386091 == TX Byte 0 ==
5714 12:45:38.392654 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5715 12:45:38.395851 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5716 12:45:38.396486 == TX Byte 1 ==
5717 12:45:38.402554 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5718 12:45:38.405410 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5719 12:45:38.405875
5720 12:45:38.406242 [DATLAT]
5721 12:45:38.409121 Freq=933, CH1 RK0
5722 12:45:38.409621
5723 12:45:38.410015 DATLAT Default: 0xd
5724 12:45:38.412036 0, 0xFFFF, sum = 0
5725 12:45:38.415717 1, 0xFFFF, sum = 0
5726 12:45:38.416298 2, 0xFFFF, sum = 0
5727 12:45:38.418713 3, 0xFFFF, sum = 0
5728 12:45:38.419297 4, 0xFFFF, sum = 0
5729 12:45:38.422294 5, 0xFFFF, sum = 0
5730 12:45:38.422791 6, 0xFFFF, sum = 0
5731 12:45:38.425285 7, 0xFFFF, sum = 0
5732 12:45:38.425755 8, 0xFFFF, sum = 0
5733 12:45:38.428450 9, 0xFFFF, sum = 0
5734 12:45:38.429037 10, 0x0, sum = 1
5735 12:45:38.431490 11, 0x0, sum = 2
5736 12:45:38.431961 12, 0x0, sum = 3
5737 12:45:38.435123 13, 0x0, sum = 4
5738 12:45:38.435549 best_step = 11
5739 12:45:38.435883
5740 12:45:38.436194 ==
5741 12:45:38.438664 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 12:45:38.441883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 12:45:38.442408 ==
5744 12:45:38.445323 RX Vref Scan: 1
5745 12:45:38.445743
5746 12:45:38.448169 RX Vref 0 -> 0, step: 1
5747 12:45:38.448640
5748 12:45:38.448983 RX Delay -69 -> 252, step: 4
5749 12:45:38.449296
5750 12:45:38.451389 Set Vref, RX VrefLevel [Byte0]: 46
5751 12:45:38.455762 [Byte1]: 52
5752 12:45:38.459851
5753 12:45:38.460269 Final RX Vref Byte 0 = 46 to rank0
5754 12:45:38.462835 Final RX Vref Byte 1 = 52 to rank0
5755 12:45:38.466171 Final RX Vref Byte 0 = 46 to rank1
5756 12:45:38.469828 Final RX Vref Byte 1 = 52 to rank1==
5757 12:45:38.473090 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 12:45:38.479476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 12:45:38.480012 ==
5760 12:45:38.480379 DQS Delay:
5761 12:45:38.483284 DQS0 = 0, DQS1 = 0
5762 12:45:38.483698 DQM Delay:
5763 12:45:38.484031 DQM0 = 102, DQM1 = 95
5764 12:45:38.486015 DQ Delay:
5765 12:45:38.489656 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5766 12:45:38.492587 DQ4 =100, DQ5 =112, DQ6 =110, DQ7 =98
5767 12:45:38.496198 DQ8 =80, DQ9 =86, DQ10 =96, DQ11 =86
5768 12:45:38.499151 DQ12 =102, DQ13 =100, DQ14 =106, DQ15 =106
5769 12:45:38.499570
5770 12:45:38.499971
5771 12:45:38.505796 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5772 12:45:38.509195 CH1 RK0: MR19=505, MR18=1C0C
5773 12:45:38.515539 CH1_RK0: MR19=0x505, MR18=0x1C0C, DQSOSC=412, MR23=63, INC=63, DEC=42
5774 12:45:38.516092
5775 12:45:38.519048 ----->DramcWriteLeveling(PI) begin...
5776 12:45:38.519633 ==
5777 12:45:38.522446 Dram Type= 6, Freq= 0, CH_1, rank 1
5778 12:45:38.529201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 12:45:38.529774 ==
5780 12:45:38.532414 Write leveling (Byte 0): 26 => 26
5781 12:45:38.532997 Write leveling (Byte 1): 27 => 27
5782 12:45:38.535360 DramcWriteLeveling(PI) end<-----
5783 12:45:38.535831
5784 12:45:38.539151 ==
5785 12:45:38.542213 Dram Type= 6, Freq= 0, CH_1, rank 1
5786 12:45:38.545364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 12:45:38.545898 ==
5788 12:45:38.548664 [Gating] SW mode calibration
5789 12:45:38.555141 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5790 12:45:38.558235 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5791 12:45:38.565010 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5792 12:45:38.568393 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 12:45:38.571757 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 12:45:38.578334 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 12:45:38.581398 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 12:45:38.585148 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 12:45:38.591577 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
5798 12:45:38.594547 0 14 28 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
5799 12:45:38.597909 0 15 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5800 12:45:38.604451 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 12:45:38.607982 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 12:45:38.611565 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 12:45:38.617645 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 12:45:38.620802 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 12:45:38.624152 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5806 12:45:38.630868 0 15 28 | B1->B0 | 3e3e 3434 | 0 0 | (0 0) (0 0)
5807 12:45:38.634186 1 0 0 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
5808 12:45:38.637489 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 12:45:38.643959 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 12:45:38.646951 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 12:45:38.650756 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 12:45:38.657126 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 12:45:38.660445 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5814 12:45:38.663597 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5815 12:45:38.670124 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 12:45:38.673890 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 12:45:38.677416 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 12:45:38.683315 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 12:45:38.686706 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 12:45:38.690513 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 12:45:38.696483 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:45:38.700083 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 12:45:38.703318 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 12:45:38.710013 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 12:45:38.712908 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:45:38.716453 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:45:38.722975 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:45:38.726375 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:45:38.733204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 12:45:38.735645 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5831 12:45:38.739367 Total UI for P1: 0, mck2ui 16
5832 12:45:38.742948 best dqsien dly found for B0: ( 1, 2, 26)
5833 12:45:38.745898 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 12:45:38.749141 Total UI for P1: 0, mck2ui 16
5835 12:45:38.752710 best dqsien dly found for B1: ( 1, 2, 28)
5836 12:45:38.755874 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5837 12:45:38.759338 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5838 12:45:38.759859
5839 12:45:38.762352 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5840 12:45:38.768866 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5841 12:45:38.769426 [Gating] SW calibration Done
5842 12:45:38.769767 ==
5843 12:45:38.772184 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 12:45:38.778806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 12:45:38.779328 ==
5846 12:45:38.779669 RX Vref Scan: 0
5847 12:45:38.779985
5848 12:45:38.781983 RX Vref 0 -> 0, step: 1
5849 12:45:38.782465
5850 12:45:38.785778 RX Delay -80 -> 252, step: 8
5851 12:45:38.789003 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5852 12:45:38.792266 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5853 12:45:38.795387 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5854 12:45:38.801804 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5855 12:45:38.805585 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5856 12:45:38.808365 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5857 12:45:38.811778 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5858 12:45:38.815059 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5859 12:45:38.818433 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5860 12:45:38.824904 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5861 12:45:38.828363 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5862 12:45:38.831686 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5863 12:45:38.835315 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5864 12:45:38.838449 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5865 12:45:38.845230 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5866 12:45:38.848378 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5867 12:45:38.848917 ==
5868 12:45:38.851467 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 12:45:38.855033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 12:45:38.855535 ==
5871 12:45:38.856012 DQS Delay:
5872 12:45:38.858169 DQS0 = 0, DQS1 = 0
5873 12:45:38.858635 DQM Delay:
5874 12:45:38.861650 DQM0 = 99, DQM1 = 91
5875 12:45:38.862113 DQ Delay:
5876 12:45:38.864980 DQ0 =107, DQ1 =91, DQ2 =91, DQ3 =99
5877 12:45:38.868107 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5878 12:45:38.871596 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =79
5879 12:45:38.874647 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5880 12:45:38.875074
5881 12:45:38.875408
5882 12:45:38.875717 ==
5883 12:45:38.878187 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 12:45:38.884418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 12:45:38.884946 ==
5886 12:45:38.885432
5887 12:45:38.885958
5888 12:45:38.886319 TX Vref Scan disable
5889 12:45:38.887681 == TX Byte 0 ==
5890 12:45:38.891439 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5891 12:45:38.898422 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5892 12:45:38.899003 == TX Byte 1 ==
5893 12:45:38.900895 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5894 12:45:38.907615 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5895 12:45:38.908137 ==
5896 12:45:38.910765 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 12:45:38.914557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 12:45:38.915159 ==
5899 12:45:38.915545
5900 12:45:38.915888
5901 12:45:38.917482 TX Vref Scan disable
5902 12:45:38.917943 == TX Byte 0 ==
5903 12:45:38.924148 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5904 12:45:38.928068 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5905 12:45:38.928652 == TX Byte 1 ==
5906 12:45:38.934177 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5907 12:45:38.937627 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5908 12:45:38.938056
5909 12:45:38.938393 [DATLAT]
5910 12:45:38.941501 Freq=933, CH1 RK1
5911 12:45:38.942036
5912 12:45:38.942378 DATLAT Default: 0xb
5913 12:45:38.944452 0, 0xFFFF, sum = 0
5914 12:45:38.945045 1, 0xFFFF, sum = 0
5915 12:45:38.947583 2, 0xFFFF, sum = 0
5916 12:45:38.948068 3, 0xFFFF, sum = 0
5917 12:45:38.950856 4, 0xFFFF, sum = 0
5918 12:45:38.953968 5, 0xFFFF, sum = 0
5919 12:45:38.954435 6, 0xFFFF, sum = 0
5920 12:45:38.957582 7, 0xFFFF, sum = 0
5921 12:45:38.958049 8, 0xFFFF, sum = 0
5922 12:45:38.960543 9, 0xFFFF, sum = 0
5923 12:45:38.960969 10, 0x0, sum = 1
5924 12:45:38.963974 11, 0x0, sum = 2
5925 12:45:38.964397 12, 0x0, sum = 3
5926 12:45:38.967704 13, 0x0, sum = 4
5927 12:45:38.968125 best_step = 11
5928 12:45:38.968456
5929 12:45:38.968844 ==
5930 12:45:38.970265 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 12:45:38.973735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 12:45:38.974155 ==
5933 12:45:38.977591 RX Vref Scan: 0
5934 12:45:38.978007
5935 12:45:38.980496 RX Vref 0 -> 0, step: 1
5936 12:45:38.980948
5937 12:45:38.981282 RX Delay -61 -> 252, step: 4
5938 12:45:38.989023 iDelay=203, Bit 0, Center 106 (19 ~ 194) 176
5939 12:45:38.991920 iDelay=203, Bit 1, Center 96 (11 ~ 182) 172
5940 12:45:38.994953 iDelay=203, Bit 2, Center 92 (7 ~ 178) 172
5941 12:45:38.998900 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5942 12:45:39.001477 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
5943 12:45:39.007968 iDelay=203, Bit 5, Center 112 (27 ~ 198) 172
5944 12:45:39.011041 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5945 12:45:39.014534 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5946 12:45:39.018284 iDelay=203, Bit 8, Center 82 (-5 ~ 170) 176
5947 12:45:39.021405 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5948 12:45:39.027828 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5949 12:45:39.031383 iDelay=203, Bit 11, Center 82 (-5 ~ 170) 176
5950 12:45:39.034320 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5951 12:45:39.038156 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5952 12:45:39.040901 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5953 12:45:39.047747 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5954 12:45:39.048466 ==
5955 12:45:39.050795 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 12:45:39.054444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 12:45:39.054930 ==
5958 12:45:39.055413 DQS Delay:
5959 12:45:39.057923 DQS0 = 0, DQS1 = 0
5960 12:45:39.058508 DQM Delay:
5961 12:45:39.060740 DQM0 = 102, DQM1 = 92
5962 12:45:39.061225 DQ Delay:
5963 12:45:39.064109 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =100
5964 12:45:39.067359 DQ4 =100, DQ5 =112, DQ6 =114, DQ7 =96
5965 12:45:39.070584 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =82
5966 12:45:39.073884 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =102
5967 12:45:39.074305
5968 12:45:39.074642
5969 12:45:39.083899 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
5970 12:45:39.084326 CH1 RK1: MR19=504, MR18=5FF
5971 12:45:39.090615 CH1_RK1: MR19=0x504, MR18=0x5FF, DQSOSC=420, MR23=63, INC=61, DEC=40
5972 12:45:39.093707 [RxdqsGatingPostProcess] freq 933
5973 12:45:39.100502 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5974 12:45:39.103466 best DQS0 dly(2T, 0.5T) = (0, 10)
5975 12:45:39.106720 best DQS1 dly(2T, 0.5T) = (0, 10)
5976 12:45:39.110585 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5977 12:45:39.113347 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5978 12:45:39.116904 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 12:45:39.119959 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 12:45:39.123374 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 12:45:39.126425 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 12:45:39.126841 Pre-setting of DQS Precalculation
5983 12:45:39.133141 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5984 12:45:39.140228 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5985 12:45:39.146798 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5986 12:45:39.147353
5987 12:45:39.147721
5988 12:45:39.149670 [Calibration Summary] 1866 Mbps
5989 12:45:39.153136 CH 0, Rank 0
5990 12:45:39.153596 SW Impedance : PASS
5991 12:45:39.156338 DUTY Scan : NO K
5992 12:45:39.159585 ZQ Calibration : PASS
5993 12:45:39.160045 Jitter Meter : NO K
5994 12:45:39.162757 CBT Training : PASS
5995 12:45:39.166085 Write leveling : PASS
5996 12:45:39.166506 RX DQS gating : PASS
5997 12:45:39.169376 RX DQ/DQS(RDDQC) : PASS
5998 12:45:39.172625 TX DQ/DQS : PASS
5999 12:45:39.173046 RX DATLAT : PASS
6000 12:45:39.176178 RX DQ/DQS(Engine): PASS
6001 12:45:39.178979 TX OE : NO K
6002 12:45:39.179396 All Pass.
6003 12:45:39.179728
6004 12:45:39.180034 CH 0, Rank 1
6005 12:45:39.182219 SW Impedance : PASS
6006 12:45:39.185734 DUTY Scan : NO K
6007 12:45:39.185999 ZQ Calibration : PASS
6008 12:45:39.189531 Jitter Meter : NO K
6009 12:45:39.192462 CBT Training : PASS
6010 12:45:39.192661 Write leveling : PASS
6011 12:45:39.195497 RX DQS gating : PASS
6012 12:45:39.195677 RX DQ/DQS(RDDQC) : PASS
6013 12:45:39.199091 TX DQ/DQS : PASS
6014 12:45:39.202291 RX DATLAT : PASS
6015 12:45:39.202422 RX DQ/DQS(Engine): PASS
6016 12:45:39.205587 TX OE : NO K
6017 12:45:39.205719 All Pass.
6018 12:45:39.205823
6019 12:45:39.208846 CH 1, Rank 0
6020 12:45:39.208960 SW Impedance : PASS
6021 12:45:39.212039 DUTY Scan : NO K
6022 12:45:39.215130 ZQ Calibration : PASS
6023 12:45:39.215244 Jitter Meter : NO K
6024 12:45:39.218295 CBT Training : PASS
6025 12:45:39.221476 Write leveling : PASS
6026 12:45:39.221562 RX DQS gating : PASS
6027 12:45:39.225110 RX DQ/DQS(RDDQC) : PASS
6028 12:45:39.228156 TX DQ/DQS : PASS
6029 12:45:39.228266 RX DATLAT : PASS
6030 12:45:39.231852 RX DQ/DQS(Engine): PASS
6031 12:45:39.234667 TX OE : NO K
6032 12:45:39.234758 All Pass.
6033 12:45:39.234833
6034 12:45:39.234962 CH 1, Rank 1
6035 12:45:39.237998 SW Impedance : PASS
6036 12:45:39.241634 DUTY Scan : NO K
6037 12:45:39.241723 ZQ Calibration : PASS
6038 12:45:39.244913 Jitter Meter : NO K
6039 12:45:39.248035 CBT Training : PASS
6040 12:45:39.248118 Write leveling : PASS
6041 12:45:39.251549 RX DQS gating : PASS
6042 12:45:39.254643 RX DQ/DQS(RDDQC) : PASS
6043 12:45:39.254726 TX DQ/DQS : PASS
6044 12:45:39.258108 RX DATLAT : PASS
6045 12:45:39.261069 RX DQ/DQS(Engine): PASS
6046 12:45:39.261151 TX OE : NO K
6047 12:45:39.264630 All Pass.
6048 12:45:39.264711
6049 12:45:39.264775 DramC Write-DBI off
6050 12:45:39.267611 PER_BANK_REFRESH: Hybrid Mode
6051 12:45:39.267693 TX_TRACKING: ON
6052 12:45:39.277773 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6053 12:45:39.280943 [FAST_K] Save calibration result to emmc
6054 12:45:39.284243 dramc_set_vcore_voltage set vcore to 650000
6055 12:45:39.287493 Read voltage for 400, 6
6056 12:45:39.287575 Vio18 = 0
6057 12:45:39.290700 Vcore = 650000
6058 12:45:39.290782 Vdram = 0
6059 12:45:39.290847 Vddq = 0
6060 12:45:39.294306 Vmddr = 0
6061 12:45:39.297372 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6062 12:45:39.304161 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6063 12:45:39.304274 MEM_TYPE=3, freq_sel=20
6064 12:45:39.307275 sv_algorithm_assistance_LP4_800
6065 12:45:39.314436 ============ PULL DRAM RESETB DOWN ============
6066 12:45:39.316978 ========== PULL DRAM RESETB DOWN end =========
6067 12:45:39.320246 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6068 12:45:39.323640 ===================================
6069 12:45:39.327276 LPDDR4 DRAM CONFIGURATION
6070 12:45:39.330235 ===================================
6071 12:45:39.333811 EX_ROW_EN[0] = 0x0
6072 12:45:39.333894 EX_ROW_EN[1] = 0x0
6073 12:45:39.336813 LP4Y_EN = 0x0
6074 12:45:39.336895 WORK_FSP = 0x0
6075 12:45:39.340567 WL = 0x2
6076 12:45:39.340649 RL = 0x2
6077 12:45:39.343676 BL = 0x2
6078 12:45:39.343757 RPST = 0x0
6079 12:45:39.346915 RD_PRE = 0x0
6080 12:45:39.346996 WR_PRE = 0x1
6081 12:45:39.349644 WR_PST = 0x0
6082 12:45:39.349725 DBI_WR = 0x0
6083 12:45:39.353601 DBI_RD = 0x0
6084 12:45:39.353683 OTF = 0x1
6085 12:45:39.356165 ===================================
6086 12:45:39.359416 ===================================
6087 12:45:39.363104 ANA top config
6088 12:45:39.367183 ===================================
6089 12:45:39.370062 DLL_ASYNC_EN = 0
6090 12:45:39.370145 ALL_SLAVE_EN = 1
6091 12:45:39.373103 NEW_RANK_MODE = 1
6092 12:45:39.376234 DLL_IDLE_MODE = 1
6093 12:45:39.379657 LP45_APHY_COMB_EN = 1
6094 12:45:39.383127 TX_ODT_DIS = 1
6095 12:45:39.383210 NEW_8X_MODE = 1
6096 12:45:39.386639 ===================================
6097 12:45:39.389841 ===================================
6098 12:45:39.393044 data_rate = 800
6099 12:45:39.396431 CKR = 1
6100 12:45:39.399243 DQ_P2S_RATIO = 4
6101 12:45:39.402745 ===================================
6102 12:45:39.406262 CA_P2S_RATIO = 4
6103 12:45:39.409263 DQ_CA_OPEN = 0
6104 12:45:39.409345 DQ_SEMI_OPEN = 1
6105 12:45:39.412916 CA_SEMI_OPEN = 1
6106 12:45:39.416687 CA_FULL_RATE = 0
6107 12:45:39.419842 DQ_CKDIV4_EN = 0
6108 12:45:39.422725 CA_CKDIV4_EN = 1
6109 12:45:39.426013 CA_PREDIV_EN = 0
6110 12:45:39.426157 PH8_DLY = 0
6111 12:45:39.429082 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6112 12:45:39.432732 DQ_AAMCK_DIV = 0
6113 12:45:39.436320 CA_AAMCK_DIV = 0
6114 12:45:39.439351 CA_ADMCK_DIV = 4
6115 12:45:39.443043 DQ_TRACK_CA_EN = 0
6116 12:45:39.443241 CA_PICK = 800
6117 12:45:39.446220 CA_MCKIO = 400
6118 12:45:39.449565 MCKIO_SEMI = 400
6119 12:45:39.452422 PLL_FREQ = 3016
6120 12:45:39.455894 DQ_UI_PI_RATIO = 32
6121 12:45:39.458933 CA_UI_PI_RATIO = 32
6122 12:45:39.462436 ===================================
6123 12:45:39.465940 ===================================
6124 12:45:39.469563 memory_type:LPDDR4
6125 12:45:39.469851 GP_NUM : 10
6126 12:45:39.472859 SRAM_EN : 1
6127 12:45:39.473192 MD32_EN : 0
6128 12:45:39.475865 ===================================
6129 12:45:39.479111 [ANA_INIT] >>>>>>>>>>>>>>
6130 12:45:39.482412 <<<<<< [CONFIGURE PHASE]: ANA_TX
6131 12:45:39.486011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6132 12:45:39.489164 ===================================
6133 12:45:39.492623 data_rate = 800,PCW = 0X7400
6134 12:45:39.496117 ===================================
6135 12:45:39.499521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6136 12:45:39.505383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6137 12:45:39.515620 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 12:45:39.519134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6139 12:45:39.522041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6140 12:45:39.525221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6141 12:45:39.528814 [ANA_INIT] flow start
6142 12:45:39.531828 [ANA_INIT] PLL >>>>>>>>
6143 12:45:39.532337 [ANA_INIT] PLL <<<<<<<<
6144 12:45:39.535063 [ANA_INIT] MIDPI >>>>>>>>
6145 12:45:39.538099 [ANA_INIT] MIDPI <<<<<<<<
6146 12:45:39.541580 [ANA_INIT] DLL >>>>>>>>
6147 12:45:39.541663 [ANA_INIT] flow end
6148 12:45:39.544467 ============ LP4 DIFF to SE enter ============
6149 12:45:39.551383 ============ LP4 DIFF to SE exit ============
6150 12:45:39.551595 [ANA_INIT] <<<<<<<<<<<<<
6151 12:45:39.554962 [Flow] Enable top DCM control >>>>>
6152 12:45:39.558059 [Flow] Enable top DCM control <<<<<
6153 12:45:39.561276 Enable DLL master slave shuffle
6154 12:45:39.567910 ==============================================================
6155 12:45:39.568064 Gating Mode config
6156 12:45:39.574728 ==============================================================
6157 12:45:39.577849 Config description:
6158 12:45:39.589032 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6159 12:45:39.594393 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6160 12:45:39.597659 SELPH_MODE 0: By rank 1: By Phase
6161 12:45:39.604405 ==============================================================
6162 12:45:39.607557 GAT_TRACK_EN = 0
6163 12:45:39.610666 RX_GATING_MODE = 2
6164 12:45:39.615189 RX_GATING_TRACK_MODE = 2
6165 12:45:39.615275 SELPH_MODE = 1
6166 12:45:39.617630 PICG_EARLY_EN = 1
6167 12:45:39.621196 VALID_LAT_VALUE = 1
6168 12:45:39.627285 ==============================================================
6169 12:45:39.630678 Enter into Gating configuration >>>>
6170 12:45:39.634135 Exit from Gating configuration <<<<
6171 12:45:39.637965 Enter into DVFS_PRE_config >>>>>
6172 12:45:39.647074 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6173 12:45:39.650095 Exit from DVFS_PRE_config <<<<<
6174 12:45:39.653511 Enter into PICG configuration >>>>
6175 12:45:39.657053 Exit from PICG configuration <<<<
6176 12:45:39.659966 [RX_INPUT] configuration >>>>>
6177 12:45:39.663126 [RX_INPUT] configuration <<<<<
6178 12:45:39.666551 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6179 12:45:39.673277 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6180 12:45:39.679726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6181 12:45:39.686837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6182 12:45:39.693279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6183 12:45:39.699611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6184 12:45:39.702989 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6185 12:45:39.706567 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6186 12:45:39.709505 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6187 12:45:39.715826 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6188 12:45:39.719580 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6189 12:45:39.722970 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6190 12:45:39.726104 ===================================
6191 12:45:39.729464 LPDDR4 DRAM CONFIGURATION
6192 12:45:39.732680 ===================================
6193 12:45:39.732763 EX_ROW_EN[0] = 0x0
6194 12:45:39.735881 EX_ROW_EN[1] = 0x0
6195 12:45:39.738987 LP4Y_EN = 0x0
6196 12:45:39.739069 WORK_FSP = 0x0
6197 12:45:39.742153 WL = 0x2
6198 12:45:39.742234 RL = 0x2
6199 12:45:39.746031 BL = 0x2
6200 12:45:39.746112 RPST = 0x0
6201 12:45:39.748773 RD_PRE = 0x0
6202 12:45:39.748855 WR_PRE = 0x1
6203 12:45:39.752208 WR_PST = 0x0
6204 12:45:39.752315 DBI_WR = 0x0
6205 12:45:39.755327 DBI_RD = 0x0
6206 12:45:39.755409 OTF = 0x1
6207 12:45:39.759324 ===================================
6208 12:45:39.762390 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6209 12:45:39.768821 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6210 12:45:39.771824 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 12:45:39.775422 ===================================
6212 12:45:39.779070 LPDDR4 DRAM CONFIGURATION
6213 12:45:39.781912 ===================================
6214 12:45:39.785273 EX_ROW_EN[0] = 0x10
6215 12:45:39.785371 EX_ROW_EN[1] = 0x0
6216 12:45:39.788474 LP4Y_EN = 0x0
6217 12:45:39.788607 WORK_FSP = 0x0
6218 12:45:39.791807 WL = 0x2
6219 12:45:39.791889 RL = 0x2
6220 12:45:39.795364 BL = 0x2
6221 12:45:39.795517 RPST = 0x0
6222 12:45:39.798115 RD_PRE = 0x0
6223 12:45:39.798242 WR_PRE = 0x1
6224 12:45:39.801513 WR_PST = 0x0
6225 12:45:39.801671 DBI_WR = 0x0
6226 12:45:39.804817 DBI_RD = 0x0
6227 12:45:39.804921 OTF = 0x1
6228 12:45:39.808812 ===================================
6229 12:45:39.815683 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6230 12:45:39.819646 nWR fixed to 30
6231 12:45:39.823108 [ModeRegInit_LP4] CH0 RK0
6232 12:45:39.823270 [ModeRegInit_LP4] CH0 RK1
6233 12:45:39.826149 [ModeRegInit_LP4] CH1 RK0
6234 12:45:39.830370 [ModeRegInit_LP4] CH1 RK1
6235 12:45:39.830529 match AC timing 19
6236 12:45:39.836124 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6237 12:45:39.839644 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6238 12:45:39.842600 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6239 12:45:39.849022 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6240 12:45:39.852177 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6241 12:45:39.852368 ==
6242 12:45:39.855518 Dram Type= 6, Freq= 0, CH_0, rank 0
6243 12:45:39.858981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 12:45:39.862550 ==
6245 12:45:39.865731 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 12:45:39.872316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6247 12:45:39.876703 [CA 0] Center 36 (8~64) winsize 57
6248 12:45:39.878498 [CA 1] Center 36 (8~64) winsize 57
6249 12:45:39.882724 [CA 2] Center 36 (8~64) winsize 57
6250 12:45:39.885386 [CA 3] Center 36 (8~64) winsize 57
6251 12:45:39.889133 [CA 4] Center 36 (8~64) winsize 57
6252 12:45:39.892263 [CA 5] Center 36 (8~64) winsize 57
6253 12:45:39.892874
6254 12:45:39.895378 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6255 12:45:39.895934
6256 12:45:39.898800 [CATrainingPosCal] consider 1 rank data
6257 12:45:39.902418 u2DelayCellTimex100 = 270/100 ps
6258 12:45:39.905504 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:45:39.908589 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:45:39.912232 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:45:39.915203 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 12:45:39.918854 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 12:45:39.922399 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 12:45:39.922977
6265 12:45:39.929147 CA PerBit enable=1, Macro0, CA PI delay=36
6266 12:45:39.929719
6267 12:45:39.930091 [CBTSetCACLKResult] CA Dly = 36
6268 12:45:39.932240 CS Dly: 1 (0~32)
6269 12:45:39.932828 ==
6270 12:45:39.935179 Dram Type= 6, Freq= 0, CH_0, rank 1
6271 12:45:39.937805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 12:45:39.937886 ==
6273 12:45:39.944650 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6274 12:45:39.951241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6275 12:45:39.954371 [CA 0] Center 36 (8~64) winsize 57
6276 12:45:39.958524 [CA 1] Center 36 (8~64) winsize 57
6277 12:45:39.961056 [CA 2] Center 36 (8~64) winsize 57
6278 12:45:39.964548 [CA 3] Center 36 (8~64) winsize 57
6279 12:45:39.967937 [CA 4] Center 36 (8~64) winsize 57
6280 12:45:39.971329 [CA 5] Center 36 (8~64) winsize 57
6281 12:45:39.971489
6282 12:45:39.974652 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6283 12:45:39.974813
6284 12:45:39.977401 [CATrainingPosCal] consider 2 rank data
6285 12:45:39.980494 u2DelayCellTimex100 = 270/100 ps
6286 12:45:39.984308 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 12:45:39.987248 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 12:45:39.990437 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 12:45:39.994034 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 12:45:39.997889 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 12:45:40.000914 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 12:45:40.001097
6293 12:45:40.003691 CA PerBit enable=1, Macro0, CA PI delay=36
6294 12:45:40.007311
6295 12:45:40.007420 [CBTSetCACLKResult] CA Dly = 36
6296 12:45:40.010892 CS Dly: 1 (0~32)
6297 12:45:40.011085
6298 12:45:40.013712 ----->DramcWriteLeveling(PI) begin...
6299 12:45:40.013909 ==
6300 12:45:40.016980 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 12:45:40.020339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 12:45:40.020561 ==
6303 12:45:40.023643 Write leveling (Byte 0): 40 => 8
6304 12:45:40.026919 Write leveling (Byte 1): 32 => 0
6305 12:45:40.030810 DramcWriteLeveling(PI) end<-----
6306 12:45:40.031031
6307 12:45:40.031177 ==
6308 12:45:40.033977 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 12:45:40.036801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 12:45:40.040192 ==
6311 12:45:40.040413 [Gating] SW mode calibration
6312 12:45:40.050468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6313 12:45:40.053806 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6314 12:45:40.056974 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6315 12:45:40.063460 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 12:45:40.066769 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 12:45:40.070084 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 12:45:40.076900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6319 12:45:40.080775 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 12:45:40.083910 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 12:45:40.090148 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 12:45:40.093499 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 12:45:40.096657 Total UI for P1: 0, mck2ui 16
6324 12:45:40.100059 best dqsien dly found for B0: ( 0, 14, 24)
6325 12:45:40.103719 Total UI for P1: 0, mck2ui 16
6326 12:45:40.106361 best dqsien dly found for B1: ( 0, 14, 24)
6327 12:45:40.109207 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6328 12:45:40.113162 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6329 12:45:40.113615
6330 12:45:40.116166 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6331 12:45:40.122560 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 12:45:40.123125 [Gating] SW calibration Done
6333 12:45:40.123541 ==
6334 12:45:40.125840 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 12:45:40.133313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 12:45:40.133897 ==
6337 12:45:40.134303 RX Vref Scan: 0
6338 12:45:40.134678
6339 12:45:40.136672 RX Vref 0 -> 0, step: 1
6340 12:45:40.137220
6341 12:45:40.139539 RX Delay -410 -> 252, step: 16
6342 12:45:40.142884 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6343 12:45:40.146376 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6344 12:45:40.152134 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6345 12:45:40.155620 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6346 12:45:40.158981 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6347 12:45:40.162341 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6348 12:45:40.168784 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6349 12:45:40.172333 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6350 12:45:40.175627 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6351 12:45:40.179568 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6352 12:45:40.185526 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6353 12:45:40.188663 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6354 12:45:40.192659 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6355 12:45:40.198961 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6356 12:45:40.202286 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6357 12:45:40.205147 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6358 12:45:40.205725 ==
6359 12:45:40.208489 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 12:45:40.212480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 12:45:40.215157 ==
6362 12:45:40.215724 DQS Delay:
6363 12:45:40.216098 DQS0 = 43, DQS1 = 59
6364 12:45:40.218621 DQM Delay:
6365 12:45:40.219191 DQM0 = 10, DQM1 = 13
6366 12:45:40.222284 DQ Delay:
6367 12:45:40.222865 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6368 12:45:40.225025 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6369 12:45:40.228893 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6370 12:45:40.231537 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6371 12:45:40.232107
6372 12:45:40.232485
6373 12:45:40.234469 ==
6374 12:45:40.237911 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 12:45:40.242444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 12:45:40.243022 ==
6377 12:45:40.243466
6378 12:45:40.243819
6379 12:45:40.244765 TX Vref Scan disable
6380 12:45:40.245232 == TX Byte 0 ==
6381 12:45:40.248205 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 12:45:40.254385 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 12:45:40.254859 == TX Byte 1 ==
6384 12:45:40.257845 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6385 12:45:40.264391 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6386 12:45:40.265017 ==
6387 12:45:40.267872 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 12:45:40.271527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 12:45:40.272000 ==
6390 12:45:40.272377
6391 12:45:40.272762
6392 12:45:40.274111 TX Vref Scan disable
6393 12:45:40.274577 == TX Byte 0 ==
6394 12:45:40.277819 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 12:45:40.284448 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 12:45:40.285044 == TX Byte 1 ==
6397 12:45:40.287644 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6398 12:45:40.294422 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6399 12:45:40.294997
6400 12:45:40.295374 [DATLAT]
6401 12:45:40.297845 Freq=400, CH0 RK0
6402 12:45:40.298415
6403 12:45:40.298790 DATLAT Default: 0xf
6404 12:45:40.300909 0, 0xFFFF, sum = 0
6405 12:45:40.301493 1, 0xFFFF, sum = 0
6406 12:45:40.304040 2, 0xFFFF, sum = 0
6407 12:45:40.304668 3, 0xFFFF, sum = 0
6408 12:45:40.307313 4, 0xFFFF, sum = 0
6409 12:45:40.307824 5, 0xFFFF, sum = 0
6410 12:45:40.310651 6, 0xFFFF, sum = 0
6411 12:45:40.311128 7, 0xFFFF, sum = 0
6412 12:45:40.313856 8, 0xFFFF, sum = 0
6413 12:45:40.314436 9, 0xFFFF, sum = 0
6414 12:45:40.317718 10, 0xFFFF, sum = 0
6415 12:45:40.321089 11, 0xFFFF, sum = 0
6416 12:45:40.321564 12, 0xFFFF, sum = 0
6417 12:45:40.323861 13, 0x0, sum = 1
6418 12:45:40.324483 14, 0x0, sum = 2
6419 12:45:40.324905 15, 0x0, sum = 3
6420 12:45:40.327168 16, 0x0, sum = 4
6421 12:45:40.327643 best_step = 14
6422 12:45:40.328013
6423 12:45:40.330143 ==
6424 12:45:40.330614 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 12:45:40.336772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 12:45:40.337268 ==
6427 12:45:40.337645 RX Vref Scan: 1
6428 12:45:40.337996
6429 12:45:40.340102 RX Vref 0 -> 0, step: 1
6430 12:45:40.340625
6431 12:45:40.343626 RX Delay -359 -> 252, step: 8
6432 12:45:40.344192
6433 12:45:40.346828 Set Vref, RX VrefLevel [Byte0]: 55
6434 12:45:40.350089 [Byte1]: 57
6435 12:45:40.353614
6436 12:45:40.354082 Final RX Vref Byte 0 = 55 to rank0
6437 12:45:40.357232 Final RX Vref Byte 1 = 57 to rank0
6438 12:45:40.360666 Final RX Vref Byte 0 = 55 to rank1
6439 12:45:40.363732 Final RX Vref Byte 1 = 57 to rank1==
6440 12:45:40.366898 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 12:45:40.374079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 12:45:40.374747 ==
6443 12:45:40.375221 DQS Delay:
6444 12:45:40.377152 DQS0 = 48, DQS1 = 60
6445 12:45:40.377622 DQM Delay:
6446 12:45:40.377993 DQM0 = 12, DQM1 = 11
6447 12:45:40.380199 DQ Delay:
6448 12:45:40.383623 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6449 12:45:40.386690 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6450 12:45:40.387164 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6451 12:45:40.390508 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6452 12:45:40.393793
6453 12:45:40.394352
6454 12:45:40.400701 [DQSOSCAuto] RK0, (LSB)MR18= 0xba7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6455 12:45:40.404285 CH0 RK0: MR19=C0C, MR18=BA7D
6456 12:45:40.409946 CH0_RK0: MR19=0xC0C, MR18=0xBA7D, DQSOSC=386, MR23=63, INC=396, DEC=264
6457 12:45:40.410420 ==
6458 12:45:40.413241 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 12:45:40.416597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 12:45:40.417073 ==
6461 12:45:40.420019 [Gating] SW mode calibration
6462 12:45:40.426248 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6463 12:45:40.434097 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6464 12:45:40.436366 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6465 12:45:40.439902 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 12:45:40.446630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 12:45:40.449984 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 12:45:40.452653 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 12:45:40.459408 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 12:45:40.462459 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 12:45:40.465956 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 12:45:40.472621 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 12:45:40.475583 Total UI for P1: 0, mck2ui 16
6474 12:45:40.478984 best dqsien dly found for B0: ( 0, 14, 24)
6475 12:45:40.479449 Total UI for P1: 0, mck2ui 16
6476 12:45:40.485864 best dqsien dly found for B1: ( 0, 14, 24)
6477 12:45:40.488933 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6478 12:45:40.492824 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6479 12:45:40.493409
6480 12:45:40.495946 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6481 12:45:40.498994 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 12:45:40.502376 [Gating] SW calibration Done
6483 12:45:40.502935 ==
6484 12:45:40.506126 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 12:45:40.509010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 12:45:40.509493 ==
6487 12:45:40.512592 RX Vref Scan: 0
6488 12:45:40.513166
6489 12:45:40.515615 RX Vref 0 -> 0, step: 1
6490 12:45:40.516179
6491 12:45:40.516586 RX Delay -410 -> 252, step: 16
6492 12:45:40.522561 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6493 12:45:40.525663 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6494 12:45:40.529281 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6495 12:45:40.532079 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6496 12:45:40.538925 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6497 12:45:40.542325 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6498 12:45:40.545057 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6499 12:45:40.552215 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6500 12:45:40.555312 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6501 12:45:40.558162 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6502 12:45:40.561926 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6503 12:45:40.568811 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6504 12:45:40.572318 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6505 12:45:40.574982 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6506 12:45:40.578596 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6507 12:45:40.584638 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6508 12:45:40.585197 ==
6509 12:45:40.588394 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 12:45:40.591796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 12:45:40.592264 ==
6512 12:45:40.592692 DQS Delay:
6513 12:45:40.594817 DQS0 = 43, DQS1 = 59
6514 12:45:40.595275 DQM Delay:
6515 12:45:40.598188 DQM0 = 11, DQM1 = 17
6516 12:45:40.598747 DQ Delay:
6517 12:45:40.601299 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6518 12:45:40.604964 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6519 12:45:40.607914 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6520 12:45:40.611301 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6521 12:45:40.611866
6522 12:45:40.612234
6523 12:45:40.612633 ==
6524 12:45:40.614781 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 12:45:40.617689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 12:45:40.618156 ==
6527 12:45:40.618564
6528 12:45:40.621125
6529 12:45:40.621586 TX Vref Scan disable
6530 12:45:40.624636 == TX Byte 0 ==
6531 12:45:40.627943 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6532 12:45:40.631152 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6533 12:45:40.634416 == TX Byte 1 ==
6534 12:45:40.637784 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6535 12:45:40.640683 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6536 12:45:40.641151 ==
6537 12:45:40.644398 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 12:45:40.647939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 12:45:40.648547 ==
6540 12:45:40.650448
6541 12:45:40.650933
6542 12:45:40.651466 TX Vref Scan disable
6543 12:45:40.654105 == TX Byte 0 ==
6544 12:45:40.658143 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6545 12:45:40.660701 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6546 12:45:40.664606 == TX Byte 1 ==
6547 12:45:40.667339 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6548 12:45:40.671068 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6549 12:45:40.671638
6550 12:45:40.672007 [DATLAT]
6551 12:45:40.673994 Freq=400, CH0 RK1
6552 12:45:40.674562
6553 12:45:40.677188 DATLAT Default: 0xe
6554 12:45:40.677653 0, 0xFFFF, sum = 0
6555 12:45:40.680689 1, 0xFFFF, sum = 0
6556 12:45:40.681357 2, 0xFFFF, sum = 0
6557 12:45:40.685190 3, 0xFFFF, sum = 0
6558 12:45:40.685665 4, 0xFFFF, sum = 0
6559 12:45:40.687134 5, 0xFFFF, sum = 0
6560 12:45:40.687609 6, 0xFFFF, sum = 0
6561 12:45:40.691054 7, 0xFFFF, sum = 0
6562 12:45:40.691630 8, 0xFFFF, sum = 0
6563 12:45:40.694288 9, 0xFFFF, sum = 0
6564 12:45:40.694766 10, 0xFFFF, sum = 0
6565 12:45:40.697269 11, 0xFFFF, sum = 0
6566 12:45:40.697851 12, 0xFFFF, sum = 0
6567 12:45:40.700433 13, 0x0, sum = 1
6568 12:45:40.701050 14, 0x0, sum = 2
6569 12:45:40.704232 15, 0x0, sum = 3
6570 12:45:40.704863 16, 0x0, sum = 4
6571 12:45:40.707306 best_step = 14
6572 12:45:40.707874
6573 12:45:40.708250 ==
6574 12:45:40.710190 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 12:45:40.713702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 12:45:40.714174 ==
6577 12:45:40.717195 RX Vref Scan: 0
6578 12:45:40.717662
6579 12:45:40.718033 RX Vref 0 -> 0, step: 1
6580 12:45:40.718383
6581 12:45:40.720212 RX Delay -359 -> 252, step: 8
6582 12:45:40.728135 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6583 12:45:40.731344 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6584 12:45:40.734670 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6585 12:45:40.738520 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6586 12:45:40.745156 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6587 12:45:40.748213 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6588 12:45:40.751699 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6589 12:45:40.754693 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6590 12:45:40.761644 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6591 12:45:40.764590 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6592 12:45:40.767798 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6593 12:45:40.774458 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6594 12:45:40.778239 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6595 12:45:40.781110 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6596 12:45:40.784632 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6597 12:45:40.791128 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6598 12:45:40.791723 ==
6599 12:45:40.794457 Dram Type= 6, Freq= 0, CH_0, rank 1
6600 12:45:40.797598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 12:45:40.798178 ==
6602 12:45:40.798554 DQS Delay:
6603 12:45:40.801753 DQS0 = 44, DQS1 = 56
6604 12:45:40.802327 DQM Delay:
6605 12:45:40.803928 DQM0 = 8, DQM1 = 11
6606 12:45:40.804394 DQ Delay:
6607 12:45:40.807679 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6608 12:45:40.810892 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6609 12:45:40.814557 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6610 12:45:40.817865 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6611 12:45:40.818439
6612 12:45:40.818819
6613 12:45:40.824207 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf3d, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6614 12:45:40.827308 CH0 RK1: MR19=C0C, MR18=AF3D
6615 12:45:40.834012 CH0_RK1: MR19=0xC0C, MR18=0xAF3D, DQSOSC=388, MR23=63, INC=392, DEC=261
6616 12:45:40.837780 [RxdqsGatingPostProcess] freq 400
6617 12:45:40.843587 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6618 12:45:40.847354 best DQS0 dly(2T, 0.5T) = (0, 10)
6619 12:45:40.847926 best DQS1 dly(2T, 0.5T) = (0, 10)
6620 12:45:40.850461 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6621 12:45:40.853783 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6622 12:45:40.857125 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 12:45:40.860196 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 12:45:40.863521 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 12:45:40.866731 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 12:45:40.869949 Pre-setting of DQS Precalculation
6627 12:45:40.877501 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6628 12:45:40.878062 ==
6629 12:45:40.880383 Dram Type= 6, Freq= 0, CH_1, rank 0
6630 12:45:40.883675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 12:45:40.884237 ==
6632 12:45:40.890319 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 12:45:40.896852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6634 12:45:40.899735 [CA 0] Center 36 (8~64) winsize 57
6635 12:45:40.900200 [CA 1] Center 36 (8~64) winsize 57
6636 12:45:40.903417 [CA 2] Center 36 (8~64) winsize 57
6637 12:45:40.906970 [CA 3] Center 36 (8~64) winsize 57
6638 12:45:40.909651 [CA 4] Center 36 (8~64) winsize 57
6639 12:45:40.913084 [CA 5] Center 36 (8~64) winsize 57
6640 12:45:40.913551
6641 12:45:40.916749 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6642 12:45:40.917297
6643 12:45:40.922948 [CATrainingPosCal] consider 1 rank data
6644 12:45:40.923510 u2DelayCellTimex100 = 270/100 ps
6645 12:45:40.929951 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:45:40.932677 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:45:40.936182 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:45:40.939715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 12:45:40.942888 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 12:45:40.945727 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 12:45:40.946192
6652 12:45:40.949303 CA PerBit enable=1, Macro0, CA PI delay=36
6653 12:45:40.950001
6654 12:45:40.952578 [CBTSetCACLKResult] CA Dly = 36
6655 12:45:40.955734 CS Dly: 1 (0~32)
6656 12:45:40.956205 ==
6657 12:45:40.959466 Dram Type= 6, Freq= 0, CH_1, rank 1
6658 12:45:40.962306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 12:45:40.962882 ==
6660 12:45:40.969184 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6661 12:45:40.972323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6662 12:45:40.975623 [CA 0] Center 36 (8~64) winsize 57
6663 12:45:40.979041 [CA 1] Center 36 (8~64) winsize 57
6664 12:45:40.982639 [CA 2] Center 36 (8~64) winsize 57
6665 12:45:40.985867 [CA 3] Center 36 (8~64) winsize 57
6666 12:45:40.989112 [CA 4] Center 36 (8~64) winsize 57
6667 12:45:40.992329 [CA 5] Center 36 (8~64) winsize 57
6668 12:45:40.992925
6669 12:45:40.995642 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6670 12:45:40.996212
6671 12:45:40.998694 [CATrainingPosCal] consider 2 rank data
6672 12:45:41.002068 u2DelayCellTimex100 = 270/100 ps
6673 12:45:41.005146 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 12:45:41.012048 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 12:45:41.015565 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 12:45:41.019171 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 12:45:41.022441 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 12:45:41.025521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 12:45:41.026008
6680 12:45:41.028943 CA PerBit enable=1, Macro0, CA PI delay=36
6681 12:45:41.029517
6682 12:45:41.032119 [CBTSetCACLKResult] CA Dly = 36
6683 12:45:41.032744 CS Dly: 1 (0~32)
6684 12:45:41.035120
6685 12:45:41.038523 ----->DramcWriteLeveling(PI) begin...
6686 12:45:41.038994 ==
6687 12:45:41.041479 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 12:45:41.045460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 12:45:41.046035 ==
6690 12:45:41.048582 Write leveling (Byte 0): 40 => 8
6691 12:45:41.051747 Write leveling (Byte 1): 40 => 8
6692 12:45:41.054833 DramcWriteLeveling(PI) end<-----
6693 12:45:41.055416
6694 12:45:41.055908 ==
6695 12:45:41.058468 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 12:45:41.061143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 12:45:41.061640 ==
6698 12:45:41.064663 [Gating] SW mode calibration
6699 12:45:41.071031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6700 12:45:41.078219 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6701 12:45:41.081332 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6702 12:45:41.084216 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 12:45:41.091280 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 12:45:41.094603 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 12:45:41.097970 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6706 12:45:41.104959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 12:45:41.107382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 12:45:41.111202 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 12:45:41.117765 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 12:45:41.118351 Total UI for P1: 0, mck2ui 16
6711 12:45:41.124337 best dqsien dly found for B0: ( 0, 14, 24)
6712 12:45:41.125038 Total UI for P1: 0, mck2ui 16
6713 12:45:41.131047 best dqsien dly found for B1: ( 0, 14, 24)
6714 12:45:41.134690 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6715 12:45:41.137462 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6716 12:45:41.137946
6717 12:45:41.140575 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6718 12:45:41.144183 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 12:45:41.147248 [Gating] SW calibration Done
6720 12:45:41.147824 ==
6721 12:45:41.150518 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 12:45:41.153489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 12:45:41.153974 ==
6724 12:45:41.157072 RX Vref Scan: 0
6725 12:45:41.157552
6726 12:45:41.159910 RX Vref 0 -> 0, step: 1
6727 12:45:41.160389
6728 12:45:41.160910 RX Delay -410 -> 252, step: 16
6729 12:45:41.167229 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6730 12:45:41.170206 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6731 12:45:41.173475 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6732 12:45:41.176647 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6733 12:45:41.183488 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6734 12:45:41.186427 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6735 12:45:41.189645 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6736 12:45:41.197195 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6737 12:45:41.199773 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6738 12:45:41.203490 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6739 12:45:41.206328 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6740 12:45:41.213062 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6741 12:45:41.216734 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6742 12:45:41.219663 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6743 12:45:41.223270 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6744 12:45:41.229881 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6745 12:45:41.230455 ==
6746 12:45:41.232615 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 12:45:41.236634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 12:45:41.237211 ==
6749 12:45:41.237699 DQS Delay:
6750 12:45:41.239913 DQS0 = 43, DQS1 = 51
6751 12:45:41.240392 DQM Delay:
6752 12:45:41.243122 DQM0 = 12, DQM1 = 14
6753 12:45:41.243694 DQ Delay:
6754 12:45:41.245969 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6755 12:45:41.249453 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6756 12:45:41.252703 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6757 12:45:41.256115 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6758 12:45:41.256740
6759 12:45:41.257233
6760 12:45:41.257689 ==
6761 12:45:41.259793 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 12:45:41.263069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 12:45:41.263642 ==
6764 12:45:41.264134
6765 12:45:41.265615
6766 12:45:41.266091 TX Vref Scan disable
6767 12:45:41.269083 == TX Byte 0 ==
6768 12:45:41.272792 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 12:45:41.276315 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 12:45:41.279602 == TX Byte 1 ==
6771 12:45:41.283379 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 12:45:41.285560 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 12:45:41.286074 ==
6774 12:45:41.288857 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 12:45:41.291878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 12:45:41.295738 ==
6777 12:45:41.296214
6778 12:45:41.296774
6779 12:45:41.297233 TX Vref Scan disable
6780 12:45:41.298539 == TX Byte 0 ==
6781 12:45:41.301990 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 12:45:41.306161 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 12:45:41.308279 == TX Byte 1 ==
6784 12:45:41.312479 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 12:45:41.315950 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 12:45:41.316433
6787 12:45:41.318999 [DATLAT]
6788 12:45:41.319570 Freq=400, CH1 RK0
6789 12:45:41.320056
6790 12:45:41.321522 DATLAT Default: 0xf
6791 12:45:41.322003 0, 0xFFFF, sum = 0
6792 12:45:41.325507 1, 0xFFFF, sum = 0
6793 12:45:41.325996 2, 0xFFFF, sum = 0
6794 12:45:41.328207 3, 0xFFFF, sum = 0
6795 12:45:41.328729 4, 0xFFFF, sum = 0
6796 12:45:41.331620 5, 0xFFFF, sum = 0
6797 12:45:41.332107 6, 0xFFFF, sum = 0
6798 12:45:41.335478 7, 0xFFFF, sum = 0
6799 12:45:41.336062 8, 0xFFFF, sum = 0
6800 12:45:41.338219 9, 0xFFFF, sum = 0
6801 12:45:41.338710 10, 0xFFFF, sum = 0
6802 12:45:41.341586 11, 0xFFFF, sum = 0
6803 12:45:41.345139 12, 0xFFFF, sum = 0
6804 12:45:41.345729 13, 0x0, sum = 1
6805 12:45:41.346223 14, 0x0, sum = 2
6806 12:45:41.348130 15, 0x0, sum = 3
6807 12:45:41.348785 16, 0x0, sum = 4
6808 12:45:41.351295 best_step = 14
6809 12:45:41.351775
6810 12:45:41.352268 ==
6811 12:45:41.354773 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 12:45:41.357986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 12:45:41.358472 ==
6814 12:45:41.361785 RX Vref Scan: 1
6815 12:45:41.362362
6816 12:45:41.362849 RX Vref 0 -> 0, step: 1
6817 12:45:41.364891
6818 12:45:41.365466 RX Delay -343 -> 252, step: 8
6819 12:45:41.365955
6820 12:45:41.368257 Set Vref, RX VrefLevel [Byte0]: 46
6821 12:45:41.371694 [Byte1]: 52
6822 12:45:41.376548
6823 12:45:41.377126 Final RX Vref Byte 0 = 46 to rank0
6824 12:45:41.380244 Final RX Vref Byte 1 = 52 to rank0
6825 12:45:41.383046 Final RX Vref Byte 0 = 46 to rank1
6826 12:45:41.385847 Final RX Vref Byte 1 = 52 to rank1==
6827 12:45:41.389560 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 12:45:41.396365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 12:45:41.397004 ==
6830 12:45:41.397494 DQS Delay:
6831 12:45:41.400155 DQS0 = 44, DQS1 = 56
6832 12:45:41.400903 DQM Delay:
6833 12:45:41.401393 DQM0 = 8, DQM1 = 12
6834 12:45:41.402744 DQ Delay:
6835 12:45:41.405969 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6836 12:45:41.406452 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6837 12:45:41.409086 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6838 12:45:41.412654 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6839 12:45:41.413348
6840 12:45:41.416095
6841 12:45:41.422433 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f66, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6842 12:45:41.425631 CH1 RK0: MR19=C0C, MR18=8F66
6843 12:45:41.432499 CH1_RK0: MR19=0xC0C, MR18=0x8F66, DQSOSC=391, MR23=63, INC=386, DEC=257
6844 12:45:41.433016 ==
6845 12:45:41.435873 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 12:45:41.438860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 12:45:41.439444 ==
6848 12:45:41.442945 [Gating] SW mode calibration
6849 12:45:41.448674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6850 12:45:41.455520 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6851 12:45:41.458442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6852 12:45:41.462137 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 12:45:41.468396 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 12:45:41.471960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 12:45:41.475605 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6856 12:45:41.482144 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 12:45:41.484706 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 12:45:41.488629 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 12:45:41.494987 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 12:45:41.495550 Total UI for P1: 0, mck2ui 16
6861 12:45:41.501902 best dqsien dly found for B0: ( 0, 14, 24)
6862 12:45:41.502466 Total UI for P1: 0, mck2ui 16
6863 12:45:41.508104 best dqsien dly found for B1: ( 0, 14, 24)
6864 12:45:41.511572 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6865 12:45:41.514502 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6866 12:45:41.514980
6867 12:45:41.517731 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6868 12:45:41.521102 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 12:45:41.524351 [Gating] SW calibration Done
6870 12:45:41.524855 ==
6871 12:45:41.527954 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 12:45:41.531142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 12:45:41.531652 ==
6874 12:45:41.534927 RX Vref Scan: 0
6875 12:45:41.535553
6876 12:45:41.535924 RX Vref 0 -> 0, step: 1
6877 12:45:41.538182
6878 12:45:41.538640 RX Delay -410 -> 252, step: 16
6879 12:45:41.544190 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6880 12:45:41.547609 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6881 12:45:41.551448 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6882 12:45:41.554789 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6883 12:45:41.561073 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6884 12:45:41.564960 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6885 12:45:41.567556 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6886 12:45:41.570939 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6887 12:45:41.577569 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6888 12:45:41.580648 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6889 12:45:41.584294 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6890 12:45:41.590692 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6891 12:45:41.594181 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6892 12:45:41.597628 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6893 12:45:41.600828 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6894 12:45:41.607326 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6895 12:45:41.607904 ==
6896 12:45:41.610555 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 12:45:41.613522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 12:45:41.614017 ==
6899 12:45:41.614395 DQS Delay:
6900 12:45:41.617030 DQS0 = 51, DQS1 = 51
6901 12:45:41.617498 DQM Delay:
6902 12:45:41.620510 DQM0 = 20, DQM1 = 14
6903 12:45:41.621131 DQ Delay:
6904 12:45:41.623198 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6905 12:45:41.627360 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6906 12:45:41.630141 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6907 12:45:41.633390 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6908 12:45:41.633872
6909 12:45:41.634245
6910 12:45:41.634588 ==
6911 12:45:41.636670 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 12:45:41.640382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 12:45:41.640902 ==
6914 12:45:41.643114
6915 12:45:41.643578
6916 12:45:41.644030 TX Vref Scan disable
6917 12:45:41.646395 == TX Byte 0 ==
6918 12:45:41.650398 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6919 12:45:41.653057 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6920 12:45:41.656598 == TX Byte 1 ==
6921 12:45:41.660085 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6922 12:45:41.663118 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6923 12:45:41.663691 ==
6924 12:45:41.666464 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 12:45:41.669792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 12:45:41.673873 ==
6927 12:45:41.674440
6928 12:45:41.674812
6929 12:45:41.675153 TX Vref Scan disable
6930 12:45:41.677196 == TX Byte 0 ==
6931 12:45:41.679975 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6932 12:45:41.683074 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6933 12:45:41.686069 == TX Byte 1 ==
6934 12:45:41.689489 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6935 12:45:41.692849 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6936 12:45:41.693424
6937 12:45:41.696488 [DATLAT]
6938 12:45:41.697086 Freq=400, CH1 RK1
6939 12:45:41.697463
6940 12:45:41.699989 DATLAT Default: 0xe
6941 12:45:41.700598 0, 0xFFFF, sum = 0
6942 12:45:41.703202 1, 0xFFFF, sum = 0
6943 12:45:41.703783 2, 0xFFFF, sum = 0
6944 12:45:41.706021 3, 0xFFFF, sum = 0
6945 12:45:41.706603 4, 0xFFFF, sum = 0
6946 12:45:41.709924 5, 0xFFFF, sum = 0
6947 12:45:41.710503 6, 0xFFFF, sum = 0
6948 12:45:41.713090 7, 0xFFFF, sum = 0
6949 12:45:41.713666 8, 0xFFFF, sum = 0
6950 12:45:41.715848 9, 0xFFFF, sum = 0
6951 12:45:41.716340 10, 0xFFFF, sum = 0
6952 12:45:41.719769 11, 0xFFFF, sum = 0
6953 12:45:41.722886 12, 0xFFFF, sum = 0
6954 12:45:41.723364 13, 0x0, sum = 1
6955 12:45:41.723745 14, 0x0, sum = 2
6956 12:45:41.726108 15, 0x0, sum = 3
6957 12:45:41.726678 16, 0x0, sum = 4
6958 12:45:41.728918 best_step = 14
6959 12:45:41.729387
6960 12:45:41.729757 ==
6961 12:45:41.732291 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 12:45:41.735729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 12:45:41.736294 ==
6964 12:45:41.738638 RX Vref Scan: 0
6965 12:45:41.739105
6966 12:45:41.739474 RX Vref 0 -> 0, step: 1
6967 12:45:41.742422
6968 12:45:41.742890 RX Delay -343 -> 252, step: 8
6969 12:45:41.751098 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6970 12:45:41.753835 iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480
6971 12:45:41.756840 iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480
6972 12:45:41.763788 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6973 12:45:41.767189 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6974 12:45:41.771084 iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480
6975 12:45:41.774220 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6976 12:45:41.780681 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6977 12:45:41.783992 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6978 12:45:41.786844 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6979 12:45:41.790490 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6980 12:45:41.796930 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6981 12:45:41.800277 iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504
6982 12:45:41.803472 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6983 12:45:41.807547 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6984 12:45:41.813586 iDelay=217, Bit 15, Center -36 (-287 ~ 216) 504
6985 12:45:41.814150 ==
6986 12:45:41.816680 Dram Type= 6, Freq= 0, CH_1, rank 1
6987 12:45:41.820089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6988 12:45:41.820710 ==
6989 12:45:41.821091 DQS Delay:
6990 12:45:41.823223 DQS0 = 48, DQS1 = 56
6991 12:45:41.823785 DQM Delay:
6992 12:45:41.826666 DQM0 = 12, DQM1 = 10
6993 12:45:41.827228 DQ Delay:
6994 12:45:41.829912 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6995 12:45:41.833096 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6996 12:45:41.837369 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6997 12:45:41.839686 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6998 12:45:41.840156
6999 12:45:41.840569
7000 12:45:41.846262 [DQSOSCAuto] RK1, (LSB)MR18= 0x6353, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7001 12:45:41.851268 CH1 RK1: MR19=C0C, MR18=6353
7002 12:45:41.856664 CH1_RK1: MR19=0xC0C, MR18=0x6353, DQSOSC=397, MR23=63, INC=374, DEC=249
7003 12:45:41.860277 [RxdqsGatingPostProcess] freq 400
7004 12:45:41.866026 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7005 12:45:41.869438 best DQS0 dly(2T, 0.5T) = (0, 10)
7006 12:45:41.873138 best DQS1 dly(2T, 0.5T) = (0, 10)
7007 12:45:41.875775 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7008 12:45:41.879987 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7009 12:45:41.880603 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 12:45:41.882459 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 12:45:41.886468 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 12:45:41.888936 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 12:45:41.892874 Pre-setting of DQS Precalculation
7014 12:45:41.899711 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7015 12:45:41.905745 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7016 12:45:41.912588 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7017 12:45:41.913163
7018 12:45:41.913534
7019 12:45:41.915357 [Calibration Summary] 800 Mbps
7020 12:45:41.919260 CH 0, Rank 0
7021 12:45:41.919727 SW Impedance : PASS
7022 12:45:41.922226 DUTY Scan : NO K
7023 12:45:41.922693 ZQ Calibration : PASS
7024 12:45:41.925581 Jitter Meter : NO K
7025 12:45:41.928934 CBT Training : PASS
7026 12:45:41.929403 Write leveling : PASS
7027 12:45:41.932348 RX DQS gating : PASS
7028 12:45:41.935473 RX DQ/DQS(RDDQC) : PASS
7029 12:45:41.936036 TX DQ/DQS : PASS
7030 12:45:41.938766 RX DATLAT : PASS
7031 12:45:41.942361 RX DQ/DQS(Engine): PASS
7032 12:45:41.942826 TX OE : NO K
7033 12:45:41.945372 All Pass.
7034 12:45:41.945837
7035 12:45:41.946209 CH 0, Rank 1
7036 12:45:41.948842 SW Impedance : PASS
7037 12:45:41.949311 DUTY Scan : NO K
7038 12:45:41.952193 ZQ Calibration : PASS
7039 12:45:41.955184 Jitter Meter : NO K
7040 12:45:41.955652 CBT Training : PASS
7041 12:45:41.958636 Write leveling : NO K
7042 12:45:41.961552 RX DQS gating : PASS
7043 12:45:41.962018 RX DQ/DQS(RDDQC) : PASS
7044 12:45:41.965232 TX DQ/DQS : PASS
7045 12:45:41.968394 RX DATLAT : PASS
7046 12:45:41.968925 RX DQ/DQS(Engine): PASS
7047 12:45:41.971618 TX OE : NO K
7048 12:45:41.972089 All Pass.
7049 12:45:41.972458
7050 12:45:41.975140 CH 1, Rank 0
7051 12:45:41.975605 SW Impedance : PASS
7052 12:45:41.978043 DUTY Scan : NO K
7053 12:45:41.981104 ZQ Calibration : PASS
7054 12:45:41.981529 Jitter Meter : NO K
7055 12:45:41.984755 CBT Training : PASS
7056 12:45:41.988139 Write leveling : PASS
7057 12:45:41.988692 RX DQS gating : PASS
7058 12:45:41.991457 RX DQ/DQS(RDDQC) : PASS
7059 12:45:41.991881 TX DQ/DQS : PASS
7060 12:45:41.994906 RX DATLAT : PASS
7061 12:45:41.998494 RX DQ/DQS(Engine): PASS
7062 12:45:41.999011 TX OE : NO K
7063 12:45:42.001165 All Pass.
7064 12:45:42.001587
7065 12:45:42.001926 CH 1, Rank 1
7066 12:45:42.004797 SW Impedance : PASS
7067 12:45:42.005318 DUTY Scan : NO K
7068 12:45:42.007722 ZQ Calibration : PASS
7069 12:45:42.011359 Jitter Meter : NO K
7070 12:45:42.011878 CBT Training : PASS
7071 12:45:42.014765 Write leveling : NO K
7072 12:45:42.018340 RX DQS gating : PASS
7073 12:45:42.018917 RX DQ/DQS(RDDQC) : PASS
7074 12:45:42.021745 TX DQ/DQS : PASS
7075 12:45:42.024916 RX DATLAT : PASS
7076 12:45:42.025436 RX DQ/DQS(Engine): PASS
7077 12:45:42.027660 TX OE : NO K
7078 12:45:42.028089 All Pass.
7079 12:45:42.028423
7080 12:45:42.031139 DramC Write-DBI off
7081 12:45:42.034250 PER_BANK_REFRESH: Hybrid Mode
7082 12:45:42.034672 TX_TRACKING: ON
7083 12:45:42.044675 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7084 12:45:42.047370 [FAST_K] Save calibration result to emmc
7085 12:45:42.050883 dramc_set_vcore_voltage set vcore to 725000
7086 12:45:42.054284 Read voltage for 1600, 0
7087 12:45:42.054751 Vio18 = 0
7088 12:45:42.055119 Vcore = 725000
7089 12:45:42.057162 Vdram = 0
7090 12:45:42.057734 Vddq = 0
7091 12:45:42.058112 Vmddr = 0
7092 12:45:42.063541 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7093 12:45:42.070528 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7094 12:45:42.071102 MEM_TYPE=3, freq_sel=13
7095 12:45:42.073752 sv_algorithm_assistance_LP4_3733
7096 12:45:42.076745 ============ PULL DRAM RESETB DOWN ============
7097 12:45:42.083566 ========== PULL DRAM RESETB DOWN end =========
7098 12:45:42.087045 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7099 12:45:42.089761 ===================================
7100 12:45:42.093318 LPDDR4 DRAM CONFIGURATION
7101 12:45:42.096269 ===================================
7102 12:45:42.096762 EX_ROW_EN[0] = 0x0
7103 12:45:42.099904 EX_ROW_EN[1] = 0x0
7104 12:45:42.100474 LP4Y_EN = 0x0
7105 12:45:42.103167 WORK_FSP = 0x1
7106 12:45:42.106648 WL = 0x5
7107 12:45:42.107223 RL = 0x5
7108 12:45:42.109428 BL = 0x2
7109 12:45:42.109895 RPST = 0x0
7110 12:45:42.113120 RD_PRE = 0x0
7111 12:45:42.113589 WR_PRE = 0x1
7112 12:45:42.116034 WR_PST = 0x1
7113 12:45:42.116501 DBI_WR = 0x0
7114 12:45:42.119659 DBI_RD = 0x0
7115 12:45:42.120126 OTF = 0x1
7116 12:45:42.123116 ===================================
7117 12:45:42.126593 ===================================
7118 12:45:42.129408 ANA top config
7119 12:45:42.132874 ===================================
7120 12:45:42.133444 DLL_ASYNC_EN = 0
7121 12:45:42.136220 ALL_SLAVE_EN = 0
7122 12:45:42.138964 NEW_RANK_MODE = 1
7123 12:45:42.142188 DLL_IDLE_MODE = 1
7124 12:45:42.145919 LP45_APHY_COMB_EN = 1
7125 12:45:42.146388 TX_ODT_DIS = 0
7126 12:45:42.149042 NEW_8X_MODE = 1
7127 12:45:42.152806 ===================================
7128 12:45:42.155400 ===================================
7129 12:45:42.159367 data_rate = 3200
7130 12:45:42.162222 CKR = 1
7131 12:45:42.165292 DQ_P2S_RATIO = 8
7132 12:45:42.169085 ===================================
7133 12:45:42.172898 CA_P2S_RATIO = 8
7134 12:45:42.173463 DQ_CA_OPEN = 0
7135 12:45:42.176472 DQ_SEMI_OPEN = 0
7136 12:45:42.178662 CA_SEMI_OPEN = 0
7137 12:45:42.182640 CA_FULL_RATE = 0
7138 12:45:42.185859 DQ_CKDIV4_EN = 0
7139 12:45:42.188666 CA_CKDIV4_EN = 0
7140 12:45:42.189222 CA_PREDIV_EN = 0
7141 12:45:42.192044 PH8_DLY = 12
7142 12:45:42.195033 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7143 12:45:42.198459 DQ_AAMCK_DIV = 4
7144 12:45:42.202055 CA_AAMCK_DIV = 4
7145 12:45:42.205113 CA_ADMCK_DIV = 4
7146 12:45:42.205681 DQ_TRACK_CA_EN = 0
7147 12:45:42.208395 CA_PICK = 1600
7148 12:45:42.211927 CA_MCKIO = 1600
7149 12:45:42.214930 MCKIO_SEMI = 0
7150 12:45:42.218648 PLL_FREQ = 3068
7151 12:45:42.222402 DQ_UI_PI_RATIO = 32
7152 12:45:42.224768 CA_UI_PI_RATIO = 0
7153 12:45:42.227996 ===================================
7154 12:45:42.231286 ===================================
7155 12:45:42.234906 memory_type:LPDDR4
7156 12:45:42.235467 GP_NUM : 10
7157 12:45:42.238056 SRAM_EN : 1
7158 12:45:42.238524 MD32_EN : 0
7159 12:45:42.241456 ===================================
7160 12:45:42.244593 [ANA_INIT] >>>>>>>>>>>>>>
7161 12:45:42.248296 <<<<<< [CONFIGURE PHASE]: ANA_TX
7162 12:45:42.251955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7163 12:45:42.254678 ===================================
7164 12:45:42.257922 data_rate = 3200,PCW = 0X7600
7165 12:45:42.261315 ===================================
7166 12:45:42.264125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7167 12:45:42.270917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7168 12:45:42.274064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 12:45:42.280835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7170 12:45:42.284475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7171 12:45:42.287950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7172 12:45:42.288550 [ANA_INIT] flow start
7173 12:45:42.290960 [ANA_INIT] PLL >>>>>>>>
7174 12:45:42.294304 [ANA_INIT] PLL <<<<<<<<
7175 12:45:42.294868 [ANA_INIT] MIDPI >>>>>>>>
7176 12:45:42.296964 [ANA_INIT] MIDPI <<<<<<<<
7177 12:45:42.301203 [ANA_INIT] DLL >>>>>>>>
7178 12:45:42.304253 [ANA_INIT] DLL <<<<<<<<
7179 12:45:42.304866 [ANA_INIT] flow end
7180 12:45:42.307049 ============ LP4 DIFF to SE enter ============
7181 12:45:42.313758 ============ LP4 DIFF to SE exit ============
7182 12:45:42.314231 [ANA_INIT] <<<<<<<<<<<<<
7183 12:45:42.316896 [Flow] Enable top DCM control >>>>>
7184 12:45:42.320120 [Flow] Enable top DCM control <<<<<
7185 12:45:42.323196 Enable DLL master slave shuffle
7186 12:45:42.329971 ==============================================================
7187 12:45:42.330536 Gating Mode config
7188 12:45:42.336762 ==============================================================
7189 12:45:42.340132 Config description:
7190 12:45:42.350091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7191 12:45:42.357199 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7192 12:45:42.359908 SELPH_MODE 0: By rank 1: By Phase
7193 12:45:42.366730 ==============================================================
7194 12:45:42.369609 GAT_TRACK_EN = 1
7195 12:45:42.373128 RX_GATING_MODE = 2
7196 12:45:42.373690 RX_GATING_TRACK_MODE = 2
7197 12:45:42.377479 SELPH_MODE = 1
7198 12:45:42.379771 PICG_EARLY_EN = 1
7199 12:45:42.383183 VALID_LAT_VALUE = 1
7200 12:45:42.390188 ==============================================================
7201 12:45:42.393886 Enter into Gating configuration >>>>
7202 12:45:42.396293 Exit from Gating configuration <<<<
7203 12:45:42.399842 Enter into DVFS_PRE_config >>>>>
7204 12:45:42.409942 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7205 12:45:42.413022 Exit from DVFS_PRE_config <<<<<
7206 12:45:42.416763 Enter into PICG configuration >>>>
7207 12:45:42.419188 Exit from PICG configuration <<<<
7208 12:45:42.422892 [RX_INPUT] configuration >>>>>
7209 12:45:42.426173 [RX_INPUT] configuration <<<<<
7210 12:45:42.429841 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7211 12:45:42.435963 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7212 12:45:42.443126 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7213 12:45:42.449653 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7214 12:45:42.455507 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7215 12:45:42.459426 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7216 12:45:42.466061 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7217 12:45:42.468646 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7218 12:45:42.472224 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7219 12:45:42.475909 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7220 12:45:42.482537 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7221 12:45:42.486018 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7222 12:45:42.488758 ===================================
7223 12:45:42.491584 LPDDR4 DRAM CONFIGURATION
7224 12:45:42.495894 ===================================
7225 12:45:42.496471 EX_ROW_EN[0] = 0x0
7226 12:45:42.498544 EX_ROW_EN[1] = 0x0
7227 12:45:42.499008 LP4Y_EN = 0x0
7228 12:45:42.502448 WORK_FSP = 0x1
7229 12:45:42.505092 WL = 0x5
7230 12:45:42.505552 RL = 0x5
7231 12:45:42.508950 BL = 0x2
7232 12:45:42.509520 RPST = 0x0
7233 12:45:42.511603 RD_PRE = 0x0
7234 12:45:42.512090 WR_PRE = 0x1
7235 12:45:42.514698 WR_PST = 0x1
7236 12:45:42.515153 DBI_WR = 0x0
7237 12:45:42.518140 DBI_RD = 0x0
7238 12:45:42.518616 OTF = 0x1
7239 12:45:42.521252 ===================================
7240 12:45:42.525142 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7241 12:45:42.531233 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7242 12:45:42.534479 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 12:45:42.538149 ===================================
7244 12:45:42.541762 LPDDR4 DRAM CONFIGURATION
7245 12:45:42.545391 ===================================
7246 12:45:42.545968 EX_ROW_EN[0] = 0x10
7247 12:45:42.548238 EX_ROW_EN[1] = 0x0
7248 12:45:42.548756 LP4Y_EN = 0x0
7249 12:45:42.550972 WORK_FSP = 0x1
7250 12:45:42.551445 WL = 0x5
7251 12:45:42.554528 RL = 0x5
7252 12:45:42.558383 BL = 0x2
7253 12:45:42.558956 RPST = 0x0
7254 12:45:42.561497 RD_PRE = 0x0
7255 12:45:42.562070 WR_PRE = 0x1
7256 12:45:42.564382 WR_PST = 0x1
7257 12:45:42.564903 DBI_WR = 0x0
7258 12:45:42.567983 DBI_RD = 0x0
7259 12:45:42.568455 OTF = 0x1
7260 12:45:42.571154 ===================================
7261 12:45:42.578270 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7262 12:45:42.578846 ==
7263 12:45:42.580885 Dram Type= 6, Freq= 0, CH_0, rank 0
7264 12:45:42.584672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7265 12:45:42.585239 ==
7266 12:45:42.587785 [Duty_Offset_Calibration]
7267 12:45:42.591390 B0:1 B1:-1 CA:1
7268 12:45:42.591963
7269 12:45:42.594019 [DutyScan_Calibration_Flow] k_type=0
7270 12:45:42.602798
7271 12:45:42.603375 ==CLK 0==
7272 12:45:42.606063 Final CLK duty delay cell = 0
7273 12:45:42.609352 [0] MAX Duty = 5156%(X100), DQS PI = 22
7274 12:45:42.613156 [0] MIN Duty = 4907%(X100), DQS PI = 6
7275 12:45:42.613729 [0] AVG Duty = 5031%(X100)
7276 12:45:42.616141
7277 12:45:42.619381 CH0 CLK Duty spec in!! Max-Min= 249%
7278 12:45:42.622265 [DutyScan_Calibration_Flow] ====Done====
7279 12:45:42.622723
7280 12:45:42.625807 [DutyScan_Calibration_Flow] k_type=1
7281 12:45:42.641750
7282 12:45:42.642308 ==DQS 0 ==
7283 12:45:42.645139 Final DQS duty delay cell = -4
7284 12:45:42.648503 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7285 12:45:42.651955 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7286 12:45:42.655080 [-4] AVG Duty = 4906%(X100)
7287 12:45:42.655693
7288 12:45:42.656067 ==DQS 1 ==
7289 12:45:42.658663 Final DQS duty delay cell = 0
7290 12:45:42.661744 [0] MAX Duty = 5187%(X100), DQS PI = 4
7291 12:45:42.665060 [0] MIN Duty = 5031%(X100), DQS PI = 20
7292 12:45:42.668251 [0] AVG Duty = 5109%(X100)
7293 12:45:42.668743
7294 12:45:42.671935 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7295 12:45:42.672387
7296 12:45:42.675137 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7297 12:45:42.678173 [DutyScan_Calibration_Flow] ====Done====
7298 12:45:42.678584
7299 12:45:42.681289 [DutyScan_Calibration_Flow] k_type=3
7300 12:45:42.699261
7301 12:45:42.699765 ==DQM 0 ==
7302 12:45:42.703057 Final DQM duty delay cell = 0
7303 12:45:42.705671 [0] MAX Duty = 5124%(X100), DQS PI = 24
7304 12:45:42.709139 [0] MIN Duty = 4907%(X100), DQS PI = 8
7305 12:45:42.712483 [0] AVG Duty = 5015%(X100)
7306 12:45:42.712941
7307 12:45:42.713267 ==DQM 1 ==
7308 12:45:42.715769 Final DQM duty delay cell = 0
7309 12:45:42.719952 [0] MAX Duty = 5000%(X100), DQS PI = 4
7310 12:45:42.722345 [0] MIN Duty = 4782%(X100), DQS PI = 22
7311 12:45:42.725629 [0] AVG Duty = 4891%(X100)
7312 12:45:42.726081
7313 12:45:42.729667 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7314 12:45:42.730142
7315 12:45:42.732183 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7316 12:45:42.735857 [DutyScan_Calibration_Flow] ====Done====
7317 12:45:42.736422
7318 12:45:42.738918 [DutyScan_Calibration_Flow] k_type=2
7319 12:45:42.755920
7320 12:45:42.756482 ==DQ 0 ==
7321 12:45:42.759436 Final DQ duty delay cell = -4
7322 12:45:42.762391 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7323 12:45:42.765475 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7324 12:45:42.769053 [-4] AVG Duty = 4953%(X100)
7325 12:45:42.769509
7326 12:45:42.769865 ==DQ 1 ==
7327 12:45:42.771784 Final DQ duty delay cell = 0
7328 12:45:42.775408 [0] MAX Duty = 5125%(X100), DQS PI = 46
7329 12:45:42.778745 [0] MIN Duty = 5000%(X100), DQS PI = 36
7330 12:45:42.781740 [0] AVG Duty = 5062%(X100)
7331 12:45:42.782194
7332 12:45:42.785513 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7333 12:45:42.785965
7334 12:45:42.788913 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7335 12:45:42.792670 [DutyScan_Calibration_Flow] ====Done====
7336 12:45:42.793229 ==
7337 12:45:42.795302 Dram Type= 6, Freq= 0, CH_1, rank 0
7338 12:45:42.799262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7339 12:45:42.799819 ==
7340 12:45:42.801907 [Duty_Offset_Calibration]
7341 12:45:42.802458 B0:-1 B1:1 CA:2
7342 12:45:42.802816
7343 12:45:42.805414 [DutyScan_Calibration_Flow] k_type=0
7344 12:45:42.816592
7345 12:45:42.817144 ==CLK 0==
7346 12:45:42.819498 Final CLK duty delay cell = 0
7347 12:45:42.822958 [0] MAX Duty = 5187%(X100), DQS PI = 24
7348 12:45:42.826336 [0] MIN Duty = 5000%(X100), DQS PI = 0
7349 12:45:42.826788 [0] AVG Duty = 5093%(X100)
7350 12:45:42.829258
7351 12:45:42.832987 CH1 CLK Duty spec in!! Max-Min= 187%
7352 12:45:42.836311 [DutyScan_Calibration_Flow] ====Done====
7353 12:45:42.836927
7354 12:45:42.839402 [DutyScan_Calibration_Flow] k_type=1
7355 12:45:42.857027
7356 12:45:42.857576 ==DQS 0 ==
7357 12:45:42.859387 Final DQS duty delay cell = 0
7358 12:45:42.862814 [0] MAX Duty = 5124%(X100), DQS PI = 18
7359 12:45:42.866220 [0] MIN Duty = 4907%(X100), DQS PI = 8
7360 12:45:42.869332 [0] AVG Duty = 5015%(X100)
7361 12:45:42.869786
7362 12:45:42.870139 ==DQS 1 ==
7363 12:45:42.872649 Final DQS duty delay cell = 0
7364 12:45:42.875673 [0] MAX Duty = 5093%(X100), DQS PI = 26
7365 12:45:42.879184 [0] MIN Duty = 4969%(X100), DQS PI = 54
7366 12:45:42.882174 [0] AVG Duty = 5031%(X100)
7367 12:45:42.882626
7368 12:45:42.885211 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7369 12:45:42.885662
7370 12:45:42.889224 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7371 12:45:42.892430 [DutyScan_Calibration_Flow] ====Done====
7372 12:45:42.893030
7373 12:45:42.895772 [DutyScan_Calibration_Flow] k_type=3
7374 12:45:42.912013
7375 12:45:42.912608 ==DQM 0 ==
7376 12:45:42.915578 Final DQM duty delay cell = -4
7377 12:45:42.918495 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7378 12:45:42.922183 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7379 12:45:42.925046 [-4] AVG Duty = 4937%(X100)
7380 12:45:42.925533
7381 12:45:42.925895 ==DQM 1 ==
7382 12:45:42.928397 Final DQM duty delay cell = 0
7383 12:45:42.931814 [0] MAX Duty = 5156%(X100), DQS PI = 0
7384 12:45:42.935031 [0] MIN Duty = 4969%(X100), DQS PI = 28
7385 12:45:42.939452 [0] AVG Duty = 5062%(X100)
7386 12:45:42.940027
7387 12:45:42.941988 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7388 12:45:42.942447
7389 12:45:42.944718 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7390 12:45:42.948546 [DutyScan_Calibration_Flow] ====Done====
7391 12:45:42.949109
7392 12:45:42.951092 [DutyScan_Calibration_Flow] k_type=2
7393 12:45:42.969056
7394 12:45:42.969610 ==DQ 0 ==
7395 12:45:42.972373 Final DQ duty delay cell = 0
7396 12:45:42.975957 [0] MAX Duty = 5156%(X100), DQS PI = 28
7397 12:45:42.978461 [0] MIN Duty = 4906%(X100), DQS PI = 10
7398 12:45:42.982087 [0] AVG Duty = 5031%(X100)
7399 12:45:42.982544
7400 12:45:42.982915 ==DQ 1 ==
7401 12:45:42.985527 Final DQ duty delay cell = 0
7402 12:45:42.989084 [0] MAX Duty = 5156%(X100), DQS PI = 8
7403 12:45:42.992141 [0] MIN Duty = 4969%(X100), DQS PI = 56
7404 12:45:42.992734 [0] AVG Duty = 5062%(X100)
7405 12:45:42.996003
7406 12:45:42.999360 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7407 12:45:42.999934
7408 12:45:43.002063 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7409 12:45:43.005669 [DutyScan_Calibration_Flow] ====Done====
7410 12:45:43.008297 nWR fixed to 30
7411 12:45:43.008805 [ModeRegInit_LP4] CH0 RK0
7412 12:45:43.012005 [ModeRegInit_LP4] CH0 RK1
7413 12:45:43.015326 [ModeRegInit_LP4] CH1 RK0
7414 12:45:43.019075 [ModeRegInit_LP4] CH1 RK1
7415 12:45:43.019646 match AC timing 5
7416 12:45:43.024832 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7417 12:45:43.028611 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7418 12:45:43.031664 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7419 12:45:43.038444 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7420 12:45:43.041612 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7421 12:45:43.042087 [MiockJmeterHQA]
7422 12:45:43.042607
7423 12:45:43.045019 [DramcMiockJmeter] u1RxGatingPI = 0
7424 12:45:43.048860 0 : 4253, 4026
7425 12:45:43.049442 4 : 4363, 4137
7426 12:45:43.052250 8 : 4258, 4029
7427 12:45:43.052886 12 : 4368, 4140
7428 12:45:43.053273 16 : 4368, 4140
7429 12:45:43.055575 20 : 4255, 4030
7430 12:45:43.056055 24 : 4253, 4026
7431 12:45:43.058434 28 : 4257, 4029
7432 12:45:43.058906 32 : 4368, 4140
7433 12:45:43.061233 36 : 4368, 4140
7434 12:45:43.061704 40 : 4365, 4137
7435 12:45:43.065028 44 : 4255, 4027
7436 12:45:43.065600 48 : 4255, 4030
7437 12:45:43.065977 52 : 4257, 4029
7438 12:45:43.068286 56 : 4255, 4029
7439 12:45:43.068946 60 : 4365, 4140
7440 12:45:43.071299 64 : 4254, 4027
7441 12:45:43.071769 68 : 4255, 4029
7442 12:45:43.074690 72 : 4258, 4030
7443 12:45:43.075276 76 : 4257, 4031
7444 12:45:43.077975 80 : 4255, 4030
7445 12:45:43.078406 84 : 4366, 4138
7446 12:45:43.078748 88 : 4366, 4140
7447 12:45:43.081202 92 : 4253, 707
7448 12:45:43.081631 96 : 4255, 0
7449 12:45:43.085000 100 : 4255, 0
7450 12:45:43.085431 104 : 4253, 0
7451 12:45:43.085777 108 : 4360, 0
7452 12:45:43.087838 112 : 4250, 0
7453 12:45:43.088374 116 : 4253, 0
7454 12:45:43.090958 120 : 4250, 0
7455 12:45:43.091389 124 : 4255, 0
7456 12:45:43.091734 128 : 4361, 0
7457 12:45:43.094986 132 : 4361, 0
7458 12:45:43.095525 136 : 4250, 0
7459 12:45:43.098424 140 : 4250, 0
7460 12:45:43.098961 144 : 4361, 0
7461 12:45:43.099311 148 : 4249, 0
7462 12:45:43.100540 152 : 4250, 0
7463 12:45:43.100973 156 : 4255, 0
7464 12:45:43.104305 160 : 4250, 0
7465 12:45:43.104881 164 : 4253, 0
7466 12:45:43.105228 168 : 4250, 0
7467 12:45:43.107275 172 : 4250, 0
7468 12:45:43.107701 176 : 4253, 0
7469 12:45:43.110893 180 : 4361, 0
7470 12:45:43.111322 184 : 4361, 0
7471 12:45:43.111689 188 : 4363, 0
7472 12:45:43.113903 192 : 4250, 0
7473 12:45:43.114440 196 : 4250, 0
7474 12:45:43.118361 200 : 4363, 0
7475 12:45:43.118897 204 : 4250, 0
7476 12:45:43.119244 208 : 4255, 0
7477 12:45:43.120665 212 : 4250, 0
7478 12:45:43.121096 216 : 4253, 0
7479 12:45:43.121434 220 : 4250, 0
7480 12:45:43.124460 224 : 4250, 251
7481 12:45:43.124934 228 : 4250, 3439
7482 12:45:43.127534 232 : 4250, 4027
7483 12:45:43.127961 236 : 4250, 4027
7484 12:45:43.130294 240 : 4363, 4140
7485 12:45:43.130723 244 : 4360, 4137
7486 12:45:43.133873 248 : 4250, 4027
7487 12:45:43.134398 252 : 4250, 4027
7488 12:45:43.137366 256 : 4249, 4027
7489 12:45:43.137894 260 : 4250, 4027
7490 12:45:43.140692 264 : 4253, 4029
7491 12:45:43.141122 268 : 4253, 4029
7492 12:45:43.145176 272 : 4252, 4029
7493 12:45:43.145781 276 : 4363, 4140
7494 12:45:43.146154 280 : 4255, 4029
7495 12:45:43.147104 284 : 4250, 4027
7496 12:45:43.147574 288 : 4250, 4027
7497 12:45:43.150130 292 : 4363, 4140
7498 12:45:43.150600 296 : 4360, 4137
7499 12:45:43.153395 300 : 4250, 4026
7500 12:45:43.153820 304 : 4363, 4140
7501 12:45:43.157127 308 : 4252, 4030
7502 12:45:43.157554 312 : 4250, 4026
7503 12:45:43.161061 316 : 4255, 4029
7504 12:45:43.161695 320 : 4253, 4029
7505 12:45:43.163536 324 : 4250, 4027
7506 12:45:43.164003 328 : 4363, 4140
7507 12:45:43.166628 332 : 4255, 4029
7508 12:45:43.167306 336 : 4250, 3764
7509 12:45:43.170235 340 : 4250, 2047
7510 12:45:43.170700
7511 12:45:43.171064 MIOCK jitter meter ch=0
7512 12:45:43.171408
7513 12:45:43.173152 1T = (340-92) = 248 dly cells
7514 12:45:43.179865 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7515 12:45:43.180373 ==
7516 12:45:43.182934 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 12:45:43.186341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 12:45:43.186809 ==
7519 12:45:43.193075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 12:45:43.196045 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 12:45:43.203329 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 12:45:43.206863 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 12:45:43.216205 [CA 0] Center 43 (13~74) winsize 62
7524 12:45:43.220348 [CA 1] Center 42 (12~73) winsize 62
7525 12:45:43.222734 [CA 2] Center 38 (9~68) winsize 60
7526 12:45:43.226098 [CA 3] Center 38 (8~68) winsize 61
7527 12:45:43.229078 [CA 4] Center 36 (7~66) winsize 60
7528 12:45:43.233095 [CA 5] Center 35 (6~65) winsize 60
7529 12:45:43.233644
7530 12:45:43.235734 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 12:45:43.236199
7532 12:45:43.242387 [CATrainingPosCal] consider 1 rank data
7533 12:45:43.242849 u2DelayCellTimex100 = 262/100 ps
7534 12:45:43.249283 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7535 12:45:43.252765 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7536 12:45:43.255754 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7537 12:45:43.259720 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7538 12:45:43.262331 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7539 12:45:43.265682 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7540 12:45:43.266284
7541 12:45:43.268564 CA PerBit enable=1, Macro0, CA PI delay=35
7542 12:45:43.269050
7543 12:45:43.272396 [CBTSetCACLKResult] CA Dly = 35
7544 12:45:43.275573 CS Dly: 11 (0~42)
7545 12:45:43.279021 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 12:45:43.282026 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 12:45:43.282588 ==
7548 12:45:43.285395 Dram Type= 6, Freq= 0, CH_0, rank 1
7549 12:45:43.292267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 12:45:43.292863 ==
7551 12:45:43.295058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 12:45:43.302285 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 12:45:43.304921 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 12:45:43.312114 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 12:45:43.320204 [CA 0] Center 43 (13~74) winsize 62
7556 12:45:43.323298 [CA 1] Center 44 (14~74) winsize 61
7557 12:45:43.326586 [CA 2] Center 38 (9~68) winsize 60
7558 12:45:43.329747 [CA 3] Center 38 (9~68) winsize 60
7559 12:45:43.332748 [CA 4] Center 36 (7~66) winsize 60
7560 12:45:43.336371 [CA 5] Center 36 (7~66) winsize 60
7561 12:45:43.336969
7562 12:45:43.339324 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 12:45:43.339885
7564 12:45:43.346906 [CATrainingPosCal] consider 2 rank data
7565 12:45:43.347454 u2DelayCellTimex100 = 262/100 ps
7566 12:45:43.352677 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7567 12:45:43.355748 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7568 12:45:43.359857 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7569 12:45:43.362243 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7570 12:45:43.365876 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7571 12:45:43.368804 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7572 12:45:43.369265
7573 12:45:43.372132 CA PerBit enable=1, Macro0, CA PI delay=36
7574 12:45:43.372664
7575 12:45:43.376365 [CBTSetCACLKResult] CA Dly = 36
7576 12:45:43.378919 CS Dly: 11 (0~43)
7577 12:45:43.382845 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 12:45:43.385253 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 12:45:43.385716
7580 12:45:43.389229 ----->DramcWriteLeveling(PI) begin...
7581 12:45:43.389697 ==
7582 12:45:43.392393 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 12:45:43.399423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 12:45:43.399979 ==
7585 12:45:43.402790 Write leveling (Byte 0): 34 => 34
7586 12:45:43.405254 Write leveling (Byte 1): 26 => 26
7587 12:45:43.405712 DramcWriteLeveling(PI) end<-----
7588 12:45:43.406077
7589 12:45:43.409233 ==
7590 12:45:43.412146 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 12:45:43.415348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 12:45:43.415912 ==
7593 12:45:43.418963 [Gating] SW mode calibration
7594 12:45:43.425247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7595 12:45:43.428678 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7596 12:45:43.435256 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 12:45:43.438837 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 12:45:43.441746 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 12:45:43.448464 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7600 12:45:43.451615 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7601 12:45:43.454737 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7602 12:45:43.461731 1 4 24 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7603 12:45:43.464791 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 12:45:43.468128 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 12:45:43.475103 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 12:45:43.478021 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 12:45:43.481424 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7608 12:45:43.489350 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7609 12:45:43.490980 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7610 12:45:43.494581 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7611 12:45:43.500937 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 12:45:43.504142 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 12:45:43.507664 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 12:45:43.514481 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 12:45:43.517714 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7616 12:45:43.521056 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7617 12:45:43.527796 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7618 12:45:43.530878 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7619 12:45:43.533941 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 12:45:43.541085 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 12:45:43.544085 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 12:45:43.547751 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7623 12:45:43.554469 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7624 12:45:43.557295 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7625 12:45:43.560926 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7626 12:45:43.567656 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7627 12:45:43.570245 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:45:43.573939 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:45:43.580673 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:45:43.583731 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 12:45:43.586739 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 12:45:43.593999 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 12:45:43.597143 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 12:45:43.600733 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 12:45:43.606932 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:45:43.610100 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:45:43.613373 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:45:43.620050 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7639 12:45:43.623097 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7640 12:45:43.626629 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7641 12:45:43.633268 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7642 12:45:43.633813 Total UI for P1: 0, mck2ui 16
7643 12:45:43.639661 best dqsien dly found for B0: ( 1, 9, 12)
7644 12:45:43.642865 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 12:45:43.646633 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 12:45:43.649181 Total UI for P1: 0, mck2ui 16
7647 12:45:43.652961 best dqsien dly found for B1: ( 1, 9, 22)
7648 12:45:43.656327 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7649 12:45:43.659923 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7650 12:45:43.660485
7651 12:45:43.666400 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7652 12:45:43.669555 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7653 12:45:43.673154 [Gating] SW calibration Done
7654 12:45:43.673618 ==
7655 12:45:43.676187 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 12:45:43.679482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 12:45:43.680061 ==
7658 12:45:43.680435 RX Vref Scan: 0
7659 12:45:43.680862
7660 12:45:43.683186 RX Vref 0 -> 0, step: 1
7661 12:45:43.683750
7662 12:45:43.685980 RX Delay 0 -> 252, step: 8
7663 12:45:43.689637 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7664 12:45:43.692669 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7665 12:45:43.699417 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7666 12:45:43.702965 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7667 12:45:43.706118 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7668 12:45:43.709315 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7669 12:45:43.712200 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7670 12:45:43.718950 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7671 12:45:43.721964 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7672 12:45:43.725366 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7673 12:45:43.729121 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7674 12:45:43.732549 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7675 12:45:43.738937 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7676 12:45:43.742061 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7677 12:45:43.745672 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7678 12:45:43.749019 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7679 12:45:43.749498 ==
7680 12:45:43.752053 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 12:45:43.758752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 12:45:43.759342 ==
7683 12:45:43.759832 DQS Delay:
7684 12:45:43.761777 DQS0 = 0, DQS1 = 0
7685 12:45:43.762252 DQM Delay:
7686 12:45:43.765104 DQM0 = 134, DQM1 = 126
7687 12:45:43.765686 DQ Delay:
7688 12:45:43.768706 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7689 12:45:43.771357 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =143
7690 12:45:43.775250 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7691 12:45:43.778180 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7692 12:45:43.778750
7693 12:45:43.779118
7694 12:45:43.779459 ==
7695 12:45:43.782183 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 12:45:43.788294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 12:45:43.788900 ==
7698 12:45:43.789280
7699 12:45:43.789625
7700 12:45:43.789955 TX Vref Scan disable
7701 12:45:43.792386 == TX Byte 0 ==
7702 12:45:43.794790 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7703 12:45:43.801768 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7704 12:45:43.802244 == TX Byte 1 ==
7705 12:45:43.804845 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7706 12:45:43.811552 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7707 12:45:43.812121 ==
7708 12:45:43.814803 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 12:45:43.818066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 12:45:43.818528 ==
7711 12:45:43.831237
7712 12:45:43.834509 TX Vref early break, caculate TX vref
7713 12:45:43.837613 TX Vref=16, minBit 7, minWin=22, winSum=370
7714 12:45:43.840953 TX Vref=18, minBit 4, minWin=22, winSum=376
7715 12:45:43.844330 TX Vref=20, minBit 1, minWin=23, winSum=390
7716 12:45:43.847640 TX Vref=22, minBit 1, minWin=24, winSum=397
7717 12:45:43.851100 TX Vref=24, minBit 7, minWin=24, winSum=404
7718 12:45:43.858141 TX Vref=26, minBit 5, minWin=25, winSum=415
7719 12:45:43.860750 TX Vref=28, minBit 4, minWin=25, winSum=418
7720 12:45:43.864442 TX Vref=30, minBit 7, minWin=24, winSum=407
7721 12:45:43.867872 TX Vref=32, minBit 7, minWin=23, winSum=398
7722 12:45:43.870864 TX Vref=34, minBit 1, minWin=23, winSum=390
7723 12:45:43.877133 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
7724 12:45:43.877699
7725 12:45:43.880650 Final TX Range 0 Vref 28
7726 12:45:43.881203
7727 12:45:43.881576 ==
7728 12:45:43.884263 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 12:45:43.887887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 12:45:43.888457 ==
7731 12:45:43.888913
7732 12:45:43.891107
7733 12:45:43.891665 TX Vref Scan disable
7734 12:45:43.897148 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7735 12:45:43.897707 == TX Byte 0 ==
7736 12:45:43.900256 u2DelayCellOfst[0]=14 cells (4 PI)
7737 12:45:43.903639 u2DelayCellOfst[1]=14 cells (4 PI)
7738 12:45:43.907324 u2DelayCellOfst[2]=11 cells (3 PI)
7739 12:45:43.910390 u2DelayCellOfst[3]=11 cells (3 PI)
7740 12:45:43.914184 u2DelayCellOfst[4]=7 cells (2 PI)
7741 12:45:43.916790 u2DelayCellOfst[5]=0 cells (0 PI)
7742 12:45:43.920623 u2DelayCellOfst[6]=18 cells (5 PI)
7743 12:45:43.923156 u2DelayCellOfst[7]=18 cells (5 PI)
7744 12:45:43.926407 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7745 12:45:43.929941 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7746 12:45:43.933180 == TX Byte 1 ==
7747 12:45:43.936349 u2DelayCellOfst[8]=0 cells (0 PI)
7748 12:45:43.939693 u2DelayCellOfst[9]=3 cells (1 PI)
7749 12:45:43.943195 u2DelayCellOfst[10]=7 cells (2 PI)
7750 12:45:43.946223 u2DelayCellOfst[11]=3 cells (1 PI)
7751 12:45:43.950031 u2DelayCellOfst[12]=14 cells (4 PI)
7752 12:45:43.950503 u2DelayCellOfst[13]=14 cells (4 PI)
7753 12:45:43.952691 u2DelayCellOfst[14]=14 cells (4 PI)
7754 12:45:43.956007 u2DelayCellOfst[15]=14 cells (4 PI)
7755 12:45:43.962799 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7756 12:45:43.966419 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7757 12:45:43.969596 DramC Write-DBI on
7758 12:45:43.970159 ==
7759 12:45:43.972588 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 12:45:43.976054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 12:45:43.976693 ==
7762 12:45:43.977083
7763 12:45:43.977430
7764 12:45:43.979819 TX Vref Scan disable
7765 12:45:43.980381 == TX Byte 0 ==
7766 12:45:43.986077 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7767 12:45:43.986643 == TX Byte 1 ==
7768 12:45:43.989353 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7769 12:45:43.992456 DramC Write-DBI off
7770 12:45:43.993064
7771 12:45:43.993437 [DATLAT]
7772 12:45:43.996356 Freq=1600, CH0 RK0
7773 12:45:43.996971
7774 12:45:43.997347 DATLAT Default: 0xf
7775 12:45:43.998777 0, 0xFFFF, sum = 0
7776 12:45:43.999293 1, 0xFFFF, sum = 0
7777 12:45:44.002247 2, 0xFFFF, sum = 0
7778 12:45:44.005580 3, 0xFFFF, sum = 0
7779 12:45:44.006151 4, 0xFFFF, sum = 0
7780 12:45:44.009213 5, 0xFFFF, sum = 0
7781 12:45:44.009782 6, 0xFFFF, sum = 0
7782 12:45:44.013207 7, 0xFFFF, sum = 0
7783 12:45:44.013783 8, 0xFFFF, sum = 0
7784 12:45:44.015816 9, 0xFFFF, sum = 0
7785 12:45:44.016395 10, 0xFFFF, sum = 0
7786 12:45:44.018559 11, 0xFFFF, sum = 0
7787 12:45:44.019032 12, 0xFFFF, sum = 0
7788 12:45:44.021955 13, 0xFFFF, sum = 0
7789 12:45:44.022427 14, 0x0, sum = 1
7790 12:45:44.025137 15, 0x0, sum = 2
7791 12:45:44.025611 16, 0x0, sum = 3
7792 12:45:44.028818 17, 0x0, sum = 4
7793 12:45:44.029292 best_step = 15
7794 12:45:44.029660
7795 12:45:44.030001 ==
7796 12:45:44.031871 Dram Type= 6, Freq= 0, CH_0, rank 0
7797 12:45:44.038398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7798 12:45:44.038870 ==
7799 12:45:44.039241 RX Vref Scan: 1
7800 12:45:44.039585
7801 12:45:44.041679 Set Vref Range= 24 -> 127
7802 12:45:44.042143
7803 12:45:44.045332 RX Vref 24 -> 127, step: 1
7804 12:45:44.045798
7805 12:45:44.046168 RX Delay 11 -> 252, step: 4
7806 12:45:44.046517
7807 12:45:44.048504 Set Vref, RX VrefLevel [Byte0]: 24
7808 12:45:44.052032 [Byte1]: 24
7809 12:45:44.056223
7810 12:45:44.056777 Set Vref, RX VrefLevel [Byte0]: 25
7811 12:45:44.059513 [Byte1]: 25
7812 12:45:44.063612
7813 12:45:44.064154 Set Vref, RX VrefLevel [Byte0]: 26
7814 12:45:44.066503 [Byte1]: 26
7815 12:45:44.071824
7816 12:45:44.072390 Set Vref, RX VrefLevel [Byte0]: 27
7817 12:45:44.074535 [Byte1]: 27
7818 12:45:44.078720
7819 12:45:44.079239 Set Vref, RX VrefLevel [Byte0]: 28
7820 12:45:44.082233 [Byte1]: 28
7821 12:45:44.086681
7822 12:45:44.087199 Set Vref, RX VrefLevel [Byte0]: 29
7823 12:45:44.090083 [Byte1]: 29
7824 12:45:44.094233
7825 12:45:44.094751 Set Vref, RX VrefLevel [Byte0]: 30
7826 12:45:44.097041 [Byte1]: 30
7827 12:45:44.102279
7828 12:45:44.102839 Set Vref, RX VrefLevel [Byte0]: 31
7829 12:45:44.105529 [Byte1]: 31
7830 12:45:44.109425
7831 12:45:44.109987 Set Vref, RX VrefLevel [Byte0]: 32
7832 12:45:44.112769 [Byte1]: 32
7833 12:45:44.117065
7834 12:45:44.117623 Set Vref, RX VrefLevel [Byte0]: 33
7835 12:45:44.120157 [Byte1]: 33
7836 12:45:44.124699
7837 12:45:44.125273 Set Vref, RX VrefLevel [Byte0]: 34
7838 12:45:44.127452 [Byte1]: 34
7839 12:45:44.132009
7840 12:45:44.132618 Set Vref, RX VrefLevel [Byte0]: 35
7841 12:45:44.139458 [Byte1]: 35
7842 12:45:44.139949
7843 12:45:44.141928 Set Vref, RX VrefLevel [Byte0]: 36
7844 12:45:44.145074 [Byte1]: 36
7845 12:45:44.145540
7846 12:45:44.148232 Set Vref, RX VrefLevel [Byte0]: 37
7847 12:45:44.152441 [Byte1]: 37
7848 12:45:44.155108
7849 12:45:44.155665 Set Vref, RX VrefLevel [Byte0]: 38
7850 12:45:44.158003 [Byte1]: 38
7851 12:45:44.162526
7852 12:45:44.163096 Set Vref, RX VrefLevel [Byte0]: 39
7853 12:45:44.165566 [Byte1]: 39
7854 12:45:44.170141
7855 12:45:44.170731 Set Vref, RX VrefLevel [Byte0]: 40
7856 12:45:44.173170 [Byte1]: 40
7857 12:45:44.177509
7858 12:45:44.177970 Set Vref, RX VrefLevel [Byte0]: 41
7859 12:45:44.181436 [Byte1]: 41
7860 12:45:44.185694
7861 12:45:44.186258 Set Vref, RX VrefLevel [Byte0]: 42
7862 12:45:44.189154 [Byte1]: 42
7863 12:45:44.193456
7864 12:45:44.194016 Set Vref, RX VrefLevel [Byte0]: 43
7865 12:45:44.196649 [Byte1]: 43
7866 12:45:44.201065
7867 12:45:44.201631 Set Vref, RX VrefLevel [Byte0]: 44
7868 12:45:44.204019 [Byte1]: 44
7869 12:45:44.208335
7870 12:45:44.208951 Set Vref, RX VrefLevel [Byte0]: 45
7871 12:45:44.211776 [Byte1]: 45
7872 12:45:44.216688
7873 12:45:44.217246 Set Vref, RX VrefLevel [Byte0]: 46
7874 12:45:44.218998 [Byte1]: 46
7875 12:45:44.223424
7876 12:45:44.223988 Set Vref, RX VrefLevel [Byte0]: 47
7877 12:45:44.227222 [Byte1]: 47
7878 12:45:44.230742
7879 12:45:44.231233 Set Vref, RX VrefLevel [Byte0]: 48
7880 12:45:44.237378 [Byte1]: 48
7881 12:45:44.237843
7882 12:45:44.240880 Set Vref, RX VrefLevel [Byte0]: 49
7883 12:45:44.244050 [Byte1]: 49
7884 12:45:44.244683
7885 12:45:44.247699 Set Vref, RX VrefLevel [Byte0]: 50
7886 12:45:44.250677 [Byte1]: 50
7887 12:45:44.254367
7888 12:45:44.254931 Set Vref, RX VrefLevel [Byte0]: 51
7889 12:45:44.257438 [Byte1]: 51
7890 12:45:44.261270
7891 12:45:44.261738 Set Vref, RX VrefLevel [Byte0]: 52
7892 12:45:44.264584 [Byte1]: 52
7893 12:45:44.269484
7894 12:45:44.270051 Set Vref, RX VrefLevel [Byte0]: 53
7895 12:45:44.273003 [Byte1]: 53
7896 12:45:44.276870
7897 12:45:44.277329 Set Vref, RX VrefLevel [Byte0]: 54
7898 12:45:44.279947 [Byte1]: 54
7899 12:45:44.284294
7900 12:45:44.284787 Set Vref, RX VrefLevel [Byte0]: 55
7901 12:45:44.287505 [Byte1]: 55
7902 12:45:44.292322
7903 12:45:44.292941 Set Vref, RX VrefLevel [Byte0]: 56
7904 12:45:44.295574 [Byte1]: 56
7905 12:45:44.300124
7906 12:45:44.300737 Set Vref, RX VrefLevel [Byte0]: 57
7907 12:45:44.303419 [Byte1]: 57
7908 12:45:44.307351
7909 12:45:44.307910 Set Vref, RX VrefLevel [Byte0]: 58
7910 12:45:44.310969 [Byte1]: 58
7911 12:45:44.315519
7912 12:45:44.316088 Set Vref, RX VrefLevel [Byte0]: 59
7913 12:45:44.318445 [Byte1]: 59
7914 12:45:44.322437
7915 12:45:44.323017 Set Vref, RX VrefLevel [Byte0]: 60
7916 12:45:44.325933 [Byte1]: 60
7917 12:45:44.330542
7918 12:45:44.331101 Set Vref, RX VrefLevel [Byte0]: 61
7919 12:45:44.336126 [Byte1]: 61
7920 12:45:44.336625
7921 12:45:44.339879 Set Vref, RX VrefLevel [Byte0]: 62
7922 12:45:44.343103 [Byte1]: 62
7923 12:45:44.343675
7924 12:45:44.346542 Set Vref, RX VrefLevel [Byte0]: 63
7925 12:45:44.350028 [Byte1]: 63
7926 12:45:44.354236
7927 12:45:44.354811 Set Vref, RX VrefLevel [Byte0]: 64
7928 12:45:44.357632 [Byte1]: 64
7929 12:45:44.360701
7930 12:45:44.361167 Set Vref, RX VrefLevel [Byte0]: 65
7931 12:45:44.364086 [Byte1]: 65
7932 12:45:44.368136
7933 12:45:44.368639 Set Vref, RX VrefLevel [Byte0]: 66
7934 12:45:44.371201 [Byte1]: 66
7935 12:45:44.375522
7936 12:45:44.376177 Set Vref, RX VrefLevel [Byte0]: 67
7937 12:45:44.379035 [Byte1]: 67
7938 12:45:44.383015
7939 12:45:44.383579 Set Vref, RX VrefLevel [Byte0]: 68
7940 12:45:44.386377 [Byte1]: 68
7941 12:45:44.390505
7942 12:45:44.390972 Set Vref, RX VrefLevel [Byte0]: 69
7943 12:45:44.394442 [Byte1]: 69
7944 12:45:44.398545
7945 12:45:44.399112 Set Vref, RX VrefLevel [Byte0]: 70
7946 12:45:44.401927 [Byte1]: 70
7947 12:45:44.406884
7948 12:45:44.407451 Set Vref, RX VrefLevel [Byte0]: 71
7949 12:45:44.409790 [Byte1]: 71
7950 12:45:44.414296
7951 12:45:44.414870 Set Vref, RX VrefLevel [Byte0]: 72
7952 12:45:44.417220 [Byte1]: 72
7953 12:45:44.421754
7954 12:45:44.422327 Set Vref, RX VrefLevel [Byte0]: 73
7955 12:45:44.424949 [Byte1]: 73
7956 12:45:44.428826
7957 12:45:44.429394 Set Vref, RX VrefLevel [Byte0]: 74
7958 12:45:44.435474 [Byte1]: 74
7959 12:45:44.436042
7960 12:45:44.438398 Set Vref, RX VrefLevel [Byte0]: 75
7961 12:45:44.441963 [Byte1]: 75
7962 12:45:44.442541
7963 12:45:44.445048 Set Vref, RX VrefLevel [Byte0]: 76
7964 12:45:44.448712 [Byte1]: 76
7965 12:45:44.451823
7966 12:45:44.452384 Set Vref, RX VrefLevel [Byte0]: 77
7967 12:45:44.454910 [Byte1]: 77
7968 12:45:44.459734
7969 12:45:44.460298 Set Vref, RX VrefLevel [Byte0]: 78
7970 12:45:44.462882 [Byte1]: 78
7971 12:45:44.467873
7972 12:45:44.468365 Final RX Vref Byte 0 = 64 to rank0
7973 12:45:44.471237 Final RX Vref Byte 1 = 60 to rank0
7974 12:45:44.474148 Final RX Vref Byte 0 = 64 to rank1
7975 12:45:44.477385 Final RX Vref Byte 1 = 60 to rank1==
7976 12:45:44.480650 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 12:45:44.487321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 12:45:44.487883 ==
7979 12:45:44.488325 DQS Delay:
7980 12:45:44.488716 DQS0 = 0, DQS1 = 0
7981 12:45:44.490093 DQM Delay:
7982 12:45:44.490557 DQM0 = 132, DQM1 = 123
7983 12:45:44.493632 DQ Delay:
7984 12:45:44.496992 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
7985 12:45:44.500064 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
7986 12:45:44.503805 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
7987 12:45:44.506825 DQ12 =130, DQ13 =126, DQ14 =134, DQ15 =128
7988 12:45:44.507397
7989 12:45:44.507768
7990 12:45:44.508113
7991 12:45:44.510196 [DramC_TX_OE_Calibration] TA2
7992 12:45:44.513040 Original DQ_B0 (3 6) =30, OEN = 27
7993 12:45:44.516674 Original DQ_B1 (3 6) =30, OEN = 27
7994 12:45:44.520189 24, 0x0, End_B0=24 End_B1=24
7995 12:45:44.520807 25, 0x0, End_B0=25 End_B1=25
7996 12:45:44.523095 26, 0x0, End_B0=26 End_B1=26
7997 12:45:44.526286 27, 0x0, End_B0=27 End_B1=27
7998 12:45:44.530101 28, 0x0, End_B0=28 End_B1=28
7999 12:45:44.533002 29, 0x0, End_B0=29 End_B1=29
8000 12:45:44.533483 30, 0x0, End_B0=30 End_B1=30
8001 12:45:44.537081 31, 0x4141, End_B0=30 End_B1=30
8002 12:45:44.539426 Byte0 end_step=30 best_step=27
8003 12:45:44.543079 Byte1 end_step=30 best_step=27
8004 12:45:44.545956 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 12:45:44.549551 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 12:45:44.550121
8007 12:45:44.550490
8008 12:45:44.556904 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8009 12:45:44.559197 CH0 RK0: MR19=303, MR18=1F10
8010 12:45:44.565739 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8011 12:45:44.566385
8012 12:45:44.569148 ----->DramcWriteLeveling(PI) begin...
8013 12:45:44.569625 ==
8014 12:45:44.572354 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 12:45:44.575958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 12:45:44.576427 ==
8017 12:45:44.579164 Write leveling (Byte 0): 35 => 35
8018 12:45:44.582430 Write leveling (Byte 1): 29 => 29
8019 12:45:44.585655 DramcWriteLeveling(PI) end<-----
8020 12:45:44.586125
8021 12:45:44.586494 ==
8022 12:45:44.588628 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 12:45:44.595396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 12:45:44.595977 ==
8025 12:45:44.596356 [Gating] SW mode calibration
8026 12:45:44.605275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 12:45:44.608588 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 12:45:44.611826 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 12:45:44.618762 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 12:45:44.621938 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 12:45:44.629184 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8032 12:45:44.631649 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8033 12:45:44.634855 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8034 12:45:44.641708 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 12:45:44.644894 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 12:45:44.648891 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 12:45:44.654910 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 12:45:44.658711 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8039 12:45:44.661215 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8040 12:45:44.667526 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8041 12:45:44.670976 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8042 12:45:44.674204 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 12:45:44.682134 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 12:45:44.684867 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 12:45:44.687261 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 12:45:44.693750 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 12:45:44.697112 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8048 12:45:44.701230 1 6 16 | B1->B0 | 2424 4545 | 1 0 | (0 0) (0 0)
8049 12:45:44.707104 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8050 12:45:44.710693 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8051 12:45:44.714048 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 12:45:44.720393 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 12:45:44.723745 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 12:45:44.726986 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8055 12:45:44.733774 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8056 12:45:44.736753 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8057 12:45:44.740106 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8058 12:45:44.747179 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:45:44.750030 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:45:44.753578 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:45:44.759861 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 12:45:44.763892 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 12:45:44.766953 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 12:45:44.773138 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 12:45:44.776496 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 12:45:44.779583 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 12:45:44.786226 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 12:45:44.789855 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 12:45:44.792582 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 12:45:44.799615 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8071 12:45:44.802848 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8072 12:45:44.806152 Total UI for P1: 0, mck2ui 16
8073 12:45:44.809131 best dqsien dly found for B0: ( 1, 9, 8)
8074 12:45:44.813278 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8075 12:45:44.819083 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 12:45:44.819555 Total UI for P1: 0, mck2ui 16
8077 12:45:44.823054 best dqsien dly found for B1: ( 1, 9, 18)
8078 12:45:44.829571 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8079 12:45:44.832436 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8080 12:45:44.832949
8081 12:45:44.836264 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8082 12:45:44.839689 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8083 12:45:44.842603 [Gating] SW calibration Done
8084 12:45:44.843169 ==
8085 12:45:44.845618 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 12:45:44.849198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 12:45:44.849777 ==
8088 12:45:44.852168 RX Vref Scan: 0
8089 12:45:44.852673
8090 12:45:44.853051 RX Vref 0 -> 0, step: 1
8091 12:45:44.853399
8092 12:45:44.855408 RX Delay 0 -> 252, step: 8
8093 12:45:44.859184 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8094 12:45:44.865938 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8095 12:45:44.869132 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8096 12:45:44.871973 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8097 12:45:44.875590 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8098 12:45:44.879170 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8099 12:45:44.881965 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8100 12:45:44.888682 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8101 12:45:44.892327 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8102 12:45:44.895743 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8103 12:45:44.898696 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8104 12:45:44.905075 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8105 12:45:44.909132 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8106 12:45:44.911568 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8107 12:45:44.914899 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8108 12:45:44.921999 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8109 12:45:44.922576 ==
8110 12:45:44.925418 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 12:45:44.928756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 12:45:44.929226 ==
8113 12:45:44.929682 DQS Delay:
8114 12:45:44.931408 DQS0 = 0, DQS1 = 0
8115 12:45:44.931978 DQM Delay:
8116 12:45:44.934808 DQM0 = 133, DQM1 = 127
8117 12:45:44.935274 DQ Delay:
8118 12:45:44.938549 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8119 12:45:44.941393 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8120 12:45:44.944650 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8121 12:45:44.947842 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8122 12:45:44.948409
8123 12:45:44.948824
8124 12:45:44.951267 ==
8125 12:45:44.954300 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 12:45:44.957985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 12:45:44.958561 ==
8128 12:45:44.958936
8129 12:45:44.959278
8130 12:45:44.960971 TX Vref Scan disable
8131 12:45:44.961439 == TX Byte 0 ==
8132 12:45:44.964664 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8133 12:45:44.971689 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8134 12:45:44.972262 == TX Byte 1 ==
8135 12:45:44.977810 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8136 12:45:44.981439 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8137 12:45:44.982011 ==
8138 12:45:44.984613 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 12:45:44.987258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 12:45:44.987731 ==
8141 12:45:45.000469
8142 12:45:45.004348 TX Vref early break, caculate TX vref
8143 12:45:45.006816 TX Vref=16, minBit 1, minWin=22, winSum=380
8144 12:45:45.010087 TX Vref=18, minBit 0, minWin=23, winSum=388
8145 12:45:45.014039 TX Vref=20, minBit 2, minWin=23, winSum=399
8146 12:45:45.016636 TX Vref=22, minBit 1, minWin=23, winSum=404
8147 12:45:45.019721 TX Vref=24, minBit 1, minWin=24, winSum=414
8148 12:45:45.026584 TX Vref=26, minBit 0, minWin=25, winSum=419
8149 12:45:45.029613 TX Vref=28, minBit 1, minWin=24, winSum=414
8150 12:45:45.033058 TX Vref=30, minBit 0, minWin=24, winSum=410
8151 12:45:45.036591 TX Vref=32, minBit 1, minWin=23, winSum=396
8152 12:45:45.043413 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8153 12:45:45.043986
8154 12:45:45.046547 Final TX Range 0 Vref 26
8155 12:45:45.047154
8156 12:45:45.047528 ==
8157 12:45:45.049506 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 12:45:45.053065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 12:45:45.053533 ==
8160 12:45:45.053899
8161 12:45:45.054243
8162 12:45:45.055827 TX Vref Scan disable
8163 12:45:45.063319 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8164 12:45:45.063907 == TX Byte 0 ==
8165 12:45:45.065937 u2DelayCellOfst[0]=14 cells (4 PI)
8166 12:45:45.069193 u2DelayCellOfst[1]=18 cells (5 PI)
8167 12:45:45.073195 u2DelayCellOfst[2]=14 cells (4 PI)
8168 12:45:45.076075 u2DelayCellOfst[3]=14 cells (4 PI)
8169 12:45:45.079647 u2DelayCellOfst[4]=11 cells (3 PI)
8170 12:45:45.082552 u2DelayCellOfst[5]=0 cells (0 PI)
8171 12:45:45.085720 u2DelayCellOfst[6]=18 cells (5 PI)
8172 12:45:45.089096 u2DelayCellOfst[7]=22 cells (6 PI)
8173 12:45:45.092272 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8174 12:45:45.095531 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8175 12:45:45.099492 == TX Byte 1 ==
8176 12:45:45.102127 u2DelayCellOfst[8]=0 cells (0 PI)
8177 12:45:45.102693 u2DelayCellOfst[9]=3 cells (1 PI)
8178 12:45:45.105286 u2DelayCellOfst[10]=11 cells (3 PI)
8179 12:45:45.109142 u2DelayCellOfst[11]=3 cells (1 PI)
8180 12:45:45.113064 u2DelayCellOfst[12]=14 cells (4 PI)
8181 12:45:45.115916 u2DelayCellOfst[13]=14 cells (4 PI)
8182 12:45:45.118788 u2DelayCellOfst[14]=18 cells (5 PI)
8183 12:45:45.121997 u2DelayCellOfst[15]=11 cells (3 PI)
8184 12:45:45.128419 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8185 12:45:45.131884 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8186 12:45:45.132455 DramC Write-DBI on
8187 12:45:45.132882 ==
8188 12:45:45.135250 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 12:45:45.141756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 12:45:45.142329 ==
8191 12:45:45.142702
8192 12:45:45.143046
8193 12:45:45.143374 TX Vref Scan disable
8194 12:45:45.146247 == TX Byte 0 ==
8195 12:45:45.149102 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8196 12:45:45.152582 == TX Byte 1 ==
8197 12:45:45.155794 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8198 12:45:45.159119 DramC Write-DBI off
8199 12:45:45.159690
8200 12:45:45.160078 [DATLAT]
8201 12:45:45.160466 Freq=1600, CH0 RK1
8202 12:45:45.160855
8203 12:45:45.162446 DATLAT Default: 0xf
8204 12:45:45.165917 0, 0xFFFF, sum = 0
8205 12:45:45.166497 1, 0xFFFF, sum = 0
8206 12:45:45.168969 2, 0xFFFF, sum = 0
8207 12:45:45.169550 3, 0xFFFF, sum = 0
8208 12:45:45.172469 4, 0xFFFF, sum = 0
8209 12:45:45.173089 5, 0xFFFF, sum = 0
8210 12:45:45.175390 6, 0xFFFF, sum = 0
8211 12:45:45.175861 7, 0xFFFF, sum = 0
8212 12:45:45.178901 8, 0xFFFF, sum = 0
8213 12:45:45.179373 9, 0xFFFF, sum = 0
8214 12:45:45.182368 10, 0xFFFF, sum = 0
8215 12:45:45.182950 11, 0xFFFF, sum = 0
8216 12:45:45.185358 12, 0xFFFF, sum = 0
8217 12:45:45.185934 13, 0xFFFF, sum = 0
8218 12:45:45.189093 14, 0x0, sum = 1
8219 12:45:45.189715 15, 0x0, sum = 2
8220 12:45:45.191941 16, 0x0, sum = 3
8221 12:45:45.192416 17, 0x0, sum = 4
8222 12:45:45.195341 best_step = 15
8223 12:45:45.195806
8224 12:45:45.196178 ==
8225 12:45:45.198666 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 12:45:45.202588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 12:45:45.203177 ==
8228 12:45:45.204955 RX Vref Scan: 0
8229 12:45:45.205419
8230 12:45:45.205789 RX Vref 0 -> 0, step: 1
8231 12:45:45.206134
8232 12:45:45.208802 RX Delay 11 -> 252, step: 4
8233 12:45:45.215273 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8234 12:45:45.218135 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8235 12:45:45.221562 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8236 12:45:45.225567 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8237 12:45:45.228587 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8238 12:45:45.234597 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8239 12:45:45.237703 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8240 12:45:45.241319 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8241 12:45:45.244456 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8242 12:45:45.247582 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8243 12:45:45.254526 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8244 12:45:45.257974 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8245 12:45:45.260852 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8246 12:45:45.264216 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8247 12:45:45.271159 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8248 12:45:45.274150 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8249 12:45:45.274743 ==
8250 12:45:45.277543 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 12:45:45.280714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 12:45:45.281142 ==
8253 12:45:45.284386 DQS Delay:
8254 12:45:45.284948 DQS0 = 0, DQS1 = 0
8255 12:45:45.285290 DQM Delay:
8256 12:45:45.287913 DQM0 = 130, DQM1 = 125
8257 12:45:45.288437 DQ Delay:
8258 12:45:45.290218 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8259 12:45:45.297470 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8260 12:45:45.300197 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8261 12:45:45.304401 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =134
8262 12:45:45.304965
8263 12:45:45.305299
8264 12:45:45.305611
8265 12:45:45.306582 [DramC_TX_OE_Calibration] TA2
8266 12:45:45.310428 Original DQ_B0 (3 6) =30, OEN = 27
8267 12:45:45.313328 Original DQ_B1 (3 6) =30, OEN = 27
8268 12:45:45.313759 24, 0x0, End_B0=24 End_B1=24
8269 12:45:45.317125 25, 0x0, End_B0=25 End_B1=25
8270 12:45:45.320102 26, 0x0, End_B0=26 End_B1=26
8271 12:45:45.323633 27, 0x0, End_B0=27 End_B1=27
8272 12:45:45.326521 28, 0x0, End_B0=28 End_B1=28
8273 12:45:45.327095 29, 0x0, End_B0=29 End_B1=29
8274 12:45:45.329696 30, 0x0, End_B0=30 End_B1=30
8275 12:45:45.333393 31, 0x4545, End_B0=30 End_B1=30
8276 12:45:45.336988 Byte0 end_step=30 best_step=27
8277 12:45:45.340434 Byte1 end_step=30 best_step=27
8278 12:45:45.342986 Byte0 TX OE(2T, 0.5T) = (3, 3)
8279 12:45:45.343506 Byte1 TX OE(2T, 0.5T) = (3, 3)
8280 12:45:45.343847
8281 12:45:45.346084
8282 12:45:45.353138 [DQSOSCAuto] RK1, (LSB)MR18= 0x1cff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps
8283 12:45:45.356126 CH0 RK1: MR19=302, MR18=1CFF
8284 12:45:45.362926 CH0_RK1: MR19=0x302, MR18=0x1CFF, DQSOSC=395, MR23=63, INC=23, DEC=15
8285 12:45:45.366226 [RxdqsGatingPostProcess] freq 1600
8286 12:45:45.369220 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8287 12:45:45.372667 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 12:45:45.376015 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 12:45:45.379047 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 12:45:45.382548 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 12:45:45.385974 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 12:45:45.388823 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 12:45:45.392253 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 12:45:45.395700 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 12:45:45.398692 Pre-setting of DQS Precalculation
8296 12:45:45.402336 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8297 12:45:45.402784 ==
8298 12:45:45.405544 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 12:45:45.409077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 12:45:45.412301 ==
8301 12:45:45.415595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 12:45:45.419356 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 12:45:45.425406 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 12:45:45.431611 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 12:45:45.439153 [CA 0] Center 42 (13~72) winsize 60
8306 12:45:45.442412 [CA 1] Center 42 (13~72) winsize 60
8307 12:45:45.446092 [CA 2] Center 38 (9~67) winsize 59
8308 12:45:45.449597 [CA 3] Center 37 (8~66) winsize 59
8309 12:45:45.452280 [CA 4] Center 37 (8~67) winsize 60
8310 12:45:45.455605 [CA 5] Center 37 (7~67) winsize 61
8311 12:45:45.456053
8312 12:45:45.458692 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8313 12:45:45.459095
8314 12:45:45.462431 [CATrainingPosCal] consider 1 rank data
8315 12:45:45.465946 u2DelayCellTimex100 = 262/100 ps
8316 12:45:45.471947 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8317 12:45:45.475334 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8318 12:45:45.479426 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8319 12:45:45.482128 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8320 12:45:45.485250 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8321 12:45:45.488905 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8322 12:45:45.489450
8323 12:45:45.492292 CA PerBit enable=1, Macro0, CA PI delay=37
8324 12:45:45.492867
8325 12:45:45.495641 [CBTSetCACLKResult] CA Dly = 37
8326 12:45:45.498690 CS Dly: 9 (0~40)
8327 12:45:45.501825 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 12:45:45.505398 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 12:45:45.505947 ==
8330 12:45:45.509168 Dram Type= 6, Freq= 0, CH_1, rank 1
8331 12:45:45.512209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 12:45:45.515371 ==
8333 12:45:45.518970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 12:45:45.521752 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 12:45:45.528431 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 12:45:45.534717 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 12:45:45.542095 [CA 0] Center 42 (13~71) winsize 59
8338 12:45:45.545341 [CA 1] Center 42 (13~72) winsize 60
8339 12:45:45.548973 [CA 2] Center 37 (8~67) winsize 60
8340 12:45:45.552199 [CA 3] Center 37 (8~67) winsize 60
8341 12:45:45.555215 [CA 4] Center 37 (8~67) winsize 60
8342 12:45:45.559256 [CA 5] Center 37 (8~67) winsize 60
8343 12:45:45.559811
8344 12:45:45.561700 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8345 12:45:45.562159
8346 12:45:45.565058 [CATrainingPosCal] consider 2 rank data
8347 12:45:45.568953 u2DelayCellTimex100 = 262/100 ps
8348 12:45:45.575135 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8349 12:45:45.578332 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8350 12:45:45.581514 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8351 12:45:45.584993 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8352 12:45:45.588501 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8353 12:45:45.591674 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8354 12:45:45.592227
8355 12:45:45.594680 CA PerBit enable=1, Macro0, CA PI delay=37
8356 12:45:45.595132
8357 12:45:45.598463 [CBTSetCACLKResult] CA Dly = 37
8358 12:45:45.601616 CS Dly: 10 (0~43)
8359 12:45:45.605130 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 12:45:45.608019 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 12:45:45.608604
8362 12:45:45.611697 ----->DramcWriteLeveling(PI) begin...
8363 12:45:45.612248 ==
8364 12:45:45.615332 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 12:45:45.621994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 12:45:45.622544 ==
8367 12:45:45.624670 Write leveling (Byte 0): 23 => 23
8368 12:45:45.627696 Write leveling (Byte 1): 27 => 27
8369 12:45:45.631159 DramcWriteLeveling(PI) end<-----
8370 12:45:45.631711
8371 12:45:45.632080 ==
8372 12:45:45.634643 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 12:45:45.637753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 12:45:45.638212 ==
8375 12:45:45.641017 [Gating] SW mode calibration
8376 12:45:45.647339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8377 12:45:45.654046 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8378 12:45:45.658060 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 12:45:45.661209 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 12:45:45.668375 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 12:45:45.670920 1 4 12 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 0)
8382 12:45:45.673966 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 12:45:45.677436 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 12:45:45.684033 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 12:45:45.687302 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 12:45:45.690629 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 12:45:45.697721 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 12:45:45.700764 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8389 12:45:45.704165 1 5 12 | B1->B0 | 3434 2929 | 0 1 | (0 1) (1 0)
8390 12:45:45.710350 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8391 12:45:45.713767 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 12:45:45.717288 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 12:45:45.723731 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 12:45:45.727028 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 12:45:45.730669 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 12:45:45.736691 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 12:45:45.740327 1 6 12 | B1->B0 | 3a3a 4343 | 0 0 | (0 0) (0 0)
8398 12:45:45.743740 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 12:45:45.750178 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 12:45:45.753539 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 12:45:45.756446 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 12:45:45.763644 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 12:45:45.766600 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 12:45:45.769486 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8405 12:45:45.775973 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 12:45:45.779568 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8407 12:45:45.782790 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:45:45.789531 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:45:45.792729 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:45:45.796410 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:45:45.803047 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:45:45.806040 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:45:45.809919 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:45:45.815991 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:45:45.819580 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 12:45:45.822941 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 12:45:45.829544 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 12:45:45.832509 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 12:45:45.836278 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 12:45:45.842213 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8421 12:45:45.845235 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 12:45:45.848826 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8423 12:45:45.852216 Total UI for P1: 0, mck2ui 16
8424 12:45:45.855644 best dqsien dly found for B0: ( 1, 9, 10)
8425 12:45:45.861888 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 12:45:45.865475 Total UI for P1: 0, mck2ui 16
8427 12:45:45.868807 best dqsien dly found for B1: ( 1, 9, 12)
8428 12:45:45.871796 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8429 12:45:45.875420 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8430 12:45:45.876062
8431 12:45:45.879270 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 12:45:45.882136 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8433 12:45:45.885396 [Gating] SW calibration Done
8434 12:45:45.885866 ==
8435 12:45:45.888504 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 12:45:45.891811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 12:45:45.895150 ==
8438 12:45:45.895615 RX Vref Scan: 0
8439 12:45:45.895983
8440 12:45:45.898596 RX Vref 0 -> 0, step: 1
8441 12:45:45.899181
8442 12:45:45.899560 RX Delay 0 -> 252, step: 8
8443 12:45:45.904872 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8444 12:45:45.907948 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8445 12:45:45.911382 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8446 12:45:45.914611 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8447 12:45:45.921247 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8448 12:45:45.924340 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8449 12:45:45.927575 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8450 12:45:45.931300 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8451 12:45:45.934637 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8452 12:45:45.940771 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8453 12:45:45.944642 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8454 12:45:45.948160 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8455 12:45:45.951228 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8456 12:45:45.954838 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8457 12:45:45.961188 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8458 12:45:45.964020 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8459 12:45:45.964630 ==
8460 12:45:45.967565 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 12:45:45.971155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 12:45:45.971718 ==
8463 12:45:45.973803 DQS Delay:
8464 12:45:45.974268 DQS0 = 0, DQS1 = 0
8465 12:45:45.974634 DQM Delay:
8466 12:45:45.977227 DQM0 = 136, DQM1 = 129
8467 12:45:45.977686 DQ Delay:
8468 12:45:45.980683 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8469 12:45:45.984159 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8470 12:45:45.990279 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8471 12:45:45.993789 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8472 12:45:45.994252
8473 12:45:45.994617
8474 12:45:45.994954 ==
8475 12:45:45.997081 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 12:45:46.000474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 12:45:46.001084 ==
8478 12:45:46.001458
8479 12:45:46.001795
8480 12:45:46.004079 TX Vref Scan disable
8481 12:45:46.006576 == TX Byte 0 ==
8482 12:45:46.010334 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8483 12:45:46.013607 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8484 12:45:46.017046 == TX Byte 1 ==
8485 12:45:46.020630 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8486 12:45:46.023125 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8487 12:45:46.023589 ==
8488 12:45:46.026637 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 12:45:46.034284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 12:45:46.034850 ==
8491 12:45:46.044951
8492 12:45:46.048060 TX Vref early break, caculate TX vref
8493 12:45:46.051340 TX Vref=16, minBit 5, minWin=21, winSum=371
8494 12:45:46.054103 TX Vref=18, minBit 0, minWin=22, winSum=380
8495 12:45:46.058842 TX Vref=20, minBit 0, minWin=23, winSum=392
8496 12:45:46.061910 TX Vref=22, minBit 5, minWin=23, winSum=400
8497 12:45:46.064642 TX Vref=24, minBit 5, minWin=23, winSum=405
8498 12:45:46.071319 TX Vref=26, minBit 0, minWin=24, winSum=415
8499 12:45:46.074420 TX Vref=28, minBit 5, minWin=24, winSum=415
8500 12:45:46.077116 TX Vref=30, minBit 0, minWin=24, winSum=410
8501 12:45:46.080403 TX Vref=32, minBit 0, minWin=23, winSum=400
8502 12:45:46.084838 TX Vref=34, minBit 5, minWin=22, winSum=393
8503 12:45:46.091041 [TxChooseVref] Worse bit 0, Min win 24, Win sum 415, Final Vref 26
8504 12:45:46.091606
8505 12:45:46.094104 Final TX Range 0 Vref 26
8506 12:45:46.094683
8507 12:45:46.095060 ==
8508 12:45:46.097956 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 12:45:46.100294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 12:45:46.100995 ==
8511 12:45:46.101395
8512 12:45:46.101743
8513 12:45:46.104621 TX Vref Scan disable
8514 12:45:46.110683 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8515 12:45:46.111249 == TX Byte 0 ==
8516 12:45:46.114104 u2DelayCellOfst[0]=18 cells (5 PI)
8517 12:45:46.117500 u2DelayCellOfst[1]=14 cells (4 PI)
8518 12:45:46.120385 u2DelayCellOfst[2]=0 cells (0 PI)
8519 12:45:46.123619 u2DelayCellOfst[3]=7 cells (2 PI)
8520 12:45:46.126738 u2DelayCellOfst[4]=11 cells (3 PI)
8521 12:45:46.130260 u2DelayCellOfst[5]=22 cells (6 PI)
8522 12:45:46.133826 u2DelayCellOfst[6]=22 cells (6 PI)
8523 12:45:46.137315 u2DelayCellOfst[7]=7 cells (2 PI)
8524 12:45:46.140230 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8525 12:45:46.143729 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8526 12:45:46.146881 == TX Byte 1 ==
8527 12:45:46.150475 u2DelayCellOfst[8]=0 cells (0 PI)
8528 12:45:46.153119 u2DelayCellOfst[9]=3 cells (1 PI)
8529 12:45:46.153579 u2DelayCellOfst[10]=11 cells (3 PI)
8530 12:45:46.156843 u2DelayCellOfst[11]=3 cells (1 PI)
8531 12:45:46.160168 u2DelayCellOfst[12]=14 cells (4 PI)
8532 12:45:46.163548 u2DelayCellOfst[13]=18 cells (5 PI)
8533 12:45:46.166776 u2DelayCellOfst[14]=18 cells (5 PI)
8534 12:45:46.169980 u2DelayCellOfst[15]=18 cells (5 PI)
8535 12:45:46.176831 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8536 12:45:46.180234 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8537 12:45:46.180854 DramC Write-DBI on
8538 12:45:46.181225 ==
8539 12:45:46.183450 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 12:45:46.189808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 12:45:46.190375 ==
8542 12:45:46.190742
8543 12:45:46.191083
8544 12:45:46.191412 TX Vref Scan disable
8545 12:45:46.193843 == TX Byte 0 ==
8546 12:45:46.197179 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8547 12:45:46.200487 == TX Byte 1 ==
8548 12:45:46.204272 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8549 12:45:46.207741 DramC Write-DBI off
8550 12:45:46.208306
8551 12:45:46.208732 [DATLAT]
8552 12:45:46.209124 Freq=1600, CH1 RK0
8553 12:45:46.209490
8554 12:45:46.210744 DATLAT Default: 0xf
8555 12:45:46.211205 0, 0xFFFF, sum = 0
8556 12:45:46.213566 1, 0xFFFF, sum = 0
8557 12:45:46.217550 2, 0xFFFF, sum = 0
8558 12:45:46.218219 3, 0xFFFF, sum = 0
8559 12:45:46.220958 4, 0xFFFF, sum = 0
8560 12:45:46.221426 5, 0xFFFF, sum = 0
8561 12:45:46.223821 6, 0xFFFF, sum = 0
8562 12:45:46.224323 7, 0xFFFF, sum = 0
8563 12:45:46.226641 8, 0xFFFF, sum = 0
8564 12:45:46.227163 9, 0xFFFF, sum = 0
8565 12:45:46.229949 10, 0xFFFF, sum = 0
8566 12:45:46.230369 11, 0xFFFF, sum = 0
8567 12:45:46.233625 12, 0xFFFF, sum = 0
8568 12:45:46.234165 13, 0xFFFF, sum = 0
8569 12:45:46.236594 14, 0x0, sum = 1
8570 12:45:46.237018 15, 0x0, sum = 2
8571 12:45:46.240132 16, 0x0, sum = 3
8572 12:45:46.240619 17, 0x0, sum = 4
8573 12:45:46.243260 best_step = 15
8574 12:45:46.243684
8575 12:45:46.244021 ==
8576 12:45:46.247063 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 12:45:46.249947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 12:45:46.250378 ==
8579 12:45:46.253572 RX Vref Scan: 1
8580 12:45:46.253994
8581 12:45:46.254384 Set Vref Range= 24 -> 127
8582 12:45:46.254720
8583 12:45:46.256616 RX Vref 24 -> 127, step: 1
8584 12:45:46.257040
8585 12:45:46.260565 RX Delay 11 -> 252, step: 4
8586 12:45:46.261091
8587 12:45:46.263575 Set Vref, RX VrefLevel [Byte0]: 24
8588 12:45:46.266511 [Byte1]: 24
8589 12:45:46.267026
8590 12:45:46.269856 Set Vref, RX VrefLevel [Byte0]: 25
8591 12:45:46.273453 [Byte1]: 25
8592 12:45:46.276845
8593 12:45:46.277401 Set Vref, RX VrefLevel [Byte0]: 26
8594 12:45:46.280000 [Byte1]: 26
8595 12:45:46.284621
8596 12:45:46.285179 Set Vref, RX VrefLevel [Byte0]: 27
8597 12:45:46.287966 [Byte1]: 27
8598 12:45:46.291820
8599 12:45:46.292378 Set Vref, RX VrefLevel [Byte0]: 28
8600 12:45:46.295241 [Byte1]: 28
8601 12:45:46.299568
8602 12:45:46.300133 Set Vref, RX VrefLevel [Byte0]: 29
8603 12:45:46.303049 [Byte1]: 29
8604 12:45:46.307087
8605 12:45:46.307642 Set Vref, RX VrefLevel [Byte0]: 30
8606 12:45:46.310250 [Byte1]: 30
8607 12:45:46.315321
8608 12:45:46.315874 Set Vref, RX VrefLevel [Byte0]: 31
8609 12:45:46.318070 [Byte1]: 31
8610 12:45:46.322052
8611 12:45:46.322513 Set Vref, RX VrefLevel [Byte0]: 32
8612 12:45:46.325409 [Byte1]: 32
8613 12:45:46.330043
8614 12:45:46.330607 Set Vref, RX VrefLevel [Byte0]: 33
8615 12:45:46.333114 [Byte1]: 33
8616 12:45:46.337217
8617 12:45:46.337631 Set Vref, RX VrefLevel [Byte0]: 34
8618 12:45:46.340927 [Byte1]: 34
8619 12:45:46.345500
8620 12:45:46.346060 Set Vref, RX VrefLevel [Byte0]: 35
8621 12:45:46.348736 [Byte1]: 35
8622 12:45:46.352838
8623 12:45:46.353401 Set Vref, RX VrefLevel [Byte0]: 36
8624 12:45:46.356217 [Byte1]: 36
8625 12:45:46.360369
8626 12:45:46.361002 Set Vref, RX VrefLevel [Byte0]: 37
8627 12:45:46.363505 [Byte1]: 37
8628 12:45:46.368394
8629 12:45:46.369048 Set Vref, RX VrefLevel [Byte0]: 38
8630 12:45:46.371849 [Byte1]: 38
8631 12:45:46.375742
8632 12:45:46.376306 Set Vref, RX VrefLevel [Byte0]: 39
8633 12:45:46.379714 [Byte1]: 39
8634 12:45:46.383437
8635 12:45:46.384003 Set Vref, RX VrefLevel [Byte0]: 40
8636 12:45:46.386697 [Byte1]: 40
8637 12:45:46.390836
8638 12:45:46.391401 Set Vref, RX VrefLevel [Byte0]: 41
8639 12:45:46.393922 [Byte1]: 41
8640 12:45:46.398514
8641 12:45:46.399078 Set Vref, RX VrefLevel [Byte0]: 42
8642 12:45:46.401843 [Byte1]: 42
8643 12:45:46.406344
8644 12:45:46.406932 Set Vref, RX VrefLevel [Byte0]: 43
8645 12:45:46.409960 [Byte1]: 43
8646 12:45:46.413417
8647 12:45:46.413876 Set Vref, RX VrefLevel [Byte0]: 44
8648 12:45:46.417062 [Byte1]: 44
8649 12:45:46.421215
8650 12:45:46.421675 Set Vref, RX VrefLevel [Byte0]: 45
8651 12:45:46.424421 [Byte1]: 45
8652 12:45:46.429523
8653 12:45:46.430077 Set Vref, RX VrefLevel [Byte0]: 46
8654 12:45:46.432050 [Byte1]: 46
8655 12:45:46.436386
8656 12:45:46.436875 Set Vref, RX VrefLevel [Byte0]: 47
8657 12:45:46.439601 [Byte1]: 47
8658 12:45:46.443749
8659 12:45:46.444207 Set Vref, RX VrefLevel [Byte0]: 48
8660 12:45:46.447204 [Byte1]: 48
8661 12:45:46.451470
8662 12:45:46.451929 Set Vref, RX VrefLevel [Byte0]: 49
8663 12:45:46.455397 [Byte1]: 49
8664 12:45:46.459302
8665 12:45:46.459772 Set Vref, RX VrefLevel [Byte0]: 50
8666 12:45:46.462530 [Byte1]: 50
8667 12:45:46.467209
8668 12:45:46.467727 Set Vref, RX VrefLevel [Byte0]: 51
8669 12:45:46.470593 [Byte1]: 51
8670 12:45:46.474760
8671 12:45:46.475320 Set Vref, RX VrefLevel [Byte0]: 52
8672 12:45:46.478488 [Byte1]: 52
8673 12:45:46.482125
8674 12:45:46.482593 Set Vref, RX VrefLevel [Byte0]: 53
8675 12:45:46.485814 [Byte1]: 53
8676 12:45:46.490143
8677 12:45:46.490700 Set Vref, RX VrefLevel [Byte0]: 54
8678 12:45:46.493355 [Byte1]: 54
8679 12:45:46.497318
8680 12:45:46.497783 Set Vref, RX VrefLevel [Byte0]: 55
8681 12:45:46.500856 [Byte1]: 55
8682 12:45:46.505436
8683 12:45:46.505992 Set Vref, RX VrefLevel [Byte0]: 56
8684 12:45:46.508968 [Byte1]: 56
8685 12:45:46.512799
8686 12:45:46.513356 Set Vref, RX VrefLevel [Byte0]: 57
8687 12:45:46.515680 [Byte1]: 57
8688 12:45:46.520197
8689 12:45:46.520801 Set Vref, RX VrefLevel [Byte0]: 58
8690 12:45:46.524169 [Byte1]: 58
8691 12:45:46.528278
8692 12:45:46.528874 Set Vref, RX VrefLevel [Byte0]: 59
8693 12:45:46.531074 [Byte1]: 59
8694 12:45:46.535586
8695 12:45:46.536170 Set Vref, RX VrefLevel [Byte0]: 60
8696 12:45:46.538795 [Byte1]: 60
8697 12:45:46.543263
8698 12:45:46.543728 Set Vref, RX VrefLevel [Byte0]: 61
8699 12:45:46.546248 [Byte1]: 61
8700 12:45:46.550686
8701 12:45:46.551145 Set Vref, RX VrefLevel [Byte0]: 62
8702 12:45:46.554117 [Byte1]: 62
8703 12:45:46.558316
8704 12:45:46.558876 Set Vref, RX VrefLevel [Byte0]: 63
8705 12:45:46.561630 [Byte1]: 63
8706 12:45:46.566446
8707 12:45:46.567007 Set Vref, RX VrefLevel [Byte0]: 64
8708 12:45:46.569079 [Byte1]: 64
8709 12:45:46.573292
8710 12:45:46.573751 Set Vref, RX VrefLevel [Byte0]: 65
8711 12:45:46.577095 [Byte1]: 65
8712 12:45:46.581198
8713 12:45:46.581713 Set Vref, RX VrefLevel [Byte0]: 66
8714 12:45:46.584979 [Byte1]: 66
8715 12:45:46.589374
8716 12:45:46.589875 Set Vref, RX VrefLevel [Byte0]: 67
8717 12:45:46.592215 [Byte1]: 67
8718 12:45:46.596398
8719 12:45:46.596902 Set Vref, RX VrefLevel [Byte0]: 68
8720 12:45:46.599758 [Byte1]: 68
8721 12:45:46.604337
8722 12:45:46.604935 Set Vref, RX VrefLevel [Byte0]: 69
8723 12:45:46.607883 [Byte1]: 69
8724 12:45:46.611809
8725 12:45:46.612366 Set Vref, RX VrefLevel [Byte0]: 70
8726 12:45:46.615575 [Byte1]: 70
8727 12:45:46.619661
8728 12:45:46.620213 Set Vref, RX VrefLevel [Byte0]: 71
8729 12:45:46.622806 [Byte1]: 71
8730 12:45:46.626917
8731 12:45:46.627484 Set Vref, RX VrefLevel [Byte0]: 72
8732 12:45:46.630220 [Byte1]: 72
8733 12:45:46.634679
8734 12:45:46.635238 Set Vref, RX VrefLevel [Byte0]: 73
8735 12:45:46.637807 [Byte1]: 73
8736 12:45:46.642978
8737 12:45:46.643443 Set Vref, RX VrefLevel [Byte0]: 74
8738 12:45:46.645882 [Byte1]: 74
8739 12:45:46.649948
8740 12:45:46.650409 Set Vref, RX VrefLevel [Byte0]: 75
8741 12:45:46.653116 [Byte1]: 75
8742 12:45:46.657611
8743 12:45:46.658071 Final RX Vref Byte 0 = 57 to rank0
8744 12:45:46.660465 Final RX Vref Byte 1 = 60 to rank0
8745 12:45:46.663959 Final RX Vref Byte 0 = 57 to rank1
8746 12:45:46.667571 Final RX Vref Byte 1 = 60 to rank1==
8747 12:45:46.670662 Dram Type= 6, Freq= 0, CH_1, rank 0
8748 12:45:46.677022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 12:45:46.677593 ==
8750 12:45:46.677963 DQS Delay:
8751 12:45:46.680784 DQS0 = 0, DQS1 = 0
8752 12:45:46.681343 DQM Delay:
8753 12:45:46.681712 DQM0 = 133, DQM1 = 127
8754 12:45:46.683816 DQ Delay:
8755 12:45:46.686872 DQ0 =140, DQ1 =126, DQ2 =124, DQ3 =130
8756 12:45:46.690804 DQ4 =132, DQ5 =146, DQ6 =144, DQ7 =128
8757 12:45:46.693273 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8758 12:45:46.697152 DQ12 =136, DQ13 =134, DQ14 =136, DQ15 =138
8759 12:45:46.697715
8760 12:45:46.698085
8761 12:45:46.698426
8762 12:45:46.700301 [DramC_TX_OE_Calibration] TA2
8763 12:45:46.703852 Original DQ_B0 (3 6) =30, OEN = 27
8764 12:45:46.706879 Original DQ_B1 (3 6) =30, OEN = 27
8765 12:45:46.709863 24, 0x0, End_B0=24 End_B1=24
8766 12:45:46.713377 25, 0x0, End_B0=25 End_B1=25
8767 12:45:46.713943 26, 0x0, End_B0=26 End_B1=26
8768 12:45:46.716938 27, 0x0, End_B0=27 End_B1=27
8769 12:45:46.719827 28, 0x0, End_B0=28 End_B1=28
8770 12:45:46.723133 29, 0x0, End_B0=29 End_B1=29
8771 12:45:46.723703 30, 0x0, End_B0=30 End_B1=30
8772 12:45:46.726380 31, 0x4141, End_B0=30 End_B1=30
8773 12:45:46.729615 Byte0 end_step=30 best_step=27
8774 12:45:46.733172 Byte1 end_step=30 best_step=27
8775 12:45:46.736385 Byte0 TX OE(2T, 0.5T) = (3, 3)
8776 12:45:46.739889 Byte1 TX OE(2T, 0.5T) = (3, 3)
8777 12:45:46.740451
8778 12:45:46.740863
8779 12:45:46.746015 [DQSOSCAuto] RK0, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8780 12:45:46.750367 CH1 RK0: MR19=303, MR18=180D
8781 12:45:46.756195 CH1_RK0: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8782 12:45:46.756820
8783 12:45:46.759554 ----->DramcWriteLeveling(PI) begin...
8784 12:45:46.760025 ==
8785 12:45:46.762568 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 12:45:46.765979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 12:45:46.766476 ==
8788 12:45:46.769402 Write leveling (Byte 0): 23 => 23
8789 12:45:46.772638 Write leveling (Byte 1): 26 => 26
8790 12:45:46.776373 DramcWriteLeveling(PI) end<-----
8791 12:45:46.777015
8792 12:45:46.777385 ==
8793 12:45:46.780061 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 12:45:46.782506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 12:45:46.785748 ==
8796 12:45:46.786211 [Gating] SW mode calibration
8797 12:45:46.796678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8798 12:45:46.800436 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8799 12:45:46.802492 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 12:45:46.809363 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 12:45:46.813372 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 12:45:46.816105 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8803 12:45:46.822724 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 12:45:46.825680 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 12:45:46.829326 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 12:45:46.836510 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 12:45:46.838813 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 12:45:46.841855 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 12:45:46.849317 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8810 12:45:46.852100 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8811 12:45:46.855936 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8812 12:45:46.862271 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 12:45:46.865312 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 12:45:46.868913 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 12:45:46.875395 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 12:45:46.878796 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 12:45:46.882309 1 6 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8818 12:45:46.888369 1 6 12 | B1->B0 | 4444 2323 | 0 0 | (0 0) (0 0)
8819 12:45:46.891623 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 12:45:46.895070 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 12:45:46.901562 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 12:45:46.905229 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 12:45:46.908436 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 12:45:46.915032 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 12:45:46.917994 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 12:45:46.921167 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8827 12:45:46.928396 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8828 12:45:46.932032 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 12:45:46.934553 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 12:45:46.941183 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 12:45:46.944417 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 12:45:46.948149 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 12:45:46.954429 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 12:45:46.957727 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 12:45:46.960664 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 12:45:46.967658 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 12:45:46.971184 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 12:45:46.974094 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 12:45:46.981028 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 12:45:46.983864 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 12:45:46.987310 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8842 12:45:46.993690 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8843 12:45:46.997105 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 12:45:47.000176 Total UI for P1: 0, mck2ui 16
8845 12:45:47.003670 best dqsien dly found for B0: ( 1, 9, 10)
8846 12:45:47.007212 Total UI for P1: 0, mck2ui 16
8847 12:45:47.010451 best dqsien dly found for B1: ( 1, 9, 10)
8848 12:45:47.013954 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8849 12:45:47.017081 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8850 12:45:47.017644
8851 12:45:47.020671 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8852 12:45:47.023604 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8853 12:45:47.027654 [Gating] SW calibration Done
8854 12:45:47.028214 ==
8855 12:45:47.030063 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 12:45:47.036785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 12:45:47.037346 ==
8858 12:45:47.037716 RX Vref Scan: 0
8859 12:45:47.038057
8860 12:45:47.040256 RX Vref 0 -> 0, step: 1
8861 12:45:47.040865
8862 12:45:47.043213 RX Delay 0 -> 252, step: 8
8863 12:45:47.046557 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8864 12:45:47.050151 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8865 12:45:47.052955 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8866 12:45:47.056457 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8867 12:45:47.063189 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8868 12:45:47.066373 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8869 12:45:47.070021 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8870 12:45:47.073072 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8871 12:45:47.077130 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8872 12:45:47.082646 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8873 12:45:47.086257 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8874 12:45:47.089531 iDelay=208, Bit 11, Center 119 (56 ~ 183) 128
8875 12:45:47.092728 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8876 12:45:47.099670 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8877 12:45:47.102772 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8878 12:45:47.106893 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8879 12:45:47.107456 ==
8880 12:45:47.110055 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 12:45:47.112848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 12:45:47.113317 ==
8883 12:45:47.116006 DQS Delay:
8884 12:45:47.116603 DQS0 = 0, DQS1 = 0
8885 12:45:47.119602 DQM Delay:
8886 12:45:47.120160 DQM0 = 136, DQM1 = 129
8887 12:45:47.122273 DQ Delay:
8888 12:45:47.126593 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8889 12:45:47.129745 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8890 12:45:47.132457 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8891 12:45:47.136253 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8892 12:45:47.136849
8893 12:45:47.137218
8894 12:45:47.137558 ==
8895 12:45:47.138763 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 12:45:47.142453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 12:45:47.143015 ==
8898 12:45:47.143389
8899 12:45:47.143728
8900 12:45:47.145871 TX Vref Scan disable
8901 12:45:47.149199 == TX Byte 0 ==
8902 12:45:47.152490 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8903 12:45:47.155800 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8904 12:45:47.158529 == TX Byte 1 ==
8905 12:45:47.162686 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8906 12:45:47.165063 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8907 12:45:47.165604 ==
8908 12:45:47.168512 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 12:45:47.175005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 12:45:47.175558 ==
8911 12:45:47.187134
8912 12:45:47.189951 TX Vref early break, caculate TX vref
8913 12:45:47.193192 TX Vref=16, minBit 0, minWin=22, winSum=380
8914 12:45:47.196554 TX Vref=18, minBit 0, minWin=22, winSum=387
8915 12:45:47.200058 TX Vref=20, minBit 0, minWin=23, winSum=394
8916 12:45:47.203236 TX Vref=22, minBit 1, minWin=23, winSum=400
8917 12:45:47.206512 TX Vref=24, minBit 1, minWin=24, winSum=414
8918 12:45:47.213186 TX Vref=26, minBit 5, minWin=24, winSum=417
8919 12:45:47.216442 TX Vref=28, minBit 0, minWin=24, winSum=418
8920 12:45:47.219835 TX Vref=30, minBit 0, minWin=23, winSum=412
8921 12:45:47.223646 TX Vref=32, minBit 0, minWin=23, winSum=405
8922 12:45:47.226941 TX Vref=34, minBit 0, minWin=22, winSum=396
8923 12:45:47.233792 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 28
8924 12:45:47.234357
8925 12:45:47.236356 Final TX Range 0 Vref 28
8926 12:45:47.236848
8927 12:45:47.237214 ==
8928 12:45:47.240775 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 12:45:47.243265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 12:45:47.243746 ==
8931 12:45:47.244113
8932 12:45:47.244451
8933 12:45:47.246891 TX Vref Scan disable
8934 12:45:47.253177 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8935 12:45:47.253738 == TX Byte 0 ==
8936 12:45:47.256511 u2DelayCellOfst[0]=18 cells (5 PI)
8937 12:45:47.260198 u2DelayCellOfst[1]=11 cells (3 PI)
8938 12:45:47.262766 u2DelayCellOfst[2]=0 cells (0 PI)
8939 12:45:47.266050 u2DelayCellOfst[3]=7 cells (2 PI)
8940 12:45:47.269749 u2DelayCellOfst[4]=7 cells (2 PI)
8941 12:45:47.272728 u2DelayCellOfst[5]=18 cells (5 PI)
8942 12:45:47.276366 u2DelayCellOfst[6]=18 cells (5 PI)
8943 12:45:47.279981 u2DelayCellOfst[7]=3 cells (1 PI)
8944 12:45:47.282622 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8945 12:45:47.286010 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8946 12:45:47.289214 == TX Byte 1 ==
8947 12:45:47.292495 u2DelayCellOfst[8]=0 cells (0 PI)
8948 12:45:47.292989 u2DelayCellOfst[9]=3 cells (1 PI)
8949 12:45:47.295536 u2DelayCellOfst[10]=7 cells (2 PI)
8950 12:45:47.299360 u2DelayCellOfst[11]=3 cells (1 PI)
8951 12:45:47.302202 u2DelayCellOfst[12]=11 cells (3 PI)
8952 12:45:47.305814 u2DelayCellOfst[13]=14 cells (4 PI)
8953 12:45:47.309170 u2DelayCellOfst[14]=14 cells (4 PI)
8954 12:45:47.312769 u2DelayCellOfst[15]=14 cells (4 PI)
8955 12:45:47.315582 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8956 12:45:47.322044 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8957 12:45:47.322601 DramC Write-DBI on
8958 12:45:47.322969 ==
8959 12:45:47.325878 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 12:45:47.331798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 12:45:47.332263 ==
8962 12:45:47.332674
8963 12:45:47.333021
8964 12:45:47.333346 TX Vref Scan disable
8965 12:45:47.336816 == TX Byte 0 ==
8966 12:45:47.339483 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8967 12:45:47.342768 == TX Byte 1 ==
8968 12:45:47.346033 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8969 12:45:47.349344 DramC Write-DBI off
8970 12:45:47.349809
8971 12:45:47.350177 [DATLAT]
8972 12:45:47.350522 Freq=1600, CH1 RK1
8973 12:45:47.350855
8974 12:45:47.353297 DATLAT Default: 0xf
8975 12:45:47.353763 0, 0xFFFF, sum = 0
8976 12:45:47.356132 1, 0xFFFF, sum = 0
8977 12:45:47.359515 2, 0xFFFF, sum = 0
8978 12:45:47.360092 3, 0xFFFF, sum = 0
8979 12:45:47.362852 4, 0xFFFF, sum = 0
8980 12:45:47.363429 5, 0xFFFF, sum = 0
8981 12:45:47.366089 6, 0xFFFF, sum = 0
8982 12:45:47.366689 7, 0xFFFF, sum = 0
8983 12:45:47.369209 8, 0xFFFF, sum = 0
8984 12:45:47.369684 9, 0xFFFF, sum = 0
8985 12:45:47.372607 10, 0xFFFF, sum = 0
8986 12:45:47.373080 11, 0xFFFF, sum = 0
8987 12:45:47.375891 12, 0xFFFF, sum = 0
8988 12:45:47.376471 13, 0xFFFF, sum = 0
8989 12:45:47.378579 14, 0x0, sum = 1
8990 12:45:47.379051 15, 0x0, sum = 2
8991 12:45:47.382312 16, 0x0, sum = 3
8992 12:45:47.382892 17, 0x0, sum = 4
8993 12:45:47.386055 best_step = 15
8994 12:45:47.386631
8995 12:45:47.387005 ==
8996 12:45:47.388429 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 12:45:47.391990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 12:45:47.392462 ==
8999 12:45:47.395203 RX Vref Scan: 0
9000 12:45:47.395790
9001 12:45:47.396166 RX Vref 0 -> 0, step: 1
9002 12:45:47.396510
9003 12:45:47.399401 RX Delay 11 -> 252, step: 4
9004 12:45:47.405475 iDelay=199, Bit 0, Center 138 (83 ~ 194) 112
9005 12:45:47.408923 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9006 12:45:47.411816 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9007 12:45:47.415052 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9008 12:45:47.418987 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9009 12:45:47.425058 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
9010 12:45:47.427875 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9011 12:45:47.431337 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9012 12:45:47.435122 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9013 12:45:47.437726 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9014 12:45:47.444953 iDelay=199, Bit 10, Center 126 (71 ~ 182) 112
9015 12:45:47.447883 iDelay=199, Bit 11, Center 116 (63 ~ 170) 108
9016 12:45:47.451378 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9017 12:45:47.454349 iDelay=199, Bit 13, Center 134 (79 ~ 190) 112
9018 12:45:47.461445 iDelay=199, Bit 14, Center 132 (75 ~ 190) 116
9019 12:45:47.464460 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9020 12:45:47.465075 ==
9021 12:45:47.467735 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 12:45:47.472226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 12:45:47.472836 ==
9024 12:45:47.474906 DQS Delay:
9025 12:45:47.475476 DQS0 = 0, DQS1 = 0
9026 12:45:47.475847 DQM Delay:
9027 12:45:47.477592 DQM0 = 133, DQM1 = 126
9028 12:45:47.478060 DQ Delay:
9029 12:45:47.481258 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9030 12:45:47.484162 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =130
9031 12:45:47.490752 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9032 12:45:47.493851 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
9033 12:45:47.494327
9034 12:45:47.494697
9035 12:45:47.495041
9036 12:45:47.497312 [DramC_TX_OE_Calibration] TA2
9037 12:45:47.501168 Original DQ_B0 (3 6) =30, OEN = 27
9038 12:45:47.504178 Original DQ_B1 (3 6) =30, OEN = 27
9039 12:45:47.504784 24, 0x0, End_B0=24 End_B1=24
9040 12:45:47.507665 25, 0x0, End_B0=25 End_B1=25
9041 12:45:47.510543 26, 0x0, End_B0=26 End_B1=26
9042 12:45:47.514314 27, 0x0, End_B0=27 End_B1=27
9043 12:45:47.514810 28, 0x0, End_B0=28 End_B1=28
9044 12:45:47.517185 29, 0x0, End_B0=29 End_B1=29
9045 12:45:47.520344 30, 0x0, End_B0=30 End_B1=30
9046 12:45:47.523856 31, 0x4141, End_B0=30 End_B1=30
9047 12:45:47.527077 Byte0 end_step=30 best_step=27
9048 12:45:47.530629 Byte1 end_step=30 best_step=27
9049 12:45:47.531199 Byte0 TX OE(2T, 0.5T) = (3, 3)
9050 12:45:47.533685 Byte1 TX OE(2T, 0.5T) = (3, 3)
9051 12:45:47.534154
9052 12:45:47.534521
9053 12:45:47.543527 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9054 12:45:47.546513 CH1 RK1: MR19=303, MR18=D09
9055 12:45:47.550132 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9056 12:45:47.553440 [RxdqsGatingPostProcess] freq 1600
9057 12:45:47.560006 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9058 12:45:47.563614 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 12:45:47.567042 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 12:45:47.570581 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 12:45:47.573130 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 12:45:47.576625 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 12:45:47.579725 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 12:45:47.583663 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 12:45:47.584228 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 12:45:47.587316 Pre-setting of DQS Precalculation
9067 12:45:47.592773 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9068 12:45:47.599948 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9069 12:45:47.606262 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 12:45:47.606892
9071 12:45:47.607275
9072 12:45:47.609147 [Calibration Summary] 3200 Mbps
9073 12:45:47.612975 CH 0, Rank 0
9074 12:45:47.613441 SW Impedance : PASS
9075 12:45:47.616443 DUTY Scan : NO K
9076 12:45:47.619627 ZQ Calibration : PASS
9077 12:45:47.620187 Jitter Meter : NO K
9078 12:45:47.622620 CBT Training : PASS
9079 12:45:47.626017 Write leveling : PASS
9080 12:45:47.626613 RX DQS gating : PASS
9081 12:45:47.629297 RX DQ/DQS(RDDQC) : PASS
9082 12:45:47.629764 TX DQ/DQS : PASS
9083 12:45:47.633139 RX DATLAT : PASS
9084 12:45:47.635776 RX DQ/DQS(Engine): PASS
9085 12:45:47.636272 TX OE : PASS
9086 12:45:47.639772 All Pass.
9087 12:45:47.640325
9088 12:45:47.640967 CH 0, Rank 1
9089 12:45:47.642498 SW Impedance : PASS
9090 12:45:47.642966 DUTY Scan : NO K
9091 12:45:47.645490 ZQ Calibration : PASS
9092 12:45:47.648785 Jitter Meter : NO K
9093 12:45:47.649210 CBT Training : PASS
9094 12:45:47.652468 Write leveling : PASS
9095 12:45:47.655599 RX DQS gating : PASS
9096 12:45:47.656020 RX DQ/DQS(RDDQC) : PASS
9097 12:45:47.658727 TX DQ/DQS : PASS
9098 12:45:47.662323 RX DATLAT : PASS
9099 12:45:47.662844 RX DQ/DQS(Engine): PASS
9100 12:45:47.665429 TX OE : PASS
9101 12:45:47.665856 All Pass.
9102 12:45:47.666190
9103 12:45:47.669638 CH 1, Rank 0
9104 12:45:47.670152 SW Impedance : PASS
9105 12:45:47.672438 DUTY Scan : NO K
9106 12:45:47.675944 ZQ Calibration : PASS
9107 12:45:47.676458 Jitter Meter : NO K
9108 12:45:47.678768 CBT Training : PASS
9109 12:45:47.681861 Write leveling : PASS
9110 12:45:47.682384 RX DQS gating : PASS
9111 12:45:47.685268 RX DQ/DQS(RDDQC) : PASS
9112 12:45:47.688876 TX DQ/DQS : PASS
9113 12:45:47.689394 RX DATLAT : PASS
9114 12:45:47.692223 RX DQ/DQS(Engine): PASS
9115 12:45:47.695013 TX OE : PASS
9116 12:45:47.695445 All Pass.
9117 12:45:47.695778
9118 12:45:47.696094 CH 1, Rank 1
9119 12:45:47.698386 SW Impedance : PASS
9120 12:45:47.701925 DUTY Scan : NO K
9121 12:45:47.702445 ZQ Calibration : PASS
9122 12:45:47.705016 Jitter Meter : NO K
9123 12:45:47.708385 CBT Training : PASS
9124 12:45:47.708937 Write leveling : PASS
9125 12:45:47.711515 RX DQS gating : PASS
9126 12:45:47.712030 RX DQ/DQS(RDDQC) : PASS
9127 12:45:47.714909 TX DQ/DQS : PASS
9128 12:45:47.718156 RX DATLAT : PASS
9129 12:45:47.718585 RX DQ/DQS(Engine): PASS
9130 12:45:47.721522 TX OE : PASS
9131 12:45:47.722053 All Pass.
9132 12:45:47.722396
9133 12:45:47.724460 DramC Write-DBI on
9134 12:45:47.728426 PER_BANK_REFRESH: Hybrid Mode
9135 12:45:47.729012 TX_TRACKING: ON
9136 12:45:47.737936 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9137 12:45:47.744564 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9138 12:45:47.754569 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 12:45:47.757395 [FAST_K] Save calibration result to emmc
9140 12:45:47.761152 sync common calibartion params.
9141 12:45:47.761581 sync cbt_mode0:1, 1:1
9142 12:45:47.764150 dram_init: ddr_geometry: 2
9143 12:45:47.767724 dram_init: ddr_geometry: 2
9144 12:45:47.768151 dram_init: ddr_geometry: 2
9145 12:45:47.771320 0:dram_rank_size:100000000
9146 12:45:47.774071 1:dram_rank_size:100000000
9147 12:45:47.777602 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9148 12:45:47.781420 DFS_SHUFFLE_HW_MODE: ON
9149 12:45:47.784588 dramc_set_vcore_voltage set vcore to 725000
9150 12:45:47.787451 Read voltage for 1600, 0
9151 12:45:47.787977 Vio18 = 0
9152 12:45:47.791487 Vcore = 725000
9153 12:45:47.792017 Vdram = 0
9154 12:45:47.792453 Vddq = 0
9155 12:45:47.792912 Vmddr = 0
9156 12:45:47.793868 switch to 3200 Mbps bootup
9157 12:45:47.797725 [DramcRunTimeConfig]
9158 12:45:47.798250 PHYPLL
9159 12:45:47.801065 DPM_CONTROL_AFTERK: ON
9160 12:45:47.801589 PER_BANK_REFRESH: ON
9161 12:45:47.803960 REFRESH_OVERHEAD_REDUCTION: ON
9162 12:45:47.807517 CMD_PICG_NEW_MODE: OFF
9163 12:45:47.808047 XRTWTW_NEW_MODE: ON
9164 12:45:47.810802 XRTRTR_NEW_MODE: ON
9165 12:45:47.811329 TX_TRACKING: ON
9166 12:45:47.814025 RDSEL_TRACKING: OFF
9167 12:45:47.817382 DQS Precalculation for DVFS: ON
9168 12:45:47.817923 RX_TRACKING: OFF
9169 12:45:47.820696 HW_GATING DBG: ON
9170 12:45:47.821219 ZQCS_ENABLE_LP4: ON
9171 12:45:47.823939 RX_PICG_NEW_MODE: ON
9172 12:45:47.824372 TX_PICG_NEW_MODE: ON
9173 12:45:47.827195 ENABLE_RX_DCM_DPHY: ON
9174 12:45:47.830815 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9175 12:45:47.833780 DUMMY_READ_FOR_TRACKING: OFF
9176 12:45:47.834194 !!! SPM_CONTROL_AFTERK: OFF
9177 12:45:47.837290 !!! SPM could not control APHY
9178 12:45:47.840330 IMPEDANCE_TRACKING: ON
9179 12:45:47.840785 TEMP_SENSOR: ON
9180 12:45:47.843647 HW_SAVE_FOR_SR: OFF
9181 12:45:47.846658 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9182 12:45:47.850822 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9183 12:45:47.851237 Read ODT Tracking: ON
9184 12:45:47.853773 Refresh Rate DeBounce: ON
9185 12:45:47.856704 DFS_NO_QUEUE_FLUSH: ON
9186 12:45:47.860345 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9187 12:45:47.860811 ENABLE_DFS_RUNTIME_MRW: OFF
9188 12:45:47.863804 DDR_RESERVE_NEW_MODE: ON
9189 12:45:47.867183 MR_CBT_SWITCH_FREQ: ON
9190 12:45:47.867599 =========================
9191 12:45:47.887800 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9192 12:45:47.891007 dram_init: ddr_geometry: 2
9193 12:45:47.908960 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9194 12:45:47.912428 dram_init: dram init end (result: 0)
9195 12:45:47.919649 DRAM-K: Full calibration passed in 24621 msecs
9196 12:45:47.922041 MRC: failed to locate region type 0.
9197 12:45:47.922606 DRAM rank0 size:0x100000000,
9198 12:45:47.925325 DRAM rank1 size=0x100000000
9199 12:45:47.935701 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9200 12:45:47.941918 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9201 12:45:47.949235 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9202 12:45:47.955267 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9203 12:45:47.958655 DRAM rank0 size:0x100000000,
9204 12:45:47.961866 DRAM rank1 size=0x100000000
9205 12:45:47.962286 CBMEM:
9206 12:45:47.965122 IMD: root @ 0xfffff000 254 entries.
9207 12:45:47.968261 IMD: root @ 0xffffec00 62 entries.
9208 12:45:47.971987 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9209 12:45:47.978046 WARNING: RO_VPD is uninitialized or empty.
9210 12:45:47.981433 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9211 12:45:47.989364 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9212 12:45:48.001728 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9213 12:45:48.013419 BS: romstage times (exec / console): total (unknown) / 24116 ms
9214 12:45:48.013981
9215 12:45:48.014346
9216 12:45:48.023265 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9217 12:45:48.026345 ARM64: Exception handlers installed.
9218 12:45:48.029402 ARM64: Testing exception
9219 12:45:48.032679 ARM64: Done test exception
9220 12:45:48.033267 Enumerating buses...
9221 12:45:48.035709 Show all devs... Before device enumeration.
9222 12:45:48.039225 Root Device: enabled 1
9223 12:45:48.042404 CPU_CLUSTER: 0: enabled 1
9224 12:45:48.042967 CPU: 00: enabled 1
9225 12:45:48.045413 Compare with tree...
9226 12:45:48.048687 Root Device: enabled 1
9227 12:45:48.049172 CPU_CLUSTER: 0: enabled 1
9228 12:45:48.052133 CPU: 00: enabled 1
9229 12:45:48.052637 Root Device scanning...
9230 12:45:48.055340 scan_static_bus for Root Device
9231 12:45:48.058995 CPU_CLUSTER: 0 enabled
9232 12:45:48.062153 scan_static_bus for Root Device done
9233 12:45:48.065243 scan_bus: bus Root Device finished in 8 msecs
9234 12:45:48.065704 done
9235 12:45:48.071976 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9236 12:45:48.075958 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9237 12:45:48.081981 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9238 12:45:48.088768 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9239 12:45:48.089339 Allocating resources...
9240 12:45:48.091697 Reading resources...
9241 12:45:48.095016 Root Device read_resources bus 0 link: 0
9242 12:45:48.098847 DRAM rank0 size:0x100000000,
9243 12:45:48.099411 DRAM rank1 size=0x100000000
9244 12:45:48.105639 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9245 12:45:48.106207 CPU: 00 missing read_resources
9246 12:45:48.112058 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9247 12:45:48.115107 Root Device read_resources bus 0 link: 0 done
9248 12:45:48.119003 Done reading resources.
9249 12:45:48.121267 Show resources in subtree (Root Device)...After reading.
9250 12:45:48.125380 Root Device child on link 0 CPU_CLUSTER: 0
9251 12:45:48.128828 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 12:45:48.137829 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 12:45:48.138406 CPU: 00
9254 12:45:48.144377 Root Device assign_resources, bus 0 link: 0
9255 12:45:48.148297 CPU_CLUSTER: 0 missing set_resources
9256 12:45:48.150953 Root Device assign_resources, bus 0 link: 0 done
9257 12:45:48.154324 Done setting resources.
9258 12:45:48.157834 Show resources in subtree (Root Device)...After assigning values.
9259 12:45:48.160784 Root Device child on link 0 CPU_CLUSTER: 0
9260 12:45:48.168348 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 12:45:48.174161 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 12:45:48.177390 CPU: 00
9263 12:45:48.177866 Done allocating resources.
9264 12:45:48.183975 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9265 12:45:48.184669 Enabling resources...
9266 12:45:48.187416 done.
9267 12:45:48.190899 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9268 12:45:48.195307 Initializing devices...
9269 12:45:48.195909 Root Device init
9270 12:45:48.197528 init hardware done!
9271 12:45:48.198000 0x00000018: ctrlr->caps
9272 12:45:48.200841 52.000 MHz: ctrlr->f_max
9273 12:45:48.203698 0.400 MHz: ctrlr->f_min
9274 12:45:48.207581 0x40ff8080: ctrlr->voltages
9275 12:45:48.208113 sclk: 390625
9276 12:45:48.208570 Bus Width = 1
9277 12:45:48.210790 sclk: 390625
9278 12:45:48.211319 Bus Width = 1
9279 12:45:48.213842 Early init status = 3
9280 12:45:48.217436 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9281 12:45:48.220393 in-header: 03 fb 00 00 01 00 00 00
9282 12:45:48.223868 in-data: 01
9283 12:45:48.227035 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9284 12:45:48.231385 in-header: 03 fb 00 00 01 00 00 00
9285 12:45:48.234719 in-data: 01
9286 12:45:48.238188 [SSUSB] Setting up USB HOST controller...
9287 12:45:48.241055 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9288 12:45:48.244559 [SSUSB] phy power-on done.
9289 12:45:48.248196 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9290 12:45:48.254319 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9291 12:45:48.257687 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9292 12:45:48.264440 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9293 12:45:48.271234 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9294 12:45:48.278099 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9295 12:45:48.284577 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9296 12:45:48.290707 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9297 12:45:48.293780 SPM: binary array size = 0x9dc
9298 12:45:48.297417 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9299 12:45:48.303903 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9300 12:45:48.310175 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9301 12:45:48.317240 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9302 12:45:48.320350 configure_display: Starting display init
9303 12:45:48.355161 anx7625_power_on_init: Init interface.
9304 12:45:48.358290 anx7625_disable_pd_protocol: Disabled PD feature.
9305 12:45:48.361166 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9306 12:45:48.389591 anx7625_start_dp_work: Secure OCM version=00
9307 12:45:48.392591 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9308 12:45:48.407765 sp_tx_get_edid_block: EDID Block = 1
9309 12:45:48.509902 Extracted contents:
9310 12:45:48.513037 header: 00 ff ff ff ff ff ff 00
9311 12:45:48.516860 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9312 12:45:48.520284 version: 01 04
9313 12:45:48.523885 basic params: 95 1f 11 78 0a
9314 12:45:48.526564 chroma info: 76 90 94 55 54 90 27 21 50 54
9315 12:45:48.530597 established: 00 00 00
9316 12:45:48.536687 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9317 12:45:48.540281 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9318 12:45:48.546774 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9319 12:45:48.552917 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9320 12:45:48.559649 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9321 12:45:48.563851 extensions: 00
9322 12:45:48.564421 checksum: fb
9323 12:45:48.564857
9324 12:45:48.565907 Manufacturer: IVO Model 57d Serial Number 0
9325 12:45:48.569288 Made week 0 of 2020
9326 12:45:48.572833 EDID version: 1.4
9327 12:45:48.573297 Digital display
9328 12:45:48.575883 6 bits per primary color channel
9329 12:45:48.576356 DisplayPort interface
9330 12:45:48.579487 Maximum image size: 31 cm x 17 cm
9331 12:45:48.583483 Gamma: 220%
9332 12:45:48.584065 Check DPMS levels
9333 12:45:48.586243 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9334 12:45:48.592536 First detailed timing is preferred timing
9335 12:45:48.593102 Established timings supported:
9336 12:45:48.595778 Standard timings supported:
9337 12:45:48.599497 Detailed timings
9338 12:45:48.602413 Hex of detail: 383680a07038204018303c0035ae10000019
9339 12:45:48.609138 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9340 12:45:48.612095 0780 0798 07c8 0820 hborder 0
9341 12:45:48.616371 0438 043b 0447 0458 vborder 0
9342 12:45:48.618545 -hsync -vsync
9343 12:45:48.619061 Did detailed timing
9344 12:45:48.625509 Hex of detail: 000000000000000000000000000000000000
9345 12:45:48.628913 Manufacturer-specified data, tag 0
9346 12:45:48.632387 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9347 12:45:48.635247 ASCII string: InfoVision
9348 12:45:48.638772 Hex of detail: 000000fe00523134304e574635205248200a
9349 12:45:48.641696 ASCII string: R140NWF5 RH
9350 12:45:48.642262 Checksum
9351 12:45:48.645143 Checksum: 0xfb (valid)
9352 12:45:48.648446 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9353 12:45:48.652067 DSI data_rate: 832800000 bps
9354 12:45:48.658683 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9355 12:45:48.662017 anx7625_parse_edid: pixelclock(138800).
9356 12:45:48.665142 hactive(1920), hsync(48), hfp(24), hbp(88)
9357 12:45:48.668030 vactive(1080), vsync(12), vfp(3), vbp(17)
9358 12:45:48.671645 anx7625_dsi_config: config dsi.
9359 12:45:48.678158 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9360 12:45:48.691872 anx7625_dsi_config: success to config DSI
9361 12:45:48.695040 anx7625_dp_start: MIPI phy setup OK.
9362 12:45:48.698691 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9363 12:45:48.701794 mtk_ddp_mode_set invalid vrefresh 60
9364 12:45:48.705634 main_disp_path_setup
9365 12:45:48.706198 ovl_layer_smi_id_en
9366 12:45:48.708663 ovl_layer_smi_id_en
9367 12:45:48.709128 ccorr_config
9368 12:45:48.709495 aal_config
9369 12:45:48.712592 gamma_config
9370 12:45:48.713060 postmask_config
9371 12:45:48.714718 dither_config
9372 12:45:48.718315 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9373 12:45:48.724818 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9374 12:45:48.729017 Root Device init finished in 530 msecs
9375 12:45:48.730935 CPU_CLUSTER: 0 init
9376 12:45:48.737942 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9377 12:45:48.744867 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9378 12:45:48.745431 APU_MBOX 0x190000b0 = 0x10001
9379 12:45:48.747828 APU_MBOX 0x190001b0 = 0x10001
9380 12:45:48.751013 APU_MBOX 0x190005b0 = 0x10001
9381 12:45:48.754240 APU_MBOX 0x190006b0 = 0x10001
9382 12:45:48.761030 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9383 12:45:48.771138 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9384 12:45:48.783954 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9385 12:45:48.790173 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9386 12:45:48.801578 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9387 12:45:48.810669 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9388 12:45:48.814511 CPU_CLUSTER: 0 init finished in 81 msecs
9389 12:45:48.817370 Devices initialized
9390 12:45:48.820808 Show all devs... After init.
9391 12:45:48.821419 Root Device: enabled 1
9392 12:45:48.824083 CPU_CLUSTER: 0: enabled 1
9393 12:45:48.827101 CPU: 00: enabled 1
9394 12:45:48.830711 BS: BS_DEV_INIT run times (exec / console): 207 / 428 ms
9395 12:45:48.833768 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9396 12:45:48.836887 ELOG: NV offset 0x57f000 size 0x1000
9397 12:45:48.843830 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9398 12:45:48.850650 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9399 12:45:48.853279 ELOG: Event(17) added with size 13 at 2023-06-14 12:45:48 UTC
9400 12:45:48.860473 out: cmd=0x121: 03 db 21 01 00 00 00 00
9401 12:45:48.863685 in-header: 03 d6 00 00 2c 00 00 00
9402 12:45:48.873282 in-data: 89 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9403 12:45:48.880312 ELOG: Event(A1) added with size 10 at 2023-06-14 12:45:48 UTC
9404 12:45:48.886449 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9405 12:45:48.893379 ELOG: Event(A0) added with size 9 at 2023-06-14 12:45:48 UTC
9406 12:45:48.896495 elog_add_boot_reason: Logged dev mode boot
9407 12:45:48.903310 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9408 12:45:48.903896 Finalize devices...
9409 12:45:48.906331 Devices finalized
9410 12:45:48.909732 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9411 12:45:48.913109 Writing coreboot table at 0xffe64000
9412 12:45:48.916558 0. 000000000010a000-0000000000113fff: RAMSTAGE
9413 12:45:48.923413 1. 0000000040000000-00000000400fffff: RAM
9414 12:45:48.926417 2. 0000000040100000-000000004032afff: RAMSTAGE
9415 12:45:48.929600 3. 000000004032b000-00000000545fffff: RAM
9416 12:45:48.932794 4. 0000000054600000-000000005465ffff: BL31
9417 12:45:48.935789 5. 0000000054660000-00000000ffe63fff: RAM
9418 12:45:48.942571 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9419 12:45:48.945583 7. 0000000100000000-000000023fffffff: RAM
9420 12:45:48.949294 Passing 5 GPIOs to payload:
9421 12:45:48.953462 NAME | PORT | POLARITY | VALUE
9422 12:45:48.958914 EC in RW | 0x000000aa | low | undefined
9423 12:45:48.961973 EC interrupt | 0x00000005 | low | undefined
9424 12:45:48.968728 TPM interrupt | 0x000000ab | high | undefined
9425 12:45:48.972453 SD card detect | 0x00000011 | high | undefined
9426 12:45:48.975900 speaker enable | 0x00000093 | high | undefined
9427 12:45:48.978632 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9428 12:45:48.982370 in-header: 03 f9 00 00 02 00 00 00
9429 12:45:48.985752 in-data: 02 00
9430 12:45:48.989208 ADC[4]: Raw value=901552 ID=7
9431 12:45:48.992242 ADC[3]: Raw value=213282 ID=1
9432 12:45:48.992832 RAM Code: 0x71
9433 12:45:48.995664 ADC[6]: Raw value=75036 ID=0
9434 12:45:48.999118 ADC[5]: Raw value=212912 ID=1
9435 12:45:48.999683 SKU Code: 0x1
9436 12:45:49.005274 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169
9437 12:45:49.005834 coreboot table: 964 bytes.
9438 12:45:49.009196 IMD ROOT 0. 0xfffff000 0x00001000
9439 12:45:49.012305 IMD SMALL 1. 0xffffe000 0x00001000
9440 12:45:49.015499 RO MCACHE 2. 0xffffc000 0x00001104
9441 12:45:49.018528 CONSOLE 3. 0xfff7c000 0x00080000
9442 12:45:49.022358 FMAP 4. 0xfff7b000 0x00000452
9443 12:45:49.025062 TIME STAMP 5. 0xfff7a000 0x00000910
9444 12:45:49.028226 VBOOT WORK 6. 0xfff66000 0x00014000
9445 12:45:49.031583 RAMOOPS 7. 0xffe66000 0x00100000
9446 12:45:49.035049 COREBOOT 8. 0xffe64000 0x00002000
9447 12:45:49.038565 IMD small region:
9448 12:45:49.041908 IMD ROOT 0. 0xffffec00 0x00000400
9449 12:45:49.045169 VPD 1. 0xffffeba0 0x0000004c
9450 12:45:49.048532 MMC STATUS 2. 0xffffeb80 0x00000004
9451 12:45:49.051835 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9452 12:45:49.054701 Probing TPM: done!
9453 12:45:49.058948 Connected to device vid:did:rid of 1ae0:0028:00
9454 12:45:49.069665 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9455 12:45:49.072875 Initialized TPM device CR50 revision 0
9456 12:45:49.076690 Checking cr50 for pending updates
9457 12:45:49.080383 Reading cr50 TPM mode
9458 12:45:49.089533 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9459 12:45:49.095819 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9460 12:45:49.136046 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9461 12:45:49.140025 Checking segment from ROM address 0x40100000
9462 12:45:49.142414 Checking segment from ROM address 0x4010001c
9463 12:45:49.150507 Loading segment from ROM address 0x40100000
9464 12:45:49.151080 code (compression=0)
9465 12:45:49.155892 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9466 12:45:49.166170 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9467 12:45:49.166739 it's not compressed!
9468 12:45:49.172472 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9469 12:45:49.176216 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9470 12:45:49.196750 Loading segment from ROM address 0x4010001c
9471 12:45:49.197312 Entry Point 0x80000000
9472 12:45:49.199753 Loaded segments
9473 12:45:49.203704 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9474 12:45:49.209711 Jumping to boot code at 0x80000000(0xffe64000)
9475 12:45:49.216642 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9476 12:45:49.223013 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9477 12:45:49.231023 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9478 12:45:49.234175 Checking segment from ROM address 0x40100000
9479 12:45:49.236842 Checking segment from ROM address 0x4010001c
9480 12:45:49.243864 Loading segment from ROM address 0x40100000
9481 12:45:49.244418 code (compression=1)
9482 12:45:49.250216 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9483 12:45:49.260562 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9484 12:45:49.261146 using LZMA
9485 12:45:49.268916 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9486 12:45:49.275922 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9487 12:45:49.279122 Loading segment from ROM address 0x4010001c
9488 12:45:49.279709 Entry Point 0x54601000
9489 12:45:49.282263 Loaded segments
9490 12:45:49.285606 NOTICE: MT8192 bl31_setup
9491 12:45:49.292427 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9492 12:45:49.295890 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9493 12:45:49.299244 WARNING: region 0:
9494 12:45:49.302652 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 12:45:49.303123 WARNING: region 1:
9496 12:45:49.309433 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9497 12:45:49.312841 WARNING: region 2:
9498 12:45:49.315981 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9499 12:45:49.319083 WARNING: region 3:
9500 12:45:49.322972 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9501 12:45:49.325864 WARNING: region 4:
9502 12:45:49.333059 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 12:45:49.333634 WARNING: region 5:
9504 12:45:49.336034 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9505 12:45:49.338895 WARNING: region 6:
9506 12:45:49.342488 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 12:45:49.345151 WARNING: region 7:
9508 12:45:49.348670 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 12:45:49.355649 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9510 12:45:49.359238 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9511 12:45:49.362058 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9512 12:45:49.369035 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9513 12:45:49.372079 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9514 12:45:49.375687 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9515 12:45:49.382070 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9516 12:45:49.385728 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9517 12:45:49.391862 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9518 12:45:49.395108 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9519 12:45:49.398782 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9520 12:45:49.405374 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9521 12:45:49.408953 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9522 12:45:49.415132 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9523 12:45:49.418570 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9524 12:45:49.422006 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9525 12:45:49.428553 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9526 12:45:49.432553 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9527 12:45:49.435606 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9528 12:45:49.442355 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9529 12:45:49.445189 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9530 12:45:49.451615 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9531 12:45:49.454927 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9532 12:45:49.459051 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9533 12:45:49.464744 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9534 12:45:49.468064 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9535 12:45:49.475514 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9536 12:45:49.478353 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9537 12:45:49.481701 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9538 12:45:49.488154 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9539 12:45:49.491239 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9540 12:45:49.498391 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9541 12:45:49.501582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9542 12:45:49.504997 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9543 12:45:49.508252 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9544 12:45:49.514871 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9545 12:45:49.517805 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9546 12:45:49.521201 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9547 12:45:49.524870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9548 12:45:49.531095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9549 12:45:49.534873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9550 12:45:49.537522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9551 12:45:49.541412 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9552 12:45:49.547614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9553 12:45:49.550713 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9554 12:45:49.554380 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9555 12:45:49.560695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9556 12:45:49.563815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9557 12:45:49.567539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9558 12:45:49.574312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9559 12:45:49.578128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9560 12:45:49.584054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9561 12:45:49.587258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9562 12:45:49.590428 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9563 12:45:49.597478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9564 12:45:49.600433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9565 12:45:49.607171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9566 12:45:49.610168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9567 12:45:49.616905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9568 12:45:49.620360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9569 12:45:49.627202 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9570 12:45:49.630480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9571 12:45:49.633390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9572 12:45:49.640075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9573 12:45:49.643334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9574 12:45:49.649838 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9575 12:45:49.653386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9576 12:45:49.659695 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9577 12:45:49.663086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9578 12:45:49.669685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9579 12:45:49.672966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9580 12:45:49.676684 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9581 12:45:49.683046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9582 12:45:49.685980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9583 12:45:49.693440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9584 12:45:49.696347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9585 12:45:49.702962 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9586 12:45:49.706441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9587 12:45:49.712623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9588 12:45:49.715883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9589 12:45:49.719649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9590 12:45:49.726108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9591 12:45:49.729115 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9592 12:45:49.735891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9593 12:45:49.739863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9594 12:45:49.745675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9595 12:45:49.749501 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9596 12:45:49.755782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9597 12:45:49.759724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9598 12:45:49.762468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9599 12:45:49.768958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9600 12:45:49.772451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9601 12:45:49.779231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9602 12:45:49.782456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9603 12:45:49.788726 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9604 12:45:49.792113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9605 12:45:49.796225 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9606 12:45:49.803261 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9607 12:45:49.805469 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9608 12:45:49.809456 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9609 12:45:49.812224 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9610 12:45:49.818921 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9611 12:45:49.821885 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9612 12:45:49.829104 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9613 12:45:49.832024 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9614 12:45:49.835550 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9615 12:45:49.842195 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9616 12:45:49.846044 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9617 12:45:49.852193 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9618 12:45:49.855255 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9619 12:45:49.858523 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9620 12:45:49.865142 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9621 12:45:49.868968 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9622 12:45:49.875730 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9623 12:45:49.878928 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9624 12:45:49.881688 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9625 12:45:49.888446 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9626 12:45:49.891633 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9627 12:45:49.895526 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9628 12:45:49.901171 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9629 12:45:49.904782 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9630 12:45:49.908335 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9631 12:45:49.911428 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9632 12:45:49.918324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9633 12:45:49.921300 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9634 12:45:49.925182 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9635 12:45:49.931593 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9636 12:45:49.934740 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9637 12:45:49.941241 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9638 12:45:49.945143 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9639 12:45:49.948019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9640 12:45:49.954276 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9641 12:45:49.957921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9642 12:45:49.964197 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9643 12:45:49.967672 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9644 12:45:49.970740 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9645 12:45:49.978024 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9646 12:45:49.980819 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9647 12:45:49.987350 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9648 12:45:49.990934 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9649 12:45:49.995027 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9650 12:45:50.001225 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9651 12:45:50.004009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9652 12:45:50.010663 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9653 12:45:50.014930 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9654 12:45:50.018116 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9655 12:45:50.023886 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9656 12:45:50.027440 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9657 12:45:50.030445 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9658 12:45:50.037356 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9659 12:45:50.040821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9660 12:45:50.047415 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9661 12:45:50.050208 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9662 12:45:50.053765 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9663 12:45:50.060228 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9664 12:45:50.063962 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9665 12:45:50.070995 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9666 12:45:50.074138 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9667 12:45:50.077192 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9668 12:45:50.084075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9669 12:45:50.087139 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9670 12:45:50.093716 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9671 12:45:50.097411 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9672 12:45:50.100223 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9673 12:45:50.106766 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9674 12:45:50.109963 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9675 12:45:50.116595 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9676 12:45:50.119532 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9677 12:45:50.123607 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9678 12:45:50.130220 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9679 12:45:50.133042 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9680 12:45:50.139812 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9681 12:45:50.142945 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9682 12:45:50.146307 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9683 12:45:50.152497 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9684 12:45:50.156852 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9685 12:45:50.162242 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9686 12:45:50.165825 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9687 12:45:50.172435 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9688 12:45:50.175907 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9689 12:45:50.178908 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9690 12:45:50.185302 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9691 12:45:50.188813 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9692 12:45:50.195636 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9693 12:45:50.199159 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9694 12:45:50.201622 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9695 12:45:50.208170 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9696 12:45:50.211999 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9697 12:45:50.218452 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9698 12:45:50.221738 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9699 12:45:50.224802 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9700 12:45:50.231740 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9701 12:45:50.234649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9702 12:45:50.241456 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9703 12:45:50.244604 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9704 12:45:50.251722 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9705 12:45:50.254500 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9706 12:45:50.257864 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9707 12:45:50.264349 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9708 12:45:50.267758 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9709 12:45:50.274217 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9710 12:45:50.277849 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9711 12:45:50.284682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9712 12:45:50.288134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9713 12:45:50.291139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9714 12:45:50.297464 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9715 12:45:50.300882 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9716 12:45:50.307511 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9717 12:45:50.310492 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9718 12:45:50.317441 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9719 12:45:50.322113 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9720 12:45:50.324406 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9721 12:45:50.330265 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9722 12:45:50.333473 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9723 12:45:50.340191 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9724 12:45:50.343807 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9725 12:45:50.350038 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9726 12:45:50.353201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9727 12:45:50.357234 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9728 12:45:50.363322 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9729 12:45:50.366582 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9730 12:45:50.373290 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9731 12:45:50.376777 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9732 12:45:50.383431 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9733 12:45:50.386657 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9734 12:45:50.390298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9735 12:45:50.397055 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9736 12:45:50.399684 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9737 12:45:50.406554 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9738 12:45:50.410206 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9739 12:45:50.413419 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9740 12:45:50.415990 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9741 12:45:50.423140 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9742 12:45:50.426618 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9743 12:45:50.429912 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9744 12:45:50.436490 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9745 12:45:50.439374 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9746 12:45:50.442613 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9747 12:45:50.448927 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9748 12:45:50.452923 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9749 12:45:50.455632 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9750 12:45:50.462349 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9751 12:45:50.466190 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9752 12:45:50.469037 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9753 12:45:50.476380 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9754 12:45:50.479528 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9755 12:45:50.486114 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9756 12:45:50.488897 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9757 12:45:50.492513 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9758 12:45:50.498964 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9759 12:45:50.502386 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9760 12:45:50.509381 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9761 12:45:50.511840 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9762 12:45:50.515726 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9763 12:45:50.522418 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9764 12:45:50.525141 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9765 12:45:50.528901 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9766 12:45:50.535370 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9767 12:45:50.538834 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9768 12:45:50.541850 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9769 12:45:50.548393 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9770 12:45:50.552023 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9771 12:45:50.558890 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9772 12:45:50.561881 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9773 12:45:50.564876 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9774 12:45:50.571497 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9775 12:45:50.575067 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9776 12:45:50.581242 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9777 12:45:50.584888 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9778 12:45:50.587800 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9779 12:45:50.591336 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9780 12:45:50.595071 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9781 12:45:50.601363 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9782 12:45:50.605104 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9783 12:45:50.608178 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9784 12:45:50.611111 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9785 12:45:50.617484 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9786 12:45:50.621618 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9787 12:45:50.624391 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9788 12:45:50.627664 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9789 12:45:50.634223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9790 12:45:50.637843 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9791 12:45:50.644165 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9792 12:45:50.647768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9793 12:45:50.650803 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9794 12:45:50.657333 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9795 12:45:50.660962 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9796 12:45:50.667427 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9797 12:45:50.671239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9798 12:45:50.673679 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9799 12:45:50.680320 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9800 12:45:50.683450 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9801 12:45:50.690177 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9802 12:45:50.693985 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9803 12:45:50.700412 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9804 12:45:50.703826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9805 12:45:50.707316 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9806 12:45:50.713629 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9807 12:45:50.717292 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9808 12:45:50.723777 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9809 12:45:50.726830 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9810 12:45:50.733358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9811 12:45:50.736605 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9812 12:45:50.740159 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9813 12:45:50.746475 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9814 12:45:50.749769 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9815 12:45:50.753010 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9816 12:45:50.760667 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9817 12:45:50.763335 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9818 12:45:50.769669 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9819 12:45:50.773208 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9820 12:45:50.780112 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9821 12:45:50.782939 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9822 12:45:50.785783 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9823 12:45:50.792443 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9824 12:45:50.796047 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9825 12:45:50.802650 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9826 12:45:50.806393 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9827 12:45:50.812337 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9828 12:45:50.816805 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9829 12:45:50.818891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9830 12:45:50.825728 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9831 12:45:50.829252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9832 12:45:50.835963 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9833 12:45:50.839073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9834 12:45:50.842108 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9835 12:45:50.848811 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9836 12:45:50.851892 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9837 12:45:50.858701 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9838 12:45:50.862471 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9839 12:45:50.868463 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9840 12:45:50.871752 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9841 12:45:50.874970 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9842 12:45:50.881972 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9843 12:45:50.884787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9844 12:45:50.892116 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9845 12:45:50.894968 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9846 12:45:50.898122 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9847 12:45:50.904837 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9848 12:45:50.908239 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9849 12:45:50.914539 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9850 12:45:50.917860 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9851 12:45:50.924967 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9852 12:45:50.927882 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9853 12:45:50.934855 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9854 12:45:50.937419 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9855 12:45:50.941046 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9856 12:45:50.947363 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9857 12:45:50.950669 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9858 12:45:50.958254 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9859 12:45:50.960583 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9860 12:45:50.963633 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9861 12:45:50.970619 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9862 12:45:50.973761 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9863 12:45:50.981189 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9864 12:45:50.983325 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9865 12:45:50.990452 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9866 12:45:50.993038 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9867 12:45:51.000807 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9868 12:45:51.003051 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9869 12:45:51.006239 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9870 12:45:51.012715 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9871 12:45:51.016216 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9872 12:45:51.023114 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9873 12:45:51.026502 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9874 12:45:51.032906 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9875 12:45:51.036368 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9876 12:45:51.043149 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9877 12:45:51.046032 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9878 12:45:51.049774 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9879 12:45:51.055807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9880 12:45:51.059892 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9881 12:45:51.066462 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9882 12:45:51.068904 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9883 12:45:51.075996 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9884 12:45:51.079556 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9885 12:45:51.085857 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9886 12:45:51.089421 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9887 12:45:51.092173 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9888 12:45:51.099086 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9889 12:45:51.102026 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9890 12:45:51.108664 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9891 12:45:51.112043 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9892 12:45:51.118732 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9893 12:45:51.122277 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9894 12:45:51.125137 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9895 12:45:51.131573 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9896 12:45:51.134806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9897 12:45:51.141688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9898 12:45:51.144999 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9899 12:45:51.151645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9900 12:45:51.155047 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9901 12:45:51.161734 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9902 12:45:51.165034 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9903 12:45:51.167999 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9904 12:45:51.174861 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9905 12:45:51.178321 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9906 12:45:51.184760 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9907 12:45:51.187694 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9908 12:45:51.194664 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9909 12:45:51.197910 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9910 12:45:51.201270 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9911 12:45:51.208155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9912 12:45:51.211027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9913 12:45:51.218040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9914 12:45:51.221059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9915 12:45:51.228274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9916 12:45:51.231634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9917 12:45:51.237773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9918 12:45:51.240799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9919 12:45:51.247192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9920 12:45:51.251039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9921 12:45:51.257102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9922 12:45:51.261004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9923 12:45:51.267160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9924 12:45:51.270720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9925 12:45:51.277101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9926 12:45:51.280858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9927 12:45:51.286801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9928 12:45:51.290205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9929 12:45:51.297421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9930 12:45:51.300274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9931 12:45:51.306995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9932 12:45:51.310012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9933 12:45:51.317266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9934 12:45:51.320380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9935 12:45:51.326636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9936 12:45:51.329992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9937 12:45:51.336626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9938 12:45:51.340102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9939 12:45:51.347059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9940 12:45:51.349711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9941 12:45:51.356995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9942 12:45:51.359619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9943 12:45:51.363703 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9944 12:45:51.366359 INFO: [APUAPC] vio 0
9945 12:45:51.372779 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9946 12:45:51.376178 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9947 12:45:51.379245 INFO: [APUAPC] D0_APC_0: 0x400510
9948 12:45:51.382484 INFO: [APUAPC] D0_APC_1: 0x0
9949 12:45:51.386642 INFO: [APUAPC] D0_APC_2: 0x1540
9950 12:45:51.389524 INFO: [APUAPC] D0_APC_3: 0x0
9951 12:45:51.392640 INFO: [APUAPC] D1_APC_0: 0xffffffff
9952 12:45:51.395860 INFO: [APUAPC] D1_APC_1: 0xffffffff
9953 12:45:51.399450 INFO: [APUAPC] D1_APC_2: 0x3fffff
9954 12:45:51.402221 INFO: [APUAPC] D1_APC_3: 0x0
9955 12:45:51.405938 INFO: [APUAPC] D2_APC_0: 0xffffffff
9956 12:45:51.409081 INFO: [APUAPC] D2_APC_1: 0xffffffff
9957 12:45:51.412647 INFO: [APUAPC] D2_APC_2: 0x3fffff
9958 12:45:51.415186 INFO: [APUAPC] D2_APC_3: 0x0
9959 12:45:51.418814 INFO: [APUAPC] D3_APC_0: 0xffffffff
9960 12:45:51.422192 INFO: [APUAPC] D3_APC_1: 0xffffffff
9961 12:45:51.425898 INFO: [APUAPC] D3_APC_2: 0x3fffff
9962 12:45:51.428682 INFO: [APUAPC] D3_APC_3: 0x0
9963 12:45:51.432296 INFO: [APUAPC] D4_APC_0: 0xffffffff
9964 12:45:51.435528 INFO: [APUAPC] D4_APC_1: 0xffffffff
9965 12:45:51.438807 INFO: [APUAPC] D4_APC_2: 0x3fffff
9966 12:45:51.441564 INFO: [APUAPC] D4_APC_3: 0x0
9967 12:45:51.445181 INFO: [APUAPC] D5_APC_0: 0xffffffff
9968 12:45:51.448345 INFO: [APUAPC] D5_APC_1: 0xffffffff
9969 12:45:51.451545 INFO: [APUAPC] D5_APC_2: 0x3fffff
9970 12:45:51.455256 INFO: [APUAPC] D5_APC_3: 0x0
9971 12:45:51.458402 INFO: [APUAPC] D6_APC_0: 0xffffffff
9972 12:45:51.461421 INFO: [APUAPC] D6_APC_1: 0xffffffff
9973 12:45:51.464833 INFO: [APUAPC] D6_APC_2: 0x3fffff
9974 12:45:51.465295 INFO: [APUAPC] D6_APC_3: 0x0
9975 12:45:51.468422 INFO: [APUAPC] D7_APC_0: 0xffffffff
9976 12:45:51.475571 INFO: [APUAPC] D7_APC_1: 0xffffffff
9977 12:45:51.477927 INFO: [APUAPC] D7_APC_2: 0x3fffff
9978 12:45:51.478489 INFO: [APUAPC] D7_APC_3: 0x0
9979 12:45:51.481459 INFO: [APUAPC] D8_APC_0: 0xffffffff
9980 12:45:51.484312 INFO: [APUAPC] D8_APC_1: 0xffffffff
9981 12:45:51.488347 INFO: [APUAPC] D8_APC_2: 0x3fffff
9982 12:45:51.491226 INFO: [APUAPC] D8_APC_3: 0x0
9983 12:45:51.494552 INFO: [APUAPC] D9_APC_0: 0xffffffff
9984 12:45:51.498303 INFO: [APUAPC] D9_APC_1: 0xffffffff
9985 12:45:51.501670 INFO: [APUAPC] D9_APC_2: 0x3fffff
9986 12:45:51.504730 INFO: [APUAPC] D9_APC_3: 0x0
9987 12:45:51.508302 INFO: [APUAPC] D10_APC_0: 0xffffffff
9988 12:45:51.511132 INFO: [APUAPC] D10_APC_1: 0xffffffff
9989 12:45:51.513964 INFO: [APUAPC] D10_APC_2: 0x3fffff
9990 12:45:51.517541 INFO: [APUAPC] D10_APC_3: 0x0
9991 12:45:51.521162 INFO: [APUAPC] D11_APC_0: 0xffffffff
9992 12:45:51.527443 INFO: [APUAPC] D11_APC_1: 0xffffffff
9993 12:45:51.530614 INFO: [APUAPC] D11_APC_2: 0x3fffff
9994 12:45:51.531178 INFO: [APUAPC] D11_APC_3: 0x0
9995 12:45:51.538352 INFO: [APUAPC] D12_APC_0: 0xffffffff
9996 12:45:51.540759 INFO: [APUAPC] D12_APC_1: 0xffffffff
9997 12:45:51.544168 INFO: [APUAPC] D12_APC_2: 0x3fffff
9998 12:45:51.544782 INFO: [APUAPC] D12_APC_3: 0x0
9999 12:45:51.550487 INFO: [APUAPC] D13_APC_0: 0xffffffff
10000 12:45:51.553594 INFO: [APUAPC] D13_APC_1: 0xffffffff
10001 12:45:51.557057 INFO: [APUAPC] D13_APC_2: 0x3fffff
10002 12:45:51.560312 INFO: [APUAPC] D13_APC_3: 0x0
10003 12:45:51.564077 INFO: [APUAPC] D14_APC_0: 0xffffffff
10004 12:45:51.566694 INFO: [APUAPC] D14_APC_1: 0xffffffff
10005 12:45:51.570526 INFO: [APUAPC] D14_APC_2: 0x3fffff
10006 12:45:51.573798 INFO: [APUAPC] D14_APC_3: 0x0
10007 12:45:51.577065 INFO: [APUAPC] D15_APC_0: 0xffffffff
10008 12:45:51.580188 INFO: [APUAPC] D15_APC_1: 0xffffffff
10009 12:45:51.583280 INFO: [APUAPC] D15_APC_2: 0x3fffff
10010 12:45:51.586559 INFO: [APUAPC] D15_APC_3: 0x0
10011 12:45:51.587067 INFO: [APUAPC] APC_CON: 0x4
10012 12:45:51.590186 INFO: [NOCDAPC] D0_APC_0: 0x0
10013 12:45:51.593375 INFO: [NOCDAPC] D0_APC_1: 0x0
10014 12:45:51.597250 INFO: [NOCDAPC] D1_APC_0: 0x0
10015 12:45:51.600510 INFO: [NOCDAPC] D1_APC_1: 0xfff
10016 12:45:51.603418 INFO: [NOCDAPC] D2_APC_0: 0x0
10017 12:45:51.606914 INFO: [NOCDAPC] D2_APC_1: 0xfff
10018 12:45:51.609762 INFO: [NOCDAPC] D3_APC_0: 0x0
10019 12:45:51.613226 INFO: [NOCDAPC] D3_APC_1: 0xfff
10020 12:45:51.616632 INFO: [NOCDAPC] D4_APC_0: 0x0
10021 12:45:51.620065 INFO: [NOCDAPC] D4_APC_1: 0xfff
10022 12:45:51.620677 INFO: [NOCDAPC] D5_APC_0: 0x0
10023 12:45:51.623454 INFO: [NOCDAPC] D5_APC_1: 0xfff
10024 12:45:51.626741 INFO: [NOCDAPC] D6_APC_0: 0x0
10025 12:45:51.630339 INFO: [NOCDAPC] D6_APC_1: 0xfff
10026 12:45:51.633051 INFO: [NOCDAPC] D7_APC_0: 0x0
10027 12:45:51.636054 INFO: [NOCDAPC] D7_APC_1: 0xfff
10028 12:45:51.639721 INFO: [NOCDAPC] D8_APC_0: 0x0
10029 12:45:51.642946 INFO: [NOCDAPC] D8_APC_1: 0xfff
10030 12:45:51.646492 INFO: [NOCDAPC] D9_APC_0: 0x0
10031 12:45:51.649858 INFO: [NOCDAPC] D9_APC_1: 0xfff
10032 12:45:51.652723 INFO: [NOCDAPC] D10_APC_0: 0x0
10033 12:45:51.655971 INFO: [NOCDAPC] D10_APC_1: 0xfff
10034 12:45:51.656560 INFO: [NOCDAPC] D11_APC_0: 0x0
10035 12:45:51.659250 INFO: [NOCDAPC] D11_APC_1: 0xfff
10036 12:45:51.662574 INFO: [NOCDAPC] D12_APC_0: 0x0
10037 12:45:51.666016 INFO: [NOCDAPC] D12_APC_1: 0xfff
10038 12:45:51.669225 INFO: [NOCDAPC] D13_APC_0: 0x0
10039 12:45:51.672241 INFO: [NOCDAPC] D13_APC_1: 0xfff
10040 12:45:51.675799 INFO: [NOCDAPC] D14_APC_0: 0x0
10041 12:45:51.679023 INFO: [NOCDAPC] D14_APC_1: 0xfff
10042 12:45:51.682349 INFO: [NOCDAPC] D15_APC_0: 0x0
10043 12:45:51.686143 INFO: [NOCDAPC] D15_APC_1: 0xfff
10044 12:45:51.689358 INFO: [NOCDAPC] APC_CON: 0x4
10045 12:45:51.692641 INFO: [APUAPC] set_apusys_apc done
10046 12:45:51.696153 INFO: [DEVAPC] devapc_init done
10047 12:45:51.699255 INFO: GICv3 without legacy support detected.
10048 12:45:51.702613 INFO: ARM GICv3 driver initialized in EL3
10049 12:45:51.705697 INFO: Maximum SPI INTID supported: 639
10050 12:45:51.712728 INFO: BL31: Initializing runtime services
10051 12:45:51.715707 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10052 12:45:51.719167 INFO: SPM: enable CPC mode
10053 12:45:51.726045 INFO: mcdi ready for mcusys-off-idle and system suspend
10054 12:45:51.729075 INFO: BL31: Preparing for EL3 exit to normal world
10055 12:45:51.732158 INFO: Entry point address = 0x80000000
10056 12:45:51.735343 INFO: SPSR = 0x8
10057 12:45:51.740282
10058 12:45:51.740869
10059 12:45:51.741238
10060 12:45:51.744302 Starting depthcharge on Spherion...
10061 12:45:51.744914
10062 12:45:51.745284 Wipe memory regions:
10063 12:45:51.745683
10064 12:45:51.748127 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10065 12:45:51.748687 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10066 12:45:51.749131 Setting prompt string to ['asurada:']
10067 12:45:51.749600 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10068 12:45:51.750537 [0x00000040000000, 0x00000054600000)
10069 12:45:51.869402
10070 12:45:51.869965 [0x00000054660000, 0x00000080000000)
10071 12:45:52.130685
10072 12:45:52.131255 [0x000000821a7280, 0x000000ffe64000)
10073 12:45:52.874555
10074 12:45:52.875121 [0x00000100000000, 0x00000240000000)
10075 12:45:54.764283
10076 12:45:54.767797 Initializing XHCI USB controller at 0x11200000.
10077 12:45:55.748866
10078 12:45:55.749424 R8152: Initializing
10079 12:45:55.749802
10080 12:45:55.752168 Version 9 (ocp_data = 6010)
10081 12:45:55.752772
10082 12:45:55.755450 R8152: Done initializing
10083 12:45:55.756014
10084 12:45:55.756386 Adding net device
10085 12:45:56.276870
10086 12:45:56.280712 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10087 12:45:56.281279
10088 12:45:56.281650
10089 12:45:56.281990
10090 12:45:56.282774 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 12:45:56.384149 asurada: tftpboot 192.168.201.1 10724910/tftp-deploy-h2rsz2y1/kernel/image.itb 10724910/tftp-deploy-h2rsz2y1/kernel/cmdline
10093 12:45:56.384845 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 12:45:56.385353 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10095 12:45:56.390129 tftpboot 192.168.201.1 10724910/tftp-deploy-h2rsz2y1/kernel/image.ittp-deploy-h2rsz2y1/kernel/cmdline
10096 12:45:56.390710
10097 12:45:56.391084 Waiting for link
10098 12:45:56.592433
10099 12:45:56.593254 done.
10100 12:45:56.593928
10101 12:45:56.594546 MAC: f4:f5:e8:50:de:0a
10102 12:45:56.594915
10103 12:45:56.595579 Sending DHCP discover... done.
10104 12:45:56.595950
10105 12:45:56.598943 Waiting for reply... done.
10106 12:45:56.599627
10107 12:45:56.602201 Sending DHCP request... done.
10108 12:45:56.602615
10109 12:45:56.602961 Waiting for reply... done.
10110 12:45:56.603291
10111 12:45:56.605281 My ip is 192.168.201.14
10112 12:45:56.605743
10113 12:45:56.608833 The DHCP server ip is 192.168.201.1
10114 12:45:56.609400
10115 12:45:56.612051 TFTP server IP predefined by user: 192.168.201.1
10116 12:45:56.612657
10117 12:45:56.619105 Bootfile predefined by user: 10724910/tftp-deploy-h2rsz2y1/kernel/image.itb
10118 12:45:56.619677
10119 12:45:56.622753 Sending tftp read request... done.
10120 12:45:56.623327
10121 12:45:56.630984 Waiting for the transfer...
10122 12:45:56.631544
10123 12:45:56.921278 00000000 ################################################################
10124 12:45:56.921427
10125 12:45:57.161835 00080000 ################################################################
10126 12:45:57.161967
10127 12:45:57.388107 00100000 ################################################################
10128 12:45:57.388238
10129 12:45:57.614158 00180000 ################################################################
10130 12:45:57.614318
10131 12:45:57.840985 00200000 ################################################################
10132 12:45:57.841147
10133 12:45:58.067260 00280000 ################################################################
10134 12:45:58.067392
10135 12:45:58.293319 00300000 ################################################################
10136 12:45:58.293447
10137 12:45:58.519638 00380000 ################################################################
10138 12:45:58.519771
10139 12:45:58.745886 00400000 ################################################################
10140 12:45:58.746020
10141 12:45:58.971790 00480000 ################################################################
10142 12:45:58.971924
10143 12:45:59.199596 00500000 ################################################################
10144 12:45:59.199734
10145 12:45:59.425945 00580000 ################################################################
10146 12:45:59.426082
10147 12:45:59.675263 00600000 ################################################################
10148 12:45:59.675403
10149 12:45:59.903480 00680000 ################################################################
10150 12:45:59.903617
10151 12:46:00.130061 00700000 ################################################################
10152 12:46:00.130205
10153 12:46:00.355451 00780000 ################################################################
10154 12:46:00.355584
10155 12:46:00.581592 00800000 ################################################################
10156 12:46:00.581724
10157 12:46:00.808497 00880000 ################################################################
10158 12:46:00.808682
10159 12:46:01.034517 00900000 ################################################################
10160 12:46:01.034649
10161 12:46:01.260917 00980000 ################################################################
10162 12:46:01.261051
10163 12:46:01.487100 00a00000 ################################################################
10164 12:46:01.487232
10165 12:46:01.713895 00a80000 ################################################################
10166 12:46:01.714031
10167 12:46:01.939235 00b00000 ################################################################
10168 12:46:01.939370
10169 12:46:02.164449 00b80000 ################################################################
10170 12:46:02.164623
10171 12:46:02.390291 00c00000 ################################################################
10172 12:46:02.390423
10173 12:46:02.616191 00c80000 ################################################################
10174 12:46:02.616331
10175 12:46:02.842054 00d00000 ################################################################
10176 12:46:02.842188
10177 12:46:03.068359 00d80000 ################################################################
10178 12:46:03.068496
10179 12:46:03.294427 00e00000 ################################################################
10180 12:46:03.294564
10181 12:46:03.520502 00e80000 ################################################################
10182 12:46:03.520677
10183 12:46:03.746809 00f00000 ################################################################
10184 12:46:03.746948
10185 12:46:03.972903 00f80000 ################################################################
10186 12:46:03.973047
10187 12:46:04.197901 01000000 ################################################################
10188 12:46:04.198040
10189 12:46:04.423862 01080000 ################################################################
10190 12:46:04.424001
10191 12:46:04.649555 01100000 ################################################################
10192 12:46:04.649688
10193 12:46:04.875494 01180000 ################################################################
10194 12:46:04.875634
10195 12:46:05.121181 01200000 ################################################################
10196 12:46:05.121321
10197 12:46:05.347699 01280000 ################################################################
10198 12:46:05.347843
10199 12:46:05.573526 01300000 ################################################################
10200 12:46:05.573665
10201 12:46:05.799192 01380000 ################################################################
10202 12:46:05.799329
10203 12:46:06.025107 01400000 ################################################################
10204 12:46:06.025269
10205 12:46:06.250902 01480000 ################################################################
10206 12:46:06.251040
10207 12:46:06.477446 01500000 ################################################################
10208 12:46:06.477596
10209 12:46:06.703823 01580000 ################################################################
10210 12:46:06.703953
10211 12:46:06.929157 01600000 ################################################################
10212 12:46:06.929290
10213 12:46:07.154936 01680000 ################################################################
10214 12:46:07.155071
10215 12:46:07.381056 01700000 ################################################################
10216 12:46:07.381189
10217 12:46:07.607283 01780000 ################################################################
10218 12:46:07.607416
10219 12:46:07.833680 01800000 ################################################################
10220 12:46:07.833814
10221 12:46:08.060312 01880000 ################################################################
10222 12:46:08.060444
10223 12:46:08.286761 01900000 ################################################################
10224 12:46:08.286895
10225 12:46:08.516963 01980000 ################################################################
10226 12:46:08.517101
10227 12:46:08.743091 01a00000 ################################################################
10228 12:46:08.743227
10229 12:46:08.970826 01a80000 ################################################################
10230 12:46:08.970959
10231 12:46:09.196618 01b00000 ################################################################
10232 12:46:09.196753
10233 12:46:09.422301 01b80000 ################################################################
10234 12:46:09.422431
10235 12:46:09.649044 01c00000 ################################################################
10236 12:46:09.649171
10237 12:46:09.874937 01c80000 ################################################################
10238 12:46:09.875073
10239 12:46:10.140190 01d00000 ################################################################
10240 12:46:10.140354
10241 12:46:10.376751 01d80000 ################################################################
10242 12:46:10.376892
10243 12:46:10.602822 01e00000 ################################################################
10244 12:46:10.602954
10245 12:46:10.829320 01e80000 ################################################################
10246 12:46:10.829456
10247 12:46:11.055616 01f00000 ################################################################
10248 12:46:11.055748
10249 12:46:11.282073 01f80000 ################################################################
10250 12:46:11.282207
10251 12:46:11.509640 02000000 ################################################################
10252 12:46:11.509771
10253 12:46:11.734227 02080000 ################################################################
10254 12:46:11.734361
10255 12:46:11.960077 02100000 ################################################################
10256 12:46:11.960211
10257 12:46:12.190274 02180000 ################################################################
10258 12:46:12.190409
10259 12:46:12.460971 02200000 ################################################################
10260 12:46:12.461108
10261 12:46:12.732355 02280000 ################################################################
10262 12:46:12.732509
10263 12:46:13.003646 02300000 ################################################################
10264 12:46:13.003783
10265 12:46:13.254213 02380000 ################################################################
10266 12:46:13.254358
10267 12:46:13.480286 02400000 ################################################################
10268 12:46:13.480421
10269 12:46:13.715532 02480000 ################################################################
10270 12:46:13.715694
10271 12:46:13.941448 02500000 ################################################################
10272 12:46:13.941583
10273 12:46:14.190565 02580000 ################################################################
10274 12:46:14.190710
10275 12:46:14.427190 02600000 ################################################################
10276 12:46:14.427330
10277 12:46:14.668503 02680000 ################################################################
10278 12:46:14.668645
10279 12:46:14.895118 02700000 ################################################################
10280 12:46:14.895246
10281 12:46:15.121405 02780000 ################################################################
10282 12:46:15.121534
10283 12:46:15.350882 02800000 ################################################################
10284 12:46:15.351058
10285 12:46:15.577349 02880000 ################################################################
10286 12:46:15.577515
10287 12:46:15.803990 02900000 ################################################################
10288 12:46:15.804153
10289 12:46:16.041336 02980000 ################################################################
10290 12:46:16.041492
10291 12:46:16.271227 02a00000 ################################################################
10292 12:46:16.271382
10293 12:46:16.499264 02a80000 ################################################################
10294 12:46:16.499422
10295 12:46:16.726167 02b00000 ################################################################
10296 12:46:16.726342
10297 12:46:16.958423 02b80000 ################################################################
10298 12:46:16.958564
10299 12:46:17.215033 02c00000 ################################################################
10300 12:46:17.215178
10301 12:46:17.480652 02c80000 ################################################################
10302 12:46:17.480800
10303 12:46:17.706607 02d00000 ################################################################
10304 12:46:17.706749
10305 12:46:17.932505 02d80000 ################################################################
10306 12:46:17.932684
10307 12:46:18.158269 02e00000 ################################################################
10308 12:46:18.158407
10309 12:46:18.396729 02e80000 ################################################################
10310 12:46:18.396867
10311 12:46:18.661954 02f00000 ################################################################
10312 12:46:18.662104
10313 12:46:18.899761 02f80000 ################################################################
10314 12:46:18.899908
10315 12:46:19.044130 03000000 ###################################### done.
10316 12:46:19.044278
10317 12:46:19.047899 The bootfile was 50635546 bytes long.
10318 12:46:19.047985
10319 12:46:19.051938 Sending tftp read request... done.
10320 12:46:19.052021
10321 12:46:19.054277 Waiting for the transfer...
10322 12:46:19.054361
10323 12:46:19.054426 00000000 # done.
10324 12:46:19.054488
10325 12:46:19.061167 Command line loaded dynamically from TFTP file: 10724910/tftp-deploy-h2rsz2y1/kernel/cmdline
10326 12:46:19.061252
10327 12:46:19.074238 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10328 12:46:19.074325
10329 12:46:19.074391 Loading FIT.
10330 12:46:19.074451
10331 12:46:19.077649 Image ramdisk-1 has 40144210 bytes.
10332 12:46:19.077733
10333 12:46:19.080887 Image fdt-1 has 46924 bytes.
10334 12:46:19.080970
10335 12:46:19.084160 Image kernel-1 has 10442380 bytes.
10336 12:46:19.084243
10337 12:46:19.093997 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10338 12:46:19.094082
10339 12:46:19.110495 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10340 12:46:19.110586
10341 12:46:19.116789 Choosing best match conf-1 for compat google,spherion-rev2.
10342 12:46:19.116873
10343 12:46:19.124145 Connected to device vid:did:rid of 1ae0:0028:00
10344 12:46:19.131046
10345 12:46:19.134476 tpm_get_response: command 0x17b, return code 0x0
10346 12:46:19.138006
10347 12:46:19.141752 ec_init: CrosEC protocol v3 supported (256, 248)
10348 12:46:19.141835
10349 12:46:19.145238 tpm_cleanup: add release locality here.
10350 12:46:19.145321
10351 12:46:19.147936 Shutting down all USB controllers.
10352 12:46:19.148019
10353 12:46:19.151372 Removing current net device
10354 12:46:19.151455
10355 12:46:19.154717 Exiting depthcharge with code 4 at timestamp: 56809788
10356 12:46:19.154800
10357 12:46:19.157905 LZMA decompressing kernel-1 to 0x821a6718
10358 12:46:19.161591
10359 12:46:19.164477 LZMA decompressing kernel-1 to 0x40000000
10360 12:46:20.474663
10361 12:46:20.474813 jumping to kernel
10362 12:46:20.475248 end: 2.2.4 bootloader-commands (duration 00:00:29) [common]
10363 12:46:20.475359 start: 2.2.5 auto-login-action (timeout 00:03:56) [common]
10364 12:46:20.475435 Setting prompt string to ['Linux version [0-9]']
10365 12:46:20.475517 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10366 12:46:20.475598 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10367 12:46:20.557334
10368 12:46:20.560544 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10369 12:46:20.564496 start: 2.2.5.1 login-action (timeout 00:03:56) [common]
10370 12:46:20.564691 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10371 12:46:20.564777 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10372 12:46:20.564855 Using line separator: #'\n'#
10373 12:46:20.564918 No login prompt set.
10374 12:46:20.564979 Parsing kernel messages
10375 12:46:20.565062 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10376 12:46:20.565162 [login-action] Waiting for messages, (timeout 00:03:56)
10377 12:46:20.583573 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10378 12:46:20.586822 [ 0.000000] random: crng init done
10379 12:46:20.590782 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10380 12:46:20.594010 [ 0.000000] efi: UEFI not found.
10381 12:46:20.603666 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10382 12:46:20.610693 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10383 12:46:20.620075 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10384 12:46:20.630124 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10385 12:46:20.636336 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10386 12:46:20.639541 [ 0.000000] printk: bootconsole [mtk8250] enabled
10387 12:46:20.648825 [ 0.000000] NUMA: No NUMA configuration found
10388 12:46:20.654979 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10389 12:46:20.661588 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10390 12:46:20.661671 [ 0.000000] Zone ranges:
10391 12:46:20.668611 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10392 12:46:20.671607 [ 0.000000] DMA32 empty
10393 12:46:20.678300 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10394 12:46:20.681268 [ 0.000000] Movable zone start for each node
10395 12:46:20.684652 [ 0.000000] Early memory node ranges
10396 12:46:20.691441 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10397 12:46:20.698104 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10398 12:46:20.704276 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10399 12:46:20.710926 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10400 12:46:20.717860 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10401 12:46:20.723908 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10402 12:46:20.780271 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10403 12:46:20.787013 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10404 12:46:20.794021 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10405 12:46:20.796913 [ 0.000000] psci: probing for conduit method from DT.
10406 12:46:20.803310 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10407 12:46:20.806831 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10408 12:46:20.813741 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10409 12:46:20.816723 [ 0.000000] psci: SMC Calling Convention v1.2
10410 12:46:20.822911 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10411 12:46:20.826254 [ 0.000000] Detected VIPT I-cache on CPU0
10412 12:46:20.833405 [ 0.000000] CPU features: detected: GIC system register CPU interface
10413 12:46:20.839630 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10414 12:46:20.845798 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10415 12:46:20.852708 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10416 12:46:20.862532 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10417 12:46:20.869089 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10418 12:46:20.872215 [ 0.000000] alternatives: applying boot alternatives
10419 12:46:20.879336 [ 0.000000] Fallback order for Node 0: 0
10420 12:46:20.885972 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10421 12:46:20.889388 [ 0.000000] Policy zone: Normal
10422 12:46:20.901978 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10423 12:46:20.912146 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10424 12:46:20.922685 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10425 12:46:20.932481 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10426 12:46:20.939365 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10427 12:46:20.942518 <6>[ 0.000000] software IO TLB: area num 8.
10428 12:46:20.999805 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10429 12:46:21.149026 <6>[ 0.000000] Memory: 7931956K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 420812K reserved, 32768K cma-reserved)
10430 12:46:21.155993 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10431 12:46:21.162152 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10432 12:46:21.165251 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10433 12:46:21.171992 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10434 12:46:21.178321 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10435 12:46:21.181473 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10436 12:46:21.191352 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10437 12:46:21.198314 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10438 12:46:21.204890 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10439 12:46:21.211448 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10440 12:46:21.214492 <6>[ 0.000000] GICv3: 608 SPIs implemented
10441 12:46:21.217786 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10442 12:46:21.224456 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10443 12:46:21.227870 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10444 12:46:21.234655 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10445 12:46:21.247784 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10446 12:46:21.261031 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10447 12:46:21.267272 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10448 12:46:21.275335 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10449 12:46:21.288554 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10450 12:46:21.294848 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10451 12:46:21.301622 <6>[ 0.009174] Console: colour dummy device 80x25
10452 12:46:21.311882 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10453 12:46:21.318515 <6>[ 0.024342] pid_max: default: 32768 minimum: 301
10454 12:46:21.321694 <6>[ 0.029215] LSM: Security Framework initializing
10455 12:46:21.328364 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10456 12:46:21.338273 <6>[ 0.041969] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10457 12:46:21.347789 <6>[ 0.051391] cblist_init_generic: Setting adjustable number of callback queues.
10458 12:46:21.354396 <6>[ 0.058889] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 12:46:21.358029 <6>[ 0.065267] cblist_init_generic: Setting shift to 3 and lim to 1.
10460 12:46:21.364416 <6>[ 0.071675] rcu: Hierarchical SRCU implementation.
10461 12:46:21.371342 <6>[ 0.076688] rcu: Max phase no-delay instances is 1000.
10462 12:46:21.377826 <6>[ 0.083738] EFI services will not be available.
10463 12:46:21.380721 <6>[ 0.088712] smp: Bringing up secondary CPUs ...
10464 12:46:21.388935 <6>[ 0.093763] Detected VIPT I-cache on CPU1
10465 12:46:21.395242 <6>[ 0.093836] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10466 12:46:21.401874 <6>[ 0.093868] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10467 12:46:21.405774 <6>[ 0.094207] Detected VIPT I-cache on CPU2
10468 12:46:21.415203 <6>[ 0.094262] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10469 12:46:21.421802 <6>[ 0.094279] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10470 12:46:21.424890 <6>[ 0.094540] Detected VIPT I-cache on CPU3
10471 12:46:21.432028 <6>[ 0.094589] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10472 12:46:21.438257 <6>[ 0.094603] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10473 12:46:21.441916 <6>[ 0.094910] CPU features: detected: Spectre-v4
10474 12:46:21.448151 <6>[ 0.094917] CPU features: detected: Spectre-BHB
10475 12:46:21.451584 <6>[ 0.094923] Detected PIPT I-cache on CPU4
10476 12:46:21.458229 <6>[ 0.094982] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10477 12:46:21.464842 <6>[ 0.094998] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10478 12:46:21.471671 <6>[ 0.095297] Detected PIPT I-cache on CPU5
10479 12:46:21.477611 <6>[ 0.095361] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10480 12:46:21.484471 <6>[ 0.095377] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10481 12:46:21.487753 <6>[ 0.095661] Detected PIPT I-cache on CPU6
10482 12:46:21.494653 <6>[ 0.095727] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10483 12:46:21.504177 <6>[ 0.095744] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10484 12:46:21.507555 <6>[ 0.096044] Detected PIPT I-cache on CPU7
10485 12:46:21.513973 <6>[ 0.096109] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10486 12:46:21.520970 <6>[ 0.096125] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10487 12:46:21.524555 <6>[ 0.096173] smp: Brought up 1 node, 8 CPUs
10488 12:46:21.530469 <6>[ 0.237423] SMP: Total of 8 processors activated.
10489 12:46:21.533760 <6>[ 0.242345] CPU features: detected: 32-bit EL0 Support
10490 12:46:21.544052 <6>[ 0.247741] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10491 12:46:21.550545 <6>[ 0.256541] CPU features: detected: Common not Private translations
10492 12:46:21.557123 <6>[ 0.263017] CPU features: detected: CRC32 instructions
10493 12:46:21.565225 <6>[ 0.268402] CPU features: detected: RCpc load-acquire (LDAPR)
10494 12:46:21.567267 <6>[ 0.274398] CPU features: detected: LSE atomic instructions
10495 12:46:21.573404 <6>[ 0.280179] CPU features: detected: Privileged Access Never
10496 12:46:21.580175 <6>[ 0.285959] CPU features: detected: RAS Extension Support
10497 12:46:21.586428 <6>[ 0.291568] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10498 12:46:21.589800 <6>[ 0.298833] CPU: All CPU(s) started at EL2
10499 12:46:21.596465 <6>[ 0.303149] alternatives: applying system-wide alternatives
10500 12:46:21.606370 <6>[ 0.313863] devtmpfs: initialized
10501 12:46:21.618486 <6>[ 0.322684] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10502 12:46:21.628656 <6>[ 0.332647] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10503 12:46:21.635065 <6>[ 0.340902] pinctrl core: initialized pinctrl subsystem
10504 12:46:21.638359 <6>[ 0.347569] DMI not present or invalid.
10505 12:46:21.645570 <6>[ 0.351977] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10506 12:46:21.654987 <6>[ 0.358781] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10507 12:46:21.661420 <6>[ 0.366359] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10508 12:46:21.672221 <6>[ 0.374581] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10509 12:46:21.675056 <6>[ 0.382826] audit: initializing netlink subsys (disabled)
10510 12:46:21.684557 <5>[ 0.388518] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10511 12:46:21.691452 <6>[ 0.389215] thermal_sys: Registered thermal governor 'step_wise'
10512 12:46:21.698483 <6>[ 0.396485] thermal_sys: Registered thermal governor 'power_allocator'
10513 12:46:21.701940 <6>[ 0.402739] cpuidle: using governor menu
10514 12:46:21.708276 <6>[ 0.413693] NET: Registered PF_QIPCRTR protocol family
10515 12:46:21.714172 <6>[ 0.419167] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10516 12:46:21.720909 <6>[ 0.426270] ASID allocator initialised with 32768 entries
10517 12:46:21.724193 <6>[ 0.432832] Serial: AMBA PL011 UART driver
10518 12:46:21.734230 <4>[ 0.441465] Trying to register duplicate clock ID: 134
10519 12:46:21.787990 <6>[ 0.498752] KASLR enabled
10520 12:46:21.802280 <6>[ 0.506414] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10521 12:46:21.808747 <6>[ 0.513427] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10522 12:46:21.815981 <6>[ 0.519918] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10523 12:46:21.821890 <6>[ 0.526924] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10524 12:46:21.828726 <6>[ 0.533412] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10525 12:46:21.835180 <6>[ 0.540416] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10526 12:46:21.841763 <6>[ 0.546904] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10527 12:46:21.848723 <6>[ 0.553907] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10528 12:46:21.851541 <6>[ 0.561374] ACPI: Interpreter disabled.
10529 12:46:21.860559 <6>[ 0.567784] iommu: Default domain type: Translated
10530 12:46:21.867298 <6>[ 0.572897] iommu: DMA domain TLB invalidation policy: strict mode
10531 12:46:21.870330 <5>[ 0.579555] SCSI subsystem initialized
10532 12:46:21.876765 <6>[ 0.583793] usbcore: registered new interface driver usbfs
10533 12:46:21.883227 <6>[ 0.589522] usbcore: registered new interface driver hub
10534 12:46:21.886774 <6>[ 0.595075] usbcore: registered new device driver usb
10535 12:46:21.893751 <6>[ 0.601174] pps_core: LinuxPPS API ver. 1 registered
10536 12:46:21.903556 <6>[ 0.606366] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10537 12:46:21.907067 <6>[ 0.615711] PTP clock support registered
10538 12:46:21.910483 <6>[ 0.619948] EDAC MC: Ver: 3.0.0
10539 12:46:21.918040 <6>[ 0.625119] FPGA manager framework
10540 12:46:21.924653 <6>[ 0.628797] Advanced Linux Sound Architecture Driver Initialized.
10541 12:46:21.927759 <6>[ 0.635566] vgaarb: loaded
10542 12:46:21.934124 <6>[ 0.638731] clocksource: Switched to clocksource arch_sys_counter
10543 12:46:21.937114 <5>[ 0.645179] VFS: Disk quotas dquot_6.6.0
10544 12:46:21.944001 <6>[ 0.649361] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10545 12:46:21.947069 <6>[ 0.656552] pnp: PnP ACPI: disabled
10546 12:46:21.955887 <6>[ 0.663210] NET: Registered PF_INET protocol family
10547 12:46:21.965687 <6>[ 0.668809] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10548 12:46:21.977156 <6>[ 0.681107] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10549 12:46:21.987785 <6>[ 0.689922] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10550 12:46:21.993495 <6>[ 0.697890] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10551 12:46:22.003175 <6>[ 0.706588] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10552 12:46:22.009969 <6>[ 0.716329] TCP: Hash tables configured (established 65536 bind 65536)
10553 12:46:22.016119 <6>[ 0.723183] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10554 12:46:22.026366 <6>[ 0.730382] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10555 12:46:22.032721 <6>[ 0.738079] NET: Registered PF_UNIX/PF_LOCAL protocol family
10556 12:46:22.039796 <6>[ 0.744172] RPC: Registered named UNIX socket transport module.
10557 12:46:22.043300 <6>[ 0.750327] RPC: Registered udp transport module.
10558 12:46:22.049538 <6>[ 0.755262] RPC: Registered tcp transport module.
10559 12:46:22.055867 <6>[ 0.760192] RPC: Registered tcp NFSv4.1 backchannel transport module.
10560 12:46:22.059231 <6>[ 0.766860] PCI: CLS 0 bytes, default 64
10561 12:46:22.062457 <6>[ 0.771232] Unpacking initramfs...
10562 12:46:22.079415 <6>[ 0.783268] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10563 12:46:22.089468 <6>[ 0.791907] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10564 12:46:22.092304 <6>[ 0.800736] kvm [1]: IPA Size Limit: 40 bits
10565 12:46:22.098903 <6>[ 0.805262] kvm [1]: GICv3: no GICV resource entry
10566 12:46:22.102358 <6>[ 0.810282] kvm [1]: disabling GICv2 emulation
10567 12:46:22.108874 <6>[ 0.814969] kvm [1]: GIC system register CPU interface enabled
10568 12:46:22.112222 <6>[ 0.821129] kvm [1]: vgic interrupt IRQ18
10569 12:46:22.119485 <6>[ 0.825491] kvm [1]: VHE mode initialized successfully
10570 12:46:22.125950 <5>[ 0.831867] Initialise system trusted keyrings
10571 12:46:22.131918 <6>[ 0.836672] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10572 12:46:22.139060 <6>[ 0.846585] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10573 12:46:22.146016 <5>[ 0.852934] NFS: Registering the id_resolver key type
10574 12:46:22.149050 <5>[ 0.858235] Key type id_resolver registered
10575 12:46:22.155599 <5>[ 0.862650] Key type id_legacy registered
10576 12:46:22.162379 <6>[ 0.866926] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10577 12:46:22.168721 <6>[ 0.873847] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10578 12:46:22.175346 <6>[ 0.881556] 9p: Installing v9fs 9p2000 file system support
10579 12:46:22.212253 <5>[ 0.919599] Key type asymmetric registered
10580 12:46:22.215838 <5>[ 0.923930] Asymmetric key parser 'x509' registered
10581 12:46:22.225275 <6>[ 0.929074] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10582 12:46:22.228546 <6>[ 0.936688] io scheduler mq-deadline registered
10583 12:46:22.232319 <6>[ 0.941471] io scheduler kyber registered
10584 12:46:22.251006 <6>[ 0.958267] EINJ: ACPI disabled.
10585 12:46:22.282423 <4>[ 0.983290] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 12:46:22.292413 <4>[ 0.993905] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10587 12:46:22.307480 <6>[ 1.014467] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10588 12:46:22.315126 <6>[ 1.022422] printk: console [ttyS0] disabled
10589 12:46:22.342798 <6>[ 1.047068] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10590 12:46:22.350004 <6>[ 1.056544] printk: console [ttyS0] enabled
10591 12:46:22.352983 <6>[ 1.056544] printk: console [ttyS0] enabled
10592 12:46:22.359504 <6>[ 1.065437] printk: bootconsole [mtk8250] disabled
10593 12:46:22.362892 <6>[ 1.065437] printk: bootconsole [mtk8250] disabled
10594 12:46:22.369430 <6>[ 1.076793] SuperH (H)SCI(F) driver initialized
10595 12:46:22.372689 <6>[ 1.082073] msm_serial: driver initialized
10596 12:46:22.387175 <6>[ 1.091013] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10597 12:46:22.397304 <6>[ 1.099556] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10598 12:46:22.403489 <6>[ 1.108099] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10599 12:46:22.414057 <6>[ 1.116726] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10600 12:46:22.423709 <6>[ 1.125431] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10601 12:46:22.429700 <6>[ 1.134144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10602 12:46:22.439922 <6>[ 1.142685] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10603 12:46:22.446247 <6>[ 1.151486] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10604 12:46:22.456487 <6>[ 1.160031] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10605 12:46:22.468424 <6>[ 1.175782] loop: module loaded
10606 12:46:22.475111 <6>[ 1.181557] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10607 12:46:22.497230 <4>[ 1.204926] mtk-pmic-keys: Failed to locate of_node [id: -1]
10608 12:46:22.504336 <6>[ 1.211732] megasas: 07.719.03.00-rc1
10609 12:46:22.513801 <6>[ 1.221308] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10610 12:46:22.523883 <6>[ 1.230112] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10611 12:46:22.539465 <6>[ 1.246790] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10612 12:46:22.601086 <6>[ 1.300875] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10613 12:46:23.680732 <6>[ 2.388315] Freeing initrd memory: 39196K
10614 12:46:23.691174 <6>[ 2.398627] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10615 12:46:23.701700 <6>[ 2.409502] tun: Universal TUN/TAP device driver, 1.6
10616 12:46:23.705250 <6>[ 2.415541] thunder_xcv, ver 1.0
10617 12:46:23.709216 <6>[ 2.419047] thunder_bgx, ver 1.0
10618 12:46:23.711655 <6>[ 2.422538] nicpf, ver 1.0
10619 12:46:23.722394 <6>[ 2.426530] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10620 12:46:23.725427 <6>[ 2.434006] hns3: Copyright (c) 2017 Huawei Corporation.
10621 12:46:23.732096 <6>[ 2.439595] hclge is initializing
10622 12:46:23.735250 <6>[ 2.443176] e1000: Intel(R) PRO/1000 Network Driver
10623 12:46:23.742176 <6>[ 2.448306] e1000: Copyright (c) 1999-2006 Intel Corporation.
10624 12:46:23.748581 <6>[ 2.454322] e1000e: Intel(R) PRO/1000 Network Driver
10625 12:46:23.751548 <6>[ 2.459538] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10626 12:46:23.759002 <6>[ 2.465722] igb: Intel(R) Gigabit Ethernet Network Driver
10627 12:46:23.765367 <6>[ 2.471373] igb: Copyright (c) 2007-2014 Intel Corporation.
10628 12:46:23.771459 <6>[ 2.477208] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10629 12:46:23.778608 <6>[ 2.483726] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10630 12:46:23.781408 <6>[ 2.490183] sky2: driver version 1.30
10631 12:46:23.788167 <6>[ 2.495153] VFIO - User Level meta-driver version: 0.3
10632 12:46:23.796093 <6>[ 2.503337] usbcore: registered new interface driver usb-storage
10633 12:46:23.802199 <6>[ 2.509777] usbcore: registered new device driver onboard-usb-hub
10634 12:46:23.811487 <6>[ 2.518851] mt6397-rtc mt6359-rtc: registered as rtc0
10635 12:46:23.821111 <6>[ 2.524313] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:46:23 UTC (1686746783)
10636 12:46:23.824231 <6>[ 2.533863] i2c_dev: i2c /dev entries driver
10637 12:46:23.841268 <6>[ 2.545478] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10638 12:46:23.848304 <6>[ 2.555621] sdhci: Secure Digital Host Controller Interface driver
10639 12:46:23.854528 <6>[ 2.562060] sdhci: Copyright(c) Pierre Ossman
10640 12:46:23.861186 <6>[ 2.567457] Synopsys Designware Multimedia Card Interface Driver
10641 12:46:23.864547 <6>[ 2.574055] mmc0: CQHCI version 5.10
10642 12:46:23.870953 <6>[ 2.574596] sdhci-pltfm: SDHCI platform and OF driver helper
10643 12:46:23.878149 <6>[ 2.585894] ledtrig-cpu: registered to indicate activity on CPUs
10644 12:46:23.889354 <6>[ 2.593250] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10645 12:46:23.895647 <6>[ 2.600639] usbcore: registered new interface driver usbhid
10646 12:46:23.898762 <6>[ 2.606472] usbhid: USB HID core driver
10647 12:46:23.905333 <6>[ 2.610707] spi_master spi0: will run message pump with realtime priority
10648 12:46:23.954644 <6>[ 2.655049] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10649 12:46:23.973567 <6>[ 2.671118] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10650 12:46:23.977079 <6>[ 2.684701] mmc0: Command Queue Engine enabled
10651 12:46:23.984038 <6>[ 2.687204] cros-ec-spi spi0.0: Chrome EC device registered
10652 12:46:23.990600 <6>[ 2.689437] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10653 12:46:23.993997 <6>[ 2.702592] mmcblk0: mmc0:0001 DA4128 116 GiB
10654 12:46:24.009232 <6>[ 2.713331] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10655 12:46:24.015928 <6>[ 2.715183] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10656 12:46:24.022344 <6>[ 2.724765] NET: Registered PF_PACKET protocol family
10657 12:46:24.025508 <6>[ 2.729916] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10658 12:46:24.032006 <6>[ 2.734002] 9pnet: Installing 9P2000 support
10659 12:46:24.035486 <6>[ 2.739798] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10660 12:46:24.041874 <5>[ 2.743664] Key type dns_resolver registered
10661 12:46:24.048431 <6>[ 2.749514] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10662 12:46:24.051661 <6>[ 2.753943] registered taskstats version 1
10663 12:46:24.058806 <5>[ 2.764291] Loading compiled-in X.509 certificates
10664 12:46:24.090536 <4>[ 2.791375] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10665 12:46:24.100365 <4>[ 2.802094] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 12:46:24.110689 <3>[ 2.815199] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10667 12:46:24.123416 <6>[ 2.830999] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10668 12:46:24.130003 <6>[ 2.837811] xhci-mtk 11200000.usb: xHCI Host Controller
10669 12:46:24.136456 <6>[ 2.843319] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10670 12:46:24.146959 <6>[ 2.851176] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10671 12:46:24.153436 <6>[ 2.860616] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10672 12:46:24.160397 <6>[ 2.866794] xhci-mtk 11200000.usb: xHCI Host Controller
10673 12:46:24.166755 <6>[ 2.872291] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10674 12:46:24.173286 <6>[ 2.879948] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10675 12:46:24.180063 <6>[ 2.887831] hub 1-0:1.0: USB hub found
10676 12:46:24.183130 <6>[ 2.891888] hub 1-0:1.0: 1 port detected
10677 12:46:24.193507 <6>[ 2.896235] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10678 12:46:24.196421 <6>[ 2.904849] hub 2-0:1.0: USB hub found
10679 12:46:24.200089 <6>[ 2.908864] hub 2-0:1.0: 1 port detected
10680 12:46:24.208637 <6>[ 2.915979] mtk-msdc 11f70000.mmc: Got CD GPIO
10681 12:46:24.226058 <6>[ 2.930332] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10682 12:46:24.232773 <6>[ 2.938382] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10683 12:46:24.242411 <4>[ 2.946367] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10684 12:46:24.252275 <6>[ 2.956032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10685 12:46:24.258823 <6>[ 2.964117] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10686 12:46:24.268947 <6>[ 2.972154] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10687 12:46:24.275608 <6>[ 2.980074] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10688 12:46:24.282519 <6>[ 2.987896] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10689 12:46:24.291935 <6>[ 2.995718] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10690 12:46:24.302603 <6>[ 3.006377] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10691 12:46:24.312099 <6>[ 3.014752] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10692 12:46:24.318671 <6>[ 3.023110] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10693 12:46:24.329458 <6>[ 3.031454] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10694 12:46:24.335202 <6>[ 3.039797] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10695 12:46:24.345831 <6>[ 3.048140] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10696 12:46:24.351815 <6>[ 3.056483] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10697 12:46:24.361669 <6>[ 3.064826] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10698 12:46:24.367922 <6>[ 3.073169] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10699 12:46:24.378335 <6>[ 3.081511] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10700 12:46:24.384467 <6>[ 3.089854] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10701 12:46:24.394603 <6>[ 3.098196] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10702 12:46:24.401538 <6>[ 3.106540] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10703 12:46:24.411176 <6>[ 3.114890] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10704 12:46:24.417583 <6>[ 3.123237] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10705 12:46:24.424828 <6>[ 3.132109] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10706 12:46:24.432206 <6>[ 3.139582] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10707 12:46:24.438965 <6>[ 3.146667] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10708 12:46:24.449480 <6>[ 3.153806] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10709 12:46:24.455880 <6>[ 3.161110] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10710 12:46:24.465854 <6>[ 3.168099] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10711 12:46:24.472760 <6>[ 3.177252] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10712 12:46:24.482294 <6>[ 3.186379] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10713 12:46:24.492181 <6>[ 3.195682] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10714 12:46:24.502235 <6>[ 3.205156] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10715 12:46:24.512411 <6>[ 3.214630] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10716 12:46:24.522197 <6>[ 3.223758] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10717 12:46:24.529033 <6>[ 3.233237] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10718 12:46:24.538700 <6>[ 3.242372] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10719 12:46:24.548293 <6>[ 3.251674] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10720 12:46:24.558375 <6>[ 3.261841] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10721 12:46:24.569415 <6>[ 3.273821] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10722 12:46:24.590583 <6>[ 3.295155] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10723 12:46:24.619684 <6>[ 3.327177] hub 2-1:1.0: USB hub found
10724 12:46:24.622776 <6>[ 3.331697] hub 2-1:1.0: 3 ports detected
10725 12:46:24.742610 <6>[ 3.446973] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10726 12:46:24.895399 <6>[ 3.602825] hub 1-1:1.0: USB hub found
10727 12:46:24.898339 <6>[ 3.607187] hub 1-1:1.0: 4 ports detected
10728 12:46:25.218481 <6>[ 3.923002] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10729 12:46:25.349005 <6>[ 4.056890] hub 1-1.1:1.0: USB hub found
10730 12:46:25.352466 <6>[ 4.061171] hub 1-1.1:1.0: 4 ports detected
10731 12:46:25.466131 <6>[ 4.170780] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10732 12:46:25.599270 <6>[ 4.307191] hub 1-1.4:1.0: USB hub found
10733 12:46:25.602683 <6>[ 4.311839] hub 1-1.4:1.0: 2 ports detected
10734 12:46:25.678758 <6>[ 4.383000] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10735 12:46:25.866585 <6>[ 4.571000] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10736 12:46:25.951268 <3>[ 4.659211] usb 1-1.1.4: device descriptor read/64, error -32
10737 12:46:26.143387 <3>[ 4.851234] usb 1-1.1.4: device descriptor read/64, error -32
10738 12:46:26.338329 <6>[ 5.043002] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10739 12:46:26.526229 <6>[ 5.231012] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10740 12:46:26.611326 <3>[ 5.319173] usb 1-1.1.4: device descriptor read/64, error -32
10741 12:46:26.803213 <3>[ 5.511207] usb 1-1.1.4: device descriptor read/64, error -32
10742 12:46:26.915972 <6>[ 5.623565] usb 1-1.1-port4: attempt power cycle
10743 12:46:27.002393 <6>[ 5.707082] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10744 12:46:27.526135 <6>[ 6.231014] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10745 12:46:27.532670 <4>[ 6.238467] usb 1-1.1.4: Device not responding to setup address.
10746 12:46:27.743890 <4>[ 6.451202] usb 1-1.1.4: Device not responding to setup address.
10747 12:46:27.955380 <3>[ 6.662990] usb 1-1.1.4: device not accepting address 10, error -71
10748 12:46:28.042524 <6>[ 6.747002] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10749 12:46:28.048681 <4>[ 6.754471] usb 1-1.1.4: Device not responding to setup address.
10750 12:46:28.259336 <4>[ 6.967298] usb 1-1.1.4: Device not responding to setup address.
10751 12:46:28.471424 <3>[ 7.179024] usb 1-1.1.4: device not accepting address 11, error -71
10752 12:46:28.477961 <3>[ 7.185930] usb 1-1.1-port4: unable to enumerate USB device
10753 12:46:36.851450 <6>[ 15.563552] ALSA device list:
10754 12:46:36.857743 <6>[ 15.566809] No soundcards found.
10755 12:46:36.870137 <6>[ 15.579214] Freeing unused kernel memory: 8384K
10756 12:46:36.873440 <6>[ 15.584121] Run /init as init process
10757 12:46:36.904194 <6>[ 15.613336] NET: Registered PF_INET6 protocol family
10758 12:46:36.911129 <6>[ 15.620138] Segment Routing with IPv6
10759 12:46:36.914639 <6>[ 15.624090] In-situ OAM (IOAM) with IPv6
10760 12:46:36.949264 <30>[ 15.638598] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10761 12:46:36.952329 <30>[ 15.662612] systemd[1]: Detected architecture arm64.
10762 12:46:36.956081
10763 12:46:36.959337 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10764 12:46:36.959412
10765 12:46:36.974059 <30>[ 15.683146] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10766 12:46:37.131187 <30>[ 15.836531] systemd[1]: Queued start job for default target Graphical Interface.
10767 12:46:37.179062 <30>[ 15.888178] systemd[1]: Created slice system-getty.slice.
10768 12:46:37.186038 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10769 12:46:37.202732 <30>[ 15.911637] systemd[1]: Created slice system-modprobe.slice.
10770 12:46:37.209317 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10771 12:46:37.226960 <30>[ 15.936148] systemd[1]: Created slice system-serial\x2dgetty.slice.
10772 12:46:37.237322 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10773 12:46:37.251287 <30>[ 15.959484] systemd[1]: Created slice User and Session Slice.
10774 12:46:37.257167 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10775 12:46:37.277770 <30>[ 15.983560] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10776 12:46:37.287460 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10777 12:46:37.305425 <30>[ 16.011171] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10778 12:46:37.311979 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10779 12:46:37.332707 <30>[ 16.035090] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10780 12:46:37.338862 <30>[ 16.047128] systemd[1]: Reached target Local Encrypted Volumes.
10781 12:46:37.345724 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10782 12:46:37.362057 <30>[ 16.071358] systemd[1]: Reached target Paths.
10783 12:46:37.365613 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10784 12:46:37.381719 <30>[ 16.091040] systemd[1]: Reached target Remote File Systems.
10785 12:46:37.388743 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10786 12:46:37.401958 <30>[ 16.111035] systemd[1]: Reached target Slices.
10787 12:46:37.405571 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10788 12:46:37.422068 <30>[ 16.131040] systemd[1]: Reached target Swap.
10789 12:46:37.425651 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10790 12:46:37.445895 <30>[ 16.151364] systemd[1]: Listening on initctl Compatibility Named Pipe.
10791 12:46:37.452153 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10792 12:46:37.458601 <30>[ 16.166053] systemd[1]: Listening on Journal Audit Socket.
10793 12:46:37.465123 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10794 12:46:37.478312 <30>[ 16.187299] systemd[1]: Listening on Journal Socket (/dev/log).
10795 12:46:37.484790 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10796 12:46:37.502284 <30>[ 16.211324] systemd[1]: Listening on Journal Socket.
10797 12:46:37.509056 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10798 12:46:37.525977 <30>[ 16.231347] systemd[1]: Listening on Network Service Netlink Socket.
10799 12:46:37.532005 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10800 12:46:37.547012 <30>[ 16.255779] systemd[1]: Listening on udev Control Socket.
10801 12:46:37.553584 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10802 12:46:37.570549 <30>[ 16.279710] systemd[1]: Listening on udev Kernel Socket.
10803 12:46:37.577227 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10804 12:46:37.609918 <30>[ 16.319123] systemd[1]: Mounting Huge Pages File System...
10805 12:46:37.616574 Mounting [0;1;39mHuge Pages File System[0m...
10806 12:46:37.631894 <30>[ 16.340975] systemd[1]: Mounting POSIX Message Queue File System...
10807 12:46:37.638708 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10808 12:46:37.656065 <30>[ 16.365121] systemd[1]: Mounting Kernel Debug File System...
10809 12:46:37.662467 Mounting [0;1;39mKernel Debug File System[0m...
10810 12:46:37.681263 <30>[ 16.387293] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10811 12:46:37.692566 <30>[ 16.398225] systemd[1]: Starting Create list of static device nodes for the current kernel...
10812 12:46:37.699715 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10813 12:46:37.716710 <30>[ 16.425382] systemd[1]: Starting Load Kernel Module configfs...
10814 12:46:37.722685 Starting [0;1;39mLoad Kernel Module configfs[0m...
10815 12:46:37.740282 <30>[ 16.449431] systemd[1]: Starting Load Kernel Module drm...
10816 12:46:37.747452 Starting [0;1;39mLoad Kernel Module drm[0m...
10817 12:46:37.765296 <30>[ 16.471172] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10818 12:46:37.776493 <30>[ 16.485021] systemd[1]: Starting Journal Service...
10819 12:46:37.778841 Starting [0;1;39mJournal Service[0m...
10820 12:46:37.796890 <30>[ 16.505569] systemd[1]: Starting Load Kernel Modules...
10821 12:46:37.803028 Starting [0;1;39mLoad Kernel Modules[0m...
10822 12:46:37.823957 <30>[ 16.530134] systemd[1]: Starting Remount Root and Kernel File Systems...
10823 12:46:37.830418 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10824 12:46:37.848382 <30>[ 16.557574] systemd[1]: Starting Coldplug All udev Devices...
10825 12:46:37.854937 Starting [0;1;39mColdplug All udev Devices[0m...
10826 12:46:37.873068 <30>[ 16.581783] systemd[1]: Mounted Huge Pages File System.
10827 12:46:37.879299 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10828 12:46:37.895030 <30>[ 16.603685] systemd[1]: Started Journal Service.
10829 12:46:37.901390 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10830 12:46:37.915444 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10831 12:46:37.930927 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10832 12:46:37.950916 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10833 12:46:37.967982 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10834 12:46:37.983749 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10835 12:46:37.999299 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10836 12:46:38.019133 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10837 12:46:38.034480 See 'systemctl status systemd-remount-fs.service' for details.
10838 12:46:38.087321 Mounting [0;1;39mKernel Configuration File System[0m...
10839 12:46:38.104669 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10840 12:46:38.122049 <46>[ 16.828116] systemd-journald[176]: Received client request to flush runtime journal.
10841 12:46:38.131395 Starting [0;1;39mLoad/Save Random Seed[0m...
10842 12:46:38.149281 Starting [0;1;39mApply Kernel Variables[0m...
10843 12:46:38.165587 Starting [0;1;39mCreate System Users[0m...
10844 12:46:38.187466 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10845 12:46:38.210704 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10846 12:46:38.222979 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10847 12:46:38.239011 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10848 12:46:38.256138 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10849 12:46:38.270582 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10850 12:46:38.306347 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10851 12:46:38.328363 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10852 12:46:38.342365 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10853 12:46:38.358164 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10854 12:46:38.398352 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10855 12:46:38.421468 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10856 12:46:38.439482 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10857 12:46:38.459474 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10858 12:46:38.520239 Starting [0;1;39mNetwork Service[0m...
10859 12:46:38.539044 Starting [0;1;39mNetwork Time Synchronization[0m...
10860 12:46:38.560149 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10861 12:46:38.599989 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10862 12:46:38.626824 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10863 12:46:38.646919 <6>[ 17.352839] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10864 12:46:38.659301 <6>[ 17.368605] remoteproc remoteproc0: scp is available
10865 12:46:38.668245 <6>[ 17.377413] remoteproc remoteproc0: powering up scp
10866 12:46:38.678336 <6>[ 17.383871] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10867 12:46:38.684312 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10868 12:46:38.695260 <3>[ 17.401152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 12:46:38.702063 <6>[ 17.406413] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10870 12:46:38.708729 <6>[ 17.412150] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10871 12:46:38.715320 <3>[ 17.412754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 12:46:38.724973 <3>[ 17.412770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 12:46:38.731728 <3>[ 17.413198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 12:46:38.741528 <3>[ 17.413216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 12:46:38.748391 <3>[ 17.413224] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 12:46:38.758020 <3>[ 17.413234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10877 12:46:38.764444 <3>[ 17.413242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 12:46:38.774293 <3>[ 17.413289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 12:46:38.781941 <3>[ 17.413338] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10880 12:46:38.788079 <3>[ 17.413346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 12:46:38.797500 <3>[ 17.413353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 12:46:38.804093 <3>[ 17.413397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 12:46:38.814336 <3>[ 17.413405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 12:46:38.820535 <3>[ 17.413412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 12:46:38.830950 <3>[ 17.413420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 12:46:38.837243 <3>[ 17.413426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 12:46:38.847564 <6>[ 17.418056] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10888 12:46:38.854325 <6>[ 17.418082] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10889 12:46:38.864312 <6>[ 17.418092] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10890 12:46:38.867491 <6>[ 17.491415] mc: Linux media interface: v0.10
10891 12:46:38.874595 <4>[ 17.491534] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10892 12:46:38.883773 <4>[ 17.506346] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10893 12:46:38.890844 <3>[ 17.515162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 12:46:38.900460 <4>[ 17.528654] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10895 12:46:38.904437 <4>[ 17.528654] Fallback method does not support PEC.
10896 12:46:38.910559 <6>[ 17.540693] usbcore: registered new interface driver r8152
10897 12:46:38.917987 <6>[ 17.541201] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10898 12:46:38.920861 <6>[ 17.541215] pci_bus 0000:00: root bus resource [bus 00-ff]
10899 12:46:38.931127 <6>[ 17.541221] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10900 12:46:38.940729 <6>[ 17.541231] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10901 12:46:38.947765 <6>[ 17.541274] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10902 12:46:38.953971 <6>[ 17.541312] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10903 12:46:38.957568 <6>[ 17.541399] pci 0000:00:00.0: supports D1 D2
10904 12:46:38.963883 <6>[ 17.541404] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10905 12:46:38.973595 <6>[ 17.544141] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10906 12:46:38.981158 <6>[ 17.548376] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10907 12:46:38.990248 <6>[ 17.548392] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10908 12:46:38.996792 <6>[ 17.548394] remoteproc remoteproc0: remote processor scp is now up
10909 12:46:39.003446 <3>[ 17.578162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 12:46:39.010010 <6>[ 17.582412] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10911 12:46:39.020145 <3>[ 17.627827] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 12:46:39.026476 <6>[ 17.631206] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10913 12:46:39.037003 <3>[ 17.631888] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10914 12:46:39.046781 <6>[ 17.643861] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10915 12:46:39.053343 <6>[ 17.644398] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10916 12:46:39.063454 <6>[ 17.659312] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10917 12:46:39.070550 <6>[ 17.660285] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10918 12:46:39.077664 <6>[ 17.668697] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10919 12:46:39.088070 <6>[ 17.672476] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10920 12:46:39.091543 <6>[ 17.672773] pci 0000:01:00.0: supports D1 D2
10921 12:46:39.098016 <6>[ 17.693331] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10922 12:46:39.104997 <6>[ 17.696522] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10923 12:46:39.111643 <6>[ 17.697608] videodev: Linux video capture interface: v2.00
10924 12:46:39.114593 <6>[ 17.704446] Bluetooth: Core ver 2.22
10925 12:46:39.121551 <6>[ 17.710338] usbcore: registered new interface driver cdc_ether
10926 12:46:39.127896 <6>[ 17.718628] NET: Registered PF_BLUETOOTH protocol family
10927 12:46:39.134695 <6>[ 17.726819] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10928 12:46:39.142285 <6>[ 17.733621] Bluetooth: HCI device and connection manager initialized
10929 12:46:39.148639 <6>[ 17.733637] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10930 12:46:39.155271 <6>[ 17.733640] Bluetooth: HCI socket layer initialized
10931 12:46:39.158353 <6>[ 17.733647] Bluetooth: L2CAP socket layer initialized
10932 12:46:39.165567 <6>[ 17.733658] Bluetooth: SCO socket layer initialized
10933 12:46:39.172197 <6>[ 17.741162] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10934 12:46:39.179000 <6>[ 17.741825] usbcore: registered new interface driver r8153_ecm
10935 12:46:39.185503 <6>[ 17.752114] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10936 12:46:39.195787 <6>[ 17.759305] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10937 12:46:39.201845 <6>[ 17.768382] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10938 12:46:39.212830 <6>[ 17.769692] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10939 12:46:39.219411 <6>[ 17.769839] usbcore: registered new interface driver uvcvideo
10940 12:46:39.225778 <6>[ 17.776849] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10941 12:46:39.232260 <6>[ 17.785353] usbcore: registered new interface driver btusb
10942 12:46:39.242441 <4>[ 17.785854] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10943 12:46:39.249352 <3>[ 17.785871] Bluetooth: hci0: Failed to load firmware file (-2)
10944 12:46:39.255689 <3>[ 17.785876] Bluetooth: hci0: Failed to set up firmware (-2)
10945 12:46:39.265432 <4>[ 17.785880] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10946 12:46:39.272062 <6>[ 17.793376] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10947 12:46:39.281654 <6>[ 17.793393] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10948 12:46:39.291652 <3>[ 17.793480] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10949 12:46:39.298404 <4>[ 17.794192] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10950 12:46:39.308403 <4>[ 17.794202] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10951 12:46:39.318623 <3>[ 17.794996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 12:46:39.325130 <3>[ 17.796710] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 12:46:39.334501 <3>[ 17.820669] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 12:46:39.337677 <6>[ 17.826065] pci 0000:00:00.0: PCI bridge to [bus 01]
10955 12:46:39.344101 <6>[ 17.854815] r8152 1-1.1.1:1.0 eth0: v1.12.13
10956 12:46:39.350840 <6>[ 17.855009] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10957 12:46:39.360938 <3>[ 17.865247] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 12:46:39.367150 <6>[ 17.868660] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10959 12:46:39.373940 <6>[ 17.876005] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10960 12:46:39.380306 <6>[ 17.879741] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10961 12:46:39.387620 <3>[ 17.898373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 12:46:39.393520 <6>[ 17.900749] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10963 12:46:39.403692 <3>[ 17.927785] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 12:46:39.413523 [[0;32m OK [<5>[ 18.118558] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10965 12:46:39.416553 0m] Started [0;1;39mNetwork Service[0m.
10966 12:46:39.431353 <5>[ 18.140245] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10967 12:46:39.441275 <4>[ 18.147300] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10968 12:46:39.448765 <6>[ 18.156191] cfg80211: failed to load regulatory.db
10969 12:46:39.452030 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10970 12:46:39.475876 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10971 12:46:39.495268 <6>[ 18.200846] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10972 12:46:39.498501 <6>[ 18.208355] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10973 12:46:39.505125 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10974 12:46:39.525798 <6>[ 18.235351] mt7921e 0000:01:00.0: ASIC revision: 79610010
10975 12:46:39.631831 <4>[ 18.334437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10976 12:46:39.675970 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10977 12:46:39.689898 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10978 12:46:39.708975 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10979 12:46:39.721861 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10980 12:46:39.751874 [[0;32m OK [0m] Reached targ<4>[ 18.453290] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10981 12:46:39.755215 et [0;1;39mSystem Time Synchronized[0m.
10982 12:46:39.774421 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10983 12:46:39.789752 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10984 12:46:39.809086 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10985 12:46:39.821704 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10986 12:46:39.841850 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10987 12:46:39.872433 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch S<4>[ 18.573053] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10988 12:46:39.872575 tatus /dev/rfkill Watch[0m.
10989 12:46:39.922350 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10990 12:46:39.947940 Starting [0;1;39mUser Login Management[0m...
10991 12:46:39.965187 Starting [0;1;39mNetwork Name Resolution[0m...
10992 12:46:39.992844 <4>[ 18.695175] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10993 12:46:39.998874 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10994 12:46:40.015672 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10995 12:46:40.043237 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10996 12:46:40.116958 <4>[ 18.818976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 12:46:40.123006 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10998 12:46:40.138946 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10999 12:46:40.161736 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11000 12:46:40.202468 Starting [0;1;39mPermit User Sessions[0m...
11001 12:46:40.236709 [[0;32m OK [0m] Finished [0;1;39mPermit Use<4>[ 18.939390] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 12:46:40.239964 r Sessions[0m.
11003 12:46:40.270936 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11004 12:46:40.289686 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11005 12:46:40.306039 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11006 12:46:40.322427 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11007 12:46:40.337972 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11008 12:46:40.358421 <4>[ 19.061502] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11009 12:46:40.406273 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11010 12:46:40.430703 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11011 12:46:40.448146
11012 12:46:40.448231
11013 12:46:40.451450 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11014 12:46:40.451531
11015 12:46:40.454984 debian-bullseye-arm64 login: root (automatic login)
11016 12:46:40.455066
11017 12:46:40.455129
11018 12:46:40.480436 <4>[ 19.183237] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 12:46:40.487080 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11020 12:46:40.487162
11021 12:46:40.493175 The programs included with the Debian GNU/Linux system are free software;
11022 12:46:40.500195 the exact distribution terms for each program are described in the
11023 12:46:40.506879 individual files in /usr/share/doc/*/copyright.
11024 12:46:40.506983
11025 12:46:40.509757 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11026 12:46:40.512953 permitted by applicable law.
11027 12:46:40.513284 Matched prompt #10: / #
11029 12:46:40.513483 Setting prompt string to ['/ #']
11030 12:46:40.513572 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11032 12:46:40.513755 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11033 12:46:40.513837 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11034 12:46:40.513907 Setting prompt string to ['/ #']
11035 12:46:40.513965 Forcing a shell prompt, looking for ['/ #']
11037 12:46:40.564173 / #
11038 12:46:40.564273 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11039 12:46:40.564349 Waiting using forced prompt support (timeout 00:02:30)
11040 12:46:40.569116
11041 12:46:40.569384 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11042 12:46:40.569476 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11043 12:46:40.569570 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11044 12:46:40.569653 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11045 12:46:40.569731 end: 2 depthcharge-action (duration 00:01:24) [common]
11046 12:46:40.569815 start: 3 lava-test-retry (timeout 00:08:17) [common]
11047 12:46:40.569893 start: 3.1 lava-test-shell (timeout 00:08:17) [common]
11048 12:46:40.569962 Using namespace: common
11050 12:46:40.670325 / # #
11051 12:46:40.670453 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11052 12:46:40.670587 <4>[ 19.305587] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11053 12:46:40.675884 #
11054 12:46:40.676147 Using /lava-10724910
11056 12:46:40.776583 / # export SHELL=/bin/sh
11057 12:46:40.776801 <4>[ 19.425219] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11058 12:46:40.778810 export SHELL=/bin/sh<6>[ 19.484972] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11059 12:46:40.824687 <6>[ 19.492990] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11060 12:46:40.824807
11062 12:46:40.925315 / # . /lava-10724910/environment
11063 12:46:40.925489 <3>[ 19.543318] mt7921e 0000:01:00.0: hardware init failed
11064 12:46:40.930953 . /lava-10724910/environment
11066 12:46:41.031472 / # /lava-10724910/bin/lava-test-runner /lava-10724910/0
11067 12:46:41.031584 Test shell timeout: 10s (minimum of the action and connection timeout)
11068 12:46:41.036430 /lava-10724910/bin/lava-test-runner /lava-10724910/0
11069 12:46:41.059562 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11070 12:46:41.065556 + cd /lava-10724910/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11071 12:46:41.065663 + cat uuid
11072 12:46:41.068843 + UUID=10724910_1.5.2.3.1
11073 12:46:41.068924 + set +x
11074 12:46:41.075991 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10724910_1.5.2.3.1>
11075 12:46:41.076244 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10724910_1.5.2.3.1
11076 12:46:41.076315 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10724910_1.5.2.3.1)
11077 12:46:41.076398 Skipping test definition patterns.
11078 12:46:41.078964 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11079 12:46:41.082240 Received signal: <TESTCASE> TEST_CASE_ID=device-presence<4
11080 12:46:41.082345 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'device-presence<4', 'result': 'unknown'}
11081 12:46:41.091983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence<4>[ 19.797205] use of bytesused == 0 is deprecated and will be removed in the future,
11082 12:46:41.092065 RESULT=pass>
11083 12:46:41.095675 d<4>[ 19.805613] use the actual size instead.
11084 12:46:41.098969 evice: /dev/video2
11085 12:46:41.101810 <4>[ 19.812759] ------------[ cut here ]------------
11086 12:46:41.109504 <4>[ 19.817691] get_vaddr_frames() cannot follow VM_IO mapping
11087 12:46:41.121577 <4>[ 19.817856] WARNING: CPU: 0 PID: 307 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11088 12:46:41.171458 <4>[ 19.835980] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb btintel mtk_vcodec_enc mtk_vcodec_common btmtk mtk_vpu btrtl uvcvideo v4l2_mem2mem btbcm r8153_ecm videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops videobuf2_v4l2 videobuf2_common cdc_ether bluetooth videodev usbnet cros_ec_rpmsg ecdh_generic ecc r8152 crct10dif_ce elan_i2c rfkill elants_i2c mc cros_ec_chardev pcie_mediatek_gen3 sbs_battery cros_ec_typec hid_google_hammer hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11089 12:46:41.178047 <4>[ 19.885366] CPU: 0 PID: 307 Comm: v4l2-compliance Not tainted 6.1.31 #1
11090 12:46:41.184489 <4>[ 19.892231] Hardware name: Google Spherion (rev0 - 3) (DT)
11091 12:46:41.191229 <4>[ 19.897965] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11092 12:46:41.197692 <4>[ 19.905176] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11093 12:46:41.204395 <4>[ 19.911266] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11094 12:46:41.207516 <4>[ 19.917357] sp : ffff8000091ab850
11095 12:46:41.214421 <4>[ 19.920921] x29: ffff8000091ab850 x28: ffffde2ed90d7000 x27: ffffde2ed90d3238
11096 12:46:41.220906 <4>[ 19.928309] x26: 0000000000000000 x25: ffffde2f29e9d1b8 x24: ffff6e534f151298
11097 12:46:41.227242 <4>[ 19.935697] x23: ffff6e534b9b9800 x22: ffff6e5340d48010 x21: 0000000000000000
11098 12:46:41.237577 <4>[ 19.943084] x20: 00000000fffffff2 x19: ffff6e534ebaf180 x18: fffffffffffe9a98
11099 12:46:41.244210 <4>[ 19.950471] x17: 0000000000000000 x16: ffffde2f27e8bb60 x15: 0000000000000038
11100 12:46:41.250654 <4>[ 19.957857] x14: ffffde2f2a7834a8 x13: 0000000000000675 x12: 0000000000000227
11101 12:46:41.257196 <4>[ 19.965244] x11: fffffffffffe9a98 x10: fffffffffffe9a60 x9 : 00000000fffff227
11102 12:46:41.267360 <4>[ 19.972631] x8 : ffffde2f2a7834a8 x7 : ffffde2f2a7db4a8 x6 : 00000000000019d4
11103 12:46:41.273903 <4>[ 19.980018] x5 : ffff6e547ef14a18 x4 : 00000000fffff227 x3 : ffff902554e51000
11104 12:46:41.280431 <4>[ 19.987405] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff6e534d37d880
11105 12:46:41.283482 <4>[ 19.994792] Call trace:
11106 12:46:41.290035 <4>[ 19.997490] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11107 12:46:41.293361 <4>[ 20.003234] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11108 12:46:41.300250 <4>[ 20.009235] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11109 12:46:41.306482 <4>[ 20.015586] __prepare_userptr+0x280/0x410 [videobuf2_common]
11110 12:46:41.313564 <4>[ 20.021589] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11111 12:46:41.320781 <4>[ 20.027245] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11112 12:46:41.323471 <4>[ 20.033422] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11113 12:46:41.329685 <4>[ 20.038923] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11114 12:46:41.336453 <4>[ 20.044698] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11115 12:46:41.343191 <4>[ 20.050963] v4l_prepare_buf+0x48/0x60 [videodev]
11116 12:46:41.346447 <4>[ 20.055991] __video_do_ioctl+0x184/0x3d0 [videodev]
11117 12:46:41.352699 <4>[ 20.061235] video_usercopy+0x358/0x680 [videodev]
11118 12:46:41.356155 <4>[ 20.066305] video_ioctl2+0x18/0x30 [videodev]
11119 12:46:41.359645 <4>[ 20.071028] v4l2_ioctl+0x40/0x60 [videodev]
11120 12:46:41.365890 <4>[ 20.075579] __arm64_sys_ioctl+0xa8/0xf0
11121 12:46:41.369882 <4>[ 20.079760] invoke_syscall+0x48/0x114
11122 12:46:41.372436 <4>[ 20.083765] el0_svc_common.constprop.0+0x44/0xec
11123 12:46:41.379252 <4>[ 20.088721] do_el0_svc+0x2c/0xd0
11124 12:46:41.383310 <4>[ 20.092286] el0_svc+0x2c/0x84
11125 12:46:41.385804 <4>[ 20.095597] el0t_64_sync_handler+0xb8/0xc0
11126 12:46:41.389253 <4>[ 20.100030] el0t_64_sync+0x18c/0x190
11127 12:46:41.395908 <4>[ 20.103943] ---[ end trace 0000000000000000 ]---
11128 12:46:41.407654 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11129 12:46:41.418106 v4l2-compliance SHA: 57b6b2492f4a 2023-06-07 12:27:03
11130 12:46:41.424615
11131 12:46:41.437398 Compliance test for mtk-vcodec-enc device /dev/video2:
11132 12:46:41.442593
11133 12:46:41.451849 Driver Info:
11134 12:46:41.461414 Driver name : mtk-vcodec-enc
11135 12:46:41.474981 Card type : MT8192 video encoder
11136 12:46:41.484535 Bus info : platform:17020000.vcodec
11137 12:46:41.490747 Driver version : 6.1.31
11138 12:46:41.499974 Capabilities : 0x84204000
11139 12:46:41.509829 Video Memory-to-Memory Multiplanar
11140 12:46:41.520452 Streaming
11141 12:46:41.529522 Extended Pix Format
11142 12:46:41.538729 Device Capabilities
11143 12:46:41.547474 Device Caps : 0x04204000
11144 12:46:41.556818 Video Memory-to-Memory Multiplanar
11145 12:46:41.566650 Streaming
11146 12:46:41.576461 Extended Pix Format
11147 12:46:41.586448 Detected Stateful Encoder
11148 12:46:41.595265
11149 12:46:41.604208 Required ioctls:
11150 12:46:41.618747 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11151 12:46:41.618828 test VIDIOC_QUERYCAP: OK
11152 12:46:41.619074 Received signal: <TESTSET> START Required-ioctls
11153 12:46:41.619144 Starting test_set Required-ioctls
11154 12:46:41.643130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11155 12:46:41.643380 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11157 12:46:41.645536 test invalid ioctls: OK
11158 12:46:41.666117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11159 12:46:41.666198
11160 12:46:41.666507 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11162 12:46:41.676817 Allow for multiple opens:
11163 12:46:41.684465 <LAVA_SIGNAL_TESTSET STOP>
11164 12:46:41.684750 Received signal: <TESTSET> STOP
11165 12:46:41.684817 Closing test_set Required-ioctls
11166 12:46:41.693462 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11167 12:46:41.693711 Received signal: <TESTSET> START Allow-for-multiple-opens
11168 12:46:41.693778 Starting test_set Allow-for-multiple-opens
11169 12:46:41.697242 test second /dev/video2 open: OK
11170 12:46:41.716422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11171 12:46:41.716746 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11173 12:46:41.719527 test VIDIOC_QUERYCAP: OK
11174 12:46:41.740084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11175 12:46:41.740332 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11177 12:46:41.743154 test VIDIOC_G/S_PRIORITY: OK
11178 12:46:41.763858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11179 12:46:41.764107 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11181 12:46:41.766927 test for unlimited opens: OK
11182 12:46:41.788281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11183 12:46:41.788381
11184 12:46:41.788614 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11186 12:46:41.797455 Debug ioctls:
11187 12:46:41.804331 <LAVA_SIGNAL_TESTSET STOP>
11188 12:46:41.804550 Received signal: <TESTSET> STOP
11189 12:46:41.804631 Closing test_set Allow-for-multiple-opens
11190 12:46:41.813865 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11191 12:46:41.814114 Received signal: <TESTSET> START Debug-ioctls
11192 12:46:41.814184 Starting test_set Debug-ioctls
11193 12:46:41.817005 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11194 12:46:41.838269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11195 12:46:41.838521 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11197 12:46:41.844665 test VIDIOC_LOG_STATUS: OK (Not Supported)
11198 12:46:41.862300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11199 12:46:41.862382
11200 12:46:41.862613 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11202 12:46:41.873152 Input ioctls:
11203 12:46:41.880083 <LAVA_SIGNAL_TESTSET STOP>
11204 12:46:41.880334 Received signal: <TESTSET> STOP
11205 12:46:41.880405 Closing test_set Debug-ioctls
11206 12:46:41.889544 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11207 12:46:41.889796 Received signal: <TESTSET> START Input-ioctls
11208 12:46:41.889866 Starting test_set Input-ioctls
11209 12:46:41.892064 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11210 12:46:41.918196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11211 12:46:41.918447 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11213 12:46:41.921223 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11214 12:46:41.942449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11215 12:46:41.942699 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11217 12:46:41.948500 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11218 12:46:41.964340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11219 12:46:41.964590 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11221 12:46:41.970649 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11222 12:46:41.988036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11223 12:46:41.988290 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11225 12:46:41.991515 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11226 12:46:42.012959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11227 12:46:42.013210 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11229 12:46:42.016240 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11230 12:46:42.036065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11231 12:46:42.036314 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11233 12:46:42.039431 Inputs: 0 Audio Inputs: 0 Tuners: 0
11234 12:46:42.045621
11235 12:46:42.062872 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11236 12:46:42.084979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11237 12:46:42.085231 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11239 12:46:42.090788 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11240 12:46:42.108451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11241 12:46:42.108760 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11243 12:46:42.115406 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11244 12:46:42.131527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11245 12:46:42.131778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11247 12:46:42.138143 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11248 12:46:42.155684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11249 12:46:42.155934 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11251 12:46:42.162334 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11252 12:46:42.179982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11253 12:46:42.180065
11254 12:46:42.180297 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11256 12:46:42.196653 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11257 12:46:42.216677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11258 12:46:42.216928 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11260 12:46:42.223141 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11261 12:46:42.244983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11262 12:46:42.245234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11264 12:46:42.247683 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11265 12:46:42.265050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11266 12:46:42.265301 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11268 12:46:42.267987 test VIDIOC_G/S_EDID: OK (Not Supported)
11269 12:46:42.288715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11270 12:46:42.288828
11271 12:46:42.289095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11273 12:46:42.299736 Control ioctls:
11274 12:46:42.306959 <LAVA_SIGNAL_TESTSET STOP>
11275 12:46:42.307208 Received signal: <TESTSET> STOP
11276 12:46:42.307276 Closing test_set Input-ioctls
11277 12:46:42.316647 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11278 12:46:42.316896 Received signal: <TESTSET> START Control-ioctls
11279 12:46:42.316965 Starting test_set Control-ioctls
11280 12:46:42.320078 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11281 12:46:42.343378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11282 12:46:42.343460 test VIDIOC_QUERYCTRL: OK
11283 12:46:42.343694 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11285 12:46:42.362563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11286 12:46:42.362812 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11288 12:46:42.365889 test VIDIOC_G/S_CTRL: OK
11289 12:46:42.387659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11290 12:46:42.387911 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11292 12:46:42.390904 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11293 12:46:42.410284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11294 12:46:42.410533 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11296 12:46:42.419841 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11297 12:46:42.423306 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11298 12:46:42.447850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11299 12:46:42.448100 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11301 12:46:42.450953 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11302 12:46:42.467993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11303 12:46:42.468240 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11305 12:46:42.471663 Standard Controls: 16 Private Controls: 0
11306 12:46:42.477339
11307 12:46:42.487239 Format ioctls:
11308 12:46:42.494241 <LAVA_SIGNAL_TESTSET STOP>
11309 12:46:42.494488 Received signal: <TESTSET> STOP
11310 12:46:42.494555 Closing test_set Control-ioctls
11311 12:46:42.503709 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11312 12:46:42.503956 Received signal: <TESTSET> START Format-ioctls
11313 12:46:42.504023 Starting test_set Format-ioctls
11314 12:46:42.507007 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11315 12:46:42.532076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11316 12:46:42.532325 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11318 12:46:42.534973 test VIDIOC_G/S_PARM: OK
11319 12:46:42.552319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11320 12:46:42.552534 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11322 12:46:42.555380 test VIDIOC_G_FBUF: OK (Not Supported)
11323 12:46:42.577747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11324 12:46:42.577994 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11326 12:46:42.580969 test VIDIOC_G_FMT: OK
11327 12:46:42.602851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11328 12:46:42.603101 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11330 12:46:42.606391 test VIDIOC_TRY_FMT: OK
11331 12:46:42.627843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11332 12:46:42.628092 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11334 12:46:42.637616 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11335 12:46:42.637726 test VIDIOC_S_FMT: FAIL
11336 12:46:42.663462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11337 12:46:42.663711 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11339 12:46:42.667146 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11340 12:46:42.688506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11341 12:46:42.688789 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11343 12:46:42.691273 test Cropping: OK
11344 12:46:42.711832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11345 12:46:42.712079 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11347 12:46:42.714958 test Composing: OK (Not Supported)
11348 12:46:42.736794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11349 12:46:42.737043 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11351 12:46:42.740051 test Scaling: OK (Not Supported)
11352 12:46:42.762822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11353 12:46:42.762904
11354 12:46:42.763134 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11356 12:46:42.773400 Codec ioctls:
11357 12:46:42.780098 <LAVA_SIGNAL_TESTSET STOP>
11358 12:46:42.780346 Received signal: <TESTSET> STOP
11359 12:46:42.780415 Closing test_set Format-ioctls
11360 12:46:42.789582 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11361 12:46:42.789845 Received signal: <TESTSET> START Codec-ioctls
11362 12:46:42.789915 Starting test_set Codec-ioctls
11363 12:46:42.793109 test VIDIOC_(TRY_)ENCODER_CMD: OK
11364 12:46:42.813307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11365 12:46:42.813556 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11367 12:46:42.818988 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11368 12:46:42.837698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11369 12:46:42.837948 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11371 12:46:42.844190 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11372 12:46:42.864370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11373 12:46:42.864458
11374 12:46:42.864716 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11376 12:46:42.875055 Buffer ioctls:
11377 12:46:42.880987 <LAVA_SIGNAL_TESTSET STOP>
11378 12:46:42.881232 Received signal: <TESTSET> STOP
11379 12:46:42.881298 Closing test_set Codec-ioctls
11380 12:46:42.889336 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11381 12:46:42.889585 Received signal: <TESTSET> START Buffer-ioctls
11382 12:46:42.889657 Starting test_set Buffer-ioctls
11383 12:46:42.893416 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11384 12:46:42.922727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11385 12:46:42.922808 test VIDIOC_EXPBUF: OK
11386 12:46:42.923038 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11388 12:46:42.945553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11389 12:46:42.945802 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11391 12:46:42.948913 test Requests: OK (Not Supported)
11392 12:46:42.972121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11393 12:46:42.972203
11394 12:46:42.972433 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11396 12:46:42.982015 Test input 0:
11397 12:46:42.990497
11398 12:46:43.000951 Streaming ioctls:
11399 12:46:43.008018 <LAVA_SIGNAL_TESTSET STOP>
11400 12:46:43.008266 Received signal: <TESTSET> STOP
11401 12:46:43.008332 Closing test_set Buffer-ioctls
11402 12:46:43.017083 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11403 12:46:43.017332 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11404 12:46:43.017403 Starting test_set Streaming-ioctls_Test-input-0
11405 12:46:43.019853 test read/write: OK (Not Supported)
11406 12:46:43.047255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11407 12:46:43.047506 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11409 12:46:43.053834 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11410 12:46:43.063178 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11411 12:46:43.066069 test blocking wait: FAIL
11412 12:46:43.089601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11413 12:46:43.089852 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11415 12:46:43.098968 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11416 12:46:43.099049 test MMAP (select): FAIL
11417 12:46:43.123505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11418 12:46:43.123754 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11420 12:46:43.130089 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11421 12:46:43.134910 test MMAP (epoll): FAIL
11422 12:46:43.159293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11423 12:46:43.159544 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11425 12:46:43.168989 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11426 12:46:43.175802 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11427 12:46:43.181319 test USERPTR (select): FAIL
11428 12:46:43.205760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11429 12:46:43.206011 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11431 12:46:43.212363 test DMABUF: Cannot test, specify --expbuf-device
11432 12:46:43.215581
11433 12:46:43.232464 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11434 12:46:43.235719 <LAVA_TEST_RUNNER EXIT>
11435 12:46:43.235997 ok: lava_test_shell seems to have completed
11436 12:46:43.236120 Marking unfinished test run as failed
11438 12:46:43.237067 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11439 12:46:43.237232 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11440 12:46:43.237334 end: 3 lava-test-retry (duration 00:00:03) [common]
11441 12:46:43.237419 start: 4 finalize (timeout 00:08:14) [common]
11442 12:46:43.237510 start: 4.1 power-off (timeout 00:00:30) [common]
11443 12:46:43.237659 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11444 12:46:43.312962 >> Command sent successfully.
11445 12:46:43.315335 Returned 0 in 0 seconds
11446 12:46:43.415815 end: 4.1 power-off (duration 00:00:00) [common]
11448 12:46:43.416125 start: 4.2 read-feedback (timeout 00:08:14) [common]
11449 12:46:43.416376 Listened to connection for namespace 'common' for up to 1s
11450 12:46:44.416633 Finalising connection for namespace 'common'
11451 12:46:44.416804 Disconnecting from shell: Finalise
11452 12:46:44.416887 / #
11453 12:46:44.517218 end: 4.2 read-feedback (duration 00:00:01) [common]
11454 12:46:44.517392 end: 4 finalize (duration 00:00:01) [common]
11455 12:46:44.517504 Cleaning after the job
11456 12:46:44.517599 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/ramdisk
11457 12:46:44.521992 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/kernel
11458 12:46:44.528138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/dtb
11459 12:46:44.528315 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724910/tftp-deploy-h2rsz2y1/modules
11460 12:46:44.533613 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724910
11461 12:46:44.588753 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724910
11462 12:46:44.588922 Job finished correctly