Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 69
- Errors: 1
1 12:47:16.667568 lava-dispatcher, installed at version: 2023.05.1
2 12:47:16.667797 start: 0 validate
3 12:47:16.667963 Start time: 2023-06-14 12:47:16.667955+00:00 (UTC)
4 12:47:16.668119 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:47:16.668305 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 12:47:16.945644 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:47:16.945877 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:47:17.216166 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:47:17.216411 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:47:17.475905 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:47:17.476086 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-46-g4cc1cc26e90f%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:47:17.745945 validate duration: 1.08
14 12:47:17.746212 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:47:17.746311 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:47:17.746408 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:47:17.746542 Not decompressing ramdisk as can be used compressed.
18 12:47:17.746632 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230609.0/arm64/rootfs.cpio.gz
19 12:47:17.746697 saving as /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/ramdisk/rootfs.cpio.gz
20 12:47:17.746757 total size: 27153005 (25MB)
21 12:47:17.747881 progress 0% (0MB)
22 12:47:17.755146 progress 5% (1MB)
23 12:47:17.762048 progress 10% (2MB)
24 12:47:17.769148 progress 15% (3MB)
25 12:47:17.776077 progress 20% (5MB)
26 12:47:17.783163 progress 25% (6MB)
27 12:47:17.790209 progress 30% (7MB)
28 12:47:17.797529 progress 35% (9MB)
29 12:47:17.804507 progress 40% (10MB)
30 12:47:17.811592 progress 45% (11MB)
31 12:47:17.818839 progress 50% (12MB)
32 12:47:17.825886 progress 55% (14MB)
33 12:47:17.833108 progress 60% (15MB)
34 12:47:17.840066 progress 65% (16MB)
35 12:47:17.847157 progress 70% (18MB)
36 12:47:17.854121 progress 75% (19MB)
37 12:47:17.861005 progress 80% (20MB)
38 12:47:17.868304 progress 85% (22MB)
39 12:47:17.875165 progress 90% (23MB)
40 12:47:17.882194 progress 95% (24MB)
41 12:47:17.889102 progress 100% (25MB)
42 12:47:17.889301 25MB downloaded in 0.14s (181.67MB/s)
43 12:47:17.889454 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:47:17.889723 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:47:17.889814 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:47:17.889897 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:47:17.890033 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:47:17.890106 saving as /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/kernel/Image
50 12:47:17.890169 total size: 47581696 (45MB)
51 12:47:17.890236 No compression specified
52 12:47:17.891464 progress 0% (0MB)
53 12:47:17.904094 progress 5% (2MB)
54 12:47:17.916500 progress 10% (4MB)
55 12:47:17.928849 progress 15% (6MB)
56 12:47:17.941295 progress 20% (9MB)
57 12:47:17.953484 progress 25% (11MB)
58 12:47:17.965579 progress 30% (13MB)
59 12:47:17.977861 progress 35% (15MB)
60 12:47:17.989826 progress 40% (18MB)
61 12:47:18.002087 progress 45% (20MB)
62 12:47:18.014560 progress 50% (22MB)
63 12:47:18.026761 progress 55% (24MB)
64 12:47:18.039236 progress 60% (27MB)
65 12:47:18.051346 progress 65% (29MB)
66 12:47:18.063552 progress 70% (31MB)
67 12:47:18.075835 progress 75% (34MB)
68 12:47:18.087976 progress 80% (36MB)
69 12:47:18.100178 progress 85% (38MB)
70 12:47:18.112246 progress 90% (40MB)
71 12:47:18.124394 progress 95% (43MB)
72 12:47:18.136534 progress 100% (45MB)
73 12:47:18.136663 45MB downloaded in 0.25s (184.09MB/s)
74 12:47:18.136813 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:47:18.137050 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:47:18.137136 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:47:18.137219 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:47:18.137364 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:47:18.137439 saving as /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/dtb/mt8192-asurada-spherion-r0.dtb
81 12:47:18.137500 total size: 46924 (0MB)
82 12:47:18.137559 No compression specified
83 12:47:18.138658 progress 69% (0MB)
84 12:47:18.138926 progress 100% (0MB)
85 12:47:18.139077 0MB downloaded in 0.00s (28.42MB/s)
86 12:47:18.139201 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:47:18.139426 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:47:18.139523 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:47:18.139612 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:47:18.139725 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-46-g4cc1cc26e90f/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:47:18.139795 saving as /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/modules/modules.tar
93 12:47:18.139888 total size: 8536768 (8MB)
94 12:47:18.139980 Using unxz to decompress xz
95 12:47:18.143678 progress 0% (0MB)
96 12:47:18.164772 progress 5% (0MB)
97 12:47:18.191213 progress 10% (0MB)
98 12:47:18.221778 progress 15% (1MB)
99 12:47:18.245485 progress 20% (1MB)
100 12:47:18.268748 progress 25% (2MB)
101 12:47:18.292634 progress 30% (2MB)
102 12:47:18.315957 progress 35% (2MB)
103 12:47:18.342694 progress 40% (3MB)
104 12:47:18.367003 progress 45% (3MB)
105 12:47:18.392375 progress 50% (4MB)
106 12:47:18.417039 progress 55% (4MB)
107 12:47:18.441998 progress 60% (4MB)
108 12:47:18.466828 progress 65% (5MB)
109 12:47:18.491196 progress 70% (5MB)
110 12:47:18.515325 progress 75% (6MB)
111 12:47:18.539111 progress 80% (6MB)
112 12:47:18.562699 progress 85% (6MB)
113 12:47:18.587386 progress 90% (7MB)
114 12:47:18.611919 progress 95% (7MB)
115 12:47:18.634683 progress 100% (8MB)
116 12:47:18.641231 8MB downloaded in 0.50s (16.24MB/s)
117 12:47:18.641511 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:47:18.641778 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:47:18.641873 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:47:18.641974 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:47:18.642058 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:47:18.642148 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:47:18.642372 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx
125 12:47:18.642505 makedir: /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin
126 12:47:18.642610 makedir: /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/tests
127 12:47:18.642707 makedir: /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/results
128 12:47:18.642819 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-add-keys
129 12:47:18.642967 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-add-sources
130 12:47:18.643096 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-background-process-start
131 12:47:18.643226 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-background-process-stop
132 12:47:18.643350 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-common-functions
133 12:47:18.643473 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-echo-ipv4
134 12:47:18.643599 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-install-packages
135 12:47:18.643722 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-installed-packages
136 12:47:18.643857 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-os-build
137 12:47:18.643983 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-probe-channel
138 12:47:18.644105 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-probe-ip
139 12:47:18.644226 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-target-ip
140 12:47:18.644348 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-target-mac
141 12:47:18.644469 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-target-storage
142 12:47:18.644633 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-test-case
143 12:47:18.644757 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-test-event
144 12:47:18.644880 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-test-feedback
145 12:47:18.645002 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-test-raise
146 12:47:18.645125 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-test-reference
147 12:47:18.645247 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-test-runner
148 12:47:18.645369 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-test-set
149 12:47:18.645493 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-test-shell
150 12:47:18.645617 Updating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-install-packages (oe)
151 12:47:18.645767 Updating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/bin/lava-installed-packages (oe)
152 12:47:18.645888 Creating /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/environment
153 12:47:18.645995 LAVA metadata
154 12:47:18.646069 - LAVA_JOB_ID=10724916
155 12:47:18.646134 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:47:18.646240 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:47:18.646308 skipped lava-vland-overlay
158 12:47:18.646383 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:47:18.646463 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:47:18.646543 skipped lava-multinode-overlay
161 12:47:18.646653 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:47:18.646744 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:47:18.646819 Loading test definitions
164 12:47:18.646910 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:47:18.646985 Using /lava-10724916 at stage 0
166 12:47:18.647281 uuid=10724916_1.5.2.3.1 testdef=None
167 12:47:18.647369 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:47:18.647454 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:47:18.647962 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:47:18.648188 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:47:18.648836 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:47:18.649093 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:47:18.649699 runner path: /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/0/tests/0_v4l2-compliance-uvc test_uuid 10724916_1.5.2.3.1
176 12:47:18.649855 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:47:18.650063 Creating lava-test-runner.conf files
179 12:47:18.650127 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10724916/lava-overlay-ejneq8xx/lava-10724916/0 for stage 0
180 12:47:18.650215 - 0_v4l2-compliance-uvc
181 12:47:18.650311 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:47:18.650397 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:47:18.657235 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:47:18.657342 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:47:18.657432 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:47:18.657546 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:47:18.657638 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:47:19.355193 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:47:19.355568 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:47:19.355683 extracting modules file /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10724916/extract-overlay-ramdisk-qy8rx18n/ramdisk
191 12:47:19.567677 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:47:19.567855 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:47:19.567954 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724916/compress-overlay-87gobpzo/overlay-1.5.2.4.tar.gz to ramdisk
194 12:47:19.568030 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10724916/compress-overlay-87gobpzo/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10724916/extract-overlay-ramdisk-qy8rx18n/ramdisk
195 12:47:19.574545 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:47:19.574656 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:47:19.574779 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:47:19.574866 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:47:19.574945 Building ramdisk /var/lib/lava/dispatcher/tmp/10724916/extract-overlay-ramdisk-qy8rx18n/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10724916/extract-overlay-ramdisk-qy8rx18n/ramdisk
200 12:47:20.102166 >> 230341 blocks
201 12:47:24.057332 rename /var/lib/lava/dispatcher/tmp/10724916/extract-overlay-ramdisk-qy8rx18n/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/ramdisk/ramdisk.cpio.gz
202 12:47:24.057771 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 12:47:24.057898 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 12:47:24.058008 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 12:47:24.058122 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/kernel/Image'
206 12:47:35.789942 Returned 0 in 11 seconds
207 12:47:35.890985 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/kernel/image.itb
208 12:47:36.609278 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:47:36.609639 output: Created: Wed Jun 14 13:47:36 2023
210 12:47:36.609717 output: Image 0 (kernel-1)
211 12:47:36.609780 output: Description:
212 12:47:36.609843 output: Created: Wed Jun 14 13:47:36 2023
213 12:47:36.609904 output: Type: Kernel Image
214 12:47:36.609965 output: Compression: lzma compressed
215 12:47:36.610024 output: Data Size: 10442380 Bytes = 10197.64 KiB = 9.96 MiB
216 12:47:36.610086 output: Architecture: AArch64
217 12:47:36.610142 output: OS: Linux
218 12:47:36.610202 output: Load Address: 0x00000000
219 12:47:36.610260 output: Entry Point: 0x00000000
220 12:47:36.610316 output: Hash algo: crc32
221 12:47:36.610370 output: Hash value: ced21bfe
222 12:47:36.610424 output: Image 1 (fdt-1)
223 12:47:36.610478 output: Description: mt8192-asurada-spherion-r0
224 12:47:36.610531 output: Created: Wed Jun 14 13:47:36 2023
225 12:47:36.610585 output: Type: Flat Device Tree
226 12:47:36.610639 output: Compression: uncompressed
227 12:47:36.610692 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 12:47:36.610746 output: Architecture: AArch64
229 12:47:36.610799 output: Hash algo: crc32
230 12:47:36.610852 output: Hash value: 1df858fa
231 12:47:36.610905 output: Image 2 (ramdisk-1)
232 12:47:36.610958 output: Description: unavailable
233 12:47:36.611011 output: Created: Wed Jun 14 13:47:36 2023
234 12:47:36.611065 output: Type: RAMDisk Image
235 12:47:36.611118 output: Compression: Unknown Compression
236 12:47:36.611171 output: Data Size: 40143219 Bytes = 39202.36 KiB = 38.28 MiB
237 12:47:36.611224 output: Architecture: AArch64
238 12:47:36.611277 output: OS: Linux
239 12:47:36.611330 output: Load Address: unavailable
240 12:47:36.611383 output: Entry Point: unavailable
241 12:47:36.611436 output: Hash algo: crc32
242 12:47:36.611489 output: Hash value: 1472979b
243 12:47:36.611542 output: Default Configuration: 'conf-1'
244 12:47:36.611594 output: Configuration 0 (conf-1)
245 12:47:36.611648 output: Description: mt8192-asurada-spherion-r0
246 12:47:36.611700 output: Kernel: kernel-1
247 12:47:36.611753 output: Init Ramdisk: ramdisk-1
248 12:47:36.611806 output: FDT: fdt-1
249 12:47:36.611859 output: Loadables: kernel-1
250 12:47:36.611911 output:
251 12:47:36.612104 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:47:36.612200 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:47:36.612305 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 12:47:36.612400 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 12:47:36.612478 No LXC device requested
256 12:47:36.612595 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:47:36.612683 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 12:47:36.612762 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:47:36.612832 Checking files for TFTP limit of 4294967296 bytes.
260 12:47:36.613320 end: 1 tftp-deploy (duration 00:00:19) [common]
261 12:47:36.613421 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:47:36.613511 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:47:36.613631 substitutions:
264 12:47:36.613698 - {DTB}: 10724916/tftp-deploy-8qwfh__e/dtb/mt8192-asurada-spherion-r0.dtb
265 12:47:36.613765 - {INITRD}: 10724916/tftp-deploy-8qwfh__e/ramdisk/ramdisk.cpio.gz
266 12:47:36.613824 - {KERNEL}: 10724916/tftp-deploy-8qwfh__e/kernel/Image
267 12:47:36.613882 - {LAVA_MAC}: None
268 12:47:36.613938 - {PRESEED_CONFIG}: None
269 12:47:36.613993 - {PRESEED_LOCAL}: None
270 12:47:36.614048 - {RAMDISK}: 10724916/tftp-deploy-8qwfh__e/ramdisk/ramdisk.cpio.gz
271 12:47:36.614103 - {ROOT_PART}: None
272 12:47:36.614157 - {ROOT}: None
273 12:47:36.614211 - {SERVER_IP}: 192.168.201.1
274 12:47:36.614264 - {TEE}: None
275 12:47:36.614318 Parsed boot commands:
276 12:47:36.614372 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:47:36.614542 Parsed boot commands: tftpboot 192.168.201.1 10724916/tftp-deploy-8qwfh__e/kernel/image.itb 10724916/tftp-deploy-8qwfh__e/kernel/cmdline
278 12:47:36.614632 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:47:36.614716 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:47:36.614806 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:47:36.614892 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:47:36.614962 Not connected, no need to disconnect.
283 12:47:36.615037 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:47:36.615118 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:47:36.615187 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
286 12:47:36.618502 Setting prompt string to ['lava-test: # ']
287 12:47:36.618820 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:47:36.618927 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:47:36.619026 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:47:36.619117 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:47:36.619312 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 12:47:41.772774 >> Command sent successfully.
293 12:47:41.783013 Returned 0 in 5 seconds
294 12:47:41.884351 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:47:41.887314 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:47:41.887968 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:47:41.888476 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:47:41.888927 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:47:41.889453 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:47:41.890840 [Enter `^Ec?' for help]
302 12:47:42.047721
303 12:47:42.048328
304 12:47:42.048885 F0: 102B 0000
305 12:47:42.049386
306 12:47:42.049839 F3: 1001 0000 [0200]
307 12:47:42.050302
308 12:47:42.051027 F3: 1001 0000
309 12:47:42.051422
310 12:47:42.051865 F7: 102D 0000
311 12:47:42.052305
312 12:47:42.054709 F1: 0000 0000
313 12:47:42.055194
314 12:47:42.055682 V0: 0000 0000 [0001]
315 12:47:42.056136
316 12:47:42.057823 00: 0007 8000
317 12:47:42.058271
318 12:47:42.058710 01: 0000 0000
319 12:47:42.059136
320 12:47:42.060623 BP: 0C00 0209 [0000]
321 12:47:42.061063
322 12:47:42.061503 G0: 1182 0000
323 12:47:42.061921
324 12:47:42.064109 EC: 0000 0021 [4000]
325 12:47:42.064573
326 12:47:42.065019 S7: 0000 0000 [0000]
327 12:47:42.065438
328 12:47:42.067542 CC: 0000 0000 [0001]
329 12:47:42.068049
330 12:47:42.068575 T0: 0000 0040 [010F]
331 12:47:42.068989
332 12:47:42.069389 Jump to BL
333 12:47:42.070635
334 12:47:42.094824
335 12:47:42.095436
336 12:47:42.095826
337 12:47:42.102261 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:47:42.105939 ARM64: Exception handlers installed.
339 12:47:42.109138 ARM64: Testing exception
340 12:47:42.112604 ARM64: Done test exception
341 12:47:42.119593 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:47:42.129851 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:47:42.136440 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:47:42.146720 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:47:42.153094 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:47:42.159495 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:47:42.171214 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:47:42.177826 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:47:42.197383 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:47:42.201071 WDT: Last reset was cold boot
351 12:47:42.204207 SPI1(PAD0) initialized at 2873684 Hz
352 12:47:42.207522 SPI5(PAD0) initialized at 992727 Hz
353 12:47:42.210723 VBOOT: Loading verstage.
354 12:47:42.217034 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:47:42.220489 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:47:42.223770 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:47:42.227272 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:47:42.234536 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:47:42.241302 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:47:42.252198 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:47:42.252796
362 12:47:42.253177
363 12:47:42.262530 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:47:42.265415 ARM64: Exception handlers installed.
365 12:47:42.269128 ARM64: Testing exception
366 12:47:42.269764 ARM64: Done test exception
367 12:47:42.275473 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:47:42.278871 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:47:42.293207 Probing TPM: . done!
370 12:47:42.293782 TPM ready after 0 ms
371 12:47:42.300019 Connected to device vid:did:rid of 1ae0:0028:00
372 12:47:42.310148 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:47:42.348292 Initialized TPM device CR50 revision 0
374 12:47:42.360374 tlcl_send_startup: Startup return code is 0
375 12:47:42.360995 TPM: setup succeeded
376 12:47:42.373299 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:47:42.382208 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:47:42.391802 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:47:42.400549 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:47:42.403633 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:47:42.407377 in-header: 03 07 00 00 08 00 00 00
382 12:47:42.410574 in-data: aa e4 47 04 13 02 00 00
383 12:47:42.413554 Chrome EC: UHEPI supported
384 12:47:42.420255 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:47:42.423734 in-header: 03 ad 00 00 08 00 00 00
386 12:47:42.426837 in-data: 00 20 20 08 00 00 00 00
387 12:47:42.427424 Phase 1
388 12:47:42.430046 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:47:42.436940 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:47:42.443097 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:47:42.446305 Recovery requested (1009000e)
392 12:47:42.450298 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:47:42.459609 tlcl_extend: response is 0
394 12:47:42.468082 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:47:42.473305 tlcl_extend: response is 0
396 12:47:42.479815 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:47:42.500107 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:47:42.507523 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:47:42.508104
400 12:47:42.508484
401 12:47:42.517455 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:47:42.520354 ARM64: Exception handlers installed.
403 12:47:42.520875 ARM64: Testing exception
404 12:47:42.523563 ARM64: Done test exception
405 12:47:42.545478 pmic_efuse_setting: Set efuses in 11 msecs
406 12:47:42.549289 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:47:42.552865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:47:42.559686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:47:42.563775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:47:42.570047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:47:42.573381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:47:42.580118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:47:42.583724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:47:42.589925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:47:42.593146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:47:42.596700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:47:42.603351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:47:42.606454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:47:42.610460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:47:42.617206 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:47:42.623541 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:47:42.630157 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:47:42.633255 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:47:42.640479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:47:42.646707 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:47:42.650550 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:47:42.657036 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:47:42.664296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:47:42.668401 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:47:42.675372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:47:42.678784 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:47:42.686263 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:47:42.689128 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:47:42.696458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:47:42.699753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:47:42.703116 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:47:42.710171 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:47:42.713215 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:47:42.719863 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:47:42.723069 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:47:42.729696 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:47:42.733211 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:47:42.740353 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:47:42.743938 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:47:42.750954 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:47:42.753883 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:47:42.757612 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:47:42.760824 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:47:42.767343 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:47:42.770620 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:47:42.774321 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:47:42.780809 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:47:42.784406 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:47:42.787448 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:47:42.793770 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:47:42.797556 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:47:42.800556 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:47:42.807089 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:47:42.817394 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:47:42.820340 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:47:42.830828 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:47:42.837358 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:47:42.843648 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:47:42.847375 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:47:42.850249 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:47:42.858132 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1f
467 12:47:42.864795 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:47:42.867947 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 12:47:42.874353 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:47:42.882403 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 12:47:42.892303 [RTC]rtc_get_frequency_meter,154: input=7, output=708
472 12:47:42.902262 [RTC]rtc_get_frequency_meter,154: input=11, output=770
473 12:47:42.911345 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 12:47:42.920512 [RTC]rtc_get_frequency_meter,154: input=12, output=787
475 12:47:42.930246 [RTC]rtc_get_frequency_meter,154: input=12, output=787
476 12:47:42.940025 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 12:47:42.943375 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 12:47:42.950185 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 12:47:42.953580 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:47:42.956739 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:47:42.963917 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:47:42.967279 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:47:42.969942 ADC[4]: Raw value=905248 ID=7
484 12:47:42.970418 ADC[3]: Raw value=213282 ID=1
485 12:47:42.973472 RAM Code: 0x71
486 12:47:42.976737 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:47:42.983471 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:47:42.989947 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:47:42.996625 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:47:43.000068 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:47:43.003554 in-header: 03 07 00 00 08 00 00 00
492 12:47:43.006807 in-data: aa e4 47 04 13 02 00 00
493 12:47:43.009862 Chrome EC: UHEPI supported
494 12:47:43.016501 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:47:43.020129 in-header: 03 dd 00 00 08 00 00 00
496 12:47:43.022987 in-data: 90 20 60 08 00 00 00 00
497 12:47:43.026456 MRC: failed to locate region type 0.
498 12:47:43.033042 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:47:43.036556 DRAM-K: Running full calibration
500 12:47:43.043392 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:47:43.043985 header.status = 0x0
502 12:47:43.046275 header.version = 0x6 (expected: 0x6)
503 12:47:43.049609 header.size = 0xd00 (expected: 0xd00)
504 12:47:43.052786 header.flags = 0x0
505 12:47:43.059397 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:47:43.076220 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 12:47:43.083127 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:47:43.086313 dram_init: ddr_geometry: 2
509 12:47:43.089978 [EMI] MDL number = 2
510 12:47:43.090570 [EMI] Get MDL freq = 0
511 12:47:43.092784 dram_init: ddr_type: 0
512 12:47:43.093269 is_discrete_lpddr4: 1
513 12:47:43.096176 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:47:43.096705
515 12:47:43.097093
516 12:47:43.099547 [Bian_co] ETT version 0.0.0.1
517 12:47:43.106168 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:47:43.106750
519 12:47:43.110027 dramc_set_vcore_voltage set vcore to 650000
520 12:47:43.113017 Read voltage for 800, 4
521 12:47:43.113592 Vio18 = 0
522 12:47:43.114004 Vcore = 650000
523 12:47:43.116184 Vdram = 0
524 12:47:43.116838 Vddq = 0
525 12:47:43.117233 Vmddr = 0
526 12:47:43.119682 dram_init: config_dvfs: 1
527 12:47:43.123330 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:47:43.129605 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:47:43.133119 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 12:47:43.136099 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 12:47:43.140080 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 12:47:43.143115 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 12:47:43.146574 MEM_TYPE=3, freq_sel=18
534 12:47:43.150208 sv_algorithm_assistance_LP4_1600
535 12:47:43.153018 ============ PULL DRAM RESETB DOWN ============
536 12:47:43.156422 ========== PULL DRAM RESETB DOWN end =========
537 12:47:43.162679 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:47:43.165841 ===================================
539 12:47:43.170215 LPDDR4 DRAM CONFIGURATION
540 12:47:43.172892 ===================================
541 12:47:43.173376 EX_ROW_EN[0] = 0x0
542 12:47:43.175873 EX_ROW_EN[1] = 0x0
543 12:47:43.176352 LP4Y_EN = 0x0
544 12:47:43.179422 WORK_FSP = 0x0
545 12:47:43.179907 WL = 0x2
546 12:47:43.182405 RL = 0x2
547 12:47:43.182996 BL = 0x2
548 12:47:43.186214 RPST = 0x0
549 12:47:43.186806 RD_PRE = 0x0
550 12:47:43.189216 WR_PRE = 0x1
551 12:47:43.189689 WR_PST = 0x0
552 12:47:43.192635 DBI_WR = 0x0
553 12:47:43.193212 DBI_RD = 0x0
554 12:47:43.195801 OTF = 0x1
555 12:47:43.199754 ===================================
556 12:47:43.202651 ===================================
557 12:47:43.203169 ANA top config
558 12:47:43.205605 ===================================
559 12:47:43.208978 DLL_ASYNC_EN = 0
560 12:47:43.212248 ALL_SLAVE_EN = 1
561 12:47:43.215868 NEW_RANK_MODE = 1
562 12:47:43.219546 DLL_IDLE_MODE = 1
563 12:47:43.220121 LP45_APHY_COMB_EN = 1
564 12:47:43.222780 TX_ODT_DIS = 1
565 12:47:43.225802 NEW_8X_MODE = 1
566 12:47:43.229315 ===================================
567 12:47:43.232740 ===================================
568 12:47:43.236256 data_rate = 1600
569 12:47:43.239329 CKR = 1
570 12:47:43.239904 DQ_P2S_RATIO = 8
571 12:47:43.242427 ===================================
572 12:47:43.245895 CA_P2S_RATIO = 8
573 12:47:43.249168 DQ_CA_OPEN = 0
574 12:47:43.252684 DQ_SEMI_OPEN = 0
575 12:47:43.255419 CA_SEMI_OPEN = 0
576 12:47:43.259091 CA_FULL_RATE = 0
577 12:47:43.259667 DQ_CKDIV4_EN = 1
578 12:47:43.262277 CA_CKDIV4_EN = 1
579 12:47:43.265881 CA_PREDIV_EN = 0
580 12:47:43.269130 PH8_DLY = 0
581 12:47:43.272088 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:47:43.275955 DQ_AAMCK_DIV = 4
583 12:47:43.276571 CA_AAMCK_DIV = 4
584 12:47:43.278823 CA_ADMCK_DIV = 4
585 12:47:43.282139 DQ_TRACK_CA_EN = 0
586 12:47:43.285862 CA_PICK = 800
587 12:47:43.288896 CA_MCKIO = 800
588 12:47:43.292356 MCKIO_SEMI = 0
589 12:47:43.294972 PLL_FREQ = 3068
590 12:47:43.295453 DQ_UI_PI_RATIO = 32
591 12:47:43.298631 CA_UI_PI_RATIO = 0
592 12:47:43.302060 ===================================
593 12:47:43.305726 ===================================
594 12:47:43.308138 memory_type:LPDDR4
595 12:47:43.311608 GP_NUM : 10
596 12:47:43.312197 SRAM_EN : 1
597 12:47:43.314910 MD32_EN : 0
598 12:47:43.318400 ===================================
599 12:47:43.321788 [ANA_INIT] >>>>>>>>>>>>>>
600 12:47:43.322368 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:47:43.325492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:47:43.328395 ===================================
603 12:47:43.331744 data_rate = 1600,PCW = 0X7600
604 12:47:43.335424 ===================================
605 12:47:43.338271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:47:43.344738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:47:43.351222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:47:43.355099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:47:43.358022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:47:43.361458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:47:43.364688 [ANA_INIT] flow start
612 12:47:43.365269 [ANA_INIT] PLL >>>>>>>>
613 12:47:43.368437 [ANA_INIT] PLL <<<<<<<<
614 12:47:43.372398 [ANA_INIT] MIDPI >>>>>>>>
615 12:47:43.374375 [ANA_INIT] MIDPI <<<<<<<<
616 12:47:43.374854 [ANA_INIT] DLL >>>>>>>>
617 12:47:43.377886 [ANA_INIT] flow end
618 12:47:43.381408 ============ LP4 DIFF to SE enter ============
619 12:47:43.384676 ============ LP4 DIFF to SE exit ============
620 12:47:43.387575 [ANA_INIT] <<<<<<<<<<<<<
621 12:47:43.391340 [Flow] Enable top DCM control >>>>>
622 12:47:43.394112 [Flow] Enable top DCM control <<<<<
623 12:47:43.398042 Enable DLL master slave shuffle
624 12:47:43.404377 ==============================================================
625 12:47:43.404920 Gating Mode config
626 12:47:43.410935 ==============================================================
627 12:47:43.411521 Config description:
628 12:47:43.421126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:47:43.427819 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:47:43.434698 SELPH_MODE 0: By rank 1: By Phase
631 12:47:43.437814 ==============================================================
632 12:47:43.441100 GAT_TRACK_EN = 1
633 12:47:43.444372 RX_GATING_MODE = 2
634 12:47:43.447569 RX_GATING_TRACK_MODE = 2
635 12:47:43.451291 SELPH_MODE = 1
636 12:47:43.454671 PICG_EARLY_EN = 1
637 12:47:43.457660 VALID_LAT_VALUE = 1
638 12:47:43.460853 ==============================================================
639 12:47:43.464176 Enter into Gating configuration >>>>
640 12:47:43.467308 Exit from Gating configuration <<<<
641 12:47:43.470690 Enter into DVFS_PRE_config >>>>>
642 12:47:43.484634 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:47:43.487821 Exit from DVFS_PRE_config <<<<<
644 12:47:43.490937 Enter into PICG configuration >>>>
645 12:47:43.491517 Exit from PICG configuration <<<<
646 12:47:43.493988 [RX_INPUT] configuration >>>>>
647 12:47:43.498409 [RX_INPUT] configuration <<<<<
648 12:47:43.504094 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:47:43.508451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:47:43.514757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:47:43.521854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:47:43.525422 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:47:43.532200 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:47:43.535847 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:47:43.540078 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:47:43.546737 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:47:43.551034 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:47:43.554062 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:47:43.557163 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:47:43.561097 ===================================
661 12:47:43.564863 LPDDR4 DRAM CONFIGURATION
662 12:47:43.568618 ===================================
663 12:47:43.569205 EX_ROW_EN[0] = 0x0
664 12:47:43.572094 EX_ROW_EN[1] = 0x0
665 12:47:43.572708 LP4Y_EN = 0x0
666 12:47:43.575907 WORK_FSP = 0x0
667 12:47:43.576552 WL = 0x2
668 12:47:43.579481 RL = 0x2
669 12:47:43.579958 BL = 0x2
670 12:47:43.583420 RPST = 0x0
671 12:47:43.584007 RD_PRE = 0x0
672 12:47:43.586974 WR_PRE = 0x1
673 12:47:43.587451 WR_PST = 0x0
674 12:47:43.587836 DBI_WR = 0x0
675 12:47:43.590957 DBI_RD = 0x0
676 12:47:43.591546 OTF = 0x1
677 12:47:43.594396 ===================================
678 12:47:43.598506 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:47:43.602141 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:47:43.609104 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:47:43.612667 ===================================
682 12:47:43.613255 LPDDR4 DRAM CONFIGURATION
683 12:47:43.616285 ===================================
684 12:47:43.620030 EX_ROW_EN[0] = 0x10
685 12:47:43.620768 EX_ROW_EN[1] = 0x0
686 12:47:43.623685 LP4Y_EN = 0x0
687 12:47:43.624160 WORK_FSP = 0x0
688 12:47:43.627651 WL = 0x2
689 12:47:43.628129 RL = 0x2
690 12:47:43.630857 BL = 0x2
691 12:47:43.631336 RPST = 0x0
692 12:47:43.631717 RD_PRE = 0x0
693 12:47:43.634564 WR_PRE = 0x1
694 12:47:43.635042 WR_PST = 0x0
695 12:47:43.638208 DBI_WR = 0x0
696 12:47:43.638683 DBI_RD = 0x0
697 12:47:43.642134 OTF = 0x1
698 12:47:43.645839 ===================================
699 12:47:43.648879 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:47:43.654677 nWR fixed to 40
701 12:47:43.658636 [ModeRegInit_LP4] CH0 RK0
702 12:47:43.659064 [ModeRegInit_LP4] CH0 RK1
703 12:47:43.662325 [ModeRegInit_LP4] CH1 RK0
704 12:47:43.665723 [ModeRegInit_LP4] CH1 RK1
705 12:47:43.666256 match AC timing 13
706 12:47:43.668739 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:47:43.675562 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:47:43.678635 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:47:43.682543 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:47:43.689004 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:47:43.689593 [EMI DOE] emi_dcm 0
712 12:47:43.695624 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:47:43.696206 ==
714 12:47:43.698856 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:47:43.702329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:47:43.702811 ==
717 12:47:43.705692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:47:43.712475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:47:43.722395 [CA 0] Center 37 (7~68) winsize 62
720 12:47:43.725558 [CA 1] Center 37 (6~68) winsize 63
721 12:47:43.728966 [CA 2] Center 34 (4~65) winsize 62
722 12:47:43.731784 [CA 3] Center 34 (4~65) winsize 62
723 12:47:43.735855 [CA 4] Center 33 (3~64) winsize 62
724 12:47:43.739514 [CA 5] Center 33 (3~64) winsize 62
725 12:47:43.740111
726 12:47:43.742688 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:47:43.743190
728 12:47:43.745801 [CATrainingPosCal] consider 1 rank data
729 12:47:43.749285 u2DelayCellTimex100 = 270/100 ps
730 12:47:43.752868 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:47:43.755756 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 12:47:43.759492 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 12:47:43.766238 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:47:43.769117 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 12:47:43.772569 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:47:43.773150
737 12:47:43.775613 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:47:43.776188
739 12:47:43.778599 [CBTSetCACLKResult] CA Dly = 33
740 12:47:43.779073 CS Dly: 7 (0~38)
741 12:47:43.779454 ==
742 12:47:43.782224 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:47:43.788788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:47:43.789368 ==
745 12:47:43.792298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:47:43.798754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:47:43.808252 [CA 0] Center 37 (6~68) winsize 63
748 12:47:43.811614 [CA 1] Center 37 (7~68) winsize 62
749 12:47:43.814929 [CA 2] Center 34 (4~65) winsize 62
750 12:47:43.818148 [CA 3] Center 34 (4~65) winsize 62
751 12:47:43.821654 [CA 4] Center 33 (3~64) winsize 62
752 12:47:43.825000 [CA 5] Center 33 (3~64) winsize 62
753 12:47:43.825600
754 12:47:43.828026 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 12:47:43.828504
756 12:47:43.831543 [CATrainingPosCal] consider 2 rank data
757 12:47:43.835301 u2DelayCellTimex100 = 270/100 ps
758 12:47:43.838304 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:47:43.844899 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 12:47:43.848260 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 12:47:43.852204 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:47:43.855305 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 12:47:43.859329 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:47:43.859912
765 12:47:43.862633 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:47:43.863116
767 12:47:43.866453 [CBTSetCACLKResult] CA Dly = 33
768 12:47:43.866934 CS Dly: 7 (0~38)
769 12:47:43.867322
770 12:47:43.870409 ----->DramcWriteLeveling(PI) begin...
771 12:47:43.870901 ==
772 12:47:43.874505 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:47:43.877435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:47:43.877943 ==
775 12:47:43.881442 Write leveling (Byte 0): 34 => 34
776 12:47:43.884720 Write leveling (Byte 1): 29 => 29
777 12:47:43.887811 DramcWriteLeveling(PI) end<-----
778 12:47:43.888382
779 12:47:43.888872 ==
780 12:47:43.891473 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:47:43.894778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:47:43.895400 ==
783 12:47:43.897883 [Gating] SW mode calibration
784 12:47:43.904746 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:47:43.911190 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:47:43.914485 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:47:43.917714 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:47:43.924228 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 12:47:43.927571 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:47:43.930968 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:47:43.938016 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:47:43.941036 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:47:43.944468 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:47:43.947606 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:47:43.954303 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:47:43.957434 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:47:43.960892 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:47:43.967762 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:47:43.970640 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:47:43.974125 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:47:43.981141 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:47:43.984892 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:47:43.987400 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 12:47:43.994058 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 12:47:43.997652 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:47:44.001428 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:47:44.007296 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:47:44.010765 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:47:44.014193 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:47:44.021129 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:47:44.023728 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:47:44.027865 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
813 12:47:44.033789 0 9 12 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
814 12:47:44.037122 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:47:44.040131 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:47:44.047286 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:47:44.050539 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:47:44.053819 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:47:44.060304 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:47:44.063508 0 10 8 | B1->B0 | 3434 2a2a | 1 1 | (1 0) (1 0)
821 12:47:44.066748 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
822 12:47:44.073870 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:47:44.076943 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:47:44.080252 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:47:44.086558 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:47:44.090357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:47:44.094041 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
828 12:47:44.100561 0 11 8 | B1->B0 | 2626 3838 | 0 1 | (0 0) (0 0)
829 12:47:44.103370 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
830 12:47:44.107116 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:47:44.113324 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:47:44.116288 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:47:44.120410 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:47:44.126654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:47:44.129910 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:47:44.133034 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 12:47:44.140057 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:47:44.143147 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:47:44.146197 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:47:44.150028 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:47:44.156432 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:47:44.159751 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:47:44.163160 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:47:44.170092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:47:44.172825 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:47:44.176465 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:47:44.183168 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:47:44.186841 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:47:44.190252 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:47:44.196088 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:47:44.199505 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:47:44.202910 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 12:47:44.209406 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 12:47:44.212837 Total UI for P1: 0, mck2ui 16
855 12:47:44.216491 best dqsien dly found for B0: ( 0, 14, 8)
856 12:47:44.220297 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:47:44.222559 Total UI for P1: 0, mck2ui 16
858 12:47:44.226543 best dqsien dly found for B1: ( 0, 14, 12)
859 12:47:44.229322 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 12:47:44.232645 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 12:47:44.233124
862 12:47:44.236296 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:47:44.240474 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 12:47:44.243833 [Gating] SW calibration Done
865 12:47:44.244405 ==
866 12:47:44.247267 Dram Type= 6, Freq= 0, CH_0, rank 0
867 12:47:44.250033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 12:47:44.250510 ==
869 12:47:44.253513 RX Vref Scan: 0
870 12:47:44.253984
871 12:47:44.254360 RX Vref 0 -> 0, step: 1
872 12:47:44.254713
873 12:47:44.256878 RX Delay -130 -> 252, step: 16
874 12:47:44.260408 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 12:47:44.266685 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 12:47:44.269969 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 12:47:44.273531 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 12:47:44.276998 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 12:47:44.280454 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 12:47:44.287352 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
881 12:47:44.290120 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 12:47:44.293289 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 12:47:44.296611 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 12:47:44.303330 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 12:47:44.306667 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 12:47:44.310456 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
887 12:47:44.313430 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
888 12:47:44.317170 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 12:47:44.320674 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
890 12:47:44.321389 ==
891 12:47:44.324595 Dram Type= 6, Freq= 0, CH_0, rank 0
892 12:47:44.328020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 12:47:44.331576 ==
894 12:47:44.332219 DQS Delay:
895 12:47:44.332651 DQS0 = 0, DQS1 = 0
896 12:47:44.335581 DQM Delay:
897 12:47:44.336176 DQM0 = 84, DQM1 = 74
898 12:47:44.336602 DQ Delay:
899 12:47:44.338932 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 12:47:44.342545 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
901 12:47:44.346283 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
902 12:47:44.349627 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
903 12:47:44.350207
904 12:47:44.350743
905 12:47:44.351115 ==
906 12:47:44.353450 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:47:44.357015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:47:44.357496 ==
909 12:47:44.358037
910 12:47:44.358524
911 12:47:44.360630 TX Vref Scan disable
912 12:47:44.364254 == TX Byte 0 ==
913 12:47:44.368086 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
914 12:47:44.372714 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
915 12:47:44.373352 == TX Byte 1 ==
916 12:47:44.375560 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 12:47:44.379707 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 12:47:44.383260 ==
919 12:47:44.383788 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:47:44.390370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:47:44.390972 ==
922 12:47:44.402719 TX Vref=22, minBit 5, minWin=27, winSum=439
923 12:47:44.406197 TX Vref=24, minBit 8, minWin=27, winSum=444
924 12:47:44.409943 TX Vref=26, minBit 3, minWin=27, winSum=444
925 12:47:44.413924 TX Vref=28, minBit 8, minWin=27, winSum=449
926 12:47:44.416729 TX Vref=30, minBit 8, minWin=27, winSum=446
927 12:47:44.419892 TX Vref=32, minBit 4, minWin=27, winSum=446
928 12:47:44.426666 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 28
929 12:47:44.427244
930 12:47:44.430152 Final TX Range 1 Vref 28
931 12:47:44.430790
932 12:47:44.431181 ==
933 12:47:44.433364 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:47:44.437208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:47:44.437714 ==
936 12:47:44.438196
937 12:47:44.438558
938 12:47:44.440317 TX Vref Scan disable
939 12:47:44.440891 == TX Byte 0 ==
940 12:47:44.448165 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
941 12:47:44.452055 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
942 12:47:44.452698 == TX Byte 1 ==
943 12:47:44.454941 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 12:47:44.458644 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 12:47:44.461982
946 12:47:44.462514 [DATLAT]
947 12:47:44.463062 Freq=800, CH0 RK0
948 12:47:44.463478
949 12:47:44.465814 DATLAT Default: 0xa
950 12:47:44.466276 0, 0xFFFF, sum = 0
951 12:47:44.469028 1, 0xFFFF, sum = 0
952 12:47:44.469482 2, 0xFFFF, sum = 0
953 12:47:44.472086 3, 0xFFFF, sum = 0
954 12:47:44.472540 4, 0xFFFF, sum = 0
955 12:47:44.475166 5, 0xFFFF, sum = 0
956 12:47:44.475603 6, 0xFFFF, sum = 0
957 12:47:44.478603 7, 0xFFFF, sum = 0
958 12:47:44.482299 8, 0xFFFF, sum = 0
959 12:47:44.482738 9, 0x0, sum = 1
960 12:47:44.483089 10, 0x0, sum = 2
961 12:47:44.485261 11, 0x0, sum = 3
962 12:47:44.485700 12, 0x0, sum = 4
963 12:47:44.488375 best_step = 10
964 12:47:44.488843
965 12:47:44.489191 ==
966 12:47:44.491714 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:47:44.495748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:47:44.496282 ==
969 12:47:44.499141 RX Vref Scan: 1
970 12:47:44.499668
971 12:47:44.500017 Set Vref Range= 32 -> 127
972 12:47:44.500341
973 12:47:44.502360 RX Vref 32 -> 127, step: 1
974 12:47:44.502889
975 12:47:44.505459 RX Delay -95 -> 252, step: 8
976 12:47:44.505987
977 12:47:44.508683 Set Vref, RX VrefLevel [Byte0]: 32
978 12:47:44.512441 [Byte1]: 32
979 12:47:44.513014
980 12:47:44.515765 Set Vref, RX VrefLevel [Byte0]: 33
981 12:47:44.518736 [Byte1]: 33
982 12:47:44.522760
983 12:47:44.523287 Set Vref, RX VrefLevel [Byte0]: 34
984 12:47:44.526088 [Byte1]: 34
985 12:47:44.530236
986 12:47:44.530870 Set Vref, RX VrefLevel [Byte0]: 35
987 12:47:44.533075 [Byte1]: 35
988 12:47:44.538520
989 12:47:44.539056 Set Vref, RX VrefLevel [Byte0]: 36
990 12:47:44.541064 [Byte1]: 36
991 12:47:44.545178
992 12:47:44.545717 Set Vref, RX VrefLevel [Byte0]: 37
993 12:47:44.548605 [Byte1]: 37
994 12:47:44.553110
995 12:47:44.553647 Set Vref, RX VrefLevel [Byte0]: 38
996 12:47:44.556590 [Byte1]: 38
997 12:47:44.560498
998 12:47:44.560985 Set Vref, RX VrefLevel [Byte0]: 39
999 12:47:44.563687 [Byte1]: 39
1000 12:47:44.568192
1001 12:47:44.568766 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:47:44.571195 [Byte1]: 40
1003 12:47:44.575459
1004 12:47:44.575906 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:47:44.578790 [Byte1]: 41
1006 12:47:44.583218
1007 12:47:44.583763 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:47:44.586297 [Byte1]: 42
1009 12:47:44.590782
1010 12:47:44.591267 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:47:44.594301 [Byte1]: 43
1012 12:47:44.597987
1013 12:47:44.598461 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:47:44.601318 [Byte1]: 44
1015 12:47:44.606208
1016 12:47:44.606784 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:47:44.608998 [Byte1]: 45
1018 12:47:44.613462
1019 12:47:44.614050 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:47:44.616923 [Byte1]: 46
1021 12:47:44.621247
1022 12:47:44.621820 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:47:44.624481 [Byte1]: 47
1024 12:47:44.629077
1025 12:47:44.629664 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:47:44.631711 [Byte1]: 48
1027 12:47:44.636626
1028 12:47:44.637184 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:47:44.639691 [Byte1]: 49
1030 12:47:44.643969
1031 12:47:44.644430 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:47:44.647456 [Byte1]: 50
1033 12:47:44.651569
1034 12:47:44.652128 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:47:44.654665 [Byte1]: 51
1036 12:47:44.658825
1037 12:47:44.659286 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:47:44.662173 [Byte1]: 52
1039 12:47:44.666726
1040 12:47:44.667286 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:47:44.670098 [Byte1]: 53
1042 12:47:44.674305
1043 12:47:44.674867 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:47:44.677257 [Byte1]: 54
1045 12:47:44.681731
1046 12:47:44.682294 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:47:44.685451 [Byte1]: 55
1048 12:47:44.689676
1049 12:47:44.690253 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:47:44.693123 [Byte1]: 56
1051 12:47:44.696960
1052 12:47:44.697422 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:47:44.700005 [Byte1]: 57
1054 12:47:44.704716
1055 12:47:44.705424 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:47:44.707840 [Byte1]: 58
1057 12:47:44.712000
1058 12:47:44.712624 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:47:44.715422 [Byte1]: 59
1060 12:47:44.720206
1061 12:47:44.720805 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:47:44.722836 [Byte1]: 60
1063 12:47:44.727447
1064 12:47:44.728007 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:47:44.730460 [Byte1]: 61
1066 12:47:44.735521
1067 12:47:44.736083 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:47:44.738216 [Byte1]: 62
1069 12:47:44.742769
1070 12:47:44.743336 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:47:44.745550 [Byte1]: 63
1072 12:47:44.750269
1073 12:47:44.750730 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:47:44.754021 [Byte1]: 64
1075 12:47:44.757955
1076 12:47:44.758518 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:47:44.760980 [Byte1]: 65
1078 12:47:44.764955
1079 12:47:44.765438 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:47:44.768684 [Byte1]: 66
1081 12:47:44.773286
1082 12:47:44.773849 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:47:44.776389 [Byte1]: 67
1084 12:47:44.780868
1085 12:47:44.781343 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:47:44.783750 [Byte1]: 68
1087 12:47:44.788051
1088 12:47:44.788585 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:47:44.791165 [Byte1]: 69
1090 12:47:44.795851
1091 12:47:44.796313 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:47:44.799360 [Byte1]: 70
1093 12:47:44.803347
1094 12:47:44.803898 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:47:44.807309 [Byte1]: 71
1096 12:47:44.810847
1097 12:47:44.811371 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:47:44.814410 [Byte1]: 72
1099 12:47:44.818150
1100 12:47:44.818612 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:47:44.821902 [Byte1]: 73
1102 12:47:44.826217
1103 12:47:44.826679 Set Vref, RX VrefLevel [Byte0]: 74
1104 12:47:44.829771 [Byte1]: 74
1105 12:47:44.833187
1106 12:47:44.836943 Set Vref, RX VrefLevel [Byte0]: 75
1107 12:47:44.837535 [Byte1]: 75
1108 12:47:44.840949
1109 12:47:44.841420 Set Vref, RX VrefLevel [Byte0]: 76
1110 12:47:44.844358 [Byte1]: 76
1111 12:47:44.849125
1112 12:47:44.849688 Set Vref, RX VrefLevel [Byte0]: 77
1113 12:47:44.851745 [Byte1]: 77
1114 12:47:44.856806
1115 12:47:44.857376 Set Vref, RX VrefLevel [Byte0]: 78
1116 12:47:44.859366 [Byte1]: 78
1117 12:47:44.864249
1118 12:47:44.864857 Set Vref, RX VrefLevel [Byte0]: 79
1119 12:47:44.867645 [Byte1]: 79
1120 12:47:44.871576
1121 12:47:44.872037 Set Vref, RX VrefLevel [Byte0]: 80
1122 12:47:44.874828 [Byte1]: 80
1123 12:47:44.879360
1124 12:47:44.879923 Set Vref, RX VrefLevel [Byte0]: 81
1125 12:47:44.882925 [Byte1]: 81
1126 12:47:44.886904
1127 12:47:44.887514 Set Vref, RX VrefLevel [Byte0]: 82
1128 12:47:44.890026 [Byte1]: 82
1129 12:47:44.895146
1130 12:47:44.895712 Final RX Vref Byte 0 = 68 to rank0
1131 12:47:44.898278 Final RX Vref Byte 1 = 49 to rank0
1132 12:47:44.902092 Final RX Vref Byte 0 = 68 to rank1
1133 12:47:44.906029 Final RX Vref Byte 1 = 49 to rank1==
1134 12:47:44.909254 Dram Type= 6, Freq= 0, CH_0, rank 0
1135 12:47:44.913055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 12:47:44.913521 ==
1137 12:47:44.914016 DQS Delay:
1138 12:47:44.915995 DQS0 = 0, DQS1 = 0
1139 12:47:44.916413 DQM Delay:
1140 12:47:44.919479 DQM0 = 89, DQM1 = 76
1141 12:47:44.920096 DQ Delay:
1142 12:47:44.922815 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1143 12:47:44.926093 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =100
1144 12:47:44.929615 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1145 12:47:44.932537 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1146 12:47:44.933123
1147 12:47:44.933500
1148 12:47:44.942611 [DQSOSCAuto] RK0, (LSB)MR18= 0x4224, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1149 12:47:44.943183 CH0 RK0: MR19=606, MR18=4224
1150 12:47:44.949499 CH0_RK0: MR19=0x606, MR18=0x4224, DQSOSC=393, MR23=63, INC=95, DEC=63
1151 12:47:44.950064
1152 12:47:44.952629 ----->DramcWriteLeveling(PI) begin...
1153 12:47:44.953101 ==
1154 12:47:44.956051 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 12:47:44.962843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 12:47:44.963416 ==
1157 12:47:44.965959 Write leveling (Byte 0): 31 => 31
1158 12:47:44.968950 Write leveling (Byte 1): 31 => 31
1159 12:47:44.969417 DramcWriteLeveling(PI) end<-----
1160 12:47:44.969783
1161 12:47:45.013210 ==
1162 12:47:45.013964 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 12:47:45.014727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 12:47:45.015209 ==
1165 12:47:45.015734 [Gating] SW mode calibration
1166 12:47:45.016149 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1167 12:47:45.016641 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1168 12:47:45.017002 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 12:47:45.017337 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 12:47:45.017658 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1171 12:47:45.017974 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1172 12:47:45.029021 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:47:45.029575 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:47:45.030260 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:47:45.031791 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:47:45.035251 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:47:45.039485 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:47:45.042355 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:47:45.045479 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:47:45.052221 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:47:45.055311 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:47:45.059200 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:47:45.065510 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:47:45.068617 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:47:45.072180 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1186 12:47:45.079442 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1187 12:47:45.081542 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1188 12:47:45.085251 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:47:45.088108 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:47:45.095043 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:47:45.098552 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:47:45.101959 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:47:45.108424 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:47:45.111824 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1195 12:47:45.114896 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
1196 12:47:45.121683 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 12:47:45.124883 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 12:47:45.128741 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 12:47:45.134818 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 12:47:45.138689 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 12:47:45.141711 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1202 12:47:45.148615 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (0 0)
1203 12:47:45.151881 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1204 12:47:45.155376 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:47:45.161360 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:47:45.165163 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:47:45.168107 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:47:45.174894 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:47:45.178159 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1210 12:47:45.181373 0 11 8 | B1->B0 | 2f2f 3b3b | 1 0 | (0 0) (0 0)
1211 12:47:45.188124 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:47:45.191156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 12:47:45.194507 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 12:47:45.201602 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 12:47:45.204894 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 12:47:45.207537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 12:47:45.214663 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1218 12:47:45.217591 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1219 12:47:45.220950 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1220 12:47:45.227930 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:47:45.230904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:47:45.234239 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:47:45.240864 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:47:45.245464 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:47:45.247933 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:47:45.254369 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:47:45.257707 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:47:45.261024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 12:47:45.267177 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 12:47:45.270796 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 12:47:45.274129 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 12:47:45.278198 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 12:47:45.284123 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 12:47:45.287770 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 12:47:45.290953 Total UI for P1: 0, mck2ui 16
1236 12:47:45.293746 best dqsien dly found for B0: ( 0, 14, 6)
1237 12:47:45.297433 Total UI for P1: 0, mck2ui 16
1238 12:47:45.301088 best dqsien dly found for B1: ( 0, 14, 6)
1239 12:47:45.304558 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1240 12:47:45.307268 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1241 12:47:45.307829
1242 12:47:45.310648 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1243 12:47:45.314242 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1244 12:47:45.317093 [Gating] SW calibration Done
1245 12:47:45.317715 ==
1246 12:47:45.320361 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 12:47:45.327574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 12:47:45.328126 ==
1249 12:47:45.328499 RX Vref Scan: 0
1250 12:47:45.328883
1251 12:47:45.330496 RX Vref 0 -> 0, step: 1
1252 12:47:45.330957
1253 12:47:45.333604 RX Delay -130 -> 252, step: 16
1254 12:47:45.337122 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1255 12:47:45.340344 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1256 12:47:45.343953 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1257 12:47:45.347632 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1258 12:47:45.354967 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1259 12:47:45.358805 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1260 12:47:45.361477 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1261 12:47:45.365396 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1262 12:47:45.369867 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1263 12:47:45.372469 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1264 12:47:45.376000 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1265 12:47:45.379884 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1266 12:47:45.383807 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1267 12:47:45.387973 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1268 12:47:45.395040 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1269 12:47:45.398802 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1270 12:47:45.399271 ==
1271 12:47:45.402456 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 12:47:45.405888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 12:47:45.406488 ==
1274 12:47:45.406867 DQS Delay:
1275 12:47:45.409119 DQS0 = 0, DQS1 = 0
1276 12:47:45.409580 DQM Delay:
1277 12:47:45.409950 DQM0 = 83, DQM1 = 78
1278 12:47:45.412956 DQ Delay:
1279 12:47:45.416391 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1280 12:47:45.416884 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1281 12:47:45.420644 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1282 12:47:45.423998 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1283 12:47:45.424644
1284 12:47:45.425027
1285 12:47:45.425369 ==
1286 12:47:45.426986 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:47:45.430855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:47:45.434286 ==
1289 12:47:45.434748
1290 12:47:45.435115
1291 12:47:45.435456 TX Vref Scan disable
1292 12:47:45.437955 == TX Byte 0 ==
1293 12:47:45.441751 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1294 12:47:45.445048 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1295 12:47:45.448915 == TX Byte 1 ==
1296 12:47:45.452805 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1297 12:47:45.456195 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1298 12:47:45.456714 ==
1299 12:47:45.459643 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 12:47:45.462962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 12:47:45.463422 ==
1302 12:47:45.476747 TX Vref=22, minBit 5, minWin=27, winSum=442
1303 12:47:45.480679 TX Vref=24, minBit 9, minWin=27, winSum=449
1304 12:47:45.483765 TX Vref=26, minBit 12, minWin=27, winSum=449
1305 12:47:45.487629 TX Vref=28, minBit 8, minWin=27, winSum=448
1306 12:47:45.491068 TX Vref=30, minBit 8, minWin=27, winSum=448
1307 12:47:45.494926 TX Vref=32, minBit 4, minWin=27, winSum=444
1308 12:47:45.502332 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 24
1309 12:47:45.502868
1310 12:47:45.503205 Final TX Range 1 Vref 24
1311 12:47:45.503513
1312 12:47:45.503802 ==
1313 12:47:45.505991 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 12:47:45.509109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 12:47:45.509577 ==
1316 12:47:45.512505
1317 12:47:45.513012
1318 12:47:45.513338 TX Vref Scan disable
1319 12:47:45.517014 == TX Byte 0 ==
1320 12:47:45.520108 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1321 12:47:45.523958 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1322 12:47:45.527543 == TX Byte 1 ==
1323 12:47:45.531469 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1324 12:47:45.535255 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1325 12:47:45.535737
1326 12:47:45.536102 [DATLAT]
1327 12:47:45.538935 Freq=800, CH0 RK1
1328 12:47:45.539582
1329 12:47:45.539956 DATLAT Default: 0xa
1330 12:47:45.542142 0, 0xFFFF, sum = 0
1331 12:47:45.542623 1, 0xFFFF, sum = 0
1332 12:47:45.545705 2, 0xFFFF, sum = 0
1333 12:47:45.546169 3, 0xFFFF, sum = 0
1334 12:47:45.549460 4, 0xFFFF, sum = 0
1335 12:47:45.549916 5, 0xFFFF, sum = 0
1336 12:47:45.550287 6, 0xFFFF, sum = 0
1337 12:47:45.553164 7, 0xFFFF, sum = 0
1338 12:47:45.553623 8, 0xFFFF, sum = 0
1339 12:47:45.557070 9, 0x0, sum = 1
1340 12:47:45.557532 10, 0x0, sum = 2
1341 12:47:45.560920 11, 0x0, sum = 3
1342 12:47:45.561466 12, 0x0, sum = 4
1343 12:47:45.561807 best_step = 10
1344 12:47:45.562111
1345 12:47:45.565161 ==
1346 12:47:45.565686 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 12:47:45.571172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 12:47:45.571714 ==
1349 12:47:45.572055 RX Vref Scan: 0
1350 12:47:45.572381
1351 12:47:45.575179 RX Vref 0 -> 0, step: 1
1352 12:47:45.575717
1353 12:47:45.576063 RX Delay -95 -> 252, step: 8
1354 12:47:45.583243 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1355 12:47:45.586913 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1356 12:47:45.590037 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1357 12:47:45.594342 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1358 12:47:45.597554 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1359 12:47:45.600705 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1360 12:47:45.604349 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1361 12:47:45.607850 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1362 12:47:45.615619 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1363 12:47:45.619520 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1364 12:47:45.622254 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1365 12:47:45.625805 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1366 12:47:45.629351 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1367 12:47:45.633410 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1368 12:47:45.637160 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1369 12:47:45.640761 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1370 12:47:45.641261 ==
1371 12:47:45.644701 Dram Type= 6, Freq= 0, CH_0, rank 1
1372 12:47:45.648335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 12:47:45.648834 ==
1374 12:47:45.651741 DQS Delay:
1375 12:47:45.652226 DQS0 = 0, DQS1 = 0
1376 12:47:45.655343 DQM Delay:
1377 12:47:45.655796 DQM0 = 86, DQM1 = 76
1378 12:47:45.656155 DQ Delay:
1379 12:47:45.659482 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1380 12:47:45.662723 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =100
1381 12:47:45.666370 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1382 12:47:45.670390 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1383 12:47:45.670930
1384 12:47:45.671264
1385 12:47:45.677574 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e05, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
1386 12:47:45.681258 CH0 RK1: MR19=606, MR18=3E05
1387 12:47:45.684980 CH0_RK1: MR19=0x606, MR18=0x3E05, DQSOSC=394, MR23=63, INC=95, DEC=63
1388 12:47:45.689186 [RxdqsGatingPostProcess] freq 800
1389 12:47:45.695517 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1390 12:47:45.699281 Pre-setting of DQS Precalculation
1391 12:47:45.703441 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1392 12:47:45.704003 ==
1393 12:47:45.706562 Dram Type= 6, Freq= 0, CH_1, rank 0
1394 12:47:45.710068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 12:47:45.710662 ==
1396 12:47:45.717565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1397 12:47:45.721490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1398 12:47:45.731453 [CA 0] Center 36 (6~67) winsize 62
1399 12:47:45.734902 [CA 1] Center 36 (6~67) winsize 62
1400 12:47:45.738550 [CA 2] Center 34 (4~65) winsize 62
1401 12:47:45.742147 [CA 3] Center 34 (3~65) winsize 63
1402 12:47:45.745401 [CA 4] Center 34 (4~65) winsize 62
1403 12:47:45.749200 [CA 5] Center 34 (3~65) winsize 63
1404 12:47:45.749832
1405 12:47:45.753763 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1406 12:47:45.754219
1407 12:47:45.756715 [CATrainingPosCal] consider 1 rank data
1408 12:47:45.760267 u2DelayCellTimex100 = 270/100 ps
1409 12:47:45.763309 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1410 12:47:45.766638 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1411 12:47:45.769785 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 12:47:45.773378 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 12:47:45.776755 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 12:47:45.780092 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1415 12:47:45.780700
1416 12:47:45.783444 CA PerBit enable=1, Macro0, CA PI delay=34
1417 12:47:45.783913
1418 12:47:45.786593 [CBTSetCACLKResult] CA Dly = 34
1419 12:47:45.789937 CS Dly: 4 (0~35)
1420 12:47:45.790491 ==
1421 12:47:45.792981 Dram Type= 6, Freq= 0, CH_1, rank 1
1422 12:47:45.796279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 12:47:45.796897 ==
1424 12:47:45.802963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1425 12:47:45.809264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1426 12:47:45.817169 [CA 0] Center 36 (6~67) winsize 62
1427 12:47:45.820703 [CA 1] Center 37 (6~68) winsize 63
1428 12:47:45.824119 [CA 2] Center 34 (4~65) winsize 62
1429 12:47:45.827260 [CA 3] Center 34 (3~65) winsize 63
1430 12:47:45.830641 [CA 4] Center 34 (4~65) winsize 62
1431 12:47:45.834237 [CA 5] Center 34 (4~65) winsize 62
1432 12:47:45.834833
1433 12:47:45.837125 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1434 12:47:45.837710
1435 12:47:45.840295 [CATrainingPosCal] consider 2 rank data
1436 12:47:45.844187 u2DelayCellTimex100 = 270/100 ps
1437 12:47:45.847235 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1438 12:47:45.850609 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 12:47:45.856993 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1440 12:47:45.860933 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1441 12:47:45.865008 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 12:47:45.867041 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 12:47:45.867511
1444 12:47:45.870201 CA PerBit enable=1, Macro0, CA PI delay=34
1445 12:47:45.870667
1446 12:47:45.873767 [CBTSetCACLKResult] CA Dly = 34
1447 12:47:45.874272 CS Dly: 5 (0~38)
1448 12:47:45.877206
1449 12:47:45.880490 ----->DramcWriteLeveling(PI) begin...
1450 12:47:45.881123 ==
1451 12:47:45.883700 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 12:47:45.887396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 12:47:45.887971 ==
1454 12:47:45.890357 Write leveling (Byte 0): 27 => 27
1455 12:47:45.893824 Write leveling (Byte 1): 28 => 28
1456 12:47:45.897049 DramcWriteLeveling(PI) end<-----
1457 12:47:45.897515
1458 12:47:45.897880 ==
1459 12:47:45.899953 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 12:47:45.904238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1461 12:47:45.904862 ==
1462 12:47:45.906848 [Gating] SW mode calibration
1463 12:47:45.913778 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1464 12:47:45.920503 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1465 12:47:45.923866 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1466 12:47:45.927200 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1467 12:47:45.933574 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1468 12:47:45.937437 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:47:45.940449 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:47:45.946486 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:47:45.950691 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:47:45.953538 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:47:45.956793 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:47:45.963188 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:47:45.967376 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:47:45.970053 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:47:45.976752 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:47:45.980324 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:47:45.983713 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:47:45.989837 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:47:45.993570 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:47:45.996960 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1483 12:47:46.003710 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1484 12:47:46.007014 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:47:46.009863 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:47:46.016393 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:47:46.019568 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:47:46.023114 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:47:46.029811 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:47:46.033014 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:47:46.035987 0 9 8 | B1->B0 | 2929 3030 | 0 1 | (1 1) (1 1)
1492 12:47:46.042962 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 12:47:46.046033 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 12:47:46.049289 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 12:47:46.056090 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 12:47:46.059448 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 12:47:46.062927 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 12:47:46.069756 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
1499 12:47:46.072888 0 10 8 | B1->B0 | 2e2e 2a2a | 1 1 | (1 0) (0 0)
1500 12:47:46.076852 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:47:46.082732 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:47:46.085952 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:47:46.090080 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:47:46.095999 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:47:46.099538 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:47:46.102640 0 11 4 | B1->B0 | 2827 2b2b | 1 0 | (0 0) (0 0)
1507 12:47:46.109607 0 11 8 | B1->B0 | 4040 3b3a | 1 1 | (0 0) (0 0)
1508 12:47:46.112805 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:47:46.115932 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 12:47:46.119523 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 12:47:46.125995 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 12:47:46.129081 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 12:47:46.132681 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 12:47:46.139524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1515 12:47:46.143025 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:47:46.145828 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:47:46.152579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:47:46.155796 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:47:46.159255 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:47:46.166177 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:47:46.169252 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:47:46.172999 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:47:46.179206 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:47:46.182485 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:47:46.185878 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:47:46.192487 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:47:46.195436 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 12:47:46.199345 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 12:47:46.205552 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 12:47:46.209093 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1531 12:47:46.212611 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1532 12:47:46.215423 Total UI for P1: 0, mck2ui 16
1533 12:47:46.219746 best dqsien dly found for B0: ( 0, 14, 4)
1534 12:47:46.226164 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 12:47:46.226734 Total UI for P1: 0, mck2ui 16
1536 12:47:46.228726 best dqsien dly found for B1: ( 0, 14, 8)
1537 12:47:46.235804 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1538 12:47:46.239174 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1539 12:47:46.239756
1540 12:47:46.243037 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1541 12:47:46.246106 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1542 12:47:46.248994 [Gating] SW calibration Done
1543 12:47:46.249459 ==
1544 12:47:46.252121 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 12:47:46.255738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 12:47:46.256312 ==
1547 12:47:46.258454 RX Vref Scan: 0
1548 12:47:46.258917
1549 12:47:46.259286 RX Vref 0 -> 0, step: 1
1550 12:47:46.259630
1551 12:47:46.262346 RX Delay -130 -> 252, step: 16
1552 12:47:46.265677 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1553 12:47:46.272027 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1554 12:47:46.275354 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1555 12:47:46.278613 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1556 12:47:46.282023 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1557 12:47:46.285399 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1558 12:47:46.292191 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1559 12:47:46.295165 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1560 12:47:46.298843 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1561 12:47:46.301652 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1562 12:47:46.305650 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1563 12:47:46.311773 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1564 12:47:46.315470 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1565 12:47:46.318617 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1566 12:47:46.321345 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1567 12:47:46.328789 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1568 12:47:46.329361 ==
1569 12:47:46.331536 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 12:47:46.335144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 12:47:46.335618 ==
1572 12:47:46.336056 DQS Delay:
1573 12:47:46.338805 DQS0 = 0, DQS1 = 0
1574 12:47:46.339371 DQM Delay:
1575 12:47:46.341643 DQM0 = 89, DQM1 = 80
1576 12:47:46.342109 DQ Delay:
1577 12:47:46.345428 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1578 12:47:46.348798 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1579 12:47:46.351702 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1580 12:47:46.354576 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1581 12:47:46.355043
1582 12:47:46.355414
1583 12:47:46.355758 ==
1584 12:47:46.358114 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:47:46.361689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:47:46.362268 ==
1587 12:47:46.362646
1588 12:47:46.364453
1589 12:47:46.364947 TX Vref Scan disable
1590 12:47:46.368573 == TX Byte 0 ==
1591 12:47:46.372100 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1592 12:47:46.374693 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1593 12:47:46.378456 == TX Byte 1 ==
1594 12:47:46.381292 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1595 12:47:46.384924 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1596 12:47:46.385493 ==
1597 12:47:46.388354 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 12:47:46.394403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 12:47:46.394903 ==
1600 12:47:46.406976 TX Vref=22, minBit 8, minWin=26, winSum=439
1601 12:47:46.409598 TX Vref=24, minBit 0, minWin=27, winSum=443
1602 12:47:46.413478 TX Vref=26, minBit 9, minWin=27, winSum=449
1603 12:47:46.416175 TX Vref=28, minBit 9, minWin=27, winSum=448
1604 12:47:46.419729 TX Vref=30, minBit 8, minWin=27, winSum=448
1605 12:47:46.426074 TX Vref=32, minBit 8, minWin=27, winSum=448
1606 12:47:46.429790 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 26
1607 12:47:46.430263
1608 12:47:46.432787 Final TX Range 1 Vref 26
1609 12:47:46.433353
1610 12:47:46.433727 ==
1611 12:47:46.436473 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 12:47:46.439385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 12:47:46.442529 ==
1614 12:47:46.442996
1615 12:47:46.443367
1616 12:47:46.443712 TX Vref Scan disable
1617 12:47:46.446123 == TX Byte 0 ==
1618 12:47:46.449902 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1619 12:47:46.456426 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1620 12:47:46.457039 == TX Byte 1 ==
1621 12:47:46.460039 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1622 12:47:46.465933 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1623 12:47:46.466505
1624 12:47:46.466883 [DATLAT]
1625 12:47:46.467235 Freq=800, CH1 RK0
1626 12:47:46.467570
1627 12:47:46.469711 DATLAT Default: 0xa
1628 12:47:46.470174 0, 0xFFFF, sum = 0
1629 12:47:46.472754 1, 0xFFFF, sum = 0
1630 12:47:46.473227 2, 0xFFFF, sum = 0
1631 12:47:46.475911 3, 0xFFFF, sum = 0
1632 12:47:46.479833 4, 0xFFFF, sum = 0
1633 12:47:46.480408 5, 0xFFFF, sum = 0
1634 12:47:46.482474 6, 0xFFFF, sum = 0
1635 12:47:46.482945 7, 0xFFFF, sum = 0
1636 12:47:46.486076 8, 0xFFFF, sum = 0
1637 12:47:46.486655 9, 0x0, sum = 1
1638 12:47:46.489400 10, 0x0, sum = 2
1639 12:47:46.489987 11, 0x0, sum = 3
1640 12:47:46.490369 12, 0x0, sum = 4
1641 12:47:46.492672 best_step = 10
1642 12:47:46.493134
1643 12:47:46.493508 ==
1644 12:47:46.495982 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 12:47:46.499409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 12:47:46.499984 ==
1647 12:47:46.502519 RX Vref Scan: 1
1648 12:47:46.502981
1649 12:47:46.506565 Set Vref Range= 32 -> 127
1650 12:47:46.507138
1651 12:47:46.507516 RX Vref 32 -> 127, step: 1
1652 12:47:46.507868
1653 12:47:46.509568 RX Delay -95 -> 252, step: 8
1654 12:47:46.510034
1655 12:47:46.512414 Set Vref, RX VrefLevel [Byte0]: 32
1656 12:47:46.516243 [Byte1]: 32
1657 12:47:46.516892
1658 12:47:46.519416 Set Vref, RX VrefLevel [Byte0]: 33
1659 12:47:46.522892 [Byte1]: 33
1660 12:47:46.526488
1661 12:47:46.527229 Set Vref, RX VrefLevel [Byte0]: 34
1662 12:47:46.529518 [Byte1]: 34
1663 12:47:46.534008
1664 12:47:46.534575 Set Vref, RX VrefLevel [Byte0]: 35
1665 12:47:46.537319 [Byte1]: 35
1666 12:47:46.541834
1667 12:47:46.542401 Set Vref, RX VrefLevel [Byte0]: 36
1668 12:47:46.545059 [Byte1]: 36
1669 12:47:46.549474
1670 12:47:46.550037 Set Vref, RX VrefLevel [Byte0]: 37
1671 12:47:46.552821 [Byte1]: 37
1672 12:47:46.556978
1673 12:47:46.559822 Set Vref, RX VrefLevel [Byte0]: 38
1674 12:47:46.563348 [Byte1]: 38
1675 12:47:46.563917
1676 12:47:46.566816 Set Vref, RX VrefLevel [Byte0]: 39
1677 12:47:46.569875 [Byte1]: 39
1678 12:47:46.570343
1679 12:47:46.573064 Set Vref, RX VrefLevel [Byte0]: 40
1680 12:47:46.576760 [Byte1]: 40
1681 12:47:46.577234
1682 12:47:46.579668 Set Vref, RX VrefLevel [Byte0]: 41
1683 12:47:46.582989 [Byte1]: 41
1684 12:47:46.587923
1685 12:47:46.588493 Set Vref, RX VrefLevel [Byte0]: 42
1686 12:47:46.590812 [Byte1]: 42
1687 12:47:46.595113
1688 12:47:46.595595 Set Vref, RX VrefLevel [Byte0]: 43
1689 12:47:46.598286 [Byte1]: 43
1690 12:47:46.602541
1691 12:47:46.603116 Set Vref, RX VrefLevel [Byte0]: 44
1692 12:47:46.606361 [Byte1]: 44
1693 12:47:46.610297
1694 12:47:46.610913 Set Vref, RX VrefLevel [Byte0]: 45
1695 12:47:46.613519 [Byte1]: 45
1696 12:47:46.617696
1697 12:47:46.618166 Set Vref, RX VrefLevel [Byte0]: 46
1698 12:47:46.620736 [Byte1]: 46
1699 12:47:46.625277
1700 12:47:46.625744 Set Vref, RX VrefLevel [Byte0]: 47
1701 12:47:46.628580 [Byte1]: 47
1702 12:47:46.633047
1703 12:47:46.633514 Set Vref, RX VrefLevel [Byte0]: 48
1704 12:47:46.636098 [Byte1]: 48
1705 12:47:46.640711
1706 12:47:46.641230 Set Vref, RX VrefLevel [Byte0]: 49
1707 12:47:46.643516 [Byte1]: 49
1708 12:47:46.648295
1709 12:47:46.648960 Set Vref, RX VrefLevel [Byte0]: 50
1710 12:47:46.651346 [Byte1]: 50
1711 12:47:46.655414
1712 12:47:46.659130 Set Vref, RX VrefLevel [Byte0]: 51
1713 12:47:46.659599 [Byte1]: 51
1714 12:47:46.663527
1715 12:47:46.664099 Set Vref, RX VrefLevel [Byte0]: 52
1716 12:47:46.666522 [Byte1]: 52
1717 12:47:46.670916
1718 12:47:46.671385 Set Vref, RX VrefLevel [Byte0]: 53
1719 12:47:46.674565 [Byte1]: 53
1720 12:47:46.678994
1721 12:47:46.679569 Set Vref, RX VrefLevel [Byte0]: 54
1722 12:47:46.681977 [Byte1]: 54
1723 12:47:46.686035
1724 12:47:46.686503 Set Vref, RX VrefLevel [Byte0]: 55
1725 12:47:46.689444 [Byte1]: 55
1726 12:47:46.693649
1727 12:47:46.694182 Set Vref, RX VrefLevel [Byte0]: 56
1728 12:47:46.696944 [Byte1]: 56
1729 12:47:46.701204
1730 12:47:46.701808 Set Vref, RX VrefLevel [Byte0]: 57
1731 12:47:46.704268 [Byte1]: 57
1732 12:47:46.709192
1733 12:47:46.709656 Set Vref, RX VrefLevel [Byte0]: 58
1734 12:47:46.712383 [Byte1]: 58
1735 12:47:46.716264
1736 12:47:46.716726 Set Vref, RX VrefLevel [Byte0]: 59
1737 12:47:46.719947 [Byte1]: 59
1738 12:47:46.724026
1739 12:47:46.724591 Set Vref, RX VrefLevel [Byte0]: 60
1740 12:47:46.727501 [Byte1]: 60
1741 12:47:46.731738
1742 12:47:46.732202 Set Vref, RX VrefLevel [Byte0]: 61
1743 12:47:46.734620 [Byte1]: 61
1744 12:47:46.739417
1745 12:47:46.739954 Set Vref, RX VrefLevel [Byte0]: 62
1746 12:47:46.742449 [Byte1]: 62
1747 12:47:46.746655
1748 12:47:46.747187 Set Vref, RX VrefLevel [Byte0]: 63
1749 12:47:46.750334 [Byte1]: 63
1750 12:47:46.754076
1751 12:47:46.754499 Set Vref, RX VrefLevel [Byte0]: 64
1752 12:47:46.757820 [Byte1]: 64
1753 12:47:46.762180
1754 12:47:46.762713 Set Vref, RX VrefLevel [Byte0]: 65
1755 12:47:46.765144 [Byte1]: 65
1756 12:47:46.770000
1757 12:47:46.770539 Set Vref, RX VrefLevel [Byte0]: 66
1758 12:47:46.772857 [Byte1]: 66
1759 12:47:46.777229
1760 12:47:46.777762 Set Vref, RX VrefLevel [Byte0]: 67
1761 12:47:46.780624 [Byte1]: 67
1762 12:47:46.784674
1763 12:47:46.785262 Set Vref, RX VrefLevel [Byte0]: 68
1764 12:47:46.791036 [Byte1]: 68
1765 12:47:46.791621
1766 12:47:46.794246 Set Vref, RX VrefLevel [Byte0]: 69
1767 12:47:46.797820 [Byte1]: 69
1768 12:47:46.798245
1769 12:47:46.801898 Set Vref, RX VrefLevel [Byte0]: 70
1770 12:47:46.804265 [Byte1]: 70
1771 12:47:46.807758
1772 12:47:46.808292 Set Vref, RX VrefLevel [Byte0]: 71
1773 12:47:46.811316 [Byte1]: 71
1774 12:47:46.815376
1775 12:47:46.815905 Set Vref, RX VrefLevel [Byte0]: 72
1776 12:47:46.818846 [Byte1]: 72
1777 12:47:46.822720
1778 12:47:46.823250 Set Vref, RX VrefLevel [Byte0]: 73
1779 12:47:46.826317 [Byte1]: 73
1780 12:47:46.830357
1781 12:47:46.830874 Set Vref, RX VrefLevel [Byte0]: 74
1782 12:47:46.833520 [Byte1]: 74
1783 12:47:46.838635
1784 12:47:46.839164 Set Vref, RX VrefLevel [Byte0]: 75
1785 12:47:46.841079 [Byte1]: 75
1786 12:47:46.846074
1787 12:47:46.846614 Final RX Vref Byte 0 = 55 to rank0
1788 12:47:46.848746 Final RX Vref Byte 1 = 65 to rank0
1789 12:47:46.852312 Final RX Vref Byte 0 = 55 to rank1
1790 12:47:46.855445 Final RX Vref Byte 1 = 65 to rank1==
1791 12:47:46.858486 Dram Type= 6, Freq= 0, CH_1, rank 0
1792 12:47:46.865627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 12:47:46.866163 ==
1794 12:47:46.866510 DQS Delay:
1795 12:47:46.866829 DQS0 = 0, DQS1 = 0
1796 12:47:46.868990 DQM Delay:
1797 12:47:46.869525 DQM0 = 87, DQM1 = 79
1798 12:47:46.872189 DQ Delay:
1799 12:47:46.875202 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1800 12:47:46.878812 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1801 12:47:46.882327 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1802 12:47:46.885491 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1803 12:47:46.886086
1804 12:47:46.886438
1805 12:47:46.892957 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1806 12:47:46.895255 CH1 RK0: MR19=606, MR18=301C
1807 12:47:46.902473 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1808 12:47:46.903006
1809 12:47:46.905294 ----->DramcWriteLeveling(PI) begin...
1810 12:47:46.905725 ==
1811 12:47:46.908694 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 12:47:46.911771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 12:47:46.912200 ==
1814 12:47:46.915332 Write leveling (Byte 0): 27 => 27
1815 12:47:46.919221 Write leveling (Byte 1): 31 => 31
1816 12:47:46.921825 DramcWriteLeveling(PI) end<-----
1817 12:47:46.922361
1818 12:47:46.922703 ==
1819 12:47:46.925354 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 12:47:46.928314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 12:47:46.928885 ==
1822 12:47:46.931999 [Gating] SW mode calibration
1823 12:47:46.938268 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1824 12:47:46.945274 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1825 12:47:46.948654 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1826 12:47:46.955331 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1827 12:47:46.958271 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:47:46.961955 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:47:46.968274 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:47:46.971565 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:47:46.975148 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:47:46.978894 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:47:46.985342 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:47:46.989036 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:47:46.991784 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:47:46.998112 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:47:47.001731 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:47:47.004965 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:47:47.011812 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:47:47.015048 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:47:47.018145 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:47:47.025187 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1843 12:47:47.028678 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1844 12:47:47.031474 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:47:47.038653 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:47:47.041908 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:47:47.044619 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:47:47.051713 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:47:47.055521 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:47:47.058278 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:47:47.064946 0 9 8 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
1852 12:47:47.068238 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 12:47:47.071783 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 12:47:47.075317 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 12:47:47.081656 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 12:47:47.085130 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 12:47:47.088595 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 12:47:47.094866 0 10 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1859 12:47:47.098010 0 10 8 | B1->B0 | 2929 2d2d | 0 0 | (0 0) (1 1)
1860 12:47:47.101363 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:47:47.108137 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:47:47.111864 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:47:47.115047 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:47:47.121665 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:47:47.125274 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:47:47.127938 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1867 12:47:47.134762 0 11 8 | B1->B0 | 4343 3c3c | 0 0 | (0 0) (0 0)
1868 12:47:47.138092 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 12:47:47.141416 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 12:47:47.148034 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:47:47.151554 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 12:47:47.154433 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 12:47:47.161289 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 12:47:47.164487 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1875 12:47:47.167517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:47:47.174631 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:47:47.178570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:47:47.181431 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:47:47.187646 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:47:47.191613 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:47:47.194620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:47:47.200999 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:47:47.204070 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:47:47.207825 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:47:47.214260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 12:47:47.217789 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 12:47:47.220631 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 12:47:47.227986 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 12:47:47.230816 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 12:47:47.234638 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1891 12:47:47.237538 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 12:47:47.240917 Total UI for P1: 0, mck2ui 16
1893 12:47:47.244223 best dqsien dly found for B0: ( 0, 14, 4)
1894 12:47:47.247996 Total UI for P1: 0, mck2ui 16
1895 12:47:47.250852 best dqsien dly found for B1: ( 0, 14, 4)
1896 12:47:47.257217 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1897 12:47:47.260809 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1898 12:47:47.261279
1899 12:47:47.264232 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1900 12:47:47.267864 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1901 12:47:47.270311 [Gating] SW calibration Done
1902 12:47:47.270783 ==
1903 12:47:47.274303 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 12:47:47.277400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 12:47:47.277873 ==
1906 12:47:47.278247 RX Vref Scan: 0
1907 12:47:47.280786
1908 12:47:47.281544 RX Vref 0 -> 0, step: 1
1909 12:47:47.281944
1910 12:47:47.284199 RX Delay -130 -> 252, step: 16
1911 12:47:47.287364 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1912 12:47:47.293803 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1913 12:47:47.296763 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1914 12:47:47.300436 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1915 12:47:47.303533 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1916 12:47:47.307104 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1917 12:47:47.313479 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1918 12:47:47.316971 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1919 12:47:47.320335 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1920 12:47:47.323445 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1921 12:47:47.327048 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1922 12:47:47.333531 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1923 12:47:47.337035 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1924 12:47:47.340546 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1925 12:47:47.343565 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1926 12:47:47.346967 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1927 12:47:47.350609 ==
1928 12:47:47.353653 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 12:47:47.357165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 12:47:47.357739 ==
1931 12:47:47.358117 DQS Delay:
1932 12:47:47.359791 DQS0 = 0, DQS1 = 0
1933 12:47:47.360258 DQM Delay:
1934 12:47:47.363536 DQM0 = 86, DQM1 = 78
1935 12:47:47.364005 DQ Delay:
1936 12:47:47.366715 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1937 12:47:47.370138 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1938 12:47:47.373060 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1939 12:47:47.376777 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1940 12:47:47.377347
1941 12:47:47.377728
1942 12:47:47.378081 ==
1943 12:47:47.380230 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 12:47:47.383453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 12:47:47.384099 ==
1946 12:47:47.384482
1947 12:47:47.384895
1948 12:47:47.386367 TX Vref Scan disable
1949 12:47:47.389942 == TX Byte 0 ==
1950 12:47:47.393167 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1951 12:47:47.396763 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1952 12:47:47.399645 == TX Byte 1 ==
1953 12:47:47.403059 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1954 12:47:47.406639 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1955 12:47:47.407218 ==
1956 12:47:47.409710 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 12:47:47.416156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 12:47:47.416775 ==
1959 12:47:47.428493 TX Vref=22, minBit 1, minWin=27, winSum=445
1960 12:47:47.431917 TX Vref=24, minBit 8, minWin=27, winSum=445
1961 12:47:47.435343 TX Vref=26, minBit 8, minWin=27, winSum=450
1962 12:47:47.438285 TX Vref=28, minBit 8, minWin=27, winSum=451
1963 12:47:47.441939 TX Vref=30, minBit 8, minWin=27, winSum=451
1964 12:47:47.447849 TX Vref=32, minBit 0, minWin=28, winSum=452
1965 12:47:47.451458 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1966 12:47:47.451931
1967 12:47:47.454540 Final TX Range 1 Vref 32
1968 12:47:47.455012
1969 12:47:47.455481 ==
1970 12:47:47.458519 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 12:47:47.462012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 12:47:47.462494 ==
1973 12:47:47.464814
1974 12:47:47.465281
1975 12:47:47.465724 TX Vref Scan disable
1976 12:47:47.467981 == TX Byte 0 ==
1977 12:47:47.471075 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1978 12:47:47.474925 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1979 12:47:47.478385 == TX Byte 1 ==
1980 12:47:47.481332 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1981 12:47:47.488313 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1982 12:47:47.488993
1983 12:47:47.489377 [DATLAT]
1984 12:47:47.489730 Freq=800, CH1 RK1
1985 12:47:47.490065
1986 12:47:47.491266 DATLAT Default: 0xa
1987 12:47:47.491735 0, 0xFFFF, sum = 0
1988 12:47:47.494576 1, 0xFFFF, sum = 0
1989 12:47:47.495161 2, 0xFFFF, sum = 0
1990 12:47:47.497818 3, 0xFFFF, sum = 0
1991 12:47:47.501231 4, 0xFFFF, sum = 0
1992 12:47:47.501705 5, 0xFFFF, sum = 0
1993 12:47:47.504785 6, 0xFFFF, sum = 0
1994 12:47:47.505358 7, 0xFFFF, sum = 0
1995 12:47:47.507886 8, 0xFFFF, sum = 0
1996 12:47:47.508458 9, 0x0, sum = 1
1997 12:47:47.511689 10, 0x0, sum = 2
1998 12:47:47.512264 11, 0x0, sum = 3
1999 12:47:47.512710 12, 0x0, sum = 4
2000 12:47:47.514563 best_step = 10
2001 12:47:47.515129
2002 12:47:47.515508 ==
2003 12:47:47.518557 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 12:47:47.521618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 12:47:47.522190 ==
2006 12:47:47.524803 RX Vref Scan: 0
2007 12:47:47.525273
2008 12:47:47.525645 RX Vref 0 -> 0, step: 1
2009 12:47:47.527969
2010 12:47:47.528559 RX Delay -95 -> 252, step: 8
2011 12:47:47.535217 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2012 12:47:47.538142 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2013 12:47:47.541143 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2014 12:47:47.545151 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2015 12:47:47.548504 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2016 12:47:47.554588 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2017 12:47:47.557923 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2018 12:47:47.561719 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2019 12:47:47.565415 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2020 12:47:47.567877 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2021 12:47:47.574833 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2022 12:47:47.578250 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2023 12:47:47.581256 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2024 12:47:47.584427 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2025 12:47:47.591035 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2026 12:47:47.594555 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2027 12:47:47.595134 ==
2028 12:47:47.597547 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 12:47:47.601025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 12:47:47.601654 ==
2031 12:47:47.604230 DQS Delay:
2032 12:47:47.604715 DQS0 = 0, DQS1 = 0
2033 12:47:47.605088 DQM Delay:
2034 12:47:47.607593 DQM0 = 88, DQM1 = 80
2035 12:47:47.608160 DQ Delay:
2036 12:47:47.610761 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =88
2037 12:47:47.614674 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2038 12:47:47.617283 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =72
2039 12:47:47.620878 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2040 12:47:47.621442
2041 12:47:47.621813
2042 12:47:47.631013 [DQSOSCAuto] RK1, (LSB)MR18= 0x140c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2043 12:47:47.633880 CH1 RK1: MR19=606, MR18=140C
2044 12:47:47.637750 CH1_RK1: MR19=0x606, MR18=0x140C, DQSOSC=404, MR23=63, INC=90, DEC=60
2045 12:47:47.640931 [RxdqsGatingPostProcess] freq 800
2046 12:47:47.647618 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2047 12:47:47.650539 Pre-setting of DQS Precalculation
2048 12:47:47.653847 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2049 12:47:47.663918 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2050 12:47:47.670443 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2051 12:47:47.670997
2052 12:47:47.671365
2053 12:47:47.673353 [Calibration Summary] 1600 Mbps
2054 12:47:47.673816 CH 0, Rank 0
2055 12:47:47.677094 SW Impedance : PASS
2056 12:47:47.677554 DUTY Scan : NO K
2057 12:47:47.680447 ZQ Calibration : PASS
2058 12:47:47.684068 Jitter Meter : NO K
2059 12:47:47.684679 CBT Training : PASS
2060 12:47:47.686746 Write leveling : PASS
2061 12:47:47.690531 RX DQS gating : PASS
2062 12:47:47.691118 RX DQ/DQS(RDDQC) : PASS
2063 12:47:47.695661 TX DQ/DQS : PASS
2064 12:47:47.697068 RX DATLAT : PASS
2065 12:47:47.697532 RX DQ/DQS(Engine): PASS
2066 12:47:47.700064 TX OE : NO K
2067 12:47:47.700592 All Pass.
2068 12:47:47.700970
2069 12:47:47.703375 CH 0, Rank 1
2070 12:47:47.703867 SW Impedance : PASS
2071 12:47:47.706768 DUTY Scan : NO K
2072 12:47:47.710367 ZQ Calibration : PASS
2073 12:47:47.710962 Jitter Meter : NO K
2074 12:47:47.713433 CBT Training : PASS
2075 12:47:47.714164 Write leveling : PASS
2076 12:47:47.716477 RX DQS gating : PASS
2077 12:47:47.720304 RX DQ/DQS(RDDQC) : PASS
2078 12:47:47.720919 TX DQ/DQS : PASS
2079 12:47:47.723897 RX DATLAT : PASS
2080 12:47:47.726948 RX DQ/DQS(Engine): PASS
2081 12:47:47.727526 TX OE : NO K
2082 12:47:47.729907 All Pass.
2083 12:47:47.730485
2084 12:47:47.730870 CH 1, Rank 0
2085 12:47:47.732856 SW Impedance : PASS
2086 12:47:47.733325 DUTY Scan : NO K
2087 12:47:47.736581 ZQ Calibration : PASS
2088 12:47:47.740175 Jitter Meter : NO K
2089 12:47:47.740783 CBT Training : PASS
2090 12:47:47.743444 Write leveling : PASS
2091 12:47:47.746646 RX DQS gating : PASS
2092 12:47:47.747222 RX DQ/DQS(RDDQC) : PASS
2093 12:47:47.750317 TX DQ/DQS : PASS
2094 12:47:47.752834 RX DATLAT : PASS
2095 12:47:47.753306 RX DQ/DQS(Engine): PASS
2096 12:47:47.756253 TX OE : NO K
2097 12:47:47.756857 All Pass.
2098 12:47:47.757236
2099 12:47:47.759644 CH 1, Rank 1
2100 12:47:47.760108 SW Impedance : PASS
2101 12:47:47.763169 DUTY Scan : NO K
2102 12:47:47.766399 ZQ Calibration : PASS
2103 12:47:47.766985 Jitter Meter : NO K
2104 12:47:47.769581 CBT Training : PASS
2105 12:47:47.772932 Write leveling : PASS
2106 12:47:47.773404 RX DQS gating : PASS
2107 12:47:47.776646 RX DQ/DQS(RDDQC) : PASS
2108 12:47:47.777231 TX DQ/DQS : PASS
2109 12:47:47.779506 RX DATLAT : PASS
2110 12:47:47.783472 RX DQ/DQS(Engine): PASS
2111 12:47:47.784032 TX OE : NO K
2112 12:47:47.786157 All Pass.
2113 12:47:47.786722
2114 12:47:47.787099 DramC Write-DBI off
2115 12:47:47.789439 PER_BANK_REFRESH: Hybrid Mode
2116 12:47:47.793182 TX_TRACKING: ON
2117 12:47:47.796246 [GetDramInforAfterCalByMRR] Vendor 6.
2118 12:47:47.799713 [GetDramInforAfterCalByMRR] Revision 606.
2119 12:47:47.803147 [GetDramInforAfterCalByMRR] Revision 2 0.
2120 12:47:47.803618 MR0 0x3b3b
2121 12:47:47.803994 MR8 0x5151
2122 12:47:47.809228 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 12:47:47.809701
2124 12:47:47.810073 MR0 0x3b3b
2125 12:47:47.810422 MR8 0x5151
2126 12:47:47.812425 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2127 12:47:47.812934
2128 12:47:47.822871 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2129 12:47:47.825531 [FAST_K] Save calibration result to emmc
2130 12:47:47.829115 [FAST_K] Save calibration result to emmc
2131 12:47:47.832198 dram_init: config_dvfs: 1
2132 12:47:47.835547 dramc_set_vcore_voltage set vcore to 662500
2133 12:47:47.838683 Read voltage for 1200, 2
2134 12:47:47.839109 Vio18 = 0
2135 12:47:47.842510 Vcore = 662500
2136 12:47:47.843032 Vdram = 0
2137 12:47:47.843378 Vddq = 0
2138 12:47:47.843696 Vmddr = 0
2139 12:47:47.848619 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2140 12:47:47.855454 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2141 12:47:47.855983 MEM_TYPE=3, freq_sel=15
2142 12:47:47.858966 sv_algorithm_assistance_LP4_1600
2143 12:47:47.862145 ============ PULL DRAM RESETB DOWN ============
2144 12:47:47.868832 ========== PULL DRAM RESETB DOWN end =========
2145 12:47:47.872161 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2146 12:47:47.876244 ===================================
2147 12:47:47.878690 LPDDR4 DRAM CONFIGURATION
2148 12:47:47.881931 ===================================
2149 12:47:47.882496 EX_ROW_EN[0] = 0x0
2150 12:47:47.885366 EX_ROW_EN[1] = 0x0
2151 12:47:47.885930 LP4Y_EN = 0x0
2152 12:47:47.888779 WORK_FSP = 0x0
2153 12:47:47.889248 WL = 0x4
2154 12:47:47.892405 RL = 0x4
2155 12:47:47.894930 BL = 0x2
2156 12:47:47.895399 RPST = 0x0
2157 12:47:47.898412 RD_PRE = 0x0
2158 12:47:47.898883 WR_PRE = 0x1
2159 12:47:47.901785 WR_PST = 0x0
2160 12:47:47.902269 DBI_WR = 0x0
2161 12:47:47.905068 DBI_RD = 0x0
2162 12:47:47.905538 OTF = 0x1
2163 12:47:47.908749 ===================================
2164 12:47:47.911848 ===================================
2165 12:47:47.912316 ANA top config
2166 12:47:47.915607 ===================================
2167 12:47:47.918843 DLL_ASYNC_EN = 0
2168 12:47:47.921926 ALL_SLAVE_EN = 0
2169 12:47:47.925058 NEW_RANK_MODE = 1
2170 12:47:47.928507 DLL_IDLE_MODE = 1
2171 12:47:47.928967 LP45_APHY_COMB_EN = 1
2172 12:47:47.931802 TX_ODT_DIS = 1
2173 12:47:47.935439 NEW_8X_MODE = 1
2174 12:47:47.938710 ===================================
2175 12:47:47.941699 ===================================
2176 12:47:47.945412 data_rate = 2400
2177 12:47:47.948855 CKR = 1
2178 12:47:47.951509 DQ_P2S_RATIO = 8
2179 12:47:47.951936 ===================================
2180 12:47:47.955463 CA_P2S_RATIO = 8
2181 12:47:47.958542 DQ_CA_OPEN = 0
2182 12:47:47.961530 DQ_SEMI_OPEN = 0
2183 12:47:47.965148 CA_SEMI_OPEN = 0
2184 12:47:47.968600 CA_FULL_RATE = 0
2185 12:47:47.969025 DQ_CKDIV4_EN = 0
2186 12:47:47.971765 CA_CKDIV4_EN = 0
2187 12:47:47.975444 CA_PREDIV_EN = 0
2188 12:47:47.978168 PH8_DLY = 17
2189 12:47:47.981668 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2190 12:47:47.984872 DQ_AAMCK_DIV = 4
2191 12:47:47.988223 CA_AAMCK_DIV = 4
2192 12:47:47.988719 CA_ADMCK_DIV = 4
2193 12:47:47.991304 DQ_TRACK_CA_EN = 0
2194 12:47:47.995011 CA_PICK = 1200
2195 12:47:47.997890 CA_MCKIO = 1200
2196 12:47:48.001231 MCKIO_SEMI = 0
2197 12:47:48.004635 PLL_FREQ = 2366
2198 12:47:48.007934 DQ_UI_PI_RATIO = 32
2199 12:47:48.008406 CA_UI_PI_RATIO = 0
2200 12:47:48.011057 ===================================
2201 12:47:48.015324 ===================================
2202 12:47:48.017856 memory_type:LPDDR4
2203 12:47:48.021085 GP_NUM : 10
2204 12:47:48.021504 SRAM_EN : 1
2205 12:47:48.025029 MD32_EN : 0
2206 12:47:48.028120 ===================================
2207 12:47:48.030964 [ANA_INIT] >>>>>>>>>>>>>>
2208 12:47:48.034384 <<<<<< [CONFIGURE PHASE]: ANA_TX
2209 12:47:48.037999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2210 12:47:48.040815 ===================================
2211 12:47:48.041237 data_rate = 2400,PCW = 0X5b00
2212 12:47:48.044894 ===================================
2213 12:47:48.047957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2214 12:47:48.054189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 12:47:48.061346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 12:47:48.064289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2217 12:47:48.067551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2218 12:47:48.070637 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2219 12:47:48.074602 [ANA_INIT] flow start
2220 12:47:48.078344 [ANA_INIT] PLL >>>>>>>>
2221 12:47:48.078864 [ANA_INIT] PLL <<<<<<<<
2222 12:47:48.080828 [ANA_INIT] MIDPI >>>>>>>>
2223 12:47:48.084194 [ANA_INIT] MIDPI <<<<<<<<
2224 12:47:48.084643 [ANA_INIT] DLL >>>>>>>>
2225 12:47:48.087605 [ANA_INIT] DLL <<<<<<<<
2226 12:47:48.090942 [ANA_INIT] flow end
2227 12:47:48.094497 ============ LP4 DIFF to SE enter ============
2228 12:47:48.097377 ============ LP4 DIFF to SE exit ============
2229 12:47:48.100481 [ANA_INIT] <<<<<<<<<<<<<
2230 12:47:48.104381 [Flow] Enable top DCM control >>>>>
2231 12:47:48.107155 [Flow] Enable top DCM control <<<<<
2232 12:47:48.110368 Enable DLL master slave shuffle
2233 12:47:48.114067 ==============================================================
2234 12:47:48.117369 Gating Mode config
2235 12:47:48.123708 ==============================================================
2236 12:47:48.124268 Config description:
2237 12:47:48.134185 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2238 12:47:48.140601 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2239 12:47:48.143836 SELPH_MODE 0: By rank 1: By Phase
2240 12:47:48.150697 ==============================================================
2241 12:47:48.153563 GAT_TRACK_EN = 1
2242 12:47:48.157197 RX_GATING_MODE = 2
2243 12:47:48.160429 RX_GATING_TRACK_MODE = 2
2244 12:47:48.164167 SELPH_MODE = 1
2245 12:47:48.166978 PICG_EARLY_EN = 1
2246 12:47:48.170642 VALID_LAT_VALUE = 1
2247 12:47:48.173848 ==============================================================
2248 12:47:48.176754 Enter into Gating configuration >>>>
2249 12:47:48.179976 Exit from Gating configuration <<<<
2250 12:47:48.183269 Enter into DVFS_PRE_config >>>>>
2251 12:47:48.197345 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2252 12:47:48.197947 Exit from DVFS_PRE_config <<<<<
2253 12:47:48.200106 Enter into PICG configuration >>>>
2254 12:47:48.203710 Exit from PICG configuration <<<<
2255 12:47:48.207162 [RX_INPUT] configuration >>>>>
2256 12:47:48.210064 [RX_INPUT] configuration <<<<<
2257 12:47:48.216673 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2258 12:47:48.220412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2259 12:47:48.226873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 12:47:48.233011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 12:47:48.239800 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2262 12:47:48.246598 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2263 12:47:48.250184 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2264 12:47:48.253707 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2265 12:47:48.256216 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2266 12:47:48.262431 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2267 12:47:48.266125 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2268 12:47:48.269396 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 12:47:48.272686 ===================================
2270 12:47:48.276028 LPDDR4 DRAM CONFIGURATION
2271 12:47:48.279651 ===================================
2272 12:47:48.282680 EX_ROW_EN[0] = 0x0
2273 12:47:48.283140 EX_ROW_EN[1] = 0x0
2274 12:47:48.286407 LP4Y_EN = 0x0
2275 12:47:48.286936 WORK_FSP = 0x0
2276 12:47:48.289446 WL = 0x4
2277 12:47:48.289873 RL = 0x4
2278 12:47:48.292713 BL = 0x2
2279 12:47:48.293140 RPST = 0x0
2280 12:47:48.296604 RD_PRE = 0x0
2281 12:47:48.297131 WR_PRE = 0x1
2282 12:47:48.299772 WR_PST = 0x0
2283 12:47:48.300304 DBI_WR = 0x0
2284 12:47:48.303129 DBI_RD = 0x0
2285 12:47:48.303578 OTF = 0x1
2286 12:47:48.305853 ===================================
2287 12:47:48.312867 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2288 12:47:48.316042 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2289 12:47:48.319305 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 12:47:48.322632 ===================================
2291 12:47:48.325409 LPDDR4 DRAM CONFIGURATION
2292 12:47:48.328810 ===================================
2293 12:47:48.332375 EX_ROW_EN[0] = 0x10
2294 12:47:48.332886 EX_ROW_EN[1] = 0x0
2295 12:47:48.335348 LP4Y_EN = 0x0
2296 12:47:48.335757 WORK_FSP = 0x0
2297 12:47:48.339057 WL = 0x4
2298 12:47:48.339464 RL = 0x4
2299 12:47:48.343017 BL = 0x2
2300 12:47:48.343305 RPST = 0x0
2301 12:47:48.345599 RD_PRE = 0x0
2302 12:47:48.345919 WR_PRE = 0x1
2303 12:47:48.348421 WR_PST = 0x0
2304 12:47:48.348678 DBI_WR = 0x0
2305 12:47:48.352045 DBI_RD = 0x0
2306 12:47:48.352358 OTF = 0x1
2307 12:47:48.355371 ===================================
2308 12:47:48.362210 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2309 12:47:48.362493 ==
2310 12:47:48.365714 Dram Type= 6, Freq= 0, CH_0, rank 0
2311 12:47:48.372052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2312 12:47:48.372367 ==
2313 12:47:48.372579 [Duty_Offset_Calibration]
2314 12:47:48.375170 B0:1 B1:-1 CA:0
2315 12:47:48.375479
2316 12:47:48.378099 [DutyScan_Calibration_Flow] k_type=0
2317 12:47:48.387843
2318 12:47:48.388299 ==CLK 0==
2319 12:47:48.391236 Final CLK duty delay cell = 0
2320 12:47:48.395027 [0] MAX Duty = 5125%(X100), DQS PI = 24
2321 12:47:48.397696 [0] MIN Duty = 4875%(X100), DQS PI = 8
2322 12:47:48.398152 [0] AVG Duty = 5000%(X100)
2323 12:47:48.401454
2324 12:47:48.401914 CH0 CLK Duty spec in!! Max-Min= 250%
2325 12:47:48.407881 [DutyScan_Calibration_Flow] ====Done====
2326 12:47:48.408430
2327 12:47:48.411035 [DutyScan_Calibration_Flow] k_type=1
2328 12:47:48.425559
2329 12:47:48.426109 ==DQS 0 ==
2330 12:47:48.428614 Final DQS duty delay cell = -4
2331 12:47:48.431901 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2332 12:47:48.435152 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2333 12:47:48.438626 [-4] AVG Duty = 4968%(X100)
2334 12:47:48.439171
2335 12:47:48.439530 ==DQS 1 ==
2336 12:47:48.441940 Final DQS duty delay cell = -4
2337 12:47:48.445249 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2338 12:47:48.448775 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2339 12:47:48.451379 [-4] AVG Duty = 4938%(X100)
2340 12:47:48.451827
2341 12:47:48.454812 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2342 12:47:48.455264
2343 12:47:48.458561 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2344 12:47:48.462003 [DutyScan_Calibration_Flow] ====Done====
2345 12:47:48.462452
2346 12:47:48.465268 [DutyScan_Calibration_Flow] k_type=3
2347 12:47:48.483467
2348 12:47:48.484014 ==DQM 0 ==
2349 12:47:48.486597 Final DQM duty delay cell = 0
2350 12:47:48.489932 [0] MAX Duty = 5062%(X100), DQS PI = 18
2351 12:47:48.493371 [0] MIN Duty = 4875%(X100), DQS PI = 6
2352 12:47:48.496861 [0] AVG Duty = 4968%(X100)
2353 12:47:48.497411
2354 12:47:48.497776 ==DQM 1 ==
2355 12:47:48.500049 Final DQM duty delay cell = 4
2356 12:47:48.502904 [4] MAX Duty = 5187%(X100), DQS PI = 14
2357 12:47:48.506990 [4] MIN Duty = 5000%(X100), DQS PI = 24
2358 12:47:48.510273 [4] AVG Duty = 5093%(X100)
2359 12:47:48.510820
2360 12:47:48.512957 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2361 12:47:48.513409
2362 12:47:48.516370 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2363 12:47:48.519866 [DutyScan_Calibration_Flow] ====Done====
2364 12:47:48.520419
2365 12:47:48.522946 [DutyScan_Calibration_Flow] k_type=2
2366 12:47:48.538302
2367 12:47:48.538857 ==DQ 0 ==
2368 12:47:48.541585 Final DQ duty delay cell = -4
2369 12:47:48.544816 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2370 12:47:48.548417 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2371 12:47:48.551449 [-4] AVG Duty = 4969%(X100)
2372 12:47:48.552004
2373 12:47:48.552403 ==DQ 1 ==
2374 12:47:48.554456 Final DQ duty delay cell = -4
2375 12:47:48.558005 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2376 12:47:48.561625 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2377 12:47:48.564854 [-4] AVG Duty = 4922%(X100)
2378 12:47:48.565411
2379 12:47:48.568664 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2380 12:47:48.569309
2381 12:47:48.571999 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2382 12:47:48.574650 [DutyScan_Calibration_Flow] ====Done====
2383 12:47:48.575104 ==
2384 12:47:48.577709 Dram Type= 6, Freq= 0, CH_1, rank 0
2385 12:47:48.581330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2386 12:47:48.581787 ==
2387 12:47:48.584304 [Duty_Offset_Calibration]
2388 12:47:48.584853 B0:-1 B1:1 CA:2
2389 12:47:48.587971
2390 12:47:48.590913 [DutyScan_Calibration_Flow] k_type=0
2391 12:47:48.598507
2392 12:47:48.598921 ==CLK 0==
2393 12:47:48.601943 Final CLK duty delay cell = 0
2394 12:47:48.605039 [0] MAX Duty = 5156%(X100), DQS PI = 4
2395 12:47:48.608362 [0] MIN Duty = 5000%(X100), DQS PI = 28
2396 12:47:48.608829 [0] AVG Duty = 5078%(X100)
2397 12:47:48.612269
2398 12:47:48.614958 CH1 CLK Duty spec in!! Max-Min= 156%
2399 12:47:48.618598 [DutyScan_Calibration_Flow] ====Done====
2400 12:47:48.619021
2401 12:47:48.622092 [DutyScan_Calibration_Flow] k_type=1
2402 12:47:48.638403
2403 12:47:48.638827 ==DQS 0 ==
2404 12:47:48.641289 Final DQS duty delay cell = 0
2405 12:47:48.644382 [0] MAX Duty = 5125%(X100), DQS PI = 18
2406 12:47:48.647975 [0] MIN Duty = 4907%(X100), DQS PI = 38
2407 12:47:48.651057 [0] AVG Duty = 5016%(X100)
2408 12:47:48.651481
2409 12:47:48.651817 ==DQS 1 ==
2410 12:47:48.654639 Final DQS duty delay cell = 0
2411 12:47:48.657790 [0] MAX Duty = 5094%(X100), DQS PI = 44
2412 12:47:48.661321 [0] MIN Duty = 4969%(X100), DQS PI = 26
2413 12:47:48.665159 [0] AVG Duty = 5031%(X100)
2414 12:47:48.665783
2415 12:47:48.667975 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2416 12:47:48.668402
2417 12:47:48.670969 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2418 12:47:48.674589 [DutyScan_Calibration_Flow] ====Done====
2419 12:47:48.675013
2420 12:47:48.677422 [DutyScan_Calibration_Flow] k_type=3
2421 12:47:48.694117
2422 12:47:48.694542 ==DQM 0 ==
2423 12:47:48.696832 Final DQM duty delay cell = -4
2424 12:47:48.700469 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2425 12:47:48.703524 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2426 12:47:48.707453 [-4] AVG Duty = 4953%(X100)
2427 12:47:48.707876
2428 12:47:48.708207 ==DQM 1 ==
2429 12:47:48.710309 Final DQM duty delay cell = 0
2430 12:47:48.713881 [0] MAX Duty = 5187%(X100), DQS PI = 36
2431 12:47:48.717248 [0] MIN Duty = 4969%(X100), DQS PI = 0
2432 12:47:48.720936 [0] AVG Duty = 5078%(X100)
2433 12:47:48.721458
2434 12:47:48.723879 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2435 12:47:48.724302
2436 12:47:48.726750 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2437 12:47:48.730612 [DutyScan_Calibration_Flow] ====Done====
2438 12:47:48.731148
2439 12:47:48.733206 [DutyScan_Calibration_Flow] k_type=2
2440 12:47:48.750496
2441 12:47:48.750919 ==DQ 0 ==
2442 12:47:48.753735 Final DQ duty delay cell = 0
2443 12:47:48.756929 [0] MAX Duty = 5156%(X100), DQS PI = 0
2444 12:47:48.760155 [0] MIN Duty = 4907%(X100), DQS PI = 38
2445 12:47:48.760752 [0] AVG Duty = 5031%(X100)
2446 12:47:48.763650
2447 12:47:48.764070 ==DQ 1 ==
2448 12:47:48.766779 Final DQ duty delay cell = 0
2449 12:47:48.770256 [0] MAX Duty = 5124%(X100), DQS PI = 42
2450 12:47:48.773504 [0] MIN Duty = 4969%(X100), DQS PI = 28
2451 12:47:48.773959 [0] AVG Duty = 5046%(X100)
2452 12:47:48.776830
2453 12:47:48.780160 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2454 12:47:48.780628
2455 12:47:48.783877 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2456 12:47:48.787368 [DutyScan_Calibration_Flow] ====Done====
2457 12:47:48.790534 nWR fixed to 30
2458 12:47:48.790971 [ModeRegInit_LP4] CH0 RK0
2459 12:47:48.793320 [ModeRegInit_LP4] CH0 RK1
2460 12:47:48.796896 [ModeRegInit_LP4] CH1 RK0
2461 12:47:48.797365 [ModeRegInit_LP4] CH1 RK1
2462 12:47:48.800055 match AC timing 7
2463 12:47:48.803780 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2464 12:47:48.809811 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2465 12:47:48.813755 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2466 12:47:48.816919 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2467 12:47:48.823670 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2468 12:47:48.824080 ==
2469 12:47:48.826873 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 12:47:48.830271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 12:47:48.830672 ==
2472 12:47:48.836892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 12:47:48.843174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2474 12:47:48.850228 [CA 0] Center 39 (9~70) winsize 62
2475 12:47:48.853478 [CA 1] Center 39 (9~70) winsize 62
2476 12:47:48.856844 [CA 2] Center 35 (5~66) winsize 62
2477 12:47:48.860181 [CA 3] Center 35 (5~65) winsize 61
2478 12:47:48.863484 [CA 4] Center 33 (3~64) winsize 62
2479 12:47:48.866714 [CA 5] Center 33 (4~63) winsize 60
2480 12:47:48.867014
2481 12:47:48.870172 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 12:47:48.870470
2483 12:47:48.874276 [CATrainingPosCal] consider 1 rank data
2484 12:47:48.876931 u2DelayCellTimex100 = 270/100 ps
2485 12:47:48.879996 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2486 12:47:48.886895 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2487 12:47:48.889719 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 12:47:48.894529 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2489 12:47:48.896315 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2490 12:47:48.900124 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2491 12:47:48.900425
2492 12:47:48.903144 CA PerBit enable=1, Macro0, CA PI delay=33
2493 12:47:48.903512
2494 12:47:48.906701 [CBTSetCACLKResult] CA Dly = 33
2495 12:47:48.907000 CS Dly: 8 (0~39)
2496 12:47:48.909801 ==
2497 12:47:48.913227 Dram Type= 6, Freq= 0, CH_0, rank 1
2498 12:47:48.916029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 12:47:48.916331 ==
2500 12:47:48.922976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 12:47:48.926198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2502 12:47:48.935994 [CA 0] Center 39 (9~70) winsize 62
2503 12:47:48.938991 [CA 1] Center 39 (9~70) winsize 62
2504 12:47:48.942713 [CA 2] Center 35 (5~66) winsize 62
2505 12:47:48.946091 [CA 3] Center 34 (4~65) winsize 62
2506 12:47:48.949185 [CA 4] Center 33 (3~64) winsize 62
2507 12:47:48.952440 [CA 5] Center 33 (3~63) winsize 61
2508 12:47:48.952763
2509 12:47:48.956133 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2510 12:47:48.956434
2511 12:47:48.959095 [CATrainingPosCal] consider 2 rank data
2512 12:47:48.962994 u2DelayCellTimex100 = 270/100 ps
2513 12:47:48.965715 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2514 12:47:48.969421 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2515 12:47:48.976252 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2516 12:47:48.979234 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2517 12:47:48.982545 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2518 12:47:48.986478 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2519 12:47:48.986954
2520 12:47:48.989034 CA PerBit enable=1, Macro0, CA PI delay=33
2521 12:47:48.989462
2522 12:47:48.992323 [CBTSetCACLKResult] CA Dly = 33
2523 12:47:48.993036 CS Dly: 8 (0~40)
2524 12:47:48.995720
2525 12:47:48.999541 ----->DramcWriteLeveling(PI) begin...
2526 12:47:49.000166 ==
2527 12:47:49.002427 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 12:47:49.005653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 12:47:49.006123 ==
2530 12:47:49.008705 Write leveling (Byte 0): 33 => 33
2531 12:47:49.012420 Write leveling (Byte 1): 28 => 28
2532 12:47:49.015280 DramcWriteLeveling(PI) end<-----
2533 12:47:49.015860
2534 12:47:49.016213 ==
2535 12:47:49.018630 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 12:47:49.022132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 12:47:49.022667 ==
2538 12:47:49.025700 [Gating] SW mode calibration
2539 12:47:49.032129 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2540 12:47:49.038591 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2541 12:47:49.041771 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2542 12:47:49.045759 0 15 4 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
2543 12:47:49.052311 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2544 12:47:49.055319 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 12:47:49.058790 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 12:47:49.064999 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 12:47:49.068704 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 12:47:49.072293 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
2549 12:47:49.078924 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
2550 12:47:49.082978 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 12:47:49.085224 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 12:47:49.091679 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 12:47:49.095311 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 12:47:49.098720 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 12:47:49.104980 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 12:47:49.108057 1 0 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
2557 12:47:49.111442 1 1 0 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2558 12:47:49.118195 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2559 12:47:49.121400 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 12:47:49.125154 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 12:47:49.131684 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 12:47:49.134813 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 12:47:49.138122 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 12:47:49.141136 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2565 12:47:49.148168 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2566 12:47:49.151595 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:47:49.154598 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:47:49.161762 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:47:49.164735 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:47:49.168020 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:47:49.175298 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:47:49.177934 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:47:49.181013 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:47:49.187943 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:47:49.191473 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 12:47:49.194454 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 12:47:49.201388 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 12:47:49.204710 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 12:47:49.208179 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 12:47:49.214671 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2581 12:47:49.215223 Total UI for P1: 0, mck2ui 16
2582 12:47:49.220966 best dqsien dly found for B0: ( 1, 3, 26)
2583 12:47:49.224449 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2584 12:47:49.227756 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 12:47:49.231422 Total UI for P1: 0, mck2ui 16
2586 12:47:49.234398 best dqsien dly found for B1: ( 1, 3, 30)
2587 12:47:49.238105 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2588 12:47:49.241156 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2589 12:47:49.241624
2590 12:47:49.247333 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2591 12:47:49.250766 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2592 12:47:49.251231 [Gating] SW calibration Done
2593 12:47:49.254568 ==
2594 12:47:49.257331 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 12:47:49.260930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 12:47:49.261398 ==
2597 12:47:49.261768 RX Vref Scan: 0
2598 12:47:49.262108
2599 12:47:49.264349 RX Vref 0 -> 0, step: 1
2600 12:47:49.265081
2601 12:47:49.267533 RX Delay -40 -> 252, step: 8
2602 12:47:49.270370 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2603 12:47:49.273887 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2604 12:47:49.280482 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2605 12:47:49.283721 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2606 12:47:49.287058 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2607 12:47:49.290407 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2608 12:47:49.294151 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2609 12:47:49.300450 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2610 12:47:49.303660 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2611 12:47:49.307334 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2612 12:47:49.310561 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2613 12:47:49.313896 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2614 12:47:49.317197 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2615 12:47:49.323900 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2616 12:47:49.327544 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2617 12:47:49.330661 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2618 12:47:49.331087 ==
2619 12:47:49.333459 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 12:47:49.340119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 12:47:49.340644 ==
2622 12:47:49.341027 DQS Delay:
2623 12:47:49.341371 DQS0 = 0, DQS1 = 0
2624 12:47:49.343359 DQM Delay:
2625 12:47:49.343817 DQM0 = 119, DQM1 = 105
2626 12:47:49.346825 DQ Delay:
2627 12:47:49.350910 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2628 12:47:49.353471 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2629 12:47:49.357001 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2630 12:47:49.360414 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2631 12:47:49.360990
2632 12:47:49.361330
2633 12:47:49.361640 ==
2634 12:47:49.363218 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 12:47:49.367194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 12:47:49.367718 ==
2637 12:47:49.370426
2638 12:47:49.370897
2639 12:47:49.371231 TX Vref Scan disable
2640 12:47:49.373088 == TX Byte 0 ==
2641 12:47:49.376504 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2642 12:47:49.380095 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2643 12:47:49.383254 == TX Byte 1 ==
2644 12:47:49.387099 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2645 12:47:49.390079 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2646 12:47:49.390508 ==
2647 12:47:49.393253 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 12:47:49.400250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 12:47:49.400800 ==
2650 12:47:49.410789 TX Vref=22, minBit 5, minWin=25, winSum=416
2651 12:47:49.414686 TX Vref=24, minBit 7, minWin=25, winSum=421
2652 12:47:49.417935 TX Vref=26, minBit 5, minWin=26, winSum=430
2653 12:47:49.421079 TX Vref=28, minBit 5, minWin=26, winSum=430
2654 12:47:49.424552 TX Vref=30, minBit 5, minWin=26, winSum=431
2655 12:47:49.430732 TX Vref=32, minBit 4, minWin=26, winSum=431
2656 12:47:49.434171 [TxChooseVref] Worse bit 5, Min win 26, Win sum 431, Final Vref 30
2657 12:47:49.434757
2658 12:47:49.437475 Final TX Range 1 Vref 30
2659 12:47:49.437937
2660 12:47:49.438302 ==
2661 12:47:49.441143 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 12:47:49.444091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 12:47:49.444710 ==
2664 12:47:49.445092
2665 12:47:49.448013
2666 12:47:49.448612 TX Vref Scan disable
2667 12:47:49.450952 == TX Byte 0 ==
2668 12:47:49.453998 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2669 12:47:49.457708 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2670 12:47:49.460578 == TX Byte 1 ==
2671 12:47:49.463980 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2672 12:47:49.470841 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2673 12:47:49.471405
2674 12:47:49.471775 [DATLAT]
2675 12:47:49.472115 Freq=1200, CH0 RK0
2676 12:47:49.472444
2677 12:47:49.473806 DATLAT Default: 0xd
2678 12:47:49.474264 0, 0xFFFF, sum = 0
2679 12:47:49.477215 1, 0xFFFF, sum = 0
2680 12:47:49.477679 2, 0xFFFF, sum = 0
2681 12:47:49.480800 3, 0xFFFF, sum = 0
2682 12:47:49.484550 4, 0xFFFF, sum = 0
2683 12:47:49.485118 5, 0xFFFF, sum = 0
2684 12:47:49.487241 6, 0xFFFF, sum = 0
2685 12:47:49.487708 7, 0xFFFF, sum = 0
2686 12:47:49.490688 8, 0xFFFF, sum = 0
2687 12:47:49.491261 9, 0xFFFF, sum = 0
2688 12:47:49.494237 10, 0xFFFF, sum = 0
2689 12:47:49.494805 11, 0xFFFF, sum = 0
2690 12:47:49.497153 12, 0x0, sum = 1
2691 12:47:49.497619 13, 0x0, sum = 2
2692 12:47:49.500570 14, 0x0, sum = 3
2693 12:47:49.501138 15, 0x0, sum = 4
2694 12:47:49.501518 best_step = 13
2695 12:47:49.503876
2696 12:47:49.504355 ==
2697 12:47:49.507394 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 12:47:49.510837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 12:47:49.511299 ==
2700 12:47:49.511663 RX Vref Scan: 1
2701 12:47:49.512003
2702 12:47:49.513876 Set Vref Range= 32 -> 127
2703 12:47:49.514335
2704 12:47:49.517148 RX Vref 32 -> 127, step: 1
2705 12:47:49.517611
2706 12:47:49.520749 RX Delay -21 -> 252, step: 4
2707 12:47:49.521332
2708 12:47:49.524349 Set Vref, RX VrefLevel [Byte0]: 32
2709 12:47:49.527266 [Byte1]: 32
2710 12:47:49.527738
2711 12:47:49.530891 Set Vref, RX VrefLevel [Byte0]: 33
2712 12:47:49.533909 [Byte1]: 33
2713 12:47:49.537446
2714 12:47:49.537915 Set Vref, RX VrefLevel [Byte0]: 34
2715 12:47:49.540484 [Byte1]: 34
2716 12:47:49.545364
2717 12:47:49.545834 Set Vref, RX VrefLevel [Byte0]: 35
2718 12:47:49.548322 [Byte1]: 35
2719 12:47:49.553200
2720 12:47:49.553759 Set Vref, RX VrefLevel [Byte0]: 36
2721 12:47:49.556310 [Byte1]: 36
2722 12:47:49.561083
2723 12:47:49.561549 Set Vref, RX VrefLevel [Byte0]: 37
2724 12:47:49.564740 [Byte1]: 37
2725 12:47:49.568916
2726 12:47:49.569475 Set Vref, RX VrefLevel [Byte0]: 38
2727 12:47:49.572363 [Byte1]: 38
2728 12:47:49.576689
2729 12:47:49.577156 Set Vref, RX VrefLevel [Byte0]: 39
2730 12:47:49.580149 [Byte1]: 39
2731 12:47:49.584663
2732 12:47:49.585131 Set Vref, RX VrefLevel [Byte0]: 40
2733 12:47:49.588494 [Byte1]: 40
2734 12:47:49.593179
2735 12:47:49.593735 Set Vref, RX VrefLevel [Byte0]: 41
2736 12:47:49.595918 [Byte1]: 41
2737 12:47:49.600467
2738 12:47:49.600973 Set Vref, RX VrefLevel [Byte0]: 42
2739 12:47:49.604442 [Byte1]: 42
2740 12:47:49.608640
2741 12:47:49.609148 Set Vref, RX VrefLevel [Byte0]: 43
2742 12:47:49.611700 [Byte1]: 43
2743 12:47:49.616771
2744 12:47:49.617334 Set Vref, RX VrefLevel [Byte0]: 44
2745 12:47:49.619539 [Byte1]: 44
2746 12:47:49.624837
2747 12:47:49.625396 Set Vref, RX VrefLevel [Byte0]: 45
2748 12:47:49.628550 [Byte1]: 45
2749 12:47:49.632351
2750 12:47:49.632994 Set Vref, RX VrefLevel [Byte0]: 46
2751 12:47:49.636100 [Byte1]: 46
2752 12:47:49.640815
2753 12:47:49.641375 Set Vref, RX VrefLevel [Byte0]: 47
2754 12:47:49.643460 [Byte1]: 47
2755 12:47:49.648235
2756 12:47:49.648839 Set Vref, RX VrefLevel [Byte0]: 48
2757 12:47:49.651492 [Byte1]: 48
2758 12:47:49.656454
2759 12:47:49.657065 Set Vref, RX VrefLevel [Byte0]: 49
2760 12:47:49.659356 [Byte1]: 49
2761 12:47:49.663769
2762 12:47:49.667689 Set Vref, RX VrefLevel [Byte0]: 50
2763 12:47:49.668249 [Byte1]: 50
2764 12:47:49.672317
2765 12:47:49.672959 Set Vref, RX VrefLevel [Byte0]: 51
2766 12:47:49.675261 [Byte1]: 51
2767 12:47:49.680046
2768 12:47:49.680674 Set Vref, RX VrefLevel [Byte0]: 52
2769 12:47:49.682965 [Byte1]: 52
2770 12:47:49.688069
2771 12:47:49.688574 Set Vref, RX VrefLevel [Byte0]: 53
2772 12:47:49.691301 [Byte1]: 53
2773 12:47:49.696276
2774 12:47:49.696867 Set Vref, RX VrefLevel [Byte0]: 54
2775 12:47:49.699114 [Byte1]: 54
2776 12:47:49.703813
2777 12:47:49.704380 Set Vref, RX VrefLevel [Byte0]: 55
2778 12:47:49.706798 [Byte1]: 55
2779 12:47:49.711538
2780 12:47:49.712004 Set Vref, RX VrefLevel [Byte0]: 56
2781 12:47:49.715653 [Byte1]: 56
2782 12:47:49.719683
2783 12:47:49.720237 Set Vref, RX VrefLevel [Byte0]: 57
2784 12:47:49.722901 [Byte1]: 57
2785 12:47:49.727734
2786 12:47:49.728300 Set Vref, RX VrefLevel [Byte0]: 58
2787 12:47:49.734540 [Byte1]: 58
2788 12:47:49.735109
2789 12:47:49.737350 Set Vref, RX VrefLevel [Byte0]: 59
2790 12:47:49.740567 [Byte1]: 59
2791 12:47:49.741055
2792 12:47:49.744245 Set Vref, RX VrefLevel [Byte0]: 60
2793 12:47:49.747639 [Byte1]: 60
2794 12:47:49.751328
2795 12:47:49.751886 Set Vref, RX VrefLevel [Byte0]: 61
2796 12:47:49.754424 [Byte1]: 61
2797 12:47:49.759043
2798 12:47:49.759508 Set Vref, RX VrefLevel [Byte0]: 62
2799 12:47:49.762226 [Byte1]: 62
2800 12:47:49.767194
2801 12:47:49.767755 Set Vref, RX VrefLevel [Byte0]: 63
2802 12:47:49.770590 [Byte1]: 63
2803 12:47:49.774801
2804 12:47:49.775275 Set Vref, RX VrefLevel [Byte0]: 64
2805 12:47:49.778703 [Byte1]: 64
2806 12:47:49.783428
2807 12:47:49.784004 Set Vref, RX VrefLevel [Byte0]: 65
2808 12:47:49.786254 [Byte1]: 65
2809 12:47:49.790883
2810 12:47:49.791449 Set Vref, RX VrefLevel [Byte0]: 66
2811 12:47:49.794265 [Byte1]: 66
2812 12:47:49.798579
2813 12:47:49.799045 Set Vref, RX VrefLevel [Byte0]: 67
2814 12:47:49.802131 [Byte1]: 67
2815 12:47:49.806709
2816 12:47:49.807173 Set Vref, RX VrefLevel [Byte0]: 68
2817 12:47:49.810018 [Byte1]: 68
2818 12:47:49.814902
2819 12:47:49.815462 Set Vref, RX VrefLevel [Byte0]: 69
2820 12:47:49.817913 [Byte1]: 69
2821 12:47:49.822615
2822 12:47:49.823228 Set Vref, RX VrefLevel [Byte0]: 70
2823 12:47:49.826053 [Byte1]: 70
2824 12:47:49.830598
2825 12:47:49.831161 Set Vref, RX VrefLevel [Byte0]: 71
2826 12:47:49.834441 [Byte1]: 71
2827 12:47:49.838560
2828 12:47:49.839125 Set Vref, RX VrefLevel [Byte0]: 72
2829 12:47:49.841978 [Byte1]: 72
2830 12:47:49.846522
2831 12:47:49.847079 Set Vref, RX VrefLevel [Byte0]: 73
2832 12:47:49.849987 [Byte1]: 73
2833 12:47:49.854482
2834 12:47:49.855050 Set Vref, RX VrefLevel [Byte0]: 74
2835 12:47:49.857819 [Byte1]: 74
2836 12:47:49.862408
2837 12:47:49.865186 Set Vref, RX VrefLevel [Byte0]: 75
2838 12:47:49.869031 [Byte1]: 75
2839 12:47:49.869597
2840 12:47:49.872019 Set Vref, RX VrefLevel [Byte0]: 76
2841 12:47:49.875172 [Byte1]: 76
2842 12:47:49.875638
2843 12:47:49.878985 Set Vref, RX VrefLevel [Byte0]: 77
2844 12:47:49.882169 [Byte1]: 77
2845 12:47:49.885853
2846 12:47:49.886414 Set Vref, RX VrefLevel [Byte0]: 78
2847 12:47:49.889413 [Byte1]: 78
2848 12:47:49.893926
2849 12:47:49.894390 Final RX Vref Byte 0 = 60 to rank0
2850 12:47:49.897264 Final RX Vref Byte 1 = 54 to rank0
2851 12:47:49.900687 Final RX Vref Byte 0 = 60 to rank1
2852 12:47:49.903560 Final RX Vref Byte 1 = 54 to rank1==
2853 12:47:49.906861 Dram Type= 6, Freq= 0, CH_0, rank 0
2854 12:47:49.913594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 12:47:49.914063 ==
2856 12:47:49.914435 DQS Delay:
2857 12:47:49.917087 DQS0 = 0, DQS1 = 0
2858 12:47:49.917546 DQM Delay:
2859 12:47:49.917912 DQM0 = 119, DQM1 = 106
2860 12:47:49.920367 DQ Delay:
2861 12:47:49.923933 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2862 12:47:49.927012 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =124
2863 12:47:49.930691 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =100
2864 12:47:49.933466 DQ12 =112, DQ13 =108, DQ14 =120, DQ15 =116
2865 12:47:49.933931
2866 12:47:49.934299
2867 12:47:49.943953 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2868 12:47:49.944558 CH0 RK0: MR19=403, MR18=BF7
2869 12:47:49.950315 CH0_RK0: MR19=0x403, MR18=0xBF7, DQSOSC=405, MR23=63, INC=39, DEC=26
2870 12:47:49.950893
2871 12:47:49.953511 ----->DramcWriteLeveling(PI) begin...
2872 12:47:49.954078 ==
2873 12:47:49.956770 Dram Type= 6, Freq= 0, CH_0, rank 1
2874 12:47:49.963486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2875 12:47:49.964054 ==
2876 12:47:49.966697 Write leveling (Byte 0): 32 => 32
2877 12:47:49.967240 Write leveling (Byte 1): 32 => 32
2878 12:47:49.970543 DramcWriteLeveling(PI) end<-----
2879 12:47:49.971104
2880 12:47:49.971490 ==
2881 12:47:49.972978 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 12:47:49.980339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 12:47:49.980850 ==
2884 12:47:49.983433 [Gating] SW mode calibration
2885 12:47:49.990032 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2886 12:47:49.993376 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2887 12:47:50.000397 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2888 12:47:50.003771 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2889 12:47:50.007517 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 12:47:50.013431 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 12:47:50.016581 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 12:47:50.020154 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 12:47:50.023846 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 12:47:50.029969 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
2895 12:47:50.033301 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
2896 12:47:50.036593 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 12:47:50.043137 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 12:47:50.046749 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 12:47:50.050039 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 12:47:50.056608 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 12:47:50.060085 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 12:47:50.062992 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2903 12:47:50.069837 1 1 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
2904 12:47:50.073369 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 12:47:50.076260 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 12:47:50.083103 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 12:47:50.086156 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 12:47:50.089765 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 12:47:50.096685 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 12:47:50.099862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2911 12:47:50.103540 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2912 12:47:50.109662 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 12:47:50.113231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 12:47:50.116322 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 12:47:50.123169 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 12:47:50.126862 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 12:47:50.129990 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 12:47:50.136475 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:47:50.139236 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:47:50.142577 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:47:50.149448 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:47:50.153083 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:47:50.156033 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:47:50.162348 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 12:47:50.165666 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2926 12:47:50.169459 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2927 12:47:50.176095 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2928 12:47:50.176689 Total UI for P1: 0, mck2ui 16
2929 12:47:50.179604 best dqsien dly found for B0: ( 1, 3, 26)
2930 12:47:50.186022 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 12:47:50.189377 Total UI for P1: 0, mck2ui 16
2932 12:47:50.192664 best dqsien dly found for B1: ( 1, 4, 0)
2933 12:47:50.195568 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2934 12:47:50.199424 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2935 12:47:50.199995
2936 12:47:50.202572 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2937 12:47:50.205700 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2938 12:47:50.208695 [Gating] SW calibration Done
2939 12:47:50.209156 ==
2940 12:47:50.212572 Dram Type= 6, Freq= 0, CH_0, rank 1
2941 12:47:50.215691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2942 12:47:50.216159 ==
2943 12:47:50.219374 RX Vref Scan: 0
2944 12:47:50.219945
2945 12:47:50.222200 RX Vref 0 -> 0, step: 1
2946 12:47:50.222771
2947 12:47:50.223146 RX Delay -40 -> 252, step: 8
2948 12:47:50.229195 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2949 12:47:50.232039 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2950 12:47:50.235756 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2951 12:47:50.238671 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2952 12:47:50.242276 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2953 12:47:50.248847 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2954 12:47:50.252372 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2955 12:47:50.255503 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2956 12:47:50.259423 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2957 12:47:50.262292 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2958 12:47:50.269068 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2959 12:47:50.272362 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2960 12:47:50.275178 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2961 12:47:50.278664 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2962 12:47:50.281569 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2963 12:47:50.288855 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2964 12:47:50.289477 ==
2965 12:47:50.291958 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 12:47:50.294855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 12:47:50.295374 ==
2968 12:47:50.295936 DQS Delay:
2969 12:47:50.298097 DQS0 = 0, DQS1 = 0
2970 12:47:50.298560 DQM Delay:
2971 12:47:50.302551 DQM0 = 117, DQM1 = 108
2972 12:47:50.303124 DQ Delay:
2973 12:47:50.305031 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2974 12:47:50.308377 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2975 12:47:50.311800 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2976 12:47:50.314882 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
2977 12:47:50.315360
2978 12:47:50.315733
2979 12:47:50.318558 ==
2980 12:47:50.321639 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 12:47:50.325044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 12:47:50.325516 ==
2983 12:47:50.325890
2984 12:47:50.326235
2985 12:47:50.328042 TX Vref Scan disable
2986 12:47:50.328506 == TX Byte 0 ==
2987 12:47:50.334600 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2988 12:47:50.337920 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2989 12:47:50.338394 == TX Byte 1 ==
2990 12:47:50.344668 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2991 12:47:50.348240 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2992 12:47:50.348837 ==
2993 12:47:50.351932 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 12:47:50.354771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 12:47:50.355340 ==
2996 12:47:50.366997 TX Vref=22, minBit 5, minWin=25, winSum=421
2997 12:47:50.370381 TX Vref=24, minBit 0, minWin=26, winSum=426
2998 12:47:50.373780 TX Vref=26, minBit 1, minWin=26, winSum=428
2999 12:47:50.376719 TX Vref=28, minBit 1, minWin=26, winSum=432
3000 12:47:50.380356 TX Vref=30, minBit 11, minWin=26, winSum=433
3001 12:47:50.386724 TX Vref=32, minBit 10, minWin=25, winSum=428
3002 12:47:50.389910 [TxChooseVref] Worse bit 11, Min win 26, Win sum 433, Final Vref 30
3003 12:47:50.390471
3004 12:47:50.393517 Final TX Range 1 Vref 30
3005 12:47:50.394082
3006 12:47:50.394455 ==
3007 12:47:50.396612 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 12:47:50.403010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 12:47:50.403577 ==
3010 12:47:50.403952
3011 12:47:50.404301
3012 12:47:50.404673 TX Vref Scan disable
3013 12:47:50.406777 == TX Byte 0 ==
3014 12:47:50.410410 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3015 12:47:50.416752 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3016 12:47:50.417309 == TX Byte 1 ==
3017 12:47:50.420146 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3018 12:47:50.426647 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3019 12:47:50.427197
3020 12:47:50.427561 [DATLAT]
3021 12:47:50.427906 Freq=1200, CH0 RK1
3022 12:47:50.428241
3023 12:47:50.430062 DATLAT Default: 0xd
3024 12:47:50.430528 0, 0xFFFF, sum = 0
3025 12:47:50.433098 1, 0xFFFF, sum = 0
3026 12:47:50.436496 2, 0xFFFF, sum = 0
3027 12:47:50.437012 3, 0xFFFF, sum = 0
3028 12:47:50.439885 4, 0xFFFF, sum = 0
3029 12:47:50.440357 5, 0xFFFF, sum = 0
3030 12:47:50.442933 6, 0xFFFF, sum = 0
3031 12:47:50.443405 7, 0xFFFF, sum = 0
3032 12:47:50.446399 8, 0xFFFF, sum = 0
3033 12:47:50.446865 9, 0xFFFF, sum = 0
3034 12:47:50.449773 10, 0xFFFF, sum = 0
3035 12:47:50.450346 11, 0xFFFF, sum = 0
3036 12:47:50.452996 12, 0x0, sum = 1
3037 12:47:50.453468 13, 0x0, sum = 2
3038 12:47:50.456752 14, 0x0, sum = 3
3039 12:47:50.457324 15, 0x0, sum = 4
3040 12:47:50.459962 best_step = 13
3041 12:47:50.460550
3042 12:47:50.460929 ==
3043 12:47:50.463589 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 12:47:50.466375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 12:47:50.466840 ==
3046 12:47:50.470531 RX Vref Scan: 0
3047 12:47:50.470995
3048 12:47:50.471362 RX Vref 0 -> 0, step: 1
3049 12:47:50.471704
3050 12:47:50.472813 RX Delay -21 -> 252, step: 4
3051 12:47:50.479446 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3052 12:47:50.482940 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3053 12:47:50.486396 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3054 12:47:50.489551 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3055 12:47:50.493246 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3056 12:47:50.499644 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3057 12:47:50.502584 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3058 12:47:50.506548 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3059 12:47:50.509088 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3060 12:47:50.512652 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3061 12:47:50.519597 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3062 12:47:50.522491 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3063 12:47:50.526586 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3064 12:47:50.529450 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3065 12:47:50.532485 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3066 12:47:50.539011 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3067 12:47:50.539724 ==
3068 12:47:50.543064 Dram Type= 6, Freq= 0, CH_0, rank 1
3069 12:47:50.546332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 12:47:50.546892 ==
3071 12:47:50.547267 DQS Delay:
3072 12:47:50.549064 DQS0 = 0, DQS1 = 0
3073 12:47:50.549532 DQM Delay:
3074 12:47:50.552254 DQM0 = 116, DQM1 = 108
3075 12:47:50.552738 DQ Delay:
3076 12:47:50.555825 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3077 12:47:50.559321 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3078 12:47:50.562594 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =100
3079 12:47:50.565626 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =116
3080 12:47:50.566116
3081 12:47:50.566517
3082 12:47:50.575747 [DQSOSCAuto] RK1, (LSB)MR18= 0xce7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3083 12:47:50.578732 CH0 RK1: MR19=403, MR18=CE7
3084 12:47:50.582515 CH0_RK1: MR19=0x403, MR18=0xCE7, DQSOSC=405, MR23=63, INC=39, DEC=26
3085 12:47:50.586222 [RxdqsGatingPostProcess] freq 1200
3086 12:47:50.592944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3087 12:47:50.595815 best DQS0 dly(2T, 0.5T) = (0, 11)
3088 12:47:50.599079 best DQS1 dly(2T, 0.5T) = (0, 11)
3089 12:47:50.603101 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3090 12:47:50.606328 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3091 12:47:50.608918 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 12:47:50.612455 best DQS1 dly(2T, 0.5T) = (0, 12)
3093 12:47:50.615532 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 12:47:50.619095 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3095 12:47:50.619666 Pre-setting of DQS Precalculation
3096 12:47:50.625381 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3097 12:47:50.625982 ==
3098 12:47:50.629030 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 12:47:50.631837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 12:47:50.632306 ==
3101 12:47:50.638323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 12:47:50.645119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 12:47:50.653311 [CA 0] Center 38 (8~68) winsize 61
3104 12:47:50.656251 [CA 1] Center 38 (8~68) winsize 61
3105 12:47:50.659610 [CA 2] Center 34 (4~64) winsize 61
3106 12:47:50.663481 [CA 3] Center 33 (3~64) winsize 62
3107 12:47:50.666132 [CA 4] Center 34 (4~64) winsize 61
3108 12:47:50.670123 [CA 5] Center 33 (3~64) winsize 62
3109 12:47:50.670694
3110 12:47:50.673230 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 12:47:50.673703
3112 12:47:50.676140 [CATrainingPosCal] consider 1 rank data
3113 12:47:50.679921 u2DelayCellTimex100 = 270/100 ps
3114 12:47:50.682837 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3115 12:47:50.689141 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 12:47:50.692784 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3117 12:47:50.696042 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3118 12:47:50.699187 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 12:47:50.702909 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3120 12:47:50.703492
3121 12:47:50.705993 CA PerBit enable=1, Macro0, CA PI delay=33
3122 12:47:50.706459
3123 12:47:50.709359 [CBTSetCACLKResult] CA Dly = 33
3124 12:47:50.709927 CS Dly: 6 (0~37)
3125 12:47:50.712970 ==
3126 12:47:50.715861 Dram Type= 6, Freq= 0, CH_1, rank 1
3127 12:47:50.719647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 12:47:50.720217 ==
3129 12:47:50.725816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 12:47:50.729195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3131 12:47:50.738595 [CA 0] Center 37 (7~67) winsize 61
3132 12:47:50.742446 [CA 1] Center 38 (8~68) winsize 61
3133 12:47:50.745046 [CA 2] Center 34 (4~65) winsize 62
3134 12:47:50.748877 [CA 3] Center 33 (3~64) winsize 62
3135 12:47:50.751859 [CA 4] Center 34 (4~65) winsize 62
3136 12:47:50.755063 [CA 5] Center 33 (3~64) winsize 62
3137 12:47:50.755634
3138 12:47:50.759267 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3139 12:47:50.759823
3140 12:47:50.762066 [CATrainingPosCal] consider 2 rank data
3141 12:47:50.765339 u2DelayCellTimex100 = 270/100 ps
3142 12:47:50.768885 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3143 12:47:50.772002 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3144 12:47:50.778630 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3145 12:47:50.782447 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3146 12:47:50.785600 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 12:47:50.788636 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3148 12:47:50.789219
3149 12:47:50.792331 CA PerBit enable=1, Macro0, CA PI delay=33
3150 12:47:50.792937
3151 12:47:50.796002 [CBTSetCACLKResult] CA Dly = 33
3152 12:47:50.796606 CS Dly: 7 (0~40)
3153 12:47:50.796982
3154 12:47:50.798849 ----->DramcWriteLeveling(PI) begin...
3155 12:47:50.801821 ==
3156 12:47:50.805157 Dram Type= 6, Freq= 0, CH_1, rank 0
3157 12:47:50.808623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3158 12:47:50.809196 ==
3159 12:47:50.811892 Write leveling (Byte 0): 27 => 27
3160 12:47:50.815443 Write leveling (Byte 1): 29 => 29
3161 12:47:50.818335 DramcWriteLeveling(PI) end<-----
3162 12:47:50.818805
3163 12:47:50.819173 ==
3164 12:47:50.822238 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 12:47:50.824957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 12:47:50.825451 ==
3167 12:47:50.828133 [Gating] SW mode calibration
3168 12:47:50.835433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3169 12:47:50.838490 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3170 12:47:50.844899 0 15 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
3171 12:47:50.848679 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 12:47:50.851861 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 12:47:50.858710 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 12:47:50.861813 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 12:47:50.865150 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 12:47:50.871768 0 15 24 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
3177 12:47:50.874972 0 15 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
3178 12:47:50.878538 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 12:47:50.884887 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 12:47:50.888165 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 12:47:50.891843 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 12:47:50.898491 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 12:47:50.901811 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 12:47:50.904845 1 0 24 | B1->B0 | 2525 3b3b | 0 1 | (0 0) (1 1)
3185 12:47:50.911755 1 0 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3186 12:47:50.914673 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 12:47:50.917940 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 12:47:50.924719 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 12:47:50.928164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 12:47:50.931129 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 12:47:50.938075 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 12:47:50.941052 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3193 12:47:50.944610 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3194 12:47:50.951227 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 12:47:50.954526 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 12:47:50.957507 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 12:47:50.964491 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 12:47:50.967440 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 12:47:50.970925 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 12:47:50.977717 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:47:50.980468 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 12:47:50.983928 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 12:47:50.990691 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:47:50.994270 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:47:50.997272 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:47:51.003676 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 12:47:51.007274 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:47:51.010511 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3209 12:47:51.014297 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3210 12:47:51.020521 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 12:47:51.023822 Total UI for P1: 0, mck2ui 16
3212 12:47:51.027539 best dqsien dly found for B0: ( 1, 3, 26)
3213 12:47:51.030340 Total UI for P1: 0, mck2ui 16
3214 12:47:51.033697 best dqsien dly found for B1: ( 1, 3, 28)
3215 12:47:51.036921 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3216 12:47:51.040484 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3217 12:47:51.040655
3218 12:47:51.043965 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3219 12:47:51.047470 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3220 12:47:51.050439 [Gating] SW calibration Done
3221 12:47:51.050642 ==
3222 12:47:51.053791 Dram Type= 6, Freq= 0, CH_1, rank 0
3223 12:47:51.056749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3224 12:47:51.056925 ==
3225 12:47:51.060209 RX Vref Scan: 0
3226 12:47:51.060349
3227 12:47:51.063431 RX Vref 0 -> 0, step: 1
3228 12:47:51.063590
3229 12:47:51.063727 RX Delay -40 -> 252, step: 8
3230 12:47:51.070078 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3231 12:47:51.073242 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3232 12:47:51.076866 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3233 12:47:51.080309 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3234 12:47:51.083553 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3235 12:47:51.090725 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3236 12:47:51.093580 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3237 12:47:51.097087 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3238 12:47:51.100086 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3239 12:47:51.103778 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3240 12:47:51.110220 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3241 12:47:51.113396 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3242 12:47:51.116788 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3243 12:47:51.120059 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3244 12:47:51.123370 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3245 12:47:51.130580 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3246 12:47:51.131143 ==
3247 12:47:51.133207 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 12:47:51.136640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 12:47:51.137106 ==
3250 12:47:51.137480 DQS Delay:
3251 12:47:51.139979 DQS0 = 0, DQS1 = 0
3252 12:47:51.140442 DQM Delay:
3253 12:47:51.143346 DQM0 = 119, DQM1 = 111
3254 12:47:51.143825 DQ Delay:
3255 12:47:51.146812 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3256 12:47:51.149935 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =115
3257 12:47:51.153419 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =99
3258 12:47:51.156796 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3259 12:47:51.159759
3260 12:47:51.160315
3261 12:47:51.160732 ==
3262 12:47:51.163151 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 12:47:51.166651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 12:47:51.167125 ==
3265 12:47:51.167608
3266 12:47:51.168127
3267 12:47:51.169390 TX Vref Scan disable
3268 12:47:51.169855 == TX Byte 0 ==
3269 12:47:51.176011 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 12:47:51.179697 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 12:47:51.180183 == TX Byte 1 ==
3272 12:47:51.186291 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3273 12:47:51.189302 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3274 12:47:51.189726 ==
3275 12:47:51.192788 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 12:47:51.195922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 12:47:51.196365 ==
3278 12:47:51.208477 TX Vref=22, minBit 0, minWin=25, winSum=413
3279 12:47:51.211811 TX Vref=24, minBit 1, minWin=25, winSum=419
3280 12:47:51.215827 TX Vref=26, minBit 0, minWin=26, winSum=426
3281 12:47:51.218378 TX Vref=28, minBit 3, minWin=25, winSum=425
3282 12:47:51.221695 TX Vref=30, minBit 1, minWin=26, winSum=426
3283 12:47:51.228619 TX Vref=32, minBit 9, minWin=25, winSum=422
3284 12:47:51.231937 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
3285 12:47:51.232361
3286 12:47:51.235003 Final TX Range 1 Vref 26
3287 12:47:51.235552
3288 12:47:51.236026 ==
3289 12:47:51.238575 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 12:47:51.242462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 12:47:51.242998 ==
3292 12:47:51.243367
3293 12:47:51.245280
3294 12:47:51.245750 TX Vref Scan disable
3295 12:47:51.248546 == TX Byte 0 ==
3296 12:47:51.252348 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3297 12:47:51.255126 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3298 12:47:51.258615 == TX Byte 1 ==
3299 12:47:51.261631 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3300 12:47:51.265114 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3301 12:47:51.268137
3302 12:47:51.268577 [DATLAT]
3303 12:47:51.268911 Freq=1200, CH1 RK0
3304 12:47:51.269219
3305 12:47:51.271993 DATLAT Default: 0xd
3306 12:47:51.272709 0, 0xFFFF, sum = 0
3307 12:47:51.274709 1, 0xFFFF, sum = 0
3308 12:47:51.275164 2, 0xFFFF, sum = 0
3309 12:47:51.278190 3, 0xFFFF, sum = 0
3310 12:47:51.281656 4, 0xFFFF, sum = 0
3311 12:47:51.282073 5, 0xFFFF, sum = 0
3312 12:47:51.284957 6, 0xFFFF, sum = 0
3313 12:47:51.285371 7, 0xFFFF, sum = 0
3314 12:47:51.287896 8, 0xFFFF, sum = 0
3315 12:47:51.288552 9, 0xFFFF, sum = 0
3316 12:47:51.291060 10, 0xFFFF, sum = 0
3317 12:47:51.291478 11, 0xFFFF, sum = 0
3318 12:47:51.294626 12, 0x0, sum = 1
3319 12:47:51.295079 13, 0x0, sum = 2
3320 12:47:51.298053 14, 0x0, sum = 3
3321 12:47:51.298535 15, 0x0, sum = 4
3322 12:47:51.301369 best_step = 13
3323 12:47:51.301776
3324 12:47:51.302100 ==
3325 12:47:51.304815 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 12:47:51.308109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 12:47:51.308597 ==
3328 12:47:51.308932 RX Vref Scan: 1
3329 12:47:51.309242
3330 12:47:51.311294 Set Vref Range= 32 -> 127
3331 12:47:51.311707
3332 12:47:51.314325 RX Vref 32 -> 127, step: 1
3333 12:47:51.314823
3334 12:47:51.317415 RX Delay -13 -> 252, step: 4
3335 12:47:51.317898
3336 12:47:51.321011 Set Vref, RX VrefLevel [Byte0]: 32
3337 12:47:51.324134 [Byte1]: 32
3338 12:47:51.324597
3339 12:47:51.327645 Set Vref, RX VrefLevel [Byte0]: 33
3340 12:47:51.331336 [Byte1]: 33
3341 12:47:51.334644
3342 12:47:51.335095 Set Vref, RX VrefLevel [Byte0]: 34
3343 12:47:51.337531 [Byte1]: 34
3344 12:47:51.342500
3345 12:47:51.342944 Set Vref, RX VrefLevel [Byte0]: 35
3346 12:47:51.345808 [Byte1]: 35
3347 12:47:51.350546
3348 12:47:51.350993 Set Vref, RX VrefLevel [Byte0]: 36
3349 12:47:51.353622 [Byte1]: 36
3350 12:47:51.358343
3351 12:47:51.358875 Set Vref, RX VrefLevel [Byte0]: 37
3352 12:47:51.361728 [Byte1]: 37
3353 12:47:51.365973
3354 12:47:51.366412 Set Vref, RX VrefLevel [Byte0]: 38
3355 12:47:51.369403 [Byte1]: 38
3356 12:47:51.374002
3357 12:47:51.374438 Set Vref, RX VrefLevel [Byte0]: 39
3358 12:47:51.377286 [Byte1]: 39
3359 12:47:51.381737
3360 12:47:51.382186 Set Vref, RX VrefLevel [Byte0]: 40
3361 12:47:51.385300 [Byte1]: 40
3362 12:47:51.389548
3363 12:47:51.389986 Set Vref, RX VrefLevel [Byte0]: 41
3364 12:47:51.393229 [Byte1]: 41
3365 12:47:51.397337
3366 12:47:51.397845 Set Vref, RX VrefLevel [Byte0]: 42
3367 12:47:51.400732 [Byte1]: 42
3368 12:47:51.405460
3369 12:47:51.405914 Set Vref, RX VrefLevel [Byte0]: 43
3370 12:47:51.409543 [Byte1]: 43
3371 12:47:51.413662
3372 12:47:51.414073 Set Vref, RX VrefLevel [Byte0]: 44
3373 12:47:51.417022 [Byte1]: 44
3374 12:47:51.421525
3375 12:47:51.421952 Set Vref, RX VrefLevel [Byte0]: 45
3376 12:47:51.425043 [Byte1]: 45
3377 12:47:51.429148
3378 12:47:51.429600 Set Vref, RX VrefLevel [Byte0]: 46
3379 12:47:51.432455 [Byte1]: 46
3380 12:47:51.437153
3381 12:47:51.437563 Set Vref, RX VrefLevel [Byte0]: 47
3382 12:47:51.440322 [Byte1]: 47
3383 12:47:51.444838
3384 12:47:51.445274 Set Vref, RX VrefLevel [Byte0]: 48
3385 12:47:51.448907 [Byte1]: 48
3386 12:47:51.452742
3387 12:47:51.453312 Set Vref, RX VrefLevel [Byte0]: 49
3388 12:47:51.456449 [Byte1]: 49
3389 12:47:51.460965
3390 12:47:51.461515 Set Vref, RX VrefLevel [Byte0]: 50
3391 12:47:51.464089 [Byte1]: 50
3392 12:47:51.468501
3393 12:47:51.468999 Set Vref, RX VrefLevel [Byte0]: 51
3394 12:47:51.471687 [Byte1]: 51
3395 12:47:51.476618
3396 12:47:51.477113 Set Vref, RX VrefLevel [Byte0]: 52
3397 12:47:51.479551 [Byte1]: 52
3398 12:47:51.484423
3399 12:47:51.484917 Set Vref, RX VrefLevel [Byte0]: 53
3400 12:47:51.487481 [Byte1]: 53
3401 12:47:51.492474
3402 12:47:51.492979 Set Vref, RX VrefLevel [Byte0]: 54
3403 12:47:51.495507 [Byte1]: 54
3404 12:47:51.500618
3405 12:47:51.501150 Set Vref, RX VrefLevel [Byte0]: 55
3406 12:47:51.503933 [Byte1]: 55
3407 12:47:51.507985
3408 12:47:51.508582 Set Vref, RX VrefLevel [Byte0]: 56
3409 12:47:51.511453 [Byte1]: 56
3410 12:47:51.516159
3411 12:47:51.516606 Set Vref, RX VrefLevel [Byte0]: 57
3412 12:47:51.519277 [Byte1]: 57
3413 12:47:51.523913
3414 12:47:51.524409 Set Vref, RX VrefLevel [Byte0]: 58
3415 12:47:51.526946 [Byte1]: 58
3416 12:47:51.531670
3417 12:47:51.532209 Set Vref, RX VrefLevel [Byte0]: 59
3418 12:47:51.535085 [Byte1]: 59
3419 12:47:51.539466
3420 12:47:51.539987 Set Vref, RX VrefLevel [Byte0]: 60
3421 12:47:51.542769 [Byte1]: 60
3422 12:47:51.547511
3423 12:47:51.548070 Set Vref, RX VrefLevel [Byte0]: 61
3424 12:47:51.550903 [Byte1]: 61
3425 12:47:51.555115
3426 12:47:51.555693 Set Vref, RX VrefLevel [Byte0]: 62
3427 12:47:51.558728 [Byte1]: 62
3428 12:47:51.563030
3429 12:47:51.563493 Set Vref, RX VrefLevel [Byte0]: 63
3430 12:47:51.566276 [Byte1]: 63
3431 12:47:51.571782
3432 12:47:51.572203 Set Vref, RX VrefLevel [Byte0]: 64
3433 12:47:51.574346 [Byte1]: 64
3434 12:47:51.578846
3435 12:47:51.579396 Set Vref, RX VrefLevel [Byte0]: 65
3436 12:47:51.582585 [Byte1]: 65
3437 12:47:51.586892
3438 12:47:51.587471 Set Vref, RX VrefLevel [Byte0]: 66
3439 12:47:51.590246 [Byte1]: 66
3440 12:47:51.594893
3441 12:47:51.595363 Set Vref, RX VrefLevel [Byte0]: 67
3442 12:47:51.598084 [Byte1]: 67
3443 12:47:51.602331
3444 12:47:51.602848 Set Vref, RX VrefLevel [Byte0]: 68
3445 12:47:51.605578 [Byte1]: 68
3446 12:47:51.610541
3447 12:47:51.610963 Final RX Vref Byte 0 = 50 to rank0
3448 12:47:51.614010 Final RX Vref Byte 1 = 54 to rank0
3449 12:47:51.616909 Final RX Vref Byte 0 = 50 to rank1
3450 12:47:51.620248 Final RX Vref Byte 1 = 54 to rank1==
3451 12:47:51.623791 Dram Type= 6, Freq= 0, CH_1, rank 0
3452 12:47:51.630274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 12:47:51.630827 ==
3454 12:47:51.631322 DQS Delay:
3455 12:47:51.633696 DQS0 = 0, DQS1 = 0
3456 12:47:51.634148 DQM Delay:
3457 12:47:51.634533 DQM0 = 117, DQM1 = 111
3458 12:47:51.636597 DQ Delay:
3459 12:47:51.640398 DQ0 =122, DQ1 =112, DQ2 =108, DQ3 =112
3460 12:47:51.643552 DQ4 =116, DQ5 =130, DQ6 =126, DQ7 =114
3461 12:47:51.647018 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =100
3462 12:47:51.650355 DQ12 =118, DQ13 =120, DQ14 =120, DQ15 =120
3463 12:47:51.650909
3464 12:47:51.651296
3465 12:47:51.659939 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3466 12:47:51.660485 CH1 RK0: MR19=403, MR18=5F8
3467 12:47:51.666533 CH1_RK0: MR19=0x403, MR18=0x5F8, DQSOSC=408, MR23=63, INC=39, DEC=26
3468 12:47:51.667110
3469 12:47:51.670484 ----->DramcWriteLeveling(PI) begin...
3470 12:47:51.671103 ==
3471 12:47:51.672952 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 12:47:51.679696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 12:47:51.680281 ==
3474 12:47:51.682862 Write leveling (Byte 0): 27 => 27
3475 12:47:51.683439 Write leveling (Byte 1): 30 => 30
3476 12:47:51.686258 DramcWriteLeveling(PI) end<-----
3477 12:47:51.686707
3478 12:47:51.689863 ==
3479 12:47:51.690363 Dram Type= 6, Freq= 0, CH_1, rank 1
3480 12:47:51.696694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3481 12:47:51.697270 ==
3482 12:47:51.699433 [Gating] SW mode calibration
3483 12:47:51.706551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3484 12:47:51.709741 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3485 12:47:51.717006 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 12:47:51.719854 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 12:47:51.724048 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 12:47:51.729669 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 12:47:51.732441 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 12:47:51.736079 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 12:47:51.742759 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3492 12:47:51.745724 0 15 28 | B1->B0 | 2828 2b2b | 0 0 | (1 0) (1 0)
3493 12:47:51.749548 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 12:47:51.756188 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 12:47:51.759064 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 12:47:51.762981 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 12:47:51.768852 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 12:47:51.772845 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 12:47:51.775548 1 0 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
3500 12:47:51.782281 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3501 12:47:51.785273 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 12:47:51.788492 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 12:47:51.795522 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 12:47:51.798970 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 12:47:51.802695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 12:47:51.808874 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 12:47:51.812099 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 12:47:51.815082 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3509 12:47:51.821931 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 12:47:51.825041 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 12:47:51.829095 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 12:47:51.835410 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 12:47:51.838359 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 12:47:51.841959 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 12:47:51.848669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 12:47:51.851671 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 12:47:51.854794 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 12:47:51.861471 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 12:47:51.864778 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 12:47:51.868456 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 12:47:51.874899 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 12:47:51.878091 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 12:47:51.881457 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3524 12:47:51.888060 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3525 12:47:51.888479 Total UI for P1: 0, mck2ui 16
3526 12:47:51.894982 best dqsien dly found for B1: ( 1, 3, 24)
3527 12:47:51.898108 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 12:47:51.900947 Total UI for P1: 0, mck2ui 16
3529 12:47:51.904276 best dqsien dly found for B0: ( 1, 3, 26)
3530 12:47:51.907441 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3531 12:47:51.910881 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3532 12:47:51.911337
3533 12:47:51.914230 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3534 12:47:51.917365 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3535 12:47:51.920713 [Gating] SW calibration Done
3536 12:47:51.921139 ==
3537 12:47:51.924448 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 12:47:51.927098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 12:47:51.930747 ==
3540 12:47:51.931171 RX Vref Scan: 0
3541 12:47:51.931513
3542 12:47:51.933724 RX Vref 0 -> 0, step: 1
3543 12:47:51.934148
3544 12:47:51.937022 RX Delay -40 -> 252, step: 8
3545 12:47:51.940423 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3546 12:47:51.944281 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3547 12:47:51.947309 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3548 12:47:51.950323 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3549 12:47:51.956841 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3550 12:47:51.960556 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3551 12:47:51.963516 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3552 12:47:51.966830 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3553 12:47:51.970386 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3554 12:47:51.976640 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3555 12:47:51.980109 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3556 12:47:51.983208 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3557 12:47:51.986412 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3558 12:47:51.993061 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3559 12:47:51.996337 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3560 12:47:51.999977 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3561 12:47:52.000406 ==
3562 12:47:52.003124 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 12:47:52.006324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 12:47:52.006753 ==
3565 12:47:52.010341 DQS Delay:
3566 12:47:52.010763 DQS0 = 0, DQS1 = 0
3567 12:47:52.013191 DQM Delay:
3568 12:47:52.013612 DQM0 = 117, DQM1 = 110
3569 12:47:52.013948 DQ Delay:
3570 12:47:52.016619 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3571 12:47:52.022799 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3572 12:47:52.025947 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3573 12:47:52.029939 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3574 12:47:52.030366
3575 12:47:52.030703
3576 12:47:52.031018 ==
3577 12:47:52.032709 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 12:47:52.036082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 12:47:52.036508 ==
3580 12:47:52.036901
3581 12:47:52.037220
3582 12:47:52.039602 TX Vref Scan disable
3583 12:47:52.042791 == TX Byte 0 ==
3584 12:47:52.046411 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3585 12:47:52.049011 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3586 12:47:52.052671 == TX Byte 1 ==
3587 12:47:52.056218 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3588 12:47:52.058872 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3589 12:47:52.059319 ==
3590 12:47:52.062725 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 12:47:52.065890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 12:47:52.069122 ==
3593 12:47:52.079336 TX Vref=22, minBit 0, minWin=25, winSum=418
3594 12:47:52.082811 TX Vref=24, minBit 3, minWin=25, winSum=427
3595 12:47:52.085935 TX Vref=26, minBit 3, minWin=25, winSum=428
3596 12:47:52.089341 TX Vref=28, minBit 3, minWin=26, winSum=429
3597 12:47:52.092393 TX Vref=30, minBit 1, minWin=26, winSum=426
3598 12:47:52.099263 TX Vref=32, minBit 9, minWin=25, winSum=424
3599 12:47:52.102650 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 28
3600 12:47:52.103056
3601 12:47:52.106015 Final TX Range 1 Vref 28
3602 12:47:52.106444
3603 12:47:52.106789 ==
3604 12:47:52.109142 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 12:47:52.112681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 12:47:52.113091 ==
3607 12:47:52.115685
3608 12:47:52.116140
3609 12:47:52.116482 TX Vref Scan disable
3610 12:47:52.118660 == TX Byte 0 ==
3611 12:47:52.122369 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3612 12:47:52.129084 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3613 12:47:52.129516 == TX Byte 1 ==
3614 12:47:52.131949 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3615 12:47:52.138965 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3616 12:47:52.139443
3617 12:47:52.139816 [DATLAT]
3618 12:47:52.140189 Freq=1200, CH1 RK1
3619 12:47:52.140570
3620 12:47:52.142330 DATLAT Default: 0xd
3621 12:47:52.145431 0, 0xFFFF, sum = 0
3622 12:47:52.145916 1, 0xFFFF, sum = 0
3623 12:47:52.148500 2, 0xFFFF, sum = 0
3624 12:47:52.148985 3, 0xFFFF, sum = 0
3625 12:47:52.151810 4, 0xFFFF, sum = 0
3626 12:47:52.152232 5, 0xFFFF, sum = 0
3627 12:47:52.155183 6, 0xFFFF, sum = 0
3628 12:47:52.155604 7, 0xFFFF, sum = 0
3629 12:47:52.158941 8, 0xFFFF, sum = 0
3630 12:47:52.159360 9, 0xFFFF, sum = 0
3631 12:47:52.162411 10, 0xFFFF, sum = 0
3632 12:47:52.162832 11, 0xFFFF, sum = 0
3633 12:47:52.165065 12, 0x0, sum = 1
3634 12:47:52.165488 13, 0x0, sum = 2
3635 12:47:52.168489 14, 0x0, sum = 3
3636 12:47:52.168935 15, 0x0, sum = 4
3637 12:47:52.171864 best_step = 13
3638 12:47:52.172276
3639 12:47:52.172639 ==
3640 12:47:52.175138 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 12:47:52.178075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 12:47:52.178492 ==
3643 12:47:52.181793 RX Vref Scan: 0
3644 12:47:52.182209
3645 12:47:52.182541 RX Vref 0 -> 0, step: 1
3646 12:47:52.182847
3647 12:47:52.184990 RX Delay -21 -> 252, step: 4
3648 12:47:52.191675 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3649 12:47:52.195244 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3650 12:47:52.198615 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3651 12:47:52.201233 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3652 12:47:52.204681 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3653 12:47:52.211528 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3654 12:47:52.214875 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3655 12:47:52.217960 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3656 12:47:52.221104 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3657 12:47:52.224386 iDelay=199, Bit 9, Center 102 (39 ~ 166) 128
3658 12:47:52.230923 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3659 12:47:52.234260 iDelay=199, Bit 11, Center 102 (39 ~ 166) 128
3660 12:47:52.237966 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3661 12:47:52.241369 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3662 12:47:52.248127 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3663 12:47:52.251479 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3664 12:47:52.251898 ==
3665 12:47:52.254293 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 12:47:52.257443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 12:47:52.257867 ==
3668 12:47:52.258200 DQS Delay:
3669 12:47:52.260887 DQS0 = 0, DQS1 = 0
3670 12:47:52.261300 DQM Delay:
3671 12:47:52.264196 DQM0 = 118, DQM1 = 111
3672 12:47:52.264646 DQ Delay:
3673 12:47:52.268001 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3674 12:47:52.270816 DQ4 =116, DQ5 =128, DQ6 =132, DQ7 =116
3675 12:47:52.274168 DQ8 =100, DQ9 =102, DQ10 =110, DQ11 =102
3676 12:47:52.280952 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3677 12:47:52.281372
3678 12:47:52.281703
3679 12:47:52.287267 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3680 12:47:52.290780 CH1 RK1: MR19=303, MR18=F3EF
3681 12:47:52.296995 CH1_RK1: MR19=0x303, MR18=0xF3EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3682 12:47:52.300558 [RxdqsGatingPostProcess] freq 1200
3683 12:47:52.303881 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3684 12:47:52.306793 best DQS0 dly(2T, 0.5T) = (0, 11)
3685 12:47:52.310852 best DQS1 dly(2T, 0.5T) = (0, 11)
3686 12:47:52.313551 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3687 12:47:52.317007 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3688 12:47:52.320311 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 12:47:52.323444 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 12:47:52.327093 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 12:47:52.330695 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 12:47:52.333579 Pre-setting of DQS Precalculation
3693 12:47:52.336618 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3694 12:47:52.346372 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3695 12:47:52.353752 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3696 12:47:52.354178
3697 12:47:52.354513
3698 12:47:52.356285 [Calibration Summary] 2400 Mbps
3699 12:47:52.356789 CH 0, Rank 0
3700 12:47:52.359529 SW Impedance : PASS
3701 12:47:52.363794 DUTY Scan : NO K
3702 12:47:52.364319 ZQ Calibration : PASS
3703 12:47:52.366058 Jitter Meter : NO K
3704 12:47:52.369791 CBT Training : PASS
3705 12:47:52.370210 Write leveling : PASS
3706 12:47:52.372544 RX DQS gating : PASS
3707 12:47:52.372972 RX DQ/DQS(RDDQC) : PASS
3708 12:47:52.376179 TX DQ/DQS : PASS
3709 12:47:52.379967 RX DATLAT : PASS
3710 12:47:52.380387 RX DQ/DQS(Engine): PASS
3711 12:47:52.382790 TX OE : NO K
3712 12:47:52.383229 All Pass.
3713 12:47:52.383564
3714 12:47:52.386406 CH 0, Rank 1
3715 12:47:52.386825 SW Impedance : PASS
3716 12:47:52.389701 DUTY Scan : NO K
3717 12:47:52.392456 ZQ Calibration : PASS
3718 12:47:52.392916 Jitter Meter : NO K
3719 12:47:52.395772 CBT Training : PASS
3720 12:47:52.399504 Write leveling : PASS
3721 12:47:52.400000 RX DQS gating : PASS
3722 12:47:52.402616 RX DQ/DQS(RDDQC) : PASS
3723 12:47:52.405915 TX DQ/DQS : PASS
3724 12:47:52.406336 RX DATLAT : PASS
3725 12:47:52.409569 RX DQ/DQS(Engine): PASS
3726 12:47:52.412243 TX OE : NO K
3727 12:47:52.412701 All Pass.
3728 12:47:52.413042
3729 12:47:52.413353 CH 1, Rank 0
3730 12:47:52.415516 SW Impedance : PASS
3731 12:47:52.418802 DUTY Scan : NO K
3732 12:47:52.419221 ZQ Calibration : PASS
3733 12:47:52.422102 Jitter Meter : NO K
3734 12:47:52.425880 CBT Training : PASS
3735 12:47:52.426299 Write leveling : PASS
3736 12:47:52.428835 RX DQS gating : PASS
3737 12:47:52.432272 RX DQ/DQS(RDDQC) : PASS
3738 12:47:52.432819 TX DQ/DQS : PASS
3739 12:47:52.435674 RX DATLAT : PASS
3740 12:47:52.436091 RX DQ/DQS(Engine): PASS
3741 12:47:52.438865 TX OE : NO K
3742 12:47:52.439285 All Pass.
3743 12:47:52.439624
3744 12:47:52.442129 CH 1, Rank 1
3745 12:47:52.445673 SW Impedance : PASS
3746 12:47:52.446094 DUTY Scan : NO K
3747 12:47:52.448914 ZQ Calibration : PASS
3748 12:47:52.449331 Jitter Meter : NO K
3749 12:47:52.451894 CBT Training : PASS
3750 12:47:52.456061 Write leveling : PASS
3751 12:47:52.456479 RX DQS gating : PASS
3752 12:47:52.459101 RX DQ/DQS(RDDQC) : PASS
3753 12:47:52.461786 TX DQ/DQS : PASS
3754 12:47:52.462208 RX DATLAT : PASS
3755 12:47:52.465402 RX DQ/DQS(Engine): PASS
3756 12:47:52.468716 TX OE : NO K
3757 12:47:52.469168 All Pass.
3758 12:47:52.469552
3759 12:47:52.472172 DramC Write-DBI off
3760 12:47:52.472631 PER_BANK_REFRESH: Hybrid Mode
3761 12:47:52.475169 TX_TRACKING: ON
3762 12:47:52.481790 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3763 12:47:52.488284 [FAST_K] Save calibration result to emmc
3764 12:47:52.491664 dramc_set_vcore_voltage set vcore to 650000
3765 12:47:52.492089 Read voltage for 600, 5
3766 12:47:52.495227 Vio18 = 0
3767 12:47:52.495657 Vcore = 650000
3768 12:47:52.496079 Vdram = 0
3769 12:47:52.498240 Vddq = 0
3770 12:47:52.498784 Vmddr = 0
3771 12:47:52.501728 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3772 12:47:52.508733 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3773 12:47:52.511718 MEM_TYPE=3, freq_sel=19
3774 12:47:52.514922 sv_algorithm_assistance_LP4_1600
3775 12:47:52.517989 ============ PULL DRAM RESETB DOWN ============
3776 12:47:52.521537 ========== PULL DRAM RESETB DOWN end =========
3777 12:47:52.527944 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3778 12:47:52.532124 ===================================
3779 12:47:52.532718 LPDDR4 DRAM CONFIGURATION
3780 12:47:52.534525 ===================================
3781 12:47:52.537964 EX_ROW_EN[0] = 0x0
3782 12:47:52.538393 EX_ROW_EN[1] = 0x0
3783 12:47:52.541438 LP4Y_EN = 0x0
3784 12:47:52.544906 WORK_FSP = 0x0
3785 12:47:52.545330 WL = 0x2
3786 12:47:52.547905 RL = 0x2
3787 12:47:52.548329 BL = 0x2
3788 12:47:52.551125 RPST = 0x0
3789 12:47:52.551653 RD_PRE = 0x0
3790 12:47:52.554452 WR_PRE = 0x1
3791 12:47:52.554879 WR_PST = 0x0
3792 12:47:52.557878 DBI_WR = 0x0
3793 12:47:52.558303 DBI_RD = 0x0
3794 12:47:52.561921 OTF = 0x1
3795 12:47:52.564720 ===================================
3796 12:47:52.567455 ===================================
3797 12:47:52.567903 ANA top config
3798 12:47:52.571059 ===================================
3799 12:47:52.574307 DLL_ASYNC_EN = 0
3800 12:47:52.577478 ALL_SLAVE_EN = 1
3801 12:47:52.580945 NEW_RANK_MODE = 1
3802 12:47:52.581375 DLL_IDLE_MODE = 1
3803 12:47:52.583914 LP45_APHY_COMB_EN = 1
3804 12:47:52.587493 TX_ODT_DIS = 1
3805 12:47:52.590854 NEW_8X_MODE = 1
3806 12:47:52.594233 ===================================
3807 12:47:52.597291 ===================================
3808 12:47:52.600466 data_rate = 1200
3809 12:47:52.600956 CKR = 1
3810 12:47:52.603742 DQ_P2S_RATIO = 8
3811 12:47:52.607248 ===================================
3812 12:47:52.610615 CA_P2S_RATIO = 8
3813 12:47:52.613748 DQ_CA_OPEN = 0
3814 12:47:52.617247 DQ_SEMI_OPEN = 0
3815 12:47:52.620488 CA_SEMI_OPEN = 0
3816 12:47:52.621036 CA_FULL_RATE = 0
3817 12:47:52.623433 DQ_CKDIV4_EN = 1
3818 12:47:52.626892 CA_CKDIV4_EN = 1
3819 12:47:52.630116 CA_PREDIV_EN = 0
3820 12:47:52.633508 PH8_DLY = 0
3821 12:47:52.636842 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3822 12:47:52.637312 DQ_AAMCK_DIV = 4
3823 12:47:52.640036 CA_AAMCK_DIV = 4
3824 12:47:52.642964 CA_ADMCK_DIV = 4
3825 12:47:52.646345 DQ_TRACK_CA_EN = 0
3826 12:47:52.649718 CA_PICK = 600
3827 12:47:52.653403 CA_MCKIO = 600
3828 12:47:52.656638 MCKIO_SEMI = 0
3829 12:47:52.659813 PLL_FREQ = 2288
3830 12:47:52.660239 DQ_UI_PI_RATIO = 32
3831 12:47:52.662973 CA_UI_PI_RATIO = 0
3832 12:47:52.666408 ===================================
3833 12:47:52.669605 ===================================
3834 12:47:52.672946 memory_type:LPDDR4
3835 12:47:52.676438 GP_NUM : 10
3836 12:47:52.676910 SRAM_EN : 1
3837 12:47:52.679437 MD32_EN : 0
3838 12:47:52.682956 ===================================
3839 12:47:52.686031 [ANA_INIT] >>>>>>>>>>>>>>
3840 12:47:52.686455 <<<<<< [CONFIGURE PHASE]: ANA_TX
3841 12:47:52.689024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3842 12:47:52.692416 ===================================
3843 12:47:52.696151 data_rate = 1200,PCW = 0X5800
3844 12:47:52.698873 ===================================
3845 12:47:52.702493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3846 12:47:52.708998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 12:47:52.715696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 12:47:52.718868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3849 12:47:52.722054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3850 12:47:52.725525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3851 12:47:52.728974 [ANA_INIT] flow start
3852 12:47:52.729396 [ANA_INIT] PLL >>>>>>>>
3853 12:47:52.731884 [ANA_INIT] PLL <<<<<<<<
3854 12:47:52.735602 [ANA_INIT] MIDPI >>>>>>>>
3855 12:47:52.738429 [ANA_INIT] MIDPI <<<<<<<<
3856 12:47:52.738853 [ANA_INIT] DLL >>>>>>>>
3857 12:47:52.741710 [ANA_INIT] flow end
3858 12:47:52.745320 ============ LP4 DIFF to SE enter ============
3859 12:47:52.749115 ============ LP4 DIFF to SE exit ============
3860 12:47:52.751846 [ANA_INIT] <<<<<<<<<<<<<
3861 12:47:52.755053 [Flow] Enable top DCM control >>>>>
3862 12:47:52.758171 [Flow] Enable top DCM control <<<<<
3863 12:47:52.761626 Enable DLL master slave shuffle
3864 12:47:52.768209 ==============================================================
3865 12:47:52.768665 Gating Mode config
3866 12:47:52.774994 ==============================================================
3867 12:47:52.775423 Config description:
3868 12:47:52.784995 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3869 12:47:52.791615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3870 12:47:52.798696 SELPH_MODE 0: By rank 1: By Phase
3871 12:47:52.801464 ==============================================================
3872 12:47:52.804830 GAT_TRACK_EN = 1
3873 12:47:52.808008 RX_GATING_MODE = 2
3874 12:47:52.811360 RX_GATING_TRACK_MODE = 2
3875 12:47:52.814332 SELPH_MODE = 1
3876 12:47:52.817710 PICG_EARLY_EN = 1
3877 12:47:52.821357 VALID_LAT_VALUE = 1
3878 12:47:52.827825 ==============================================================
3879 12:47:52.831142 Enter into Gating configuration >>>>
3880 12:47:52.834488 Exit from Gating configuration <<<<
3881 12:47:52.837589 Enter into DVFS_PRE_config >>>>>
3882 12:47:52.847334 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3883 12:47:52.850967 Exit from DVFS_PRE_config <<<<<
3884 12:47:52.854094 Enter into PICG configuration >>>>
3885 12:47:52.857474 Exit from PICG configuration <<<<
3886 12:47:52.861161 [RX_INPUT] configuration >>>>>
3887 12:47:52.863972 [RX_INPUT] configuration <<<<<
3888 12:47:52.867646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3889 12:47:52.873886 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3890 12:47:52.881223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 12:47:52.883643 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 12:47:52.890965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3893 12:47:52.897079 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3894 12:47:52.900483 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3895 12:47:52.907260 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3896 12:47:52.910376 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3897 12:47:52.913482 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3898 12:47:52.917009 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3899 12:47:52.923857 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 12:47:52.926944 ===================================
3901 12:47:52.927375 LPDDR4 DRAM CONFIGURATION
3902 12:47:52.930426 ===================================
3903 12:47:52.934011 EX_ROW_EN[0] = 0x0
3904 12:47:52.937089 EX_ROW_EN[1] = 0x0
3905 12:47:52.937516 LP4Y_EN = 0x0
3906 12:47:52.940130 WORK_FSP = 0x0
3907 12:47:52.940590 WL = 0x2
3908 12:47:52.943511 RL = 0x2
3909 12:47:52.943931 BL = 0x2
3910 12:47:52.946816 RPST = 0x0
3911 12:47:52.947240 RD_PRE = 0x0
3912 12:47:52.949875 WR_PRE = 0x1
3913 12:47:52.950299 WR_PST = 0x0
3914 12:47:52.953591 DBI_WR = 0x0
3915 12:47:52.954017 DBI_RD = 0x0
3916 12:47:52.956875 OTF = 0x1
3917 12:47:52.959823 ===================================
3918 12:47:52.962927 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3919 12:47:52.966946 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3920 12:47:52.972953 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 12:47:52.976623 ===================================
3922 12:47:52.977103 LPDDR4 DRAM CONFIGURATION
3923 12:47:52.980267 ===================================
3924 12:47:52.983154 EX_ROW_EN[0] = 0x10
3925 12:47:52.986689 EX_ROW_EN[1] = 0x0
3926 12:47:52.987122 LP4Y_EN = 0x0
3927 12:47:52.989913 WORK_FSP = 0x0
3928 12:47:52.990337 WL = 0x2
3929 12:47:52.992937 RL = 0x2
3930 12:47:52.993360 BL = 0x2
3931 12:47:52.996005 RPST = 0x0
3932 12:47:52.996427 RD_PRE = 0x0
3933 12:47:52.999968 WR_PRE = 0x1
3934 12:47:53.000651 WR_PST = 0x0
3935 12:47:53.002653 DBI_WR = 0x0
3936 12:47:53.003079 DBI_RD = 0x0
3937 12:47:53.005886 OTF = 0x1
3938 12:47:53.009430 ===================================
3939 12:47:53.016170 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3940 12:47:53.019098 nWR fixed to 30
3941 12:47:53.022581 [ModeRegInit_LP4] CH0 RK0
3942 12:47:53.023109 [ModeRegInit_LP4] CH0 RK1
3943 12:47:53.025899 [ModeRegInit_LP4] CH1 RK0
3944 12:47:53.029214 [ModeRegInit_LP4] CH1 RK1
3945 12:47:53.029637 match AC timing 17
3946 12:47:53.035799 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3947 12:47:53.038866 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3948 12:47:53.042347 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3949 12:47:53.048889 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3950 12:47:53.052186 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3951 12:47:53.052747 ==
3952 12:47:53.055482 Dram Type= 6, Freq= 0, CH_0, rank 0
3953 12:47:53.059447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3954 12:47:53.059872 ==
3955 12:47:53.065350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3956 12:47:53.072268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3957 12:47:53.075142 [CA 0] Center 36 (6~66) winsize 61
3958 12:47:53.078857 [CA 1] Center 36 (6~66) winsize 61
3959 12:47:53.082038 [CA 2] Center 34 (4~65) winsize 62
3960 12:47:53.085676 [CA 3] Center 34 (4~65) winsize 62
3961 12:47:53.088870 [CA 4] Center 33 (3~64) winsize 62
3962 12:47:53.091827 [CA 5] Center 33 (3~64) winsize 62
3963 12:47:53.092260
3964 12:47:53.095344 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3965 12:47:53.095919
3966 12:47:53.098613 [CATrainingPosCal] consider 1 rank data
3967 12:47:53.101768 u2DelayCellTimex100 = 270/100 ps
3968 12:47:53.104802 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 12:47:53.108140 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3970 12:47:53.111659 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 12:47:53.115728 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 12:47:53.121252 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 12:47:53.124949 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3974 12:47:53.125376
3975 12:47:53.128216 CA PerBit enable=1, Macro0, CA PI delay=33
3976 12:47:53.128670
3977 12:47:53.131143 [CBTSetCACLKResult] CA Dly = 33
3978 12:47:53.131568 CS Dly: 5 (0~36)
3979 12:47:53.131905 ==
3980 12:47:53.134735 Dram Type= 6, Freq= 0, CH_0, rank 1
3981 12:47:53.140970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 12:47:53.141400 ==
3983 12:47:53.144685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3984 12:47:53.151436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3985 12:47:53.153996 [CA 0] Center 36 (6~66) winsize 61
3986 12:47:53.157575 [CA 1] Center 36 (6~66) winsize 61
3987 12:47:53.161166 [CA 2] Center 34 (4~65) winsize 62
3988 12:47:53.164498 [CA 3] Center 34 (4~64) winsize 61
3989 12:47:53.168069 [CA 4] Center 33 (2~64) winsize 63
3990 12:47:53.170829 [CA 5] Center 33 (2~64) winsize 63
3991 12:47:53.171290
3992 12:47:53.174316 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3993 12:47:53.174752
3994 12:47:53.177809 [CATrainingPosCal] consider 2 rank data
3995 12:47:53.180794 u2DelayCellTimex100 = 270/100 ps
3996 12:47:53.183857 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3997 12:47:53.190477 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3998 12:47:53.194128 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3999 12:47:53.197165 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4000 12:47:53.200596 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 12:47:53.203684 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4002 12:47:53.204110
4003 12:47:53.207405 CA PerBit enable=1, Macro0, CA PI delay=33
4004 12:47:53.207829
4005 12:47:53.210072 [CBTSetCACLKResult] CA Dly = 33
4006 12:47:53.213644 CS Dly: 5 (0~36)
4007 12:47:53.214173
4008 12:47:53.217013 ----->DramcWriteLeveling(PI) begin...
4009 12:47:53.217438 ==
4010 12:47:53.219968 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 12:47:53.223737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 12:47:53.224258 ==
4013 12:47:53.226962 Write leveling (Byte 0): 34 => 34
4014 12:47:53.230090 Write leveling (Byte 1): 30 => 30
4015 12:47:53.233457 DramcWriteLeveling(PI) end<-----
4016 12:47:53.233879
4017 12:47:53.234296 ==
4018 12:47:53.236703 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 12:47:53.240061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 12:47:53.240544 ==
4021 12:47:53.243185 [Gating] SW mode calibration
4022 12:47:53.250309 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4023 12:47:53.256179 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4024 12:47:53.260024 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 12:47:53.262899 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 12:47:53.269619 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 12:47:53.272825 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4028 12:47:53.276105 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (1 1) (1 1)
4029 12:47:53.283580 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 12:47:53.286152 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 12:47:53.289755 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 12:47:53.295873 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 12:47:53.299218 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 12:47:53.303036 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 12:47:53.309190 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 12:47:53.312495 0 10 16 | B1->B0 | 3434 4040 | 1 1 | (0 0) (0 0)
4037 12:47:53.315520 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 12:47:53.322225 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 12:47:53.325481 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 12:47:53.332068 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 12:47:53.336028 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 12:47:53.338896 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 12:47:53.345210 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 12:47:53.348422 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4045 12:47:53.351758 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 12:47:53.358371 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:47:53.361477 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 12:47:53.364506 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 12:47:53.371482 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 12:47:53.374649 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:47:53.378172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:47:53.384486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:47:53.387847 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 12:47:53.391119 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:47:53.397429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 12:47:53.400995 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:47:53.404650 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:47:53.411309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:47:53.414871 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4060 12:47:53.417456 Total UI for P1: 0, mck2ui 16
4061 12:47:53.420906 best dqsien dly found for B0: ( 0, 13, 10)
4062 12:47:53.424186 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4063 12:47:53.427608 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 12:47:53.431224 Total UI for P1: 0, mck2ui 16
4065 12:47:53.434191 best dqsien dly found for B1: ( 0, 13, 14)
4066 12:47:53.440850 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4067 12:47:53.444029 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4068 12:47:53.444464
4069 12:47:53.447754 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4070 12:47:53.450482 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4071 12:47:53.454552 [Gating] SW calibration Done
4072 12:47:53.454923 ==
4073 12:47:53.457352 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 12:47:53.460309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 12:47:53.460844 ==
4076 12:47:53.464010 RX Vref Scan: 0
4077 12:47:53.464554
4078 12:47:53.464922 RX Vref 0 -> 0, step: 1
4079 12:47:53.465247
4080 12:47:53.467285 RX Delay -230 -> 252, step: 16
4081 12:47:53.473856 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4082 12:47:53.476869 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4083 12:47:53.480104 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4084 12:47:53.483473 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4085 12:47:53.486768 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4086 12:47:53.493590 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4087 12:47:53.496585 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4088 12:47:53.499869 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4089 12:47:53.503498 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4090 12:47:53.509898 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4091 12:47:53.513054 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4092 12:47:53.516501 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4093 12:47:53.519998 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4094 12:47:53.526270 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4095 12:47:53.529693 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4096 12:47:53.533408 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4097 12:47:53.533829 ==
4098 12:47:53.536295 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 12:47:53.539589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 12:47:53.542805 ==
4101 12:47:53.543219 DQS Delay:
4102 12:47:53.543629 DQS0 = 0, DQS1 = 0
4103 12:47:53.545970 DQM Delay:
4104 12:47:53.546387 DQM0 = 40, DQM1 = 30
4105 12:47:53.549451 DQ Delay:
4106 12:47:53.552952 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4107 12:47:53.553371 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4108 12:47:53.556249 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4109 12:47:53.562507 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4110 12:47:53.563022
4111 12:47:53.563360
4112 12:47:53.563666 ==
4113 12:47:53.565789 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 12:47:53.569206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 12:47:53.569750 ==
4116 12:47:53.570132
4117 12:47:53.570443
4118 12:47:53.572350 TX Vref Scan disable
4119 12:47:53.572844 == TX Byte 0 ==
4120 12:47:53.579904 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4121 12:47:53.582752 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4122 12:47:53.583184 == TX Byte 1 ==
4123 12:47:53.589085 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4124 12:47:53.592486 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4125 12:47:53.593034 ==
4126 12:47:53.595560 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 12:47:53.599010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 12:47:53.599538 ==
4129 12:47:53.602223
4130 12:47:53.602637
4131 12:47:53.602967 TX Vref Scan disable
4132 12:47:53.605668 == TX Byte 0 ==
4133 12:47:53.608910 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4134 12:47:53.615612 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4135 12:47:53.616178 == TX Byte 1 ==
4136 12:47:53.618849 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4137 12:47:53.625260 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4138 12:47:53.625682
4139 12:47:53.626040 [DATLAT]
4140 12:47:53.626359 Freq=600, CH0 RK0
4141 12:47:53.626665
4142 12:47:53.628756 DATLAT Default: 0x9
4143 12:47:53.629174 0, 0xFFFF, sum = 0
4144 12:47:53.633031 1, 0xFFFF, sum = 0
4145 12:47:53.635730 2, 0xFFFF, sum = 0
4146 12:47:53.636156 3, 0xFFFF, sum = 0
4147 12:47:53.639009 4, 0xFFFF, sum = 0
4148 12:47:53.639432 5, 0xFFFF, sum = 0
4149 12:47:53.642483 6, 0xFFFF, sum = 0
4150 12:47:53.642908 7, 0xFFFF, sum = 0
4151 12:47:53.645516 8, 0x0, sum = 1
4152 12:47:53.645945 9, 0x0, sum = 2
4153 12:47:53.648503 10, 0x0, sum = 3
4154 12:47:53.649229 11, 0x0, sum = 4
4155 12:47:53.649570 best_step = 9
4156 12:47:53.649880
4157 12:47:53.652124 ==
4158 12:47:53.655204 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 12:47:53.658727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 12:47:53.659149 ==
4161 12:47:53.659485 RX Vref Scan: 1
4162 12:47:53.659796
4163 12:47:53.661725 RX Vref 0 -> 0, step: 1
4164 12:47:53.662236
4165 12:47:53.664929 RX Delay -195 -> 252, step: 8
4166 12:47:53.665356
4167 12:47:53.668264 Set Vref, RX VrefLevel [Byte0]: 60
4168 12:47:53.671547 [Byte1]: 54
4169 12:47:53.671976
4170 12:47:53.675319 Final RX Vref Byte 0 = 60 to rank0
4171 12:47:53.678409 Final RX Vref Byte 1 = 54 to rank0
4172 12:47:53.681885 Final RX Vref Byte 0 = 60 to rank1
4173 12:47:53.684958 Final RX Vref Byte 1 = 54 to rank1==
4174 12:47:53.688549 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 12:47:53.691525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 12:47:53.694671 ==
4177 12:47:53.695091 DQS Delay:
4178 12:47:53.695427 DQS0 = 0, DQS1 = 0
4179 12:47:53.697981 DQM Delay:
4180 12:47:53.698402 DQM0 = 43, DQM1 = 33
4181 12:47:53.701262 DQ Delay:
4182 12:47:53.704750 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4183 12:47:53.705303 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4184 12:47:53.708316 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4185 12:47:53.714460 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4186 12:47:53.714883
4187 12:47:53.715220
4188 12:47:53.721242 [DQSOSCAuto] RK0, (LSB)MR18= 0x653e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4189 12:47:53.724796 CH0 RK0: MR19=808, MR18=653E
4190 12:47:53.730781 CH0_RK0: MR19=0x808, MR18=0x653E, DQSOSC=390, MR23=63, INC=172, DEC=114
4191 12:47:53.731254
4192 12:47:53.734000 ----->DramcWriteLeveling(PI) begin...
4193 12:47:53.734429 ==
4194 12:47:53.737417 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 12:47:53.741122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 12:47:53.741814 ==
4197 12:47:53.744376 Write leveling (Byte 0): 31 => 31
4198 12:47:53.747170 Write leveling (Byte 1): 31 => 31
4199 12:47:53.750786 DramcWriteLeveling(PI) end<-----
4200 12:47:53.751210
4201 12:47:53.751547 ==
4202 12:47:53.754146 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 12:47:53.757184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 12:47:53.757711 ==
4205 12:47:53.760555 [Gating] SW mode calibration
4206 12:47:53.767307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4207 12:47:53.773963 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4208 12:47:53.777248 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 12:47:53.783725 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 12:47:53.786910 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 12:47:53.790248 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 12:47:53.796871 0 9 16 | B1->B0 | 2e2e 2c2c | 0 0 | (0 0) (0 0)
4213 12:47:53.800364 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 12:47:53.803938 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 12:47:53.810148 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 12:47:53.813630 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 12:47:53.816635 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 12:47:53.823091 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 12:47:53.826731 0 10 12 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4220 12:47:53.829907 0 10 16 | B1->B0 | 3c3c 3f3f | 0 0 | (1 1) (1 1)
4221 12:47:53.836477 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 12:47:53.839418 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 12:47:53.843738 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 12:47:53.849529 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 12:47:53.853145 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 12:47:53.856134 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 12:47:53.862830 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 12:47:53.866315 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4229 12:47:53.869380 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 12:47:53.876304 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 12:47:53.879306 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 12:47:53.882530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 12:47:53.889398 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 12:47:53.892497 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 12:47:53.895740 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 12:47:53.902307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 12:47:53.905742 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 12:47:53.908855 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 12:47:53.916176 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 12:47:53.919144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 12:47:53.922335 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 12:47:53.928916 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:47:53.932246 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4244 12:47:53.935649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4245 12:47:53.938538 Total UI for P1: 0, mck2ui 16
4246 12:47:53.941857 best dqsien dly found for B0: ( 0, 13, 12)
4247 12:47:53.948486 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 12:47:53.948992 Total UI for P1: 0, mck2ui 16
4249 12:47:53.955068 best dqsien dly found for B1: ( 0, 13, 16)
4250 12:47:53.958402 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4251 12:47:53.961502 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4252 12:47:53.961921
4253 12:47:53.964640 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4254 12:47:53.968177 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4255 12:47:53.971185 [Gating] SW calibration Done
4256 12:47:53.971606 ==
4257 12:47:53.975323 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 12:47:53.978078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 12:47:53.978591 ==
4260 12:47:53.981677 RX Vref Scan: 0
4261 12:47:53.982151
4262 12:47:53.982492 RX Vref 0 -> 0, step: 1
4263 12:47:53.984691
4264 12:47:53.985109 RX Delay -230 -> 252, step: 16
4265 12:47:53.991486 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4266 12:47:53.994319 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4267 12:47:53.997720 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4268 12:47:54.001763 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4269 12:47:54.007612 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4270 12:47:54.011377 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4271 12:47:54.014641 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4272 12:47:54.017663 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4273 12:47:54.020791 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4274 12:47:54.027926 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4275 12:47:54.030812 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4276 12:47:54.033942 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4277 12:47:54.037939 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4278 12:47:54.044346 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4279 12:47:54.047470 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4280 12:47:54.051070 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4281 12:47:54.051544 ==
4282 12:47:54.054478 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 12:47:54.061255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 12:47:54.061783 ==
4285 12:47:54.062130 DQS Delay:
4286 12:47:54.064353 DQS0 = 0, DQS1 = 0
4287 12:47:54.064941 DQM Delay:
4288 12:47:54.065285 DQM0 = 44, DQM1 = 36
4289 12:47:54.067623 DQ Delay:
4290 12:47:54.070434 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4291 12:47:54.073766 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4292 12:47:54.077097 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4293 12:47:54.080143 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4294 12:47:54.080653
4295 12:47:54.081024
4296 12:47:54.081331 ==
4297 12:47:54.083604 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 12:47:54.086739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 12:47:54.087160 ==
4300 12:47:54.087490
4301 12:47:54.087798
4302 12:47:54.089846 TX Vref Scan disable
4303 12:47:54.093612 == TX Byte 0 ==
4304 12:47:54.096431 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4305 12:47:54.099750 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4306 12:47:54.103583 == TX Byte 1 ==
4307 12:47:54.107857 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4308 12:47:54.109697 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4309 12:47:54.109948 ==
4310 12:47:54.112740 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 12:47:54.116669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 12:47:54.119700 ==
4313 12:47:54.119922
4314 12:47:54.120099
4315 12:47:54.120263 TX Vref Scan disable
4316 12:47:54.123614 == TX Byte 0 ==
4317 12:47:54.127018 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4318 12:47:54.133475 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4319 12:47:54.133872 == TX Byte 1 ==
4320 12:47:54.136826 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4321 12:47:54.143425 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4322 12:47:54.144075
4323 12:47:54.144620 [DATLAT]
4324 12:47:54.145072 Freq=600, CH0 RK1
4325 12:47:54.145465
4326 12:47:54.146609 DATLAT Default: 0x9
4327 12:47:54.149695 0, 0xFFFF, sum = 0
4328 12:47:54.150111 1, 0xFFFF, sum = 0
4329 12:47:54.153145 2, 0xFFFF, sum = 0
4330 12:47:54.153560 3, 0xFFFF, sum = 0
4331 12:47:54.156679 4, 0xFFFF, sum = 0
4332 12:47:54.157150 5, 0xFFFF, sum = 0
4333 12:47:54.159647 6, 0xFFFF, sum = 0
4334 12:47:54.160238 7, 0xFFFF, sum = 0
4335 12:47:54.163174 8, 0x0, sum = 1
4336 12:47:54.163731 9, 0x0, sum = 2
4337 12:47:54.166812 10, 0x0, sum = 3
4338 12:47:54.167228 11, 0x0, sum = 4
4339 12:47:54.167558 best_step = 9
4340 12:47:54.167857
4341 12:47:54.170097 ==
4342 12:47:54.172758 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 12:47:54.176249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 12:47:54.176862 ==
4345 12:47:54.177351 RX Vref Scan: 0
4346 12:47:54.177833
4347 12:47:54.179572 RX Vref 0 -> 0, step: 1
4348 12:47:54.180111
4349 12:47:54.182870 RX Delay -195 -> 252, step: 8
4350 12:47:54.190094 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4351 12:47:54.193145 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4352 12:47:54.195875 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4353 12:47:54.199220 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4354 12:47:54.202899 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4355 12:47:54.209978 iDelay=205, Bit 5, Center 36 (-115 ~ 188) 304
4356 12:47:54.212739 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4357 12:47:54.216709 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4358 12:47:54.220078 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4359 12:47:54.225685 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4360 12:47:54.228925 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4361 12:47:54.232318 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4362 12:47:54.235430 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4363 12:47:54.242225 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4364 12:47:54.245438 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4365 12:47:54.249090 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4366 12:47:54.249505 ==
4367 12:47:54.252734 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 12:47:54.255499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 12:47:54.255982 ==
4370 12:47:54.258637 DQS Delay:
4371 12:47:54.259056 DQS0 = 0, DQS1 = 0
4372 12:47:54.262296 DQM Delay:
4373 12:47:54.262719 DQM0 = 42, DQM1 = 36
4374 12:47:54.263057 DQ Delay:
4375 12:47:54.265417 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4376 12:47:54.268766 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4377 12:47:54.271851 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4378 12:47:54.275316 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4379 12:47:54.275845
4380 12:47:54.278602
4381 12:47:54.285242 [DQSOSCAuto] RK1, (LSB)MR18= 0x6014, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4382 12:47:54.288727 CH0 RK1: MR19=808, MR18=6014
4383 12:47:54.294892 CH0_RK1: MR19=0x808, MR18=0x6014, DQSOSC=391, MR23=63, INC=171, DEC=114
4384 12:47:54.298589 [RxdqsGatingPostProcess] freq 600
4385 12:47:54.301527 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4386 12:47:54.304906 Pre-setting of DQS Precalculation
4387 12:47:54.311850 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4388 12:47:54.312379 ==
4389 12:47:54.315403 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 12:47:54.317929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 12:47:54.318359 ==
4392 12:47:54.324914 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4393 12:47:54.328286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4394 12:47:54.332732 [CA 0] Center 35 (5~66) winsize 62
4395 12:47:54.335827 [CA 1] Center 36 (6~66) winsize 61
4396 12:47:54.339250 [CA 2] Center 34 (4~65) winsize 62
4397 12:47:54.342978 [CA 3] Center 33 (3~64) winsize 62
4398 12:47:54.345734 [CA 4] Center 34 (4~65) winsize 62
4399 12:47:54.348983 [CA 5] Center 33 (3~64) winsize 62
4400 12:47:54.349455
4401 12:47:54.351977 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4402 12:47:54.352405
4403 12:47:54.355486 [CATrainingPosCal] consider 1 rank data
4404 12:47:54.358729 u2DelayCellTimex100 = 270/100 ps
4405 12:47:54.361844 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4406 12:47:54.368570 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 12:47:54.372237 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 12:47:54.375270 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 12:47:54.378243 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4410 12:47:54.381916 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 12:47:54.382366
4412 12:47:54.384892 CA PerBit enable=1, Macro0, CA PI delay=33
4413 12:47:54.385330
4414 12:47:54.388814 [CBTSetCACLKResult] CA Dly = 33
4415 12:47:54.391855 CS Dly: 4 (0~35)
4416 12:47:54.392276 ==
4417 12:47:54.394945 Dram Type= 6, Freq= 0, CH_1, rank 1
4418 12:47:54.398418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 12:47:54.398938 ==
4420 12:47:54.405184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4421 12:47:54.407896 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4422 12:47:54.412614 [CA 0] Center 35 (5~66) winsize 62
4423 12:47:54.415650 [CA 1] Center 36 (6~66) winsize 61
4424 12:47:54.419117 [CA 2] Center 34 (4~65) winsize 62
4425 12:47:54.422421 [CA 3] Center 34 (4~65) winsize 62
4426 12:47:54.425930 [CA 4] Center 34 (4~65) winsize 62
4427 12:47:54.429253 [CA 5] Center 34 (3~65) winsize 63
4428 12:47:54.429678
4429 12:47:54.432544 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4430 12:47:54.432971
4431 12:47:54.435968 [CATrainingPosCal] consider 2 rank data
4432 12:47:54.438939 u2DelayCellTimex100 = 270/100 ps
4433 12:47:54.442350 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4434 12:47:54.449059 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4435 12:47:54.451813 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 12:47:54.455162 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4437 12:47:54.459145 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 12:47:54.462083 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 12:47:54.462607
4440 12:47:54.465010 CA PerBit enable=1, Macro0, CA PI delay=33
4441 12:47:54.465660
4442 12:47:54.468583 [CBTSetCACLKResult] CA Dly = 33
4443 12:47:54.471546 CS Dly: 5 (0~37)
4444 12:47:54.471970
4445 12:47:54.475474 ----->DramcWriteLeveling(PI) begin...
4446 12:47:54.475904 ==
4447 12:47:54.478783 Dram Type= 6, Freq= 0, CH_1, rank 0
4448 12:47:54.481961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 12:47:54.482393 ==
4450 12:47:54.485002 Write leveling (Byte 0): 28 => 28
4451 12:47:54.488468 Write leveling (Byte 1): 31 => 31
4452 12:47:54.491258 DramcWriteLeveling(PI) end<-----
4453 12:47:54.491683
4454 12:47:54.492020 ==
4455 12:47:54.494920 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 12:47:54.498041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 12:47:54.498472 ==
4458 12:47:54.501804 [Gating] SW mode calibration
4459 12:47:54.507775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4460 12:47:54.514539 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4461 12:47:54.518555 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4462 12:47:54.521921 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 12:47:54.528033 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4464 12:47:54.531252 0 9 12 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (1 1)
4465 12:47:54.534439 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 12:47:54.541248 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 12:47:54.544677 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 12:47:54.547383 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 12:47:54.554338 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 12:47:54.557890 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 12:47:54.561613 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 12:47:54.567147 0 10 12 | B1->B0 | 2d2d 3737 | 0 0 | (1 1) (0 0)
4473 12:47:54.570463 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4474 12:47:54.573983 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 12:47:54.580752 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 12:47:54.584251 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 12:47:54.587658 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 12:47:54.593829 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 12:47:54.596868 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 12:47:54.600409 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4481 12:47:54.607064 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:47:54.610397 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 12:47:54.613514 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:47:54.619949 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:47:54.624076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 12:47:54.626726 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:47:54.633403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:47:54.636475 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:47:54.639894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:47:54.646559 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:47:54.649736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 12:47:54.653234 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:47:54.659719 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:47:54.663399 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:47:54.666451 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:47:54.673348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4497 12:47:54.676547 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 12:47:54.679861 Total UI for P1: 0, mck2ui 16
4499 12:47:54.682809 best dqsien dly found for B0: ( 0, 13, 12)
4500 12:47:54.686155 Total UI for P1: 0, mck2ui 16
4501 12:47:54.689595 best dqsien dly found for B1: ( 0, 13, 14)
4502 12:47:54.692677 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4503 12:47:54.696119 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4504 12:47:54.696580
4505 12:47:54.699586 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4506 12:47:54.702827 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4507 12:47:54.706200 [Gating] SW calibration Done
4508 12:47:54.706623 ==
4509 12:47:54.709663 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 12:47:54.715804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 12:47:54.716333 ==
4512 12:47:54.716741 RX Vref Scan: 0
4513 12:47:54.717110
4514 12:47:54.719361 RX Vref 0 -> 0, step: 1
4515 12:47:54.719796
4516 12:47:54.722437 RX Delay -230 -> 252, step: 16
4517 12:47:54.726078 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4518 12:47:54.729086 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4519 12:47:54.735474 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4520 12:47:54.739449 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4521 12:47:54.742386 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4522 12:47:54.745376 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4523 12:47:54.748582 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4524 12:47:54.755561 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4525 12:47:54.758864 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4526 12:47:54.762457 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4527 12:47:54.765256 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4528 12:47:54.772059 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4529 12:47:54.775024 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4530 12:47:54.778130 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4531 12:47:54.781702 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4532 12:47:54.787960 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4533 12:47:54.788392 ==
4534 12:47:54.791603 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 12:47:54.794741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 12:47:54.795211 ==
4537 12:47:54.795683 DQS Delay:
4538 12:47:54.798203 DQS0 = 0, DQS1 = 0
4539 12:47:54.798633 DQM Delay:
4540 12:47:54.801082 DQM0 = 46, DQM1 = 37
4541 12:47:54.801522 DQ Delay:
4542 12:47:54.804778 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4543 12:47:54.807914 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4544 12:47:54.811073 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4545 12:47:54.814637 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4546 12:47:54.815063
4547 12:47:54.815399
4548 12:47:54.815708 ==
4549 12:47:54.817659 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 12:47:54.824500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 12:47:54.824963 ==
4552 12:47:54.825298
4553 12:47:54.825639
4554 12:47:54.825946 TX Vref Scan disable
4555 12:47:54.827708 == TX Byte 0 ==
4556 12:47:54.830986 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4557 12:47:54.838298 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4558 12:47:54.838868 == TX Byte 1 ==
4559 12:47:54.840630 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4560 12:47:54.847436 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4561 12:47:54.847857 ==
4562 12:47:54.850574 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 12:47:54.854193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 12:47:54.854617 ==
4565 12:47:54.854950
4566 12:47:54.855260
4567 12:47:54.857394 TX Vref Scan disable
4568 12:47:54.860570 == TX Byte 0 ==
4569 12:47:54.863872 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4570 12:47:54.867164 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4571 12:47:54.870492 == TX Byte 1 ==
4572 12:47:54.874085 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4573 12:47:54.877469 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4574 12:47:54.877887
4575 12:47:54.880302 [DATLAT]
4576 12:47:54.880762 Freq=600, CH1 RK0
4577 12:47:54.881104
4578 12:47:54.883760 DATLAT Default: 0x9
4579 12:47:54.884178 0, 0xFFFF, sum = 0
4580 12:47:54.886522 1, 0xFFFF, sum = 0
4581 12:47:54.886947 2, 0xFFFF, sum = 0
4582 12:47:54.889755 3, 0xFFFF, sum = 0
4583 12:47:54.890200 4, 0xFFFF, sum = 0
4584 12:47:54.893394 5, 0xFFFF, sum = 0
4585 12:47:54.893819 6, 0xFFFF, sum = 0
4586 12:47:54.896558 7, 0xFFFF, sum = 0
4587 12:47:54.896987 8, 0x0, sum = 1
4588 12:47:54.900011 9, 0x0, sum = 2
4589 12:47:54.900595 10, 0x0, sum = 3
4590 12:47:54.903192 11, 0x0, sum = 4
4591 12:47:54.903618 best_step = 9
4592 12:47:54.903951
4593 12:47:54.904259 ==
4594 12:47:54.906395 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 12:47:54.912965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 12:47:54.913388 ==
4597 12:47:54.913754 RX Vref Scan: 1
4598 12:47:54.914090
4599 12:47:54.915928 RX Vref 0 -> 0, step: 1
4600 12:47:54.916347
4601 12:47:54.919136 RX Delay -195 -> 252, step: 8
4602 12:47:54.919580
4603 12:47:54.922406 Set Vref, RX VrefLevel [Byte0]: 50
4604 12:47:54.926269 [Byte1]: 54
4605 12:47:54.926688
4606 12:47:54.929658 Final RX Vref Byte 0 = 50 to rank0
4607 12:47:54.932647 Final RX Vref Byte 1 = 54 to rank0
4608 12:47:54.935905 Final RX Vref Byte 0 = 50 to rank1
4609 12:47:54.939175 Final RX Vref Byte 1 = 54 to rank1==
4610 12:47:54.942311 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 12:47:54.945918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 12:47:54.946343 ==
4613 12:47:54.949144 DQS Delay:
4614 12:47:54.949581 DQS0 = 0, DQS1 = 0
4615 12:47:54.952121 DQM Delay:
4616 12:47:54.952583 DQM0 = 47, DQM1 = 38
4617 12:47:54.952938 DQ Delay:
4618 12:47:54.955820 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4619 12:47:54.959503 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4620 12:47:54.962312 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4621 12:47:54.965582 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4622 12:47:54.966025
4623 12:47:54.966400
4624 12:47:54.976256 [DQSOSCAuto] RK0, (LSB)MR18= 0x5034, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4625 12:47:54.978826 CH1 RK0: MR19=808, MR18=5034
4626 12:47:54.985574 CH1_RK0: MR19=0x808, MR18=0x5034, DQSOSC=394, MR23=63, INC=168, DEC=112
4627 12:47:54.986092
4628 12:47:54.988992 ----->DramcWriteLeveling(PI) begin...
4629 12:47:54.989482 ==
4630 12:47:54.992101 Dram Type= 6, Freq= 0, CH_1, rank 1
4631 12:47:54.995276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 12:47:54.995716 ==
4633 12:47:54.998904 Write leveling (Byte 0): 30 => 30
4634 12:47:55.002001 Write leveling (Byte 1): 30 => 30
4635 12:47:55.004936 DramcWriteLeveling(PI) end<-----
4636 12:47:55.005372
4637 12:47:55.005811 ==
4638 12:47:55.008179 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 12:47:55.011913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 12:47:55.012352 ==
4641 12:47:55.015219 [Gating] SW mode calibration
4642 12:47:55.021975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4643 12:47:55.027992 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4644 12:47:55.031414 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 12:47:55.034779 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 12:47:55.041276 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 12:47:55.044650 0 9 12 | B1->B0 | 3030 3333 | 1 0 | (1 0) (0 1)
4648 12:47:55.047839 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4649 12:47:55.054617 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 12:47:55.058176 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 12:47:55.060836 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 12:47:55.067440 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 12:47:55.070965 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 12:47:55.074473 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 12:47:55.080714 0 10 12 | B1->B0 | 3838 2d2d | 0 0 | (0 0) (1 1)
4656 12:47:55.084291 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4657 12:47:55.087420 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 12:47:55.094023 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 12:47:55.097182 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 12:47:55.100957 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 12:47:55.107101 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 12:47:55.111288 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 12:47:55.113674 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4664 12:47:55.121111 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:47:55.124337 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 12:47:55.127869 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 12:47:55.133763 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 12:47:55.137092 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 12:47:55.140290 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 12:47:55.147067 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 12:47:55.150326 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:47:55.153443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:47:55.159830 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 12:47:55.163132 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 12:47:55.166571 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 12:47:55.173486 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:47:55.176628 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:47:55.180225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:47:55.186353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:47:55.190160 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 12:47:55.193207 Total UI for P1: 0, mck2ui 16
4682 12:47:55.196616 best dqsien dly found for B0: ( 0, 13, 14)
4683 12:47:55.199459 Total UI for P1: 0, mck2ui 16
4684 12:47:55.202858 best dqsien dly found for B1: ( 0, 13, 14)
4685 12:47:55.206278 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4686 12:47:55.209588 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4687 12:47:55.210011
4688 12:47:55.212887 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4689 12:47:55.216851 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4690 12:47:55.220076 [Gating] SW calibration Done
4691 12:47:55.220506 ==
4692 12:47:55.222628 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 12:47:55.229877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 12:47:55.230407 ==
4695 12:47:55.230748 RX Vref Scan: 0
4696 12:47:55.231062
4697 12:47:55.233395 RX Vref 0 -> 0, step: 1
4698 12:47:55.233916
4699 12:47:55.235767 RX Delay -230 -> 252, step: 16
4700 12:47:55.239600 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4701 12:47:55.242222 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4702 12:47:55.249309 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4703 12:47:55.252377 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4704 12:47:55.256065 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4705 12:47:55.259200 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4706 12:47:55.262548 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4707 12:47:55.269185 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4708 12:47:55.271986 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4709 12:47:55.275187 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4710 12:47:55.278317 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4711 12:47:55.285420 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4712 12:47:55.288558 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4713 12:47:55.291861 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4714 12:47:55.294987 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4715 12:47:55.301740 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4716 12:47:55.302338 ==
4717 12:47:55.304967 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 12:47:55.308424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 12:47:55.308824 ==
4720 12:47:55.309172 DQS Delay:
4721 12:47:55.311246 DQS0 = 0, DQS1 = 0
4722 12:47:55.311489 DQM Delay:
4723 12:47:55.314532 DQM0 = 42, DQM1 = 36
4724 12:47:55.314833 DQ Delay:
4725 12:47:55.317924 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4726 12:47:55.321615 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =41
4727 12:47:55.324499 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4728 12:47:55.327898 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4729 12:47:55.328104
4730 12:47:55.328289
4731 12:47:55.328465 ==
4732 12:47:55.331356 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 12:47:55.334807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 12:47:55.338056 ==
4735 12:47:55.338256
4736 12:47:55.338441
4737 12:47:55.338623 TX Vref Scan disable
4738 12:47:55.341345 == TX Byte 0 ==
4739 12:47:55.344460 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4740 12:47:55.347911 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4741 12:47:55.350883 == TX Byte 1 ==
4742 12:47:55.354200 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4743 12:47:55.358026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4744 12:47:55.361188 ==
4745 12:47:55.364287 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 12:47:55.367707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 12:47:55.367900 ==
4748 12:47:55.368064
4749 12:47:55.368288
4750 12:47:55.371260 TX Vref Scan disable
4751 12:47:55.371451 == TX Byte 0 ==
4752 12:47:55.377229 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4753 12:47:55.381472 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4754 12:47:55.384233 == TX Byte 1 ==
4755 12:47:55.387351 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4756 12:47:55.391224 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4757 12:47:55.391475
4758 12:47:55.391709 [DATLAT]
4759 12:47:55.394254 Freq=600, CH1 RK1
4760 12:47:55.394439
4761 12:47:55.394602 DATLAT Default: 0x9
4762 12:47:55.397110 0, 0xFFFF, sum = 0
4763 12:47:55.401031 1, 0xFFFF, sum = 0
4764 12:47:55.401220 2, 0xFFFF, sum = 0
4765 12:47:55.403907 3, 0xFFFF, sum = 0
4766 12:47:55.404160 4, 0xFFFF, sum = 0
4767 12:47:55.406994 5, 0xFFFF, sum = 0
4768 12:47:55.407250 6, 0xFFFF, sum = 0
4769 12:47:55.410289 7, 0xFFFF, sum = 0
4770 12:47:55.410533 8, 0x0, sum = 1
4771 12:47:55.414094 9, 0x0, sum = 2
4772 12:47:55.414341 10, 0x0, sum = 3
4773 12:47:55.414569 11, 0x0, sum = 4
4774 12:47:55.417255 best_step = 9
4775 12:47:55.417498
4776 12:47:55.417730 ==
4777 12:47:55.420470 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 12:47:55.423726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 12:47:55.423970 ==
4780 12:47:55.426875 RX Vref Scan: 0
4781 12:47:55.427116
4782 12:47:55.430027 RX Vref 0 -> 0, step: 1
4783 12:47:55.430271
4784 12:47:55.430494 RX Delay -195 -> 252, step: 8
4785 12:47:55.437822 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4786 12:47:55.441053 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4787 12:47:55.444286 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4788 12:47:55.447963 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4789 12:47:55.454527 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4790 12:47:55.457506 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4791 12:47:55.460831 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4792 12:47:55.464116 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4793 12:47:55.470457 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4794 12:47:55.473709 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4795 12:47:55.477234 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4796 12:47:55.480602 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4797 12:47:55.487154 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4798 12:47:55.490567 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4799 12:47:55.493450 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4800 12:47:55.497002 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4801 12:47:55.497101 ==
4802 12:47:55.500360 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 12:47:55.506795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 12:47:55.506897 ==
4805 12:47:55.506987 DQS Delay:
4806 12:47:55.510342 DQS0 = 0, DQS1 = 0
4807 12:47:55.510435 DQM Delay:
4808 12:47:55.510524 DQM0 = 45, DQM1 = 37
4809 12:47:55.513204 DQ Delay:
4810 12:47:55.516469 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4811 12:47:55.520118 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4812 12:47:55.523484 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4813 12:47:55.526504 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4814 12:47:55.526576
4815 12:47:55.526636
4816 12:47:55.533657 [DQSOSCAuto] RK1, (LSB)MR18= 0x291e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4817 12:47:55.536741 CH1 RK1: MR19=808, MR18=291E
4818 12:47:55.542987 CH1_RK1: MR19=0x808, MR18=0x291E, DQSOSC=402, MR23=63, INC=162, DEC=108
4819 12:47:55.546403 [RxdqsGatingPostProcess] freq 600
4820 12:47:55.552822 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4821 12:47:55.552898 Pre-setting of DQS Precalculation
4822 12:47:55.559479 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4823 12:47:55.566200 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4824 12:47:55.572423 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4825 12:47:55.572566
4826 12:47:55.572662
4827 12:47:55.575620 [Calibration Summary] 1200 Mbps
4828 12:47:55.579302 CH 0, Rank 0
4829 12:47:55.579399 SW Impedance : PASS
4830 12:47:55.582509 DUTY Scan : NO K
4831 12:47:55.585465 ZQ Calibration : PASS
4832 12:47:55.585563 Jitter Meter : NO K
4833 12:47:55.589005 CBT Training : PASS
4834 12:47:55.592357 Write leveling : PASS
4835 12:47:55.592444 RX DQS gating : PASS
4836 12:47:55.595766 RX DQ/DQS(RDDQC) : PASS
4837 12:47:55.595835 TX DQ/DQS : PASS
4838 12:47:55.598934 RX DATLAT : PASS
4839 12:47:55.602248 RX DQ/DQS(Engine): PASS
4840 12:47:55.602319 TX OE : NO K
4841 12:47:55.605591 All Pass.
4842 12:47:55.605687
4843 12:47:55.605775 CH 0, Rank 1
4844 12:47:55.609128 SW Impedance : PASS
4845 12:47:55.609220 DUTY Scan : NO K
4846 12:47:55.612347 ZQ Calibration : PASS
4847 12:47:55.615216 Jitter Meter : NO K
4848 12:47:55.615312 CBT Training : PASS
4849 12:47:55.618863 Write leveling : PASS
4850 12:47:55.621784 RX DQS gating : PASS
4851 12:47:55.621877 RX DQ/DQS(RDDQC) : PASS
4852 12:47:55.625119 TX DQ/DQS : PASS
4853 12:47:55.628510 RX DATLAT : PASS
4854 12:47:55.628609 RX DQ/DQS(Engine): PASS
4855 12:47:55.631653 TX OE : NO K
4856 12:47:55.631745 All Pass.
4857 12:47:55.631835
4858 12:47:55.635145 CH 1, Rank 0
4859 12:47:55.635240 SW Impedance : PASS
4860 12:47:55.638467 DUTY Scan : NO K
4861 12:47:55.641596 ZQ Calibration : PASS
4862 12:47:55.641691 Jitter Meter : NO K
4863 12:47:55.644895 CBT Training : PASS
4864 12:47:55.648404 Write leveling : PASS
4865 12:47:55.648508 RX DQS gating : PASS
4866 12:47:55.651899 RX DQ/DQS(RDDQC) : PASS
4867 12:47:55.654580 TX DQ/DQS : PASS
4868 12:47:55.654682 RX DATLAT : PASS
4869 12:47:55.658165 RX DQ/DQS(Engine): PASS
4870 12:47:55.661252 TX OE : NO K
4871 12:47:55.661324 All Pass.
4872 12:47:55.661387
4873 12:47:55.661445 CH 1, Rank 1
4874 12:47:55.664440 SW Impedance : PASS
4875 12:47:55.668125 DUTY Scan : NO K
4876 12:47:55.668218 ZQ Calibration : PASS
4877 12:47:55.671429 Jitter Meter : NO K
4878 12:47:55.674448 CBT Training : PASS
4879 12:47:55.674550 Write leveling : PASS
4880 12:47:55.677829 RX DQS gating : PASS
4881 12:47:55.681309 RX DQ/DQS(RDDQC) : PASS
4882 12:47:55.681406 TX DQ/DQS : PASS
4883 12:47:55.684589 RX DATLAT : PASS
4884 12:47:55.687912 RX DQ/DQS(Engine): PASS
4885 12:47:55.688007 TX OE : NO K
4886 12:47:55.688098 All Pass.
4887 12:47:55.691316
4888 12:47:55.691384 DramC Write-DBI off
4889 12:47:55.694549 PER_BANK_REFRESH: Hybrid Mode
4890 12:47:55.694618 TX_TRACKING: ON
4891 12:47:55.704622 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4892 12:47:55.707750 [FAST_K] Save calibration result to emmc
4893 12:47:55.711321 dramc_set_vcore_voltage set vcore to 662500
4894 12:47:55.714169 Read voltage for 933, 3
4895 12:47:55.714265 Vio18 = 0
4896 12:47:55.717758 Vcore = 662500
4897 12:47:55.717853 Vdram = 0
4898 12:47:55.717942 Vddq = 0
4899 12:47:55.718042 Vmddr = 0
4900 12:47:55.724055 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4901 12:47:55.730737 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4902 12:47:55.730812 MEM_TYPE=3, freq_sel=17
4903 12:47:55.734321 sv_algorithm_assistance_LP4_1600
4904 12:47:55.737969 ============ PULL DRAM RESETB DOWN ============
4905 12:47:55.743885 ========== PULL DRAM RESETB DOWN end =========
4906 12:47:55.747121 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4907 12:47:55.750712 ===================================
4908 12:47:55.754223 LPDDR4 DRAM CONFIGURATION
4909 12:47:55.757830 ===================================
4910 12:47:55.757912 EX_ROW_EN[0] = 0x0
4911 12:47:55.760608 EX_ROW_EN[1] = 0x0
4912 12:47:55.760692 LP4Y_EN = 0x0
4913 12:47:55.764115 WORK_FSP = 0x0
4914 12:47:55.764210 WL = 0x3
4915 12:47:55.767258 RL = 0x3
4916 12:47:55.770920 BL = 0x2
4917 12:47:55.771035 RPST = 0x0
4918 12:47:55.774821 RD_PRE = 0x0
4919 12:47:55.774927 WR_PRE = 0x1
4920 12:47:55.776928 WR_PST = 0x0
4921 12:47:55.777000 DBI_WR = 0x0
4922 12:47:55.780283 DBI_RD = 0x0
4923 12:47:55.780386 OTF = 0x1
4924 12:47:55.783759 ===================================
4925 12:47:55.786772 ===================================
4926 12:47:55.790470 ANA top config
4927 12:47:55.793452 ===================================
4928 12:47:55.793534 DLL_ASYNC_EN = 0
4929 12:47:55.796694 ALL_SLAVE_EN = 1
4930 12:47:55.799904 NEW_RANK_MODE = 1
4931 12:47:55.803153 DLL_IDLE_MODE = 1
4932 12:47:55.806952 LP45_APHY_COMB_EN = 1
4933 12:47:55.807035 TX_ODT_DIS = 1
4934 12:47:55.809862 NEW_8X_MODE = 1
4935 12:47:55.813102 ===================================
4936 12:47:55.816404 ===================================
4937 12:47:55.819555 data_rate = 1866
4938 12:47:55.823166 CKR = 1
4939 12:47:55.826515 DQ_P2S_RATIO = 8
4940 12:47:55.829785 ===================================
4941 12:47:55.833272 CA_P2S_RATIO = 8
4942 12:47:55.833338 DQ_CA_OPEN = 0
4943 12:47:55.836411 DQ_SEMI_OPEN = 0
4944 12:47:55.839367 CA_SEMI_OPEN = 0
4945 12:47:55.842836 CA_FULL_RATE = 0
4946 12:47:55.845938 DQ_CKDIV4_EN = 1
4947 12:47:55.849333 CA_CKDIV4_EN = 1
4948 12:47:55.849402 CA_PREDIV_EN = 0
4949 12:47:55.852569 PH8_DLY = 0
4950 12:47:55.856638 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4951 12:47:55.859210 DQ_AAMCK_DIV = 4
4952 12:47:55.862643 CA_AAMCK_DIV = 4
4953 12:47:55.865933 CA_ADMCK_DIV = 4
4954 12:47:55.866046 DQ_TRACK_CA_EN = 0
4955 12:47:55.869299 CA_PICK = 933
4956 12:47:55.872284 CA_MCKIO = 933
4957 12:47:55.875736 MCKIO_SEMI = 0
4958 12:47:55.878857 PLL_FREQ = 3732
4959 12:47:55.882020 DQ_UI_PI_RATIO = 32
4960 12:47:55.885387 CA_UI_PI_RATIO = 0
4961 12:47:55.889189 ===================================
4962 12:47:55.892004 ===================================
4963 12:47:55.892093 memory_type:LPDDR4
4964 12:47:55.895358 GP_NUM : 10
4965 12:47:55.898541 SRAM_EN : 1
4966 12:47:55.898624 MD32_EN : 0
4967 12:47:55.902063 ===================================
4968 12:47:55.905158 [ANA_INIT] >>>>>>>>>>>>>>
4969 12:47:55.908473 <<<<<< [CONFIGURE PHASE]: ANA_TX
4970 12:47:55.912370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4971 12:47:55.914996 ===================================
4972 12:47:55.918855 data_rate = 1866,PCW = 0X8f00
4973 12:47:55.921901 ===================================
4974 12:47:55.924941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4975 12:47:55.928348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4976 12:47:55.935042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 12:47:55.938262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4978 12:47:55.944843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4979 12:47:55.948353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4980 12:47:55.948435 [ANA_INIT] flow start
4981 12:47:55.951733 [ANA_INIT] PLL >>>>>>>>
4982 12:47:55.954765 [ANA_INIT] PLL <<<<<<<<
4983 12:47:55.954847 [ANA_INIT] MIDPI >>>>>>>>
4984 12:47:55.958366 [ANA_INIT] MIDPI <<<<<<<<
4985 12:47:55.961959 [ANA_INIT] DLL >>>>>>>>
4986 12:47:55.962041 [ANA_INIT] flow end
4987 12:47:55.964929 ============ LP4 DIFF to SE enter ============
4988 12:47:55.971742 ============ LP4 DIFF to SE exit ============
4989 12:47:55.971830 [ANA_INIT] <<<<<<<<<<<<<
4990 12:47:55.974702 [Flow] Enable top DCM control >>>>>
4991 12:47:55.977906 [Flow] Enable top DCM control <<<<<
4992 12:47:55.981735 Enable DLL master slave shuffle
4993 12:47:55.988272 ==============================================================
4994 12:47:55.991373 Gating Mode config
4995 12:47:55.994719 ==============================================================
4996 12:47:55.998050 Config description:
4997 12:47:56.007597 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4998 12:47:56.014290 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4999 12:47:56.017936 SELPH_MODE 0: By rank 1: By Phase
5000 12:47:56.023958 ==============================================================
5001 12:47:56.027748 GAT_TRACK_EN = 1
5002 12:47:56.031131 RX_GATING_MODE = 2
5003 12:47:56.034197 RX_GATING_TRACK_MODE = 2
5004 12:47:56.034279 SELPH_MODE = 1
5005 12:47:56.037448 PICG_EARLY_EN = 1
5006 12:47:56.040413 VALID_LAT_VALUE = 1
5007 12:47:56.047181 ==============================================================
5008 12:47:56.050455 Enter into Gating configuration >>>>
5009 12:47:56.053919 Exit from Gating configuration <<<<
5010 12:47:56.057307 Enter into DVFS_PRE_config >>>>>
5011 12:47:56.067263 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5012 12:47:56.070193 Exit from DVFS_PRE_config <<<<<
5013 12:47:56.073345 Enter into PICG configuration >>>>
5014 12:47:56.076863 Exit from PICG configuration <<<<
5015 12:47:56.080186 [RX_INPUT] configuration >>>>>
5016 12:47:56.083941 [RX_INPUT] configuration <<<<<
5017 12:47:56.086730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5018 12:47:56.093539 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5019 12:47:56.100121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 12:47:56.106429 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 12:47:56.113072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 12:47:56.119531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 12:47:56.123437 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5024 12:47:56.126136 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5025 12:47:56.129477 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5026 12:47:56.136252 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5027 12:47:56.139705 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5028 12:47:56.143212 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5029 12:47:56.146267 ===================================
5030 12:47:56.149267 LPDDR4 DRAM CONFIGURATION
5031 12:47:56.153068 ===================================
5032 12:47:56.153198 EX_ROW_EN[0] = 0x0
5033 12:47:56.155966 EX_ROW_EN[1] = 0x0
5034 12:47:56.159294 LP4Y_EN = 0x0
5035 12:47:56.159378 WORK_FSP = 0x0
5036 12:47:56.162816 WL = 0x3
5037 12:47:56.162900 RL = 0x3
5038 12:47:56.166017 BL = 0x2
5039 12:47:56.166101 RPST = 0x0
5040 12:47:56.169409 RD_PRE = 0x0
5041 12:47:56.169493 WR_PRE = 0x1
5042 12:47:56.172812 WR_PST = 0x0
5043 12:47:56.172896 DBI_WR = 0x0
5044 12:47:56.175885 DBI_RD = 0x0
5045 12:47:56.175969 OTF = 0x1
5046 12:47:56.179481 ===================================
5047 12:47:56.182391 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5048 12:47:56.188993 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5049 12:47:56.192419 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 12:47:56.195638 ===================================
5051 12:47:56.199013 LPDDR4 DRAM CONFIGURATION
5052 12:47:56.202323 ===================================
5053 12:47:56.202408 EX_ROW_EN[0] = 0x10
5054 12:47:56.205354 EX_ROW_EN[1] = 0x0
5055 12:47:56.209144 LP4Y_EN = 0x0
5056 12:47:56.209228 WORK_FSP = 0x0
5057 12:47:56.212403 WL = 0x3
5058 12:47:56.212486 RL = 0x3
5059 12:47:56.215669 BL = 0x2
5060 12:47:56.215753 RPST = 0x0
5061 12:47:56.218696 RD_PRE = 0x0
5062 12:47:56.218780 WR_PRE = 0x1
5063 12:47:56.222640 WR_PST = 0x0
5064 12:47:56.222723 DBI_WR = 0x0
5065 12:47:56.225320 DBI_RD = 0x0
5066 12:47:56.225402 OTF = 0x1
5067 12:47:56.228658 ===================================
5068 12:47:56.235183 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5069 12:47:56.239508 nWR fixed to 30
5070 12:47:56.243080 [ModeRegInit_LP4] CH0 RK0
5071 12:47:56.243165 [ModeRegInit_LP4] CH0 RK1
5072 12:47:56.246588 [ModeRegInit_LP4] CH1 RK0
5073 12:47:56.249934 [ModeRegInit_LP4] CH1 RK1
5074 12:47:56.250018 match AC timing 9
5075 12:47:56.256005 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5076 12:47:56.259493 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5077 12:47:56.262496 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5078 12:47:56.269395 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5079 12:47:56.272457 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5080 12:47:56.272597 ==
5081 12:47:56.275878 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 12:47:56.279145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5083 12:47:56.282485 ==
5084 12:47:56.285769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5085 12:47:56.292695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5086 12:47:56.295598 [CA 0] Center 37 (7~68) winsize 62
5087 12:47:56.299216 [CA 1] Center 37 (7~68) winsize 62
5088 12:47:56.302112 [CA 2] Center 34 (4~65) winsize 62
5089 12:47:56.305202 [CA 3] Center 34 (4~65) winsize 62
5090 12:47:56.308616 [CA 4] Center 33 (3~64) winsize 62
5091 12:47:56.311887 [CA 5] Center 33 (4~63) winsize 60
5092 12:47:56.311969
5093 12:47:56.315280 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5094 12:47:56.315363
5095 12:47:56.318630 [CATrainingPosCal] consider 1 rank data
5096 12:47:56.321986 u2DelayCellTimex100 = 270/100 ps
5097 12:47:56.325362 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5098 12:47:56.328910 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5099 12:47:56.331828 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5100 12:47:56.338590 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5101 12:47:56.342010 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5102 12:47:56.345530 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5103 12:47:56.345716
5104 12:47:56.348679 CA PerBit enable=1, Macro0, CA PI delay=33
5105 12:47:56.348871
5106 12:47:56.352382 [CBTSetCACLKResult] CA Dly = 33
5107 12:47:56.352602 CS Dly: 7 (0~38)
5108 12:47:56.352723 ==
5109 12:47:56.355270 Dram Type= 6, Freq= 0, CH_0, rank 1
5110 12:47:56.362148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 12:47:56.362391 ==
5112 12:47:56.364876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 12:47:56.371360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5114 12:47:56.375190 [CA 0] Center 37 (7~68) winsize 62
5115 12:47:56.378658 [CA 1] Center 37 (7~68) winsize 62
5116 12:47:56.381393 [CA 2] Center 34 (4~65) winsize 62
5117 12:47:56.384709 [CA 3] Center 34 (4~65) winsize 62
5118 12:47:56.388335 [CA 4] Center 33 (3~64) winsize 62
5119 12:47:56.391503 [CA 5] Center 33 (3~63) winsize 61
5120 12:47:56.392063
5121 12:47:56.395070 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5122 12:47:56.395543
5123 12:47:56.397833 [CATrainingPosCal] consider 2 rank data
5124 12:47:56.401170 u2DelayCellTimex100 = 270/100 ps
5125 12:47:56.405037 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5126 12:47:56.411186 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5127 12:47:56.414602 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5128 12:47:56.417905 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5129 12:47:56.421051 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5130 12:47:56.424792 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5131 12:47:56.424876
5132 12:47:56.427305 CA PerBit enable=1, Macro0, CA PI delay=33
5133 12:47:56.427387
5134 12:47:56.430597 [CBTSetCACLKResult] CA Dly = 33
5135 12:47:56.433835 CS Dly: 7 (0~39)
5136 12:47:56.433917
5137 12:47:56.437309 ----->DramcWriteLeveling(PI) begin...
5138 12:47:56.437395 ==
5139 12:47:56.440446 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 12:47:56.443889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 12:47:56.443975 ==
5142 12:47:56.447119 Write leveling (Byte 0): 31 => 31
5143 12:47:56.450357 Write leveling (Byte 1): 27 => 27
5144 12:47:56.453975 DramcWriteLeveling(PI) end<-----
5145 12:47:56.454059
5146 12:47:56.454144 ==
5147 12:47:56.456814 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 12:47:56.460421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 12:47:56.460506 ==
5150 12:47:56.463289 [Gating] SW mode calibration
5151 12:47:56.470478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5152 12:47:56.476666 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5153 12:47:56.480423 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5154 12:47:56.486626 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5155 12:47:56.489809 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 12:47:56.493291 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 12:47:56.499568 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 12:47:56.503113 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 12:47:56.506707 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5160 12:47:56.512864 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5161 12:47:56.516483 0 15 0 | B1->B0 | 3333 2a2a | 0 0 | (0 1) (1 1)
5162 12:47:56.519358 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 12:47:56.525893 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 12:47:56.529304 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 12:47:56.532680 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 12:47:56.536660 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 12:47:56.542902 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 12:47:56.546379 0 15 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5169 12:47:56.549558 1 0 0 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
5170 12:47:56.556310 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 12:47:56.559502 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 12:47:56.562248 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 12:47:56.569006 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 12:47:56.572125 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 12:47:56.575482 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 12:47:56.582137 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5177 12:47:56.585555 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5178 12:47:56.591947 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5179 12:47:56.595554 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:47:56.598784 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 12:47:56.605358 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:47:56.609006 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:47:56.612123 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:47:56.618441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:47:56.621590 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:47:56.624931 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:47:56.632166 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:47:56.635092 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:47:56.638749 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:47:56.645109 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:47:56.648592 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:47:56.651996 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5193 12:47:56.655183 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 12:47:56.658678 Total UI for P1: 0, mck2ui 16
5195 12:47:56.661952 best dqsien dly found for B0: ( 1, 2, 28)
5196 12:47:56.665027 Total UI for P1: 0, mck2ui 16
5197 12:47:56.668296 best dqsien dly found for B1: ( 1, 2, 30)
5198 12:47:56.671586 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5199 12:47:56.678358 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5200 12:47:56.678794
5201 12:47:56.681676 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5202 12:47:56.684803 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5203 12:47:56.688350 [Gating] SW calibration Done
5204 12:47:56.688826 ==
5205 12:47:56.691662 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 12:47:56.694684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 12:47:56.695128 ==
5208 12:47:56.697874 RX Vref Scan: 0
5209 12:47:56.698326
5210 12:47:56.698767 RX Vref 0 -> 0, step: 1
5211 12:47:56.699204
5212 12:47:56.700930 RX Delay -80 -> 252, step: 8
5213 12:47:56.704726 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5214 12:47:56.711018 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5215 12:47:56.714675 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5216 12:47:56.717445 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5217 12:47:56.721049 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5218 12:47:56.724269 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5219 12:47:56.727298 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5220 12:47:56.734610 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5221 12:47:56.737348 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5222 12:47:56.740673 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5223 12:47:56.743981 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5224 12:47:56.747071 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5225 12:47:56.754545 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5226 12:47:56.757472 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5227 12:47:56.760577 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5228 12:47:56.763904 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5229 12:47:56.764447 ==
5230 12:47:56.767343 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 12:47:56.774488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 12:47:56.775014 ==
5233 12:47:56.775362 DQS Delay:
5234 12:47:56.775683 DQS0 = 0, DQS1 = 0
5235 12:47:56.777000 DQM Delay:
5236 12:47:56.777369 DQM0 = 97, DQM1 = 86
5237 12:47:56.780211 DQ Delay:
5238 12:47:56.783933 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5239 12:47:56.786842 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5240 12:47:56.790541 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5241 12:47:56.793457 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5242 12:47:56.793889
5243 12:47:56.794223
5244 12:47:56.794534 ==
5245 12:47:56.797094 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 12:47:56.800290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 12:47:56.800872 ==
5248 12:47:56.801219
5249 12:47:56.801534
5250 12:47:56.803806 TX Vref Scan disable
5251 12:47:56.804227 == TX Byte 0 ==
5252 12:47:56.809978 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5253 12:47:56.813276 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5254 12:47:56.813774 == TX Byte 1 ==
5255 12:47:56.820186 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5256 12:47:56.823527 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5257 12:47:56.824147 ==
5258 12:47:56.826900 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:47:56.829772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:47:56.830198 ==
5261 12:47:56.833173
5262 12:47:56.833621
5263 12:47:56.833996 TX Vref Scan disable
5264 12:47:56.836567 == TX Byte 0 ==
5265 12:47:56.839811 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5266 12:47:56.846653 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5267 12:47:56.847100 == TX Byte 1 ==
5268 12:47:56.850005 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5269 12:47:56.856333 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5270 12:47:56.856858
5271 12:47:56.857197 [DATLAT]
5272 12:47:56.857512 Freq=933, CH0 RK0
5273 12:47:56.857819
5274 12:47:56.859853 DATLAT Default: 0xd
5275 12:47:56.860272 0, 0xFFFF, sum = 0
5276 12:47:56.862796 1, 0xFFFF, sum = 0
5277 12:47:56.866902 2, 0xFFFF, sum = 0
5278 12:47:56.867432 3, 0xFFFF, sum = 0
5279 12:47:56.869819 4, 0xFFFF, sum = 0
5280 12:47:56.870356 5, 0xFFFF, sum = 0
5281 12:47:56.873189 6, 0xFFFF, sum = 0
5282 12:47:56.873614 7, 0xFFFF, sum = 0
5283 12:47:56.876199 8, 0xFFFF, sum = 0
5284 12:47:56.876774 9, 0xFFFF, sum = 0
5285 12:47:56.879729 10, 0x0, sum = 1
5286 12:47:56.880297 11, 0x0, sum = 2
5287 12:47:56.882996 12, 0x0, sum = 3
5288 12:47:56.883620 13, 0x0, sum = 4
5289 12:47:56.884074 best_step = 11
5290 12:47:56.884566
5291 12:47:56.885989 ==
5292 12:47:56.889498 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 12:47:56.892702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 12:47:56.893117 ==
5295 12:47:56.893651 RX Vref Scan: 1
5296 12:47:56.893940
5297 12:47:56.895736 RX Vref 0 -> 0, step: 1
5298 12:47:56.895817
5299 12:47:56.899624 RX Delay -61 -> 252, step: 4
5300 12:47:56.899729
5301 12:47:56.902396 Set Vref, RX VrefLevel [Byte0]: 60
5302 12:47:56.905870 [Byte1]: 54
5303 12:47:56.905950
5304 12:47:56.908817 Final RX Vref Byte 0 = 60 to rank0
5305 12:47:56.912429 Final RX Vref Byte 1 = 54 to rank0
5306 12:47:56.915435 Final RX Vref Byte 0 = 60 to rank1
5307 12:47:56.919093 Final RX Vref Byte 1 = 54 to rank1==
5308 12:47:56.922692 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 12:47:56.925776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 12:47:56.928808 ==
5311 12:47:56.928898 DQS Delay:
5312 12:47:56.928993 DQS0 = 0, DQS1 = 0
5313 12:47:56.932266 DQM Delay:
5314 12:47:56.932392 DQM0 = 97, DQM1 = 87
5315 12:47:56.935306 DQ Delay:
5316 12:47:56.938525 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5317 12:47:56.941804 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5318 12:47:56.945461 DQ8 =78, DQ9 =78, DQ10 =86, DQ11 =82
5319 12:47:56.949214 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5320 12:47:56.949313
5321 12:47:56.949414
5322 12:47:56.955579 [DQSOSCAuto] RK0, (LSB)MR18= 0x280e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5323 12:47:56.958854 CH0 RK0: MR19=505, MR18=280E
5324 12:47:56.965063 CH0_RK0: MR19=0x505, MR18=0x280E, DQSOSC=409, MR23=63, INC=64, DEC=43
5325 12:47:56.965149
5326 12:47:56.968354 ----->DramcWriteLeveling(PI) begin...
5327 12:47:56.968447 ==
5328 12:47:56.971694 Dram Type= 6, Freq= 0, CH_0, rank 1
5329 12:47:56.975525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 12:47:56.975625 ==
5331 12:47:56.978543 Write leveling (Byte 0): 34 => 34
5332 12:47:56.982131 Write leveling (Byte 1): 30 => 30
5333 12:47:56.985512 DramcWriteLeveling(PI) end<-----
5334 12:47:56.985709
5335 12:47:56.985842 ==
5336 12:47:56.988747 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 12:47:56.991666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 12:47:56.991900 ==
5339 12:47:56.995666 [Gating] SW mode calibration
5340 12:47:57.001849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5341 12:47:57.008146 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5342 12:47:57.011527 0 14 0 | B1->B0 | 2929 3030 | 0 1 | (0 0) (0 0)
5343 12:47:57.018464 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5344 12:47:57.021919 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 12:47:57.025326 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 12:47:57.031965 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 12:47:57.034567 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 12:47:57.038305 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 12:47:57.044930 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5350 12:47:57.048086 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5351 12:47:57.051955 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 12:47:57.057681 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 12:47:57.061171 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 12:47:57.064213 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 12:47:57.070967 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 12:47:57.074223 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 12:47:57.077697 0 15 28 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
5358 12:47:57.083907 1 0 0 | B1->B0 | 4343 4545 | 0 0 | (1 1) (0 0)
5359 12:47:57.087768 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 12:47:57.090722 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 12:47:57.097033 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 12:47:57.101034 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 12:47:57.103729 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 12:47:57.110489 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 12:47:57.113818 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5366 12:47:57.117076 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5367 12:47:57.123559 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:47:57.126988 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 12:47:57.130523 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 12:47:57.136855 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 12:47:57.140257 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 12:47:57.143760 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 12:47:57.150145 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:47:57.153188 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:47:57.157033 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 12:47:57.163774 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 12:47:57.166155 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 12:47:57.169529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 12:47:57.176544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 12:47:57.179305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 12:47:57.183120 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:47:57.189346 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5383 12:47:57.189455 Total UI for P1: 0, mck2ui 16
5384 12:47:57.196180 best dqsien dly found for B0: ( 1, 2, 30)
5385 12:47:57.199273 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 12:47:57.202524 Total UI for P1: 0, mck2ui 16
5387 12:47:57.205984 best dqsien dly found for B1: ( 1, 3, 0)
5388 12:47:57.209540 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5389 12:47:57.212456 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5390 12:47:57.212593
5391 12:47:57.216408 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5392 12:47:57.218929 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5393 12:47:57.223144 [Gating] SW calibration Done
5394 12:47:57.223243 ==
5395 12:47:57.225741 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 12:47:57.228712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 12:47:57.228788 ==
5398 12:47:57.232879 RX Vref Scan: 0
5399 12:47:57.232992
5400 12:47:57.235665 RX Vref 0 -> 0, step: 1
5401 12:47:57.235740
5402 12:47:57.235802 RX Delay -80 -> 252, step: 8
5403 12:47:57.242281 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5404 12:47:57.245734 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5405 12:47:57.249090 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5406 12:47:57.252609 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5407 12:47:57.255747 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5408 12:47:57.262577 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5409 12:47:57.266094 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5410 12:47:57.268807 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5411 12:47:57.272446 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5412 12:47:57.275625 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5413 12:47:57.279125 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5414 12:47:57.285611 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5415 12:47:57.288839 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5416 12:47:57.291940 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5417 12:47:57.295221 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5418 12:47:57.298547 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5419 12:47:57.302322 ==
5420 12:47:57.305351 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 12:47:57.308465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 12:47:57.308990 ==
5423 12:47:57.309337 DQS Delay:
5424 12:47:57.311863 DQS0 = 0, DQS1 = 0
5425 12:47:57.312333 DQM Delay:
5426 12:47:57.315811 DQM0 = 97, DQM1 = 88
5427 12:47:57.316252 DQ Delay:
5428 12:47:57.318053 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5429 12:47:57.321717 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5430 12:47:57.324787 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5431 12:47:57.327982 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =91
5432 12:47:57.328404
5433 12:47:57.328824
5434 12:47:57.329218 ==
5435 12:47:57.331237 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 12:47:57.334702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 12:47:57.335154 ==
5438 12:47:57.338149
5439 12:47:57.338588
5440 12:47:57.338930 TX Vref Scan disable
5441 12:47:57.341096 == TX Byte 0 ==
5442 12:47:57.344510 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5443 12:47:57.347682 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5444 12:47:57.351307 == TX Byte 1 ==
5445 12:47:57.354329 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5446 12:47:57.358001 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5447 12:47:57.360840 ==
5448 12:47:57.361305 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 12:47:57.367741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 12:47:57.368348 ==
5451 12:47:57.368876
5452 12:47:57.369259
5453 12:47:57.370609 TX Vref Scan disable
5454 12:47:57.371119 == TX Byte 0 ==
5455 12:47:57.377489 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5456 12:47:57.381203 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5457 12:47:57.381625 == TX Byte 1 ==
5458 12:47:57.387228 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5459 12:47:57.390461 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5460 12:47:57.391084
5461 12:47:57.391624 [DATLAT]
5462 12:47:57.394018 Freq=933, CH0 RK1
5463 12:47:57.394622
5464 12:47:57.394977 DATLAT Default: 0xb
5465 12:47:57.396937 0, 0xFFFF, sum = 0
5466 12:47:57.397434 1, 0xFFFF, sum = 0
5467 12:47:57.400275 2, 0xFFFF, sum = 0
5468 12:47:57.400831 3, 0xFFFF, sum = 0
5469 12:47:57.403768 4, 0xFFFF, sum = 0
5470 12:47:57.407533 5, 0xFFFF, sum = 0
5471 12:47:57.408023 6, 0xFFFF, sum = 0
5472 12:47:57.410074 7, 0xFFFF, sum = 0
5473 12:47:57.410530 8, 0xFFFF, sum = 0
5474 12:47:57.414133 9, 0xFFFF, sum = 0
5475 12:47:57.414764 10, 0x0, sum = 1
5476 12:47:57.416827 11, 0x0, sum = 2
5477 12:47:57.417302 12, 0x0, sum = 3
5478 12:47:57.417661 13, 0x0, sum = 4
5479 12:47:57.420431 best_step = 11
5480 12:47:57.420937
5481 12:47:57.421399 ==
5482 12:47:57.423299 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 12:47:57.426762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 12:47:57.427377 ==
5485 12:47:57.430115 RX Vref Scan: 0
5486 12:47:57.430685
5487 12:47:57.433642 RX Vref 0 -> 0, step: 1
5488 12:47:57.434158
5489 12:47:57.434740 RX Delay -61 -> 252, step: 4
5490 12:47:57.440904 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5491 12:47:57.444550 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5492 12:47:57.447580 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5493 12:47:57.450971 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5494 12:47:57.453946 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5495 12:47:57.460446 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5496 12:47:57.463837 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5497 12:47:57.467271 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5498 12:47:57.470882 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5499 12:47:57.473946 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5500 12:47:57.480464 iDelay=203, Bit 10, Center 88 (-9 ~ 186) 196
5501 12:47:57.484043 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5502 12:47:57.486950 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5503 12:47:57.490389 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5504 12:47:57.493533 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5505 12:47:57.500825 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5506 12:47:57.501284 ==
5507 12:47:57.503946 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 12:47:57.506813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 12:47:57.507211 ==
5510 12:47:57.507563 DQS Delay:
5511 12:47:57.510776 DQS0 = 0, DQS1 = 0
5512 12:47:57.511251 DQM Delay:
5513 12:47:57.513774 DQM0 = 96, DQM1 = 87
5514 12:47:57.514252 DQ Delay:
5515 12:47:57.516912 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =94
5516 12:47:57.520246 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5517 12:47:57.523872 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5518 12:47:57.526902 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5519 12:47:57.527296
5520 12:47:57.527645
5521 12:47:57.536446 [DQSOSCAuto] RK1, (LSB)MR18= 0x24f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5522 12:47:57.536906 CH0 RK1: MR19=504, MR18=24F5
5523 12:47:57.543303 CH0_RK1: MR19=0x504, MR18=0x24F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5524 12:47:57.546510 [RxdqsGatingPostProcess] freq 933
5525 12:47:57.553188 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5526 12:47:57.556319 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 12:47:57.559624 best DQS1 dly(2T, 0.5T) = (0, 10)
5528 12:47:57.563244 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 12:47:57.566305 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5530 12:47:57.566833 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 12:47:57.569774 best DQS1 dly(2T, 0.5T) = (0, 11)
5532 12:47:57.573019 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 12:47:57.576399 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5534 12:47:57.579561 Pre-setting of DQS Precalculation
5535 12:47:57.586552 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5536 12:47:57.587108 ==
5537 12:47:57.589532 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 12:47:57.592913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 12:47:57.593333 ==
5540 12:47:57.599644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 12:47:57.606187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5542 12:47:57.609219 [CA 0] Center 36 (6~67) winsize 62
5543 12:47:57.612661 [CA 1] Center 37 (6~68) winsize 63
5544 12:47:57.616017 [CA 2] Center 34 (4~65) winsize 62
5545 12:47:57.619397 [CA 3] Center 33 (3~64) winsize 62
5546 12:47:57.623022 [CA 4] Center 34 (4~64) winsize 61
5547 12:47:57.625496 [CA 5] Center 33 (3~64) winsize 62
5548 12:47:57.625944
5549 12:47:57.629123 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5550 12:47:57.629523
5551 12:47:57.632577 [CATrainingPosCal] consider 1 rank data
5552 12:47:57.635324 u2DelayCellTimex100 = 270/100 ps
5553 12:47:57.638655 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5554 12:47:57.641935 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5555 12:47:57.645501 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 12:47:57.648693 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 12:47:57.651918 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5558 12:47:57.655618 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 12:47:57.656042
5560 12:47:57.661769 CA PerBit enable=1, Macro0, CA PI delay=33
5561 12:47:57.662196
5562 12:47:57.665452 [CBTSetCACLKResult] CA Dly = 33
5563 12:47:57.665878 CS Dly: 5 (0~36)
5564 12:47:57.666215 ==
5565 12:47:57.669097 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 12:47:57.671826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 12:47:57.672258 ==
5568 12:47:57.678691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 12:47:57.684644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5570 12:47:57.689351 [CA 0] Center 36 (6~67) winsize 62
5571 12:47:57.691944 [CA 1] Center 36 (6~67) winsize 62
5572 12:47:57.694914 [CA 2] Center 34 (3~65) winsize 63
5573 12:47:57.698310 [CA 3] Center 33 (3~64) winsize 62
5574 12:47:57.701292 [CA 4] Center 34 (3~65) winsize 63
5575 12:47:57.704848 [CA 5] Center 33 (3~64) winsize 62
5576 12:47:57.705278
5577 12:47:57.707865 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5578 12:47:57.708289
5579 12:47:57.711380 [CATrainingPosCal] consider 2 rank data
5580 12:47:57.715306 u2DelayCellTimex100 = 270/100 ps
5581 12:47:57.718013 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5582 12:47:57.720976 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 12:47:57.724994 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5584 12:47:57.731325 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 12:47:57.734382 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5586 12:47:57.737654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5587 12:47:57.738084
5588 12:47:57.741056 CA PerBit enable=1, Macro0, CA PI delay=33
5589 12:47:57.741590
5590 12:47:57.744637 [CBTSetCACLKResult] CA Dly = 33
5591 12:47:57.745069 CS Dly: 6 (0~39)
5592 12:47:57.745410
5593 12:47:57.747569 ----->DramcWriteLeveling(PI) begin...
5594 12:47:57.748001 ==
5595 12:47:57.750841 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 12:47:57.757404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 12:47:57.757831 ==
5598 12:47:57.760809 Write leveling (Byte 0): 25 => 25
5599 12:47:57.764695 Write leveling (Byte 1): 28 => 28
5600 12:47:57.767172 DramcWriteLeveling(PI) end<-----
5601 12:47:57.767598
5602 12:47:57.767980 ==
5603 12:47:57.771047 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 12:47:57.773956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 12:47:57.774384 ==
5606 12:47:57.777304 [Gating] SW mode calibration
5607 12:47:57.784085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5608 12:47:57.790508 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5609 12:47:57.793676 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5610 12:47:57.796767 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 12:47:57.803334 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 12:47:57.806755 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 12:47:57.810326 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 12:47:57.816969 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 12:47:57.820267 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5616 12:47:57.823602 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (1 1)
5617 12:47:57.826718 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5618 12:47:57.833500 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 12:47:57.836361 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 12:47:57.842965 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 12:47:57.847009 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 12:47:57.849615 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 12:47:57.852945 0 15 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5624 12:47:57.860080 0 15 28 | B1->B0 | 3535 3d3d | 0 0 | (0 0) (0 0)
5625 12:47:57.862990 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5626 12:47:57.866479 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 12:47:57.872873 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 12:47:57.876314 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 12:47:57.879760 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 12:47:57.886060 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 12:47:57.889240 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5632 12:47:57.892589 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5633 12:47:57.899538 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:47:57.902685 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:47:57.906065 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:47:57.912297 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:47:57.915524 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:47:57.918919 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:47:57.925357 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:47:57.928519 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:47:57.932234 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:47:57.938427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:47:57.941944 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:47:57.945357 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:47:57.951492 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:47:57.955220 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:47:57.958303 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5648 12:47:57.964839 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 12:47:57.968157 Total UI for P1: 0, mck2ui 16
5650 12:47:57.971532 best dqsien dly found for B0: ( 1, 2, 24)
5651 12:47:57.974622 Total UI for P1: 0, mck2ui 16
5652 12:47:57.977951 best dqsien dly found for B1: ( 1, 2, 26)
5653 12:47:57.981336 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5654 12:47:57.984805 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5655 12:47:57.984887
5656 12:47:57.988181 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5657 12:47:57.991655 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5658 12:47:57.994836 [Gating] SW calibration Done
5659 12:47:57.994919 ==
5660 12:47:57.998166 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 12:47:58.001636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 12:47:58.001720 ==
5663 12:47:58.004411 RX Vref Scan: 0
5664 12:47:58.004494
5665 12:47:58.008010 RX Vref 0 -> 0, step: 1
5666 12:47:58.008092
5667 12:47:58.008158 RX Delay -80 -> 252, step: 8
5668 12:47:58.014566 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5669 12:47:58.017449 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5670 12:47:58.021491 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5671 12:47:58.024833 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5672 12:47:58.027507 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5673 12:47:58.034331 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5674 12:47:58.037638 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5675 12:47:58.041289 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5676 12:47:58.044299 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5677 12:47:58.047272 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5678 12:47:58.050554 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5679 12:47:58.057240 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5680 12:47:58.060649 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5681 12:47:58.064139 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5682 12:47:58.067158 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5683 12:47:58.070292 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5684 12:47:58.070375 ==
5685 12:47:58.073995 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 12:47:58.080383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 12:47:58.080466 ==
5688 12:47:58.080572 DQS Delay:
5689 12:47:58.083888 DQS0 = 0, DQS1 = 0
5690 12:47:58.083973 DQM Delay:
5691 12:47:58.086914 DQM0 = 102, DQM1 = 91
5692 12:47:58.086996 DQ Delay:
5693 12:47:58.090094 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5694 12:47:58.093828 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5695 12:47:58.097251 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83
5696 12:47:58.100563 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5697 12:47:58.100993
5698 12:47:58.101330
5699 12:47:58.101645 ==
5700 12:47:58.104451 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:47:58.106993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:47:58.107420 ==
5703 12:47:58.110174
5704 12:47:58.110598
5705 12:47:58.110937 TX Vref Scan disable
5706 12:47:58.113709 == TX Byte 0 ==
5707 12:47:58.116990 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5708 12:47:58.120474 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5709 12:47:58.123823 == TX Byte 1 ==
5710 12:47:58.126951 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5711 12:47:58.130046 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5712 12:47:58.133217 ==
5713 12:47:58.133642 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 12:47:58.140662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 12:47:58.141091 ==
5716 12:47:58.141435
5717 12:47:58.141758
5718 12:47:58.143401 TX Vref Scan disable
5719 12:47:58.143836 == TX Byte 0 ==
5720 12:47:58.149685 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5721 12:47:58.153094 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5722 12:47:58.153521 == TX Byte 1 ==
5723 12:47:58.159360 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 12:47:58.163129 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 12:47:58.163557
5726 12:47:58.163896 [DATLAT]
5727 12:47:58.166315 Freq=933, CH1 RK0
5728 12:47:58.166740
5729 12:47:58.167076 DATLAT Default: 0xd
5730 12:47:58.169743 0, 0xFFFF, sum = 0
5731 12:47:58.170360 1, 0xFFFF, sum = 0
5732 12:47:58.172882 2, 0xFFFF, sum = 0
5733 12:47:58.173342 3, 0xFFFF, sum = 0
5734 12:47:58.176205 4, 0xFFFF, sum = 0
5735 12:47:58.179583 5, 0xFFFF, sum = 0
5736 12:47:58.180086 6, 0xFFFF, sum = 0
5737 12:47:58.182588 7, 0xFFFF, sum = 0
5738 12:47:58.183016 8, 0xFFFF, sum = 0
5739 12:47:58.186226 9, 0xFFFF, sum = 0
5740 12:47:58.186655 10, 0x0, sum = 1
5741 12:47:58.189169 11, 0x0, sum = 2
5742 12:47:58.189602 12, 0x0, sum = 3
5743 12:47:58.189948 13, 0x0, sum = 4
5744 12:47:58.192781 best_step = 11
5745 12:47:58.193225
5746 12:47:58.193606 ==
5747 12:47:58.195654 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 12:47:58.199171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 12:47:58.199612 ==
5750 12:47:58.203145 RX Vref Scan: 1
5751 12:47:58.203660
5752 12:47:58.205539 RX Vref 0 -> 0, step: 1
5753 12:47:58.205961
5754 12:47:58.206296 RX Delay -69 -> 252, step: 4
5755 12:47:58.206612
5756 12:47:58.209334 Set Vref, RX VrefLevel [Byte0]: 50
5757 12:47:58.212691 [Byte1]: 54
5758 12:47:58.217313
5759 12:47:58.217831 Final RX Vref Byte 0 = 50 to rank0
5760 12:47:58.220824 Final RX Vref Byte 1 = 54 to rank0
5761 12:47:58.223981 Final RX Vref Byte 0 = 50 to rank1
5762 12:47:58.227515 Final RX Vref Byte 1 = 54 to rank1==
5763 12:47:58.230767 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 12:47:58.236761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 12:47:58.237557 ==
5766 12:47:58.238055 DQS Delay:
5767 12:47:58.240004 DQS0 = 0, DQS1 = 0
5768 12:47:58.240706 DQM Delay:
5769 12:47:58.241140 DQM0 = 100, DQM1 = 93
5770 12:47:58.243610 DQ Delay:
5771 12:47:58.246511 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =96
5772 12:47:58.249673 DQ4 =98, DQ5 =110, DQ6 =110, DQ7 =98
5773 12:47:58.253013 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5774 12:47:58.256310 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =104
5775 12:47:58.256836
5776 12:47:58.257205
5777 12:47:58.263027 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5778 12:47:58.266708 CH1 RK0: MR19=505, MR18=1B0A
5779 12:47:58.272973 CH1_RK0: MR19=0x505, MR18=0x1B0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5780 12:47:58.273476
5781 12:47:58.276338 ----->DramcWriteLeveling(PI) begin...
5782 12:47:58.276842 ==
5783 12:47:58.279599 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 12:47:58.283120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 12:47:58.286585 ==
5786 12:47:58.287005 Write leveling (Byte 0): 27 => 27
5787 12:47:58.289870 Write leveling (Byte 1): 28 => 28
5788 12:47:58.292976 DramcWriteLeveling(PI) end<-----
5789 12:47:58.293402
5790 12:47:58.293740 ==
5791 12:47:58.296286 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 12:47:58.303111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 12:47:58.303538 ==
5794 12:47:58.303878 [Gating] SW mode calibration
5795 12:47:58.313088 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5796 12:47:58.315452 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5797 12:47:58.322409 0 14 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5798 12:47:58.325652 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 12:47:58.328476 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 12:47:58.335620 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 12:47:58.338619 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 12:47:58.342057 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5803 12:47:58.348417 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
5804 12:47:58.351898 0 14 28 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
5805 12:47:58.355603 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5806 12:47:58.362117 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 12:47:58.365345 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 12:47:58.368383 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 12:47:58.371691 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 12:47:58.378895 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 12:47:58.381953 0 15 24 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
5812 12:47:58.385556 0 15 28 | B1->B0 | 3737 2e2e | 0 0 | (0 0) (0 0)
5813 12:47:58.391796 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 12:47:58.395092 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 12:47:58.398221 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 12:47:58.405370 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 12:47:58.408795 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 12:47:58.411666 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5819 12:47:58.418980 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 12:47:58.421663 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5821 12:47:58.425289 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:47:58.431379 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 12:47:58.434864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 12:47:58.438359 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 12:47:58.445287 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:47:58.448611 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:47:58.451479 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:47:58.457909 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:47:58.461815 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 12:47:58.464844 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 12:47:58.471745 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:47:58.474508 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 12:47:58.477731 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:47:58.484684 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:47:58.488158 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5836 12:47:58.491031 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5837 12:47:58.495015 Total UI for P1: 0, mck2ui 16
5838 12:47:58.498009 best dqsien dly found for B1: ( 1, 2, 24)
5839 12:47:58.504164 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5840 12:47:58.507548 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 12:47:58.510927 Total UI for P1: 0, mck2ui 16
5842 12:47:58.514414 best dqsien dly found for B0: ( 1, 2, 28)
5843 12:47:58.517686 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5844 12:47:58.520822 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5845 12:47:58.521248
5846 12:47:58.524129 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5847 12:47:58.527776 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5848 12:47:58.530563 [Gating] SW calibration Done
5849 12:47:58.531097 ==
5850 12:47:58.534116 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 12:47:58.540476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 12:47:58.541013 ==
5853 12:47:58.541457 RX Vref Scan: 0
5854 12:47:58.541815
5855 12:47:58.543938 RX Vref 0 -> 0, step: 1
5856 12:47:58.544420
5857 12:47:58.547205 RX Delay -80 -> 252, step: 8
5858 12:47:58.550474 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5859 12:47:58.554201 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5860 12:47:58.557697 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5861 12:47:58.560471 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5862 12:47:58.567111 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5863 12:47:58.570046 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5864 12:47:58.574109 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5865 12:47:58.577079 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5866 12:47:58.580446 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5867 12:47:58.587142 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5868 12:47:58.589912 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5869 12:47:58.593596 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5870 12:47:58.596970 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5871 12:47:58.600331 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5872 12:47:58.603537 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5873 12:47:58.610175 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5874 12:47:58.610662 ==
5875 12:47:58.613013 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 12:47:58.616844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 12:47:58.617342 ==
5878 12:47:58.617751 DQS Delay:
5879 12:47:58.620095 DQS0 = 0, DQS1 = 0
5880 12:47:58.620625 DQM Delay:
5881 12:47:58.623623 DQM0 = 100, DQM1 = 91
5882 12:47:58.624090 DQ Delay:
5883 12:47:58.627539 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5884 12:47:58.629583 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5885 12:47:58.632856 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =87
5886 12:47:58.636434 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5887 12:47:58.637005
5888 12:47:58.637375
5889 12:47:58.637723 ==
5890 12:47:58.639729 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 12:47:58.646054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 12:47:58.646504 ==
5893 12:47:58.646836
5894 12:47:58.647146
5895 12:47:58.647441 TX Vref Scan disable
5896 12:47:58.649362 == TX Byte 0 ==
5897 12:47:58.653088 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5898 12:47:58.659409 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5899 12:47:58.659964 == TX Byte 1 ==
5900 12:47:58.662698 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5901 12:47:58.669231 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5902 12:47:58.669691 ==
5903 12:47:58.672680 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 12:47:58.676272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 12:47:58.676750 ==
5906 12:47:58.677093
5907 12:47:58.677409
5908 12:47:58.679527 TX Vref Scan disable
5909 12:47:58.679963 == TX Byte 0 ==
5910 12:47:58.685555 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5911 12:47:58.688967 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5912 12:47:58.693072 == TX Byte 1 ==
5913 12:47:58.695430 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5914 12:47:58.698853 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5915 12:47:58.699359
5916 12:47:58.699824 [DATLAT]
5917 12:47:58.702149 Freq=933, CH1 RK1
5918 12:47:58.702606
5919 12:47:58.702940 DATLAT Default: 0xb
5920 12:47:58.705524 0, 0xFFFF, sum = 0
5921 12:47:58.708810 1, 0xFFFF, sum = 0
5922 12:47:58.709240 2, 0xFFFF, sum = 0
5923 12:47:58.712438 3, 0xFFFF, sum = 0
5924 12:47:58.712910 4, 0xFFFF, sum = 0
5925 12:47:58.715117 5, 0xFFFF, sum = 0
5926 12:47:58.715588 6, 0xFFFF, sum = 0
5927 12:47:58.718985 7, 0xFFFF, sum = 0
5928 12:47:58.719460 8, 0xFFFF, sum = 0
5929 12:47:58.722063 9, 0xFFFF, sum = 0
5930 12:47:58.722519 10, 0x0, sum = 1
5931 12:47:58.725044 11, 0x0, sum = 2
5932 12:47:58.725526 12, 0x0, sum = 3
5933 12:47:58.728687 13, 0x0, sum = 4
5934 12:47:58.729123 best_step = 11
5935 12:47:58.729456
5936 12:47:58.729768 ==
5937 12:47:58.732213 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 12:47:58.735049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 12:47:58.738453 ==
5940 12:47:58.738920 RX Vref Scan: 0
5941 12:47:58.739279
5942 12:47:58.741567 RX Vref 0 -> 0, step: 1
5943 12:47:58.742006
5944 12:47:58.745358 RX Delay -61 -> 252, step: 4
5945 12:47:58.748029 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5946 12:47:58.751663 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5947 12:47:58.758413 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
5948 12:47:58.761887 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5949 12:47:58.764654 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5950 12:47:58.768191 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5951 12:47:58.771212 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5952 12:47:58.774687 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5953 12:47:58.781381 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5954 12:47:58.784794 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5955 12:47:58.788434 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5956 12:47:58.790824 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5957 12:47:58.794286 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5958 12:47:58.800970 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
5959 12:47:58.804245 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
5960 12:47:58.807293 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5961 12:47:58.807715 ==
5962 12:47:58.810678 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 12:47:58.814517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 12:47:58.818160 ==
5965 12:47:58.818602 DQS Delay:
5966 12:47:58.818936 DQS0 = 0, DQS1 = 0
5967 12:47:58.821316 DQM Delay:
5968 12:47:58.821798 DQM0 = 101, DQM1 = 93
5969 12:47:58.824202 DQ Delay:
5970 12:47:58.827583 DQ0 =106, DQ1 =96, DQ2 =88, DQ3 =98
5971 12:47:58.831089 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
5972 12:47:58.834827 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
5973 12:47:58.837165 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5974 12:47:58.837605
5975 12:47:58.838043
5976 12:47:58.844007 [DQSOSCAuto] RK1, (LSB)MR18= 0x802, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5977 12:47:58.847138 CH1 RK1: MR19=505, MR18=802
5978 12:47:58.853534 CH1_RK1: MR19=0x505, MR18=0x802, DQSOSC=419, MR23=63, INC=61, DEC=41
5979 12:47:58.857019 [RxdqsGatingPostProcess] freq 933
5980 12:47:58.860839 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5981 12:47:58.863921 best DQS0 dly(2T, 0.5T) = (0, 10)
5982 12:47:58.867278 best DQS1 dly(2T, 0.5T) = (0, 10)
5983 12:47:58.870711 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5984 12:47:58.873528 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5985 12:47:58.877108 best DQS0 dly(2T, 0.5T) = (0, 10)
5986 12:47:58.880329 best DQS1 dly(2T, 0.5T) = (0, 10)
5987 12:47:58.884049 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5988 12:47:58.886786 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5989 12:47:58.890180 Pre-setting of DQS Precalculation
5990 12:47:58.893692 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5991 12:47:58.903376 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5992 12:47:58.910061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5993 12:47:58.910490
5994 12:47:58.910829
5995 12:47:58.913496 [Calibration Summary] 1866 Mbps
5996 12:47:58.913924 CH 0, Rank 0
5997 12:47:58.916322 SW Impedance : PASS
5998 12:47:58.919965 DUTY Scan : NO K
5999 12:47:58.920392 ZQ Calibration : PASS
6000 12:47:58.922753 Jitter Meter : NO K
6001 12:47:58.923182 CBT Training : PASS
6002 12:47:58.926075 Write leveling : PASS
6003 12:47:58.929726 RX DQS gating : PASS
6004 12:47:58.930095 RX DQ/DQS(RDDQC) : PASS
6005 12:47:58.932917 TX DQ/DQS : PASS
6006 12:47:58.936162 RX DATLAT : PASS
6007 12:47:58.936607 RX DQ/DQS(Engine): PASS
6008 12:47:58.939669 TX OE : NO K
6009 12:47:58.940094 All Pass.
6010 12:47:58.940434
6011 12:47:58.943127 CH 0, Rank 1
6012 12:47:58.943552 SW Impedance : PASS
6013 12:47:58.946147 DUTY Scan : NO K
6014 12:47:58.949748 ZQ Calibration : PASS
6015 12:47:58.950173 Jitter Meter : NO K
6016 12:47:58.952673 CBT Training : PASS
6017 12:47:58.955769 Write leveling : PASS
6018 12:47:58.956193 RX DQS gating : PASS
6019 12:47:58.959051 RX DQ/DQS(RDDQC) : PASS
6020 12:47:58.962488 TX DQ/DQS : PASS
6021 12:47:58.962917 RX DATLAT : PASS
6022 12:47:58.965591 RX DQ/DQS(Engine): PASS
6023 12:47:58.968902 TX OE : NO K
6024 12:47:58.969327 All Pass.
6025 12:47:58.969666
6026 12:47:58.969983 CH 1, Rank 0
6027 12:47:58.972396 SW Impedance : PASS
6028 12:47:58.975469 DUTY Scan : NO K
6029 12:47:58.975892 ZQ Calibration : PASS
6030 12:47:58.978751 Jitter Meter : NO K
6031 12:47:58.982192 CBT Training : PASS
6032 12:47:58.982618 Write leveling : PASS
6033 12:47:58.985168 RX DQS gating : PASS
6034 12:47:58.988704 RX DQ/DQS(RDDQC) : PASS
6035 12:47:58.989129 TX DQ/DQS : PASS
6036 12:47:58.992246 RX DATLAT : PASS
6037 12:47:58.995233 RX DQ/DQS(Engine): PASS
6038 12:47:58.995657 TX OE : NO K
6039 12:47:58.998202 All Pass.
6040 12:47:58.998653
6041 12:47:58.999002 CH 1, Rank 1
6042 12:47:59.001931 SW Impedance : PASS
6043 12:47:59.002376 DUTY Scan : NO K
6044 12:47:59.005033 ZQ Calibration : PASS
6045 12:47:59.008197 Jitter Meter : NO K
6046 12:47:59.008642 CBT Training : PASS
6047 12:47:59.011697 Write leveling : PASS
6048 12:47:59.015029 RX DQS gating : PASS
6049 12:47:59.015455 RX DQ/DQS(RDDQC) : PASS
6050 12:47:59.017961 TX DQ/DQS : PASS
6051 12:47:59.021215 RX DATLAT : PASS
6052 12:47:59.021643 RX DQ/DQS(Engine): PASS
6053 12:47:59.024496 TX OE : NO K
6054 12:47:59.024957 All Pass.
6055 12:47:59.025297
6056 12:47:59.028232 DramC Write-DBI off
6057 12:47:59.031496 PER_BANK_REFRESH: Hybrid Mode
6058 12:47:59.031921 TX_TRACKING: ON
6059 12:47:59.041348 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6060 12:47:59.044687 [FAST_K] Save calibration result to emmc
6061 12:47:59.047934 dramc_set_vcore_voltage set vcore to 650000
6062 12:47:59.051012 Read voltage for 400, 6
6063 12:47:59.051436 Vio18 = 0
6064 12:47:59.051776 Vcore = 650000
6065 12:47:59.054185 Vdram = 0
6066 12:47:59.054612 Vddq = 0
6067 12:47:59.054952 Vmddr = 0
6068 12:47:59.061115 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6069 12:47:59.063943 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6070 12:47:59.067829 MEM_TYPE=3, freq_sel=20
6071 12:47:59.070726 sv_algorithm_assistance_LP4_800
6072 12:47:59.074524 ============ PULL DRAM RESETB DOWN ============
6073 12:47:59.077781 ========== PULL DRAM RESETB DOWN end =========
6074 12:47:59.084284 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6075 12:47:59.087364 ===================================
6076 12:47:59.090657 LPDDR4 DRAM CONFIGURATION
6077 12:47:59.091163 ===================================
6078 12:47:59.094310 EX_ROW_EN[0] = 0x0
6079 12:47:59.097676 EX_ROW_EN[1] = 0x0
6080 12:47:59.098101 LP4Y_EN = 0x0
6081 12:47:59.101040 WORK_FSP = 0x0
6082 12:47:59.101467 WL = 0x2
6083 12:47:59.103686 RL = 0x2
6084 12:47:59.104112 BL = 0x2
6085 12:47:59.107222 RPST = 0x0
6086 12:47:59.107648 RD_PRE = 0x0
6087 12:47:59.110494 WR_PRE = 0x1
6088 12:47:59.110919 WR_PST = 0x0
6089 12:47:59.113768 DBI_WR = 0x0
6090 12:47:59.114191 DBI_RD = 0x0
6091 12:47:59.117060 OTF = 0x1
6092 12:47:59.120252 ===================================
6093 12:47:59.123405 ===================================
6094 12:47:59.123833 ANA top config
6095 12:47:59.126754 ===================================
6096 12:47:59.130134 DLL_ASYNC_EN = 0
6097 12:47:59.133688 ALL_SLAVE_EN = 1
6098 12:47:59.136799 NEW_RANK_MODE = 1
6099 12:47:59.137229 DLL_IDLE_MODE = 1
6100 12:47:59.140577 LP45_APHY_COMB_EN = 1
6101 12:47:59.143259 TX_ODT_DIS = 1
6102 12:47:59.146797 NEW_8X_MODE = 1
6103 12:47:59.149860 ===================================
6104 12:47:59.153676 ===================================
6105 12:47:59.156619 data_rate = 800
6106 12:47:59.160254 CKR = 1
6107 12:47:59.160716 DQ_P2S_RATIO = 4
6108 12:47:59.163400 ===================================
6109 12:47:59.166472 CA_P2S_RATIO = 4
6110 12:47:59.169960 DQ_CA_OPEN = 0
6111 12:47:59.172766 DQ_SEMI_OPEN = 1
6112 12:47:59.176462 CA_SEMI_OPEN = 1
6113 12:47:59.179821 CA_FULL_RATE = 0
6114 12:47:59.180248 DQ_CKDIV4_EN = 0
6115 12:47:59.183107 CA_CKDIV4_EN = 1
6116 12:47:59.186324 CA_PREDIV_EN = 0
6117 12:47:59.189612 PH8_DLY = 0
6118 12:47:59.193183 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6119 12:47:59.196032 DQ_AAMCK_DIV = 0
6120 12:47:59.196457 CA_AAMCK_DIV = 0
6121 12:47:59.199430 CA_ADMCK_DIV = 4
6122 12:47:59.202982 DQ_TRACK_CA_EN = 0
6123 12:47:59.206515 CA_PICK = 800
6124 12:47:59.210196 CA_MCKIO = 400
6125 12:47:59.212845 MCKIO_SEMI = 400
6126 12:47:59.215829 PLL_FREQ = 3016
6127 12:47:59.219310 DQ_UI_PI_RATIO = 32
6128 12:47:59.219741 CA_UI_PI_RATIO = 32
6129 12:47:59.223303 ===================================
6130 12:47:59.225956 ===================================
6131 12:47:59.229548 memory_type:LPDDR4
6132 12:47:59.232280 GP_NUM : 10
6133 12:47:59.232737 SRAM_EN : 1
6134 12:47:59.235988 MD32_EN : 0
6135 12:47:59.239076 ===================================
6136 12:47:59.242510 [ANA_INIT] >>>>>>>>>>>>>>
6137 12:47:59.245709 <<<<<< [CONFIGURE PHASE]: ANA_TX
6138 12:47:59.248917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6139 12:47:59.252330 ===================================
6140 12:47:59.252786 data_rate = 800,PCW = 0X7400
6141 12:47:59.256752 ===================================
6142 12:47:59.258979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6143 12:47:59.265580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 12:47:59.278644 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6145 12:47:59.282447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6146 12:47:59.285263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6147 12:47:59.289124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6148 12:47:59.291868 [ANA_INIT] flow start
6149 12:47:59.292431 [ANA_INIT] PLL >>>>>>>>
6150 12:47:59.295440 [ANA_INIT] PLL <<<<<<<<
6151 12:47:59.298245 [ANA_INIT] MIDPI >>>>>>>>
6152 12:47:59.301809 [ANA_INIT] MIDPI <<<<<<<<
6153 12:47:59.302291 [ANA_INIT] DLL >>>>>>>>
6154 12:47:59.304850 [ANA_INIT] flow end
6155 12:47:59.308320 ============ LP4 DIFF to SE enter ============
6156 12:47:59.311492 ============ LP4 DIFF to SE exit ============
6157 12:47:59.314992 [ANA_INIT] <<<<<<<<<<<<<
6158 12:47:59.317968 [Flow] Enable top DCM control >>>>>
6159 12:47:59.321218 [Flow] Enable top DCM control <<<<<
6160 12:47:59.325193 Enable DLL master slave shuffle
6161 12:47:59.331260 ==============================================================
6162 12:47:59.331725 Gating Mode config
6163 12:47:59.338385 ==============================================================
6164 12:47:59.339043 Config description:
6165 12:47:59.348138 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6166 12:47:59.354516 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6167 12:47:59.360801 SELPH_MODE 0: By rank 1: By Phase
6168 12:47:59.364464 ==============================================================
6169 12:47:59.367942 GAT_TRACK_EN = 0
6170 12:47:59.371019 RX_GATING_MODE = 2
6171 12:47:59.374364 RX_GATING_TRACK_MODE = 2
6172 12:47:59.377762 SELPH_MODE = 1
6173 12:47:59.381163 PICG_EARLY_EN = 1
6174 12:47:59.383984 VALID_LAT_VALUE = 1
6175 12:47:59.390956 ==============================================================
6176 12:47:59.394458 Enter into Gating configuration >>>>
6177 12:47:59.397739 Exit from Gating configuration <<<<
6178 12:47:59.401092 Enter into DVFS_PRE_config >>>>>
6179 12:47:59.410627 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6180 12:47:59.413962 Exit from DVFS_PRE_config <<<<<
6181 12:47:59.417291 Enter into PICG configuration >>>>
6182 12:47:59.420774 Exit from PICG configuration <<<<
6183 12:47:59.424097 [RX_INPUT] configuration >>>>>
6184 12:47:59.424601 [RX_INPUT] configuration <<<<<
6185 12:47:59.430708 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6186 12:47:59.437406 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6187 12:47:59.440781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 12:47:59.446944 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 12:47:59.453647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 12:47:59.460716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 12:47:59.463444 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6192 12:47:59.466767 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6193 12:47:59.473381 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6194 12:47:59.476497 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6195 12:47:59.480019 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6196 12:47:59.487145 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 12:47:59.489649 ===================================
6198 12:47:59.490124 LPDDR4 DRAM CONFIGURATION
6199 12:47:59.493019 ===================================
6200 12:47:59.496603 EX_ROW_EN[0] = 0x0
6201 12:47:59.499590 EX_ROW_EN[1] = 0x0
6202 12:47:59.500102 LP4Y_EN = 0x0
6203 12:47:59.503345 WORK_FSP = 0x0
6204 12:47:59.503918 WL = 0x2
6205 12:47:59.506554 RL = 0x2
6206 12:47:59.507126 BL = 0x2
6207 12:47:59.509794 RPST = 0x0
6208 12:47:59.510263 RD_PRE = 0x0
6209 12:47:59.513297 WR_PRE = 0x1
6210 12:47:59.513758 WR_PST = 0x0
6211 12:47:59.516331 DBI_WR = 0x0
6212 12:47:59.516833 DBI_RD = 0x0
6213 12:47:59.519699 OTF = 0x1
6214 12:47:59.522854 ===================================
6215 12:47:59.526093 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6216 12:47:59.530060 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6217 12:47:59.536134 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6218 12:47:59.539555 ===================================
6219 12:47:59.540022 LPDDR4 DRAM CONFIGURATION
6220 12:47:59.542494 ===================================
6221 12:47:59.545703 EX_ROW_EN[0] = 0x10
6222 12:47:59.549439 EX_ROW_EN[1] = 0x0
6223 12:47:59.549858 LP4Y_EN = 0x0
6224 12:47:59.552390 WORK_FSP = 0x0
6225 12:47:59.552860 WL = 0x2
6226 12:47:59.555506 RL = 0x2
6227 12:47:59.555973 BL = 0x2
6228 12:47:59.559573 RPST = 0x0
6229 12:47:59.560035 RD_PRE = 0x0
6230 12:47:59.562096 WR_PRE = 0x1
6231 12:47:59.562547 WR_PST = 0x0
6232 12:47:59.565723 DBI_WR = 0x0
6233 12:47:59.566137 DBI_RD = 0x0
6234 12:47:59.569150 OTF = 0x1
6235 12:47:59.572332 ===================================
6236 12:47:59.579013 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6237 12:47:59.582141 nWR fixed to 30
6238 12:47:59.585283 [ModeRegInit_LP4] CH0 RK0
6239 12:47:59.585867 [ModeRegInit_LP4] CH0 RK1
6240 12:47:59.588467 [ModeRegInit_LP4] CH1 RK0
6241 12:47:59.592167 [ModeRegInit_LP4] CH1 RK1
6242 12:47:59.592680 match AC timing 19
6243 12:47:59.598300 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6244 12:47:59.602534 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6245 12:47:59.605345 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6246 12:47:59.612068 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6247 12:47:59.615029 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6248 12:47:59.615612 ==
6249 12:47:59.618912 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 12:47:59.621654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 12:47:59.622278 ==
6252 12:47:59.628059 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6253 12:47:59.635075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6254 12:47:59.637979 [CA 0] Center 36 (8~64) winsize 57
6255 12:47:59.641488 [CA 1] Center 36 (8~64) winsize 57
6256 12:47:59.644758 [CA 2] Center 36 (8~64) winsize 57
6257 12:47:59.648311 [CA 3] Center 36 (8~64) winsize 57
6258 12:47:59.648919 [CA 4] Center 36 (8~64) winsize 57
6259 12:47:59.651092 [CA 5] Center 36 (8~64) winsize 57
6260 12:47:59.651555
6261 12:47:59.658344 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6262 12:47:59.658856
6263 12:47:59.661347 [CATrainingPosCal] consider 1 rank data
6264 12:47:59.665020 u2DelayCellTimex100 = 270/100 ps
6265 12:47:59.668414 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 12:47:59.671497 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 12:47:59.674939 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 12:47:59.677920 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:47:59.681426 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:47:59.684930 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 12:47:59.685531
6272 12:47:59.687975 CA PerBit enable=1, Macro0, CA PI delay=36
6273 12:47:59.688585
6274 12:47:59.690910 [CBTSetCACLKResult] CA Dly = 36
6275 12:47:59.694129 CS Dly: 1 (0~32)
6276 12:47:59.694645 ==
6277 12:47:59.697563 Dram Type= 6, Freq= 0, CH_0, rank 1
6278 12:47:59.701255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 12:47:59.701734 ==
6280 12:47:59.707318 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 12:47:59.714262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6282 12:47:59.717298 [CA 0] Center 36 (8~64) winsize 57
6283 12:47:59.720940 [CA 1] Center 36 (8~64) winsize 57
6284 12:47:59.723774 [CA 2] Center 36 (8~64) winsize 57
6285 12:47:59.724230 [CA 3] Center 36 (8~64) winsize 57
6286 12:47:59.727265 [CA 4] Center 36 (8~64) winsize 57
6287 12:47:59.730867 [CA 5] Center 36 (8~64) winsize 57
6288 12:47:59.731416
6289 12:47:59.736890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6290 12:47:59.737482
6291 12:47:59.740940 [CATrainingPosCal] consider 2 rank data
6292 12:47:59.743515 u2DelayCellTimex100 = 270/100 ps
6293 12:47:59.746831 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 12:47:59.750236 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:47:59.753491 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:47:59.756798 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:47:59.759949 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:47:59.763346 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 12:47:59.763782
6300 12:47:59.766634 CA PerBit enable=1, Macro0, CA PI delay=36
6301 12:47:59.767043
6302 12:47:59.769959 [CBTSetCACLKResult] CA Dly = 36
6303 12:47:59.773595 CS Dly: 1 (0~32)
6304 12:47:59.774264
6305 12:47:59.776928 ----->DramcWriteLeveling(PI) begin...
6306 12:47:59.777331 ==
6307 12:47:59.780502 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 12:47:59.782975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 12:47:59.783386 ==
6310 12:47:59.786381 Write leveling (Byte 0): 40 => 8
6311 12:47:59.790146 Write leveling (Byte 1): 32 => 0
6312 12:47:59.792771 DramcWriteLeveling(PI) end<-----
6313 12:47:59.793177
6314 12:47:59.793497 ==
6315 12:47:59.796647 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 12:47:59.799832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 12:47:59.800244 ==
6318 12:47:59.802847 [Gating] SW mode calibration
6319 12:47:59.809502 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6320 12:47:59.816030 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6321 12:47:59.819256 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 12:47:59.826097 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6323 12:47:59.829078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 12:47:59.832348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6325 12:47:59.839034 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 12:47:59.842231 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 12:47:59.845631 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 12:47:59.851888 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 12:47:59.855206 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 12:47:59.858693 Total UI for P1: 0, mck2ui 16
6331 12:47:59.862102 best dqsien dly found for B0: ( 0, 14, 24)
6332 12:47:59.865257 Total UI for P1: 0, mck2ui 16
6333 12:47:59.868475 best dqsien dly found for B1: ( 0, 14, 24)
6334 12:47:59.872118 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6335 12:47:59.875140 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6336 12:47:59.875548
6337 12:47:59.879022 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 12:47:59.881583 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6339 12:47:59.885258 [Gating] SW calibration Done
6340 12:47:59.885667 ==
6341 12:47:59.888594 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 12:47:59.891932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 12:47:59.894833 ==
6344 12:47:59.895245 RX Vref Scan: 0
6345 12:47:59.895572
6346 12:47:59.898308 RX Vref 0 -> 0, step: 1
6347 12:47:59.898719
6348 12:47:59.901270 RX Delay -410 -> 252, step: 16
6349 12:47:59.904953 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6350 12:47:59.908321 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6351 12:47:59.911567 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6352 12:47:59.918241 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6353 12:47:59.921296 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6354 12:47:59.924928 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6355 12:47:59.931554 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6356 12:47:59.934875 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6357 12:47:59.938053 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6358 12:47:59.941421 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6359 12:47:59.947768 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6360 12:47:59.951437 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6361 12:47:59.954369 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6362 12:47:59.957531 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6363 12:47:59.964392 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6364 12:47:59.967957 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6365 12:47:59.968420 ==
6366 12:47:59.970584 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 12:47:59.974063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 12:47:59.974528 ==
6369 12:47:59.977670 DQS Delay:
6370 12:47:59.978099 DQS0 = 43, DQS1 = 59
6371 12:47:59.980433 DQM Delay:
6372 12:47:59.980893 DQM0 = 9, DQM1 = 11
6373 12:47:59.981228 DQ Delay:
6374 12:47:59.984054 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6375 12:47:59.987319 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6376 12:47:59.991211 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6377 12:47:59.993940 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6378 12:47:59.994364
6379 12:47:59.994699
6380 12:47:59.995006 ==
6381 12:47:59.996965 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 12:48:00.004214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 12:48:00.004669 ==
6384 12:48:00.005012
6385 12:48:00.005325
6386 12:48:00.005624 TX Vref Scan disable
6387 12:48:00.007025 == TX Byte 0 ==
6388 12:48:00.010500 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 12:48:00.013720 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 12:48:00.017045 == TX Byte 1 ==
6391 12:48:00.020680 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6392 12:48:00.023759 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6393 12:48:00.027340 ==
6394 12:48:00.027765 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 12:48:00.033413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 12:48:00.033884 ==
6397 12:48:00.034260
6398 12:48:00.034604
6399 12:48:00.037099 TX Vref Scan disable
6400 12:48:00.037678 == TX Byte 0 ==
6401 12:48:00.039959 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 12:48:00.047347 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 12:48:00.047920 == TX Byte 1 ==
6404 12:48:00.050070 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6405 12:48:00.056576 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6406 12:48:00.057047
6407 12:48:00.057421 [DATLAT]
6408 12:48:00.057772 Freq=400, CH0 RK0
6409 12:48:00.058127
6410 12:48:00.060121 DATLAT Default: 0xf
6411 12:48:00.063320 0, 0xFFFF, sum = 0
6412 12:48:00.063823 1, 0xFFFF, sum = 0
6413 12:48:00.066075 2, 0xFFFF, sum = 0
6414 12:48:00.066548 3, 0xFFFF, sum = 0
6415 12:48:00.069676 4, 0xFFFF, sum = 0
6416 12:48:00.070151 5, 0xFFFF, sum = 0
6417 12:48:00.073132 6, 0xFFFF, sum = 0
6418 12:48:00.073559 7, 0xFFFF, sum = 0
6419 12:48:00.076459 8, 0xFFFF, sum = 0
6420 12:48:00.076916 9, 0xFFFF, sum = 0
6421 12:48:00.079813 10, 0xFFFF, sum = 0
6422 12:48:00.080239 11, 0xFFFF, sum = 0
6423 12:48:00.082746 12, 0xFFFF, sum = 0
6424 12:48:00.083179 13, 0x0, sum = 1
6425 12:48:00.086087 14, 0x0, sum = 2
6426 12:48:00.086515 15, 0x0, sum = 3
6427 12:48:00.089599 16, 0x0, sum = 4
6428 12:48:00.090026 best_step = 14
6429 12:48:00.090358
6430 12:48:00.090667 ==
6431 12:48:00.092943 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 12:48:00.099498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 12:48:00.099927 ==
6434 12:48:00.100266 RX Vref Scan: 1
6435 12:48:00.100630
6436 12:48:00.102511 RX Vref 0 -> 0, step: 1
6437 12:48:00.103117
6438 12:48:00.106206 RX Delay -359 -> 252, step: 8
6439 12:48:00.106628
6440 12:48:00.109095 Set Vref, RX VrefLevel [Byte0]: 60
6441 12:48:00.112600 [Byte1]: 54
6442 12:48:00.113035
6443 12:48:00.115653 Final RX Vref Byte 0 = 60 to rank0
6444 12:48:00.119180 Final RX Vref Byte 1 = 54 to rank0
6445 12:48:00.122433 Final RX Vref Byte 0 = 60 to rank1
6446 12:48:00.125704 Final RX Vref Byte 1 = 54 to rank1==
6447 12:48:00.128735 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 12:48:00.135415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 12:48:00.135840 ==
6450 12:48:00.136181 DQS Delay:
6451 12:48:00.139470 DQS0 = 48, DQS1 = 60
6452 12:48:00.139891 DQM Delay:
6453 12:48:00.140226 DQM0 = 11, DQM1 = 11
6454 12:48:00.142449 DQ Delay:
6455 12:48:00.145796 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6456 12:48:00.146218 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6457 12:48:00.148817 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6458 12:48:00.152185 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6459 12:48:00.152644
6460 12:48:00.155188
6461 12:48:00.162438 [DQSOSCAuto] RK0, (LSB)MR18= 0xb377, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6462 12:48:00.165565 CH0 RK0: MR19=C0C, MR18=B377
6463 12:48:00.172258 CH0_RK0: MR19=0xC0C, MR18=0xB377, DQSOSC=387, MR23=63, INC=394, DEC=262
6464 12:48:00.172709 ==
6465 12:48:00.175598 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 12:48:00.178576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 12:48:00.179004 ==
6468 12:48:00.182106 [Gating] SW mode calibration
6469 12:48:00.188926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6470 12:48:00.195226 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6471 12:48:00.198575 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 12:48:00.201746 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6473 12:48:00.208666 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 12:48:00.211676 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6475 12:48:00.214927 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 12:48:00.221606 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 12:48:00.225119 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 12:48:00.227815 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 12:48:00.234873 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 12:48:00.235471 Total UI for P1: 0, mck2ui 16
6481 12:48:00.241082 best dqsien dly found for B0: ( 0, 14, 24)
6482 12:48:00.241710 Total UI for P1: 0, mck2ui 16
6483 12:48:00.247842 best dqsien dly found for B1: ( 0, 14, 24)
6484 12:48:00.251122 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6485 12:48:00.254281 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6486 12:48:00.254755
6487 12:48:00.257477 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 12:48:00.260859 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6489 12:48:00.264178 [Gating] SW calibration Done
6490 12:48:00.264809 ==
6491 12:48:00.267566 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 12:48:00.270865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 12:48:00.271322 ==
6494 12:48:00.274222 RX Vref Scan: 0
6495 12:48:00.274642
6496 12:48:00.274979 RX Vref 0 -> 0, step: 1
6497 12:48:00.277598
6498 12:48:00.278018 RX Delay -410 -> 252, step: 16
6499 12:48:00.284287 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6500 12:48:00.287207 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6501 12:48:00.290947 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6502 12:48:00.293791 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6503 12:48:00.300484 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6504 12:48:00.303773 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6505 12:48:00.307012 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6506 12:48:00.310619 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6507 12:48:00.316811 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6508 12:48:00.320086 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6509 12:48:00.323387 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6510 12:48:00.330117 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6511 12:48:00.332910 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6512 12:48:00.336646 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6513 12:48:00.339742 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6514 12:48:00.346750 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6515 12:48:00.346933 ==
6516 12:48:00.349950 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 12:48:00.352692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 12:48:00.352778 ==
6519 12:48:00.352863 DQS Delay:
6520 12:48:00.355818 DQS0 = 35, DQS1 = 59
6521 12:48:00.355941 DQM Delay:
6522 12:48:00.359244 DQM0 = 3, DQM1 = 17
6523 12:48:00.359329 DQ Delay:
6524 12:48:00.362871 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6525 12:48:00.365647 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6526 12:48:00.369350 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6527 12:48:00.372678 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6528 12:48:00.372763
6529 12:48:00.372849
6530 12:48:00.372929 ==
6531 12:48:00.376346 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 12:48:00.379589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 12:48:00.379765 ==
6534 12:48:00.379878
6535 12:48:00.382698
6536 12:48:00.382868 TX Vref Scan disable
6537 12:48:00.386118 == TX Byte 0 ==
6538 12:48:00.388703 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6539 12:48:00.392058 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6540 12:48:00.395843 == TX Byte 1 ==
6541 12:48:00.399170 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6542 12:48:00.402248 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6543 12:48:00.402390 ==
6544 12:48:00.405802 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 12:48:00.408897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 12:48:00.412325 ==
6547 12:48:00.412612
6548 12:48:00.412781
6549 12:48:00.412921 TX Vref Scan disable
6550 12:48:00.415368 == TX Byte 0 ==
6551 12:48:00.419138 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6552 12:48:00.422073 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6553 12:48:00.425621 == TX Byte 1 ==
6554 12:48:00.429046 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6555 12:48:00.432550 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6556 12:48:00.433060
6557 12:48:00.433378 [DATLAT]
6558 12:48:00.435237 Freq=400, CH0 RK1
6559 12:48:00.435627
6560 12:48:00.439048 DATLAT Default: 0xe
6561 12:48:00.439641 0, 0xFFFF, sum = 0
6562 12:48:00.442296 1, 0xFFFF, sum = 0
6563 12:48:00.442996 2, 0xFFFF, sum = 0
6564 12:48:00.445408 3, 0xFFFF, sum = 0
6565 12:48:00.446278 4, 0xFFFF, sum = 0
6566 12:48:00.448402 5, 0xFFFF, sum = 0
6567 12:48:00.449259 6, 0xFFFF, sum = 0
6568 12:48:00.451821 7, 0xFFFF, sum = 0
6569 12:48:00.452691 8, 0xFFFF, sum = 0
6570 12:48:00.455258 9, 0xFFFF, sum = 0
6571 12:48:00.456115 10, 0xFFFF, sum = 0
6572 12:48:00.458643 11, 0xFFFF, sum = 0
6573 12:48:00.459478 12, 0xFFFF, sum = 0
6574 12:48:00.461647 13, 0x0, sum = 1
6575 12:48:00.462474 14, 0x0, sum = 2
6576 12:48:00.465205 15, 0x0, sum = 3
6577 12:48:00.466002 16, 0x0, sum = 4
6578 12:48:00.468609 best_step = 14
6579 12:48:00.468938
6580 12:48:00.469202 ==
6581 12:48:00.471795 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 12:48:00.475125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 12:48:00.475460 ==
6584 12:48:00.478034 RX Vref Scan: 0
6585 12:48:00.478363
6586 12:48:00.478626 RX Vref 0 -> 0, step: 1
6587 12:48:00.478877
6588 12:48:00.481400 RX Delay -359 -> 252, step: 8
6589 12:48:00.489536 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6590 12:48:00.492811 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6591 12:48:00.496028 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6592 12:48:00.502634 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6593 12:48:00.506037 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6594 12:48:00.509605 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6595 12:48:00.512890 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6596 12:48:00.519458 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6597 12:48:00.522446 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6598 12:48:00.526138 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6599 12:48:00.529416 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6600 12:48:00.535943 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6601 12:48:00.539401 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6602 12:48:00.542253 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6603 12:48:00.545629 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6604 12:48:00.552730 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6605 12:48:00.553209 ==
6606 12:48:00.555771 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 12:48:00.558742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 12:48:00.559246 ==
6609 12:48:00.559627 DQS Delay:
6610 12:48:00.562278 DQS0 = 44, DQS1 = 60
6611 12:48:00.562774 DQM Delay:
6612 12:48:00.565516 DQM0 = 8, DQM1 = 14
6613 12:48:00.566066 DQ Delay:
6614 12:48:00.569052 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6615 12:48:00.572103 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6616 12:48:00.575111 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6617 12:48:00.578611 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6618 12:48:00.579083
6619 12:48:00.579475
6620 12:48:00.585129 [DQSOSCAuto] RK1, (LSB)MR18= 0xb23f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6621 12:48:00.588481 CH0 RK1: MR19=C0C, MR18=B23F
6622 12:48:00.595229 CH0_RK1: MR19=0xC0C, MR18=0xB23F, DQSOSC=387, MR23=63, INC=394, DEC=262
6623 12:48:00.598374 [RxdqsGatingPostProcess] freq 400
6624 12:48:00.605230 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6625 12:48:00.608643 best DQS0 dly(2T, 0.5T) = (0, 10)
6626 12:48:00.611735 best DQS1 dly(2T, 0.5T) = (0, 10)
6627 12:48:00.615483 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6628 12:48:00.618583 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6629 12:48:00.619102 best DQS0 dly(2T, 0.5T) = (0, 10)
6630 12:48:00.621645 best DQS1 dly(2T, 0.5T) = (0, 10)
6631 12:48:00.625287 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6632 12:48:00.628404 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6633 12:48:00.631752 Pre-setting of DQS Precalculation
6634 12:48:00.638371 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6635 12:48:00.638885 ==
6636 12:48:00.642038 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 12:48:00.644624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 12:48:00.645082 ==
6639 12:48:00.651436 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6640 12:48:00.657941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6641 12:48:00.661698 [CA 0] Center 36 (8~64) winsize 57
6642 12:48:00.662126 [CA 1] Center 36 (8~64) winsize 57
6643 12:48:00.664916 [CA 2] Center 36 (8~64) winsize 57
6644 12:48:00.667877 [CA 3] Center 36 (8~64) winsize 57
6645 12:48:00.671253 [CA 4] Center 36 (8~64) winsize 57
6646 12:48:00.674694 [CA 5] Center 36 (8~64) winsize 57
6647 12:48:00.675165
6648 12:48:00.677555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6649 12:48:00.677992
6650 12:48:00.684347 [CATrainingPosCal] consider 1 rank data
6651 12:48:00.684815 u2DelayCellTimex100 = 270/100 ps
6652 12:48:00.691119 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 12:48:00.694252 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 12:48:00.697994 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 12:48:00.701102 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:48:00.704380 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:48:00.707620 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 12:48:00.708198
6659 12:48:00.710928 CA PerBit enable=1, Macro0, CA PI delay=36
6660 12:48:00.711397
6661 12:48:00.714408 [CBTSetCACLKResult] CA Dly = 36
6662 12:48:00.717724 CS Dly: 1 (0~32)
6663 12:48:00.718195 ==
6664 12:48:00.720782 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 12:48:00.724012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 12:48:00.724443 ==
6667 12:48:00.730839 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 12:48:00.733951 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6669 12:48:00.737161 [CA 0] Center 36 (8~64) winsize 57
6670 12:48:00.740168 [CA 1] Center 36 (8~64) winsize 57
6671 12:48:00.743768 [CA 2] Center 36 (8~64) winsize 57
6672 12:48:00.746815 [CA 3] Center 36 (8~64) winsize 57
6673 12:48:00.750204 [CA 4] Center 36 (8~64) winsize 57
6674 12:48:00.753551 [CA 5] Center 36 (8~64) winsize 57
6675 12:48:00.754060
6676 12:48:00.757127 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6677 12:48:00.757557
6678 12:48:00.760218 [CATrainingPosCal] consider 2 rank data
6679 12:48:00.763439 u2DelayCellTimex100 = 270/100 ps
6680 12:48:00.767188 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 12:48:00.773322 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:48:00.776490 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:48:00.780196 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:48:00.783026 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:48:00.786755 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 12:48:00.787183
6687 12:48:00.789891 CA PerBit enable=1, Macro0, CA PI delay=36
6688 12:48:00.790318
6689 12:48:00.793336 [CBTSetCACLKResult] CA Dly = 36
6690 12:48:00.797150 CS Dly: 1 (0~32)
6691 12:48:00.797575
6692 12:48:00.799781 ----->DramcWriteLeveling(PI) begin...
6693 12:48:00.800293 ==
6694 12:48:00.803068 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 12:48:00.806520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 12:48:00.806950 ==
6697 12:48:00.809880 Write leveling (Byte 0): 40 => 8
6698 12:48:00.813106 Write leveling (Byte 1): 32 => 0
6699 12:48:00.815952 DramcWriteLeveling(PI) end<-----
6700 12:48:00.816038
6701 12:48:00.816104 ==
6702 12:48:00.819755 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 12:48:00.823064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 12:48:00.823236 ==
6705 12:48:00.826037 [Gating] SW mode calibration
6706 12:48:00.832405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6707 12:48:00.839273 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6708 12:48:00.842358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 12:48:00.845808 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6710 12:48:00.852595 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 12:48:00.855753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6712 12:48:00.858911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 12:48:00.865830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 12:48:00.868980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 12:48:00.872586 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 12:48:00.879413 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 12:48:00.879904 Total UI for P1: 0, mck2ui 16
6718 12:48:00.885382 best dqsien dly found for B0: ( 0, 14, 24)
6719 12:48:00.885931 Total UI for P1: 0, mck2ui 16
6720 12:48:00.892350 best dqsien dly found for B1: ( 0, 14, 24)
6721 12:48:00.895641 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6722 12:48:00.898944 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6723 12:48:00.899520
6724 12:48:00.902004 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 12:48:00.905876 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6726 12:48:00.908964 [Gating] SW calibration Done
6727 12:48:00.909432 ==
6728 12:48:00.912494 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 12:48:00.915222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 12:48:00.915690 ==
6731 12:48:00.918973 RX Vref Scan: 0
6732 12:48:00.919545
6733 12:48:00.919923 RX Vref 0 -> 0, step: 1
6734 12:48:00.920273
6735 12:48:00.921829 RX Delay -410 -> 252, step: 16
6736 12:48:00.928380 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6737 12:48:00.932830 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6738 12:48:00.935429 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6739 12:48:00.938508 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6740 12:48:00.945701 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6741 12:48:00.948460 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6742 12:48:00.952107 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6743 12:48:00.955370 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6744 12:48:00.961497 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6745 12:48:00.964934 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6746 12:48:00.968324 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6747 12:48:00.975254 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6748 12:48:00.978270 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6749 12:48:00.981089 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6750 12:48:00.984495 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6751 12:48:00.991115 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6752 12:48:00.991584 ==
6753 12:48:00.995444 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 12:48:00.997633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 12:48:00.998103 ==
6756 12:48:00.998473 DQS Delay:
6757 12:48:01.001452 DQS0 = 43, DQS1 = 51
6758 12:48:01.001912 DQM Delay:
6759 12:48:01.004509 DQM0 = 11, DQM1 = 14
6760 12:48:01.005244 DQ Delay:
6761 12:48:01.008130 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6762 12:48:01.011020 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6763 12:48:01.014461 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6764 12:48:01.017979 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6765 12:48:01.018549
6766 12:48:01.018925
6767 12:48:01.019273 ==
6768 12:48:01.020793 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 12:48:01.024821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 12:48:01.025286 ==
6771 12:48:01.025654
6772 12:48:01.025994
6773 12:48:01.027699 TX Vref Scan disable
6774 12:48:01.031312 == TX Byte 0 ==
6775 12:48:01.034582 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 12:48:01.037510 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 12:48:01.040730 == TX Byte 1 ==
6778 12:48:01.044289 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6779 12:48:01.047669 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6780 12:48:01.048246 ==
6781 12:48:01.050672 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 12:48:01.054666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 12:48:01.057081 ==
6784 12:48:01.057548
6785 12:48:01.057916
6786 12:48:01.058258 TX Vref Scan disable
6787 12:48:01.060868 == TX Byte 0 ==
6788 12:48:01.063874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 12:48:01.067612 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 12:48:01.070700 == TX Byte 1 ==
6791 12:48:01.073347 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6792 12:48:01.077033 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6793 12:48:01.077603
6794 12:48:01.080213 [DATLAT]
6795 12:48:01.080935 Freq=400, CH1 RK0
6796 12:48:01.081327
6797 12:48:01.083392 DATLAT Default: 0xf
6798 12:48:01.083860 0, 0xFFFF, sum = 0
6799 12:48:01.086889 1, 0xFFFF, sum = 0
6800 12:48:01.087465 2, 0xFFFF, sum = 0
6801 12:48:01.090442 3, 0xFFFF, sum = 0
6802 12:48:01.091038 4, 0xFFFF, sum = 0
6803 12:48:01.093702 5, 0xFFFF, sum = 0
6804 12:48:01.094192 6, 0xFFFF, sum = 0
6805 12:48:01.096407 7, 0xFFFF, sum = 0
6806 12:48:01.096928 8, 0xFFFF, sum = 0
6807 12:48:01.099941 9, 0xFFFF, sum = 0
6808 12:48:01.103502 10, 0xFFFF, sum = 0
6809 12:48:01.104239 11, 0xFFFF, sum = 0
6810 12:48:01.106368 12, 0xFFFF, sum = 0
6811 12:48:01.106842 13, 0x0, sum = 1
6812 12:48:01.110586 14, 0x0, sum = 2
6813 12:48:01.111165 15, 0x0, sum = 3
6814 12:48:01.113837 16, 0x0, sum = 4
6815 12:48:01.114418 best_step = 14
6816 12:48:01.114792
6817 12:48:01.115138 ==
6818 12:48:01.116332 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 12:48:01.119383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 12:48:01.119853 ==
6821 12:48:01.122768 RX Vref Scan: 1
6822 12:48:01.123232
6823 12:48:01.126356 RX Vref 0 -> 0, step: 1
6824 12:48:01.126823
6825 12:48:01.127194 RX Delay -343 -> 252, step: 8
6826 12:48:01.127542
6827 12:48:01.129426 Set Vref, RX VrefLevel [Byte0]: 50
6828 12:48:01.132986 [Byte1]: 54
6829 12:48:01.138459
6830 12:48:01.138554 Final RX Vref Byte 0 = 50 to rank0
6831 12:48:01.141326 Final RX Vref Byte 1 = 54 to rank0
6832 12:48:01.144700 Final RX Vref Byte 0 = 50 to rank1
6833 12:48:01.148135 Final RX Vref Byte 1 = 54 to rank1==
6834 12:48:01.151178 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 12:48:01.158381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 12:48:01.158950 ==
6837 12:48:01.159331 DQS Delay:
6838 12:48:01.161369 DQS0 = 44, DQS1 = 56
6839 12:48:01.161854 DQM Delay:
6840 12:48:01.162191 DQM0 = 7, DQM1 = 12
6841 12:48:01.164770 DQ Delay:
6842 12:48:01.168045 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6843 12:48:01.171542 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6844 12:48:01.172116 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6845 12:48:01.175018 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6846 12:48:01.177678
6847 12:48:01.178150
6848 12:48:01.184214 [DQSOSCAuto] RK0, (LSB)MR18= 0x956b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6849 12:48:01.187806 CH1 RK0: MR19=C0C, MR18=956B
6850 12:48:01.194112 CH1_RK0: MR19=0xC0C, MR18=0x956B, DQSOSC=391, MR23=63, INC=386, DEC=257
6851 12:48:01.194583 ==
6852 12:48:01.197644 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 12:48:01.200883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 12:48:01.201358 ==
6855 12:48:01.204091 [Gating] SW mode calibration
6856 12:48:01.210758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6857 12:48:01.217874 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6858 12:48:01.220579 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 12:48:01.223641 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6860 12:48:01.230379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 12:48:01.233848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6862 12:48:01.236860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 12:48:01.243926 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 12:48:01.246915 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 12:48:01.250184 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 12:48:01.256729 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 12:48:01.257250 Total UI for P1: 0, mck2ui 16
6868 12:48:01.263913 best dqsien dly found for B0: ( 0, 14, 24)
6869 12:48:01.264335 Total UI for P1: 0, mck2ui 16
6870 12:48:01.270380 best dqsien dly found for B1: ( 0, 14, 24)
6871 12:48:01.273678 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6872 12:48:01.276637 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6873 12:48:01.277060
6874 12:48:01.280240 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 12:48:01.283633 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6876 12:48:01.286593 [Gating] SW calibration Done
6877 12:48:01.287017 ==
6878 12:48:01.289742 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 12:48:01.293232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 12:48:01.293661 ==
6881 12:48:01.296209 RX Vref Scan: 0
6882 12:48:01.296655
6883 12:48:01.296993 RX Vref 0 -> 0, step: 1
6884 12:48:01.297310
6885 12:48:01.299867 RX Delay -410 -> 252, step: 16
6886 12:48:01.306598 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6887 12:48:01.310201 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6888 12:48:01.312878 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6889 12:48:01.316468 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6890 12:48:01.323027 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6891 12:48:01.326319 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6892 12:48:01.329665 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6893 12:48:01.332974 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6894 12:48:01.340153 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6895 12:48:01.342848 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6896 12:48:01.346589 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6897 12:48:01.349601 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6898 12:48:01.356103 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6899 12:48:01.359282 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6900 12:48:01.362832 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6901 12:48:01.369315 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6902 12:48:01.369798 ==
6903 12:48:01.372581 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 12:48:01.376107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 12:48:01.376840 ==
6906 12:48:01.377238 DQS Delay:
6907 12:48:01.378919 DQS0 = 51, DQS1 = 51
6908 12:48:01.379399 DQM Delay:
6909 12:48:01.382509 DQM0 = 19, DQM1 = 14
6910 12:48:01.382931 DQ Delay:
6911 12:48:01.386401 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6912 12:48:01.388899 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6913 12:48:01.392326 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6914 12:48:01.395558 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6915 12:48:01.395985
6916 12:48:01.396346
6917 12:48:01.396722 ==
6918 12:48:01.398749 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 12:48:01.401860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 12:48:01.402294 ==
6921 12:48:01.402639
6922 12:48:01.405239
6923 12:48:01.405663 TX Vref Scan disable
6924 12:48:01.408936 == TX Byte 0 ==
6925 12:48:01.412276 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6926 12:48:01.415453 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6927 12:48:01.418560 == TX Byte 1 ==
6928 12:48:01.421975 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6929 12:48:01.425037 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6930 12:48:01.425464 ==
6931 12:48:01.428873 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 12:48:01.432103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 12:48:01.432554 ==
6934 12:48:01.435283
6935 12:48:01.435703
6936 12:48:01.436039 TX Vref Scan disable
6937 12:48:01.438440 == TX Byte 0 ==
6938 12:48:01.441877 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6939 12:48:01.445054 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6940 12:48:01.448121 == TX Byte 1 ==
6941 12:48:01.451601 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6942 12:48:01.455334 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6943 12:48:01.455920
6944 12:48:01.458991 [DATLAT]
6945 12:48:01.459528 Freq=400, CH1 RK1
6946 12:48:01.459890
6947 12:48:01.461104 DATLAT Default: 0xe
6948 12:48:01.461530 0, 0xFFFF, sum = 0
6949 12:48:01.464430 1, 0xFFFF, sum = 0
6950 12:48:01.464924 2, 0xFFFF, sum = 0
6951 12:48:01.468005 3, 0xFFFF, sum = 0
6952 12:48:01.468570 4, 0xFFFF, sum = 0
6953 12:48:01.471332 5, 0xFFFF, sum = 0
6954 12:48:01.471859 6, 0xFFFF, sum = 0
6955 12:48:01.475404 7, 0xFFFF, sum = 0
6956 12:48:01.475930 8, 0xFFFF, sum = 0
6957 12:48:01.477890 9, 0xFFFF, sum = 0
6958 12:48:01.478418 10, 0xFFFF, sum = 0
6959 12:48:01.481122 11, 0xFFFF, sum = 0
6960 12:48:01.484266 12, 0xFFFF, sum = 0
6961 12:48:01.484722 13, 0x0, sum = 1
6962 12:48:01.485063 14, 0x0, sum = 2
6963 12:48:01.487645 15, 0x0, sum = 3
6964 12:48:01.488109 16, 0x0, sum = 4
6965 12:48:01.491315 best_step = 14
6966 12:48:01.491834
6967 12:48:01.492171 ==
6968 12:48:01.494335 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 12:48:01.497268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 12:48:01.497690 ==
6971 12:48:01.500941 RX Vref Scan: 0
6972 12:48:01.501357
6973 12:48:01.501695 RX Vref 0 -> 0, step: 1
6974 12:48:01.504173
6975 12:48:01.504721 RX Delay -343 -> 252, step: 8
6976 12:48:01.512240 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6977 12:48:01.515929 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6978 12:48:01.519350 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6979 12:48:01.526268 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6980 12:48:01.528922 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6981 12:48:01.532158 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6982 12:48:01.535903 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6983 12:48:01.542390 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6984 12:48:01.545946 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6985 12:48:01.548968 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6986 12:48:01.552631 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6987 12:48:01.559536 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6988 12:48:01.561948 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6989 12:48:01.565239 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6990 12:48:01.568439 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6991 12:48:01.575425 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6992 12:48:01.575901 ==
6993 12:48:01.579024 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 12:48:01.582093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 12:48:01.582671 ==
6996 12:48:01.583054 DQS Delay:
6997 12:48:01.585514 DQS0 = 44, DQS1 = 56
6998 12:48:01.585986 DQM Delay:
6999 12:48:01.589437 DQM0 = 8, DQM1 = 11
7000 12:48:01.590037 DQ Delay:
7001 12:48:01.592133 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7002 12:48:01.595547 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7003 12:48:01.598635 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7004 12:48:01.601613 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7005 12:48:01.602205
7006 12:48:01.602588
7007 12:48:01.608930 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7008 12:48:01.612315 CH1 RK1: MR19=C0C, MR18=6A59
7009 12:48:01.618586 CH1_RK1: MR19=0xC0C, MR18=0x6A59, DQSOSC=396, MR23=63, INC=376, DEC=251
7010 12:48:01.621904 [RxdqsGatingPostProcess] freq 400
7011 12:48:01.627968 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7012 12:48:01.631326 best DQS0 dly(2T, 0.5T) = (0, 10)
7013 12:48:01.635235 best DQS1 dly(2T, 0.5T) = (0, 10)
7014 12:48:01.638398 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7015 12:48:01.641422 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7016 12:48:01.641902 best DQS0 dly(2T, 0.5T) = (0, 10)
7017 12:48:01.645409 best DQS1 dly(2T, 0.5T) = (0, 10)
7018 12:48:01.647854 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7019 12:48:01.651826 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7020 12:48:01.654847 Pre-setting of DQS Precalculation
7021 12:48:01.661236 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7022 12:48:01.667666 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7023 12:48:01.674192 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7024 12:48:01.674664
7025 12:48:01.675093
7026 12:48:01.677910 [Calibration Summary] 800 Mbps
7027 12:48:01.678376 CH 0, Rank 0
7028 12:48:01.680793 SW Impedance : PASS
7029 12:48:01.684351 DUTY Scan : NO K
7030 12:48:01.684944 ZQ Calibration : PASS
7031 12:48:01.687517 Jitter Meter : NO K
7032 12:48:01.690712 CBT Training : PASS
7033 12:48:01.691128 Write leveling : PASS
7034 12:48:01.694265 RX DQS gating : PASS
7035 12:48:01.697413 RX DQ/DQS(RDDQC) : PASS
7036 12:48:01.697865 TX DQ/DQS : PASS
7037 12:48:01.700628 RX DATLAT : PASS
7038 12:48:01.703955 RX DQ/DQS(Engine): PASS
7039 12:48:01.704369 TX OE : NO K
7040 12:48:01.707365 All Pass.
7041 12:48:01.707828
7042 12:48:01.708252 CH 0, Rank 1
7043 12:48:01.710725 SW Impedance : PASS
7044 12:48:01.711243 DUTY Scan : NO K
7045 12:48:01.714295 ZQ Calibration : PASS
7046 12:48:01.717671 Jitter Meter : NO K
7047 12:48:01.718093 CBT Training : PASS
7048 12:48:01.720833 Write leveling : NO K
7049 12:48:01.724578 RX DQS gating : PASS
7050 12:48:01.724999 RX DQ/DQS(RDDQC) : PASS
7051 12:48:01.727061 TX DQ/DQS : PASS
7052 12:48:01.727478 RX DATLAT : PASS
7053 12:48:01.730345 RX DQ/DQS(Engine): PASS
7054 12:48:01.733762 TX OE : NO K
7055 12:48:01.734349 All Pass.
7056 12:48:01.734695
7057 12:48:01.735010 CH 1, Rank 0
7058 12:48:01.737279 SW Impedance : PASS
7059 12:48:01.740456 DUTY Scan : NO K
7060 12:48:01.740910 ZQ Calibration : PASS
7061 12:48:01.743678 Jitter Meter : NO K
7062 12:48:01.747229 CBT Training : PASS
7063 12:48:01.747751 Write leveling : PASS
7064 12:48:01.749904 RX DQS gating : PASS
7065 12:48:01.753459 RX DQ/DQS(RDDQC) : PASS
7066 12:48:01.753978 TX DQ/DQS : PASS
7067 12:48:01.757168 RX DATLAT : PASS
7068 12:48:01.760859 RX DQ/DQS(Engine): PASS
7069 12:48:01.761404 TX OE : NO K
7070 12:48:01.763537 All Pass.
7071 12:48:01.763988
7072 12:48:01.764322 CH 1, Rank 1
7073 12:48:01.766474 SW Impedance : PASS
7074 12:48:01.766896 DUTY Scan : NO K
7075 12:48:01.770142 ZQ Calibration : PASS
7076 12:48:01.773216 Jitter Meter : NO K
7077 12:48:01.773640 CBT Training : PASS
7078 12:48:01.777212 Write leveling : NO K
7079 12:48:01.779798 RX DQS gating : PASS
7080 12:48:01.780285 RX DQ/DQS(RDDQC) : PASS
7081 12:48:01.783260 TX DQ/DQS : PASS
7082 12:48:01.786589 RX DATLAT : PASS
7083 12:48:01.787168 RX DQ/DQS(Engine): PASS
7084 12:48:01.790094 TX OE : NO K
7085 12:48:01.790658 All Pass.
7086 12:48:01.791042
7087 12:48:01.793342 DramC Write-DBI off
7088 12:48:01.796536 PER_BANK_REFRESH: Hybrid Mode
7089 12:48:01.797143 TX_TRACKING: ON
7090 12:48:01.807093 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7091 12:48:01.809585 [FAST_K] Save calibration result to emmc
7092 12:48:01.813144 dramc_set_vcore_voltage set vcore to 725000
7093 12:48:01.816229 Read voltage for 1600, 0
7094 12:48:01.816733 Vio18 = 0
7095 12:48:01.817110 Vcore = 725000
7096 12:48:01.819888 Vdram = 0
7097 12:48:01.820552 Vddq = 0
7098 12:48:01.820966 Vmddr = 0
7099 12:48:01.825858 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7100 12:48:01.829754 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7101 12:48:01.832414 MEM_TYPE=3, freq_sel=13
7102 12:48:01.835962 sv_algorithm_assistance_LP4_3733
7103 12:48:01.839635 ============ PULL DRAM RESETB DOWN ============
7104 12:48:01.842486 ========== PULL DRAM RESETB DOWN end =========
7105 12:48:01.849195 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7106 12:48:01.852654 ===================================
7107 12:48:01.856048 LPDDR4 DRAM CONFIGURATION
7108 12:48:01.859350 ===================================
7109 12:48:01.859922 EX_ROW_EN[0] = 0x0
7110 12:48:01.862135 EX_ROW_EN[1] = 0x0
7111 12:48:01.862601 LP4Y_EN = 0x0
7112 12:48:01.865460 WORK_FSP = 0x1
7113 12:48:01.865926 WL = 0x5
7114 12:48:01.869355 RL = 0x5
7115 12:48:01.869927 BL = 0x2
7116 12:48:01.872967 RPST = 0x0
7117 12:48:01.873542 RD_PRE = 0x0
7118 12:48:01.875645 WR_PRE = 0x1
7119 12:48:01.879140 WR_PST = 0x1
7120 12:48:01.879718 DBI_WR = 0x0
7121 12:48:01.882064 DBI_RD = 0x0
7122 12:48:01.882630 OTF = 0x1
7123 12:48:01.885132 ===================================
7124 12:48:01.888664 ===================================
7125 12:48:01.891926 ANA top config
7126 12:48:01.895575 ===================================
7127 12:48:01.896153 DLL_ASYNC_EN = 0
7128 12:48:01.898722 ALL_SLAVE_EN = 0
7129 12:48:01.901854 NEW_RANK_MODE = 1
7130 12:48:01.905089 DLL_IDLE_MODE = 1
7131 12:48:01.905555 LP45_APHY_COMB_EN = 1
7132 12:48:01.908676 TX_ODT_DIS = 0
7133 12:48:01.912006 NEW_8X_MODE = 1
7134 12:48:01.915330 ===================================
7135 12:48:01.918464 ===================================
7136 12:48:01.921500 data_rate = 3200
7137 12:48:01.925136 CKR = 1
7138 12:48:01.928296 DQ_P2S_RATIO = 8
7139 12:48:01.931913 ===================================
7140 12:48:01.932484 CA_P2S_RATIO = 8
7141 12:48:01.934786 DQ_CA_OPEN = 0
7142 12:48:01.937740 DQ_SEMI_OPEN = 0
7143 12:48:01.941081 CA_SEMI_OPEN = 0
7144 12:48:01.944687 CA_FULL_RATE = 0
7145 12:48:01.947753 DQ_CKDIV4_EN = 0
7146 12:48:01.948324 CA_CKDIV4_EN = 0
7147 12:48:01.951056 CA_PREDIV_EN = 0
7148 12:48:01.954566 PH8_DLY = 12
7149 12:48:01.957794 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7150 12:48:01.961186 DQ_AAMCK_DIV = 4
7151 12:48:01.964219 CA_AAMCK_DIV = 4
7152 12:48:01.964727 CA_ADMCK_DIV = 4
7153 12:48:01.967877 DQ_TRACK_CA_EN = 0
7154 12:48:01.971234 CA_PICK = 1600
7155 12:48:01.974211 CA_MCKIO = 1600
7156 12:48:01.977797 MCKIO_SEMI = 0
7157 12:48:01.981533 PLL_FREQ = 3068
7158 12:48:01.984023 DQ_UI_PI_RATIO = 32
7159 12:48:01.987763 CA_UI_PI_RATIO = 0
7160 12:48:01.990971 ===================================
7161 12:48:01.994240 ===================================
7162 12:48:01.994806 memory_type:LPDDR4
7163 12:48:01.997101 GP_NUM : 10
7164 12:48:02.001081 SRAM_EN : 1
7165 12:48:02.001548 MD32_EN : 0
7166 12:48:02.004032 ===================================
7167 12:48:02.006894 [ANA_INIT] >>>>>>>>>>>>>>
7168 12:48:02.010490 <<<<<< [CONFIGURE PHASE]: ANA_TX
7169 12:48:02.013790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7170 12:48:02.017244 ===================================
7171 12:48:02.020699 data_rate = 3200,PCW = 0X7600
7172 12:48:02.023566 ===================================
7173 12:48:02.027301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7174 12:48:02.030146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 12:48:02.036801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7176 12:48:02.040189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7177 12:48:02.043143 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7178 12:48:02.046661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7179 12:48:02.050257 [ANA_INIT] flow start
7180 12:48:02.053693 [ANA_INIT] PLL >>>>>>>>
7181 12:48:02.054286 [ANA_INIT] PLL <<<<<<<<
7182 12:48:02.056482 [ANA_INIT] MIDPI >>>>>>>>
7183 12:48:02.059839 [ANA_INIT] MIDPI <<<<<<<<
7184 12:48:02.063040 [ANA_INIT] DLL >>>>>>>>
7185 12:48:02.063505 [ANA_INIT] DLL <<<<<<<<
7186 12:48:02.066422 [ANA_INIT] flow end
7187 12:48:02.070274 ============ LP4 DIFF to SE enter ============
7188 12:48:02.073660 ============ LP4 DIFF to SE exit ============
7189 12:48:02.076381 [ANA_INIT] <<<<<<<<<<<<<
7190 12:48:02.079809 [Flow] Enable top DCM control >>>>>
7191 12:48:02.083421 [Flow] Enable top DCM control <<<<<
7192 12:48:02.086624 Enable DLL master slave shuffle
7193 12:48:02.093523 ==============================================================
7194 12:48:02.094154 Gating Mode config
7195 12:48:02.099707 ==============================================================
7196 12:48:02.100177 Config description:
7197 12:48:02.109137 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7198 12:48:02.115925 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7199 12:48:02.122709 SELPH_MODE 0: By rank 1: By Phase
7200 12:48:02.129020 ==============================================================
7201 12:48:02.129595 GAT_TRACK_EN = 1
7202 12:48:02.132924 RX_GATING_MODE = 2
7203 12:48:02.135645 RX_GATING_TRACK_MODE = 2
7204 12:48:02.139513 SELPH_MODE = 1
7205 12:48:02.143124 PICG_EARLY_EN = 1
7206 12:48:02.145890 VALID_LAT_VALUE = 1
7207 12:48:02.152370 ==============================================================
7208 12:48:02.155771 Enter into Gating configuration >>>>
7209 12:48:02.158824 Exit from Gating configuration <<<<
7210 12:48:02.162115 Enter into DVFS_PRE_config >>>>>
7211 12:48:02.172079 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7212 12:48:02.175452 Exit from DVFS_PRE_config <<<<<
7213 12:48:02.178923 Enter into PICG configuration >>>>
7214 12:48:02.181859 Exit from PICG configuration <<<<
7215 12:48:02.185345 [RX_INPUT] configuration >>>>>
7216 12:48:02.185768 [RX_INPUT] configuration <<<<<
7217 12:48:02.191737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7218 12:48:02.198596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7219 12:48:02.204775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 12:48:02.208351 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 12:48:02.215766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 12:48:02.221495 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 12:48:02.225461 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7224 12:48:02.231417 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7225 12:48:02.234785 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7226 12:48:02.237919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7227 12:48:02.241076 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7228 12:48:02.247884 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 12:48:02.251064 ===================================
7230 12:48:02.251486 LPDDR4 DRAM CONFIGURATION
7231 12:48:02.254658 ===================================
7232 12:48:02.257745 EX_ROW_EN[0] = 0x0
7233 12:48:02.260992 EX_ROW_EN[1] = 0x0
7234 12:48:02.261414 LP4Y_EN = 0x0
7235 12:48:02.264347 WORK_FSP = 0x1
7236 12:48:02.264853 WL = 0x5
7237 12:48:02.268093 RL = 0x5
7238 12:48:02.268545 BL = 0x2
7239 12:48:02.271510 RPST = 0x0
7240 12:48:02.271975 RD_PRE = 0x0
7241 12:48:02.274312 WR_PRE = 0x1
7242 12:48:02.274808 WR_PST = 0x1
7243 12:48:02.277657 DBI_WR = 0x0
7244 12:48:02.278078 DBI_RD = 0x0
7245 12:48:02.280662 OTF = 0x1
7246 12:48:02.284133 ===================================
7247 12:48:02.287720 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7248 12:48:02.291011 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7249 12:48:02.297302 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7250 12:48:02.300602 ===================================
7251 12:48:02.301028 LPDDR4 DRAM CONFIGURATION
7252 12:48:02.304468 ===================================
7253 12:48:02.307257 EX_ROW_EN[0] = 0x10
7254 12:48:02.310955 EX_ROW_EN[1] = 0x0
7255 12:48:02.311393 LP4Y_EN = 0x0
7256 12:48:02.314057 WORK_FSP = 0x1
7257 12:48:02.314478 WL = 0x5
7258 12:48:02.316968 RL = 0x5
7259 12:48:02.317386 BL = 0x2
7260 12:48:02.320334 RPST = 0x0
7261 12:48:02.320863 RD_PRE = 0x0
7262 12:48:02.323803 WR_PRE = 0x1
7263 12:48:02.324222 WR_PST = 0x1
7264 12:48:02.327397 DBI_WR = 0x0
7265 12:48:02.327817 DBI_RD = 0x0
7266 12:48:02.330597 OTF = 0x1
7267 12:48:02.333652 ===================================
7268 12:48:02.340337 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7269 12:48:02.340888 ==
7270 12:48:02.344067 Dram Type= 6, Freq= 0, CH_0, rank 0
7271 12:48:02.346959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7272 12:48:02.347385 ==
7273 12:48:02.350991 [Duty_Offset_Calibration]
7274 12:48:02.351413 B0:1 B1:-1 CA:0
7275 12:48:02.351749
7276 12:48:02.353658 [DutyScan_Calibration_Flow] k_type=0
7277 12:48:02.364670
7278 12:48:02.365102 ==CLK 0==
7279 12:48:02.368213 Final CLK duty delay cell = 0
7280 12:48:02.371272 [0] MAX Duty = 5125%(X100), DQS PI = 20
7281 12:48:02.374429 [0] MIN Duty = 4907%(X100), DQS PI = 4
7282 12:48:02.374887 [0] AVG Duty = 5016%(X100)
7283 12:48:02.377809
7284 12:48:02.378231 CH0 CLK Duty spec in!! Max-Min= 218%
7285 12:48:02.384618 [DutyScan_Calibration_Flow] ====Done====
7286 12:48:02.385038
7287 12:48:02.387958 [DutyScan_Calibration_Flow] k_type=1
7288 12:48:02.403622
7289 12:48:02.404105 ==DQS 0 ==
7290 12:48:02.406892 Final DQS duty delay cell = -4
7291 12:48:02.410639 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7292 12:48:02.413732 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7293 12:48:02.416908 [-4] AVG Duty = 4906%(X100)
7294 12:48:02.417325
7295 12:48:02.417654 ==DQS 1 ==
7296 12:48:02.420123 Final DQS duty delay cell = 0
7297 12:48:02.423374 [0] MAX Duty = 5156%(X100), DQS PI = 0
7298 12:48:02.426610 [0] MIN Duty = 5031%(X100), DQS PI = 18
7299 12:48:02.430077 [0] AVG Duty = 5093%(X100)
7300 12:48:02.430535
7301 12:48:02.433596 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7302 12:48:02.434016
7303 12:48:02.436949 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7304 12:48:02.439766 [DutyScan_Calibration_Flow] ====Done====
7305 12:48:02.440181
7306 12:48:02.443469 [DutyScan_Calibration_Flow] k_type=3
7307 12:48:02.461475
7308 12:48:02.461983 ==DQM 0 ==
7309 12:48:02.464698 Final DQM duty delay cell = 0
7310 12:48:02.467658 [0] MAX Duty = 5124%(X100), DQS PI = 22
7311 12:48:02.470737 [0] MIN Duty = 4907%(X100), DQS PI = 10
7312 12:48:02.473919 [0] AVG Duty = 5015%(X100)
7313 12:48:02.474028
7314 12:48:02.474129 ==DQM 1 ==
7315 12:48:02.477489 Final DQM duty delay cell = 0
7316 12:48:02.480881 [0] MAX Duty = 5000%(X100), DQS PI = 6
7317 12:48:02.484093 [0] MIN Duty = 4782%(X100), DQS PI = 22
7318 12:48:02.487098 [0] AVG Duty = 4891%(X100)
7319 12:48:02.487190
7320 12:48:02.490482 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7321 12:48:02.490574
7322 12:48:02.493416 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7323 12:48:02.497207 [DutyScan_Calibration_Flow] ====Done====
7324 12:48:02.497316
7325 12:48:02.500549 [DutyScan_Calibration_Flow] k_type=2
7326 12:48:02.518129
7327 12:48:02.518302 ==DQ 0 ==
7328 12:48:02.520819 Final DQ duty delay cell = -4
7329 12:48:02.523660 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7330 12:48:02.527712 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7331 12:48:02.530844 [-4] AVG Duty = 4953%(X100)
7332 12:48:02.531257
7333 12:48:02.531582 ==DQ 1 ==
7334 12:48:02.533593 Final DQ duty delay cell = 0
7335 12:48:02.537331 [0] MAX Duty = 5125%(X100), DQS PI = 4
7336 12:48:02.540541 [0] MIN Duty = 5000%(X100), DQS PI = 36
7337 12:48:02.543841 [0] AVG Duty = 5062%(X100)
7338 12:48:02.544255
7339 12:48:02.546886 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7340 12:48:02.547301
7341 12:48:02.550947 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7342 12:48:02.554057 [DutyScan_Calibration_Flow] ====Done====
7343 12:48:02.554474 ==
7344 12:48:02.556857 Dram Type= 6, Freq= 0, CH_1, rank 0
7345 12:48:02.560410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7346 12:48:02.560850 ==
7347 12:48:02.563429 [Duty_Offset_Calibration]
7348 12:48:02.563841 B0:-1 B1:1 CA:2
7349 12:48:02.566670
7350 12:48:02.569950 [DutyScan_Calibration_Flow] k_type=0
7351 12:48:02.578600
7352 12:48:02.579026 ==CLK 0==
7353 12:48:02.581559 Final CLK duty delay cell = 0
7354 12:48:02.584854 [0] MAX Duty = 5187%(X100), DQS PI = 24
7355 12:48:02.588064 [0] MIN Duty = 4969%(X100), DQS PI = 0
7356 12:48:02.588477 [0] AVG Duty = 5078%(X100)
7357 12:48:02.591828
7358 12:48:02.594742 CH1 CLK Duty spec in!! Max-Min= 218%
7359 12:48:02.597783 [DutyScan_Calibration_Flow] ====Done====
7360 12:48:02.598195
7361 12:48:02.601141 [DutyScan_Calibration_Flow] k_type=1
7362 12:48:02.617804
7363 12:48:02.618250 ==DQS 0 ==
7364 12:48:02.621009 Final DQS duty delay cell = 0
7365 12:48:02.624107 [0] MAX Duty = 5156%(X100), DQS PI = 18
7366 12:48:02.627686 [0] MIN Duty = 4907%(X100), DQS PI = 8
7367 12:48:02.630737 [0] AVG Duty = 5031%(X100)
7368 12:48:02.631219
7369 12:48:02.631605 ==DQS 1 ==
7370 12:48:02.634044 Final DQS duty delay cell = 0
7371 12:48:02.637550 [0] MAX Duty = 5093%(X100), DQS PI = 24
7372 12:48:02.640985 [0] MIN Duty = 4969%(X100), DQS PI = 56
7373 12:48:02.643641 [0] AVG Duty = 5031%(X100)
7374 12:48:02.644148
7375 12:48:02.647145 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7376 12:48:02.647560
7377 12:48:02.650332 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7378 12:48:02.653785 [DutyScan_Calibration_Flow] ====Done====
7379 12:48:02.654209
7380 12:48:02.656772 [DutyScan_Calibration_Flow] k_type=3
7381 12:48:02.673701
7382 12:48:02.674118 ==DQM 0 ==
7383 12:48:02.677123 Final DQM duty delay cell = -4
7384 12:48:02.680386 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7385 12:48:02.683902 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7386 12:48:02.687243 [-4] AVG Duty = 4922%(X100)
7387 12:48:02.687708
7388 12:48:02.688045 ==DQM 1 ==
7389 12:48:02.690295 Final DQM duty delay cell = 0
7390 12:48:02.693382 [0] MAX Duty = 5156%(X100), DQS PI = 6
7391 12:48:02.696939 [0] MIN Duty = 4969%(X100), DQS PI = 34
7392 12:48:02.700234 [0] AVG Duty = 5062%(X100)
7393 12:48:02.700701
7394 12:48:02.703644 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7395 12:48:02.704057
7396 12:48:02.706625 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7397 12:48:02.709806 [DutyScan_Calibration_Flow] ====Done====
7398 12:48:02.710235
7399 12:48:02.713178 [DutyScan_Calibration_Flow] k_type=2
7400 12:48:02.731248
7401 12:48:02.731797 ==DQ 0 ==
7402 12:48:02.734325 Final DQ duty delay cell = 0
7403 12:48:02.737432 [0] MAX Duty = 5187%(X100), DQS PI = 32
7404 12:48:02.740841 [0] MIN Duty = 4906%(X100), DQS PI = 8
7405 12:48:02.741304 [0] AVG Duty = 5046%(X100)
7406 12:48:02.743959
7407 12:48:02.744473 ==DQ 1 ==
7408 12:48:02.747117 Final DQ duty delay cell = 0
7409 12:48:02.750964 [0] MAX Duty = 5156%(X100), DQS PI = 10
7410 12:48:02.753952 [0] MIN Duty = 4969%(X100), DQS PI = 56
7411 12:48:02.754498 [0] AVG Duty = 5062%(X100)
7412 12:48:02.757512
7413 12:48:02.760786 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7414 12:48:02.761235
7415 12:48:02.763730 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7416 12:48:02.767004 [DutyScan_Calibration_Flow] ====Done====
7417 12:48:02.770371 nWR fixed to 30
7418 12:48:02.773977 [ModeRegInit_LP4] CH0 RK0
7419 12:48:02.774525 [ModeRegInit_LP4] CH0 RK1
7420 12:48:02.777431 [ModeRegInit_LP4] CH1 RK0
7421 12:48:02.780513 [ModeRegInit_LP4] CH1 RK1
7422 12:48:02.780969 match AC timing 5
7423 12:48:02.787340 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7424 12:48:02.790180 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7425 12:48:02.793348 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7426 12:48:02.800313 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7427 12:48:02.803449 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7428 12:48:02.803968 [MiockJmeterHQA]
7429 12:48:02.804459
7430 12:48:02.806810 [DramcMiockJmeter] u1RxGatingPI = 0
7431 12:48:02.810245 0 : 4255, 4029
7432 12:48:02.810672 4 : 4252, 4027
7433 12:48:02.813501 8 : 4255, 4029
7434 12:48:02.813926 12 : 4363, 4138
7435 12:48:02.816629 16 : 4255, 4030
7436 12:48:02.817072 20 : 4363, 4137
7437 12:48:02.817482 24 : 4253, 4027
7438 12:48:02.819981 28 : 4253, 4026
7439 12:48:02.820595 32 : 4252, 4027
7440 12:48:02.823620 36 : 4254, 4029
7441 12:48:02.824045 40 : 4253, 4026
7442 12:48:02.826710 44 : 4252, 4027
7443 12:48:02.827131 48 : 4366, 4140
7444 12:48:02.829558 52 : 4253, 4027
7445 12:48:02.829985 56 : 4254, 4029
7446 12:48:02.830328 60 : 4250, 4027
7447 12:48:02.833364 64 : 4361, 4138
7448 12:48:02.833792 68 : 4250, 4027
7449 12:48:02.836333 72 : 4360, 4138
7450 12:48:02.836830 76 : 4250, 4027
7451 12:48:02.839876 80 : 4250, 4027
7452 12:48:02.840302 84 : 4250, 4027
7453 12:48:02.843230 88 : 4253, 4029
7454 12:48:02.843844 92 : 4360, 796
7455 12:48:02.844289 96 : 4253, 0
7456 12:48:02.846677 100 : 4250, 0
7457 12:48:02.847105 104 : 4250, 0
7458 12:48:02.849856 108 : 4249, 0
7459 12:48:02.850314 112 : 4250, 0
7460 12:48:02.850661 116 : 4250, 0
7461 12:48:02.852993 120 : 4250, 0
7462 12:48:02.853551 124 : 4253, 0
7463 12:48:02.853996 128 : 4250, 0
7464 12:48:02.855901 132 : 4250, 0
7465 12:48:02.856424 136 : 4250, 0
7466 12:48:02.859546 140 : 4361, 0
7467 12:48:02.860102 144 : 4250, 0
7468 12:48:02.860689 148 : 4250, 0
7469 12:48:02.862786 152 : 4250, 0
7470 12:48:02.863211 156 : 4360, 0
7471 12:48:02.866932 160 : 4361, 0
7472 12:48:02.867376 164 : 4248, 0
7473 12:48:02.867722 168 : 4250, 0
7474 12:48:02.869909 172 : 4250, 0
7475 12:48:02.870368 176 : 4250, 0
7476 12:48:02.872584 180 : 4250, 0
7477 12:48:02.873022 184 : 4250, 0
7478 12:48:02.873370 188 : 4252, 0
7479 12:48:02.876565 192 : 4361, 0
7480 12:48:02.877170 196 : 4250, 0
7481 12:48:02.879301 200 : 4250, 0
7482 12:48:02.879731 204 : 4249, 0
7483 12:48:02.880075 208 : 4360, 0
7484 12:48:02.882671 212 : 4361, 0
7485 12:48:02.883102 216 : 4250, 0
7486 12:48:02.883446 220 : 4250, 0
7487 12:48:02.885718 224 : 4250, 103
7488 12:48:02.886150 228 : 4250, 3231
7489 12:48:02.888983 232 : 4250, 4027
7490 12:48:02.889432 236 : 4250, 4027
7491 12:48:02.892500 240 : 4252, 4029
7492 12:48:02.892968 244 : 4250, 4027
7493 12:48:02.896671 248 : 4251, 4027
7494 12:48:02.897198 252 : 4252, 4029
7495 12:48:02.899059 256 : 4250, 4027
7496 12:48:02.899590 260 : 4360, 4138
7497 12:48:02.902180 264 : 4360, 4138
7498 12:48:02.902611 268 : 4250, 4027
7499 12:48:02.905599 272 : 4363, 4139
7500 12:48:02.906029 276 : 4360, 4138
7501 12:48:02.909702 280 : 4250, 4027
7502 12:48:02.910229 284 : 4250, 4027
7503 12:48:02.910577 288 : 4252, 4029
7504 12:48:02.912180 292 : 4250, 4027
7505 12:48:02.912643 296 : 4250, 4027
7506 12:48:02.915871 300 : 4250, 4027
7507 12:48:02.916305 304 : 4249, 4027
7508 12:48:02.919178 308 : 4250, 4026
7509 12:48:02.919707 312 : 4360, 4138
7510 12:48:02.922704 316 : 4360, 4138
7511 12:48:02.923234 320 : 4250, 4027
7512 12:48:02.925089 324 : 4360, 4137
7513 12:48:02.925521 328 : 4360, 4138
7514 12:48:02.928799 332 : 4250, 4027
7515 12:48:02.929228 336 : 4250, 3948
7516 12:48:02.931900 340 : 4252, 2217
7517 12:48:02.932332 344 : 4250, 182
7518 12:48:02.932726
7519 12:48:02.935514 MIOCK jitter meter ch=0
7520 12:48:02.936034
7521 12:48:02.938786 1T = (344-92) = 252 dly cells
7522 12:48:02.941908 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7523 12:48:02.942431 ==
7524 12:48:02.945371 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 12:48:02.952050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 12:48:02.952625 ==
7527 12:48:02.954850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7528 12:48:02.962009 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7529 12:48:02.965142 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7530 12:48:02.971469 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7531 12:48:02.979515 [CA 0] Center 43 (13~74) winsize 62
7532 12:48:02.983018 [CA 1] Center 43 (13~74) winsize 62
7533 12:48:02.986432 [CA 2] Center 39 (10~69) winsize 60
7534 12:48:02.990098 [CA 3] Center 39 (9~69) winsize 61
7535 12:48:02.992690 [CA 4] Center 37 (8~66) winsize 59
7536 12:48:02.996343 [CA 5] Center 36 (7~66) winsize 60
7537 12:48:02.996845
7538 12:48:02.999401 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7539 12:48:02.999871
7540 12:48:03.005523 [CATrainingPosCal] consider 1 rank data
7541 12:48:03.005954 u2DelayCellTimex100 = 258/100 ps
7542 12:48:03.012451 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7543 12:48:03.015891 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7544 12:48:03.019178 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7545 12:48:03.022391 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7546 12:48:03.026323 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7547 12:48:03.029029 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7548 12:48:03.029466
7549 12:48:03.032656 CA PerBit enable=1, Macro0, CA PI delay=36
7550 12:48:03.033103
7551 12:48:03.035441 [CBTSetCACLKResult] CA Dly = 36
7552 12:48:03.039014 CS Dly: 12 (0~43)
7553 12:48:03.042387 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7554 12:48:03.045572 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7555 12:48:03.046094 ==
7556 12:48:03.049219 Dram Type= 6, Freq= 0, CH_0, rank 1
7557 12:48:03.055653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 12:48:03.056180 ==
7559 12:48:03.058788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7560 12:48:03.065395 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7561 12:48:03.068433 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7562 12:48:03.075281 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7563 12:48:03.083623 [CA 0] Center 42 (12~73) winsize 62
7564 12:48:03.086268 [CA 1] Center 43 (13~73) winsize 61
7565 12:48:03.089917 [CA 2] Center 37 (8~67) winsize 60
7566 12:48:03.093148 [CA 3] Center 37 (8~67) winsize 60
7567 12:48:03.096548 [CA 4] Center 35 (6~65) winsize 60
7568 12:48:03.099603 [CA 5] Center 35 (5~65) winsize 61
7569 12:48:03.100099
7570 12:48:03.102731 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7571 12:48:03.103203
7572 12:48:03.109380 [CATrainingPosCal] consider 2 rank data
7573 12:48:03.109850 u2DelayCellTimex100 = 258/100 ps
7574 12:48:03.116036 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7575 12:48:03.119705 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7576 12:48:03.123316 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7577 12:48:03.126412 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7578 12:48:03.130632 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7579 12:48:03.132482 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7580 12:48:03.133010
7581 12:48:03.135873 CA PerBit enable=1, Macro0, CA PI delay=36
7582 12:48:03.136346
7583 12:48:03.138925 [CBTSetCACLKResult] CA Dly = 36
7584 12:48:03.142239 CS Dly: 12 (0~44)
7585 12:48:03.145737 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7586 12:48:03.149040 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7587 12:48:03.149513
7588 12:48:03.153004 ----->DramcWriteLeveling(PI) begin...
7589 12:48:03.153685 ==
7590 12:48:03.155736 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 12:48:03.162774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 12:48:03.163301 ==
7593 12:48:03.165497 Write leveling (Byte 0): 36 => 36
7594 12:48:03.169060 Write leveling (Byte 1): 25 => 25
7595 12:48:03.169499 DramcWriteLeveling(PI) end<-----
7596 12:48:03.172463
7597 12:48:03.172936 ==
7598 12:48:03.175638 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 12:48:03.179499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 12:48:03.180044 ==
7601 12:48:03.182737 [Gating] SW mode calibration
7602 12:48:03.188690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7603 12:48:03.195448 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7604 12:48:03.198331 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 12:48:03.201649 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 12:48:03.208587 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 12:48:03.212376 1 4 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7608 12:48:03.215527 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7609 12:48:03.221771 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7610 12:48:03.225101 1 4 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7611 12:48:03.228216 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 12:48:03.234931 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 12:48:03.238545 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 12:48:03.241613 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7615 12:48:03.248151 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7616 12:48:03.251655 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7617 12:48:03.254218 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7618 12:48:03.261251 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7619 12:48:03.264406 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 12:48:03.267615 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 12:48:03.274843 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 12:48:03.277570 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 12:48:03.281228 1 6 12 | B1->B0 | 2323 3838 | 0 1 | (0 0) (0 0)
7624 12:48:03.287834 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7625 12:48:03.291075 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7626 12:48:03.293952 1 6 24 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
7627 12:48:03.300571 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 12:48:03.304038 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 12:48:03.307398 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 12:48:03.314432 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 12:48:03.317227 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7632 12:48:03.320898 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7633 12:48:03.327149 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7634 12:48:03.330481 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7635 12:48:03.333581 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:48:03.340258 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:48:03.343427 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:48:03.346884 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:48:03.353063 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:48:03.356449 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 12:48:03.359907 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:48:03.366675 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:48:03.369863 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 12:48:03.373124 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 12:48:03.380273 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 12:48:03.383193 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 12:48:03.386559 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7648 12:48:03.393530 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7649 12:48:03.394387 Total UI for P1: 0, mck2ui 16
7650 12:48:03.399498 best dqsien dly found for B0: ( 1, 9, 10)
7651 12:48:03.402768 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 12:48:03.406129 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 12:48:03.409808 Total UI for P1: 0, mck2ui 16
7654 12:48:03.412736 best dqsien dly found for B1: ( 1, 9, 20)
7655 12:48:03.415822 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7656 12:48:03.419274 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7657 12:48:03.419738
7658 12:48:03.425728 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7659 12:48:03.429084 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7660 12:48:03.432509 [Gating] SW calibration Done
7661 12:48:03.433002 ==
7662 12:48:03.435880 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 12:48:03.439137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 12:48:03.439720 ==
7665 12:48:03.440094 RX Vref Scan: 0
7666 12:48:03.440438
7667 12:48:03.442805 RX Vref 0 -> 0, step: 1
7668 12:48:03.443394
7669 12:48:03.445620 RX Delay 0 -> 252, step: 8
7670 12:48:03.449139 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7671 12:48:03.452553 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7672 12:48:03.455621 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7673 12:48:03.462384 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7674 12:48:03.465748 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7675 12:48:03.469104 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7676 12:48:03.471930 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7677 12:48:03.475632 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7678 12:48:03.481756 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7679 12:48:03.485058 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7680 12:48:03.488856 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7681 12:48:03.491565 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7682 12:48:03.498466 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7683 12:48:03.501523 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7684 12:48:03.504764 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7685 12:48:03.508342 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7686 12:48:03.508877 ==
7687 12:48:03.511436 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 12:48:03.518175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 12:48:03.518725 ==
7690 12:48:03.519100 DQS Delay:
7691 12:48:03.521617 DQS0 = 0, DQS1 = 0
7692 12:48:03.522075 DQM Delay:
7693 12:48:03.522437 DQM0 = 133, DQM1 = 126
7694 12:48:03.524990 DQ Delay:
7695 12:48:03.528058 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =131
7696 12:48:03.531691 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7697 12:48:03.535016 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7698 12:48:03.538064 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7699 12:48:03.538479
7700 12:48:03.538808
7701 12:48:03.539117 ==
7702 12:48:03.540831 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 12:48:03.547696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 12:48:03.548242 ==
7705 12:48:03.548641
7706 12:48:03.548965
7707 12:48:03.549269 TX Vref Scan disable
7708 12:48:03.551313 == TX Byte 0 ==
7709 12:48:03.554853 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7710 12:48:03.561317 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7711 12:48:03.561842 == TX Byte 1 ==
7712 12:48:03.564413 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7713 12:48:03.570962 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7714 12:48:03.571465 ==
7715 12:48:03.574638 Dram Type= 6, Freq= 0, CH_0, rank 0
7716 12:48:03.577708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7717 12:48:03.578286 ==
7718 12:48:03.591747
7719 12:48:03.594673 TX Vref early break, caculate TX vref
7720 12:48:03.597717 TX Vref=16, minBit 9, minWin=22, winSum=371
7721 12:48:03.601281 TX Vref=18, minBit 1, minWin=23, winSum=375
7722 12:48:03.603819 TX Vref=20, minBit 4, minWin=23, winSum=387
7723 12:48:03.607450 TX Vref=22, minBit 1, minWin=23, winSum=398
7724 12:48:03.611213 TX Vref=24, minBit 0, minWin=25, winSum=406
7725 12:48:03.617661 TX Vref=26, minBit 1, minWin=25, winSum=416
7726 12:48:03.620895 TX Vref=28, minBit 0, minWin=25, winSum=416
7727 12:48:03.624246 TX Vref=30, minBit 5, minWin=23, winSum=405
7728 12:48:03.627402 TX Vref=32, minBit 0, minWin=24, winSum=399
7729 12:48:03.630395 TX Vref=34, minBit 7, minWin=23, winSum=394
7730 12:48:03.637053 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 26
7731 12:48:03.637626
7732 12:48:03.641085 Final TX Range 0 Vref 26
7733 12:48:03.641660
7734 12:48:03.642037 ==
7735 12:48:03.644335 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 12:48:03.647104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 12:48:03.647687 ==
7738 12:48:03.648067
7739 12:48:03.648414
7740 12:48:03.650392 TX Vref Scan disable
7741 12:48:03.657283 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7742 12:48:03.657850 == TX Byte 0 ==
7743 12:48:03.660196 u2DelayCellOfst[0]=18 cells (5 PI)
7744 12:48:03.663423 u2DelayCellOfst[1]=18 cells (5 PI)
7745 12:48:03.666589 u2DelayCellOfst[2]=15 cells (4 PI)
7746 12:48:03.670343 u2DelayCellOfst[3]=18 cells (5 PI)
7747 12:48:03.673395 u2DelayCellOfst[4]=11 cells (3 PI)
7748 12:48:03.676385 u2DelayCellOfst[5]=0 cells (0 PI)
7749 12:48:03.680361 u2DelayCellOfst[6]=18 cells (5 PI)
7750 12:48:03.683265 u2DelayCellOfst[7]=22 cells (6 PI)
7751 12:48:03.686934 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7752 12:48:03.689707 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7753 12:48:03.693052 == TX Byte 1 ==
7754 12:48:03.696349 u2DelayCellOfst[8]=0 cells (0 PI)
7755 12:48:03.699962 u2DelayCellOfst[9]=3 cells (1 PI)
7756 12:48:03.702676 u2DelayCellOfst[10]=7 cells (2 PI)
7757 12:48:03.706089 u2DelayCellOfst[11]=3 cells (1 PI)
7758 12:48:03.709496 u2DelayCellOfst[12]=15 cells (4 PI)
7759 12:48:03.709957 u2DelayCellOfst[13]=11 cells (3 PI)
7760 12:48:03.712538 u2DelayCellOfst[14]=15 cells (4 PI)
7761 12:48:03.716247 u2DelayCellOfst[15]=11 cells (3 PI)
7762 12:48:03.722497 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7763 12:48:03.725960 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7764 12:48:03.726428 DramC Write-DBI on
7765 12:48:03.729072 ==
7766 12:48:03.733327 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 12:48:03.736621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 12:48:03.737091 ==
7769 12:48:03.737462
7770 12:48:03.737806
7771 12:48:03.739059 TX Vref Scan disable
7772 12:48:03.739480 == TX Byte 0 ==
7773 12:48:03.746004 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7774 12:48:03.746578 == TX Byte 1 ==
7775 12:48:03.749085 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7776 12:48:03.752309 DramC Write-DBI off
7777 12:48:03.752906
7778 12:48:03.753280 [DATLAT]
7779 12:48:03.756322 Freq=1600, CH0 RK0
7780 12:48:03.756928
7781 12:48:03.757302 DATLAT Default: 0xf
7782 12:48:03.759079 0, 0xFFFF, sum = 0
7783 12:48:03.762130 1, 0xFFFF, sum = 0
7784 12:48:03.762710 2, 0xFFFF, sum = 0
7785 12:48:03.766114 3, 0xFFFF, sum = 0
7786 12:48:03.766689 4, 0xFFFF, sum = 0
7787 12:48:03.768681 5, 0xFFFF, sum = 0
7788 12:48:03.769223 6, 0xFFFF, sum = 0
7789 12:48:03.772210 7, 0xFFFF, sum = 0
7790 12:48:03.772736 8, 0xFFFF, sum = 0
7791 12:48:03.775464 9, 0xFFFF, sum = 0
7792 12:48:03.776038 10, 0xFFFF, sum = 0
7793 12:48:03.779130 11, 0xFFFF, sum = 0
7794 12:48:03.779708 12, 0xFFFF, sum = 0
7795 12:48:03.782557 13, 0xFFFF, sum = 0
7796 12:48:03.783135 14, 0x0, sum = 1
7797 12:48:03.785235 15, 0x0, sum = 2
7798 12:48:03.785707 16, 0x0, sum = 3
7799 12:48:03.788875 17, 0x0, sum = 4
7800 12:48:03.789344 best_step = 15
7801 12:48:03.789711
7802 12:48:03.790053 ==
7803 12:48:03.792174 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 12:48:03.798465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 12:48:03.798938 ==
7806 12:48:03.799308 RX Vref Scan: 1
7807 12:48:03.799656
7808 12:48:03.801685 Set Vref Range= 24 -> 127
7809 12:48:03.802109
7810 12:48:03.804729 RX Vref 24 -> 127, step: 1
7811 12:48:03.805152
7812 12:48:03.805490 RX Delay 11 -> 252, step: 4
7813 12:48:03.808291
7814 12:48:03.808753 Set Vref, RX VrefLevel [Byte0]: 24
7815 12:48:03.811932 [Byte1]: 24
7816 12:48:03.816140
7817 12:48:03.816594 Set Vref, RX VrefLevel [Byte0]: 25
7818 12:48:03.818915 [Byte1]: 25
7819 12:48:03.823762
7820 12:48:03.824212 Set Vref, RX VrefLevel [Byte0]: 26
7821 12:48:03.826636 [Byte1]: 26
7822 12:48:03.831439
7823 12:48:03.831869 Set Vref, RX VrefLevel [Byte0]: 27
7824 12:48:03.834149 [Byte1]: 27
7825 12:48:03.838708
7826 12:48:03.839226 Set Vref, RX VrefLevel [Byte0]: 28
7827 12:48:03.842604 [Byte1]: 28
7828 12:48:03.846670
7829 12:48:03.847189 Set Vref, RX VrefLevel [Byte0]: 29
7830 12:48:03.849765 [Byte1]: 29
7831 12:48:03.853816
7832 12:48:03.854333 Set Vref, RX VrefLevel [Byte0]: 30
7833 12:48:03.860512 [Byte1]: 30
7834 12:48:03.861064
7835 12:48:03.863905 Set Vref, RX VrefLevel [Byte0]: 31
7836 12:48:03.866768 [Byte1]: 31
7837 12:48:03.867252
7838 12:48:03.870260 Set Vref, RX VrefLevel [Byte0]: 32
7839 12:48:03.873552 [Byte1]: 32
7840 12:48:03.876547
7841 12:48:03.877015 Set Vref, RX VrefLevel [Byte0]: 33
7842 12:48:03.880378 [Byte1]: 33
7843 12:48:03.885017
7844 12:48:03.885583 Set Vref, RX VrefLevel [Byte0]: 34
7845 12:48:03.887933 [Byte1]: 34
7846 12:48:03.892744
7847 12:48:03.893303 Set Vref, RX VrefLevel [Byte0]: 35
7848 12:48:03.895418 [Byte1]: 35
7849 12:48:03.899838
7850 12:48:03.900402 Set Vref, RX VrefLevel [Byte0]: 36
7851 12:48:03.902958 [Byte1]: 36
7852 12:48:03.907569
7853 12:48:03.908251 Set Vref, RX VrefLevel [Byte0]: 37
7854 12:48:03.910445 [Byte1]: 37
7855 12:48:03.915166
7856 12:48:03.915762 Set Vref, RX VrefLevel [Byte0]: 38
7857 12:48:03.918823 [Byte1]: 38
7858 12:48:03.922558
7859 12:48:03.923016 Set Vref, RX VrefLevel [Byte0]: 39
7860 12:48:03.925939 [Byte1]: 39
7861 12:48:03.929990
7862 12:48:03.930467 Set Vref, RX VrefLevel [Byte0]: 40
7863 12:48:03.933244 [Byte1]: 40
7864 12:48:03.937617
7865 12:48:03.938075 Set Vref, RX VrefLevel [Byte0]: 41
7866 12:48:03.941168 [Byte1]: 41
7867 12:48:03.945046
7868 12:48:03.945505 Set Vref, RX VrefLevel [Byte0]: 42
7869 12:48:03.948577 [Byte1]: 42
7870 12:48:03.952657
7871 12:48:03.953072 Set Vref, RX VrefLevel [Byte0]: 43
7872 12:48:03.956018 [Byte1]: 43
7873 12:48:03.960421
7874 12:48:03.960867 Set Vref, RX VrefLevel [Byte0]: 44
7875 12:48:03.963869 [Byte1]: 44
7876 12:48:03.968986
7877 12:48:03.969598 Set Vref, RX VrefLevel [Byte0]: 45
7878 12:48:03.971475 [Byte1]: 45
7879 12:48:03.975658
7880 12:48:03.976117 Set Vref, RX VrefLevel [Byte0]: 46
7881 12:48:03.979414 [Byte1]: 46
7882 12:48:03.983432
7883 12:48:03.983990 Set Vref, RX VrefLevel [Byte0]: 47
7884 12:48:03.987150 [Byte1]: 47
7885 12:48:03.990966
7886 12:48:03.991427 Set Vref, RX VrefLevel [Byte0]: 48
7887 12:48:03.994580 [Byte1]: 48
7888 12:48:03.999393
7889 12:48:03.999956 Set Vref, RX VrefLevel [Byte0]: 49
7890 12:48:04.002419 [Byte1]: 49
7891 12:48:04.006030
7892 12:48:04.006485 Set Vref, RX VrefLevel [Byte0]: 50
7893 12:48:04.009430 [Byte1]: 50
7894 12:48:04.013566
7895 12:48:04.014032 Set Vref, RX VrefLevel [Byte0]: 51
7896 12:48:04.017836 [Byte1]: 51
7897 12:48:04.021187
7898 12:48:04.021648 Set Vref, RX VrefLevel [Byte0]: 52
7899 12:48:04.025047 [Byte1]: 52
7900 12:48:04.029014
7901 12:48:04.029477 Set Vref, RX VrefLevel [Byte0]: 53
7902 12:48:04.032216 [Byte1]: 53
7903 12:48:04.036715
7904 12:48:04.037336 Set Vref, RX VrefLevel [Byte0]: 54
7905 12:48:04.039974 [Byte1]: 54
7906 12:48:04.044642
7907 12:48:04.045207 Set Vref, RX VrefLevel [Byte0]: 55
7908 12:48:04.047562 [Byte1]: 55
7909 12:48:04.052009
7910 12:48:04.052468 Set Vref, RX VrefLevel [Byte0]: 56
7911 12:48:04.055029 [Byte1]: 56
7912 12:48:04.059891
7913 12:48:04.060304 Set Vref, RX VrefLevel [Byte0]: 57
7914 12:48:04.062097 [Byte1]: 57
7915 12:48:04.066648
7916 12:48:04.066729 Set Vref, RX VrefLevel [Byte0]: 58
7917 12:48:04.070431 [Byte1]: 58
7918 12:48:04.074130
7919 12:48:04.074211 Set Vref, RX VrefLevel [Byte0]: 59
7920 12:48:04.077655 [Byte1]: 59
7921 12:48:04.081964
7922 12:48:04.082050 Set Vref, RX VrefLevel [Byte0]: 60
7923 12:48:04.085933 [Byte1]: 60
7924 12:48:04.089245
7925 12:48:04.089338 Set Vref, RX VrefLevel [Byte0]: 61
7926 12:48:04.092605 [Byte1]: 61
7927 12:48:04.097034
7928 12:48:04.097143 Set Vref, RX VrefLevel [Byte0]: 62
7929 12:48:04.100403 [Byte1]: 62
7930 12:48:04.105330
7931 12:48:04.105748 Set Vref, RX VrefLevel [Byte0]: 63
7932 12:48:04.108495 [Byte1]: 63
7933 12:48:04.112698
7934 12:48:04.113217 Set Vref, RX VrefLevel [Byte0]: 64
7935 12:48:04.116073 [Byte1]: 64
7936 12:48:04.120726
7937 12:48:04.121293 Set Vref, RX VrefLevel [Byte0]: 65
7938 12:48:04.123663 [Byte1]: 65
7939 12:48:04.127900
7940 12:48:04.128454 Set Vref, RX VrefLevel [Byte0]: 66
7941 12:48:04.131373 [Byte1]: 66
7942 12:48:04.135765
7943 12:48:04.136319 Set Vref, RX VrefLevel [Byte0]: 67
7944 12:48:04.138811 [Byte1]: 67
7945 12:48:04.143436
7946 12:48:04.143907 Set Vref, RX VrefLevel [Byte0]: 68
7947 12:48:04.146400 [Byte1]: 68
7948 12:48:04.151049
7949 12:48:04.151506 Set Vref, RX VrefLevel [Byte0]: 69
7950 12:48:04.154073 [Byte1]: 69
7951 12:48:04.159103
7952 12:48:04.159670 Set Vref, RX VrefLevel [Byte0]: 70
7953 12:48:04.161559 [Byte1]: 70
7954 12:48:04.166542
7955 12:48:04.167098 Set Vref, RX VrefLevel [Byte0]: 71
7956 12:48:04.169643 [Byte1]: 71
7957 12:48:04.173759
7958 12:48:04.174445 Set Vref, RX VrefLevel [Byte0]: 72
7959 12:48:04.177255 [Byte1]: 72
7960 12:48:04.180997
7961 12:48:04.181475 Set Vref, RX VrefLevel [Byte0]: 73
7962 12:48:04.184556 [Byte1]: 73
7963 12:48:04.188657
7964 12:48:04.189133 Set Vref, RX VrefLevel [Byte0]: 74
7965 12:48:04.192277 [Byte1]: 74
7966 12:48:04.196483
7967 12:48:04.196952 Set Vref, RX VrefLevel [Byte0]: 75
7968 12:48:04.200031 [Byte1]: 75
7969 12:48:04.203846
7970 12:48:04.204277 Set Vref, RX VrefLevel [Byte0]: 76
7971 12:48:04.207260 [Byte1]: 76
7972 12:48:04.211515
7973 12:48:04.211945 Set Vref, RX VrefLevel [Byte0]: 77
7974 12:48:04.215151 [Byte1]: 77
7975 12:48:04.219242
7976 12:48:04.219673 Set Vref, RX VrefLevel [Byte0]: 78
7977 12:48:04.222512 [Byte1]: 78
7978 12:48:04.226822
7979 12:48:04.227253 Set Vref, RX VrefLevel [Byte0]: 79
7980 12:48:04.229903 [Byte1]: 79
7981 12:48:04.234608
7982 12:48:04.235040 Final RX Vref Byte 0 = 66 to rank0
7983 12:48:04.238151 Final RX Vref Byte 1 = 58 to rank0
7984 12:48:04.241479 Final RX Vref Byte 0 = 66 to rank1
7985 12:48:04.244460 Final RX Vref Byte 1 = 58 to rank1==
7986 12:48:04.247823 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 12:48:04.254987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 12:48:04.255546 ==
7989 12:48:04.256002 DQS Delay:
7990 12:48:04.257873 DQS0 = 0, DQS1 = 0
7991 12:48:04.258416 DQM Delay:
7992 12:48:04.258860 DQM0 = 133, DQM1 = 123
7993 12:48:04.260992 DQ Delay:
7994 12:48:04.264675 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
7995 12:48:04.267323 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
7996 12:48:04.270705 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
7997 12:48:04.273807 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
7998 12:48:04.274269
7999 12:48:04.274709
8000 12:48:04.275134
8001 12:48:04.277610 [DramC_TX_OE_Calibration] TA2
8002 12:48:04.280609 Original DQ_B0 (3 6) =30, OEN = 27
8003 12:48:04.283809 Original DQ_B1 (3 6) =30, OEN = 27
8004 12:48:04.287235 24, 0x0, End_B0=24 End_B1=24
8005 12:48:04.287676 25, 0x0, End_B0=25 End_B1=25
8006 12:48:04.290545 26, 0x0, End_B0=26 End_B1=26
8007 12:48:04.294051 27, 0x0, End_B0=27 End_B1=27
8008 12:48:04.297044 28, 0x0, End_B0=28 End_B1=28
8009 12:48:04.300770 29, 0x0, End_B0=29 End_B1=29
8010 12:48:04.301310 30, 0x0, End_B0=30 End_B1=30
8011 12:48:04.303700 31, 0x4141, End_B0=30 End_B1=30
8012 12:48:04.307109 Byte0 end_step=30 best_step=27
8013 12:48:04.310253 Byte1 end_step=30 best_step=27
8014 12:48:04.313703 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 12:48:04.317145 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 12:48:04.317662
8017 12:48:04.318046
8018 12:48:04.323509 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f11, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8019 12:48:04.326811 CH0 RK0: MR19=303, MR18=1F11
8020 12:48:04.333179 CH0_RK0: MR19=0x303, MR18=0x1F11, DQSOSC=394, MR23=63, INC=23, DEC=15
8021 12:48:04.333607
8022 12:48:04.336641 ----->DramcWriteLeveling(PI) begin...
8023 12:48:04.337078 ==
8024 12:48:04.340085 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 12:48:04.343514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 12:48:04.344082 ==
8027 12:48:04.346598 Write leveling (Byte 0): 35 => 35
8028 12:48:04.350227 Write leveling (Byte 1): 26 => 26
8029 12:48:04.353076 DramcWriteLeveling(PI) end<-----
8030 12:48:04.353502
8031 12:48:04.353840 ==
8032 12:48:04.357200 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 12:48:04.360347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 12:48:04.363363 ==
8035 12:48:04.363835 [Gating] SW mode calibration
8036 12:48:04.373326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 12:48:04.376036 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 12:48:04.379932 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 12:48:04.386267 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 12:48:04.389347 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 12:48:04.392814 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8042 12:48:04.399966 1 4 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8043 12:48:04.403113 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
8044 12:48:04.406027 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 12:48:04.413066 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 12:48:04.416048 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 12:48:04.419288 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 12:48:04.426154 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8049 12:48:04.429114 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8050 12:48:04.432213 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8051 12:48:04.439557 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8052 12:48:04.442108 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 12:48:04.446225 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 12:48:04.452193 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 12:48:04.455372 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 12:48:04.458702 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 12:48:04.465688 1 6 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8058 12:48:04.469011 1 6 16 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
8059 12:48:04.471996 1 6 20 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
8060 12:48:04.478531 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 12:48:04.482319 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 12:48:04.485188 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 12:48:04.491658 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 12:48:04.495053 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8065 12:48:04.498796 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8066 12:48:04.505023 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8067 12:48:04.508670 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8068 12:48:04.511374 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 12:48:04.517831 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 12:48:04.520973 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 12:48:04.524761 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 12:48:04.530896 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 12:48:04.534250 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 12:48:04.538022 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 12:48:04.544212 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 12:48:04.548066 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 12:48:04.551265 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 12:48:04.557238 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 12:48:04.561040 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 12:48:04.564136 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 12:48:04.570346 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8082 12:48:04.573576 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8083 12:48:04.577345 Total UI for P1: 0, mck2ui 16
8084 12:48:04.580159 best dqsien dly found for B0: ( 1, 9, 12)
8085 12:48:04.583815 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8086 12:48:04.590352 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 12:48:04.593555 Total UI for P1: 0, mck2ui 16
8088 12:48:04.596699 best dqsien dly found for B1: ( 1, 9, 16)
8089 12:48:04.599882 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8090 12:48:04.603599 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8091 12:48:04.604049
8092 12:48:04.607087 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8093 12:48:04.609946 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8094 12:48:04.613395 [Gating] SW calibration Done
8095 12:48:04.613821 ==
8096 12:48:04.616887 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 12:48:04.620390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 12:48:04.620864 ==
8099 12:48:04.623512 RX Vref Scan: 0
8100 12:48:04.624143
8101 12:48:04.626242 RX Vref 0 -> 0, step: 1
8102 12:48:04.626669
8103 12:48:04.627008 RX Delay 0 -> 252, step: 8
8104 12:48:04.633005 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8105 12:48:04.636926 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8106 12:48:04.639797 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8107 12:48:04.643128 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8108 12:48:04.646441 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8109 12:48:04.652711 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8110 12:48:04.655963 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8111 12:48:04.659257 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8112 12:48:04.662842 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8113 12:48:04.668994 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8114 12:48:04.672807 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8115 12:48:04.675753 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8116 12:48:04.679017 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8117 12:48:04.682231 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8118 12:48:04.688598 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8119 12:48:04.692331 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8120 12:48:04.692611 ==
8121 12:48:04.695397 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 12:48:04.698950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 12:48:04.699180 ==
8124 12:48:04.702033 DQS Delay:
8125 12:48:04.702314 DQS0 = 0, DQS1 = 0
8126 12:48:04.702547 DQM Delay:
8127 12:48:04.705113 DQM0 = 133, DQM1 = 128
8128 12:48:04.705402 DQ Delay:
8129 12:48:04.708298 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8130 12:48:04.715469 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8131 12:48:04.718729 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8132 12:48:04.721913 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8133 12:48:04.722230
8134 12:48:04.722423
8135 12:48:04.722595 ==
8136 12:48:04.725266 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 12:48:04.728412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 12:48:04.728686 ==
8139 12:48:04.728875
8140 12:48:04.729045
8141 12:48:04.731435 TX Vref Scan disable
8142 12:48:04.735198 == TX Byte 0 ==
8143 12:48:04.738669 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8144 12:48:04.741728 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8145 12:48:04.744782 == TX Byte 1 ==
8146 12:48:04.748566 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8147 12:48:04.752079 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8148 12:48:04.752496 ==
8149 12:48:04.754894 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 12:48:04.761218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 12:48:04.761668 ==
8152 12:48:04.774382
8153 12:48:04.776867 TX Vref early break, caculate TX vref
8154 12:48:04.780696 TX Vref=16, minBit 5, minWin=22, winSum=374
8155 12:48:04.783462 TX Vref=18, minBit 1, minWin=23, winSum=385
8156 12:48:04.787121 TX Vref=20, minBit 3, minWin=23, winSum=391
8157 12:48:04.790165 TX Vref=22, minBit 8, minWin=23, winSum=393
8158 12:48:04.793499 TX Vref=24, minBit 1, minWin=24, winSum=407
8159 12:48:04.799947 TX Vref=26, minBit 0, minWin=24, winSum=409
8160 12:48:04.803179 TX Vref=28, minBit 0, minWin=24, winSum=410
8161 12:48:04.806991 TX Vref=30, minBit 1, minWin=24, winSum=404
8162 12:48:04.810302 TX Vref=32, minBit 0, minWin=23, winSum=393
8163 12:48:04.813386 TX Vref=34, minBit 6, minWin=23, winSum=388
8164 12:48:04.820209 [TxChooseVref] Worse bit 0, Min win 24, Win sum 410, Final Vref 28
8165 12:48:04.820658
8166 12:48:04.823260 Final TX Range 0 Vref 28
8167 12:48:04.823679
8168 12:48:04.824008 ==
8169 12:48:04.826777 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 12:48:04.829875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 12:48:04.830295 ==
8172 12:48:04.830630
8173 12:48:04.830936
8174 12:48:04.833203 TX Vref Scan disable
8175 12:48:04.839571 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8176 12:48:04.839989 == TX Byte 0 ==
8177 12:48:04.843084 u2DelayCellOfst[0]=11 cells (3 PI)
8178 12:48:04.846171 u2DelayCellOfst[1]=15 cells (4 PI)
8179 12:48:04.849782 u2DelayCellOfst[2]=11 cells (3 PI)
8180 12:48:04.852601 u2DelayCellOfst[3]=15 cells (4 PI)
8181 12:48:04.856425 u2DelayCellOfst[4]=7 cells (2 PI)
8182 12:48:04.859408 u2DelayCellOfst[5]=0 cells (0 PI)
8183 12:48:04.862962 u2DelayCellOfst[6]=15 cells (4 PI)
8184 12:48:04.866015 u2DelayCellOfst[7]=18 cells (5 PI)
8185 12:48:04.869433 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8186 12:48:04.873842 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8187 12:48:04.875940 == TX Byte 1 ==
8188 12:48:04.879274 u2DelayCellOfst[8]=0 cells (0 PI)
8189 12:48:04.883237 u2DelayCellOfst[9]=3 cells (1 PI)
8190 12:48:04.883826 u2DelayCellOfst[10]=7 cells (2 PI)
8191 12:48:04.886080 u2DelayCellOfst[11]=3 cells (1 PI)
8192 12:48:04.889616 u2DelayCellOfst[12]=11 cells (3 PI)
8193 12:48:04.892586 u2DelayCellOfst[13]=11 cells (3 PI)
8194 12:48:04.896127 u2DelayCellOfst[14]=15 cells (4 PI)
8195 12:48:04.899719 u2DelayCellOfst[15]=11 cells (3 PI)
8196 12:48:04.906527 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8197 12:48:04.910393 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8198 12:48:04.910821 DramC Write-DBI on
8199 12:48:04.911152 ==
8200 12:48:04.912417 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 12:48:04.919143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 12:48:04.919575 ==
8203 12:48:04.919915
8204 12:48:04.920228
8205 12:48:04.920567 TX Vref Scan disable
8206 12:48:04.923389 == TX Byte 0 ==
8207 12:48:04.926561 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8208 12:48:04.930304 == TX Byte 1 ==
8209 12:48:04.933408 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8210 12:48:04.936414 DramC Write-DBI off
8211 12:48:04.936862
8212 12:48:04.937198 [DATLAT]
8213 12:48:04.937507 Freq=1600, CH0 RK1
8214 12:48:04.937809
8215 12:48:04.939701 DATLAT Default: 0xf
8216 12:48:04.943181 0, 0xFFFF, sum = 0
8217 12:48:04.943642 1, 0xFFFF, sum = 0
8218 12:48:04.946764 2, 0xFFFF, sum = 0
8219 12:48:04.947195 3, 0xFFFF, sum = 0
8220 12:48:04.950102 4, 0xFFFF, sum = 0
8221 12:48:04.950558 5, 0xFFFF, sum = 0
8222 12:48:04.952771 6, 0xFFFF, sum = 0
8223 12:48:04.953200 7, 0xFFFF, sum = 0
8224 12:48:04.956010 8, 0xFFFF, sum = 0
8225 12:48:04.956454 9, 0xFFFF, sum = 0
8226 12:48:04.959792 10, 0xFFFF, sum = 0
8227 12:48:04.960253 11, 0xFFFF, sum = 0
8228 12:48:04.963021 12, 0xFFFF, sum = 0
8229 12:48:04.963453 13, 0xFFFF, sum = 0
8230 12:48:04.966219 14, 0x0, sum = 1
8231 12:48:04.966671 15, 0x0, sum = 2
8232 12:48:04.969473 16, 0x0, sum = 3
8233 12:48:04.969905 17, 0x0, sum = 4
8234 12:48:04.972744 best_step = 15
8235 12:48:04.973165
8236 12:48:04.973524 ==
8237 12:48:04.975969 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 12:48:04.979456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 12:48:04.980093 ==
8240 12:48:04.982826 RX Vref Scan: 0
8241 12:48:04.983267
8242 12:48:04.983640 RX Vref 0 -> 0, step: 1
8243 12:48:04.984098
8244 12:48:04.986032 RX Delay 11 -> 252, step: 4
8245 12:48:04.992506 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8246 12:48:04.995991 iDelay=191, Bit 1, Center 134 (79 ~ 190) 112
8247 12:48:04.999027 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8248 12:48:05.002354 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
8249 12:48:05.005374 iDelay=191, Bit 4, Center 132 (79 ~ 186) 108
8250 12:48:05.012550 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8251 12:48:05.015714 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8252 12:48:05.018787 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8253 12:48:05.022062 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8254 12:48:05.025304 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8255 12:48:05.032232 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8256 12:48:05.035450 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8257 12:48:05.038546 iDelay=191, Bit 12, Center 132 (79 ~ 186) 108
8258 12:48:05.041714 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8259 12:48:05.048117 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8260 12:48:05.051570 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8261 12:48:05.052012 ==
8262 12:48:05.055169 Dram Type= 6, Freq= 0, CH_0, rank 1
8263 12:48:05.058406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 12:48:05.058834 ==
8265 12:48:05.061832 DQS Delay:
8266 12:48:05.062369 DQS0 = 0, DQS1 = 0
8267 12:48:05.062712 DQM Delay:
8268 12:48:05.065138 DQM0 = 130, DQM1 = 125
8269 12:48:05.065558 DQ Delay:
8270 12:48:05.068137 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8271 12:48:05.071199 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
8272 12:48:05.078068 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8273 12:48:05.081007 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8274 12:48:05.081465
8275 12:48:05.081808
8276 12:48:05.082151
8277 12:48:05.084408 [DramC_TX_OE_Calibration] TA2
8278 12:48:05.087810 Original DQ_B0 (3 6) =30, OEN = 27
8279 12:48:05.091205 Original DQ_B1 (3 6) =30, OEN = 27
8280 12:48:05.091626 24, 0x0, End_B0=24 End_B1=24
8281 12:48:05.094166 25, 0x0, End_B0=25 End_B1=25
8282 12:48:05.097746 26, 0x0, End_B0=26 End_B1=26
8283 12:48:05.101159 27, 0x0, End_B0=27 End_B1=27
8284 12:48:05.101589 28, 0x0, End_B0=28 End_B1=28
8285 12:48:05.104136 29, 0x0, End_B0=29 End_B1=29
8286 12:48:05.107621 30, 0x0, End_B0=30 End_B1=30
8287 12:48:05.110671 31, 0x4141, End_B0=30 End_B1=30
8288 12:48:05.113923 Byte0 end_step=30 best_step=27
8289 12:48:05.117624 Byte1 end_step=30 best_step=27
8290 12:48:05.120662 Byte0 TX OE(2T, 0.5T) = (3, 3)
8291 12:48:05.121087 Byte1 TX OE(2T, 0.5T) = (3, 3)
8292 12:48:05.121425
8293 12:48:05.121734
8294 12:48:05.130595 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8295 12:48:05.133564 CH0 RK1: MR19=303, MR18=1E01
8296 12:48:05.140303 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8297 12:48:05.140756 [RxdqsGatingPostProcess] freq 1600
8298 12:48:05.147504 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8299 12:48:05.150560 best DQS0 dly(2T, 0.5T) = (1, 1)
8300 12:48:05.153453 best DQS1 dly(2T, 0.5T) = (1, 1)
8301 12:48:05.156975 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8302 12:48:05.160124 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8303 12:48:05.163673 best DQS0 dly(2T, 0.5T) = (1, 1)
8304 12:48:05.166678 best DQS1 dly(2T, 0.5T) = (1, 1)
8305 12:48:05.169991 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8306 12:48:05.173206 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8307 12:48:05.176739 Pre-setting of DQS Precalculation
8308 12:48:05.180239 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8309 12:48:05.180696 ==
8310 12:48:05.183306 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 12:48:05.186995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 12:48:05.187433 ==
8313 12:48:05.192979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8314 12:48:05.197334 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8315 12:48:05.203067 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8316 12:48:05.206188 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8317 12:48:05.216272 [CA 0] Center 41 (11~71) winsize 61
8318 12:48:05.219786 [CA 1] Center 42 (12~72) winsize 61
8319 12:48:05.223391 [CA 2] Center 37 (8~66) winsize 59
8320 12:48:05.226378 [CA 3] Center 36 (7~65) winsize 59
8321 12:48:05.230078 [CA 4] Center 37 (8~66) winsize 59
8322 12:48:05.233288 [CA 5] Center 36 (6~66) winsize 61
8323 12:48:05.233703
8324 12:48:05.236333 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8325 12:48:05.236804
8326 12:48:05.239658 [CATrainingPosCal] consider 1 rank data
8327 12:48:05.242929 u2DelayCellTimex100 = 258/100 ps
8328 12:48:05.249737 CA0 delay=41 (11~71),Diff = 5 PI (18 cell)
8329 12:48:05.253132 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8330 12:48:05.256320 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 12:48:05.259322 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8332 12:48:05.262797 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8333 12:48:05.266167 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8334 12:48:05.266593
8335 12:48:05.269561 CA PerBit enable=1, Macro0, CA PI delay=36
8336 12:48:05.270077
8337 12:48:05.272903 [CBTSetCACLKResult] CA Dly = 36
8338 12:48:05.275887 CS Dly: 9 (0~40)
8339 12:48:05.279334 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8340 12:48:05.282594 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8341 12:48:05.283004 ==
8342 12:48:05.285678 Dram Type= 6, Freq= 0, CH_1, rank 1
8343 12:48:05.292634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 12:48:05.293179 ==
8345 12:48:05.295648 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8346 12:48:05.301918 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8347 12:48:05.305864 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8348 12:48:05.312008 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8349 12:48:05.319537 [CA 0] Center 42 (12~72) winsize 61
8350 12:48:05.323030 [CA 1] Center 42 (12~72) winsize 61
8351 12:48:05.326283 [CA 2] Center 37 (8~67) winsize 60
8352 12:48:05.329930 [CA 3] Center 37 (8~66) winsize 59
8353 12:48:05.332667 [CA 4] Center 37 (8~67) winsize 60
8354 12:48:05.336436 [CA 5] Center 37 (7~67) winsize 61
8355 12:48:05.336903
8356 12:48:05.339548 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8357 12:48:05.339968
8358 12:48:05.342509 [CATrainingPosCal] consider 2 rank data
8359 12:48:05.345794 u2DelayCellTimex100 = 258/100 ps
8360 12:48:05.352550 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8361 12:48:05.356246 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8362 12:48:05.358928 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8363 12:48:05.362677 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8364 12:48:05.365658 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8365 12:48:05.369474 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8366 12:48:05.369905
8367 12:48:05.372449 CA PerBit enable=1, Macro0, CA PI delay=36
8368 12:48:05.372912
8369 12:48:05.376020 [CBTSetCACLKResult] CA Dly = 36
8370 12:48:05.379516 CS Dly: 10 (0~43)
8371 12:48:05.382876 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8372 12:48:05.385398 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8373 12:48:05.385818
8374 12:48:05.389013 ----->DramcWriteLeveling(PI) begin...
8375 12:48:05.389439 ==
8376 12:48:05.392440 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 12:48:05.398718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 12:48:05.399211 ==
8379 12:48:05.401803 Write leveling (Byte 0): 22 => 22
8380 12:48:05.406193 Write leveling (Byte 1): 28 => 28
8381 12:48:05.406618 DramcWriteLeveling(PI) end<-----
8382 12:48:05.408636
8383 12:48:05.409064 ==
8384 12:48:05.411699 Dram Type= 6, Freq= 0, CH_1, rank 0
8385 12:48:05.415319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 12:48:05.415759 ==
8387 12:48:05.418040 [Gating] SW mode calibration
8388 12:48:05.424852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8389 12:48:05.431324 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8390 12:48:05.434998 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 12:48:05.437877 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 12:48:05.444667 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 12:48:05.448297 1 4 12 | B1->B0 | 2c2c 3131 | 1 0 | (1 1) (1 1)
8394 12:48:05.451469 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 12:48:05.458188 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 12:48:05.461084 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 12:48:05.464570 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 12:48:05.470810 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 12:48:05.474553 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 12:48:05.477651 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8401 12:48:05.484419 1 5 12 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
8402 12:48:05.488039 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8403 12:48:05.490965 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 12:48:05.497377 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 12:48:05.501263 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 12:48:05.504403 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 12:48:05.510493 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 12:48:05.514310 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8409 12:48:05.517056 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8410 12:48:05.523956 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 12:48:05.527279 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 12:48:05.530326 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 12:48:05.536666 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 12:48:05.540090 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 12:48:05.543612 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 12:48:05.550373 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8417 12:48:05.553453 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8418 12:48:05.557329 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8419 12:48:05.563932 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 12:48:05.566323 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 12:48:05.569755 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 12:48:05.576578 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 12:48:05.579722 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 12:48:05.582896 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 12:48:05.589443 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 12:48:05.593111 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 12:48:05.596234 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 12:48:05.602773 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 12:48:05.605977 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 12:48:05.609440 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 12:48:05.616854 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 12:48:05.619495 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8433 12:48:05.622546 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8434 12:48:05.626197 Total UI for P1: 0, mck2ui 16
8435 12:48:05.629045 best dqsien dly found for B0: ( 1, 9, 8)
8436 12:48:05.632627 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8437 12:48:05.639457 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 12:48:05.643122 Total UI for P1: 0, mck2ui 16
8439 12:48:05.646064 best dqsien dly found for B1: ( 1, 9, 14)
8440 12:48:05.649375 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8441 12:48:05.652189 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8442 12:48:05.652660
8443 12:48:05.655612 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8444 12:48:05.658872 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8445 12:48:05.662456 [Gating] SW calibration Done
8446 12:48:05.662884 ==
8447 12:48:05.665445 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 12:48:05.668650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 12:48:05.668733 ==
8450 12:48:05.671699 RX Vref Scan: 0
8451 12:48:05.671781
8452 12:48:05.675145 RX Vref 0 -> 0, step: 1
8453 12:48:05.675228
8454 12:48:05.675294 RX Delay 0 -> 252, step: 8
8455 12:48:05.682042 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8456 12:48:05.684828 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8457 12:48:05.688125 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8458 12:48:05.691616 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8459 12:48:05.695015 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8460 12:48:05.702128 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8461 12:48:05.705286 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8462 12:48:05.708125 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8463 12:48:05.711528 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8464 12:48:05.715110 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8465 12:48:05.721154 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8466 12:48:05.724730 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8467 12:48:05.727779 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8468 12:48:05.731008 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8469 12:48:05.737827 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8470 12:48:05.740959 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8471 12:48:05.741034 ==
8472 12:48:05.744744 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 12:48:05.747739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 12:48:05.747813 ==
8475 12:48:05.751094 DQS Delay:
8476 12:48:05.751183 DQS0 = 0, DQS1 = 0
8477 12:48:05.751246 DQM Delay:
8478 12:48:05.754302 DQM0 = 138, DQM1 = 130
8479 12:48:05.754395 DQ Delay:
8480 12:48:05.757682 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8481 12:48:05.760974 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8482 12:48:05.764906 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8483 12:48:05.770989 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8484 12:48:05.771077
8485 12:48:05.771147
8486 12:48:05.771214 ==
8487 12:48:05.774290 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 12:48:05.777807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 12:48:05.777981 ==
8490 12:48:05.778065
8491 12:48:05.778143
8492 12:48:05.781032 TX Vref Scan disable
8493 12:48:05.781216 == TX Byte 0 ==
8494 12:48:05.788207 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8495 12:48:05.791074 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8496 12:48:05.791280 == TX Byte 1 ==
8497 12:48:05.797606 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8498 12:48:05.801114 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8499 12:48:05.801386 ==
8500 12:48:05.804374 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 12:48:05.807360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 12:48:05.807619 ==
8503 12:48:05.821959
8504 12:48:05.825087 TX Vref early break, caculate TX vref
8505 12:48:05.828399 TX Vref=16, minBit 5, minWin=21, winSum=371
8506 12:48:05.831685 TX Vref=18, minBit 5, minWin=21, winSum=377
8507 12:48:05.834774 TX Vref=20, minBit 0, minWin=22, winSum=388
8508 12:48:05.838001 TX Vref=22, minBit 5, minWin=23, winSum=400
8509 12:48:05.841481 TX Vref=24, minBit 5, minWin=23, winSum=407
8510 12:48:05.848217 TX Vref=26, minBit 0, minWin=24, winSum=412
8511 12:48:05.851800 TX Vref=28, minBit 0, minWin=24, winSum=411
8512 12:48:05.854938 TX Vref=30, minBit 0, minWin=23, winSum=406
8513 12:48:05.858435 TX Vref=32, minBit 6, minWin=23, winSum=400
8514 12:48:05.861647 TX Vref=34, minBit 0, minWin=23, winSum=388
8515 12:48:05.868415 [TxChooseVref] Worse bit 0, Min win 24, Win sum 412, Final Vref 26
8516 12:48:05.868615
8517 12:48:05.871444 Final TX Range 0 Vref 26
8518 12:48:05.871615
8519 12:48:05.871727 ==
8520 12:48:05.874826 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 12:48:05.878034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 12:48:05.878171 ==
8523 12:48:05.878277
8524 12:48:05.878386
8525 12:48:05.880864 TX Vref Scan disable
8526 12:48:05.887779 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8527 12:48:05.887857 == TX Byte 0 ==
8528 12:48:05.891469 u2DelayCellOfst[0]=18 cells (5 PI)
8529 12:48:05.894084 u2DelayCellOfst[1]=11 cells (3 PI)
8530 12:48:05.897183 u2DelayCellOfst[2]=0 cells (0 PI)
8531 12:48:05.900624 u2DelayCellOfst[3]=7 cells (2 PI)
8532 12:48:05.904019 u2DelayCellOfst[4]=11 cells (3 PI)
8533 12:48:05.906993 u2DelayCellOfst[5]=22 cells (6 PI)
8534 12:48:05.910746 u2DelayCellOfst[6]=18 cells (5 PI)
8535 12:48:05.913807 u2DelayCellOfst[7]=7 cells (2 PI)
8536 12:48:05.917642 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8537 12:48:05.920425 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8538 12:48:05.923811 == TX Byte 1 ==
8539 12:48:05.927895 u2DelayCellOfst[8]=0 cells (0 PI)
8540 12:48:05.930948 u2DelayCellOfst[9]=3 cells (1 PI)
8541 12:48:05.933790 u2DelayCellOfst[10]=15 cells (4 PI)
8542 12:48:05.933931 u2DelayCellOfst[11]=3 cells (1 PI)
8543 12:48:05.936992 u2DelayCellOfst[12]=15 cells (4 PI)
8544 12:48:05.941009 u2DelayCellOfst[13]=18 cells (5 PI)
8545 12:48:05.943960 u2DelayCellOfst[14]=18 cells (5 PI)
8546 12:48:05.947278 u2DelayCellOfst[15]=18 cells (5 PI)
8547 12:48:05.954106 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8548 12:48:05.956616 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8549 12:48:05.956697 DramC Write-DBI on
8550 12:48:05.959959 ==
8551 12:48:05.960032 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 12:48:05.966717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 12:48:05.966792 ==
8554 12:48:05.966863
8555 12:48:05.966925
8556 12:48:05.969824 TX Vref Scan disable
8557 12:48:05.969900 == TX Byte 0 ==
8558 12:48:05.976457 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8559 12:48:05.976566 == TX Byte 1 ==
8560 12:48:05.980055 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8561 12:48:05.983106 DramC Write-DBI off
8562 12:48:05.983209
8563 12:48:05.983298 [DATLAT]
8564 12:48:05.986313 Freq=1600, CH1 RK0
8565 12:48:05.986411
8566 12:48:05.986500 DATLAT Default: 0xf
8567 12:48:05.989577 0, 0xFFFF, sum = 0
8568 12:48:05.989677 1, 0xFFFF, sum = 0
8569 12:48:05.993015 2, 0xFFFF, sum = 0
8570 12:48:05.993114 3, 0xFFFF, sum = 0
8571 12:48:05.996302 4, 0xFFFF, sum = 0
8572 12:48:05.996375 5, 0xFFFF, sum = 0
8573 12:48:05.999295 6, 0xFFFF, sum = 0
8574 12:48:06.002703 7, 0xFFFF, sum = 0
8575 12:48:06.002786 8, 0xFFFF, sum = 0
8576 12:48:06.006041 9, 0xFFFF, sum = 0
8577 12:48:06.006129 10, 0xFFFF, sum = 0
8578 12:48:06.009710 11, 0xFFFF, sum = 0
8579 12:48:06.009812 12, 0xFFFF, sum = 0
8580 12:48:06.013252 13, 0xFFFF, sum = 0
8581 12:48:06.013347 14, 0x0, sum = 1
8582 12:48:06.016030 15, 0x0, sum = 2
8583 12:48:06.016133 16, 0x0, sum = 3
8584 12:48:06.019512 17, 0x0, sum = 4
8585 12:48:06.019698 best_step = 15
8586 12:48:06.019805
8587 12:48:06.019897 ==
8588 12:48:06.022786 Dram Type= 6, Freq= 0, CH_1, rank 0
8589 12:48:06.025998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8590 12:48:06.029250 ==
8591 12:48:06.029410 RX Vref Scan: 1
8592 12:48:06.029509
8593 12:48:06.032531 Set Vref Range= 24 -> 127
8594 12:48:06.032708
8595 12:48:06.035859 RX Vref 24 -> 127, step: 1
8596 12:48:06.036061
8597 12:48:06.036245 RX Delay 19 -> 252, step: 4
8598 12:48:06.036418
8599 12:48:06.038987 Set Vref, RX VrefLevel [Byte0]: 24
8600 12:48:06.042003 [Byte1]: 24
8601 12:48:06.046237
8602 12:48:06.046315 Set Vref, RX VrefLevel [Byte0]: 25
8603 12:48:06.049322 [Byte1]: 25
8604 12:48:06.053852
8605 12:48:06.053924 Set Vref, RX VrefLevel [Byte0]: 26
8606 12:48:06.056698 [Byte1]: 26
8607 12:48:06.061218
8608 12:48:06.061293 Set Vref, RX VrefLevel [Byte0]: 27
8609 12:48:06.064512 [Byte1]: 27
8610 12:48:06.068793
8611 12:48:06.068864 Set Vref, RX VrefLevel [Byte0]: 28
8612 12:48:06.072023 [Byte1]: 28
8613 12:48:06.076725
8614 12:48:06.076798 Set Vref, RX VrefLevel [Byte0]: 29
8615 12:48:06.080210 [Byte1]: 29
8616 12:48:06.083936
8617 12:48:06.084008 Set Vref, RX VrefLevel [Byte0]: 30
8618 12:48:06.087513 [Byte1]: 30
8619 12:48:06.091903
8620 12:48:06.092321 Set Vref, RX VrefLevel [Byte0]: 31
8621 12:48:06.095472 [Byte1]: 31
8622 12:48:06.099839
8623 12:48:06.100361 Set Vref, RX VrefLevel [Byte0]: 32
8624 12:48:06.102928 [Byte1]: 32
8625 12:48:06.107366
8626 12:48:06.107886 Set Vref, RX VrefLevel [Byte0]: 33
8627 12:48:06.110351 [Byte1]: 33
8628 12:48:06.115231
8629 12:48:06.115789 Set Vref, RX VrefLevel [Byte0]: 34
8630 12:48:06.117930 [Byte1]: 34
8631 12:48:06.122289
8632 12:48:06.122902 Set Vref, RX VrefLevel [Byte0]: 35
8633 12:48:06.125726 [Byte1]: 35
8634 12:48:06.129714
8635 12:48:06.130198 Set Vref, RX VrefLevel [Byte0]: 36
8636 12:48:06.133247 [Byte1]: 36
8637 12:48:06.137569
8638 12:48:06.138031 Set Vref, RX VrefLevel [Byte0]: 37
8639 12:48:06.140631 [Byte1]: 37
8640 12:48:06.145050
8641 12:48:06.145463 Set Vref, RX VrefLevel [Byte0]: 38
8642 12:48:06.148221 [Byte1]: 38
8643 12:48:06.152872
8644 12:48:06.153293 Set Vref, RX VrefLevel [Byte0]: 39
8645 12:48:06.155725 [Byte1]: 39
8646 12:48:06.160320
8647 12:48:06.160769 Set Vref, RX VrefLevel [Byte0]: 40
8648 12:48:06.163093 [Byte1]: 40
8649 12:48:06.167108
8650 12:48:06.170618 Set Vref, RX VrefLevel [Byte0]: 41
8651 12:48:06.174069 [Byte1]: 41
8652 12:48:06.174149
8653 12:48:06.177148 Set Vref, RX VrefLevel [Byte0]: 42
8654 12:48:06.180473 [Byte1]: 42
8655 12:48:06.180678
8656 12:48:06.183777 Set Vref, RX VrefLevel [Byte0]: 43
8657 12:48:06.187610 [Byte1]: 43
8658 12:48:06.187776
8659 12:48:06.190813 Set Vref, RX VrefLevel [Byte0]: 44
8660 12:48:06.193683 [Byte1]: 44
8661 12:48:06.198154
8662 12:48:06.198334 Set Vref, RX VrefLevel [Byte0]: 45
8663 12:48:06.204303 [Byte1]: 45
8664 12:48:06.204496
8665 12:48:06.207582 Set Vref, RX VrefLevel [Byte0]: 46
8666 12:48:06.210764 [Byte1]: 46
8667 12:48:06.210844
8668 12:48:06.213733 Set Vref, RX VrefLevel [Byte0]: 47
8669 12:48:06.216940 [Byte1]: 47
8670 12:48:06.220182
8671 12:48:06.220262 Set Vref, RX VrefLevel [Byte0]: 48
8672 12:48:06.223672 [Byte1]: 48
8673 12:48:06.228783
8674 12:48:06.228864 Set Vref, RX VrefLevel [Byte0]: 49
8675 12:48:06.231006 [Byte1]: 49
8676 12:48:06.235219
8677 12:48:06.239027 Set Vref, RX VrefLevel [Byte0]: 50
8678 12:48:06.241926 [Byte1]: 50
8679 12:48:06.242007
8680 12:48:06.245062 Set Vref, RX VrefLevel [Byte0]: 51
8681 12:48:06.248567 [Byte1]: 51
8682 12:48:06.248649
8683 12:48:06.252066 Set Vref, RX VrefLevel [Byte0]: 52
8684 12:48:06.254974 [Byte1]: 52
8685 12:48:06.255056
8686 12:48:06.258482 Set Vref, RX VrefLevel [Byte0]: 53
8687 12:48:06.261746 [Byte1]: 53
8688 12:48:06.265796
8689 12:48:06.265882 Set Vref, RX VrefLevel [Byte0]: 54
8690 12:48:06.269208 [Byte1]: 54
8691 12:48:06.273818
8692 12:48:06.273992 Set Vref, RX VrefLevel [Byte0]: 55
8693 12:48:06.276733 [Byte1]: 55
8694 12:48:06.280887
8695 12:48:06.281052 Set Vref, RX VrefLevel [Byte0]: 56
8696 12:48:06.284891 [Byte1]: 56
8697 12:48:06.289118
8698 12:48:06.289327 Set Vref, RX VrefLevel [Byte0]: 57
8699 12:48:06.291870 [Byte1]: 57
8700 12:48:06.296127
8701 12:48:06.296246 Set Vref, RX VrefLevel [Byte0]: 58
8702 12:48:06.299238 [Byte1]: 58
8703 12:48:06.303771
8704 12:48:06.303853 Set Vref, RX VrefLevel [Byte0]: 59
8705 12:48:06.306866 [Byte1]: 59
8706 12:48:06.311025
8707 12:48:06.311108 Set Vref, RX VrefLevel [Byte0]: 60
8708 12:48:06.314796 [Byte1]: 60
8709 12:48:06.319013
8710 12:48:06.319095 Set Vref, RX VrefLevel [Byte0]: 61
8711 12:48:06.322162 [Byte1]: 61
8712 12:48:06.326342
8713 12:48:06.326424 Set Vref, RX VrefLevel [Byte0]: 62
8714 12:48:06.329816 [Byte1]: 62
8715 12:48:06.334088
8716 12:48:06.334171 Set Vref, RX VrefLevel [Byte0]: 63
8717 12:48:06.337058 [Byte1]: 63
8718 12:48:06.341799
8719 12:48:06.341881 Set Vref, RX VrefLevel [Byte0]: 64
8720 12:48:06.345071 [Byte1]: 64
8721 12:48:06.349087
8722 12:48:06.349175 Set Vref, RX VrefLevel [Byte0]: 65
8723 12:48:06.352703 [Byte1]: 65
8724 12:48:06.356990
8725 12:48:06.357175 Set Vref, RX VrefLevel [Byte0]: 66
8726 12:48:06.360611 [Byte1]: 66
8727 12:48:06.364443
8728 12:48:06.364609 Set Vref, RX VrefLevel [Byte0]: 67
8729 12:48:06.368703 [Byte1]: 67
8730 12:48:06.372971
8731 12:48:06.373481 Set Vref, RX VrefLevel [Byte0]: 68
8732 12:48:06.375838 [Byte1]: 68
8733 12:48:06.379672
8734 12:48:06.380153 Set Vref, RX VrefLevel [Byte0]: 69
8735 12:48:06.382965 [Byte1]: 69
8736 12:48:06.386721
8737 12:48:06.386804 Set Vref, RX VrefLevel [Byte0]: 70
8738 12:48:06.390227 [Byte1]: 70
8739 12:48:06.394924
8740 12:48:06.395006 Set Vref, RX VrefLevel [Byte0]: 71
8741 12:48:06.397866 [Byte1]: 71
8742 12:48:06.402168
8743 12:48:06.402250 Set Vref, RX VrefLevel [Byte0]: 72
8744 12:48:06.405324 [Byte1]: 72
8745 12:48:06.410007
8746 12:48:06.410089 Set Vref, RX VrefLevel [Byte0]: 73
8747 12:48:06.413094 [Byte1]: 73
8748 12:48:06.417461
8749 12:48:06.417547 Final RX Vref Byte 0 = 56 to rank0
8750 12:48:06.420423 Final RX Vref Byte 1 = 60 to rank0
8751 12:48:06.423557 Final RX Vref Byte 0 = 56 to rank1
8752 12:48:06.427001 Final RX Vref Byte 1 = 60 to rank1==
8753 12:48:06.430282 Dram Type= 6, Freq= 0, CH_1, rank 0
8754 12:48:06.437283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 12:48:06.437372 ==
8756 12:48:06.437442 DQS Delay:
8757 12:48:06.440429 DQS0 = 0, DQS1 = 0
8758 12:48:06.440551 DQM Delay:
8759 12:48:06.440624 DQM0 = 134, DQM1 = 129
8760 12:48:06.443892 DQ Delay:
8761 12:48:06.447672 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8762 12:48:06.450439 DQ4 =132, DQ5 =146, DQ6 =144, DQ7 =130
8763 12:48:06.454131 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8764 12:48:06.456916 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8765 12:48:06.457081
8766 12:48:06.457183
8767 12:48:06.457276
8768 12:48:06.460358 [DramC_TX_OE_Calibration] TA2
8769 12:48:06.463366 Original DQ_B0 (3 6) =30, OEN = 27
8770 12:48:06.467071 Original DQ_B1 (3 6) =30, OEN = 27
8771 12:48:06.469829 24, 0x0, End_B0=24 End_B1=24
8772 12:48:06.473206 25, 0x0, End_B0=25 End_B1=25
8773 12:48:06.473289 26, 0x0, End_B0=26 End_B1=26
8774 12:48:06.476268 27, 0x0, End_B0=27 End_B1=27
8775 12:48:06.479607 28, 0x0, End_B0=28 End_B1=28
8776 12:48:06.483040 29, 0x0, End_B0=29 End_B1=29
8777 12:48:06.483149 30, 0x0, End_B0=30 End_B1=30
8778 12:48:06.486352 31, 0x5151, End_B0=30 End_B1=30
8779 12:48:06.489436 Byte0 end_step=30 best_step=27
8780 12:48:06.493293 Byte1 end_step=30 best_step=27
8781 12:48:06.496336 Byte0 TX OE(2T, 0.5T) = (3, 3)
8782 12:48:06.499590 Byte1 TX OE(2T, 0.5T) = (3, 3)
8783 12:48:06.499672
8784 12:48:06.499737
8785 12:48:06.506236 [DQSOSCAuto] RK0, (LSB)MR18= 0x150b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8786 12:48:06.509491 CH1 RK0: MR19=303, MR18=150B
8787 12:48:06.516197 CH1_RK0: MR19=0x303, MR18=0x150B, DQSOSC=399, MR23=63, INC=23, DEC=15
8788 12:48:06.516281
8789 12:48:06.519566 ----->DramcWriteLeveling(PI) begin...
8790 12:48:06.519656 ==
8791 12:48:06.523150 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 12:48:06.526072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 12:48:06.526249 ==
8794 12:48:06.529486 Write leveling (Byte 0): 24 => 24
8795 12:48:06.532717 Write leveling (Byte 1): 26 => 26
8796 12:48:06.536144 DramcWriteLeveling(PI) end<-----
8797 12:48:06.536317
8798 12:48:06.536418 ==
8799 12:48:06.539412 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 12:48:06.542790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 12:48:06.545895 ==
8802 12:48:06.546096 [Gating] SW mode calibration
8803 12:48:06.555863 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8804 12:48:06.558965 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8805 12:48:06.562001 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 12:48:06.569083 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 12:48:06.572219 1 4 8 | B1->B0 | 2726 2323 | 1 0 | (0 0) (0 0)
8808 12:48:06.575560 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8809 12:48:06.582407 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 12:48:06.585559 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 12:48:06.588789 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 12:48:06.595119 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 12:48:06.598737 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 12:48:06.602225 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 12:48:06.608864 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8816 12:48:06.611886 1 5 12 | B1->B0 | 2727 3434 | 1 1 | (1 0) (1 0)
8817 12:48:06.615504 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 12:48:06.621960 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 12:48:06.625190 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 12:48:06.628105 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 12:48:06.634634 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 12:48:06.638284 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 12:48:06.641234 1 6 8 | B1->B0 | 3333 2323 | 0 0 | (1 1) (0 0)
8824 12:48:06.647952 1 6 12 | B1->B0 | 4545 2423 | 0 1 | (0 0) (0 0)
8825 12:48:06.651204 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 12:48:06.654703 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 12:48:06.661301 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 12:48:06.664426 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 12:48:06.667502 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 12:48:06.674821 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 12:48:06.678309 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8832 12:48:06.680921 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8833 12:48:06.688150 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8834 12:48:06.690978 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8835 12:48:06.694938 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 12:48:06.701363 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 12:48:06.704461 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 12:48:06.707856 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 12:48:06.714206 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 12:48:06.717491 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 12:48:06.721320 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 12:48:06.727556 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 12:48:06.731032 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 12:48:06.733973 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 12:48:06.740395 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 12:48:06.743735 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 12:48:06.747055 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8848 12:48:06.754147 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8849 12:48:06.757196 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 12:48:06.760309 Total UI for P1: 0, mck2ui 16
8851 12:48:06.763712 best dqsien dly found for B0: ( 1, 9, 10)
8852 12:48:06.767812 Total UI for P1: 0, mck2ui 16
8853 12:48:06.770603 best dqsien dly found for B1: ( 1, 9, 10)
8854 12:48:06.774352 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8855 12:48:06.777855 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8856 12:48:06.778380
8857 12:48:06.780772 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8858 12:48:06.786883 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8859 12:48:06.787410 [Gating] SW calibration Done
8860 12:48:06.787901 ==
8861 12:48:06.790348 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 12:48:06.796766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 12:48:06.797310 ==
8864 12:48:06.797920 RX Vref Scan: 0
8865 12:48:06.798348
8866 12:48:06.800206 RX Vref 0 -> 0, step: 1
8867 12:48:06.800791
8868 12:48:06.803475 RX Delay 0 -> 252, step: 8
8869 12:48:06.806549 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8870 12:48:06.809906 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8871 12:48:06.813588 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8872 12:48:06.819925 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8873 12:48:06.823131 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8874 12:48:06.826665 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8875 12:48:06.830052 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8876 12:48:06.832925 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8877 12:48:06.839389 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8878 12:48:06.843115 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8879 12:48:06.846501 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8880 12:48:06.849741 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8881 12:48:06.852929 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8882 12:48:06.859966 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8883 12:48:06.863259 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8884 12:48:06.865943 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8885 12:48:06.866409 ==
8886 12:48:06.869228 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 12:48:06.872779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 12:48:06.875759 ==
8889 12:48:06.876218 DQS Delay:
8890 12:48:06.876779 DQS0 = 0, DQS1 = 0
8891 12:48:06.879075 DQM Delay:
8892 12:48:06.879536 DQM0 = 136, DQM1 = 129
8893 12:48:06.882384 DQ Delay:
8894 12:48:06.885845 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8895 12:48:06.888859 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8896 12:48:06.892349 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8897 12:48:06.895382 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8898 12:48:06.895967
8899 12:48:06.896485
8900 12:48:06.897024 ==
8901 12:48:06.898828 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 12:48:06.902291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 12:48:06.905807 ==
8904 12:48:06.906341
8905 12:48:06.906862
8906 12:48:06.907353 TX Vref Scan disable
8907 12:48:06.908644 == TX Byte 0 ==
8908 12:48:06.912104 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8909 12:48:06.915443 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8910 12:48:06.919075 == TX Byte 1 ==
8911 12:48:06.922249 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8912 12:48:06.926060 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8913 12:48:06.928554 ==
8914 12:48:06.928984 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 12:48:06.935142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 12:48:06.935717 ==
8917 12:48:06.947081
8918 12:48:06.950004 TX Vref early break, caculate TX vref
8919 12:48:06.953479 TX Vref=16, minBit 0, minWin=22, winSum=382
8920 12:48:06.956440 TX Vref=18, minBit 1, minWin=22, winSum=395
8921 12:48:06.960133 TX Vref=20, minBit 0, minWin=24, winSum=402
8922 12:48:06.963163 TX Vref=22, minBit 1, minWin=24, winSum=410
8923 12:48:06.966853 TX Vref=24, minBit 0, minWin=25, winSum=421
8924 12:48:06.972852 TX Vref=26, minBit 0, minWin=24, winSum=424
8925 12:48:06.976698 TX Vref=28, minBit 0, minWin=24, winSum=422
8926 12:48:06.979740 TX Vref=30, minBit 0, minWin=25, winSum=419
8927 12:48:06.982918 TX Vref=32, minBit 0, minWin=24, winSum=409
8928 12:48:06.985961 TX Vref=34, minBit 0, minWin=23, winSum=400
8929 12:48:06.993005 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 24
8930 12:48:06.993089
8931 12:48:06.995910 Final TX Range 0 Vref 24
8932 12:48:06.995992
8933 12:48:06.996057 ==
8934 12:48:07.000318 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 12:48:07.003042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 12:48:07.003206 ==
8937 12:48:07.003288
8938 12:48:07.003359
8939 12:48:07.006364 TX Vref Scan disable
8940 12:48:07.012932 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8941 12:48:07.013092 == TX Byte 0 ==
8942 12:48:07.016007 u2DelayCellOfst[0]=18 cells (5 PI)
8943 12:48:07.019987 u2DelayCellOfst[1]=11 cells (3 PI)
8944 12:48:07.023005 u2DelayCellOfst[2]=0 cells (0 PI)
8945 12:48:07.025974 u2DelayCellOfst[3]=3 cells (1 PI)
8946 12:48:07.029217 u2DelayCellOfst[4]=7 cells (2 PI)
8947 12:48:07.032367 u2DelayCellOfst[5]=22 cells (6 PI)
8948 12:48:07.036465 u2DelayCellOfst[6]=18 cells (5 PI)
8949 12:48:07.039027 u2DelayCellOfst[7]=3 cells (1 PI)
8950 12:48:07.042134 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8951 12:48:07.046034 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8952 12:48:07.049077 == TX Byte 1 ==
8953 12:48:07.052364 u2DelayCellOfst[8]=0 cells (0 PI)
8954 12:48:07.055876 u2DelayCellOfst[9]=7 cells (2 PI)
8955 12:48:07.055951 u2DelayCellOfst[10]=15 cells (4 PI)
8956 12:48:07.058705 u2DelayCellOfst[11]=7 cells (2 PI)
8957 12:48:07.062078 u2DelayCellOfst[12]=15 cells (4 PI)
8958 12:48:07.065165 u2DelayCellOfst[13]=18 cells (5 PI)
8959 12:48:07.068574 u2DelayCellOfst[14]=18 cells (5 PI)
8960 12:48:07.071962 u2DelayCellOfst[15]=18 cells (5 PI)
8961 12:48:07.079008 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8962 12:48:07.081997 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8963 12:48:07.082091 DramC Write-DBI on
8964 12:48:07.082166 ==
8965 12:48:07.085207 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 12:48:07.091871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 12:48:07.092053 ==
8968 12:48:07.092146
8969 12:48:07.092229
8970 12:48:07.095321 TX Vref Scan disable
8971 12:48:07.095509 == TX Byte 0 ==
8972 12:48:07.101748 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8973 12:48:07.101935 == TX Byte 1 ==
8974 12:48:07.104834 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8975 12:48:07.108178 DramC Write-DBI off
8976 12:48:07.108285
8977 12:48:07.108382 [DATLAT]
8978 12:48:07.111863 Freq=1600, CH1 RK1
8979 12:48:07.111963
8980 12:48:07.112060 DATLAT Default: 0xf
8981 12:48:07.114966 0, 0xFFFF, sum = 0
8982 12:48:07.115043 1, 0xFFFF, sum = 0
8983 12:48:07.118179 2, 0xFFFF, sum = 0
8984 12:48:07.118279 3, 0xFFFF, sum = 0
8985 12:48:07.121227 4, 0xFFFF, sum = 0
8986 12:48:07.121326 5, 0xFFFF, sum = 0
8987 12:48:07.124306 6, 0xFFFF, sum = 0
8988 12:48:07.128060 7, 0xFFFF, sum = 0
8989 12:48:07.128160 8, 0xFFFF, sum = 0
8990 12:48:07.131299 9, 0xFFFF, sum = 0
8991 12:48:07.131412 10, 0xFFFF, sum = 0
8992 12:48:07.134343 11, 0xFFFF, sum = 0
8993 12:48:07.134443 12, 0xFFFF, sum = 0
8994 12:48:07.138078 13, 0xFFFF, sum = 0
8995 12:48:07.138154 14, 0x0, sum = 1
8996 12:48:07.141459 15, 0x0, sum = 2
8997 12:48:07.141530 16, 0x0, sum = 3
8998 12:48:07.144136 17, 0x0, sum = 4
8999 12:48:07.144219 best_step = 15
9000 12:48:07.144352
9001 12:48:07.144441 ==
9002 12:48:07.147859 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 12:48:07.150814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 12:48:07.154337 ==
9005 12:48:07.154405 RX Vref Scan: 0
9006 12:48:07.154465
9007 12:48:07.157571 RX Vref 0 -> 0, step: 1
9008 12:48:07.157650
9009 12:48:07.160812 RX Delay 11 -> 252, step: 4
9010 12:48:07.163969 iDelay=199, Bit 0, Center 140 (87 ~ 194) 108
9011 12:48:07.167061 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9012 12:48:07.170450 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9013 12:48:07.177415 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9014 12:48:07.180333 iDelay=199, Bit 4, Center 132 (75 ~ 190) 116
9015 12:48:07.184040 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
9016 12:48:07.187470 iDelay=199, Bit 6, Center 146 (95 ~ 198) 104
9017 12:48:07.190435 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9018 12:48:07.197478 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9019 12:48:07.200659 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9020 12:48:07.204450 iDelay=199, Bit 10, Center 128 (75 ~ 182) 108
9021 12:48:07.206773 iDelay=199, Bit 11, Center 116 (63 ~ 170) 108
9022 12:48:07.210881 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9023 12:48:07.216755 iDelay=199, Bit 13, Center 134 (79 ~ 190) 112
9024 12:48:07.220316 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9025 12:48:07.223410 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9026 12:48:07.223484 ==
9027 12:48:07.227039 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 12:48:07.230592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 12:48:07.233445 ==
9030 12:48:07.233546 DQS Delay:
9031 12:48:07.233639 DQS0 = 0, DQS1 = 0
9032 12:48:07.236842 DQM Delay:
9033 12:48:07.236915 DQM0 = 134, DQM1 = 126
9034 12:48:07.239889 DQ Delay:
9035 12:48:07.243315 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9036 12:48:07.246553 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9037 12:48:07.249992 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9038 12:48:07.252992 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9039 12:48:07.253063
9040 12:48:07.253124
9041 12:48:07.253182
9042 12:48:07.256464 [DramC_TX_OE_Calibration] TA2
9043 12:48:07.259892 Original DQ_B0 (3 6) =30, OEN = 27
9044 12:48:07.263845 Original DQ_B1 (3 6) =30, OEN = 27
9045 12:48:07.266619 24, 0x0, End_B0=24 End_B1=24
9046 12:48:07.266691 25, 0x0, End_B0=25 End_B1=25
9047 12:48:07.269647 26, 0x0, End_B0=26 End_B1=26
9048 12:48:07.272775 27, 0x0, End_B0=27 End_B1=27
9049 12:48:07.276397 28, 0x0, End_B0=28 End_B1=28
9050 12:48:07.276496 29, 0x0, End_B0=29 End_B1=29
9051 12:48:07.279665 30, 0x0, End_B0=30 End_B1=30
9052 12:48:07.283009 31, 0x5151, End_B0=30 End_B1=30
9053 12:48:07.286313 Byte0 end_step=30 best_step=27
9054 12:48:07.289832 Byte1 end_step=30 best_step=27
9055 12:48:07.292821 Byte0 TX OE(2T, 0.5T) = (3, 3)
9056 12:48:07.296257 Byte1 TX OE(2T, 0.5T) = (3, 3)
9057 12:48:07.296359
9058 12:48:07.296439
9059 12:48:07.303648 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9060 12:48:07.306090 CH1 RK1: MR19=303, MR18=D09
9061 12:48:07.313121 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9062 12:48:07.316499 [RxdqsGatingPostProcess] freq 1600
9063 12:48:07.319441 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9064 12:48:07.322495 best DQS0 dly(2T, 0.5T) = (1, 1)
9065 12:48:07.326088 best DQS1 dly(2T, 0.5T) = (1, 1)
9066 12:48:07.329842 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9067 12:48:07.332589 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9068 12:48:07.335735 best DQS0 dly(2T, 0.5T) = (1, 1)
9069 12:48:07.339507 best DQS1 dly(2T, 0.5T) = (1, 1)
9070 12:48:07.343528 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9071 12:48:07.345840 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9072 12:48:07.349276 Pre-setting of DQS Precalculation
9073 12:48:07.352551 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9074 12:48:07.359599 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9075 12:48:07.369007 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9076 12:48:07.369563
9077 12:48:07.369936
9078 12:48:07.372221 [Calibration Summary] 3200 Mbps
9079 12:48:07.372850 CH 0, Rank 0
9080 12:48:07.375367 SW Impedance : PASS
9081 12:48:07.375831 DUTY Scan : NO K
9082 12:48:07.379165 ZQ Calibration : PASS
9083 12:48:07.382392 Jitter Meter : NO K
9084 12:48:07.382864 CBT Training : PASS
9085 12:48:07.385084 Write leveling : PASS
9086 12:48:07.388448 RX DQS gating : PASS
9087 12:48:07.388962 RX DQ/DQS(RDDQC) : PASS
9088 12:48:07.392102 TX DQ/DQS : PASS
9089 12:48:07.394957 RX DATLAT : PASS
9090 12:48:07.395419 RX DQ/DQS(Engine): PASS
9091 12:48:07.398153 TX OE : PASS
9092 12:48:07.398619 All Pass.
9093 12:48:07.399072
9094 12:48:07.401541 CH 0, Rank 1
9095 12:48:07.402167 SW Impedance : PASS
9096 12:48:07.405005 DUTY Scan : NO K
9097 12:48:07.405545 ZQ Calibration : PASS
9098 12:48:07.408000 Jitter Meter : NO K
9099 12:48:07.411182 CBT Training : PASS
9100 12:48:07.411757 Write leveling : PASS
9101 12:48:07.414612 RX DQS gating : PASS
9102 12:48:07.418038 RX DQ/DQS(RDDQC) : PASS
9103 12:48:07.418513 TX DQ/DQS : PASS
9104 12:48:07.421267 RX DATLAT : PASS
9105 12:48:07.424536 RX DQ/DQS(Engine): PASS
9106 12:48:07.425026 TX OE : PASS
9107 12:48:07.428010 All Pass.
9108 12:48:07.428612
9109 12:48:07.429036 CH 1, Rank 0
9110 12:48:07.431197 SW Impedance : PASS
9111 12:48:07.431791 DUTY Scan : NO K
9112 12:48:07.434310 ZQ Calibration : PASS
9113 12:48:07.437690 Jitter Meter : NO K
9114 12:48:07.438286 CBT Training : PASS
9115 12:48:07.440895 Write leveling : PASS
9116 12:48:07.445012 RX DQS gating : PASS
9117 12:48:07.445539 RX DQ/DQS(RDDQC) : PASS
9118 12:48:07.447410 TX DQ/DQS : PASS
9119 12:48:07.450995 RX DATLAT : PASS
9120 12:48:07.451574 RX DQ/DQS(Engine): PASS
9121 12:48:07.454253 TX OE : PASS
9122 12:48:07.454838 All Pass.
9123 12:48:07.455364
9124 12:48:07.457434 CH 1, Rank 1
9125 12:48:07.457946 SW Impedance : PASS
9126 12:48:07.461207 DUTY Scan : NO K
9127 12:48:07.464226 ZQ Calibration : PASS
9128 12:48:07.464807 Jitter Meter : NO K
9129 12:48:07.467558 CBT Training : PASS
9130 12:48:07.470904 Write leveling : PASS
9131 12:48:07.471312 RX DQS gating : PASS
9132 12:48:07.474032 RX DQ/DQS(RDDQC) : PASS
9133 12:48:07.477266 TX DQ/DQS : PASS
9134 12:48:07.477533 RX DATLAT : PASS
9135 12:48:07.480552 RX DQ/DQS(Engine): PASS
9136 12:48:07.480828 TX OE : PASS
9137 12:48:07.483646 All Pass.
9138 12:48:07.483885
9139 12:48:07.484101 DramC Write-DBI on
9140 12:48:07.487034 PER_BANK_REFRESH: Hybrid Mode
9141 12:48:07.490282 TX_TRACKING: ON
9142 12:48:07.496653 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9143 12:48:07.507371 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9144 12:48:07.513748 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9145 12:48:07.517144 [FAST_K] Save calibration result to emmc
9146 12:48:07.519731 sync common calibartion params.
9147 12:48:07.519829 sync cbt_mode0:1, 1:1
9148 12:48:07.523527 dram_init: ddr_geometry: 2
9149 12:48:07.526734 dram_init: ddr_geometry: 2
9150 12:48:07.529744 dram_init: ddr_geometry: 2
9151 12:48:07.529815 0:dram_rank_size:100000000
9152 12:48:07.533049 1:dram_rank_size:100000000
9153 12:48:07.539470 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9154 12:48:07.543212 DFS_SHUFFLE_HW_MODE: ON
9155 12:48:07.545983 dramc_set_vcore_voltage set vcore to 725000
9156 12:48:07.546082 Read voltage for 1600, 0
9157 12:48:07.549313 Vio18 = 0
9158 12:48:07.549406 Vcore = 725000
9159 12:48:07.549496 Vdram = 0
9160 12:48:07.552789 Vddq = 0
9161 12:48:07.552857 Vmddr = 0
9162 12:48:07.556445 switch to 3200 Mbps bootup
9163 12:48:07.556541 [DramcRunTimeConfig]
9164 12:48:07.556623 PHYPLL
9165 12:48:07.559511 DPM_CONTROL_AFTERK: ON
9166 12:48:07.562970 PER_BANK_REFRESH: ON
9167 12:48:07.563038 REFRESH_OVERHEAD_REDUCTION: ON
9168 12:48:07.565996 CMD_PICG_NEW_MODE: OFF
9169 12:48:07.569747 XRTWTW_NEW_MODE: ON
9170 12:48:07.569848 XRTRTR_NEW_MODE: ON
9171 12:48:07.572361 TX_TRACKING: ON
9172 12:48:07.572454 RDSEL_TRACKING: OFF
9173 12:48:07.575760 DQS Precalculation for DVFS: ON
9174 12:48:07.579118 RX_TRACKING: OFF
9175 12:48:07.579240 HW_GATING DBG: ON
9176 12:48:07.582695 ZQCS_ENABLE_LP4: ON
9177 12:48:07.582800 RX_PICG_NEW_MODE: ON
9178 12:48:07.585910 TX_PICG_NEW_MODE: ON
9179 12:48:07.586031 ENABLE_RX_DCM_DPHY: ON
9180 12:48:07.589000 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9181 12:48:07.592188 DUMMY_READ_FOR_TRACKING: OFF
9182 12:48:07.595567 !!! SPM_CONTROL_AFTERK: OFF
9183 12:48:07.599004 !!! SPM could not control APHY
9184 12:48:07.599118 IMPEDANCE_TRACKING: ON
9185 12:48:07.602235 TEMP_SENSOR: ON
9186 12:48:07.602319 HW_SAVE_FOR_SR: OFF
9187 12:48:07.605534 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9188 12:48:07.609044 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9189 12:48:07.612285 Read ODT Tracking: ON
9190 12:48:07.615599 Refresh Rate DeBounce: ON
9191 12:48:07.615682 DFS_NO_QUEUE_FLUSH: ON
9192 12:48:07.618803 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9193 12:48:07.622105 ENABLE_DFS_RUNTIME_MRW: OFF
9194 12:48:07.625477 DDR_RESERVE_NEW_MODE: ON
9195 12:48:07.625559 MR_CBT_SWITCH_FREQ: ON
9196 12:48:07.628550 =========================
9197 12:48:07.647025 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9198 12:48:07.650722 dram_init: ddr_geometry: 2
9199 12:48:07.669030 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9200 12:48:07.672406 dram_init: dram init end (result: 0)
9201 12:48:07.678659 DRAM-K: Full calibration passed in 24631 msecs
9202 12:48:07.682111 MRC: failed to locate region type 0.
9203 12:48:07.682194 DRAM rank0 size:0x100000000,
9204 12:48:07.685224 DRAM rank1 size=0x100000000
9205 12:48:07.695491 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9206 12:48:07.701387 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9207 12:48:07.711295 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9208 12:48:07.718225 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9209 12:48:07.718308 DRAM rank0 size:0x100000000,
9210 12:48:07.721382 DRAM rank1 size=0x100000000
9211 12:48:07.721465 CBMEM:
9212 12:48:07.724777 IMD: root @ 0xfffff000 254 entries.
9213 12:48:07.727755 IMD: root @ 0xffffec00 62 entries.
9214 12:48:07.731126 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9215 12:48:07.737855 WARNING: RO_VPD is uninitialized or empty.
9216 12:48:07.741404 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9217 12:48:07.748760 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9218 12:48:07.761547 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9219 12:48:07.772912 BS: romstage times (exec / console): total (unknown) / 24125 ms
9220 12:48:07.773004
9221 12:48:07.773071
9222 12:48:07.783087 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9223 12:48:07.786210 ARM64: Exception handlers installed.
9224 12:48:07.789603 ARM64: Testing exception
9225 12:48:07.792924 ARM64: Done test exception
9226 12:48:07.793008 Enumerating buses...
9227 12:48:07.795871 Show all devs... Before device enumeration.
9228 12:48:07.799047 Root Device: enabled 1
9229 12:48:07.802888 CPU_CLUSTER: 0: enabled 1
9230 12:48:07.802970 CPU: 00: enabled 1
9231 12:48:07.806256 Compare with tree...
9232 12:48:07.806340 Root Device: enabled 1
9233 12:48:07.809350 CPU_CLUSTER: 0: enabled 1
9234 12:48:07.812381 CPU: 00: enabled 1
9235 12:48:07.812463 Root Device scanning...
9236 12:48:07.816000 scan_static_bus for Root Device
9237 12:48:07.819200 CPU_CLUSTER: 0 enabled
9238 12:48:07.822147 scan_static_bus for Root Device done
9239 12:48:07.826047 scan_bus: bus Root Device finished in 8 msecs
9240 12:48:07.826130 done
9241 12:48:07.832217 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9242 12:48:07.835745 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9243 12:48:07.842478 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9244 12:48:07.848807 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9245 12:48:07.848890 Allocating resources...
9246 12:48:07.852076 Reading resources...
9247 12:48:07.855812 Root Device read_resources bus 0 link: 0
9248 12:48:07.858828 DRAM rank0 size:0x100000000,
9249 12:48:07.859337 DRAM rank1 size=0x100000000
9250 12:48:07.865552 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9251 12:48:07.866057 CPU: 00 missing read_resources
9252 12:48:07.871710 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9253 12:48:07.875485 Root Device read_resources bus 0 link: 0 done
9254 12:48:07.878767 Done reading resources.
9255 12:48:07.881979 Show resources in subtree (Root Device)...After reading.
9256 12:48:07.884954 Root Device child on link 0 CPU_CLUSTER: 0
9257 12:48:07.888318 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 12:48:07.898221 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 12:48:07.899082 CPU: 00
9260 12:48:07.905211 Root Device assign_resources, bus 0 link: 0
9261 12:48:07.908355 CPU_CLUSTER: 0 missing set_resources
9262 12:48:07.911072 Root Device assign_resources, bus 0 link: 0 done
9263 12:48:07.914687 Done setting resources.
9264 12:48:07.918081 Show resources in subtree (Root Device)...After assigning values.
9265 12:48:07.921296 Root Device child on link 0 CPU_CLUSTER: 0
9266 12:48:07.927941 CPU_CLUSTER: 0 child on link 0 CPU: 00
9267 12:48:07.934990 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9268 12:48:07.938254 CPU: 00
9269 12:48:07.938580 Done allocating resources.
9270 12:48:07.944149 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9271 12:48:07.944469 Enabling resources...
9272 12:48:07.947955 done.
9273 12:48:07.950868 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9274 12:48:07.954199 Initializing devices...
9275 12:48:07.954493 Root Device init
9276 12:48:07.957424 init hardware done!
9277 12:48:07.957722 0x00000018: ctrlr->caps
9278 12:48:07.960922 52.000 MHz: ctrlr->f_max
9279 12:48:07.964189 0.400 MHz: ctrlr->f_min
9280 12:48:07.967448 0x40ff8080: ctrlr->voltages
9281 12:48:07.967751 sclk: 390625
9282 12:48:07.967989 Bus Width = 1
9283 12:48:07.970723 sclk: 390625
9284 12:48:07.971019 Bus Width = 1
9285 12:48:07.973934 Early init status = 3
9286 12:48:07.976968 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9287 12:48:07.981284 in-header: 03 fc 00 00 01 00 00 00
9288 12:48:07.984595 in-data: 00
9289 12:48:07.988212 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9290 12:48:07.993208 in-header: 03 fd 00 00 00 00 00 00
9291 12:48:07.997051 in-data:
9292 12:48:07.999408 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9293 12:48:08.002883 in-header: 03 fc 00 00 01 00 00 00
9294 12:48:08.006509 in-data: 00
9295 12:48:08.009073 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9296 12:48:08.014001 in-header: 03 fd 00 00 00 00 00 00
9297 12:48:08.018350 in-data:
9298 12:48:08.020547 [SSUSB] Setting up USB HOST controller...
9299 12:48:08.024030 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9300 12:48:08.027002 [SSUSB] phy power-on done.
9301 12:48:08.030486 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9302 12:48:08.037209 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9303 12:48:08.040587 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9304 12:48:08.047289 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9305 12:48:08.054028 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9306 12:48:08.060247 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9307 12:48:08.066959 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9308 12:48:08.073642 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9309 12:48:08.077340 SPM: binary array size = 0x9dc
9310 12:48:08.080149 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9311 12:48:08.086802 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9312 12:48:08.093469 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9313 12:48:08.099714 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9314 12:48:08.103072 configure_display: Starting display init
9315 12:48:08.137957 anx7625_power_on_init: Init interface.
9316 12:48:08.141528 anx7625_disable_pd_protocol: Disabled PD feature.
9317 12:48:08.144172 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9318 12:48:08.172736 anx7625_start_dp_work: Secure OCM version=00
9319 12:48:08.175484 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9320 12:48:08.190396 sp_tx_get_edid_block: EDID Block = 1
9321 12:48:08.292648 Extracted contents:
9322 12:48:08.296319 header: 00 ff ff ff ff ff ff 00
9323 12:48:08.299801 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9324 12:48:08.302659 version: 01 04
9325 12:48:08.306255 basic params: 95 1f 11 78 0a
9326 12:48:08.309006 chroma info: 76 90 94 55 54 90 27 21 50 54
9327 12:48:08.312793 established: 00 00 00
9328 12:48:08.318870 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9329 12:48:08.325554 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9330 12:48:08.328632 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9331 12:48:08.335408 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9332 12:48:08.342450 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9333 12:48:08.345307 extensions: 00
9334 12:48:08.345410 checksum: fb
9335 12:48:08.345492
9336 12:48:08.351562 Manufacturer: IVO Model 57d Serial Number 0
9337 12:48:08.351686 Made week 0 of 2020
9338 12:48:08.355134 EDID version: 1.4
9339 12:48:08.355256 Digital display
9340 12:48:08.358195 6 bits per primary color channel
9341 12:48:08.361618 DisplayPort interface
9342 12:48:08.361771 Maximum image size: 31 cm x 17 cm
9343 12:48:08.364951 Gamma: 220%
9344 12:48:08.365104 Check DPMS levels
9345 12:48:08.371682 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9346 12:48:08.374510 First detailed timing is preferred timing
9347 12:48:08.378866 Established timings supported:
9348 12:48:08.379107 Standard timings supported:
9349 12:48:08.381073 Detailed timings
9350 12:48:08.384479 Hex of detail: 383680a07038204018303c0035ae10000019
9351 12:48:08.391230 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9352 12:48:08.394386 0780 0798 07c8 0820 hborder 0
9353 12:48:08.397970 0438 043b 0447 0458 vborder 0
9354 12:48:08.400917 -hsync -vsync
9355 12:48:08.401340 Did detailed timing
9356 12:48:08.407926 Hex of detail: 000000000000000000000000000000000000
9357 12:48:08.410938 Manufacturer-specified data, tag 0
9358 12:48:08.414430 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9359 12:48:08.418103 ASCII string: InfoVision
9360 12:48:08.420805 Hex of detail: 000000fe00523134304e574635205248200a
9361 12:48:08.423970 ASCII string: R140NWF5 RH
9362 12:48:08.424397 Checksum
9363 12:48:08.427213 Checksum: 0xfb (valid)
9364 12:48:08.431034 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9365 12:48:08.433870 DSI data_rate: 832800000 bps
9366 12:48:08.440766 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9367 12:48:08.443720 anx7625_parse_edid: pixelclock(138800).
9368 12:48:08.447244 hactive(1920), hsync(48), hfp(24), hbp(88)
9369 12:48:08.450784 vactive(1080), vsync(12), vfp(3), vbp(17)
9370 12:48:08.453729 anx7625_dsi_config: config dsi.
9371 12:48:08.460442 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9372 12:48:08.474539 anx7625_dsi_config: success to config DSI
9373 12:48:08.477889 anx7625_dp_start: MIPI phy setup OK.
9374 12:48:08.481531 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9375 12:48:08.484430 mtk_ddp_mode_set invalid vrefresh 60
9376 12:48:08.487664 main_disp_path_setup
9377 12:48:08.488222 ovl_layer_smi_id_en
9378 12:48:08.491022 ovl_layer_smi_id_en
9379 12:48:08.491525 ccorr_config
9380 12:48:08.491892 aal_config
9381 12:48:08.494548 gamma_config
9382 12:48:08.494947 postmask_config
9383 12:48:08.497502 dither_config
9384 12:48:08.501052 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9385 12:48:08.507348 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9386 12:48:08.510752 Root Device init finished in 552 msecs
9387 12:48:08.513858 CPU_CLUSTER: 0 init
9388 12:48:08.520464 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9389 12:48:08.527106 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9390 12:48:08.527535 APU_MBOX 0x190000b0 = 0x10001
9391 12:48:08.530800 APU_MBOX 0x190001b0 = 0x10001
9392 12:48:08.534176 APU_MBOX 0x190005b0 = 0x10001
9393 12:48:08.537097 APU_MBOX 0x190006b0 = 0x10001
9394 12:48:08.543600 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9395 12:48:08.553783 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9396 12:48:08.566697 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9397 12:48:08.572761 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9398 12:48:08.584316 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9399 12:48:08.593259 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9400 12:48:08.596509 CPU_CLUSTER: 0 init finished in 81 msecs
9401 12:48:08.599970 Devices initialized
9402 12:48:08.603515 Show all devs... After init.
9403 12:48:08.603942 Root Device: enabled 1
9404 12:48:08.606747 CPU_CLUSTER: 0: enabled 1
9405 12:48:08.609914 CPU: 00: enabled 1
9406 12:48:08.613303 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9407 12:48:08.616596 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9408 12:48:08.619633 ELOG: NV offset 0x57f000 size 0x1000
9409 12:48:08.626633 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9410 12:48:08.633333 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9411 12:48:08.636434 ELOG: Event(17) added with size 13 at 2023-06-14 12:48:08 UTC
9412 12:48:08.643121 out: cmd=0x121: 03 db 21 01 00 00 00 00
9413 12:48:08.646532 in-header: 03 b5 00 00 2c 00 00 00
9414 12:48:08.656256 in-data: aa 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9415 12:48:08.662319 ELOG: Event(A1) added with size 10 at 2023-06-14 12:48:08 UTC
9416 12:48:08.669472 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9417 12:48:08.675837 ELOG: Event(A0) added with size 9 at 2023-06-14 12:48:08 UTC
9418 12:48:08.679137 elog_add_boot_reason: Logged dev mode boot
9419 12:48:08.685635 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9420 12:48:08.685728 Finalize devices...
9421 12:48:08.689055 Devices finalized
9422 12:48:08.692247 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9423 12:48:08.695476 Writing coreboot table at 0xffe64000
9424 12:48:08.698728 0. 000000000010a000-0000000000113fff: RAMSTAGE
9425 12:48:08.705877 1. 0000000040000000-00000000400fffff: RAM
9426 12:48:08.708770 2. 0000000040100000-000000004032afff: RAMSTAGE
9427 12:48:08.712061 3. 000000004032b000-00000000545fffff: RAM
9428 12:48:08.715283 4. 0000000054600000-000000005465ffff: BL31
9429 12:48:08.718693 5. 0000000054660000-00000000ffe63fff: RAM
9430 12:48:08.725772 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9431 12:48:08.728660 7. 0000000100000000-000000023fffffff: RAM
9432 12:48:08.732224 Passing 5 GPIOs to payload:
9433 12:48:08.735185 NAME | PORT | POLARITY | VALUE
9434 12:48:08.742068 EC in RW | 0x000000aa | low | undefined
9435 12:48:08.745066 EC interrupt | 0x00000005 | low | undefined
9436 12:48:08.748437 TPM interrupt | 0x000000ab | high | undefined
9437 12:48:08.755006 SD card detect | 0x00000011 | high | undefined
9438 12:48:08.758593 speaker enable | 0x00000093 | high | undefined
9439 12:48:08.762082 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9440 12:48:08.764765 in-header: 03 f9 00 00 02 00 00 00
9441 12:48:08.768268 in-data: 02 00
9442 12:48:08.771413 ADC[4]: Raw value=901922 ID=7
9443 12:48:08.771495 ADC[3]: Raw value=213652 ID=1
9444 12:48:08.775240 RAM Code: 0x71
9445 12:48:08.778054 ADC[6]: Raw value=75036 ID=0
9446 12:48:08.781782 ADC[5]: Raw value=213282 ID=1
9447 12:48:08.781864 SKU Code: 0x1
9448 12:48:08.788193 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169
9449 12:48:08.788276 coreboot table: 964 bytes.
9450 12:48:08.791390 IMD ROOT 0. 0xfffff000 0x00001000
9451 12:48:08.794901 IMD SMALL 1. 0xffffe000 0x00001000
9452 12:48:08.798151 RO MCACHE 2. 0xffffc000 0x00001104
9453 12:48:08.801226 CONSOLE 3. 0xfff7c000 0x00080000
9454 12:48:08.804719 FMAP 4. 0xfff7b000 0x00000452
9455 12:48:08.807993 TIME STAMP 5. 0xfff7a000 0x00000910
9456 12:48:08.811200 VBOOT WORK 6. 0xfff66000 0x00014000
9457 12:48:08.814731 RAMOOPS 7. 0xffe66000 0x00100000
9458 12:48:08.817878 COREBOOT 8. 0xffe64000 0x00002000
9459 12:48:08.821178 IMD small region:
9460 12:48:08.824572 IMD ROOT 0. 0xffffec00 0x00000400
9461 12:48:08.827601 VPD 1. 0xffffeba0 0x0000004c
9462 12:48:08.831185 MMC STATUS 2. 0xffffeb80 0x00000004
9463 12:48:08.834181 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9464 12:48:08.837927 Probing TPM: done!
9465 12:48:08.841537 Connected to device vid:did:rid of 1ae0:0028:00
9466 12:48:08.852631 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9467 12:48:08.855524 Initialized TPM device CR50 revision 0
9468 12:48:08.858743 Checking cr50 for pending updates
9469 12:48:08.863160 Reading cr50 TPM mode
9470 12:48:08.871701 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9471 12:48:08.878432 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9472 12:48:08.918887 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9473 12:48:08.921741 Checking segment from ROM address 0x40100000
9474 12:48:08.924953 Checking segment from ROM address 0x4010001c
9475 12:48:08.931575 Loading segment from ROM address 0x40100000
9476 12:48:08.931658 code (compression=0)
9477 12:48:08.938290 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9478 12:48:08.948607 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9479 12:48:08.948691 it's not compressed!
9480 12:48:08.955138 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9481 12:48:08.958629 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9482 12:48:08.978595 Loading segment from ROM address 0x4010001c
9483 12:48:08.978781 Entry Point 0x80000000
9484 12:48:08.982532 Loaded segments
9485 12:48:08.985360 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9486 12:48:08.991732 Jumping to boot code at 0x80000000(0xffe64000)
9487 12:48:08.998808 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9488 12:48:09.005017 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9489 12:48:09.013267 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9490 12:48:09.017051 Checking segment from ROM address 0x40100000
9491 12:48:09.019959 Checking segment from ROM address 0x4010001c
9492 12:48:09.026752 Loading segment from ROM address 0x40100000
9493 12:48:09.026861 code (compression=1)
9494 12:48:09.032998 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9495 12:48:09.042893 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9496 12:48:09.042981 using LZMA
9497 12:48:09.051640 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9498 12:48:09.058083 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9499 12:48:09.061859 Loading segment from ROM address 0x4010001c
9500 12:48:09.061967 Entry Point 0x54601000
9501 12:48:09.064641 Loaded segments
9502 12:48:09.067642 NOTICE: MT8192 bl31_setup
9503 12:48:09.075223 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9504 12:48:09.078395 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9505 12:48:09.081756 WARNING: region 0:
9506 12:48:09.084991 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 12:48:09.085073 WARNING: region 1:
9508 12:48:09.091440 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9509 12:48:09.094937 WARNING: region 2:
9510 12:48:09.098317 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9511 12:48:09.101302 WARNING: region 3:
9512 12:48:09.104613 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9513 12:48:09.108082 WARNING: region 4:
9514 12:48:09.114867 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 12:48:09.114974 WARNING: region 5:
9516 12:48:09.117812 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 12:48:09.121411 WARNING: region 6:
9518 12:48:09.124727 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 12:48:09.127953 WARNING: region 7:
9520 12:48:09.131006 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 12:48:09.137588 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9522 12:48:09.140989 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9523 12:48:09.147875 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9524 12:48:09.151016 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9525 12:48:09.154232 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9526 12:48:09.160888 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9527 12:48:09.164550 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9528 12:48:09.168140 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9529 12:48:09.174097 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9530 12:48:09.178000 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9531 12:48:09.184652 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9532 12:48:09.187666 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9533 12:48:09.191469 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9534 12:48:09.198200 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9535 12:48:09.201700 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9536 12:48:09.204710 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9537 12:48:09.211240 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9538 12:48:09.214281 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9539 12:48:09.221107 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9540 12:48:09.224295 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9541 12:48:09.227931 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9542 12:48:09.234469 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9543 12:48:09.237451 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9544 12:48:09.240965 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9545 12:48:09.247504 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9546 12:48:09.251220 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9547 12:48:09.258007 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9548 12:48:09.261285 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9549 12:48:09.267564 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9550 12:48:09.271198 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9551 12:48:09.274316 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9552 12:48:09.280647 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9553 12:48:09.284491 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9554 12:48:09.287530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9555 12:48:09.290815 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9556 12:48:09.298032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9557 12:48:09.300615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9558 12:48:09.303841 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9559 12:48:09.307425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9560 12:48:09.313669 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9561 12:48:09.317777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9562 12:48:09.320901 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9563 12:48:09.324147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9564 12:48:09.330427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9565 12:48:09.333738 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9566 12:48:09.337398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9567 12:48:09.343635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9568 12:48:09.347465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9569 12:48:09.350431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9570 12:48:09.357115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9571 12:48:09.360493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9572 12:48:09.366966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9573 12:48:09.370526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9574 12:48:09.373617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9575 12:48:09.380179 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9576 12:48:09.383661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9577 12:48:09.390280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9578 12:48:09.393649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9579 12:48:09.400245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9580 12:48:09.404191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9581 12:48:09.406710 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9582 12:48:09.413436 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9583 12:48:09.416965 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9584 12:48:09.423543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9585 12:48:09.426728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9586 12:48:09.433053 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9587 12:48:09.436410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9588 12:48:09.443672 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9589 12:48:09.446354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9590 12:48:09.449612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9591 12:48:09.456665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9592 12:48:09.459862 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9593 12:48:09.467008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9594 12:48:09.469920 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9595 12:48:09.476624 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9596 12:48:09.479895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9597 12:48:09.482973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9598 12:48:09.489741 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9599 12:48:09.493070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9600 12:48:09.500338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9601 12:48:09.502989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9602 12:48:09.509565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9603 12:48:09.512917 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9604 12:48:09.520004 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9605 12:48:09.523251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9606 12:48:09.526489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9607 12:48:09.532574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9608 12:48:09.536059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9609 12:48:09.542962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9610 12:48:09.546395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9611 12:48:09.552618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9612 12:48:09.555905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9613 12:48:09.560047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9614 12:48:09.566369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9615 12:48:09.569326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9616 12:48:09.576134 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9617 12:48:09.579741 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9618 12:48:09.583336 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9619 12:48:09.589537 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9620 12:48:09.592729 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9621 12:48:09.596011 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9622 12:48:09.599354 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9623 12:48:09.605790 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9624 12:48:09.609218 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9625 12:48:09.615777 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9626 12:48:09.619213 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9627 12:48:09.622440 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9628 12:48:09.629585 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9629 12:48:09.632303 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9630 12:48:09.639036 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9631 12:48:09.642588 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9632 12:48:09.649088 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9633 12:48:09.652501 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9634 12:48:09.655424 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9635 12:48:09.662454 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9636 12:48:09.665622 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9637 12:48:09.669402 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9638 12:48:09.675531 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9639 12:48:09.678844 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9640 12:48:09.682210 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9641 12:48:09.688764 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9642 12:48:09.692198 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9643 12:48:09.695335 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9644 12:48:09.698584 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9645 12:48:09.705396 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9646 12:48:09.709050 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9647 12:48:09.712309 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9648 12:48:09.719019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9649 12:48:09.722069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9650 12:48:09.728830 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9651 12:48:09.731698 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9652 12:48:09.734861 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9653 12:48:09.741598 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9654 12:48:09.744762 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9655 12:48:09.751695 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9656 12:48:09.754985 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9657 12:48:09.758248 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9658 12:48:09.764691 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9659 12:48:09.768070 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9660 12:48:09.774592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9661 12:48:09.777920 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9662 12:48:09.781590 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9663 12:48:09.788442 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9664 12:48:09.791304 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9665 12:48:09.798038 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9666 12:48:09.801644 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9667 12:48:09.804620 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9668 12:48:09.811534 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9669 12:48:09.814588 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9670 12:48:09.821257 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9671 12:48:09.824370 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9672 12:48:09.827547 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9673 12:48:09.834393 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9674 12:48:09.837733 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9675 12:48:09.844661 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9676 12:48:09.847420 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9677 12:48:09.851565 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9678 12:48:09.857992 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9679 12:48:09.861264 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9680 12:48:09.863987 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9681 12:48:09.870526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9682 12:48:09.873904 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9683 12:48:09.880567 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9684 12:48:09.883694 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9685 12:48:09.890210 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9686 12:48:09.893903 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9687 12:48:09.896976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9688 12:48:09.904270 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9689 12:48:09.907233 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9690 12:48:09.913421 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9691 12:48:09.917045 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9692 12:48:09.920153 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9693 12:48:09.927568 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9694 12:48:09.930527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9695 12:48:09.933555 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9696 12:48:09.939922 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9697 12:48:09.943509 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9698 12:48:09.949667 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9699 12:48:09.953054 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9700 12:48:09.956742 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9701 12:48:09.963456 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9702 12:48:09.966261 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9703 12:48:09.973204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9704 12:48:09.976800 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9705 12:48:09.983063 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9706 12:48:09.986756 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9707 12:48:09.989464 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9708 12:48:09.996108 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9709 12:48:09.999333 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9710 12:48:10.005849 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9711 12:48:10.009268 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9712 12:48:10.012654 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9713 12:48:10.019083 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9714 12:48:10.022273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9715 12:48:10.029068 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9716 12:48:10.032091 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9717 12:48:10.039145 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9718 12:48:10.042025 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9719 12:48:10.045874 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9720 12:48:10.052175 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9721 12:48:10.055170 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9722 12:48:10.062037 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9723 12:48:10.065109 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9724 12:48:10.071920 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9725 12:48:10.075331 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9726 12:48:10.078689 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9727 12:48:10.084959 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9728 12:48:10.088141 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9729 12:48:10.094848 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9730 12:48:10.098145 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9731 12:48:10.104793 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9732 12:48:10.107884 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9733 12:48:10.111455 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9734 12:48:10.118119 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9735 12:48:10.121502 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9736 12:48:10.127660 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9737 12:48:10.131364 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9738 12:48:10.138395 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9739 12:48:10.140764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9740 12:48:10.144694 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9741 12:48:10.150920 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9742 12:48:10.154211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9743 12:48:10.161568 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9744 12:48:10.164159 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9745 12:48:10.167351 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9746 12:48:10.174194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9747 12:48:10.177824 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9748 12:48:10.184443 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9749 12:48:10.187617 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9750 12:48:10.190774 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9751 12:48:10.197106 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9752 12:48:10.200639 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9753 12:48:10.204451 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9754 12:48:10.207636 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9755 12:48:10.213517 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9756 12:48:10.217245 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9757 12:48:10.220265 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9758 12:48:10.227402 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9759 12:48:10.230519 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9760 12:48:10.234365 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9761 12:48:10.241361 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9762 12:48:10.244355 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9763 12:48:10.250896 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9764 12:48:10.253765 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9765 12:48:10.256872 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9766 12:48:10.263709 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9767 12:48:10.267112 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9768 12:48:10.273614 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9769 12:48:10.276709 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9770 12:48:10.279721 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9771 12:48:10.286927 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9772 12:48:10.289919 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9773 12:48:10.293292 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9774 12:48:10.300074 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9775 12:48:10.303638 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9776 12:48:10.306676 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9777 12:48:10.313212 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9778 12:48:10.316594 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9779 12:48:10.319896 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9780 12:48:10.326102 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9781 12:48:10.329852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9782 12:48:10.336136 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9783 12:48:10.339339 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9784 12:48:10.343224 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9785 12:48:10.349829 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9786 12:48:10.352615 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9787 12:48:10.359465 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9788 12:48:10.362398 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9789 12:48:10.365981 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9790 12:48:10.369270 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9791 12:48:10.376480 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9792 12:48:10.379373 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9793 12:48:10.382541 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9794 12:48:10.385784 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9795 12:48:10.392918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9796 12:48:10.395785 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9797 12:48:10.399058 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9798 12:48:10.402572 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9799 12:48:10.408976 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9800 12:48:10.412438 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9801 12:48:10.415573 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9802 12:48:10.422171 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9803 12:48:10.425217 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9804 12:48:10.428403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9805 12:48:10.435506 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9806 12:48:10.438697 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9807 12:48:10.445118 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9808 12:48:10.449169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9809 12:48:10.455047 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9810 12:48:10.458846 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9811 12:48:10.461370 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9812 12:48:10.467992 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9813 12:48:10.471448 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9814 12:48:10.478132 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9815 12:48:10.481728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9816 12:48:10.487842 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9817 12:48:10.491497 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9818 12:48:10.494661 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9819 12:48:10.501342 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9820 12:48:10.504480 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9821 12:48:10.511076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9822 12:48:10.514731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9823 12:48:10.517636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9824 12:48:10.524572 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9825 12:48:10.527489 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9826 12:48:10.534277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9827 12:48:10.537418 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9828 12:48:10.540946 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9829 12:48:10.547264 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9830 12:48:10.550883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9831 12:48:10.557421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9832 12:48:10.560893 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9833 12:48:10.566968 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9834 12:48:10.570638 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9835 12:48:10.574173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9836 12:48:10.580616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9837 12:48:10.583976 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9838 12:48:10.590512 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9839 12:48:10.593941 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9840 12:48:10.597067 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9841 12:48:10.603661 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9842 12:48:10.607158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9843 12:48:10.613492 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9844 12:48:10.616774 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9845 12:48:10.623693 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9846 12:48:10.626311 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9847 12:48:10.629700 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9848 12:48:10.636342 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9849 12:48:10.639726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9850 12:48:10.646542 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9851 12:48:10.649767 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9852 12:48:10.653044 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9853 12:48:10.659745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9854 12:48:10.663166 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9855 12:48:10.669337 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9856 12:48:10.672429 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9857 12:48:10.679596 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9858 12:48:10.682668 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9859 12:48:10.686052 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9860 12:48:10.692678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9861 12:48:10.695766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9862 12:48:10.703008 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9863 12:48:10.705997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9864 12:48:10.712633 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9865 12:48:10.715838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9866 12:48:10.718800 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9867 12:48:10.725452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9868 12:48:10.728683 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9869 12:48:10.735568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9870 12:48:10.738768 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9871 12:48:10.741973 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9872 12:48:10.748876 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9873 12:48:10.752148 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9874 12:48:10.758539 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9875 12:48:10.763121 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9876 12:48:10.768230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9877 12:48:10.771550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9878 12:48:10.775078 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9879 12:48:10.781689 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9880 12:48:10.784743 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9881 12:48:10.791628 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9882 12:48:10.794837 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9883 12:48:10.801364 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9884 12:48:10.804370 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9885 12:48:10.810632 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9886 12:48:10.814288 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9887 12:48:10.821010 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9888 12:48:10.824251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9889 12:48:10.827636 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9890 12:48:10.834336 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9891 12:48:10.837068 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9892 12:48:10.843859 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9893 12:48:10.847069 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9894 12:48:10.853592 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9895 12:48:10.857439 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9896 12:48:10.863594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9897 12:48:10.867367 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9898 12:48:10.870200 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9899 12:48:10.876678 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9900 12:48:10.879875 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9901 12:48:10.886255 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9902 12:48:10.889759 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9903 12:48:10.896423 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9904 12:48:10.899537 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9905 12:48:10.905918 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9906 12:48:10.909309 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9907 12:48:10.912463 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9908 12:48:10.919440 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9909 12:48:10.922566 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9910 12:48:10.929428 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9911 12:48:10.932495 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9912 12:48:10.939465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9913 12:48:10.942774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9914 12:48:10.945873 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9915 12:48:10.952440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9916 12:48:10.955537 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9917 12:48:10.962343 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9918 12:48:10.965844 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9919 12:48:10.972609 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9920 12:48:10.975605 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9921 12:48:10.982657 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9922 12:48:10.985519 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9923 12:48:10.988865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9924 12:48:10.995489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9925 12:48:10.999430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9926 12:48:11.005190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9927 12:48:11.008325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9928 12:48:11.015102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9929 12:48:11.018338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9930 12:48:11.025233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9931 12:48:11.028639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9932 12:48:11.035087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9933 12:48:11.038183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9934 12:48:11.044966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9935 12:48:11.048209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9936 12:48:11.054501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9937 12:48:11.058250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9938 12:48:11.064754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9939 12:48:11.068033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9940 12:48:11.074138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9941 12:48:11.077500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9942 12:48:11.084412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9943 12:48:11.087280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9944 12:48:11.094042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9945 12:48:11.097212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9946 12:48:11.104142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9947 12:48:11.107311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9948 12:48:11.113667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9949 12:48:11.117218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9950 12:48:11.123611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9951 12:48:11.127141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9952 12:48:11.133433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9953 12:48:11.136511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9954 12:48:11.143287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9955 12:48:11.146745 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9956 12:48:11.149765 INFO: [APUAPC] vio 0
9957 12:48:11.153398 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9958 12:48:11.159694 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9959 12:48:11.162792 INFO: [APUAPC] D0_APC_0: 0x400510
9960 12:48:11.166310 INFO: [APUAPC] D0_APC_1: 0x0
9961 12:48:11.166393 INFO: [APUAPC] D0_APC_2: 0x1540
9962 12:48:11.169749 INFO: [APUAPC] D0_APC_3: 0x0
9963 12:48:11.173009 INFO: [APUAPC] D1_APC_0: 0xffffffff
9964 12:48:11.175903 INFO: [APUAPC] D1_APC_1: 0xffffffff
9965 12:48:11.179504 INFO: [APUAPC] D1_APC_2: 0x3fffff
9966 12:48:11.182833 INFO: [APUAPC] D1_APC_3: 0x0
9967 12:48:11.186044 INFO: [APUAPC] D2_APC_0: 0xffffffff
9968 12:48:11.189640 INFO: [APUAPC] D2_APC_1: 0xffffffff
9969 12:48:11.193077 INFO: [APUAPC] D2_APC_2: 0x3fffff
9970 12:48:11.196202 INFO: [APUAPC] D2_APC_3: 0x0
9971 12:48:11.199632 INFO: [APUAPC] D3_APC_0: 0xffffffff
9972 12:48:11.202258 INFO: [APUAPC] D3_APC_1: 0xffffffff
9973 12:48:11.205663 INFO: [APUAPC] D3_APC_2: 0x3fffff
9974 12:48:11.209004 INFO: [APUAPC] D3_APC_3: 0x0
9975 12:48:11.212709 INFO: [APUAPC] D4_APC_0: 0xffffffff
9976 12:48:11.215367 INFO: [APUAPC] D4_APC_1: 0xffffffff
9977 12:48:11.218873 INFO: [APUAPC] D4_APC_2: 0x3fffff
9978 12:48:11.222083 INFO: [APUAPC] D4_APC_3: 0x0
9979 12:48:11.225772 INFO: [APUAPC] D5_APC_0: 0xffffffff
9980 12:48:11.228946 INFO: [APUAPC] D5_APC_1: 0xffffffff
9981 12:48:11.232566 INFO: [APUAPC] D5_APC_2: 0x3fffff
9982 12:48:11.235534 INFO: [APUAPC] D5_APC_3: 0x0
9983 12:48:11.238903 INFO: [APUAPC] D6_APC_0: 0xffffffff
9984 12:48:11.242240 INFO: [APUAPC] D6_APC_1: 0xffffffff
9985 12:48:11.245934 INFO: [APUAPC] D6_APC_2: 0x3fffff
9986 12:48:11.248545 INFO: [APUAPC] D6_APC_3: 0x0
9987 12:48:11.252129 INFO: [APUAPC] D7_APC_0: 0xffffffff
9988 12:48:11.255712 INFO: [APUAPC] D7_APC_1: 0xffffffff
9989 12:48:11.259259 INFO: [APUAPC] D7_APC_2: 0x3fffff
9990 12:48:11.261909 INFO: [APUAPC] D7_APC_3: 0x0
9991 12:48:11.265159 INFO: [APUAPC] D8_APC_0: 0xffffffff
9992 12:48:11.269028 INFO: [APUAPC] D8_APC_1: 0xffffffff
9993 12:48:11.272316 INFO: [APUAPC] D8_APC_2: 0x3fffff
9994 12:48:11.275260 INFO: [APUAPC] D8_APC_3: 0x0
9995 12:48:11.278526 INFO: [APUAPC] D9_APC_0: 0xffffffff
9996 12:48:11.281839 INFO: [APUAPC] D9_APC_1: 0xffffffff
9997 12:48:11.285134 INFO: [APUAPC] D9_APC_2: 0x3fffff
9998 12:48:11.288421 INFO: [APUAPC] D9_APC_3: 0x0
9999 12:48:11.291886 INFO: [APUAPC] D10_APC_0: 0xffffffff
10000 12:48:11.295197 INFO: [APUAPC] D10_APC_1: 0xffffffff
10001 12:48:11.298805 INFO: [APUAPC] D10_APC_2: 0x3fffff
10002 12:48:11.301676 INFO: [APUAPC] D10_APC_3: 0x0
10003 12:48:11.304838 INFO: [APUAPC] D11_APC_0: 0xffffffff
10004 12:48:11.308183 INFO: [APUAPC] D11_APC_1: 0xffffffff
10005 12:48:11.311660 INFO: [APUAPC] D11_APC_2: 0x3fffff
10006 12:48:11.315231 INFO: [APUAPC] D11_APC_3: 0x0
10007 12:48:11.318299 INFO: [APUAPC] D12_APC_0: 0xffffffff
10008 12:48:11.321313 INFO: [APUAPC] D12_APC_1: 0xffffffff
10009 12:48:11.324739 INFO: [APUAPC] D12_APC_2: 0x3fffff
10010 12:48:11.328338 INFO: [APUAPC] D12_APC_3: 0x0
10011 12:48:11.331255 INFO: [APUAPC] D13_APC_0: 0xffffffff
10012 12:48:11.334879 INFO: [APUAPC] D13_APC_1: 0xffffffff
10013 12:48:11.338251 INFO: [APUAPC] D13_APC_2: 0x3fffff
10014 12:48:11.341262 INFO: [APUAPC] D13_APC_3: 0x0
10015 12:48:11.344373 INFO: [APUAPC] D14_APC_0: 0xffffffff
10016 12:48:11.347818 INFO: [APUAPC] D14_APC_1: 0xffffffff
10017 12:48:11.351706 INFO: [APUAPC] D14_APC_2: 0x3fffff
10018 12:48:11.354627 INFO: [APUAPC] D14_APC_3: 0x0
10019 12:48:11.357571 INFO: [APUAPC] D15_APC_0: 0xffffffff
10020 12:48:11.360968 INFO: [APUAPC] D15_APC_1: 0xffffffff
10021 12:48:11.364310 INFO: [APUAPC] D15_APC_2: 0x3fffff
10022 12:48:11.367677 INFO: [APUAPC] D15_APC_3: 0x0
10023 12:48:11.370818 INFO: [APUAPC] APC_CON: 0x4
10024 12:48:11.374675 INFO: [NOCDAPC] D0_APC_0: 0x0
10025 12:48:11.377428 INFO: [NOCDAPC] D0_APC_1: 0x0
10026 12:48:11.380686 INFO: [NOCDAPC] D1_APC_0: 0x0
10027 12:48:11.383985 INFO: [NOCDAPC] D1_APC_1: 0xfff
10028 12:48:11.387531 INFO: [NOCDAPC] D2_APC_0: 0x0
10029 12:48:11.387950 INFO: [NOCDAPC] D2_APC_1: 0xfff
10030 12:48:11.390773 INFO: [NOCDAPC] D3_APC_0: 0x0
10031 12:48:11.394646 INFO: [NOCDAPC] D3_APC_1: 0xfff
10032 12:48:11.397424 INFO: [NOCDAPC] D4_APC_0: 0x0
10033 12:48:11.400355 INFO: [NOCDAPC] D4_APC_1: 0xfff
10034 12:48:11.403878 INFO: [NOCDAPC] D5_APC_0: 0x0
10035 12:48:11.406894 INFO: [NOCDAPC] D5_APC_1: 0xfff
10036 12:48:11.410446 INFO: [NOCDAPC] D6_APC_0: 0x0
10037 12:48:11.413596 INFO: [NOCDAPC] D6_APC_1: 0xfff
10038 12:48:11.416810 INFO: [NOCDAPC] D7_APC_0: 0x0
10039 12:48:11.420361 INFO: [NOCDAPC] D7_APC_1: 0xfff
10040 12:48:11.423300 INFO: [NOCDAPC] D8_APC_0: 0x0
10041 12:48:11.423723 INFO: [NOCDAPC] D8_APC_1: 0xfff
10042 12:48:11.426569 INFO: [NOCDAPC] D9_APC_0: 0x0
10043 12:48:11.430429 INFO: [NOCDAPC] D9_APC_1: 0xfff
10044 12:48:11.433585 INFO: [NOCDAPC] D10_APC_0: 0x0
10045 12:48:11.436374 INFO: [NOCDAPC] D10_APC_1: 0xfff
10046 12:48:11.439754 INFO: [NOCDAPC] D11_APC_0: 0x0
10047 12:48:11.442852 INFO: [NOCDAPC] D11_APC_1: 0xfff
10048 12:48:11.446325 INFO: [NOCDAPC] D12_APC_0: 0x0
10049 12:48:11.449455 INFO: [NOCDAPC] D12_APC_1: 0xfff
10050 12:48:11.452810 INFO: [NOCDAPC] D13_APC_0: 0x0
10051 12:48:11.455868 INFO: [NOCDAPC] D13_APC_1: 0xfff
10052 12:48:11.459204 INFO: [NOCDAPC] D14_APC_0: 0x0
10053 12:48:11.462963 INFO: [NOCDAPC] D14_APC_1: 0xfff
10054 12:48:11.466023 INFO: [NOCDAPC] D15_APC_0: 0x0
10055 12:48:11.469864 INFO: [NOCDAPC] D15_APC_1: 0xfff
10056 12:48:11.469946 INFO: [NOCDAPC] APC_CON: 0x4
10057 12:48:11.472482 INFO: [APUAPC] set_apusys_apc done
10058 12:48:11.475902 INFO: [DEVAPC] devapc_init done
10059 12:48:11.482933 INFO: GICv3 without legacy support detected.
10060 12:48:11.486209 INFO: ARM GICv3 driver initialized in EL3
10061 12:48:11.489850 INFO: Maximum SPI INTID supported: 639
10062 12:48:11.492858 INFO: BL31: Initializing runtime services
10063 12:48:11.498747 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10064 12:48:11.502314 INFO: SPM: enable CPC mode
10065 12:48:11.505886 INFO: mcdi ready for mcusys-off-idle and system suspend
10066 12:48:11.512188 INFO: BL31: Preparing for EL3 exit to normal world
10067 12:48:11.515365 INFO: Entry point address = 0x80000000
10068 12:48:11.515447 INFO: SPSR = 0x8
10069 12:48:11.522828
10070 12:48:11.522910
10071 12:48:11.522974
10072 12:48:11.525933 Starting depthcharge on Spherion...
10073 12:48:11.526015
10074 12:48:11.526080 Wipe memory regions:
10075 12:48:11.526139
10076 12:48:11.526771 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10077 12:48:11.526870 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10078 12:48:11.526955 Setting prompt string to ['asurada:']
10079 12:48:11.527041 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10080 12:48:11.529646 [0x00000040000000, 0x00000054600000)
10081 12:48:11.652294
10082 12:48:11.652792 [0x00000054660000, 0x00000080000000)
10083 12:48:11.912489
10084 12:48:11.912663 [0x000000821a7280, 0x000000ffe64000)
10085 12:48:12.657960
10086 12:48:12.658452 [0x00000100000000, 0x00000240000000)
10087 12:48:14.547497
10088 12:48:14.550866 Initializing XHCI USB controller at 0x11200000.
10089 12:48:15.532415
10090 12:48:15.533123 R8152: Initializing
10091 12:48:15.533645
10092 12:48:15.535449 Version 9 (ocp_data = 6010)
10093 12:48:15.536057
10094 12:48:15.538866 R8152: Done initializing
10095 12:48:15.539516
10096 12:48:15.539973 Adding net device
10097 12:48:16.060699
10098 12:48:16.063484 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10099 12:48:16.063954
10100 12:48:16.064330
10101 12:48:16.064709
10102 12:48:16.065485 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 12:48:16.166918 asurada: tftpboot 192.168.201.1 10724916/tftp-deploy-8qwfh__e/kernel/image.itb 10724916/tftp-deploy-8qwfh__e/kernel/cmdline
10105 12:48:16.167600 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 12:48:16.168137 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10107 12:48:16.173038 tftpboot 192.168.201.1 10724916/tftp-deploy-8qwfh__e/kernel/image.itp-deploy-8qwfh__e/kernel/cmdline
10108 12:48:16.173516
10109 12:48:16.173893 Waiting for link
10110 12:48:16.375571
10111 12:48:16.376155 done.
10112 12:48:16.376574
10113 12:48:16.376936 MAC: f4:f5:e8:50:de:0a
10114 12:48:16.377283
10115 12:48:16.378573 Sending DHCP discover... done.
10116 12:48:16.379041
10117 12:48:16.381918 Waiting for reply... done.
10118 12:48:16.382385
10119 12:48:16.385173 Sending DHCP request... done.
10120 12:48:16.385642
10121 12:48:16.386016 Waiting for reply... done.
10122 12:48:16.388032
10123 12:48:16.388567 My ip is 192.168.201.14
10124 12:48:16.388959
10125 12:48:16.391435 The DHCP server ip is 192.168.201.1
10126 12:48:16.392035
10127 12:48:16.394855 TFTP server IP predefined by user: 192.168.201.1
10128 12:48:16.395329
10129 12:48:16.401426 Bootfile predefined by user: 10724916/tftp-deploy-8qwfh__e/kernel/image.itb
10130 12:48:16.401990
10131 12:48:16.405019 Sending tftp read request... done.
10132 12:48:16.405490
10133 12:48:16.413527 Waiting for the transfer...
10134 12:48:16.414096
10135 12:48:16.766081 00000000 ################################################################
10136 12:48:16.766610
10137 12:48:17.114631 00080000 ################################################################
10138 12:48:17.115182
10139 12:48:17.467962 00100000 ################################################################
10140 12:48:17.468481
10141 12:48:17.813728 00180000 ################################################################
10142 12:48:17.814248
10143 12:48:18.163895 00200000 ################################################################
10144 12:48:18.164441
10145 12:48:18.515005 00280000 ################################################################
10146 12:48:18.515546
10147 12:48:18.758520 00300000 ################################################################
10148 12:48:18.758661
10149 12:48:18.985661 00380000 ################################################################
10150 12:48:18.985795
10151 12:48:19.212264 00400000 ################################################################
10152 12:48:19.212396
10153 12:48:19.438973 00480000 ################################################################
10154 12:48:19.439103
10155 12:48:19.666162 00500000 ################################################################
10156 12:48:19.666297
10157 12:48:19.893279 00580000 ################################################################
10158 12:48:19.893424
10159 12:48:20.119867 00600000 ################################################################
10160 12:48:20.120017
10161 12:48:20.346819 00680000 ################################################################
10162 12:48:20.346958
10163 12:48:20.576951 00700000 ################################################################
10164 12:48:20.577088
10165 12:48:20.842635 00780000 ################################################################
10166 12:48:20.842778
10167 12:48:21.094454 00800000 ################################################################
10168 12:48:21.094594
10169 12:48:21.320003 00880000 ################################################################
10170 12:48:21.320135
10171 12:48:21.548300 00900000 ################################################################
10172 12:48:21.548434
10173 12:48:21.774407 00980000 ################################################################
10174 12:48:21.774542
10175 12:48:22.005539 00a00000 ################################################################
10176 12:48:22.005677
10177 12:48:22.243408 00a80000 ################################################################
10178 12:48:22.243567
10179 12:48:22.469401 00b00000 ################################################################
10180 12:48:22.469531
10181 12:48:22.696094 00b80000 ################################################################
10182 12:48:22.696234
10183 12:48:22.926415 00c00000 ################################################################
10184 12:48:22.926548
10185 12:48:23.169892 00c80000 ################################################################
10186 12:48:23.170034
10187 12:48:23.417403 00d00000 ################################################################
10188 12:48:23.417541
10189 12:48:23.653135 00d80000 ################################################################
10190 12:48:23.653277
10191 12:48:23.889267 00e00000 ################################################################
10192 12:48:23.889401
10193 12:48:24.130593 00e80000 ################################################################
10194 12:48:24.130735
10195 12:48:24.367378 00f00000 ################################################################
10196 12:48:24.367515
10197 12:48:24.609116 00f80000 ################################################################
10198 12:48:24.609255
10199 12:48:24.838760 01000000 ################################################################
10200 12:48:24.838919
10201 12:48:25.074740 01080000 ################################################################
10202 12:48:25.074882
10203 12:48:25.309153 01100000 ################################################################
10204 12:48:25.309293
10205 12:48:25.535347 01180000 ################################################################
10206 12:48:25.535519
10207 12:48:25.762068 01200000 ################################################################
10208 12:48:25.762203
10209 12:48:25.988625 01280000 ################################################################
10210 12:48:25.988759
10211 12:48:26.214884 01300000 ################################################################
10212 12:48:26.215018
10213 12:48:26.439649 01380000 ################################################################
10214 12:48:26.439776
10215 12:48:26.667016 01400000 ################################################################
10216 12:48:26.667150
10217 12:48:26.896481 01480000 ################################################################
10218 12:48:26.896618
10219 12:48:27.123398 01500000 ################################################################
10220 12:48:27.123534
10221 12:48:27.350695 01580000 ################################################################
10222 12:48:27.350833
10223 12:48:27.584766 01600000 ################################################################
10224 12:48:27.584912
10225 12:48:27.821279 01680000 ################################################################
10226 12:48:27.821422
10227 12:48:28.052635 01700000 ################################################################
10228 12:48:28.052809
10229 12:48:28.281657 01780000 ################################################################
10230 12:48:28.281815
10231 12:48:28.508713 01800000 ################################################################
10232 12:48:28.508870
10233 12:48:28.733274 01880000 ################################################################
10234 12:48:28.733441
10235 12:48:28.959210 01900000 ################################################################
10236 12:48:28.959369
10237 12:48:29.182441 01980000 ################################################################
10238 12:48:29.182598
10239 12:48:29.406039 01a00000 ################################################################
10240 12:48:29.406182
10241 12:48:29.630102 01a80000 ################################################################
10242 12:48:29.630242
10243 12:48:29.859354 01b00000 ################################################################
10244 12:48:29.859512
10245 12:48:30.083413 01b80000 ################################################################
10246 12:48:30.083544
10247 12:48:30.307036 01c00000 ################################################################
10248 12:48:30.307172
10249 12:48:30.531860 01c80000 ################################################################
10250 12:48:30.531991
10251 12:48:30.757310 01d00000 ################################################################
10252 12:48:30.757447
10253 12:48:30.981600 01d80000 ################################################################
10254 12:48:30.981756
10255 12:48:31.206547 01e00000 ################################################################
10256 12:48:31.206700
10257 12:48:31.432286 01e80000 ################################################################
10258 12:48:31.432420
10259 12:48:31.657290 01f00000 ################################################################
10260 12:48:31.657423
10261 12:48:31.882608 01f80000 ################################################################
10262 12:48:31.882742
10263 12:48:32.108308 02000000 ################################################################
10264 12:48:32.108446
10265 12:48:32.344313 02080000 ################################################################
10266 12:48:32.344445
10267 12:48:32.573416 02100000 ################################################################
10268 12:48:32.573551
10269 12:48:32.797174 02180000 ################################################################
10270 12:48:32.797312
10271 12:48:33.029948 02200000 ################################################################
10272 12:48:33.030087
10273 12:48:33.268416 02280000 ################################################################
10274 12:48:33.268611
10275 12:48:33.493512 02300000 ################################################################
10276 12:48:33.493677
10277 12:48:33.719708 02380000 ################################################################
10278 12:48:33.719843
10279 12:48:33.944152 02400000 ################################################################
10280 12:48:33.944325
10281 12:48:34.168377 02480000 ################################################################
10282 12:48:34.168570
10283 12:48:34.394014 02500000 ################################################################
10284 12:48:34.394147
10285 12:48:34.625689 02580000 ################################################################
10286 12:48:34.625848
10287 12:48:34.854169 02600000 ################################################################
10288 12:48:34.854336
10289 12:48:35.085132 02680000 ################################################################
10290 12:48:35.085266
10291 12:48:35.310953 02700000 ################################################################
10292 12:48:35.311088
10293 12:48:35.539762 02780000 ################################################################
10294 12:48:35.539898
10295 12:48:35.782513 02800000 ################################################################
10296 12:48:35.782679
10297 12:48:36.039886 02880000 ################################################################
10298 12:48:36.040051
10299 12:48:36.265303 02900000 ################################################################
10300 12:48:36.265493
10301 12:48:36.521221 02980000 ################################################################
10302 12:48:36.521360
10303 12:48:36.792173 02a00000 ################################################################
10304 12:48:36.792313
10305 12:48:37.064238 02a80000 ################################################################
10306 12:48:37.064398
10307 12:48:37.338024 02b00000 ################################################################
10308 12:48:37.338160
10309 12:48:37.580968 02b80000 ################################################################
10310 12:48:37.581097
10311 12:48:37.820368 02c00000 ################################################################
10312 12:48:37.820577
10313 12:48:38.075262 02c80000 ################################################################
10314 12:48:38.075440
10315 12:48:38.352488 02d00000 ################################################################
10316 12:48:38.352657
10317 12:48:38.627151 02d80000 ################################################################
10318 12:48:38.627307
10319 12:48:38.892905 02e00000 ################################################################
10320 12:48:38.893042
10321 12:48:39.169211 02e80000 ################################################################
10322 12:48:39.169373
10323 12:48:39.443780 02f00000 ################################################################
10324 12:48:39.443922
10325 12:48:39.701551 02f80000 ################################################################
10326 12:48:39.701690
10327 12:48:39.857911 03000000 ##################################### done.
10328 12:48:39.858400
10329 12:48:39.860986 The bootfile was 50634554 bytes long.
10330 12:48:39.861419
10331 12:48:39.864478 Sending tftp read request... done.
10332 12:48:39.864944
10333 12:48:39.865287 Waiting for the transfer...
10334 12:48:39.868087
10335 12:48:39.868512 00000000 # done.
10336 12:48:39.868914
10337 12:48:39.874528 Command line loaded dynamically from TFTP file: 10724916/tftp-deploy-8qwfh__e/kernel/cmdline
10338 12:48:39.875061
10339 12:48:39.887436 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10340 12:48:39.887974
10341 12:48:39.888312 Loading FIT.
10342 12:48:39.888680
10343 12:48:39.890993 Image ramdisk-1 has 40143219 bytes.
10344 12:48:39.891513
10345 12:48:39.894782 Image fdt-1 has 46924 bytes.
10346 12:48:39.895351
10347 12:48:39.897787 Image kernel-1 has 10442380 bytes.
10348 12:48:39.898355
10349 12:48:39.906986 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10350 12:48:39.907531
10351 12:48:39.923837 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10352 12:48:39.924416
10353 12:48:39.927013 Choosing best match conf-1 for compat google,spherion-rev2.
10354 12:48:39.930804
10355 12:48:39.934390 Connected to device vid:did:rid of 1ae0:0028:00
10356 12:48:39.944396
10357 12:48:39.947523 tpm_get_response: command 0x17b, return code 0x0
10358 12:48:39.948092
10359 12:48:39.950775 ec_init: CrosEC protocol v3 supported (256, 248)
10360 12:48:39.955246
10361 12:48:39.958175 tpm_cleanup: add release locality here.
10362 12:48:39.958661
10363 12:48:39.959031 Shutting down all USB controllers.
10364 12:48:39.961839
10365 12:48:39.962298 Removing current net device
10366 12:48:39.962670
10367 12:48:39.968347 Exiting depthcharge with code 4 at timestamp: 57870098
10368 12:48:39.968859
10369 12:48:39.972007 LZMA decompressing kernel-1 to 0x821a6718
10370 12:48:39.972470
10371 12:48:39.974920 LZMA decompressing kernel-1 to 0x40000000
10372 12:48:41.285711
10373 12:48:41.286271 jumping to kernel
10374 12:48:41.287820 end: 2.2.4 bootloader-commands (duration 00:00:30) [common]
10375 12:48:41.288363 start: 2.2.5 auto-login-action (timeout 00:03:55) [common]
10376 12:48:41.288805 Setting prompt string to ['Linux version [0-9]']
10377 12:48:41.289172 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10378 12:48:41.289540 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10379 12:48:41.366969
10380 12:48:41.370462 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10381 12:48:41.373906 start: 2.2.5.1 login-action (timeout 00:03:55) [common]
10382 12:48:41.374421 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10383 12:48:41.374892 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10384 12:48:41.375319 Using line separator: #'\n'#
10385 12:48:41.375676 No login prompt set.
10386 12:48:41.376019 Parsing kernel messages
10387 12:48:41.376341 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10388 12:48:41.376984 [login-action] Waiting for messages, (timeout 00:03:55)
10389 12:48:41.394027 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j35827-arm64-gcc-10-defconfig-arm64-chromebook-fwl9s) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023
10390 12:48:41.396607 [ 0.000000] random: crng init done
10391 12:48:41.403929 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10392 12:48:41.404489 [ 0.000000] efi: UEFI not found.
10393 12:48:41.412547 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10394 12:48:41.419865 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10395 12:48:41.429566 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10396 12:48:41.439697 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10397 12:48:41.446845 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10398 12:48:41.452812 [ 0.000000] printk: bootconsole [mtk8250] enabled
10399 12:48:41.459062 [ 0.000000] NUMA: No NUMA configuration found
10400 12:48:41.465775 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10401 12:48:41.469237 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10402 12:48:41.472499 [ 0.000000] Zone ranges:
10403 12:48:41.479237 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10404 12:48:41.482678 [ 0.000000] DMA32 empty
10405 12:48:41.489070 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10406 12:48:41.492456 [ 0.000000] Movable zone start for each node
10407 12:48:41.495744 [ 0.000000] Early memory node ranges
10408 12:48:41.502607 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10409 12:48:41.508916 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10410 12:48:41.516248 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10411 12:48:41.521675 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10412 12:48:41.529048 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10413 12:48:41.534884 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10414 12:48:41.591127 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10415 12:48:41.597717 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10416 12:48:41.604627 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10417 12:48:41.607711 [ 0.000000] psci: probing for conduit method from DT.
10418 12:48:41.614323 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10419 12:48:41.617356 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10420 12:48:41.623791 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10421 12:48:41.627583 [ 0.000000] psci: SMC Calling Convention v1.2
10422 12:48:41.633926 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10423 12:48:41.637469 [ 0.000000] Detected VIPT I-cache on CPU0
10424 12:48:41.644000 [ 0.000000] CPU features: detected: GIC system register CPU interface
10425 12:48:41.650910 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10426 12:48:41.657125 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10427 12:48:41.663674 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10428 12:48:41.673912 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10429 12:48:41.679989 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10430 12:48:41.683192 [ 0.000000] alternatives: applying boot alternatives
10431 12:48:41.690722 [ 0.000000] Fallback order for Node 0: 0
10432 12:48:41.697182 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10433 12:48:41.700117 [ 0.000000] Policy zone: Normal
10434 12:48:41.710184 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10435 12:48:41.723310 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10436 12:48:41.733000 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10437 12:48:41.743168 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10438 12:48:41.749280 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10439 12:48:41.752510 <6>[ 0.000000] software IO TLB: area num 8.
10440 12:48:41.809400 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10441 12:48:41.959704 <6>[ 0.000000] Memory: 7931956K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 420812K reserved, 32768K cma-reserved)
10442 12:48:41.966002 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10443 12:48:41.972368 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10444 12:48:41.975340 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10445 12:48:41.982570 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10446 12:48:41.988870 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10447 12:48:41.991594 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10448 12:48:42.001956 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10449 12:48:42.008808 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10450 12:48:42.015285 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10451 12:48:42.021694 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10452 12:48:42.024853 <6>[ 0.000000] GICv3: 608 SPIs implemented
10453 12:48:42.028003 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10454 12:48:42.034921 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10455 12:48:42.038172 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10456 12:48:42.044902 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10457 12:48:42.057549 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10458 12:48:42.070796 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10459 12:48:42.077172 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10460 12:48:42.085786 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10461 12:48:42.098253 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10462 12:48:42.105380 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10463 12:48:42.112618 <6>[ 0.009179] Console: colour dummy device 80x25
10464 12:48:42.121987 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10465 12:48:42.128363 <6>[ 0.024347] pid_max: default: 32768 minimum: 301
10466 12:48:42.131989 <6>[ 0.029219] LSM: Security Framework initializing
10467 12:48:42.138373 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10468 12:48:42.148217 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10469 12:48:42.158948 <6>[ 0.051448] cblist_init_generic: Setting adjustable number of callback queues.
10470 12:48:42.161958 <6>[ 0.058949] cblist_init_generic: Setting shift to 3 and lim to 1.
10471 12:48:42.167742 <6>[ 0.065289] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 12:48:42.174487 <6>[ 0.071737] rcu: Hierarchical SRCU implementation.
10473 12:48:42.181007 <6>[ 0.076751] rcu: Max phase no-delay instances is 1000.
10474 12:48:42.187596 <6>[ 0.083766] EFI services will not be available.
10475 12:48:42.191104 <6>[ 0.088736] smp: Bringing up secondary CPUs ...
10476 12:48:42.199191 <6>[ 0.093784] Detected VIPT I-cache on CPU1
10477 12:48:42.205428 <6>[ 0.093855] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10478 12:48:42.212236 <6>[ 0.093886] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10479 12:48:42.215363 <6>[ 0.094218] Detected VIPT I-cache on CPU2
10480 12:48:42.225460 <6>[ 0.094268] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10481 12:48:42.232208 <6>[ 0.094283] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10482 12:48:42.235615 <6>[ 0.094544] Detected VIPT I-cache on CPU3
10483 12:48:42.241710 <6>[ 0.094591] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10484 12:48:42.248664 <6>[ 0.094606] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10485 12:48:42.255614 <6>[ 0.094909] CPU features: detected: Spectre-v4
10486 12:48:42.257909 <6>[ 0.094917] CPU features: detected: Spectre-BHB
10487 12:48:42.261667 <6>[ 0.094922] Detected PIPT I-cache on CPU4
10488 12:48:42.268455 <6>[ 0.094980] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10489 12:48:42.274697 <6>[ 0.094996] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10490 12:48:42.281551 <6>[ 0.095291] Detected PIPT I-cache on CPU5
10491 12:48:42.287785 <6>[ 0.095354] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10492 12:48:42.294184 <6>[ 0.095370] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10493 12:48:42.297424 <6>[ 0.095651] Detected PIPT I-cache on CPU6
10494 12:48:42.303989 <6>[ 0.095715] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10495 12:48:42.314348 <6>[ 0.095731] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10496 12:48:42.318151 <6>[ 0.096031] Detected PIPT I-cache on CPU7
10497 12:48:42.324431 <6>[ 0.096095] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10498 12:48:42.331202 <6>[ 0.096111] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10499 12:48:42.333889 <6>[ 0.096157] smp: Brought up 1 node, 8 CPUs
10500 12:48:42.340469 <6>[ 0.237583] SMP: Total of 8 processors activated.
10501 12:48:42.344010 <6>[ 0.242504] CPU features: detected: 32-bit EL0 Support
10502 12:48:42.353817 <6>[ 0.247866] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10503 12:48:42.360727 <6>[ 0.256666] CPU features: detected: Common not Private translations
10504 12:48:42.367347 <6>[ 0.263142] CPU features: detected: CRC32 instructions
10505 12:48:42.373324 <6>[ 0.268527] CPU features: detected: RCpc load-acquire (LDAPR)
10506 12:48:42.376606 <6>[ 0.274523] CPU features: detected: LSE atomic instructions
10507 12:48:42.383247 <6>[ 0.280340] CPU features: detected: Privileged Access Never
10508 12:48:42.390279 <6>[ 0.286120] CPU features: detected: RAS Extension Support
10509 12:48:42.396778 <6>[ 0.291729] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10510 12:48:42.399753 <6>[ 0.298950] CPU: All CPU(s) started at EL2
10511 12:48:42.406539 <6>[ 0.303267] alternatives: applying system-wide alternatives
10512 12:48:42.416573 <6>[ 0.314004] devtmpfs: initialized
10513 12:48:42.432746 <6>[ 0.322884] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10514 12:48:42.438687 <6>[ 0.332845] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10515 12:48:42.445995 <6>[ 0.341070] pinctrl core: initialized pinctrl subsystem
10516 12:48:42.448657 <6>[ 0.347745] DMI not present or invalid.
10517 12:48:42.455371 <6>[ 0.352150] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10518 12:48:42.465236 <6>[ 0.359011] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10519 12:48:42.471404 <6>[ 0.366588] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10520 12:48:42.481572 <6>[ 0.374811] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10521 12:48:42.485107 <6>[ 0.383054] audit: initializing netlink subsys (disabled)
10522 12:48:42.495887 <5>[ 0.388747] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10523 12:48:42.501517 <6>[ 0.389451] thermal_sys: Registered thermal governor 'step_wise'
10524 12:48:42.508296 <6>[ 0.396710] thermal_sys: Registered thermal governor 'power_allocator'
10525 12:48:42.511864 <6>[ 0.402966] cpuidle: using governor menu
10526 12:48:42.518055 <6>[ 0.413925] NET: Registered PF_QIPCRTR protocol family
10527 12:48:42.524318 <6>[ 0.419395] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10528 12:48:42.531306 <6>[ 0.426493] ASID allocator initialised with 32768 entries
10529 12:48:42.534147 <6>[ 0.433071] Serial: AMBA PL011 UART driver
10530 12:48:42.544724 <4>[ 0.441685] Trying to register duplicate clock ID: 134
10531 12:48:42.600837 <6>[ 0.501248] KASLR enabled
10532 12:48:42.615466 <6>[ 0.509014] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10533 12:48:42.621702 <6>[ 0.516029] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10534 12:48:42.627901 <6>[ 0.522519] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10535 12:48:42.634323 <6>[ 0.529522] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10536 12:48:42.641050 <6>[ 0.536008] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10537 12:48:42.648184 <6>[ 0.543013] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10538 12:48:42.654468 <6>[ 0.549500] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10539 12:48:42.661303 <6>[ 0.556504] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10540 12:48:42.664269 <6>[ 0.564026] ACPI: Interpreter disabled.
10541 12:48:42.673148 <6>[ 0.570425] iommu: Default domain type: Translated
10542 12:48:42.679834 <6>[ 0.575535] iommu: DMA domain TLB invalidation policy: strict mode
10543 12:48:42.683214 <5>[ 0.582193] SCSI subsystem initialized
10544 12:48:42.690114 <6>[ 0.586362] usbcore: registered new interface driver usbfs
10545 12:48:42.696242 <6>[ 0.592096] usbcore: registered new interface driver hub
10546 12:48:42.699858 <6>[ 0.597651] usbcore: registered new device driver usb
10547 12:48:42.706802 <6>[ 0.603741] pps_core: LinuxPPS API ver. 1 registered
10548 12:48:42.716122 <6>[ 0.608935] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10549 12:48:42.719987 <6>[ 0.618275] PTP clock support registered
10550 12:48:42.723144 <6>[ 0.622513] EDAC MC: Ver: 3.0.0
10551 12:48:42.730367 <6>[ 0.627671] FPGA manager framework
10552 12:48:42.737027 <6>[ 0.631352] Advanced Linux Sound Architecture Driver Initialized.
10553 12:48:42.739864 <6>[ 0.638132] vgaarb: loaded
10554 12:48:42.746934 <6>[ 0.641297] clocksource: Switched to clocksource arch_sys_counter
10555 12:48:42.750243 <5>[ 0.647736] VFS: Disk quotas dquot_6.6.0
10556 12:48:42.756440 <6>[ 0.651923] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10557 12:48:42.760500 <6>[ 0.659112] pnp: PnP ACPI: disabled
10558 12:48:42.769409 <6>[ 0.665862] NET: Registered PF_INET protocol family
10559 12:48:42.778269 <6>[ 0.671445] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10560 12:48:42.790509 <6>[ 0.683764] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10561 12:48:42.799554 <6>[ 0.692580] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10562 12:48:42.806545 <6>[ 0.700551] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10563 12:48:42.813393 <6>[ 0.709249] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10564 12:48:42.824965 <6>[ 0.718993] TCP: Hash tables configured (established 65536 bind 65536)
10565 12:48:42.831410 <6>[ 0.725851] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10566 12:48:42.838158 <6>[ 0.733048] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10567 12:48:42.844782 <6>[ 0.740750] NET: Registered PF_UNIX/PF_LOCAL protocol family
10568 12:48:42.851576 <6>[ 0.746929] RPC: Registered named UNIX socket transport module.
10569 12:48:42.854259 <6>[ 0.753082] RPC: Registered udp transport module.
10570 12:48:42.861012 <6>[ 0.758015] RPC: Registered tcp transport module.
10571 12:48:42.867790 <6>[ 0.762949] RPC: Registered tcp NFSv4.1 backchannel transport module.
10572 12:48:42.871170 <6>[ 0.769618] PCI: CLS 0 bytes, default 64
10573 12:48:42.873948 <6>[ 0.773975] Unpacking initramfs...
10574 12:48:42.891948 <6>[ 0.785944] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10575 12:48:42.901926 <6>[ 0.794608] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10576 12:48:42.905264 <6>[ 0.803466] kvm [1]: IPA Size Limit: 40 bits
10577 12:48:42.911966 <6>[ 0.807990] kvm [1]: GICv3: no GICV resource entry
10578 12:48:42.915532 <6>[ 0.813008] kvm [1]: disabling GICv2 emulation
10579 12:48:42.921729 <6>[ 0.817701] kvm [1]: GIC system register CPU interface enabled
10580 12:48:42.925691 <6>[ 0.823868] kvm [1]: vgic interrupt IRQ18
10581 12:48:42.931411 <6>[ 0.828230] kvm [1]: VHE mode initialized successfully
10582 12:48:42.937788 <5>[ 0.834709] Initialise system trusted keyrings
10583 12:48:42.944355 <6>[ 0.839538] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10584 12:48:42.952191 <6>[ 0.849552] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10585 12:48:42.959535 <5>[ 0.855932] NFS: Registering the id_resolver key type
10586 12:48:42.962239 <5>[ 0.861238] Key type id_resolver registered
10587 12:48:42.968862 <5>[ 0.865655] Key type id_legacy registered
10588 12:48:42.975586 <6>[ 0.869937] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10589 12:48:42.982115 <6>[ 0.876861] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10590 12:48:42.988636 <6>[ 0.884582] 9p: Installing v9fs 9p2000 file system support
10591 12:48:43.023928 <5>[ 0.921263] Key type asymmetric registered
10592 12:48:43.027220 <5>[ 0.925594] Asymmetric key parser 'x509' registered
10593 12:48:43.036927 <6>[ 0.930738] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10594 12:48:43.040469 <6>[ 0.938349] io scheduler mq-deadline registered
10595 12:48:43.044482 <6>[ 0.943107] io scheduler kyber registered
10596 12:48:43.062970 <6>[ 0.960060] EINJ: ACPI disabled.
10597 12:48:43.094951 <4>[ 0.985848] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 12:48:43.105312 <4>[ 0.996506] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10599 12:48:43.119785 <6>[ 1.017081] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10600 12:48:43.128004 <6>[ 1.025063] printk: console [ttyS0] disabled
10601 12:48:43.155611 <6>[ 1.049717] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10602 12:48:43.162188 <6>[ 1.059194] printk: console [ttyS0] enabled
10603 12:48:43.165357 <6>[ 1.059194] printk: console [ttyS0] enabled
10604 12:48:43.171952 <6>[ 1.068091] printk: bootconsole [mtk8250] disabled
10605 12:48:43.175318 <6>[ 1.068091] printk: bootconsole [mtk8250] disabled
10606 12:48:43.181976 <6>[ 1.079391] SuperH (H)SCI(F) driver initialized
10607 12:48:43.186181 <6>[ 1.084675] msm_serial: driver initialized
10608 12:48:43.199686 <6>[ 1.093694] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10609 12:48:43.209922 <6>[ 1.102243] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10610 12:48:43.215999 <6>[ 1.110785] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10611 12:48:43.225758 <6>[ 1.119414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10612 12:48:43.235753 <6>[ 1.128120] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10613 12:48:43.242514 <6>[ 1.136846] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10614 12:48:43.252826 <6>[ 1.145387] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10615 12:48:43.259000 <6>[ 1.154197] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10616 12:48:43.268705 <6>[ 1.162740] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10617 12:48:43.280788 <6>[ 1.178380] loop: module loaded
10618 12:48:43.287935 <6>[ 1.184464] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10619 12:48:43.310930 <4>[ 1.207898] mtk-pmic-keys: Failed to locate of_node [id: -1]
10620 12:48:43.317267 <6>[ 1.214709] megasas: 07.719.03.00-rc1
10621 12:48:43.327145 <6>[ 1.224281] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10622 12:48:43.339775 <6>[ 1.236684] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10623 12:48:43.356206 <6>[ 1.253390] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10624 12:48:43.416744 <6>[ 1.307377] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10625 12:48:44.483490 <6>[ 2.381010] Freeing initrd memory: 39196K
10626 12:48:44.493783 <6>[ 2.391411] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10627 12:48:44.505039 <6>[ 2.402525] tun: Universal TUN/TAP device driver, 1.6
10628 12:48:44.508184 <6>[ 2.408583] thunder_xcv, ver 1.0
10629 12:48:44.511546 <6>[ 2.412086] thunder_bgx, ver 1.0
10630 12:48:44.514960 <6>[ 2.415583] nicpf, ver 1.0
10631 12:48:44.525308 <6>[ 2.419602] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10632 12:48:44.528692 <6>[ 2.427078] hns3: Copyright (c) 2017 Huawei Corporation.
10633 12:48:44.535714 <6>[ 2.432666] hclge is initializing
10634 12:48:44.538899 <6>[ 2.436250] e1000: Intel(R) PRO/1000 Network Driver
10635 12:48:44.545192 <6>[ 2.441379] e1000: Copyright (c) 1999-2006 Intel Corporation.
10636 12:48:44.548746 <6>[ 2.447397] e1000e: Intel(R) PRO/1000 Network Driver
10637 12:48:44.555086 <6>[ 2.452613] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10638 12:48:44.561764 <6>[ 2.458799] igb: Intel(R) Gigabit Ethernet Network Driver
10639 12:48:44.568662 <6>[ 2.464449] igb: Copyright (c) 2007-2014 Intel Corporation.
10640 12:48:44.575202 <6>[ 2.470285] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10641 12:48:44.582381 <6>[ 2.476803] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10642 12:48:44.585376 <6>[ 2.483267] sky2: driver version 1.30
10643 12:48:44.591710 <6>[ 2.488251] VFIO - User Level meta-driver version: 0.3
10644 12:48:44.598703 <6>[ 2.496486] usbcore: registered new interface driver usb-storage
10645 12:48:44.605926 <6>[ 2.502937] usbcore: registered new device driver onboard-usb-hub
10646 12:48:44.614762 <6>[ 2.512083] mt6397-rtc mt6359-rtc: registered as rtc0
10647 12:48:44.625248 <6>[ 2.517549] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-14T12:48:44 UTC (1686746924)
10648 12:48:44.628067 <6>[ 2.527113] i2c_dev: i2c /dev entries driver
10649 12:48:44.644897 <6>[ 2.538902] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10650 12:48:44.651547 <6>[ 2.549142] sdhci: Secure Digital Host Controller Interface driver
10651 12:48:44.658640 <6>[ 2.555582] sdhci: Copyright(c) Pierre Ossman
10652 12:48:44.665013 <6>[ 2.560969] Synopsys Designware Multimedia Card Interface Driver
10653 12:48:44.668627 <6>[ 2.567561] mmc0: CQHCI version 5.10
10654 12:48:44.674848 <6>[ 2.568115] sdhci-pltfm: SDHCI platform and OF driver helper
10655 12:48:44.681956 <6>[ 2.579416] ledtrig-cpu: registered to indicate activity on CPUs
10656 12:48:44.692275 <6>[ 2.586807] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10657 12:48:44.695730 <6>[ 2.594209] usbcore: registered new interface driver usbhid
10658 12:48:44.702447 <6>[ 2.600041] usbhid: USB HID core driver
10659 12:48:44.708563 <6>[ 2.604282] spi_master spi0: will run message pump with realtime priority
10660 12:48:44.756672 <6>[ 2.647092] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10661 12:48:44.775903 <6>[ 2.663018] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10662 12:48:44.779160 <6>[ 2.676601] mmc0: Command Queue Engine enabled
10663 12:48:44.785742 <6>[ 2.678997] cros-ec-spi spi0.0: Chrome EC device registered
10664 12:48:44.792321 <6>[ 2.681335] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10665 12:48:44.796745 <6>[ 2.694583] mmcblk0: mmc0:0001 DA4128 116 GiB
10666 12:48:44.807514 <6>[ 2.704335] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10667 12:48:44.816820 <6>[ 2.704918] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10668 12:48:44.823442 <6>[ 2.711700] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10669 12:48:44.826838 <6>[ 2.721728] NET: Registered PF_PACKET protocol family
10670 12:48:44.833285 <6>[ 2.725481] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10671 12:48:44.836685 <6>[ 2.730236] 9pnet: Installing 9P2000 support
10672 12:48:44.843296 <6>[ 2.736013] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10673 12:48:44.849791 <5>[ 2.739892] Key type dns_resolver registered
10674 12:48:44.853442 <6>[ 2.751355] registered taskstats version 1
10675 12:48:44.859292 <5>[ 2.755739] Loading compiled-in X.509 certificates
10676 12:48:44.891113 <4>[ 2.782078] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10677 12:48:44.901338 <4>[ 2.792789] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10678 12:48:44.913186 <3>[ 2.805894] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10679 12:48:44.924468 <6>[ 2.821818] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10680 12:48:44.931058 <6>[ 2.828699] xhci-mtk 11200000.usb: xHCI Host Controller
10681 12:48:44.937990 <6>[ 2.834204] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10682 12:48:44.947705 <6>[ 2.842060] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10683 12:48:44.954615 <6>[ 2.851480] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10684 12:48:44.961190 <6>[ 2.857561] xhci-mtk 11200000.usb: xHCI Host Controller
10685 12:48:44.968281 <6>[ 2.863044] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10686 12:48:44.974873 <6>[ 2.870697] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10687 12:48:44.980904 <6>[ 2.878423] hub 1-0:1.0: USB hub found
10688 12:48:44.984705 <6>[ 2.882444] hub 1-0:1.0: 1 port detected
10689 12:48:44.993727 <6>[ 2.886780] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10690 12:48:44.997634 <6>[ 2.895376] hub 2-0:1.0: USB hub found
10691 12:48:45.001121 <6>[ 2.899390] hub 2-0:1.0: 1 port detected
10692 12:48:45.009685 <6>[ 2.906567] mtk-msdc 11f70000.mmc: Got CD GPIO
10693 12:48:45.028717 <6>[ 2.922617] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10694 12:48:45.035088 <6>[ 2.930642] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10695 12:48:45.044830 <4>[ 2.938627] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10696 12:48:45.054450 <6>[ 2.948305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10697 12:48:45.061545 <6>[ 2.956387] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10698 12:48:45.071706 <6>[ 2.964428] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10699 12:48:45.077981 <6>[ 2.972353] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10700 12:48:45.084132 <6>[ 2.980174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10701 12:48:45.094042 <6>[ 2.987996] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10702 12:48:45.104419 <6>[ 2.998805] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10703 12:48:45.114385 <6>[ 3.007190] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10704 12:48:45.121348 <6>[ 3.015535] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10705 12:48:45.130597 <6>[ 3.023877] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10706 12:48:45.137088 <6>[ 3.032220] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10707 12:48:45.147227 <6>[ 3.040569] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10708 12:48:45.153835 <6>[ 3.048912] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10709 12:48:45.163912 <6>[ 3.057256] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10710 12:48:45.170836 <6>[ 3.065600] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10711 12:48:45.180575 <6>[ 3.073944] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10712 12:48:45.187297 <6>[ 3.082287] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10713 12:48:45.196681 <6>[ 3.090631] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10714 12:48:45.203740 <6>[ 3.098974] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10715 12:48:45.214425 <6>[ 3.107320] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10716 12:48:45.220319 <6>[ 3.115669] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10717 12:48:45.227771 <6>[ 3.124578] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10718 12:48:45.234199 <6>[ 3.132016] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10719 12:48:45.241620 <6>[ 3.139056] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10720 12:48:45.251753 <6>[ 3.146165] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10721 12:48:45.258350 <6>[ 3.153457] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10722 12:48:45.268070 <6>[ 3.160383] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10723 12:48:45.275274 <6>[ 3.169529] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10724 12:48:45.285408 <6>[ 3.178656] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10725 12:48:45.294598 <6>[ 3.187958] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10726 12:48:45.304344 <6>[ 3.197436] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10727 12:48:45.314578 <6>[ 3.206910] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10728 12:48:45.325038 <6>[ 3.216036] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10729 12:48:45.331224 <6>[ 3.225514] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10730 12:48:45.341232 <6>[ 3.234642] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10731 12:48:45.350812 <6>[ 3.243953] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10732 12:48:45.360935 <6>[ 3.254120] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10733 12:48:45.371476 <6>[ 3.265752] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10734 12:48:45.391252 <6>[ 3.285696] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10735 12:48:45.420474 <6>[ 3.317951] hub 2-1:1.0: USB hub found
10736 12:48:45.423527 <6>[ 3.322493] hub 2-1:1.0: 3 ports detected
10737 12:48:45.543155 <6>[ 3.437542] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10738 12:48:45.695657 <6>[ 3.593214] hub 1-1:1.0: USB hub found
10739 12:48:45.699260 <6>[ 3.597578] hub 1-1:1.0: 4 ports detected
10740 12:48:46.019221 <6>[ 3.913572] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10741 12:48:46.149677 <6>[ 4.047459] hub 1-1.1:1.0: USB hub found
10742 12:48:46.153243 <6>[ 4.051741] hub 1-1.1:1.0: 4 ports detected
10743 12:48:46.267003 <6>[ 4.161347] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10744 12:48:46.399836 <6>[ 4.297706] hub 1-1.4:1.0: USB hub found
10745 12:48:46.403505 <6>[ 4.302353] hub 1-1.4:1.0: 2 ports detected
10746 12:48:46.479193 <6>[ 4.373573] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10747 12:48:46.667251 <6>[ 4.561573] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10748 12:48:46.752232 <3>[ 4.649777] usb 1-1.1.4: device descriptor read/64, error -32
10749 12:48:46.944105 <3>[ 4.841809] usb 1-1.1.4: device descriptor read/64, error -32
10750 12:48:47.139041 <6>[ 5.033572] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10751 12:48:47.326805 <6>[ 5.221572] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10752 12:48:47.412599 <3>[ 5.309661] usb 1-1.1.4: device descriptor read/64, error -32
10753 12:48:47.603878 <3>[ 5.501777] usb 1-1.1.4: device descriptor read/64, error -32
10754 12:48:47.717128 <6>[ 5.614148] usb 1-1.1-port4: attempt power cycle
10755 12:48:47.802979 <6>[ 5.697571] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10756 12:48:48.327096 <6>[ 6.221570] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10757 12:48:48.333186 <4>[ 6.228922] usb 1-1.1.4: Device not responding to setup address.
10758 12:48:48.543809 <4>[ 6.441839] usb 1-1.1.4: Device not responding to setup address.
10759 12:48:48.756584 <3>[ 6.653583] usb 1-1.1.4: device not accepting address 10, error -71
10760 12:48:48.842949 <6>[ 6.737575] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10761 12:48:48.849628 <4>[ 6.745020] usb 1-1.1.4: Device not responding to setup address.
10762 12:48:49.060413 <4>[ 6.957813] usb 1-1.1.4: Device not responding to setup address.
10763 12:48:49.271829 <3>[ 7.169558] usb 1-1.1.4: device not accepting address 11, error -71
10764 12:48:49.278440 <3>[ 7.176510] usb 1-1.1-port4: unable to enumerate USB device
10765 12:48:57.660108 <6>[ 15.562120] ALSA device list:
10766 12:48:57.666650 <6>[ 15.565376] No soundcards found.
10767 12:48:57.678580 <6>[ 15.577842] Freeing unused kernel memory: 8384K
10768 12:48:57.682349 <6>[ 15.582741] Run /init as init process
10769 12:48:57.713176 <6>[ 15.611750] NET: Registered PF_INET6 protocol family
10770 12:48:57.719413 <6>[ 15.618024] Segment Routing with IPv6
10771 12:48:57.722818 <6>[ 15.621962] In-situ OAM (IOAM) with IPv6
10772 12:48:57.757177 <30>[ 15.636395] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10773 12:48:57.760854 <30>[ 15.660201] systemd[1]: Detected architecture arm64.
10774 12:48:57.761435
10775 12:48:57.767140 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10776 12:48:57.767701
10777 12:48:57.782832 <30>[ 15.681668] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10778 12:48:57.926059 <30>[ 15.821281] systemd[1]: Queued start job for default target Graphical Interface.
10779 12:48:57.972080 <30>[ 15.870974] systemd[1]: Created slice system-getty.slice.
10780 12:48:57.978523 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10781 12:48:57.995168 <30>[ 15.894200] systemd[1]: Created slice system-modprobe.slice.
10782 12:48:58.001799 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10783 12:48:58.019510 <30>[ 15.918692] systemd[1]: Created slice system-serial\x2dgetty.slice.
10784 12:48:58.029570 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10785 12:48:58.043039 <30>[ 15.942080] systemd[1]: Created slice User and Session Slice.
10786 12:48:58.050189 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10787 12:48:58.070563 <30>[ 15.966132] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10788 12:48:58.080237 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10789 12:48:58.098670 <30>[ 15.994082] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10790 12:48:58.104940 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10791 12:48:58.125355 <30>[ 16.017619] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10792 12:48:58.132646 <30>[ 16.029663] systemd[1]: Reached target Local Encrypted Volumes.
10793 12:48:58.138201 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10794 12:48:58.155378 <30>[ 16.053949] systemd[1]: Reached target Paths.
10795 12:48:58.158152 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10796 12:48:58.174796 <30>[ 16.073618] systemd[1]: Reached target Remote File Systems.
10797 12:48:58.180962 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10798 12:48:58.194790 <30>[ 16.093552] systemd[1]: Reached target Slices.
10799 12:48:58.200765 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10800 12:48:58.215231 <30>[ 16.113618] systemd[1]: Reached target Swap.
10801 12:48:58.218259 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10802 12:48:58.238459 <30>[ 16.133862] systemd[1]: Listening on initctl Compatibility Named Pipe.
10803 12:48:58.244919 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10804 12:48:58.250900 <30>[ 16.148597] systemd[1]: Listening on Journal Audit Socket.
10805 12:48:58.258086 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10806 12:48:58.271084 <30>[ 16.169870] systemd[1]: Listening on Journal Socket (/dev/log).
10807 12:48:58.277439 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10808 12:48:58.295285 <30>[ 16.193902] systemd[1]: Listening on Journal Socket.
10809 12:48:58.301733 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10810 12:48:58.317986 <30>[ 16.213859] systemd[1]: Listening on Network Service Netlink Socket.
10811 12:48:58.325338 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10812 12:48:58.339488 <30>[ 16.238345] systemd[1]: Listening on udev Control Socket.
10813 12:48:58.345583 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10814 12:48:58.363291 <30>[ 16.262285] systemd[1]: Listening on udev Kernel Socket.
10815 12:48:58.369864 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10816 12:48:58.402833 <30>[ 16.301729] systemd[1]: Mounting Huge Pages File System...
10817 12:48:58.409572 Mounting [0;1;39mHuge Pages File System[0m...
10818 12:48:58.424820 <30>[ 16.323539] systemd[1]: Mounting POSIX Message Queue File System...
10819 12:48:58.431143 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10820 12:48:58.448445 <30>[ 16.347469] systemd[1]: Mounting Kernel Debug File System...
10821 12:48:58.454768 Mounting [0;1;39mKernel Debug File System[0m...
10822 12:48:58.473876 <30>[ 16.369809] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10823 12:48:58.485751 <30>[ 16.380684] systemd[1]: Starting Create list of static device nodes for the current kernel...
10824 12:48:58.491430 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10825 12:48:58.508673 <30>[ 16.407708] systemd[1]: Starting Load Kernel Module configfs...
10826 12:48:58.514979 Starting [0;1;39mLoad Kernel Module configfs[0m...
10827 12:48:58.532478 <30>[ 16.431727] systemd[1]: Starting Load Kernel Module drm...
10828 12:48:58.539176 Starting [0;1;39mLoad Kernel Module drm[0m...
10829 12:48:58.559193 <30>[ 16.453763] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10830 12:48:58.568111 <30>[ 16.467371] systemd[1]: Starting Journal Service...
10831 12:48:58.571775 Starting [0;1;39mJournal Service[0m...
10832 12:48:58.589225 <30>[ 16.488199] systemd[1]: Starting Load Kernel Modules...
10833 12:48:58.595999 Starting [0;1;39mLoad Kernel Modules[0m...
10834 12:48:58.616667 <30>[ 16.512451] systemd[1]: Starting Remount Root and Kernel File Systems...
10835 12:48:58.623267 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10836 12:48:58.641291 <30>[ 16.540269] systemd[1]: Starting Coldplug All udev Devices...
10837 12:48:58.647759 Starting [0;1;39mColdplug All udev Devices[0m...
10838 12:48:58.665104 <30>[ 16.564327] systemd[1]: Mounted Huge Pages File System.
10839 12:48:58.672113 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10840 12:48:58.687373 <30>[ 16.586224] systemd[1]: Started Journal Service.
10841 12:48:58.695349 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10842 12:48:58.708299 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10843 12:48:58.723213 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10844 12:48:58.743230 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10845 12:48:58.760310 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10846 12:48:58.776048 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10847 12:48:58.791751 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10848 12:48:58.811658 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10849 12:48:58.826556 See 'systemctl status systemd-remount-fs.service' for details.
10850 12:48:58.863012 Mounting [0;1;39mKernel Configuration File System[0m...
10851 12:48:58.885421 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10852 12:48:58.902896 <46>[ 16.798823] systemd-journald[178]: Received client request to flush runtime journal.
10853 12:48:58.911340 Starting [0;1;39mLoad/Save Random Seed[0m...
10854 12:48:58.929812 Starting [0;1;39mApply Kernel Variables[0m...
10855 12:48:58.949478 Starting [0;1;39mCreate System Users[0m...
10856 12:48:58.971153 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10857 12:48:58.994866 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10858 12:48:59.012162 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10859 12:48:59.027858 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10860 12:48:59.043759 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10861 12:48:59.059510 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10862 12:48:59.111646 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10863 12:48:59.134480 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10864 12:48:59.147300 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10865 12:48:59.163045 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10866 12:48:59.215082 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10867 12:48:59.238363 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10868 12:48:59.256036 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10869 12:48:59.275817 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10870 12:48:59.315537 Starting [0;1;39mNetwork Service[0m...
10871 12:48:59.337684 Starting [0;1;39mNetwork Time Synchronization[0m...
10872 12:48:59.355457 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10873 12:48:59.397883 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10874 12:48:59.412032 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10875 12:48:59.473295 <6>[ 17.368829] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10876 12:48:59.476468 Starting [0;1;39mNetwork Name Resolution[0m...
10877 12:48:59.492009 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10878 12:48:59.505872 <6>[ 17.404869] remoteproc remoteproc0: scp is available
10879 12:48:59.512446 <6>[ 17.407033] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10880 12:48:59.518665 <6>[ 17.411391] remoteproc remoteproc0: powering up scp
10881 12:48:59.528491 <6>[ 17.420945] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10882 12:48:59.535685 <6>[ 17.423203] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10883 12:48:59.545504 <6>[ 17.431893] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10884 12:48:59.552130 <6>[ 17.440359] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10885 12:48:59.555552 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10886 12:48:59.572659 <3>[ 17.468390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10887 12:48:59.579469 <3>[ 17.476567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10888 12:48:59.588891 <3>[ 17.484680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10889 12:48:59.601925 <3>[ 17.497769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10890 12:48:59.608712 <3>[ 17.505962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10891 12:48:59.618657 <3>[ 17.514123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 12:48:59.624900 <3>[ 17.522266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10893 12:48:59.631784 <6>[ 17.529651] mc: Linux media interface: v0.10
10894 12:48:59.638823 <3>[ 17.530363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 12:48:59.644678 <4>[ 17.534484] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10896 12:48:59.654669 <4>[ 17.537720] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10897 12:48:59.668294 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m<3>[ 17.564340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 12:48:59.668928 .
10899 12:48:59.681051 <3>[ 17.576846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10900 12:48:59.687286 <6>[ 17.578209] usbcore: registered new interface driver r8152
10901 12:48:59.694767 <6>[ 17.580402] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10902 12:48:59.701090 <6>[ 17.580427] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10903 12:48:59.707653 <6>[ 17.580433] remoteproc remoteproc0: remote processor scp is now up
10904 12:48:59.717529 <6>[ 17.580528] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10905 12:48:59.724253 <6>[ 17.581224] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10906 12:48:59.730780 <6>[ 17.581233] pci_bus 0000:00: root bus resource [bus 00-ff]
10907 12:48:59.737249 <6>[ 17.581240] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10908 12:48:59.747419 <6>[ 17.581247] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10909 12:48:59.753625 <6>[ 17.581323] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10910 12:48:59.760239 <6>[ 17.581347] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10911 12:48:59.763427 <6>[ 17.581429] pci 0000:00:00.0: supports D1 D2
10912 12:48:59.769901 <6>[ 17.581434] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10913 12:48:59.780408 <3>[ 17.585003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10914 12:48:59.786518 <3>[ 17.585015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 12:48:59.796647 <3>[ 17.586698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 12:48:59.803774 <6>[ 17.594713] videodev: Linux video capture interface: v2.00
10917 12:48:59.810275 <6>[ 17.597610] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10918 12:48:59.816691 <3>[ 17.598203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 12:48:59.829601 <6>[ 17.602009] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10920 12:48:59.833009 <6>[ 17.603699] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10921 12:48:59.843335 <6>[ 17.603736] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10922 12:48:59.849549 <6>[ 17.603759] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10923 12:48:59.856112 <6>[ 17.603777] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10924 12:48:59.862789 <6>[ 17.603909] pci 0000:01:00.0: supports D1 D2
10925 12:48:59.869125 <6>[ 17.603913] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10926 12:48:59.876748 <6>[ 17.611982] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10927 12:48:59.886704 <3>[ 17.613049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 12:48:59.893226 <6>[ 17.613712] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10929 12:48:59.899772 <6>[ 17.613794] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10930 12:48:59.909447 <6>[ 17.613810] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10931 12:48:59.916255 <6>[ 17.613837] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10932 12:48:59.923470 <6>[ 17.613935] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10933 12:48:59.934108 <6>[ 17.613958] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10934 12:48:59.937546 <6>[ 17.613976] pci 0000:00:00.0: PCI bridge to [bus 01]
10935 12:48:59.948101 <6>[ 17.613984] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10936 12:48:59.950993 <6>[ 17.614371] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10937 12:48:59.957478 <6>[ 17.644441] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10938 12:48:59.967551 <3>[ 17.650289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10939 12:48:59.974528 <6>[ 17.656950] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10940 12:48:59.981220 <3>[ 17.664026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 12:48:59.987786 <3>[ 17.664166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10942 12:48:59.998740 <6>[ 17.672822] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10943 12:49:00.004894 <4>[ 17.680999] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10944 12:49:00.011996 <4>[ 17.680999] Fallback method does not support PEC.
10945 12:49:00.019329 <6>[ 17.684502] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10946 12:49:00.029438 <3>[ 17.707749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:49:00.035553 <6>[ 17.732137] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10948 12:49:00.039164 <6>[ 17.741221] Bluetooth: Core ver 2.22
10949 12:49:00.048780 <5>[ 17.742910] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10950 12:49:00.055433 <6>[ 17.751949] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10951 12:49:00.062894 <6>[ 17.754252] NET: Registered PF_BLUETOOTH protocol family
10952 12:49:00.069607 <6>[ 17.754842] usbcore: registered new interface driver cdc_ether
10953 12:49:00.072910 <6>[ 17.761867] usbcore: registered new interface driver r8153_ecm
10954 12:49:00.079336 <5>[ 17.762818] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10955 12:49:00.086058 <6>[ 17.765966] Bluetooth: HCI device and connection manager initialized
10956 12:49:00.095690 <4>[ 17.766068] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10957 12:49:00.102859 <6>[ 17.766086] cfg80211: failed to load regulatory.db
10958 12:49:00.109330 <6>[ 17.783989] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10959 12:49:00.112689 <6>[ 17.790065] Bluetooth: HCI socket layer initialized
10960 12:49:00.118625 <6>[ 17.791090] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10961 12:49:00.132168 <6>[ 17.798405] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10962 12:49:00.139307 <6>[ 17.805109] Bluetooth: L2CAP socket layer initialized
10963 12:49:00.145305 <3>[ 17.809967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 12:49:00.154759 <3>[ 17.810660] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10965 12:49:00.161335 <6>[ 17.813257] usbcore: registered new interface driver uvcvideo
10966 12:49:00.164861 <6>[ 17.821121] Bluetooth: SCO socket layer initialized
10967 12:49:00.174871 <4>[ 17.833053] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10968 12:49:00.184489 <3>[ 17.839484] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10969 12:49:00.191272 <4>[ 17.842329] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10970 12:49:00.202437 <3>[ 17.854680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 12:49:00.208635 <3>[ 17.855390] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 12:49:00.215278 <6>[ 17.878324] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10973 12:49:00.226512 <3>[ 17.879108] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 12:49:00.232806 <6>[ 17.903042] usbcore: registered new interface driver btusb
10975 12:49:00.242840 <4>[ 17.903598] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10976 12:49:00.249258 <3>[ 17.903609] Bluetooth: hci0: Failed to load firmware file (-2)
10977 12:49:00.253843 <3>[ 17.903612] Bluetooth: hci0: Failed to set up firmware (-2)
10978 12:49:00.262927 <4>[ 17.903616] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10979 12:49:00.273077 <3>[ 17.904274] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 12:49:00.279734 <6>[ 17.916028] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10981 12:49:00.283325 <6>[ 17.917476] r8152 1-1.1.1:1.0 eth0: v1.12.13
10982 12:49:00.292617 <3>[ 17.924674] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10983 12:49:00.299867 <6>[ 17.929993] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10984 12:49:00.302753 <6>[ 17.949499] mt7921e 0000:01:00.0: ASIC revision: 79610010
10985 12:49:00.313329 <3>[ 17.972767] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 12:49:00.323304 <4>[ 18.076876] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10987 12:49:00.329654 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10988 12:49:00.340687 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10989 12:49:00.398181 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10990 12:49:00.410635 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10991 12:49:00.434055 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10992 12:49:00.448279 <4>[ 18.340571] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10993 12:49:00.566285 <4>[ 18.459328] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10994 12:49:00.616255 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10995 12:49:00.630371 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10996 12:49:00.649344 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10997 12:49:00.663222 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10998 12:49:00.686199 [[0;32m OK [<4>[ 18.579892] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10999 12:49:00.692429 0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11000 12:49:00.710637 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11001 12:49:00.726251 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11002 12:49:00.750437 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11003 12:49:00.766503 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11004 12:49:00.782987 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11005 12:49:00.808987 [[0;32m OK [0m] Listening on<4>[ 18.699668] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 12:49:00.811949 [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11007 12:49:00.862733 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11008 12:49:00.888680 Starting [0;1;39mUser Login Management[0m...
11009 12:49:00.904491 Starting [0;1;39mPermit User Sessions[0m...
11010 12:49:00.930402 <4>[ 18.822600] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11011 12:49:00.936381 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11012 12:49:00.955317 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11013 12:49:00.979597 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11014 12:49:00.995780 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11015 12:49:01.051364 [[0;32m OK [<4>[ 18.944334] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11016 12:49:01.054730 0m] Started [0;1;39mGetty on tty1[0m.
11017 12:49:01.100178 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11018 12:49:01.114690 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11019 12:49:01.130651 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11020 12:49:01.146520 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11021 12:49:01.171451 <4>[ 19.064041] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11022 12:49:01.203184 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11023 12:49:01.227771 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11024 12:49:01.278382
11025 12:49:01.278945
11026 12:49:01.281533 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11027 12:49:01.282104
11028 12:49:01.295508 debian-bullse<4>[ 19.186040] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11029 12:49:01.298209 ye-arm64 login: root (automatic login)
11030 12:49:01.298787
11031 12:49:01.299162
11032 12:49:01.308365 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Wed Jun 14 12:30:40 UTC 2023 aarch64
11033 12:49:01.308978
11034 12:49:01.315458 The programs included with the Debian GNU/Linux system are free software;
11035 12:49:01.321997 the exact distribution terms for each program are described in the
11036 12:49:01.325681 individual files in /usr/share/doc/*/copyright.
11037 12:49:01.326255
11038 12:49:01.331559 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11039 12:49:01.334863 permitted by applicable law.
11040 12:49:01.336255 Matched prompt #10: / #
11042 12:49:01.337429 Setting prompt string to ['/ #']
11043 12:49:01.337900 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11045 12:49:01.339059 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11046 12:49:01.339546 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11047 12:49:01.339934 Setting prompt string to ['/ #']
11048 12:49:01.340314 Forcing a shell prompt, looking for ['/ #']
11050 12:49:01.391335 / #
11051 12:49:01.391993 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11052 12:49:01.392610 Waiting using forced prompt support (timeout 00:02:30)
11053 12:49:01.398126
11054 12:49:01.402919 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11055 12:49:01.403598 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11056 12:49:01.404113 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11057 12:49:01.404648 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11058 12:49:01.405174 end: 2 depthcharge-action (duration 00:01:25) [common]
11059 12:49:01.405727 start: 3 lava-test-retry (timeout 00:08:16) [common]
11060 12:49:01.406204 start: 3.1 lava-test-shell (timeout 00:08:16) [common]
11061 12:49:01.406608 Using namespace: common
11063 12:49:01.507907 / # #
11064 12:49:01.508626 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11065 12:49:01.509369 <4>[ 19.308499] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11066 12:49:01.514950 #
11067 12:49:01.519626 Using /lava-10724916
11069 12:49:01.621097 / # export SHELL=/bin/sh
11070 12:49:01.621897 <3>[ 19.426231] mt7921e 0000:01:00.0: hardware init failed
11071 12:49:01.627709 export SHELL=/bin/sh
11073 12:49:01.729673 / # . /lava-10724916/environment
11074 12:49:01.730482 . /lava-10724916/environment<6>[ 19.603620] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
11075 12:49:01.731042 <6>[ 19.611604] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11076 12:49:01.736658
11078 12:49:01.838515 / # /lava-10724916/bin/lava-test-runner /lava-10724916/0
11079 12:49:01.839187 Test shell timeout: 10s (minimum of the action and connection timeout)
11080 12:49:01.844847 /lava-10724916/bin/lava-test-runner /lava-10724916/0
11081 12:49:01.867113 + export TESTRUN_ID=0_v4l2-compliance-uvc
11082 12:49:01.870099 + cd /lava-10724916/0/tests/0_v4l2-compliance-uvc
11083 12:49:01.870573 + cat uuid
11084 12:49:01.873364 + UUID=10724916_1.5.2.3.1
11085 12:49:01.873837 + set +x
11086 12:49:01.880641 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10724916_1.5.2.3.1>
11087 12:49:01.881522 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10724916_1.5.2.3.1
11088 12:49:01.881937 Starting test lava.0_v4l2-compliance-uvc (10724916_1.5.2.3.1)
11089 12:49:01.882382 Skipping test definition patterns.
11090 12:49:01.883146 + /usr/bin/v4l2-parser.sh -d uvcvideo
11091 12:49:01.889868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11092 12:49:01.890338 device: /dev/video1
11093 12:49:01.890987 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11095 12:49:05.943279 <4>[ 23.843151] ------------[ cut here ]------------
11096 12:49:05.950353 <4>[ 23.848082] get_vaddr_frames() cannot follow VM_IO mapping
11097 12:49:05.962624 <4>[ 23.848228] WARNING: CPU: 1 PID: 306 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11098 12:49:06.009835 <4>[ 23.866332] Modules linked in: btusb btintel btmtk btrtl mt7921e btbcm mt7921_common mt76_connac_lib mt76 mac80211 mtk_vcodec_enc mtk_vcodec_common uvcvideo mtk_vpu libarc4 v4l2_mem2mem r8153_ecm videobuf2_vmalloc videobuf2_dma_contig cdc_ether videobuf2_memops videobuf2_v4l2 cfg80211 bluetooth videobuf2_common usbnet ecdh_generic cros_ec_rpmsg ecc videodev cros_ec_chardev r8152 crct10dif_ce rfkill mc elants_i2c sbs_battery hid_google_hammer elan_i2c cros_ec_typec pcie_mediatek_gen3 hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11099 12:49:06.019740 <4>[ 23.915717] CPU: 1 PID: 306 Comm: v4l2-compliance Not tainted 6.1.31 #1
11100 12:49:06.022430 <4>[ 23.922580] Hardware name: Google Spherion (rev0 - 3) (DT)
11101 12:49:06.029362 <4>[ 23.928315] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11102 12:49:06.035977 <4>[ 23.935526] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11103 12:49:06.042198 <4>[ 23.941618] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11104 12:49:06.045473 <4>[ 23.947709] sp : ffff8000091a3810
11105 12:49:06.052986 <4>[ 23.951272] x29: ffff8000091a3810 x28: ffffdbb6e69da000 x27: ffffdbb6e69d6238
11106 12:49:06.062402 <4>[ 23.958659] x26: 0000000000000000 x25: ffffdbb6e69da4c0 x24: ffff04b74bb60538
11107 12:49:06.068643 <4>[ 23.966046] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11108 12:49:06.075452 <4>[ 23.973433] x20: 00000000fffffff2 x19: ffff04b74eb0d000 x18: fffffffffffe9a08
11109 12:49:06.081592 <4>[ 23.980821] x17: 0000000000000000 x16: ffffdbb70528bb60 x15: 0000000000000038
11110 12:49:06.091527 <4>[ 23.988208] x14: ffffdbb707b834a8 x13: 000000000000066f x12: 0000000000000225
11111 12:49:06.098446 <4>[ 23.995594] x11: fffffffffffe9a08 x10: fffffffffffe99d0 x9 : 00000000fffff225
11112 12:49:06.105393 <4>[ 24.002980] x8 : ffffdbb707b834a8 x7 : ffffdbb707bdb4a8 x6 : 00000000000019bc
11113 12:49:06.111672 <4>[ 24.010366] x5 : ffff04b87ef29a18 x4 : 00000000fffff225 x3 : ffff290177a66000
11114 12:49:06.121357 <4>[ 24.017752] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff04b74eae49c0
11115 12:49:06.121927 <4>[ 24.025139] Call trace:
11116 12:49:06.128615 <4>[ 24.027836] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11117 12:49:06.134513 <4>[ 24.033580] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11118 12:49:06.141508 <4>[ 24.039582] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11119 12:49:06.147941 <4>[ 24.046104] __prepare_userptr+0x280/0x410 [videobuf2_common]
11120 12:49:06.151165 <4>[ 24.052107] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11121 12:49:06.158372 <4>[ 24.057762] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11122 12:49:06.164900 <4>[ 24.063418] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11123 12:49:06.167894 <4>[ 24.068312] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11124 12:49:06.174751 <4>[ 24.073375] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11125 12:49:06.177673 <4>[ 24.078250] v4l_qbuf+0x48/0x60 [videodev]
11126 12:49:06.184267 <4>[ 24.082670] __video_do_ioctl+0x184/0x3d0 [videodev]
11127 12:49:06.187353 <4>[ 24.087914] video_usercopy+0x358/0x680 [videodev]
11128 12:49:06.194734 <4>[ 24.092985] video_ioctl2+0x18/0x30 [videodev]
11129 12:49:06.197715 <4>[ 24.097708] v4l2_ioctl+0x40/0x60 [videodev]
11130 12:49:06.200807 <4>[ 24.102258] __arm64_sys_ioctl+0xa8/0xf0
11131 12:49:06.204652 <4>[ 24.106440] invoke_syscall+0x48/0x114
11132 12:49:06.211079 <4>[ 24.110445] el0_svc_common.constprop.0+0x44/0xec
11133 12:49:06.214471 <4>[ 24.115400] do_el0_svc+0x2c/0xd0
11134 12:49:06.217139 <4>[ 24.118965] el0_svc+0x2c/0x84
11135 12:49:06.220930 <4>[ 24.122277] el0t_64_sync_handler+0xb8/0xc0
11136 12:49:06.227299 <4>[ 24.126710] el0t_64_sync+0x18c/0x190
11137 12:49:06.230541 <4>[ 24.130623] ---[ end trace 0000000000000000 ]---
11138 12:49:08.650284 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11139 12:49:08.660748 v4l2-compliance SHA: 57b6b2492f4a 2023-06-07 12:27:03
11140 12:49:08.666360
11141 12:49:08.679211 Compliance test for uvcvideo device /dev/video1:
11142 12:49:08.685333
11143 12:49:08.695556 Driver Info:
11144 12:49:08.705399 Driver name : uvcvideo
11145 12:49:08.718003 Card type : HD User Facing: HD User Facing
11146 12:49:08.727692 Bus info : usb-11200000.usb-1.4.1
11147 12:49:08.733553 Driver version : 6.1.31
11148 12:49:08.743358 Capabilities : 0x84a00001
11149 12:49:08.754886 Metadata Capture
11150 12:49:08.764666 Streaming
11151 12:49:08.774185 Extended Pix Format
11152 12:49:08.784065 Device Capabilities
11153 12:49:08.792971 Device Caps : 0x04200001
11154 12:49:08.805464 Streaming
11155 12:49:08.815511 Extended Pix Format
11156 12:49:08.824966 Media Driver Info:
11157 12:49:08.834124 Driver name : uvcvideo
11158 12:49:08.846689 Model : HD User Facing: HD User Facing
11159 12:49:08.853272 Serial : 200901010001
11160 12:49:08.866619 Bus info : usb-11200000.usb-1.4.1
11161 12:49:08.872888 Media version : 6.1.31
11162 12:49:08.885777 Hardware revision: 0x00009758 (38744)
11163 12:49:08.892674 Driver version : 6.1.31
11164 12:49:08.903797 Interface Info:
11165 12:49:08.917760 <LAVA_SIGNAL_TESTSET START Interface-Info>
11166 12:49:08.918326 ID : 0x03000002
11167 12:49:08.919029 Received signal: <TESTSET> START Interface-Info
11168 12:49:08.919436 Starting test_set Interface-Info
11169 12:49:08.928197 Type : V4L Video
11170 12:49:08.936965 Entity Info:
11171 12:49:08.942543 <LAVA_SIGNAL_TESTSET STOP>
11172 12:49:08.943385 Received signal: <TESTSET> STOP
11173 12:49:08.943981 Closing test_set Interface-Info
11174 12:49:08.952483 <LAVA_SIGNAL_TESTSET START Entity-Info>
11175 12:49:08.953364 Received signal: <TESTSET> START Entity-Info
11176 12:49:08.953764 Starting test_set Entity-Info
11177 12:49:08.955348 ID : 0x00000001 (1)
11178 12:49:08.965804 Name : HD User Facing: HD User Facing
11179 12:49:08.972641 Function : V4L2 I/O
11180 12:49:08.983735 Flags : default
11181 12:49:08.993699 Pad 0x01000007 : 0: Sink
11182 12:49:09.013316 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11183 12:49:09.013875
11184 12:49:09.023645 Required ioctls:
11185 12:49:09.031527 <LAVA_SIGNAL_TESTSET STOP>
11186 12:49:09.032365 Received signal: <TESTSET> STOP
11187 12:49:09.032793 Closing test_set Entity-Info
11188 12:49:09.040762 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11189 12:49:09.041770 Received signal: <TESTSET> START Required-ioctls
11190 12:49:09.042253 Starting test_set Required-ioctls
11191 12:49:09.043996 test MC information (see 'Media Driver Info' above): OK
11192 12:49:09.067986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11193 12:49:09.068849 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11195 12:49:09.071057 test VIDIOC_QUERYCAP: OK
11196 12:49:09.088066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11197 12:49:09.088917 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11199 12:49:09.091589 test invalid ioctls: OK
11200 12:49:09.111910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11201 12:49:09.112499
11202 12:49:09.113182 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11204 12:49:09.121628 Allow for multiple opens:
11205 12:49:09.127649 <LAVA_SIGNAL_TESTSET STOP>
11206 12:49:09.128482 Received signal: <TESTSET> STOP
11207 12:49:09.128909 Closing test_set Required-ioctls
11208 12:49:09.137248 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11209 12:49:09.138094 Received signal: <TESTSET> START Allow-for-multiple-opens
11210 12:49:09.138513 Starting test_set Allow-for-multiple-opens
11211 12:49:09.139983 test second /dev/video1 open: OK
11212 12:49:09.159986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video1-open RESULT=pass>
11213 12:49:09.160846 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video1-open RESULT=pass
11215 12:49:09.163113 test VIDIOC_QUERYCAP: OK
11216 12:49:09.184022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11217 12:49:09.184894 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11219 12:49:09.187424 test VIDIOC_G/S_PRIORITY: OK
11220 12:49:09.207372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11221 12:49:09.208206 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11223 12:49:09.210663 test for unlimited opens: OK
11224 12:49:09.231890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11225 12:49:09.232458
11226 12:49:09.233147 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11228 12:49:09.241352 Debug ioctls:
11229 12:49:09.248607 <LAVA_SIGNAL_TESTSET STOP>
11230 12:49:09.249444 Received signal: <TESTSET> STOP
11231 12:49:09.249841 Closing test_set Allow-for-multiple-opens
11232 12:49:09.258424 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11233 12:49:09.259259 Received signal: <TESTSET> START Debug-ioctls
11234 12:49:09.259665 Starting test_set Debug-ioctls
11235 12:49:09.261706 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11236 12:49:09.282681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11237 12:49:09.283492 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11239 12:49:09.289028 test VIDIOC_LOG_STATUS: OK (Not Supported)
11240 12:49:09.307764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11241 12:49:09.308347
11242 12:49:09.309099 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11244 12:49:09.318079 Input ioctls:
11245 12:49:09.325101 <LAVA_SIGNAL_TESTSET STOP>
11246 12:49:09.325933 Received signal: <TESTSET> STOP
11247 12:49:09.326327 Closing test_set Debug-ioctls
11248 12:49:09.333888 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11249 12:49:09.334724 Received signal: <TESTSET> START Input-ioctls
11250 12:49:09.335129 Starting test_set Input-ioctls
11251 12:49:09.337510 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11252 12:49:09.359951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11253 12:49:09.360835 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11255 12:49:09.363357 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11256 12:49:09.380919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11257 12:49:09.381760 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11259 12:49:09.387414 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11260 12:49:09.403687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11261 12:49:09.404593 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11263 12:49:09.410296 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11264 12:49:09.427869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11265 12:49:09.428681 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11267 12:49:09.431333 test VIDIOC_G/S/ENUMINPUT: OK
11268 12:49:09.451595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11269 12:49:09.452423 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11271 12:49:09.453909 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11272 12:49:09.475424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11273 12:49:09.476287 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11275 12:49:09.478176 Inputs: 1 Audio Inputs: 0 Tuners: 0
11276 12:49:09.486217
11277 12:49:09.501524 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11278 12:49:09.523006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11279 12:49:09.523843 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11281 12:49:09.529704 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11282 12:49:09.548011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11283 12:49:09.548881 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11285 12:49:09.554619 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11286 12:49:09.572017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11287 12:49:09.572886 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11289 12:49:09.578246 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11290 12:49:09.595856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11291 12:49:09.596694 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11293 12:49:09.602600 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11294 12:49:09.619087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11295 12:49:09.619690
11296 12:49:09.620318 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11298 12:49:09.637198 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11299 12:49:09.659134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11300 12:49:09.659972 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11302 12:49:09.665412 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11303 12:49:09.685984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11304 12:49:09.686861 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11306 12:49:09.689635 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11307 12:49:09.706797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11308 12:49:09.707625 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11310 12:49:09.709783 test VIDIOC_G/S_EDID: OK (Not Supported)
11311 12:49:09.731273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11312 12:49:09.731841
11313 12:49:09.732650 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11315 12:49:09.740605 Control ioctls (Input 0):
11316 12:49:09.746629 <LAVA_SIGNAL_TESTSET STOP>
11317 12:49:09.747462 Received signal: <TESTSET> STOP
11318 12:49:09.747849 Closing test_set Input-ioctls
11319 12:49:09.756582 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11320 12:49:09.757420 Received signal: <TESTSET> START Control-ioctls-Input-0
11321 12:49:09.757813 Starting test_set Control-ioctls-Input-0
11322 12:49:09.759389 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11323 12:49:09.782409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11324 12:49:09.782981 test VIDIOC_QUERYCTRL: OK
11325 12:49:09.783622 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11327 12:49:09.802960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11328 12:49:09.803839 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11330 12:49:09.805287 test VIDIOC_G/S_CTRL: OK
11331 12:49:09.825915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11332 12:49:09.826740 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11334 12:49:09.828690 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11335 12:49:09.848981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11336 12:49:09.849797 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11338 12:49:09.855490 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11339 12:49:09.874883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11340 12:49:09.875731 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11342 12:49:09.878568 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11343 12:49:09.895987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11344 12:49:09.896843 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11346 12:49:09.899345 Standard Controls: 16 Private Controls: 0
11347 12:49:09.906213
11348 12:49:09.916676 Format ioctls (Input 0):
11349 12:49:09.924036 <LAVA_SIGNAL_TESTSET STOP>
11350 12:49:09.924904 Received signal: <TESTSET> STOP
11351 12:49:09.925301 Closing test_set Control-ioctls-Input-0
11352 12:49:09.932160 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11353 12:49:09.933039 Received signal: <TESTSET> START Format-ioctls-Input-0
11354 12:49:09.933440 Starting test_set Format-ioctls-Input-0
11355 12:49:09.935811 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11356 12:49:09.960159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11357 12:49:09.961014 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11359 12:49:09.962900 test VIDIOC_G/S_PARM: OK
11360 12:49:09.980260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11361 12:49:09.981135 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11363 12:49:09.982794 test VIDIOC_G_FBUF: OK (Not Supported)
11364 12:49:10.004106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11365 12:49:10.004979 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11367 12:49:10.007343 test VIDIOC_G_FMT: OK
11368 12:49:10.028023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11369 12:49:10.028923 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11371 12:49:10.031656 test VIDIOC_TRY_FMT: OK
11372 12:49:10.051055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11373 12:49:10.051898 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11375 12:49:10.057963 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11376 12:49:10.061557 test VIDIOC_S_FMT: OK
11377 12:49:10.086270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11378 12:49:10.087168 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11380 12:49:10.089065 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11381 12:49:10.111289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11382 12:49:10.112116 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11384 12:49:10.114183 test Cropping: OK (Not Supported)
11385 12:49:10.135463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11386 12:49:10.136291 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11388 12:49:10.138885 test Composing: OK (Not Supported)
11389 12:49:10.159952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11390 12:49:10.160924 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11392 12:49:10.162595 test Scaling: OK (Not Supported)
11393 12:49:10.183439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11394 12:49:10.184007
11395 12:49:10.184652 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11397 12:49:10.193644 Codec ioctls (Input 0):
11398 12:49:10.201193 <LAVA_SIGNAL_TESTSET STOP>
11399 12:49:10.202039 Received signal: <TESTSET> STOP
11400 12:49:10.202451 Closing test_set Format-ioctls-Input-0
11401 12:49:10.209887 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11402 12:49:10.210726 Received signal: <TESTSET> START Codec-ioctls-Input-0
11403 12:49:10.211213 Starting test_set Codec-ioctls-Input-0
11404 12:49:10.213751 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11405 12:49:10.235944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11406 12:49:10.236818 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11408 12:49:10.241578 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11409 12:49:10.259878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11410 12:49:10.260695 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11412 12:49:10.266956 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11413 12:49:10.284486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11414 12:49:10.285099
11415 12:49:10.285737 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11417 12:49:10.294262 Buffer ioctls (Input 0):
11418 12:49:10.301216 <LAVA_SIGNAL_TESTSET STOP>
11419 12:49:10.302048 Received signal: <TESTSET> STOP
11420 12:49:10.302435 Closing test_set Codec-ioctls-Input-0
11421 12:49:10.310110 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11422 12:49:10.310952 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11423 12:49:10.311345 Starting test_set Buffer-ioctls-Input-0
11424 12:49:10.313875 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11425 12:49:10.336980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11426 12:49:10.337551 test VIDIOC_EXPBUF: OK
11427 12:49:10.338191 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11429 12:49:10.358299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11430 12:49:10.359138 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11432 12:49:10.361559 test Requests: OK (Not Supported)
11433 12:49:10.383632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11434 12:49:10.384200
11435 12:49:10.384889 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11437 12:49:10.394056 Test input 0:
11438 12:49:10.403397
11439 12:49:10.414185 Streaming ioctls:
11440 12:49:10.421220 <LAVA_SIGNAL_TESTSET STOP>
11441 12:49:10.422051 Received signal: <TESTSET> STOP
11442 12:49:10.422440 Closing test_set Buffer-ioctls-Input-0
11443 12:49:10.429699 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11444 12:49:10.430539 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11445 12:49:10.430935 Starting test_set Streaming-ioctls_Test-input-0
11446 12:49:10.433428 test read/write: OK (Not Supported)
11447 12:49:10.454345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11448 12:49:10.455193 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11450 12:49:10.457246 test blocking wait: OK
11451 12:49:10.478664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11452 12:49:10.479494 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11454 12:49:10.488323 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11455 12:49:10.489060 test MMAP (no poll): FAIL
11456 12:49:10.511605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11457 12:49:10.512423 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11459 12:49:10.521584 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11460 12:49:10.525028 test MMAP (select): FAIL
11461 12:49:10.547370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11462 12:49:10.548192 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11464 12:49:10.557713 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11465 12:49:10.558316 test MMAP (epoll): FAIL
11466 12:49:10.583894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11467 12:49:10.584445
11468 12:49:10.585123 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11470 12:49:10.596352
11471 12:49:10.778544
11472 12:49:10.785317 test USERPTR (no poll): OK
11473 12:49:10.810467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11474 12:49:10.811021
11475 12:49:10.811692 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11477 12:49:10.823738
11478 12:49:10.990938
11479 12:49:10.997013 test USERPTR (select): OK
11480 12:49:11.020966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11481 12:49:11.021768 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11483 12:49:11.027380 test DMABUF: Cannot test, specify --expbuf-device
11484 12:49:11.031593
11485 12:49:11.049803 Total for uvcvideo device /dev/video1: 53, Succeeded: 50, Failed: 3, Warnings: 3
11486 12:49:11.053010 <LAVA_TEST_RUNNER EXIT>
11487 12:49:11.053732 ok: lava_test_shell seems to have completed
11488 12:49:11.054134 Marking unfinished test run as failed
11490 12:49:11.059334 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video1-open:
result: pass
set: Allow-for-multiple-opens
11491 12:49:11.059991 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11492 12:49:11.060464 end: 3 lava-test-retry (duration 00:00:10) [common]
11493 12:49:11.060953 start: 4 finalize (timeout 00:08:07) [common]
11494 12:49:11.061423 start: 4.1 power-off (timeout 00:00:30) [common]
11495 12:49:11.062240 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11496 12:49:11.150199 >> Command sent successfully.
11497 12:49:11.155131 Returned 0 in 0 seconds
11498 12:49:11.256186 end: 4.1 power-off (duration 00:00:00) [common]
11500 12:49:11.257774 start: 4.2 read-feedback (timeout 00:08:06) [common]
11501 12:49:11.259064 Listened to connection for namespace 'common' for up to 1s
11502 12:49:12.259673 Finalising connection for namespace 'common'
11503 12:49:12.260641 Disconnecting from shell: Finalise
11504 12:49:12.261106 / #
11505 12:49:12.362107 end: 4.2 read-feedback (duration 00:00:01) [common]
11506 12:49:12.362814 end: 4 finalize (duration 00:00:01) [common]
11507 12:49:12.363444 Cleaning after the job
11508 12:49:12.363940 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/ramdisk
11509 12:49:12.385178 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/kernel
11510 12:49:12.414973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/dtb
11511 12:49:12.415279 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10724916/tftp-deploy-8qwfh__e/modules
11512 12:49:12.422790 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10724916
11513 12:49:12.478213 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10724916
11514 12:49:12.478397 Job finished correctly