Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 27
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 23
- Errors: 2
1 11:39:50.520085 lava-dispatcher, installed at version: 2023.05.1
2 11:39:50.520303 start: 0 validate
3 11:39:50.520439 Start time: 2023-06-15 11:39:50.520431+00:00 (UTC)
4 11:39:50.520575 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:39:50.520705 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 11:39:50.793802 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:39:50.793999 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:40:18.571308 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:40:18.572011 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:40:18.826907 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:40:18.827587 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:40:21.084804 validate duration: 30.56
14 11:40:21.085964 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:40:21.086472 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:40:21.086939 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:40:21.087522 Not decompressing ramdisk as can be used compressed.
18 11:40:21.087966 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230609.0/arm64/rootfs.cpio.gz
19 11:40:21.088365 saving as /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/ramdisk/rootfs.cpio.gz
20 11:40:21.088690 total size: 8200575 (7MB)
21 11:40:21.349863 progress 0% (0MB)
22 11:40:21.352276 progress 5% (0MB)
23 11:40:21.354680 progress 10% (0MB)
24 11:40:21.356805 progress 15% (1MB)
25 11:40:21.359134 progress 20% (1MB)
26 11:40:21.361218 progress 25% (1MB)
27 11:40:21.363451 progress 30% (2MB)
28 11:40:21.365569 progress 35% (2MB)
29 11:40:21.367753 progress 40% (3MB)
30 11:40:21.369828 progress 45% (3MB)
31 11:40:21.372013 progress 50% (3MB)
32 11:40:21.374158 progress 55% (4MB)
33 11:40:21.376367 progress 60% (4MB)
34 11:40:21.378355 progress 65% (5MB)
35 11:40:21.380557 progress 70% (5MB)
36 11:40:21.382636 progress 75% (5MB)
37 11:40:21.384913 progress 80% (6MB)
38 11:40:21.386909 progress 85% (6MB)
39 11:40:21.389110 progress 90% (7MB)
40 11:40:21.391098 progress 95% (7MB)
41 11:40:21.393309 progress 100% (7MB)
42 11:40:21.393446 7MB downloaded in 0.30s (25.66MB/s)
43 11:40:21.393599 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:40:21.393835 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:40:21.393921 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:40:21.394006 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:40:21.394138 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:40:21.394207 saving as /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/kernel/Image
50 11:40:21.394268 total size: 47581696 (45MB)
51 11:40:21.394327 No compression specified
52 11:40:21.395429 progress 0% (0MB)
53 11:40:21.407483 progress 5% (2MB)
54 11:40:21.419436 progress 10% (4MB)
55 11:40:21.431265 progress 15% (6MB)
56 11:40:21.443380 progress 20% (9MB)
57 11:40:21.455518 progress 25% (11MB)
58 11:40:21.467434 progress 30% (13MB)
59 11:40:21.479420 progress 35% (15MB)
60 11:40:21.491467 progress 40% (18MB)
61 11:40:21.503774 progress 45% (20MB)
62 11:40:21.515766 progress 50% (22MB)
63 11:40:21.527603 progress 55% (24MB)
64 11:40:21.539544 progress 60% (27MB)
65 11:40:21.551296 progress 65% (29MB)
66 11:40:21.563554 progress 70% (31MB)
67 11:40:21.575606 progress 75% (34MB)
68 11:40:21.587561 progress 80% (36MB)
69 11:40:21.599785 progress 85% (38MB)
70 11:40:21.611870 progress 90% (40MB)
71 11:40:21.623712 progress 95% (43MB)
72 11:40:21.635466 progress 100% (45MB)
73 11:40:21.635618 45MB downloaded in 0.24s (188.02MB/s)
74 11:40:21.635773 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:40:21.636007 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:40:21.636106 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:40:21.636194 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:40:21.636333 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:40:21.636403 saving as /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/dtb/mt8192-asurada-spherion-r0.dtb
81 11:40:21.636466 total size: 46924 (0MB)
82 11:40:21.636527 No compression specified
83 11:40:21.637643 progress 69% (0MB)
84 11:40:21.637912 progress 100% (0MB)
85 11:40:21.638066 0MB downloaded in 0.00s (28.00MB/s)
86 11:40:21.638189 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:40:21.638411 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:40:21.638497 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:40:21.638579 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:40:21.638689 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:40:21.638757 saving as /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/modules/modules.tar
93 11:40:21.638818 total size: 8555256 (8MB)
94 11:40:21.638879 Using unxz to decompress xz
95 11:40:21.642304 progress 0% (0MB)
96 11:40:21.664475 progress 5% (0MB)
97 11:40:21.689328 progress 10% (0MB)
98 11:40:21.714598 progress 15% (1MB)
99 11:40:21.739786 progress 20% (1MB)
100 11:40:21.764226 progress 25% (2MB)
101 11:40:21.787116 progress 30% (2MB)
102 11:40:21.812878 progress 35% (2MB)
103 11:40:21.837342 progress 40% (3MB)
104 11:40:21.860698 progress 45% (3MB)
105 11:40:21.887989 progress 50% (4MB)
106 11:40:21.912890 progress 55% (4MB)
107 11:40:21.938292 progress 60% (4MB)
108 11:40:21.963651 progress 65% (5MB)
109 11:40:21.988821 progress 70% (5MB)
110 11:40:22.012853 progress 75% (6MB)
111 11:40:22.036041 progress 80% (6MB)
112 11:40:22.059817 progress 85% (6MB)
113 11:40:22.088774 progress 90% (7MB)
114 11:40:22.115938 progress 95% (7MB)
115 11:40:22.140764 progress 100% (8MB)
116 11:40:22.145048 8MB downloaded in 0.51s (16.12MB/s)
117 11:40:22.145328 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:40:22.145591 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:40:22.145684 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:40:22.145780 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:40:22.145861 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:40:22.145945 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:40:22.146162 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs
125 11:40:22.146342 makedir: /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin
126 11:40:22.146459 makedir: /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/tests
127 11:40:22.146555 makedir: /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/results
128 11:40:22.146667 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-add-keys
129 11:40:22.146805 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-add-sources
130 11:40:22.146932 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-background-process-start
131 11:40:22.147056 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-background-process-stop
132 11:40:22.147175 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-common-functions
133 11:40:22.147297 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-echo-ipv4
134 11:40:22.147419 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-install-packages
135 11:40:22.147537 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-installed-packages
136 11:40:22.147654 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-os-build
137 11:40:22.147772 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-probe-channel
138 11:40:22.147889 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-probe-ip
139 11:40:22.148007 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-target-ip
140 11:40:22.148163 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-target-mac
141 11:40:22.148280 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-target-storage
142 11:40:22.148401 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-test-case
143 11:40:22.148519 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-test-event
144 11:40:22.148635 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-test-feedback
145 11:40:22.148750 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-test-raise
146 11:40:22.148869 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-test-reference
147 11:40:22.148986 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-test-runner
148 11:40:22.149102 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-test-set
149 11:40:22.149221 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-test-shell
150 11:40:22.149345 Updating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-install-packages (oe)
151 11:40:22.149532 Updating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/bin/lava-installed-packages (oe)
152 11:40:22.149683 Creating /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/environment
153 11:40:22.149783 LAVA metadata
154 11:40:22.149854 - LAVA_JOB_ID=10742201
155 11:40:22.149919 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:40:22.150022 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:40:22.150087 skipped lava-vland-overlay
158 11:40:22.150160 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:40:22.150239 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:40:22.150299 skipped lava-multinode-overlay
161 11:40:22.150373 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:40:22.150451 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:40:22.150523 Loading test definitions
164 11:40:22.150611 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:40:22.150682 Using /lava-10742201 at stage 0
166 11:40:22.150980 uuid=10742201_1.5.2.3.1 testdef=None
167 11:40:22.151067 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:40:22.151151 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:40:22.151663 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:40:22.151885 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:40:22.152543 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:40:22.152772 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:40:22.153374 runner path: /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/0/tests/0_dmesg test_uuid 10742201_1.5.2.3.1
176 11:40:22.153571 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:40:22.153839 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 11:40:22.153909 Using /lava-10742201 at stage 1
180 11:40:22.154195 uuid=10742201_1.5.2.3.5 testdef=None
181 11:40:22.154282 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 11:40:22.154365 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 11:40:22.154823 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 11:40:22.155042 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 11:40:22.156169 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 11:40:22.156399 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 11:40:22.157007 runner path: /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/1/tests/1_bootrr test_uuid 10742201_1.5.2.3.5
190 11:40:22.157156 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 11:40:22.157364 Creating lava-test-runner.conf files
193 11:40:22.157428 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/0 for stage 0
194 11:40:22.157516 - 0_dmesg
195 11:40:22.157595 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742201/lava-overlay-513qjvhs/lava-10742201/1 for stage 1
196 11:40:22.157684 - 1_bootrr
197 11:40:22.157775 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 11:40:22.157857 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 11:40:22.165689 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 11:40:22.165802 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 11:40:22.165889 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 11:40:22.165974 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 11:40:22.166059 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 11:40:22.400170 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 11:40:22.400539 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 11:40:22.400694 extracting modules file /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742201/extract-overlay-ramdisk-7x2yl908/ramdisk
207 11:40:22.608881 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 11:40:22.609042 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 11:40:22.609141 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742201/compress-overlay-rbplssjt/overlay-1.5.2.4.tar.gz to ramdisk
210 11:40:22.609211 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742201/compress-overlay-rbplssjt/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742201/extract-overlay-ramdisk-7x2yl908/ramdisk
211 11:40:22.617480 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 11:40:22.617595 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 11:40:22.617685 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 11:40:22.617773 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 11:40:22.617852 Building ramdisk /var/lib/lava/dispatcher/tmp/10742201/extract-overlay-ramdisk-7x2yl908/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742201/extract-overlay-ramdisk-7x2yl908/ramdisk
216 11:40:22.949475 >> 143719 blocks
217 11:40:25.190669 rename /var/lib/lava/dispatcher/tmp/10742201/extract-overlay-ramdisk-7x2yl908/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/ramdisk/ramdisk.cpio.gz
218 11:40:25.191097 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 11:40:25.191225 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 11:40:25.191327 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 11:40:25.191433 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/kernel/Image'
222 11:40:37.815411 Returned 0 in 12 seconds
223 11:40:37.916315 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/kernel/image.itb
224 11:40:38.277601 output: FIT description: Kernel Image image with one or more FDT blobs
225 11:40:38.277952 output: Created: Thu Jun 15 12:40:38 2023
226 11:40:38.278027 output: Image 0 (kernel-1)
227 11:40:38.278093 output: Description:
228 11:40:38.278156 output: Created: Thu Jun 15 12:40:38 2023
229 11:40:38.278217 output: Type: Kernel Image
230 11:40:38.278275 output: Compression: lzma compressed
231 11:40:38.278336 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
232 11:40:38.278399 output: Architecture: AArch64
233 11:40:38.278469 output: OS: Linux
234 11:40:38.278531 output: Load Address: 0x00000000
235 11:40:38.278590 output: Entry Point: 0x00000000
236 11:40:38.278649 output: Hash algo: crc32
237 11:40:38.278708 output: Hash value: cd22d0e5
238 11:40:38.278761 output: Image 1 (fdt-1)
239 11:40:38.278815 output: Description: mt8192-asurada-spherion-r0
240 11:40:38.278868 output: Created: Thu Jun 15 12:40:38 2023
241 11:40:38.278922 output: Type: Flat Device Tree
242 11:40:38.278975 output: Compression: uncompressed
243 11:40:38.279028 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 11:40:38.279082 output: Architecture: AArch64
245 11:40:38.279134 output: Hash algo: crc32
246 11:40:38.279186 output: Hash value: 1df858fa
247 11:40:38.279239 output: Image 2 (ramdisk-1)
248 11:40:38.279291 output: Description: unavailable
249 11:40:38.279343 output: Created: Thu Jun 15 12:40:38 2023
250 11:40:38.279396 output: Type: RAMDisk Image
251 11:40:38.279449 output: Compression: Unknown Compression
252 11:40:38.279501 output: Data Size: 21230103 Bytes = 20732.52 KiB = 20.25 MiB
253 11:40:38.279554 output: Architecture: AArch64
254 11:40:38.279606 output: OS: Linux
255 11:40:38.279659 output: Load Address: unavailable
256 11:40:38.279712 output: Entry Point: unavailable
257 11:40:38.279764 output: Hash algo: crc32
258 11:40:38.279816 output: Hash value: 9876ebd4
259 11:40:38.279869 output: Default Configuration: 'conf-1'
260 11:40:38.279921 output: Configuration 0 (conf-1)
261 11:40:38.279975 output: Description: mt8192-asurada-spherion-r0
262 11:40:38.280027 output: Kernel: kernel-1
263 11:40:38.280120 output: Init Ramdisk: ramdisk-1
264 11:40:38.280173 output: FDT: fdt-1
265 11:40:38.280225 output: Loadables: kernel-1
266 11:40:38.280277 output:
267 11:40:38.280464 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 11:40:38.280562 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 11:40:38.280668 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 11:40:38.280757 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 11:40:38.280835 No LXC device requested
272 11:40:38.280913 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 11:40:38.280998 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 11:40:38.281077 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 11:40:38.281156 Checking files for TFTP limit of 4294967296 bytes.
276 11:40:38.281648 end: 1 tftp-deploy (duration 00:00:17) [common]
277 11:40:38.281761 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 11:40:38.281848 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 11:40:38.281978 substitutions:
280 11:40:38.282044 - {DTB}: 10742201/tftp-deploy-nwrhfab6/dtb/mt8192-asurada-spherion-r0.dtb
281 11:40:38.282109 - {INITRD}: 10742201/tftp-deploy-nwrhfab6/ramdisk/ramdisk.cpio.gz
282 11:40:38.282168 - {KERNEL}: 10742201/tftp-deploy-nwrhfab6/kernel/Image
283 11:40:38.282225 - {LAVA_MAC}: None
284 11:40:38.282280 - {PRESEED_CONFIG}: None
285 11:40:38.282335 - {PRESEED_LOCAL}: None
286 11:40:38.282390 - {RAMDISK}: 10742201/tftp-deploy-nwrhfab6/ramdisk/ramdisk.cpio.gz
287 11:40:38.282455 - {ROOT_PART}: None
288 11:40:38.282521 - {ROOT}: None
289 11:40:38.282607 - {SERVER_IP}: 192.168.201.1
290 11:40:38.282664 - {TEE}: None
291 11:40:38.282719 Parsed boot commands:
292 11:40:38.282773 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 11:40:38.282941 Parsed boot commands: tftpboot 192.168.201.1 10742201/tftp-deploy-nwrhfab6/kernel/image.itb 10742201/tftp-deploy-nwrhfab6/kernel/cmdline
294 11:40:38.283030 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 11:40:38.283112 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 11:40:38.283205 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 11:40:38.283292 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 11:40:38.283359 Not connected, no need to disconnect.
299 11:40:38.283432 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 11:40:38.283512 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 11:40:38.283579 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
302 11:40:38.287266 Setting prompt string to ['lava-test: # ']
303 11:40:38.287802 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 11:40:38.287903 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 11:40:38.287997 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 11:40:38.288139 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 11:40:38.288345 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
308 11:40:43.419014 >> Command sent successfully.
309 11:40:43.421385 Returned 0 in 5 seconds
310 11:40:43.521805 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 11:40:43.522173 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 11:40:43.522273 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 11:40:43.522365 Setting prompt string to 'Starting depthcharge on Spherion...'
315 11:40:43.522436 Changing prompt to 'Starting depthcharge on Spherion...'
316 11:40:43.522506 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 11:40:43.522802 [Enter `^Ec?' for help]
318 11:40:43.698378
319 11:40:43.698551
320 11:40:43.698634 F0: 102B 0000
321 11:40:43.698701
322 11:40:43.698763 F3: 1001 0000 [0200]
323 11:40:43.701173
324 11:40:43.701259 F3: 1001 0000
325 11:40:43.701328
326 11:40:43.701392 F7: 102D 0000
327 11:40:43.701453
328 11:40:43.705302 F1: 0000 0000
329 11:40:43.705388
330 11:40:43.705456 V0: 0000 0000 [0001]
331 11:40:43.705525
332 11:40:43.708045 00: 0007 8000
333 11:40:43.708133
334 11:40:43.708202 01: 0000 0000
335 11:40:43.708267
336 11:40:43.711361 BP: 0C00 0209 [0000]
337 11:40:43.711446
338 11:40:43.711514 G0: 1182 0000
339 11:40:43.711578
340 11:40:43.715227 EC: 0000 0021 [4000]
341 11:40:43.715312
342 11:40:43.715381 S7: 0000 0000 [0000]
343 11:40:43.715445
344 11:40:43.718594 CC: 0000 0000 [0001]
345 11:40:43.718680
346 11:40:43.718749 T0: 0000 0040 [010F]
347 11:40:43.718813
348 11:40:43.718874 Jump to BL
349 11:40:43.721649
350 11:40:43.745190
351 11:40:43.745294
352 11:40:43.745365
353 11:40:43.752763 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 11:40:43.755941 ARM64: Exception handlers installed.
355 11:40:43.760263 ARM64: Testing exception
356 11:40:43.763301 ARM64: Done test exception
357 11:40:43.769689 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 11:40:43.779877 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 11:40:43.786645 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 11:40:43.796262 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 11:40:43.803844 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 11:40:43.809604 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 11:40:43.822617 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 11:40:43.828531 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 11:40:43.847995 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 11:40:43.851350 WDT: Last reset was cold boot
367 11:40:43.854406 SPI1(PAD0) initialized at 2873684 Hz
368 11:40:43.857870 SPI5(PAD0) initialized at 992727 Hz
369 11:40:43.861091 VBOOT: Loading verstage.
370 11:40:43.867765 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 11:40:43.871032 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 11:40:43.874544 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 11:40:43.877716 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 11:40:43.885680 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 11:40:43.891953 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 11:40:43.902589 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 11:40:43.902687
378 11:40:43.902761
379 11:40:43.912882 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 11:40:43.915967 ARM64: Exception handlers installed.
381 11:40:43.919713 ARM64: Testing exception
382 11:40:43.919795 ARM64: Done test exception
383 11:40:43.926772 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 11:40:43.930238 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 11:40:43.943686 Probing TPM: . done!
386 11:40:43.943777 TPM ready after 0 ms
387 11:40:43.950965 Connected to device vid:did:rid of 1ae0:0028:00
388 11:40:43.957989 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 11:40:44.016367 Initialized TPM device CR50 revision 0
390 11:40:44.027477 tlcl_send_startup: Startup return code is 0
391 11:40:44.027613 TPM: setup succeeded
392 11:40:44.038954 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 11:40:44.047764 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 11:40:44.060823 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 11:40:44.070446 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 11:40:44.073388 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 11:40:44.077759 in-header: 03 07 00 00 08 00 00 00
398 11:40:44.081216 in-data: aa e4 47 04 13 02 00 00
399 11:40:44.084888 Chrome EC: UHEPI supported
400 11:40:44.091906 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 11:40:44.095432 in-header: 03 95 00 00 08 00 00 00
402 11:40:44.099195 in-data: 18 20 20 08 00 00 00 00
403 11:40:44.099279 Phase 1
404 11:40:44.103334 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 11:40:44.110888 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 11:40:44.114293 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 11:40:44.117619 Recovery requested (1009000e)
408 11:40:44.126455 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 11:40:44.131381 tlcl_extend: response is 0
410 11:40:44.140841 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 11:40:44.146404 tlcl_extend: response is 0
412 11:40:44.153318 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 11:40:44.173517 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 11:40:44.180021 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 11:40:44.180110
416 11:40:44.180178
417 11:40:44.189858 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 11:40:44.193367 ARM64: Exception handlers installed.
419 11:40:44.196643 ARM64: Testing exception
420 11:40:44.196771 ARM64: Done test exception
421 11:40:44.218803 pmic_efuse_setting: Set efuses in 11 msecs
422 11:40:44.222192 pmwrap_interface_init: Select PMIF_VLD_RDY
423 11:40:44.228657 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 11:40:44.232424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 11:40:44.239072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 11:40:44.242537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 11:40:44.246170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 11:40:44.254005 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 11:40:44.257465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 11:40:44.261080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 11:40:44.264960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 11:40:44.272072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 11:40:44.275862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 11:40:44.279600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 11:40:44.283667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 11:40:44.291186 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 11:40:44.298546 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 11:40:44.302323 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 11:40:44.309650 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 11:40:44.313438 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 11:40:44.320801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 11:40:44.325158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 11:40:44.332353 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 11:40:44.336046 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 11:40:44.343471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 11:40:44.347184 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 11:40:44.350816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 11:40:44.358358 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 11:40:44.361801 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 11:40:44.369274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 11:40:44.372194 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 11:40:44.376309 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 11:40:44.383667 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 11:40:44.386902 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 11:40:44.393961 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 11:40:44.398065 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 11:40:44.401593 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 11:40:44.408831 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 11:40:44.412916 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 11:40:44.416141 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 11:40:44.423613 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 11:40:44.427076 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 11:40:44.430686 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 11:40:44.434845 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 11:40:44.441450 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 11:40:44.444973 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 11:40:44.449268 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 11:40:44.452787 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 11:40:44.456254 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 11:40:44.459850 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 11:40:44.466608 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 11:40:44.470592 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 11:40:44.474144 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 11:40:44.481412 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 11:40:44.489298 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 11:40:44.495972 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 11:40:44.503662 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 11:40:44.510550 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 11:40:44.518154 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 11:40:44.521849 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 11:40:44.524989 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 11:40:44.532300 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x24
483 11:40:44.535666 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 11:40:44.543951 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
485 11:40:44.547376 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 11:40:44.556607 [RTC]rtc_get_frequency_meter,154: input=15, output=851
487 11:40:44.566029 [RTC]rtc_get_frequency_meter,154: input=7, output=723
488 11:40:44.575573 [RTC]rtc_get_frequency_meter,154: input=11, output=789
489 11:40:44.584898 [RTC]rtc_get_frequency_meter,154: input=13, output=819
490 11:40:44.594627 [RTC]rtc_get_frequency_meter,154: input=12, output=804
491 11:40:44.603785 [RTC]rtc_get_frequency_meter,154: input=11, output=787
492 11:40:44.613959 [RTC]rtc_get_frequency_meter,154: input=12, output=803
493 11:40:44.617539 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
494 11:40:44.621358 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
495 11:40:44.624712 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 11:40:44.632274 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 11:40:44.636289 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 11:40:44.639953 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 11:40:44.644382 ADC[4]: Raw value=905172 ID=7
500 11:40:44.644465 ADC[3]: Raw value=213546 ID=1
501 11:40:44.648096 RAM Code: 0x71
502 11:40:44.651048 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 11:40:44.654681 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 11:40:44.665780 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 11:40:44.669508 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 11:40:44.673000 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 11:40:44.677162 in-header: 03 07 00 00 08 00 00 00
508 11:40:44.680785 in-data: aa e4 47 04 13 02 00 00
509 11:40:44.684895 Chrome EC: UHEPI supported
510 11:40:44.691671 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 11:40:44.695277 in-header: 03 95 00 00 08 00 00 00
512 11:40:44.699114 in-data: 18 20 20 08 00 00 00 00
513 11:40:44.702307 MRC: failed to locate region type 0.
514 11:40:44.710180 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 11:40:44.710261 DRAM-K: Running full calibration
516 11:40:44.717054 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 11:40:44.721031 header.status = 0x0
518 11:40:44.721115 header.version = 0x6 (expected: 0x6)
519 11:40:44.724548 header.size = 0xd00 (expected: 0xd00)
520 11:40:44.728140 header.flags = 0x0
521 11:40:44.734715 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 11:40:44.752097 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
523 11:40:44.759489 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 11:40:44.762741 dram_init: ddr_geometry: 2
525 11:40:44.762827 [EMI] MDL number = 2
526 11:40:44.766773 [EMI] Get MDL freq = 0
527 11:40:44.766859 dram_init: ddr_type: 0
528 11:40:44.770159 is_discrete_lpddr4: 1
529 11:40:44.773762 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 11:40:44.773900
531 11:40:44.774029
532 11:40:44.774093 [Bian_co] ETT version 0.0.0.1
533 11:40:44.781273 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 11:40:44.781375
535 11:40:44.784947 dramc_set_vcore_voltage set vcore to 650000
536 11:40:44.785030 Read voltage for 800, 4
537 11:40:44.788886 Vio18 = 0
538 11:40:44.788996 Vcore = 650000
539 11:40:44.789091 Vdram = 0
540 11:40:44.789181 Vddq = 0
541 11:40:44.792671 Vmddr = 0
542 11:40:44.792754 dram_init: config_dvfs: 1
543 11:40:44.799807 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 11:40:44.803713 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 11:40:44.806712 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 11:40:44.813234 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 11:40:44.816244 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 11:40:44.819465 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 11:40:44.819549 MEM_TYPE=3, freq_sel=18
550 11:40:44.823371 sv_algorithm_assistance_LP4_1600
551 11:40:44.830741 ============ PULL DRAM RESETB DOWN ============
552 11:40:44.834295 ========== PULL DRAM RESETB DOWN end =========
553 11:40:44.837626 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 11:40:44.841502 ===================================
555 11:40:44.841586 LPDDR4 DRAM CONFIGURATION
556 11:40:44.845353 ===================================
557 11:40:44.848350 EX_ROW_EN[0] = 0x0
558 11:40:44.851613 EX_ROW_EN[1] = 0x0
559 11:40:44.851765 LP4Y_EN = 0x0
560 11:40:44.855564 WORK_FSP = 0x0
561 11:40:44.855703 WL = 0x2
562 11:40:44.858248 RL = 0x2
563 11:40:44.858353 BL = 0x2
564 11:40:44.861882 RPST = 0x0
565 11:40:44.861968 RD_PRE = 0x0
566 11:40:44.865161 WR_PRE = 0x1
567 11:40:44.865287 WR_PST = 0x0
568 11:40:44.868960 DBI_WR = 0x0
569 11:40:44.869066 DBI_RD = 0x0
570 11:40:44.871899 OTF = 0x1
571 11:40:44.875085 ===================================
572 11:40:44.878720 ===================================
573 11:40:44.878813 ANA top config
574 11:40:44.881764 ===================================
575 11:40:44.885120 DLL_ASYNC_EN = 0
576 11:40:44.888251 ALL_SLAVE_EN = 1
577 11:40:44.888321 NEW_RANK_MODE = 1
578 11:40:44.891880 DLL_IDLE_MODE = 1
579 11:40:44.895204 LP45_APHY_COMB_EN = 1
580 11:40:44.898576 TX_ODT_DIS = 1
581 11:40:44.901769 NEW_8X_MODE = 1
582 11:40:44.904889 ===================================
583 11:40:44.908321 ===================================
584 11:40:44.908393 data_rate = 1600
585 11:40:44.911567 CKR = 1
586 11:40:44.914851 DQ_P2S_RATIO = 8
587 11:40:44.918210 ===================================
588 11:40:44.921409 CA_P2S_RATIO = 8
589 11:40:44.925651 DQ_CA_OPEN = 0
590 11:40:44.925727 DQ_SEMI_OPEN = 0
591 11:40:44.928410 CA_SEMI_OPEN = 0
592 11:40:44.931506 CA_FULL_RATE = 0
593 11:40:44.935311 DQ_CKDIV4_EN = 1
594 11:40:44.938572 CA_CKDIV4_EN = 1
595 11:40:44.941500 CA_PREDIV_EN = 0
596 11:40:44.941577 PH8_DLY = 0
597 11:40:44.944925 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 11:40:44.948285 DQ_AAMCK_DIV = 4
599 11:40:44.951893 CA_AAMCK_DIV = 4
600 11:40:44.954717 CA_ADMCK_DIV = 4
601 11:40:44.958360 DQ_TRACK_CA_EN = 0
602 11:40:44.961761 CA_PICK = 800
603 11:40:44.961851 CA_MCKIO = 800
604 11:40:44.964868 MCKIO_SEMI = 0
605 11:40:44.968447 PLL_FREQ = 3068
606 11:40:44.972608 DQ_UI_PI_RATIO = 32
607 11:40:44.975976 CA_UI_PI_RATIO = 0
608 11:40:44.976086 ===================================
609 11:40:44.979657 ===================================
610 11:40:44.983854 memory_type:LPDDR4
611 11:40:44.987292 GP_NUM : 10
612 11:40:44.987382 SRAM_EN : 1
613 11:40:44.990836 MD32_EN : 0
614 11:40:44.990925 ===================================
615 11:40:44.994870 [ANA_INIT] >>>>>>>>>>>>>>
616 11:40:44.998273 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 11:40:45.001941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 11:40:45.005463 ===================================
619 11:40:45.008829 data_rate = 1600,PCW = 0X7600
620 11:40:45.011765 ===================================
621 11:40:45.015440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 11:40:45.018758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 11:40:45.025983 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 11:40:45.028880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 11:40:45.032362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 11:40:45.035330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 11:40:45.038754 [ANA_INIT] flow start
628 11:40:45.042341 [ANA_INIT] PLL >>>>>>>>
629 11:40:45.042427 [ANA_INIT] PLL <<<<<<<<
630 11:40:45.045244 [ANA_INIT] MIDPI >>>>>>>>
631 11:40:45.048645 [ANA_INIT] MIDPI <<<<<<<<
632 11:40:45.048732 [ANA_INIT] DLL >>>>>>>>
633 11:40:45.052485 [ANA_INIT] flow end
634 11:40:45.055129 ============ LP4 DIFF to SE enter ============
635 11:40:45.061984 ============ LP4 DIFF to SE exit ============
636 11:40:45.062073 [ANA_INIT] <<<<<<<<<<<<<
637 11:40:45.065120 [Flow] Enable top DCM control >>>>>
638 11:40:45.068247 [Flow] Enable top DCM control <<<<<
639 11:40:45.071968 Enable DLL master slave shuffle
640 11:40:45.078970 ==============================================================
641 11:40:45.079062 Gating Mode config
642 11:40:45.085559 ==============================================================
643 11:40:45.088502 Config description:
644 11:40:45.094943 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 11:40:45.101633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 11:40:45.108814 SELPH_MODE 0: By rank 1: By Phase
647 11:40:45.115241 ==============================================================
648 11:40:45.115351 GAT_TRACK_EN = 1
649 11:40:45.119193 RX_GATING_MODE = 2
650 11:40:45.121638 RX_GATING_TRACK_MODE = 2
651 11:40:45.125146 SELPH_MODE = 1
652 11:40:45.128692 PICG_EARLY_EN = 1
653 11:40:45.131594 VALID_LAT_VALUE = 1
654 11:40:45.138872 ==============================================================
655 11:40:45.141857 Enter into Gating configuration >>>>
656 11:40:45.145032 Exit from Gating configuration <<<<
657 11:40:45.148264 Enter into DVFS_PRE_config >>>>>
658 11:40:45.158107 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 11:40:45.161520 Exit from DVFS_PRE_config <<<<<
660 11:40:45.164926 Enter into PICG configuration >>>>
661 11:40:45.168140 Exit from PICG configuration <<<<
662 11:40:45.171612 [RX_INPUT] configuration >>>>>
663 11:40:45.171746 [RX_INPUT] configuration <<<<<
664 11:40:45.178241 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 11:40:45.184553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 11:40:45.191728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 11:40:45.194833 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 11:40:45.201020 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 11:40:45.207324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 11:40:45.211123 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 11:40:45.217771 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 11:40:45.221318 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 11:40:45.224744 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 11:40:45.227500 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 11:40:45.234120 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 11:40:45.237660 ===================================
677 11:40:45.237745 LPDDR4 DRAM CONFIGURATION
678 11:40:45.240845 ===================================
679 11:40:45.244121 EX_ROW_EN[0] = 0x0
680 11:40:45.247946 EX_ROW_EN[1] = 0x0
681 11:40:45.248050 LP4Y_EN = 0x0
682 11:40:45.250964 WORK_FSP = 0x0
683 11:40:45.251063 WL = 0x2
684 11:40:45.254255 RL = 0x2
685 11:40:45.254326 BL = 0x2
686 11:40:45.257731 RPST = 0x0
687 11:40:45.257800 RD_PRE = 0x0
688 11:40:45.260976 WR_PRE = 0x1
689 11:40:45.261050 WR_PST = 0x0
690 11:40:45.263970 DBI_WR = 0x0
691 11:40:45.264072 DBI_RD = 0x0
692 11:40:45.267640 OTF = 0x1
693 11:40:45.271091 ===================================
694 11:40:45.274002 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 11:40:45.277296 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 11:40:45.284028 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:40:45.287190 ===================================
698 11:40:45.287277 LPDDR4 DRAM CONFIGURATION
699 11:40:45.290745 ===================================
700 11:40:45.293726 EX_ROW_EN[0] = 0x10
701 11:40:45.297397 EX_ROW_EN[1] = 0x0
702 11:40:45.297476 LP4Y_EN = 0x0
703 11:40:45.300724 WORK_FSP = 0x0
704 11:40:45.300838 WL = 0x2
705 11:40:45.303918 RL = 0x2
706 11:40:45.303994 BL = 0x2
707 11:40:45.306713 RPST = 0x0
708 11:40:45.306789 RD_PRE = 0x0
709 11:40:45.310319 WR_PRE = 0x1
710 11:40:45.310417 WR_PST = 0x0
711 11:40:45.313566 DBI_WR = 0x0
712 11:40:45.313650 DBI_RD = 0x0
713 11:40:45.316845 OTF = 0x1
714 11:40:45.320336 ===================================
715 11:40:45.326884 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 11:40:45.330292 nWR fixed to 40
717 11:40:45.330377 [ModeRegInit_LP4] CH0 RK0
718 11:40:45.333896 [ModeRegInit_LP4] CH0 RK1
719 11:40:45.336869 [ModeRegInit_LP4] CH1 RK0
720 11:40:45.339901 [ModeRegInit_LP4] CH1 RK1
721 11:40:45.339985 match AC timing 13
722 11:40:45.343658 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 11:40:45.350463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 11:40:45.353646 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 11:40:45.360091 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 11:40:45.363312 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 11:40:45.363398 [EMI DOE] emi_dcm 0
728 11:40:45.370188 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 11:40:45.370272 ==
730 11:40:45.373563 Dram Type= 6, Freq= 0, CH_0, rank 0
731 11:40:45.376645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 11:40:45.376800 ==
733 11:40:45.383379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 11:40:45.387040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 11:40:45.396878 [CA 0] Center 38 (7~69) winsize 63
736 11:40:45.400627 [CA 1] Center 37 (6~68) winsize 63
737 11:40:45.404122 [CA 2] Center 34 (4~65) winsize 62
738 11:40:45.406750 [CA 3] Center 34 (4~65) winsize 62
739 11:40:45.410363 [CA 4] Center 33 (3~64) winsize 62
740 11:40:45.414262 [CA 5] Center 33 (3~64) winsize 62
741 11:40:45.414379
742 11:40:45.416931 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 11:40:45.417015
744 11:40:45.420389 [CATrainingPosCal] consider 1 rank data
745 11:40:45.423714 u2DelayCellTimex100 = 270/100 ps
746 11:40:45.426986 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
747 11:40:45.433272 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
748 11:40:45.436907 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 11:40:45.440372 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 11:40:45.443735 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 11:40:45.446804 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 11:40:45.446913
753 11:40:45.450510 CA PerBit enable=1, Macro0, CA PI delay=33
754 11:40:45.450593
755 11:40:45.453672 [CBTSetCACLKResult] CA Dly = 33
756 11:40:45.453755 CS Dly: 5 (0~36)
757 11:40:45.456644 ==
758 11:40:45.459795 Dram Type= 6, Freq= 0, CH_0, rank 1
759 11:40:45.463239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 11:40:45.463323 ==
761 11:40:45.466992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 11:40:45.473828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 11:40:45.483280 [CA 0] Center 38 (7~69) winsize 63
764 11:40:45.486889 [CA 1] Center 37 (7~68) winsize 62
765 11:40:45.489994 [CA 2] Center 35 (4~66) winsize 63
766 11:40:45.493122 [CA 3] Center 35 (4~66) winsize 63
767 11:40:45.496709 [CA 4] Center 34 (3~65) winsize 63
768 11:40:45.500199 [CA 5] Center 33 (3~64) winsize 62
769 11:40:45.500283
770 11:40:45.502953 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 11:40:45.503037
772 11:40:45.506397 [CATrainingPosCal] consider 2 rank data
773 11:40:45.510101 u2DelayCellTimex100 = 270/100 ps
774 11:40:45.513064 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
775 11:40:45.516579 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 11:40:45.522914 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 11:40:45.526594 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 11:40:45.529643 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 11:40:45.533480 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 11:40:45.533558
781 11:40:45.536479 CA PerBit enable=1, Macro0, CA PI delay=33
782 11:40:45.536552
783 11:40:45.539999 [CBTSetCACLKResult] CA Dly = 33
784 11:40:45.540094 CS Dly: 6 (0~38)
785 11:40:45.540156
786 11:40:45.543491 ----->DramcWriteLeveling(PI) begin...
787 11:40:45.546559 ==
788 11:40:45.546643 Dram Type= 6, Freq= 0, CH_0, rank 0
789 11:40:45.554203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 11:40:45.554288 ==
791 11:40:45.557930 Write leveling (Byte 0): 30 => 30
792 11:40:45.558015 Write leveling (Byte 1): 29 => 29
793 11:40:45.561463 DramcWriteLeveling(PI) end<-----
794 11:40:45.561580
795 11:40:45.561647 ==
796 11:40:45.565117 Dram Type= 6, Freq= 0, CH_0, rank 0
797 11:40:45.568164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 11:40:45.571834 ==
799 11:40:45.571918 [Gating] SW mode calibration
800 11:40:45.578712 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 11:40:45.585724 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 11:40:45.588636 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 11:40:45.591727 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 11:40:45.598793 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 11:40:45.601767 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:40:45.605625 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:40:45.612067 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:40:45.615084 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:40:45.618495 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:40:45.625077 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:40:45.628644 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:40:45.631891 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:40:45.638894 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:40:45.641615 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 11:40:45.645334 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:40:45.652028 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:40:45.654848 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:40:45.658897 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:40:45.665158 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 11:40:45.669034 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
821 11:40:45.671907 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:40:45.678186 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:40:45.681766 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:40:45.685181 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:40:45.691448 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:40:45.694669 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:40:45.698305 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:40:45.704769 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
829 11:40:45.708125 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
830 11:40:45.711821 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 11:40:45.718349 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 11:40:45.721664 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 11:40:45.724641 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 11:40:45.728200 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
835 11:40:45.735048 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
836 11:40:45.738034 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 1) (1 0)
837 11:40:45.741480 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
838 11:40:45.748186 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:40:45.751939 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:40:45.754678 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 11:40:45.761569 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 11:40:45.765514 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:40:45.768401 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
844 11:40:45.775042 0 11 8 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
845 11:40:45.778328 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
846 11:40:45.781370 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 11:40:45.787933 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 11:40:45.791544 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 11:40:45.794857 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:40:45.801372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 11:40:45.804443 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
852 11:40:45.808180 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 11:40:45.814575 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 11:40:45.817708 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 11:40:45.821085 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 11:40:45.827776 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 11:40:45.831368 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 11:40:45.834371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 11:40:45.841069 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 11:40:45.844207 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 11:40:45.847666 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 11:40:45.854167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 11:40:45.857930 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 11:40:45.861302 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 11:40:45.864126 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 11:40:45.871155 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 11:40:45.874136 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 11:40:45.881069 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 11:40:45.881157 Total UI for P1: 0, mck2ui 16
870 11:40:45.883932 best dqsien dly found for B0: ( 0, 14, 4)
871 11:40:45.891045 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:40:45.894374 Total UI for P1: 0, mck2ui 16
873 11:40:45.897687 best dqsien dly found for B1: ( 0, 14, 8)
874 11:40:45.900483 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 11:40:45.903970 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 11:40:45.904112
877 11:40:45.907532 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 11:40:45.910780 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 11:40:45.913804 [Gating] SW calibration Done
880 11:40:45.913892 ==
881 11:40:45.917141 Dram Type= 6, Freq= 0, CH_0, rank 0
882 11:40:45.920985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 11:40:45.921073 ==
884 11:40:45.925176 RX Vref Scan: 0
885 11:40:45.925265
886 11:40:45.925352 RX Vref 0 -> 0, step: 1
887 11:40:45.925434
888 11:40:45.928649 RX Delay -130 -> 252, step: 16
889 11:40:45.931522 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 11:40:45.935249 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
891 11:40:45.941886 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 11:40:45.945224 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 11:40:45.948550 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
894 11:40:45.951778 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 11:40:45.955139 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 11:40:45.961544 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
897 11:40:45.964526 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
898 11:40:45.968072 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
899 11:40:45.971548 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
900 11:40:45.978230 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
901 11:40:45.981125 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
902 11:40:45.984536 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
903 11:40:45.987683 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
904 11:40:45.991308 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 11:40:45.994639 ==
906 11:40:45.997483 Dram Type= 6, Freq= 0, CH_0, rank 0
907 11:40:46.001441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 11:40:46.001527 ==
909 11:40:46.001595 DQS Delay:
910 11:40:46.004194 DQS0 = 0, DQS1 = 0
911 11:40:46.004280 DQM Delay:
912 11:40:46.007785 DQM0 = 88, DQM1 = 75
913 11:40:46.007869 DQ Delay:
914 11:40:46.010833 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
915 11:40:46.014539 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
916 11:40:46.017426 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
917 11:40:46.020815 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
918 11:40:46.020900
919 11:40:46.020969
920 11:40:46.021031 ==
921 11:40:46.023996 Dram Type= 6, Freq= 0, CH_0, rank 0
922 11:40:46.027438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 11:40:46.027523 ==
924 11:40:46.027591
925 11:40:46.030494
926 11:40:46.030581 TX Vref Scan disable
927 11:40:46.033856 == TX Byte 0 ==
928 11:40:46.037390 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
929 11:40:46.040440 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
930 11:40:46.043860 == TX Byte 1 ==
931 11:40:46.046841 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
932 11:40:46.050375 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
933 11:40:46.050476 ==
934 11:40:46.053538 Dram Type= 6, Freq= 0, CH_0, rank 0
935 11:40:46.060383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 11:40:46.060487 ==
937 11:40:46.071886 TX Vref=22, minBit 6, minWin=26, winSum=439
938 11:40:46.075181 TX Vref=24, minBit 1, minWin=27, winSum=446
939 11:40:46.079020 TX Vref=26, minBit 2, minWin=27, winSum=449
940 11:40:46.082351 TX Vref=28, minBit 6, minWin=27, winSum=451
941 11:40:46.085176 TX Vref=30, minBit 0, minWin=28, winSum=454
942 11:40:46.092378 TX Vref=32, minBit 2, minWin=27, winSum=447
943 11:40:46.095030 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
944 11:40:46.095114
945 11:40:46.098560 Final TX Range 1 Vref 30
946 11:40:46.098645
947 11:40:46.098711 ==
948 11:40:46.102083 Dram Type= 6, Freq= 0, CH_0, rank 0
949 11:40:46.105054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 11:40:46.105139 ==
951 11:40:46.108910
952 11:40:46.108994
953 11:40:46.109060 TX Vref Scan disable
954 11:40:46.111775 == TX Byte 0 ==
955 11:40:46.115354 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
956 11:40:46.119068 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
957 11:40:46.122286 == TX Byte 1 ==
958 11:40:46.125676 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
959 11:40:46.128245 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
960 11:40:46.131718
961 11:40:46.131803 [DATLAT]
962 11:40:46.131871 Freq=800, CH0 RK0
963 11:40:46.131934
964 11:40:46.134900 DATLAT Default: 0xa
965 11:40:46.134984 0, 0xFFFF, sum = 0
966 11:40:46.138680 1, 0xFFFF, sum = 0
967 11:40:46.138770 2, 0xFFFF, sum = 0
968 11:40:46.141984 3, 0xFFFF, sum = 0
969 11:40:46.142069 4, 0xFFFF, sum = 0
970 11:40:46.145061 5, 0xFFFF, sum = 0
971 11:40:46.148431 6, 0xFFFF, sum = 0
972 11:40:46.148532 7, 0xFFFF, sum = 0
973 11:40:46.151736 8, 0xFFFF, sum = 0
974 11:40:46.151824 9, 0x0, sum = 1
975 11:40:46.151893 10, 0x0, sum = 2
976 11:40:46.154889 11, 0x0, sum = 3
977 11:40:46.154976 12, 0x0, sum = 4
978 11:40:46.158836 best_step = 10
979 11:40:46.158921
980 11:40:46.158988 ==
981 11:40:46.162000 Dram Type= 6, Freq= 0, CH_0, rank 0
982 11:40:46.165112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 11:40:46.165196 ==
984 11:40:46.168532 RX Vref Scan: 1
985 11:40:46.168615
986 11:40:46.168682 Set Vref Range= 32 -> 127
987 11:40:46.171632
988 11:40:46.171709 RX Vref 32 -> 127, step: 1
989 11:40:46.171773
990 11:40:46.175351 RX Delay -111 -> 252, step: 8
991 11:40:46.175421
992 11:40:46.178317 Set Vref, RX VrefLevel [Byte0]: 32
993 11:40:46.181964 [Byte1]: 32
994 11:40:46.182033
995 11:40:46.185501 Set Vref, RX VrefLevel [Byte0]: 33
996 11:40:46.187941 [Byte1]: 33
997 11:40:46.192415
998 11:40:46.192488 Set Vref, RX VrefLevel [Byte0]: 34
999 11:40:46.195916 [Byte1]: 34
1000 11:40:46.200508
1001 11:40:46.200586 Set Vref, RX VrefLevel [Byte0]: 35
1002 11:40:46.203438 [Byte1]: 35
1003 11:40:46.207839
1004 11:40:46.207937 Set Vref, RX VrefLevel [Byte0]: 36
1005 11:40:46.210879 [Byte1]: 36
1006 11:40:46.215545
1007 11:40:46.215624 Set Vref, RX VrefLevel [Byte0]: 37
1008 11:40:46.218669 [Byte1]: 37
1009 11:40:46.223296
1010 11:40:46.223379 Set Vref, RX VrefLevel [Byte0]: 38
1011 11:40:46.226675 [Byte1]: 38
1012 11:40:46.231047
1013 11:40:46.231137 Set Vref, RX VrefLevel [Byte0]: 39
1014 11:40:46.234127 [Byte1]: 39
1015 11:40:46.238467
1016 11:40:46.238552 Set Vref, RX VrefLevel [Byte0]: 40
1017 11:40:46.242268 [Byte1]: 40
1018 11:40:46.246129
1019 11:40:46.246213 Set Vref, RX VrefLevel [Byte0]: 41
1020 11:40:46.249688 [Byte1]: 41
1021 11:40:46.253748
1022 11:40:46.253833 Set Vref, RX VrefLevel [Byte0]: 42
1023 11:40:46.256963 [Byte1]: 42
1024 11:40:46.261544
1025 11:40:46.261665 Set Vref, RX VrefLevel [Byte0]: 43
1026 11:40:46.264424 [Byte1]: 43
1027 11:40:46.268697
1028 11:40:46.268772 Set Vref, RX VrefLevel [Byte0]: 44
1029 11:40:46.272045 [Byte1]: 44
1030 11:40:46.276313
1031 11:40:46.276387 Set Vref, RX VrefLevel [Byte0]: 45
1032 11:40:46.279983 [Byte1]: 45
1033 11:40:46.284498
1034 11:40:46.284583 Set Vref, RX VrefLevel [Byte0]: 46
1035 11:40:46.287728 [Byte1]: 46
1036 11:40:46.291748
1037 11:40:46.291833 Set Vref, RX VrefLevel [Byte0]: 47
1038 11:40:46.294952 [Byte1]: 47
1039 11:40:46.299463
1040 11:40:46.299535 Set Vref, RX VrefLevel [Byte0]: 48
1041 11:40:46.302527 [Byte1]: 48
1042 11:40:46.307197
1043 11:40:46.307273 Set Vref, RX VrefLevel [Byte0]: 49
1044 11:40:46.310827 [Byte1]: 49
1045 11:40:46.314676
1046 11:40:46.314775 Set Vref, RX VrefLevel [Byte0]: 50
1047 11:40:46.318439 [Byte1]: 50
1048 11:40:46.322288
1049 11:40:46.322372 Set Vref, RX VrefLevel [Byte0]: 51
1050 11:40:46.325664 [Byte1]: 51
1051 11:40:46.330008
1052 11:40:46.330096 Set Vref, RX VrefLevel [Byte0]: 52
1053 11:40:46.333310 [Byte1]: 52
1054 11:40:46.337936
1055 11:40:46.338020 Set Vref, RX VrefLevel [Byte0]: 53
1056 11:40:46.340752 [Byte1]: 53
1057 11:40:46.345674
1058 11:40:46.345758 Set Vref, RX VrefLevel [Byte0]: 54
1059 11:40:46.348414 [Byte1]: 54
1060 11:40:46.353378
1061 11:40:46.353462 Set Vref, RX VrefLevel [Byte0]: 55
1062 11:40:46.356190 [Byte1]: 55
1063 11:40:46.360718
1064 11:40:46.360802 Set Vref, RX VrefLevel [Byte0]: 56
1065 11:40:46.363769 [Byte1]: 56
1066 11:40:46.368745
1067 11:40:46.368830 Set Vref, RX VrefLevel [Byte0]: 57
1068 11:40:46.371500 [Byte1]: 57
1069 11:40:46.375956
1070 11:40:46.376045 Set Vref, RX VrefLevel [Byte0]: 58
1071 11:40:46.379290 [Byte1]: 58
1072 11:40:46.383502
1073 11:40:46.383586 Set Vref, RX VrefLevel [Byte0]: 59
1074 11:40:46.387101 [Byte1]: 59
1075 11:40:46.391210
1076 11:40:46.391294 Set Vref, RX VrefLevel [Byte0]: 60
1077 11:40:46.394511 [Byte1]: 60
1078 11:40:46.399018
1079 11:40:46.399102 Set Vref, RX VrefLevel [Byte0]: 61
1080 11:40:46.402462 [Byte1]: 61
1081 11:40:46.406654
1082 11:40:46.406736 Set Vref, RX VrefLevel [Byte0]: 62
1083 11:40:46.409760 [Byte1]: 62
1084 11:40:46.414345
1085 11:40:46.414458 Set Vref, RX VrefLevel [Byte0]: 63
1086 11:40:46.417246 [Byte1]: 63
1087 11:40:46.421643
1088 11:40:46.421729 Set Vref, RX VrefLevel [Byte0]: 64
1089 11:40:46.424832 [Byte1]: 64
1090 11:40:46.429481
1091 11:40:46.429572 Set Vref, RX VrefLevel [Byte0]: 65
1092 11:40:46.432710 [Byte1]: 65
1093 11:40:46.437374
1094 11:40:46.437456 Set Vref, RX VrefLevel [Byte0]: 66
1095 11:40:46.440670 [Byte1]: 66
1096 11:40:46.444849
1097 11:40:46.444932 Set Vref, RX VrefLevel [Byte0]: 67
1098 11:40:46.448268 [Byte1]: 67
1099 11:40:46.452976
1100 11:40:46.453058 Set Vref, RX VrefLevel [Byte0]: 68
1101 11:40:46.455328 [Byte1]: 68
1102 11:40:46.459968
1103 11:40:46.460074 Set Vref, RX VrefLevel [Byte0]: 69
1104 11:40:46.463325 [Byte1]: 69
1105 11:40:46.467827
1106 11:40:46.467910 Set Vref, RX VrefLevel [Byte0]: 70
1107 11:40:46.470654 [Byte1]: 70
1108 11:40:46.475184
1109 11:40:46.475266 Set Vref, RX VrefLevel [Byte0]: 71
1110 11:40:46.478754 [Byte1]: 71
1111 11:40:46.483066
1112 11:40:46.483166 Set Vref, RX VrefLevel [Byte0]: 72
1113 11:40:46.486010 [Byte1]: 72
1114 11:40:46.490248
1115 11:40:46.490344 Set Vref, RX VrefLevel [Byte0]: 73
1116 11:40:46.494061 [Byte1]: 73
1117 11:40:46.498275
1118 11:40:46.498357 Set Vref, RX VrefLevel [Byte0]: 74
1119 11:40:46.501371 [Byte1]: 74
1120 11:40:46.505698
1121 11:40:46.505780 Final RX Vref Byte 0 = 57 to rank0
1122 11:40:46.508930 Final RX Vref Byte 1 = 60 to rank0
1123 11:40:46.512618 Final RX Vref Byte 0 = 57 to rank1
1124 11:40:46.515729 Final RX Vref Byte 1 = 60 to rank1==
1125 11:40:46.518898 Dram Type= 6, Freq= 0, CH_0, rank 0
1126 11:40:46.525575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1127 11:40:46.525659 ==
1128 11:40:46.525724 DQS Delay:
1129 11:40:46.525785 DQS0 = 0, DQS1 = 0
1130 11:40:46.529034 DQM Delay:
1131 11:40:46.529168 DQM0 = 88, DQM1 = 77
1132 11:40:46.532122 DQ Delay:
1133 11:40:46.535383 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1134 11:40:46.539046 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1135 11:40:46.542501 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1136 11:40:46.545580 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1137 11:40:46.545663
1138 11:40:46.545728
1139 11:40:46.552166 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1140 11:40:46.555671 CH0 RK0: MR19=606, MR18=2F28
1141 11:40:46.562374 CH0_RK0: MR19=0x606, MR18=0x2F28, DQSOSC=397, MR23=63, INC=93, DEC=62
1142 11:40:46.562458
1143 11:40:46.565276 ----->DramcWriteLeveling(PI) begin...
1144 11:40:46.565379 ==
1145 11:40:46.568996 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 11:40:46.572270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 11:40:46.572353 ==
1148 11:40:46.575277 Write leveling (Byte 0): 32 => 32
1149 11:40:46.578782 Write leveling (Byte 1): 27 => 27
1150 11:40:46.581911 DramcWriteLeveling(PI) end<-----
1151 11:40:46.582010
1152 11:40:46.582076 ==
1153 11:40:46.585708 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 11:40:46.588817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 11:40:46.588900 ==
1156 11:40:46.591990 [Gating] SW mode calibration
1157 11:40:46.598490 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1158 11:40:46.605434 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1159 11:40:46.608558 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 11:40:46.653211 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1161 11:40:46.654111 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:40:46.654600 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:40:46.654726 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:40:46.654976 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:40:46.655045 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:40:46.655159 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:40:46.655261 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:40:46.655323 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:40:46.655432 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:40:46.687662 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:40:46.688236 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:40:46.688520 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:40:46.688593 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:40:46.688726 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:40:46.689011 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:40:46.689407 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1177 11:40:46.692468 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1178 11:40:46.692572 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:40:46.695704 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:40:46.702559 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:40:46.705509 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:40:46.709338 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:40:46.715475 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:40:46.719270 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1185 11:40:46.722444 0 9 8 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
1186 11:40:46.728550 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
1187 11:40:46.732329 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:40:46.735433 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 11:40:46.742052 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 11:40:46.745284 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 11:40:46.748853 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1192 11:40:46.755320 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
1193 11:40:46.758493 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1194 11:40:46.762215 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:40:46.769247 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:40:46.772052 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:40:46.775133 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:40:46.782325 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:40:46.785447 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:40:46.788946 0 11 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1201 11:40:46.795283 0 11 8 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
1202 11:40:46.799479 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:40:46.802915 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:40:46.806759 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:40:46.810201 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 11:40:46.816940 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 11:40:46.820185 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:40:46.824028 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 11:40:46.827335 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1210 11:40:46.833798 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:40:46.837307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:40:46.840818 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:40:46.847480 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:40:46.850474 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:40:46.853735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:40:46.860522 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:40:46.863533 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:40:46.866962 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:40:46.874144 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:40:46.877548 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:40:46.880398 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 11:40:46.887219 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 11:40:46.889921 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 11:40:46.894049 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1225 11:40:46.899910 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 11:40:46.903283 Total UI for P1: 0, mck2ui 16
1227 11:40:46.906460 best dqsien dly found for B0: ( 0, 14, 4)
1228 11:40:46.909985 Total UI for P1: 0, mck2ui 16
1229 11:40:46.913583 best dqsien dly found for B1: ( 0, 14, 6)
1230 11:40:46.916735 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1231 11:40:46.919915 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1232 11:40:46.920015
1233 11:40:46.923444 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1234 11:40:46.926184 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1235 11:40:46.929684 [Gating] SW calibration Done
1236 11:40:46.929789 ==
1237 11:40:46.933950 Dram Type= 6, Freq= 0, CH_0, rank 1
1238 11:40:46.936686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1239 11:40:46.936767 ==
1240 11:40:46.939593 RX Vref Scan: 0
1241 11:40:46.939692
1242 11:40:46.939788 RX Vref 0 -> 0, step: 1
1243 11:40:46.939884
1244 11:40:46.943007 RX Delay -130 -> 252, step: 16
1245 11:40:46.949657 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1246 11:40:46.952702 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1247 11:40:46.956069 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1248 11:40:46.959381 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1249 11:40:46.963197 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1250 11:40:46.969638 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1251 11:40:46.972609 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1252 11:40:46.975826 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1253 11:40:46.979572 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1254 11:40:46.982740 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1255 11:40:46.989417 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1256 11:40:46.992883 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1257 11:40:46.995890 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1258 11:40:46.998897 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1259 11:40:47.002387 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1260 11:40:47.008853 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1261 11:40:47.008959 ==
1262 11:40:47.012447 Dram Type= 6, Freq= 0, CH_0, rank 1
1263 11:40:47.016445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1264 11:40:47.016569 ==
1265 11:40:47.016667 DQS Delay:
1266 11:40:47.019046 DQS0 = 0, DQS1 = 0
1267 11:40:47.019148 DQM Delay:
1268 11:40:47.022641 DQM0 = 89, DQM1 = 78
1269 11:40:47.022742 DQ Delay:
1270 11:40:47.025825 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1271 11:40:47.029024 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1272 11:40:47.032270 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =77
1273 11:40:47.036215 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1274 11:40:47.036326
1275 11:40:47.036439
1276 11:40:47.036605 ==
1277 11:40:47.039367 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 11:40:47.042580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 11:40:47.042693 ==
1280 11:40:47.042791
1281 11:40:47.045882
1282 11:40:47.045982 TX Vref Scan disable
1283 11:40:47.048895 == TX Byte 0 ==
1284 11:40:47.052181 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1285 11:40:47.056084 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1286 11:40:47.058923 == TX Byte 1 ==
1287 11:40:47.062212 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1288 11:40:47.066034 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1289 11:40:47.066136 ==
1290 11:40:47.069560 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 11:40:47.075551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 11:40:47.075669 ==
1293 11:40:47.088507 TX Vref=22, minBit 1, minWin=27, winSum=441
1294 11:40:47.091282 TX Vref=24, minBit 1, minWin=27, winSum=448
1295 11:40:47.094820 TX Vref=26, minBit 1, minWin=27, winSum=448
1296 11:40:47.098136 TX Vref=28, minBit 1, minWin=27, winSum=450
1297 11:40:47.101553 TX Vref=30, minBit 0, minWin=28, winSum=453
1298 11:40:47.108178 TX Vref=32, minBit 4, minWin=27, winSum=450
1299 11:40:47.111828 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1300 11:40:47.111957
1301 11:40:47.114448 Final TX Range 1 Vref 30
1302 11:40:47.114573
1303 11:40:47.114668 ==
1304 11:40:47.118254 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 11:40:47.121462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 11:40:47.121586 ==
1307 11:40:47.124705
1308 11:40:47.124811
1309 11:40:47.124903 TX Vref Scan disable
1310 11:40:47.128077 == TX Byte 0 ==
1311 11:40:47.131641 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1312 11:40:47.137969 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1313 11:40:47.138092 == TX Byte 1 ==
1314 11:40:47.141373 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1315 11:40:47.148247 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1316 11:40:47.148359
1317 11:40:47.148426 [DATLAT]
1318 11:40:47.148504 Freq=800, CH0 RK1
1319 11:40:47.148589
1320 11:40:47.151433 DATLAT Default: 0xa
1321 11:40:47.151535 0, 0xFFFF, sum = 0
1322 11:40:47.155351 1, 0xFFFF, sum = 0
1323 11:40:47.155429 2, 0xFFFF, sum = 0
1324 11:40:47.158644 3, 0xFFFF, sum = 0
1325 11:40:47.158741 4, 0xFFFF, sum = 0
1326 11:40:47.161252 5, 0xFFFF, sum = 0
1327 11:40:47.161325 6, 0xFFFF, sum = 0
1328 11:40:47.164622 7, 0xFFFF, sum = 0
1329 11:40:47.167950 8, 0xFFFF, sum = 0
1330 11:40:47.168066 9, 0x0, sum = 1
1331 11:40:47.168144 10, 0x0, sum = 2
1332 11:40:47.171726 11, 0x0, sum = 3
1333 11:40:47.171818 12, 0x0, sum = 4
1334 11:40:47.174585 best_step = 10
1335 11:40:47.174696
1336 11:40:47.174761 ==
1337 11:40:47.178211 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 11:40:47.181530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 11:40:47.181618 ==
1340 11:40:47.184833 RX Vref Scan: 0
1341 11:40:47.184915
1342 11:40:47.184979 RX Vref 0 -> 0, step: 1
1343 11:40:47.185040
1344 11:40:47.187702 RX Delay -111 -> 252, step: 8
1345 11:40:47.194738 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1346 11:40:47.198433 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1347 11:40:47.201257 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1348 11:40:47.204610 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1349 11:40:47.208152 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1350 11:40:47.214790 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1351 11:40:47.218107 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1352 11:40:47.221319 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1353 11:40:47.225221 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1354 11:40:47.227900 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1355 11:40:47.234526 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1356 11:40:47.237948 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1357 11:40:47.240979 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1358 11:40:47.244544 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1359 11:40:47.251122 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1360 11:40:47.254259 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1361 11:40:47.254355 ==
1362 11:40:47.257580 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 11:40:47.260769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 11:40:47.260917 ==
1365 11:40:47.263933 DQS Delay:
1366 11:40:47.264042 DQS0 = 0, DQS1 = 0
1367 11:40:47.264158 DQM Delay:
1368 11:40:47.267545 DQM0 = 86, DQM1 = 77
1369 11:40:47.267646 DQ Delay:
1370 11:40:47.271084 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1371 11:40:47.274538 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1372 11:40:47.277344 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1373 11:40:47.280625 DQ12 =88, DQ13 =80, DQ14 =88, DQ15 =88
1374 11:40:47.280738
1375 11:40:47.280831
1376 11:40:47.290971 [DQSOSCAuto] RK1, (LSB)MR18= 0x2521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1377 11:40:47.294120 CH0 RK1: MR19=606, MR18=2521
1378 11:40:47.297433 CH0_RK1: MR19=0x606, MR18=0x2521, DQSOSC=400, MR23=63, INC=92, DEC=61
1379 11:40:47.300699 [RxdqsGatingPostProcess] freq 800
1380 11:40:47.307700 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1381 11:40:47.310327 Pre-setting of DQS Precalculation
1382 11:40:47.313674 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1383 11:40:47.313788 ==
1384 11:40:47.317369 Dram Type= 6, Freq= 0, CH_1, rank 0
1385 11:40:47.324511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 11:40:47.324639 ==
1387 11:40:47.327533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1388 11:40:47.333762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1389 11:40:47.343535 [CA 0] Center 36 (6~67) winsize 62
1390 11:40:47.346368 [CA 1] Center 36 (6~67) winsize 62
1391 11:40:47.349697 [CA 2] Center 35 (5~65) winsize 61
1392 11:40:47.353201 [CA 3] Center 34 (4~65) winsize 62
1393 11:40:47.356453 [CA 4] Center 34 (4~65) winsize 62
1394 11:40:47.360045 [CA 5] Center 33 (3~64) winsize 62
1395 11:40:47.360132
1396 11:40:47.363312 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1397 11:40:47.363395
1398 11:40:47.366362 [CATrainingPosCal] consider 1 rank data
1399 11:40:47.369476 u2DelayCellTimex100 = 270/100 ps
1400 11:40:47.372729 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1401 11:40:47.379698 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1402 11:40:47.383254 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1403 11:40:47.385920 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1404 11:40:47.389449 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1405 11:40:47.393162 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1406 11:40:47.393243
1407 11:40:47.396164 CA PerBit enable=1, Macro0, CA PI delay=33
1408 11:40:47.396246
1409 11:40:47.399096 [CBTSetCACLKResult] CA Dly = 33
1410 11:40:47.402774 CS Dly: 4 (0~35)
1411 11:40:47.402857 ==
1412 11:40:47.405709 Dram Type= 6, Freq= 0, CH_1, rank 1
1413 11:40:47.409289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 11:40:47.409372 ==
1415 11:40:47.415901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1416 11:40:47.419006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1417 11:40:47.429536 [CA 0] Center 36 (6~67) winsize 62
1418 11:40:47.433022 [CA 1] Center 36 (6~67) winsize 62
1419 11:40:47.436340 [CA 2] Center 34 (4~65) winsize 62
1420 11:40:47.439186 [CA 3] Center 34 (3~65) winsize 63
1421 11:40:47.442971 [CA 4] Center 34 (4~65) winsize 62
1422 11:40:47.445833 [CA 5] Center 34 (3~65) winsize 63
1423 11:40:47.445949
1424 11:40:47.449369 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1425 11:40:47.449471
1426 11:40:47.452514 [CATrainingPosCal] consider 2 rank data
1427 11:40:47.455551 u2DelayCellTimex100 = 270/100 ps
1428 11:40:47.459745 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1429 11:40:47.462997 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1430 11:40:47.466606 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1431 11:40:47.470144 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1432 11:40:47.473899 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1433 11:40:47.478023 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1434 11:40:47.478132
1435 11:40:47.482191 CA PerBit enable=1, Macro0, CA PI delay=33
1436 11:40:47.482290
1437 11:40:47.485365 [CBTSetCACLKResult] CA Dly = 33
1438 11:40:47.488588 CS Dly: 5 (0~37)
1439 11:40:47.488697
1440 11:40:47.492930 ----->DramcWriteLeveling(PI) begin...
1441 11:40:47.493040 ==
1442 11:40:47.496512 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:40:47.499760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:40:47.499843 ==
1445 11:40:47.502854 Write leveling (Byte 0): 29 => 29
1446 11:40:47.506225 Write leveling (Byte 1): 29 => 29
1447 11:40:47.506308 DramcWriteLeveling(PI) end<-----
1448 11:40:47.509842
1449 11:40:47.509958 ==
1450 11:40:47.512916 Dram Type= 6, Freq= 0, CH_1, rank 0
1451 11:40:47.515943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 11:40:47.516071 ==
1453 11:40:47.519326 [Gating] SW mode calibration
1454 11:40:47.526274 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1455 11:40:47.529685 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1456 11:40:47.535842 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1457 11:40:47.539513 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1458 11:40:47.542896 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:40:47.549719 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:40:47.552714 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:40:47.556224 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:40:47.562464 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:40:47.566347 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:40:47.569156 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:40:47.576153 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:40:47.579564 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:40:47.582673 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:40:47.589376 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:40:47.592539 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:40:47.595683 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:40:47.602551 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:40:47.605733 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:40:47.609050 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1474 11:40:47.615785 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:40:47.619027 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:40:47.622198 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:40:47.628651 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:40:47.632320 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:40:47.635945 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:40:47.642185 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:40:47.645210 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:40:47.648820 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1483 11:40:47.655192 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:40:47.658705 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:40:47.661910 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 11:40:47.668556 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 11:40:47.671977 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 11:40:47.675532 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 11:40:47.681816 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
1490 11:40:47.685193 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
1491 11:40:47.688498 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:40:47.695132 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:40:47.698640 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:40:47.701788 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:40:47.708252 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:40:47.711438 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:40:47.715365 0 11 4 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
1498 11:40:47.717928 0 11 8 | B1->B0 | 3b3b 3d3d | 0 0 | (0 0) (0 0)
1499 11:40:47.725212 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:40:47.728034 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:40:47.731382 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:40:47.738168 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 11:40:47.741384 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 11:40:47.744627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:40:47.751583 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 11:40:47.754689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1507 11:40:47.757769 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:40:47.764719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:40:47.767833 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:40:47.771755 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:40:47.777684 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:40:47.780884 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:40:47.784342 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:40:47.791158 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:40:47.794168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:40:47.797683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:40:47.804423 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:40:47.808208 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 11:40:47.811037 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:40:47.817596 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:40:47.821094 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1522 11:40:47.823991 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1523 11:40:47.827612 Total UI for P1: 0, mck2ui 16
1524 11:40:47.831030 best dqsien dly found for B0: ( 0, 14, 4)
1525 11:40:47.837727 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 11:40:47.837827 Total UI for P1: 0, mck2ui 16
1527 11:40:47.841120 best dqsien dly found for B1: ( 0, 14, 8)
1528 11:40:47.847661 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1529 11:40:47.850829 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1530 11:40:47.850916
1531 11:40:47.854567 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1532 11:40:47.857585 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1533 11:40:47.860980 [Gating] SW calibration Done
1534 11:40:47.861070 ==
1535 11:40:47.864216 Dram Type= 6, Freq= 0, CH_1, rank 0
1536 11:40:47.867800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1537 11:40:47.867911 ==
1538 11:40:47.870870 RX Vref Scan: 0
1539 11:40:47.870945
1540 11:40:47.871017 RX Vref 0 -> 0, step: 1
1541 11:40:47.871078
1542 11:40:47.874347 RX Delay -130 -> 252, step: 16
1543 11:40:47.877381 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1544 11:40:47.884285 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1545 11:40:47.887169 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1546 11:40:47.890940 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1547 11:40:47.894298 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1548 11:40:47.897474 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1549 11:40:47.904068 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1550 11:40:47.908006 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1551 11:40:47.911380 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1552 11:40:47.913997 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1553 11:40:47.918097 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1554 11:40:47.924418 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1555 11:40:47.927181 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1556 11:40:47.930723 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1557 11:40:47.933684 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1558 11:40:47.937346 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1559 11:40:47.937429 ==
1560 11:40:47.940589 Dram Type= 6, Freq= 0, CH_1, rank 0
1561 11:40:47.948287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1562 11:40:47.948363 ==
1563 11:40:47.948427 DQS Delay:
1564 11:40:47.950883 DQS0 = 0, DQS1 = 0
1565 11:40:47.950952 DQM Delay:
1566 11:40:47.951012 DQM0 = 85, DQM1 = 78
1567 11:40:47.954379 DQ Delay:
1568 11:40:47.958049 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1569 11:40:47.960513 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1570 11:40:47.964224 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1571 11:40:47.967048 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1572 11:40:47.967118
1573 11:40:47.967182
1574 11:40:47.967243 ==
1575 11:40:47.970351 Dram Type= 6, Freq= 0, CH_1, rank 0
1576 11:40:47.973939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1577 11:40:47.974023 ==
1578 11:40:47.974087
1579 11:40:47.974147
1580 11:40:47.976859 TX Vref Scan disable
1581 11:40:47.980498 == TX Byte 0 ==
1582 11:40:47.984004 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1583 11:40:47.986985 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1584 11:40:47.990393 == TX Byte 1 ==
1585 11:40:47.993691 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1586 11:40:47.997126 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1587 11:40:47.997204 ==
1588 11:40:48.000075 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 11:40:48.006360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 11:40:48.006440 ==
1591 11:40:48.018324 TX Vref=22, minBit 6, minWin=26, winSum=439
1592 11:40:48.021712 TX Vref=24, minBit 4, minWin=27, winSum=447
1593 11:40:48.024972 TX Vref=26, minBit 1, minWin=27, winSum=449
1594 11:40:48.028205 TX Vref=28, minBit 1, minWin=27, winSum=455
1595 11:40:48.031089 TX Vref=30, minBit 1, minWin=27, winSum=455
1596 11:40:48.037871 TX Vref=32, minBit 1, minWin=27, winSum=453
1597 11:40:48.041449 [TxChooseVref] Worse bit 1, Min win 27, Win sum 455, Final Vref 28
1598 11:40:48.041542
1599 11:40:48.045448 Final TX Range 1 Vref 28
1600 11:40:48.045567
1601 11:40:48.045634 ==
1602 11:40:48.048589 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 11:40:48.051876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 11:40:48.051959 ==
1605 11:40:48.052025
1606 11:40:48.052124
1607 11:40:48.055061 TX Vref Scan disable
1608 11:40:48.058324 == TX Byte 0 ==
1609 11:40:48.061713 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1610 11:40:48.065174 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1611 11:40:48.068572 == TX Byte 1 ==
1612 11:40:48.071702 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1613 11:40:48.075440 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1614 11:40:48.075524
1615 11:40:48.078412 [DATLAT]
1616 11:40:48.078508 Freq=800, CH1 RK0
1617 11:40:48.078602
1618 11:40:48.081805 DATLAT Default: 0xa
1619 11:40:48.081928 0, 0xFFFF, sum = 0
1620 11:40:48.084843 1, 0xFFFF, sum = 0
1621 11:40:48.084944 2, 0xFFFF, sum = 0
1622 11:40:48.087999 3, 0xFFFF, sum = 0
1623 11:40:48.088134 4, 0xFFFF, sum = 0
1624 11:40:48.091496 5, 0xFFFF, sum = 0
1625 11:40:48.091581 6, 0xFFFF, sum = 0
1626 11:40:48.094655 7, 0xFFFF, sum = 0
1627 11:40:48.094780 8, 0xFFFF, sum = 0
1628 11:40:48.098272 9, 0x0, sum = 1
1629 11:40:48.098397 10, 0x0, sum = 2
1630 11:40:48.101787 11, 0x0, sum = 3
1631 11:40:48.101892 12, 0x0, sum = 4
1632 11:40:48.105358 best_step = 10
1633 11:40:48.105459
1634 11:40:48.105554 ==
1635 11:40:48.108200 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 11:40:48.111646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 11:40:48.111748 ==
1638 11:40:48.114591 RX Vref Scan: 1
1639 11:40:48.114689
1640 11:40:48.114778 Set Vref Range= 32 -> 127
1641 11:40:48.114839
1642 11:40:48.118286 RX Vref 32 -> 127, step: 1
1643 11:40:48.118358
1644 11:40:48.121879 RX Delay -95 -> 252, step: 8
1645 11:40:48.121964
1646 11:40:48.124879 Set Vref, RX VrefLevel [Byte0]: 32
1647 11:40:48.128044 [Byte1]: 32
1648 11:40:48.128129
1649 11:40:48.131573 Set Vref, RX VrefLevel [Byte0]: 33
1650 11:40:48.135063 [Byte1]: 33
1651 11:40:48.138126
1652 11:40:48.138205 Set Vref, RX VrefLevel [Byte0]: 34
1653 11:40:48.141442 [Byte1]: 34
1654 11:40:48.145686
1655 11:40:48.145775 Set Vref, RX VrefLevel [Byte0]: 35
1656 11:40:48.149131 [Byte1]: 35
1657 11:40:48.153753
1658 11:40:48.153837 Set Vref, RX VrefLevel [Byte0]: 36
1659 11:40:48.156876 [Byte1]: 36
1660 11:40:48.161311
1661 11:40:48.161396 Set Vref, RX VrefLevel [Byte0]: 37
1662 11:40:48.164206 [Byte1]: 37
1663 11:40:48.169008
1664 11:40:48.169093 Set Vref, RX VrefLevel [Byte0]: 38
1665 11:40:48.171768 [Byte1]: 38
1666 11:40:48.176488
1667 11:40:48.176572 Set Vref, RX VrefLevel [Byte0]: 39
1668 11:40:48.179516 [Byte1]: 39
1669 11:40:48.183845
1670 11:40:48.183929 Set Vref, RX VrefLevel [Byte0]: 40
1671 11:40:48.187099 [Byte1]: 40
1672 11:40:48.191749
1673 11:40:48.191834 Set Vref, RX VrefLevel [Byte0]: 41
1674 11:40:48.194623 [Byte1]: 41
1675 11:40:48.199459
1676 11:40:48.199543 Set Vref, RX VrefLevel [Byte0]: 42
1677 11:40:48.202219 [Byte1]: 42
1678 11:40:48.206390
1679 11:40:48.206495 Set Vref, RX VrefLevel [Byte0]: 43
1680 11:40:48.210158 [Byte1]: 43
1681 11:40:48.214338
1682 11:40:48.214442 Set Vref, RX VrefLevel [Byte0]: 44
1683 11:40:48.217695 [Byte1]: 44
1684 11:40:48.221741
1685 11:40:48.221843 Set Vref, RX VrefLevel [Byte0]: 45
1686 11:40:48.225412 [Byte1]: 45
1687 11:40:48.229681
1688 11:40:48.229765 Set Vref, RX VrefLevel [Byte0]: 46
1689 11:40:48.232612 [Byte1]: 46
1690 11:40:48.237148
1691 11:40:48.237269 Set Vref, RX VrefLevel [Byte0]: 47
1692 11:40:48.240069 [Byte1]: 47
1693 11:40:48.244634
1694 11:40:48.244742 Set Vref, RX VrefLevel [Byte0]: 48
1695 11:40:48.248292 [Byte1]: 48
1696 11:40:48.252014
1697 11:40:48.252144 Set Vref, RX VrefLevel [Byte0]: 49
1698 11:40:48.255613 [Byte1]: 49
1699 11:40:48.259899
1700 11:40:48.260017 Set Vref, RX VrefLevel [Byte0]: 50
1701 11:40:48.263068 [Byte1]: 50
1702 11:40:48.267791
1703 11:40:48.267913 Set Vref, RX VrefLevel [Byte0]: 51
1704 11:40:48.270833 [Byte1]: 51
1705 11:40:48.274714
1706 11:40:48.274819 Set Vref, RX VrefLevel [Byte0]: 52
1707 11:40:48.278275 [Byte1]: 52
1708 11:40:48.282618
1709 11:40:48.282724 Set Vref, RX VrefLevel [Byte0]: 53
1710 11:40:48.286337 [Byte1]: 53
1711 11:40:48.290209
1712 11:40:48.290313 Set Vref, RX VrefLevel [Byte0]: 54
1713 11:40:48.293371 [Byte1]: 54
1714 11:40:48.297687
1715 11:40:48.297789 Set Vref, RX VrefLevel [Byte0]: 55
1716 11:40:48.301038 [Byte1]: 55
1717 11:40:48.305464
1718 11:40:48.305602 Set Vref, RX VrefLevel [Byte0]: 56
1719 11:40:48.308889 [Byte1]: 56
1720 11:40:48.313916
1721 11:40:48.314041 Set Vref, RX VrefLevel [Byte0]: 57
1722 11:40:48.316376 [Byte1]: 57
1723 11:40:48.320845
1724 11:40:48.320922 Set Vref, RX VrefLevel [Byte0]: 58
1725 11:40:48.323781 [Byte1]: 58
1726 11:40:48.327998
1727 11:40:48.328084 Set Vref, RX VrefLevel [Byte0]: 59
1728 11:40:48.331549 [Byte1]: 59
1729 11:40:48.335734
1730 11:40:48.335826 Set Vref, RX VrefLevel [Byte0]: 60
1731 11:40:48.339345 [Byte1]: 60
1732 11:40:48.343224
1733 11:40:48.343311 Set Vref, RX VrefLevel [Byte0]: 61
1734 11:40:48.346968 [Byte1]: 61
1735 11:40:48.350672
1736 11:40:48.350756 Set Vref, RX VrefLevel [Byte0]: 62
1737 11:40:48.354520 [Byte1]: 62
1738 11:40:48.358465
1739 11:40:48.358550 Set Vref, RX VrefLevel [Byte0]: 63
1740 11:40:48.362135 [Byte1]: 63
1741 11:40:48.366248
1742 11:40:48.366332 Set Vref, RX VrefLevel [Byte0]: 64
1743 11:40:48.369211 [Byte1]: 64
1744 11:40:48.373699
1745 11:40:48.373784 Set Vref, RX VrefLevel [Byte0]: 65
1746 11:40:48.377485 [Byte1]: 65
1747 11:40:48.381712
1748 11:40:48.381797 Set Vref, RX VrefLevel [Byte0]: 66
1749 11:40:48.384727 [Byte1]: 66
1750 11:40:48.389452
1751 11:40:48.389535 Set Vref, RX VrefLevel [Byte0]: 67
1752 11:40:48.392960 [Byte1]: 67
1753 11:40:48.396741
1754 11:40:48.396825 Set Vref, RX VrefLevel [Byte0]: 68
1755 11:40:48.399858 [Byte1]: 68
1756 11:40:48.404356
1757 11:40:48.404440 Set Vref, RX VrefLevel [Byte0]: 69
1758 11:40:48.407522 [Byte1]: 69
1759 11:40:48.411498
1760 11:40:48.411581 Set Vref, RX VrefLevel [Byte0]: 70
1761 11:40:48.414886 [Byte1]: 70
1762 11:40:48.419433
1763 11:40:48.419517 Set Vref, RX VrefLevel [Byte0]: 71
1764 11:40:48.422428 [Byte1]: 71
1765 11:40:48.427329
1766 11:40:48.427412 Set Vref, RX VrefLevel [Byte0]: 72
1767 11:40:48.430272 [Byte1]: 72
1768 11:40:48.434447
1769 11:40:48.434556 Set Vref, RX VrefLevel [Byte0]: 73
1770 11:40:48.438233 [Byte1]: 73
1771 11:40:48.442531
1772 11:40:48.442615 Set Vref, RX VrefLevel [Byte0]: 74
1773 11:40:48.445529 [Byte1]: 74
1774 11:40:48.449479
1775 11:40:48.449562 Final RX Vref Byte 0 = 58 to rank0
1776 11:40:48.452966 Final RX Vref Byte 1 = 53 to rank0
1777 11:40:48.456419 Final RX Vref Byte 0 = 58 to rank1
1778 11:40:48.459620 Final RX Vref Byte 1 = 53 to rank1==
1779 11:40:48.463269 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 11:40:48.469760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 11:40:48.469845 ==
1782 11:40:48.469912 DQS Delay:
1783 11:40:48.469973 DQS0 = 0, DQS1 = 0
1784 11:40:48.472924 DQM Delay:
1785 11:40:48.473008 DQM0 = 86, DQM1 = 80
1786 11:40:48.476089 DQ Delay:
1787 11:40:48.479379 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1788 11:40:48.483015 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1789 11:40:48.486195 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1790 11:40:48.489705 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1791 11:40:48.489802
1792 11:40:48.489882
1793 11:40:48.495844 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1794 11:40:48.499379 CH1 RK0: MR19=606, MR18=1C2F
1795 11:40:48.506168 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1796 11:40:48.506253
1797 11:40:48.509540 ----->DramcWriteLeveling(PI) begin...
1798 11:40:48.509625 ==
1799 11:40:48.512886 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 11:40:48.515892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 11:40:48.515977 ==
1802 11:40:48.519378 Write leveling (Byte 0): 25 => 25
1803 11:40:48.523332 Write leveling (Byte 1): 25 => 25
1804 11:40:48.526182 DramcWriteLeveling(PI) end<-----
1805 11:40:48.526265
1806 11:40:48.526331 ==
1807 11:40:48.529434 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 11:40:48.532673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 11:40:48.532777 ==
1810 11:40:48.535926 [Gating] SW mode calibration
1811 11:40:48.542572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 11:40:48.549080 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 11:40:48.552727 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1814 11:40:48.559177 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1815 11:40:48.562595 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:40:48.565723 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:40:48.572211 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:40:48.575540 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:40:48.579153 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:40:48.582245 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:40:48.589032 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:40:48.592117 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:40:48.595769 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:40:48.602273 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:40:48.605651 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:40:48.609153 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:40:48.615281 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:40:48.618845 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:40:48.622208 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1830 11:40:48.628785 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1831 11:40:48.631938 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:40:48.636186 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:40:48.642135 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:40:48.645431 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:40:48.648926 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:40:48.655529 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:40:48.658949 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:40:48.661711 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:40:48.668494 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1840 11:40:48.671635 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:40:48.675430 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:40:48.681784 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 11:40:48.685126 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 11:40:48.688796 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 11:40:48.695258 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1846 11:40:48.698226 0 10 4 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
1847 11:40:48.701892 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:40:48.708536 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:40:48.711292 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:40:48.714646 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:40:48.721163 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:40:48.724731 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:40:48.728024 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:40:48.734808 0 11 4 | B1->B0 | 2626 3535 | 1 0 | (1 1) (0 0)
1855 11:40:48.737844 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1856 11:40:48.741422 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:40:48.747831 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:40:48.751006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 11:40:48.754700 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 11:40:48.761086 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 11:40:48.764420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1862 11:40:48.767896 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1863 11:40:48.774211 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1864 11:40:48.777538 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:40:48.780906 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:40:48.787640 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:40:48.790803 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:40:48.794107 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:40:48.800744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:40:48.804486 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:40:48.807613 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:40:48.811095 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:40:48.817488 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:40:48.820839 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:40:48.823832 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:40:48.830328 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:40:48.834160 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1878 11:40:48.837488 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1879 11:40:48.841068 Total UI for P1: 0, mck2ui 16
1880 11:40:48.843871 best dqsien dly found for B0: ( 0, 14, 0)
1881 11:40:48.850877 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 11:40:48.850965 Total UI for P1: 0, mck2ui 16
1883 11:40:48.857050 best dqsien dly found for B1: ( 0, 14, 4)
1884 11:40:48.860400 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1885 11:40:48.863635 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1886 11:40:48.863720
1887 11:40:48.867564 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1888 11:40:48.870752 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 11:40:48.873989 [Gating] SW calibration Done
1890 11:40:48.874073 ==
1891 11:40:48.877047 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 11:40:48.880296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 11:40:48.880386 ==
1894 11:40:48.883877 RX Vref Scan: 0
1895 11:40:48.883962
1896 11:40:48.884028 RX Vref 0 -> 0, step: 1
1897 11:40:48.884101
1898 11:40:48.886880 RX Delay -130 -> 252, step: 16
1899 11:40:48.894041 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1900 11:40:48.896982 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1901 11:40:48.900017 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1902 11:40:48.903525 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1903 11:40:48.906958 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1904 11:40:48.910279 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1905 11:40:48.916657 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1906 11:40:48.920496 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1907 11:40:48.923925 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1908 11:40:48.926729 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1909 11:40:48.930148 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1910 11:40:48.937004 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1911 11:40:48.940078 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1912 11:40:48.943583 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1913 11:40:48.946773 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1914 11:40:48.953787 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1915 11:40:48.953872 ==
1916 11:40:48.956511 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 11:40:48.960148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 11:40:48.960232 ==
1919 11:40:48.960299 DQS Delay:
1920 11:40:48.963613 DQS0 = 0, DQS1 = 0
1921 11:40:48.963697 DQM Delay:
1922 11:40:48.966989 DQM0 = 83, DQM1 = 80
1923 11:40:48.967073 DQ Delay:
1924 11:40:48.970001 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1925 11:40:48.973390 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1926 11:40:48.976758 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1927 11:40:48.979813 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1928 11:40:48.979896
1929 11:40:48.979963
1930 11:40:48.980024 ==
1931 11:40:48.983027 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 11:40:48.987113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 11:40:48.987198 ==
1934 11:40:48.987265
1935 11:40:48.990024
1936 11:40:48.990107 TX Vref Scan disable
1937 11:40:48.992906 == TX Byte 0 ==
1938 11:40:48.996814 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1939 11:40:48.999856 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1940 11:40:49.003146 == TX Byte 1 ==
1941 11:40:49.006430 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1942 11:40:49.010020 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1943 11:40:49.010118 ==
1944 11:40:49.013185 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 11:40:49.019447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 11:40:49.019522 ==
1947 11:40:49.031366 TX Vref=22, minBit 2, minWin=26, winSum=447
1948 11:40:49.034762 TX Vref=24, minBit 1, minWin=27, winSum=451
1949 11:40:49.038016 TX Vref=26, minBit 1, minWin=27, winSum=452
1950 11:40:49.042105 TX Vref=28, minBit 0, minWin=28, winSum=457
1951 11:40:49.045199 TX Vref=30, minBit 0, minWin=28, winSum=454
1952 11:40:49.051676 TX Vref=32, minBit 0, minWin=28, winSum=458
1953 11:40:49.054831 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 32
1954 11:40:49.054930
1955 11:40:49.057617 Final TX Range 1 Vref 32
1956 11:40:49.057688
1957 11:40:49.057748 ==
1958 11:40:49.061094 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 11:40:49.064754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 11:40:49.064827 ==
1961 11:40:49.067823
1962 11:40:49.067918
1963 11:40:49.068026 TX Vref Scan disable
1964 11:40:49.071766 == TX Byte 0 ==
1965 11:40:49.074521 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1966 11:40:49.077642 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1967 11:40:49.081094 == TX Byte 1 ==
1968 11:40:49.084317 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1969 11:40:49.088308 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1970 11:40:49.091087
1971 11:40:49.091188 [DATLAT]
1972 11:40:49.091282 Freq=800, CH1 RK1
1973 11:40:49.091387
1974 11:40:49.094533 DATLAT Default: 0xa
1975 11:40:49.094646 0, 0xFFFF, sum = 0
1976 11:40:49.097681 1, 0xFFFF, sum = 0
1977 11:40:49.097787 2, 0xFFFF, sum = 0
1978 11:40:49.101041 3, 0xFFFF, sum = 0
1979 11:40:49.104561 4, 0xFFFF, sum = 0
1980 11:40:49.104666 5, 0xFFFF, sum = 0
1981 11:40:49.107942 6, 0xFFFF, sum = 0
1982 11:40:49.108049 7, 0xFFFF, sum = 0
1983 11:40:49.111198 8, 0xFFFF, sum = 0
1984 11:40:49.111277 9, 0x0, sum = 1
1985 11:40:49.111383 10, 0x0, sum = 2
1986 11:40:49.114514 11, 0x0, sum = 3
1987 11:40:49.114615 12, 0x0, sum = 4
1988 11:40:49.117854 best_step = 10
1989 11:40:49.117957
1990 11:40:49.118051 ==
1991 11:40:49.120970 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 11:40:49.124218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 11:40:49.124319 ==
1994 11:40:49.127766 RX Vref Scan: 0
1995 11:40:49.127878
1996 11:40:49.130814 RX Vref 0 -> 0, step: 1
1997 11:40:49.130913
1998 11:40:49.131003 RX Delay -95 -> 252, step: 8
1999 11:40:49.137746 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2000 11:40:49.141245 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2001 11:40:49.144450 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2002 11:40:49.148036 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2003 11:40:49.151101 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2004 11:40:49.157893 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2005 11:40:49.160932 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2006 11:40:49.164304 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2007 11:40:49.168264 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2008 11:40:49.170800 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2009 11:40:49.177503 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2010 11:40:49.181059 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2011 11:40:49.184338 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2012 11:40:49.187754 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2013 11:40:49.194356 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2014 11:40:49.197609 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2015 11:40:49.197718 ==
2016 11:40:49.200734 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 11:40:49.204003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 11:40:49.204097 ==
2019 11:40:49.204163 DQS Delay:
2020 11:40:49.207242 DQS0 = 0, DQS1 = 0
2021 11:40:49.207320 DQM Delay:
2022 11:40:49.210924 DQM0 = 86, DQM1 = 81
2023 11:40:49.211024 DQ Delay:
2024 11:40:49.214231 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2025 11:40:49.217531 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2026 11:40:49.221223 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2027 11:40:49.224208 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
2028 11:40:49.224290
2029 11:40:49.224366
2030 11:40:49.233897 [DQSOSCAuto] RK1, (LSB)MR18= 0x1935, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2031 11:40:49.234021 CH1 RK1: MR19=606, MR18=1935
2032 11:40:49.240756 CH1_RK1: MR19=0x606, MR18=0x1935, DQSOSC=396, MR23=63, INC=94, DEC=62
2033 11:40:49.244484 [RxdqsGatingPostProcess] freq 800
2034 11:40:49.250716 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 11:40:49.254085 Pre-setting of DQS Precalculation
2036 11:40:49.257418 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 11:40:49.263995 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 11:40:49.273739 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 11:40:49.273854
2040 11:40:49.273959
2041 11:40:49.277043 [Calibration Summary] 1600 Mbps
2042 11:40:49.277143 CH 0, Rank 0
2043 11:40:49.280518 SW Impedance : PASS
2044 11:40:49.280606 DUTY Scan : NO K
2045 11:40:49.284108 ZQ Calibration : PASS
2046 11:40:49.284184 Jitter Meter : NO K
2047 11:40:49.287424 CBT Training : PASS
2048 11:40:49.290792 Write leveling : PASS
2049 11:40:49.290875 RX DQS gating : PASS
2050 11:40:49.293475 RX DQ/DQS(RDDQC) : PASS
2051 11:40:49.297647 TX DQ/DQS : PASS
2052 11:40:49.297755 RX DATLAT : PASS
2053 11:40:49.300518 RX DQ/DQS(Engine): PASS
2054 11:40:49.304197 TX OE : NO K
2055 11:40:49.304277 All Pass.
2056 11:40:49.304343
2057 11:40:49.304406 CH 0, Rank 1
2058 11:40:49.307179 SW Impedance : PASS
2059 11:40:49.310656 DUTY Scan : NO K
2060 11:40:49.310730 ZQ Calibration : PASS
2061 11:40:49.313890 Jitter Meter : NO K
2062 11:40:49.317063 CBT Training : PASS
2063 11:40:49.317168 Write leveling : PASS
2064 11:40:49.320108 RX DQS gating : PASS
2065 11:40:49.323500 RX DQ/DQS(RDDQC) : PASS
2066 11:40:49.323588 TX DQ/DQS : PASS
2067 11:40:49.327239 RX DATLAT : PASS
2068 11:40:49.330617 RX DQ/DQS(Engine): PASS
2069 11:40:49.330702 TX OE : NO K
2070 11:40:49.330769 All Pass.
2071 11:40:49.333929
2072 11:40:49.334044 CH 1, Rank 0
2073 11:40:49.337377 SW Impedance : PASS
2074 11:40:49.337462 DUTY Scan : NO K
2075 11:40:49.339895 ZQ Calibration : PASS
2076 11:40:49.339979 Jitter Meter : NO K
2077 11:40:49.343661 CBT Training : PASS
2078 11:40:49.346745 Write leveling : PASS
2079 11:40:49.346830 RX DQS gating : PASS
2080 11:40:49.349996 RX DQ/DQS(RDDQC) : PASS
2081 11:40:49.353290 TX DQ/DQS : PASS
2082 11:40:49.353381 RX DATLAT : PASS
2083 11:40:49.356969 RX DQ/DQS(Engine): PASS
2084 11:40:49.359842 TX OE : NO K
2085 11:40:49.359925 All Pass.
2086 11:40:49.359992
2087 11:40:49.360062 CH 1, Rank 1
2088 11:40:49.363234 SW Impedance : PASS
2089 11:40:49.367007 DUTY Scan : NO K
2090 11:40:49.367096 ZQ Calibration : PASS
2091 11:40:49.370167 Jitter Meter : NO K
2092 11:40:49.373138 CBT Training : PASS
2093 11:40:49.373236 Write leveling : PASS
2094 11:40:49.376542 RX DQS gating : PASS
2095 11:40:49.379669 RX DQ/DQS(RDDQC) : PASS
2096 11:40:49.379779 TX DQ/DQS : PASS
2097 11:40:49.383493 RX DATLAT : PASS
2098 11:40:49.386983 RX DQ/DQS(Engine): PASS
2099 11:40:49.387084 TX OE : NO K
2100 11:40:49.387176 All Pass.
2101 11:40:49.389674
2102 11:40:49.389746 DramC Write-DBI off
2103 11:40:49.393004 PER_BANK_REFRESH: Hybrid Mode
2104 11:40:49.393079 TX_TRACKING: ON
2105 11:40:49.396329 [GetDramInforAfterCalByMRR] Vendor 6.
2106 11:40:49.399683 [GetDramInforAfterCalByMRR] Revision 606.
2107 11:40:49.406282 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 11:40:49.406395 MR0 0x3b3b
2109 11:40:49.406494 MR8 0x5151
2110 11:40:49.409801 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 11:40:49.409909
2112 11:40:49.413027 MR0 0x3b3b
2113 11:40:49.413132 MR8 0x5151
2114 11:40:49.416081 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 11:40:49.416198
2116 11:40:49.426367 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 11:40:49.429706 [FAST_K] Save calibration result to emmc
2118 11:40:49.432607 [FAST_K] Save calibration result to emmc
2119 11:40:49.436257 dram_init: config_dvfs: 1
2120 11:40:49.439368 dramc_set_vcore_voltage set vcore to 662500
2121 11:40:49.443011 Read voltage for 1200, 2
2122 11:40:49.443133 Vio18 = 0
2123 11:40:49.443236 Vcore = 662500
2124 11:40:49.446078 Vdram = 0
2125 11:40:49.446192 Vddq = 0
2126 11:40:49.446287 Vmddr = 0
2127 11:40:49.453067 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 11:40:49.456181 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 11:40:49.459810 MEM_TYPE=3, freq_sel=15
2130 11:40:49.462916 sv_algorithm_assistance_LP4_1600
2131 11:40:49.465972 ============ PULL DRAM RESETB DOWN ============
2132 11:40:49.469148 ========== PULL DRAM RESETB DOWN end =========
2133 11:40:49.476596 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 11:40:49.479294 ===================================
2135 11:40:49.479406 LPDDR4 DRAM CONFIGURATION
2136 11:40:49.482925 ===================================
2137 11:40:49.486006 EX_ROW_EN[0] = 0x0
2138 11:40:49.490085 EX_ROW_EN[1] = 0x0
2139 11:40:49.490206 LP4Y_EN = 0x0
2140 11:40:49.492340 WORK_FSP = 0x0
2141 11:40:49.492452 WL = 0x4
2142 11:40:49.495560 RL = 0x4
2143 11:40:49.495671 BL = 0x2
2144 11:40:49.499455 RPST = 0x0
2145 11:40:49.499561 RD_PRE = 0x0
2146 11:40:49.502278 WR_PRE = 0x1
2147 11:40:49.502400 WR_PST = 0x0
2148 11:40:49.505853 DBI_WR = 0x0
2149 11:40:49.505970 DBI_RD = 0x0
2150 11:40:49.508872 OTF = 0x1
2151 11:40:49.512084 ===================================
2152 11:40:49.515814 ===================================
2153 11:40:49.515926 ANA top config
2154 11:40:49.519377 ===================================
2155 11:40:49.522152 DLL_ASYNC_EN = 0
2156 11:40:49.525916 ALL_SLAVE_EN = 0
2157 11:40:49.528959 NEW_RANK_MODE = 1
2158 11:40:49.529068 DLL_IDLE_MODE = 1
2159 11:40:49.532122 LP45_APHY_COMB_EN = 1
2160 11:40:49.535396 TX_ODT_DIS = 1
2161 11:40:49.538734 NEW_8X_MODE = 1
2162 11:40:49.541764 ===================================
2163 11:40:49.545305 ===================================
2164 11:40:49.548968 data_rate = 2400
2165 11:40:49.549075 CKR = 1
2166 11:40:49.551675 DQ_P2S_RATIO = 8
2167 11:40:49.555538 ===================================
2168 11:40:49.558394 CA_P2S_RATIO = 8
2169 11:40:49.561732 DQ_CA_OPEN = 0
2170 11:40:49.565370 DQ_SEMI_OPEN = 0
2171 11:40:49.568495 CA_SEMI_OPEN = 0
2172 11:40:49.568605 CA_FULL_RATE = 0
2173 11:40:49.571792 DQ_CKDIV4_EN = 0
2174 11:40:49.575860 CA_CKDIV4_EN = 0
2175 11:40:49.578702 CA_PREDIV_EN = 0
2176 11:40:49.582396 PH8_DLY = 17
2177 11:40:49.585235 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 11:40:49.585346 DQ_AAMCK_DIV = 4
2179 11:40:49.588965 CA_AAMCK_DIV = 4
2180 11:40:49.591589 CA_ADMCK_DIV = 4
2181 11:40:49.595286 DQ_TRACK_CA_EN = 0
2182 11:40:49.598586 CA_PICK = 1200
2183 11:40:49.601769 CA_MCKIO = 1200
2184 11:40:49.605452 MCKIO_SEMI = 0
2185 11:40:49.608267 PLL_FREQ = 2366
2186 11:40:49.608351 DQ_UI_PI_RATIO = 32
2187 11:40:49.611636 CA_UI_PI_RATIO = 0
2188 11:40:49.615083 ===================================
2189 11:40:49.618281 ===================================
2190 11:40:49.621573 memory_type:LPDDR4
2191 11:40:49.624719 GP_NUM : 10
2192 11:40:49.624798 SRAM_EN : 1
2193 11:40:49.628008 MD32_EN : 0
2194 11:40:49.631544 ===================================
2195 11:40:49.634567 [ANA_INIT] >>>>>>>>>>>>>>
2196 11:40:49.634698 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 11:40:49.638021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 11:40:49.641545 ===================================
2199 11:40:49.644681 data_rate = 2400,PCW = 0X5b00
2200 11:40:49.647923 ===================================
2201 11:40:49.651749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 11:40:49.658138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 11:40:49.664853 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 11:40:49.668386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 11:40:49.671151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 11:40:49.674577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 11:40:49.677638 [ANA_INIT] flow start
2208 11:40:49.677745 [ANA_INIT] PLL >>>>>>>>
2209 11:40:49.681632 [ANA_INIT] PLL <<<<<<<<
2210 11:40:49.684347 [ANA_INIT] MIDPI >>>>>>>>
2211 11:40:49.684426 [ANA_INIT] MIDPI <<<<<<<<
2212 11:40:49.687600 [ANA_INIT] DLL >>>>>>>>
2213 11:40:49.691656 [ANA_INIT] DLL <<<<<<<<
2214 11:40:49.691765 [ANA_INIT] flow end
2215 11:40:49.697840 ============ LP4 DIFF to SE enter ============
2216 11:40:49.701302 ============ LP4 DIFF to SE exit ============
2217 11:40:49.704650 [ANA_INIT] <<<<<<<<<<<<<
2218 11:40:49.707361 [Flow] Enable top DCM control >>>>>
2219 11:40:49.710754 [Flow] Enable top DCM control <<<<<
2220 11:40:49.710830 Enable DLL master slave shuffle
2221 11:40:49.717856 ==============================================================
2222 11:40:49.720941 Gating Mode config
2223 11:40:49.724368 ==============================================================
2224 11:40:49.727490 Config description:
2225 11:40:49.737508 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 11:40:49.744190 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 11:40:49.747342 SELPH_MODE 0: By rank 1: By Phase
2228 11:40:49.753910 ==============================================================
2229 11:40:49.757168 GAT_TRACK_EN = 1
2230 11:40:49.760506 RX_GATING_MODE = 2
2231 11:40:49.764150 RX_GATING_TRACK_MODE = 2
2232 11:40:49.767043 SELPH_MODE = 1
2233 11:40:49.770619 PICG_EARLY_EN = 1
2234 11:40:49.770731 VALID_LAT_VALUE = 1
2235 11:40:49.777165 ==============================================================
2236 11:40:49.780419 Enter into Gating configuration >>>>
2237 11:40:49.783736 Exit from Gating configuration <<<<
2238 11:40:49.787139 Enter into DVFS_PRE_config >>>>>
2239 11:40:49.796779 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 11:40:49.800491 Exit from DVFS_PRE_config <<<<<
2241 11:40:49.803644 Enter into PICG configuration >>>>
2242 11:40:49.807183 Exit from PICG configuration <<<<
2243 11:40:49.810615 [RX_INPUT] configuration >>>>>
2244 11:40:49.813540 [RX_INPUT] configuration <<<<<
2245 11:40:49.816808 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 11:40:49.823417 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 11:40:49.830001 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 11:40:49.837010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 11:40:49.843331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 11:40:49.849789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 11:40:49.853170 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 11:40:49.856560 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 11:40:49.859970 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 11:40:49.866474 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 11:40:49.869832 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 11:40:49.873616 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 11:40:49.876518 ===================================
2258 11:40:49.879504 LPDDR4 DRAM CONFIGURATION
2259 11:40:49.883234 ===================================
2260 11:40:49.883319 EX_ROW_EN[0] = 0x0
2261 11:40:49.886371 EX_ROW_EN[1] = 0x0
2262 11:40:49.890204 LP4Y_EN = 0x0
2263 11:40:49.890289 WORK_FSP = 0x0
2264 11:40:49.893355 WL = 0x4
2265 11:40:49.893439 RL = 0x4
2266 11:40:49.896187 BL = 0x2
2267 11:40:49.896271 RPST = 0x0
2268 11:40:49.899525 RD_PRE = 0x0
2269 11:40:49.899608 WR_PRE = 0x1
2270 11:40:49.902874 WR_PST = 0x0
2271 11:40:49.902957 DBI_WR = 0x0
2272 11:40:49.906099 DBI_RD = 0x0
2273 11:40:49.906184 OTF = 0x1
2274 11:40:49.909696 ===================================
2275 11:40:49.913223 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 11:40:49.919859 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 11:40:49.923354 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 11:40:49.926120 ===================================
2279 11:40:49.929620 LPDDR4 DRAM CONFIGURATION
2280 11:40:49.932882 ===================================
2281 11:40:49.932966 EX_ROW_EN[0] = 0x10
2282 11:40:49.936029 EX_ROW_EN[1] = 0x0
2283 11:40:49.936125 LP4Y_EN = 0x0
2284 11:40:49.939783 WORK_FSP = 0x0
2285 11:40:49.939867 WL = 0x4
2286 11:40:49.943038 RL = 0x4
2287 11:40:49.945957 BL = 0x2
2288 11:40:49.946041 RPST = 0x0
2289 11:40:49.949081 RD_PRE = 0x0
2290 11:40:49.949166 WR_PRE = 0x1
2291 11:40:49.952879 WR_PST = 0x0
2292 11:40:49.952963 DBI_WR = 0x0
2293 11:40:49.955826 DBI_RD = 0x0
2294 11:40:49.955936 OTF = 0x1
2295 11:40:49.959373 ===================================
2296 11:40:49.965674 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 11:40:49.965765 ==
2298 11:40:49.969113 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 11:40:49.973244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 11:40:49.973326 ==
2301 11:40:49.976084 [Duty_Offset_Calibration]
2302 11:40:49.979661 B0:2 B1:0 CA:4
2303 11:40:49.979739
2304 11:40:49.982493 [DutyScan_Calibration_Flow] k_type=0
2305 11:40:49.989587
2306 11:40:49.989664 ==CLK 0==
2307 11:40:49.993136 Final CLK duty delay cell = -4
2308 11:40:49.997072 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2309 11:40:49.999834 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2310 11:40:50.003097 [-4] AVG Duty = 4953%(X100)
2311 11:40:50.003183
2312 11:40:50.006848 CH0 CLK Duty spec in!! Max-Min= 218%
2313 11:40:50.009929 [DutyScan_Calibration_Flow] ====Done====
2314 11:40:50.010001
2315 11:40:50.013138 [DutyScan_Calibration_Flow] k_type=1
2316 11:40:50.029482
2317 11:40:50.029564 ==DQS 0 ==
2318 11:40:50.032740 Final DQS duty delay cell = 0
2319 11:40:50.036212 [0] MAX Duty = 5156%(X100), DQS PI = 18
2320 11:40:50.039516 [0] MIN Duty = 5093%(X100), DQS PI = 0
2321 11:40:50.039626 [0] AVG Duty = 5124%(X100)
2322 11:40:50.042527
2323 11:40:50.042636 ==DQS 1 ==
2324 11:40:50.045776 Final DQS duty delay cell = 0
2325 11:40:50.049230 [0] MAX Duty = 5125%(X100), DQS PI = 48
2326 11:40:50.052890 [0] MIN Duty = 5000%(X100), DQS PI = 0
2327 11:40:50.052963 [0] AVG Duty = 5062%(X100)
2328 11:40:50.055991
2329 11:40:50.059125 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2330 11:40:50.059198
2331 11:40:50.062819 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2332 11:40:50.065875 [DutyScan_Calibration_Flow] ====Done====
2333 11:40:50.065974
2334 11:40:50.069335 [DutyScan_Calibration_Flow] k_type=3
2335 11:40:50.085873
2336 11:40:50.085981 ==DQM 0 ==
2337 11:40:50.089142 Final DQM duty delay cell = 0
2338 11:40:50.092378 [0] MAX Duty = 5125%(X100), DQS PI = 20
2339 11:40:50.095805 [0] MIN Duty = 4844%(X100), DQS PI = 52
2340 11:40:50.099154 [0] AVG Duty = 4984%(X100)
2341 11:40:50.099265
2342 11:40:50.099370 ==DQM 1 ==
2343 11:40:50.102252 Final DQM duty delay cell = 0
2344 11:40:50.105862 [0] MAX Duty = 4969%(X100), DQS PI = 2
2345 11:40:50.109216 [0] MIN Duty = 4876%(X100), DQS PI = 28
2346 11:40:50.112111 [0] AVG Duty = 4922%(X100)
2347 11:40:50.112187
2348 11:40:50.115286 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2349 11:40:50.115388
2350 11:40:50.119329 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2351 11:40:50.122188 [DutyScan_Calibration_Flow] ====Done====
2352 11:40:50.122273
2353 11:40:50.125201 [DutyScan_Calibration_Flow] k_type=2
2354 11:40:50.142006
2355 11:40:50.142102 ==DQ 0 ==
2356 11:40:50.145482 Final DQ duty delay cell = 0
2357 11:40:50.148793 [0] MAX Duty = 5125%(X100), DQS PI = 18
2358 11:40:50.151919 [0] MIN Duty = 4969%(X100), DQS PI = 52
2359 11:40:50.155436 [0] AVG Duty = 5047%(X100)
2360 11:40:50.155545
2361 11:40:50.155649 ==DQ 1 ==
2362 11:40:50.158414 Final DQ duty delay cell = 0
2363 11:40:50.161992 [0] MAX Duty = 5125%(X100), DQS PI = 4
2364 11:40:50.165280 [0] MIN Duty = 4938%(X100), DQS PI = 16
2365 11:40:50.165388 [0] AVG Duty = 5031%(X100)
2366 11:40:50.168740
2367 11:40:50.171887 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2368 11:40:50.172000
2369 11:40:50.174886 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2370 11:40:50.178396 [DutyScan_Calibration_Flow] ====Done====
2371 11:40:50.178500 ==
2372 11:40:50.181825 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 11:40:50.185209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 11:40:50.185327 ==
2375 11:40:50.188793 [Duty_Offset_Calibration]
2376 11:40:50.188909 B0:0 B1:-1 CA:3
2377 11:40:50.189004
2378 11:40:50.191962 [DutyScan_Calibration_Flow] k_type=0
2379 11:40:50.201307
2380 11:40:50.201427 ==CLK 0==
2381 11:40:50.204483 Final CLK duty delay cell = -4
2382 11:40:50.208043 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2383 11:40:50.210984 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2384 11:40:50.214375 [-4] AVG Duty = 4938%(X100)
2385 11:40:50.214478
2386 11:40:50.217888 CH1 CLK Duty spec in!! Max-Min= 124%
2387 11:40:50.221324 [DutyScan_Calibration_Flow] ====Done====
2388 11:40:50.221427
2389 11:40:50.224167 [DutyScan_Calibration_Flow] k_type=1
2390 11:40:50.241047
2391 11:40:50.241168 ==DQS 0 ==
2392 11:40:50.244492 Final DQS duty delay cell = 0
2393 11:40:50.247875 [0] MAX Duty = 5187%(X100), DQS PI = 28
2394 11:40:50.250933 [0] MIN Duty = 4907%(X100), DQS PI = 38
2395 11:40:50.254275 [0] AVG Duty = 5047%(X100)
2396 11:40:50.254375
2397 11:40:50.254467 ==DQS 1 ==
2398 11:40:50.257568 Final DQS duty delay cell = 0
2399 11:40:50.260559 [0] MAX Duty = 5156%(X100), DQS PI = 8
2400 11:40:50.264339 [0] MIN Duty = 5031%(X100), DQS PI = 24
2401 11:40:50.267359 [0] AVG Duty = 5093%(X100)
2402 11:40:50.267461
2403 11:40:50.270756 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2404 11:40:50.270857
2405 11:40:50.273892 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2406 11:40:50.277518 [DutyScan_Calibration_Flow] ====Done====
2407 11:40:50.277619
2408 11:40:50.280840 [DutyScan_Calibration_Flow] k_type=3
2409 11:40:50.297235
2410 11:40:50.297344 ==DQM 0 ==
2411 11:40:50.301013 Final DQM duty delay cell = 0
2412 11:40:50.304612 [0] MAX Duty = 5031%(X100), DQS PI = 28
2413 11:40:50.308296 [0] MIN Duty = 4813%(X100), DQS PI = 38
2414 11:40:50.308380 [0] AVG Duty = 4922%(X100)
2415 11:40:50.310872
2416 11:40:50.310972 ==DQM 1 ==
2417 11:40:50.314004 Final DQM duty delay cell = 0
2418 11:40:50.317853 [0] MAX Duty = 5000%(X100), DQS PI = 34
2419 11:40:50.321526 [0] MIN Duty = 4844%(X100), DQS PI = 0
2420 11:40:50.321611 [0] AVG Duty = 4922%(X100)
2421 11:40:50.321678
2422 11:40:50.327695 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2423 11:40:50.327779
2424 11:40:50.330945 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2425 11:40:50.333922 [DutyScan_Calibration_Flow] ====Done====
2426 11:40:50.334006
2427 11:40:50.337936 [DutyScan_Calibration_Flow] k_type=2
2428 11:40:50.353542
2429 11:40:50.353660 ==DQ 0 ==
2430 11:40:50.357205 Final DQ duty delay cell = -4
2431 11:40:50.361031 [-4] MAX Duty = 5031%(X100), DQS PI = 28
2432 11:40:50.364183 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2433 11:40:50.367352 [-4] AVG Duty = 4937%(X100)
2434 11:40:50.367427
2435 11:40:50.367490 ==DQ 1 ==
2436 11:40:50.370472 Final DQ duty delay cell = 4
2437 11:40:50.373962 [4] MAX Duty = 5156%(X100), DQS PI = 10
2438 11:40:50.377286 [4] MIN Duty = 5031%(X100), DQS PI = 62
2439 11:40:50.380618 [4] AVG Duty = 5093%(X100)
2440 11:40:50.380710
2441 11:40:50.383857 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2442 11:40:50.383946
2443 11:40:50.386935 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2444 11:40:50.390369 [DutyScan_Calibration_Flow] ====Done====
2445 11:40:50.393365 nWR fixed to 30
2446 11:40:50.396923 [ModeRegInit_LP4] CH0 RK0
2447 11:40:50.397003 [ModeRegInit_LP4] CH0 RK1
2448 11:40:50.400949 [ModeRegInit_LP4] CH1 RK0
2449 11:40:50.403106 [ModeRegInit_LP4] CH1 RK1
2450 11:40:50.403193 match AC timing 7
2451 11:40:50.409850 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 11:40:50.413603 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 11:40:50.416731 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 11:40:50.423050 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 11:40:50.426780 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 11:40:50.426858 ==
2457 11:40:50.429768 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 11:40:50.433910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 11:40:50.433996 ==
2460 11:40:50.440018 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 11:40:50.446442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 11:40:50.454598 [CA 0] Center 39 (9~70) winsize 62
2463 11:40:50.457629 [CA 1] Center 39 (9~69) winsize 61
2464 11:40:50.460941 [CA 2] Center 35 (5~66) winsize 62
2465 11:40:50.464016 [CA 3] Center 35 (5~66) winsize 62
2466 11:40:50.467424 [CA 4] Center 33 (3~64) winsize 62
2467 11:40:50.471139 [CA 5] Center 33 (3~63) winsize 61
2468 11:40:50.471225
2469 11:40:50.473826 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2470 11:40:50.473912
2471 11:40:50.477124 [CATrainingPosCal] consider 1 rank data
2472 11:40:50.480835 u2DelayCellTimex100 = 270/100 ps
2473 11:40:50.483671 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2474 11:40:50.490718 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2475 11:40:50.493917 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 11:40:50.497075 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 11:40:50.500380 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2478 11:40:50.503504 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2479 11:40:50.503587
2480 11:40:50.507030 CA PerBit enable=1, Macro0, CA PI delay=33
2481 11:40:50.507112
2482 11:40:50.510340 [CBTSetCACLKResult] CA Dly = 33
2483 11:40:50.513725 CS Dly: 7 (0~38)
2484 11:40:50.513808 ==
2485 11:40:50.516832 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 11:40:50.520239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 11:40:50.520323 ==
2488 11:40:50.527046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 11:40:50.530608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 11:40:50.539848 [CA 0] Center 39 (9~70) winsize 62
2491 11:40:50.543383 [CA 1] Center 39 (9~70) winsize 62
2492 11:40:50.546267 [CA 2] Center 35 (5~66) winsize 62
2493 11:40:50.550347 [CA 3] Center 35 (5~66) winsize 62
2494 11:40:50.553246 [CA 4] Center 34 (4~65) winsize 62
2495 11:40:50.556452 [CA 5] Center 33 (3~64) winsize 62
2496 11:40:50.556542
2497 11:40:50.559789 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2498 11:40:50.559885
2499 11:40:50.563039 [CATrainingPosCal] consider 2 rank data
2500 11:40:50.566587 u2DelayCellTimex100 = 270/100 ps
2501 11:40:50.569829 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2502 11:40:50.576526 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2503 11:40:50.579717 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 11:40:50.582898 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 11:40:50.586510 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2506 11:40:50.589882 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2507 11:40:50.589968
2508 11:40:50.593862 CA PerBit enable=1, Macro0, CA PI delay=33
2509 11:40:50.593960
2510 11:40:50.596152 [CBTSetCACLKResult] CA Dly = 33
2511 11:40:50.596235 CS Dly: 8 (0~41)
2512 11:40:50.596302
2513 11:40:50.602686 ----->DramcWriteLeveling(PI) begin...
2514 11:40:50.602806 ==
2515 11:40:50.606290 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 11:40:50.609248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 11:40:50.609337 ==
2518 11:40:50.612917 Write leveling (Byte 0): 32 => 32
2519 11:40:50.615972 Write leveling (Byte 1): 28 => 28
2520 11:40:50.619452 DramcWriteLeveling(PI) end<-----
2521 11:40:50.619538
2522 11:40:50.619605 ==
2523 11:40:50.622671 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 11:40:50.625892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 11:40:50.625980 ==
2526 11:40:50.629575 [Gating] SW mode calibration
2527 11:40:50.636005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 11:40:50.643109 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 11:40:50.645782 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2530 11:40:50.649746 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2531 11:40:50.655846 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 11:40:50.659509 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:40:50.663169 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 11:40:50.669572 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 11:40:50.672335 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2536 11:40:50.675867 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2537 11:40:50.682334 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
2538 11:40:50.685710 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2539 11:40:50.689046 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:40:50.695754 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:40:50.698907 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 11:40:50.702294 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 11:40:50.706185 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
2544 11:40:50.712302 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2545 11:40:50.715493 1 1 0 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2546 11:40:50.718915 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2547 11:40:50.726182 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:40:50.729371 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:40:50.732224 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 11:40:50.738753 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 11:40:50.742065 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 11:40:50.745525 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 11:40:50.752293 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 11:40:50.755129 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 11:40:50.758807 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:40:50.765433 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:40:50.768669 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:40:50.772493 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:40:50.778748 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:40:50.781976 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:40:50.785123 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:40:50.791663 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:40:50.795155 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:40:50.798634 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:40:50.805210 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:40:50.808255 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:40:50.811599 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:40:50.818942 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2569 11:40:50.819077 Total UI for P1: 0, mck2ui 16
2570 11:40:50.824999 best dqsien dly found for B0: ( 1, 3, 26)
2571 11:40:50.828590 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 11:40:50.831754 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 11:40:50.838320 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 11:40:50.838480 Total UI for P1: 0, mck2ui 16
2575 11:40:50.845571 best dqsien dly found for B1: ( 1, 4, 2)
2576 11:40:50.848539 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2577 11:40:50.851469 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2578 11:40:50.851579
2579 11:40:50.854697 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2580 11:40:50.858117 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2581 11:40:50.861263 [Gating] SW calibration Done
2582 11:40:50.861394 ==
2583 11:40:50.864921 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 11:40:50.868459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 11:40:50.868562 ==
2586 11:40:50.871644 RX Vref Scan: 0
2587 11:40:50.871721
2588 11:40:50.871785 RX Vref 0 -> 0, step: 1
2589 11:40:50.871846
2590 11:40:50.875000 RX Delay -40 -> 252, step: 8
2591 11:40:50.877967 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2592 11:40:50.884407 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2593 11:40:50.887680 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2594 11:40:50.891666 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2595 11:40:50.894334 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2596 11:40:50.897796 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2597 11:40:50.904857 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2598 11:40:50.907912 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2599 11:40:50.910821 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2600 11:40:50.914459 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2601 11:40:50.917832 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2602 11:40:50.924697 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2603 11:40:50.928012 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2604 11:40:50.931177 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2605 11:40:50.934115 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2606 11:40:50.937622 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2607 11:40:50.937772 ==
2608 11:40:50.941085 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 11:40:50.947874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 11:40:50.948015 ==
2611 11:40:50.948103 DQS Delay:
2612 11:40:50.950919 DQS0 = 0, DQS1 = 0
2613 11:40:50.951036 DQM Delay:
2614 11:40:50.954202 DQM0 = 118, DQM1 = 108
2615 11:40:50.954321 DQ Delay:
2616 11:40:50.957655 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2617 11:40:50.960840 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2618 11:40:50.964099 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2619 11:40:50.967748 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2620 11:40:50.967868
2621 11:40:50.967967
2622 11:40:50.968064 ==
2623 11:40:50.970883 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 11:40:50.977208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 11:40:50.977324 ==
2626 11:40:50.977436
2627 11:40:50.977533
2628 11:40:50.977644 TX Vref Scan disable
2629 11:40:50.980519 == TX Byte 0 ==
2630 11:40:50.983880 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2631 11:40:50.990727 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2632 11:40:50.990861 == TX Byte 1 ==
2633 11:40:50.993960 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2634 11:40:51.000477 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2635 11:40:51.000605 ==
2636 11:40:51.004079 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 11:40:51.007021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 11:40:51.007131 ==
2639 11:40:51.018930 TX Vref=22, minBit 0, minWin=25, winSum=417
2640 11:40:51.022405 TX Vref=24, minBit 14, minWin=25, winSum=420
2641 11:40:51.025680 TX Vref=26, minBit 10, minWin=25, winSum=427
2642 11:40:51.028746 TX Vref=28, minBit 1, minWin=26, winSum=430
2643 11:40:51.032458 TX Vref=30, minBit 12, minWin=26, winSum=433
2644 11:40:51.038382 TX Vref=32, minBit 2, minWin=26, winSum=430
2645 11:40:51.042086 [TxChooseVref] Worse bit 12, Min win 26, Win sum 433, Final Vref 30
2646 11:40:51.042212
2647 11:40:51.045238 Final TX Range 1 Vref 30
2648 11:40:51.045341
2649 11:40:51.045434 ==
2650 11:40:51.048326 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 11:40:51.051773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 11:40:51.054915 ==
2653 11:40:51.055013
2654 11:40:51.055110
2655 11:40:51.055202 TX Vref Scan disable
2656 11:40:51.059201 == TX Byte 0 ==
2657 11:40:51.062213 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2658 11:40:51.068824 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2659 11:40:51.068916 == TX Byte 1 ==
2660 11:40:51.071838 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2661 11:40:51.078736 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2662 11:40:51.078827
2663 11:40:51.078893 [DATLAT]
2664 11:40:51.078954 Freq=1200, CH0 RK0
2665 11:40:51.079019
2666 11:40:51.081787 DATLAT Default: 0xd
2667 11:40:51.081865 0, 0xFFFF, sum = 0
2668 11:40:51.085085 1, 0xFFFF, sum = 0
2669 11:40:51.088949 2, 0xFFFF, sum = 0
2670 11:40:51.089024 3, 0xFFFF, sum = 0
2671 11:40:51.091768 4, 0xFFFF, sum = 0
2672 11:40:51.091869 5, 0xFFFF, sum = 0
2673 11:40:51.095326 6, 0xFFFF, sum = 0
2674 11:40:51.095402 7, 0xFFFF, sum = 0
2675 11:40:51.098698 8, 0xFFFF, sum = 0
2676 11:40:51.098776 9, 0xFFFF, sum = 0
2677 11:40:51.102049 10, 0xFFFF, sum = 0
2678 11:40:51.102122 11, 0xFFFF, sum = 0
2679 11:40:51.104955 12, 0x0, sum = 1
2680 11:40:51.105027 13, 0x0, sum = 2
2681 11:40:51.108627 14, 0x0, sum = 3
2682 11:40:51.108730 15, 0x0, sum = 4
2683 11:40:51.111675 best_step = 13
2684 11:40:51.111755
2685 11:40:51.111820 ==
2686 11:40:51.115091 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 11:40:51.118984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 11:40:51.119064 ==
2689 11:40:51.119128 RX Vref Scan: 1
2690 11:40:51.119190
2691 11:40:51.122213 Set Vref Range= 32 -> 127
2692 11:40:51.122299
2693 11:40:51.125249 RX Vref 32 -> 127, step: 1
2694 11:40:51.125335
2695 11:40:51.128302 RX Delay -21 -> 252, step: 4
2696 11:40:51.128388
2697 11:40:51.131880 Set Vref, RX VrefLevel [Byte0]: 32
2698 11:40:51.134928 [Byte1]: 32
2699 11:40:51.135015
2700 11:40:51.138168 Set Vref, RX VrefLevel [Byte0]: 33
2701 11:40:51.141902 [Byte1]: 33
2702 11:40:51.145704
2703 11:40:51.145795 Set Vref, RX VrefLevel [Byte0]: 34
2704 11:40:51.149155 [Byte1]: 34
2705 11:40:51.153337
2706 11:40:51.153428 Set Vref, RX VrefLevel [Byte0]: 35
2707 11:40:51.156860 [Byte1]: 35
2708 11:40:51.161337
2709 11:40:51.161432 Set Vref, RX VrefLevel [Byte0]: 36
2710 11:40:51.164352 [Byte1]: 36
2711 11:40:51.169026
2712 11:40:51.169120 Set Vref, RX VrefLevel [Byte0]: 37
2713 11:40:51.172464 [Byte1]: 37
2714 11:40:51.176929
2715 11:40:51.177021 Set Vref, RX VrefLevel [Byte0]: 38
2716 11:40:51.180520 [Byte1]: 38
2717 11:40:51.185258
2718 11:40:51.185351 Set Vref, RX VrefLevel [Byte0]: 39
2719 11:40:51.188291 [Byte1]: 39
2720 11:40:51.193267
2721 11:40:51.193358 Set Vref, RX VrefLevel [Byte0]: 40
2722 11:40:51.196046 [Byte1]: 40
2723 11:40:51.201139
2724 11:40:51.201244 Set Vref, RX VrefLevel [Byte0]: 41
2725 11:40:51.204424 [Byte1]: 41
2726 11:40:51.208671
2727 11:40:51.208792 Set Vref, RX VrefLevel [Byte0]: 42
2728 11:40:51.212444 [Byte1]: 42
2729 11:40:51.216629
2730 11:40:51.216730 Set Vref, RX VrefLevel [Byte0]: 43
2731 11:40:51.220024 [Byte1]: 43
2732 11:40:51.225194
2733 11:40:51.225304 Set Vref, RX VrefLevel [Byte0]: 44
2734 11:40:51.228057 [Byte1]: 44
2735 11:40:51.232316
2736 11:40:51.232425 Set Vref, RX VrefLevel [Byte0]: 45
2737 11:40:51.235565 [Byte1]: 45
2738 11:40:51.240763
2739 11:40:51.240900 Set Vref, RX VrefLevel [Byte0]: 46
2740 11:40:51.243838 [Byte1]: 46
2741 11:40:51.248414
2742 11:40:51.248534 Set Vref, RX VrefLevel [Byte0]: 47
2743 11:40:51.251798 [Byte1]: 47
2744 11:40:51.256546
2745 11:40:51.256741 Set Vref, RX VrefLevel [Byte0]: 48
2746 11:40:51.259456 [Byte1]: 48
2747 11:40:51.264547
2748 11:40:51.264699 Set Vref, RX VrefLevel [Byte0]: 49
2749 11:40:51.267430 [Byte1]: 49
2750 11:40:51.272107
2751 11:40:51.272234 Set Vref, RX VrefLevel [Byte0]: 50
2752 11:40:51.275412 [Byte1]: 50
2753 11:40:51.279925
2754 11:40:51.280025 Set Vref, RX VrefLevel [Byte0]: 51
2755 11:40:51.283665 [Byte1]: 51
2756 11:40:51.288536
2757 11:40:51.288627 Set Vref, RX VrefLevel [Byte0]: 52
2758 11:40:51.291766 [Byte1]: 52
2759 11:40:51.296014
2760 11:40:51.296133 Set Vref, RX VrefLevel [Byte0]: 53
2761 11:40:51.299523 [Byte1]: 53
2762 11:40:51.303777
2763 11:40:51.303867 Set Vref, RX VrefLevel [Byte0]: 54
2764 11:40:51.307524 [Byte1]: 54
2765 11:40:51.311999
2766 11:40:51.312115 Set Vref, RX VrefLevel [Byte0]: 55
2767 11:40:51.314956 [Byte1]: 55
2768 11:40:51.319530
2769 11:40:51.319620 Set Vref, RX VrefLevel [Byte0]: 56
2770 11:40:51.323164 [Byte1]: 56
2771 11:40:51.327991
2772 11:40:51.328092 Set Vref, RX VrefLevel [Byte0]: 57
2773 11:40:51.331193 [Byte1]: 57
2774 11:40:51.335959
2775 11:40:51.336078 Set Vref, RX VrefLevel [Byte0]: 58
2776 11:40:51.339465 [Byte1]: 58
2777 11:40:51.343306
2778 11:40:51.343403 Set Vref, RX VrefLevel [Byte0]: 59
2779 11:40:51.346839 [Byte1]: 59
2780 11:40:51.351455
2781 11:40:51.351550 Set Vref, RX VrefLevel [Byte0]: 60
2782 11:40:51.354757 [Byte1]: 60
2783 11:40:51.359156
2784 11:40:51.359251 Set Vref, RX VrefLevel [Byte0]: 61
2785 11:40:51.362762 [Byte1]: 61
2786 11:40:51.367048
2787 11:40:51.367143 Set Vref, RX VrefLevel [Byte0]: 62
2788 11:40:51.370556 [Byte1]: 62
2789 11:40:51.375549
2790 11:40:51.375649 Set Vref, RX VrefLevel [Byte0]: 63
2791 11:40:51.378230 [Byte1]: 63
2792 11:40:51.383512
2793 11:40:51.383607 Set Vref, RX VrefLevel [Byte0]: 64
2794 11:40:51.386194 [Byte1]: 64
2795 11:40:51.391078
2796 11:40:51.391173 Set Vref, RX VrefLevel [Byte0]: 65
2797 11:40:51.394547 [Byte1]: 65
2798 11:40:51.399168
2799 11:40:51.399262 Set Vref, RX VrefLevel [Byte0]: 66
2800 11:40:51.402196 [Byte1]: 66
2801 11:40:51.406744
2802 11:40:51.406843 Set Vref, RX VrefLevel [Byte0]: 67
2803 11:40:51.410247 [Byte1]: 67
2804 11:40:51.415098
2805 11:40:51.415193 Set Vref, RX VrefLevel [Byte0]: 68
2806 11:40:51.418008 [Byte1]: 68
2807 11:40:51.422676
2808 11:40:51.422769 Set Vref, RX VrefLevel [Byte0]: 69
2809 11:40:51.425877 [Byte1]: 69
2810 11:40:51.430735
2811 11:40:51.430832 Set Vref, RX VrefLevel [Byte0]: 70
2812 11:40:51.434161 [Byte1]: 70
2813 11:40:51.438496
2814 11:40:51.438601 Final RX Vref Byte 0 = 51 to rank0
2815 11:40:51.441717 Final RX Vref Byte 1 = 59 to rank0
2816 11:40:51.444974 Final RX Vref Byte 0 = 51 to rank1
2817 11:40:51.449060 Final RX Vref Byte 1 = 59 to rank1==
2818 11:40:51.452238 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 11:40:51.458726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 11:40:51.458855 ==
2821 11:40:51.458953 DQS Delay:
2822 11:40:51.461683 DQS0 = 0, DQS1 = 0
2823 11:40:51.461787 DQM Delay:
2824 11:40:51.461870 DQM0 = 117, DQM1 = 105
2825 11:40:51.465590 DQ Delay:
2826 11:40:51.468706 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2827 11:40:51.471535 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2828 11:40:51.475057 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2829 11:40:51.478643 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2830 11:40:51.478723
2831 11:40:51.478822
2832 11:40:51.488371 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2833 11:40:51.488486 CH0 RK0: MR19=403, MR18=1FC
2834 11:40:51.495024 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2835 11:40:51.495125
2836 11:40:51.498523 ----->DramcWriteLeveling(PI) begin...
2837 11:40:51.498606 ==
2838 11:40:51.501940 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 11:40:51.505005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 11:40:51.508477 ==
2841 11:40:51.508555 Write leveling (Byte 0): 31 => 31
2842 11:40:51.511923 Write leveling (Byte 1): 27 => 27
2843 11:40:51.515223 DramcWriteLeveling(PI) end<-----
2844 11:40:51.515325
2845 11:40:51.515396 ==
2846 11:40:51.518310 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 11:40:51.524693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 11:40:51.524789 ==
2849 11:40:51.528406 [Gating] SW mode calibration
2850 11:40:51.534412 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 11:40:51.537865 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 11:40:51.544623 0 15 0 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
2853 11:40:51.548054 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2854 11:40:51.551615 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 11:40:51.558095 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:40:51.561131 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 11:40:51.564417 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 11:40:51.567678 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2859 11:40:51.574859 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
2860 11:40:51.577715 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
2861 11:40:51.581158 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:40:51.588067 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:40:51.591108 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 11:40:51.594819 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 11:40:51.601121 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 11:40:51.604277 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
2867 11:40:51.607831 1 0 28 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
2868 11:40:51.614229 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
2869 11:40:51.617750 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:40:51.620708 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 11:40:51.627745 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:40:51.630552 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:40:51.634405 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 11:40:51.641492 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2875 11:40:51.644200 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2876 11:40:51.647379 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2877 11:40:51.654147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:40:51.657384 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:40:51.660590 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:40:51.667361 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:40:51.671006 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:40:51.673714 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:40:51.680895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:40:51.683956 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:40:51.687000 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:40:51.693793 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:40:51.697031 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:40:51.700315 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:40:51.707107 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2890 11:40:51.710441 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2891 11:40:51.713401 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2892 11:40:51.717154 Total UI for P1: 0, mck2ui 16
2893 11:40:51.720471 best dqsien dly found for B0: ( 1, 3, 22)
2894 11:40:51.726927 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 11:40:51.730178 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 11:40:51.733272 Total UI for P1: 0, mck2ui 16
2897 11:40:51.736749 best dqsien dly found for B1: ( 1, 4, 0)
2898 11:40:51.739928 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2899 11:40:51.743284 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2900 11:40:51.743384
2901 11:40:51.746616 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2902 11:40:51.750230 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2903 11:40:51.753678 [Gating] SW calibration Done
2904 11:40:51.753788 ==
2905 11:40:51.756963 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 11:40:51.760250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 11:40:51.760341 ==
2908 11:40:51.763648 RX Vref Scan: 0
2909 11:40:51.763766
2910 11:40:51.766644 RX Vref 0 -> 0, step: 1
2911 11:40:51.766742
2912 11:40:51.766810 RX Delay -40 -> 252, step: 8
2913 11:40:51.773340 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2914 11:40:51.776915 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2915 11:40:51.779951 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2916 11:40:51.782969 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2917 11:40:51.787013 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2918 11:40:51.793011 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2919 11:40:51.796640 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2920 11:40:51.799623 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2921 11:40:51.803016 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2922 11:40:51.806303 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2923 11:40:51.813287 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2924 11:40:51.816096 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2925 11:40:51.819260 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2926 11:40:51.823026 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2927 11:40:51.829549 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2928 11:40:51.832662 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2929 11:40:51.832815 ==
2930 11:40:51.836187 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 11:40:51.839599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 11:40:51.839742 ==
2933 11:40:51.839850 DQS Delay:
2934 11:40:51.843465 DQS0 = 0, DQS1 = 0
2935 11:40:51.843574 DQM Delay:
2936 11:40:51.846200 DQM0 = 115, DQM1 = 109
2937 11:40:51.846348 DQ Delay:
2938 11:40:51.849276 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2939 11:40:51.852913 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2940 11:40:51.856365 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2941 11:40:51.859613 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2942 11:40:51.859749
2943 11:40:51.862810
2944 11:40:51.862941 ==
2945 11:40:51.865970 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 11:40:51.869200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 11:40:51.869346 ==
2948 11:40:51.869447
2949 11:40:51.869540
2950 11:40:51.873029 TX Vref Scan disable
2951 11:40:51.873136 == TX Byte 0 ==
2952 11:40:51.879166 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2953 11:40:51.882853 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2954 11:40:51.883026 == TX Byte 1 ==
2955 11:40:51.889256 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2956 11:40:51.892937 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2957 11:40:51.893054 ==
2958 11:40:51.895800 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 11:40:51.899283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 11:40:51.899381 ==
2961 11:40:51.911741 TX Vref=22, minBit 3, minWin=25, winSum=408
2962 11:40:51.914957 TX Vref=24, minBit 3, minWin=25, winSum=419
2963 11:40:51.918257 TX Vref=26, minBit 13, minWin=25, winSum=419
2964 11:40:51.921328 TX Vref=28, minBit 15, minWin=25, winSum=427
2965 11:40:51.924882 TX Vref=30, minBit 5, minWin=25, winSum=419
2966 11:40:51.931426 TX Vref=32, minBit 13, minWin=25, winSum=421
2967 11:40:51.934745 [TxChooseVref] Worse bit 15, Min win 25, Win sum 427, Final Vref 28
2968 11:40:51.937817
2969 11:40:51.937918 Final TX Range 1 Vref 28
2970 11:40:51.937991
2971 11:40:51.938055 ==
2972 11:40:51.941070 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 11:40:51.947868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 11:40:51.947976 ==
2975 11:40:51.948059
2976 11:40:51.948123
2977 11:40:51.948183 TX Vref Scan disable
2978 11:40:51.951768 == TX Byte 0 ==
2979 11:40:51.955091 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2980 11:40:51.961828 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2981 11:40:51.961931 == TX Byte 1 ==
2982 11:40:51.964973 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2983 11:40:51.971741 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2984 11:40:51.971851
2985 11:40:51.971922 [DATLAT]
2986 11:40:51.971985 Freq=1200, CH0 RK1
2987 11:40:51.972054
2988 11:40:51.975435 DATLAT Default: 0xd
2989 11:40:51.975521 0, 0xFFFF, sum = 0
2990 11:40:51.978309 1, 0xFFFF, sum = 0
2991 11:40:51.981567 2, 0xFFFF, sum = 0
2992 11:40:51.981655 3, 0xFFFF, sum = 0
2993 11:40:51.985111 4, 0xFFFF, sum = 0
2994 11:40:51.985198 5, 0xFFFF, sum = 0
2995 11:40:51.988253 6, 0xFFFF, sum = 0
2996 11:40:51.988342 7, 0xFFFF, sum = 0
2997 11:40:51.991714 8, 0xFFFF, sum = 0
2998 11:40:51.991801 9, 0xFFFF, sum = 0
2999 11:40:51.995451 10, 0xFFFF, sum = 0
3000 11:40:51.995540 11, 0xFFFF, sum = 0
3001 11:40:51.998327 12, 0x0, sum = 1
3002 11:40:51.998416 13, 0x0, sum = 2
3003 11:40:52.001636 14, 0x0, sum = 3
3004 11:40:52.001724 15, 0x0, sum = 4
3005 11:40:52.004914 best_step = 13
3006 11:40:52.005001
3007 11:40:52.005069 ==
3008 11:40:52.008504 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 11:40:52.011501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 11:40:52.011592 ==
3011 11:40:52.011661 RX Vref Scan: 0
3012 11:40:52.014846
3013 11:40:52.014935 RX Vref 0 -> 0, step: 1
3014 11:40:52.015004
3015 11:40:52.017846 RX Delay -21 -> 252, step: 4
3016 11:40:52.024420 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3017 11:40:52.027837 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3018 11:40:52.031679 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3019 11:40:52.034444 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3020 11:40:52.038591 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3021 11:40:52.044317 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3022 11:40:52.047910 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3023 11:40:52.050731 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3024 11:40:52.054561 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3025 11:40:52.057715 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3026 11:40:52.064096 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3027 11:40:52.068123 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3028 11:40:52.070680 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3029 11:40:52.074317 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3030 11:40:52.077741 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3031 11:40:52.083958 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3032 11:40:52.084081 ==
3033 11:40:52.087651 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 11:40:52.091214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 11:40:52.091305 ==
3036 11:40:52.091381 DQS Delay:
3037 11:40:52.094720 DQS0 = 0, DQS1 = 0
3038 11:40:52.094826 DQM Delay:
3039 11:40:52.097239 DQM0 = 115, DQM1 = 107
3040 11:40:52.097342 DQ Delay:
3041 11:40:52.100519 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3042 11:40:52.103838 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3043 11:40:52.107362 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3044 11:40:52.110683 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3045 11:40:52.110804
3046 11:40:52.110902
3047 11:40:52.120596 [DQSOSCAuto] RK1, (LSB)MR18= 0xfcfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3048 11:40:52.124181 CH0 RK1: MR19=303, MR18=FCFA
3049 11:40:52.130892 CH0_RK1: MR19=0x303, MR18=0xFCFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3050 11:40:52.131030 [RxdqsGatingPostProcess] freq 1200
3051 11:40:52.137316 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3052 11:40:52.140785 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 11:40:52.143946 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 11:40:52.147290 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 11:40:52.150866 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 11:40:52.153719 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 11:40:52.157225 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 11:40:52.160583 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 11:40:52.163552 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 11:40:52.167425 Pre-setting of DQS Precalculation
3061 11:40:52.170387 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3062 11:40:52.170470 ==
3063 11:40:52.173726 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 11:40:52.177097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 11:40:52.177187 ==
3066 11:40:52.183643 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 11:40:52.190222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3068 11:40:52.198024 [CA 0] Center 38 (8~68) winsize 61
3069 11:40:52.201507 [CA 1] Center 38 (8~68) winsize 61
3070 11:40:52.205250 [CA 2] Center 35 (5~65) winsize 61
3071 11:40:52.208228 [CA 3] Center 34 (4~64) winsize 61
3072 11:40:52.211507 [CA 4] Center 34 (4~65) winsize 62
3073 11:40:52.215305 [CA 5] Center 34 (4~64) winsize 61
3074 11:40:52.215389
3075 11:40:52.218501 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3076 11:40:52.218576
3077 11:40:52.221560 [CATrainingPosCal] consider 1 rank data
3078 11:40:52.224759 u2DelayCellTimex100 = 270/100 ps
3079 11:40:52.228237 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3080 11:40:52.234606 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3081 11:40:52.237981 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3082 11:40:52.241248 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3083 11:40:52.244611 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3084 11:40:52.247873 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3085 11:40:52.247969
3086 11:40:52.252140 CA PerBit enable=1, Macro0, CA PI delay=34
3087 11:40:52.252247
3088 11:40:52.254598 [CBTSetCACLKResult] CA Dly = 34
3089 11:40:52.254678 CS Dly: 5 (0~36)
3090 11:40:52.258397 ==
3091 11:40:52.261226 Dram Type= 6, Freq= 0, CH_1, rank 1
3092 11:40:52.264640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 11:40:52.264732 ==
3094 11:40:52.268290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 11:40:52.274945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 11:40:52.283894 [CA 0] Center 37 (7~68) winsize 62
3097 11:40:52.287069 [CA 1] Center 38 (8~68) winsize 61
3098 11:40:52.290647 [CA 2] Center 35 (5~65) winsize 61
3099 11:40:52.293959 [CA 3] Center 33 (3~64) winsize 62
3100 11:40:52.296897 [CA 4] Center 34 (4~64) winsize 61
3101 11:40:52.300406 [CA 5] Center 34 (4~64) winsize 61
3102 11:40:52.300502
3103 11:40:52.303686 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 11:40:52.303774
3105 11:40:52.307354 [CATrainingPosCal] consider 2 rank data
3106 11:40:52.310286 u2DelayCellTimex100 = 270/100 ps
3107 11:40:52.313718 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3108 11:40:52.320245 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3109 11:40:52.323727 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3110 11:40:52.326900 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3111 11:40:52.330080 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3112 11:40:52.333978 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3113 11:40:52.334101
3114 11:40:52.337219 CA PerBit enable=1, Macro0, CA PI delay=34
3115 11:40:52.337328
3116 11:40:52.340006 [CBTSetCACLKResult] CA Dly = 34
3117 11:40:52.340153 CS Dly: 6 (0~39)
3118 11:40:52.343495
3119 11:40:52.346669 ----->DramcWriteLeveling(PI) begin...
3120 11:40:52.346810 ==
3121 11:40:52.349722 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 11:40:52.353484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 11:40:52.353644 ==
3124 11:40:52.356438 Write leveling (Byte 0): 24 => 24
3125 11:40:52.360081 Write leveling (Byte 1): 29 => 29
3126 11:40:52.362900 DramcWriteLeveling(PI) end<-----
3127 11:40:52.363005
3128 11:40:52.363100 ==
3129 11:40:52.366426 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 11:40:52.369871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:40:52.369972 ==
3132 11:40:52.373106 [Gating] SW mode calibration
3133 11:40:52.379947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3134 11:40:52.386464 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3135 11:40:52.389838 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 11:40:52.393069 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 11:40:52.399769 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 11:40:52.403792 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 11:40:52.406218 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 11:40:52.413072 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 11:40:52.416110 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3142 11:40:52.419654 0 15 28 | B1->B0 | 2c2c 2525 | 1 0 | (1 0) (1 0)
3143 11:40:52.426402 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 11:40:52.429739 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 11:40:52.432961 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 11:40:52.439406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 11:40:52.442964 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 11:40:52.446107 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 11:40:52.452415 1 0 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
3150 11:40:52.456055 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3151 11:40:52.459331 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 11:40:52.465708 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:40:52.469712 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:40:52.472400 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 11:40:52.478850 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 11:40:52.482432 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 11:40:52.485986 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 11:40:52.492467 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3159 11:40:52.495766 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:40:52.499121 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:40:52.506245 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:40:52.508860 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:40:52.512449 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:40:52.515312 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:40:52.522423 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:40:52.525681 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:40:52.528897 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:40:52.535582 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:40:52.538739 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:40:52.541886 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:40:52.548617 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:40:52.552025 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:40:52.555269 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 11:40:52.562322 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3175 11:40:52.565369 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 11:40:52.568693 Total UI for P1: 0, mck2ui 16
3177 11:40:52.571894 best dqsien dly found for B0: ( 1, 3, 28)
3178 11:40:52.575010 Total UI for P1: 0, mck2ui 16
3179 11:40:52.578693 best dqsien dly found for B1: ( 1, 3, 28)
3180 11:40:52.581795 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3181 11:40:52.585838 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3182 11:40:52.585952
3183 11:40:52.588483 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3184 11:40:52.591619 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3185 11:40:52.594994 [Gating] SW calibration Done
3186 11:40:52.595097 ==
3187 11:40:52.598355 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 11:40:52.604677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 11:40:52.604768 ==
3190 11:40:52.604837 RX Vref Scan: 0
3191 11:40:52.604900
3192 11:40:52.608077 RX Vref 0 -> 0, step: 1
3193 11:40:52.608155
3194 11:40:52.611259 RX Delay -40 -> 252, step: 8
3195 11:40:52.614730 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3196 11:40:52.617964 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3197 11:40:52.621603 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3198 11:40:52.627793 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3199 11:40:52.631108 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3200 11:40:52.634760 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3201 11:40:52.637643 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3202 11:40:52.641217 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3203 11:40:52.644363 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3204 11:40:52.651449 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3205 11:40:52.654211 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3206 11:40:52.657845 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3207 11:40:52.661512 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3208 11:40:52.667971 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3209 11:40:52.671713 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3210 11:40:52.674180 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3211 11:40:52.674271 ==
3212 11:40:52.678160 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 11:40:52.681142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 11:40:52.681222 ==
3215 11:40:52.684550 DQS Delay:
3216 11:40:52.684623 DQS0 = 0, DQS1 = 0
3217 11:40:52.687446 DQM Delay:
3218 11:40:52.687519 DQM0 = 115, DQM1 = 112
3219 11:40:52.687580 DQ Delay:
3220 11:40:52.691331 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3221 11:40:52.697424 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3222 11:40:52.701013 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3223 11:40:52.704356 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3224 11:40:52.704446
3225 11:40:52.704513
3226 11:40:52.704575 ==
3227 11:40:52.707411 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 11:40:52.710824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 11:40:52.710916 ==
3230 11:40:52.710986
3231 11:40:52.711049
3232 11:40:52.714655 TX Vref Scan disable
3233 11:40:52.717545 == TX Byte 0 ==
3234 11:40:52.720686 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3235 11:40:52.724599 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3236 11:40:52.727244 == TX Byte 1 ==
3237 11:40:52.730549 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3238 11:40:52.734416 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3239 11:40:52.734507 ==
3240 11:40:52.737048 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 11:40:52.740673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 11:40:52.744429 ==
3243 11:40:52.754261 TX Vref=22, minBit 10, minWin=25, winSum=415
3244 11:40:52.757452 TX Vref=24, minBit 2, minWin=25, winSum=418
3245 11:40:52.761013 TX Vref=26, minBit 1, minWin=26, winSum=424
3246 11:40:52.764257 TX Vref=28, minBit 1, minWin=26, winSum=426
3247 11:40:52.767861 TX Vref=30, minBit 7, minWin=26, winSum=432
3248 11:40:52.774298 TX Vref=32, minBit 2, minWin=26, winSum=434
3249 11:40:52.777463 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 32
3250 11:40:52.777595
3251 11:40:52.780819 Final TX Range 1 Vref 32
3252 11:40:52.780911
3253 11:40:52.780998 ==
3254 11:40:52.784419 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 11:40:52.788010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 11:40:52.790773 ==
3257 11:40:52.790881
3258 11:40:52.790973
3259 11:40:52.791064 TX Vref Scan disable
3260 11:40:52.794578 == TX Byte 0 ==
3261 11:40:52.797475 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3262 11:40:52.803673 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3263 11:40:52.803811 == TX Byte 1 ==
3264 11:40:52.807358 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 11:40:52.813695 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 11:40:52.813821
3267 11:40:52.813919 [DATLAT]
3268 11:40:52.814010 Freq=1200, CH1 RK0
3269 11:40:52.814099
3270 11:40:52.817218 DATLAT Default: 0xd
3271 11:40:52.821206 0, 0xFFFF, sum = 0
3272 11:40:52.821314 1, 0xFFFF, sum = 0
3273 11:40:52.824138 2, 0xFFFF, sum = 0
3274 11:40:52.824214 3, 0xFFFF, sum = 0
3275 11:40:52.826557 4, 0xFFFF, sum = 0
3276 11:40:52.826628 5, 0xFFFF, sum = 0
3277 11:40:52.830320 6, 0xFFFF, sum = 0
3278 11:40:52.830408 7, 0xFFFF, sum = 0
3279 11:40:52.833236 8, 0xFFFF, sum = 0
3280 11:40:52.833323 9, 0xFFFF, sum = 0
3281 11:40:52.836686 10, 0xFFFF, sum = 0
3282 11:40:52.836799 11, 0xFFFF, sum = 0
3283 11:40:52.839718 12, 0x0, sum = 1
3284 11:40:52.839853 13, 0x0, sum = 2
3285 11:40:52.842926 14, 0x0, sum = 3
3286 11:40:52.843005 15, 0x0, sum = 4
3287 11:40:52.846687 best_step = 13
3288 11:40:52.846772
3289 11:40:52.846839 ==
3290 11:40:52.849727 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 11:40:52.852950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 11:40:52.853035 ==
3293 11:40:52.856337 RX Vref Scan: 1
3294 11:40:52.856421
3295 11:40:52.856486 Set Vref Range= 32 -> 127
3296 11:40:52.856547
3297 11:40:52.860141 RX Vref 32 -> 127, step: 1
3298 11:40:52.860225
3299 11:40:52.863168 RX Delay -13 -> 252, step: 4
3300 11:40:52.863252
3301 11:40:52.866197 Set Vref, RX VrefLevel [Byte0]: 32
3302 11:40:52.870113 [Byte1]: 32
3303 11:40:52.870204
3304 11:40:52.872595 Set Vref, RX VrefLevel [Byte0]: 33
3305 11:40:52.875957 [Byte1]: 33
3306 11:40:52.880715
3307 11:40:52.880807 Set Vref, RX VrefLevel [Byte0]: 34
3308 11:40:52.883411 [Byte1]: 34
3309 11:40:52.888141
3310 11:40:52.888250 Set Vref, RX VrefLevel [Byte0]: 35
3311 11:40:52.891806 [Byte1]: 35
3312 11:40:52.895929
3313 11:40:52.896081 Set Vref, RX VrefLevel [Byte0]: 36
3314 11:40:52.899784 [Byte1]: 36
3315 11:40:52.903792
3316 11:40:52.903908 Set Vref, RX VrefLevel [Byte0]: 37
3317 11:40:52.907368 [Byte1]: 37
3318 11:40:52.911930
3319 11:40:52.912069 Set Vref, RX VrefLevel [Byte0]: 38
3320 11:40:52.915151 [Byte1]: 38
3321 11:40:52.919510
3322 11:40:52.919597 Set Vref, RX VrefLevel [Byte0]: 39
3323 11:40:52.922958 [Byte1]: 39
3324 11:40:52.927859
3325 11:40:52.927975 Set Vref, RX VrefLevel [Byte0]: 40
3326 11:40:52.931251 [Byte1]: 40
3327 11:40:52.936226
3328 11:40:52.936317 Set Vref, RX VrefLevel [Byte0]: 41
3329 11:40:52.939158 [Byte1]: 41
3330 11:40:52.943418
3331 11:40:52.943513 Set Vref, RX VrefLevel [Byte0]: 42
3332 11:40:52.947225 [Byte1]: 42
3333 11:40:52.951372
3334 11:40:52.951458 Set Vref, RX VrefLevel [Byte0]: 43
3335 11:40:52.954891 [Byte1]: 43
3336 11:40:52.959269
3337 11:40:52.959356 Set Vref, RX VrefLevel [Byte0]: 44
3338 11:40:52.962223 [Byte1]: 44
3339 11:40:52.967191
3340 11:40:52.967283 Set Vref, RX VrefLevel [Byte0]: 45
3341 11:40:52.970544 [Byte1]: 45
3342 11:40:52.975056
3343 11:40:52.975147 Set Vref, RX VrefLevel [Byte0]: 46
3344 11:40:52.978335 [Byte1]: 46
3345 11:40:52.982853
3346 11:40:52.982940 Set Vref, RX VrefLevel [Byte0]: 47
3347 11:40:52.986136 [Byte1]: 47
3348 11:40:52.990880
3349 11:40:52.990970 Set Vref, RX VrefLevel [Byte0]: 48
3350 11:40:52.994061 [Byte1]: 48
3351 11:40:52.998751
3352 11:40:52.998843 Set Vref, RX VrefLevel [Byte0]: 49
3353 11:40:53.002115 [Byte1]: 49
3354 11:40:53.006236
3355 11:40:53.006352 Set Vref, RX VrefLevel [Byte0]: 50
3356 11:40:53.010196 [Byte1]: 50
3357 11:40:53.014277
3358 11:40:53.014397 Set Vref, RX VrefLevel [Byte0]: 51
3359 11:40:53.017850 [Byte1]: 51
3360 11:40:53.022161
3361 11:40:53.022250 Set Vref, RX VrefLevel [Byte0]: 52
3362 11:40:53.025376 [Byte1]: 52
3363 11:40:53.030083
3364 11:40:53.030181 Set Vref, RX VrefLevel [Byte0]: 53
3365 11:40:53.033516 [Byte1]: 53
3366 11:40:53.038007
3367 11:40:53.038105 Set Vref, RX VrefLevel [Byte0]: 54
3368 11:40:53.041337 [Byte1]: 54
3369 11:40:53.046232
3370 11:40:53.046365 Set Vref, RX VrefLevel [Byte0]: 55
3371 11:40:53.049303 [Byte1]: 55
3372 11:40:53.054246
3373 11:40:53.054387 Set Vref, RX VrefLevel [Byte0]: 56
3374 11:40:53.057473 [Byte1]: 56
3375 11:40:53.061802
3376 11:40:53.061905 Set Vref, RX VrefLevel [Byte0]: 57
3377 11:40:53.064976 [Byte1]: 57
3378 11:40:53.069462
3379 11:40:53.069562 Set Vref, RX VrefLevel [Byte0]: 58
3380 11:40:53.072852 [Byte1]: 58
3381 11:40:53.077321
3382 11:40:53.077414 Set Vref, RX VrefLevel [Byte0]: 59
3383 11:40:53.080882 [Byte1]: 59
3384 11:40:53.085605
3385 11:40:53.085690 Set Vref, RX VrefLevel [Byte0]: 60
3386 11:40:53.088802 [Byte1]: 60
3387 11:40:53.093244
3388 11:40:53.093342 Set Vref, RX VrefLevel [Byte0]: 61
3389 11:40:53.096454 [Byte1]: 61
3390 11:40:53.101169
3391 11:40:53.101291 Set Vref, RX VrefLevel [Byte0]: 62
3392 11:40:53.104200 [Byte1]: 62
3393 11:40:53.108985
3394 11:40:53.109090 Set Vref, RX VrefLevel [Byte0]: 63
3395 11:40:53.112373 [Byte1]: 63
3396 11:40:53.116764
3397 11:40:53.116875 Set Vref, RX VrefLevel [Byte0]: 64
3398 11:40:53.119861 [Byte1]: 64
3399 11:40:53.124683
3400 11:40:53.124796 Set Vref, RX VrefLevel [Byte0]: 65
3401 11:40:53.128277 [Byte1]: 65
3402 11:40:53.132671
3403 11:40:53.135770 Set Vref, RX VrefLevel [Byte0]: 66
3404 11:40:53.138602 [Byte1]: 66
3405 11:40:53.138713
3406 11:40:53.142083 Final RX Vref Byte 0 = 50 to rank0
3407 11:40:53.145165 Final RX Vref Byte 1 = 52 to rank0
3408 11:40:53.148478 Final RX Vref Byte 0 = 50 to rank1
3409 11:40:53.152195 Final RX Vref Byte 1 = 52 to rank1==
3410 11:40:53.155684 Dram Type= 6, Freq= 0, CH_1, rank 0
3411 11:40:53.158905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3412 11:40:53.158998 ==
3413 11:40:53.159066 DQS Delay:
3414 11:40:53.162160 DQS0 = 0, DQS1 = 0
3415 11:40:53.162245 DQM Delay:
3416 11:40:53.165387 DQM0 = 114, DQM1 = 113
3417 11:40:53.165472 DQ Delay:
3418 11:40:53.168636 DQ0 =120, DQ1 =108, DQ2 =106, DQ3 =116
3419 11:40:53.171944 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3420 11:40:53.175229 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3421 11:40:53.181664 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3422 11:40:53.181782
3423 11:40:53.181885
3424 11:40:53.188512 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3425 11:40:53.192213 CH1 RK0: MR19=303, MR18=F3FF
3426 11:40:53.198219 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3427 11:40:53.198321
3428 11:40:53.201881 ----->DramcWriteLeveling(PI) begin...
3429 11:40:53.201971 ==
3430 11:40:53.204926 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 11:40:53.208373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 11:40:53.208467 ==
3433 11:40:53.211449 Write leveling (Byte 0): 24 => 24
3434 11:40:53.214801 Write leveling (Byte 1): 28 => 28
3435 11:40:53.217858 DramcWriteLeveling(PI) end<-----
3436 11:40:53.217958
3437 11:40:53.218026 ==
3438 11:40:53.221365 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 11:40:53.225071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 11:40:53.225159 ==
3441 11:40:53.227883 [Gating] SW mode calibration
3442 11:40:53.234680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3443 11:40:53.241314 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3444 11:40:53.244494 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3445 11:40:53.250989 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 11:40:53.254369 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 11:40:53.257702 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 11:40:53.264215 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 11:40:53.267473 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3450 11:40:53.271226 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
3451 11:40:53.277498 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
3452 11:40:53.281174 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 11:40:53.284692 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 11:40:53.291580 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 11:40:53.294641 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 11:40:53.297499 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 11:40:53.304283 1 0 20 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3458 11:40:53.307234 1 0 24 | B1->B0 | 2424 4545 | 0 0 | (0 0) (0 0)
3459 11:40:53.310730 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3460 11:40:53.317749 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 11:40:53.320828 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 11:40:53.323814 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 11:40:53.330660 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 11:40:53.333953 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 11:40:53.336876 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 11:40:53.343415 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3467 11:40:53.346649 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3468 11:40:53.350089 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:40:53.356891 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:40:53.360306 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:40:53.363294 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:40:53.369591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:40:53.373557 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:40:53.376186 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:40:53.382806 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:40:53.386440 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:40:53.389905 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:40:53.396303 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 11:40:53.399526 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:40:53.402863 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:40:53.409332 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3482 11:40:53.412676 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3483 11:40:53.416618 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3484 11:40:53.419595 Total UI for P1: 0, mck2ui 16
3485 11:40:53.423241 best dqsien dly found for B0: ( 1, 3, 22)
3486 11:40:53.426097 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3487 11:40:53.429283 Total UI for P1: 0, mck2ui 16
3488 11:40:53.432775 best dqsien dly found for B1: ( 1, 3, 28)
3489 11:40:53.439234 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3490 11:40:53.442995 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3491 11:40:53.443116
3492 11:40:53.446053 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3493 11:40:53.448930 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3494 11:40:53.452573 [Gating] SW calibration Done
3495 11:40:53.452670 ==
3496 11:40:53.455833 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 11:40:53.459020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 11:40:53.459129 ==
3499 11:40:53.462394 RX Vref Scan: 0
3500 11:40:53.462484
3501 11:40:53.462569 RX Vref 0 -> 0, step: 1
3502 11:40:53.462678
3503 11:40:53.465642 RX Delay -40 -> 252, step: 8
3504 11:40:53.469361 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3505 11:40:53.475835 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3506 11:40:53.478827 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3507 11:40:53.481933 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3508 11:40:53.485390 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3509 11:40:53.489014 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3510 11:40:53.495224 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3511 11:40:53.498560 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3512 11:40:53.501579 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3513 11:40:53.505582 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3514 11:40:53.508702 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3515 11:40:53.515175 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3516 11:40:53.518736 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3517 11:40:53.521634 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3518 11:40:53.525073 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3519 11:40:53.531271 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3520 11:40:53.531397 ==
3521 11:40:53.534997 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 11:40:53.537876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 11:40:53.537985 ==
3524 11:40:53.538080 DQS Delay:
3525 11:40:53.541107 DQS0 = 0, DQS1 = 0
3526 11:40:53.541244 DQM Delay:
3527 11:40:53.544468 DQM0 = 114, DQM1 = 111
3528 11:40:53.544572 DQ Delay:
3529 11:40:53.548027 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3530 11:40:53.551131 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3531 11:40:53.554392 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3532 11:40:53.557820 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3533 11:40:53.557919
3534 11:40:53.557989
3535 11:40:53.561193 ==
3536 11:40:53.564203 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 11:40:53.567693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 11:40:53.567791 ==
3539 11:40:53.567862
3540 11:40:53.567925
3541 11:40:53.570920 TX Vref Scan disable
3542 11:40:53.571011 == TX Byte 0 ==
3543 11:40:53.574471 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3544 11:40:53.580854 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3545 11:40:53.580959 == TX Byte 1 ==
3546 11:40:53.587698 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3547 11:40:53.590939 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3548 11:40:53.591038 ==
3549 11:40:53.593697 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 11:40:53.597046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 11:40:53.597139 ==
3552 11:40:53.609589 TX Vref=22, minBit 3, minWin=24, winSum=421
3553 11:40:53.613022 TX Vref=24, minBit 1, minWin=26, winSum=425
3554 11:40:53.616476 TX Vref=26, minBit 1, minWin=26, winSum=429
3555 11:40:53.619603 TX Vref=28, minBit 1, minWin=26, winSum=430
3556 11:40:53.622816 TX Vref=30, minBit 2, minWin=26, winSum=433
3557 11:40:53.629789 TX Vref=32, minBit 2, minWin=26, winSum=430
3558 11:40:53.632737 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 30
3559 11:40:53.632835
3560 11:40:53.635730 Final TX Range 1 Vref 30
3561 11:40:53.635817
3562 11:40:53.635883 ==
3563 11:40:53.639855 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 11:40:53.643026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 11:40:53.645748 ==
3566 11:40:53.645842
3567 11:40:53.645910
3568 11:40:53.645971 TX Vref Scan disable
3569 11:40:53.649576 == TX Byte 0 ==
3570 11:40:53.652470 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3571 11:40:53.659135 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3572 11:40:53.659245 == TX Byte 1 ==
3573 11:40:53.662866 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3574 11:40:53.669406 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3575 11:40:53.669516
3576 11:40:53.669588 [DATLAT]
3577 11:40:53.669648 Freq=1200, CH1 RK1
3578 11:40:53.669708
3579 11:40:53.672257 DATLAT Default: 0xd
3580 11:40:53.675471 0, 0xFFFF, sum = 0
3581 11:40:53.675561 1, 0xFFFF, sum = 0
3582 11:40:53.679534 2, 0xFFFF, sum = 0
3583 11:40:53.679629 3, 0xFFFF, sum = 0
3584 11:40:53.682943 4, 0xFFFF, sum = 0
3585 11:40:53.683039 5, 0xFFFF, sum = 0
3586 11:40:53.685750 6, 0xFFFF, sum = 0
3587 11:40:53.685839 7, 0xFFFF, sum = 0
3588 11:40:53.688640 8, 0xFFFF, sum = 0
3589 11:40:53.688763 9, 0xFFFF, sum = 0
3590 11:40:53.692235 10, 0xFFFF, sum = 0
3591 11:40:53.692316 11, 0xFFFF, sum = 0
3592 11:40:53.695402 12, 0x0, sum = 1
3593 11:40:53.695492 13, 0x0, sum = 2
3594 11:40:53.698523 14, 0x0, sum = 3
3595 11:40:53.698603 15, 0x0, sum = 4
3596 11:40:53.702047 best_step = 13
3597 11:40:53.702123
3598 11:40:53.702184 ==
3599 11:40:53.705546 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 11:40:53.709079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 11:40:53.709169 ==
3602 11:40:53.711759 RX Vref Scan: 0
3603 11:40:53.711845
3604 11:40:53.711913 RX Vref 0 -> 0, step: 1
3605 11:40:53.711975
3606 11:40:53.715484 RX Delay -13 -> 252, step: 4
3607 11:40:53.721860 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3608 11:40:53.725061 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3609 11:40:53.728432 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3610 11:40:53.731686 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3611 11:40:53.735913 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3612 11:40:53.741360 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3613 11:40:53.745200 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3614 11:40:53.748598 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3615 11:40:53.751352 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3616 11:40:53.754874 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3617 11:40:53.761083 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3618 11:40:53.764828 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3619 11:40:53.767846 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3620 11:40:53.771550 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3621 11:40:53.777700 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3622 11:40:53.780891 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3623 11:40:53.780981 ==
3624 11:40:53.784194 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 11:40:53.787414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 11:40:53.787521 ==
3627 11:40:53.790778 DQS Delay:
3628 11:40:53.790889 DQS0 = 0, DQS1 = 0
3629 11:40:53.794201 DQM Delay:
3630 11:40:53.794287 DQM0 = 114, DQM1 = 112
3631 11:40:53.794354 DQ Delay:
3632 11:40:53.797398 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3633 11:40:53.804432 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3634 11:40:53.807371 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3635 11:40:53.810387 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3636 11:40:53.810479
3637 11:40:53.810562
3638 11:40:53.817087 [DQSOSCAuto] RK1, (LSB)MR18= 0xf305, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3639 11:40:53.820769 CH1 RK1: MR19=304, MR18=F305
3640 11:40:53.827296 CH1_RK1: MR19=0x304, MR18=0xF305, DQSOSC=408, MR23=63, INC=39, DEC=26
3641 11:40:53.830122 [RxdqsGatingPostProcess] freq 1200
3642 11:40:53.836559 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3643 11:40:53.839905 best DQS0 dly(2T, 0.5T) = (0, 11)
3644 11:40:53.840019 best DQS1 dly(2T, 0.5T) = (0, 11)
3645 11:40:53.843220 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3646 11:40:53.846586 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3647 11:40:53.849865 best DQS0 dly(2T, 0.5T) = (0, 11)
3648 11:40:53.853290 best DQS1 dly(2T, 0.5T) = (0, 11)
3649 11:40:53.856592 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3650 11:40:53.859955 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3651 11:40:53.863153 Pre-setting of DQS Precalculation
3652 11:40:53.869522 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3653 11:40:53.875992 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3654 11:40:53.882787 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3655 11:40:53.882895
3656 11:40:53.882962
3657 11:40:53.886446 [Calibration Summary] 2400 Mbps
3658 11:40:53.886522 CH 0, Rank 0
3659 11:40:53.889462 SW Impedance : PASS
3660 11:40:53.892658 DUTY Scan : NO K
3661 11:40:53.892738 ZQ Calibration : PASS
3662 11:40:53.895759 Jitter Meter : NO K
3663 11:40:53.899257 CBT Training : PASS
3664 11:40:53.899336 Write leveling : PASS
3665 11:40:53.902728 RX DQS gating : PASS
3666 11:40:53.905609 RX DQ/DQS(RDDQC) : PASS
3667 11:40:53.905696 TX DQ/DQS : PASS
3668 11:40:53.909271 RX DATLAT : PASS
3669 11:40:53.912635 RX DQ/DQS(Engine): PASS
3670 11:40:53.912712 TX OE : NO K
3671 11:40:53.915949 All Pass.
3672 11:40:53.916042
3673 11:40:53.916118 CH 0, Rank 1
3674 11:40:53.919274 SW Impedance : PASS
3675 11:40:53.919343 DUTY Scan : NO K
3676 11:40:53.922073 ZQ Calibration : PASS
3677 11:40:53.925798 Jitter Meter : NO K
3678 11:40:53.925876 CBT Training : PASS
3679 11:40:53.929283 Write leveling : PASS
3680 11:40:53.932320 RX DQS gating : PASS
3681 11:40:53.932414 RX DQ/DQS(RDDQC) : PASS
3682 11:40:53.936054 TX DQ/DQS : PASS
3683 11:40:53.939354 RX DATLAT : PASS
3684 11:40:53.939442 RX DQ/DQS(Engine): PASS
3685 11:40:53.942640 TX OE : NO K
3686 11:40:53.942742 All Pass.
3687 11:40:53.942811
3688 11:40:53.945294 CH 1, Rank 0
3689 11:40:53.945379 SW Impedance : PASS
3690 11:40:53.948821 DUTY Scan : NO K
3691 11:40:53.948908 ZQ Calibration : PASS
3692 11:40:53.952197 Jitter Meter : NO K
3693 11:40:53.955146 CBT Training : PASS
3694 11:40:53.955233 Write leveling : PASS
3695 11:40:53.958687 RX DQS gating : PASS
3696 11:40:53.961878 RX DQ/DQS(RDDQC) : PASS
3697 11:40:53.961969 TX DQ/DQS : PASS
3698 11:40:53.965465 RX DATLAT : PASS
3699 11:40:53.968251 RX DQ/DQS(Engine): PASS
3700 11:40:53.968342 TX OE : NO K
3701 11:40:53.971759 All Pass.
3702 11:40:53.971846
3703 11:40:53.971914 CH 1, Rank 1
3704 11:40:53.975073 SW Impedance : PASS
3705 11:40:53.975159 DUTY Scan : NO K
3706 11:40:53.978359 ZQ Calibration : PASS
3707 11:40:53.981417 Jitter Meter : NO K
3708 11:40:53.981571 CBT Training : PASS
3709 11:40:53.984772 Write leveling : PASS
3710 11:40:53.988010 RX DQS gating : PASS
3711 11:40:53.988136 RX DQ/DQS(RDDQC) : PASS
3712 11:40:53.991642 TX DQ/DQS : PASS
3713 11:40:53.995004 RX DATLAT : PASS
3714 11:40:53.995094 RX DQ/DQS(Engine): PASS
3715 11:40:53.998222 TX OE : NO K
3716 11:40:53.998311 All Pass.
3717 11:40:53.998378
3718 11:40:54.001355 DramC Write-DBI off
3719 11:40:54.004526 PER_BANK_REFRESH: Hybrid Mode
3720 11:40:54.004680 TX_TRACKING: ON
3721 11:40:54.014713 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3722 11:40:54.018046 [FAST_K] Save calibration result to emmc
3723 11:40:54.021533 dramc_set_vcore_voltage set vcore to 650000
3724 11:40:54.024138 Read voltage for 600, 5
3725 11:40:54.024229 Vio18 = 0
3726 11:40:54.024295 Vcore = 650000
3727 11:40:54.027712 Vdram = 0
3728 11:40:54.027822 Vddq = 0
3729 11:40:54.027952 Vmddr = 0
3730 11:40:54.034650 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3731 11:40:54.037474 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3732 11:40:54.040656 MEM_TYPE=3, freq_sel=19
3733 11:40:54.044216 sv_algorithm_assistance_LP4_1600
3734 11:40:54.047624 ============ PULL DRAM RESETB DOWN ============
3735 11:40:54.054251 ========== PULL DRAM RESETB DOWN end =========
3736 11:40:54.057150 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3737 11:40:54.060698 ===================================
3738 11:40:54.063681 LPDDR4 DRAM CONFIGURATION
3739 11:40:54.067122 ===================================
3740 11:40:54.067235 EX_ROW_EN[0] = 0x0
3741 11:40:54.070274 EX_ROW_EN[1] = 0x0
3742 11:40:54.070362 LP4Y_EN = 0x0
3743 11:40:54.073701 WORK_FSP = 0x0
3744 11:40:54.073791 WL = 0x2
3745 11:40:54.077080 RL = 0x2
3746 11:40:54.080467 BL = 0x2
3747 11:40:54.080558 RPST = 0x0
3748 11:40:54.083632 RD_PRE = 0x0
3749 11:40:54.083750 WR_PRE = 0x1
3750 11:40:54.086891 WR_PST = 0x0
3751 11:40:54.086976 DBI_WR = 0x0
3752 11:40:54.089994 DBI_RD = 0x0
3753 11:40:54.090080 OTF = 0x1
3754 11:40:54.093107 ===================================
3755 11:40:54.096397 ===================================
3756 11:40:54.100574 ANA top config
3757 11:40:54.103510 ===================================
3758 11:40:54.103615 DLL_ASYNC_EN = 0
3759 11:40:54.106291 ALL_SLAVE_EN = 1
3760 11:40:54.109735 NEW_RANK_MODE = 1
3761 11:40:54.113201 DLL_IDLE_MODE = 1
3762 11:40:54.116562 LP45_APHY_COMB_EN = 1
3763 11:40:54.116653 TX_ODT_DIS = 1
3764 11:40:54.119579 NEW_8X_MODE = 1
3765 11:40:54.123209 ===================================
3766 11:40:54.126154 ===================================
3767 11:40:54.129785 data_rate = 1200
3768 11:40:54.132827 CKR = 1
3769 11:40:54.136311 DQ_P2S_RATIO = 8
3770 11:40:54.139351 ===================================
3771 11:40:54.142795 CA_P2S_RATIO = 8
3772 11:40:54.142926 DQ_CA_OPEN = 0
3773 11:40:54.145987 DQ_SEMI_OPEN = 0
3774 11:40:54.149632 CA_SEMI_OPEN = 0
3775 11:40:54.152540 CA_FULL_RATE = 0
3776 11:40:54.156378 DQ_CKDIV4_EN = 1
3777 11:40:54.159156 CA_CKDIV4_EN = 1
3778 11:40:54.159273 CA_PREDIV_EN = 0
3779 11:40:54.162721 PH8_DLY = 0
3780 11:40:54.165759 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3781 11:40:54.169302 DQ_AAMCK_DIV = 4
3782 11:40:54.172548 CA_AAMCK_DIV = 4
3783 11:40:54.175726 CA_ADMCK_DIV = 4
3784 11:40:54.175854 DQ_TRACK_CA_EN = 0
3785 11:40:54.179108 CA_PICK = 600
3786 11:40:54.182512 CA_MCKIO = 600
3787 11:40:54.185849 MCKIO_SEMI = 0
3788 11:40:54.188765 PLL_FREQ = 2288
3789 11:40:54.192348 DQ_UI_PI_RATIO = 32
3790 11:40:54.195428 CA_UI_PI_RATIO = 0
3791 11:40:54.198786 ===================================
3792 11:40:54.202411 ===================================
3793 11:40:54.202505 memory_type:LPDDR4
3794 11:40:54.205282 GP_NUM : 10
3795 11:40:54.209286 SRAM_EN : 1
3796 11:40:54.209405 MD32_EN : 0
3797 11:40:54.212187 ===================================
3798 11:40:54.215815 [ANA_INIT] >>>>>>>>>>>>>>
3799 11:40:54.219076 <<<<<< [CONFIGURE PHASE]: ANA_TX
3800 11:40:54.222419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3801 11:40:54.225575 ===================================
3802 11:40:54.228893 data_rate = 1200,PCW = 0X5800
3803 11:40:54.231728 ===================================
3804 11:40:54.235697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3805 11:40:54.238505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 11:40:54.244892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3807 11:40:54.248396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3808 11:40:54.251404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3809 11:40:54.257913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3810 11:40:54.258020 [ANA_INIT] flow start
3811 11:40:54.261703 [ANA_INIT] PLL >>>>>>>>
3812 11:40:54.264799 [ANA_INIT] PLL <<<<<<<<
3813 11:40:54.264889 [ANA_INIT] MIDPI >>>>>>>>
3814 11:40:54.267949 [ANA_INIT] MIDPI <<<<<<<<
3815 11:40:54.271473 [ANA_INIT] DLL >>>>>>>>
3816 11:40:54.271632 [ANA_INIT] flow end
3817 11:40:54.277972 ============ LP4 DIFF to SE enter ============
3818 11:40:54.281126 ============ LP4 DIFF to SE exit ============
3819 11:40:54.281220 [ANA_INIT] <<<<<<<<<<<<<
3820 11:40:54.284325 [Flow] Enable top DCM control >>>>>
3821 11:40:54.287742 [Flow] Enable top DCM control <<<<<
3822 11:40:54.291083 Enable DLL master slave shuffle
3823 11:40:54.297621 ==============================================================
3824 11:40:54.300780 Gating Mode config
3825 11:40:54.304324 ==============================================================
3826 11:40:54.307354 Config description:
3827 11:40:54.317313 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3828 11:40:54.323790 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3829 11:40:54.327642 SELPH_MODE 0: By rank 1: By Phase
3830 11:40:54.333601 ==============================================================
3831 11:40:54.337114 GAT_TRACK_EN = 1
3832 11:40:54.340194 RX_GATING_MODE = 2
3833 11:40:54.343855 RX_GATING_TRACK_MODE = 2
3834 11:40:54.346856 SELPH_MODE = 1
3835 11:40:54.349809 PICG_EARLY_EN = 1
3836 11:40:54.349900 VALID_LAT_VALUE = 1
3837 11:40:54.356597 ==============================================================
3838 11:40:54.360306 Enter into Gating configuration >>>>
3839 11:40:54.363368 Exit from Gating configuration <<<<
3840 11:40:54.366509 Enter into DVFS_PRE_config >>>>>
3841 11:40:54.376870 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3842 11:40:54.379823 Exit from DVFS_PRE_config <<<<<
3843 11:40:54.383515 Enter into PICG configuration >>>>
3844 11:40:54.386719 Exit from PICG configuration <<<<
3845 11:40:54.389627 [RX_INPUT] configuration >>>>>
3846 11:40:54.393168 [RX_INPUT] configuration <<<<<
3847 11:40:54.399544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3848 11:40:54.402801 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3849 11:40:54.409636 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3850 11:40:54.416545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3851 11:40:54.422693 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 11:40:54.429167 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 11:40:54.432568 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3854 11:40:54.435718 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3855 11:40:54.439306 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3856 11:40:54.446178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3857 11:40:54.449173 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3858 11:40:54.452069 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3859 11:40:54.455726 ===================================
3860 11:40:54.458780 LPDDR4 DRAM CONFIGURATION
3861 11:40:54.462015 ===================================
3862 11:40:54.465530 EX_ROW_EN[0] = 0x0
3863 11:40:54.465627 EX_ROW_EN[1] = 0x0
3864 11:40:54.468814 LP4Y_EN = 0x0
3865 11:40:54.468902 WORK_FSP = 0x0
3866 11:40:54.471978 WL = 0x2
3867 11:40:54.472088 RL = 0x2
3868 11:40:54.475189 BL = 0x2
3869 11:40:54.475275 RPST = 0x0
3870 11:40:54.478714 RD_PRE = 0x0
3871 11:40:54.478801 WR_PRE = 0x1
3872 11:40:54.481720 WR_PST = 0x0
3873 11:40:54.481805 DBI_WR = 0x0
3874 11:40:54.485189 DBI_RD = 0x0
3875 11:40:54.485276 OTF = 0x1
3876 11:40:54.488250 ===================================
3877 11:40:54.494955 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3878 11:40:54.498029 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3879 11:40:54.501706 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 11:40:54.504543 ===================================
3881 11:40:54.508343 LPDDR4 DRAM CONFIGURATION
3882 11:40:54.511417 ===================================
3883 11:40:54.514684 EX_ROW_EN[0] = 0x10
3884 11:40:54.514802 EX_ROW_EN[1] = 0x0
3885 11:40:54.517732 LP4Y_EN = 0x0
3886 11:40:54.517835 WORK_FSP = 0x0
3887 11:40:54.521244 WL = 0x2
3888 11:40:54.521333 RL = 0x2
3889 11:40:54.525210 BL = 0x2
3890 11:40:54.525302 RPST = 0x0
3891 11:40:54.527763 RD_PRE = 0x0
3892 11:40:54.527848 WR_PRE = 0x1
3893 11:40:54.530805 WR_PST = 0x0
3894 11:40:54.534445 DBI_WR = 0x0
3895 11:40:54.534541 DBI_RD = 0x0
3896 11:40:54.538003 OTF = 0x1
3897 11:40:54.541326 ===================================
3898 11:40:54.544973 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3899 11:40:54.550084 nWR fixed to 30
3900 11:40:54.552601 [ModeRegInit_LP4] CH0 RK0
3901 11:40:54.552691 [ModeRegInit_LP4] CH0 RK1
3902 11:40:54.556235 [ModeRegInit_LP4] CH1 RK0
3903 11:40:54.559291 [ModeRegInit_LP4] CH1 RK1
3904 11:40:54.559379 match AC timing 17
3905 11:40:54.565983 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3906 11:40:54.569158 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3907 11:40:54.572223 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3908 11:40:54.579479 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3909 11:40:54.582794 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3910 11:40:54.582941 ==
3911 11:40:54.585645 Dram Type= 6, Freq= 0, CH_0, rank 0
3912 11:40:54.589352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3913 11:40:54.589445 ==
3914 11:40:54.595465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3915 11:40:54.602418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3916 11:40:54.605483 [CA 0] Center 36 (6~67) winsize 62
3917 11:40:54.608554 [CA 1] Center 36 (6~66) winsize 61
3918 11:40:54.612465 [CA 2] Center 34 (4~65) winsize 62
3919 11:40:54.615199 [CA 3] Center 34 (4~65) winsize 62
3920 11:40:54.618908 [CA 4] Center 33 (3~64) winsize 62
3921 11:40:54.622038 [CA 5] Center 33 (3~64) winsize 62
3922 11:40:54.622132
3923 11:40:54.625649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3924 11:40:54.625739
3925 11:40:54.628619 [CATrainingPosCal] consider 1 rank data
3926 11:40:54.632530 u2DelayCellTimex100 = 270/100 ps
3927 11:40:54.635466 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 11:40:54.638223 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3929 11:40:54.641672 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3930 11:40:54.648666 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3931 11:40:54.651703 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3932 11:40:54.654791 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3933 11:40:54.654909
3934 11:40:54.658234 CA PerBit enable=1, Macro0, CA PI delay=33
3935 11:40:54.658347
3936 11:40:54.661390 [CBTSetCACLKResult] CA Dly = 33
3937 11:40:54.661482 CS Dly: 6 (0~37)
3938 11:40:54.661571 ==
3939 11:40:54.665280 Dram Type= 6, Freq= 0, CH_0, rank 1
3940 11:40:54.671521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3941 11:40:54.671629 ==
3942 11:40:54.674920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3943 11:40:54.681581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3944 11:40:54.685234 [CA 0] Center 36 (6~67) winsize 62
3945 11:40:54.688855 [CA 1] Center 36 (6~67) winsize 62
3946 11:40:54.691393 [CA 2] Center 34 (4~65) winsize 62
3947 11:40:54.694940 [CA 3] Center 34 (4~65) winsize 62
3948 11:40:54.698277 [CA 4] Center 33 (3~64) winsize 62
3949 11:40:54.701071 [CA 5] Center 33 (3~64) winsize 62
3950 11:40:54.701154
3951 11:40:54.704872 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3952 11:40:54.704966
3953 11:40:54.707751 [CATrainingPosCal] consider 2 rank data
3954 11:40:54.710765 u2DelayCellTimex100 = 270/100 ps
3955 11:40:54.714632 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3956 11:40:54.720700 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3957 11:40:54.724552 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 11:40:54.727729 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3959 11:40:54.730792 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 11:40:54.734412 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3961 11:40:54.734519
3962 11:40:54.737398 CA PerBit enable=1, Macro0, CA PI delay=33
3963 11:40:54.737508
3964 11:40:54.741005 [CBTSetCACLKResult] CA Dly = 33
3965 11:40:54.743884 CS Dly: 6 (0~37)
3966 11:40:54.744015
3967 11:40:54.747333 ----->DramcWriteLeveling(PI) begin...
3968 11:40:54.747425 ==
3969 11:40:54.750854 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 11:40:54.754005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 11:40:54.754094 ==
3972 11:40:54.757075 Write leveling (Byte 0): 32 => 32
3973 11:40:54.760472 Write leveling (Byte 1): 32 => 32
3974 11:40:54.763845 DramcWriteLeveling(PI) end<-----
3975 11:40:54.763937
3976 11:40:54.764004 ==
3977 11:40:54.766870 Dram Type= 6, Freq= 0, CH_0, rank 0
3978 11:40:54.770916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 11:40:54.771006 ==
3980 11:40:54.774133 [Gating] SW mode calibration
3981 11:40:54.780422 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3982 11:40:54.786851 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3983 11:40:54.790549 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 11:40:54.793316 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 11:40:54.800616 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 11:40:54.803382 0 9 12 | B1->B0 | 3434 3131 | 0 1 | (0 1) (1 0)
3987 11:40:54.806713 0 9 16 | B1->B0 | 2929 2626 | 0 0 | (0 1) (0 0)
3988 11:40:54.813231 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 11:40:54.816529 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 11:40:54.819551 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 11:40:54.826269 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 11:40:54.829469 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 11:40:54.832771 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 11:40:54.839939 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3995 11:40:54.842938 0 10 16 | B1->B0 | 3a3a 4444 | 0 1 | (0 0) (0 0)
3996 11:40:54.846200 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 11:40:54.852623 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 11:40:54.855826 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 11:40:54.859564 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 11:40:54.865711 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 11:40:54.869223 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 11:40:54.875759 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4003 11:40:54.878813 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:40:54.882214 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:40:54.888745 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:40:54.892200 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:40:54.895057 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:40:54.901931 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:40:54.905068 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:40:54.908592 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:40:54.914972 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:40:54.918685 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:40:54.921749 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:40:54.928220 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:40:54.932344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:40:54.935127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:40:54.941308 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:40:54.945062 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4019 11:40:54.947848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 11:40:54.951145 Total UI for P1: 0, mck2ui 16
4021 11:40:54.954625 best dqsien dly found for B0: ( 0, 13, 12)
4022 11:40:54.957893 Total UI for P1: 0, mck2ui 16
4023 11:40:54.961433 best dqsien dly found for B1: ( 0, 13, 14)
4024 11:40:54.964501 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4025 11:40:54.967668 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4026 11:40:54.967773
4027 11:40:54.974045 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4028 11:40:54.977636 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4029 11:40:54.981171 [Gating] SW calibration Done
4030 11:40:54.981265 ==
4031 11:40:54.984384 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 11:40:54.987448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 11:40:54.987544 ==
4034 11:40:54.987612 RX Vref Scan: 0
4035 11:40:54.987675
4036 11:40:54.990921 RX Vref 0 -> 0, step: 1
4037 11:40:54.991010
4038 11:40:54.993970 RX Delay -230 -> 252, step: 16
4039 11:40:54.997235 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4040 11:40:55.001060 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4041 11:40:55.007494 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4042 11:40:55.010105 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4043 11:40:55.013698 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4044 11:40:55.017064 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4045 11:40:55.023402 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4046 11:40:55.026917 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4047 11:40:55.030327 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4048 11:40:55.033392 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4049 11:40:55.040071 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4050 11:40:55.043613 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4051 11:40:55.047097 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4052 11:40:55.049863 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4053 11:40:55.056807 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4054 11:40:55.060320 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4055 11:40:55.060410 ==
4056 11:40:55.062944 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 11:40:55.066546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 11:40:55.066650 ==
4059 11:40:55.069797 DQS Delay:
4060 11:40:55.069883 DQS0 = 0, DQS1 = 0
4061 11:40:55.069950 DQM Delay:
4062 11:40:55.072814 DQM0 = 42, DQM1 = 35
4063 11:40:55.072900 DQ Delay:
4064 11:40:55.076393 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4065 11:40:55.079866 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4066 11:40:55.082922 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4067 11:40:55.085979 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4068 11:40:55.086068
4069 11:40:55.086136
4070 11:40:55.089367 ==
4071 11:40:55.093051 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 11:40:55.096373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 11:40:55.096463 ==
4074 11:40:55.096530
4075 11:40:55.096591
4076 11:40:55.099347 TX Vref Scan disable
4077 11:40:55.099431 == TX Byte 0 ==
4078 11:40:55.105678 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4079 11:40:55.109593 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4080 11:40:55.109684 == TX Byte 1 ==
4081 11:40:55.115864 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4082 11:40:55.119019 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4083 11:40:55.119108 ==
4084 11:40:55.122401 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 11:40:55.125491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 11:40:55.125580 ==
4087 11:40:55.125647
4088 11:40:55.125784
4089 11:40:55.129153 TX Vref Scan disable
4090 11:40:55.131961 == TX Byte 0 ==
4091 11:40:55.135254 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4092 11:40:55.138695 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4093 11:40:55.141646 == TX Byte 1 ==
4094 11:40:55.145424 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4095 11:40:55.148841 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4096 11:40:55.152271
4097 11:40:55.152354 [DATLAT]
4098 11:40:55.152418 Freq=600, CH0 RK0
4099 11:40:55.152480
4100 11:40:55.155405 DATLAT Default: 0x9
4101 11:40:55.155481 0, 0xFFFF, sum = 0
4102 11:40:55.158310 1, 0xFFFF, sum = 0
4103 11:40:55.158413 2, 0xFFFF, sum = 0
4104 11:40:55.162153 3, 0xFFFF, sum = 0
4105 11:40:55.162254 4, 0xFFFF, sum = 0
4106 11:40:55.164731 5, 0xFFFF, sum = 0
4107 11:40:55.168530 6, 0xFFFF, sum = 0
4108 11:40:55.168621 7, 0xFFFF, sum = 0
4109 11:40:55.171538 8, 0x0, sum = 1
4110 11:40:55.171628 9, 0x0, sum = 2
4111 11:40:55.171696 10, 0x0, sum = 3
4112 11:40:55.174636 11, 0x0, sum = 4
4113 11:40:55.174738 best_step = 9
4114 11:40:55.174837
4115 11:40:55.174930 ==
4116 11:40:55.178005 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 11:40:55.185185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 11:40:55.185317 ==
4119 11:40:55.185481 RX Vref Scan: 1
4120 11:40:55.185603
4121 11:40:55.188355 RX Vref 0 -> 0, step: 1
4122 11:40:55.188439
4123 11:40:55.191501 RX Delay -179 -> 252, step: 8
4124 11:40:55.191586
4125 11:40:55.194566 Set Vref, RX VrefLevel [Byte0]: 51
4126 11:40:55.197635 [Byte1]: 59
4127 11:40:55.197782
4128 11:40:55.201348 Final RX Vref Byte 0 = 51 to rank0
4129 11:40:55.204300 Final RX Vref Byte 1 = 59 to rank0
4130 11:40:55.207886 Final RX Vref Byte 0 = 51 to rank1
4131 11:40:55.211124 Final RX Vref Byte 1 = 59 to rank1==
4132 11:40:55.214811 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 11:40:55.217647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 11:40:55.217736 ==
4135 11:40:55.220747 DQS Delay:
4136 11:40:55.220832 DQS0 = 0, DQS1 = 0
4137 11:40:55.224149 DQM Delay:
4138 11:40:55.224234 DQM0 = 42, DQM1 = 33
4139 11:40:55.224300 DQ Delay:
4140 11:40:55.227436 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4141 11:40:55.230946 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4142 11:40:55.234328 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4143 11:40:55.237441 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4144 11:40:55.240714
4145 11:40:55.240803
4146 11:40:55.247216 [DQSOSCAuto] RK0, (LSB)MR18= 0x463d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4147 11:40:55.250852 CH0 RK0: MR19=808, MR18=463D
4148 11:40:55.256967 CH0_RK0: MR19=0x808, MR18=0x463D, DQSOSC=396, MR23=63, INC=167, DEC=111
4149 11:40:55.257098
4150 11:40:55.260700 ----->DramcWriteLeveling(PI) begin...
4151 11:40:55.260823 ==
4152 11:40:55.263603 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 11:40:55.266970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 11:40:55.267073 ==
4155 11:40:55.270007 Write leveling (Byte 0): 34 => 34
4156 11:40:55.273687 Write leveling (Byte 1): 29 => 29
4157 11:40:55.276941 DramcWriteLeveling(PI) end<-----
4158 11:40:55.277061
4159 11:40:55.277190 ==
4160 11:40:55.279951 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 11:40:55.283468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 11:40:55.283681 ==
4163 11:40:55.286725 [Gating] SW mode calibration
4164 11:40:55.293419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4165 11:40:55.299739 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4166 11:40:55.303434 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 11:40:55.310258 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 11:40:55.312834 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 11:40:55.316868 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4170 11:40:55.323367 0 9 16 | B1->B0 | 2e2e 2727 | 1 1 | (1 1) (0 0)
4171 11:40:55.326167 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 11:40:55.329908 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 11:40:55.335928 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 11:40:55.339423 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 11:40:55.342695 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 11:40:55.349289 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 11:40:55.352518 0 10 12 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
4178 11:40:55.356026 0 10 16 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (1 1)
4179 11:40:55.362647 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 11:40:55.365501 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 11:40:55.369282 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 11:40:55.375428 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 11:40:55.378747 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 11:40:55.382428 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 11:40:55.388775 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 11:40:55.391982 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4187 11:40:55.396100 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:40:55.402612 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:40:55.405474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:40:55.408834 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:40:55.415538 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:40:55.418521 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:40:55.422074 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:40:55.428583 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:40:55.431873 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:40:55.434919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:40:55.441845 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:40:55.445166 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:40:55.448068 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:40:55.454540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:40:55.458244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4202 11:40:55.461395 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 11:40:55.464913 Total UI for P1: 0, mck2ui 16
4204 11:40:55.467758 best dqsien dly found for B0: ( 0, 13, 12)
4205 11:40:55.471056 Total UI for P1: 0, mck2ui 16
4206 11:40:55.474563 best dqsien dly found for B1: ( 0, 13, 14)
4207 11:40:55.477819 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4208 11:40:55.481212 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4209 11:40:55.481300
4210 11:40:55.487907 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4211 11:40:55.490864 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4212 11:40:55.494330 [Gating] SW calibration Done
4213 11:40:55.494419 ==
4214 11:40:55.497688 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 11:40:55.501031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 11:40:55.501149 ==
4217 11:40:55.501248 RX Vref Scan: 0
4218 11:40:55.501341
4219 11:40:55.504053 RX Vref 0 -> 0, step: 1
4220 11:40:55.504151
4221 11:40:55.507834 RX Delay -230 -> 252, step: 16
4222 11:40:55.510421 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4223 11:40:55.517560 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4224 11:40:55.520509 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4225 11:40:55.524402 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4226 11:40:55.527230 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4227 11:40:55.530396 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4228 11:40:55.537085 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4229 11:40:55.540197 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4230 11:40:55.543798 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4231 11:40:55.547213 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4232 11:40:55.553541 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4233 11:40:55.556817 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4234 11:40:55.560177 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4235 11:40:55.563199 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4236 11:40:55.569830 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4237 11:40:55.573028 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4238 11:40:55.573114 ==
4239 11:40:55.576690 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 11:40:55.579616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 11:40:55.579695 ==
4242 11:40:55.582942 DQS Delay:
4243 11:40:55.583045 DQS0 = 0, DQS1 = 0
4244 11:40:55.583135 DQM Delay:
4245 11:40:55.586335 DQM0 = 42, DQM1 = 33
4246 11:40:55.586407 DQ Delay:
4247 11:40:55.589751 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4248 11:40:55.593087 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4249 11:40:55.596111 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4250 11:40:55.599899 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4251 11:40:55.600002
4252 11:40:55.600117
4253 11:40:55.603071 ==
4254 11:40:55.603168 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 11:40:55.609377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 11:40:55.609470 ==
4257 11:40:55.609535
4258 11:40:55.609593
4259 11:40:55.612576 TX Vref Scan disable
4260 11:40:55.612652 == TX Byte 0 ==
4261 11:40:55.619180 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4262 11:40:55.622532 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4263 11:40:55.622645 == TX Byte 1 ==
4264 11:40:55.629015 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4265 11:40:55.632460 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4266 11:40:55.632548 ==
4267 11:40:55.635431 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 11:40:55.638842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 11:40:55.638934 ==
4270 11:40:55.639001
4271 11:40:55.639062
4272 11:40:55.642126 TX Vref Scan disable
4273 11:40:55.645601 == TX Byte 0 ==
4274 11:40:55.649878 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4275 11:40:55.652379 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4276 11:40:55.655719 == TX Byte 1 ==
4277 11:40:55.658723 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4278 11:40:55.665499 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4279 11:40:55.665604
4280 11:40:55.665673 [DATLAT]
4281 11:40:55.665733 Freq=600, CH0 RK1
4282 11:40:55.665793
4283 11:40:55.668833 DATLAT Default: 0x9
4284 11:40:55.668917 0, 0xFFFF, sum = 0
4285 11:40:55.671984 1, 0xFFFF, sum = 0
4286 11:40:55.672118 2, 0xFFFF, sum = 0
4287 11:40:55.675118 3, 0xFFFF, sum = 0
4288 11:40:55.678208 4, 0xFFFF, sum = 0
4289 11:40:55.678296 5, 0xFFFF, sum = 0
4290 11:40:55.681585 6, 0xFFFF, sum = 0
4291 11:40:55.681671 7, 0xFFFF, sum = 0
4292 11:40:55.685041 8, 0x0, sum = 1
4293 11:40:55.685129 9, 0x0, sum = 2
4294 11:40:55.685196 10, 0x0, sum = 3
4295 11:40:55.688014 11, 0x0, sum = 4
4296 11:40:55.688148 best_step = 9
4297 11:40:55.688215
4298 11:40:55.691571 ==
4299 11:40:55.691684 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 11:40:55.698245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 11:40:55.698374 ==
4302 11:40:55.698472 RX Vref Scan: 0
4303 11:40:55.698562
4304 11:40:55.701489 RX Vref 0 -> 0, step: 1
4305 11:40:55.701575
4306 11:40:55.704713 RX Delay -179 -> 252, step: 8
4307 11:40:55.711431 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4308 11:40:55.714733 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4309 11:40:55.717591 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4310 11:40:55.720975 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4311 11:40:55.724172 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4312 11:40:55.731227 iDelay=197, Bit 5, Center 32 (-115 ~ 180) 296
4313 11:40:55.734254 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4314 11:40:55.738083 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4315 11:40:55.740697 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4316 11:40:55.747634 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4317 11:40:55.750977 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4318 11:40:55.754122 iDelay=197, Bit 11, Center 24 (-131 ~ 180) 312
4319 11:40:55.757910 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4320 11:40:55.763825 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4321 11:40:55.767170 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4322 11:40:55.770586 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4323 11:40:55.770673 ==
4324 11:40:55.773707 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 11:40:55.777233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 11:40:55.780421 ==
4327 11:40:55.780509 DQS Delay:
4328 11:40:55.780574 DQS0 = 0, DQS1 = 0
4329 11:40:55.784086 DQM Delay:
4330 11:40:55.784169 DQM0 = 40, DQM1 = 32
4331 11:40:55.787761 DQ Delay:
4332 11:40:55.787844 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4333 11:40:55.790315 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4334 11:40:55.793884 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4335 11:40:55.796973 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4336 11:40:55.797060
4337 11:40:55.800675
4338 11:40:55.807058 [DQSOSCAuto] RK1, (LSB)MR18= 0x423d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4339 11:40:55.809868 CH0 RK1: MR19=808, MR18=423D
4340 11:40:55.816974 CH0_RK1: MR19=0x808, MR18=0x423D, DQSOSC=397, MR23=63, INC=166, DEC=110
4341 11:40:55.820103 [RxdqsGatingPostProcess] freq 600
4342 11:40:55.823291 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 11:40:55.826842 Pre-setting of DQS Precalculation
4344 11:40:55.833035 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 11:40:55.833146 ==
4346 11:40:55.836490 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 11:40:55.840062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 11:40:55.840167 ==
4349 11:40:55.846749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 11:40:55.849798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4351 11:40:55.854322 [CA 0] Center 35 (5~66) winsize 62
4352 11:40:55.857418 [CA 1] Center 35 (5~66) winsize 62
4353 11:40:55.860460 [CA 2] Center 34 (4~65) winsize 62
4354 11:40:55.864468 [CA 3] Center 34 (3~65) winsize 63
4355 11:40:55.868037 [CA 4] Center 34 (3~65) winsize 63
4356 11:40:55.870370 [CA 5] Center 33 (3~64) winsize 62
4357 11:40:55.870458
4358 11:40:55.873980 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4359 11:40:55.874067
4360 11:40:55.877336 [CATrainingPosCal] consider 1 rank data
4361 11:40:55.880353 u2DelayCellTimex100 = 270/100 ps
4362 11:40:55.883786 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 11:40:55.890354 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4364 11:40:55.893571 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 11:40:55.897103 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4366 11:40:55.899926 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4367 11:40:55.903418 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 11:40:55.903505
4369 11:40:55.907030 CA PerBit enable=1, Macro0, CA PI delay=33
4370 11:40:55.907117
4371 11:40:55.910584 [CBTSetCACLKResult] CA Dly = 33
4372 11:40:55.913902 CS Dly: 3 (0~34)
4373 11:40:55.914007 ==
4374 11:40:55.917406 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 11:40:55.920167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 11:40:55.920254 ==
4377 11:40:55.926501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 11:40:55.929648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4379 11:40:55.934279 [CA 0] Center 35 (5~66) winsize 62
4380 11:40:55.937729 [CA 1] Center 35 (5~66) winsize 62
4381 11:40:55.940886 [CA 2] Center 34 (4~65) winsize 62
4382 11:40:55.944480 [CA 3] Center 34 (3~65) winsize 63
4383 11:40:55.947212 [CA 4] Center 34 (4~65) winsize 62
4384 11:40:55.950680 [CA 5] Center 33 (3~64) winsize 62
4385 11:40:55.950780
4386 11:40:55.954078 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4387 11:40:55.954166
4388 11:40:55.957450 [CATrainingPosCal] consider 2 rank data
4389 11:40:55.960425 u2DelayCellTimex100 = 270/100 ps
4390 11:40:55.966939 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4391 11:40:55.970727 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 11:40:55.973880 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 11:40:55.977178 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4394 11:40:55.980193 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 11:40:55.983432 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 11:40:55.983519
4397 11:40:55.986624 CA PerBit enable=1, Macro0, CA PI delay=33
4398 11:40:55.986711
4399 11:40:55.990317 [CBTSetCACLKResult] CA Dly = 33
4400 11:40:55.993464 CS Dly: 4 (0~36)
4401 11:40:55.993550
4402 11:40:55.997193 ----->DramcWriteLeveling(PI) begin...
4403 11:40:55.997279 ==
4404 11:40:56.000312 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 11:40:56.003569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 11:40:56.003656 ==
4407 11:40:56.006778 Write leveling (Byte 0): 27 => 27
4408 11:40:56.009863 Write leveling (Byte 1): 28 => 28
4409 11:40:56.013190 DramcWriteLeveling(PI) end<-----
4410 11:40:56.013279
4411 11:40:56.013345 ==
4412 11:40:56.016652 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 11:40:56.020138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 11:40:56.020227 ==
4415 11:40:56.022882 [Gating] SW mode calibration
4416 11:40:56.029609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 11:40:56.036192 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 11:40:56.039380 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 11:40:56.046095 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 11:40:56.049148 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 11:40:56.052405 0 9 12 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
4422 11:40:56.058901 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 11:40:56.062669 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 11:40:56.065779 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 11:40:56.072665 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 11:40:56.075689 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 11:40:56.079286 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 11:40:56.086136 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 11:40:56.089201 0 10 12 | B1->B0 | 3232 3535 | 0 0 | (0 0) (1 1)
4430 11:40:56.092253 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:40:56.098810 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:40:56.101953 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 11:40:56.105115 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 11:40:56.112012 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 11:40:56.115478 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 11:40:56.118909 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 11:40:56.124828 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 11:40:56.128613 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:40:56.131729 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:40:56.138176 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:40:56.141710 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:40:56.144949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:40:56.151447 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:40:56.154502 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:40:56.157998 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:40:56.164271 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:40:56.168351 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:40:56.170726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:40:56.177873 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:40:56.181013 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:40:56.184191 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:40:56.190646 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:40:56.194512 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4454 11:40:56.197287 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 11:40:56.200453 Total UI for P1: 0, mck2ui 16
4456 11:40:56.204012 best dqsien dly found for B0: ( 0, 13, 12)
4457 11:40:56.207530 Total UI for P1: 0, mck2ui 16
4458 11:40:56.210453 best dqsien dly found for B1: ( 0, 13, 14)
4459 11:40:56.213961 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4460 11:40:56.217472 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4461 11:40:56.217562
4462 11:40:56.223602 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4463 11:40:56.227169 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4464 11:40:56.230210 [Gating] SW calibration Done
4465 11:40:56.230324 ==
4466 11:40:56.233522 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 11:40:56.236766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 11:40:56.236854 ==
4469 11:40:56.236922 RX Vref Scan: 0
4470 11:40:56.236984
4471 11:40:56.239853 RX Vref 0 -> 0, step: 1
4472 11:40:56.239937
4473 11:40:56.243585 RX Delay -230 -> 252, step: 16
4474 11:40:56.247153 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4475 11:40:56.253895 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4476 11:40:56.256747 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4477 11:40:56.260326 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4478 11:40:56.262903 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4479 11:40:56.266296 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4480 11:40:56.273131 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4481 11:40:56.276249 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4482 11:40:56.279994 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4483 11:40:56.283151 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4484 11:40:56.289647 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4485 11:40:56.292618 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4486 11:40:56.296488 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4487 11:40:56.299276 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4488 11:40:56.305827 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4489 11:40:56.308884 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4490 11:40:56.308992 ==
4491 11:40:56.312655 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 11:40:56.315678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 11:40:56.315786 ==
4494 11:40:56.319151 DQS Delay:
4495 11:40:56.319230 DQS0 = 0, DQS1 = 0
4496 11:40:56.322410 DQM Delay:
4497 11:40:56.322490 DQM0 = 45, DQM1 = 37
4498 11:40:56.322555 DQ Delay:
4499 11:40:56.325742 DQ0 =57, DQ1 =33, DQ2 =33, DQ3 =41
4500 11:40:56.328788 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4501 11:40:56.332452 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4502 11:40:56.335560 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4503 11:40:56.335686
4504 11:40:56.335781
4505 11:40:56.338625 ==
4506 11:40:56.341717 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 11:40:56.345474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 11:40:56.345592 ==
4509 11:40:56.345694
4510 11:40:56.345785
4511 11:40:56.348391 TX Vref Scan disable
4512 11:40:56.348485 == TX Byte 0 ==
4513 11:40:56.355092 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4514 11:40:56.358288 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4515 11:40:56.358403 == TX Byte 1 ==
4516 11:40:56.364685 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4517 11:40:56.368430 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4518 11:40:56.368521 ==
4519 11:40:56.371485 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 11:40:56.374490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 11:40:56.374603 ==
4522 11:40:56.374699
4523 11:40:56.374793
4524 11:40:56.378089 TX Vref Scan disable
4525 11:40:56.381290 == TX Byte 0 ==
4526 11:40:56.384547 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4527 11:40:56.387898 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4528 11:40:56.391056 == TX Byte 1 ==
4529 11:40:56.394335 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4530 11:40:56.400969 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4531 11:40:56.401088
4532 11:40:56.401175 [DATLAT]
4533 11:40:56.401241 Freq=600, CH1 RK0
4534 11:40:56.401305
4535 11:40:56.404672 DATLAT Default: 0x9
4536 11:40:56.404750 0, 0xFFFF, sum = 0
4537 11:40:56.407627 1, 0xFFFF, sum = 0
4538 11:40:56.410970 2, 0xFFFF, sum = 0
4539 11:40:56.411055 3, 0xFFFF, sum = 0
4540 11:40:56.414401 4, 0xFFFF, sum = 0
4541 11:40:56.414510 5, 0xFFFF, sum = 0
4542 11:40:56.417590 6, 0xFFFF, sum = 0
4543 11:40:56.417673 7, 0xFFFF, sum = 0
4544 11:40:56.420816 8, 0x0, sum = 1
4545 11:40:56.420893 9, 0x0, sum = 2
4546 11:40:56.420957 10, 0x0, sum = 3
4547 11:40:56.424198 11, 0x0, sum = 4
4548 11:40:56.424292 best_step = 9
4549 11:40:56.424359
4550 11:40:56.427324 ==
4551 11:40:56.427405 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 11:40:56.433771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 11:40:56.433899 ==
4554 11:40:56.433982 RX Vref Scan: 1
4555 11:40:56.434046
4556 11:40:56.437418 RX Vref 0 -> 0, step: 1
4557 11:40:56.437492
4558 11:40:56.440111 RX Delay -179 -> 252, step: 8
4559 11:40:56.440190
4560 11:40:56.443883 Set Vref, RX VrefLevel [Byte0]: 50
4561 11:40:56.447050 [Byte1]: 52
4562 11:40:56.447176
4563 11:40:56.450325 Final RX Vref Byte 0 = 50 to rank0
4564 11:40:56.453656 Final RX Vref Byte 1 = 52 to rank0
4565 11:40:56.456982 Final RX Vref Byte 0 = 50 to rank1
4566 11:40:56.459982 Final RX Vref Byte 1 = 52 to rank1==
4567 11:40:56.463657 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 11:40:56.467117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 11:40:56.470250 ==
4570 11:40:56.470367 DQS Delay:
4571 11:40:56.470462 DQS0 = 0, DQS1 = 0
4572 11:40:56.473653 DQM Delay:
4573 11:40:56.473778 DQM0 = 41, DQM1 = 34
4574 11:40:56.477104 DQ Delay:
4575 11:40:56.479699 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =44
4576 11:40:56.479802 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4577 11:40:56.483009 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4578 11:40:56.490086 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4579 11:40:56.490227
4580 11:40:56.490329
4581 11:40:56.496287 [DQSOSCAuto] RK0, (LSB)MR18= 0x2741, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4582 11:40:56.499570 CH1 RK0: MR19=808, MR18=2741
4583 11:40:56.506223 CH1_RK0: MR19=0x808, MR18=0x2741, DQSOSC=397, MR23=63, INC=166, DEC=110
4584 11:40:56.506361
4585 11:40:56.509993 ----->DramcWriteLeveling(PI) begin...
4586 11:40:56.510088 ==
4587 11:40:56.512738 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 11:40:56.516648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:40:56.516741 ==
4590 11:40:56.519093 Write leveling (Byte 0): 28 => 28
4591 11:40:56.523094 Write leveling (Byte 1): 28 => 28
4592 11:40:56.526012 DramcWriteLeveling(PI) end<-----
4593 11:40:56.526102
4594 11:40:56.526205 ==
4595 11:40:56.529184 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 11:40:56.532453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 11:40:56.535802 ==
4598 11:40:56.535890 [Gating] SW mode calibration
4599 11:40:56.545777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4600 11:40:56.548694 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4601 11:40:56.552189 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 11:40:56.559041 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 11:40:56.561924 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4604 11:40:56.565209 0 9 12 | B1->B0 | 3030 2828 | 0 0 | (0 0) (1 0)
4605 11:40:56.572261 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 11:40:56.575540 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 11:40:56.578711 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 11:40:56.584923 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 11:40:56.589015 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 11:40:56.591943 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 11:40:56.598169 0 10 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
4612 11:40:56.601739 0 10 12 | B1->B0 | 3232 3f3f | 0 1 | (0 0) (0 0)
4613 11:40:56.604650 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 11:40:56.611551 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 11:40:56.614700 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 11:40:56.618168 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 11:40:56.624984 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 11:40:56.628431 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 11:40:56.631263 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4620 11:40:56.638393 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4621 11:40:56.641225 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:40:56.644694 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:40:56.651237 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:40:56.654678 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:40:56.657545 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:40:56.664395 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:40:56.667781 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:40:56.671008 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:40:56.677335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:40:56.681155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:40:56.683601 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:40:56.690206 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:40:56.693729 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:40:56.696940 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 11:40:56.703321 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:40:56.706893 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 11:40:56.710161 Total UI for P1: 0, mck2ui 16
4638 11:40:56.713809 best dqsien dly found for B0: ( 0, 13, 10)
4639 11:40:56.716629 Total UI for P1: 0, mck2ui 16
4640 11:40:56.720065 best dqsien dly found for B1: ( 0, 13, 10)
4641 11:40:56.722896 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4642 11:40:56.726755 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4643 11:40:56.726875
4644 11:40:56.730227 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4645 11:40:56.736473 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4646 11:40:56.736577 [Gating] SW calibration Done
4647 11:40:56.739741 ==
4648 11:40:56.739832 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 11:40:56.746111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 11:40:56.746218 ==
4651 11:40:56.746307 RX Vref Scan: 0
4652 11:40:56.746389
4653 11:40:56.749451 RX Vref 0 -> 0, step: 1
4654 11:40:56.749547
4655 11:40:56.752772 RX Delay -230 -> 252, step: 16
4656 11:40:56.755782 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4657 11:40:56.759709 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4658 11:40:56.765806 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4659 11:40:56.769286 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4660 11:40:56.772461 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4661 11:40:56.775900 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4662 11:40:56.782837 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4663 11:40:56.786141 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4664 11:40:56.788841 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4665 11:40:56.791978 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4666 11:40:56.798889 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4667 11:40:56.802118 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4668 11:40:56.805298 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4669 11:40:56.808955 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4670 11:40:56.815209 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4671 11:40:56.818406 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4672 11:40:56.818504 ==
4673 11:40:56.821767 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 11:40:56.825394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 11:40:56.825514 ==
4676 11:40:56.828790 DQS Delay:
4677 11:40:56.828878 DQS0 = 0, DQS1 = 0
4678 11:40:56.828964 DQM Delay:
4679 11:40:56.831553 DQM0 = 42, DQM1 = 39
4680 11:40:56.831663 DQ Delay:
4681 11:40:56.835279 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4682 11:40:56.838281 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4683 11:40:56.841821 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4684 11:40:56.844966 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4685 11:40:56.845060
4686 11:40:56.845146
4687 11:40:56.845227 ==
4688 11:40:56.848060 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 11:40:56.854851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 11:40:56.854963 ==
4691 11:40:56.855053
4692 11:40:56.855135
4693 11:40:56.855217 TX Vref Scan disable
4694 11:40:56.858775 == TX Byte 0 ==
4695 11:40:56.862056 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4696 11:40:56.868437 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4697 11:40:56.868540 == TX Byte 1 ==
4698 11:40:56.871565 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4699 11:40:56.877972 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4700 11:40:56.878074 ==
4701 11:40:56.881661 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 11:40:56.884718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 11:40:56.884811 ==
4704 11:40:56.884897
4705 11:40:56.884980
4706 11:40:56.888213 TX Vref Scan disable
4707 11:40:56.891832 == TX Byte 0 ==
4708 11:40:56.895288 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4709 11:40:56.898243 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4710 11:40:56.902180 == TX Byte 1 ==
4711 11:40:56.904788 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4712 11:40:56.907690 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4713 11:40:56.907775
4714 11:40:56.907859 [DATLAT]
4715 11:40:56.910977 Freq=600, CH1 RK1
4716 11:40:56.911084
4717 11:40:56.914664 DATLAT Default: 0x9
4718 11:40:56.914744 0, 0xFFFF, sum = 0
4719 11:40:56.917833 1, 0xFFFF, sum = 0
4720 11:40:56.917913 2, 0xFFFF, sum = 0
4721 11:40:56.921507 3, 0xFFFF, sum = 0
4722 11:40:56.921600 4, 0xFFFF, sum = 0
4723 11:40:56.924249 5, 0xFFFF, sum = 0
4724 11:40:56.924359 6, 0xFFFF, sum = 0
4725 11:40:56.927389 7, 0xFFFF, sum = 0
4726 11:40:56.927480 8, 0x0, sum = 1
4727 11:40:56.931456 9, 0x0, sum = 2
4728 11:40:56.931551 10, 0x0, sum = 3
4729 11:40:56.934058 11, 0x0, sum = 4
4730 11:40:56.934176 best_step = 9
4731 11:40:56.934280
4732 11:40:56.934385 ==
4733 11:40:56.937630 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 11:40:56.940818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 11:40:56.940911 ==
4736 11:40:56.943998 RX Vref Scan: 0
4737 11:40:56.944152
4738 11:40:56.947323 RX Vref 0 -> 0, step: 1
4739 11:40:56.947418
4740 11:40:56.947524 RX Delay -179 -> 252, step: 8
4741 11:40:56.955558 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4742 11:40:56.958711 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4743 11:40:56.962085 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4744 11:40:56.965064 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4745 11:40:56.972329 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4746 11:40:56.975135 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4747 11:40:56.978646 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4748 11:40:56.981629 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4749 11:40:56.988369 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4750 11:40:56.992056 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4751 11:40:56.994886 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4752 11:40:56.998415 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4753 11:40:57.005222 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4754 11:40:57.008413 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4755 11:40:57.011679 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4756 11:40:57.014772 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4757 11:40:57.014859 ==
4758 11:40:57.017968 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 11:40:57.024580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 11:40:57.024689 ==
4761 11:40:57.024760 DQS Delay:
4762 11:40:57.028465 DQS0 = 0, DQS1 = 0
4763 11:40:57.028556 DQM Delay:
4764 11:40:57.031129 DQM0 = 38, DQM1 = 35
4765 11:40:57.031215 DQ Delay:
4766 11:40:57.034738 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =40
4767 11:40:57.037544 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4768 11:40:57.041211 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4769 11:40:57.044018 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4770 11:40:57.044151
4771 11:40:57.044219
4772 11:40:57.050977 [DQSOSCAuto] RK1, (LSB)MR18= 0x385c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4773 11:40:57.054349 CH1 RK1: MR19=808, MR18=385C
4774 11:40:57.060872 CH1_RK1: MR19=0x808, MR18=0x385C, DQSOSC=392, MR23=63, INC=170, DEC=113
4775 11:40:57.064794 [RxdqsGatingPostProcess] freq 600
4776 11:40:57.070609 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4777 11:40:57.070742 Pre-setting of DQS Precalculation
4778 11:40:57.076919 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4779 11:40:57.083838 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4780 11:40:57.090345 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4781 11:40:57.090483
4782 11:40:57.090593
4783 11:40:57.093872 [Calibration Summary] 1200 Mbps
4784 11:40:57.097310 CH 0, Rank 0
4785 11:40:57.097399 SW Impedance : PASS
4786 11:40:57.100304 DUTY Scan : NO K
4787 11:40:57.103736 ZQ Calibration : PASS
4788 11:40:57.103826 Jitter Meter : NO K
4789 11:40:57.107185 CBT Training : PASS
4790 11:40:57.107260 Write leveling : PASS
4791 11:40:57.110246 RX DQS gating : PASS
4792 11:40:57.113608 RX DQ/DQS(RDDQC) : PASS
4793 11:40:57.113711 TX DQ/DQS : PASS
4794 11:40:57.117287 RX DATLAT : PASS
4795 11:40:57.120359 RX DQ/DQS(Engine): PASS
4796 11:40:57.120433 TX OE : NO K
4797 11:40:57.123758 All Pass.
4798 11:40:57.123836
4799 11:40:57.123901 CH 0, Rank 1
4800 11:40:57.126688 SW Impedance : PASS
4801 11:40:57.126838 DUTY Scan : NO K
4802 11:40:57.130275 ZQ Calibration : PASS
4803 11:40:57.133128 Jitter Meter : NO K
4804 11:40:57.133203 CBT Training : PASS
4805 11:40:57.136523 Write leveling : PASS
4806 11:40:57.139944 RX DQS gating : PASS
4807 11:40:57.140099 RX DQ/DQS(RDDQC) : PASS
4808 11:40:57.142979 TX DQ/DQS : PASS
4809 11:40:57.146483 RX DATLAT : PASS
4810 11:40:57.146572 RX DQ/DQS(Engine): PASS
4811 11:40:57.150126 TX OE : NO K
4812 11:40:57.150230 All Pass.
4813 11:40:57.150299
4814 11:40:57.153775 CH 1, Rank 0
4815 11:40:57.153862 SW Impedance : PASS
4816 11:40:57.156500 DUTY Scan : NO K
4817 11:40:57.159823 ZQ Calibration : PASS
4818 11:40:57.159910 Jitter Meter : NO K
4819 11:40:57.162885 CBT Training : PASS
4820 11:40:57.166221 Write leveling : PASS
4821 11:40:57.166310 RX DQS gating : PASS
4822 11:40:57.170359 RX DQ/DQS(RDDQC) : PASS
4823 11:40:57.173222 TX DQ/DQS : PASS
4824 11:40:57.173311 RX DATLAT : PASS
4825 11:40:57.176162 RX DQ/DQS(Engine): PASS
4826 11:40:57.176247 TX OE : NO K
4827 11:40:57.180239 All Pass.
4828 11:40:57.180325
4829 11:40:57.180392 CH 1, Rank 1
4830 11:40:57.183341 SW Impedance : PASS
4831 11:40:57.183425 DUTY Scan : NO K
4832 11:40:57.186565 ZQ Calibration : PASS
4833 11:40:57.189626 Jitter Meter : NO K
4834 11:40:57.189713 CBT Training : PASS
4835 11:40:57.192687 Write leveling : PASS
4836 11:40:57.196010 RX DQS gating : PASS
4837 11:40:57.196113 RX DQ/DQS(RDDQC) : PASS
4838 11:40:57.199461 TX DQ/DQS : PASS
4839 11:40:57.202457 RX DATLAT : PASS
4840 11:40:57.202546 RX DQ/DQS(Engine): PASS
4841 11:40:57.205894 TX OE : NO K
4842 11:40:57.205982 All Pass.
4843 11:40:57.206049
4844 11:40:57.209483 DramC Write-DBI off
4845 11:40:57.212406 PER_BANK_REFRESH: Hybrid Mode
4846 11:40:57.212493 TX_TRACKING: ON
4847 11:40:57.222597 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4848 11:40:57.225723 [FAST_K] Save calibration result to emmc
4849 11:40:57.228762 dramc_set_vcore_voltage set vcore to 662500
4850 11:40:57.232078 Read voltage for 933, 3
4851 11:40:57.232175 Vio18 = 0
4852 11:40:57.232248 Vcore = 662500
4853 11:40:57.235468 Vdram = 0
4854 11:40:57.235540 Vddq = 0
4855 11:40:57.235606 Vmddr = 0
4856 11:40:57.242227 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4857 11:40:57.248733 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4858 11:40:57.248887 MEM_TYPE=3, freq_sel=17
4859 11:40:57.251770 sv_algorithm_assistance_LP4_1600
4860 11:40:57.255344 ============ PULL DRAM RESETB DOWN ============
4861 11:40:57.261634 ========== PULL DRAM RESETB DOWN end =========
4862 11:40:57.265480 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4863 11:40:57.268208 ===================================
4864 11:40:57.271442 LPDDR4 DRAM CONFIGURATION
4865 11:40:57.274770 ===================================
4866 11:40:57.274861 EX_ROW_EN[0] = 0x0
4867 11:40:57.278545 EX_ROW_EN[1] = 0x0
4868 11:40:57.278630 LP4Y_EN = 0x0
4869 11:40:57.281337 WORK_FSP = 0x0
4870 11:40:57.284835 WL = 0x3
4871 11:40:57.284922 RL = 0x3
4872 11:40:57.288225 BL = 0x2
4873 11:40:57.288310 RPST = 0x0
4874 11:40:57.291533 RD_PRE = 0x0
4875 11:40:57.291616 WR_PRE = 0x1
4876 11:40:57.295013 WR_PST = 0x0
4877 11:40:57.295096 DBI_WR = 0x0
4878 11:40:57.297804 DBI_RD = 0x0
4879 11:40:57.297888 OTF = 0x1
4880 11:40:57.300989 ===================================
4881 11:40:57.304610 ===================================
4882 11:40:57.307503 ANA top config
4883 11:40:57.311109 ===================================
4884 11:40:57.311198 DLL_ASYNC_EN = 0
4885 11:40:57.314401 ALL_SLAVE_EN = 1
4886 11:40:57.317887 NEW_RANK_MODE = 1
4887 11:40:57.321263 DLL_IDLE_MODE = 1
4888 11:40:57.324428 LP45_APHY_COMB_EN = 1
4889 11:40:57.324516 TX_ODT_DIS = 1
4890 11:40:57.327530 NEW_8X_MODE = 1
4891 11:40:57.331093 ===================================
4892 11:40:57.333793 ===================================
4893 11:40:57.337145 data_rate = 1866
4894 11:40:57.340768 CKR = 1
4895 11:40:57.344150 DQ_P2S_RATIO = 8
4896 11:40:57.347218 ===================================
4897 11:40:57.350223 CA_P2S_RATIO = 8
4898 11:40:57.350321 DQ_CA_OPEN = 0
4899 11:40:57.353682 DQ_SEMI_OPEN = 0
4900 11:40:57.357282 CA_SEMI_OPEN = 0
4901 11:40:57.360528 CA_FULL_RATE = 0
4902 11:40:57.363787 DQ_CKDIV4_EN = 1
4903 11:40:57.367260 CA_CKDIV4_EN = 1
4904 11:40:57.367350 CA_PREDIV_EN = 0
4905 11:40:57.370517 PH8_DLY = 0
4906 11:40:57.373760 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4907 11:40:57.376765 DQ_AAMCK_DIV = 4
4908 11:40:57.380482 CA_AAMCK_DIV = 4
4909 11:40:57.383666 CA_ADMCK_DIV = 4
4910 11:40:57.383744 DQ_TRACK_CA_EN = 0
4911 11:40:57.386600 CA_PICK = 933
4912 11:40:57.390886 CA_MCKIO = 933
4913 11:40:57.393791 MCKIO_SEMI = 0
4914 11:40:57.396539 PLL_FREQ = 3732
4915 11:40:57.400141 DQ_UI_PI_RATIO = 32
4916 11:40:57.403454 CA_UI_PI_RATIO = 0
4917 11:40:57.406955 ===================================
4918 11:40:57.409745 ===================================
4919 11:40:57.409838 memory_type:LPDDR4
4920 11:40:57.413251 GP_NUM : 10
4921 11:40:57.416652 SRAM_EN : 1
4922 11:40:57.416741 MD32_EN : 0
4923 11:40:57.420085 ===================================
4924 11:40:57.422813 [ANA_INIT] >>>>>>>>>>>>>>
4925 11:40:57.426674 <<<<<< [CONFIGURE PHASE]: ANA_TX
4926 11:40:57.429794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4927 11:40:57.433552 ===================================
4928 11:40:57.436242 data_rate = 1866,PCW = 0X8f00
4929 11:40:57.439385 ===================================
4930 11:40:57.442887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4931 11:40:57.445947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 11:40:57.452756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4933 11:40:57.455928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4934 11:40:57.459284 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4935 11:40:57.465778 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4936 11:40:57.465894 [ANA_INIT] flow start
4937 11:40:57.469403 [ANA_INIT] PLL >>>>>>>>
4938 11:40:57.473256 [ANA_INIT] PLL <<<<<<<<
4939 11:40:57.473353 [ANA_INIT] MIDPI >>>>>>>>
4940 11:40:57.476094 [ANA_INIT] MIDPI <<<<<<<<
4941 11:40:57.478963 [ANA_INIT] DLL >>>>>>>>
4942 11:40:57.479050 [ANA_INIT] flow end
4943 11:40:57.485639 ============ LP4 DIFF to SE enter ============
4944 11:40:57.489356 ============ LP4 DIFF to SE exit ============
4945 11:40:57.489457 [ANA_INIT] <<<<<<<<<<<<<
4946 11:40:57.492516 [Flow] Enable top DCM control >>>>>
4947 11:40:57.495826 [Flow] Enable top DCM control <<<<<
4948 11:40:57.498826 Enable DLL master slave shuffle
4949 11:40:57.505313 ==============================================================
4950 11:40:57.508875 Gating Mode config
4951 11:40:57.512182 ==============================================================
4952 11:40:57.515236 Config description:
4953 11:40:57.525426 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4954 11:40:57.532146 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4955 11:40:57.534967 SELPH_MODE 0: By rank 1: By Phase
4956 11:40:57.542142 ==============================================================
4957 11:40:57.545173 GAT_TRACK_EN = 1
4958 11:40:57.548459 RX_GATING_MODE = 2
4959 11:40:57.551527 RX_GATING_TRACK_MODE = 2
4960 11:40:57.554831 SELPH_MODE = 1
4961 11:40:57.554926 PICG_EARLY_EN = 1
4962 11:40:57.558746 VALID_LAT_VALUE = 1
4963 11:40:57.564873 ==============================================================
4964 11:40:57.568212 Enter into Gating configuration >>>>
4965 11:40:57.571128 Exit from Gating configuration <<<<
4966 11:40:57.574366 Enter into DVFS_PRE_config >>>>>
4967 11:40:57.584348 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4968 11:40:57.588121 Exit from DVFS_PRE_config <<<<<
4969 11:40:57.591010 Enter into PICG configuration >>>>
4970 11:40:57.594454 Exit from PICG configuration <<<<
4971 11:40:57.597688 [RX_INPUT] configuration >>>>>
4972 11:40:57.600730 [RX_INPUT] configuration <<<<<
4973 11:40:57.607348 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4974 11:40:57.610826 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4975 11:40:57.617451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 11:40:57.624021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 11:40:57.630742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4978 11:40:57.637084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4979 11:40:57.640700 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4980 11:40:57.643971 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4981 11:40:57.646994 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4982 11:40:57.653421 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4983 11:40:57.656766 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4984 11:40:57.660186 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4985 11:40:57.663184 ===================================
4986 11:40:57.666479 LPDDR4 DRAM CONFIGURATION
4987 11:40:57.669903 ===================================
4988 11:40:57.673167 EX_ROW_EN[0] = 0x0
4989 11:40:57.673256 EX_ROW_EN[1] = 0x0
4990 11:40:57.676484 LP4Y_EN = 0x0
4991 11:40:57.676572 WORK_FSP = 0x0
4992 11:40:57.679708 WL = 0x3
4993 11:40:57.679794 RL = 0x3
4994 11:40:57.683138 BL = 0x2
4995 11:40:57.683224 RPST = 0x0
4996 11:40:57.686126 RD_PRE = 0x0
4997 11:40:57.686212 WR_PRE = 0x1
4998 11:40:57.689677 WR_PST = 0x0
4999 11:40:57.689764 DBI_WR = 0x0
5000 11:40:57.692764 DBI_RD = 0x0
5001 11:40:57.696353 OTF = 0x1
5002 11:40:57.699267 ===================================
5003 11:40:57.703122 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5004 11:40:57.706192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5005 11:40:57.709343 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 11:40:57.712889 ===================================
5007 11:40:57.715941 LPDDR4 DRAM CONFIGURATION
5008 11:40:57.719284 ===================================
5009 11:40:57.722558 EX_ROW_EN[0] = 0x10
5010 11:40:57.722646 EX_ROW_EN[1] = 0x0
5011 11:40:57.725953 LP4Y_EN = 0x0
5012 11:40:57.726038 WORK_FSP = 0x0
5013 11:40:57.729468 WL = 0x3
5014 11:40:57.729555 RL = 0x3
5015 11:40:57.732300 BL = 0x2
5016 11:40:57.732383 RPST = 0x0
5017 11:40:57.736014 RD_PRE = 0x0
5018 11:40:57.736120 WR_PRE = 0x1
5019 11:40:57.739152 WR_PST = 0x0
5020 11:40:57.742353 DBI_WR = 0x0
5021 11:40:57.742440 DBI_RD = 0x0
5022 11:40:57.745662 OTF = 0x1
5023 11:40:57.748947 ===================================
5024 11:40:57.752152 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5025 11:40:57.757665 nWR fixed to 30
5026 11:40:57.760828 [ModeRegInit_LP4] CH0 RK0
5027 11:40:57.760921 [ModeRegInit_LP4] CH0 RK1
5028 11:40:57.764204 [ModeRegInit_LP4] CH1 RK0
5029 11:40:57.767772 [ModeRegInit_LP4] CH1 RK1
5030 11:40:57.767860 match AC timing 9
5031 11:40:57.773913 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5032 11:40:57.777233 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5033 11:40:57.780696 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5034 11:40:57.786925 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5035 11:40:57.790248 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5036 11:40:57.790347 ==
5037 11:40:57.793320 Dram Type= 6, Freq= 0, CH_0, rank 0
5038 11:40:57.797211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 11:40:57.800469 ==
5040 11:40:57.803496 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 11:40:57.810045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5042 11:40:57.813571 [CA 0] Center 37 (7~68) winsize 62
5043 11:40:57.816517 [CA 1] Center 37 (7~68) winsize 62
5044 11:40:57.820213 [CA 2] Center 34 (4~65) winsize 62
5045 11:40:57.823384 [CA 3] Center 34 (4~65) winsize 62
5046 11:40:57.826420 [CA 4] Center 33 (3~63) winsize 61
5047 11:40:57.829791 [CA 5] Center 32 (2~63) winsize 62
5048 11:40:57.829885
5049 11:40:57.832734 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5050 11:40:57.832820
5051 11:40:57.836472 [CATrainingPosCal] consider 1 rank data
5052 11:40:57.839683 u2DelayCellTimex100 = 270/100 ps
5053 11:40:57.843024 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5054 11:40:57.846559 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5055 11:40:57.852743 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5056 11:40:57.855962 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5057 11:40:57.859171 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5058 11:40:57.862935 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5059 11:40:57.863027
5060 11:40:57.865813 CA PerBit enable=1, Macro0, CA PI delay=32
5061 11:40:57.865900
5062 11:40:57.868857 [CBTSetCACLKResult] CA Dly = 32
5063 11:40:57.868943 CS Dly: 6 (0~37)
5064 11:40:57.872306 ==
5065 11:40:57.875783 Dram Type= 6, Freq= 0, CH_0, rank 1
5066 11:40:57.878916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5067 11:40:57.879006 ==
5068 11:40:57.882516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5069 11:40:57.889317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5070 11:40:57.892578 [CA 0] Center 38 (8~68) winsize 61
5071 11:40:57.895963 [CA 1] Center 37 (7~68) winsize 62
5072 11:40:57.899639 [CA 2] Center 34 (4~65) winsize 62
5073 11:40:57.903263 [CA 3] Center 34 (4~65) winsize 62
5074 11:40:57.905637 [CA 4] Center 33 (3~64) winsize 62
5075 11:40:57.909023 [CA 5] Center 32 (2~63) winsize 62
5076 11:40:57.909115
5077 11:40:57.912077 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5078 11:40:57.912177
5079 11:40:57.915570 [CATrainingPosCal] consider 2 rank data
5080 11:40:57.919015 u2DelayCellTimex100 = 270/100 ps
5081 11:40:57.922115 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5082 11:40:57.928601 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5083 11:40:57.932218 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5084 11:40:57.935428 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5085 11:40:57.938786 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5086 11:40:57.941796 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5087 11:40:57.941888
5088 11:40:57.945510 CA PerBit enable=1, Macro0, CA PI delay=32
5089 11:40:57.945599
5090 11:40:57.948703 [CBTSetCACLKResult] CA Dly = 32
5091 11:40:57.952221 CS Dly: 7 (0~39)
5092 11:40:57.952313
5093 11:40:57.954972 ----->DramcWriteLeveling(PI) begin...
5094 11:40:57.955059 ==
5095 11:40:57.958299 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 11:40:57.961400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 11:40:57.961490 ==
5098 11:40:57.964798 Write leveling (Byte 0): 32 => 32
5099 11:40:57.968447 Write leveling (Byte 1): 27 => 27
5100 11:40:57.971533 DramcWriteLeveling(PI) end<-----
5101 11:40:57.971620
5102 11:40:57.971692 ==
5103 11:40:57.974897 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 11:40:57.978105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 11:40:57.978193 ==
5106 11:40:57.981914 [Gating] SW mode calibration
5107 11:40:57.987942 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 11:40:57.995041 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5109 11:40:57.998454 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5110 11:40:58.004990 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 11:40:58.007894 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 11:40:58.011506 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 11:40:58.018414 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 11:40:58.020950 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 11:40:58.025378 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5116 11:40:58.031143 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5117 11:40:58.034440 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5118 11:40:58.037758 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 11:40:58.044201 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 11:40:58.047583 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 11:40:58.051297 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 11:40:58.057579 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:40:58.060938 0 15 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
5124 11:40:58.063923 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5125 11:40:58.070952 1 0 0 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5126 11:40:58.074026 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 11:40:58.076929 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:40:58.083855 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:40:58.086767 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 11:40:58.090460 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:40:58.096656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 11:40:58.100160 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5133 11:40:58.103547 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5134 11:40:58.109865 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:40:58.113794 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:40:58.117057 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:40:58.123312 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:40:58.126747 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:40:58.129983 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:40:58.136444 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:40:58.139699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:40:58.143302 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:40:58.149510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:40:58.152868 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:40:58.156204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:40:58.162837 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:40:58.166045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 11:40:58.169423 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5149 11:40:58.172551 Total UI for P1: 0, mck2ui 16
5150 11:40:58.175999 best dqsien dly found for B0: ( 1, 2, 24)
5151 11:40:58.182786 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5152 11:40:58.185993 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 11:40:58.189212 Total UI for P1: 0, mck2ui 16
5154 11:40:58.192153 best dqsien dly found for B1: ( 1, 3, 0)
5155 11:40:58.195562 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5156 11:40:58.198972 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5157 11:40:58.199061
5158 11:40:58.202404 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5159 11:40:58.205261 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5160 11:40:58.209271 [Gating] SW calibration Done
5161 11:40:58.209363 ==
5162 11:40:58.211813 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 11:40:58.215360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 11:40:58.218491 ==
5165 11:40:58.218599 RX Vref Scan: 0
5166 11:40:58.218668
5167 11:40:58.222296 RX Vref 0 -> 0, step: 1
5168 11:40:58.222382
5169 11:40:58.225292 RX Delay -80 -> 252, step: 8
5170 11:40:58.228503 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5171 11:40:58.231440 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5172 11:40:58.235431 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5173 11:40:58.238498 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5174 11:40:58.241745 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5175 11:40:58.247895 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5176 11:40:58.251778 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5177 11:40:58.254772 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5178 11:40:58.257701 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5179 11:40:58.261321 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5180 11:40:58.267797 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5181 11:40:58.271631 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5182 11:40:58.274867 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5183 11:40:58.277794 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5184 11:40:58.280762 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5185 11:40:58.287299 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5186 11:40:58.287384 ==
5187 11:40:58.291216 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 11:40:58.294172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 11:40:58.294257 ==
5190 11:40:58.294324 DQS Delay:
5191 11:40:58.297226 DQS0 = 0, DQS1 = 0
5192 11:40:58.297309 DQM Delay:
5193 11:40:58.300652 DQM0 = 101, DQM1 = 88
5194 11:40:58.300735 DQ Delay:
5195 11:40:58.303769 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5196 11:40:58.307182 DQ4 =103, DQ5 =95, DQ6 =107, DQ7 =107
5197 11:40:58.310505 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5198 11:40:58.313792 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5199 11:40:58.313876
5200 11:40:58.313941
5201 11:40:58.314001 ==
5202 11:40:58.317199 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 11:40:58.323539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 11:40:58.323624 ==
5205 11:40:58.323691
5206 11:40:58.323751
5207 11:40:58.323809 TX Vref Scan disable
5208 11:40:58.327342 == TX Byte 0 ==
5209 11:40:58.330471 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5210 11:40:58.333844 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5211 11:40:58.337049 == TX Byte 1 ==
5212 11:40:58.340443 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5213 11:40:58.346960 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5214 11:40:58.347043 ==
5215 11:40:58.350280 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 11:40:58.353530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 11:40:58.353614 ==
5218 11:40:58.353681
5219 11:40:58.353742
5220 11:40:58.356881 TX Vref Scan disable
5221 11:40:58.356964 == TX Byte 0 ==
5222 11:40:58.363700 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5223 11:40:58.366736 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5224 11:40:58.366820 == TX Byte 1 ==
5225 11:40:58.372973 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5226 11:40:58.376851 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5227 11:40:58.376934
5228 11:40:58.377000 [DATLAT]
5229 11:40:58.379697 Freq=933, CH0 RK0
5230 11:40:58.379780
5231 11:40:58.379845 DATLAT Default: 0xd
5232 11:40:58.382869 0, 0xFFFF, sum = 0
5233 11:40:58.386501 1, 0xFFFF, sum = 0
5234 11:40:58.386585 2, 0xFFFF, sum = 0
5235 11:40:58.389520 3, 0xFFFF, sum = 0
5236 11:40:58.389604 4, 0xFFFF, sum = 0
5237 11:40:58.392904 5, 0xFFFF, sum = 0
5238 11:40:58.392988 6, 0xFFFF, sum = 0
5239 11:40:58.395912 7, 0xFFFF, sum = 0
5240 11:40:58.395996 8, 0xFFFF, sum = 0
5241 11:40:58.399102 9, 0xFFFF, sum = 0
5242 11:40:58.399186 10, 0x0, sum = 1
5243 11:40:58.402703 11, 0x0, sum = 2
5244 11:40:58.402787 12, 0x0, sum = 3
5245 11:40:58.405719 13, 0x0, sum = 4
5246 11:40:58.405803 best_step = 11
5247 11:40:58.405868
5248 11:40:58.405929 ==
5249 11:40:58.409306 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 11:40:58.412612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 11:40:58.415841 ==
5252 11:40:58.415924 RX Vref Scan: 1
5253 11:40:58.415989
5254 11:40:58.419292 RX Vref 0 -> 0, step: 1
5255 11:40:58.419374
5256 11:40:58.422365 RX Delay -61 -> 252, step: 4
5257 11:40:58.422468
5258 11:40:58.425774 Set Vref, RX VrefLevel [Byte0]: 51
5259 11:40:58.428984 [Byte1]: 59
5260 11:40:58.429067
5261 11:40:58.432554 Final RX Vref Byte 0 = 51 to rank0
5262 11:40:58.435881 Final RX Vref Byte 1 = 59 to rank0
5263 11:40:58.438960 Final RX Vref Byte 0 = 51 to rank1
5264 11:40:58.442241 Final RX Vref Byte 1 = 59 to rank1==
5265 11:40:58.445532 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 11:40:58.448687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:40:58.448820 ==
5268 11:40:58.452296 DQS Delay:
5269 11:40:58.452383 DQS0 = 0, DQS1 = 0
5270 11:40:58.452451 DQM Delay:
5271 11:40:58.455004 DQM0 = 99, DQM1 = 88
5272 11:40:58.455105 DQ Delay:
5273 11:40:58.458249 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5274 11:40:58.461786 DQ4 =100, DQ5 =92, DQ6 =110, DQ7 =106
5275 11:40:58.465281 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5276 11:40:58.468258 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5277 11:40:58.468341
5278 11:40:58.468407
5279 11:40:58.478235 [DQSOSCAuto] RK0, (LSB)MR18= 0x150f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
5280 11:40:58.481346 CH0 RK0: MR19=505, MR18=150F
5281 11:40:58.487846 CH0_RK0: MR19=0x505, MR18=0x150F, DQSOSC=415, MR23=63, INC=62, DEC=41
5282 11:40:58.487936
5283 11:40:58.491594 ----->DramcWriteLeveling(PI) begin...
5284 11:40:58.491695 ==
5285 11:40:58.494728 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 11:40:58.497934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:40:58.498036 ==
5288 11:40:58.501081 Write leveling (Byte 0): 31 => 31
5289 11:40:58.504121 Write leveling (Byte 1): 28 => 28
5290 11:40:58.507322 DramcWriteLeveling(PI) end<-----
5291 11:40:58.507406
5292 11:40:58.507509 ==
5293 11:40:58.510883 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 11:40:58.514402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 11:40:58.514486 ==
5296 11:40:58.517592 [Gating] SW mode calibration
5297 11:40:58.524781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5298 11:40:58.530661 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5299 11:40:58.534180 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5300 11:40:58.540604 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 11:40:58.543892 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 11:40:58.547666 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 11:40:58.554199 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 11:40:58.557244 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 11:40:58.560014 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5306 11:40:58.566850 0 14 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
5307 11:40:58.570140 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5308 11:40:58.573821 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 11:40:58.579935 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 11:40:58.583479 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 11:40:58.586618 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 11:40:58.593606 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 11:40:58.596433 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5314 11:40:58.599895 0 15 28 | B1->B0 | 2727 3939 | 1 0 | (0 0) (0 0)
5315 11:40:58.606488 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5316 11:40:58.609803 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 11:40:58.613175 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:40:58.619710 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 11:40:58.622984 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 11:40:58.626274 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 11:40:58.632745 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5322 11:40:58.635942 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5323 11:40:58.639411 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5324 11:40:58.645767 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:40:58.648864 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:40:58.652730 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:40:58.658784 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:40:58.662594 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:40:58.665762 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:40:58.671945 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:40:58.675469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:40:58.678543 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:40:58.685217 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:40:58.688785 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:40:58.691672 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:40:58.698157 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 11:40:58.701773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5338 11:40:58.705172 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5339 11:40:58.711618 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5340 11:40:58.711727 Total UI for P1: 0, mck2ui 16
5341 11:40:58.718261 best dqsien dly found for B0: ( 1, 2, 26)
5342 11:40:58.721253 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 11:40:58.725111 Total UI for P1: 0, mck2ui 16
5344 11:40:58.728284 best dqsien dly found for B1: ( 1, 2, 30)
5345 11:40:58.731219 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5346 11:40:58.735020 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5347 11:40:58.735122
5348 11:40:58.738134 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5349 11:40:58.741011 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5350 11:40:58.744203 [Gating] SW calibration Done
5351 11:40:58.744302 ==
5352 11:40:58.747612 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 11:40:58.755278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 11:40:58.755403 ==
5355 11:40:58.755498 RX Vref Scan: 0
5356 11:40:58.755587
5357 11:40:58.757681 RX Vref 0 -> 0, step: 1
5358 11:40:58.757752
5359 11:40:58.761094 RX Delay -80 -> 252, step: 8
5360 11:40:58.764798 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5361 11:40:58.767288 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5362 11:40:58.770709 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5363 11:40:58.774395 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5364 11:40:58.777723 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5365 11:40:58.783990 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5366 11:40:58.787497 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5367 11:40:58.790601 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5368 11:40:58.793627 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5369 11:40:58.797285 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5370 11:40:58.803883 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5371 11:40:58.807005 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5372 11:40:58.810337 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5373 11:40:58.813365 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5374 11:40:58.816834 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5375 11:40:58.820146 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5376 11:40:58.823646 ==
5377 11:40:58.827105 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 11:40:58.830219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 11:40:58.830325 ==
5380 11:40:58.830417 DQS Delay:
5381 11:40:58.833264 DQS0 = 0, DQS1 = 0
5382 11:40:58.833363 DQM Delay:
5383 11:40:58.836458 DQM0 = 97, DQM1 = 91
5384 11:40:58.836556 DQ Delay:
5385 11:40:58.839808 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5386 11:40:58.843630 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5387 11:40:58.846640 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5388 11:40:58.850223 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5389 11:40:58.850324
5390 11:40:58.850421
5391 11:40:58.850515 ==
5392 11:40:58.853473 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 11:40:58.856459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 11:40:58.856562 ==
5395 11:40:58.856645
5396 11:40:58.859632
5397 11:40:58.859731 TX Vref Scan disable
5398 11:40:58.863139 == TX Byte 0 ==
5399 11:40:58.867002 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5400 11:40:58.869968 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5401 11:40:58.873118 == TX Byte 1 ==
5402 11:40:58.876069 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5403 11:40:58.879530 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5404 11:40:58.879614 ==
5405 11:40:58.882682 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 11:40:58.889861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 11:40:58.889946 ==
5408 11:40:58.890012
5409 11:40:58.890073
5410 11:40:58.893011 TX Vref Scan disable
5411 11:40:58.893094 == TX Byte 0 ==
5412 11:40:58.899272 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5413 11:40:58.902614 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5414 11:40:58.902697 == TX Byte 1 ==
5415 11:40:58.909411 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5416 11:40:58.912483 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5417 11:40:58.912567
5418 11:40:58.912632 [DATLAT]
5419 11:40:58.916024 Freq=933, CH0 RK1
5420 11:40:58.916113
5421 11:40:58.916178 DATLAT Default: 0xb
5422 11:40:58.918626 0, 0xFFFF, sum = 0
5423 11:40:58.918711 1, 0xFFFF, sum = 0
5424 11:40:58.922492 2, 0xFFFF, sum = 0
5425 11:40:58.922576 3, 0xFFFF, sum = 0
5426 11:40:58.925071 4, 0xFFFF, sum = 0
5427 11:40:58.928902 5, 0xFFFF, sum = 0
5428 11:40:58.929022 6, 0xFFFF, sum = 0
5429 11:40:58.932132 7, 0xFFFF, sum = 0
5430 11:40:58.932218 8, 0xFFFF, sum = 0
5431 11:40:58.935671 9, 0xFFFF, sum = 0
5432 11:40:58.935775 10, 0x0, sum = 1
5433 11:40:58.938715 11, 0x0, sum = 2
5434 11:40:58.938825 12, 0x0, sum = 3
5435 11:40:58.938921 13, 0x0, sum = 4
5436 11:40:58.941784 best_step = 11
5437 11:40:58.941884
5438 11:40:58.941975 ==
5439 11:40:58.944947 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 11:40:58.948334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 11:40:58.948450 ==
5442 11:40:58.951546 RX Vref Scan: 0
5443 11:40:58.951635
5444 11:40:58.954845 RX Vref 0 -> 0, step: 1
5445 11:40:58.954920
5446 11:40:58.954982 RX Delay -53 -> 252, step: 4
5447 11:40:58.962488 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5448 11:40:58.966043 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5449 11:40:58.969016 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5450 11:40:58.972397 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5451 11:40:58.976580 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5452 11:40:58.982334 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5453 11:40:58.985841 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5454 11:40:58.989017 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5455 11:40:58.992343 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5456 11:40:58.995357 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5457 11:40:58.998696 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5458 11:40:59.005427 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5459 11:40:59.008690 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5460 11:40:59.012026 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5461 11:40:59.015221 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5462 11:40:59.021928 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5463 11:40:59.022016 ==
5464 11:40:59.025135 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 11:40:59.028277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 11:40:59.028361 ==
5467 11:40:59.028428 DQS Delay:
5468 11:40:59.031658 DQS0 = 0, DQS1 = 0
5469 11:40:59.031741 DQM Delay:
5470 11:40:59.034734 DQM0 = 97, DQM1 = 89
5471 11:40:59.034817 DQ Delay:
5472 11:40:59.038520 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =96
5473 11:40:59.041316 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5474 11:40:59.044507 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5475 11:40:59.048332 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5476 11:40:59.048442
5477 11:40:59.048551
5478 11:40:59.058119 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5479 11:40:59.058227 CH0 RK1: MR19=505, MR18=1411
5480 11:40:59.065417 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5481 11:40:59.067781 [RxdqsGatingPostProcess] freq 933
5482 11:40:59.074489 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5483 11:40:59.078186 best DQS0 dly(2T, 0.5T) = (0, 10)
5484 11:40:59.080462 best DQS1 dly(2T, 0.5T) = (0, 11)
5485 11:40:59.084239 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5486 11:40:59.087357 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5487 11:40:59.090409 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 11:40:59.093930 best DQS1 dly(2T, 0.5T) = (0, 10)
5489 11:40:59.094021 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 11:40:59.097449 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5491 11:40:59.100547 Pre-setting of DQS Precalculation
5492 11:40:59.107243 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5493 11:40:59.107334 ==
5494 11:40:59.110122 Dram Type= 6, Freq= 0, CH_1, rank 0
5495 11:40:59.113574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 11:40:59.113660 ==
5497 11:40:59.120466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 11:40:59.126783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5499 11:40:59.130417 [CA 0] Center 36 (6~67) winsize 62
5500 11:40:59.133469 [CA 1] Center 36 (6~67) winsize 62
5501 11:40:59.137045 [CA 2] Center 34 (4~65) winsize 62
5502 11:40:59.140712 [CA 3] Center 34 (3~65) winsize 63
5503 11:40:59.143556 [CA 4] Center 34 (3~65) winsize 63
5504 11:40:59.146583 [CA 5] Center 33 (3~64) winsize 62
5505 11:40:59.146667
5506 11:40:59.149806 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5507 11:40:59.149890
5508 11:40:59.153466 [CATrainingPosCal] consider 1 rank data
5509 11:40:59.156692 u2DelayCellTimex100 = 270/100 ps
5510 11:40:59.159752 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 11:40:59.163455 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5512 11:40:59.166470 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5513 11:40:59.170155 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5514 11:40:59.172867 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5515 11:40:59.179701 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 11:40:59.179850
5517 11:40:59.183416 CA PerBit enable=1, Macro0, CA PI delay=33
5518 11:40:59.183514
5519 11:40:59.186712 [CBTSetCACLKResult] CA Dly = 33
5520 11:40:59.186808 CS Dly: 5 (0~36)
5521 11:40:59.186877 ==
5522 11:40:59.189329 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 11:40:59.192656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 11:40:59.196127 ==
5525 11:40:59.200166 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5526 11:40:59.205958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5527 11:40:59.209662 [CA 0] Center 36 (6~67) winsize 62
5528 11:40:59.212473 [CA 1] Center 36 (6~67) winsize 62
5529 11:40:59.216320 [CA 2] Center 34 (4~65) winsize 62
5530 11:40:59.219208 [CA 3] Center 33 (3~64) winsize 62
5531 11:40:59.223028 [CA 4] Center 34 (4~64) winsize 61
5532 11:40:59.226043 [CA 5] Center 33 (3~64) winsize 62
5533 11:40:59.226138
5534 11:40:59.229338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5535 11:40:59.229453
5536 11:40:59.232900 [CATrainingPosCal] consider 2 rank data
5537 11:40:59.236052 u2DelayCellTimex100 = 270/100 ps
5538 11:40:59.238993 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5539 11:40:59.242319 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5540 11:40:59.246143 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5541 11:40:59.252237 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5542 11:40:59.255665 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5543 11:40:59.259030 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5544 11:40:59.259114
5545 11:40:59.262408 CA PerBit enable=1, Macro0, CA PI delay=33
5546 11:40:59.262492
5547 11:40:59.265511 [CBTSetCACLKResult] CA Dly = 33
5548 11:40:59.265594 CS Dly: 6 (0~38)
5549 11:40:59.265660
5550 11:40:59.268887 ----->DramcWriteLeveling(PI) begin...
5551 11:40:59.272181 ==
5552 11:40:59.272265 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 11:40:59.278901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 11:40:59.278985 ==
5555 11:40:59.282441 Write leveling (Byte 0): 25 => 25
5556 11:40:59.285096 Write leveling (Byte 1): 27 => 27
5557 11:40:59.288417 DramcWriteLeveling(PI) end<-----
5558 11:40:59.288500
5559 11:40:59.288565 ==
5560 11:40:59.292124 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 11:40:59.295030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 11:40:59.295112 ==
5563 11:40:59.298513 [Gating] SW mode calibration
5564 11:40:59.304861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5565 11:40:59.311379 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5566 11:40:59.314737 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 11:40:59.318378 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 11:40:59.324844 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 11:40:59.327826 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 11:40:59.331509 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 11:40:59.338051 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 11:40:59.341123 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
5573 11:40:59.344329 0 14 28 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (0 0)
5574 11:40:59.350999 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 11:40:59.354153 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 11:40:59.357428 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 11:40:59.364186 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 11:40:59.367292 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 11:40:59.370422 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 11:40:59.377469 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 11:40:59.380567 0 15 28 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
5582 11:40:59.383739 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 11:40:59.390095 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 11:40:59.393639 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 11:40:59.397175 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 11:40:59.404290 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 11:40:59.406863 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 11:40:59.409863 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 11:40:59.416616 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5590 11:40:59.419961 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5591 11:40:59.423394 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:40:59.429658 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:40:59.433002 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:40:59.436805 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:40:59.442970 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:40:59.446552 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:40:59.449791 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:40:59.456097 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:40:59.460078 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:40:59.463275 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:40:59.469079 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:40:59.472378 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:40:59.475673 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 11:40:59.482509 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5605 11:40:59.485988 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 11:40:59.488733 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 11:40:59.492412 Total UI for P1: 0, mck2ui 16
5608 11:40:59.495319 best dqsien dly found for B0: ( 1, 2, 28)
5609 11:40:59.498591 Total UI for P1: 0, mck2ui 16
5610 11:40:59.502233 best dqsien dly found for B1: ( 1, 2, 26)
5611 11:40:59.505262 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5612 11:40:59.512300 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5613 11:40:59.512385
5614 11:40:59.515324 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5615 11:40:59.518391 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5616 11:40:59.521896 [Gating] SW calibration Done
5617 11:40:59.521980 ==
5618 11:40:59.525479 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 11:40:59.528754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 11:40:59.528839 ==
5621 11:40:59.531700 RX Vref Scan: 0
5622 11:40:59.531785
5623 11:40:59.531852 RX Vref 0 -> 0, step: 1
5624 11:40:59.531913
5625 11:40:59.535000 RX Delay -80 -> 252, step: 8
5626 11:40:59.538838 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5627 11:40:59.545026 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5628 11:40:59.548329 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5629 11:40:59.551541 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5630 11:40:59.554460 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5631 11:40:59.558163 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5632 11:40:59.561622 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5633 11:40:59.567991 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5634 11:40:59.571762 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5635 11:40:59.574886 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5636 11:40:59.578247 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5637 11:40:59.581289 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5638 11:40:59.588192 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5639 11:40:59.590803 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5640 11:40:59.594489 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5641 11:40:59.597882 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5642 11:40:59.597957 ==
5643 11:40:59.601337 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 11:40:59.603943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 11:40:59.607294 ==
5646 11:40:59.607366 DQS Delay:
5647 11:40:59.607427 DQS0 = 0, DQS1 = 0
5648 11:40:59.611615 DQM Delay:
5649 11:40:59.611685 DQM0 = 99, DQM1 = 94
5650 11:40:59.613948 DQ Delay:
5651 11:40:59.617592 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5652 11:40:59.620593 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5653 11:40:59.623728 DQ8 =79, DQ9 =87, DQ10 =91, DQ11 =87
5654 11:40:59.627194 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5655 11:40:59.627292
5656 11:40:59.627383
5657 11:40:59.627469 ==
5658 11:40:59.630683 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 11:40:59.634078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 11:40:59.634187 ==
5661 11:40:59.634281
5662 11:40:59.634370
5663 11:40:59.637169 TX Vref Scan disable
5664 11:40:59.640343 == TX Byte 0 ==
5665 11:40:59.643895 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5666 11:40:59.646976 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5667 11:40:59.650470 == TX Byte 1 ==
5668 11:40:59.653926 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5669 11:40:59.656925 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5670 11:40:59.657010 ==
5671 11:40:59.660183 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 11:40:59.663632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 11:40:59.667013 ==
5674 11:40:59.667096
5675 11:40:59.667162
5676 11:40:59.667223 TX Vref Scan disable
5677 11:40:59.670345 == TX Byte 0 ==
5678 11:40:59.673691 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5679 11:40:59.680008 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5680 11:40:59.680159 == TX Byte 1 ==
5681 11:40:59.684118 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5682 11:40:59.690193 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5683 11:40:59.690278
5684 11:40:59.690344 [DATLAT]
5685 11:40:59.690405 Freq=933, CH1 RK0
5686 11:40:59.690464
5687 11:40:59.693420 DATLAT Default: 0xd
5688 11:40:59.696642 0, 0xFFFF, sum = 0
5689 11:40:59.696727 1, 0xFFFF, sum = 0
5690 11:40:59.700216 2, 0xFFFF, sum = 0
5691 11:40:59.700300 3, 0xFFFF, sum = 0
5692 11:40:59.703728 4, 0xFFFF, sum = 0
5693 11:40:59.703813 5, 0xFFFF, sum = 0
5694 11:40:59.706804 6, 0xFFFF, sum = 0
5695 11:40:59.706889 7, 0xFFFF, sum = 0
5696 11:40:59.710027 8, 0xFFFF, sum = 0
5697 11:40:59.710113 9, 0xFFFF, sum = 0
5698 11:40:59.713141 10, 0x0, sum = 1
5699 11:40:59.713226 11, 0x0, sum = 2
5700 11:40:59.716347 12, 0x0, sum = 3
5701 11:40:59.716432 13, 0x0, sum = 4
5702 11:40:59.720208 best_step = 11
5703 11:40:59.720292
5704 11:40:59.720358 ==
5705 11:40:59.723409 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 11:40:59.726171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 11:40:59.726255 ==
5708 11:40:59.726321 RX Vref Scan: 1
5709 11:40:59.729348
5710 11:40:59.729431 RX Vref 0 -> 0, step: 1
5711 11:40:59.729511
5712 11:40:59.732950 RX Delay -61 -> 252, step: 4
5713 11:40:59.733033
5714 11:40:59.736363 Set Vref, RX VrefLevel [Byte0]: 50
5715 11:40:59.739459 [Byte1]: 52
5716 11:40:59.742981
5717 11:40:59.743065 Final RX Vref Byte 0 = 50 to rank0
5718 11:40:59.746349 Final RX Vref Byte 1 = 52 to rank0
5719 11:40:59.749405 Final RX Vref Byte 0 = 50 to rank1
5720 11:40:59.752637 Final RX Vref Byte 1 = 52 to rank1==
5721 11:40:59.756234 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:40:59.762530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:40:59.762648 ==
5724 11:40:59.762743 DQS Delay:
5725 11:40:59.765975 DQS0 = 0, DQS1 = 0
5726 11:40:59.766083 DQM Delay:
5727 11:40:59.766182 DQM0 = 98, DQM1 = 94
5728 11:40:59.769420 DQ Delay:
5729 11:40:59.773057 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5730 11:40:59.775715 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5731 11:40:59.779231 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88
5732 11:40:59.782872 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5733 11:40:59.782973
5734 11:40:59.783065
5735 11:40:59.789617 [DQSOSCAuto] RK0, (LSB)MR18= 0x414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5736 11:40:59.792919 CH1 RK0: MR19=505, MR18=414
5737 11:40:59.798678 CH1_RK0: MR19=0x505, MR18=0x414, DQSOSC=415, MR23=63, INC=62, DEC=41
5738 11:40:59.798764
5739 11:40:59.802350 ----->DramcWriteLeveling(PI) begin...
5740 11:40:59.802436 ==
5741 11:40:59.805280 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 11:40:59.809258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 11:40:59.809342 ==
5744 11:40:59.812489 Write leveling (Byte 0): 28 => 28
5745 11:40:59.815650 Write leveling (Byte 1): 28 => 28
5746 11:40:59.818489 DramcWriteLeveling(PI) end<-----
5747 11:40:59.818576
5748 11:40:59.818643 ==
5749 11:40:59.822279 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 11:40:59.828710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 11:40:59.828821 ==
5752 11:40:59.828915 [Gating] SW mode calibration
5753 11:40:59.838387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5754 11:40:59.841658 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5755 11:40:59.848076 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5756 11:40:59.851680 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 11:40:59.855138 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 11:40:59.861652 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 11:40:59.864766 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 11:40:59.868561 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 11:40:59.874803 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5762 11:40:59.878151 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5763 11:40:59.881149 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 11:40:59.887915 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 11:40:59.890970 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 11:40:59.894366 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 11:40:59.901072 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 11:40:59.904452 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 11:40:59.907428 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5770 11:40:59.913933 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5771 11:40:59.917689 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:40:59.921189 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 11:40:59.927546 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 11:40:59.930764 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 11:40:59.934022 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 11:40:59.940892 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 11:40:59.943728 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5778 11:40:59.947395 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5779 11:40:59.953667 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5780 11:40:59.957497 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:40:59.960206 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:40:59.966948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:40:59.970457 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:40:59.973779 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:40:59.980177 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:40:59.983389 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:40:59.986570 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:40:59.993365 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:40:59.996345 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:41:00.000070 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:41:00.006500 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 11:41:00.009745 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 11:41:00.012856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5794 11:41:00.016628 Total UI for P1: 0, mck2ui 16
5795 11:41:00.019361 best dqsien dly found for B0: ( 1, 2, 22)
5796 11:41:00.026170 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5797 11:41:00.029856 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 11:41:00.032510 Total UI for P1: 0, mck2ui 16
5799 11:41:00.036043 best dqsien dly found for B1: ( 1, 2, 28)
5800 11:41:00.039935 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5801 11:41:00.042463 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5802 11:41:00.042562
5803 11:41:00.045536 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5804 11:41:00.048867 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5805 11:41:00.052380 [Gating] SW calibration Done
5806 11:41:00.052504 ==
5807 11:41:00.055586 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 11:41:00.058940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 11:41:00.062436 ==
5810 11:41:00.062552 RX Vref Scan: 0
5811 11:41:00.062664
5812 11:41:00.065484 RX Vref 0 -> 0, step: 1
5813 11:41:00.065589
5814 11:41:00.068863 RX Delay -80 -> 252, step: 8
5815 11:41:00.071936 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5816 11:41:00.075477 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5817 11:41:00.078721 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5818 11:41:00.081936 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5819 11:41:00.088849 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5820 11:41:00.092167 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5821 11:41:00.095475 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5822 11:41:00.098231 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5823 11:41:00.101794 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5824 11:41:00.105204 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5825 11:41:00.111698 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5826 11:41:00.114708 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5827 11:41:00.118373 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5828 11:41:00.121249 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5829 11:41:00.124948 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5830 11:41:00.131184 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5831 11:41:00.131275 ==
5832 11:41:00.134615 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 11:41:00.137882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 11:41:00.137966 ==
5835 11:41:00.138033 DQS Delay:
5836 11:41:00.141206 DQS0 = 0, DQS1 = 0
5837 11:41:00.141290 DQM Delay:
5838 11:41:00.144501 DQM0 = 97, DQM1 = 94
5839 11:41:00.144584 DQ Delay:
5840 11:41:00.147864 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5841 11:41:00.151244 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5842 11:41:00.154612 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5843 11:41:00.157694 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5844 11:41:00.157784
5845 11:41:00.157850
5846 11:41:00.157911 ==
5847 11:41:00.160857 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 11:41:00.167337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 11:41:00.167426 ==
5850 11:41:00.167494
5851 11:41:00.167554
5852 11:41:00.167612 TX Vref Scan disable
5853 11:41:00.170656 == TX Byte 0 ==
5854 11:41:00.174281 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5855 11:41:00.180796 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5856 11:41:00.180884 == TX Byte 1 ==
5857 11:41:00.184264 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5858 11:41:00.190604 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5859 11:41:00.190690 ==
5860 11:41:00.193701 Dram Type= 6, Freq= 0, CH_1, rank 1
5861 11:41:00.196792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5862 11:41:00.196876 ==
5863 11:41:00.196942
5864 11:41:00.197002
5865 11:41:00.200019 TX Vref Scan disable
5866 11:41:00.203814 == TX Byte 0 ==
5867 11:41:00.207053 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5868 11:41:00.210647 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5869 11:41:00.213471 == TX Byte 1 ==
5870 11:41:00.216691 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5871 11:41:00.220323 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5872 11:41:00.220423
5873 11:41:00.220512 [DATLAT]
5874 11:41:00.223059 Freq=933, CH1 RK1
5875 11:41:00.223144
5876 11:41:00.226575 DATLAT Default: 0xb
5877 11:41:00.226659 0, 0xFFFF, sum = 0
5878 11:41:00.229593 1, 0xFFFF, sum = 0
5879 11:41:00.229678 2, 0xFFFF, sum = 0
5880 11:41:00.233147 3, 0xFFFF, sum = 0
5881 11:41:00.233234 4, 0xFFFF, sum = 0
5882 11:41:00.236242 5, 0xFFFF, sum = 0
5883 11:41:00.236328 6, 0xFFFF, sum = 0
5884 11:41:00.239361 7, 0xFFFF, sum = 0
5885 11:41:00.239446 8, 0xFFFF, sum = 0
5886 11:41:00.243064 9, 0xFFFF, sum = 0
5887 11:41:00.243150 10, 0x0, sum = 1
5888 11:41:00.246285 11, 0x0, sum = 2
5889 11:41:00.246369 12, 0x0, sum = 3
5890 11:41:00.249858 13, 0x0, sum = 4
5891 11:41:00.249945 best_step = 11
5892 11:41:00.250025
5893 11:41:00.250137 ==
5894 11:41:00.252764 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 11:41:00.256211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 11:41:00.259493 ==
5897 11:41:00.259578 RX Vref Scan: 0
5898 11:41:00.259644
5899 11:41:00.262793 RX Vref 0 -> 0, step: 1
5900 11:41:00.262877
5901 11:41:00.265811 RX Delay -53 -> 252, step: 4
5902 11:41:00.269077 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5903 11:41:00.272241 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5904 11:41:00.278877 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5905 11:41:00.282291 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5906 11:41:00.286219 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5907 11:41:00.288895 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5908 11:41:00.292419 iDelay=203, Bit 6, Center 102 (11 ~ 194) 184
5909 11:41:00.298916 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5910 11:41:00.302509 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5911 11:41:00.305598 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5912 11:41:00.308700 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5913 11:41:00.311778 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5914 11:41:00.318249 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5915 11:41:00.321789 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5916 11:41:00.324935 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5917 11:41:00.328539 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5918 11:41:00.328673 ==
5919 11:41:00.332019 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 11:41:00.334842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 11:41:00.338704 ==
5922 11:41:00.338791 DQS Delay:
5923 11:41:00.338858 DQS0 = 0, DQS1 = 0
5924 11:41:00.341984 DQM Delay:
5925 11:41:00.342069 DQM0 = 96, DQM1 = 92
5926 11:41:00.344875 DQ Delay:
5927 11:41:00.348250 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5928 11:41:00.351492 DQ4 =96, DQ5 =108, DQ6 =102, DQ7 =92
5929 11:41:00.354822 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =86
5930 11:41:00.357918 DQ12 =100, DQ13 =98, DQ14 =96, DQ15 =102
5931 11:41:00.358007
5932 11:41:00.358073
5933 11:41:00.364363 [DQSOSCAuto] RK1, (LSB)MR18= 0x81f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 419 ps
5934 11:41:00.368028 CH1 RK1: MR19=505, MR18=81F
5935 11:41:00.374458 CH1_RK1: MR19=0x505, MR18=0x81F, DQSOSC=412, MR23=63, INC=63, DEC=42
5936 11:41:00.377592 [RxdqsGatingPostProcess] freq 933
5937 11:41:00.381745 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5938 11:41:00.384673 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 11:41:00.387904 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 11:41:00.391114 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 11:41:00.394482 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 11:41:00.398173 best DQS0 dly(2T, 0.5T) = (0, 10)
5943 11:41:00.400852 best DQS1 dly(2T, 0.5T) = (0, 10)
5944 11:41:00.404278 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5945 11:41:00.407947 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5946 11:41:00.410677 Pre-setting of DQS Precalculation
5947 11:41:00.414423 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5948 11:41:00.424445 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5949 11:41:00.430377 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5950 11:41:00.430484
5951 11:41:00.430562
5952 11:41:00.434261 [Calibration Summary] 1866 Mbps
5953 11:41:00.434349 CH 0, Rank 0
5954 11:41:00.437576 SW Impedance : PASS
5955 11:41:00.437662 DUTY Scan : NO K
5956 11:41:00.440776 ZQ Calibration : PASS
5957 11:41:00.443910 Jitter Meter : NO K
5958 11:41:00.444012 CBT Training : PASS
5959 11:41:00.446966 Write leveling : PASS
5960 11:41:00.450187 RX DQS gating : PASS
5961 11:41:00.450304 RX DQ/DQS(RDDQC) : PASS
5962 11:41:00.453444 TX DQ/DQS : PASS
5963 11:41:00.456905 RX DATLAT : PASS
5964 11:41:00.456999 RX DQ/DQS(Engine): PASS
5965 11:41:00.459967 TX OE : NO K
5966 11:41:00.460118 All Pass.
5967 11:41:00.460186
5968 11:41:00.463201 CH 0, Rank 1
5969 11:41:00.463285 SW Impedance : PASS
5970 11:41:00.466961 DUTY Scan : NO K
5971 11:41:00.469587 ZQ Calibration : PASS
5972 11:41:00.469673 Jitter Meter : NO K
5973 11:41:00.473188 CBT Training : PASS
5974 11:41:00.476564 Write leveling : PASS
5975 11:41:00.476651 RX DQS gating : PASS
5976 11:41:00.479655 RX DQ/DQS(RDDQC) : PASS
5977 11:41:00.482863 TX DQ/DQS : PASS
5978 11:41:00.482983 RX DATLAT : PASS
5979 11:41:00.486400 RX DQ/DQS(Engine): PASS
5980 11:41:00.489600 TX OE : NO K
5981 11:41:00.489687 All Pass.
5982 11:41:00.489753
5983 11:41:00.489814 CH 1, Rank 0
5984 11:41:00.493659 SW Impedance : PASS
5985 11:41:00.496301 DUTY Scan : NO K
5986 11:41:00.496388 ZQ Calibration : PASS
5987 11:41:00.499639 Jitter Meter : NO K
5988 11:41:00.502852 CBT Training : PASS
5989 11:41:00.502937 Write leveling : PASS
5990 11:41:00.506480 RX DQS gating : PASS
5991 11:41:00.509367 RX DQ/DQS(RDDQC) : PASS
5992 11:41:00.509454 TX DQ/DQS : PASS
5993 11:41:00.512632 RX DATLAT : PASS
5994 11:41:00.515596 RX DQ/DQS(Engine): PASS
5995 11:41:00.515708 TX OE : NO K
5996 11:41:00.515805 All Pass.
5997 11:41:00.518875
5998 11:41:00.518960 CH 1, Rank 1
5999 11:41:00.522547 SW Impedance : PASS
6000 11:41:00.522631 DUTY Scan : NO K
6001 11:41:00.525655 ZQ Calibration : PASS
6002 11:41:00.529254 Jitter Meter : NO K
6003 11:41:00.529340 CBT Training : PASS
6004 11:41:00.532438 Write leveling : PASS
6005 11:41:00.532523 RX DQS gating : PASS
6006 11:41:00.535644 RX DQ/DQS(RDDQC) : PASS
6007 11:41:00.538835 TX DQ/DQS : PASS
6008 11:41:00.538922 RX DATLAT : PASS
6009 11:41:00.542357 RX DQ/DQS(Engine): PASS
6010 11:41:00.545601 TX OE : NO K
6011 11:41:00.545688 All Pass.
6012 11:41:00.545757
6013 11:41:00.548619 DramC Write-DBI off
6014 11:41:00.548704 PER_BANK_REFRESH: Hybrid Mode
6015 11:41:00.552238 TX_TRACKING: ON
6016 11:41:00.562462 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6017 11:41:00.565324 [FAST_K] Save calibration result to emmc
6018 11:41:00.568876 dramc_set_vcore_voltage set vcore to 650000
6019 11:41:00.568968 Read voltage for 400, 6
6020 11:41:00.572078 Vio18 = 0
6021 11:41:00.572181 Vcore = 650000
6022 11:41:00.572248 Vdram = 0
6023 11:41:00.575461 Vddq = 0
6024 11:41:00.575549 Vmddr = 0
6025 11:41:00.581889 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6026 11:41:00.584969 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6027 11:41:00.588618 MEM_TYPE=3, freq_sel=20
6028 11:41:00.591339 sv_algorithm_assistance_LP4_800
6029 11:41:00.594917 ============ PULL DRAM RESETB DOWN ============
6030 11:41:00.598110 ========== PULL DRAM RESETB DOWN end =========
6031 11:41:00.604723 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6032 11:41:00.607888 ===================================
6033 11:41:00.607984 LPDDR4 DRAM CONFIGURATION
6034 11:41:00.611544 ===================================
6035 11:41:00.614407 EX_ROW_EN[0] = 0x0
6036 11:41:00.617935 EX_ROW_EN[1] = 0x0
6037 11:41:00.618024 LP4Y_EN = 0x0
6038 11:41:00.621503 WORK_FSP = 0x0
6039 11:41:00.621593 WL = 0x2
6040 11:41:00.624521 RL = 0x2
6041 11:41:00.624606 BL = 0x2
6042 11:41:00.627961 RPST = 0x0
6043 11:41:00.628094 RD_PRE = 0x0
6044 11:41:00.631495 WR_PRE = 0x1
6045 11:41:00.631580 WR_PST = 0x0
6046 11:41:00.634633 DBI_WR = 0x0
6047 11:41:00.634717 DBI_RD = 0x0
6048 11:41:00.637831 OTF = 0x1
6049 11:41:00.641508 ===================================
6050 11:41:00.644589 ===================================
6051 11:41:00.644675 ANA top config
6052 11:41:00.647455 ===================================
6053 11:41:00.650644 DLL_ASYNC_EN = 0
6054 11:41:00.654560 ALL_SLAVE_EN = 1
6055 11:41:00.657385 NEW_RANK_MODE = 1
6056 11:41:00.657479 DLL_IDLE_MODE = 1
6057 11:41:00.660507 LP45_APHY_COMB_EN = 1
6058 11:41:00.664178 TX_ODT_DIS = 1
6059 11:41:00.667315 NEW_8X_MODE = 1
6060 11:41:00.670832 ===================================
6061 11:41:00.673930 ===================================
6062 11:41:00.677016 data_rate = 800
6063 11:41:00.680733 CKR = 1
6064 11:41:00.680820 DQ_P2S_RATIO = 4
6065 11:41:00.683609 ===================================
6066 11:41:00.687443 CA_P2S_RATIO = 4
6067 11:41:00.690380 DQ_CA_OPEN = 0
6068 11:41:00.693669 DQ_SEMI_OPEN = 1
6069 11:41:00.696872 CA_SEMI_OPEN = 1
6070 11:41:00.700314 CA_FULL_RATE = 0
6071 11:41:00.700400 DQ_CKDIV4_EN = 0
6072 11:41:00.703037 CA_CKDIV4_EN = 1
6073 11:41:00.706828 CA_PREDIV_EN = 0
6074 11:41:00.709642 PH8_DLY = 0
6075 11:41:00.713698 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6076 11:41:00.716704 DQ_AAMCK_DIV = 0
6077 11:41:00.716794 CA_AAMCK_DIV = 0
6078 11:41:00.719498 CA_ADMCK_DIV = 4
6079 11:41:00.723083 DQ_TRACK_CA_EN = 0
6080 11:41:00.726831 CA_PICK = 800
6081 11:41:00.729837 CA_MCKIO = 400
6082 11:41:00.733012 MCKIO_SEMI = 400
6083 11:41:00.736256 PLL_FREQ = 3016
6084 11:41:00.739686 DQ_UI_PI_RATIO = 32
6085 11:41:00.739763 CA_UI_PI_RATIO = 32
6086 11:41:00.743058 ===================================
6087 11:41:00.746614 ===================================
6088 11:41:00.749829 memory_type:LPDDR4
6089 11:41:00.752644 GP_NUM : 10
6090 11:41:00.752751 SRAM_EN : 1
6091 11:41:00.756214 MD32_EN : 0
6092 11:41:00.759437 ===================================
6093 11:41:00.762405 [ANA_INIT] >>>>>>>>>>>>>>
6094 11:41:00.766149 <<<<<< [CONFIGURE PHASE]: ANA_TX
6095 11:41:00.769406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6096 11:41:00.772255 ===================================
6097 11:41:00.772340 data_rate = 800,PCW = 0X7400
6098 11:41:00.775993 ===================================
6099 11:41:00.782560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6100 11:41:00.785290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6101 11:41:00.798810 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 11:41:00.802223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6103 11:41:00.804993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6104 11:41:00.808709 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6105 11:41:00.811924 [ANA_INIT] flow start
6106 11:41:00.814916 [ANA_INIT] PLL >>>>>>>>
6107 11:41:00.815002 [ANA_INIT] PLL <<<<<<<<
6108 11:41:00.818137 [ANA_INIT] MIDPI >>>>>>>>
6109 11:41:00.822067 [ANA_INIT] MIDPI <<<<<<<<
6110 11:41:00.822152 [ANA_INIT] DLL >>>>>>>>
6111 11:41:00.824793 [ANA_INIT] flow end
6112 11:41:00.828311 ============ LP4 DIFF to SE enter ============
6113 11:41:00.831311 ============ LP4 DIFF to SE exit ============
6114 11:41:00.834768 [ANA_INIT] <<<<<<<<<<<<<
6115 11:41:00.837953 [Flow] Enable top DCM control >>>>>
6116 11:41:00.841090 [Flow] Enable top DCM control <<<<<
6117 11:41:00.844437 Enable DLL master slave shuffle
6118 11:41:00.851326 ==============================================================
6119 11:41:00.851426 Gating Mode config
6120 11:41:00.857904 ==============================================================
6121 11:41:00.861016 Config description:
6122 11:41:00.867429 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6123 11:41:00.874474 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6124 11:41:00.880580 SELPH_MODE 0: By rank 1: By Phase
6125 11:41:00.887731 ==============================================================
6126 11:41:00.890570 GAT_TRACK_EN = 0
6127 11:41:00.890657 RX_GATING_MODE = 2
6128 11:41:00.893843 RX_GATING_TRACK_MODE = 2
6129 11:41:00.897699 SELPH_MODE = 1
6130 11:41:00.900706 PICG_EARLY_EN = 1
6131 11:41:00.904418 VALID_LAT_VALUE = 1
6132 11:41:00.910582 ==============================================================
6133 11:41:00.913862 Enter into Gating configuration >>>>
6134 11:41:00.917150 Exit from Gating configuration <<<<
6135 11:41:00.920474 Enter into DVFS_PRE_config >>>>>
6136 11:41:00.930684 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6137 11:41:00.933853 Exit from DVFS_PRE_config <<<<<
6138 11:41:00.937151 Enter into PICG configuration >>>>
6139 11:41:00.940024 Exit from PICG configuration <<<<
6140 11:41:00.943554 [RX_INPUT] configuration >>>>>
6141 11:41:00.947210 [RX_INPUT] configuration <<<<<
6142 11:41:00.950027 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6143 11:41:00.956622 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6144 11:41:00.963569 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 11:41:00.969919 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 11:41:00.973070 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 11:41:00.980078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 11:41:00.986386 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6149 11:41:00.990017 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6150 11:41:00.992642 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6151 11:41:00.995885 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6152 11:41:01.002777 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6153 11:41:01.006139 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 11:41:01.009036 ===================================
6155 11:41:01.012397 LPDDR4 DRAM CONFIGURATION
6156 11:41:01.015675 ===================================
6157 11:41:01.015759 EX_ROW_EN[0] = 0x0
6158 11:41:01.019232 EX_ROW_EN[1] = 0x0
6159 11:41:01.019315 LP4Y_EN = 0x0
6160 11:41:01.022112 WORK_FSP = 0x0
6161 11:41:01.022195 WL = 0x2
6162 11:41:01.025778 RL = 0x2
6163 11:41:01.025866 BL = 0x2
6164 11:41:01.028965 RPST = 0x0
6165 11:41:01.032296 RD_PRE = 0x0
6166 11:41:01.032379 WR_PRE = 0x1
6167 11:41:01.035676 WR_PST = 0x0
6168 11:41:01.035759 DBI_WR = 0x0
6169 11:41:01.039053 DBI_RD = 0x0
6170 11:41:01.039136 OTF = 0x1
6171 11:41:01.042499 ===================================
6172 11:41:01.045861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6173 11:41:01.052006 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6174 11:41:01.055206 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6175 11:41:01.058471 ===================================
6176 11:41:01.061533 LPDDR4 DRAM CONFIGURATION
6177 11:41:01.064850 ===================================
6178 11:41:01.064935 EX_ROW_EN[0] = 0x10
6179 11:41:01.068554 EX_ROW_EN[1] = 0x0
6180 11:41:01.068663 LP4Y_EN = 0x0
6181 11:41:01.071705 WORK_FSP = 0x0
6182 11:41:01.075092 WL = 0x2
6183 11:41:01.075176 RL = 0x2
6184 11:41:01.078006 BL = 0x2
6185 11:41:01.078089 RPST = 0x0
6186 11:41:01.081553 RD_PRE = 0x0
6187 11:41:01.081636 WR_PRE = 0x1
6188 11:41:01.084951 WR_PST = 0x0
6189 11:41:01.085033 DBI_WR = 0x0
6190 11:41:01.088007 DBI_RD = 0x0
6191 11:41:01.088114 OTF = 0x1
6192 11:41:01.091737 ===================================
6193 11:41:01.097903 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6194 11:41:01.102072 nWR fixed to 30
6195 11:41:01.105256 [ModeRegInit_LP4] CH0 RK0
6196 11:41:01.105338 [ModeRegInit_LP4] CH0 RK1
6197 11:41:01.108506 [ModeRegInit_LP4] CH1 RK0
6198 11:41:01.112163 [ModeRegInit_LP4] CH1 RK1
6199 11:41:01.112246 match AC timing 19
6200 11:41:01.118850 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6201 11:41:01.122038 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6202 11:41:01.124888 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6203 11:41:01.131916 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6204 11:41:01.135187 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6205 11:41:01.135270 ==
6206 11:41:01.138486 Dram Type= 6, Freq= 0, CH_0, rank 0
6207 11:41:01.141755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6208 11:41:01.141839 ==
6209 11:41:01.148505 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6210 11:41:01.154848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6211 11:41:01.158197 [CA 0] Center 36 (8~64) winsize 57
6212 11:41:01.161967 [CA 1] Center 36 (8~64) winsize 57
6213 11:41:01.164815 [CA 2] Center 36 (8~64) winsize 57
6214 11:41:01.167959 [CA 3] Center 36 (8~64) winsize 57
6215 11:41:01.171778 [CA 4] Center 36 (8~64) winsize 57
6216 11:41:01.174509 [CA 5] Center 36 (8~64) winsize 57
6217 11:41:01.174592
6218 11:41:01.178190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6219 11:41:01.178274
6220 11:41:01.181365 [CATrainingPosCal] consider 1 rank data
6221 11:41:01.184814 u2DelayCellTimex100 = 270/100 ps
6222 11:41:01.187912 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:41:01.191063 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:41:01.195135 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:41:01.198222 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:41:01.201154 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:41:01.204759 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 11:41:01.204842
6229 11:41:01.207477 CA PerBit enable=1, Macro0, CA PI delay=36
6230 11:41:01.211587
6231 11:41:01.211669 [CBTSetCACLKResult] CA Dly = 36
6232 11:41:01.214492 CS Dly: 1 (0~32)
6233 11:41:01.214574 ==
6234 11:41:01.217409 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 11:41:01.220971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6236 11:41:01.221054 ==
6237 11:41:01.227044 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6238 11:41:01.234032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6239 11:41:01.237013 [CA 0] Center 36 (8~64) winsize 57
6240 11:41:01.240590 [CA 1] Center 36 (8~64) winsize 57
6241 11:41:01.243740 [CA 2] Center 36 (8~64) winsize 57
6242 11:41:01.247373 [CA 3] Center 36 (8~64) winsize 57
6243 11:41:01.247457 [CA 4] Center 36 (8~64) winsize 57
6244 11:41:01.250156 [CA 5] Center 36 (8~64) winsize 57
6245 11:41:01.250239
6246 11:41:01.257020 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6247 11:41:01.257114
6248 11:41:01.260518 [CATrainingPosCal] consider 2 rank data
6249 11:41:01.263716 u2DelayCellTimex100 = 270/100 ps
6250 11:41:01.266938 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:41:01.269931 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:41:01.273356 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:41:01.276859 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:41:01.280381 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:41:01.283384 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 11:41:01.283467
6257 11:41:01.286765 CA PerBit enable=1, Macro0, CA PI delay=36
6258 11:41:01.286848
6259 11:41:01.290604 [CBTSetCACLKResult] CA Dly = 36
6260 11:41:01.293549 CS Dly: 1 (0~32)
6261 11:41:01.293633
6262 11:41:01.296717 ----->DramcWriteLeveling(PI) begin...
6263 11:41:01.296801 ==
6264 11:41:01.300401 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 11:41:01.303473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 11:41:01.303556 ==
6267 11:41:01.307213 Write leveling (Byte 0): 40 => 8
6268 11:41:01.309913 Write leveling (Byte 1): 40 => 8
6269 11:41:01.313209 DramcWriteLeveling(PI) end<-----
6270 11:41:01.313292
6271 11:41:01.313357 ==
6272 11:41:01.316319 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 11:41:01.320062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 11:41:01.320145 ==
6275 11:41:01.323326 [Gating] SW mode calibration
6276 11:41:01.330016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6277 11:41:01.336202 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6278 11:41:01.339947 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6279 11:41:01.346290 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 11:41:01.349816 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 11:41:01.352726 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 11:41:01.359979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 11:41:01.362785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 11:41:01.366146 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 11:41:01.373010 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 11:41:01.376216 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 11:41:01.379375 Total UI for P1: 0, mck2ui 16
6288 11:41:01.382406 best dqsien dly found for B0: ( 0, 14, 24)
6289 11:41:01.386039 Total UI for P1: 0, mck2ui 16
6290 11:41:01.389024 best dqsien dly found for B1: ( 0, 14, 24)
6291 11:41:01.392186 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6292 11:41:01.396461 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6293 11:41:01.396544
6294 11:41:01.399391 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6295 11:41:01.402555 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 11:41:01.405684 [Gating] SW calibration Done
6297 11:41:01.405766 ==
6298 11:41:01.408695 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 11:41:01.412221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 11:41:01.415760 ==
6301 11:41:01.415842 RX Vref Scan: 0
6302 11:41:01.415907
6303 11:41:01.418494 RX Vref 0 -> 0, step: 1
6304 11:41:01.418576
6305 11:41:01.421789 RX Delay -410 -> 252, step: 16
6306 11:41:01.425225 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6307 11:41:01.428911 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6308 11:41:01.431650 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6309 11:41:01.438853 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6310 11:41:01.442133 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6311 11:41:01.445629 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6312 11:41:01.451897 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6313 11:41:01.455126 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6314 11:41:01.458216 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6315 11:41:01.461398 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6316 11:41:01.469149 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6317 11:41:01.471233 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6318 11:41:01.474862 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6319 11:41:01.478176 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6320 11:41:01.484662 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6321 11:41:01.487992 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6322 11:41:01.488120 ==
6323 11:41:01.491388 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 11:41:01.494670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 11:41:01.494755 ==
6326 11:41:01.497939 DQS Delay:
6327 11:41:01.498020 DQS0 = 35, DQS1 = 51
6328 11:41:01.500834 DQM Delay:
6329 11:41:01.500915 DQM0 = 4, DQM1 = 10
6330 11:41:01.500979 DQ Delay:
6331 11:41:01.504790 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6332 11:41:01.508050 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6333 11:41:01.511039 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6334 11:41:01.514194 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6335 11:41:01.514276
6336 11:41:01.514340
6337 11:41:01.514399 ==
6338 11:41:01.517791 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 11:41:01.523906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 11:41:01.523988 ==
6341 11:41:01.524091
6342 11:41:01.524152
6343 11:41:01.524210 TX Vref Scan disable
6344 11:41:01.527571 == TX Byte 0 ==
6345 11:41:01.530680 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 11:41:01.534014 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 11:41:01.537534 == TX Byte 1 ==
6348 11:41:01.540524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 11:41:01.543614 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 11:41:01.543695 ==
6351 11:41:01.547099 Dram Type= 6, Freq= 0, CH_0, rank 0
6352 11:41:01.553731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6353 11:41:01.553818 ==
6354 11:41:01.553883
6355 11:41:01.553941
6356 11:41:01.553998 TX Vref Scan disable
6357 11:41:01.557374 == TX Byte 0 ==
6358 11:41:01.560744 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 11:41:01.563546 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 11:41:01.566866 == TX Byte 1 ==
6361 11:41:01.571112 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 11:41:01.573848 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 11:41:01.576899
6364 11:41:01.576980 [DATLAT]
6365 11:41:01.577044 Freq=400, CH0 RK0
6366 11:41:01.577105
6367 11:41:01.580192 DATLAT Default: 0xf
6368 11:41:01.580273 0, 0xFFFF, sum = 0
6369 11:41:01.583179 1, 0xFFFF, sum = 0
6370 11:41:01.583262 2, 0xFFFF, sum = 0
6371 11:41:01.586775 3, 0xFFFF, sum = 0
6372 11:41:01.589737 4, 0xFFFF, sum = 0
6373 11:41:01.589820 5, 0xFFFF, sum = 0
6374 11:41:01.593136 6, 0xFFFF, sum = 0
6375 11:41:01.593218 7, 0xFFFF, sum = 0
6376 11:41:01.596309 8, 0xFFFF, sum = 0
6377 11:41:01.596392 9, 0xFFFF, sum = 0
6378 11:41:01.600134 10, 0xFFFF, sum = 0
6379 11:41:01.600217 11, 0xFFFF, sum = 0
6380 11:41:01.602783 12, 0xFFFF, sum = 0
6381 11:41:01.602892 13, 0x0, sum = 1
6382 11:41:01.606566 14, 0x0, sum = 2
6383 11:41:01.606649 15, 0x0, sum = 3
6384 11:41:01.610401 16, 0x0, sum = 4
6385 11:41:01.610484 best_step = 14
6386 11:41:01.610547
6387 11:41:01.610607 ==
6388 11:41:01.612763 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 11:41:01.616439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 11:41:01.619923 ==
6391 11:41:01.620004 RX Vref Scan: 1
6392 11:41:01.620078
6393 11:41:01.622848 RX Vref 0 -> 0, step: 1
6394 11:41:01.622929
6395 11:41:01.626652 RX Delay -343 -> 252, step: 8
6396 11:41:01.626732
6397 11:41:01.629797 Set Vref, RX VrefLevel [Byte0]: 51
6398 11:41:01.632515 [Byte1]: 59
6399 11:41:01.632596
6400 11:41:01.635723 Final RX Vref Byte 0 = 51 to rank0
6401 11:41:01.640040 Final RX Vref Byte 1 = 59 to rank0
6402 11:41:01.642460 Final RX Vref Byte 0 = 51 to rank1
6403 11:41:01.645849 Final RX Vref Byte 1 = 59 to rank1==
6404 11:41:01.649020 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 11:41:01.652864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 11:41:01.652949 ==
6407 11:41:01.655713 DQS Delay:
6408 11:41:01.655822 DQS0 = 40, DQS1 = 60
6409 11:41:01.659905 DQM Delay:
6410 11:41:01.659988 DQM0 = 6, DQM1 = 16
6411 11:41:01.662616 DQ Delay:
6412 11:41:01.662700 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6413 11:41:01.665492 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6414 11:41:01.669177 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6415 11:41:01.672615 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6416 11:41:01.672698
6417 11:41:01.672769
6418 11:41:01.682482 [DQSOSCAuto] RK0, (LSB)MR18= 0x9184, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6419 11:41:01.685373 CH0 RK0: MR19=C0C, MR18=9184
6420 11:41:01.689065 CH0_RK0: MR19=0xC0C, MR18=0x9184, DQSOSC=391, MR23=63, INC=386, DEC=257
6421 11:41:01.691822 ==
6422 11:41:01.695726 Dram Type= 6, Freq= 0, CH_0, rank 1
6423 11:41:01.698989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 11:41:01.699074 ==
6425 11:41:01.701728 [Gating] SW mode calibration
6426 11:41:01.708258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6427 11:41:01.711819 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6428 11:41:01.718398 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6429 11:41:01.721803 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 11:41:01.725265 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 11:41:01.731829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 11:41:01.734960 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 11:41:01.738006 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 11:41:01.744961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 11:41:01.748633 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 11:41:01.751606 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 11:41:01.754716 Total UI for P1: 0, mck2ui 16
6438 11:41:01.758440 best dqsien dly found for B0: ( 0, 14, 24)
6439 11:41:01.761221 Total UI for P1: 0, mck2ui 16
6440 11:41:01.764697 best dqsien dly found for B1: ( 0, 14, 24)
6441 11:41:01.767839 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6442 11:41:01.774594 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6443 11:41:01.774679
6444 11:41:01.778299 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6445 11:41:01.780632 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 11:41:01.784322 [Gating] SW calibration Done
6447 11:41:01.784407 ==
6448 11:41:01.787822 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 11:41:01.791081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 11:41:01.791166 ==
6451 11:41:01.794046 RX Vref Scan: 0
6452 11:41:01.794128
6453 11:41:01.794195 RX Vref 0 -> 0, step: 1
6454 11:41:01.794256
6455 11:41:01.797483 RX Delay -410 -> 252, step: 16
6456 11:41:01.803802 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6457 11:41:01.807079 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6458 11:41:01.810770 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6459 11:41:01.813941 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6460 11:41:01.820380 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6461 11:41:01.823851 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6462 11:41:01.827366 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6463 11:41:01.830014 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6464 11:41:01.836703 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6465 11:41:01.839918 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6466 11:41:01.843565 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6467 11:41:01.846973 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6468 11:41:01.853599 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6469 11:41:01.856723 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6470 11:41:01.859929 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6471 11:41:01.866229 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6472 11:41:01.866314 ==
6473 11:41:01.870656 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 11:41:01.873358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 11:41:01.873442 ==
6476 11:41:01.873509 DQS Delay:
6477 11:41:01.876167 DQS0 = 35, DQS1 = 51
6478 11:41:01.876250 DQM Delay:
6479 11:41:01.879954 DQM0 = 8, DQM1 = 9
6480 11:41:01.880063 DQ Delay:
6481 11:41:01.882629 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6482 11:41:01.886207 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6483 11:41:01.889899 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6484 11:41:01.893126 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6485 11:41:01.893210
6486 11:41:01.893275
6487 11:41:01.893336 ==
6488 11:41:01.896870 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 11:41:01.899351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 11:41:01.899450 ==
6491 11:41:01.899538
6492 11:41:01.899601
6493 11:41:01.902700 TX Vref Scan disable
6494 11:41:01.902783 == TX Byte 0 ==
6495 11:41:01.909373 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6496 11:41:01.912359 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6497 11:41:01.912444 == TX Byte 1 ==
6498 11:41:01.919130 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6499 11:41:01.922564 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6500 11:41:01.922647 ==
6501 11:41:01.925763 Dram Type= 6, Freq= 0, CH_0, rank 1
6502 11:41:01.928893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6503 11:41:01.928976 ==
6504 11:41:01.929042
6505 11:41:01.929101
6506 11:41:01.932731 TX Vref Scan disable
6507 11:41:01.936057 == TX Byte 0 ==
6508 11:41:01.938730 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6509 11:41:01.942240 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6510 11:41:01.945525 == TX Byte 1 ==
6511 11:41:01.948665 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6512 11:41:01.951796 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6513 11:41:01.951880
6514 11:41:01.951945 [DATLAT]
6515 11:41:01.955017 Freq=400, CH0 RK1
6516 11:41:01.955100
6517 11:41:01.955165 DATLAT Default: 0xe
6518 11:41:01.958817 0, 0xFFFF, sum = 0
6519 11:41:01.961906 1, 0xFFFF, sum = 0
6520 11:41:01.961992 2, 0xFFFF, sum = 0
6521 11:41:01.965392 3, 0xFFFF, sum = 0
6522 11:41:01.965476 4, 0xFFFF, sum = 0
6523 11:41:01.968527 5, 0xFFFF, sum = 0
6524 11:41:01.968611 6, 0xFFFF, sum = 0
6525 11:41:01.971868 7, 0xFFFF, sum = 0
6526 11:41:01.971952 8, 0xFFFF, sum = 0
6527 11:41:01.975142 9, 0xFFFF, sum = 0
6528 11:41:01.975226 10, 0xFFFF, sum = 0
6529 11:41:01.978316 11, 0xFFFF, sum = 0
6530 11:41:01.978401 12, 0xFFFF, sum = 0
6531 11:41:01.981600 13, 0x0, sum = 1
6532 11:41:01.981684 14, 0x0, sum = 2
6533 11:41:01.984944 15, 0x0, sum = 3
6534 11:41:01.985028 16, 0x0, sum = 4
6535 11:41:01.988305 best_step = 14
6536 11:41:01.988387
6537 11:41:01.988453 ==
6538 11:41:01.991103 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 11:41:01.994501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 11:41:01.994585 ==
6541 11:41:01.998488 RX Vref Scan: 0
6542 11:41:01.998571
6543 11:41:01.998637 RX Vref 0 -> 0, step: 1
6544 11:41:01.998699
6545 11:41:02.001877 RX Delay -343 -> 252, step: 8
6546 11:41:02.009264 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6547 11:41:02.012325 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6548 11:41:02.015472 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6549 11:41:02.021835 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6550 11:41:02.025588 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6551 11:41:02.029105 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6552 11:41:02.031836 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6553 11:41:02.038637 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6554 11:41:02.042032 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6555 11:41:02.045339 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6556 11:41:02.048719 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6557 11:41:02.054915 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6558 11:41:02.058331 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6559 11:41:02.061804 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6560 11:41:02.065765 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6561 11:41:02.071358 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6562 11:41:02.071441 ==
6563 11:41:02.074973 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 11:41:02.078134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 11:41:02.078218 ==
6566 11:41:02.081749 DQS Delay:
6567 11:41:02.081832 DQS0 = 44, DQS1 = 60
6568 11:41:02.081897 DQM Delay:
6569 11:41:02.084660 DQM0 = 9, DQM1 = 16
6570 11:41:02.084744 DQ Delay:
6571 11:41:02.088067 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6572 11:41:02.091105 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6573 11:41:02.094664 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6574 11:41:02.097804 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6575 11:41:02.097888
6576 11:41:02.097952
6577 11:41:02.107460 [DQSOSCAuto] RK1, (LSB)MR18= 0x8882, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6578 11:41:02.107549 CH0 RK1: MR19=C0C, MR18=8882
6579 11:41:02.114091 CH0_RK1: MR19=0xC0C, MR18=0x8882, DQSOSC=392, MR23=63, INC=384, DEC=256
6580 11:41:02.117407 [RxdqsGatingPostProcess] freq 400
6581 11:41:02.124416 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6582 11:41:02.127023 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 11:41:02.130758 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 11:41:02.133830 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 11:41:02.137147 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 11:41:02.140761 best DQS0 dly(2T, 0.5T) = (0, 10)
6587 11:41:02.144228 best DQS1 dly(2T, 0.5T) = (0, 10)
6588 11:41:02.147204 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6589 11:41:02.150771 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6590 11:41:02.150854 Pre-setting of DQS Precalculation
6591 11:41:02.157099 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6592 11:41:02.157189 ==
6593 11:41:02.160400 Dram Type= 6, Freq= 0, CH_1, rank 0
6594 11:41:02.163669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 11:41:02.163757 ==
6596 11:41:02.170235 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6597 11:41:02.176889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6598 11:41:02.180486 [CA 0] Center 36 (8~64) winsize 57
6599 11:41:02.183950 [CA 1] Center 36 (8~64) winsize 57
6600 11:41:02.186850 [CA 2] Center 36 (8~64) winsize 57
6601 11:41:02.189947 [CA 3] Center 36 (8~64) winsize 57
6602 11:41:02.193033 [CA 4] Center 36 (8~64) winsize 57
6603 11:41:02.193121 [CA 5] Center 36 (8~64) winsize 57
6604 11:41:02.196911
6605 11:41:02.199964 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6606 11:41:02.200054
6607 11:41:02.202901 [CATrainingPosCal] consider 1 rank data
6608 11:41:02.206759 u2DelayCellTimex100 = 270/100 ps
6609 11:41:02.210363 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:41:02.213044 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:41:02.216324 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:41:02.219914 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:41:02.223303 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:41:02.226142 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 11:41:02.226228
6616 11:41:02.229313 CA PerBit enable=1, Macro0, CA PI delay=36
6617 11:41:02.232816
6618 11:41:02.232924 [CBTSetCACLKResult] CA Dly = 36
6619 11:41:02.236073 CS Dly: 1 (0~32)
6620 11:41:02.236159 ==
6621 11:41:02.239454 Dram Type= 6, Freq= 0, CH_1, rank 1
6622 11:41:02.242758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 11:41:02.242844 ==
6624 11:41:02.248956 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6625 11:41:02.255547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6626 11:41:02.258878 [CA 0] Center 36 (8~64) winsize 57
6627 11:41:02.261984 [CA 1] Center 36 (8~64) winsize 57
6628 11:41:02.265729 [CA 2] Center 36 (8~64) winsize 57
6629 11:41:02.269178 [CA 3] Center 36 (8~64) winsize 57
6630 11:41:02.269260 [CA 4] Center 36 (8~64) winsize 57
6631 11:41:02.271899 [CA 5] Center 36 (8~64) winsize 57
6632 11:41:02.272007
6633 11:41:02.278950 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6634 11:41:02.279033
6635 11:41:02.282112 [CATrainingPosCal] consider 2 rank data
6636 11:41:02.285407 u2DelayCellTimex100 = 270/100 ps
6637 11:41:02.288945 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:41:02.291701 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:41:02.295282 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:41:02.298555 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:41:02.301816 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:41:02.305418 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 11:41:02.305502
6644 11:41:02.308384 CA PerBit enable=1, Macro0, CA PI delay=36
6645 11:41:02.308466
6646 11:41:02.311735 [CBTSetCACLKResult] CA Dly = 36
6647 11:41:02.314946 CS Dly: 1 (0~32)
6648 11:41:02.315029
6649 11:41:02.318391 ----->DramcWriteLeveling(PI) begin...
6650 11:41:02.318476 ==
6651 11:41:02.321770 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 11:41:02.324741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 11:41:02.324826 ==
6654 11:41:02.328060 Write leveling (Byte 0): 40 => 8
6655 11:41:02.331667 Write leveling (Byte 1): 40 => 8
6656 11:41:02.335134 DramcWriteLeveling(PI) end<-----
6657 11:41:02.335218
6658 11:41:02.335283 ==
6659 11:41:02.337929 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 11:41:02.341283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 11:41:02.341367 ==
6662 11:41:02.344468 [Gating] SW mode calibration
6663 11:41:02.351413 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6664 11:41:02.357962 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6665 11:41:02.361602 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6666 11:41:02.368307 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 11:41:02.371308 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 11:41:02.374745 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 11:41:02.381210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 11:41:02.384444 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 11:41:02.387407 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 11:41:02.394251 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 11:41:02.397687 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 11:41:02.400366 Total UI for P1: 0, mck2ui 16
6675 11:41:02.404100 best dqsien dly found for B0: ( 0, 14, 24)
6676 11:41:02.407367 Total UI for P1: 0, mck2ui 16
6677 11:41:02.410376 best dqsien dly found for B1: ( 0, 14, 24)
6678 11:41:02.414256 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6679 11:41:02.417322 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6680 11:41:02.417406
6681 11:41:02.420458 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6682 11:41:02.423701 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 11:41:02.427338 [Gating] SW calibration Done
6684 11:41:02.427421 ==
6685 11:41:02.430203 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 11:41:02.436435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 11:41:02.436522 ==
6688 11:41:02.436588 RX Vref Scan: 0
6689 11:41:02.436649
6690 11:41:02.439834 RX Vref 0 -> 0, step: 1
6691 11:41:02.439917
6692 11:41:02.443247 RX Delay -410 -> 252, step: 16
6693 11:41:02.447091 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6694 11:41:02.449606 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6695 11:41:02.457132 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6696 11:41:02.460616 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6697 11:41:02.463287 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6698 11:41:02.466745 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6699 11:41:02.472918 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6700 11:41:02.476523 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6701 11:41:02.479654 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6702 11:41:02.483229 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6703 11:41:02.489305 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6704 11:41:02.492715 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6705 11:41:02.496319 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6706 11:41:02.502819 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6707 11:41:02.505898 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6708 11:41:02.508954 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6709 11:41:02.509045 ==
6710 11:41:02.512273 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 11:41:02.515789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 11:41:02.519181 ==
6713 11:41:02.519313 DQS Delay:
6714 11:41:02.519405 DQS0 = 35, DQS1 = 51
6715 11:41:02.522353 DQM Delay:
6716 11:41:02.522471 DQM0 = 6, DQM1 = 13
6717 11:41:02.525731 DQ Delay:
6718 11:41:02.525804 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6719 11:41:02.528810 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6720 11:41:02.531819 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6721 11:41:02.535155 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6722 11:41:02.535231
6723 11:41:02.535294
6724 11:41:02.538623 ==
6725 11:41:02.541773 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 11:41:02.544833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 11:41:02.544911 ==
6728 11:41:02.544975
6729 11:41:02.545034
6730 11:41:02.548339 TX Vref Scan disable
6731 11:41:02.548409 == TX Byte 0 ==
6732 11:41:02.551909 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 11:41:02.558034 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 11:41:02.558165 == TX Byte 1 ==
6735 11:41:02.561483 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 11:41:02.568231 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 11:41:02.568318 ==
6738 11:41:02.571407 Dram Type= 6, Freq= 0, CH_1, rank 0
6739 11:41:02.574659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6740 11:41:02.574743 ==
6741 11:41:02.574809
6742 11:41:02.574871
6743 11:41:02.578258 TX Vref Scan disable
6744 11:41:02.578341 == TX Byte 0 ==
6745 11:41:02.581077 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 11:41:02.587988 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 11:41:02.588126 == TX Byte 1 ==
6748 11:41:02.591037 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 11:41:02.597715 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 11:41:02.597799
6751 11:41:02.597866 [DATLAT]
6752 11:41:02.601160 Freq=400, CH1 RK0
6753 11:41:02.601244
6754 11:41:02.601311 DATLAT Default: 0xf
6755 11:41:02.604427 0, 0xFFFF, sum = 0
6756 11:41:02.604511 1, 0xFFFF, sum = 0
6757 11:41:02.607517 2, 0xFFFF, sum = 0
6758 11:41:02.607605 3, 0xFFFF, sum = 0
6759 11:41:02.611127 4, 0xFFFF, sum = 0
6760 11:41:02.611211 5, 0xFFFF, sum = 0
6761 11:41:02.614193 6, 0xFFFF, sum = 0
6762 11:41:02.614279 7, 0xFFFF, sum = 0
6763 11:41:02.617740 8, 0xFFFF, sum = 0
6764 11:41:02.617825 9, 0xFFFF, sum = 0
6765 11:41:02.621279 10, 0xFFFF, sum = 0
6766 11:41:02.621363 11, 0xFFFF, sum = 0
6767 11:41:02.624209 12, 0xFFFF, sum = 0
6768 11:41:02.627432 13, 0x0, sum = 1
6769 11:41:02.627517 14, 0x0, sum = 2
6770 11:41:02.627584 15, 0x0, sum = 3
6771 11:41:02.630689 16, 0x0, sum = 4
6772 11:41:02.630773 best_step = 14
6773 11:41:02.630838
6774 11:41:02.630899 ==
6775 11:41:02.633969 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 11:41:02.640561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 11:41:02.640646 ==
6778 11:41:02.640713 RX Vref Scan: 1
6779 11:41:02.640799
6780 11:41:02.644268 RX Vref 0 -> 0, step: 1
6781 11:41:02.644351
6782 11:41:02.646954 RX Delay -343 -> 252, step: 8
6783 11:41:02.647036
6784 11:41:02.650862 Set Vref, RX VrefLevel [Byte0]: 50
6785 11:41:02.653475 [Byte1]: 52
6786 11:41:02.657090
6787 11:41:02.657213 Final RX Vref Byte 0 = 50 to rank0
6788 11:41:02.660262 Final RX Vref Byte 1 = 52 to rank0
6789 11:41:02.663634 Final RX Vref Byte 0 = 50 to rank1
6790 11:41:02.667269 Final RX Vref Byte 1 = 52 to rank1==
6791 11:41:02.671068 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 11:41:02.677362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 11:41:02.677449 ==
6794 11:41:02.677517 DQS Delay:
6795 11:41:02.680167 DQS0 = 44, DQS1 = 52
6796 11:41:02.680250 DQM Delay:
6797 11:41:02.680315 DQM0 = 10, DQM1 = 10
6798 11:41:02.683939 DQ Delay:
6799 11:41:02.686655 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6800 11:41:02.690761 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6801 11:41:02.690845 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6802 11:41:02.693239 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6803 11:41:02.696967
6804 11:41:02.697051
6805 11:41:02.703101 [DQSOSCAuto] RK0, (LSB)MR18= 0x6087, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6806 11:41:02.706575 CH1 RK0: MR19=C0C, MR18=6087
6807 11:41:02.713046 CH1_RK0: MR19=0xC0C, MR18=0x6087, DQSOSC=392, MR23=63, INC=384, DEC=256
6808 11:41:02.713131 ==
6809 11:41:02.716267 Dram Type= 6, Freq= 0, CH_1, rank 1
6810 11:41:02.719608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 11:41:02.719693 ==
6812 11:41:02.723459 [Gating] SW mode calibration
6813 11:41:02.729414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6814 11:41:02.735981 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6815 11:41:02.739384 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6816 11:41:02.742751 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 11:41:02.749181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 11:41:02.752288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 11:41:02.755580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 11:41:02.762163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 11:41:02.765456 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 11:41:02.769091 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 11:41:02.775485 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 11:41:02.779099 Total UI for P1: 0, mck2ui 16
6825 11:41:02.782416 best dqsien dly found for B0: ( 0, 14, 24)
6826 11:41:02.785433 Total UI for P1: 0, mck2ui 16
6827 11:41:02.789088 best dqsien dly found for B1: ( 0, 14, 24)
6828 11:41:02.792317 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6829 11:41:02.795734 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6830 11:41:02.795819
6831 11:41:02.798993 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6832 11:41:02.801814 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 11:41:02.804977 [Gating] SW calibration Done
6834 11:41:02.805061 ==
6835 11:41:02.808460 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 11:41:02.811617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 11:41:02.811701 ==
6838 11:41:02.815339 RX Vref Scan: 0
6839 11:41:02.815422
6840 11:41:02.818309 RX Vref 0 -> 0, step: 1
6841 11:41:02.818392
6842 11:41:02.821533 RX Delay -410 -> 252, step: 16
6843 11:41:02.824838 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6844 11:41:02.828299 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6845 11:41:02.831613 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6846 11:41:02.837866 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6847 11:41:02.841238 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6848 11:41:02.844466 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6849 11:41:02.848622 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6850 11:41:02.854628 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6851 11:41:02.857904 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6852 11:41:02.860917 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6853 11:41:02.864119 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6854 11:41:02.870642 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6855 11:41:02.873910 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6856 11:41:02.877276 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6857 11:41:02.884136 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6858 11:41:02.887407 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6859 11:41:02.887491 ==
6860 11:41:02.890692 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 11:41:02.894221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 11:41:02.894310 ==
6863 11:41:02.897084 DQS Delay:
6864 11:41:02.897162 DQS0 = 43, DQS1 = 51
6865 11:41:02.897244 DQM Delay:
6866 11:41:02.900796 DQM0 = 9, DQM1 = 14
6867 11:41:02.900877 DQ Delay:
6868 11:41:02.904045 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6869 11:41:02.907630 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6870 11:41:02.910300 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6871 11:41:02.914123 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6872 11:41:02.914213
6873 11:41:02.914295
6874 11:41:02.914376 ==
6875 11:41:02.916720 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 11:41:02.920155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 11:41:02.923864 ==
6878 11:41:02.923937
6879 11:41:02.924041
6880 11:41:02.924151 TX Vref Scan disable
6881 11:41:02.926751 == TX Byte 0 ==
6882 11:41:02.930703 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6883 11:41:02.933484 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6884 11:41:02.936839 == TX Byte 1 ==
6885 11:41:02.940126 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6886 11:41:02.943491 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6887 11:41:02.943575 ==
6888 11:41:02.946977 Dram Type= 6, Freq= 0, CH_1, rank 1
6889 11:41:02.953057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6890 11:41:02.953202 ==
6891 11:41:02.953275
6892 11:41:02.953337
6893 11:41:02.953398 TX Vref Scan disable
6894 11:41:02.956911 == TX Byte 0 ==
6895 11:41:02.959845 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6896 11:41:02.963410 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6897 11:41:02.966476 == TX Byte 1 ==
6898 11:41:02.969749 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6899 11:41:02.972869 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6900 11:41:02.972970
6901 11:41:02.976359 [DATLAT]
6902 11:41:02.976445 Freq=400, CH1 RK1
6903 11:41:02.976512
6904 11:41:02.979771 DATLAT Default: 0xe
6905 11:41:02.979854 0, 0xFFFF, sum = 0
6906 11:41:02.982970 1, 0xFFFF, sum = 0
6907 11:41:02.983056 2, 0xFFFF, sum = 0
6908 11:41:02.986344 3, 0xFFFF, sum = 0
6909 11:41:02.986455 4, 0xFFFF, sum = 0
6910 11:41:02.989328 5, 0xFFFF, sum = 0
6911 11:41:02.989412 6, 0xFFFF, sum = 0
6912 11:41:02.993111 7, 0xFFFF, sum = 0
6913 11:41:02.993195 8, 0xFFFF, sum = 0
6914 11:41:02.996256 9, 0xFFFF, sum = 0
6915 11:41:02.999232 10, 0xFFFF, sum = 0
6916 11:41:02.999316 11, 0xFFFF, sum = 0
6917 11:41:03.002820 12, 0xFFFF, sum = 0
6918 11:41:03.002904 13, 0x0, sum = 1
6919 11:41:03.006084 14, 0x0, sum = 2
6920 11:41:03.006168 15, 0x0, sum = 3
6921 11:41:03.009778 16, 0x0, sum = 4
6922 11:41:03.009861 best_step = 14
6923 11:41:03.009926
6924 11:41:03.009986 ==
6925 11:41:03.012319 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 11:41:03.016212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 11:41:03.016297 ==
6928 11:41:03.019101 RX Vref Scan: 0
6929 11:41:03.019184
6930 11:41:03.022696 RX Vref 0 -> 0, step: 1
6931 11:41:03.022778
6932 11:41:03.022844 RX Delay -343 -> 252, step: 8
6933 11:41:03.031443 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6934 11:41:03.034223 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6935 11:41:03.037478 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6936 11:41:03.044571 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6937 11:41:03.047896 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6938 11:41:03.050661 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6939 11:41:03.053913 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6940 11:41:03.061349 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6941 11:41:03.064476 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6942 11:41:03.067326 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6943 11:41:03.070474 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6944 11:41:03.077146 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6945 11:41:03.080538 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6946 11:41:03.084027 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6947 11:41:03.087510 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6948 11:41:03.093644 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6949 11:41:03.093730 ==
6950 11:41:03.096943 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 11:41:03.100524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 11:41:03.100608 ==
6953 11:41:03.103456 DQS Delay:
6954 11:41:03.103539 DQS0 = 48, DQS1 = 52
6955 11:41:03.103605 DQM Delay:
6956 11:41:03.106706 DQM0 = 11, DQM1 = 11
6957 11:41:03.106790 DQ Delay:
6958 11:41:03.109953 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6959 11:41:03.113373 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6960 11:41:03.117093 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6961 11:41:03.119891 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6962 11:41:03.119975
6963 11:41:03.120050
6964 11:41:03.130152 [DQSOSCAuto] RK1, (LSB)MR18= 0x71a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6965 11:41:03.130243 CH1 RK1: MR19=C0C, MR18=71A7
6966 11:41:03.136296 CH1_RK1: MR19=0xC0C, MR18=0x71A7, DQSOSC=389, MR23=63, INC=390, DEC=260
6967 11:41:03.139517 [RxdqsGatingPostProcess] freq 400
6968 11:41:03.146442 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6969 11:41:03.149450 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 11:41:03.153400 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 11:41:03.156176 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 11:41:03.159194 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 11:41:03.162470 best DQS0 dly(2T, 0.5T) = (0, 10)
6974 11:41:03.166014 best DQS1 dly(2T, 0.5T) = (0, 10)
6975 11:41:03.169234 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6976 11:41:03.172407 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6977 11:41:03.176410 Pre-setting of DQS Precalculation
6978 11:41:03.179501 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6979 11:41:03.185782 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6980 11:41:03.192382 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6981 11:41:03.192476
6982 11:41:03.192544
6983 11:41:03.195619 [Calibration Summary] 800 Mbps
6984 11:41:03.198871 CH 0, Rank 0
6985 11:41:03.198954 SW Impedance : PASS
6986 11:41:03.202219 DUTY Scan : NO K
6987 11:41:03.205975 ZQ Calibration : PASS
6988 11:41:03.206059 Jitter Meter : NO K
6989 11:41:03.208970 CBT Training : PASS
6990 11:41:03.212289 Write leveling : PASS
6991 11:41:03.212374 RX DQS gating : PASS
6992 11:41:03.215473 RX DQ/DQS(RDDQC) : PASS
6993 11:41:03.218720 TX DQ/DQS : PASS
6994 11:41:03.218804 RX DATLAT : PASS
6995 11:41:03.222076 RX DQ/DQS(Engine): PASS
6996 11:41:03.225538 TX OE : NO K
6997 11:41:03.225626 All Pass.
6998 11:41:03.225692
6999 11:41:03.225753 CH 0, Rank 1
7000 11:41:03.228151 SW Impedance : PASS
7001 11:41:03.231397 DUTY Scan : NO K
7002 11:41:03.231481 ZQ Calibration : PASS
7003 11:41:03.235188 Jitter Meter : NO K
7004 11:41:03.238188 CBT Training : PASS
7005 11:41:03.238270 Write leveling : NO K
7006 11:41:03.241678 RX DQS gating : PASS
7007 11:41:03.245136 RX DQ/DQS(RDDQC) : PASS
7008 11:41:03.245218 TX DQ/DQS : PASS
7009 11:41:03.248185 RX DATLAT : PASS
7010 11:41:03.251564 RX DQ/DQS(Engine): PASS
7011 11:41:03.251668 TX OE : NO K
7012 11:41:03.251753 All Pass.
7013 11:41:03.254851
7014 11:41:03.254940 CH 1, Rank 0
7015 11:41:03.257989 SW Impedance : PASS
7016 11:41:03.258074 DUTY Scan : NO K
7017 11:41:03.261675 ZQ Calibration : PASS
7018 11:41:03.264673 Jitter Meter : NO K
7019 11:41:03.264757 CBT Training : PASS
7020 11:41:03.267758 Write leveling : PASS
7021 11:41:03.271024 RX DQS gating : PASS
7022 11:41:03.271133 RX DQ/DQS(RDDQC) : PASS
7023 11:41:03.274384 TX DQ/DQS : PASS
7024 11:41:03.274493 RX DATLAT : PASS
7025 11:41:03.277718 RX DQ/DQS(Engine): PASS
7026 11:41:03.280759 TX OE : NO K
7027 11:41:03.280843 All Pass.
7028 11:41:03.280909
7029 11:41:03.283835 CH 1, Rank 1
7030 11:41:03.283944 SW Impedance : PASS
7031 11:41:03.287840 DUTY Scan : NO K
7032 11:41:03.287948 ZQ Calibration : PASS
7033 11:41:03.290640 Jitter Meter : NO K
7034 11:41:03.293806 CBT Training : PASS
7035 11:41:03.293889 Write leveling : NO K
7036 11:41:03.297255 RX DQS gating : PASS
7037 11:41:03.301022 RX DQ/DQS(RDDQC) : PASS
7038 11:41:03.301104 TX DQ/DQS : PASS
7039 11:41:03.303736 RX DATLAT : PASS
7040 11:41:03.307002 RX DQ/DQS(Engine): PASS
7041 11:41:03.307085 TX OE : NO K
7042 11:41:03.310884 All Pass.
7043 11:41:03.310968
7044 11:41:03.311033 DramC Write-DBI off
7045 11:41:03.314250 PER_BANK_REFRESH: Hybrid Mode
7046 11:41:03.317073 TX_TRACKING: ON
7047 11:41:03.323497 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7048 11:41:03.327316 [FAST_K] Save calibration result to emmc
7049 11:41:03.329952 dramc_set_vcore_voltage set vcore to 725000
7050 11:41:03.333195 Read voltage for 1600, 0
7051 11:41:03.333278 Vio18 = 0
7052 11:41:03.336713 Vcore = 725000
7053 11:41:03.336795 Vdram = 0
7054 11:41:03.336861 Vddq = 0
7055 11:41:03.340193 Vmddr = 0
7056 11:41:03.343246 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7057 11:41:03.349888 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7058 11:41:03.353280 MEM_TYPE=3, freq_sel=13
7059 11:41:03.353363 sv_algorithm_assistance_LP4_3733
7060 11:41:03.360353 ============ PULL DRAM RESETB DOWN ============
7061 11:41:03.363281 ========== PULL DRAM RESETB DOWN end =========
7062 11:41:03.366772 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7063 11:41:03.370006 ===================================
7064 11:41:03.372774 LPDDR4 DRAM CONFIGURATION
7065 11:41:03.376196 ===================================
7066 11:41:03.379760 EX_ROW_EN[0] = 0x0
7067 11:41:03.379870 EX_ROW_EN[1] = 0x0
7068 11:41:03.382714 LP4Y_EN = 0x0
7069 11:41:03.382799 WORK_FSP = 0x1
7070 11:41:03.386762 WL = 0x5
7071 11:41:03.386882 RL = 0x5
7072 11:41:03.389817 BL = 0x2
7073 11:41:03.389900 RPST = 0x0
7074 11:41:03.392665 RD_PRE = 0x0
7075 11:41:03.392747 WR_PRE = 0x1
7076 11:41:03.396532 WR_PST = 0x1
7077 11:41:03.396614 DBI_WR = 0x0
7078 11:41:03.399293 DBI_RD = 0x0
7079 11:41:03.402683 OTF = 0x1
7080 11:41:03.406461 ===================================
7081 11:41:03.409262 ===================================
7082 11:41:03.409344 ANA top config
7083 11:41:03.412625 ===================================
7084 11:41:03.415856 DLL_ASYNC_EN = 0
7085 11:41:03.415964 ALL_SLAVE_EN = 0
7086 11:41:03.418964 NEW_RANK_MODE = 1
7087 11:41:03.422587 DLL_IDLE_MODE = 1
7088 11:41:03.425846 LP45_APHY_COMB_EN = 1
7089 11:41:03.429091 TX_ODT_DIS = 0
7090 11:41:03.429173 NEW_8X_MODE = 1
7091 11:41:03.432598 ===================================
7092 11:41:03.435633 ===================================
7093 11:41:03.438738 data_rate = 3200
7094 11:41:03.442808 CKR = 1
7095 11:41:03.445957 DQ_P2S_RATIO = 8
7096 11:41:03.448781 ===================================
7097 11:41:03.452422 CA_P2S_RATIO = 8
7098 11:41:03.455230 DQ_CA_OPEN = 0
7099 11:41:03.455312 DQ_SEMI_OPEN = 0
7100 11:41:03.458725 CA_SEMI_OPEN = 0
7101 11:41:03.461830 CA_FULL_RATE = 0
7102 11:41:03.465410 DQ_CKDIV4_EN = 0
7103 11:41:03.468826 CA_CKDIV4_EN = 0
7104 11:41:03.471992 CA_PREDIV_EN = 0
7105 11:41:03.475126 PH8_DLY = 12
7106 11:41:03.475208 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7107 11:41:03.478213 DQ_AAMCK_DIV = 4
7108 11:41:03.481672 CA_AAMCK_DIV = 4
7109 11:41:03.485065 CA_ADMCK_DIV = 4
7110 11:41:03.488288 DQ_TRACK_CA_EN = 0
7111 11:41:03.491677 CA_PICK = 1600
7112 11:41:03.494998 CA_MCKIO = 1600
7113 11:41:03.495109 MCKIO_SEMI = 0
7114 11:41:03.498485 PLL_FREQ = 3068
7115 11:41:03.501923 DQ_UI_PI_RATIO = 32
7116 11:41:03.504900 CA_UI_PI_RATIO = 0
7117 11:41:03.507958 ===================================
7118 11:41:03.511320 ===================================
7119 11:41:03.515571 memory_type:LPDDR4
7120 11:41:03.515656 GP_NUM : 10
7121 11:41:03.518238 SRAM_EN : 1
7122 11:41:03.521609 MD32_EN : 0
7123 11:41:03.524729 ===================================
7124 11:41:03.524815 [ANA_INIT] >>>>>>>>>>>>>>
7125 11:41:03.527906 <<<<<< [CONFIGURE PHASE]: ANA_TX
7126 11:41:03.531563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7127 11:41:03.535052 ===================================
7128 11:41:03.537699 data_rate = 3200,PCW = 0X7600
7129 11:41:03.541062 ===================================
7130 11:41:03.544535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7131 11:41:03.550873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7132 11:41:03.554135 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 11:41:03.560973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7134 11:41:03.564362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7135 11:41:03.567227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7136 11:41:03.570753 [ANA_INIT] flow start
7137 11:41:03.570836 [ANA_INIT] PLL >>>>>>>>
7138 11:41:03.573998 [ANA_INIT] PLL <<<<<<<<
7139 11:41:03.577182 [ANA_INIT] MIDPI >>>>>>>>
7140 11:41:03.577265 [ANA_INIT] MIDPI <<<<<<<<
7141 11:41:03.580302 [ANA_INIT] DLL >>>>>>>>
7142 11:41:03.583932 [ANA_INIT] DLL <<<<<<<<
7143 11:41:03.584080 [ANA_INIT] flow end
7144 11:41:03.590558 ============ LP4 DIFF to SE enter ============
7145 11:41:03.594387 ============ LP4 DIFF to SE exit ============
7146 11:41:03.597283 [ANA_INIT] <<<<<<<<<<<<<
7147 11:41:03.600151 [Flow] Enable top DCM control >>>>>
7148 11:41:03.603454 [Flow] Enable top DCM control <<<<<
7149 11:41:03.603536 Enable DLL master slave shuffle
7150 11:41:03.610394 ==============================================================
7151 11:41:03.613464 Gating Mode config
7152 11:41:03.616809 ==============================================================
7153 11:41:03.619953 Config description:
7154 11:41:03.629949 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7155 11:41:03.636506 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7156 11:41:03.639954 SELPH_MODE 0: By rank 1: By Phase
7157 11:41:03.646711 ==============================================================
7158 11:41:03.649402 GAT_TRACK_EN = 1
7159 11:41:03.652691 RX_GATING_MODE = 2
7160 11:41:03.656246 RX_GATING_TRACK_MODE = 2
7161 11:41:03.659143 SELPH_MODE = 1
7162 11:41:03.663270 PICG_EARLY_EN = 1
7163 11:41:03.665818 VALID_LAT_VALUE = 1
7164 11:41:03.669543 ==============================================================
7165 11:41:03.672497 Enter into Gating configuration >>>>
7166 11:41:03.675914 Exit from Gating configuration <<<<
7167 11:41:03.678983 Enter into DVFS_PRE_config >>>>>
7168 11:41:03.692005 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7169 11:41:03.692114 Exit from DVFS_PRE_config <<<<<
7170 11:41:03.695414 Enter into PICG configuration >>>>
7171 11:41:03.698823 Exit from PICG configuration <<<<
7172 11:41:03.702309 [RX_INPUT] configuration >>>>>
7173 11:41:03.705491 [RX_INPUT] configuration <<<<<
7174 11:41:03.711811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7175 11:41:03.715598 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7176 11:41:03.721634 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 11:41:03.728698 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 11:41:03.734927 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 11:41:03.741523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 11:41:03.745180 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7181 11:41:03.748318 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7182 11:41:03.755159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7183 11:41:03.758386 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7184 11:41:03.762070 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7185 11:41:03.764914 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 11:41:03.768378 ===================================
7187 11:41:03.771574 LPDDR4 DRAM CONFIGURATION
7188 11:41:03.774605 ===================================
7189 11:41:03.778032 EX_ROW_EN[0] = 0x0
7190 11:41:03.778334 EX_ROW_EN[1] = 0x0
7191 11:41:03.781128 LP4Y_EN = 0x0
7192 11:41:03.781441 WORK_FSP = 0x1
7193 11:41:03.784995 WL = 0x5
7194 11:41:03.785326 RL = 0x5
7195 11:41:03.788381 BL = 0x2
7196 11:41:03.788709 RPST = 0x0
7197 11:41:03.791041 RD_PRE = 0x0
7198 11:41:03.794509 WR_PRE = 0x1
7199 11:41:03.794849 WR_PST = 0x1
7200 11:41:03.797731 DBI_WR = 0x0
7201 11:41:03.798127 DBI_RD = 0x0
7202 11:41:03.801343 OTF = 0x1
7203 11:41:03.804234 ===================================
7204 11:41:03.807538 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7205 11:41:03.811173 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7206 11:41:03.814484 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7207 11:41:03.817490 ===================================
7208 11:41:03.820966 LPDDR4 DRAM CONFIGURATION
7209 11:41:03.824143 ===================================
7210 11:41:03.827759 EX_ROW_EN[0] = 0x10
7211 11:41:03.828119 EX_ROW_EN[1] = 0x0
7212 11:41:03.830731 LP4Y_EN = 0x0
7213 11:41:03.831063 WORK_FSP = 0x1
7214 11:41:03.833994 WL = 0x5
7215 11:41:03.834359 RL = 0x5
7216 11:41:03.838156 BL = 0x2
7217 11:41:03.838520 RPST = 0x0
7218 11:41:03.841071 RD_PRE = 0x0
7219 11:41:03.841671 WR_PRE = 0x1
7220 11:41:03.844541 WR_PST = 0x1
7221 11:41:03.847377 DBI_WR = 0x0
7222 11:41:03.847763 DBI_RD = 0x0
7223 11:41:03.851089 OTF = 0x1
7224 11:41:03.854387 ===================================
7225 11:41:03.857643 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7226 11:41:03.861017 ==
7227 11:41:03.863914 Dram Type= 6, Freq= 0, CH_0, rank 0
7228 11:41:03.867241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7229 11:41:03.867454 ==
7230 11:41:03.870309 [Duty_Offset_Calibration]
7231 11:41:03.870480 B0:2 B1:0 CA:4
7232 11:41:03.870614
7233 11:41:03.874055 [DutyScan_Calibration_Flow] k_type=0
7234 11:41:03.882784
7235 11:41:03.882955 ==CLK 0==
7236 11:41:03.886124 Final CLK duty delay cell = -4
7237 11:41:03.889595 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7238 11:41:03.892865 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7239 11:41:03.896410 [-4] AVG Duty = 4906%(X100)
7240 11:41:03.896501
7241 11:41:03.899317 CH0 CLK Duty spec in!! Max-Min= 187%
7242 11:41:03.902329 [DutyScan_Calibration_Flow] ====Done====
7243 11:41:03.902460
7244 11:41:03.905758 [DutyScan_Calibration_Flow] k_type=1
7245 11:41:03.922484
7246 11:41:03.922619 ==DQS 0 ==
7247 11:41:03.925312 Final DQS duty delay cell = -4
7248 11:41:03.929130 [-4] MAX Duty = 4938%(X100), DQS PI = 46
7249 11:41:03.931894 [-4] MIN Duty = 4782%(X100), DQS PI = 4
7250 11:41:03.935458 [-4] AVG Duty = 4860%(X100)
7251 11:41:03.935542
7252 11:41:03.935608 ==DQS 1 ==
7253 11:41:03.938456 Final DQS duty delay cell = 0
7254 11:41:03.942085 [0] MAX Duty = 5156%(X100), DQS PI = 0
7255 11:41:03.945150 [0] MIN Duty = 4969%(X100), DQS PI = 12
7256 11:41:03.948737 [0] AVG Duty = 5062%(X100)
7257 11:41:03.948821
7258 11:41:03.951714 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7259 11:41:03.951797
7260 11:41:03.955034 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7261 11:41:03.958183 [DutyScan_Calibration_Flow] ====Done====
7262 11:41:03.958268
7263 11:41:03.961873 [DutyScan_Calibration_Flow] k_type=3
7264 11:41:03.979542
7265 11:41:03.979632 ==DQM 0 ==
7266 11:41:03.982666 Final DQM duty delay cell = 0
7267 11:41:03.986437 [0] MAX Duty = 5124%(X100), DQS PI = 22
7268 11:41:03.989314 [0] MIN Duty = 4875%(X100), DQS PI = 54
7269 11:41:03.992683 [0] AVG Duty = 4999%(X100)
7270 11:41:03.992768
7271 11:41:03.992854 ==DQM 1 ==
7272 11:41:03.996072 Final DQM duty delay cell = 0
7273 11:41:03.999235 [0] MAX Duty = 4969%(X100), DQS PI = 2
7274 11:41:04.002865 [0] MIN Duty = 4844%(X100), DQS PI = 18
7275 11:41:04.006103 [0] AVG Duty = 4906%(X100)
7276 11:41:04.006187
7277 11:41:04.009219 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7278 11:41:04.009304
7279 11:41:04.012620 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7280 11:41:04.015818 [DutyScan_Calibration_Flow] ====Done====
7281 11:41:04.015901
7282 11:41:04.019314 [DutyScan_Calibration_Flow] k_type=2
7283 11:41:04.036816
7284 11:41:04.036926 ==DQ 0 ==
7285 11:41:04.039706 Final DQ duty delay cell = 0
7286 11:41:04.043452 [0] MAX Duty = 5124%(X100), DQS PI = 20
7287 11:41:04.046606 [0] MIN Duty = 4938%(X100), DQS PI = 12
7288 11:41:04.049822 [0] AVG Duty = 5031%(X100)
7289 11:41:04.049919
7290 11:41:04.050008 ==DQ 1 ==
7291 11:41:04.052717 Final DQ duty delay cell = 0
7292 11:41:04.056536 [0] MAX Duty = 5187%(X100), DQS PI = 2
7293 11:41:04.059695 [0] MIN Duty = 4938%(X100), DQS PI = 12
7294 11:41:04.063346 [0] AVG Duty = 5062%(X100)
7295 11:41:04.063431
7296 11:41:04.066338 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7297 11:41:04.066420
7298 11:41:04.069827 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7299 11:41:04.072815 [DutyScan_Calibration_Flow] ====Done====
7300 11:41:04.072898 ==
7301 11:41:04.076281 Dram Type= 6, Freq= 0, CH_1, rank 0
7302 11:41:04.079207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7303 11:41:04.079316 ==
7304 11:41:04.082412 [Duty_Offset_Calibration]
7305 11:41:04.082509 B0:0 B1:-1 CA:3
7306 11:41:04.082597
7307 11:41:04.086218 [DutyScan_Calibration_Flow] k_type=0
7308 11:41:04.096459
7309 11:41:04.096543 ==CLK 0==
7310 11:41:04.099659 Final CLK duty delay cell = -4
7311 11:41:04.102743 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7312 11:41:04.105682 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7313 11:41:04.109190 [-4] AVG Duty = 4937%(X100)
7314 11:41:04.109271
7315 11:41:04.112598 CH1 CLK Duty spec in!! Max-Min= 125%
7316 11:41:04.116058 [DutyScan_Calibration_Flow] ====Done====
7317 11:41:04.116152
7318 11:41:04.118956 [DutyScan_Calibration_Flow] k_type=1
7319 11:41:04.135474
7320 11:41:04.135564 ==DQS 0 ==
7321 11:41:04.138863 Final DQS duty delay cell = 0
7322 11:41:04.141672 [0] MAX Duty = 5250%(X100), DQS PI = 28
7323 11:41:04.145153 [0] MIN Duty = 4938%(X100), DQS PI = 56
7324 11:41:04.148345 [0] AVG Duty = 5094%(X100)
7325 11:41:04.148428
7326 11:41:04.148492 ==DQS 1 ==
7327 11:41:04.151927 Final DQS duty delay cell = -4
7328 11:41:04.155090 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7329 11:41:04.158630 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7330 11:41:04.161512 [-4] AVG Duty = 4922%(X100)
7331 11:41:04.161593
7332 11:41:04.164978 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7333 11:41:04.165058
7334 11:41:04.168309 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7335 11:41:04.171608 [DutyScan_Calibration_Flow] ====Done====
7336 11:41:04.171713
7337 11:41:04.174623 [DutyScan_Calibration_Flow] k_type=3
7338 11:41:04.192478
7339 11:41:04.192573 ==DQM 0 ==
7340 11:41:04.195722 Final DQM duty delay cell = 0
7341 11:41:04.199845 [0] MAX Duty = 5062%(X100), DQS PI = 30
7342 11:41:04.202394 [0] MIN Duty = 4750%(X100), DQS PI = 40
7343 11:41:04.206203 [0] AVG Duty = 4906%(X100)
7344 11:41:04.206287
7345 11:41:04.206351 ==DQM 1 ==
7346 11:41:04.209074 Final DQM duty delay cell = 0
7347 11:41:04.212193 [0] MAX Duty = 5000%(X100), DQS PI = 32
7348 11:41:04.215539 [0] MIN Duty = 4813%(X100), DQS PI = 0
7349 11:41:04.219067 [0] AVG Duty = 4906%(X100)
7350 11:41:04.219156
7351 11:41:04.222343 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7352 11:41:04.222425
7353 11:41:04.225610 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7354 11:41:04.229340 [DutyScan_Calibration_Flow] ====Done====
7355 11:41:04.229421
7356 11:41:04.232712 [DutyScan_Calibration_Flow] k_type=2
7357 11:41:04.248577
7358 11:41:04.248686 ==DQ 0 ==
7359 11:41:04.251726 Final DQ duty delay cell = -4
7360 11:41:04.254997 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7361 11:41:04.258384 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7362 11:41:04.262095 [-4] AVG Duty = 4891%(X100)
7363 11:41:04.262227
7364 11:41:04.262332 ==DQ 1 ==
7365 11:41:04.265578 Final DQ duty delay cell = 0
7366 11:41:04.268289 [0] MAX Duty = 5031%(X100), DQS PI = 30
7367 11:41:04.271901 [0] MIN Duty = 4875%(X100), DQS PI = 56
7368 11:41:04.275303 [0] AVG Duty = 4953%(X100)
7369 11:41:04.275502
7370 11:41:04.278654 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7371 11:41:04.278888
7372 11:41:04.281785 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7373 11:41:04.285125 [DutyScan_Calibration_Flow] ====Done====
7374 11:41:04.288161 nWR fixed to 30
7375 11:41:04.291496 [ModeRegInit_LP4] CH0 RK0
7376 11:41:04.291581 [ModeRegInit_LP4] CH0 RK1
7377 11:41:04.295023 [ModeRegInit_LP4] CH1 RK0
7378 11:41:04.298246 [ModeRegInit_LP4] CH1 RK1
7379 11:41:04.298346 match AC timing 5
7380 11:41:04.304398 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7381 11:41:04.307644 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7382 11:41:04.310917 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7383 11:41:04.317894 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7384 11:41:04.321154 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7385 11:41:04.324300 [MiockJmeterHQA]
7386 11:41:04.324379
7387 11:41:04.327861 [DramcMiockJmeter] u1RxGatingPI = 0
7388 11:41:04.327941 0 : 4257, 4029
7389 11:41:04.328006 4 : 4363, 4137
7390 11:41:04.330871 8 : 4252, 4027
7391 11:41:04.330952 12 : 4363, 4137
7392 11:41:04.334395 16 : 4363, 4138
7393 11:41:04.334476 20 : 4253, 4026
7394 11:41:04.337249 24 : 4252, 4027
7395 11:41:04.337329 28 : 4252, 4027
7396 11:41:04.337393 32 : 4363, 4137
7397 11:41:04.340563 36 : 4252, 4027
7398 11:41:04.340644 40 : 4360, 4137
7399 11:41:04.343997 44 : 4252, 4027
7400 11:41:04.344120 48 : 4250, 4027
7401 11:41:04.347448 52 : 4250, 4026
7402 11:41:04.347529 56 : 4252, 4030
7403 11:41:04.350820 60 : 4250, 4027
7404 11:41:04.350901 64 : 4250, 4027
7405 11:41:04.350965 68 : 4363, 4140
7406 11:41:04.354132 72 : 4250, 4026
7407 11:41:04.354214 76 : 4252, 4030
7408 11:41:04.357080 80 : 4250, 4027
7409 11:41:04.357162 84 : 4361, 4137
7410 11:41:04.360479 88 : 4250, 4027
7411 11:41:04.360563 92 : 4360, 4137
7412 11:41:04.363865 96 : 4252, 2971
7413 11:41:04.363977 100 : 4250, 0
7414 11:41:04.364120 104 : 4250, 0
7415 11:41:04.367197 108 : 4254, 0
7416 11:41:04.367297 112 : 4250, 0
7417 11:41:04.370578 116 : 4252, 0
7418 11:41:04.370663 120 : 4361, 0
7419 11:41:04.370749 124 : 4250, 0
7420 11:41:04.373758 128 : 4250, 0
7421 11:41:04.373843 132 : 4360, 0
7422 11:41:04.373929 136 : 4360, 0
7423 11:41:04.377108 140 : 4250, 0
7424 11:41:04.377194 144 : 4250, 0
7425 11:41:04.380380 148 : 4361, 0
7426 11:41:04.380465 152 : 4360, 0
7427 11:41:04.380549 156 : 4249, 0
7428 11:41:04.383985 160 : 4250, 0
7429 11:41:04.384112 164 : 4250, 0
7430 11:41:04.387328 168 : 4250, 0
7431 11:41:04.387413 172 : 4250, 0
7432 11:41:04.387498 176 : 4250, 0
7433 11:41:04.389854 180 : 4250, 0
7434 11:41:04.389954 184 : 4360, 0
7435 11:41:04.393489 188 : 4361, 0
7436 11:41:04.393574 192 : 4361, 0
7437 11:41:04.393659 196 : 4250, 0
7438 11:41:04.396603 200 : 4361, 0
7439 11:41:04.396691 204 : 4360, 0
7440 11:41:04.399803 208 : 4250, 0
7441 11:41:04.399888 212 : 4250, 0
7442 11:41:04.399992 216 : 4250, 0
7443 11:41:04.403316 220 : 4250, 961
7444 11:41:04.403401 224 : 4250, 4019
7445 11:41:04.406731 228 : 4250, 4026
7446 11:41:04.406817 232 : 4250, 4027
7447 11:41:04.410274 236 : 4250, 4027
7448 11:41:04.410384 240 : 4250, 4027
7449 11:41:04.413182 244 : 4250, 4026
7450 11:41:04.413267 248 : 4250, 4027
7451 11:41:04.416480 252 : 4252, 4030
7452 11:41:04.416566 256 : 4250, 4027
7453 11:41:04.419782 260 : 4360, 4137
7454 11:41:04.419892 264 : 4361, 4137
7455 11:41:04.419996 268 : 4250, 4027
7456 11:41:04.422913 272 : 4363, 4140
7457 11:41:04.423014 276 : 4250, 4027
7458 11:41:04.426404 280 : 4250, 4026
7459 11:41:04.426489 284 : 4250, 4027
7460 11:41:04.430077 288 : 4252, 4030
7461 11:41:04.430163 292 : 4250, 4027
7462 11:41:04.433104 296 : 4250, 4026
7463 11:41:04.433190 300 : 4250, 4027
7464 11:41:04.436008 304 : 4252, 4030
7465 11:41:04.436118 308 : 4250, 4027
7466 11:41:04.439531 312 : 4360, 4137
7467 11:41:04.439616 316 : 4361, 4137
7468 11:41:04.442694 320 : 4250, 4027
7469 11:41:04.442780 324 : 4363, 4140
7470 11:41:04.446053 328 : 4250, 4027
7471 11:41:04.446138 332 : 4250, 3935
7472 11:41:04.446224 336 : 4250, 1670
7473 11:41:04.449537
7474 11:41:04.449620 MIOCK jitter meter ch=0
7475 11:41:04.449704
7476 11:41:04.452458 1T = (336-100) = 236 dly cells
7477 11:41:04.459478 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7478 11:41:04.459563 ==
7479 11:41:04.462332 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 11:41:04.465444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7481 11:41:04.465530 ==
7482 11:41:04.472638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7483 11:41:04.475504 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7484 11:41:04.478820 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7485 11:41:04.485842 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7486 11:41:04.495553 [CA 0] Center 44 (14~74) winsize 61
7487 11:41:04.498931 [CA 1] Center 43 (13~74) winsize 62
7488 11:41:04.501679 [CA 2] Center 39 (10~68) winsize 59
7489 11:41:04.505053 [CA 3] Center 38 (9~68) winsize 60
7490 11:41:04.508340 [CA 4] Center 36 (7~66) winsize 60
7491 11:41:04.511772 [CA 5] Center 36 (6~66) winsize 61
7492 11:41:04.511862
7493 11:41:04.515000 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7494 11:41:04.515098
7495 11:41:04.521643 [CATrainingPosCal] consider 1 rank data
7496 11:41:04.521748 u2DelayCellTimex100 = 275/100 ps
7497 11:41:04.528090 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7498 11:41:04.531842 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7499 11:41:04.535027 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7500 11:41:04.538265 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7501 11:41:04.541521 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7502 11:41:04.544616 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7503 11:41:04.544792
7504 11:41:04.547904 CA PerBit enable=1, Macro0, CA PI delay=36
7505 11:41:04.548130
7506 11:41:04.551290 [CBTSetCACLKResult] CA Dly = 36
7507 11:41:04.554424 CS Dly: 11 (0~42)
7508 11:41:04.557835 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7509 11:41:04.561241 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7510 11:41:04.564856 ==
7511 11:41:04.565244 Dram Type= 6, Freq= 0, CH_0, rank 1
7512 11:41:04.571136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7513 11:41:04.571749 ==
7514 11:41:04.574138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7515 11:41:04.580992 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7516 11:41:04.584367 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7517 11:41:04.590739 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7518 11:41:04.599275 [CA 0] Center 43 (13~74) winsize 62
7519 11:41:04.602786 [CA 1] Center 43 (13~73) winsize 61
7520 11:41:04.606054 [CA 2] Center 38 (9~68) winsize 60
7521 11:41:04.609332 [CA 3] Center 38 (9~68) winsize 60
7522 11:41:04.611894 [CA 4] Center 37 (7~67) winsize 61
7523 11:41:04.615293 [CA 5] Center 36 (6~66) winsize 61
7524 11:41:04.615698
7525 11:41:04.618633 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7526 11:41:04.619008
7527 11:41:04.625671 [CATrainingPosCal] consider 2 rank data
7528 11:41:04.626028 u2DelayCellTimex100 = 275/100 ps
7529 11:41:04.632107 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7530 11:41:04.635620 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7531 11:41:04.638560 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7532 11:41:04.641704 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7533 11:41:04.645212 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7534 11:41:04.648684 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7535 11:41:04.649044
7536 11:41:04.651976 CA PerBit enable=1, Macro0, CA PI delay=36
7537 11:41:04.652517
7538 11:41:04.655242 [CBTSetCACLKResult] CA Dly = 36
7539 11:41:04.658719 CS Dly: 12 (0~44)
7540 11:41:04.661897 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7541 11:41:04.664696 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7542 11:41:04.665088
7543 11:41:04.668381 ----->DramcWriteLeveling(PI) begin...
7544 11:41:04.671573 ==
7545 11:41:04.674898 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 11:41:04.677791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 11:41:04.678308 ==
7548 11:41:04.681482 Write leveling (Byte 0): 36 => 36
7549 11:41:04.684505 Write leveling (Byte 1): 27 => 27
7550 11:41:04.688135 DramcWriteLeveling(PI) end<-----
7551 11:41:04.688545
7552 11:41:04.688859 ==
7553 11:41:04.691239 Dram Type= 6, Freq= 0, CH_0, rank 0
7554 11:41:04.694590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 11:41:04.694985 ==
7556 11:41:04.697857 [Gating] SW mode calibration
7557 11:41:04.704887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7558 11:41:04.710628 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7559 11:41:04.714041 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 11:41:04.717372 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 11:41:04.724017 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 11:41:04.726998 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7563 11:41:04.730353 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7564 11:41:04.736990 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 0) (1 1)
7565 11:41:04.740301 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7566 11:41:04.743662 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 11:41:04.750232 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 11:41:04.753405 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7569 11:41:04.756881 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7570 11:41:04.763817 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
7571 11:41:04.766447 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7572 11:41:04.769483 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
7573 11:41:04.776325 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7574 11:41:04.779639 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 11:41:04.782921 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 11:41:04.789366 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 11:41:04.792861 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7578 11:41:04.796217 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7579 11:41:04.802983 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7580 11:41:04.805726 1 6 20 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7581 11:41:04.809383 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 11:41:04.815954 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 11:41:04.819064 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 11:41:04.822460 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 11:41:04.828788 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7586 11:41:04.832142 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7587 11:41:04.838562 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7588 11:41:04.841841 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7589 11:41:04.845505 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 11:41:04.852161 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:41:04.855277 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:41:04.858964 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:41:04.865015 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 11:41:04.868169 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 11:41:04.871376 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:41:04.878176 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 11:41:04.881649 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 11:41:04.884699 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 11:41:04.891440 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 11:41:04.895089 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 11:41:04.898157 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7602 11:41:04.904449 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 11:41:04.908209 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7604 11:41:04.911262 Total UI for P1: 0, mck2ui 16
7605 11:41:04.914188 best dqsien dly found for B0: ( 1, 9, 10)
7606 11:41:04.917551 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 11:41:04.924555 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 11:41:04.928082 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 11:41:04.930974 Total UI for P1: 0, mck2ui 16
7610 11:41:04.934163 best dqsien dly found for B1: ( 1, 9, 22)
7611 11:41:04.937491 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7612 11:41:04.940811 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7613 11:41:04.941216
7614 11:41:04.943689 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7615 11:41:04.947558 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7616 11:41:04.950954 [Gating] SW calibration Done
7617 11:41:04.951366 ==
7618 11:41:04.953537 Dram Type= 6, Freq= 0, CH_0, rank 0
7619 11:41:04.960485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7620 11:41:04.960895 ==
7621 11:41:04.961318 RX Vref Scan: 0
7622 11:41:04.961759
7623 11:41:04.963913 RX Vref 0 -> 0, step: 1
7624 11:41:04.964428
7625 11:41:04.967152 RX Delay 0 -> 252, step: 8
7626 11:41:04.970291 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7627 11:41:04.974149 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7628 11:41:04.976866 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7629 11:41:04.980415 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7630 11:41:04.986518 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7631 11:41:04.989988 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7632 11:41:04.993576 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7633 11:41:04.996916 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7634 11:41:04.999689 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7635 11:41:05.006875 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7636 11:41:05.009563 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7637 11:41:05.012956 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7638 11:41:05.016259 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7639 11:41:05.022683 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7640 11:41:05.026049 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7641 11:41:05.029523 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7642 11:41:05.029958 ==
7643 11:41:05.032807 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 11:41:05.035983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 11:41:05.036431 ==
7646 11:41:05.039429 DQS Delay:
7647 11:41:05.039827 DQS0 = 0, DQS1 = 0
7648 11:41:05.042606 DQM Delay:
7649 11:41:05.043011 DQM0 = 131, DQM1 = 126
7650 11:41:05.043423 DQ Delay:
7651 11:41:05.049299 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7652 11:41:05.052915 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7653 11:41:05.055970 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7654 11:41:05.059361 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7655 11:41:05.059772
7656 11:41:05.060268
7657 11:41:05.060708 ==
7658 11:41:05.062411 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 11:41:05.065613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 11:41:05.066194 ==
7661 11:41:05.066713
7662 11:41:05.069364
7663 11:41:05.069772 TX Vref Scan disable
7664 11:41:05.072160 == TX Byte 0 ==
7665 11:41:05.075754 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7666 11:41:05.079071 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7667 11:41:05.082455 == TX Byte 1 ==
7668 11:41:05.085317 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7669 11:41:05.088787 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7670 11:41:05.089200 ==
7671 11:41:05.092000 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 11:41:05.098584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 11:41:05.099224 ==
7674 11:41:05.111039
7675 11:41:05.114664 TX Vref early break, caculate TX vref
7676 11:41:05.117678 TX Vref=16, minBit 1, minWin=21, winSum=358
7677 11:41:05.121013 TX Vref=18, minBit 7, minWin=21, winSum=373
7678 11:41:05.124800 TX Vref=20, minBit 1, minWin=22, winSum=380
7679 11:41:05.127478 TX Vref=22, minBit 1, minWin=23, winSum=393
7680 11:41:05.130907 TX Vref=24, minBit 1, minWin=23, winSum=403
7681 11:41:05.138039 TX Vref=26, minBit 0, minWin=24, winSum=408
7682 11:41:05.141311 TX Vref=28, minBit 0, minWin=24, winSum=415
7683 11:41:05.144229 TX Vref=30, minBit 0, minWin=24, winSum=409
7684 11:41:05.147516 TX Vref=32, minBit 4, minWin=23, winSum=401
7685 11:41:05.151245 TX Vref=34, minBit 4, minWin=22, winSum=392
7686 11:41:05.157628 [TxChooseVref] Worse bit 0, Min win 24, Win sum 415, Final Vref 28
7687 11:41:05.158024
7688 11:41:05.161416 Final TX Range 0 Vref 28
7689 11:41:05.161878
7690 11:41:05.162293 ==
7691 11:41:05.164175 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 11:41:05.167439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 11:41:05.167804 ==
7694 11:41:05.168115
7695 11:41:05.168388
7696 11:41:05.170571 TX Vref Scan disable
7697 11:41:05.177542 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7698 11:41:05.177908 == TX Byte 0 ==
7699 11:41:05.180477 u2DelayCellOfst[0]=10 cells (3 PI)
7700 11:41:05.183714 u2DelayCellOfst[1]=14 cells (4 PI)
7701 11:41:05.187656 u2DelayCellOfst[2]=10 cells (3 PI)
7702 11:41:05.190467 u2DelayCellOfst[3]=10 cells (3 PI)
7703 11:41:05.193757 u2DelayCellOfst[4]=7 cells (2 PI)
7704 11:41:05.197166 u2DelayCellOfst[5]=0 cells (0 PI)
7705 11:41:05.200090 u2DelayCellOfst[6]=17 cells (5 PI)
7706 11:41:05.203125 u2DelayCellOfst[7]=14 cells (4 PI)
7707 11:41:05.207415 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7708 11:41:05.210197 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7709 11:41:05.213364 == TX Byte 1 ==
7710 11:41:05.216596 u2DelayCellOfst[8]=0 cells (0 PI)
7711 11:41:05.220272 u2DelayCellOfst[9]=0 cells (0 PI)
7712 11:41:05.223004 u2DelayCellOfst[10]=7 cells (2 PI)
7713 11:41:05.226442 u2DelayCellOfst[11]=3 cells (1 PI)
7714 11:41:05.226911 u2DelayCellOfst[12]=10 cells (3 PI)
7715 11:41:05.229442 u2DelayCellOfst[13]=10 cells (3 PI)
7716 11:41:05.233306 u2DelayCellOfst[14]=14 cells (4 PI)
7717 11:41:05.236497 u2DelayCellOfst[15]=10 cells (3 PI)
7718 11:41:05.242799 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7719 11:41:05.246749 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7720 11:41:05.247150 DramC Write-DBI on
7721 11:41:05.249618 ==
7722 11:41:05.252621 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 11:41:05.255870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 11:41:05.256331 ==
7725 11:41:05.256768
7726 11:41:05.257198
7727 11:41:05.259267 TX Vref Scan disable
7728 11:41:05.259801 == TX Byte 0 ==
7729 11:41:05.266145 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7730 11:41:05.266726 == TX Byte 1 ==
7731 11:41:05.269197 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7732 11:41:05.272274 DramC Write-DBI off
7733 11:41:05.272706
7734 11:41:05.273131 [DATLAT]
7735 11:41:05.275720 Freq=1600, CH0 RK0
7736 11:41:05.276274
7737 11:41:05.276660 DATLAT Default: 0xf
7738 11:41:05.279106 0, 0xFFFF, sum = 0
7739 11:41:05.279566 1, 0xFFFF, sum = 0
7740 11:41:05.282500 2, 0xFFFF, sum = 0
7741 11:41:05.285827 3, 0xFFFF, sum = 0
7742 11:41:05.286235 4, 0xFFFF, sum = 0
7743 11:41:05.289253 5, 0xFFFF, sum = 0
7744 11:41:05.289705 6, 0xFFFF, sum = 0
7745 11:41:05.292116 7, 0xFFFF, sum = 0
7746 11:41:05.292504 8, 0xFFFF, sum = 0
7747 11:41:05.295432 9, 0xFFFF, sum = 0
7748 11:41:05.295805 10, 0xFFFF, sum = 0
7749 11:41:05.298786 11, 0xFFFF, sum = 0
7750 11:41:05.299306 12, 0xFFFF, sum = 0
7751 11:41:05.302149 13, 0xFFFF, sum = 0
7752 11:41:05.302496 14, 0x0, sum = 1
7753 11:41:05.305284 15, 0x0, sum = 2
7754 11:41:05.305713 16, 0x0, sum = 3
7755 11:41:05.308542 17, 0x0, sum = 4
7756 11:41:05.308937 best_step = 15
7757 11:41:05.309263
7758 11:41:05.309551 ==
7759 11:41:05.312215 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 11:41:05.318490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 11:41:05.318881 ==
7762 11:41:05.319279 RX Vref Scan: 1
7763 11:41:05.319690
7764 11:41:05.321695 Set Vref Range= 24 -> 127
7765 11:41:05.322081
7766 11:41:05.325067 RX Vref 24 -> 127, step: 1
7767 11:41:05.325453
7768 11:41:05.325755 RX Delay 11 -> 252, step: 4
7769 11:41:05.328469
7770 11:41:05.328853 Set Vref, RX VrefLevel [Byte0]: 24
7771 11:41:05.331813 [Byte1]: 24
7772 11:41:05.335897
7773 11:41:05.336352 Set Vref, RX VrefLevel [Byte0]: 25
7774 11:41:05.339039 [Byte1]: 25
7775 11:41:05.343535
7776 11:41:05.343920 Set Vref, RX VrefLevel [Byte0]: 26
7777 11:41:05.346975 [Byte1]: 26
7778 11:41:05.351314
7779 11:41:05.351765 Set Vref, RX VrefLevel [Byte0]: 27
7780 11:41:05.354779 [Byte1]: 27
7781 11:41:05.358714
7782 11:41:05.359138 Set Vref, RX VrefLevel [Byte0]: 28
7783 11:41:05.362022 [Byte1]: 28
7784 11:41:05.366255
7785 11:41:05.366677 Set Vref, RX VrefLevel [Byte0]: 29
7786 11:41:05.370175 [Byte1]: 29
7787 11:41:05.374078
7788 11:41:05.374581 Set Vref, RX VrefLevel [Byte0]: 30
7789 11:41:05.377165 [Byte1]: 30
7790 11:41:05.381443
7791 11:41:05.381827 Set Vref, RX VrefLevel [Byte0]: 31
7792 11:41:05.384700 [Byte1]: 31
7793 11:41:05.389068
7794 11:41:05.389572 Set Vref, RX VrefLevel [Byte0]: 32
7795 11:41:05.392435 [Byte1]: 32
7796 11:41:05.396746
7797 11:41:05.397132 Set Vref, RX VrefLevel [Byte0]: 33
7798 11:41:05.400123 [Byte1]: 33
7799 11:41:05.404120
7800 11:41:05.404473 Set Vref, RX VrefLevel [Byte0]: 34
7801 11:41:05.407735 [Byte1]: 34
7802 11:41:05.411965
7803 11:41:05.412401 Set Vref, RX VrefLevel [Byte0]: 35
7804 11:41:05.415277 [Byte1]: 35
7805 11:41:05.419873
7806 11:41:05.420388 Set Vref, RX VrefLevel [Byte0]: 36
7807 11:41:05.423035 [Byte1]: 36
7808 11:41:05.427195
7809 11:41:05.427579 Set Vref, RX VrefLevel [Byte0]: 37
7810 11:41:05.430653 [Byte1]: 37
7811 11:41:05.434836
7812 11:41:05.435263 Set Vref, RX VrefLevel [Byte0]: 38
7813 11:41:05.438353 [Byte1]: 38
7814 11:41:05.443197
7815 11:41:05.443786 Set Vref, RX VrefLevel [Byte0]: 39
7816 11:41:05.446181 [Byte1]: 39
7817 11:41:05.450423
7818 11:41:05.450842 Set Vref, RX VrefLevel [Byte0]: 40
7819 11:41:05.453719 [Byte1]: 40
7820 11:41:05.457614
7821 11:41:05.458121 Set Vref, RX VrefLevel [Byte0]: 41
7822 11:41:05.460993 [Byte1]: 41
7823 11:41:05.465711
7824 11:41:05.466358 Set Vref, RX VrefLevel [Byte0]: 42
7825 11:41:05.469076 [Byte1]: 42
7826 11:41:05.473440
7827 11:41:05.473862 Set Vref, RX VrefLevel [Byte0]: 43
7828 11:41:05.476504 [Byte1]: 43
7829 11:41:05.480689
7830 11:41:05.481169 Set Vref, RX VrefLevel [Byte0]: 44
7831 11:41:05.483997 [Byte1]: 44
7832 11:41:05.488398
7833 11:41:05.488824 Set Vref, RX VrefLevel [Byte0]: 45
7834 11:41:05.491520 [Byte1]: 45
7835 11:41:05.495723
7836 11:41:05.496228 Set Vref, RX VrefLevel [Byte0]: 46
7837 11:41:05.499195 [Byte1]: 46
7838 11:41:05.503671
7839 11:41:05.504124 Set Vref, RX VrefLevel [Byte0]: 47
7840 11:41:05.507062 [Byte1]: 47
7841 11:41:05.511239
7842 11:41:05.511708 Set Vref, RX VrefLevel [Byte0]: 48
7843 11:41:05.514784 [Byte1]: 48
7844 11:41:05.518595
7845 11:41:05.519020 Set Vref, RX VrefLevel [Byte0]: 49
7846 11:41:05.522172 [Byte1]: 49
7847 11:41:05.526529
7848 11:41:05.526950 Set Vref, RX VrefLevel [Byte0]: 50
7849 11:41:05.530081 [Byte1]: 50
7850 11:41:05.533993
7851 11:41:05.534414 Set Vref, RX VrefLevel [Byte0]: 51
7852 11:41:05.537462 [Byte1]: 51
7853 11:41:05.541575
7854 11:41:05.542067 Set Vref, RX VrefLevel [Byte0]: 52
7855 11:41:05.544607 [Byte1]: 52
7856 11:41:05.549106
7857 11:41:05.549555 Set Vref, RX VrefLevel [Byte0]: 53
7858 11:41:05.552438 [Byte1]: 53
7859 11:41:05.557063
7860 11:41:05.557517 Set Vref, RX VrefLevel [Byte0]: 54
7861 11:41:05.560159 [Byte1]: 54
7862 11:41:05.564389
7863 11:41:05.564877 Set Vref, RX VrefLevel [Byte0]: 55
7864 11:41:05.567497 [Byte1]: 55
7865 11:41:05.572322
7866 11:41:05.572740 Set Vref, RX VrefLevel [Byte0]: 56
7867 11:41:05.575040 [Byte1]: 56
7868 11:41:05.579541
7869 11:41:05.580151 Set Vref, RX VrefLevel [Byte0]: 57
7870 11:41:05.582805 [Byte1]: 57
7871 11:41:05.587014
7872 11:41:05.587435 Set Vref, RX VrefLevel [Byte0]: 58
7873 11:41:05.590484 [Byte1]: 58
7874 11:41:05.595147
7875 11:41:05.595699 Set Vref, RX VrefLevel [Byte0]: 59
7876 11:41:05.598124 [Byte1]: 59
7877 11:41:05.602291
7878 11:41:05.602930 Set Vref, RX VrefLevel [Byte0]: 60
7879 11:41:05.605628 [Byte1]: 60
7880 11:41:05.609969
7881 11:41:05.610459 Set Vref, RX VrefLevel [Byte0]: 61
7882 11:41:05.613243 [Byte1]: 61
7883 11:41:05.618051
7884 11:41:05.618602 Set Vref, RX VrefLevel [Byte0]: 62
7885 11:41:05.620811 [Byte1]: 62
7886 11:41:05.625294
7887 11:41:05.625791 Set Vref, RX VrefLevel [Byte0]: 63
7888 11:41:05.628303 [Byte1]: 63
7889 11:41:05.632631
7890 11:41:05.633051 Set Vref, RX VrefLevel [Byte0]: 64
7891 11:41:05.636394 [Byte1]: 64
7892 11:41:05.640262
7893 11:41:05.640681 Set Vref, RX VrefLevel [Byte0]: 65
7894 11:41:05.643852 [Byte1]: 65
7895 11:41:05.648185
7896 11:41:05.648602 Set Vref, RX VrefLevel [Byte0]: 66
7897 11:41:05.651104 [Byte1]: 66
7898 11:41:05.655670
7899 11:41:05.656132 Set Vref, RX VrefLevel [Byte0]: 67
7900 11:41:05.659182 [Byte1]: 67
7901 11:41:05.663075
7902 11:41:05.663492 Set Vref, RX VrefLevel [Byte0]: 68
7903 11:41:05.666827 [Byte1]: 68
7904 11:41:05.670746
7905 11:41:05.671165 Set Vref, RX VrefLevel [Byte0]: 69
7906 11:41:05.674153 [Byte1]: 69
7907 11:41:05.678616
7908 11:41:05.679035 Set Vref, RX VrefLevel [Byte0]: 70
7909 11:41:05.681980 [Byte1]: 70
7910 11:41:05.686659
7911 11:41:05.687076 Set Vref, RX VrefLevel [Byte0]: 71
7912 11:41:05.689605 [Byte1]: 71
7913 11:41:05.693952
7914 11:41:05.694372 Set Vref, RX VrefLevel [Byte0]: 72
7915 11:41:05.696991 [Byte1]: 72
7916 11:41:05.701550
7917 11:41:05.701971 Set Vref, RX VrefLevel [Byte0]: 73
7918 11:41:05.704404 [Byte1]: 73
7919 11:41:05.709207
7920 11:41:05.709624 Set Vref, RX VrefLevel [Byte0]: 74
7921 11:41:05.712395 [Byte1]: 74
7922 11:41:05.716366
7923 11:41:05.716785 Final RX Vref Byte 0 = 55 to rank0
7924 11:41:05.719763 Final RX Vref Byte 1 = 58 to rank0
7925 11:41:05.722917 Final RX Vref Byte 0 = 55 to rank1
7926 11:41:05.726562 Final RX Vref Byte 1 = 58 to rank1==
7927 11:41:05.729971 Dram Type= 6, Freq= 0, CH_0, rank 0
7928 11:41:05.735999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7929 11:41:05.736472 ==
7930 11:41:05.736809 DQS Delay:
7931 11:41:05.739302 DQS0 = 0, DQS1 = 0
7932 11:41:05.739723 DQM Delay:
7933 11:41:05.742516 DQM0 = 128, DQM1 = 124
7934 11:41:05.742935 DQ Delay:
7935 11:41:05.746302 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7936 11:41:05.749213 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7937 11:41:05.752469 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7938 11:41:05.755917 DQ12 =132, DQ13 =128, DQ14 =134, DQ15 =132
7939 11:41:05.756403
7940 11:41:05.756741
7941 11:41:05.757052
7942 11:41:05.759253 [DramC_TX_OE_Calibration] TA2
7943 11:41:05.762445 Original DQ_B0 (3 6) =30, OEN = 27
7944 11:41:05.765622 Original DQ_B1 (3 6) =30, OEN = 27
7945 11:41:05.769026 24, 0x0, End_B0=24 End_B1=24
7946 11:41:05.772735 25, 0x0, End_B0=25 End_B1=25
7947 11:41:05.773164 26, 0x0, End_B0=26 End_B1=26
7948 11:41:05.776020 27, 0x0, End_B0=27 End_B1=27
7949 11:41:05.778971 28, 0x0, End_B0=28 End_B1=28
7950 11:41:05.782576 29, 0x0, End_B0=29 End_B1=29
7951 11:41:05.782976 30, 0x0, End_B0=30 End_B1=30
7952 11:41:05.785874 31, 0x4141, End_B0=30 End_B1=30
7953 11:41:05.788685 Byte0 end_step=30 best_step=27
7954 11:41:05.791973 Byte1 end_step=30 best_step=27
7955 11:41:05.795305 Byte0 TX OE(2T, 0.5T) = (3, 3)
7956 11:41:05.798751 Byte1 TX OE(2T, 0.5T) = (3, 3)
7957 11:41:05.799235
7958 11:41:05.799567
7959 11:41:05.805408 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7960 11:41:05.808655 CH0 RK0: MR19=303, MR18=1916
7961 11:41:05.815321 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7962 11:41:05.815744
7963 11:41:05.818383 ----->DramcWriteLeveling(PI) begin...
7964 11:41:05.818811 ==
7965 11:41:05.821637 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 11:41:05.824962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 11:41:05.825385 ==
7968 11:41:05.828484 Write leveling (Byte 0): 35 => 35
7969 11:41:05.831617 Write leveling (Byte 1): 28 => 28
7970 11:41:05.835315 DramcWriteLeveling(PI) end<-----
7971 11:41:05.835751
7972 11:41:05.836234 ==
7973 11:41:05.838409 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 11:41:05.844797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 11:41:05.845225 ==
7976 11:41:05.845561 [Gating] SW mode calibration
7977 11:41:05.855072 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7978 11:41:05.857897 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7979 11:41:05.864956 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 11:41:05.867786 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 11:41:05.871382 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7982 11:41:05.877573 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7983 11:41:05.880745 1 4 16 | B1->B0 | 2726 3434 | 1 1 | (1 1) (1 1)
7984 11:41:05.884092 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 11:41:05.891168 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 11:41:05.894405 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 11:41:05.897839 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 11:41:05.904301 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7989 11:41:05.907426 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7990 11:41:05.910907 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
7991 11:41:05.917105 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7992 11:41:05.920522 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7993 11:41:05.924135 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 11:41:05.930116 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 11:41:05.933624 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 11:41:05.936832 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 11:41:05.943308 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7998 11:41:05.946851 1 6 12 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)
7999 11:41:05.950158 1 6 16 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8000 11:41:05.956462 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8001 11:41:05.960119 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 11:41:05.963226 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 11:41:05.969981 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 11:41:05.973468 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8005 11:41:05.976402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8006 11:41:05.983041 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8007 11:41:05.986085 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8008 11:41:05.989440 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8009 11:41:05.995655 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8010 11:41:05.998885 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 11:41:06.002704 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:41:06.008767 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:41:06.012181 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 11:41:06.015499 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 11:41:06.022294 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 11:41:06.025225 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 11:41:06.028663 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 11:41:06.035472 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 11:41:06.038347 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 11:41:06.041962 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8021 11:41:06.048373 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8022 11:41:06.051627 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8023 11:41:06.055207 Total UI for P1: 0, mck2ui 16
8024 11:41:06.058403 best dqsien dly found for B0: ( 1, 9, 6)
8025 11:41:06.061677 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8026 11:41:06.068095 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 11:41:06.071871 Total UI for P1: 0, mck2ui 16
8028 11:41:06.075137 best dqsien dly found for B1: ( 1, 9, 16)
8029 11:41:06.078132 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8030 11:41:06.082076 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8031 11:41:06.082501
8032 11:41:06.084855 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8033 11:41:06.087843 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8034 11:41:06.091077 [Gating] SW calibration Done
8035 11:41:06.091500 ==
8036 11:41:06.094584 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 11:41:06.097980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 11:41:06.098561 ==
8039 11:41:06.101169 RX Vref Scan: 0
8040 11:41:06.101589
8041 11:41:06.104417 RX Vref 0 -> 0, step: 1
8042 11:41:06.104842
8043 11:41:06.105176 RX Delay 0 -> 252, step: 8
8044 11:41:06.110812 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8045 11:41:06.114180 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8046 11:41:06.117642 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8047 11:41:06.121064 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8048 11:41:06.124801 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8049 11:41:06.131061 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8050 11:41:06.133957 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8051 11:41:06.137445 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8052 11:41:06.140500 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8053 11:41:06.143803 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8054 11:41:06.150383 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8055 11:41:06.153692 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8056 11:41:06.156862 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8057 11:41:06.160618 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8058 11:41:06.167072 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8059 11:41:06.170058 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8060 11:41:06.170567 ==
8061 11:41:06.173777 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 11:41:06.176872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 11:41:06.177537 ==
8064 11:41:06.180092 DQS Delay:
8065 11:41:06.180598 DQS0 = 0, DQS1 = 0
8066 11:41:06.181058 DQM Delay:
8067 11:41:06.183430 DQM0 = 131, DQM1 = 128
8068 11:41:06.183917 DQ Delay:
8069 11:41:06.186978 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8070 11:41:06.190110 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8071 11:41:06.193149 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8072 11:41:06.199737 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8073 11:41:06.200242
8074 11:41:06.200583
8075 11:41:06.200912 ==
8076 11:41:06.203389 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 11:41:06.206215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 11:41:06.206715 ==
8079 11:41:06.207167
8080 11:41:06.207605
8081 11:41:06.209700 TX Vref Scan disable
8082 11:41:06.210119 == TX Byte 0 ==
8083 11:41:06.216454 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8084 11:41:06.219578 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8085 11:41:06.223077 == TX Byte 1 ==
8086 11:41:06.226040 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8087 11:41:06.229527 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8088 11:41:06.229950 ==
8089 11:41:06.233131 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 11:41:06.236223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 11:41:06.236648 ==
8092 11:41:06.250949
8093 11:41:06.254508 TX Vref early break, caculate TX vref
8094 11:41:06.258597 TX Vref=16, minBit 3, minWin=22, winSum=375
8095 11:41:06.261163 TX Vref=18, minBit 3, minWin=22, winSum=383
8096 11:41:06.264128 TX Vref=20, minBit 1, minWin=23, winSum=394
8097 11:41:06.267685 TX Vref=22, minBit 0, minWin=24, winSum=401
8098 11:41:06.271056 TX Vref=24, minBit 1, minWin=23, winSum=406
8099 11:41:06.277553 TX Vref=26, minBit 0, minWin=25, winSum=414
8100 11:41:06.280592 TX Vref=28, minBit 0, minWin=24, winSum=417
8101 11:41:06.284325 TX Vref=30, minBit 1, minWin=24, winSum=411
8102 11:41:06.287522 TX Vref=32, minBit 0, minWin=24, winSum=402
8103 11:41:06.291147 TX Vref=34, minBit 1, minWin=23, winSum=395
8104 11:41:06.298055 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8105 11:41:06.298479
8106 11:41:06.300831 Final TX Range 0 Vref 26
8107 11:41:06.301256
8108 11:41:06.301593 ==
8109 11:41:06.304138 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 11:41:06.307214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 11:41:06.307638 ==
8112 11:41:06.307972
8113 11:41:06.308333
8114 11:41:06.310560 TX Vref Scan disable
8115 11:41:06.316934 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8116 11:41:06.317355 == TX Byte 0 ==
8117 11:41:06.320292 u2DelayCellOfst[0]=14 cells (4 PI)
8118 11:41:06.323569 u2DelayCellOfst[1]=17 cells (5 PI)
8119 11:41:06.327157 u2DelayCellOfst[2]=10 cells (3 PI)
8120 11:41:06.330187 u2DelayCellOfst[3]=14 cells (4 PI)
8121 11:41:06.333611 u2DelayCellOfst[4]=10 cells (3 PI)
8122 11:41:06.336956 u2DelayCellOfst[5]=0 cells (0 PI)
8123 11:41:06.340135 u2DelayCellOfst[6]=17 cells (5 PI)
8124 11:41:06.343421 u2DelayCellOfst[7]=17 cells (5 PI)
8125 11:41:06.346259 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8126 11:41:06.349543 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8127 11:41:06.352889 == TX Byte 1 ==
8128 11:41:06.356485 u2DelayCellOfst[8]=0 cells (0 PI)
8129 11:41:06.359718 u2DelayCellOfst[9]=0 cells (0 PI)
8130 11:41:06.362541 u2DelayCellOfst[10]=3 cells (1 PI)
8131 11:41:06.366275 u2DelayCellOfst[11]=3 cells (1 PI)
8132 11:41:06.369566 u2DelayCellOfst[12]=10 cells (3 PI)
8133 11:41:06.372652 u2DelayCellOfst[13]=10 cells (3 PI)
8134 11:41:06.376294 u2DelayCellOfst[14]=14 cells (4 PI)
8135 11:41:06.376719 u2DelayCellOfst[15]=10 cells (3 PI)
8136 11:41:06.382779 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8137 11:41:06.385689 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8138 11:41:06.389524 DramC Write-DBI on
8139 11:41:06.389944 ==
8140 11:41:06.392320 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 11:41:06.395870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 11:41:06.396387 ==
8143 11:41:06.396727
8144 11:41:06.397037
8145 11:41:06.399144 TX Vref Scan disable
8146 11:41:06.399582 == TX Byte 0 ==
8147 11:41:06.405764 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8148 11:41:06.406187 == TX Byte 1 ==
8149 11:41:06.412522 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8150 11:41:06.412949 DramC Write-DBI off
8151 11:41:06.413283
8152 11:41:06.413593 [DATLAT]
8153 11:41:06.415805 Freq=1600, CH0 RK1
8154 11:41:06.416258
8155 11:41:06.416600 DATLAT Default: 0xf
8156 11:41:06.418712 0, 0xFFFF, sum = 0
8157 11:41:06.422021 1, 0xFFFF, sum = 0
8158 11:41:06.422586 2, 0xFFFF, sum = 0
8159 11:41:06.425320 3, 0xFFFF, sum = 0
8160 11:41:06.425752 4, 0xFFFF, sum = 0
8161 11:41:06.428942 5, 0xFFFF, sum = 0
8162 11:41:06.429371 6, 0xFFFF, sum = 0
8163 11:41:06.431661 7, 0xFFFF, sum = 0
8164 11:41:06.432127 8, 0xFFFF, sum = 0
8165 11:41:06.435659 9, 0xFFFF, sum = 0
8166 11:41:06.436126 10, 0xFFFF, sum = 0
8167 11:41:06.438696 11, 0xFFFF, sum = 0
8168 11:41:06.439125 12, 0xFFFF, sum = 0
8169 11:41:06.441917 13, 0xFFFF, sum = 0
8170 11:41:06.442346 14, 0x0, sum = 1
8171 11:41:06.445140 15, 0x0, sum = 2
8172 11:41:06.445569 16, 0x0, sum = 3
8173 11:41:06.448328 17, 0x0, sum = 4
8174 11:41:06.448759 best_step = 15
8175 11:41:06.449090
8176 11:41:06.449399 ==
8177 11:41:06.451730 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 11:41:06.458088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 11:41:06.458511 ==
8180 11:41:06.458848 RX Vref Scan: 0
8181 11:41:06.459159
8182 11:41:06.461354 RX Vref 0 -> 0, step: 1
8183 11:41:06.461776
8184 11:41:06.464922 RX Delay 11 -> 252, step: 4
8185 11:41:06.467991 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8186 11:41:06.471304 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8187 11:41:06.478213 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8188 11:41:06.481703 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8189 11:41:06.484750 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8190 11:41:06.487916 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8191 11:41:06.491191 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8192 11:41:06.494935 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8193 11:41:06.501156 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8194 11:41:06.504554 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8195 11:41:06.507938 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8196 11:41:06.511146 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8197 11:41:06.517643 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8198 11:41:06.521403 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8199 11:41:06.524020 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8200 11:41:06.527184 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8201 11:41:06.527604 ==
8202 11:41:06.530805 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 11:41:06.537220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 11:41:06.537646 ==
8205 11:41:06.537982 DQS Delay:
8206 11:41:06.540939 DQS0 = 0, DQS1 = 0
8207 11:41:06.541360 DQM Delay:
8208 11:41:06.544108 DQM0 = 128, DQM1 = 124
8209 11:41:06.544600 DQ Delay:
8210 11:41:06.547032 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8211 11:41:06.550448 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8212 11:41:06.553984 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8213 11:41:06.557227 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8214 11:41:06.557648
8215 11:41:06.557980
8216 11:41:06.558287
8217 11:41:06.560517 [DramC_TX_OE_Calibration] TA2
8218 11:41:06.563693 Original DQ_B0 (3 6) =30, OEN = 27
8219 11:41:06.566846 Original DQ_B1 (3 6) =30, OEN = 27
8220 11:41:06.570201 24, 0x0, End_B0=24 End_B1=24
8221 11:41:06.573755 25, 0x0, End_B0=25 End_B1=25
8222 11:41:06.574190 26, 0x0, End_B0=26 End_B1=26
8223 11:41:06.576833 27, 0x0, End_B0=27 End_B1=27
8224 11:41:06.580145 28, 0x0, End_B0=28 End_B1=28
8225 11:41:06.583073 29, 0x0, End_B0=29 End_B1=29
8226 11:41:06.586631 30, 0x0, End_B0=30 End_B1=30
8227 11:41:06.587062 31, 0x4545, End_B0=30 End_B1=30
8228 11:41:06.589867 Byte0 end_step=30 best_step=27
8229 11:41:06.593034 Byte1 end_step=30 best_step=27
8230 11:41:06.596828 Byte0 TX OE(2T, 0.5T) = (3, 3)
8231 11:41:06.600250 Byte1 TX OE(2T, 0.5T) = (3, 3)
8232 11:41:06.600776
8233 11:41:06.601360
8234 11:41:06.606538 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8235 11:41:06.609789 CH0 RK1: MR19=303, MR18=1412
8236 11:41:06.616348 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8237 11:41:06.620104 [RxdqsGatingPostProcess] freq 1600
8238 11:41:06.626337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8239 11:41:06.626761 best DQS0 dly(2T, 0.5T) = (1, 1)
8240 11:41:06.629757 best DQS1 dly(2T, 0.5T) = (1, 1)
8241 11:41:06.632684 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8242 11:41:06.636293 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8243 11:41:06.639316 best DQS0 dly(2T, 0.5T) = (1, 1)
8244 11:41:06.642708 best DQS1 dly(2T, 0.5T) = (1, 1)
8245 11:41:06.645942 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8246 11:41:06.649756 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8247 11:41:06.652574 Pre-setting of DQS Precalculation
8248 11:41:06.656025 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8249 11:41:06.659132 ==
8250 11:41:06.662527 Dram Type= 6, Freq= 0, CH_1, rank 0
8251 11:41:06.665873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 11:41:06.666300 ==
8253 11:41:06.672028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8254 11:41:06.675652 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8255 11:41:06.678788 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8256 11:41:06.685293 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8257 11:41:06.693638 [CA 0] Center 42 (12~72) winsize 61
8258 11:41:06.696824 [CA 1] Center 42 (12~72) winsize 61
8259 11:41:06.700415 [CA 2] Center 38 (9~68) winsize 60
8260 11:41:06.703651 [CA 3] Center 37 (8~67) winsize 60
8261 11:41:06.706840 [CA 4] Center 38 (8~68) winsize 61
8262 11:41:06.710517 [CA 5] Center 37 (8~67) winsize 60
8263 11:41:06.710947
8264 11:41:06.713554 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8265 11:41:06.713982
8266 11:41:06.719763 [CATrainingPosCal] consider 1 rank data
8267 11:41:06.720239 u2DelayCellTimex100 = 275/100 ps
8268 11:41:06.726876 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8269 11:41:06.729816 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8270 11:41:06.733181 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8271 11:41:06.736282 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8272 11:41:06.740141 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8273 11:41:06.743257 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8274 11:41:06.743683
8275 11:41:06.746472 CA PerBit enable=1, Macro0, CA PI delay=37
8276 11:41:06.746897
8277 11:41:06.750077 [CBTSetCACLKResult] CA Dly = 37
8278 11:41:06.752806 CS Dly: 8 (0~39)
8279 11:41:06.756485 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8280 11:41:06.759353 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8281 11:41:06.759776 ==
8282 11:41:06.763102 Dram Type= 6, Freq= 0, CH_1, rank 1
8283 11:41:06.769238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8284 11:41:06.769662 ==
8285 11:41:06.772862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8286 11:41:06.779015 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8287 11:41:06.782348 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8288 11:41:06.788706 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8289 11:41:06.796834 [CA 0] Center 42 (12~72) winsize 61
8290 11:41:06.800425 [CA 1] Center 42 (13~72) winsize 60
8291 11:41:06.803384 [CA 2] Center 38 (8~68) winsize 61
8292 11:41:06.806684 [CA 3] Center 37 (7~67) winsize 61
8293 11:41:06.809700 [CA 4] Center 37 (8~67) winsize 60
8294 11:41:06.813448 [CA 5] Center 37 (7~67) winsize 61
8295 11:41:06.814023
8296 11:41:06.816662 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8297 11:41:06.817063
8298 11:41:06.819863 [CATrainingPosCal] consider 2 rank data
8299 11:41:06.823258 u2DelayCellTimex100 = 275/100 ps
8300 11:41:06.826805 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8301 11:41:06.833341 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8302 11:41:06.836568 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8303 11:41:06.839759 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8304 11:41:06.843019 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8305 11:41:06.846387 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8306 11:41:06.846973
8307 11:41:06.849440 CA PerBit enable=1, Macro0, CA PI delay=37
8308 11:41:06.850050
8309 11:41:06.853212 [CBTSetCACLKResult] CA Dly = 37
8310 11:41:06.856275 CS Dly: 9 (0~42)
8311 11:41:06.859060 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8312 11:41:06.862695 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8313 11:41:06.863285
8314 11:41:06.866205 ----->DramcWriteLeveling(PI) begin...
8315 11:41:06.866787 ==
8316 11:41:06.869209 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 11:41:06.876151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 11:41:06.876570 ==
8319 11:41:06.878915 Write leveling (Byte 0): 25 => 25
8320 11:41:06.882734 Write leveling (Byte 1): 27 => 27
8321 11:41:06.883046 DramcWriteLeveling(PI) end<-----
8322 11:41:06.883254
8323 11:41:06.885869 ==
8324 11:41:06.888998 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 11:41:06.892450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 11:41:06.892623 ==
8327 11:41:06.895769 [Gating] SW mode calibration
8328 11:41:06.902144 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8329 11:41:06.905561 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8330 11:41:06.912315 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 11:41:06.915401 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 11:41:06.918580 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 11:41:06.925416 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
8334 11:41:06.928939 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 11:41:06.932151 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 11:41:06.938446 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 11:41:06.942190 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 11:41:06.945416 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 11:41:06.952127 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 11:41:06.955097 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 11:41:06.958260 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
8342 11:41:06.964963 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8343 11:41:06.968115 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 11:41:06.971284 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 11:41:06.977983 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 11:41:06.981361 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 11:41:06.984943 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 11:41:06.991368 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8349 11:41:06.994891 1 6 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8350 11:41:06.998089 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 11:41:07.004792 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 11:41:07.007670 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 11:41:07.011083 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 11:41:07.017873 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 11:41:07.021164 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 11:41:07.024154 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 11:41:07.031034 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8358 11:41:07.034393 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8359 11:41:07.040610 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:41:07.043609 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:41:07.047172 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:41:07.054229 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:41:07.056909 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 11:41:07.059995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 11:41:07.066919 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 11:41:07.069811 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 11:41:07.072951 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 11:41:07.079777 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 11:41:07.082819 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 11:41:07.086905 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 11:41:07.093413 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 11:41:07.096535 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:41:07.099624 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8374 11:41:07.106329 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 11:41:07.106883 Total UI for P1: 0, mck2ui 16
8376 11:41:07.112975 best dqsien dly found for B0: ( 1, 9, 12)
8377 11:41:07.113467 Total UI for P1: 0, mck2ui 16
8378 11:41:07.119395 best dqsien dly found for B1: ( 1, 9, 12)
8379 11:41:07.122717 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8380 11:41:07.126057 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8381 11:41:07.126531
8382 11:41:07.128977 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8383 11:41:07.132565 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8384 11:41:07.135938 [Gating] SW calibration Done
8385 11:41:07.136536 ==
8386 11:41:07.139061 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 11:41:07.142864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 11:41:07.143347 ==
8389 11:41:07.145516 RX Vref Scan: 0
8390 11:41:07.146044
8391 11:41:07.146428 RX Vref 0 -> 0, step: 1
8392 11:41:07.149422
8393 11:41:07.149888 RX Delay 0 -> 252, step: 8
8394 11:41:07.155465 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8395 11:41:07.158830 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8396 11:41:07.161849 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8397 11:41:07.165546 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8398 11:41:07.168708 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8399 11:41:07.175337 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8400 11:41:07.178360 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8401 11:41:07.181792 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8402 11:41:07.185074 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8403 11:41:07.188405 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8404 11:41:07.194864 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8405 11:41:07.198323 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8406 11:41:07.201519 iDelay=200, Bit 12, Center 143 (96 ~ 191) 96
8407 11:41:07.204941 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8408 11:41:07.208305 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8409 11:41:07.215005 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8410 11:41:07.215678 ==
8411 11:41:07.218111 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 11:41:07.221385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 11:41:07.221980 ==
8414 11:41:07.222510 DQS Delay:
8415 11:41:07.224568 DQS0 = 0, DQS1 = 0
8416 11:41:07.225030 DQM Delay:
8417 11:41:07.227841 DQM0 = 135, DQM1 = 132
8418 11:41:07.228383 DQ Delay:
8419 11:41:07.231003 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8420 11:41:07.234133 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8421 11:41:07.237572 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8422 11:41:07.244405 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8423 11:41:07.244998
8424 11:41:07.245512
8425 11:41:07.245932 ==
8426 11:41:07.247649 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 11:41:07.250919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 11:41:07.251382 ==
8429 11:41:07.251794
8430 11:41:07.252285
8431 11:41:07.254126 TX Vref Scan disable
8432 11:41:07.254596 == TX Byte 0 ==
8433 11:41:07.260436 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8434 11:41:07.263976 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8435 11:41:07.267193 == TX Byte 1 ==
8436 11:41:07.270043 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8437 11:41:07.273657 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8438 11:41:07.274054 ==
8439 11:41:07.276911 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 11:41:07.279890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 11:41:07.283307 ==
8442 11:41:07.295315
8443 11:41:07.298544 TX Vref early break, caculate TX vref
8444 11:41:07.301742 TX Vref=16, minBit 8, minWin=21, winSum=370
8445 11:41:07.305358 TX Vref=18, minBit 8, minWin=22, winSum=376
8446 11:41:07.308233 TX Vref=20, minBit 8, minWin=23, winSum=385
8447 11:41:07.312201 TX Vref=22, minBit 8, minWin=23, winSum=395
8448 11:41:07.315064 TX Vref=24, minBit 8, minWin=23, winSum=405
8449 11:41:07.321660 TX Vref=26, minBit 3, minWin=25, winSum=415
8450 11:41:07.325673 TX Vref=28, minBit 0, minWin=25, winSum=415
8451 11:41:07.328523 TX Vref=30, minBit 0, minWin=25, winSum=412
8452 11:41:07.331546 TX Vref=32, minBit 9, minWin=24, winSum=408
8453 11:41:07.335221 TX Vref=34, minBit 9, minWin=23, winSum=397
8454 11:41:07.338614 TX Vref=36, minBit 9, minWin=22, winSum=387
8455 11:41:07.344705 [TxChooseVref] Worse bit 3, Min win 25, Win sum 415, Final Vref 26
8456 11:41:07.345230
8457 11:41:07.348155 Final TX Range 0 Vref 26
8458 11:41:07.348635
8459 11:41:07.348976 ==
8460 11:41:07.351254 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 11:41:07.355257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 11:41:07.355685 ==
8463 11:41:07.358244
8464 11:41:07.358668
8465 11:41:07.359004 TX Vref Scan disable
8466 11:41:07.365034 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8467 11:41:07.365457 == TX Byte 0 ==
8468 11:41:07.367980 u2DelayCellOfst[0]=14 cells (4 PI)
8469 11:41:07.371219 u2DelayCellOfst[1]=10 cells (3 PI)
8470 11:41:07.374323 u2DelayCellOfst[2]=0 cells (0 PI)
8471 11:41:07.377920 u2DelayCellOfst[3]=7 cells (2 PI)
8472 11:41:07.381441 u2DelayCellOfst[4]=10 cells (3 PI)
8473 11:41:07.384016 u2DelayCellOfst[5]=17 cells (5 PI)
8474 11:41:07.387429 u2DelayCellOfst[6]=14 cells (4 PI)
8475 11:41:07.390652 u2DelayCellOfst[7]=7 cells (2 PI)
8476 11:41:07.394086 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8477 11:41:07.397449 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8478 11:41:07.400974 == TX Byte 1 ==
8479 11:41:07.404019 u2DelayCellOfst[8]=0 cells (0 PI)
8480 11:41:07.407764 u2DelayCellOfst[9]=3 cells (1 PI)
8481 11:41:07.411036 u2DelayCellOfst[10]=10 cells (3 PI)
8482 11:41:07.413687 u2DelayCellOfst[11]=7 cells (2 PI)
8483 11:41:07.417388 u2DelayCellOfst[12]=14 cells (4 PI)
8484 11:41:07.420638 u2DelayCellOfst[13]=14 cells (4 PI)
8485 11:41:07.423847 u2DelayCellOfst[14]=17 cells (5 PI)
8486 11:41:07.427127 u2DelayCellOfst[15]=17 cells (5 PI)
8487 11:41:07.430257 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8488 11:41:07.433619 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8489 11:41:07.436634 DramC Write-DBI on
8490 11:41:07.437124 ==
8491 11:41:07.440257 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 11:41:07.443348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 11:41:07.443961 ==
8494 11:41:07.444415
8495 11:41:07.444770
8496 11:41:07.446489 TX Vref Scan disable
8497 11:41:07.450203 == TX Byte 0 ==
8498 11:41:07.453203 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8499 11:41:07.453772 == TX Byte 1 ==
8500 11:41:07.459537 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8501 11:41:07.460151 DramC Write-DBI off
8502 11:41:07.460611
8503 11:41:07.461112 [DATLAT]
8504 11:41:07.463290 Freq=1600, CH1 RK0
8505 11:41:07.463931
8506 11:41:07.466321 DATLAT Default: 0xf
8507 11:41:07.466885 0, 0xFFFF, sum = 0
8508 11:41:07.469489 1, 0xFFFF, sum = 0
8509 11:41:07.469886 2, 0xFFFF, sum = 0
8510 11:41:07.472690 3, 0xFFFF, sum = 0
8511 11:41:07.473310 4, 0xFFFF, sum = 0
8512 11:41:07.476349 5, 0xFFFF, sum = 0
8513 11:41:07.476800 6, 0xFFFF, sum = 0
8514 11:41:07.479298 7, 0xFFFF, sum = 0
8515 11:41:07.479773 8, 0xFFFF, sum = 0
8516 11:41:07.483106 9, 0xFFFF, sum = 0
8517 11:41:07.483675 10, 0xFFFF, sum = 0
8518 11:41:07.486298 11, 0xFFFF, sum = 0
8519 11:41:07.486891 12, 0xFFFF, sum = 0
8520 11:41:07.489550 13, 0xFFFF, sum = 0
8521 11:41:07.492972 14, 0x0, sum = 1
8522 11:41:07.493428 15, 0x0, sum = 2
8523 11:41:07.493787 16, 0x0, sum = 3
8524 11:41:07.496312 17, 0x0, sum = 4
8525 11:41:07.496749 best_step = 15
8526 11:41:07.497120
8527 11:41:07.497531 ==
8528 11:41:07.499584 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 11:41:07.505984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 11:41:07.506419 ==
8531 11:41:07.506799 RX Vref Scan: 1
8532 11:41:07.507161
8533 11:41:07.509366 Set Vref Range= 24 -> 127
8534 11:41:07.509865
8535 11:41:07.512741 RX Vref 24 -> 127, step: 1
8536 11:41:07.513180
8537 11:41:07.515843 RX Delay 19 -> 252, step: 4
8538 11:41:07.516338
8539 11:41:07.519065 Set Vref, RX VrefLevel [Byte0]: 24
8540 11:41:07.522083 [Byte1]: 24
8541 11:41:07.522166
8542 11:41:07.525533 Set Vref, RX VrefLevel [Byte0]: 25
8543 11:41:07.528960 [Byte1]: 25
8544 11:41:07.529085
8545 11:41:07.531710 Set Vref, RX VrefLevel [Byte0]: 26
8546 11:41:07.535221 [Byte1]: 26
8547 11:41:07.538398
8548 11:41:07.538500 Set Vref, RX VrefLevel [Byte0]: 27
8549 11:41:07.542066 [Byte1]: 27
8550 11:41:07.546257
8551 11:41:07.546364 Set Vref, RX VrefLevel [Byte0]: 28
8552 11:41:07.549690 [Byte1]: 28
8553 11:41:07.553839
8554 11:41:07.553951 Set Vref, RX VrefLevel [Byte0]: 29
8555 11:41:07.557146 [Byte1]: 29
8556 11:41:07.561305
8557 11:41:07.561387 Set Vref, RX VrefLevel [Byte0]: 30
8558 11:41:07.564978 [Byte1]: 30
8559 11:41:07.568835
8560 11:41:07.568943 Set Vref, RX VrefLevel [Byte0]: 31
8561 11:41:07.572317 [Byte1]: 31
8562 11:41:07.576566
8563 11:41:07.576648 Set Vref, RX VrefLevel [Byte0]: 32
8564 11:41:07.579465 [Byte1]: 32
8565 11:41:07.584149
8566 11:41:07.584252 Set Vref, RX VrefLevel [Byte0]: 33
8567 11:41:07.587514 [Byte1]: 33
8568 11:41:07.591467
8569 11:41:07.591574 Set Vref, RX VrefLevel [Byte0]: 34
8570 11:41:07.594872 [Byte1]: 34
8571 11:41:07.599032
8572 11:41:07.599139 Set Vref, RX VrefLevel [Byte0]: 35
8573 11:41:07.602615 [Byte1]: 35
8574 11:41:07.606665
8575 11:41:07.606763 Set Vref, RX VrefLevel [Byte0]: 36
8576 11:41:07.610173 [Byte1]: 36
8577 11:41:07.614530
8578 11:41:07.614632 Set Vref, RX VrefLevel [Byte0]: 37
8579 11:41:07.618192 [Byte1]: 37
8580 11:41:07.621812
8581 11:41:07.621895 Set Vref, RX VrefLevel [Byte0]: 38
8582 11:41:07.625394 [Byte1]: 38
8583 11:41:07.629661
8584 11:41:07.629743 Set Vref, RX VrefLevel [Byte0]: 39
8585 11:41:07.632963 [Byte1]: 39
8586 11:41:07.636983
8587 11:41:07.637065 Set Vref, RX VrefLevel [Byte0]: 40
8588 11:41:07.640318 [Byte1]: 40
8589 11:41:07.644601
8590 11:41:07.644706 Set Vref, RX VrefLevel [Byte0]: 41
8591 11:41:07.647822 [Byte1]: 41
8592 11:41:07.651910
8593 11:41:07.651992 Set Vref, RX VrefLevel [Byte0]: 42
8594 11:41:07.655890 [Byte1]: 42
8595 11:41:07.659807
8596 11:41:07.659914 Set Vref, RX VrefLevel [Byte0]: 43
8597 11:41:07.662850 [Byte1]: 43
8598 11:41:07.667445
8599 11:41:07.667528 Set Vref, RX VrefLevel [Byte0]: 44
8600 11:41:07.671164 [Byte1]: 44
8601 11:41:07.675020
8602 11:41:07.675102 Set Vref, RX VrefLevel [Byte0]: 45
8603 11:41:07.678277 [Byte1]: 45
8604 11:41:07.682301
8605 11:41:07.682386 Set Vref, RX VrefLevel [Byte0]: 46
8606 11:41:07.685613 [Byte1]: 46
8607 11:41:07.690412
8608 11:41:07.690494 Set Vref, RX VrefLevel [Byte0]: 47
8609 11:41:07.693536 [Byte1]: 47
8610 11:41:07.697483
8611 11:41:07.697565 Set Vref, RX VrefLevel [Byte0]: 48
8612 11:41:07.700730 [Byte1]: 48
8613 11:41:07.705433
8614 11:41:07.705515 Set Vref, RX VrefLevel [Byte0]: 49
8615 11:41:07.708254 [Byte1]: 49
8616 11:41:07.712603
8617 11:41:07.712685 Set Vref, RX VrefLevel [Byte0]: 50
8618 11:41:07.715932 [Byte1]: 50
8619 11:41:07.720615
8620 11:41:07.720698 Set Vref, RX VrefLevel [Byte0]: 51
8621 11:41:07.723847 [Byte1]: 51
8622 11:41:07.727612
8623 11:41:07.730768 Set Vref, RX VrefLevel [Byte0]: 52
8624 11:41:07.734446 [Byte1]: 52
8625 11:41:07.734529
8626 11:41:07.737521 Set Vref, RX VrefLevel [Byte0]: 53
8627 11:41:07.740796 [Byte1]: 53
8628 11:41:07.740879
8629 11:41:07.744348 Set Vref, RX VrefLevel [Byte0]: 54
8630 11:41:07.747417 [Byte1]: 54
8631 11:41:07.750655
8632 11:41:07.750793 Set Vref, RX VrefLevel [Byte0]: 55
8633 11:41:07.754124 [Byte1]: 55
8634 11:41:07.758130
8635 11:41:07.758213 Set Vref, RX VrefLevel [Byte0]: 56
8636 11:41:07.761612 [Byte1]: 56
8637 11:41:07.765753
8638 11:41:07.765835 Set Vref, RX VrefLevel [Byte0]: 57
8639 11:41:07.768964 [Byte1]: 57
8640 11:41:07.773291
8641 11:41:07.773373 Set Vref, RX VrefLevel [Byte0]: 58
8642 11:41:07.776386 [Byte1]: 58
8643 11:41:07.781182
8644 11:41:07.781265 Set Vref, RX VrefLevel [Byte0]: 59
8645 11:41:07.784068 [Byte1]: 59
8646 11:41:07.788415
8647 11:41:07.788518 Set Vref, RX VrefLevel [Byte0]: 60
8648 11:41:07.791570 [Byte1]: 60
8649 11:41:07.795972
8650 11:41:07.796107 Set Vref, RX VrefLevel [Byte0]: 61
8651 11:41:07.799100 [Byte1]: 61
8652 11:41:07.803567
8653 11:41:07.803649 Set Vref, RX VrefLevel [Byte0]: 62
8654 11:41:07.806972 [Byte1]: 62
8655 11:41:07.811071
8656 11:41:07.811153 Set Vref, RX VrefLevel [Byte0]: 63
8657 11:41:07.814451 [Byte1]: 63
8658 11:41:07.819219
8659 11:41:07.819327 Set Vref, RX VrefLevel [Byte0]: 64
8660 11:41:07.822291 [Byte1]: 64
8661 11:41:07.826484
8662 11:41:07.826581 Set Vref, RX VrefLevel [Byte0]: 65
8663 11:41:07.829386 [Byte1]: 65
8664 11:41:07.833911
8665 11:41:07.833993 Set Vref, RX VrefLevel [Byte0]: 66
8666 11:41:07.837193 [Byte1]: 66
8667 11:41:07.841826
8668 11:41:07.841919 Set Vref, RX VrefLevel [Byte0]: 67
8669 11:41:07.844647 [Byte1]: 67
8670 11:41:07.849039
8671 11:41:07.849121 Set Vref, RX VrefLevel [Byte0]: 68
8672 11:41:07.852517 [Byte1]: 68
8673 11:41:07.856941
8674 11:41:07.857049 Set Vref, RX VrefLevel [Byte0]: 69
8675 11:41:07.859703 [Byte1]: 69
8676 11:41:07.863952
8677 11:41:07.864080 Set Vref, RX VrefLevel [Byte0]: 70
8678 11:41:07.867898 [Byte1]: 70
8679 11:41:07.871655
8680 11:41:07.871737 Final RX Vref Byte 0 = 63 to rank0
8681 11:41:07.874917 Final RX Vref Byte 1 = 61 to rank0
8682 11:41:07.878431 Final RX Vref Byte 0 = 63 to rank1
8683 11:41:07.881864 Final RX Vref Byte 1 = 61 to rank1==
8684 11:41:07.884843 Dram Type= 6, Freq= 0, CH_1, rank 0
8685 11:41:07.891668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8686 11:41:07.891798 ==
8687 11:41:07.891905 DQS Delay:
8688 11:41:07.894881 DQS0 = 0, DQS1 = 0
8689 11:41:07.894976 DQM Delay:
8690 11:41:07.895042 DQM0 = 133, DQM1 = 130
8691 11:41:07.898070 DQ Delay:
8692 11:41:07.901341 DQ0 =140, DQ1 =132, DQ2 =118, DQ3 =132
8693 11:41:07.904674 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =130
8694 11:41:07.907951 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8695 11:41:07.911441 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8696 11:41:07.911598
8697 11:41:07.911678
8698 11:41:07.911768
8699 11:41:07.914380 [DramC_TX_OE_Calibration] TA2
8700 11:41:07.917581 Original DQ_B0 (3 6) =30, OEN = 27
8701 11:41:07.921177 Original DQ_B1 (3 6) =30, OEN = 27
8702 11:41:07.924865 24, 0x0, End_B0=24 End_B1=24
8703 11:41:07.924948 25, 0x0, End_B0=25 End_B1=25
8704 11:41:07.927483 26, 0x0, End_B0=26 End_B1=26
8705 11:41:07.931230 27, 0x0, End_B0=27 End_B1=27
8706 11:41:07.934328 28, 0x0, End_B0=28 End_B1=28
8707 11:41:07.937385 29, 0x0, End_B0=29 End_B1=29
8708 11:41:07.937468 30, 0x0, End_B0=30 End_B1=30
8709 11:41:07.941146 31, 0x4141, End_B0=30 End_B1=30
8710 11:41:07.944522 Byte0 end_step=30 best_step=27
8711 11:41:07.947383 Byte1 end_step=30 best_step=27
8712 11:41:07.951082 Byte0 TX OE(2T, 0.5T) = (3, 3)
8713 11:41:07.954068 Byte1 TX OE(2T, 0.5T) = (3, 3)
8714 11:41:07.954150
8715 11:41:07.954215
8716 11:41:07.960615 [DQSOSCAuto] RK0, (LSB)MR18= 0xb14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8717 11:41:07.963964 CH1 RK0: MR19=303, MR18=B14
8718 11:41:07.970588 CH1_RK0: MR19=0x303, MR18=0xB14, DQSOSC=399, MR23=63, INC=23, DEC=15
8719 11:41:07.970671
8720 11:41:07.973667 ----->DramcWriteLeveling(PI) begin...
8721 11:41:07.973754 ==
8722 11:41:07.977320 Dram Type= 6, Freq= 0, CH_1, rank 1
8723 11:41:07.980584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 11:41:07.980667 ==
8725 11:41:07.983702 Write leveling (Byte 0): 25 => 25
8726 11:41:07.987286 Write leveling (Byte 1): 27 => 27
8727 11:41:07.990741 DramcWriteLeveling(PI) end<-----
8728 11:41:07.990826
8729 11:41:07.990897 ==
8730 11:41:07.993862 Dram Type= 6, Freq= 0, CH_1, rank 1
8731 11:41:07.997122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 11:41:07.999963 ==
8733 11:41:08.000053 [Gating] SW mode calibration
8734 11:41:08.010111 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8735 11:41:08.013131 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8736 11:41:08.016599 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 11:41:08.023209 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 11:41:08.026524 1 4 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8739 11:41:08.029883 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8740 11:41:08.036480 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 11:41:08.039757 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 11:41:08.043094 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 11:41:08.049424 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 11:41:08.053036 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 11:41:08.056340 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8746 11:41:08.062768 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8747 11:41:08.065882 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8748 11:41:08.069027 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 11:41:08.075892 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 11:41:08.078772 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 11:41:08.082320 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 11:41:08.088775 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 11:41:08.092248 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8754 11:41:08.095309 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8755 11:41:08.101816 1 6 12 | B1->B0 | 2b2a 4646 | 1 0 | (0 0) (0 0)
8756 11:41:08.105196 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 11:41:08.111530 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 11:41:08.115525 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 11:41:08.118465 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 11:41:08.121941 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 11:41:08.128281 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 11:41:08.131470 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8763 11:41:08.134768 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8764 11:41:08.141763 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8765 11:41:08.144842 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 11:41:08.147900 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 11:41:08.154400 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 11:41:08.158077 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 11:41:08.164595 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 11:41:08.167908 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 11:41:08.171119 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 11:41:08.175308 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 11:41:08.181287 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 11:41:08.184239 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 11:41:08.191008 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 11:41:08.194032 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 11:41:08.197838 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8778 11:41:08.204271 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8779 11:41:08.207897 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8780 11:41:08.210854 Total UI for P1: 0, mck2ui 16
8781 11:41:08.214208 best dqsien dly found for B0: ( 1, 9, 6)
8782 11:41:08.217425 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 11:41:08.220570 Total UI for P1: 0, mck2ui 16
8784 11:41:08.223789 best dqsien dly found for B1: ( 1, 9, 10)
8785 11:41:08.227171 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8786 11:41:08.230943 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8787 11:41:08.231049
8788 11:41:08.234093 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8789 11:41:08.240300 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8790 11:41:08.240382 [Gating] SW calibration Done
8791 11:41:08.240448 ==
8792 11:41:08.243602 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 11:41:08.250157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 11:41:08.250234 ==
8795 11:41:08.250306 RX Vref Scan: 0
8796 11:41:08.250367
8797 11:41:08.253679 RX Vref 0 -> 0, step: 1
8798 11:41:08.253763
8799 11:41:08.256661 RX Delay 0 -> 252, step: 8
8800 11:41:08.260024 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8801 11:41:08.263302 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8802 11:41:08.266939 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8803 11:41:08.273046 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8804 11:41:08.276465 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8805 11:41:08.279955 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8806 11:41:08.283107 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8807 11:41:08.286757 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8808 11:41:08.292995 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8809 11:41:08.296267 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8810 11:41:08.299417 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8811 11:41:08.302407 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8812 11:41:08.309224 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8813 11:41:08.312872 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8814 11:41:08.315903 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8815 11:41:08.319130 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8816 11:41:08.319214 ==
8817 11:41:08.322567 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 11:41:08.328843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 11:41:08.328953 ==
8820 11:41:08.329054 DQS Delay:
8821 11:41:08.331995 DQS0 = 0, DQS1 = 0
8822 11:41:08.332145 DQM Delay:
8823 11:41:08.335643 DQM0 = 135, DQM1 = 129
8824 11:41:08.335759 DQ Delay:
8825 11:41:08.338707 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8826 11:41:08.341917 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8827 11:41:08.345090 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8828 11:41:08.348606 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =135
8829 11:41:08.348723
8830 11:41:08.348849
8831 11:41:08.348983 ==
8832 11:41:08.351734 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 11:41:08.358411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 11:41:08.358525 ==
8835 11:41:08.358621
8836 11:41:08.358711
8837 11:41:08.358818 TX Vref Scan disable
8838 11:41:08.361968 == TX Byte 0 ==
8839 11:41:08.365372 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8840 11:41:08.371498 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8841 11:41:08.371610 == TX Byte 1 ==
8842 11:41:08.375047 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8843 11:41:08.381700 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8844 11:41:08.381813 ==
8845 11:41:08.384924 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 11:41:08.388194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 11:41:08.388304 ==
8848 11:41:08.401786
8849 11:41:08.404990 TX Vref early break, caculate TX vref
8850 11:41:08.408198 TX Vref=16, minBit 9, minWin=22, winSum=376
8851 11:41:08.411659 TX Vref=18, minBit 9, minWin=22, winSum=385
8852 11:41:08.415265 TX Vref=20, minBit 9, minWin=22, winSum=390
8853 11:41:08.418752 TX Vref=22, minBit 9, minWin=24, winSum=401
8854 11:41:08.421951 TX Vref=24, minBit 8, minWin=24, winSum=404
8855 11:41:08.428281 TX Vref=26, minBit 9, minWin=24, winSum=414
8856 11:41:08.431035 TX Vref=28, minBit 9, minWin=25, winSum=418
8857 11:41:08.434698 TX Vref=30, minBit 9, minWin=24, winSum=416
8858 11:41:08.437804 TX Vref=32, minBit 8, minWin=24, winSum=410
8859 11:41:08.440898 TX Vref=34, minBit 9, minWin=23, winSum=403
8860 11:41:08.447727 TX Vref=36, minBit 8, minWin=23, winSum=396
8861 11:41:08.451161 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 28
8862 11:41:08.451275
8863 11:41:08.454560 Final TX Range 0 Vref 28
8864 11:41:08.454656
8865 11:41:08.454749 ==
8866 11:41:08.458064 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 11:41:08.460794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 11:41:08.464193 ==
8869 11:41:08.464275
8870 11:41:08.464339
8871 11:41:08.464400 TX Vref Scan disable
8872 11:41:08.470701 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8873 11:41:08.470784 == TX Byte 0 ==
8874 11:41:08.474211 u2DelayCellOfst[0]=14 cells (4 PI)
8875 11:41:08.477626 u2DelayCellOfst[1]=7 cells (2 PI)
8876 11:41:08.480642 u2DelayCellOfst[2]=0 cells (0 PI)
8877 11:41:08.484640 u2DelayCellOfst[3]=7 cells (2 PI)
8878 11:41:08.487685 u2DelayCellOfst[4]=7 cells (2 PI)
8879 11:41:08.490650 u2DelayCellOfst[5]=14 cells (4 PI)
8880 11:41:08.494229 u2DelayCellOfst[6]=17 cells (5 PI)
8881 11:41:08.497393 u2DelayCellOfst[7]=7 cells (2 PI)
8882 11:41:08.500734 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8883 11:41:08.504306 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8884 11:41:08.507309 == TX Byte 1 ==
8885 11:41:08.510565 u2DelayCellOfst[8]=0 cells (0 PI)
8886 11:41:08.514218 u2DelayCellOfst[9]=3 cells (1 PI)
8887 11:41:08.517429 u2DelayCellOfst[10]=10 cells (3 PI)
8888 11:41:08.520329 u2DelayCellOfst[11]=7 cells (2 PI)
8889 11:41:08.523810 u2DelayCellOfst[12]=14 cells (4 PI)
8890 11:41:08.523884 u2DelayCellOfst[13]=14 cells (4 PI)
8891 11:41:08.527292 u2DelayCellOfst[14]=17 cells (5 PI)
8892 11:41:08.530546 u2DelayCellOfst[15]=17 cells (5 PI)
8893 11:41:08.536939 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8894 11:41:08.540269 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8895 11:41:08.543521 DramC Write-DBI on
8896 11:41:08.543620 ==
8897 11:41:08.546509 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 11:41:08.549931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 11:41:08.550013 ==
8900 11:41:08.550078
8901 11:41:08.550139
8902 11:41:08.553455 TX Vref Scan disable
8903 11:41:08.553538 == TX Byte 0 ==
8904 11:41:08.559954 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8905 11:41:08.560099 == TX Byte 1 ==
8906 11:41:08.563257 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8907 11:41:08.566481 DramC Write-DBI off
8908 11:41:08.566563
8909 11:41:08.566629 [DATLAT]
8910 11:41:08.569821 Freq=1600, CH1 RK1
8911 11:41:08.569903
8912 11:41:08.569967 DATLAT Default: 0xf
8913 11:41:08.572872 0, 0xFFFF, sum = 0
8914 11:41:08.572956 1, 0xFFFF, sum = 0
8915 11:41:08.576358 2, 0xFFFF, sum = 0
8916 11:41:08.579881 3, 0xFFFF, sum = 0
8917 11:41:08.579992 4, 0xFFFF, sum = 0
8918 11:41:08.583427 5, 0xFFFF, sum = 0
8919 11:41:08.583510 6, 0xFFFF, sum = 0
8920 11:41:08.586346 7, 0xFFFF, sum = 0
8921 11:41:08.586429 8, 0xFFFF, sum = 0
8922 11:41:08.589258 9, 0xFFFF, sum = 0
8923 11:41:08.589341 10, 0xFFFF, sum = 0
8924 11:41:08.593003 11, 0xFFFF, sum = 0
8925 11:41:08.593086 12, 0xFFFF, sum = 0
8926 11:41:08.596214 13, 0xFFFF, sum = 0
8927 11:41:08.596297 14, 0x0, sum = 1
8928 11:41:08.599526 15, 0x0, sum = 2
8929 11:41:08.599609 16, 0x0, sum = 3
8930 11:41:08.602773 17, 0x0, sum = 4
8931 11:41:08.602857 best_step = 15
8932 11:41:08.602922
8933 11:41:08.602982 ==
8934 11:41:08.606279 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 11:41:08.612353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 11:41:08.612436 ==
8937 11:41:08.612500 RX Vref Scan: 0
8938 11:41:08.612577
8939 11:41:08.615976 RX Vref 0 -> 0, step: 1
8940 11:41:08.616113
8941 11:41:08.618874 RX Delay 19 -> 252, step: 4
8942 11:41:08.622438 iDelay=195, Bit 0, Center 138 (87 ~ 190) 104
8943 11:41:08.625597 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8944 11:41:08.632291 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8945 11:41:08.635753 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8946 11:41:08.639006 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8947 11:41:08.642087 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8948 11:41:08.645658 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8949 11:41:08.652143 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8950 11:41:08.655380 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8951 11:41:08.659087 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8952 11:41:08.662045 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8953 11:41:08.665325 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8954 11:41:08.671762 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8955 11:41:08.675008 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8956 11:41:08.678381 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8957 11:41:08.681429 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8958 11:41:08.681511 ==
8959 11:41:08.684772 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 11:41:08.691298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 11:41:08.691381 ==
8962 11:41:08.691446 DQS Delay:
8963 11:41:08.694660 DQS0 = 0, DQS1 = 0
8964 11:41:08.694742 DQM Delay:
8965 11:41:08.698263 DQM0 = 133, DQM1 = 128
8966 11:41:08.698345 DQ Delay:
8967 11:41:08.701427 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8968 11:41:08.704395 DQ4 =130, DQ5 =144, DQ6 =142, DQ7 =130
8969 11:41:08.707941 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8970 11:41:08.711220 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8971 11:41:08.711302
8972 11:41:08.711366
8973 11:41:08.711426
8974 11:41:08.714143 [DramC_TX_OE_Calibration] TA2
8975 11:41:08.717862 Original DQ_B0 (3 6) =30, OEN = 27
8976 11:41:08.720828 Original DQ_B1 (3 6) =30, OEN = 27
8977 11:41:08.724351 24, 0x0, End_B0=24 End_B1=24
8978 11:41:08.727443 25, 0x0, End_B0=25 End_B1=25
8979 11:41:08.727528 26, 0x0, End_B0=26 End_B1=26
8980 11:41:08.730756 27, 0x0, End_B0=27 End_B1=27
8981 11:41:08.734561 28, 0x0, End_B0=28 End_B1=28
8982 11:41:08.737266 29, 0x0, End_B0=29 End_B1=29
8983 11:41:08.741046 30, 0x0, End_B0=30 End_B1=30
8984 11:41:08.741130 31, 0x4141, End_B0=30 End_B1=30
8985 11:41:08.744378 Byte0 end_step=30 best_step=27
8986 11:41:08.747264 Byte1 end_step=30 best_step=27
8987 11:41:08.750277 Byte0 TX OE(2T, 0.5T) = (3, 3)
8988 11:41:08.753872 Byte1 TX OE(2T, 0.5T) = (3, 3)
8989 11:41:08.753982
8990 11:41:08.754085
8991 11:41:08.760128 [DQSOSCAuto] RK1, (LSB)MR18= 0x101d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
8992 11:41:08.763423 CH1 RK1: MR19=303, MR18=101D
8993 11:41:08.770032 CH1_RK1: MR19=0x303, MR18=0x101D, DQSOSC=395, MR23=63, INC=23, DEC=15
8994 11:41:08.773552 [RxdqsGatingPostProcess] freq 1600
8995 11:41:08.780047 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8996 11:41:08.783166 best DQS0 dly(2T, 0.5T) = (1, 1)
8997 11:41:08.783248 best DQS1 dly(2T, 0.5T) = (1, 1)
8998 11:41:08.786564 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8999 11:41:08.790041 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9000 11:41:08.793408 best DQS0 dly(2T, 0.5T) = (1, 1)
9001 11:41:08.796463 best DQS1 dly(2T, 0.5T) = (1, 1)
9002 11:41:08.799893 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9003 11:41:08.803290 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9004 11:41:08.806370 Pre-setting of DQS Precalculation
9005 11:41:08.812950 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9006 11:41:08.819457 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9007 11:41:08.826133 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9008 11:41:08.826216
9009 11:41:08.826282
9010 11:41:08.829280 [Calibration Summary] 3200 Mbps
9011 11:41:08.829362 CH 0, Rank 0
9012 11:41:08.832387 SW Impedance : PASS
9013 11:41:08.835740 DUTY Scan : NO K
9014 11:41:08.835840 ZQ Calibration : PASS
9015 11:41:08.839465 Jitter Meter : NO K
9016 11:41:08.842681 CBT Training : PASS
9017 11:41:08.842790 Write leveling : PASS
9018 11:41:08.845924 RX DQS gating : PASS
9019 11:41:08.849147 RX DQ/DQS(RDDQC) : PASS
9020 11:41:08.849233 TX DQ/DQS : PASS
9021 11:41:08.852363 RX DATLAT : PASS
9022 11:41:08.855596 RX DQ/DQS(Engine): PASS
9023 11:41:08.855704 TX OE : PASS
9024 11:41:08.855798 All Pass.
9025 11:41:08.859099
9026 11:41:08.859195 CH 0, Rank 1
9027 11:41:08.862342 SW Impedance : PASS
9028 11:41:08.862438 DUTY Scan : NO K
9029 11:41:08.866113 ZQ Calibration : PASS
9030 11:41:08.866221 Jitter Meter : NO K
9031 11:41:08.869273 CBT Training : PASS
9032 11:41:08.871964 Write leveling : PASS
9033 11:41:08.872073 RX DQS gating : PASS
9034 11:41:08.875381 RX DQ/DQS(RDDQC) : PASS
9035 11:41:08.878806 TX DQ/DQS : PASS
9036 11:41:08.878888 RX DATLAT : PASS
9037 11:41:08.882134 RX DQ/DQS(Engine): PASS
9038 11:41:08.885513 TX OE : PASS
9039 11:41:08.885596 All Pass.
9040 11:41:08.885662
9041 11:41:08.885722 CH 1, Rank 0
9042 11:41:08.888697 SW Impedance : PASS
9043 11:41:08.892332 DUTY Scan : NO K
9044 11:41:08.892415 ZQ Calibration : PASS
9045 11:41:08.895477 Jitter Meter : NO K
9046 11:41:08.899013 CBT Training : PASS
9047 11:41:08.899095 Write leveling : PASS
9048 11:41:08.902014 RX DQS gating : PASS
9049 11:41:08.905515 RX DQ/DQS(RDDQC) : PASS
9050 11:41:08.905597 TX DQ/DQS : PASS
9051 11:41:08.908732 RX DATLAT : PASS
9052 11:41:08.911990 RX DQ/DQS(Engine): PASS
9053 11:41:08.912081 TX OE : PASS
9054 11:41:08.915494 All Pass.
9055 11:41:08.915576
9056 11:41:08.915641 CH 1, Rank 1
9057 11:41:08.918721 SW Impedance : PASS
9058 11:41:08.918803 DUTY Scan : NO K
9059 11:41:08.921752 ZQ Calibration : PASS
9060 11:41:08.925206 Jitter Meter : NO K
9061 11:41:08.925289 CBT Training : PASS
9062 11:41:08.928455 Write leveling : PASS
9063 11:41:08.931555 RX DQS gating : PASS
9064 11:41:08.931638 RX DQ/DQS(RDDQC) : PASS
9065 11:41:08.935014 TX DQ/DQS : PASS
9066 11:41:08.935100 RX DATLAT : PASS
9067 11:41:08.937982 RX DQ/DQS(Engine): PASS
9068 11:41:08.941210 TX OE : PASS
9069 11:41:08.941293 All Pass.
9070 11:41:08.941359
9071 11:41:08.944850 DramC Write-DBI on
9072 11:41:08.948300 PER_BANK_REFRESH: Hybrid Mode
9073 11:41:08.948383 TX_TRACKING: ON
9074 11:41:08.957974 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9075 11:41:08.964383 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9076 11:41:08.970991 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 11:41:08.974142 [FAST_K] Save calibration result to emmc
9078 11:41:08.977776 sync common calibartion params.
9079 11:41:08.981010 sync cbt_mode0:1, 1:1
9080 11:41:08.983908 dram_init: ddr_geometry: 2
9081 11:41:08.983990 dram_init: ddr_geometry: 2
9082 11:41:08.987409 dram_init: ddr_geometry: 2
9083 11:41:08.990423 0:dram_rank_size:100000000
9084 11:41:08.994227 1:dram_rank_size:100000000
9085 11:41:08.997086 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9086 11:41:09.000443 DFS_SHUFFLE_HW_MODE: ON
9087 11:41:09.003918 dramc_set_vcore_voltage set vcore to 725000
9088 11:41:09.006851 Read voltage for 1600, 0
9089 11:41:09.006934 Vio18 = 0
9090 11:41:09.010539 Vcore = 725000
9091 11:41:09.010621 Vdram = 0
9092 11:41:09.010687 Vddq = 0
9093 11:41:09.010748 Vmddr = 0
9094 11:41:09.013520 switch to 3200 Mbps bootup
9095 11:41:09.017270 [DramcRunTimeConfig]
9096 11:41:09.017385 PHYPLL
9097 11:41:09.020012 DPM_CONTROL_AFTERK: ON
9098 11:41:09.020129 PER_BANK_REFRESH: ON
9099 11:41:09.023434 REFRESH_OVERHEAD_REDUCTION: ON
9100 11:41:09.026704 CMD_PICG_NEW_MODE: OFF
9101 11:41:09.026787 XRTWTW_NEW_MODE: ON
9102 11:41:09.029790 XRTRTR_NEW_MODE: ON
9103 11:41:09.029873 TX_TRACKING: ON
9104 11:41:09.033481 RDSEL_TRACKING: OFF
9105 11:41:09.036640 DQS Precalculation for DVFS: ON
9106 11:41:09.036722 RX_TRACKING: OFF
9107 11:41:09.036787 HW_GATING DBG: ON
9108 11:41:09.039863 ZQCS_ENABLE_LP4: ON
9109 11:41:09.043268 RX_PICG_NEW_MODE: ON
9110 11:41:09.043350 TX_PICG_NEW_MODE: ON
9111 11:41:09.046088 ENABLE_RX_DCM_DPHY: ON
9112 11:41:09.049543 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9113 11:41:09.052976 DUMMY_READ_FOR_TRACKING: OFF
9114 11:41:09.053059 !!! SPM_CONTROL_AFTERK: OFF
9115 11:41:09.056316 !!! SPM could not control APHY
9116 11:41:09.059756 IMPEDANCE_TRACKING: ON
9117 11:41:09.059856 TEMP_SENSOR: ON
9118 11:41:09.062946 HW_SAVE_FOR_SR: OFF
9119 11:41:09.066727 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9120 11:41:09.069623 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9121 11:41:09.069699 Read ODT Tracking: ON
9122 11:41:09.072716 Refresh Rate DeBounce: ON
9123 11:41:09.076108 DFS_NO_QUEUE_FLUSH: ON
9124 11:41:09.079184 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9125 11:41:09.079260 ENABLE_DFS_RUNTIME_MRW: OFF
9126 11:41:09.082644 DDR_RESERVE_NEW_MODE: ON
9127 11:41:09.086546 MR_CBT_SWITCH_FREQ: ON
9128 11:41:09.086645 =========================
9129 11:41:09.106344 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9130 11:41:09.109970 dram_init: ddr_geometry: 2
9131 11:41:09.127812 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9132 11:41:09.130902 dram_init: dram init end (result: 0)
9133 11:41:09.137483 DRAM-K: Full calibration passed in 24414 msecs
9134 11:41:09.141072 MRC: failed to locate region type 0.
9135 11:41:09.141155 DRAM rank0 size:0x100000000,
9136 11:41:09.144456 DRAM rank1 size=0x100000000
9137 11:41:09.154256 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9138 11:41:09.161009 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9139 11:41:09.167765 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9140 11:41:09.174040 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9141 11:41:09.177597 DRAM rank0 size:0x100000000,
9142 11:41:09.180631 DRAM rank1 size=0x100000000
9143 11:41:09.180716 CBMEM:
9144 11:41:09.183859 IMD: root @ 0xfffff000 254 entries.
9145 11:41:09.187060 IMD: root @ 0xffffec00 62 entries.
9146 11:41:09.190379 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9147 11:41:09.197295 WARNING: RO_VPD is uninitialized or empty.
9148 11:41:09.200590 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9149 11:41:09.208016 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9150 11:41:09.220639 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9151 11:41:09.231821 BS: romstage times (exec / console): total (unknown) / 23944 ms
9152 11:41:09.231931
9153 11:41:09.232001
9154 11:41:09.241926 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9155 11:41:09.245321 ARM64: Exception handlers installed.
9156 11:41:09.248267 ARM64: Testing exception
9157 11:41:09.251869 ARM64: Done test exception
9158 11:41:09.251981 Enumerating buses...
9159 11:41:09.254840 Show all devs... Before device enumeration.
9160 11:41:09.258208 Root Device: enabled 1
9161 11:41:09.261689 CPU_CLUSTER: 0: enabled 1
9162 11:41:09.261807 CPU: 00: enabled 1
9163 11:41:09.264876 Compare with tree...
9164 11:41:09.264988 Root Device: enabled 1
9165 11:41:09.268026 CPU_CLUSTER: 0: enabled 1
9166 11:41:09.271820 CPU: 00: enabled 1
9167 11:41:09.271933 Root Device scanning...
9168 11:41:09.275016 scan_static_bus for Root Device
9169 11:41:09.278132 CPU_CLUSTER: 0 enabled
9170 11:41:09.281147 scan_static_bus for Root Device done
9171 11:41:09.284491 scan_bus: bus Root Device finished in 8 msecs
9172 11:41:09.284567 done
9173 11:41:09.291323 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9174 11:41:09.294814 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9175 11:41:09.301211 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9176 11:41:09.307617 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9177 11:41:09.307704 Allocating resources...
9178 11:41:09.310816 Reading resources...
9179 11:41:09.314108 Root Device read_resources bus 0 link: 0
9180 11:41:09.318158 DRAM rank0 size:0x100000000,
9181 11:41:09.318239 DRAM rank1 size=0x100000000
9182 11:41:09.324412 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9183 11:41:09.324537 CPU: 00 missing read_resources
9184 11:41:09.330703 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9185 11:41:09.333881 Root Device read_resources bus 0 link: 0 done
9186 11:41:09.337344 Done reading resources.
9187 11:41:09.340626 Show resources in subtree (Root Device)...After reading.
9188 11:41:09.344068 Root Device child on link 0 CPU_CLUSTER: 0
9189 11:41:09.347161 CPU_CLUSTER: 0 child on link 0 CPU: 00
9190 11:41:09.356808 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9191 11:41:09.356945 CPU: 00
9192 11:41:09.363885 Root Device assign_resources, bus 0 link: 0
9193 11:41:09.367013 CPU_CLUSTER: 0 missing set_resources
9194 11:41:09.370139 Root Device assign_resources, bus 0 link: 0 done
9195 11:41:09.373845 Done setting resources.
9196 11:41:09.376643 Show resources in subtree (Root Device)...After assigning values.
9197 11:41:09.380390 Root Device child on link 0 CPU_CLUSTER: 0
9198 11:41:09.386747 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 11:41:09.392863 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 11:41:09.396901 CPU: 00
9201 11:41:09.396982 Done allocating resources.
9202 11:41:09.403238 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9203 11:41:09.403348 Enabling resources...
9204 11:41:09.406272 done.
9205 11:41:09.409679 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9206 11:41:09.412849 Initializing devices...
9207 11:41:09.412925 Root Device init
9208 11:41:09.416395 init hardware done!
9209 11:41:09.416467 0x00000018: ctrlr->caps
9210 11:41:09.419492 52.000 MHz: ctrlr->f_max
9211 11:41:09.422463 0.400 MHz: ctrlr->f_min
9212 11:41:09.425821 0x40ff8080: ctrlr->voltages
9213 11:41:09.425896 sclk: 390625
9214 11:41:09.425960 Bus Width = 1
9215 11:41:09.429495 sclk: 390625
9216 11:41:09.429564 Bus Width = 1
9217 11:41:09.432756 Early init status = 3
9218 11:41:09.435824 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9219 11:41:09.439515 in-header: 03 fb 00 00 01 00 00 00
9220 11:41:09.442894 in-data: 01
9221 11:41:09.446117 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9222 11:41:09.450356 in-header: 03 fb 00 00 01 00 00 00
9223 11:41:09.454038 in-data: 01
9224 11:41:09.456888 [SSUSB] Setting up USB HOST controller...
9225 11:41:09.460506 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9226 11:41:09.463774 [SSUSB] phy power-on done.
9227 11:41:09.466961 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9228 11:41:09.473558 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9229 11:41:09.476752 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9230 11:41:09.483532 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9231 11:41:09.489769 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9232 11:41:09.496335 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9233 11:41:09.503201 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9234 11:41:09.509866 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9235 11:41:09.513060 SPM: binary array size = 0x9dc
9236 11:41:09.519407 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9237 11:41:09.522614 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9238 11:41:09.529724 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9239 11:41:09.536459 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9240 11:41:09.539434 configure_display: Starting display init
9241 11:41:09.574022 anx7625_power_on_init: Init interface.
9242 11:41:09.577136 anx7625_disable_pd_protocol: Disabled PD feature.
9243 11:41:09.580800 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9244 11:41:09.608701 anx7625_start_dp_work: Secure OCM version=00
9245 11:41:09.611514 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9246 11:41:09.626781 sp_tx_get_edid_block: EDID Block = 1
9247 11:41:09.729238 Extracted contents:
9248 11:41:09.732555 header: 00 ff ff ff ff ff ff 00
9249 11:41:09.735784 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9250 11:41:09.739402 version: 01 04
9251 11:41:09.742563 basic params: 95 1f 11 78 0a
9252 11:41:09.745806 chroma info: 76 90 94 55 54 90 27 21 50 54
9253 11:41:09.749048 established: 00 00 00
9254 11:41:09.755536 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9255 11:41:09.758816 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9256 11:41:09.765268 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9257 11:41:09.772465 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9258 11:41:09.778736 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9259 11:41:09.782049 extensions: 00
9260 11:41:09.782132 checksum: fb
9261 11:41:09.782197
9262 11:41:09.785506 Manufacturer: IVO Model 57d Serial Number 0
9263 11:41:09.788358 Made week 0 of 2020
9264 11:41:09.791577 EDID version: 1.4
9265 11:41:09.791684 Digital display
9266 11:41:09.795006 6 bits per primary color channel
9267 11:41:09.795091 DisplayPort interface
9268 11:41:09.798701 Maximum image size: 31 cm x 17 cm
9269 11:41:09.801994 Gamma: 220%
9270 11:41:09.802080 Check DPMS levels
9271 11:41:09.805338 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9272 11:41:09.811430 First detailed timing is preferred timing
9273 11:41:09.811539 Established timings supported:
9274 11:41:09.815094 Standard timings supported:
9275 11:41:09.818176 Detailed timings
9276 11:41:09.821569 Hex of detail: 383680a07038204018303c0035ae10000019
9277 11:41:09.827879 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9278 11:41:09.831376 0780 0798 07c8 0820 hborder 0
9279 11:41:09.835068 0438 043b 0447 0458 vborder 0
9280 11:41:09.837855 -hsync -vsync
9281 11:41:09.837944 Did detailed timing
9282 11:41:09.844501 Hex of detail: 000000000000000000000000000000000000
9283 11:41:09.847855 Manufacturer-specified data, tag 0
9284 11:41:09.851498 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9285 11:41:09.854737 ASCII string: InfoVision
9286 11:41:09.857491 Hex of detail: 000000fe00523134304e574635205248200a
9287 11:41:09.861202 ASCII string: R140NWF5 RH
9288 11:41:09.861280 Checksum
9289 11:41:09.864245 Checksum: 0xfb (valid)
9290 11:41:09.867570 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9291 11:41:09.870647 DSI data_rate: 832800000 bps
9292 11:41:09.877557 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9293 11:41:09.880939 anx7625_parse_edid: pixelclock(138800).
9294 11:41:09.884120 hactive(1920), hsync(48), hfp(24), hbp(88)
9295 11:41:09.887426 vactive(1080), vsync(12), vfp(3), vbp(17)
9296 11:41:09.890785 anx7625_dsi_config: config dsi.
9297 11:41:09.897384 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9298 11:41:09.911055 anx7625_dsi_config: success to config DSI
9299 11:41:09.914581 anx7625_dp_start: MIPI phy setup OK.
9300 11:41:09.917885 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9301 11:41:09.921205 mtk_ddp_mode_set invalid vrefresh 60
9302 11:41:09.925172 main_disp_path_setup
9303 11:41:09.925255 ovl_layer_smi_id_en
9304 11:41:09.927785 ovl_layer_smi_id_en
9305 11:41:09.927866 ccorr_config
9306 11:41:09.927933 aal_config
9307 11:41:09.930917 gamma_config
9308 11:41:09.930992 postmask_config
9309 11:41:09.934520 dither_config
9310 11:41:09.938038 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9311 11:41:09.944108 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9312 11:41:09.947744 Root Device init finished in 530 msecs
9313 11:41:09.950734 CPU_CLUSTER: 0 init
9314 11:41:09.957661 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9315 11:41:09.964137 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9316 11:41:09.964236 APU_MBOX 0x190000b0 = 0x10001
9317 11:41:09.967494 APU_MBOX 0x190001b0 = 0x10001
9318 11:41:09.970468 APU_MBOX 0x190005b0 = 0x10001
9319 11:41:09.973679 APU_MBOX 0x190006b0 = 0x10001
9320 11:41:09.980403 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9321 11:41:09.990252 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9322 11:41:10.002825 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9323 11:41:10.009068 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9324 11:41:10.020921 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9325 11:41:10.030153 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9326 11:41:10.033329 CPU_CLUSTER: 0 init finished in 81 msecs
9327 11:41:10.036298 Devices initialized
9328 11:41:10.039724 Show all devs... After init.
9329 11:41:10.039800 Root Device: enabled 1
9330 11:41:10.043560 CPU_CLUSTER: 0: enabled 1
9331 11:41:10.046648 CPU: 00: enabled 1
9332 11:41:10.049811 BS: BS_DEV_INIT run times (exec / console): 207 / 428 ms
9333 11:41:10.053109 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9334 11:41:10.056009 ELOG: NV offset 0x57f000 size 0x1000
9335 11:41:10.063423 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9336 11:41:10.069709 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9337 11:41:10.072978 ELOG: Event(17) added with size 13 at 2023-06-15 11:41:09 UTC
9338 11:41:10.079341 out: cmd=0x121: 03 db 21 01 00 00 00 00
9339 11:41:10.082817 in-header: 03 4a 00 00 2c 00 00 00
9340 11:41:10.092733 in-data: 15 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 11:41:10.099160 ELOG: Event(A1) added with size 10 at 2023-06-15 11:41:09 UTC
9342 11:41:10.105801 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9343 11:41:10.112806 ELOG: Event(A0) added with size 9 at 2023-06-15 11:41:09 UTC
9344 11:41:10.115698 elog_add_boot_reason: Logged dev mode boot
9345 11:41:10.122262 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9346 11:41:10.122366 Finalize devices...
9347 11:41:10.125480 Devices finalized
9348 11:41:10.129204 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9349 11:41:10.132024 Writing coreboot table at 0xffe64000
9350 11:41:10.135347 0. 000000000010a000-0000000000113fff: RAMSTAGE
9351 11:41:10.141970 1. 0000000040000000-00000000400fffff: RAM
9352 11:41:10.145515 2. 0000000040100000-000000004032afff: RAMSTAGE
9353 11:41:10.148742 3. 000000004032b000-00000000545fffff: RAM
9354 11:41:10.151706 4. 0000000054600000-000000005465ffff: BL31
9355 11:41:10.155399 5. 0000000054660000-00000000ffe63fff: RAM
9356 11:41:10.162055 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9357 11:41:10.165244 7. 0000000100000000-000000023fffffff: RAM
9358 11:41:10.168243 Passing 5 GPIOs to payload:
9359 11:41:10.171740 NAME | PORT | POLARITY | VALUE
9360 11:41:10.178233 EC in RW | 0x000000aa | low | undefined
9361 11:41:10.181306 EC interrupt | 0x00000005 | low | undefined
9362 11:41:10.188239 TPM interrupt | 0x000000ab | high | undefined
9363 11:41:10.191535 SD card detect | 0x00000011 | high | undefined
9364 11:41:10.194814 speaker enable | 0x00000093 | high | undefined
9365 11:41:10.198209 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9366 11:41:10.201274 in-header: 03 f9 00 00 02 00 00 00
9367 11:41:10.204838 in-data: 02 00
9368 11:41:10.208274 ADC[4]: Raw value=902586 ID=7
9369 11:41:10.211617 ADC[3]: Raw value=213916 ID=1
9370 11:41:10.211690 RAM Code: 0x71
9371 11:41:10.214920 ADC[6]: Raw value=74630 ID=0
9372 11:41:10.218130 ADC[5]: Raw value=213546 ID=1
9373 11:41:10.218230 SKU Code: 0x1
9374 11:41:10.224504 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 951a
9375 11:41:10.224611 coreboot table: 964 bytes.
9376 11:41:10.228138 IMD ROOT 0. 0xfffff000 0x00001000
9377 11:41:10.231188 IMD SMALL 1. 0xffffe000 0x00001000
9378 11:41:10.234474 RO MCACHE 2. 0xffffc000 0x00001104
9379 11:41:10.238063 CONSOLE 3. 0xfff7c000 0x00080000
9380 11:41:10.240933 FMAP 4. 0xfff7b000 0x00000452
9381 11:41:10.244146 TIME STAMP 5. 0xfff7a000 0x00000910
9382 11:41:10.247594 VBOOT WORK 6. 0xfff66000 0x00014000
9383 11:41:10.250638 RAMOOPS 7. 0xffe66000 0x00100000
9384 11:41:10.253817 COREBOOT 8. 0xffe64000 0x00002000
9385 11:41:10.257170 IMD small region:
9386 11:41:10.260644 IMD ROOT 0. 0xffffec00 0x00000400
9387 11:41:10.263719 VPD 1. 0xffffeba0 0x0000004c
9388 11:41:10.266944 MMC STATUS 2. 0xffffeb80 0x00000004
9389 11:41:10.274141 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9390 11:41:10.274227 Probing TPM: done!
9391 11:41:10.280560 Connected to device vid:did:rid of 1ae0:0028:00
9392 11:41:10.287632 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9393 11:41:10.290570 Initialized TPM device CR50 revision 0
9394 11:41:10.294781 Checking cr50 for pending updates
9395 11:41:10.299477 Reading cr50 TPM mode
9396 11:41:10.308373 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9397 11:41:10.315012 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9398 11:41:10.354826 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9399 11:41:10.358537 Checking segment from ROM address 0x40100000
9400 11:41:10.362109 Checking segment from ROM address 0x4010001c
9401 11:41:10.368574 Loading segment from ROM address 0x40100000
9402 11:41:10.368660 code (compression=0)
9403 11:41:10.378224 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9404 11:41:10.384879 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9405 11:41:10.385014 it's not compressed!
9406 11:41:10.391487 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9407 11:41:10.397886 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9408 11:41:10.415504 Loading segment from ROM address 0x4010001c
9409 11:41:10.415612 Entry Point 0x80000000
9410 11:41:10.418877 Loaded segments
9411 11:41:10.422286 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9412 11:41:10.428764 Jumping to boot code at 0x80000000(0xffe64000)
9413 11:41:10.435405 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9414 11:41:10.441874 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9415 11:41:10.449793 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9416 11:41:10.453050 Checking segment from ROM address 0x40100000
9417 11:41:10.456486 Checking segment from ROM address 0x4010001c
9418 11:41:10.463187 Loading segment from ROM address 0x40100000
9419 11:41:10.463291 code (compression=1)
9420 11:41:10.469494 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9421 11:41:10.479160 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9422 11:41:10.479283 using LZMA
9423 11:41:10.488343 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9424 11:41:10.495115 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9425 11:41:10.498519 Loading segment from ROM address 0x4010001c
9426 11:41:10.498603 Entry Point 0x54601000
9427 11:41:10.501952 Loaded segments
9428 11:41:10.504906 NOTICE: MT8192 bl31_setup
9429 11:41:10.511867 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9430 11:41:10.515271 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9431 11:41:10.518459 WARNING: region 0:
9432 11:41:10.521740 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 11:41:10.521849 WARNING: region 1:
9434 11:41:10.528966 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9435 11:41:10.532308 WARNING: region 2:
9436 11:41:10.535459 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9437 11:41:10.538705 WARNING: region 3:
9438 11:41:10.542014 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9439 11:41:10.545367 WARNING: region 4:
9440 11:41:10.551560 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9441 11:41:10.551643 WARNING: region 5:
9442 11:41:10.555429 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 11:41:10.558649 WARNING: region 6:
9444 11:41:10.561962 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 11:41:10.564922 WARNING: region 7:
9446 11:41:10.568601 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 11:41:10.574906 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9448 11:41:10.578547 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9449 11:41:10.581877 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9450 11:41:10.588201 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9451 11:41:10.591553 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9452 11:41:10.594597 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9453 11:41:10.601310 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9454 11:41:10.604648 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9455 11:41:10.611320 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9456 11:41:10.614574 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9457 11:41:10.618319 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9458 11:41:10.624504 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9459 11:41:10.628103 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9460 11:41:10.631216 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9461 11:41:10.638103 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9462 11:41:10.641180 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9463 11:41:10.647757 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9464 11:41:10.651378 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9465 11:41:10.655084 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9466 11:41:10.661595 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9467 11:41:10.664441 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9468 11:41:10.668038 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9469 11:41:10.674883 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9470 11:41:10.678117 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9471 11:41:10.684517 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9472 11:41:10.688164 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9473 11:41:10.694341 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9474 11:41:10.697789 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9475 11:41:10.700971 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9476 11:41:10.707774 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9477 11:41:10.710903 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9478 11:41:10.717446 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9479 11:41:10.721109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9480 11:41:10.724011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9481 11:41:10.727307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9482 11:41:10.734150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9483 11:41:10.737501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9484 11:41:10.740801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9485 11:41:10.744385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9486 11:41:10.750640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9487 11:41:10.753930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9488 11:41:10.757608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9489 11:41:10.760856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9490 11:41:10.767047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9491 11:41:10.770953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9492 11:41:10.773552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9493 11:41:10.777411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9494 11:41:10.783574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9495 11:41:10.787435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9496 11:41:10.793486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9497 11:41:10.796920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9498 11:41:10.800356 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9499 11:41:10.807241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9500 11:41:10.810274 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9501 11:41:10.816637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9502 11:41:10.819894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9503 11:41:10.827007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9504 11:41:10.829999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9505 11:41:10.833476 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9506 11:41:10.840490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9507 11:41:10.843627 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9508 11:41:10.850415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9509 11:41:10.853579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9510 11:41:10.859936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9511 11:41:10.863690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9512 11:41:10.870251 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9513 11:41:10.873817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9514 11:41:10.876767 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9515 11:41:10.883644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9516 11:41:10.886926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9517 11:41:10.893911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9518 11:41:10.896813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9519 11:41:10.900190 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9520 11:41:10.907079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9521 11:41:10.910626 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9522 11:41:10.916957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9523 11:41:10.920312 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9524 11:41:10.926845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9525 11:41:10.930064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9526 11:41:10.936968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9527 11:41:10.939849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9528 11:41:10.947110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9529 11:41:10.950190 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9530 11:41:10.953463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9531 11:41:10.960090 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9532 11:41:10.963526 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9533 11:41:10.970509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9534 11:41:10.973219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9535 11:41:10.979838 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9536 11:41:10.983665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9537 11:41:10.986560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9538 11:41:10.992988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9539 11:41:10.996462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9540 11:41:11.003083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9541 11:41:11.006674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9542 11:41:11.013097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9543 11:41:11.016507 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9544 11:41:11.019312 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9545 11:41:11.026158 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9546 11:41:11.029351 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9547 11:41:11.032631 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9548 11:41:11.036292 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9549 11:41:11.042612 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9550 11:41:11.046048 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9551 11:41:11.052428 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9552 11:41:11.055529 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9553 11:41:11.059169 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9554 11:41:11.066456 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9555 11:41:11.069205 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9556 11:41:11.075960 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9557 11:41:11.079288 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9558 11:41:11.085855 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9559 11:41:11.089120 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9560 11:41:11.093050 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9561 11:41:11.098685 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9562 11:41:11.102221 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9563 11:41:11.105580 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9564 11:41:11.112306 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9565 11:41:11.115927 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9566 11:41:11.119187 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9567 11:41:11.125386 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9568 11:41:11.128445 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9569 11:41:11.132148 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9570 11:41:11.135441 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9571 11:41:11.142056 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9572 11:41:11.144906 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9573 11:41:11.151866 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9574 11:41:11.155140 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9575 11:41:11.158428 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9576 11:41:11.165147 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9577 11:41:11.168310 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9578 11:41:11.171874 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9579 11:41:11.178313 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9580 11:41:11.182008 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9581 11:41:11.188378 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9582 11:41:11.191388 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9583 11:41:11.194694 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9584 11:41:11.201423 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9585 11:41:11.204630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9586 11:41:11.211692 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9587 11:41:11.214821 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9588 11:41:11.218108 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9589 11:41:11.224913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9590 11:41:11.228157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9591 11:41:11.234746 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9592 11:41:11.237717 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9593 11:41:11.241024 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9594 11:41:11.248088 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9595 11:41:11.250923 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9596 11:41:11.257921 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9597 11:41:11.261011 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9598 11:41:11.264413 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9599 11:41:11.271076 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9600 11:41:11.274194 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9601 11:41:11.281050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9602 11:41:11.284095 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9603 11:41:11.287233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9604 11:41:11.294086 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9605 11:41:11.297372 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9606 11:41:11.300607 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9607 11:41:11.307305 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9608 11:41:11.310863 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9609 11:41:11.317510 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9610 11:41:11.320705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9611 11:41:11.327018 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9612 11:41:11.330291 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9613 11:41:11.333738 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9614 11:41:11.340234 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9615 11:41:11.343341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9616 11:41:11.346916 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9617 11:41:11.353742 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9618 11:41:11.356824 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9619 11:41:11.363261 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9620 11:41:11.366665 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9621 11:41:11.369705 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9622 11:41:11.376636 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9623 11:41:11.379709 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9624 11:41:11.386513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9625 11:41:11.390411 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9626 11:41:11.393576 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9627 11:41:11.399700 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9628 11:41:11.402757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9629 11:41:11.409893 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9630 11:41:11.412597 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9631 11:41:11.415808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9632 11:41:11.423097 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9633 11:41:11.426096 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9634 11:41:11.432554 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9635 11:41:11.435977 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9636 11:41:11.443089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9637 11:41:11.446058 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9638 11:41:11.449180 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9639 11:41:11.455475 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9640 11:41:11.459024 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9641 11:41:11.465966 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9642 11:41:11.468856 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9643 11:41:11.475463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9644 11:41:11.478744 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9645 11:41:11.481922 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9646 11:41:11.488817 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9647 11:41:11.491706 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9648 11:41:11.498309 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9649 11:41:11.501511 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9650 11:41:11.508380 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9651 11:41:11.511623 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9652 11:41:11.514644 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9653 11:41:11.521410 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9654 11:41:11.524869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9655 11:41:11.531316 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9656 11:41:11.534536 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9657 11:41:11.541402 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9658 11:41:11.544405 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9659 11:41:11.547932 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9660 11:41:11.554254 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9661 11:41:11.557340 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9662 11:41:11.564412 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9663 11:41:11.567531 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9664 11:41:11.574053 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9665 11:41:11.577584 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9666 11:41:11.580341 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9667 11:41:11.587496 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9668 11:41:11.590274 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9669 11:41:11.597061 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9670 11:41:11.599919 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9671 11:41:11.606463 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9672 11:41:11.610329 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9673 11:41:11.613286 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9674 11:41:11.620359 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9675 11:41:11.623267 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9676 11:41:11.626838 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9677 11:41:11.633333 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9678 11:41:11.636454 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9679 11:41:11.639830 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9680 11:41:11.643245 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9681 11:41:11.650165 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9682 11:41:11.653078 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9683 11:41:11.659473 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9684 11:41:11.662747 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9685 11:41:11.665924 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9686 11:41:11.672482 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9687 11:41:11.676497 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9688 11:41:11.682662 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9689 11:41:11.686140 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9690 11:41:11.689428 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9691 11:41:11.695521 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9692 11:41:11.699660 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9693 11:41:11.702532 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9694 11:41:11.709085 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9695 11:41:11.712254 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9696 11:41:11.715391 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9697 11:41:11.721979 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9698 11:41:11.725404 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9699 11:41:11.731637 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9700 11:41:11.734914 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9701 11:41:11.738474 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9702 11:41:11.744973 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9703 11:41:11.748343 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9704 11:41:11.755109 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9705 11:41:11.758227 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9706 11:41:11.761492 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9707 11:41:11.768374 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9708 11:41:11.771360 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9709 11:41:11.777800 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9710 11:41:11.781348 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9711 11:41:11.784473 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9712 11:41:11.791048 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9713 11:41:11.794282 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9714 11:41:11.797788 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9715 11:41:11.804240 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9716 11:41:11.808129 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9717 11:41:11.810511 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9718 11:41:11.814646 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9719 11:41:11.821002 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9720 11:41:11.824167 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9721 11:41:11.827675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9722 11:41:11.830808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9723 11:41:11.837493 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9724 11:41:11.840565 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9725 11:41:11.843713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9726 11:41:11.847030 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9727 11:41:11.853636 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9728 11:41:11.856888 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9729 11:41:11.860442 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9730 11:41:11.866947 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9731 11:41:11.869999 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9732 11:41:11.877009 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9733 11:41:11.879739 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9734 11:41:11.886819 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9735 11:41:11.889771 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9736 11:41:11.893144 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9737 11:41:11.899594 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9738 11:41:11.903148 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9739 11:41:11.909600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9740 11:41:11.912628 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9741 11:41:11.919175 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9742 11:41:11.922500 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9743 11:41:11.925993 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9744 11:41:11.932456 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9745 11:41:11.935747 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9746 11:41:11.942277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9747 11:41:11.945590 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9748 11:41:11.952699 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9749 11:41:11.955477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9750 11:41:11.959153 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9751 11:41:11.965230 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9752 11:41:11.968719 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9753 11:41:11.975303 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9754 11:41:11.978659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9755 11:41:11.981841 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9756 11:41:11.988477 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9757 11:41:11.991716 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9758 11:41:11.998965 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9759 11:41:12.001715 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9760 11:41:12.007978 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9761 11:41:12.011447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9762 11:41:12.014798 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9763 11:41:12.021150 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9764 11:41:12.025074 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9765 11:41:12.031626 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9766 11:41:12.034604 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9767 11:41:12.041205 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9768 11:41:12.044541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9769 11:41:12.047697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9770 11:41:12.054401 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9771 11:41:12.058045 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9772 11:41:12.064124 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9773 11:41:12.067061 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9774 11:41:12.074107 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9775 11:41:12.077217 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9776 11:41:12.081010 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9777 11:41:12.087098 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9778 11:41:12.090384 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9779 11:41:12.097188 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9780 11:41:12.100490 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9781 11:41:12.103556 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9782 11:41:12.110207 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9783 11:41:12.113389 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9784 11:41:12.120537 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9785 11:41:12.123683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9786 11:41:12.126546 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9787 11:41:12.133280 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9788 11:41:12.136255 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9789 11:41:12.142933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9790 11:41:12.146202 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9791 11:41:12.152909 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9792 11:41:12.156028 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9793 11:41:12.159524 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9794 11:41:12.166263 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9795 11:41:12.169313 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9796 11:41:12.175756 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9797 11:41:12.178916 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9798 11:41:12.185786 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9799 11:41:12.189296 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9800 11:41:12.192213 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9801 11:41:12.198985 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9802 11:41:12.202243 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9803 11:41:12.209064 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9804 11:41:12.212229 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9805 11:41:12.218793 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9806 11:41:12.222290 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9807 11:41:12.228681 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9808 11:41:12.231865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9809 11:41:12.235055 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9810 11:41:12.242169 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9811 11:41:12.245304 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9812 11:41:12.251396 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9813 11:41:12.254777 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9814 11:41:12.262118 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9815 11:41:12.264991 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9816 11:41:12.268326 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9817 11:41:12.274822 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9818 11:41:12.278399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9819 11:41:12.284575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9820 11:41:12.287672 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9821 11:41:12.294479 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9822 11:41:12.297694 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9823 11:41:12.304657 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9824 11:41:12.307352 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9825 11:41:12.314227 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9826 11:41:12.317158 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9827 11:41:12.320478 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9828 11:41:12.327675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9829 11:41:12.330524 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9830 11:41:12.337326 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9831 11:41:12.340161 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9832 11:41:12.346988 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9833 11:41:12.350488 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9834 11:41:12.356869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9835 11:41:12.360262 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9836 11:41:12.366926 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9837 11:41:12.370157 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9838 11:41:12.373425 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9839 11:41:12.379721 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9840 11:41:12.382878 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9841 11:41:12.389747 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9842 11:41:12.393092 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9843 11:41:12.399721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9844 11:41:12.402979 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9845 11:41:12.409493 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9846 11:41:12.412916 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9847 11:41:12.419538 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9848 11:41:12.422706 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9849 11:41:12.426061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9850 11:41:12.432507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9851 11:41:12.435904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9852 11:41:12.442414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9853 11:41:12.445744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9854 11:41:12.452460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9855 11:41:12.455631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9856 11:41:12.461758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9857 11:41:12.465387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9858 11:41:12.471752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9859 11:41:12.475112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9860 11:41:12.481851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9861 11:41:12.485308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9862 11:41:12.491787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9863 11:41:12.494849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9864 11:41:12.498341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9865 11:41:12.504844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9866 11:41:12.507956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9867 11:41:12.515001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9868 11:41:12.518067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9869 11:41:12.524970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9870 11:41:12.528298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9871 11:41:12.534712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9872 11:41:12.541380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9873 11:41:12.544339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9874 11:41:12.550673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9875 11:41:12.554386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9876 11:41:12.560396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9877 11:41:12.563858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9878 11:41:12.570867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9879 11:41:12.574075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9880 11:41:12.580658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9881 11:41:12.583929 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9882 11:41:12.587277 INFO: [APUAPC] vio 0
9883 11:41:12.590637 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9884 11:41:12.596985 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9885 11:41:12.600207 INFO: [APUAPC] D0_APC_0: 0x400510
9886 11:41:12.600289 INFO: [APUAPC] D0_APC_1: 0x0
9887 11:41:12.603346 INFO: [APUAPC] D0_APC_2: 0x1540
9888 11:41:12.606716 INFO: [APUAPC] D0_APC_3: 0x0
9889 11:41:12.610468 INFO: [APUAPC] D1_APC_0: 0xffffffff
9890 11:41:12.613547 INFO: [APUAPC] D1_APC_1: 0xffffffff
9891 11:41:12.616790 INFO: [APUAPC] D1_APC_2: 0x3fffff
9892 11:41:12.619737 INFO: [APUAPC] D1_APC_3: 0x0
9893 11:41:12.623094 INFO: [APUAPC] D2_APC_0: 0xffffffff
9894 11:41:12.626458 INFO: [APUAPC] D2_APC_1: 0xffffffff
9895 11:41:12.630151 INFO: [APUAPC] D2_APC_2: 0x3fffff
9896 11:41:12.633121 INFO: [APUAPC] D2_APC_3: 0x0
9897 11:41:12.636216 INFO: [APUAPC] D3_APC_0: 0xffffffff
9898 11:41:12.639836 INFO: [APUAPC] D3_APC_1: 0xffffffff
9899 11:41:12.643806 INFO: [APUAPC] D3_APC_2: 0x3fffff
9900 11:41:12.646369 INFO: [APUAPC] D3_APC_3: 0x0
9901 11:41:12.649672 INFO: [APUAPC] D4_APC_0: 0xffffffff
9902 11:41:12.652909 INFO: [APUAPC] D4_APC_1: 0xffffffff
9903 11:41:12.656004 INFO: [APUAPC] D4_APC_2: 0x3fffff
9904 11:41:12.659866 INFO: [APUAPC] D4_APC_3: 0x0
9905 11:41:12.662961 INFO: [APUAPC] D5_APC_0: 0xffffffff
9906 11:41:12.666447 INFO: [APUAPC] D5_APC_1: 0xffffffff
9907 11:41:12.669488 INFO: [APUAPC] D5_APC_2: 0x3fffff
9908 11:41:12.672750 INFO: [APUAPC] D5_APC_3: 0x0
9909 11:41:12.675969 INFO: [APUAPC] D6_APC_0: 0xffffffff
9910 11:41:12.679356 INFO: [APUAPC] D6_APC_1: 0xffffffff
9911 11:41:12.683074 INFO: [APUAPC] D6_APC_2: 0x3fffff
9912 11:41:12.686143 INFO: [APUAPC] D6_APC_3: 0x0
9913 11:41:12.689488 INFO: [APUAPC] D7_APC_0: 0xffffffff
9914 11:41:12.692914 INFO: [APUAPC] D7_APC_1: 0xffffffff
9915 11:41:12.696248 INFO: [APUAPC] D7_APC_2: 0x3fffff
9916 11:41:12.698938 INFO: [APUAPC] D7_APC_3: 0x0
9917 11:41:12.702329 INFO: [APUAPC] D8_APC_0: 0xffffffff
9918 11:41:12.705668 INFO: [APUAPC] D8_APC_1: 0xffffffff
9919 11:41:12.709229 INFO: [APUAPC] D8_APC_2: 0x3fffff
9920 11:41:12.712455 INFO: [APUAPC] D8_APC_3: 0x0
9921 11:41:12.715593 INFO: [APUAPC] D9_APC_0: 0xffffffff
9922 11:41:12.719241 INFO: [APUAPC] D9_APC_1: 0xffffffff
9923 11:41:12.722224 INFO: [APUAPC] D9_APC_2: 0x3fffff
9924 11:41:12.725691 INFO: [APUAPC] D9_APC_3: 0x0
9925 11:41:12.729073 INFO: [APUAPC] D10_APC_0: 0xffffffff
9926 11:41:12.732417 INFO: [APUAPC] D10_APC_1: 0xffffffff
9927 11:41:12.735393 INFO: [APUAPC] D10_APC_2: 0x3fffff
9928 11:41:12.738630 INFO: [APUAPC] D10_APC_3: 0x0
9929 11:41:12.742181 INFO: [APUAPC] D11_APC_0: 0xffffffff
9930 11:41:12.745782 INFO: [APUAPC] D11_APC_1: 0xffffffff
9931 11:41:12.748639 INFO: [APUAPC] D11_APC_2: 0x3fffff
9932 11:41:12.751951 INFO: [APUAPC] D11_APC_3: 0x0
9933 11:41:12.755134 INFO: [APUAPC] D12_APC_0: 0xffffffff
9934 11:41:12.758663 INFO: [APUAPC] D12_APC_1: 0xffffffff
9935 11:41:12.762172 INFO: [APUAPC] D12_APC_2: 0x3fffff
9936 11:41:12.765351 INFO: [APUAPC] D12_APC_3: 0x0
9937 11:41:12.768756 INFO: [APUAPC] D13_APC_0: 0xffffffff
9938 11:41:12.771536 INFO: [APUAPC] D13_APC_1: 0xffffffff
9939 11:41:12.774917 INFO: [APUAPC] D13_APC_2: 0x3fffff
9940 11:41:12.778518 INFO: [APUAPC] D13_APC_3: 0x0
9941 11:41:12.781842 INFO: [APUAPC] D14_APC_0: 0xffffffff
9942 11:41:12.784978 INFO: [APUAPC] D14_APC_1: 0xffffffff
9943 11:41:12.788437 INFO: [APUAPC] D14_APC_2: 0x3fffff
9944 11:41:12.791296 INFO: [APUAPC] D14_APC_3: 0x0
9945 11:41:12.794681 INFO: [APUAPC] D15_APC_0: 0xffffffff
9946 11:41:12.797978 INFO: [APUAPC] D15_APC_1: 0xffffffff
9947 11:41:12.801217 INFO: [APUAPC] D15_APC_2: 0x3fffff
9948 11:41:12.804675 INFO: [APUAPC] D15_APC_3: 0x0
9949 11:41:12.807560 INFO: [APUAPC] APC_CON: 0x4
9950 11:41:12.810955 INFO: [NOCDAPC] D0_APC_0: 0x0
9951 11:41:12.813957 INFO: [NOCDAPC] D0_APC_1: 0x0
9952 11:41:12.817213 INFO: [NOCDAPC] D1_APC_0: 0x0
9953 11:41:12.820822 INFO: [NOCDAPC] D1_APC_1: 0xfff
9954 11:41:12.824469 INFO: [NOCDAPC] D2_APC_0: 0x0
9955 11:41:12.824956 INFO: [NOCDAPC] D2_APC_1: 0xfff
9956 11:41:12.827484 INFO: [NOCDAPC] D3_APC_0: 0x0
9957 11:41:12.830759 INFO: [NOCDAPC] D3_APC_1: 0xfff
9958 11:41:12.833907 INFO: [NOCDAPC] D4_APC_0: 0x0
9959 11:41:12.837460 INFO: [NOCDAPC] D4_APC_1: 0xfff
9960 11:41:12.840170 INFO: [NOCDAPC] D5_APC_0: 0x0
9961 11:41:12.843620 INFO: [NOCDAPC] D5_APC_1: 0xfff
9962 11:41:12.847209 INFO: [NOCDAPC] D6_APC_0: 0x0
9963 11:41:12.850604 INFO: [NOCDAPC] D6_APC_1: 0xfff
9964 11:41:12.853434 INFO: [NOCDAPC] D7_APC_0: 0x0
9965 11:41:12.857037 INFO: [NOCDAPC] D7_APC_1: 0xfff
9966 11:41:12.859912 INFO: [NOCDAPC] D8_APC_0: 0x0
9967 11:41:12.860019 INFO: [NOCDAPC] D8_APC_1: 0xfff
9968 11:41:12.862893 INFO: [NOCDAPC] D9_APC_0: 0x0
9969 11:41:12.866876 INFO: [NOCDAPC] D9_APC_1: 0xfff
9970 11:41:12.869722 INFO: [NOCDAPC] D10_APC_0: 0x0
9971 11:41:12.872950 INFO: [NOCDAPC] D10_APC_1: 0xfff
9972 11:41:12.876268 INFO: [NOCDAPC] D11_APC_0: 0x0
9973 11:41:12.879832 INFO: [NOCDAPC] D11_APC_1: 0xfff
9974 11:41:12.883032 INFO: [NOCDAPC] D12_APC_0: 0x0
9975 11:41:12.886633 INFO: [NOCDAPC] D12_APC_1: 0xfff
9976 11:41:12.889609 INFO: [NOCDAPC] D13_APC_0: 0x0
9977 11:41:12.892489 INFO: [NOCDAPC] D13_APC_1: 0xfff
9978 11:41:12.895824 INFO: [NOCDAPC] D14_APC_0: 0x0
9979 11:41:12.899137 INFO: [NOCDAPC] D14_APC_1: 0xfff
9980 11:41:12.902694 INFO: [NOCDAPC] D15_APC_0: 0x0
9981 11:41:12.905665 INFO: [NOCDAPC] D15_APC_1: 0xfff
9982 11:41:12.909347 INFO: [NOCDAPC] APC_CON: 0x4
9983 11:41:12.913030 INFO: [APUAPC] set_apusys_apc done
9984 11:41:12.915513 INFO: [DEVAPC] devapc_init done
9985 11:41:12.919106 INFO: GICv3 without legacy support detected.
9986 11:41:12.922851 INFO: ARM GICv3 driver initialized in EL3
9987 11:41:12.925685 INFO: Maximum SPI INTID supported: 639
9988 11:41:12.929368 INFO: BL31: Initializing runtime services
9989 11:41:12.935871 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9990 11:41:12.939320 INFO: SPM: enable CPC mode
9991 11:41:12.942251 INFO: mcdi ready for mcusys-off-idle and system suspend
9992 11:41:12.948962 INFO: BL31: Preparing for EL3 exit to normal world
9993 11:41:12.952393 INFO: Entry point address = 0x80000000
9994 11:41:12.955218 INFO: SPSR = 0x8
9995 11:41:12.959852
9996 11:41:12.959934
9997 11:41:12.960000
9998 11:41:12.963180 Starting depthcharge on Spherion...
9999 11:41:12.963262
10000 11:41:12.963328 Wipe memory regions:
10001 11:41:12.963389
10002 11:41:12.964005 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10003 11:41:12.964221 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10004 11:41:12.964378 Setting prompt string to ['asurada:']
10005 11:41:12.964481 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10006 11:41:12.966196 [0x00000040000000, 0x00000054600000)
10007 11:41:13.088836
10008 11:41:13.089053 [0x00000054660000, 0x00000080000000)
10009 11:41:13.349469
10010 11:41:13.351928 [0x000000821a7280, 0x000000ffe64000)
10011 11:41:14.094576
10012 11:41:14.094738 [0x00000100000000, 0x00000240000000)
10013 11:41:15.984604
10014 11:41:15.987747 Initializing XHCI USB controller at 0x11200000.
10015 11:41:17.025813
10016 11:41:17.028468 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10017 11:41:17.028560
10018 11:41:17.028626
10019 11:41:17.028686
10020 11:41:17.028965 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10022 11:41:17.129310 asurada: tftpboot 192.168.201.1 10742201/tftp-deploy-nwrhfab6/kernel/image.itb 10742201/tftp-deploy-nwrhfab6/kernel/cmdline
10023 11:41:17.129436 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10024 11:41:17.129557 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10025 11:41:17.134147 tftpboot 192.168.201.1 10742201/tftp-deploy-nwrhfab6/kernel/image.ittp-deploy-nwrhfab6/kernel/cmdline
10026 11:41:17.134232
10027 11:41:17.134298 Waiting for link
10028 11:41:17.294925
10029 11:41:17.295567 R8152: Initializing
10030 11:41:17.296175
10031 11:41:17.297949 Version 6 (ocp_data = 5c30)
10032 11:41:17.298376
10033 11:41:17.301530 R8152: Done initializing
10034 11:41:17.301977
10035 11:41:17.302403 Adding net device
10036 11:41:19.172090
10037 11:41:19.172244 done.
10038 11:41:19.172312
10039 11:41:19.172374 MAC: 00:24:32:30:7c:7b
10040 11:41:19.172435
10041 11:41:19.175743 Sending DHCP discover... done.
10042 11:41:19.175827
10043 11:41:19.178912 Waiting for reply... done.
10044 11:41:19.179058
10045 11:41:19.182197 Sending DHCP request... done.
10046 11:41:19.182281
10047 11:41:19.182347 Waiting for reply... done.
10048 11:41:19.182408
10049 11:41:19.185463 My ip is 192.168.201.14
10050 11:41:19.185546
10051 11:41:19.188731 The DHCP server ip is 192.168.201.1
10052 11:41:19.188814
10053 11:41:19.192023 TFTP server IP predefined by user: 192.168.201.1
10054 11:41:19.192143
10055 11:41:19.198574 Bootfile predefined by user: 10742201/tftp-deploy-nwrhfab6/kernel/image.itb
10056 11:41:19.198657
10057 11:41:19.202017 Sending tftp read request... done.
10058 11:41:19.202101
10059 11:41:19.205067 Waiting for the transfer...
10060 11:41:19.207891
10061 11:41:19.756558 00000000 ################################################################
10062 11:41:19.756734
10063 11:41:20.289122 00080000 ################################################################
10064 11:41:20.289302
10065 11:41:20.823011 00100000 ################################################################
10066 11:41:20.823168
10067 11:41:21.360977 00180000 ################################################################
10068 11:41:21.361116
10069 11:41:21.896480 00200000 ################################################################
10070 11:41:21.896641
10071 11:41:22.446972 00280000 ################################################################
10072 11:41:22.447112
10073 11:41:23.005762 00300000 ################################################################
10074 11:41:23.005925
10075 11:41:23.560441 00380000 ################################################################
10076 11:41:23.560617
10077 11:41:24.126661 00400000 ################################################################
10078 11:41:24.126834
10079 11:41:24.682096 00480000 ################################################################
10080 11:41:24.682268
10081 11:41:25.247293 00500000 ################################################################
10082 11:41:25.247449
10083 11:41:25.803373 00580000 ################################################################
10084 11:41:25.803528
10085 11:41:26.351450 00600000 ################################################################
10086 11:41:26.351604
10087 11:41:26.907048 00680000 ################################################################
10088 11:41:26.907210
10089 11:41:27.466720 00700000 ################################################################
10090 11:41:27.466865
10091 11:41:28.042356 00780000 ################################################################
10092 11:41:28.042538
10093 11:41:28.633828 00800000 ################################################################
10094 11:41:28.633984
10095 11:41:29.206025 00880000 ################################################################
10096 11:41:29.206166
10097 11:41:29.761525 00900000 ################################################################
10098 11:41:29.761673
10099 11:41:30.328554 00980000 ################################################################
10100 11:41:30.328699
10101 11:41:30.884466 00a00000 ################################################################
10102 11:41:30.884618
10103 11:41:31.442723 00a80000 ################################################################
10104 11:41:31.442918
10105 11:41:31.991844 00b00000 ################################################################
10106 11:41:31.991999
10107 11:41:32.523087 00b80000 ################################################################
10108 11:41:32.523237
10109 11:41:33.073785 00c00000 ################################################################
10110 11:41:33.073942
10111 11:41:33.627705 00c80000 ################################################################
10112 11:41:33.627888
10113 11:41:34.200251 00d00000 ################################################################
10114 11:41:34.200409
10115 11:41:34.769895 00d80000 ################################################################
10116 11:41:34.770048
10117 11:41:35.342585 00e00000 ################################################################
10118 11:41:35.342735
10119 11:41:35.895136 00e80000 ################################################################
10120 11:41:35.895277
10121 11:41:36.426190 00f00000 ################################################################
10122 11:41:36.426328
10123 11:41:36.971067 00f80000 ################################################################
10124 11:41:36.971203
10125 11:41:37.515845 01000000 ################################################################
10126 11:41:37.515980
10127 11:41:38.078539 01080000 ################################################################
10128 11:41:38.078688
10129 11:41:38.632105 01100000 ################################################################
10130 11:41:38.632300
10131 11:41:39.202054 01180000 ################################################################
10132 11:41:39.202201
10133 11:41:39.785187 01200000 ################################################################
10134 11:41:39.785339
10135 11:41:40.342555 01280000 ################################################################
10136 11:41:40.342700
10137 11:41:40.916980 01300000 ################################################################
10138 11:41:40.917135
10139 11:41:41.457787 01380000 ################################################################
10140 11:41:41.458001
10141 11:41:41.992310 01400000 ################################################################
10142 11:41:41.992493
10143 11:41:42.553345 01480000 ################################################################
10144 11:41:42.553498
10145 11:41:43.114343 01500000 ################################################################
10146 11:41:43.114575
10147 11:41:43.700091 01580000 ################################################################
10148 11:41:43.700239
10149 11:41:44.276168 01600000 ################################################################
10150 11:41:44.276332
10151 11:41:44.809699 01680000 ################################################################
10152 11:41:44.809864
10153 11:41:45.333699 01700000 ################################################################
10154 11:41:45.333855
10155 11:41:45.880516 01780000 ################################################################
10156 11:41:45.880679
10157 11:41:46.462151 01800000 ################################################################
10158 11:41:46.462700
10159 11:41:47.138190 01880000 ################################################################
10160 11:41:47.138786
10161 11:41:47.836426 01900000 ################################################################
10162 11:41:47.836943
10163 11:41:48.549843 01980000 ################################################################
10164 11:41:48.550390
10165 11:41:49.161317 01a00000 ################################################################
10166 11:41:49.161468
10167 11:41:49.819210 01a80000 ################################################################
10168 11:41:49.819723
10169 11:41:50.493634 01b00000 ################################################################
10170 11:41:50.493785
10171 11:41:51.055144 01b80000 ################################################################
10172 11:41:51.055297
10173 11:41:51.590024 01c00000 ################################################################
10174 11:41:51.590260
10175 11:41:52.126823 01c80000 ################################################################
10176 11:41:52.127031
10177 11:41:52.670852 01d00000 ################################################################
10178 11:41:52.671008
10179 11:41:53.195364 01d80000 ################################################################
10180 11:41:53.195530
10181 11:41:53.458958 01e00000 ################################# done.
10182 11:41:53.461959
10183 11:41:53.462073 The bootfile was 31722422 bytes long.
10184 11:41:53.465322
10185 11:41:53.465427 Sending tftp read request... done.
10186 11:41:53.465498
10187 11:41:53.468709 Waiting for the transfer...
10188 11:41:53.468844
10189 11:41:53.471802 00000000 # done.
10190 11:41:53.471961
10191 11:41:53.478410 Command line loaded dynamically from TFTP file: 10742201/tftp-deploy-nwrhfab6/kernel/cmdline
10192 11:41:53.478549
10193 11:41:53.491604 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10194 11:41:53.491763
10195 11:41:53.491867 Loading FIT.
10196 11:41:53.491959
10197 11:41:53.495180 Image ramdisk-1 has 21230103 bytes.
10198 11:41:53.495292
10199 11:41:53.498500 Image fdt-1 has 46924 bytes.
10200 11:41:53.498613
10201 11:41:53.501630 Image kernel-1 has 10443363 bytes.
10202 11:41:53.501751
10203 11:41:53.508332 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10204 11:41:53.508475
10205 11:41:53.528258 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10206 11:41:53.528402
10207 11:41:53.531393 Choosing best match conf-1 for compat google,spherion-rev2.
10208 11:41:53.536201
10209 11:41:53.541138 Connected to device vid:did:rid of 1ae0:0028:00
10210 11:41:53.549006
10211 11:41:53.552522 tpm_get_response: command 0x17b, return code 0x0
10212 11:41:53.552632
10213 11:41:53.556063 ec_init: CrosEC protocol v3 supported (256, 248)
10214 11:41:53.559342
10215 11:41:53.562850 tpm_cleanup: add release locality here.
10216 11:41:53.562974
10217 11:41:53.563073 Shutting down all USB controllers.
10218 11:41:53.566355
10219 11:41:53.566469 Removing current net device
10220 11:41:53.566566
10221 11:41:53.572822 Exiting depthcharge with code 4 at timestamp: 69824023
10222 11:41:53.572980
10223 11:41:53.576021 LZMA decompressing kernel-1 to 0x821a6718
10224 11:41:53.576150
10225 11:41:53.579308 LZMA decompressing kernel-1 to 0x40000000
10226 11:41:54.890332
10227 11:41:54.890500 jumping to kernel
10228 11:41:54.891174 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10229 11:41:54.891278 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10230 11:41:54.891360 Setting prompt string to ['Linux version [0-9]']
10231 11:41:54.891446 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10232 11:41:54.891531 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10233 11:41:54.972286
10234 11:41:54.976237 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10235 11:41:54.979343 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10236 11:41:54.979452 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10237 11:41:54.979551 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10238 11:41:54.979635 Using line separator: #'\n'#
10239 11:41:54.979699 No login prompt set.
10240 11:41:54.979764 Parsing kernel messages
10241 11:41:54.979822 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10242 11:41:54.979930 [login-action] Waiting for messages, (timeout 00:03:43)
10243 11:41:54.998920 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10244 11:41:55.002547 [ 0.000000] random: crng init done
10245 11:41:55.005683 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10246 11:41:55.009209 [ 0.000000] efi: UEFI not found.
10247 11:41:55.018538 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10248 11:41:55.025023 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10249 11:41:55.035137 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10250 11:41:55.045101 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10251 11:41:55.051268 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10252 11:41:55.054870 [ 0.000000] printk: bootconsole [mtk8250] enabled
10253 11:41:55.063460 [ 0.000000] NUMA: No NUMA configuration found
10254 11:41:55.070286 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10255 11:41:55.076664 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10256 11:41:55.076810 [ 0.000000] Zone ranges:
10257 11:41:55.083581 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10258 11:41:55.086523 [ 0.000000] DMA32 empty
10259 11:41:55.092875 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10260 11:41:55.096508 [ 0.000000] Movable zone start for each node
10261 11:41:55.099663 [ 0.000000] Early memory node ranges
10262 11:41:55.106267 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10263 11:41:55.112505 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10264 11:41:55.119436 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10265 11:41:55.125789 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10266 11:41:55.132812 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10267 11:41:55.138970 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10268 11:41:55.196329 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10269 11:41:55.202776 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10270 11:41:55.209823 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10271 11:41:55.212766 [ 0.000000] psci: probing for conduit method from DT.
10272 11:41:55.219041 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10273 11:41:55.222529 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10274 11:41:55.228911 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10275 11:41:55.232441 [ 0.000000] psci: SMC Calling Convention v1.2
10276 11:41:55.239099 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10277 11:41:55.242362 [ 0.000000] Detected VIPT I-cache on CPU0
10278 11:41:55.248704 [ 0.000000] CPU features: detected: GIC system register CPU interface
10279 11:41:55.255628 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10280 11:41:55.262371 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10281 11:41:55.268891 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10282 11:41:55.278633 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10283 11:41:55.284873 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10284 11:41:55.288381 [ 0.000000] alternatives: applying boot alternatives
10285 11:41:55.295016 [ 0.000000] Fallback order for Node 0: 0
10286 11:41:55.301738 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10287 11:41:55.304873 [ 0.000000] Policy zone: Normal
10288 11:41:55.314397 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10289 11:41:55.327563 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10290 11:41:55.338192 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10291 11:41:55.347772 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10292 11:41:55.354347 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10293 11:41:55.357767 <6>[ 0.000000] software IO TLB: area num 8.
10294 11:41:55.414177 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10295 11:41:55.563786 <6>[ 0.000000] Memory: 7950424K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 402344K reserved, 32768K cma-reserved)
10296 11:41:55.570006 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10297 11:41:55.576633 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10298 11:41:55.579982 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10299 11:41:55.586620 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10300 11:41:55.593058 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10301 11:41:55.596760 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10302 11:41:55.606257 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10303 11:41:55.613161 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10304 11:41:55.619599 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10305 11:41:55.626295 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10306 11:41:55.629433 <6>[ 0.000000] GICv3: 608 SPIs implemented
10307 11:41:55.632676 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10308 11:41:55.638965 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10309 11:41:55.642735 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10310 11:41:55.649434 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10311 11:41:55.662121 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10312 11:41:55.675447 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10313 11:41:55.682067 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10314 11:41:55.690074 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10315 11:41:55.703676 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10316 11:41:55.709619 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10317 11:41:55.716470 <6>[ 0.009176] Console: colour dummy device 80x25
10318 11:41:55.726137 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10319 11:41:55.733200 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10320 11:41:55.736404 <6>[ 0.029247] LSM: Security Framework initializing
10321 11:41:55.742970 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10322 11:41:55.753199 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10323 11:41:55.762913 <6>[ 0.051469] cblist_init_generic: Setting adjustable number of callback queues.
10324 11:41:55.765827 <6>[ 0.058922] cblist_init_generic: Setting shift to 3 and lim to 1.
10325 11:41:55.772959 <6>[ 0.065262] cblist_init_generic: Setting shift to 3 and lim to 1.
10326 11:41:55.779566 <6>[ 0.071668] rcu: Hierarchical SRCU implementation.
10327 11:41:55.785627 <6>[ 0.076712] rcu: Max phase no-delay instances is 1000.
10328 11:41:55.791983 <6>[ 0.083765] EFI services will not be available.
10329 11:41:55.795382 <6>[ 0.088739] smp: Bringing up secondary CPUs ...
10330 11:41:55.803561 <6>[ 0.093792] Detected VIPT I-cache on CPU1
10331 11:41:55.810255 <6>[ 0.093865] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10332 11:41:55.817156 <6>[ 0.093896] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10333 11:41:55.819981 <6>[ 0.094231] Detected VIPT I-cache on CPU2
10334 11:41:55.826795 <6>[ 0.094286] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10335 11:41:55.836407 <6>[ 0.094302] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10336 11:41:55.839517 <6>[ 0.094563] Detected VIPT I-cache on CPU3
10337 11:41:55.846196 <6>[ 0.094612] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10338 11:41:55.853230 <6>[ 0.094626] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10339 11:41:55.860092 <6>[ 0.094934] CPU features: detected: Spectre-v4
10340 11:41:55.862936 <6>[ 0.094941] CPU features: detected: Spectre-BHB
10341 11:41:55.866345 <6>[ 0.094948] Detected PIPT I-cache on CPU4
10342 11:41:55.872707 <6>[ 0.095007] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10343 11:41:55.879384 <6>[ 0.095024] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10344 11:41:55.885615 <6>[ 0.095322] Detected PIPT I-cache on CPU5
10345 11:41:55.892686 <6>[ 0.095385] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10346 11:41:55.898969 <6>[ 0.095402] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10347 11:41:55.902511 <6>[ 0.095688] Detected PIPT I-cache on CPU6
10348 11:41:55.912194 <6>[ 0.095752] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10349 11:41:55.918954 <6>[ 0.095768] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10350 11:41:55.921885 <6>[ 0.096069] Detected PIPT I-cache on CPU7
10351 11:41:55.928640 <6>[ 0.096134] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10352 11:41:55.934930 <6>[ 0.096150] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10353 11:41:55.938463 <6>[ 0.096200] smp: Brought up 1 node, 8 CPUs
10354 11:41:55.944963 <6>[ 0.237486] SMP: Total of 8 processors activated.
10355 11:41:55.951830 <6>[ 0.242408] CPU features: detected: 32-bit EL0 Support
10356 11:41:55.958210 <6>[ 0.247770] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10357 11:41:55.964920 <6>[ 0.256570] CPU features: detected: Common not Private translations
10358 11:41:55.971527 <6>[ 0.263046] CPU features: detected: CRC32 instructions
10359 11:41:55.977875 <6>[ 0.268397] CPU features: detected: RCpc load-acquire (LDAPR)
10360 11:41:55.981221 <6>[ 0.274357] CPU features: detected: LSE atomic instructions
10361 11:41:55.987506 <6>[ 0.280174] CPU features: detected: Privileged Access Never
10362 11:41:55.994508 <6>[ 0.285954] CPU features: detected: RAS Extension Support
10363 11:41:56.000974 <6>[ 0.291562] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10364 11:41:56.004259 <6>[ 0.298784] CPU: All CPU(s) started at EL2
10365 11:41:56.010889 <6>[ 0.303100] alternatives: applying system-wide alternatives
10366 11:41:56.021487 <6>[ 0.313809] devtmpfs: initialized
10367 11:41:56.036745 <6>[ 0.322673] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10368 11:41:56.043270 <6>[ 0.332634] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10369 11:41:56.049884 <6>[ 0.340853] pinctrl core: initialized pinctrl subsystem
10370 11:41:56.052851 <6>[ 0.347526] DMI not present or invalid.
10371 11:41:56.059892 <6>[ 0.351935] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10372 11:41:56.069505 <6>[ 0.358802] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10373 11:41:56.076147 <6>[ 0.366380] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10374 11:41:56.086201 <6>[ 0.374600] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10375 11:41:56.089029 <6>[ 0.382842] audit: initializing netlink subsys (disabled)
10376 11:41:56.099314 <5>[ 0.388536] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10377 11:41:56.105746 <6>[ 0.389244] thermal_sys: Registered thermal governor 'step_wise'
10378 11:41:56.112470 <6>[ 0.396499] thermal_sys: Registered thermal governor 'power_allocator'
10379 11:41:56.115446 <6>[ 0.402753] cpuidle: using governor menu
10380 11:41:56.122947 <6>[ 0.413715] NET: Registered PF_QIPCRTR protocol family
10381 11:41:56.129045 <6>[ 0.419193] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10382 11:41:56.135479 <6>[ 0.426292] ASID allocator initialised with 32768 entries
10383 11:41:56.138475 <6>[ 0.432857] Serial: AMBA PL011 UART driver
10384 11:41:56.149147 <4>[ 0.441597] Trying to register duplicate clock ID: 134
10385 11:41:56.205313 <6>[ 0.501099] KASLR enabled
10386 11:41:56.219388 <6>[ 0.508904] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10387 11:41:56.226567 <6>[ 0.515918] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10388 11:41:56.232585 <6>[ 0.522407] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10389 11:41:56.239229 <6>[ 0.529411] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10390 11:41:56.245654 <6>[ 0.535899] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10391 11:41:56.252538 <6>[ 0.542905] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10392 11:41:56.258786 <6>[ 0.549392] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10393 11:41:56.265643 <6>[ 0.556396] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10394 11:41:56.268866 <6>[ 0.563908] ACPI: Interpreter disabled.
10395 11:41:56.277554 <6>[ 0.570320] iommu: Default domain type: Translated
10396 11:41:56.284663 <6>[ 0.575431] iommu: DMA domain TLB invalidation policy: strict mode
10397 11:41:56.287344 <5>[ 0.582086] SCSI subsystem initialized
10398 11:41:56.293992 <6>[ 0.586234] usbcore: registered new interface driver usbfs
10399 11:41:56.300783 <6>[ 0.591969] usbcore: registered new interface driver hub
10400 11:41:56.303900 <6>[ 0.597523] usbcore: registered new device driver usb
10401 11:41:56.310746 <6>[ 0.603605] pps_core: LinuxPPS API ver. 1 registered
10402 11:41:56.320462 <6>[ 0.608797] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10403 11:41:56.323974 <6>[ 0.618141] PTP clock support registered
10404 11:41:56.327118 <6>[ 0.622383] EDAC MC: Ver: 3.0.0
10405 11:41:56.334880 <6>[ 0.627534] FPGA manager framework
10406 11:41:56.341203 <6>[ 0.631214] Advanced Linux Sound Architecture Driver Initialized.
10407 11:41:56.344863 <6>[ 0.637993] vgaarb: loaded
10408 11:41:56.351083 <6>[ 0.641145] clocksource: Switched to clocksource arch_sys_counter
10409 11:41:56.354592 <5>[ 0.647583] VFS: Disk quotas dquot_6.6.0
10410 11:41:56.361196 <6>[ 0.651768] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10411 11:41:56.364390 <6>[ 0.658958] pnp: PnP ACPI: disabled
10412 11:41:56.373202 <6>[ 0.665698] NET: Registered PF_INET protocol family
10413 11:41:56.382763 <6>[ 0.671304] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10414 11:41:56.394430 <6>[ 0.683607] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10415 11:41:56.403996 <6>[ 0.692421] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10416 11:41:56.410292 <6>[ 0.700390] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10417 11:41:56.420452 <6>[ 0.709089] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10418 11:41:56.427246 <6>[ 0.718833] TCP: Hash tables configured (established 65536 bind 65536)
10419 11:41:56.433487 <6>[ 0.725690] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10420 11:41:56.443709 <6>[ 0.732887] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10421 11:41:56.450130 <6>[ 0.740590] NET: Registered PF_UNIX/PF_LOCAL protocol family
10422 11:41:56.456595 <6>[ 0.746754] RPC: Registered named UNIX socket transport module.
10423 11:41:56.460023 <6>[ 0.752908] RPC: Registered udp transport module.
10424 11:41:56.466834 <6>[ 0.757841] RPC: Registered tcp transport module.
10425 11:41:56.472986 <6>[ 0.762774] RPC: Registered tcp NFSv4.1 backchannel transport module.
10426 11:41:56.476478 <6>[ 0.769443] PCI: CLS 0 bytes, default 64
10427 11:41:56.479952 <6>[ 0.773787] Unpacking initramfs...
10428 11:41:56.489827 <6>[ 0.777908] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10429 11:41:56.496197 <6>[ 0.786558] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10430 11:41:56.503188 <6>[ 0.795419] kvm [1]: IPA Size Limit: 40 bits
10431 11:41:56.506497 <6>[ 0.799944] kvm [1]: GICv3: no GICV resource entry
10432 11:41:56.513300 <6>[ 0.804965] kvm [1]: disabling GICv2 emulation
10433 11:41:56.519784 <6>[ 0.809659] kvm [1]: GIC system register CPU interface enabled
10434 11:41:56.522542 <6>[ 0.815829] kvm [1]: vgic interrupt IRQ18
10435 11:41:56.526073 <6>[ 0.820191] kvm [1]: VHE mode initialized successfully
10436 11:41:56.534093 <5>[ 0.826618] Initialise system trusted keyrings
10437 11:41:56.540223 <6>[ 0.831407] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10438 11:41:56.548718 <6>[ 0.841509] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10439 11:41:56.555182 <5>[ 0.847899] NFS: Registering the id_resolver key type
10440 11:41:56.558632 <5>[ 0.853226] Key type id_resolver registered
10441 11:41:56.565544 <5>[ 0.857640] Key type id_legacy registered
10442 11:41:56.571656 <6>[ 0.861921] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10443 11:41:56.578597 <6>[ 0.868840] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10444 11:41:56.585034 <6>[ 0.876539] 9p: Installing v9fs 9p2000 file system support
10445 11:41:56.620951 <5>[ 0.913412] Key type asymmetric registered
10446 11:41:56.624370 <5>[ 0.917742] Asymmetric key parser 'x509' registered
10447 11:41:56.633778 <6>[ 0.922887] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10448 11:41:56.637414 <6>[ 0.930498] io scheduler mq-deadline registered
10449 11:41:56.640147 <6>[ 0.935258] io scheduler kyber registered
10450 11:41:56.659241 <6>[ 0.952094] EINJ: ACPI disabled.
10451 11:41:56.691492 <4>[ 0.977881] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10452 11:41:56.701459 <4>[ 0.988498] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10453 11:41:56.716607 <6>[ 1.009455] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10454 11:41:56.724952 <6>[ 1.017469] printk: console [ttyS0] disabled
10455 11:41:56.752816 <6>[ 1.042124] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10456 11:41:56.759110 <6>[ 1.051601] printk: console [ttyS0] enabled
10457 11:41:56.762497 <6>[ 1.051601] printk: console [ttyS0] enabled
10458 11:41:56.769277 <6>[ 1.060494] printk: bootconsole [mtk8250] disabled
10459 11:41:56.772745 <6>[ 1.060494] printk: bootconsole [mtk8250] disabled
10460 11:41:56.779156 <6>[ 1.071763] SuperH (H)SCI(F) driver initialized
10461 11:41:56.782406 <6>[ 1.077050] msm_serial: driver initialized
10462 11:41:56.796729 <6>[ 1.086080] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10463 11:41:56.806402 <6>[ 1.094630] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10464 11:41:56.813248 <6>[ 1.103173] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10465 11:41:56.823148 <6>[ 1.111803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10466 11:41:56.833255 <6>[ 1.120519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10467 11:41:56.839938 <6>[ 1.129233] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10468 11:41:56.849881 <6>[ 1.137773] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10469 11:41:56.856398 <6>[ 1.146583] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10470 11:41:56.866513 <6>[ 1.155128] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10471 11:41:56.878507 <6>[ 1.170939] loop: module loaded
10472 11:41:56.884792 <6>[ 1.176943] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10473 11:41:56.908206 <4>[ 1.200467] mtk-pmic-keys: Failed to locate of_node [id: -1]
10474 11:41:56.914599 <6>[ 1.207299] megasas: 07.719.03.00-rc1
10475 11:41:56.924214 <6>[ 1.216932] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10476 11:41:56.931654 <6>[ 1.224530] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10477 11:41:56.948885 <6>[ 1.241280] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10478 11:41:57.005056 <6>[ 1.291488] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10479 11:41:57.413923 <6>[ 1.707009] Freeing initrd memory: 20728K
10480 11:41:57.429826 <6>[ 1.722757] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10481 11:41:57.441294 <6>[ 1.733976] tun: Universal TUN/TAP device driver, 1.6
10482 11:41:57.444426 <6>[ 1.740040] thunder_xcv, ver 1.0
10483 11:41:57.447732 <6>[ 1.743546] thunder_bgx, ver 1.0
10484 11:41:57.451264 <6>[ 1.747041] nicpf, ver 1.0
10485 11:41:57.461461 <6>[ 1.751057] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10486 11:41:57.465047 <6>[ 1.758532] hns3: Copyright (c) 2017 Huawei Corporation.
10487 11:41:57.471973 <6>[ 1.764119] hclge is initializing
10488 11:41:57.474795 <6>[ 1.767707] e1000: Intel(R) PRO/1000 Network Driver
10489 11:41:57.481529 <6>[ 1.772835] e1000: Copyright (c) 1999-2006 Intel Corporation.
10490 11:41:57.484586 <6>[ 1.778850] e1000e: Intel(R) PRO/1000 Network Driver
10491 11:41:57.491082 <6>[ 1.784066] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10492 11:41:57.498170 <6>[ 1.790255] igb: Intel(R) Gigabit Ethernet Network Driver
10493 11:41:57.504361 <6>[ 1.795905] igb: Copyright (c) 2007-2014 Intel Corporation.
10494 11:41:57.511480 <6>[ 1.801742] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10495 11:41:57.518041 <6>[ 1.808260] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10496 11:41:57.520857 <6>[ 1.814722] sky2: driver version 1.30
10497 11:41:57.527746 <6>[ 1.819706] VFIO - User Level meta-driver version: 0.3
10498 11:41:57.535106 <6>[ 1.827928] usbcore: registered new interface driver usb-storage
10499 11:41:57.541477 <6>[ 1.834377] usbcore: registered new device driver onboard-usb-hub
10500 11:41:57.550775 <6>[ 1.843493] mt6397-rtc mt6359-rtc: registered as rtc0
10501 11:41:57.560165 <6>[ 1.848960] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:41:57 UTC (1686829317)
10502 11:41:57.563936 <6>[ 1.858537] i2c_dev: i2c /dev entries driver
10503 11:41:57.581031 <6>[ 1.870361] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10504 11:41:57.588029 <6>[ 1.880612] sdhci: Secure Digital Host Controller Interface driver
10505 11:41:57.594421 <6>[ 1.887051] sdhci: Copyright(c) Pierre Ossman
10506 11:41:57.601003 <6>[ 1.892445] Synopsys Designware Multimedia Card Interface Driver
10507 11:41:57.604233 <6>[ 1.899086] mmc0: CQHCI version 5.10
10508 11:41:57.611291 <6>[ 1.899609] sdhci-pltfm: SDHCI platform and OF driver helper
10509 11:41:57.618183 <6>[ 1.911033] ledtrig-cpu: registered to indicate activity on CPUs
10510 11:41:57.628970 <6>[ 1.918427] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10511 11:41:57.632906 <6>[ 1.925833] usbcore: registered new interface driver usbhid
10512 11:41:57.638852 <6>[ 1.931665] usbhid: USB HID core driver
10513 11:41:57.645764 <6>[ 1.935902] spi_master spi0: will run message pump with realtime priority
10514 11:41:57.692294 <6>[ 1.978597] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10515 11:41:57.711560 <6>[ 1.993891] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10516 11:41:57.714832 <6>[ 2.007471] mmc0: Command Queue Engine enabled
10517 11:41:57.721596 <6>[ 2.008813] cros-ec-spi spi0.0: Chrome EC device registered
10518 11:41:57.725498 <6>[ 2.012222] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10519 11:41:57.732178 <6>[ 2.025402] mmcblk0: mmc0:0001 DA4128 116 GiB
10520 11:41:57.746447 <6>[ 2.036009] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10521 11:41:57.753566 <6>[ 2.036662] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10522 11:41:57.759662 <6>[ 2.047485] NET: Registered PF_PACKET protocol family
10523 11:41:57.762931 <6>[ 2.052626] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10524 11:41:57.770018 <6>[ 2.056683] 9pnet: Installing 9P2000 support
10525 11:41:57.773102 <6>[ 2.062488] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10526 11:41:57.779576 <5>[ 2.066356] Key type dns_resolver registered
10527 11:41:57.786709 <6>[ 2.072223] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10528 11:41:57.789763 <6>[ 2.076677] registered taskstats version 1
10529 11:41:57.793630 <5>[ 2.086969] Loading compiled-in X.509 certificates
10530 11:41:57.827778 <4>[ 2.113761] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 11:41:57.837765 <4>[ 2.124486] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10532 11:41:57.848057 <3>[ 2.137539] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10533 11:41:57.860901 <6>[ 2.153941] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10534 11:41:57.868022 <6>[ 2.160765] xhci-mtk 11200000.usb: xHCI Host Controller
10535 11:41:57.874872 <6>[ 2.166274] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10536 11:41:57.885053 <6>[ 2.174228] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10537 11:41:57.891377 <6>[ 2.183687] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10538 11:41:57.898018 <6>[ 2.189779] xhci-mtk 11200000.usb: xHCI Host Controller
10539 11:41:57.904895 <6>[ 2.195266] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10540 11:41:57.911754 <6>[ 2.202920] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10541 11:41:57.918152 <6>[ 2.210828] hub 1-0:1.0: USB hub found
10542 11:41:57.921353 <6>[ 2.214870] hub 1-0:1.0: 1 port detected
10543 11:41:57.931453 <6>[ 2.219238] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10544 11:41:57.934662 <6>[ 2.228051] hub 2-0:1.0: USB hub found
10545 11:41:57.937783 <6>[ 2.232100] hub 2-0:1.0: 1 port detected
10546 11:41:57.946424 <6>[ 2.239524] mtk-msdc 11f70000.mmc: Got CD GPIO
10547 11:41:57.964401 <6>[ 2.253658] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10548 11:41:57.970514 <6>[ 2.261680] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10549 11:41:57.980911 <4>[ 2.269660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10550 11:41:57.990719 <6>[ 2.279314] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10551 11:41:57.997295 <6>[ 2.287396] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10552 11:41:58.004299 <6>[ 2.295396] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10553 11:41:58.013667 <6>[ 2.303311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10554 11:41:58.020372 <6>[ 2.311133] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10555 11:41:58.030182 <6>[ 2.318954] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10556 11:41:58.040042 <6>[ 2.329562] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10557 11:41:58.050040 <6>[ 2.337943] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10558 11:41:58.056568 <6>[ 2.346287] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10559 11:41:58.066493 <6>[ 2.354630] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10560 11:41:58.072708 <6>[ 2.362973] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10561 11:41:58.083098 <6>[ 2.371316] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10562 11:41:58.089386 <6>[ 2.379658] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10563 11:41:58.099612 <6>[ 2.388002] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10564 11:41:58.106086 <6>[ 2.396345] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10565 11:41:58.116693 <6>[ 2.404688] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10566 11:41:58.122236 <6>[ 2.413031] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10567 11:41:58.133037 <6>[ 2.421375] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10568 11:41:58.139330 <6>[ 2.429725] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10569 11:41:58.149341 <6>[ 2.438070] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10570 11:41:58.155570 <6>[ 2.446418] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10571 11:41:58.162140 <6>[ 2.455301] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10572 11:41:58.169807 <6>[ 2.462735] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10573 11:41:58.176907 <6>[ 2.469778] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10574 11:41:58.187047 <6>[ 2.476881] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10575 11:41:58.193846 <6>[ 2.484165] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10576 11:41:58.203896 <6>[ 2.491119] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10577 11:41:58.210662 <6>[ 2.500272] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10578 11:41:58.220369 <6>[ 2.509399] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10579 11:41:58.230154 <6>[ 2.518702] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10580 11:41:58.240559 <6>[ 2.528176] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10581 11:41:58.250571 <6>[ 2.537649] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10582 11:41:58.256947 <6>[ 2.546777] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10583 11:41:58.266710 <6>[ 2.556250] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10584 11:41:58.276576 <6>[ 2.565376] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10585 11:41:58.287124 <6>[ 2.574678] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10586 11:41:58.296307 <6>[ 2.584843] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10587 11:41:58.307193 <6>[ 2.596882] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10588 11:41:58.328443 <6>[ 2.617542] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10589 11:41:58.356930 <6>[ 2.649750] hub 2-1:1.0: USB hub found
10590 11:41:58.360098 <6>[ 2.654262] hub 2-1:1.0: 3 ports detected
10591 11:41:58.479676 <6>[ 2.769391] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10592 11:41:58.632600 <6>[ 2.925552] hub 1-1:1.0: USB hub found
10593 11:41:58.635954 <6>[ 2.929914] hub 1-1:1.0: 4 ports detected
10594 11:41:58.712199 <6>[ 3.001660] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10595 11:41:58.955838 <6>[ 3.245420] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10596 11:41:59.089244 <6>[ 3.381722] hub 1-1.4:1.0: USB hub found
10597 11:41:59.091810 <6>[ 3.386411] hub 1-1.4:1.0: 2 ports detected
10598 11:41:59.387435 <6>[ 3.677419] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10599 11:41:59.579624 <6>[ 3.869448] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10600 11:42:10.592920 <6>[ 14.889977] ALSA device list:
10601 11:42:10.598761 <6>[ 14.893233] No soundcards found.
10602 11:42:10.610945 <6>[ 14.905597] Freeing unused kernel memory: 8384K
10603 11:42:10.614314 <6>[ 14.910494] Run /init as init process
10604 11:42:10.641567 Starting syslogd: OK
10605 11:42:10.645434 Starting klogd: OK
10606 11:42:10.654235 Running sysctl: OK
10607 11:42:10.663868 Populating /dev using udev: <30>[ 14.957483] udevd[190]: starting version 3.2.9
10608 11:42:10.670844 <27>[ 14.965309] udevd[190]: specified user 'tss' unknown
10609 11:42:10.677555 <27>[ 14.970832] udevd[190]: specified group 'tss' unknown
10610 11:42:10.681044 <30>[ 14.977239] udevd[191]: starting eudev-3.2.9
10611 11:42:10.713365 <27>[ 15.007609] udevd[191]: specified user 'tss' unknown
10612 11:42:10.719688 <27>[ 15.013000] udevd[191]: specified group 'tss' unknown
10613 11:42:10.869305 <6>[ 15.160474] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10614 11:42:10.883423 <6>[ 15.177735] remoteproc remoteproc0: scp is available
10615 11:42:10.893683 <4>[ 15.183491] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10616 11:42:10.900318 <6>[ 15.193682] remoteproc remoteproc0: powering up scp
10617 11:42:10.914266 <4>[ 15.205341] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10618 11:42:10.920827 <3>[ 15.215394] remoteproc remoteproc0: request_firmware failed: -2
10619 11:42:10.935715 <6>[ 15.226691] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10620 11:42:10.942299 <6>[ 15.234362] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10621 11:42:10.952262 <6>[ 15.243078] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10622 11:42:10.989524 <3>[ 15.280805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 11:42:10.999883 <3>[ 15.289921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 11:42:11.006251 <3>[ 15.298448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 11:42:11.016844 <4>[ 15.307818] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10626 11:42:11.023613 <3>[ 15.311129] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 11:42:11.029983 <4>[ 15.315272] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10628 11:42:11.039566 <3>[ 15.323411] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 11:42:11.046441 <3>[ 15.339300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 11:42:11.053370 <6>[ 15.344931] usbcore: registered new interface driver r8152
10631 11:42:11.063152 <3>[ 15.348236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 11:42:11.066694 <6>[ 15.358269] mc: Linux media interface: v0.10
10633 11:42:11.073164 <3>[ 15.361311] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10634 11:42:11.082938 <6>[ 15.364489] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10635 11:42:11.089174 <6>[ 15.379825] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10636 11:42:11.095770 <3>[ 15.382028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 11:42:11.103161 <6>[ 15.384156] videodev: Linux video capture interface: v2.00
10638 11:42:11.109567 <6>[ 15.388526] pci_bus 0000:00: root bus resource [bus 00-ff]
10639 11:42:11.119781 <6>[ 15.393939] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10640 11:42:11.130023 <6>[ 15.394511] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10641 11:42:11.136269 <3>[ 15.396901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 11:42:11.143047 <6>[ 15.402356] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10643 11:42:11.152505 <6>[ 15.402369] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10644 11:42:11.159238 <6>[ 15.402499] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10645 11:42:11.169657 <3>[ 15.408166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 11:42:11.176024 <6>[ 15.418237] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10647 11:42:11.182680 <3>[ 15.427282] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10648 11:42:11.193190 <6>[ 15.429467] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10649 11:42:11.196061 <6>[ 15.435442] pci 0000:00:00.0: supports D1 D2
10650 11:42:11.206270 <6>[ 15.439736] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10651 11:42:11.212995 <3>[ 15.443044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10652 11:42:11.222494 <4>[ 15.450188] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10653 11:42:11.226484 <4>[ 15.450188] Fallback method does not support PEC.
10654 11:42:11.232757 <6>[ 15.452518] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10655 11:42:11.236653 <6>[ 15.453815] Bluetooth: Core ver 2.22
10656 11:42:11.242739 <6>[ 15.453818] usbcore: registered new interface driver cdc_ether
10657 11:42:11.252441 <6>[ 15.454740] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10658 11:42:11.259323 <6>[ 15.454886] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10659 11:42:11.265797 <6>[ 15.454918] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10660 11:42:11.272138 <6>[ 15.454940] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10661 11:42:11.279062 <6>[ 15.454958] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10662 11:42:11.285534 <6>[ 15.455098] pci 0000:01:00.0: supports D1 D2
10663 11:42:11.292692 <6>[ 15.455102] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10664 11:42:11.299152 <3>[ 15.459294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10665 11:42:11.305683 <6>[ 15.459813] usbcore: registered new interface driver r8153_ecm
10666 11:42:11.315423 <3>[ 15.467417] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10667 11:42:11.322290 <6>[ 15.467693] NET: Registered PF_BLUETOOTH protocol family
10668 11:42:11.328404 <6>[ 15.467697] Bluetooth: HCI device and connection manager initialized
10669 11:42:11.331820 <6>[ 15.467731] Bluetooth: HCI socket layer initialized
10670 11:42:11.338308 <6>[ 15.467746] Bluetooth: L2CAP socket layer initialized
10671 11:42:11.342007 <6>[ 15.467771] Bluetooth: SCO socket layer initialized
10672 11:42:11.351687 <4>[ 15.468323] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10673 11:42:11.358146 <4>[ 15.468333] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10674 11:42:11.368159 <6>[ 15.469259] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10675 11:42:11.374527 <6>[ 15.469312] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10676 11:42:11.381343 <6>[ 15.469319] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10677 11:42:11.391429 <6>[ 15.469334] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10678 11:42:11.397891 <6>[ 15.469350] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10679 11:42:11.408019 <6>[ 15.469366] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10680 11:42:11.411394 <6>[ 15.469382] pci 0000:00:00.0: PCI bridge to [bus 01]
10681 11:42:11.421089 <6>[ 15.469391] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10682 11:42:11.428007 <6>[ 15.469601] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10683 11:42:11.431435 <6>[ 15.470531] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10684 11:42:11.437604 <6>[ 15.470755] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10685 11:42:11.447474 <3>[ 15.475254] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 11:42:11.454503 <6>[ 15.476311] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10687 11:42:11.467332 <6>[ 15.477769] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10688 11:42:11.470930 <6>[ 15.477935] usbcore: registered new interface driver uvcvideo
10689 11:42:11.480843 <5>[ 15.494761] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10690 11:42:11.487216 <3>[ 15.494811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 11:42:11.497495 <3>[ 15.504560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10692 11:42:11.503856 <3>[ 15.512174] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 11:42:11.513608 <3>[ 15.512245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 11:42:11.517063 <6>[ 15.513314] r8152 2-1.3:1.0 eth0: v1.12.13
10695 11:42:11.523425 <6>[ 15.526949] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10696 11:42:11.530395 <6>[ 15.527044] usbcore: registered new interface driver btusb
10697 11:42:11.539925 <4>[ 15.527792] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10698 11:42:11.546746 <3>[ 15.527806] Bluetooth: hci0: Failed to load firmware file (-2)
10699 11:42:11.553634 <3>[ 15.527811] Bluetooth: hci0: Failed to set up firmware (-2)
10700 11:42:11.562833 <4>[ 15.527817] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10701 11:42:11.569789 <5>[ 15.551760] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10702 11:42:11.573070 <6>[ 15.562837] remoteproc remoteproc0: powering up scp
10703 11:42:11.582687 <4>[ 15.564896] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10704 11:42:11.592356 <4>[ 15.572165] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10705 11:42:11.598976 <6>[ 15.579602] cfg80211: failed to load regulatory.db
10706 11:42:11.602573 <3>[ 15.584124] remoteproc remoteproc0: request_firmware failed: -2
10707 11:42:11.612354 <6>[ 15.663500] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10708 11:42:11.618806 <3>[ 15.665755] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10709 11:42:11.625028 <6>[ 15.674099] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10710 11:42:11.650695 <6>[ 15.944671] mt7921e 0000:01:00.0: ASIC revision: 79610010
10711 11:42:11.758715 <4>[ 16.046037] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10712 11:42:11.766740 done
10713 11:42:11.781687 Saving random seed: OK
10714 11:42:11.797168 Starting network: OK
10715 11:42:11.836957 Starting dropbear sshd: <6>[ 16.131243] NET: Registered PF_INET6 protocol family
10716 11:42:11.843764 <6>[ 16.137453] Segment Routing with IPv6
10717 11:42:11.847212 <6>[ 16.141389] In-situ OAM (IOAM) with IPv6
10718 11:42:11.850596 OK
10719 11:42:11.860761 /bin/sh: can't access tty; job control turned off
10720 11:42:11.861672 Matched prompt #10: / #
10722 11:42:11.862731 Setting prompt string to ['/ #']
10723 11:42:11.863180 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10725 11:42:11.864307 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10726 11:42:11.864785 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
10727 11:42:11.865178 Setting prompt string to ['/ #']
10728 11:42:11.865521 Forcing a shell prompt, looking for ['/ #']
10730 11:42:11.916277 / #
10731 11:42:11.916852 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10732 11:42:11.917294 Waiting using forced prompt support (timeout 00:02:30)
10733 11:42:11.917797 <4>[ 16.168050] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10734 11:42:11.922579
10735 11:42:11.923479 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10736 11:42:11.924322 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10737 11:42:11.925106 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10738 11:42:11.925780 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
10739 11:42:11.926545 end: 2 depthcharge-action (duration 00:01:34) [common]
10740 11:42:11.927330 start: 3 lava-test-retry (timeout 00:01:00) [common]
10741 11:42:11.928140 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10742 11:42:11.928864 Using namespace: common
10744 11:42:12.029940 / # #
10745 11:42:12.030113 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10746 11:42:12.030229 #<4>[ 16.288005] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10747 11:42:12.035410
10748 11:42:12.035679 Using /lava-10742201
10750 11:42:12.135953 / # export SHELL=/bin/sh
10751 11:42:12.136150 export SHELL=/bin/sh<4>[ 16.407536] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10752 11:42:12.141204
10754 11:42:12.241844 / # . /lava-10742201/environment
10755 11:42:12.242489 . /lava-10742201/environment<4>[ 16.527799] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 11:42:12.248066
10758 11:42:12.349023 / # /lava-10742201/bin/lava-test-runner /lava-10742201/0
10759 11:42:12.349637 Test shell timeout: 10s (minimum of the action and connection timeout)
10760 11:42:12.360286 /lava-10742201/bin/lava-test-runner /lava-10742201/0<4>[ 16.647680] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 11:42:12.361055
10762 11:42:12.390392 + export 'TESTRUN_ID=0_dmesg'
10763 11:42:12.396682 +<8>[ 16.689344] <LAVA_SIGNAL_STARTRUN 0_dmesg 10742201_1.5.2.3.1>
10764 11:42:12.397364 Received signal: <STARTRUN> 0_dmesg 10742201_1.5.2.3.1
10765 11:42:12.397759 Starting test lava.0_dmesg (10742201_1.5.2.3.1)
10766 11:42:12.398181 Skipping test definition patterns.
10767 11:42:12.400388 cd /lava-10742201/0/tests/0_dmesg
10768 11:42:12.400894 + cat uuid
10769 11:42:12.403431 + UUID=10742201_1.5.2.3.1
10770 11:42:12.404247 + set +x
10771 11:42:12.410076 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10772 11:42:12.416391 <8>[ 16.708355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10773 11:42:12.417075 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10775 11:42:12.436673 <8>[ 16.727775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10776 11:42:12.437376 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10778 11:42:12.457934 <8>[ 16.748542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10779 11:42:12.458789 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10781 11:42:12.462057 + set +x
10782 11:42:12.465808 Received signal: <ENDRUN> 0_dmesg 10742201_1.5.2.3.1
10783 11:42:12.466412 Ending use of test pattern.
10784 11:42:12.466917 Ending test lava.0_dmesg (10742201_1.5.2.3.1), duration 0.07
10786 11:42:12.468962 <8>[ 16.759646] <LAVA_SIGNAL_ENDRUN 0_dmesg 10742201_1.5.2.3.1>
10787 11:42:12.481683 <LAVA_TEST_RUNNE<4>[ 16.768196] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 11:42:12.482129 R EXIT>
10789 11:42:12.600082 / # <4>[ 16.887774] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 11:42:12.719658 <4>[ 17.007785] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10791 11:42:12.839785 <4>[ 17.127761] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10792 11:42:13.079596 <3>[ 17.245535] mt7921e 0000:01:00.0: hardware init failed
10793 11:42:41.852518 <6>[ 46.153509] vpu: disabling
10794 11:42:41.855820 <6>[ 46.156571] vproc2: disabling
10795 11:42:41.859089 <6>[ 46.159857] vproc1: disabling
10796 11:42:41.862014 <6>[ 46.163118] vaud18: disabling
10797 11:42:41.869000 <6>[ 46.166526] vsram_others: disabling
10798 11:42:41.872348 <6>[ 46.170397] va09: disabling
10799 11:42:41.875175 <6>[ 46.173502] vsram_md: disabling
10800 11:42:41.878488 <6>[ 46.176988] Vgpu: disabling
10802 11:43:11.928491 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10804 11:43:11.928929 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10806 11:43:11.929232 end: 3 lava-test-retry (duration 00:01:00) [common]
10808 11:43:11.929685 Cleaning after the job
10809 11:43:11.929828 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/ramdisk
10810 11:43:11.933612 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/kernel
10811 11:43:11.948267 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/dtb
10812 11:43:11.948670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742201/tftp-deploy-nwrhfab6/modules
10813 11:43:11.956859 start: 5.1 power-off (timeout 00:00:30) [common]
10814 11:43:11.957342 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
10815 11:43:12.035246 >> Command sent successfully.
10816 11:43:12.038180 Returned 0 in 0 seconds
10817 11:43:12.138623 end: 5.1 power-off (duration 00:00:00) [common]
10819 11:43:12.138972 start: 5.2 read-feedback (timeout 00:10:00) [common]
10820 11:43:12.139260 Listened to connection for namespace 'common' for up to 1s
10821 11:43:13.140110 Finalising connection for namespace 'common'
10822 11:43:13.140298 Disconnecting from shell: Finalise
10823 11:43:13.240608 end: 5.2 read-feedback (duration 00:00:01) [common]
10824 11:43:13.240794 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742201
10825 11:43:13.288385 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742201
10826 11:43:13.288598 TestError: A test failed to run, look at the error message.