Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
- Errors: 2
1 11:39:50.108981 lava-dispatcher, installed at version: 2023.05.1
2 11:39:50.109213 start: 0 validate
3 11:39:50.109418 Start time: 2023-06-15 11:39:50.109407+00:00 (UTC)
4 11:39:50.109556 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:39:50.109698 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 11:39:50.378472 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:39:50.378677 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:40:14.907944 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:40:14.908117 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:40:15.168230 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:40:15.168407 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:40:15.988328 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:40:15.988507 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:40:18.992951 validate duration: 28.88
16 11:40:18.993247 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:40:18.993369 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:40:18.993496 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:40:18.993668 Not decompressing ramdisk as can be used compressed.
20 11:40:18.993792 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230609.0/arm64/initrd.cpio.gz
21 11:40:18.993891 saving as /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/ramdisk/initrd.cpio.gz
22 11:40:18.993991 total size: 4665598 (4MB)
23 11:40:19.244612 progress 0% (0MB)
24 11:40:19.246086 progress 5% (0MB)
25 11:40:19.247442 progress 10% (0MB)
26 11:40:19.248709 progress 15% (0MB)
27 11:40:19.250027 progress 20% (0MB)
28 11:40:19.251305 progress 25% (1MB)
29 11:40:19.252666 progress 30% (1MB)
30 11:40:19.253979 progress 35% (1MB)
31 11:40:19.255263 progress 40% (1MB)
32 11:40:19.256770 progress 45% (2MB)
33 11:40:19.258096 progress 50% (2MB)
34 11:40:19.259413 progress 55% (2MB)
35 11:40:19.260704 progress 60% (2MB)
36 11:40:19.262083 progress 65% (2MB)
37 11:40:19.263406 progress 70% (3MB)
38 11:40:19.264683 progress 75% (3MB)
39 11:40:19.266006 progress 80% (3MB)
40 11:40:19.267473 progress 85% (3MB)
41 11:40:19.268747 progress 90% (4MB)
42 11:40:19.270041 progress 95% (4MB)
43 11:40:19.271337 progress 100% (4MB)
44 11:40:19.271528 4MB downloaded in 0.28s (16.03MB/s)
45 11:40:19.271698 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:40:19.271996 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:40:19.272124 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:40:19.272254 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:40:19.272432 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:40:19.272533 saving as /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/kernel/Image
52 11:40:19.272633 total size: 47581696 (45MB)
53 11:40:19.272734 No compression specified
54 11:40:19.274345 progress 0% (0MB)
55 11:40:19.286725 progress 5% (2MB)
56 11:40:19.299156 progress 10% (4MB)
57 11:40:19.311812 progress 15% (6MB)
58 11:40:19.324403 progress 20% (9MB)
59 11:40:19.336782 progress 25% (11MB)
60 11:40:19.349167 progress 30% (13MB)
61 11:40:19.361854 progress 35% (15MB)
62 11:40:19.374687 progress 40% (18MB)
63 11:40:19.387147 progress 45% (20MB)
64 11:40:19.400049 progress 50% (22MB)
65 11:40:19.412628 progress 55% (24MB)
66 11:40:19.425327 progress 60% (27MB)
67 11:40:19.437712 progress 65% (29MB)
68 11:40:19.450238 progress 70% (31MB)
69 11:40:19.462976 progress 75% (34MB)
70 11:40:19.475333 progress 80% (36MB)
71 11:40:19.488310 progress 85% (38MB)
72 11:40:19.500898 progress 90% (40MB)
73 11:40:19.513399 progress 95% (43MB)
74 11:40:19.525753 progress 100% (45MB)
75 11:40:19.525926 45MB downloaded in 0.25s (179.15MB/s)
76 11:40:19.526097 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:40:19.526374 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:40:19.526502 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:40:19.526634 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:40:19.526791 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:40:19.526894 saving as /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/dtb/mt8192-asurada-spherion-r0.dtb
83 11:40:19.526994 total size: 46924 (0MB)
84 11:40:19.527095 No compression specified
85 11:40:19.528394 progress 69% (0MB)
86 11:40:19.528677 progress 100% (0MB)
87 11:40:19.528847 0MB downloaded in 0.00s (24.18MB/s)
88 11:40:19.528986 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:40:19.529242 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:40:19.529349 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:40:19.529450 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:40:19.529608 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230609.0/arm64/full.rootfs.tar.xz
94 11:40:19.529705 saving as /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/nfsrootfs/full.rootfs.tar
95 11:40:19.529808 total size: 125248124 (119MB)
96 11:40:19.529907 Using unxz to decompress xz
97 11:40:19.533541 progress 0% (0MB)
98 11:40:19.853222 progress 5% (6MB)
99 11:40:20.179434 progress 10% (11MB)
100 11:40:20.501594 progress 15% (17MB)
101 11:40:20.683747 progress 20% (23MB)
102 11:40:20.858796 progress 25% (29MB)
103 11:40:21.208445 progress 30% (35MB)
104 11:40:21.559224 progress 35% (41MB)
105 11:40:21.935745 progress 40% (47MB)
106 11:40:22.304954 progress 45% (53MB)
107 11:40:22.688358 progress 50% (59MB)
108 11:40:23.043428 progress 55% (65MB)
109 11:40:23.408077 progress 60% (71MB)
110 11:40:23.750123 progress 65% (77MB)
111 11:40:24.112013 progress 70% (83MB)
112 11:40:24.488481 progress 75% (89MB)
113 11:40:24.912310 progress 80% (95MB)
114 11:40:25.704671 progress 85% (101MB)
115 11:40:25.954148 progress 90% (107MB)
116 11:40:26.292992 progress 95% (113MB)
117 11:40:26.671106 progress 100% (119MB)
118 11:40:26.676205 119MB downloaded in 7.15s (16.71MB/s)
119 11:40:26.676508 end: 1.4.1 http-download (duration 00:00:07) [common]
121 11:40:26.676810 end: 1.4 download-retry (duration 00:00:07) [common]
122 11:40:26.676899 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:40:26.677017 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:40:26.677172 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:40:26.677242 saving as /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/modules/modules.tar
126 11:40:26.677304 total size: 8555256 (8MB)
127 11:40:26.677367 Using unxz to decompress xz
128 11:40:26.937928 progress 0% (0MB)
129 11:40:26.960086 progress 5% (0MB)
130 11:40:26.984541 progress 10% (0MB)
131 11:40:27.008135 progress 15% (1MB)
132 11:40:27.033083 progress 20% (1MB)
133 11:40:27.057360 progress 25% (2MB)
134 11:40:27.080182 progress 30% (2MB)
135 11:40:27.105391 progress 35% (2MB)
136 11:40:27.130300 progress 40% (3MB)
137 11:40:27.153924 progress 45% (3MB)
138 11:40:27.181234 progress 50% (4MB)
139 11:40:27.205874 progress 55% (4MB)
140 11:40:27.231527 progress 60% (4MB)
141 11:40:27.257095 progress 65% (5MB)
142 11:40:27.282375 progress 70% (5MB)
143 11:40:27.306357 progress 75% (6MB)
144 11:40:27.329527 progress 80% (6MB)
145 11:40:27.353679 progress 85% (6MB)
146 11:40:27.384362 progress 90% (7MB)
147 11:40:27.411732 progress 95% (7MB)
148 11:40:27.436572 progress 100% (8MB)
149 11:40:27.440838 8MB downloaded in 0.76s (10.69MB/s)
150 11:40:27.441116 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:40:27.441380 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:40:27.441472 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 11:40:27.441582 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 11:40:29.462659 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10742196/extract-nfsrootfs-p6y5mcne
156 11:40:29.462863 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:40:29.462966 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 11:40:29.463131 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n
159 11:40:29.463260 makedir: /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin
160 11:40:29.463362 makedir: /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/tests
161 11:40:29.463493 makedir: /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/results
162 11:40:29.463593 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-add-keys
163 11:40:29.463728 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-add-sources
164 11:40:29.463850 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-background-process-start
165 11:40:29.463972 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-background-process-stop
166 11:40:29.464091 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-common-functions
167 11:40:29.464209 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-echo-ipv4
168 11:40:29.464330 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-install-packages
169 11:40:29.464448 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-installed-packages
170 11:40:29.464564 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-os-build
171 11:40:29.464683 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-probe-channel
172 11:40:29.464805 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-probe-ip
173 11:40:29.464925 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-target-ip
174 11:40:29.465040 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-target-mac
175 11:40:29.465156 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-target-storage
176 11:40:29.465272 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-test-case
177 11:40:29.465388 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-test-event
178 11:40:29.465503 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-test-feedback
179 11:40:29.465618 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-test-raise
180 11:40:29.465732 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-test-reference
181 11:40:29.465847 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-test-runner
182 11:40:29.465962 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-test-set
183 11:40:29.466077 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-test-shell
184 11:40:29.466200 Updating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-install-packages (oe)
185 11:40:29.517250 Updating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/bin/lava-installed-packages (oe)
186 11:40:29.517435 Creating /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/environment
187 11:40:29.517539 LAVA metadata
188 11:40:29.517612 - LAVA_JOB_ID=10742196
189 11:40:29.517677 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:40:29.517785 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 11:40:29.517851 skipped lava-vland-overlay
192 11:40:29.517926 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:40:29.518005 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 11:40:29.518066 skipped lava-multinode-overlay
195 11:40:29.518137 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:40:29.518214 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 11:40:29.518288 Loading test definitions
198 11:40:29.518381 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 11:40:29.518451 Using /lava-10742196 at stage 0
200 11:40:29.518753 uuid=10742196_1.6.2.3.1 testdef=None
201 11:40:29.518842 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:40:29.518927 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 11:40:29.519494 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:40:29.519717 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 11:40:29.520391 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:40:29.520635 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 11:40:29.647792 runner path: /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/0/tests/0_dmesg test_uuid 10742196_1.6.2.3.1
210 11:40:29.647998 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:40:29.648237 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 11:40:29.648311 Using /lava-10742196 at stage 1
214 11:40:29.648610 uuid=10742196_1.6.2.3.5 testdef=None
215 11:40:29.648699 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 11:40:29.648783 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 11:40:29.649283 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 11:40:29.649496 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 11:40:29.650123 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 11:40:29.650349 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 11:40:29.751786 runner path: /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/1/tests/1_bootrr test_uuid 10742196_1.6.2.3.5
224 11:40:29.752020 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 11:40:29.752238 Creating lava-test-runner.conf files
227 11:40:29.752301 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/0 for stage 0
228 11:40:29.752391 - 0_dmesg
229 11:40:29.752489 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742196/lava-overlay-uuc0pw0n/lava-10742196/1 for stage 1
230 11:40:29.752595 - 1_bootrr
231 11:40:29.752691 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 11:40:29.752778 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 11:40:29.760207 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 11:40:29.760338 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 11:40:29.760426 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 11:40:29.760516 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 11:40:29.760601 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 11:40:29.879044 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 11:40:29.879428 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 11:40:29.879554 extracting modules file /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742196/extract-nfsrootfs-p6y5mcne
241 11:40:30.735869 extracting modules file /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742196/extract-overlay-ramdisk-0whmidtn/ramdisk
242 11:40:30.963253 end: 1.6.4 extract-modules (duration 00:00:01) [common]
243 11:40:30.963428 start: 1.6.5 apply-overlay-tftp (timeout 00:09:48) [common]
244 11:40:30.963525 [common] Applying overlay to NFS
245 11:40:30.963598 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742196/compress-overlay-eaanyko1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742196/extract-nfsrootfs-p6y5mcne
246 11:40:30.971446 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 11:40:30.971578 start: 1.6.6 configure-preseed-file (timeout 00:09:48) [common]
248 11:40:30.971670 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 11:40:30.971761 start: 1.6.7 compress-ramdisk (timeout 00:09:48) [common]
250 11:40:30.971861 Building ramdisk /var/lib/lava/dispatcher/tmp/10742196/extract-overlay-ramdisk-0whmidtn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742196/extract-overlay-ramdisk-0whmidtn/ramdisk
251 11:40:32.208225 >> 117806 blocks
252 11:40:34.134167 rename /var/lib/lava/dispatcher/tmp/10742196/extract-overlay-ramdisk-0whmidtn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/ramdisk/ramdisk.cpio.gz
253 11:40:34.134582 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
254 11:40:34.134703 start: 1.6.8 prepare-kernel (timeout 00:09:45) [common]
255 11:40:34.134801 start: 1.6.8.1 prepare-fit (timeout 00:09:45) [common]
256 11:40:34.134910 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/kernel/Image'
257 11:40:46.528331 Returned 0 in 12 seconds
258 11:40:46.628934 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/kernel/image.itb
259 11:40:46.939278 output: FIT description: Kernel Image image with one or more FDT blobs
260 11:40:46.939676 output: Created: Thu Jun 15 12:40:46 2023
261 11:40:46.939755 output: Image 0 (kernel-1)
262 11:40:46.939821 output: Description:
263 11:40:46.939884 output: Created: Thu Jun 15 12:40:46 2023
264 11:40:46.939948 output: Type: Kernel Image
265 11:40:46.940009 output: Compression: lzma compressed
266 11:40:46.940067 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
267 11:40:46.940127 output: Architecture: AArch64
268 11:40:46.940183 output: OS: Linux
269 11:40:46.940240 output: Load Address: 0x00000000
270 11:40:46.940299 output: Entry Point: 0x00000000
271 11:40:46.940357 output: Hash algo: crc32
272 11:40:46.940416 output: Hash value: cd22d0e5
273 11:40:46.940470 output: Image 1 (fdt-1)
274 11:40:46.940524 output: Description: mt8192-asurada-spherion-r0
275 11:40:46.940579 output: Created: Thu Jun 15 12:40:46 2023
276 11:40:46.940633 output: Type: Flat Device Tree
277 11:40:46.940686 output: Compression: uncompressed
278 11:40:46.940740 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 11:40:46.940794 output: Architecture: AArch64
280 11:40:46.940847 output: Hash algo: crc32
281 11:40:46.940901 output: Hash value: 1df858fa
282 11:40:46.940954 output: Image 2 (ramdisk-1)
283 11:40:46.941007 output: Description: unavailable
284 11:40:46.941060 output: Created: Thu Jun 15 12:40:46 2023
285 11:40:46.941113 output: Type: RAMDisk Image
286 11:40:46.941167 output: Compression: Unknown Compression
287 11:40:46.941220 output: Data Size: 17640084 Bytes = 17226.64 KiB = 16.82 MiB
288 11:40:46.941274 output: Architecture: AArch64
289 11:40:46.941328 output: OS: Linux
290 11:40:46.941381 output: Load Address: unavailable
291 11:40:46.941434 output: Entry Point: unavailable
292 11:40:46.941487 output: Hash algo: crc32
293 11:40:46.941540 output: Hash value: b7f23790
294 11:40:46.941594 output: Default Configuration: 'conf-1'
295 11:40:46.941647 output: Configuration 0 (conf-1)
296 11:40:46.941700 output: Description: mt8192-asurada-spherion-r0
297 11:40:46.941753 output: Kernel: kernel-1
298 11:40:46.941806 output: Init Ramdisk: ramdisk-1
299 11:40:46.941860 output: FDT: fdt-1
300 11:40:46.941913 output: Loadables: kernel-1
301 11:40:46.941966 output:
302 11:40:46.942166 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 11:40:46.942265 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 11:40:46.942370 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
305 11:40:46.942462 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
306 11:40:46.942541 No LXC device requested
307 11:40:46.942620 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 11:40:46.942710 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
309 11:40:46.942789 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 11:40:46.942857 Checking files for TFTP limit of 4294967296 bytes.
311 11:40:46.943338 end: 1 tftp-deploy (duration 00:00:28) [common]
312 11:40:46.943484 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 11:40:46.943576 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 11:40:46.943701 substitutions:
315 11:40:46.943769 - {DTB}: 10742196/tftp-deploy-dr7wgtj6/dtb/mt8192-asurada-spherion-r0.dtb
316 11:40:46.943833 - {INITRD}: 10742196/tftp-deploy-dr7wgtj6/ramdisk/ramdisk.cpio.gz
317 11:40:46.943892 - {KERNEL}: 10742196/tftp-deploy-dr7wgtj6/kernel/Image
318 11:40:46.943949 - {LAVA_MAC}: None
319 11:40:46.944006 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10742196/extract-nfsrootfs-p6y5mcne
320 11:40:46.944061 - {NFS_SERVER_IP}: 192.168.201.1
321 11:40:46.944117 - {PRESEED_CONFIG}: None
322 11:40:46.944172 - {PRESEED_LOCAL}: None
323 11:40:46.944227 - {RAMDISK}: 10742196/tftp-deploy-dr7wgtj6/ramdisk/ramdisk.cpio.gz
324 11:40:46.944281 - {ROOT_PART}: None
325 11:40:46.944335 - {ROOT}: None
326 11:40:46.944389 - {SERVER_IP}: 192.168.201.1
327 11:40:46.944443 - {TEE}: None
328 11:40:46.944496 Parsed boot commands:
329 11:40:46.944549 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 11:40:46.944721 Parsed boot commands: tftpboot 192.168.201.1 10742196/tftp-deploy-dr7wgtj6/kernel/image.itb 10742196/tftp-deploy-dr7wgtj6/kernel/cmdline
331 11:40:46.944812 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 11:40:46.944896 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 11:40:46.944989 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 11:40:46.945073 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 11:40:46.945144 Not connected, no need to disconnect.
336 11:40:46.945219 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 11:40:46.945301 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 11:40:46.945368 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
339 11:40:46.948640 Setting prompt string to ['lava-test: # ']
340 11:40:46.948983 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 11:40:46.949091 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 11:40:46.949193 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 11:40:46.949286 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 11:40:46.949511 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
345 11:40:52.086238 >> Command sent successfully.
346 11:40:52.088774 Returned 0 in 5 seconds
347 11:40:52.189193 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 11:40:52.189639 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 11:40:52.189777 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 11:40:52.189898 Setting prompt string to 'Starting depthcharge on Spherion...'
352 11:40:52.190030 Changing prompt to 'Starting depthcharge on Spherion...'
353 11:40:52.190130 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 11:40:52.190498 [Enter `^Ec?' for help]
355 11:40:52.362970
356 11:40:52.363139
357 11:40:52.363212 F0: 102B 0000
358 11:40:52.363276
359 11:40:52.363337 F3: 1001 0000 [0200]
360 11:40:52.366182
361 11:40:52.366282 F3: 1001 0000
362 11:40:52.366351
363 11:40:52.366427 F7: 102D 0000
364 11:40:52.366510
365 11:40:52.369495 F1: 0000 0000
366 11:40:52.369584
367 11:40:52.369653 V0: 0000 0000 [0001]
368 11:40:52.369719
369 11:40:52.373057 00: 0007 8000
370 11:40:52.373148
371 11:40:52.373216 01: 0000 0000
372 11:40:52.373280
373 11:40:52.376340 BP: 0C00 0209 [0000]
374 11:40:52.376427
375 11:40:52.376494 G0: 1182 0000
376 11:40:52.376557
377 11:40:52.380289 EC: 0000 0021 [4000]
378 11:40:52.380378
379 11:40:52.380445 S7: 0000 0000 [0000]
380 11:40:52.380507
381 11:40:52.383652 CC: 0000 0000 [0001]
382 11:40:52.383745
383 11:40:52.383815 T0: 0000 0040 [010F]
384 11:40:52.383881
385 11:40:52.383942 Jump to BL
386 11:40:52.384004
387 11:40:52.409954
388 11:40:52.410113
389 11:40:52.410188
390 11:40:52.416487 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 11:40:52.423557 ARM64: Exception handlers installed.
392 11:40:52.423684 ARM64: Testing exception
393 11:40:52.426669 ARM64: Done test exception
394 11:40:52.433829 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 11:40:52.443780 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 11:40:52.450668 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 11:40:52.461087 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 11:40:52.467241 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 11:40:52.477646 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 11:40:52.487903 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 11:40:52.494201 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 11:40:52.512426 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 11:40:52.515941 WDT: Last reset was cold boot
404 11:40:52.519086 SPI1(PAD0) initialized at 2873684 Hz
405 11:40:52.522830 SPI5(PAD0) initialized at 992727 Hz
406 11:40:52.526313 VBOOT: Loading verstage.
407 11:40:52.532913 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 11:40:52.536297 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 11:40:52.539393 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 11:40:52.542951 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 11:40:52.550451 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 11:40:52.556595 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 11:40:52.567628 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 11:40:52.567775
415 11:40:52.567845
416 11:40:52.577606 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 11:40:52.581156 ARM64: Exception handlers installed.
418 11:40:52.584640 ARM64: Testing exception
419 11:40:52.584732 ARM64: Done test exception
420 11:40:52.591244 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 11:40:52.594884 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:40:52.608484 Probing TPM: . done!
423 11:40:52.608625 TPM ready after 0 ms
424 11:40:52.615001 Connected to device vid:did:rid of 1ae0:0028:00
425 11:40:52.624812 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 11:40:52.682646 Initialized TPM device CR50 revision 0
427 11:40:52.693154 tlcl_send_startup: Startup return code is 0
428 11:40:52.693307 TPM: setup succeeded
429 11:40:52.704999 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 11:40:52.713385 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 11:40:52.725663 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 11:40:52.735604 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 11:40:52.738401 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 11:40:52.744001 in-header: 03 07 00 00 08 00 00 00
435 11:40:52.747519 in-data: aa e4 47 04 13 02 00 00
436 11:40:52.751090 Chrome EC: UHEPI supported
437 11:40:52.757991 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 11:40:52.762009 in-header: 03 ad 00 00 08 00 00 00
439 11:40:52.765526 in-data: 00 20 20 08 00 00 00 00
440 11:40:52.765640 Phase 1
441 11:40:52.769314 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 11:40:52.776509 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 11:40:52.780557 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 11:40:52.783667 Recovery requested (1009000e)
445 11:40:52.793219 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 11:40:52.799528 tlcl_extend: response is 0
447 11:40:52.808990 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 11:40:52.815443 tlcl_extend: response is 0
449 11:40:52.821975 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 11:40:52.842037 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
451 11:40:52.848643 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 11:40:52.848768
453 11:40:52.848837
454 11:40:52.859564 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 11:40:52.862458 ARM64: Exception handlers installed.
456 11:40:52.865505 ARM64: Testing exception
457 11:40:52.865645 ARM64: Done test exception
458 11:40:52.887717 pmic_efuse_setting: Set efuses in 11 msecs
459 11:40:52.890902 pmwrap_interface_init: Select PMIF_VLD_RDY
460 11:40:52.898138 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 11:40:52.900704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 11:40:52.907725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 11:40:52.911676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 11:40:52.915245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 11:40:52.922201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 11:40:52.926219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 11:40:52.929447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 11:40:52.933732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 11:40:52.940524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 11:40:52.944524 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 11:40:52.948510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 11:40:52.951859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 11:40:52.958916 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 11:40:52.966531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 11:40:52.970365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 11:40:52.977508 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 11:40:52.981077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 11:40:52.988457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 11:40:52.992317 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 11:40:52.999993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 11:40:53.003221 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 11:40:53.010677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 11:40:53.014011 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 11:40:53.022051 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 11:40:53.028735 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 11:40:53.032602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 11:40:53.035953 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 11:40:53.043233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 11:40:53.046938 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 11:40:53.050747 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 11:40:53.057569 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 11:40:53.061314 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 11:40:53.064798 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 11:40:53.072316 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 11:40:53.076195 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 11:40:53.083694 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 11:40:53.087179 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 11:40:53.090603 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 11:40:53.094806 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 11:40:53.098460 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 11:40:53.105203 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 11:40:53.109170 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 11:40:53.112644 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 11:40:53.116670 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 11:40:53.123674 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 11:40:53.127326 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 11:40:53.130923 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 11:40:53.134499 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 11:40:53.137955 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 11:40:53.141835 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 11:40:53.149060 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 11:40:53.160321 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 11:40:53.163578 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 11:40:53.171291 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 11:40:53.178271 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 11:40:53.186035 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 11:40:53.189241 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 11:40:53.192779 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 11:40:53.200875 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
520 11:40:53.204334 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 11:40:53.212575 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 11:40:53.215316 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 11:40:53.225029 [RTC]rtc_get_frequency_meter,154: input=15, output=790
524 11:40:53.234366 [RTC]rtc_get_frequency_meter,154: input=23, output=978
525 11:40:53.244291 [RTC]rtc_get_frequency_meter,154: input=19, output=884
526 11:40:53.253024 [RTC]rtc_get_frequency_meter,154: input=17, output=837
527 11:40:53.263271 [RTC]rtc_get_frequency_meter,154: input=16, output=813
528 11:40:53.272503 [RTC]rtc_get_frequency_meter,154: input=15, output=790
529 11:40:53.282135 [RTC]rtc_get_frequency_meter,154: input=16, output=813
530 11:40:53.286030 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
531 11:40:53.289725 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
532 11:40:53.297343 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 11:40:53.300753 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 11:40:53.304595 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 11:40:53.308029 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 11:40:53.311796 ADC[4]: Raw value=902436 ID=7
537 11:40:53.311963 ADC[3]: Raw value=213336 ID=1
538 11:40:53.315655 RAM Code: 0x71
539 11:40:53.319134 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 11:40:53.326669 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 11:40:53.334299 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 11:40:53.341371 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 11:40:53.341514 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 11:40:53.345571 in-header: 03 07 00 00 08 00 00 00
545 11:40:53.349455 in-data: aa e4 47 04 13 02 00 00
546 11:40:53.353090 Chrome EC: UHEPI supported
547 11:40:53.360150 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 11:40:53.363860 in-header: 03 ed 00 00 08 00 00 00
549 11:40:53.367600 in-data: 80 20 60 08 00 00 00 00
550 11:40:53.371230 MRC: failed to locate region type 0.
551 11:40:53.375433 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 11:40:53.378307 DRAM-K: Running full calibration
553 11:40:53.385950 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 11:40:53.386082 header.status = 0x0
555 11:40:53.389687 header.version = 0x6 (expected: 0x6)
556 11:40:53.393067 header.size = 0xd00 (expected: 0xd00)
557 11:40:53.397134 header.flags = 0x0
558 11:40:53.400062 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 11:40:53.420415 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
560 11:40:53.427823 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 11:40:53.427962 dram_init: ddr_geometry: 2
562 11:40:53.432220 [EMI] MDL number = 2
563 11:40:53.435511 [EMI] Get MDL freq = 0
564 11:40:53.435610 dram_init: ddr_type: 0
565 11:40:53.438908 is_discrete_lpddr4: 1
566 11:40:53.442355 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 11:40:53.442459
568 11:40:53.442529
569 11:40:53.442592 [Bian_co] ETT version 0.0.0.1
570 11:40:53.449149 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 11:40:53.449263
572 11:40:53.452625 dramc_set_vcore_voltage set vcore to 650000
573 11:40:53.452715 Read voltage for 800, 4
574 11:40:53.456254 Vio18 = 0
575 11:40:53.456345 Vcore = 650000
576 11:40:53.456415 Vdram = 0
577 11:40:53.459119 Vddq = 0
578 11:40:53.459208 Vmddr = 0
579 11:40:53.462389 dram_init: config_dvfs: 1
580 11:40:53.466423 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 11:40:53.472527 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 11:40:53.475622 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
583 11:40:53.479397 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
584 11:40:53.483040 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
585 11:40:53.485941 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
586 11:40:53.489020 MEM_TYPE=3, freq_sel=18
587 11:40:53.492691 sv_algorithm_assistance_LP4_1600
588 11:40:53.496022 ============ PULL DRAM RESETB DOWN ============
589 11:40:53.502403 ========== PULL DRAM RESETB DOWN end =========
590 11:40:53.506144 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 11:40:53.509357 ===================================
592 11:40:53.512597 LPDDR4 DRAM CONFIGURATION
593 11:40:53.516048 ===================================
594 11:40:53.516207 EX_ROW_EN[0] = 0x0
595 11:40:53.518986 EX_ROW_EN[1] = 0x0
596 11:40:53.519093 LP4Y_EN = 0x0
597 11:40:53.522526 WORK_FSP = 0x0
598 11:40:53.522639 WL = 0x2
599 11:40:53.525438 RL = 0x2
600 11:40:53.525551 BL = 0x2
601 11:40:53.528924 RPST = 0x0
602 11:40:53.529028 RD_PRE = 0x0
603 11:40:53.532356 WR_PRE = 0x1
604 11:40:53.532461 WR_PST = 0x0
605 11:40:53.535946 DBI_WR = 0x0
606 11:40:53.536051 DBI_RD = 0x0
607 11:40:53.539272 OTF = 0x1
608 11:40:53.542621 ===================================
609 11:40:53.545518 ===================================
610 11:40:53.545629 ANA top config
611 11:40:53.548933 ===================================
612 11:40:53.552454 DLL_ASYNC_EN = 0
613 11:40:53.555459 ALL_SLAVE_EN = 1
614 11:40:53.558857 NEW_RANK_MODE = 1
615 11:40:53.561998 DLL_IDLE_MODE = 1
616 11:40:53.562122 LP45_APHY_COMB_EN = 1
617 11:40:53.565785 TX_ODT_DIS = 1
618 11:40:53.568955 NEW_8X_MODE = 1
619 11:40:53.572274 ===================================
620 11:40:53.575534 ===================================
621 11:40:53.578633 data_rate = 1600
622 11:40:53.582086 CKR = 1
623 11:40:53.582204 DQ_P2S_RATIO = 8
624 11:40:53.585607 ===================================
625 11:40:53.589146 CA_P2S_RATIO = 8
626 11:40:53.592095 DQ_CA_OPEN = 0
627 11:40:53.595181 DQ_SEMI_OPEN = 0
628 11:40:53.598506 CA_SEMI_OPEN = 0
629 11:40:53.601808 CA_FULL_RATE = 0
630 11:40:53.601902 DQ_CKDIV4_EN = 1
631 11:40:53.605874 CA_CKDIV4_EN = 1
632 11:40:53.608631 CA_PREDIV_EN = 0
633 11:40:53.612062 PH8_DLY = 0
634 11:40:53.615295 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 11:40:53.618738 DQ_AAMCK_DIV = 4
636 11:40:53.618822 CA_AAMCK_DIV = 4
637 11:40:53.622071 CA_ADMCK_DIV = 4
638 11:40:53.625026 DQ_TRACK_CA_EN = 0
639 11:40:53.628353 CA_PICK = 800
640 11:40:53.631786 CA_MCKIO = 800
641 11:40:53.635637 MCKIO_SEMI = 0
642 11:40:53.635724 PLL_FREQ = 3068
643 11:40:53.639701 DQ_UI_PI_RATIO = 32
644 11:40:53.643224 CA_UI_PI_RATIO = 0
645 11:40:53.646679 ===================================
646 11:40:53.650164 ===================================
647 11:40:53.650247 memory_type:LPDDR4
648 11:40:53.654252 GP_NUM : 10
649 11:40:53.654336 SRAM_EN : 1
650 11:40:53.657845 MD32_EN : 0
651 11:40:53.661787 ===================================
652 11:40:53.665398 [ANA_INIT] >>>>>>>>>>>>>>
653 11:40:53.665486 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 11:40:53.668789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 11:40:53.672154 ===================================
656 11:40:53.676008 data_rate = 1600,PCW = 0X7600
657 11:40:53.679434 ===================================
658 11:40:53.682457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 11:40:53.689012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 11:40:53.692202 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 11:40:53.698902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 11:40:53.702755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 11:40:53.705606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 11:40:53.705689 [ANA_INIT] flow start
665 11:40:53.709586 [ANA_INIT] PLL >>>>>>>>
666 11:40:53.712786 [ANA_INIT] PLL <<<<<<<<
667 11:40:53.712876 [ANA_INIT] MIDPI >>>>>>>>
668 11:40:53.715663 [ANA_INIT] MIDPI <<<<<<<<
669 11:40:53.719121 [ANA_INIT] DLL >>>>>>>>
670 11:40:53.719197 [ANA_INIT] flow end
671 11:40:53.725960 ============ LP4 DIFF to SE enter ============
672 11:40:53.729408 ============ LP4 DIFF to SE exit ============
673 11:40:53.732309 [ANA_INIT] <<<<<<<<<<<<<
674 11:40:53.735796 [Flow] Enable top DCM control >>>>>
675 11:40:53.739224 [Flow] Enable top DCM control <<<<<
676 11:40:53.739321 Enable DLL master slave shuffle
677 11:40:53.745600 ==============================================================
678 11:40:53.749011 Gating Mode config
679 11:40:53.752483 ==============================================================
680 11:40:53.755634 Config description:
681 11:40:53.765826 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 11:40:53.772721 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 11:40:53.775789 SELPH_MODE 0: By rank 1: By Phase
684 11:40:53.782589 ==============================================================
685 11:40:53.785905 GAT_TRACK_EN = 1
686 11:40:53.789145 RX_GATING_MODE = 2
687 11:40:53.789238 RX_GATING_TRACK_MODE = 2
688 11:40:53.792398 SELPH_MODE = 1
689 11:40:53.796039 PICG_EARLY_EN = 1
690 11:40:53.799172 VALID_LAT_VALUE = 1
691 11:40:53.805964 ==============================================================
692 11:40:53.809575 Enter into Gating configuration >>>>
693 11:40:53.812588 Exit from Gating configuration <<<<
694 11:40:53.816263 Enter into DVFS_PRE_config >>>>>
695 11:40:53.826097 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 11:40:53.829506 Exit from DVFS_PRE_config <<<<<
697 11:40:53.832929 Enter into PICG configuration >>>>
698 11:40:53.835871 Exit from PICG configuration <<<<
699 11:40:53.839456 [RX_INPUT] configuration >>>>>
700 11:40:53.843041 [RX_INPUT] configuration <<<<<
701 11:40:53.846273 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 11:40:53.852663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 11:40:53.859440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 11:40:53.862885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 11:40:53.869275 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 11:40:53.876021 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 11:40:53.879291 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 11:40:53.882881 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 11:40:53.889350 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 11:40:53.893031 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 11:40:53.896468 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 11:40:53.902907 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 11:40:53.906160 ===================================
714 11:40:53.906263 LPDDR4 DRAM CONFIGURATION
715 11:40:53.909614 ===================================
716 11:40:53.912928 EX_ROW_EN[0] = 0x0
717 11:40:53.913036 EX_ROW_EN[1] = 0x0
718 11:40:53.916084 LP4Y_EN = 0x0
719 11:40:53.916187 WORK_FSP = 0x0
720 11:40:53.920084 WL = 0x2
721 11:40:53.920188 RL = 0x2
722 11:40:53.922989 BL = 0x2
723 11:40:53.926134 RPST = 0x0
724 11:40:53.926223 RD_PRE = 0x0
725 11:40:53.929480 WR_PRE = 0x1
726 11:40:53.929567 WR_PST = 0x0
727 11:40:53.933037 DBI_WR = 0x0
728 11:40:53.933125 DBI_RD = 0x0
729 11:40:53.936265 OTF = 0x1
730 11:40:53.939730 ===================================
731 11:40:53.942938 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 11:40:53.946427 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 11:40:53.949895 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 11:40:53.952812 ===================================
735 11:40:53.956130 LPDDR4 DRAM CONFIGURATION
736 11:40:53.959438 ===================================
737 11:40:53.962845 EX_ROW_EN[0] = 0x10
738 11:40:53.962951 EX_ROW_EN[1] = 0x0
739 11:40:53.966733 LP4Y_EN = 0x0
740 11:40:53.966868 WORK_FSP = 0x0
741 11:40:53.969882 WL = 0x2
742 11:40:53.969995 RL = 0x2
743 11:40:53.972817 BL = 0x2
744 11:40:53.972920 RPST = 0x0
745 11:40:53.976262 RD_PRE = 0x0
746 11:40:53.976365 WR_PRE = 0x1
747 11:40:53.979611 WR_PST = 0x0
748 11:40:53.979714 DBI_WR = 0x0
749 11:40:53.982852 DBI_RD = 0x0
750 11:40:53.982954 OTF = 0x1
751 11:40:53.986191 ===================================
752 11:40:53.992977 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 11:40:53.997952 nWR fixed to 40
754 11:40:54.001383 [ModeRegInit_LP4] CH0 RK0
755 11:40:54.001484 [ModeRegInit_LP4] CH0 RK1
756 11:40:54.004642 [ModeRegInit_LP4] CH1 RK0
757 11:40:54.007917 [ModeRegInit_LP4] CH1 RK1
758 11:40:54.008010 match AC timing 13
759 11:40:54.014391 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 11:40:54.018095 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 11:40:54.021301 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 11:40:54.027888 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 11:40:54.031036 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 11:40:54.031136 [EMI DOE] emi_dcm 0
765 11:40:54.038358 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 11:40:54.038495 ==
767 11:40:54.040943 Dram Type= 6, Freq= 0, CH_0, rank 0
768 11:40:54.044306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 11:40:54.044389 ==
770 11:40:54.051527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 11:40:54.057856 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 11:40:54.065613 [CA 0] Center 37 (7~68) winsize 62
773 11:40:54.068874 [CA 1] Center 37 (6~68) winsize 63
774 11:40:54.072076 [CA 2] Center 34 (4~65) winsize 62
775 11:40:54.075598 [CA 3] Center 34 (4~65) winsize 62
776 11:40:54.078953 [CA 4] Center 33 (3~64) winsize 62
777 11:40:54.082430 [CA 5] Center 34 (4~64) winsize 61
778 11:40:54.082522
779 11:40:54.085085 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 11:40:54.085210
781 11:40:54.088641 [CATrainingPosCal] consider 1 rank data
782 11:40:54.091992 u2DelayCellTimex100 = 270/100 ps
783 11:40:54.095324 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
784 11:40:54.098594 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
785 11:40:54.105392 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
786 11:40:54.108680 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
787 11:40:54.112365 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
788 11:40:54.115486 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
789 11:40:54.115612
790 11:40:54.118540 CA PerBit enable=1, Macro0, CA PI delay=33
791 11:40:54.118674
792 11:40:54.121874 [CBTSetCACLKResult] CA Dly = 33
793 11:40:54.121978 CS Dly: 5 (0~36)
794 11:40:54.122084 ==
795 11:40:54.125450 Dram Type= 6, Freq= 0, CH_0, rank 1
796 11:40:54.132338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 11:40:54.132450 ==
798 11:40:54.135570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 11:40:54.141782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 11:40:54.151177 [CA 0] Center 37 (7~68) winsize 62
801 11:40:54.154853 [CA 1] Center 37 (6~68) winsize 63
802 11:40:54.158235 [CA 2] Center 35 (4~66) winsize 63
803 11:40:54.161648 [CA 3] Center 34 (4~65) winsize 62
804 11:40:54.165015 [CA 4] Center 33 (3~64) winsize 62
805 11:40:54.168173 [CA 5] Center 33 (3~64) winsize 62
806 11:40:54.168371
807 11:40:54.171230 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 11:40:54.171334
809 11:40:54.174801 [CATrainingPosCal] consider 2 rank data
810 11:40:54.178343 u2DelayCellTimex100 = 270/100 ps
811 11:40:54.181716 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
812 11:40:54.185092 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
813 11:40:54.188288 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
814 11:40:54.194984 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
815 11:40:54.198494 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
816 11:40:54.201607 CA5 delay=34 (4~64),Diff = 1 PI (7 cell)
817 11:40:54.201703
818 11:40:54.205000 CA PerBit enable=1, Macro0, CA PI delay=33
819 11:40:54.205088
820 11:40:54.207944 [CBTSetCACLKResult] CA Dly = 33
821 11:40:54.208039 CS Dly: 6 (0~38)
822 11:40:54.208105
823 11:40:54.212012 ----->DramcWriteLeveling(PI) begin...
824 11:40:54.214654 ==
825 11:40:54.214732 Dram Type= 6, Freq= 0, CH_0, rank 0
826 11:40:54.222135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 11:40:54.222252 ==
828 11:40:54.222322 Write leveling (Byte 0): 29 => 29
829 11:40:54.225888 Write leveling (Byte 1): 29 => 29
830 11:40:54.229572 DramcWriteLeveling(PI) end<-----
831 11:40:54.229668
832 11:40:54.229787 ==
833 11:40:54.233413 Dram Type= 6, Freq= 0, CH_0, rank 0
834 11:40:54.236889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 11:40:54.236989 ==
836 11:40:54.240353 [Gating] SW mode calibration
837 11:40:54.247160 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 11:40:54.254184 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 11:40:54.257580 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 11:40:54.261302 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
841 11:40:54.267957 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
842 11:40:54.270534 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 11:40:54.274103 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:40:54.280826 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:40:54.284366 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:40:54.287582 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:40:54.291231 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:40:54.297544 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:40:54.300802 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 11:40:54.304128 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:40:54.311107 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:40:54.314004 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:40:54.317704 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:40:54.324096 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:40:54.327543 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:40:54.331077 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:40:54.337847 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
858 11:40:54.340917 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
859 11:40:54.344366 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:40:54.351074 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:40:54.354544 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:40:54.357516 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:40:54.361588 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:40:54.367599 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:40:54.371064 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:40:54.374621 0 9 12 | B1->B0 | 2b2a 3332 | 1 1 | (0 0) (0 0)
867 11:40:54.381612 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 11:40:54.384981 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 11:40:54.387841 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 11:40:54.394669 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 11:40:54.398120 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 11:40:54.401609 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
873 11:40:54.407824 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
874 11:40:54.411140 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
875 11:40:54.414495 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:40:54.421428 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:40:54.424413 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:40:54.427879 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:40:54.431490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 11:40:54.438246 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 11:40:54.441736 0 11 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
882 11:40:54.444744 0 11 12 | B1->B0 | 3434 3e3e | 0 0 | (1 1) (0 0)
883 11:40:54.451585 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 11:40:54.454863 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 11:40:54.458076 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 11:40:54.464650 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 11:40:54.468599 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 11:40:54.471541 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
889 11:40:54.478431 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
890 11:40:54.481708 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 11:40:54.484672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 11:40:54.491337 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 11:40:54.494791 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 11:40:54.498021 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 11:40:54.504672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 11:40:54.508096 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 11:40:54.511475 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 11:40:54.514804 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:40:54.521721 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:40:54.525219 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:40:54.528357 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:40:54.535040 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:40:54.537941 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:40:54.541647 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:40:54.548355 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
906 11:40:54.551546 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
907 11:40:54.555001 Total UI for P1: 0, mck2ui 16
908 11:40:54.558412 best dqsien dly found for B0: ( 0, 14, 8)
909 11:40:54.561228 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 11:40:54.564914 Total UI for P1: 0, mck2ui 16
911 11:40:54.568330 best dqsien dly found for B1: ( 0, 14, 10)
912 11:40:54.571765 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
913 11:40:54.574581 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
914 11:40:54.574677
915 11:40:54.581395 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 11:40:54.585064 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
917 11:40:54.585164 [Gating] SW calibration Done
918 11:40:54.588097 ==
919 11:40:54.591722 Dram Type= 6, Freq= 0, CH_0, rank 0
920 11:40:54.594820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 11:40:54.594913 ==
922 11:40:54.594979 RX Vref Scan: 0
923 11:40:54.595040
924 11:40:54.598328 RX Vref 0 -> 0, step: 1
925 11:40:54.598431
926 11:40:54.601224 RX Delay -130 -> 252, step: 16
927 11:40:54.604781 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
928 11:40:54.608345 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
929 11:40:54.614930 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
930 11:40:54.618292 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
931 11:40:54.621596 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
932 11:40:54.624504 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
933 11:40:54.628223 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
934 11:40:54.631769 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
935 11:40:54.638044 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
936 11:40:54.641422 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
937 11:40:54.644677 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
938 11:40:54.648432 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
939 11:40:54.654775 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
940 11:40:54.658069 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
941 11:40:54.661528 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
942 11:40:54.664668 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
943 11:40:54.664765 ==
944 11:40:54.668256 Dram Type= 6, Freq= 0, CH_0, rank 0
945 11:40:54.671216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 11:40:54.674580 ==
947 11:40:54.674674 DQS Delay:
948 11:40:54.674740 DQS0 = 0, DQS1 = 0
949 11:40:54.678339 DQM Delay:
950 11:40:54.678425 DQM0 = 83, DQM1 = 77
951 11:40:54.681396 DQ Delay:
952 11:40:54.681482 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
953 11:40:54.684604 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
954 11:40:54.688040 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
955 11:40:54.691644 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
956 11:40:54.691739
957 11:40:54.694643
958 11:40:54.694728 ==
959 11:40:54.697826 Dram Type= 6, Freq= 0, CH_0, rank 0
960 11:40:54.701100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 11:40:54.701190 ==
962 11:40:54.701294
963 11:40:54.701353
964 11:40:54.704490 TX Vref Scan disable
965 11:40:54.704592 == TX Byte 0 ==
966 11:40:54.711510 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
967 11:40:54.714569 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
968 11:40:54.714663 == TX Byte 1 ==
969 11:40:54.721207 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
970 11:40:54.724725 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
971 11:40:54.724826 ==
972 11:40:54.728252 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:40:54.731261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:40:54.731391 ==
975 11:40:54.744493 TX Vref=22, minBit 3, minWin=27, winSum=440
976 11:40:54.747933 TX Vref=24, minBit 3, minWin=27, winSum=441
977 11:40:54.751200 TX Vref=26, minBit 3, minWin=27, winSum=446
978 11:40:54.754319 TX Vref=28, minBit 1, minWin=28, winSum=450
979 11:40:54.757759 TX Vref=30, minBit 1, minWin=28, winSum=454
980 11:40:54.764514 TX Vref=32, minBit 1, minWin=28, winSum=451
981 11:40:54.767982 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 30
982 11:40:54.768084
983 11:40:54.771340 Final TX Range 1 Vref 30
984 11:40:54.771465
985 11:40:54.771531 ==
986 11:40:54.774628 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:40:54.778262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:40:54.778370 ==
989 11:40:54.778451
990 11:40:54.781001
991 11:40:54.781113 TX Vref Scan disable
992 11:40:54.784395 == TX Byte 0 ==
993 11:40:54.787645 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
994 11:40:54.791078 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
995 11:40:54.794679 == TX Byte 1 ==
996 11:40:54.797848 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
997 11:40:54.801110 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
998 11:40:54.804431
999 11:40:54.804529 [DATLAT]
1000 11:40:54.804597 Freq=800, CH0 RK0
1001 11:40:54.804659
1002 11:40:54.807834 DATLAT Default: 0xa
1003 11:40:54.807920 0, 0xFFFF, sum = 0
1004 11:40:54.811458 1, 0xFFFF, sum = 0
1005 11:40:54.811547 2, 0xFFFF, sum = 0
1006 11:40:54.814970 3, 0xFFFF, sum = 0
1007 11:40:54.815060 4, 0xFFFF, sum = 0
1008 11:40:54.817896 5, 0xFFFF, sum = 0
1009 11:40:54.821106 6, 0xFFFF, sum = 0
1010 11:40:54.821202 7, 0xFFFF, sum = 0
1011 11:40:54.824522 8, 0xFFFF, sum = 0
1012 11:40:54.824612 9, 0x0, sum = 1
1013 11:40:54.824680 10, 0x0, sum = 2
1014 11:40:54.827786 11, 0x0, sum = 3
1015 11:40:54.827874 12, 0x0, sum = 4
1016 11:40:54.831259 best_step = 10
1017 11:40:54.831409
1018 11:40:54.831479 ==
1019 11:40:54.834802 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 11:40:54.837626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 11:40:54.837739 ==
1022 11:40:54.841165 RX Vref Scan: 1
1023 11:40:54.841253
1024 11:40:54.841320 Set Vref Range= 32 -> 127
1025 11:40:54.841388
1026 11:40:54.844582 RX Vref 32 -> 127, step: 1
1027 11:40:54.844668
1028 11:40:54.847948 RX Delay -95 -> 252, step: 8
1029 11:40:54.848036
1030 11:40:54.851340 Set Vref, RX VrefLevel [Byte0]: 32
1031 11:40:54.854508 [Byte1]: 32
1032 11:40:54.854595
1033 11:40:54.857612 Set Vref, RX VrefLevel [Byte0]: 33
1034 11:40:54.861376 [Byte1]: 33
1035 11:40:54.864858
1036 11:40:54.864955 Set Vref, RX VrefLevel [Byte0]: 34
1037 11:40:54.868221 [Byte1]: 34
1038 11:40:54.872743
1039 11:40:54.872874 Set Vref, RX VrefLevel [Byte0]: 35
1040 11:40:54.875917 [Byte1]: 35
1041 11:40:54.880391
1042 11:40:54.880498 Set Vref, RX VrefLevel [Byte0]: 36
1043 11:40:54.886148 [Byte1]: 36
1044 11:40:54.886248
1045 11:40:54.890185 Set Vref, RX VrefLevel [Byte0]: 37
1046 11:40:54.893612 [Byte1]: 37
1047 11:40:54.893710
1048 11:40:54.897435 Set Vref, RX VrefLevel [Byte0]: 38
1049 11:40:54.900856 [Byte1]: 38
1050 11:40:54.900954
1051 11:40:54.904732 Set Vref, RX VrefLevel [Byte0]: 39
1052 11:40:54.908453 [Byte1]: 39
1053 11:40:54.908554
1054 11:40:54.911921 Set Vref, RX VrefLevel [Byte0]: 40
1055 11:40:54.915967 [Byte1]: 40
1056 11:40:54.916073
1057 11:40:54.919467 Set Vref, RX VrefLevel [Byte0]: 41
1058 11:40:54.922886 [Byte1]: 41
1059 11:40:54.922981
1060 11:40:54.926110 Set Vref, RX VrefLevel [Byte0]: 42
1061 11:40:54.929461 [Byte1]: 42
1062 11:40:54.933218
1063 11:40:54.933312 Set Vref, RX VrefLevel [Byte0]: 43
1064 11:40:54.936636 [Byte1]: 43
1065 11:40:54.941133
1066 11:40:54.941230 Set Vref, RX VrefLevel [Byte0]: 44
1067 11:40:54.944046 [Byte1]: 44
1068 11:40:54.948497
1069 11:40:54.948619 Set Vref, RX VrefLevel [Byte0]: 45
1070 11:40:54.951855 [Byte1]: 45
1071 11:40:54.955701
1072 11:40:54.955796 Set Vref, RX VrefLevel [Byte0]: 46
1073 11:40:54.959609 [Byte1]: 46
1074 11:40:54.963776
1075 11:40:54.963874 Set Vref, RX VrefLevel [Byte0]: 47
1076 11:40:54.967182 [Byte1]: 47
1077 11:40:54.971192
1078 11:40:54.971294 Set Vref, RX VrefLevel [Byte0]: 48
1079 11:40:54.974372 [Byte1]: 48
1080 11:40:54.978748
1081 11:40:54.978844 Set Vref, RX VrefLevel [Byte0]: 49
1082 11:40:54.982590 [Byte1]: 49
1083 11:40:54.986113
1084 11:40:54.986205 Set Vref, RX VrefLevel [Byte0]: 50
1085 11:40:54.989843 [Byte1]: 50
1086 11:40:54.993799
1087 11:40:54.993898 Set Vref, RX VrefLevel [Byte0]: 51
1088 11:40:54.997349 [Byte1]: 51
1089 11:40:55.001432
1090 11:40:55.001528 Set Vref, RX VrefLevel [Byte0]: 52
1091 11:40:55.004675 [Byte1]: 52
1092 11:40:55.009175
1093 11:40:55.009278 Set Vref, RX VrefLevel [Byte0]: 53
1094 11:40:55.012741 [Byte1]: 53
1095 11:40:55.016478
1096 11:40:55.016574 Set Vref, RX VrefLevel [Byte0]: 54
1097 11:40:55.019977 [Byte1]: 54
1098 11:40:55.024533
1099 11:40:55.024653 Set Vref, RX VrefLevel [Byte0]: 55
1100 11:40:55.027671 [Byte1]: 55
1101 11:40:55.031845
1102 11:40:55.031964 Set Vref, RX VrefLevel [Byte0]: 56
1103 11:40:55.035239 [Byte1]: 56
1104 11:40:55.039242
1105 11:40:55.039379 Set Vref, RX VrefLevel [Byte0]: 57
1106 11:40:55.043054 [Byte1]: 57
1107 11:40:55.046868
1108 11:40:55.046978 Set Vref, RX VrefLevel [Byte0]: 58
1109 11:40:55.050461 [Byte1]: 58
1110 11:40:55.054833
1111 11:40:55.054950 Set Vref, RX VrefLevel [Byte0]: 59
1112 11:40:55.057837 [Byte1]: 59
1113 11:40:55.062451
1114 11:40:55.062545 Set Vref, RX VrefLevel [Byte0]: 60
1115 11:40:55.065914 [Byte1]: 60
1116 11:40:55.069990
1117 11:40:55.070123 Set Vref, RX VrefLevel [Byte0]: 61
1118 11:40:55.072968 [Byte1]: 61
1119 11:40:55.077418
1120 11:40:55.077519 Set Vref, RX VrefLevel [Byte0]: 62
1121 11:40:55.080731 [Byte1]: 62
1122 11:40:55.085258
1123 11:40:55.085355 Set Vref, RX VrefLevel [Byte0]: 63
1124 11:40:55.088454 [Byte1]: 63
1125 11:40:55.092360
1126 11:40:55.092455 Set Vref, RX VrefLevel [Byte0]: 64
1127 11:40:55.095876 [Byte1]: 64
1128 11:40:55.100136
1129 11:40:55.100232 Set Vref, RX VrefLevel [Byte0]: 65
1130 11:40:55.103448 [Byte1]: 65
1131 11:40:55.107743
1132 11:40:55.107839 Set Vref, RX VrefLevel [Byte0]: 66
1133 11:40:55.110884 [Byte1]: 66
1134 11:40:55.115899
1135 11:40:55.116001 Set Vref, RX VrefLevel [Byte0]: 67
1136 11:40:55.118608 [Byte1]: 67
1137 11:40:55.123053
1138 11:40:55.123138 Set Vref, RX VrefLevel [Byte0]: 68
1139 11:40:55.126356 [Byte1]: 68
1140 11:40:55.130494
1141 11:40:55.130573 Set Vref, RX VrefLevel [Byte0]: 69
1142 11:40:55.133633 [Byte1]: 69
1143 11:40:55.138038
1144 11:40:55.138119 Set Vref, RX VrefLevel [Byte0]: 70
1145 11:40:55.141513 [Byte1]: 70
1146 11:40:55.145575
1147 11:40:55.145671 Set Vref, RX VrefLevel [Byte0]: 71
1148 11:40:55.149191 [Byte1]: 71
1149 11:40:55.153512
1150 11:40:55.153598 Set Vref, RX VrefLevel [Byte0]: 72
1151 11:40:55.156899 [Byte1]: 72
1152 11:40:55.161244
1153 11:40:55.161330 Set Vref, RX VrefLevel [Byte0]: 73
1154 11:40:55.164302 [Byte1]: 73
1155 11:40:55.168417
1156 11:40:55.168508 Set Vref, RX VrefLevel [Byte0]: 74
1157 11:40:55.171816 [Byte1]: 74
1158 11:40:55.175945
1159 11:40:55.176036 Set Vref, RX VrefLevel [Byte0]: 75
1160 11:40:55.179292 [Byte1]: 75
1161 11:40:55.183580
1162 11:40:55.183666 Set Vref, RX VrefLevel [Byte0]: 76
1163 11:40:55.186898 [Byte1]: 76
1164 11:40:55.191680
1165 11:40:55.191792 Set Vref, RX VrefLevel [Byte0]: 77
1166 11:40:55.195141 [Byte1]: 77
1167 11:40:55.198798
1168 11:40:55.198882 Final RX Vref Byte 0 = 62 to rank0
1169 11:40:55.202718 Final RX Vref Byte 1 = 59 to rank0
1170 11:40:55.205794 Final RX Vref Byte 0 = 62 to rank1
1171 11:40:55.209309 Final RX Vref Byte 1 = 59 to rank1==
1172 11:40:55.212545 Dram Type= 6, Freq= 0, CH_0, rank 0
1173 11:40:55.215623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1174 11:40:55.219199 ==
1175 11:40:55.219285 DQS Delay:
1176 11:40:55.219376 DQS0 = 0, DQS1 = 0
1177 11:40:55.222546 DQM Delay:
1178 11:40:55.222621 DQM0 = 88, DQM1 = 79
1179 11:40:55.225853 DQ Delay:
1180 11:40:55.229291 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1181 11:40:55.229366 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1182 11:40:55.232335 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =76
1183 11:40:55.235708 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1184 11:40:55.235785
1185 11:40:55.239042
1186 11:40:55.245636 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1187 11:40:55.249125 CH0 RK0: MR19=606, MR18=2A11
1188 11:40:55.256149 CH0_RK0: MR19=0x606, MR18=0x2A11, DQSOSC=399, MR23=63, INC=92, DEC=61
1189 11:40:55.256255
1190 11:40:55.259053 ----->DramcWriteLeveling(PI) begin...
1191 11:40:55.259157 ==
1192 11:40:55.262428 Dram Type= 6, Freq= 0, CH_0, rank 1
1193 11:40:55.265864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1194 11:40:55.265947 ==
1195 11:40:55.269335 Write leveling (Byte 0): 29 => 29
1196 11:40:55.272864 Write leveling (Byte 1): 30 => 30
1197 11:40:55.275684 DramcWriteLeveling(PI) end<-----
1198 11:40:55.275766
1199 11:40:55.275831 ==
1200 11:40:55.279177 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 11:40:55.282549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 11:40:55.282627 ==
1203 11:40:55.285909 [Gating] SW mode calibration
1204 11:40:55.292633 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1205 11:40:55.299357 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1206 11:40:55.343622 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1207 11:40:55.343975 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1208 11:40:55.344084 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:40:55.344371 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:40:55.344985 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:40:55.345269 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:40:55.345548 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:40:55.345642 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 11:40:55.345920 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:40:55.346035 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:40:55.387505 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:40:55.387881 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:40:55.387982 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:40:55.388079 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:40:55.388204 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:40:55.388555 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:40:55.388698 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:40:55.388829 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1224 11:40:55.388992 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1225 11:40:55.389110 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1226 11:40:55.425633 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:40:55.425803 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:40:55.426077 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:40:55.426149 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:40:55.426229 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:40:55.426476 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:40:55.426549 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1233 11:40:55.426902 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1234 11:40:55.427533 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 11:40:55.430212 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 11:40:55.433353 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 11:40:55.440267 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 11:40:55.443520 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 11:40:55.446769 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
1240 11:40:55.450258 0 10 8 | B1->B0 | 3131 2828 | 0 0 | (0 1) (1 1)
1241 11:40:55.456530 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1242 11:40:55.459992 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:40:55.463571 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:40:55.470394 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:40:55.474285 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:40:55.477712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:40:55.481655 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1248 11:40:55.488572 0 11 8 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
1249 11:40:55.491978 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1250 11:40:55.495590 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 11:40:55.498981 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 11:40:55.505770 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 11:40:55.509342 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 11:40:55.512123 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 11:40:55.518939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1256 11:40:55.522723 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1257 11:40:55.525764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 11:40:55.532150 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 11:40:55.535897 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 11:40:55.538916 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 11:40:55.542491 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 11:40:55.549233 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 11:40:55.552928 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:40:55.556512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:40:55.562748 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:40:55.565674 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:40:55.569107 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:40:55.576080 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:40:55.579553 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:40:55.582847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:40:55.589180 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:40:55.592536 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1273 11:40:55.595638 Total UI for P1: 0, mck2ui 16
1274 11:40:55.599051 best dqsien dly found for B0: ( 0, 14, 6)
1275 11:40:55.602517 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1276 11:40:55.605704 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 11:40:55.609372 Total UI for P1: 0, mck2ui 16
1278 11:40:55.612472 best dqsien dly found for B1: ( 0, 14, 10)
1279 11:40:55.615890 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1280 11:40:55.622760 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1281 11:40:55.622911
1282 11:40:55.626019 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1283 11:40:55.629079 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1284 11:40:55.633123 [Gating] SW calibration Done
1285 11:40:55.633248 ==
1286 11:40:55.636223 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 11:40:55.639090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 11:40:55.639212 ==
1289 11:40:55.639309 RX Vref Scan: 0
1290 11:40:55.642397
1291 11:40:55.642511 RX Vref 0 -> 0, step: 1
1292 11:40:55.642616
1293 11:40:55.645852 RX Delay -130 -> 252, step: 16
1294 11:40:55.649577 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1295 11:40:55.652808 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1296 11:40:55.659006 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1297 11:40:55.662332 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1298 11:40:55.665782 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1299 11:40:55.669204 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1300 11:40:55.672865 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1301 11:40:55.679215 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1302 11:40:55.682478 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1303 11:40:55.685983 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1304 11:40:55.688963 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1305 11:40:55.692392 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1306 11:40:55.699078 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1307 11:40:55.702551 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1308 11:40:55.705571 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1309 11:40:55.709068 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1310 11:40:55.709196 ==
1311 11:40:55.712680 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 11:40:55.718969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 11:40:55.719113 ==
1314 11:40:55.719218 DQS Delay:
1315 11:40:55.722295 DQS0 = 0, DQS1 = 0
1316 11:40:55.722402 DQM Delay:
1317 11:40:55.722522 DQM0 = 84, DQM1 = 76
1318 11:40:55.725852 DQ Delay:
1319 11:40:55.729476 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1320 11:40:55.732871 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1321 11:40:55.736067 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1322 11:40:55.738899 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1323 11:40:55.739018
1324 11:40:55.739120
1325 11:40:55.739212 ==
1326 11:40:55.742329 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 11:40:55.746130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 11:40:55.746255 ==
1329 11:40:55.746351
1330 11:40:55.746451
1331 11:40:55.749015 TX Vref Scan disable
1332 11:40:55.749128 == TX Byte 0 ==
1333 11:40:55.756227 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1334 11:40:55.758926 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1335 11:40:55.759049 == TX Byte 1 ==
1336 11:40:55.765817 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1337 11:40:55.769004 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1338 11:40:55.769133 ==
1339 11:40:55.772295 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 11:40:55.776161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 11:40:55.776319 ==
1342 11:40:55.789461 TX Vref=22, minBit 6, minWin=27, winSum=447
1343 11:40:55.792989 TX Vref=24, minBit 2, minWin=27, winSum=445
1344 11:40:55.796387 TX Vref=26, minBit 6, minWin=27, winSum=445
1345 11:40:55.799331 TX Vref=28, minBit 9, minWin=27, winSum=452
1346 11:40:55.803449 TX Vref=30, minBit 0, minWin=28, winSum=452
1347 11:40:55.806115 TX Vref=32, minBit 0, minWin=28, winSum=452
1348 11:40:55.812829 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1349 11:40:55.812979
1350 11:40:55.816582 Final TX Range 1 Vref 30
1351 11:40:55.816710
1352 11:40:55.816806 ==
1353 11:40:55.819856 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 11:40:55.822842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 11:40:55.822961 ==
1356 11:40:55.823054
1357 11:40:55.826304
1358 11:40:55.826418 TX Vref Scan disable
1359 11:40:55.829702 == TX Byte 0 ==
1360 11:40:55.832693 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1361 11:40:55.836093 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1362 11:40:55.839544 == TX Byte 1 ==
1363 11:40:55.843042 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1364 11:40:55.846243 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1365 11:40:55.849641
1366 11:40:55.849762 [DATLAT]
1367 11:40:55.849864 Freq=800, CH0 RK1
1368 11:40:55.849963
1369 11:40:55.853061 DATLAT Default: 0xa
1370 11:40:55.853182 0, 0xFFFF, sum = 0
1371 11:40:55.856045 1, 0xFFFF, sum = 0
1372 11:40:55.856162 2, 0xFFFF, sum = 0
1373 11:40:55.859370 3, 0xFFFF, sum = 0
1374 11:40:55.862435 4, 0xFFFF, sum = 0
1375 11:40:55.862555 5, 0xFFFF, sum = 0
1376 11:40:55.865829 6, 0xFFFF, sum = 0
1377 11:40:55.865963 7, 0xFFFF, sum = 0
1378 11:40:55.869164 8, 0xFFFF, sum = 0
1379 11:40:55.869281 9, 0x0, sum = 1
1380 11:40:55.872954 10, 0x0, sum = 2
1381 11:40:55.873078 11, 0x0, sum = 3
1382 11:40:55.873185 12, 0x0, sum = 4
1383 11:40:55.876129 best_step = 10
1384 11:40:55.876244
1385 11:40:55.876340 ==
1386 11:40:55.879431 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 11:40:55.882898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 11:40:55.883008 ==
1389 11:40:55.885971 RX Vref Scan: 0
1390 11:40:55.886082
1391 11:40:55.886174 RX Vref 0 -> 0, step: 1
1392 11:40:55.886262
1393 11:40:55.889305 RX Delay -95 -> 252, step: 8
1394 11:40:55.896309 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1395 11:40:55.899695 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1396 11:40:55.902994 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1397 11:40:55.906332 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1398 11:40:55.910064 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1399 11:40:55.915934 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1400 11:40:55.919378 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1401 11:40:55.922848 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1402 11:40:55.926254 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1403 11:40:55.930055 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1404 11:40:55.935976 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1405 11:40:55.939609 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1406 11:40:55.942739 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1407 11:40:55.946236 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1408 11:40:55.949855 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1409 11:40:55.956384 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1410 11:40:55.956507 ==
1411 11:40:55.959311 Dram Type= 6, Freq= 0, CH_0, rank 1
1412 11:40:55.962850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 11:40:55.962960 ==
1414 11:40:55.963053 DQS Delay:
1415 11:40:55.966220 DQS0 = 0, DQS1 = 0
1416 11:40:55.966327 DQM Delay:
1417 11:40:55.969185 DQM0 = 87, DQM1 = 78
1418 11:40:55.969301 DQ Delay:
1419 11:40:55.972539 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1420 11:40:55.976171 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1421 11:40:55.979210 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1422 11:40:55.982888 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1423 11:40:55.983012
1424 11:40:55.983120
1425 11:40:55.992702 [DQSOSCAuto] RK1, (LSB)MR18= 0x311a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1426 11:40:55.992861 CH0 RK1: MR19=606, MR18=311A
1427 11:40:55.999535 CH0_RK1: MR19=0x606, MR18=0x311A, DQSOSC=397, MR23=63, INC=93, DEC=62
1428 11:40:56.002962 [RxdqsGatingPostProcess] freq 800
1429 11:40:56.009403 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1430 11:40:56.013111 Pre-setting of DQS Precalculation
1431 11:40:56.016362 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1432 11:40:56.016490 ==
1433 11:40:56.019727 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 11:40:56.023236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 11:40:56.023355 ==
1436 11:40:56.029406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 11:40:56.036241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 11:40:56.044484 [CA 0] Center 36 (6~67) winsize 62
1439 11:40:56.047832 [CA 1] Center 36 (6~67) winsize 62
1440 11:40:56.051330 [CA 2] Center 34 (4~65) winsize 62
1441 11:40:56.054201 [CA 3] Center 34 (3~65) winsize 63
1442 11:40:56.057551 [CA 4] Center 33 (3~64) winsize 62
1443 11:40:56.060910 [CA 5] Center 33 (3~64) winsize 62
1444 11:40:56.061036
1445 11:40:56.064150 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1446 11:40:56.064261
1447 11:40:56.067405 [CATrainingPosCal] consider 1 rank data
1448 11:40:56.070897 u2DelayCellTimex100 = 270/100 ps
1449 11:40:56.074276 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1450 11:40:56.077404 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1451 11:40:56.084140 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1452 11:40:56.087924 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1453 11:40:56.090833 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1454 11:40:56.094291 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1455 11:40:56.094416
1456 11:40:56.097648 CA PerBit enable=1, Macro0, CA PI delay=33
1457 11:40:56.097766
1458 11:40:56.101088 [CBTSetCACLKResult] CA Dly = 33
1459 11:40:56.101212 CS Dly: 4 (0~35)
1460 11:40:56.101307 ==
1461 11:40:56.104794 Dram Type= 6, Freq= 0, CH_1, rank 1
1462 11:40:56.111273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 11:40:56.111449 ==
1464 11:40:56.114716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 11:40:56.121085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 11:40:56.130456 [CA 0] Center 36 (6~67) winsize 62
1467 11:40:56.133940 [CA 1] Center 36 (5~67) winsize 63
1468 11:40:56.137820 [CA 2] Center 34 (4~65) winsize 62
1469 11:40:56.141163 [CA 3] Center 34 (3~65) winsize 63
1470 11:40:56.145345 [CA 4] Center 34 (3~65) winsize 63
1471 11:40:56.149353 [CA 5] Center 33 (3~64) winsize 62
1472 11:40:56.149492
1473 11:40:56.152688 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1474 11:40:56.152805
1475 11:40:56.156341 [CATrainingPosCal] consider 2 rank data
1476 11:40:56.156461 u2DelayCellTimex100 = 270/100 ps
1477 11:40:56.160394 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1478 11:40:56.164047 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1479 11:40:56.167863 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1480 11:40:56.170982 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1481 11:40:56.177472 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1482 11:40:56.181191 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1483 11:40:56.181314
1484 11:40:56.184768 CA PerBit enable=1, Macro0, CA PI delay=33
1485 11:40:56.184887
1486 11:40:56.187827 [CBTSetCACLKResult] CA Dly = 33
1487 11:40:56.187938 CS Dly: 4 (0~36)
1488 11:40:56.188041
1489 11:40:56.191282 ----->DramcWriteLeveling(PI) begin...
1490 11:40:56.191415 ==
1491 11:40:56.194217 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 11:40:56.200776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 11:40:56.200922 ==
1494 11:40:56.204175 Write leveling (Byte 0): 29 => 29
1495 11:40:56.207507 Write leveling (Byte 1): 29 => 29
1496 11:40:56.207631 DramcWriteLeveling(PI) end<-----
1497 11:40:56.207726
1498 11:40:56.210956 ==
1499 11:40:56.211075 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 11:40:56.217599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 11:40:56.217742 ==
1502 11:40:56.220884 [Gating] SW mode calibration
1503 11:40:56.227476 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1504 11:40:56.230910 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1505 11:40:56.237714 0 6 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1506 11:40:56.241136 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1507 11:40:56.244473 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1508 11:40:56.251050 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:40:56.254401 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1510 11:40:56.257510 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 11:40:56.261009 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:40:56.267501 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:40:56.270997 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:40:56.274225 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:40:56.280761 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:40:56.284698 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1517 11:40:56.287971 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1518 11:40:56.294091 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1519 11:40:56.297758 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1520 11:40:56.300860 0 7 28 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1521 11:40:56.307539 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:40:56.310662 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1523 11:40:56.314160 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1524 11:40:56.320755 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:40:56.323962 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:40:56.327835 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:40:56.333993 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:40:56.337464 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1529 11:40:56.340887 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:40:56.347319 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:40:56.350825 0 9 8 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
1532 11:40:56.354480 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1533 11:40:56.360928 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 11:40:56.364446 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1535 11:40:56.367325 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 11:40:56.370972 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1537 11:40:56.377909 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 11:40:56.381053 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1539 11:40:56.384461 0 10 8 | B1->B0 | 2e2e 2f2f | 0 0 | (0 1) (0 1)
1540 11:40:56.390849 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:40:56.394371 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:40:56.397180 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1543 11:40:56.403889 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1544 11:40:56.407586 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:40:56.410843 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:40:56.417459 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:40:56.420526 0 11 8 | B1->B0 | 3636 3232 | 0 0 | (0 0) (1 1)
1548 11:40:56.424038 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 11:40:56.430441 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 11:40:56.433919 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 11:40:56.437308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 11:40:56.444070 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 11:40:56.447623 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 11:40:56.450671 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:40:56.457617 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1556 11:40:56.460893 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 11:40:56.464040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 11:40:56.470925 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 11:40:56.473881 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 11:40:56.477091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:40:56.484004 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:40:56.487422 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:40:56.490866 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:40:56.493979 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:40:56.500943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:40:56.504105 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:40:56.507259 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:40:56.514077 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:40:56.517213 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:40:56.520730 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:40:56.526957 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1572 11:40:56.530395 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 11:40:56.533899 Total UI for P1: 0, mck2ui 16
1574 11:40:56.537355 best dqsien dly found for B0: ( 0, 14, 8)
1575 11:40:56.540212 Total UI for P1: 0, mck2ui 16
1576 11:40:56.543612 best dqsien dly found for B1: ( 0, 14, 8)
1577 11:40:56.546986 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1578 11:40:56.550411 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1579 11:40:56.550501
1580 11:40:56.553588 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1581 11:40:56.557384 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1582 11:40:56.560324 [Gating] SW calibration Done
1583 11:40:56.560412 ==
1584 11:40:56.563754 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 11:40:56.567106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 11:40:56.570456 ==
1587 11:40:56.570545 RX Vref Scan: 0
1588 11:40:56.570610
1589 11:40:56.573891 RX Vref 0 -> 0, step: 1
1590 11:40:56.573984
1591 11:40:56.576771 RX Delay -130 -> 252, step: 16
1592 11:40:56.580398 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1593 11:40:56.584352 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1594 11:40:56.587196 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1595 11:40:56.590513 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1596 11:40:56.596736 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1597 11:40:56.600433 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1598 11:40:56.604125 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1599 11:40:56.606923 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1600 11:40:56.610056 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1601 11:40:56.616924 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1602 11:40:56.620180 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1603 11:40:56.623612 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1604 11:40:56.626766 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1605 11:40:56.630430 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1606 11:40:56.636886 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1607 11:40:56.640332 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1608 11:40:56.640454 ==
1609 11:40:56.643901 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 11:40:56.647126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 11:40:56.647260 ==
1612 11:40:56.650438 DQS Delay:
1613 11:40:56.650526 DQS0 = 0, DQS1 = 0
1614 11:40:56.650591 DQM Delay:
1615 11:40:56.653977 DQM0 = 82, DQM1 = 74
1616 11:40:56.654064 DQ Delay:
1617 11:40:56.656997 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1618 11:40:56.660300 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1619 11:40:56.663892 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1620 11:40:56.666901 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1621 11:40:56.667013
1622 11:40:56.667110
1623 11:40:56.667202 ==
1624 11:40:56.670419 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:40:56.673929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:40:56.676821 ==
1627 11:40:56.676933
1628 11:40:56.677025
1629 11:40:56.677114 TX Vref Scan disable
1630 11:40:56.680401 == TX Byte 0 ==
1631 11:40:56.683904 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1632 11:40:56.686956 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1633 11:40:56.690369 == TX Byte 1 ==
1634 11:40:56.693881 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1635 11:40:56.697188 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1636 11:40:56.700049 ==
1637 11:40:56.703606 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 11:40:56.706884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 11:40:56.706971 ==
1640 11:40:56.719534 TX Vref=22, minBit 8, minWin=26, winSum=434
1641 11:40:56.723206 TX Vref=24, minBit 11, minWin=26, winSum=440
1642 11:40:56.726587 TX Vref=26, minBit 3, minWin=27, winSum=444
1643 11:40:56.729557 TX Vref=28, minBit 3, minWin=27, winSum=448
1644 11:40:56.732979 TX Vref=30, minBit 13, minWin=27, winSum=452
1645 11:40:56.736033 TX Vref=32, minBit 5, minWin=28, winSum=455
1646 11:40:56.742710 [TxChooseVref] Worse bit 5, Min win 28, Win sum 455, Final Vref 32
1647 11:40:56.742847
1648 11:40:56.746711 Final TX Range 1 Vref 32
1649 11:40:56.746799
1650 11:40:56.746864 ==
1651 11:40:56.749418 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 11:40:56.753043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 11:40:56.753132 ==
1654 11:40:56.753196
1655 11:40:56.753255
1656 11:40:56.756783 TX Vref Scan disable
1657 11:40:56.759784 == TX Byte 0 ==
1658 11:40:56.762980 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1659 11:40:56.766289 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1660 11:40:56.769790 == TX Byte 1 ==
1661 11:40:56.773282 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1662 11:40:56.776042 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1663 11:40:56.776133
1664 11:40:56.779606 [DATLAT]
1665 11:40:56.779690 Freq=800, CH1 RK0
1666 11:40:56.779754
1667 11:40:56.782997 DATLAT Default: 0xa
1668 11:40:56.783080 0, 0xFFFF, sum = 0
1669 11:40:56.786742 1, 0xFFFF, sum = 0
1670 11:40:56.786826 2, 0xFFFF, sum = 0
1671 11:40:56.789681 3, 0xFFFF, sum = 0
1672 11:40:56.789768 4, 0xFFFF, sum = 0
1673 11:40:56.793145 5, 0xFFFF, sum = 0
1674 11:40:56.793232 6, 0xFFFF, sum = 0
1675 11:40:56.796180 7, 0xFFFF, sum = 0
1676 11:40:56.796267 8, 0xFFFF, sum = 0
1677 11:40:56.799319 9, 0x0, sum = 1
1678 11:40:56.799445 10, 0x0, sum = 2
1679 11:40:56.802948 11, 0x0, sum = 3
1680 11:40:56.803037 12, 0x0, sum = 4
1681 11:40:56.806026 best_step = 10
1682 11:40:56.806097
1683 11:40:56.806159 ==
1684 11:40:56.809586 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 11:40:56.813416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 11:40:56.813511 ==
1687 11:40:56.816006 RX Vref Scan: 1
1688 11:40:56.816094
1689 11:40:56.816177 Set Vref Range= 32 -> 127
1690 11:40:56.816268
1691 11:40:56.819737 RX Vref 32 -> 127, step: 1
1692 11:40:56.819825
1693 11:40:56.822954 RX Delay -111 -> 252, step: 8
1694 11:40:56.823039
1695 11:40:56.825924 Set Vref, RX VrefLevel [Byte0]: 32
1696 11:40:56.830020 [Byte1]: 32
1697 11:40:56.830113
1698 11:40:56.832620 Set Vref, RX VrefLevel [Byte0]: 33
1699 11:40:56.836414 [Byte1]: 33
1700 11:40:56.839702
1701 11:40:56.839806 Set Vref, RX VrefLevel [Byte0]: 34
1702 11:40:56.842873 [Byte1]: 34
1703 11:40:56.846848
1704 11:40:56.846936 Set Vref, RX VrefLevel [Byte0]: 35
1705 11:40:56.850183 [Byte1]: 35
1706 11:40:56.854818
1707 11:40:56.854913 Set Vref, RX VrefLevel [Byte0]: 36
1708 11:40:56.858125 [Byte1]: 36
1709 11:40:56.862629
1710 11:40:56.862729 Set Vref, RX VrefLevel [Byte0]: 37
1711 11:40:56.865994 [Byte1]: 37
1712 11:40:56.869932
1713 11:40:56.870067 Set Vref, RX VrefLevel [Byte0]: 38
1714 11:40:56.873442 [Byte1]: 38
1715 11:40:56.877989
1716 11:40:56.878107 Set Vref, RX VrefLevel [Byte0]: 39
1717 11:40:56.880836 [Byte1]: 39
1718 11:40:56.885507
1719 11:40:56.885620 Set Vref, RX VrefLevel [Byte0]: 40
1720 11:40:56.888796 [Byte1]: 40
1721 11:40:56.893252
1722 11:40:56.893385 Set Vref, RX VrefLevel [Byte0]: 41
1723 11:40:56.896076 [Byte1]: 41
1724 11:40:56.900850
1725 11:40:56.900958 Set Vref, RX VrefLevel [Byte0]: 42
1726 11:40:56.903933 [Byte1]: 42
1727 11:40:56.908576
1728 11:40:56.908689 Set Vref, RX VrefLevel [Byte0]: 43
1729 11:40:56.911565 [Byte1]: 43
1730 11:40:56.915783
1731 11:40:56.915901 Set Vref, RX VrefLevel [Byte0]: 44
1732 11:40:56.919201 [Byte1]: 44
1733 11:40:56.923497
1734 11:40:56.923591 Set Vref, RX VrefLevel [Byte0]: 45
1735 11:40:56.926811 [Byte1]: 45
1736 11:40:56.931312
1737 11:40:56.931430 Set Vref, RX VrefLevel [Byte0]: 46
1738 11:40:56.934681 [Byte1]: 46
1739 11:40:56.938884
1740 11:40:56.938994 Set Vref, RX VrefLevel [Byte0]: 47
1741 11:40:56.942267 [Byte1]: 47
1742 11:40:56.946514
1743 11:40:56.946619 Set Vref, RX VrefLevel [Byte0]: 48
1744 11:40:56.949847 [Byte1]: 48
1745 11:40:56.954069
1746 11:40:56.954164 Set Vref, RX VrefLevel [Byte0]: 49
1747 11:40:56.957284 [Byte1]: 49
1748 11:40:56.961725
1749 11:40:56.961850 Set Vref, RX VrefLevel [Byte0]: 50
1750 11:40:56.965005 [Byte1]: 50
1751 11:40:56.969649
1752 11:40:56.969749 Set Vref, RX VrefLevel [Byte0]: 51
1753 11:40:56.972604 [Byte1]: 51
1754 11:40:56.977293
1755 11:40:56.977398 Set Vref, RX VrefLevel [Byte0]: 52
1756 11:40:56.980125 [Byte1]: 52
1757 11:40:56.984541
1758 11:40:56.984636 Set Vref, RX VrefLevel [Byte0]: 53
1759 11:40:56.988114 [Byte1]: 53
1760 11:40:56.992577
1761 11:40:56.992668 Set Vref, RX VrefLevel [Byte0]: 54
1762 11:40:56.995505 [Byte1]: 54
1763 11:40:57.000186
1764 11:40:57.000278 Set Vref, RX VrefLevel [Byte0]: 55
1765 11:40:57.003070 [Byte1]: 55
1766 11:40:57.007505
1767 11:40:57.007596 Set Vref, RX VrefLevel [Byte0]: 56
1768 11:40:57.010899 [Byte1]: 56
1769 11:40:57.015514
1770 11:40:57.015643 Set Vref, RX VrefLevel [Byte0]: 57
1771 11:40:57.018462 [Byte1]: 57
1772 11:40:57.022938
1773 11:40:57.023032 Set Vref, RX VrefLevel [Byte0]: 58
1774 11:40:57.026298 [Byte1]: 58
1775 11:40:57.030407
1776 11:40:57.030500 Set Vref, RX VrefLevel [Byte0]: 59
1777 11:40:57.033645 [Byte1]: 59
1778 11:40:57.038382
1779 11:40:57.038497 Set Vref, RX VrefLevel [Byte0]: 60
1780 11:40:57.041546 [Byte1]: 60
1781 11:40:57.046057
1782 11:40:57.046155 Set Vref, RX VrefLevel [Byte0]: 61
1783 11:40:57.049813 [Byte1]: 61
1784 11:40:57.053444
1785 11:40:57.053539 Set Vref, RX VrefLevel [Byte0]: 62
1786 11:40:57.057036 [Byte1]: 62
1787 11:40:57.061321
1788 11:40:57.061417 Set Vref, RX VrefLevel [Byte0]: 63
1789 11:40:57.064579 [Byte1]: 63
1790 11:40:57.068575
1791 11:40:57.068670 Set Vref, RX VrefLevel [Byte0]: 64
1792 11:40:57.072063 [Byte1]: 64
1793 11:40:57.076672
1794 11:40:57.076777 Set Vref, RX VrefLevel [Byte0]: 65
1795 11:40:57.080096 [Byte1]: 65
1796 11:40:57.084215
1797 11:40:57.084325 Set Vref, RX VrefLevel [Byte0]: 66
1798 11:40:57.087177 [Byte1]: 66
1799 11:40:57.092199
1800 11:40:57.092304 Set Vref, RX VrefLevel [Byte0]: 67
1801 11:40:57.094945 [Byte1]: 67
1802 11:40:57.099728
1803 11:40:57.099843 Set Vref, RX VrefLevel [Byte0]: 68
1804 11:40:57.102670 [Byte1]: 68
1805 11:40:57.107150
1806 11:40:57.107246 Set Vref, RX VrefLevel [Byte0]: 69
1807 11:40:57.110446 [Byte1]: 69
1808 11:40:57.114894
1809 11:40:57.114993 Set Vref, RX VrefLevel [Byte0]: 70
1810 11:40:57.118804 [Byte1]: 70
1811 11:40:57.122213
1812 11:40:57.122305 Set Vref, RX VrefLevel [Byte0]: 71
1813 11:40:57.125618 [Byte1]: 71
1814 11:40:57.130268
1815 11:40:57.130364 Set Vref, RX VrefLevel [Byte0]: 72
1816 11:40:57.133151 [Byte1]: 72
1817 11:40:57.137666
1818 11:40:57.137764 Set Vref, RX VrefLevel [Byte0]: 73
1819 11:40:57.141123 [Byte1]: 73
1820 11:40:57.145663
1821 11:40:57.145756 Set Vref, RX VrefLevel [Byte0]: 74
1822 11:40:57.148782 [Byte1]: 74
1823 11:40:57.152893
1824 11:40:57.152979 Set Vref, RX VrefLevel [Byte0]: 75
1825 11:40:57.156620 [Byte1]: 75
1826 11:40:57.160556
1827 11:40:57.160645 Set Vref, RX VrefLevel [Byte0]: 76
1828 11:40:57.163891 [Byte1]: 76
1829 11:40:57.168468
1830 11:40:57.168556 Set Vref, RX VrefLevel [Byte0]: 77
1831 11:40:57.171521 [Byte1]: 77
1832 11:40:57.176017
1833 11:40:57.176123 Final RX Vref Byte 0 = 59 to rank0
1834 11:40:57.179432 Final RX Vref Byte 1 = 60 to rank0
1835 11:40:57.182563 Final RX Vref Byte 0 = 59 to rank1
1836 11:40:57.185963 Final RX Vref Byte 1 = 60 to rank1==
1837 11:40:57.189576 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 11:40:57.195810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 11:40:57.195914 ==
1840 11:40:57.196003 DQS Delay:
1841 11:40:57.196067 DQS0 = 0, DQS1 = 0
1842 11:40:57.199207 DQM Delay:
1843 11:40:57.199279 DQM0 = 83, DQM1 = 74
1844 11:40:57.202687 DQ Delay:
1845 11:40:57.206195 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1846 11:40:57.206273 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1847 11:40:57.209096 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =76
1848 11:40:57.212597 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1849 11:40:57.215981
1850 11:40:57.216080
1851 11:40:57.222343 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1852 11:40:57.225805 CH1 RK0: MR19=606, MR18=2A00
1853 11:40:57.232568 CH1_RK0: MR19=0x606, MR18=0x2A00, DQSOSC=399, MR23=63, INC=92, DEC=61
1854 11:40:57.232667
1855 11:40:57.236208 ----->DramcWriteLeveling(PI) begin...
1856 11:40:57.236290 ==
1857 11:40:57.239402 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 11:40:57.242991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 11:40:57.243086 ==
1860 11:40:57.245793 Write leveling (Byte 0): 28 => 28
1861 11:40:57.249723 Write leveling (Byte 1): 28 => 28
1862 11:40:57.252583 DramcWriteLeveling(PI) end<-----
1863 11:40:57.252661
1864 11:40:57.252724 ==
1865 11:40:57.255830 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 11:40:57.259196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 11:40:57.259289 ==
1868 11:40:57.262827 [Gating] SW mode calibration
1869 11:40:57.269194 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 11:40:57.276284 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 11:40:57.279185 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 11:40:57.282707 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1873 11:40:57.288986 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1874 11:40:57.293243 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:40:57.296045 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:40:57.302610 0 6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1877 11:40:57.306082 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:40:57.309543 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:40:57.315947 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:40:57.319255 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:40:57.322813 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:40:57.326361 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:40:57.332622 0 7 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1884 11:40:57.336120 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1885 11:40:57.339658 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:40:57.346056 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1887 11:40:57.349427 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1888 11:40:57.353177 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1889 11:40:57.359963 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1890 11:40:57.362627 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:40:57.366082 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:40:57.372928 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:40:57.376258 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:40:57.379309 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:40:57.386009 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1896 11:40:57.389366 0 9 4 | B1->B0 | 2323 2424 | 1 1 | (1 1) (1 1)
1897 11:40:57.392699 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1898 11:40:57.399239 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1899 11:40:57.402606 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 11:40:57.406159 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 11:40:57.412543 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 11:40:57.415816 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 11:40:57.419657 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 11:40:57.422972 0 10 4 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (1 1)
1905 11:40:57.429121 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1906 11:40:57.432506 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1907 11:40:57.436008 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:40:57.442907 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:40:57.446168 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1910 11:40:57.449757 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:40:57.455941 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1912 11:40:57.459403 0 11 4 | B1->B0 | 2a2a 3c3c | 1 0 | (0 0) (0 0)
1913 11:40:57.462403 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1914 11:40:57.469420 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:40:57.472614 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 11:40:57.475883 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 11:40:57.482965 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 11:40:57.486164 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 11:40:57.489458 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 11:40:57.495937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1921 11:40:57.499733 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:40:57.503040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:40:57.506050 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:40:57.512704 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:40:57.516082 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:40:57.519634 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:40:57.525945 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:40:57.529899 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:40:57.532865 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:40:57.539804 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:40:57.542699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:40:57.546269 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:40:57.552740 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:40:57.555993 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:40:57.559202 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:40:57.566118 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1937 11:40:57.569449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1938 11:40:57.572594 Total UI for P1: 0, mck2ui 16
1939 11:40:57.576230 best dqsien dly found for B0: ( 0, 14, 4)
1940 11:40:57.579337 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 11:40:57.582465 Total UI for P1: 0, mck2ui 16
1942 11:40:57.585838 best dqsien dly found for B1: ( 0, 14, 8)
1943 11:40:57.589740 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1944 11:40:57.593160 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1945 11:40:57.593252
1946 11:40:57.596230 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 11:40:57.602859 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1948 11:40:57.602967 [Gating] SW calibration Done
1949 11:40:57.603032 ==
1950 11:40:57.605969 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 11:40:57.612970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 11:40:57.613074 ==
1953 11:40:57.613140 RX Vref Scan: 0
1954 11:40:57.613200
1955 11:40:57.615970 RX Vref 0 -> 0, step: 1
1956 11:40:57.616053
1957 11:40:57.619854 RX Delay -130 -> 252, step: 16
1958 11:40:57.622807 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1959 11:40:57.626260 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1960 11:40:57.629942 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1961 11:40:57.632783 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
1962 11:40:57.639653 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1963 11:40:57.643393 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1964 11:40:57.645909 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1965 11:40:57.649670 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1966 11:40:57.652736 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1967 11:40:57.659372 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1968 11:40:57.662857 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1969 11:40:57.666058 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1970 11:40:57.669571 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1971 11:40:57.673370 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1972 11:40:57.679694 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1973 11:40:57.682637 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1974 11:40:57.682729 ==
1975 11:40:57.686276 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 11:40:57.689357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 11:40:57.689457 ==
1978 11:40:57.692724 DQS Delay:
1979 11:40:57.692819 DQS0 = 0, DQS1 = 0
1980 11:40:57.692883 DQM Delay:
1981 11:40:57.696181 DQM0 = 78, DQM1 = 77
1982 11:40:57.696294 DQ Delay:
1983 11:40:57.699500 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1984 11:40:57.702900 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1985 11:40:57.706145 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1986 11:40:57.709293 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1987 11:40:57.709405
1988 11:40:57.709531
1989 11:40:57.709607 ==
1990 11:40:57.713121 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 11:40:57.719667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 11:40:57.719806 ==
1993 11:40:57.719893
1994 11:40:57.719985
1995 11:40:57.720060 TX Vref Scan disable
1996 11:40:57.723046 == TX Byte 0 ==
1997 11:40:57.726440 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1998 11:40:57.732806 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1999 11:40:57.732904 == TX Byte 1 ==
2000 11:40:57.736609 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2001 11:40:57.742942 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2002 11:40:57.743052 ==
2003 11:40:57.746150 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 11:40:57.749571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 11:40:57.749683 ==
2006 11:40:57.761641 TX Vref=22, minBit 4, minWin=27, winSum=441
2007 11:40:57.764975 TX Vref=24, minBit 9, minWin=27, winSum=444
2008 11:40:57.768778 TX Vref=26, minBit 0, minWin=27, winSum=446
2009 11:40:57.772042 TX Vref=28, minBit 11, minWin=27, winSum=451
2010 11:40:57.775471 TX Vref=30, minBit 3, minWin=28, winSum=454
2011 11:40:57.781751 TX Vref=32, minBit 9, minWin=27, winSum=450
2012 11:40:57.785041 [TxChooseVref] Worse bit 3, Min win 28, Win sum 454, Final Vref 30
2013 11:40:57.785142
2014 11:40:57.788745 Final TX Range 1 Vref 30
2015 11:40:57.788836
2016 11:40:57.788905 ==
2017 11:40:57.791620 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:40:57.794966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:40:57.795057 ==
2020 11:40:57.798343
2021 11:40:57.798433
2022 11:40:57.798500 TX Vref Scan disable
2023 11:40:57.801667 == TX Byte 0 ==
2024 11:40:57.804931 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2025 11:40:57.811585 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2026 11:40:57.811721 == TX Byte 1 ==
2027 11:40:57.815137 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2028 11:40:57.821899 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2029 11:40:57.822046
2030 11:40:57.822144 [DATLAT]
2031 11:40:57.822238 Freq=800, CH1 RK1
2032 11:40:57.822331
2033 11:40:57.825030 DATLAT Default: 0xa
2034 11:40:57.825133 0, 0xFFFF, sum = 0
2035 11:40:57.828544 1, 0xFFFF, sum = 0
2036 11:40:57.828660 2, 0xFFFF, sum = 0
2037 11:40:57.832019 3, 0xFFFF, sum = 0
2038 11:40:57.832127 4, 0xFFFF, sum = 0
2039 11:40:57.835806 5, 0xFFFF, sum = 0
2040 11:40:57.838639 6, 0xFFFF, sum = 0
2041 11:40:57.838758 7, 0xFFFF, sum = 0
2042 11:40:57.842005 8, 0xFFFF, sum = 0
2043 11:40:57.842115 9, 0x0, sum = 1
2044 11:40:57.842211 10, 0x0, sum = 2
2045 11:40:57.845497 11, 0x0, sum = 3
2046 11:40:57.845615 12, 0x0, sum = 4
2047 11:40:57.848422 best_step = 10
2048 11:40:57.848533
2049 11:40:57.848632 ==
2050 11:40:57.851933 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 11:40:57.855419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 11:40:57.855537 ==
2053 11:40:57.858799 RX Vref Scan: 0
2054 11:40:57.858896
2055 11:40:57.858988 RX Vref 0 -> 0, step: 1
2056 11:40:57.859082
2057 11:40:57.861612 RX Delay -95 -> 252, step: 8
2058 11:40:57.868376 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2059 11:40:57.871927 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2060 11:40:57.875110 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2061 11:40:57.878508 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2062 11:40:57.881841 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2063 11:40:57.888225 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2064 11:40:57.891589 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2065 11:40:57.894990 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2066 11:40:57.898198 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2067 11:40:57.902164 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2068 11:40:57.909040 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2069 11:40:57.912068 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2070 11:40:57.915331 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2071 11:40:57.918503 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2072 11:40:57.921956 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2073 11:40:57.928574 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2074 11:40:57.928687 ==
2075 11:40:57.931619 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 11:40:57.935296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 11:40:57.935453 ==
2078 11:40:57.935547 DQS Delay:
2079 11:40:57.938254 DQS0 = 0, DQS1 = 0
2080 11:40:57.938337 DQM Delay:
2081 11:40:57.941640 DQM0 = 80, DQM1 = 75
2082 11:40:57.941720 DQ Delay:
2083 11:40:57.944975 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2084 11:40:57.948416 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
2085 11:40:57.951910 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2086 11:40:57.955271 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2087 11:40:57.955402
2088 11:40:57.955491
2089 11:40:57.965237 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
2090 11:40:57.965355 CH1 RK1: MR19=606, MR18=1C27
2091 11:40:57.971943 CH1_RK1: MR19=0x606, MR18=0x1C27, DQSOSC=400, MR23=63, INC=92, DEC=61
2092 11:40:57.975112 [RxdqsGatingPostProcess] freq 800
2093 11:40:57.981582 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2094 11:40:57.984876 Pre-setting of DQS Precalculation
2095 11:40:57.988472 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2096 11:40:57.995237 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2097 11:40:58.001546 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2098 11:40:58.001660
2099 11:40:58.001747
2100 11:40:58.004894 [Calibration Summary] 1600 Mbps
2101 11:40:58.008723 CH 0, Rank 0
2102 11:40:58.008813 SW Impedance : PASS
2103 11:40:58.012015 DUTY Scan : NO K
2104 11:40:58.014944 ZQ Calibration : PASS
2105 11:40:58.015092 Jitter Meter : NO K
2106 11:40:58.018353 CBT Training : PASS
2107 11:40:58.021960 Write leveling : PASS
2108 11:40:58.022078 RX DQS gating : PASS
2109 11:40:58.024941 RX DQ/DQS(RDDQC) : PASS
2110 11:40:58.028212 TX DQ/DQS : PASS
2111 11:40:58.028322 RX DATLAT : PASS
2112 11:40:58.031957 RX DQ/DQS(Engine): PASS
2113 11:40:58.032064 TX OE : NO K
2114 11:40:58.035145 All Pass.
2115 11:40:58.035247
2116 11:40:58.035340 CH 0, Rank 1
2117 11:40:58.038546 SW Impedance : PASS
2118 11:40:58.038626 DUTY Scan : NO K
2119 11:40:58.041690 ZQ Calibration : PASS
2120 11:40:58.045208 Jitter Meter : NO K
2121 11:40:58.045315 CBT Training : PASS
2122 11:40:58.048544 Write leveling : PASS
2123 11:40:58.051859 RX DQS gating : PASS
2124 11:40:58.051937 RX DQ/DQS(RDDQC) : PASS
2125 11:40:58.055195 TX DQ/DQS : PASS
2126 11:40:58.058472 RX DATLAT : PASS
2127 11:40:58.058558 RX DQ/DQS(Engine): PASS
2128 11:40:58.061628 TX OE : NO K
2129 11:40:58.061714 All Pass.
2130 11:40:58.061778
2131 11:40:58.064877 CH 1, Rank 0
2132 11:40:58.064962 SW Impedance : PASS
2133 11:40:58.068316 DUTY Scan : NO K
2134 11:40:58.071633 ZQ Calibration : PASS
2135 11:40:58.071748 Jitter Meter : NO K
2136 11:40:58.075179 CBT Training : PASS
2137 11:40:58.075301 Write leveling : PASS
2138 11:40:58.078439 RX DQS gating : PASS
2139 11:40:58.081984 RX DQ/DQS(RDDQC) : PASS
2140 11:40:58.082104 TX DQ/DQS : PASS
2141 11:40:58.084898 RX DATLAT : PASS
2142 11:40:58.088380 RX DQ/DQS(Engine): PASS
2143 11:40:58.088493 TX OE : NO K
2144 11:40:58.091941 All Pass.
2145 11:40:58.092047
2146 11:40:58.092143 CH 1, Rank 1
2147 11:40:58.095113 SW Impedance : PASS
2148 11:40:58.095217 DUTY Scan : NO K
2149 11:40:58.098572 ZQ Calibration : PASS
2150 11:40:58.101543 Jitter Meter : NO K
2151 11:40:58.101647 CBT Training : PASS
2152 11:40:58.104897 Write leveling : PASS
2153 11:40:58.108257 RX DQS gating : PASS
2154 11:40:58.108336 RX DQ/DQS(RDDQC) : PASS
2155 11:40:58.111658 TX DQ/DQS : PASS
2156 11:40:58.115008 RX DATLAT : PASS
2157 11:40:58.115113 RX DQ/DQS(Engine): PASS
2158 11:40:58.118177 TX OE : NO K
2159 11:40:58.118264 All Pass.
2160 11:40:58.118327
2161 11:40:58.121414 DramC Write-DBI off
2162 11:40:58.125115 PER_BANK_REFRESH: Hybrid Mode
2163 11:40:58.125191 TX_TRACKING: ON
2164 11:40:58.128361 [GetDramInforAfterCalByMRR] Vendor 6.
2165 11:40:58.131743 [GetDramInforAfterCalByMRR] Revision 606.
2166 11:40:58.135151 [GetDramInforAfterCalByMRR] Revision 2 0.
2167 11:40:58.138344 MR0 0x3b3b
2168 11:40:58.138423 MR8 0x5151
2169 11:40:58.141634 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 11:40:58.141713
2171 11:40:58.141774 MR0 0x3b3b
2172 11:40:58.145022 MR8 0x5151
2173 11:40:58.148495 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 11:40:58.148607
2175 11:40:58.155044 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2176 11:40:58.161813 [FAST_K] Save calibration result to emmc
2177 11:40:58.165060 [FAST_K] Save calibration result to emmc
2178 11:40:58.165157 dram_init: config_dvfs: 1
2179 11:40:58.171517 dramc_set_vcore_voltage set vcore to 662500
2180 11:40:58.171619 Read voltage for 1200, 2
2181 11:40:58.171685 Vio18 = 0
2182 11:40:58.174830 Vcore = 662500
2183 11:40:58.174941 Vdram = 0
2184 11:40:58.175034 Vddq = 0
2185 11:40:58.178338 Vmddr = 0
2186 11:40:58.181771 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2187 11:40:58.187889 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2188 11:40:58.188040 MEM_TYPE=3, freq_sel=15
2189 11:40:58.191293 sv_algorithm_assistance_LP4_1600
2190 11:40:58.198123 ============ PULL DRAM RESETB DOWN ============
2191 11:40:58.201998 ========== PULL DRAM RESETB DOWN end =========
2192 11:40:58.205142 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 11:40:58.208017 ===================================
2194 11:40:58.211288 LPDDR4 DRAM CONFIGURATION
2195 11:40:58.214809 ===================================
2196 11:40:58.218198 EX_ROW_EN[0] = 0x0
2197 11:40:58.218305 EX_ROW_EN[1] = 0x0
2198 11:40:58.221301 LP4Y_EN = 0x0
2199 11:40:58.221399 WORK_FSP = 0x0
2200 11:40:58.224811 WL = 0x4
2201 11:40:58.224887 RL = 0x4
2202 11:40:58.228019 BL = 0x2
2203 11:40:58.228096 RPST = 0x0
2204 11:40:58.231190 RD_PRE = 0x0
2205 11:40:58.231287 WR_PRE = 0x1
2206 11:40:58.234836 WR_PST = 0x0
2207 11:40:58.234909 DBI_WR = 0x0
2208 11:40:58.237904 DBI_RD = 0x0
2209 11:40:58.238007 OTF = 0x1
2210 11:40:58.241633 ===================================
2211 11:40:58.244957 ===================================
2212 11:40:58.248264 ANA top config
2213 11:40:58.251344 ===================================
2214 11:40:58.254558 DLL_ASYNC_EN = 0
2215 11:40:58.254673 ALL_SLAVE_EN = 0
2216 11:40:58.257914 NEW_RANK_MODE = 1
2217 11:40:58.261322 DLL_IDLE_MODE = 1
2218 11:40:58.264830 LP45_APHY_COMB_EN = 1
2219 11:40:58.264926 TX_ODT_DIS = 1
2220 11:40:58.268263 NEW_8X_MODE = 1
2221 11:40:58.271206 ===================================
2222 11:40:58.274747 ===================================
2223 11:40:58.278159 data_rate = 2400
2224 11:40:58.281561 CKR = 1
2225 11:40:58.284635 DQ_P2S_RATIO = 8
2226 11:40:58.287935 ===================================
2227 11:40:58.291068 CA_P2S_RATIO = 8
2228 11:40:58.291173 DQ_CA_OPEN = 0
2229 11:40:58.294366 DQ_SEMI_OPEN = 0
2230 11:40:58.298002 CA_SEMI_OPEN = 0
2231 11:40:58.301405 CA_FULL_RATE = 0
2232 11:40:58.304814 DQ_CKDIV4_EN = 0
2233 11:40:58.304906 CA_CKDIV4_EN = 0
2234 11:40:58.308733 CA_PREDIV_EN = 0
2235 11:40:58.311053 PH8_DLY = 17
2236 11:40:58.314497 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2237 11:40:58.317918 DQ_AAMCK_DIV = 4
2238 11:40:58.321133 CA_AAMCK_DIV = 4
2239 11:40:58.321236 CA_ADMCK_DIV = 4
2240 11:40:58.324490 DQ_TRACK_CA_EN = 0
2241 11:40:58.327887 CA_PICK = 1200
2242 11:40:58.331045 CA_MCKIO = 1200
2243 11:40:58.334946 MCKIO_SEMI = 0
2244 11:40:58.338067 PLL_FREQ = 2366
2245 11:40:58.341116 DQ_UI_PI_RATIO = 32
2246 11:40:58.344975 CA_UI_PI_RATIO = 0
2247 11:40:58.347541 ===================================
2248 11:40:58.351167 ===================================
2249 11:40:58.351298 memory_type:LPDDR4
2250 11:40:58.354376 GP_NUM : 10
2251 11:40:58.357508 SRAM_EN : 1
2252 11:40:58.357656 MD32_EN : 0
2253 11:40:58.361302 ===================================
2254 11:40:58.364906 [ANA_INIT] >>>>>>>>>>>>>>
2255 11:40:58.367601 <<<<<< [CONFIGURE PHASE]: ANA_TX
2256 11:40:58.371047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2257 11:40:58.374451 ===================================
2258 11:40:58.377795 data_rate = 2400,PCW = 0X5b00
2259 11:40:58.377933 ===================================
2260 11:40:58.384373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2261 11:40:58.388125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 11:40:58.394823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 11:40:58.397477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2264 11:40:58.401060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2265 11:40:58.404502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2266 11:40:58.407904 [ANA_INIT] flow start
2267 11:40:58.411039 [ANA_INIT] PLL >>>>>>>>
2268 11:40:58.411142 [ANA_INIT] PLL <<<<<<<<
2269 11:40:58.414566 [ANA_INIT] MIDPI >>>>>>>>
2270 11:40:58.417469 [ANA_INIT] MIDPI <<<<<<<<
2271 11:40:58.417566 [ANA_INIT] DLL >>>>>>>>
2272 11:40:58.421021 [ANA_INIT] DLL <<<<<<<<
2273 11:40:58.424369 [ANA_INIT] flow end
2274 11:40:58.427682 ============ LP4 DIFF to SE enter ============
2275 11:40:58.430913 ============ LP4 DIFF to SE exit ============
2276 11:40:58.434632 [ANA_INIT] <<<<<<<<<<<<<
2277 11:40:58.437671 [Flow] Enable top DCM control >>>>>
2278 11:40:58.440968 [Flow] Enable top DCM control <<<<<
2279 11:40:58.444381 Enable DLL master slave shuffle
2280 11:40:58.447806 ==============================================================
2281 11:40:58.451083 Gating Mode config
2282 11:40:58.457687 ==============================================================
2283 11:40:58.457793 Config description:
2284 11:40:58.467790 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2285 11:40:58.474519 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2286 11:40:58.477831 SELPH_MODE 0: By rank 1: By Phase
2287 11:40:58.484497 ==============================================================
2288 11:40:58.487552 GAT_TRACK_EN = 1
2289 11:40:58.490875 RX_GATING_MODE = 2
2290 11:40:58.494341 RX_GATING_TRACK_MODE = 2
2291 11:40:58.497710 SELPH_MODE = 1
2292 11:40:58.501182 PICG_EARLY_EN = 1
2293 11:40:58.501269 VALID_LAT_VALUE = 1
2294 11:40:58.507579 ==============================================================
2295 11:40:58.511003 Enter into Gating configuration >>>>
2296 11:40:58.514282 Exit from Gating configuration <<<<
2297 11:40:58.517657 Enter into DVFS_PRE_config >>>>>
2298 11:40:58.527410 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2299 11:40:58.530788 Exit from DVFS_PRE_config <<<<<
2300 11:40:58.534148 Enter into PICG configuration >>>>
2301 11:40:58.537660 Exit from PICG configuration <<<<
2302 11:40:58.541030 [RX_INPUT] configuration >>>>>
2303 11:40:58.544237 [RX_INPUT] configuration <<<<<
2304 11:40:58.548039 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2305 11:40:58.554174 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2306 11:40:58.560668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2307 11:40:58.567120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2308 11:40:58.574399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2309 11:40:58.580859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2310 11:40:58.584143 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2311 11:40:58.587290 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2312 11:40:58.590979 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2313 11:40:58.594104 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2314 11:40:58.600550 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2315 11:40:58.603890 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2316 11:40:58.607225 ===================================
2317 11:40:58.610603 LPDDR4 DRAM CONFIGURATION
2318 11:40:58.614076 ===================================
2319 11:40:58.614159 EX_ROW_EN[0] = 0x0
2320 11:40:58.617463 EX_ROW_EN[1] = 0x0
2321 11:40:58.617552 LP4Y_EN = 0x0
2322 11:40:58.620951 WORK_FSP = 0x0
2323 11:40:58.621040 WL = 0x4
2324 11:40:58.624452 RL = 0x4
2325 11:40:58.624541 BL = 0x2
2326 11:40:58.627311 RPST = 0x0
2327 11:40:58.627395 RD_PRE = 0x0
2328 11:40:58.630601 WR_PRE = 0x1
2329 11:40:58.634013 WR_PST = 0x0
2330 11:40:58.634086 DBI_WR = 0x0
2331 11:40:58.637565 DBI_RD = 0x0
2332 11:40:58.637647 OTF = 0x1
2333 11:40:58.640848 ===================================
2334 11:40:58.643921 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2335 11:40:58.647282 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2336 11:40:58.654575 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2337 11:40:58.657753 ===================================
2338 11:40:58.660525 LPDDR4 DRAM CONFIGURATION
2339 11:40:58.663918 ===================================
2340 11:40:58.663991 EX_ROW_EN[0] = 0x10
2341 11:40:58.667596 EX_ROW_EN[1] = 0x0
2342 11:40:58.667668 LP4Y_EN = 0x0
2343 11:40:58.670802 WORK_FSP = 0x0
2344 11:40:58.670879 WL = 0x4
2345 11:40:58.673788 RL = 0x4
2346 11:40:58.673869 BL = 0x2
2347 11:40:58.677874 RPST = 0x0
2348 11:40:58.677963 RD_PRE = 0x0
2349 11:40:58.681473 WR_PRE = 0x1
2350 11:40:58.681547 WR_PST = 0x0
2351 11:40:58.683968 DBI_WR = 0x0
2352 11:40:58.684068 DBI_RD = 0x0
2353 11:40:58.687343 OTF = 0x1
2354 11:40:58.690869 ===================================
2355 11:40:58.697745 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2356 11:40:58.697843 ==
2357 11:40:58.700643 Dram Type= 6, Freq= 0, CH_0, rank 0
2358 11:40:58.704030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 11:40:58.704103 ==
2360 11:40:58.707294 [Duty_Offset_Calibration]
2361 11:40:58.707405 B0:2 B1:-1 CA:1
2362 11:40:58.707465
2363 11:40:58.710753 [DutyScan_Calibration_Flow] k_type=0
2364 11:40:58.720439
2365 11:40:58.720524 ==CLK 0==
2366 11:40:58.723944 Final CLK duty delay cell = -4
2367 11:40:58.727288 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2368 11:40:58.730745 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2369 11:40:58.734003 [-4] AVG Duty = 4953%(X100)
2370 11:40:58.734086
2371 11:40:58.737435 CH0 CLK Duty spec in!! Max-Min= 156%
2372 11:40:58.740569 [DutyScan_Calibration_Flow] ====Done====
2373 11:40:58.740651
2374 11:40:58.744018 [DutyScan_Calibration_Flow] k_type=1
2375 11:40:58.759853
2376 11:40:58.759948 ==DQS 0 ==
2377 11:40:58.762471 Final DQS duty delay cell = 0
2378 11:40:58.765953 [0] MAX Duty = 5125%(X100), DQS PI = 48
2379 11:40:58.769461 [0] MIN Duty = 5000%(X100), DQS PI = 14
2380 11:40:58.769569 [0] AVG Duty = 5062%(X100)
2381 11:40:58.772580
2382 11:40:58.772661 ==DQS 1 ==
2383 11:40:58.775803 Final DQS duty delay cell = -4
2384 11:40:58.779483 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2385 11:40:58.782658 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2386 11:40:58.785892 [-4] AVG Duty = 5062%(X100)
2387 11:40:58.785973
2388 11:40:58.789271 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2389 11:40:58.789354
2390 11:40:58.792521 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2391 11:40:58.796248 [DutyScan_Calibration_Flow] ====Done====
2392 11:40:58.796329
2393 11:40:58.798981 [DutyScan_Calibration_Flow] k_type=3
2394 11:40:58.816301
2395 11:40:58.816396 ==DQM 0 ==
2396 11:40:58.819720 Final DQM duty delay cell = 0
2397 11:40:58.823018 [0] MAX Duty = 5031%(X100), DQS PI = 54
2398 11:40:58.825908 [0] MIN Duty = 4907%(X100), DQS PI = 2
2399 11:40:58.825991 [0] AVG Duty = 4969%(X100)
2400 11:40:58.829368
2401 11:40:58.829438 ==DQM 1 ==
2402 11:40:58.832904 Final DQM duty delay cell = 0
2403 11:40:58.835862 [0] MAX Duty = 5156%(X100), DQS PI = 62
2404 11:40:58.839304 [0] MIN Duty = 5000%(X100), DQS PI = 10
2405 11:40:58.842566 [0] AVG Duty = 5078%(X100)
2406 11:40:58.842649
2407 11:40:58.845925 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2408 11:40:58.846008
2409 11:40:58.849450 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2410 11:40:58.852421 [DutyScan_Calibration_Flow] ====Done====
2411 11:40:58.852503
2412 11:40:58.855692 [DutyScan_Calibration_Flow] k_type=2
2413 11:40:58.871693
2414 11:40:58.871779 ==DQ 0 ==
2415 11:40:58.875632 Final DQ duty delay cell = -4
2416 11:40:58.878712 [-4] MAX Duty = 5031%(X100), DQS PI = 0
2417 11:40:58.881930 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2418 11:40:58.885183 [-4] AVG Duty = 4969%(X100)
2419 11:40:58.885267
2420 11:40:58.885331 ==DQ 1 ==
2421 11:40:58.888357 Final DQ duty delay cell = 0
2422 11:40:58.891891 [0] MAX Duty = 5031%(X100), DQS PI = 18
2423 11:40:58.895072 [0] MIN Duty = 4907%(X100), DQS PI = 46
2424 11:40:58.895155 [0] AVG Duty = 4969%(X100)
2425 11:40:58.898457
2426 11:40:58.901765 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2427 11:40:58.901874
2428 11:40:58.905224 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2429 11:40:58.908740 [DutyScan_Calibration_Flow] ====Done====
2430 11:40:58.908853 ==
2431 11:40:58.911958 Dram Type= 6, Freq= 0, CH_1, rank 0
2432 11:40:58.915331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2433 11:40:58.915443 ==
2434 11:40:58.918574 [Duty_Offset_Calibration]
2435 11:40:58.918712 B0:1 B1:1 CA:2
2436 11:40:58.918815
2437 11:40:58.922284 [DutyScan_Calibration_Flow] k_type=0
2438 11:40:58.931780
2439 11:40:58.931888 ==CLK 0==
2440 11:40:58.935201 Final CLK duty delay cell = 0
2441 11:40:58.938501 [0] MAX Duty = 5156%(X100), DQS PI = 24
2442 11:40:58.941974 [0] MIN Duty = 4969%(X100), DQS PI = 40
2443 11:40:58.942076 [0] AVG Duty = 5062%(X100)
2444 11:40:58.945437
2445 11:40:58.948660 CH1 CLK Duty spec in!! Max-Min= 187%
2446 11:40:58.952004 [DutyScan_Calibration_Flow] ====Done====
2447 11:40:58.952103
2448 11:40:58.955508 [DutyScan_Calibration_Flow] k_type=1
2449 11:40:58.971522
2450 11:40:58.971611 ==DQS 0 ==
2451 11:40:58.974842 Final DQS duty delay cell = 0
2452 11:40:58.977733 [0] MAX Duty = 5031%(X100), DQS PI = 18
2453 11:40:58.981061 [0] MIN Duty = 4844%(X100), DQS PI = 50
2454 11:40:58.984826 [0] AVG Duty = 4937%(X100)
2455 11:40:58.984939
2456 11:40:58.985030 ==DQS 1 ==
2457 11:40:58.988015 Final DQS duty delay cell = 0
2458 11:40:58.991095 [0] MAX Duty = 5062%(X100), DQS PI = 36
2459 11:40:58.994409 [0] MIN Duty = 4907%(X100), DQS PI = 32
2460 11:40:58.998228 [0] AVG Duty = 4984%(X100)
2461 11:40:58.998331
2462 11:40:59.001270 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2463 11:40:59.001373
2464 11:40:59.004436 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2465 11:40:59.008166 [DutyScan_Calibration_Flow] ====Done====
2466 11:40:59.008268
2467 11:40:59.011129 [DutyScan_Calibration_Flow] k_type=3
2468 11:40:59.028217
2469 11:40:59.028310 ==DQM 0 ==
2470 11:40:59.031114 Final DQM duty delay cell = 0
2471 11:40:59.034723 [0] MAX Duty = 5093%(X100), DQS PI = 16
2472 11:40:59.038041 [0] MIN Duty = 4907%(X100), DQS PI = 48
2473 11:40:59.041185 [0] AVG Duty = 5000%(X100)
2474 11:40:59.041281
2475 11:40:59.041357 ==DQM 1 ==
2476 11:40:59.044766 Final DQM duty delay cell = 0
2477 11:40:59.048177 [0] MAX Duty = 5125%(X100), DQS PI = 62
2478 11:40:59.051025 [0] MIN Duty = 4938%(X100), DQS PI = 22
2479 11:40:59.051128 [0] AVG Duty = 5031%(X100)
2480 11:40:59.054349
2481 11:40:59.057793 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2482 11:40:59.057893
2483 11:40:59.061233 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2484 11:40:59.064502 [DutyScan_Calibration_Flow] ====Done====
2485 11:40:59.064604
2486 11:40:59.067836 [DutyScan_Calibration_Flow] k_type=2
2487 11:40:59.084514
2488 11:40:59.084746 ==DQ 0 ==
2489 11:40:59.087912 Final DQ duty delay cell = 0
2490 11:40:59.091057 [0] MAX Duty = 5156%(X100), DQS PI = 18
2491 11:40:59.094703 [0] MIN Duty = 4969%(X100), DQS PI = 30
2492 11:40:59.094824 [0] AVG Duty = 5062%(X100)
2493 11:40:59.094927
2494 11:40:59.097907 ==DQ 1 ==
2495 11:40:59.101268 Final DQ duty delay cell = 0
2496 11:40:59.104447 [0] MAX Duty = 5093%(X100), DQS PI = 10
2497 11:40:59.108324 [0] MIN Duty = 5031%(X100), DQS PI = 2
2498 11:40:59.108432 [0] AVG Duty = 5062%(X100)
2499 11:40:59.108524
2500 11:40:59.111035 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2501 11:40:59.111154
2502 11:40:59.115906 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2503 11:40:59.121917 [DutyScan_Calibration_Flow] ====Done====
2504 11:40:59.124467 nWR fixed to 30
2505 11:40:59.124590 [ModeRegInit_LP4] CH0 RK0
2506 11:40:59.127973 [ModeRegInit_LP4] CH0 RK1
2507 11:40:59.131443 [ModeRegInit_LP4] CH1 RK0
2508 11:40:59.131525 [ModeRegInit_LP4] CH1 RK1
2509 11:40:59.134551 match AC timing 7
2510 11:40:59.138075 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2511 11:40:59.141248 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2512 11:40:59.148179 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2513 11:40:59.151079 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2514 11:40:59.158216 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2515 11:40:59.158304 ==
2516 11:40:59.161181 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 11:40:59.164559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 11:40:59.164643 ==
2519 11:40:59.171260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2520 11:40:59.174779 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2521 11:40:59.184301 [CA 0] Center 40 (10~71) winsize 62
2522 11:40:59.187864 [CA 1] Center 39 (9~70) winsize 62
2523 11:40:59.191215 [CA 2] Center 36 (6~67) winsize 62
2524 11:40:59.194212 [CA 3] Center 36 (5~67) winsize 63
2525 11:40:59.197601 [CA 4] Center 35 (5~65) winsize 61
2526 11:40:59.201479 [CA 5] Center 34 (4~64) winsize 61
2527 11:40:59.201588
2528 11:40:59.204653 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2529 11:40:59.204764
2530 11:40:59.208069 [CATrainingPosCal] consider 1 rank data
2531 11:40:59.211328 u2DelayCellTimex100 = 270/100 ps
2532 11:40:59.214761 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2533 11:40:59.220921 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2534 11:40:59.224686 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2535 11:40:59.227555 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2536 11:40:59.231153 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2537 11:40:59.234580 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2538 11:40:59.234665
2539 11:40:59.237962 CA PerBit enable=1, Macro0, CA PI delay=34
2540 11:40:59.238047
2541 11:40:59.240844 [CBTSetCACLKResult] CA Dly = 34
2542 11:40:59.240931 CS Dly: 7 (0~38)
2543 11:40:59.244686 ==
2544 11:40:59.244771 Dram Type= 6, Freq= 0, CH_0, rank 1
2545 11:40:59.250903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 11:40:59.250988 ==
2547 11:40:59.254475 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2548 11:40:59.261200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2549 11:40:59.270441 [CA 0] Center 39 (9~70) winsize 62
2550 11:40:59.273861 [CA 1] Center 40 (10~70) winsize 61
2551 11:40:59.276762 [CA 2] Center 36 (6~67) winsize 62
2552 11:40:59.280283 [CA 3] Center 36 (5~67) winsize 63
2553 11:40:59.283725 [CA 4] Center 34 (4~65) winsize 62
2554 11:40:59.287061 [CA 5] Center 34 (4~64) winsize 61
2555 11:40:59.287148
2556 11:40:59.290451 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2557 11:40:59.290535
2558 11:40:59.293446 [CATrainingPosCal] consider 2 rank data
2559 11:40:59.296939 u2DelayCellTimex100 = 270/100 ps
2560 11:40:59.300322 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2561 11:40:59.306994 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2562 11:40:59.310179 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2563 11:40:59.313966 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2564 11:40:59.316764 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2565 11:40:59.320312 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2566 11:40:59.320401
2567 11:40:59.323602 CA PerBit enable=1, Macro0, CA PI delay=34
2568 11:40:59.323687
2569 11:40:59.327008 [CBTSetCACLKResult] CA Dly = 34
2570 11:40:59.327093 CS Dly: 8 (0~41)
2571 11:40:59.330395
2572 11:40:59.333432 ----->DramcWriteLeveling(PI) begin...
2573 11:40:59.333518 ==
2574 11:40:59.337074 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 11:40:59.340519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 11:40:59.340613 ==
2577 11:40:59.343583 Write leveling (Byte 0): 30 => 30
2578 11:40:59.346876 Write leveling (Byte 1): 30 => 30
2579 11:40:59.350268 DramcWriteLeveling(PI) end<-----
2580 11:40:59.350361
2581 11:40:59.350426 ==
2582 11:40:59.353879 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 11:40:59.356773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 11:40:59.356887 ==
2585 11:40:59.360096 [Gating] SW mode calibration
2586 11:40:59.366930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2587 11:40:59.373493 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2588 11:40:59.376902 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 11:40:59.380449 0 15 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
2590 11:40:59.383520 0 15 8 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2591 11:40:59.390151 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 11:40:59.393682 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 11:40:59.397030 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 11:40:59.403525 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 11:40:59.407299 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 11:40:59.410418 1 0 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
2597 11:40:59.416820 1 0 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2598 11:40:59.420035 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 11:40:59.423455 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 11:40:59.430239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 11:40:59.433983 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 11:40:59.437155 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 11:40:59.444020 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 11:40:59.447211 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2605 11:40:59.450251 1 1 4 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
2606 11:40:59.456698 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:40:59.460139 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 11:40:59.463701 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 11:40:59.470809 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 11:40:59.473904 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 11:40:59.477218 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 11:40:59.483622 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2613 11:40:59.487057 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2614 11:40:59.489907 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:40:59.493349 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:40:59.500174 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:40:59.503618 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:40:59.507124 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:40:59.513606 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:40:59.516640 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:40:59.519978 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:40:59.526796 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:40:59.530252 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:40:59.533435 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:40:59.540321 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:40:59.543272 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:40:59.547015 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:40:59.553140 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2629 11:40:59.557007 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2630 11:40:59.559813 Total UI for P1: 0, mck2ui 16
2631 11:40:59.563506 best dqsien dly found for B0: ( 1, 4, 0)
2632 11:40:59.566834 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 11:40:59.569797 Total UI for P1: 0, mck2ui 16
2634 11:40:59.573607 best dqsien dly found for B1: ( 1, 4, 4)
2635 11:40:59.576437 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2636 11:40:59.579906 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2637 11:40:59.579991
2638 11:40:59.583760 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2639 11:40:59.590217 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2640 11:40:59.590300 [Gating] SW calibration Done
2641 11:40:59.590365 ==
2642 11:40:59.593146 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 11:40:59.600237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 11:40:59.600322 ==
2645 11:40:59.600387 RX Vref Scan: 0
2646 11:40:59.600447
2647 11:40:59.603794 RX Vref 0 -> 0, step: 1
2648 11:40:59.603876
2649 11:40:59.606760 RX Delay -40 -> 252, step: 8
2650 11:40:59.610207 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2651 11:40:59.613428 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2652 11:40:59.616904 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2653 11:40:59.620176 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2654 11:40:59.626833 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2655 11:40:59.630366 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2656 11:40:59.633609 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2657 11:40:59.636525 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2658 11:40:59.639848 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2659 11:40:59.646692 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2660 11:40:59.650046 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2661 11:40:59.653556 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2662 11:40:59.656732 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2663 11:40:59.659864 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2664 11:40:59.666447 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2665 11:40:59.670065 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2666 11:40:59.670149 ==
2667 11:40:59.673585 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 11:40:59.677100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 11:40:59.677184 ==
2670 11:40:59.679870 DQS Delay:
2671 11:40:59.679954 DQS0 = 0, DQS1 = 0
2672 11:40:59.680019 DQM Delay:
2673 11:40:59.683359 DQM0 = 116, DQM1 = 107
2674 11:40:59.683481 DQ Delay:
2675 11:40:59.686374 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2676 11:40:59.689871 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2677 11:40:59.693499 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2678 11:40:59.699882 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2679 11:40:59.699967
2680 11:40:59.700032
2681 11:40:59.700090 ==
2682 11:40:59.703144 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:40:59.706585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:40:59.706673 ==
2685 11:40:59.706737
2686 11:40:59.706796
2687 11:40:59.710039 TX Vref Scan disable
2688 11:40:59.710121 == TX Byte 0 ==
2689 11:40:59.716973 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2690 11:40:59.719870 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2691 11:40:59.719956 == TX Byte 1 ==
2692 11:40:59.726654 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2693 11:40:59.729957 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2694 11:40:59.730040 ==
2695 11:40:59.733426 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 11:40:59.736381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 11:40:59.736461 ==
2698 11:40:59.749221 TX Vref=22, minBit 1, minWin=25, winSum=418
2699 11:40:59.752547 TX Vref=24, minBit 5, minWin=25, winSum=421
2700 11:40:59.755734 TX Vref=26, minBit 0, minWin=26, winSum=428
2701 11:40:59.758650 TX Vref=28, minBit 1, minWin=25, winSum=434
2702 11:40:59.762374 TX Vref=30, minBit 0, minWin=26, winSum=433
2703 11:40:59.765692 TX Vref=32, minBit 0, minWin=26, winSum=431
2704 11:40:59.772099 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 30
2705 11:40:59.772176
2706 11:40:59.775710 Final TX Range 1 Vref 30
2707 11:40:59.775780
2708 11:40:59.775839 ==
2709 11:40:59.779139 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 11:40:59.782177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 11:40:59.782278 ==
2712 11:40:59.785698
2713 11:40:59.785794
2714 11:40:59.785881 TX Vref Scan disable
2715 11:40:59.789138 == TX Byte 0 ==
2716 11:40:59.792172 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2717 11:40:59.795559 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2718 11:40:59.799104 == TX Byte 1 ==
2719 11:40:59.802044 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2720 11:40:59.805469 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2721 11:40:59.805540
2722 11:40:59.808836 [DATLAT]
2723 11:40:59.808906 Freq=1200, CH0 RK0
2724 11:40:59.808966
2725 11:40:59.812377 DATLAT Default: 0xd
2726 11:40:59.812450 0, 0xFFFF, sum = 0
2727 11:40:59.815746 1, 0xFFFF, sum = 0
2728 11:40:59.815843 2, 0xFFFF, sum = 0
2729 11:40:59.818994 3, 0xFFFF, sum = 0
2730 11:40:59.819089 4, 0xFFFF, sum = 0
2731 11:40:59.821953 5, 0xFFFF, sum = 0
2732 11:40:59.822024 6, 0xFFFF, sum = 0
2733 11:40:59.825382 7, 0xFFFF, sum = 0
2734 11:40:59.828716 8, 0xFFFF, sum = 0
2735 11:40:59.828786 9, 0xFFFF, sum = 0
2736 11:40:59.832117 10, 0xFFFF, sum = 0
2737 11:40:59.832192 11, 0xFFFF, sum = 0
2738 11:40:59.835264 12, 0x0, sum = 1
2739 11:40:59.835369 13, 0x0, sum = 2
2740 11:40:59.838548 14, 0x0, sum = 3
2741 11:40:59.838644 15, 0x0, sum = 4
2742 11:40:59.838733 best_step = 13
2743 11:40:59.838816
2744 11:40:59.842068 ==
2745 11:40:59.845732 Dram Type= 6, Freq= 0, CH_0, rank 0
2746 11:40:59.848628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2747 11:40:59.848699 ==
2748 11:40:59.848756 RX Vref Scan: 1
2749 11:40:59.848816
2750 11:40:59.852155 Set Vref Range= 32 -> 127
2751 11:40:59.852226
2752 11:40:59.855644 RX Vref 32 -> 127, step: 1
2753 11:40:59.855720
2754 11:40:59.858813 RX Delay -21 -> 252, step: 4
2755 11:40:59.858884
2756 11:40:59.861873 Set Vref, RX VrefLevel [Byte0]: 32
2757 11:40:59.865189 [Byte1]: 32
2758 11:40:59.865258
2759 11:40:59.868719 Set Vref, RX VrefLevel [Byte0]: 33
2760 11:40:59.872479 [Byte1]: 33
2761 11:40:59.872552
2762 11:40:59.875255 Set Vref, RX VrefLevel [Byte0]: 34
2763 11:40:59.878560 [Byte1]: 34
2764 11:40:59.883065
2765 11:40:59.883171 Set Vref, RX VrefLevel [Byte0]: 35
2766 11:40:59.886595 [Byte1]: 35
2767 11:40:59.891014
2768 11:40:59.891114 Set Vref, RX VrefLevel [Byte0]: 36
2769 11:40:59.894704 [Byte1]: 36
2770 11:40:59.898924
2771 11:40:59.898994 Set Vref, RX VrefLevel [Byte0]: 37
2772 11:40:59.901955 [Byte1]: 37
2773 11:40:59.907096
2774 11:40:59.907170 Set Vref, RX VrefLevel [Byte0]: 38
2775 11:40:59.909826 [Byte1]: 38
2776 11:40:59.915003
2777 11:40:59.915073 Set Vref, RX VrefLevel [Byte0]: 39
2778 11:40:59.918045 [Byte1]: 39
2779 11:40:59.922947
2780 11:40:59.923031 Set Vref, RX VrefLevel [Byte0]: 40
2781 11:40:59.926308 [Byte1]: 40
2782 11:40:59.930881
2783 11:40:59.930963 Set Vref, RX VrefLevel [Byte0]: 41
2784 11:40:59.933704 [Byte1]: 41
2785 11:40:59.938416
2786 11:40:59.938497 Set Vref, RX VrefLevel [Byte0]: 42
2787 11:40:59.941721 [Byte1]: 42
2788 11:40:59.946504
2789 11:40:59.946585 Set Vref, RX VrefLevel [Byte0]: 43
2790 11:40:59.949839 [Byte1]: 43
2791 11:40:59.954160
2792 11:40:59.954243 Set Vref, RX VrefLevel [Byte0]: 44
2793 11:40:59.958053 [Byte1]: 44
2794 11:40:59.962510
2795 11:40:59.962592 Set Vref, RX VrefLevel [Byte0]: 45
2796 11:40:59.965663 [Byte1]: 45
2797 11:40:59.970038
2798 11:40:59.970160 Set Vref, RX VrefLevel [Byte0]: 46
2799 11:40:59.973941 [Byte1]: 46
2800 11:40:59.978220
2801 11:40:59.978352 Set Vref, RX VrefLevel [Byte0]: 47
2802 11:40:59.981368 [Byte1]: 47
2803 11:40:59.986203
2804 11:40:59.986285 Set Vref, RX VrefLevel [Byte0]: 48
2805 11:40:59.989310 [Byte1]: 48
2806 11:40:59.994219
2807 11:40:59.994327 Set Vref, RX VrefLevel [Byte0]: 49
2808 11:40:59.997305 [Byte1]: 49
2809 11:41:00.001901
2810 11:41:00.001982 Set Vref, RX VrefLevel [Byte0]: 50
2811 11:41:00.005272 [Byte1]: 50
2812 11:41:00.010159
2813 11:41:00.010240 Set Vref, RX VrefLevel [Byte0]: 51
2814 11:41:00.013383 [Byte1]: 51
2815 11:41:00.017857
2816 11:41:00.017938 Set Vref, RX VrefLevel [Byte0]: 52
2817 11:41:00.020849 [Byte1]: 52
2818 11:41:00.026000
2819 11:41:00.026082 Set Vref, RX VrefLevel [Byte0]: 53
2820 11:41:00.028846 [Byte1]: 53
2821 11:41:00.033542
2822 11:41:00.033624 Set Vref, RX VrefLevel [Byte0]: 54
2823 11:41:00.036922 [Byte1]: 54
2824 11:41:00.041437
2825 11:41:00.041518 Set Vref, RX VrefLevel [Byte0]: 55
2826 11:41:00.045118 [Byte1]: 55
2827 11:41:00.049262
2828 11:41:00.049345 Set Vref, RX VrefLevel [Byte0]: 56
2829 11:41:00.053018 [Byte1]: 56
2830 11:41:00.057569
2831 11:41:00.057651 Set Vref, RX VrefLevel [Byte0]: 57
2832 11:41:00.061231 [Byte1]: 57
2833 11:41:00.065517
2834 11:41:00.065600 Set Vref, RX VrefLevel [Byte0]: 58
2835 11:41:00.068752 [Byte1]: 58
2836 11:41:00.073023
2837 11:41:00.073107 Set Vref, RX VrefLevel [Byte0]: 59
2838 11:41:00.076392 [Byte1]: 59
2839 11:41:00.081428
2840 11:41:00.081519 Set Vref, RX VrefLevel [Byte0]: 60
2841 11:41:00.084565 [Byte1]: 60
2842 11:41:00.088933
2843 11:41:00.089017 Set Vref, RX VrefLevel [Byte0]: 61
2844 11:41:00.092669 [Byte1]: 61
2845 11:41:00.097193
2846 11:41:00.097279 Set Vref, RX VrefLevel [Byte0]: 62
2847 11:41:00.100492 [Byte1]: 62
2848 11:41:00.105007
2849 11:41:00.105094 Set Vref, RX VrefLevel [Byte0]: 63
2850 11:41:00.108497 [Byte1]: 63
2851 11:41:00.112670
2852 11:41:00.112753 Set Vref, RX VrefLevel [Byte0]: 64
2853 11:41:00.116007 [Byte1]: 64
2854 11:41:00.120958
2855 11:41:00.121042 Set Vref, RX VrefLevel [Byte0]: 65
2856 11:41:00.124112 [Byte1]: 65
2857 11:41:00.128601
2858 11:41:00.128683 Set Vref, RX VrefLevel [Byte0]: 66
2859 11:41:00.132032 [Byte1]: 66
2860 11:41:00.136712
2861 11:41:00.136795 Set Vref, RX VrefLevel [Byte0]: 67
2862 11:41:00.140146 [Byte1]: 67
2863 11:41:00.144719
2864 11:41:00.144801 Set Vref, RX VrefLevel [Byte0]: 68
2865 11:41:00.147930 [Byte1]: 68
2866 11:41:00.152664
2867 11:41:00.152747 Final RX Vref Byte 0 = 54 to rank0
2868 11:41:00.155623 Final RX Vref Byte 1 = 51 to rank0
2869 11:41:00.159049 Final RX Vref Byte 0 = 54 to rank1
2870 11:41:00.162478 Final RX Vref Byte 1 = 51 to rank1==
2871 11:41:00.165767 Dram Type= 6, Freq= 0, CH_0, rank 0
2872 11:41:00.172505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 11:41:00.172593 ==
2874 11:41:00.172659 DQS Delay:
2875 11:41:00.172717 DQS0 = 0, DQS1 = 0
2876 11:41:00.175868 DQM Delay:
2877 11:41:00.175950 DQM0 = 114, DQM1 = 104
2878 11:41:00.179030 DQ Delay:
2879 11:41:00.182498 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2880 11:41:00.185727 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2881 11:41:00.189377 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2882 11:41:00.192381 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2883 11:41:00.192467
2884 11:41:00.192530
2885 11:41:00.198933 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2886 11:41:00.202769 CH0 RK0: MR19=303, MR18=FDEC
2887 11:41:00.208993 CH0_RK0: MR19=0x303, MR18=0xFDEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2888 11:41:00.209087
2889 11:41:00.212462 ----->DramcWriteLeveling(PI) begin...
2890 11:41:00.212547 ==
2891 11:41:00.215958 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 11:41:00.219123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 11:41:00.222428 ==
2894 11:41:00.222512 Write leveling (Byte 0): 33 => 33
2895 11:41:00.225780 Write leveling (Byte 1): 30 => 30
2896 11:41:00.228908 DramcWriteLeveling(PI) end<-----
2897 11:41:00.228992
2898 11:41:00.229055 ==
2899 11:41:00.232302 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 11:41:00.238888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 11:41:00.238974 ==
2902 11:41:00.239038 [Gating] SW mode calibration
2903 11:41:00.249063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2904 11:41:00.252376 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2905 11:41:00.255806 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2906 11:41:00.262678 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2907 11:41:00.266147 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:41:00.269547 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 11:41:00.275909 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 11:41:00.279116 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 11:41:00.282935 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2912 11:41:00.289379 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
2913 11:41:00.292464 1 0 0 | B1->B0 | 2e2e 2d2d | 0 0 | (0 1) (0 0)
2914 11:41:00.296068 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:41:00.302412 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:41:00.305866 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:41:00.309597 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 11:41:00.315839 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 11:41:00.319384 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
2920 11:41:00.322330 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2921 11:41:00.325803 1 1 0 | B1->B0 | 3434 4242 | 0 0 | (1 1) (0 0)
2922 11:41:00.332744 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2923 11:41:00.336106 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:41:00.339136 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 11:41:00.346092 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 11:41:00.349476 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 11:41:00.352549 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 11:41:00.359296 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2929 11:41:00.362776 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2930 11:41:00.366193 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2931 11:41:00.372617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:41:00.376161 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:41:00.379526 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:41:00.386155 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:41:00.389737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:41:00.393007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:41:00.399387 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:41:00.402693 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:41:00.406339 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:41:00.409548 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:41:00.415989 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 11:41:00.419311 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 11:41:00.422789 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2944 11:41:00.429768 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2945 11:41:00.433439 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2946 11:41:00.436542 Total UI for P1: 0, mck2ui 16
2947 11:41:00.439362 best dqsien dly found for B0: ( 1, 3, 26)
2948 11:41:00.442914 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 11:41:00.446361 Total UI for P1: 0, mck2ui 16
2950 11:41:00.449266 best dqsien dly found for B1: ( 1, 4, 0)
2951 11:41:00.452721 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2952 11:41:00.456501 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2953 11:41:00.456584
2954 11:41:00.459727 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2955 11:41:00.466589 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2956 11:41:00.466678 [Gating] SW calibration Done
2957 11:41:00.466745 ==
2958 11:41:00.469453 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 11:41:00.476264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 11:41:00.476349 ==
2961 11:41:00.476413 RX Vref Scan: 0
2962 11:41:00.476473
2963 11:41:00.479902 RX Vref 0 -> 0, step: 1
2964 11:41:00.480006
2965 11:41:00.483200 RX Delay -40 -> 252, step: 8
2966 11:41:00.486131 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2967 11:41:00.489363 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2968 11:41:00.493236 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2969 11:41:00.499266 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2970 11:41:00.502841 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2971 11:41:00.506588 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2972 11:41:00.509753 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2973 11:41:00.512839 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2974 11:41:00.516160 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2975 11:41:00.522973 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2976 11:41:00.526182 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2977 11:41:00.529808 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2978 11:41:00.532847 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2979 11:41:00.535892 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2980 11:41:00.542762 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2981 11:41:00.546451 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2982 11:41:00.546552 ==
2983 11:41:00.549800 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 11:41:00.552640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 11:41:00.552715 ==
2986 11:41:00.556125 DQS Delay:
2987 11:41:00.556216 DQS0 = 0, DQS1 = 0
2988 11:41:00.556302 DQM Delay:
2989 11:41:00.559317 DQM0 = 116, DQM1 = 105
2990 11:41:00.559443 DQ Delay:
2991 11:41:00.562717 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2992 11:41:00.566071 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2993 11:41:00.569499 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2994 11:41:00.576113 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2995 11:41:00.576197
2996 11:41:00.576263
2997 11:41:00.576323 ==
2998 11:41:00.579609 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 11:41:00.583016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 11:41:00.583101 ==
3001 11:41:00.583166
3002 11:41:00.583226
3003 11:41:00.586419 TX Vref Scan disable
3004 11:41:00.586506 == TX Byte 0 ==
3005 11:41:00.593588 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3006 11:41:00.596419 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3007 11:41:00.596509 == TX Byte 1 ==
3008 11:41:00.602629 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3009 11:41:00.606460 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3010 11:41:00.606551 ==
3011 11:41:00.609760 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 11:41:00.612955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 11:41:00.613035 ==
3014 11:41:00.625700 TX Vref=22, minBit 4, minWin=25, winSum=422
3015 11:41:00.628834 TX Vref=24, minBit 0, minWin=26, winSum=424
3016 11:41:00.632429 TX Vref=26, minBit 2, minWin=26, winSum=430
3017 11:41:00.636312 TX Vref=28, minBit 3, minWin=26, winSum=434
3018 11:41:00.639193 TX Vref=30, minBit 3, minWin=26, winSum=437
3019 11:41:00.642814 TX Vref=32, minBit 2, minWin=26, winSum=434
3020 11:41:00.649220 [TxChooseVref] Worse bit 3, Min win 26, Win sum 437, Final Vref 30
3021 11:41:00.649316
3022 11:41:00.652232 Final TX Range 1 Vref 30
3023 11:41:00.652317
3024 11:41:00.652383 ==
3025 11:41:00.655763 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 11:41:00.659182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 11:41:00.659268 ==
3028 11:41:00.659332
3029 11:41:00.662428
3030 11:41:00.662510 TX Vref Scan disable
3031 11:41:00.665671 == TX Byte 0 ==
3032 11:41:00.668926 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3033 11:41:00.672382 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3034 11:41:00.676078 == TX Byte 1 ==
3035 11:41:00.679326 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3036 11:41:00.682632 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3037 11:41:00.682725
3038 11:41:00.685989 [DATLAT]
3039 11:41:00.686074 Freq=1200, CH0 RK1
3040 11:41:00.686140
3041 11:41:00.689261 DATLAT Default: 0xd
3042 11:41:00.689345 0, 0xFFFF, sum = 0
3043 11:41:00.692545 1, 0xFFFF, sum = 0
3044 11:41:00.692631 2, 0xFFFF, sum = 0
3045 11:41:00.695678 3, 0xFFFF, sum = 0
3046 11:41:00.695764 4, 0xFFFF, sum = 0
3047 11:41:00.699089 5, 0xFFFF, sum = 0
3048 11:41:00.699174 6, 0xFFFF, sum = 0
3049 11:41:00.702416 7, 0xFFFF, sum = 0
3050 11:41:00.702501 8, 0xFFFF, sum = 0
3051 11:41:00.705962 9, 0xFFFF, sum = 0
3052 11:41:00.708960 10, 0xFFFF, sum = 0
3053 11:41:00.709048 11, 0xFFFF, sum = 0
3054 11:41:00.712121 12, 0x0, sum = 1
3055 11:41:00.712210 13, 0x0, sum = 2
3056 11:41:00.712279 14, 0x0, sum = 3
3057 11:41:00.715735 15, 0x0, sum = 4
3058 11:41:00.715813 best_step = 13
3059 11:41:00.715874
3060 11:41:00.718735 ==
3061 11:41:00.718834 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 11:41:00.726062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 11:41:00.726159 ==
3064 11:41:00.726236 RX Vref Scan: 0
3065 11:41:00.726298
3066 11:41:00.728903 RX Vref 0 -> 0, step: 1
3067 11:41:00.728977
3068 11:41:00.732123 RX Delay -21 -> 252, step: 4
3069 11:41:00.735464 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3070 11:41:00.738752 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3071 11:41:00.745496 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3072 11:41:00.748755 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3073 11:41:00.751982 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3074 11:41:00.755527 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3075 11:41:00.759048 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3076 11:41:00.765622 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3077 11:41:00.769257 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3078 11:41:00.772711 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3079 11:41:00.775533 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3080 11:41:00.778659 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3081 11:41:00.785500 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3082 11:41:00.788919 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3083 11:41:00.792503 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3084 11:41:00.795362 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3085 11:41:00.795486 ==
3086 11:41:00.799138 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 11:41:00.805514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 11:41:00.805609 ==
3089 11:41:00.805676 DQS Delay:
3090 11:41:00.805737 DQS0 = 0, DQS1 = 0
3091 11:41:00.809019 DQM Delay:
3092 11:41:00.809134 DQM0 = 114, DQM1 = 104
3093 11:41:00.812293 DQ Delay:
3094 11:41:00.815505 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3095 11:41:00.819123 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3096 11:41:00.822169 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3097 11:41:00.825993 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3098 11:41:00.826083
3099 11:41:00.826149
3100 11:41:00.832103 [DQSOSCAuto] RK1, (LSB)MR18= 0xfff1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3101 11:41:00.835587 CH0 RK1: MR19=303, MR18=FFF1
3102 11:41:00.842050 CH0_RK1: MR19=0x303, MR18=0xFFF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3103 11:41:00.845908 [RxdqsGatingPostProcess] freq 1200
3104 11:41:00.852317 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3105 11:41:00.855698 best DQS0 dly(2T, 0.5T) = (0, 12)
3106 11:41:00.855791 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 11:41:00.859194 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3108 11:41:00.862677 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 11:41:00.865655 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 11:41:00.869088 best DQS1 dly(2T, 0.5T) = (0, 12)
3111 11:41:00.872330 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 11:41:00.875562 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3113 11:41:00.878901 Pre-setting of DQS Precalculation
3114 11:41:00.885486 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3115 11:41:00.885602 ==
3116 11:41:00.888768 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 11:41:00.892371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 11:41:00.892459 ==
3119 11:41:00.895791 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 11:41:00.902110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 11:41:00.911447 [CA 0] Center 38 (9~68) winsize 60
3122 11:41:00.914795 [CA 1] Center 38 (8~68) winsize 61
3123 11:41:00.918319 [CA 2] Center 35 (5~65) winsize 61
3124 11:41:00.921278 [CA 3] Center 34 (4~65) winsize 62
3125 11:41:00.924964 [CA 4] Center 34 (4~65) winsize 62
3126 11:41:00.927858 [CA 5] Center 34 (4~64) winsize 61
3127 11:41:00.927950
3128 11:41:00.931711 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 11:41:00.931799
3130 11:41:00.935159 [CATrainingPosCal] consider 1 rank data
3131 11:41:00.937777 u2DelayCellTimex100 = 270/100 ps
3132 11:41:00.941759 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3133 11:41:00.945086 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3134 11:41:00.951208 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3135 11:41:00.954847 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3136 11:41:00.958325 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3137 11:41:00.961293 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3138 11:41:00.961377
3139 11:41:00.964918 CA PerBit enable=1, Macro0, CA PI delay=34
3140 11:41:00.965002
3141 11:41:00.967933 [CBTSetCACLKResult] CA Dly = 34
3142 11:41:00.968017 CS Dly: 6 (0~37)
3143 11:41:00.968116 ==
3144 11:41:00.971300 Dram Type= 6, Freq= 0, CH_1, rank 1
3145 11:41:00.978129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 11:41:00.978220 ==
3147 11:41:00.981628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3148 11:41:00.988223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3149 11:41:00.996987 [CA 0] Center 38 (8~68) winsize 61
3150 11:41:01.000542 [CA 1] Center 38 (9~68) winsize 60
3151 11:41:01.004095 [CA 2] Center 34 (4~65) winsize 62
3152 11:41:01.007262 [CA 3] Center 34 (4~65) winsize 62
3153 11:41:01.010190 [CA 4] Center 34 (4~65) winsize 62
3154 11:41:01.013736 [CA 5] Center 33 (3~63) winsize 61
3155 11:41:01.013816
3156 11:41:01.017258 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3157 11:41:01.017335
3158 11:41:01.020130 [CATrainingPosCal] consider 2 rank data
3159 11:41:01.023507 u2DelayCellTimex100 = 270/100 ps
3160 11:41:01.026788 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3161 11:41:01.030141 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3162 11:41:01.036719 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3163 11:41:01.040132 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3164 11:41:01.043806 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3165 11:41:01.046938 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3166 11:41:01.047014
3167 11:41:01.050690 CA PerBit enable=1, Macro0, CA PI delay=33
3168 11:41:01.050801
3169 11:41:01.053633 [CBTSetCACLKResult] CA Dly = 33
3170 11:41:01.053715 CS Dly: 7 (0~40)
3171 11:41:01.053778
3172 11:41:01.056969 ----->DramcWriteLeveling(PI) begin...
3173 11:41:01.060216 ==
3174 11:41:01.060295 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 11:41:01.067138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 11:41:01.067219 ==
3177 11:41:01.070653 Write leveling (Byte 0): 26 => 26
3178 11:41:01.074182 Write leveling (Byte 1): 30 => 30
3179 11:41:01.074340 DramcWriteLeveling(PI) end<-----
3180 11:41:01.077256
3181 11:41:01.077337 ==
3182 11:41:01.080562 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 11:41:01.084054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 11:41:01.084141 ==
3185 11:41:01.086829 [Gating] SW mode calibration
3186 11:41:01.093817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3187 11:41:01.097360 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3188 11:41:01.103978 0 15 0 | B1->B0 | 2929 2424 | 1 0 | (0 0) (0 0)
3189 11:41:01.107152 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3190 11:41:01.110666 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3191 11:41:01.116970 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:41:01.120440 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 11:41:01.123822 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3194 11:41:01.130626 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 11:41:01.133803 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3196 11:41:01.137304 1 0 0 | B1->B0 | 2323 2929 | 0 0 | (1 0) (0 1)
3197 11:41:01.143962 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:41:01.147126 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3199 11:41:01.150550 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 11:41:01.154209 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 11:41:01.161003 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3202 11:41:01.164383 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 11:41:01.167635 1 0 28 | B1->B0 | 3030 2727 | 0 0 | (1 1) (0 0)
3204 11:41:01.174422 1 1 0 | B1->B0 | 4141 3636 | 0 0 | (0 0) (0 0)
3205 11:41:01.177810 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:41:01.181120 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:41:01.187535 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:41:01.191033 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 11:41:01.194550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 11:41:01.200871 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 11:41:01.204387 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3212 11:41:01.207463 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3213 11:41:01.214465 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:41:01.217330 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:41:01.220909 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:41:01.224249 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:41:01.231179 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:41:01.234045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:41:01.237876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:41:01.244604 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:41:01.247687 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:41:01.251141 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:41:01.257503 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:41:01.260953 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 11:41:01.264077 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 11:41:01.270809 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 11:41:01.273951 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 11:41:01.277564 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:41:01.280649 Total UI for P1: 0, mck2ui 16
3230 11:41:01.284106 best dqsien dly found for B0: ( 1, 3, 28)
3231 11:41:01.287591 Total UI for P1: 0, mck2ui 16
3232 11:41:01.290724 best dqsien dly found for B1: ( 1, 3, 28)
3233 11:41:01.294086 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3234 11:41:01.297966 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3235 11:41:01.298050
3236 11:41:01.304044 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3237 11:41:01.307611 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3238 11:41:01.310377 [Gating] SW calibration Done
3239 11:41:01.310461 ==
3240 11:41:01.314085 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 11:41:01.317238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 11:41:01.317322 ==
3243 11:41:01.317386 RX Vref Scan: 0
3244 11:41:01.317447
3245 11:41:01.320746 RX Vref 0 -> 0, step: 1
3246 11:41:01.320864
3247 11:41:01.324196 RX Delay -40 -> 252, step: 8
3248 11:41:01.327149 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3249 11:41:01.330594 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3250 11:41:01.334046 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3251 11:41:01.340799 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3252 11:41:01.343973 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3253 11:41:01.347046 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3254 11:41:01.350594 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3255 11:41:01.353943 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3256 11:41:01.360719 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3257 11:41:01.364063 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3258 11:41:01.367506 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3259 11:41:01.370808 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3260 11:41:01.374024 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3261 11:41:01.380688 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3262 11:41:01.383868 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3263 11:41:01.387319 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3264 11:41:01.387468 ==
3265 11:41:01.390835 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 11:41:01.394210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 11:41:01.394286 ==
3268 11:41:01.397091 DQS Delay:
3269 11:41:01.397171 DQS0 = 0, DQS1 = 0
3270 11:41:01.400400 DQM Delay:
3271 11:41:01.400482 DQM0 = 116, DQM1 = 108
3272 11:41:01.403788 DQ Delay:
3273 11:41:01.407628 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3274 11:41:01.410455 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3275 11:41:01.413904 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3276 11:41:01.417338 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3277 11:41:01.417420
3278 11:41:01.417523
3279 11:41:01.417582 ==
3280 11:41:01.420788 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 11:41:01.423810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 11:41:01.423894 ==
3283 11:41:01.423958
3284 11:41:01.424018
3285 11:41:01.427151 TX Vref Scan disable
3286 11:41:01.430710 == TX Byte 0 ==
3287 11:41:01.433698 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3288 11:41:01.437087 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3289 11:41:01.440707 == TX Byte 1 ==
3290 11:41:01.444066 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3291 11:41:01.447526 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3292 11:41:01.447601 ==
3293 11:41:01.450741 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 11:41:01.454186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 11:41:01.454288 ==
3296 11:41:01.467369 TX Vref=22, minBit 1, minWin=24, winSum=409
3297 11:41:01.470463 TX Vref=24, minBit 10, minWin=25, winSum=415
3298 11:41:01.474214 TX Vref=26, minBit 13, minWin=25, winSum=417
3299 11:41:01.477151 TX Vref=28, minBit 0, minWin=26, winSum=426
3300 11:41:01.480901 TX Vref=30, minBit 13, minWin=25, winSum=427
3301 11:41:01.487258 TX Vref=32, minBit 1, minWin=26, winSum=427
3302 11:41:01.491027 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 32
3303 11:41:01.491135
3304 11:41:01.493929 Final TX Range 1 Vref 32
3305 11:41:01.494039
3306 11:41:01.494129 ==
3307 11:41:01.497105 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 11:41:01.500762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 11:41:01.500861 ==
3310 11:41:01.504230
3311 11:41:01.504335
3312 11:41:01.504425 TX Vref Scan disable
3313 11:41:01.507432 == TX Byte 0 ==
3314 11:41:01.510439 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3315 11:41:01.513822 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3316 11:41:01.517379 == TX Byte 1 ==
3317 11:41:01.520880 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3318 11:41:01.523959 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3319 11:41:01.524059
3320 11:41:01.527340 [DATLAT]
3321 11:41:01.527446 Freq=1200, CH1 RK0
3322 11:41:01.527506
3323 11:41:01.530788 DATLAT Default: 0xd
3324 11:41:01.530881 0, 0xFFFF, sum = 0
3325 11:41:01.534317 1, 0xFFFF, sum = 0
3326 11:41:01.534412 2, 0xFFFF, sum = 0
3327 11:41:01.537698 3, 0xFFFF, sum = 0
3328 11:41:01.537788 4, 0xFFFF, sum = 0
3329 11:41:01.540944 5, 0xFFFF, sum = 0
3330 11:41:01.541042 6, 0xFFFF, sum = 0
3331 11:41:01.544460 7, 0xFFFF, sum = 0
3332 11:41:01.544586 8, 0xFFFF, sum = 0
3333 11:41:01.547262 9, 0xFFFF, sum = 0
3334 11:41:01.551091 10, 0xFFFF, sum = 0
3335 11:41:01.551209 11, 0xFFFF, sum = 0
3336 11:41:01.554318 12, 0x0, sum = 1
3337 11:41:01.554439 13, 0x0, sum = 2
3338 11:41:01.554577 14, 0x0, sum = 3
3339 11:41:01.557405 15, 0x0, sum = 4
3340 11:41:01.557522 best_step = 13
3341 11:41:01.557655
3342 11:41:01.557776 ==
3343 11:41:01.560791 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 11:41:01.567352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 11:41:01.567469 ==
3346 11:41:01.567562 RX Vref Scan: 1
3347 11:41:01.567649
3348 11:41:01.571439 Set Vref Range= 32 -> 127
3349 11:41:01.571556
3350 11:41:01.574045 RX Vref 32 -> 127, step: 1
3351 11:41:01.574141
3352 11:41:01.577876 RX Delay -21 -> 252, step: 4
3353 11:41:01.577984
3354 11:41:01.580788 Set Vref, RX VrefLevel [Byte0]: 32
3355 11:41:01.584326 [Byte1]: 32
3356 11:41:01.584434
3357 11:41:01.587637 Set Vref, RX VrefLevel [Byte0]: 33
3358 11:41:01.590966 [Byte1]: 33
3359 11:41:01.591068
3360 11:41:01.594120 Set Vref, RX VrefLevel [Byte0]: 34
3361 11:41:01.597616 [Byte1]: 34
3362 11:41:01.602206
3363 11:41:01.602309 Set Vref, RX VrefLevel [Byte0]: 35
3364 11:41:01.604688 [Byte1]: 35
3365 11:41:01.609409
3366 11:41:01.609524 Set Vref, RX VrefLevel [Byte0]: 36
3367 11:41:01.612827 [Byte1]: 36
3368 11:41:01.618009
3369 11:41:01.618113 Set Vref, RX VrefLevel [Byte0]: 37
3370 11:41:01.620923 [Byte1]: 37
3371 11:41:01.625464
3372 11:41:01.625546 Set Vref, RX VrefLevel [Byte0]: 38
3373 11:41:01.628957 [Byte1]: 38
3374 11:41:01.633442
3375 11:41:01.633521 Set Vref, RX VrefLevel [Byte0]: 39
3376 11:41:01.636415 [Byte1]: 39
3377 11:41:01.641308
3378 11:41:01.641388 Set Vref, RX VrefLevel [Byte0]: 40
3379 11:41:01.644401 [Byte1]: 40
3380 11:41:01.649059
3381 11:41:01.649138 Set Vref, RX VrefLevel [Byte0]: 41
3382 11:41:01.652837 [Byte1]: 41
3383 11:41:01.656831
3384 11:41:01.656911 Set Vref, RX VrefLevel [Byte0]: 42
3385 11:41:01.660617 [Byte1]: 42
3386 11:41:01.665130
3387 11:41:01.665209 Set Vref, RX VrefLevel [Byte0]: 43
3388 11:41:01.668087 [Byte1]: 43
3389 11:41:01.672871
3390 11:41:01.672951 Set Vref, RX VrefLevel [Byte0]: 44
3391 11:41:01.676147 [Byte1]: 44
3392 11:41:01.681247
3393 11:41:01.681327 Set Vref, RX VrefLevel [Byte0]: 45
3394 11:41:01.684076 [Byte1]: 45
3395 11:41:01.688872
3396 11:41:01.688955 Set Vref, RX VrefLevel [Byte0]: 46
3397 11:41:01.692038 [Byte1]: 46
3398 11:41:01.696589
3399 11:41:01.696669 Set Vref, RX VrefLevel [Byte0]: 47
3400 11:41:01.700269 [Byte1]: 47
3401 11:41:01.704688
3402 11:41:01.704801 Set Vref, RX VrefLevel [Byte0]: 48
3403 11:41:01.707686 [Byte1]: 48
3404 11:41:01.712663
3405 11:41:01.712743 Set Vref, RX VrefLevel [Byte0]: 49
3406 11:41:01.715547 [Byte1]: 49
3407 11:41:01.720292
3408 11:41:01.720371 Set Vref, RX VrefLevel [Byte0]: 50
3409 11:41:01.723883 [Byte1]: 50
3410 11:41:01.728473
3411 11:41:01.728586 Set Vref, RX VrefLevel [Byte0]: 51
3412 11:41:01.731902 [Byte1]: 51
3413 11:41:01.736441
3414 11:41:01.736539 Set Vref, RX VrefLevel [Byte0]: 52
3415 11:41:01.739254 [Byte1]: 52
3416 11:41:01.743917
3417 11:41:01.743983 Set Vref, RX VrefLevel [Byte0]: 53
3418 11:41:01.747468 [Byte1]: 53
3419 11:41:01.751953
3420 11:41:01.752024 Set Vref, RX VrefLevel [Byte0]: 54
3421 11:41:01.755324 [Byte1]: 54
3422 11:41:01.759784
3423 11:41:01.759850 Set Vref, RX VrefLevel [Byte0]: 55
3424 11:41:01.763218 [Byte1]: 55
3425 11:41:01.767657
3426 11:41:01.767753 Set Vref, RX VrefLevel [Byte0]: 56
3427 11:41:01.771186 [Byte1]: 56
3428 11:41:01.775784
3429 11:41:01.775899 Set Vref, RX VrefLevel [Byte0]: 57
3430 11:41:01.778895 [Byte1]: 57
3431 11:41:01.783606
3432 11:41:01.783691 Set Vref, RX VrefLevel [Byte0]: 58
3433 11:41:01.786994 [Byte1]: 58
3434 11:41:01.791572
3435 11:41:01.791653 Set Vref, RX VrefLevel [Byte0]: 59
3436 11:41:01.794869 [Byte1]: 59
3437 11:41:01.799573
3438 11:41:01.799680 Set Vref, RX VrefLevel [Byte0]: 60
3439 11:41:01.802806 [Byte1]: 60
3440 11:41:01.807722
3441 11:41:01.807827 Set Vref, RX VrefLevel [Byte0]: 61
3442 11:41:01.810573 [Byte1]: 61
3443 11:41:01.815638
3444 11:41:01.815714 Set Vref, RX VrefLevel [Byte0]: 62
3445 11:41:01.818741 [Byte1]: 62
3446 11:41:01.823285
3447 11:41:01.823438 Set Vref, RX VrefLevel [Byte0]: 63
3448 11:41:01.826697 [Byte1]: 63
3449 11:41:01.831147
3450 11:41:01.831255 Set Vref, RX VrefLevel [Byte0]: 64
3451 11:41:01.834925 [Byte1]: 64
3452 11:41:01.839387
3453 11:41:01.839487 Set Vref, RX VrefLevel [Byte0]: 65
3454 11:41:01.842853 [Byte1]: 65
3455 11:41:01.847282
3456 11:41:01.847402 Set Vref, RX VrefLevel [Byte0]: 66
3457 11:41:01.850381 [Byte1]: 66
3458 11:41:01.855272
3459 11:41:01.855363 Set Vref, RX VrefLevel [Byte0]: 67
3460 11:41:01.858174 [Byte1]: 67
3461 11:41:01.863194
3462 11:41:01.863279 Set Vref, RX VrefLevel [Byte0]: 68
3463 11:41:01.865992 [Byte1]: 68
3464 11:41:01.870704
3465 11:41:01.874013 Set Vref, RX VrefLevel [Byte0]: 69
3466 11:41:01.874097 [Byte1]: 69
3467 11:41:01.878613
3468 11:41:01.878698 Set Vref, RX VrefLevel [Byte0]: 70
3469 11:41:01.882267 [Byte1]: 70
3470 11:41:01.886903
3471 11:41:01.886990 Final RX Vref Byte 0 = 58 to rank0
3472 11:41:01.890400 Final RX Vref Byte 1 = 53 to rank0
3473 11:41:01.893202 Final RX Vref Byte 0 = 58 to rank1
3474 11:41:01.897119 Final RX Vref Byte 1 = 53 to rank1==
3475 11:41:01.899881 Dram Type= 6, Freq= 0, CH_1, rank 0
3476 11:41:01.906788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 11:41:01.906873 ==
3478 11:41:01.906977 DQS Delay:
3479 11:41:01.907038 DQS0 = 0, DQS1 = 0
3480 11:41:01.909922 DQM Delay:
3481 11:41:01.910018 DQM0 = 116, DQM1 = 109
3482 11:41:01.913050 DQ Delay:
3483 11:41:01.916594 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3484 11:41:01.920549 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =114
3485 11:41:01.923187 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3486 11:41:01.927305 DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114
3487 11:41:01.927428
3488 11:41:01.927494
3489 11:41:01.933233 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3490 11:41:01.936789 CH1 RK0: MR19=303, MR18=FDE1
3491 11:41:01.943542 CH1_RK0: MR19=0x303, MR18=0xFDE1, DQSOSC=411, MR23=63, INC=38, DEC=25
3492 11:41:01.943628
3493 11:41:01.946850 ----->DramcWriteLeveling(PI) begin...
3494 11:41:01.946934 ==
3495 11:41:01.950167 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 11:41:01.953390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 11:41:01.956523 ==
3498 11:41:01.956607 Write leveling (Byte 0): 26 => 26
3499 11:41:01.960299 Write leveling (Byte 1): 28 => 28
3500 11:41:01.963252 DramcWriteLeveling(PI) end<-----
3501 11:41:01.963337
3502 11:41:01.963425 ==
3503 11:41:01.967035 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 11:41:01.973314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 11:41:01.973398 ==
3506 11:41:01.973463 [Gating] SW mode calibration
3507 11:41:01.983334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3508 11:41:01.986748 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3509 11:41:01.993079 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3510 11:41:01.996563 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 11:41:02.000070 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 11:41:02.002985 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3513 11:41:02.009860 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 11:41:02.012876 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3515 11:41:02.016867 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 1)
3516 11:41:02.023086 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3517 11:41:02.026533 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 11:41:02.030206 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 11:41:02.036492 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 11:41:02.039737 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 11:41:02.042823 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 11:41:02.049718 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3523 11:41:02.053065 1 0 24 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
3524 11:41:02.056571 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 11:41:02.063308 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3526 11:41:02.065935 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 11:41:02.069376 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 11:41:02.076035 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 11:41:02.079498 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 11:41:02.083087 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3531 11:41:02.089761 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3532 11:41:02.092628 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3533 11:41:02.096010 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:41:02.103025 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:41:02.106006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:41:02.109363 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:41:02.116311 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:41:02.119537 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:41:02.122569 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:41:02.129300 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:41:02.132796 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:41:02.136340 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:41:02.139396 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:41:02.145958 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:41:02.150019 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:41:02.152830 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:41:02.159533 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3548 11:41:02.162616 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3549 11:41:02.166079 Total UI for P1: 0, mck2ui 16
3550 11:41:02.168894 best dqsien dly found for B0: ( 1, 3, 24)
3551 11:41:02.172464 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 11:41:02.175734 Total UI for P1: 0, mck2ui 16
3553 11:41:02.179171 best dqsien dly found for B1: ( 1, 3, 28)
3554 11:41:02.182507 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3555 11:41:02.185762 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3556 11:41:02.185867
3557 11:41:02.192710 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3558 11:41:02.195944 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3559 11:41:02.199116 [Gating] SW calibration Done
3560 11:41:02.199215 ==
3561 11:41:02.202663 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 11:41:02.205489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 11:41:02.205596 ==
3564 11:41:02.205687 RX Vref Scan: 0
3565 11:41:02.205777
3566 11:41:02.209004 RX Vref 0 -> 0, step: 1
3567 11:41:02.209101
3568 11:41:02.212560 RX Delay -40 -> 252, step: 8
3569 11:41:02.216072 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3570 11:41:02.219124 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3571 11:41:02.226062 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3572 11:41:02.229075 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3573 11:41:02.232136 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3574 11:41:02.235645 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3575 11:41:02.238986 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3576 11:41:02.245786 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3577 11:41:02.248751 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3578 11:41:02.252362 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3579 11:41:02.255450 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3580 11:41:02.259039 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3581 11:41:02.265241 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3582 11:41:02.268641 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3583 11:41:02.271971 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3584 11:41:02.275457 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3585 11:41:02.275542 ==
3586 11:41:02.278846 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 11:41:02.285602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 11:41:02.285696 ==
3589 11:41:02.285763 DQS Delay:
3590 11:41:02.285824 DQS0 = 0, DQS1 = 0
3591 11:41:02.288932 DQM Delay:
3592 11:41:02.289016 DQM0 = 113, DQM1 = 111
3593 11:41:02.291840 DQ Delay:
3594 11:41:02.295237 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3595 11:41:02.298725 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3596 11:41:02.302279 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3597 11:41:02.305168 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3598 11:41:02.305295
3599 11:41:02.305360
3600 11:41:02.305451 ==
3601 11:41:02.308607 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 11:41:02.312282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 11:41:02.315034 ==
3604 11:41:02.315117
3605 11:41:02.315180
3606 11:41:02.315240 TX Vref Scan disable
3607 11:41:02.318520 == TX Byte 0 ==
3608 11:41:02.321869 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3609 11:41:02.325200 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3610 11:41:02.328803 == TX Byte 1 ==
3611 11:41:02.331841 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3612 11:41:02.335102 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3613 11:41:02.335188 ==
3614 11:41:02.338609 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:41:02.345615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:41:02.345711 ==
3617 11:41:02.355634 TX Vref=22, minBit 0, minWin=25, winSum=413
3618 11:41:02.359232 TX Vref=24, minBit 0, minWin=25, winSum=424
3619 11:41:02.362609 TX Vref=26, minBit 3, minWin=25, winSum=429
3620 11:41:02.365761 TX Vref=28, minBit 0, minWin=26, winSum=430
3621 11:41:02.369218 TX Vref=30, minBit 4, minWin=26, winSum=432
3622 11:41:02.375677 TX Vref=32, minBit 3, minWin=26, winSum=432
3623 11:41:02.379022 [TxChooseVref] Worse bit 4, Min win 26, Win sum 432, Final Vref 30
3624 11:41:02.379108
3625 11:41:02.382288 Final TX Range 1 Vref 30
3626 11:41:02.382373
3627 11:41:02.382453 ==
3628 11:41:02.385208 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 11:41:02.388640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 11:41:02.392036 ==
3631 11:41:02.392114
3632 11:41:02.392177
3633 11:41:02.392236 TX Vref Scan disable
3634 11:41:02.395590 == TX Byte 0 ==
3635 11:41:02.398858 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3636 11:41:02.405135 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3637 11:41:02.405228 == TX Byte 1 ==
3638 11:41:02.408545 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3639 11:41:02.415180 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3640 11:41:02.415275
3641 11:41:02.415374 [DATLAT]
3642 11:41:02.415438 Freq=1200, CH1 RK1
3643 11:41:02.415497
3644 11:41:02.418981 DATLAT Default: 0xd
3645 11:41:02.419064 0, 0xFFFF, sum = 0
3646 11:41:02.421817 1, 0xFFFF, sum = 0
3647 11:41:02.425184 2, 0xFFFF, sum = 0
3648 11:41:02.425269 3, 0xFFFF, sum = 0
3649 11:41:02.428401 4, 0xFFFF, sum = 0
3650 11:41:02.428486 5, 0xFFFF, sum = 0
3651 11:41:02.431866 6, 0xFFFF, sum = 0
3652 11:41:02.431951 7, 0xFFFF, sum = 0
3653 11:41:02.435075 8, 0xFFFF, sum = 0
3654 11:41:02.435186 9, 0xFFFF, sum = 0
3655 11:41:02.438367 10, 0xFFFF, sum = 0
3656 11:41:02.438452 11, 0xFFFF, sum = 0
3657 11:41:02.441800 12, 0x0, sum = 1
3658 11:41:02.441906 13, 0x0, sum = 2
3659 11:41:02.444841 14, 0x0, sum = 3
3660 11:41:02.444913 15, 0x0, sum = 4
3661 11:41:02.448512 best_step = 13
3662 11:41:02.448584
3663 11:41:02.448652 ==
3664 11:41:02.451744 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 11:41:02.454998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 11:41:02.455109 ==
3667 11:41:02.455202 RX Vref Scan: 0
3668 11:41:02.458094
3669 11:41:02.458203 RX Vref 0 -> 0, step: 1
3670 11:41:02.458296
3671 11:41:02.461529 RX Delay -21 -> 252, step: 4
3672 11:41:02.468554 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3673 11:41:02.471621 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3674 11:41:02.475035 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3675 11:41:02.478194 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3676 11:41:02.481351 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3677 11:41:02.487914 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3678 11:41:02.491850 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3679 11:41:02.494915 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3680 11:41:02.497806 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3681 11:41:02.501287 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3682 11:41:02.505040 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3683 11:41:02.511735 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3684 11:41:02.514644 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3685 11:41:02.518134 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3686 11:41:02.521589 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3687 11:41:02.527959 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3688 11:41:02.528047 ==
3689 11:41:02.531361 Dram Type= 6, Freq= 0, CH_1, rank 1
3690 11:41:02.534733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3691 11:41:02.534824 ==
3692 11:41:02.534920 DQS Delay:
3693 11:41:02.538045 DQS0 = 0, DQS1 = 0
3694 11:41:02.538156 DQM Delay:
3695 11:41:02.541333 DQM0 = 113, DQM1 = 110
3696 11:41:02.541439 DQ Delay:
3697 11:41:02.544511 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3698 11:41:02.547882 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3699 11:41:02.551237 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3700 11:41:02.554708 DQ12 =116, DQ13 =120, DQ14 =118, DQ15 =120
3701 11:41:02.554823
3702 11:41:02.554927
3703 11:41:02.564931 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3704 11:41:02.568127 CH1 RK1: MR19=304, MR18=FA02
3705 11:41:02.571218 CH1_RK1: MR19=0x304, MR18=0xFA02, DQSOSC=409, MR23=63, INC=39, DEC=26
3706 11:41:02.574423 [RxdqsGatingPostProcess] freq 1200
3707 11:41:02.581111 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3708 11:41:02.584273 best DQS0 dly(2T, 0.5T) = (0, 11)
3709 11:41:02.587931 best DQS1 dly(2T, 0.5T) = (0, 11)
3710 11:41:02.591176 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3711 11:41:02.594301 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3712 11:41:02.597764 best DQS0 dly(2T, 0.5T) = (0, 11)
3713 11:41:02.601133 best DQS1 dly(2T, 0.5T) = (0, 11)
3714 11:41:02.604933 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3715 11:41:02.607778 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3716 11:41:02.611138 Pre-setting of DQS Precalculation
3717 11:41:02.614615 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3718 11:41:02.621515 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3719 11:41:02.627790 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3720 11:41:02.627877
3721 11:41:02.627942
3722 11:41:02.631253 [Calibration Summary] 2400 Mbps
3723 11:41:02.634277 CH 0, Rank 0
3724 11:41:02.634360 SW Impedance : PASS
3725 11:41:02.637777 DUTY Scan : NO K
3726 11:41:02.641196 ZQ Calibration : PASS
3727 11:41:02.641280 Jitter Meter : NO K
3728 11:41:02.644737 CBT Training : PASS
3729 11:41:02.647893 Write leveling : PASS
3730 11:41:02.647976 RX DQS gating : PASS
3731 11:41:02.651274 RX DQ/DQS(RDDQC) : PASS
3732 11:41:02.654053 TX DQ/DQS : PASS
3733 11:41:02.654137 RX DATLAT : PASS
3734 11:41:02.657467 RX DQ/DQS(Engine): PASS
3735 11:41:02.657549 TX OE : NO K
3736 11:41:02.660847 All Pass.
3737 11:41:02.660930
3738 11:41:02.660994 CH 0, Rank 1
3739 11:41:02.664502 SW Impedance : PASS
3740 11:41:02.664586 DUTY Scan : NO K
3741 11:41:02.667387 ZQ Calibration : PASS
3742 11:41:02.671017 Jitter Meter : NO K
3743 11:41:02.671100 CBT Training : PASS
3744 11:41:02.674347 Write leveling : PASS
3745 11:41:02.677780 RX DQS gating : PASS
3746 11:41:02.677864 RX DQ/DQS(RDDQC) : PASS
3747 11:41:02.680830 TX DQ/DQS : PASS
3748 11:41:02.684098 RX DATLAT : PASS
3749 11:41:02.684188 RX DQ/DQS(Engine): PASS
3750 11:41:02.687610 TX OE : NO K
3751 11:41:02.687694 All Pass.
3752 11:41:02.687758
3753 11:41:02.690804 CH 1, Rank 0
3754 11:41:02.690888 SW Impedance : PASS
3755 11:41:02.694060 DUTY Scan : NO K
3756 11:41:02.697458 ZQ Calibration : PASS
3757 11:41:02.697540 Jitter Meter : NO K
3758 11:41:02.701171 CBT Training : PASS
3759 11:41:02.704244 Write leveling : PASS
3760 11:41:02.704328 RX DQS gating : PASS
3761 11:41:02.707369 RX DQ/DQS(RDDQC) : PASS
3762 11:41:02.707452 TX DQ/DQS : PASS
3763 11:41:02.710886 RX DATLAT : PASS
3764 11:41:02.713856 RX DQ/DQS(Engine): PASS
3765 11:41:02.713940 TX OE : NO K
3766 11:41:02.717348 All Pass.
3767 11:41:02.717433
3768 11:41:02.717498 CH 1, Rank 1
3769 11:41:02.720829 SW Impedance : PASS
3770 11:41:02.720912 DUTY Scan : NO K
3771 11:41:02.724240 ZQ Calibration : PASS
3772 11:41:02.727120 Jitter Meter : NO K
3773 11:41:02.727203 CBT Training : PASS
3774 11:41:02.730517 Write leveling : PASS
3775 11:41:02.733879 RX DQS gating : PASS
3776 11:41:02.733964 RX DQ/DQS(RDDQC) : PASS
3777 11:41:02.737428 TX DQ/DQS : PASS
3778 11:41:02.740768 RX DATLAT : PASS
3779 11:41:02.740852 RX DQ/DQS(Engine): PASS
3780 11:41:02.744218 TX OE : NO K
3781 11:41:02.744302 All Pass.
3782 11:41:02.744370
3783 11:41:02.747672 DramC Write-DBI off
3784 11:41:02.750498 PER_BANK_REFRESH: Hybrid Mode
3785 11:41:02.750582 TX_TRACKING: ON
3786 11:41:02.760637 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3787 11:41:02.764007 [FAST_K] Save calibration result to emmc
3788 11:41:02.767259 dramc_set_vcore_voltage set vcore to 650000
3789 11:41:02.770812 Read voltage for 600, 5
3790 11:41:02.770899 Vio18 = 0
3791 11:41:02.770965 Vcore = 650000
3792 11:41:02.773740 Vdram = 0
3793 11:41:02.773821 Vddq = 0
3794 11:41:02.773885 Vmddr = 0
3795 11:41:02.780599 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3796 11:41:02.783980 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3797 11:41:02.787501 MEM_TYPE=3, freq_sel=19
3798 11:41:02.790429 sv_algorithm_assistance_LP4_1600
3799 11:41:02.793529 ============ PULL DRAM RESETB DOWN ============
3800 11:41:02.797040 ========== PULL DRAM RESETB DOWN end =========
3801 11:41:02.803736 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3802 11:41:02.806779 ===================================
3803 11:41:02.809802 LPDDR4 DRAM CONFIGURATION
3804 11:41:02.813509 ===================================
3805 11:41:02.813589 EX_ROW_EN[0] = 0x0
3806 11:41:02.816758 EX_ROW_EN[1] = 0x0
3807 11:41:02.816840 LP4Y_EN = 0x0
3808 11:41:02.820291 WORK_FSP = 0x0
3809 11:41:02.820373 WL = 0x2
3810 11:41:02.823169 RL = 0x2
3811 11:41:02.823250 BL = 0x2
3812 11:41:02.827021 RPST = 0x0
3813 11:41:02.827104 RD_PRE = 0x0
3814 11:41:02.830489 WR_PRE = 0x1
3815 11:41:02.830570 WR_PST = 0x0
3816 11:41:02.833569 DBI_WR = 0x0
3817 11:41:02.833666 DBI_RD = 0x0
3818 11:41:02.836811 OTF = 0x1
3819 11:41:02.840304 ===================================
3820 11:41:02.843593 ===================================
3821 11:41:02.843691 ANA top config
3822 11:41:02.846461 ===================================
3823 11:41:02.850294 DLL_ASYNC_EN = 0
3824 11:41:02.853492 ALL_SLAVE_EN = 1
3825 11:41:02.856532 NEW_RANK_MODE = 1
3826 11:41:02.856677 DLL_IDLE_MODE = 1
3827 11:41:02.860287 LP45_APHY_COMB_EN = 1
3828 11:41:02.863170 TX_ODT_DIS = 1
3829 11:41:02.866656 NEW_8X_MODE = 1
3830 11:41:02.870012 ===================================
3831 11:41:02.873446 ===================================
3832 11:41:02.876810 data_rate = 1200
3833 11:41:02.876893 CKR = 1
3834 11:41:02.879983 DQ_P2S_RATIO = 8
3835 11:41:02.883451 ===================================
3836 11:41:02.886651 CA_P2S_RATIO = 8
3837 11:41:02.889969 DQ_CA_OPEN = 0
3838 11:41:02.893045 DQ_SEMI_OPEN = 0
3839 11:41:02.896345 CA_SEMI_OPEN = 0
3840 11:41:02.896426 CA_FULL_RATE = 0
3841 11:41:02.899820 DQ_CKDIV4_EN = 1
3842 11:41:02.903202 CA_CKDIV4_EN = 1
3843 11:41:02.906318 CA_PREDIV_EN = 0
3844 11:41:02.910052 PH8_DLY = 0
3845 11:41:02.913009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3846 11:41:02.913121 DQ_AAMCK_DIV = 4
3847 11:41:02.916348 CA_AAMCK_DIV = 4
3848 11:41:02.920167 CA_ADMCK_DIV = 4
3849 11:41:02.923079 DQ_TRACK_CA_EN = 0
3850 11:41:02.926335 CA_PICK = 600
3851 11:41:02.929843 CA_MCKIO = 600
3852 11:41:02.929957 MCKIO_SEMI = 0
3853 11:41:02.933062 PLL_FREQ = 2288
3854 11:41:02.936562 DQ_UI_PI_RATIO = 32
3855 11:41:02.939848 CA_UI_PI_RATIO = 0
3856 11:41:02.943133 ===================================
3857 11:41:02.946426 ===================================
3858 11:41:02.949750 memory_type:LPDDR4
3859 11:41:02.949860 GP_NUM : 10
3860 11:41:02.952717 SRAM_EN : 1
3861 11:41:02.956102 MD32_EN : 0
3862 11:41:02.959759 ===================================
3863 11:41:02.959861 [ANA_INIT] >>>>>>>>>>>>>>
3864 11:41:02.963395 <<<<<< [CONFIGURE PHASE]: ANA_TX
3865 11:41:02.965934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3866 11:41:02.969587 ===================================
3867 11:41:02.973076 data_rate = 1200,PCW = 0X5800
3868 11:41:02.975872 ===================================
3869 11:41:02.979728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3870 11:41:02.986008 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3871 11:41:02.989400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 11:41:02.996214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3873 11:41:02.999986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3874 11:41:03.002337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3875 11:41:03.005864 [ANA_INIT] flow start
3876 11:41:03.005972 [ANA_INIT] PLL >>>>>>>>
3877 11:41:03.009026 [ANA_INIT] PLL <<<<<<<<
3878 11:41:03.012239 [ANA_INIT] MIDPI >>>>>>>>
3879 11:41:03.012351 [ANA_INIT] MIDPI <<<<<<<<
3880 11:41:03.016097 [ANA_INIT] DLL >>>>>>>>
3881 11:41:03.019005 [ANA_INIT] flow end
3882 11:41:03.022371 ============ LP4 DIFF to SE enter ============
3883 11:41:03.026000 ============ LP4 DIFF to SE exit ============
3884 11:41:03.029217 [ANA_INIT] <<<<<<<<<<<<<
3885 11:41:03.032537 [Flow] Enable top DCM control >>>>>
3886 11:41:03.036093 [Flow] Enable top DCM control <<<<<
3887 11:41:03.039065 Enable DLL master slave shuffle
3888 11:41:03.042351 ==============================================================
3889 11:41:03.046068 Gating Mode config
3890 11:41:03.049055 ==============================================================
3891 11:41:03.052509 Config description:
3892 11:41:03.062329 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3893 11:41:03.069045 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3894 11:41:03.072854 SELPH_MODE 0: By rank 1: By Phase
3895 11:41:03.078765 ==============================================================
3896 11:41:03.082188 GAT_TRACK_EN = 1
3897 11:41:03.085771 RX_GATING_MODE = 2
3898 11:41:03.088947 RX_GATING_TRACK_MODE = 2
3899 11:41:03.092649 SELPH_MODE = 1
3900 11:41:03.095926 PICG_EARLY_EN = 1
3901 11:41:03.096047 VALID_LAT_VALUE = 1
3902 11:41:03.102419 ==============================================================
3903 11:41:03.105734 Enter into Gating configuration >>>>
3904 11:41:03.108560 Exit from Gating configuration <<<<
3905 11:41:03.112334 Enter into DVFS_PRE_config >>>>>
3906 11:41:03.122417 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3907 11:41:03.125393 Exit from DVFS_PRE_config <<<<<
3908 11:41:03.128500 Enter into PICG configuration >>>>
3909 11:41:03.131960 Exit from PICG configuration <<<<
3910 11:41:03.135660 [RX_INPUT] configuration >>>>>
3911 11:41:03.138952 [RX_INPUT] configuration <<<<<
3912 11:41:03.145427 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3913 11:41:03.148879 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3914 11:41:03.155498 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 11:41:03.162122 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 11:41:03.168477 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 11:41:03.175424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 11:41:03.178886 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3919 11:41:03.181794 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3920 11:41:03.185290 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3921 11:41:03.191831 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3922 11:41:03.195239 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3923 11:41:03.198614 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3924 11:41:03.201623 ===================================
3925 11:41:03.205488 LPDDR4 DRAM CONFIGURATION
3926 11:41:03.208574 ===================================
3927 11:41:03.208696 EX_ROW_EN[0] = 0x0
3928 11:41:03.211803 EX_ROW_EN[1] = 0x0
3929 11:41:03.211917 LP4Y_EN = 0x0
3930 11:41:03.215340 WORK_FSP = 0x0
3931 11:41:03.218353 WL = 0x2
3932 11:41:03.218470 RL = 0x2
3933 11:41:03.221737 BL = 0x2
3934 11:41:03.221849 RPST = 0x0
3935 11:41:03.225155 RD_PRE = 0x0
3936 11:41:03.225265 WR_PRE = 0x1
3937 11:41:03.228549 WR_PST = 0x0
3938 11:41:03.228654 DBI_WR = 0x0
3939 11:41:03.231771 DBI_RD = 0x0
3940 11:41:03.231852 OTF = 0x1
3941 11:41:03.235041 ===================================
3942 11:41:03.238126 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3943 11:41:03.244918 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3944 11:41:03.248218 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3945 11:41:03.251428 ===================================
3946 11:41:03.254936 LPDDR4 DRAM CONFIGURATION
3947 11:41:03.258275 ===================================
3948 11:41:03.258398 EX_ROW_EN[0] = 0x10
3949 11:41:03.261585 EX_ROW_EN[1] = 0x0
3950 11:41:03.261703 LP4Y_EN = 0x0
3951 11:41:03.264963 WORK_FSP = 0x0
3952 11:41:03.265077 WL = 0x2
3953 11:41:03.268351 RL = 0x2
3954 11:41:03.271775 BL = 0x2
3955 11:41:03.271891 RPST = 0x0
3956 11:41:03.274613 RD_PRE = 0x0
3957 11:41:03.274737 WR_PRE = 0x1
3958 11:41:03.278384 WR_PST = 0x0
3959 11:41:03.278486 DBI_WR = 0x0
3960 11:41:03.281256 DBI_RD = 0x0
3961 11:41:03.281340 OTF = 0x1
3962 11:41:03.284962 ===================================
3963 11:41:03.291781 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3964 11:41:03.294954 nWR fixed to 30
3965 11:41:03.298614 [ModeRegInit_LP4] CH0 RK0
3966 11:41:03.298728 [ModeRegInit_LP4] CH0 RK1
3967 11:41:03.301753 [ModeRegInit_LP4] CH1 RK0
3968 11:41:03.305242 [ModeRegInit_LP4] CH1 RK1
3969 11:41:03.305326 match AC timing 17
3970 11:41:03.312163 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3971 11:41:03.315077 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3972 11:41:03.318328 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3973 11:41:03.325089 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3974 11:41:03.328928 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3975 11:41:03.329038 ==
3976 11:41:03.331777 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 11:41:03.335067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 11:41:03.335167 ==
3979 11:41:03.341890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 11:41:03.348400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3981 11:41:03.352326 [CA 0] Center 36 (6~66) winsize 61
3982 11:41:03.355216 [CA 1] Center 35 (5~66) winsize 62
3983 11:41:03.358578 [CA 2] Center 34 (4~65) winsize 62
3984 11:41:03.361525 [CA 3] Center 34 (4~65) winsize 62
3985 11:41:03.364991 [CA 4] Center 33 (3~64) winsize 62
3986 11:41:03.368261 [CA 5] Center 33 (3~64) winsize 62
3987 11:41:03.368336
3988 11:41:03.371748 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3989 11:41:03.371848
3990 11:41:03.375270 [CATrainingPosCal] consider 1 rank data
3991 11:41:03.378001 u2DelayCellTimex100 = 270/100 ps
3992 11:41:03.381357 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3993 11:41:03.384825 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3994 11:41:03.388430 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 11:41:03.391727 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 11:41:03.395106 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 11:41:03.398045 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 11:41:03.401638
3999 11:41:03.405028 CA PerBit enable=1, Macro0, CA PI delay=33
4000 11:41:03.405113
4001 11:41:03.408394 [CBTSetCACLKResult] CA Dly = 33
4002 11:41:03.408479 CS Dly: 5 (0~36)
4003 11:41:03.408545 ==
4004 11:41:03.411324 Dram Type= 6, Freq= 0, CH_0, rank 1
4005 11:41:03.414802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 11:41:03.414917 ==
4007 11:41:03.421408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4008 11:41:03.428136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4009 11:41:03.431630 [CA 0] Center 36 (6~66) winsize 61
4010 11:41:03.435000 [CA 1] Center 36 (6~66) winsize 61
4011 11:41:03.437910 [CA 2] Center 34 (4~65) winsize 62
4012 11:41:03.441060 [CA 3] Center 34 (4~65) winsize 62
4013 11:41:03.444429 [CA 4] Center 33 (3~64) winsize 62
4014 11:41:03.447912 [CA 5] Center 33 (3~64) winsize 62
4015 11:41:03.448020
4016 11:41:03.451010 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4017 11:41:03.451083
4018 11:41:03.454566 [CATrainingPosCal] consider 2 rank data
4019 11:41:03.457511 u2DelayCellTimex100 = 270/100 ps
4020 11:41:03.460989 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4021 11:41:03.464658 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 11:41:03.467944 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4023 11:41:03.471035 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4024 11:41:03.477967 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4025 11:41:03.480937 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 11:41:03.481043
4027 11:41:03.484485 CA PerBit enable=1, Macro0, CA PI delay=33
4028 11:41:03.484576
4029 11:41:03.487893 [CBTSetCACLKResult] CA Dly = 33
4030 11:41:03.487983 CS Dly: 5 (0~36)
4031 11:41:03.488057
4032 11:41:03.491342 ----->DramcWriteLeveling(PI) begin...
4033 11:41:03.491442 ==
4034 11:41:03.494171 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 11:41:03.501033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 11:41:03.501128 ==
4037 11:41:03.504023 Write leveling (Byte 0): 32 => 32
4038 11:41:03.507665 Write leveling (Byte 1): 30 => 30
4039 11:41:03.507760 DramcWriteLeveling(PI) end<-----
4040 11:41:03.507825
4041 11:41:03.511093 ==
4042 11:41:03.514816 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 11:41:03.517389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 11:41:03.517511 ==
4045 11:41:03.520976 [Gating] SW mode calibration
4046 11:41:03.528167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4047 11:41:03.530785 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4048 11:41:03.537254 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 11:41:03.540841 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 11:41:03.543980 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 11:41:03.550547 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4052 11:41:03.553841 0 9 16 | B1->B0 | 2f2f 2727 | 0 1 | (0 0) (1 0)
4053 11:41:03.557248 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4054 11:41:03.564021 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 11:41:03.567213 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 11:41:03.570415 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 11:41:03.577033 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 11:41:03.580553 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 11:41:03.583773 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 11:41:03.590394 0 10 16 | B1->B0 | 3030 3b3b | 0 1 | (0 0) (0 0)
4061 11:41:03.593895 0 10 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4062 11:41:03.597036 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:41:03.603584 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:41:03.607015 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 11:41:03.610435 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 11:41:03.617050 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 11:41:03.620505 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 11:41:03.623435 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4069 11:41:03.630235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:41:03.633953 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:41:03.636707 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:41:03.640412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:41:03.646870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:41:03.650021 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:41:03.653361 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:41:03.660099 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:41:03.663534 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:41:03.667110 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:41:03.673661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:41:03.676995 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:41:03.679745 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:41:03.686666 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:41:03.690131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:41:03.693477 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4085 11:41:03.699847 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4086 11:41:03.703262 Total UI for P1: 0, mck2ui 16
4087 11:41:03.706848 best dqsien dly found for B0: ( 0, 13, 16)
4088 11:41:03.709704 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 11:41:03.713373 Total UI for P1: 0, mck2ui 16
4090 11:41:03.716650 best dqsien dly found for B1: ( 0, 13, 18)
4091 11:41:03.719533 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4092 11:41:03.723097 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4093 11:41:03.723185
4094 11:41:03.726490 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4095 11:41:03.729872 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4096 11:41:03.732725 [Gating] SW calibration Done
4097 11:41:03.732845 ==
4098 11:41:03.736215 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 11:41:03.742690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 11:41:03.742806 ==
4101 11:41:03.742916 RX Vref Scan: 0
4102 11:41:03.743022
4103 11:41:03.745919 RX Vref 0 -> 0, step: 1
4104 11:41:03.746034
4105 11:41:03.749343 RX Delay -230 -> 252, step: 16
4106 11:41:03.752602 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4107 11:41:03.756113 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4108 11:41:03.759792 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4109 11:41:03.766165 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4110 11:41:03.769491 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4111 11:41:03.772976 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4112 11:41:03.776208 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4113 11:41:03.779527 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4114 11:41:03.786205 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4115 11:41:03.789655 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4116 11:41:03.792443 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4117 11:41:03.795756 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4118 11:41:03.802530 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4119 11:41:03.805958 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4120 11:41:03.808983 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4121 11:41:03.812846 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4122 11:41:03.815680 ==
4123 11:41:03.818933 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 11:41:03.822332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 11:41:03.822436 ==
4126 11:41:03.822516 DQS Delay:
4127 11:41:03.825817 DQS0 = 0, DQS1 = 0
4128 11:41:03.825922 DQM Delay:
4129 11:41:03.828893 DQM0 = 41, DQM1 = 33
4130 11:41:03.828993 DQ Delay:
4131 11:41:03.832227 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4132 11:41:03.835745 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4133 11:41:03.839105 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4134 11:41:03.842498 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4135 11:41:03.842573
4136 11:41:03.842635
4137 11:41:03.842694 ==
4138 11:41:03.845900 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 11:41:03.849326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 11:41:03.849411 ==
4141 11:41:03.849477
4142 11:41:03.849537
4143 11:41:03.852341 TX Vref Scan disable
4144 11:41:03.855475 == TX Byte 0 ==
4145 11:41:03.858948 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4146 11:41:03.862281 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4147 11:41:03.865643 == TX Byte 1 ==
4148 11:41:03.868917 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4149 11:41:03.872233 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4150 11:41:03.872317 ==
4151 11:41:03.875610 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 11:41:03.878912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 11:41:03.882058 ==
4154 11:41:03.882170
4155 11:41:03.882263
4156 11:41:03.882359 TX Vref Scan disable
4157 11:41:03.886424 == TX Byte 0 ==
4158 11:41:03.889600 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4159 11:41:03.892776 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4160 11:41:03.896477 == TX Byte 1 ==
4161 11:41:03.899849 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4162 11:41:03.906111 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4163 11:41:03.906228
4164 11:41:03.906325 [DATLAT]
4165 11:41:03.906439 Freq=600, CH0 RK0
4166 11:41:03.906547
4167 11:41:03.909633 DATLAT Default: 0x9
4168 11:41:03.909745 0, 0xFFFF, sum = 0
4169 11:41:03.912973 1, 0xFFFF, sum = 0
4170 11:41:03.913057 2, 0xFFFF, sum = 0
4171 11:41:03.916624 3, 0xFFFF, sum = 0
4172 11:41:03.919506 4, 0xFFFF, sum = 0
4173 11:41:03.919591 5, 0xFFFF, sum = 0
4174 11:41:03.922707 6, 0xFFFF, sum = 0
4175 11:41:03.922792 7, 0xFFFF, sum = 0
4176 11:41:03.926110 8, 0x0, sum = 1
4177 11:41:03.926195 9, 0x0, sum = 2
4178 11:41:03.926263 10, 0x0, sum = 3
4179 11:41:03.929691 11, 0x0, sum = 4
4180 11:41:03.929776 best_step = 9
4181 11:41:03.929842
4182 11:41:03.929903 ==
4183 11:41:03.932958 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 11:41:03.940019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 11:41:03.940104 ==
4186 11:41:03.940170 RX Vref Scan: 1
4187 11:41:03.940231
4188 11:41:03.942779 RX Vref 0 -> 0, step: 1
4189 11:41:03.942862
4190 11:41:03.946321 RX Delay -195 -> 252, step: 8
4191 11:41:03.946404
4192 11:41:03.949654 Set Vref, RX VrefLevel [Byte0]: 54
4193 11:41:03.953367 [Byte1]: 51
4194 11:41:03.953451
4195 11:41:03.955878 Final RX Vref Byte 0 = 54 to rank0
4196 11:41:03.959722 Final RX Vref Byte 1 = 51 to rank0
4197 11:41:03.962865 Final RX Vref Byte 0 = 54 to rank1
4198 11:41:03.966236 Final RX Vref Byte 1 = 51 to rank1==
4199 11:41:03.969143 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 11:41:03.972602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 11:41:03.972686 ==
4202 11:41:03.976073 DQS Delay:
4203 11:41:03.976157 DQS0 = 0, DQS1 = 0
4204 11:41:03.979544 DQM Delay:
4205 11:41:03.979628 DQM0 = 42, DQM1 = 33
4206 11:41:03.979694 DQ Delay:
4207 11:41:03.982958 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4208 11:41:03.985809 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4209 11:41:03.989114 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4210 11:41:03.992450 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4211 11:41:03.992536
4212 11:41:03.992602
4213 11:41:04.002475 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4214 11:41:04.005934 CH0 RK0: MR19=808, MR18=3F1D
4215 11:41:04.009005 CH0_RK0: MR19=0x808, MR18=0x3F1D, DQSOSC=397, MR23=63, INC=166, DEC=110
4216 11:41:04.012458
4217 11:41:04.016029 ----->DramcWriteLeveling(PI) begin...
4218 11:41:04.016148 ==
4219 11:41:04.019380 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 11:41:04.022230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 11:41:04.022316 ==
4222 11:41:04.025595 Write leveling (Byte 0): 31 => 31
4223 11:41:04.029046 Write leveling (Byte 1): 31 => 31
4224 11:41:04.032312 DramcWriteLeveling(PI) end<-----
4225 11:41:04.032395
4226 11:41:04.032459 ==
4227 11:41:04.035873 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 11:41:04.039321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 11:41:04.039417 ==
4230 11:41:04.042365 [Gating] SW mode calibration
4231 11:41:04.049304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4232 11:41:04.055470 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4233 11:41:04.058941 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 11:41:04.062243 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 11:41:04.069001 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4236 11:41:04.072366 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4237 11:41:04.075346 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4238 11:41:04.082166 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 11:41:04.085294 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 11:41:04.088607 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 11:41:04.095883 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 11:41:04.099151 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 11:41:04.102257 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 11:41:04.106183 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4245 11:41:04.112246 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
4246 11:41:04.115802 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:41:04.118807 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 11:41:04.125294 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 11:41:04.128955 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 11:41:04.132361 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 11:41:04.138864 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:41:04.142248 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4253 11:41:04.145371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:41:04.152146 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4255 11:41:04.155751 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:41:04.159262 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:41:04.165494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:41:04.168875 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:41:04.172080 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:41:04.178803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:41:04.182198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:41:04.185887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:41:04.192367 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:41:04.195817 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:41:04.198493 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:41:04.202087 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:41:04.208808 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:41:04.211968 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4269 11:41:04.215377 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4270 11:41:04.218557 Total UI for P1: 0, mck2ui 16
4271 11:41:04.221972 best dqsien dly found for B0: ( 0, 13, 12)
4272 11:41:04.228765 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 11:41:04.231760 Total UI for P1: 0, mck2ui 16
4274 11:41:04.235096 best dqsien dly found for B1: ( 0, 13, 14)
4275 11:41:04.238511 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4276 11:41:04.241942 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4277 11:41:04.242058
4278 11:41:04.245480 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4279 11:41:04.248346 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4280 11:41:04.251799 [Gating] SW calibration Done
4281 11:41:04.251886 ==
4282 11:41:04.255087 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 11:41:04.258484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 11:41:04.258574 ==
4285 11:41:04.261664 RX Vref Scan: 0
4286 11:41:04.261750
4287 11:41:04.264960 RX Vref 0 -> 0, step: 1
4288 11:41:04.265047
4289 11:41:04.265113 RX Delay -230 -> 252, step: 16
4290 11:41:04.271815 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4291 11:41:04.275263 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4292 11:41:04.278509 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4293 11:41:04.281958 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 11:41:04.289154 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4295 11:41:04.291588 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4296 11:41:04.294832 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 11:41:04.298550 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4298 11:41:04.301517 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4299 11:41:04.308557 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4300 11:41:04.311813 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 11:41:04.314904 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4302 11:41:04.318286 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4303 11:41:04.325092 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4304 11:41:04.328209 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4305 11:41:04.331671 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4306 11:41:04.331755 ==
4307 11:41:04.334692 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 11:41:04.338015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 11:41:04.341082 ==
4310 11:41:04.341186 DQS Delay:
4311 11:41:04.341269 DQS0 = 0, DQS1 = 0
4312 11:41:04.344590 DQM Delay:
4313 11:41:04.344663 DQM0 = 39, DQM1 = 34
4314 11:41:04.348246 DQ Delay:
4315 11:41:04.351609 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4316 11:41:04.351710 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4317 11:41:04.354944 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4318 11:41:04.357810 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4319 11:41:04.361313
4320 11:41:04.361447
4321 11:41:04.361579 ==
4322 11:41:04.364769 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 11:41:04.368191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 11:41:04.368331 ==
4325 11:41:04.368426
4326 11:41:04.368513
4327 11:41:04.371046 TX Vref Scan disable
4328 11:41:04.371141 == TX Byte 0 ==
4329 11:41:04.378071 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4330 11:41:04.381352 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4331 11:41:04.381458 == TX Byte 1 ==
4332 11:41:04.387795 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4333 11:41:04.391128 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4334 11:41:04.391311 ==
4335 11:41:04.394462 Dram Type= 6, Freq= 0, CH_0, rank 1
4336 11:41:04.397796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 11:41:04.397922 ==
4338 11:41:04.397991
4339 11:41:04.398052
4340 11:41:04.401507 TX Vref Scan disable
4341 11:41:04.404497 == TX Byte 0 ==
4342 11:41:04.407606 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4343 11:41:04.411309 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4344 11:41:04.414473 == TX Byte 1 ==
4345 11:41:04.417826 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4346 11:41:04.420947 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4347 11:41:04.424052
4348 11:41:04.424167 [DATLAT]
4349 11:41:04.424256 Freq=600, CH0 RK1
4350 11:41:04.424321
4351 11:41:04.427380 DATLAT Default: 0x9
4352 11:41:04.427487 0, 0xFFFF, sum = 0
4353 11:41:04.431009 1, 0xFFFF, sum = 0
4354 11:41:04.431147 2, 0xFFFF, sum = 0
4355 11:41:04.434354 3, 0xFFFF, sum = 0
4356 11:41:04.434436 4, 0xFFFF, sum = 0
4357 11:41:04.437509 5, 0xFFFF, sum = 0
4358 11:41:04.441188 6, 0xFFFF, sum = 0
4359 11:41:04.441293 7, 0xFFFF, sum = 0
4360 11:41:04.443831 8, 0x0, sum = 1
4361 11:41:04.443909 9, 0x0, sum = 2
4362 11:41:04.443992 10, 0x0, sum = 3
4363 11:41:04.447733 11, 0x0, sum = 4
4364 11:41:04.447804 best_step = 9
4365 11:41:04.447868
4366 11:41:04.447931 ==
4367 11:41:04.450575 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 11:41:04.457360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 11:41:04.457465 ==
4370 11:41:04.457555 RX Vref Scan: 0
4371 11:41:04.457641
4372 11:41:04.460833 RX Vref 0 -> 0, step: 1
4373 11:41:04.460931
4374 11:41:04.463599 RX Delay -179 -> 252, step: 8
4375 11:41:04.467153 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4376 11:41:04.473803 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4377 11:41:04.477263 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4378 11:41:04.480743 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4379 11:41:04.484116 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4380 11:41:04.487482 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4381 11:41:04.493951 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4382 11:41:04.497346 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4383 11:41:04.500395 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4384 11:41:04.503658 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4385 11:41:04.510291 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4386 11:41:04.514108 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4387 11:41:04.517167 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4388 11:41:04.520590 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4389 11:41:04.527049 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4390 11:41:04.530766 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4391 11:41:04.530853 ==
4392 11:41:04.533746 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 11:41:04.537622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 11:41:04.537729 ==
4395 11:41:04.540526 DQS Delay:
4396 11:41:04.540621 DQS0 = 0, DQS1 = 0
4397 11:41:04.540709 DQM Delay:
4398 11:41:04.543706 DQM0 = 39, DQM1 = 32
4399 11:41:04.543773 DQ Delay:
4400 11:41:04.547035 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4401 11:41:04.550237 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4402 11:41:04.553630 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4403 11:41:04.557018 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4404 11:41:04.557088
4405 11:41:04.557146
4406 11:41:04.566784 [DQSOSCAuto] RK1, (LSB)MR18= 0x482a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4407 11:41:04.566871 CH0 RK1: MR19=808, MR18=482A
4408 11:41:04.574143 CH0_RK1: MR19=0x808, MR18=0x482A, DQSOSC=396, MR23=63, INC=167, DEC=111
4409 11:41:04.576788 [RxdqsGatingPostProcess] freq 600
4410 11:41:04.583767 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4411 11:41:04.587252 Pre-setting of DQS Precalculation
4412 11:41:04.590639 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4413 11:41:04.590714 ==
4414 11:41:04.593563 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 11:41:04.596893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 11:41:04.600534 ==
4417 11:41:04.603975 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 11:41:04.610008 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4419 11:41:04.613276 [CA 0] Center 35 (5~65) winsize 61
4420 11:41:04.617059 [CA 1] Center 35 (5~66) winsize 62
4421 11:41:04.620460 [CA 2] Center 33 (3~64) winsize 62
4422 11:41:04.623540 [CA 3] Center 33 (3~64) winsize 62
4423 11:41:04.626851 [CA 4] Center 34 (3~65) winsize 63
4424 11:41:04.630194 [CA 5] Center 33 (3~64) winsize 62
4425 11:41:04.630281
4426 11:41:04.633614 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4427 11:41:04.633707
4428 11:41:04.636745 [CATrainingPosCal] consider 1 rank data
4429 11:41:04.640195 u2DelayCellTimex100 = 270/100 ps
4430 11:41:04.643220 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4431 11:41:04.647256 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 11:41:04.649712 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 11:41:04.656524 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 11:41:04.660036 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4435 11:41:04.663209 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 11:41:04.663318
4437 11:41:04.666676 CA PerBit enable=1, Macro0, CA PI delay=33
4438 11:41:04.666751
4439 11:41:04.670128 [CBTSetCACLKResult] CA Dly = 33
4440 11:41:04.670242 CS Dly: 4 (0~35)
4441 11:41:04.670339 ==
4442 11:41:04.673400 Dram Type= 6, Freq= 0, CH_1, rank 1
4443 11:41:04.679763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 11:41:04.679847 ==
4445 11:41:04.683027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4446 11:41:04.689981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4447 11:41:04.693620 [CA 0] Center 35 (5~66) winsize 62
4448 11:41:04.696567 [CA 1] Center 36 (6~66) winsize 61
4449 11:41:04.699611 [CA 2] Center 34 (3~65) winsize 63
4450 11:41:04.703332 [CA 3] Center 34 (3~65) winsize 63
4451 11:41:04.706744 [CA 4] Center 34 (4~65) winsize 62
4452 11:41:04.709654 [CA 5] Center 33 (3~64) winsize 62
4453 11:41:04.709739
4454 11:41:04.713109 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4455 11:41:04.713195
4456 11:41:04.716448 [CATrainingPosCal] consider 2 rank data
4457 11:41:04.719757 u2DelayCellTimex100 = 270/100 ps
4458 11:41:04.722859 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4459 11:41:04.729303 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4460 11:41:04.732710 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 11:41:04.735948 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4462 11:41:04.739577 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4463 11:41:04.743055 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4464 11:41:04.743178
4465 11:41:04.746323 CA PerBit enable=1, Macro0, CA PI delay=33
4466 11:41:04.746418
4467 11:41:04.749599 [CBTSetCACLKResult] CA Dly = 33
4468 11:41:04.752653 CS Dly: 4 (0~36)
4469 11:41:04.752750
4470 11:41:04.755884 ----->DramcWriteLeveling(PI) begin...
4471 11:41:04.755969 ==
4472 11:41:04.759530 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 11:41:04.762794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 11:41:04.762879 ==
4475 11:41:04.765926 Write leveling (Byte 0): 29 => 29
4476 11:41:04.769140 Write leveling (Byte 1): 30 => 30
4477 11:41:04.772749 DramcWriteLeveling(PI) end<-----
4478 11:41:04.772827
4479 11:41:04.772891 ==
4480 11:41:04.775687 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 11:41:04.779204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 11:41:04.779295 ==
4483 11:41:04.782772 [Gating] SW mode calibration
4484 11:41:04.789125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4485 11:41:04.796235 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4486 11:41:04.799593 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 11:41:04.802217 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 11:41:04.809120 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 11:41:04.812759 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
4490 11:41:04.815981 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (0 0)
4491 11:41:04.822676 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 11:41:04.825602 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 11:41:04.829199 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 11:41:04.835695 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 11:41:04.839154 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 11:41:04.842477 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 11:41:04.845663 0 10 12 | B1->B0 | 2828 2b2b | 0 0 | (0 0) (0 0)
4498 11:41:04.852509 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
4499 11:41:04.855840 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 11:41:04.859240 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 11:41:04.865629 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 11:41:04.868904 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 11:41:04.872181 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:41:04.879104 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 11:41:04.882594 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 11:41:04.885717 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:41:04.892598 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:41:04.895718 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:41:04.899198 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:41:04.905735 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:41:04.908685 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:41:04.912197 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:41:04.918623 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:41:04.922549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:41:04.925516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:41:04.932060 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:41:04.935955 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:41:04.938617 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:41:04.945547 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:41:04.948897 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:41:04.952162 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4522 11:41:04.958687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 11:41:04.958774 Total UI for P1: 0, mck2ui 16
4524 11:41:04.965328 best dqsien dly found for B0: ( 0, 13, 12)
4525 11:41:04.965416 Total UI for P1: 0, mck2ui 16
4526 11:41:04.968714 best dqsien dly found for B1: ( 0, 13, 14)
4527 11:41:04.975539 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4528 11:41:04.978478 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4529 11:41:04.978564
4530 11:41:04.981811 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4531 11:41:04.985396 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4532 11:41:04.988366 [Gating] SW calibration Done
4533 11:41:04.988453 ==
4534 11:41:04.991565 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 11:41:04.995149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 11:41:04.995259 ==
4537 11:41:04.998777 RX Vref Scan: 0
4538 11:41:04.998862
4539 11:41:04.998948 RX Vref 0 -> 0, step: 1
4540 11:41:04.999048
4541 11:41:05.001778 RX Delay -230 -> 252, step: 16
4542 11:41:05.005242 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4543 11:41:05.011867 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4544 11:41:05.014861 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4545 11:41:05.018234 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4546 11:41:05.022035 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4547 11:41:05.028735 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4548 11:41:05.031751 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4549 11:41:05.035226 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4550 11:41:05.038240 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4551 11:41:05.041820 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4552 11:41:05.048441 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4553 11:41:05.051308 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4554 11:41:05.054948 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4555 11:41:05.058110 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4556 11:41:05.065122 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4557 11:41:05.068049 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4558 11:41:05.068160 ==
4559 11:41:05.071309 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 11:41:05.074520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 11:41:05.074611 ==
4562 11:41:05.078120 DQS Delay:
4563 11:41:05.078228 DQS0 = 0, DQS1 = 0
4564 11:41:05.078321 DQM Delay:
4565 11:41:05.081143 DQM0 = 43, DQM1 = 35
4566 11:41:05.081252 DQ Delay:
4567 11:41:05.084375 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4568 11:41:05.088129 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4569 11:41:05.091079 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4570 11:41:05.094859 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4571 11:41:05.095004
4572 11:41:05.095101
4573 11:41:05.095191 ==
4574 11:41:05.097808 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 11:41:05.104395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 11:41:05.104504 ==
4577 11:41:05.104597
4578 11:41:05.104687
4579 11:41:05.104783 TX Vref Scan disable
4580 11:41:05.108468 == TX Byte 0 ==
4581 11:41:05.111884 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4582 11:41:05.118523 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4583 11:41:05.118640 == TX Byte 1 ==
4584 11:41:05.121612 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4585 11:41:05.128650 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4586 11:41:05.128755 ==
4587 11:41:05.131685 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 11:41:05.134759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:41:05.134859 ==
4590 11:41:05.134954
4591 11:41:05.135044
4592 11:41:05.138207 TX Vref Scan disable
4593 11:41:05.141213 == TX Byte 0 ==
4594 11:41:05.144771 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4595 11:41:05.148325 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4596 11:41:05.151718 == TX Byte 1 ==
4597 11:41:05.154983 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4598 11:41:05.158342 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4599 11:41:05.158448
4600 11:41:05.158538 [DATLAT]
4601 11:41:05.161256 Freq=600, CH1 RK0
4602 11:41:05.161356
4603 11:41:05.164702 DATLAT Default: 0x9
4604 11:41:05.164801 0, 0xFFFF, sum = 0
4605 11:41:05.168250 1, 0xFFFF, sum = 0
4606 11:41:05.168408 2, 0xFFFF, sum = 0
4607 11:41:05.171309 3, 0xFFFF, sum = 0
4608 11:41:05.171443 4, 0xFFFF, sum = 0
4609 11:41:05.174763 5, 0xFFFF, sum = 0
4610 11:41:05.174880 6, 0xFFFF, sum = 0
4611 11:41:05.177863 7, 0xFFFF, sum = 0
4612 11:41:05.177969 8, 0x0, sum = 1
4613 11:41:05.180957 9, 0x0, sum = 2
4614 11:41:05.181065 10, 0x0, sum = 3
4615 11:41:05.181156 11, 0x0, sum = 4
4616 11:41:05.184865 best_step = 9
4617 11:41:05.184970
4618 11:41:05.185071 ==
4619 11:41:05.188098 Dram Type= 6, Freq= 0, CH_1, rank 0
4620 11:41:05.191230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 11:41:05.191342 ==
4622 11:41:05.194468 RX Vref Scan: 1
4623 11:41:05.194570
4624 11:41:05.197761 RX Vref 0 -> 0, step: 1
4625 11:41:05.197861
4626 11:41:05.197951 RX Delay -195 -> 252, step: 8
4627 11:41:05.198041
4628 11:41:05.200946 Set Vref, RX VrefLevel [Byte0]: 58
4629 11:41:05.204642 [Byte1]: 53
4630 11:41:05.208651
4631 11:41:05.208731 Final RX Vref Byte 0 = 58 to rank0
4632 11:41:05.212325 Final RX Vref Byte 1 = 53 to rank0
4633 11:41:05.215825 Final RX Vref Byte 0 = 58 to rank1
4634 11:41:05.219213 Final RX Vref Byte 1 = 53 to rank1==
4635 11:41:05.221998 Dram Type= 6, Freq= 0, CH_1, rank 0
4636 11:41:05.229096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 11:41:05.229193 ==
4638 11:41:05.229272 DQS Delay:
4639 11:41:05.229348 DQS0 = 0, DQS1 = 0
4640 11:41:05.232091 DQM Delay:
4641 11:41:05.232171 DQM0 = 41, DQM1 = 33
4642 11:41:05.235726 DQ Delay:
4643 11:41:05.238684 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4644 11:41:05.242287 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4645 11:41:05.245284 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4646 11:41:05.248886 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4647 11:41:05.248967
4648 11:41:05.249060
4649 11:41:05.255067 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4650 11:41:05.258719 CH1 RK0: MR19=808, MR18=3E04
4651 11:41:05.265182 CH1_RK0: MR19=0x808, MR18=0x3E04, DQSOSC=398, MR23=63, INC=165, DEC=110
4652 11:41:05.265288
4653 11:41:05.268166 ----->DramcWriteLeveling(PI) begin...
4654 11:41:05.268267 ==
4655 11:41:05.271634 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 11:41:05.274961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 11:41:05.275064 ==
4658 11:41:05.278547 Write leveling (Byte 0): 32 => 32
4659 11:41:05.282103 Write leveling (Byte 1): 32 => 32
4660 11:41:05.285389 DramcWriteLeveling(PI) end<-----
4661 11:41:05.285463
4662 11:41:05.285523 ==
4663 11:41:05.288427 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 11:41:05.291327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 11:41:05.295069 ==
4666 11:41:05.295171 [Gating] SW mode calibration
4667 11:41:05.301466 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4668 11:41:05.308008 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4669 11:41:05.311458 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 11:41:05.318333 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4671 11:41:05.321249 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4672 11:41:05.324586 0 9 12 | B1->B0 | 3131 2d2d | 0 1 | (0 0) (1 0)
4673 11:41:05.331136 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4674 11:41:05.334834 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 11:41:05.337752 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 11:41:05.344923 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4677 11:41:05.347869 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 11:41:05.351386 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 11:41:05.358149 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4680 11:41:05.360901 0 10 12 | B1->B0 | 3232 3e3e | 0 0 | (1 1) (0 0)
4681 11:41:05.364477 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4682 11:41:05.371160 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:41:05.374595 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 11:41:05.378009 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 11:41:05.381012 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 11:41:05.387665 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 11:41:05.391470 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4688 11:41:05.394628 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4689 11:41:05.400990 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:41:05.404153 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:41:05.407895 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:41:05.414427 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:41:05.417343 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:41:05.421125 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:41:05.427659 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:41:05.431144 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:41:05.434067 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:41:05.440529 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:41:05.444172 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:41:05.447222 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:41:05.453714 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:41:05.457226 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:41:05.460804 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4704 11:41:05.467631 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4705 11:41:05.467711 Total UI for P1: 0, mck2ui 16
4706 11:41:05.474023 best dqsien dly found for B0: ( 0, 13, 8)
4707 11:41:05.477572 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 11:41:05.480466 Total UI for P1: 0, mck2ui 16
4709 11:41:05.483716 best dqsien dly found for B1: ( 0, 13, 12)
4710 11:41:05.487170 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4711 11:41:05.490238 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4712 11:41:05.490331
4713 11:41:05.493689 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4714 11:41:05.497124 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4715 11:41:05.500576 [Gating] SW calibration Done
4716 11:41:05.500666 ==
4717 11:41:05.503839 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 11:41:05.507180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 11:41:05.510372 ==
4720 11:41:05.510461 RX Vref Scan: 0
4721 11:41:05.510526
4722 11:41:05.513653 RX Vref 0 -> 0, step: 1
4723 11:41:05.513741
4724 11:41:05.516977 RX Delay -230 -> 252, step: 16
4725 11:41:05.520201 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4726 11:41:05.523461 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4727 11:41:05.527362 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4728 11:41:05.533617 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4729 11:41:05.536885 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4730 11:41:05.540181 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4731 11:41:05.543813 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4732 11:41:05.546748 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4733 11:41:05.553269 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4734 11:41:05.556857 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4735 11:41:05.560384 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4736 11:41:05.563306 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4737 11:41:05.570412 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4738 11:41:05.573347 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4739 11:41:05.576980 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4740 11:41:05.579896 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4741 11:41:05.579979 ==
4742 11:41:05.583511 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 11:41:05.590016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 11:41:05.590101 ==
4745 11:41:05.590208 DQS Delay:
4746 11:41:05.593028 DQS0 = 0, DQS1 = 0
4747 11:41:05.593109 DQM Delay:
4748 11:41:05.593173 DQM0 = 43, DQM1 = 36
4749 11:41:05.596536 DQ Delay:
4750 11:41:05.600109 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4751 11:41:05.603504 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4752 11:41:05.606691 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4753 11:41:05.609683 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4754 11:41:05.609756
4755 11:41:05.609845
4756 11:41:05.609922 ==
4757 11:41:05.613215 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 11:41:05.616509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 11:41:05.616591 ==
4760 11:41:05.616655
4761 11:41:05.616714
4762 11:41:05.620077 TX Vref Scan disable
4763 11:41:05.623455 == TX Byte 0 ==
4764 11:41:05.626467 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4765 11:41:05.629886 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4766 11:41:05.633459 == TX Byte 1 ==
4767 11:41:05.636613 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4768 11:41:05.639772 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4769 11:41:05.639855 ==
4770 11:41:05.643061 Dram Type= 6, Freq= 0, CH_1, rank 1
4771 11:41:05.646388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4772 11:41:05.646475 ==
4773 11:41:05.649383
4774 11:41:05.649466
4775 11:41:05.649530 TX Vref Scan disable
4776 11:41:05.653572 == TX Byte 0 ==
4777 11:41:05.656706 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4778 11:41:05.663232 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4779 11:41:05.663314 == TX Byte 1 ==
4780 11:41:05.666806 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4781 11:41:05.673148 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4782 11:41:05.673231
4783 11:41:05.673295 [DATLAT]
4784 11:41:05.673355 Freq=600, CH1 RK1
4785 11:41:05.673412
4786 11:41:05.676688 DATLAT Default: 0x9
4787 11:41:05.676770 0, 0xFFFF, sum = 0
4788 11:41:05.679610 1, 0xFFFF, sum = 0
4789 11:41:05.683232 2, 0xFFFF, sum = 0
4790 11:41:05.683316 3, 0xFFFF, sum = 0
4791 11:41:05.686121 4, 0xFFFF, sum = 0
4792 11:41:05.686205 5, 0xFFFF, sum = 0
4793 11:41:05.689534 6, 0xFFFF, sum = 0
4794 11:41:05.689641 7, 0xFFFF, sum = 0
4795 11:41:05.693072 8, 0x0, sum = 1
4796 11:41:05.693164 9, 0x0, sum = 2
4797 11:41:05.693251 10, 0x0, sum = 3
4798 11:41:05.695987 11, 0x0, sum = 4
4799 11:41:05.696071 best_step = 9
4800 11:41:05.696135
4801 11:41:05.699562 ==
4802 11:41:05.699645 Dram Type= 6, Freq= 0, CH_1, rank 1
4803 11:41:05.706030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4804 11:41:05.706115 ==
4805 11:41:05.706181 RX Vref Scan: 0
4806 11:41:05.706243
4807 11:41:05.709895 RX Vref 0 -> 0, step: 1
4808 11:41:05.709978
4809 11:41:05.712947 RX Delay -179 -> 252, step: 8
4810 11:41:05.716016 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4811 11:41:05.722691 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4812 11:41:05.726328 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4813 11:41:05.729726 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4814 11:41:05.733084 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4815 11:41:05.739564 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4816 11:41:05.743114 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4817 11:41:05.746263 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4818 11:41:05.749092 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4819 11:41:05.752965 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4820 11:41:05.759617 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4821 11:41:05.762615 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4822 11:41:05.766179 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4823 11:41:05.769088 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4824 11:41:05.776168 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4825 11:41:05.779162 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4826 11:41:05.779245 ==
4827 11:41:05.782736 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 11:41:05.786244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 11:41:05.786328 ==
4830 11:41:05.789216 DQS Delay:
4831 11:41:05.789348 DQS0 = 0, DQS1 = 0
4832 11:41:05.789415 DQM Delay:
4833 11:41:05.792210 DQM0 = 39, DQM1 = 32
4834 11:41:05.792294 DQ Delay:
4835 11:41:05.795613 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4836 11:41:05.799221 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4837 11:41:05.802825 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4838 11:41:05.805750 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4839 11:41:05.805833
4840 11:41:05.805897
4841 11:41:05.815993 [DQSOSCAuto] RK1, (LSB)MR18= 0x3745, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4842 11:41:05.819069 CH1 RK1: MR19=808, MR18=3745
4843 11:41:05.822317 CH1_RK1: MR19=0x808, MR18=0x3745, DQSOSC=396, MR23=63, INC=167, DEC=111
4844 11:41:05.825520 [RxdqsGatingPostProcess] freq 600
4845 11:41:05.832415 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4846 11:41:05.835935 Pre-setting of DQS Precalculation
4847 11:41:05.839334 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4848 11:41:05.849165 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4849 11:41:05.855554 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4850 11:41:05.855667
4851 11:41:05.855777
4852 11:41:05.858840 [Calibration Summary] 1200 Mbps
4853 11:41:05.858938 CH 0, Rank 0
4854 11:41:05.862253 SW Impedance : PASS
4855 11:41:05.862351 DUTY Scan : NO K
4856 11:41:05.865422 ZQ Calibration : PASS
4857 11:41:05.868951 Jitter Meter : NO K
4858 11:41:05.869033 CBT Training : PASS
4859 11:41:05.871895 Write leveling : PASS
4860 11:41:05.875541 RX DQS gating : PASS
4861 11:41:05.875640 RX DQ/DQS(RDDQC) : PASS
4862 11:41:05.879019 TX DQ/DQS : PASS
4863 11:41:05.879118 RX DATLAT : PASS
4864 11:41:05.881869 RX DQ/DQS(Engine): PASS
4865 11:41:05.885575 TX OE : NO K
4866 11:41:05.885703 All Pass.
4867 11:41:05.885809
4868 11:41:05.885908 CH 0, Rank 1
4869 11:41:05.888548 SW Impedance : PASS
4870 11:41:05.892148 DUTY Scan : NO K
4871 11:41:05.892246 ZQ Calibration : PASS
4872 11:41:05.895658 Jitter Meter : NO K
4873 11:41:05.898985 CBT Training : PASS
4874 11:41:05.899082 Write leveling : PASS
4875 11:41:05.902186 RX DQS gating : PASS
4876 11:41:05.905265 RX DQ/DQS(RDDQC) : PASS
4877 11:41:05.905371 TX DQ/DQS : PASS
4878 11:41:05.908810 RX DATLAT : PASS
4879 11:41:05.912265 RX DQ/DQS(Engine): PASS
4880 11:41:05.912384 TX OE : NO K
4881 11:41:05.915283 All Pass.
4882 11:41:05.915389
4883 11:41:05.915489 CH 1, Rank 0
4884 11:41:05.918970 SW Impedance : PASS
4885 11:41:05.919053 DUTY Scan : NO K
4886 11:41:05.922223 ZQ Calibration : PASS
4887 11:41:05.925093 Jitter Meter : NO K
4888 11:41:05.925190 CBT Training : PASS
4889 11:41:05.928596 Write leveling : PASS
4890 11:41:05.931801 RX DQS gating : PASS
4891 11:41:05.931931 RX DQ/DQS(RDDQC) : PASS
4892 11:41:05.935079 TX DQ/DQS : PASS
4893 11:41:05.935180 RX DATLAT : PASS
4894 11:41:05.939029 RX DQ/DQS(Engine): PASS
4895 11:41:05.942032 TX OE : NO K
4896 11:41:05.942130 All Pass.
4897 11:41:05.942209
4898 11:41:05.942284 CH 1, Rank 1
4899 11:41:05.945333 SW Impedance : PASS
4900 11:41:05.948318 DUTY Scan : NO K
4901 11:41:05.948416 ZQ Calibration : PASS
4902 11:41:05.951687 Jitter Meter : NO K
4903 11:41:05.955094 CBT Training : PASS
4904 11:41:05.955191 Write leveling : PASS
4905 11:41:05.959100 RX DQS gating : PASS
4906 11:41:05.961891 RX DQ/DQS(RDDQC) : PASS
4907 11:41:05.961988 TX DQ/DQS : PASS
4908 11:41:05.965279 RX DATLAT : PASS
4909 11:41:05.968621 RX DQ/DQS(Engine): PASS
4910 11:41:05.968719 TX OE : NO K
4911 11:41:05.971644 All Pass.
4912 11:41:05.971743
4913 11:41:05.971839 DramC Write-DBI off
4914 11:41:05.975218 PER_BANK_REFRESH: Hybrid Mode
4915 11:41:05.975302 TX_TRACKING: ON
4916 11:41:05.985317 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4917 11:41:05.988266 [FAST_K] Save calibration result to emmc
4918 11:41:05.991818 dramc_set_vcore_voltage set vcore to 662500
4919 11:41:05.994787 Read voltage for 933, 3
4920 11:41:05.994874 Vio18 = 0
4921 11:41:05.998305 Vcore = 662500
4922 11:41:05.998388 Vdram = 0
4923 11:41:05.998453 Vddq = 0
4924 11:41:05.998513 Vmddr = 0
4925 11:41:06.004601 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4926 11:41:06.011103 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4927 11:41:06.011187 MEM_TYPE=3, freq_sel=17
4928 11:41:06.014804 sv_algorithm_assistance_LP4_1600
4929 11:41:06.021225 ============ PULL DRAM RESETB DOWN ============
4930 11:41:06.024765 ========== PULL DRAM RESETB DOWN end =========
4931 11:41:06.027788 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4932 11:41:06.031296 ===================================
4933 11:41:06.034493 LPDDR4 DRAM CONFIGURATION
4934 11:41:06.037655 ===================================
4935 11:41:06.037739 EX_ROW_EN[0] = 0x0
4936 11:41:06.040890 EX_ROW_EN[1] = 0x0
4937 11:41:06.044220 LP4Y_EN = 0x0
4938 11:41:06.044304 WORK_FSP = 0x0
4939 11:41:06.047901 WL = 0x3
4940 11:41:06.048002 RL = 0x3
4941 11:41:06.051034 BL = 0x2
4942 11:41:06.051119 RPST = 0x0
4943 11:41:06.054224 RD_PRE = 0x0
4944 11:41:06.054308 WR_PRE = 0x1
4945 11:41:06.058009 WR_PST = 0x0
4946 11:41:06.058094 DBI_WR = 0x0
4947 11:41:06.060674 DBI_RD = 0x0
4948 11:41:06.060767 OTF = 0x1
4949 11:41:06.064171 ===================================
4950 11:41:06.067297 ===================================
4951 11:41:06.070747 ANA top config
4952 11:41:06.074145 ===================================
4953 11:41:06.074249 DLL_ASYNC_EN = 0
4954 11:41:06.077684 ALL_SLAVE_EN = 1
4955 11:41:06.080920 NEW_RANK_MODE = 1
4956 11:41:06.084278 DLL_IDLE_MODE = 1
4957 11:41:06.087756 LP45_APHY_COMB_EN = 1
4958 11:41:06.087828 TX_ODT_DIS = 1
4959 11:41:06.090691 NEW_8X_MODE = 1
4960 11:41:06.094249 ===================================
4961 11:41:06.097239 ===================================
4962 11:41:06.100848 data_rate = 1866
4963 11:41:06.104132 CKR = 1
4964 11:41:06.107276 DQ_P2S_RATIO = 8
4965 11:41:06.110464 ===================================
4966 11:41:06.110566 CA_P2S_RATIO = 8
4967 11:41:06.114000 DQ_CA_OPEN = 0
4968 11:41:06.117591 DQ_SEMI_OPEN = 0
4969 11:41:06.120558 CA_SEMI_OPEN = 0
4970 11:41:06.124011 CA_FULL_RATE = 0
4971 11:41:06.126951 DQ_CKDIV4_EN = 1
4972 11:41:06.130592 CA_CKDIV4_EN = 1
4973 11:41:06.130670 CA_PREDIV_EN = 0
4974 11:41:06.133551 PH8_DLY = 0
4975 11:41:06.137351 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4976 11:41:06.140355 DQ_AAMCK_DIV = 4
4977 11:41:06.143789 CA_AAMCK_DIV = 4
4978 11:41:06.147071 CA_ADMCK_DIV = 4
4979 11:41:06.147169 DQ_TRACK_CA_EN = 0
4980 11:41:06.150466 CA_PICK = 933
4981 11:41:06.153655 CA_MCKIO = 933
4982 11:41:06.156952 MCKIO_SEMI = 0
4983 11:41:06.160244 PLL_FREQ = 3732
4984 11:41:06.163644 DQ_UI_PI_RATIO = 32
4985 11:41:06.166706 CA_UI_PI_RATIO = 0
4986 11:41:06.169950 ===================================
4987 11:41:06.173796 ===================================
4988 11:41:06.173879 memory_type:LPDDR4
4989 11:41:06.176996 GP_NUM : 10
4990 11:41:06.180451 SRAM_EN : 1
4991 11:41:06.180534 MD32_EN : 0
4992 11:41:06.183415 ===================================
4993 11:41:06.186950 [ANA_INIT] >>>>>>>>>>>>>>
4994 11:41:06.190023 <<<<<< [CONFIGURE PHASE]: ANA_TX
4995 11:41:06.193359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4996 11:41:06.196436 ===================================
4997 11:41:06.199894 data_rate = 1866,PCW = 0X8f00
4998 11:41:06.202957 ===================================
4999 11:41:06.206573 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5000 11:41:06.209810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 11:41:06.216242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5002 11:41:06.219920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5003 11:41:06.222803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5004 11:41:06.226291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5005 11:41:06.229798 [ANA_INIT] flow start
5006 11:41:06.233246 [ANA_INIT] PLL >>>>>>>>
5007 11:41:06.233351 [ANA_INIT] PLL <<<<<<<<
5008 11:41:06.236227 [ANA_INIT] MIDPI >>>>>>>>
5009 11:41:06.239787 [ANA_INIT] MIDPI <<<<<<<<
5010 11:41:06.239892 [ANA_INIT] DLL >>>>>>>>
5011 11:41:06.242790 [ANA_INIT] flow end
5012 11:41:06.246394 ============ LP4 DIFF to SE enter ============
5013 11:41:06.253111 ============ LP4 DIFF to SE exit ============
5014 11:41:06.253219 [ANA_INIT] <<<<<<<<<<<<<
5015 11:41:06.256671 [Flow] Enable top DCM control >>>>>
5016 11:41:06.259930 [Flow] Enable top DCM control <<<<<
5017 11:41:06.262864 Enable DLL master slave shuffle
5018 11:41:06.269719 ==============================================================
5019 11:41:06.269826 Gating Mode config
5020 11:41:06.276340 ==============================================================
5021 11:41:06.279855 Config description:
5022 11:41:06.285980 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5023 11:41:06.292614 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5024 11:41:06.299488 SELPH_MODE 0: By rank 1: By Phase
5025 11:41:06.306021 ==============================================================
5026 11:41:06.306126 GAT_TRACK_EN = 1
5027 11:41:06.309663 RX_GATING_MODE = 2
5028 11:41:06.312460 RX_GATING_TRACK_MODE = 2
5029 11:41:06.315762 SELPH_MODE = 1
5030 11:41:06.319163 PICG_EARLY_EN = 1
5031 11:41:06.322719 VALID_LAT_VALUE = 1
5032 11:41:06.329263 ==============================================================
5033 11:41:06.332767 Enter into Gating configuration >>>>
5034 11:41:06.335954 Exit from Gating configuration <<<<
5035 11:41:06.338970 Enter into DVFS_PRE_config >>>>>
5036 11:41:06.349107 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5037 11:41:06.352723 Exit from DVFS_PRE_config <<<<<
5038 11:41:06.355979 Enter into PICG configuration >>>>
5039 11:41:06.359207 Exit from PICG configuration <<<<
5040 11:41:06.362438 [RX_INPUT] configuration >>>>>
5041 11:41:06.365502 [RX_INPUT] configuration <<<<<
5042 11:41:06.368941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5043 11:41:06.375850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5044 11:41:06.382601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5045 11:41:06.385362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5046 11:41:06.392187 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5047 11:41:06.399091 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5048 11:41:06.401942 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5049 11:41:06.405543 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5050 11:41:06.412305 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5051 11:41:06.415245 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5052 11:41:06.418751 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5053 11:41:06.425364 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 11:41:06.428952 ===================================
5055 11:41:06.429049 LPDDR4 DRAM CONFIGURATION
5056 11:41:06.431951 ===================================
5057 11:41:06.435484 EX_ROW_EN[0] = 0x0
5058 11:41:06.438891 EX_ROW_EN[1] = 0x0
5059 11:41:06.438988 LP4Y_EN = 0x0
5060 11:41:06.441927 WORK_FSP = 0x0
5061 11:41:06.442028 WL = 0x3
5062 11:41:06.445507 RL = 0x3
5063 11:41:06.445620 BL = 0x2
5064 11:41:06.448423 RPST = 0x0
5065 11:41:06.448535 RD_PRE = 0x0
5066 11:41:06.451898 WR_PRE = 0x1
5067 11:41:06.452010 WR_PST = 0x0
5068 11:41:06.455344 DBI_WR = 0x0
5069 11:41:06.455445 DBI_RD = 0x0
5070 11:41:06.458852 OTF = 0x1
5071 11:41:06.462010 ===================================
5072 11:41:06.465784 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5073 11:41:06.468838 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5074 11:41:06.475310 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 11:41:06.478706 ===================================
5076 11:41:06.478785 LPDDR4 DRAM CONFIGURATION
5077 11:41:06.482062 ===================================
5078 11:41:06.485353 EX_ROW_EN[0] = 0x10
5079 11:41:06.485439 EX_ROW_EN[1] = 0x0
5080 11:41:06.488533 LP4Y_EN = 0x0
5081 11:41:06.488635 WORK_FSP = 0x0
5082 11:41:06.491888 WL = 0x3
5083 11:41:06.492022 RL = 0x3
5084 11:41:06.495176 BL = 0x2
5085 11:41:06.498976 RPST = 0x0
5086 11:41:06.499082 RD_PRE = 0x0
5087 11:41:06.501603 WR_PRE = 0x1
5088 11:41:06.501705 WR_PST = 0x0
5089 11:41:06.505025 DBI_WR = 0x0
5090 11:41:06.505130 DBI_RD = 0x0
5091 11:41:06.508526 OTF = 0x1
5092 11:41:06.512139 ===================================
5093 11:41:06.514960 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5094 11:41:06.520391 nWR fixed to 30
5095 11:41:06.523855 [ModeRegInit_LP4] CH0 RK0
5096 11:41:06.523937 [ModeRegInit_LP4] CH0 RK1
5097 11:41:06.527285 [ModeRegInit_LP4] CH1 RK0
5098 11:41:06.530866 [ModeRegInit_LP4] CH1 RK1
5099 11:41:06.530974 match AC timing 9
5100 11:41:06.537413 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5101 11:41:06.540880 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5102 11:41:06.543703 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5103 11:41:06.550264 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5104 11:41:06.553893 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5105 11:41:06.553995 ==
5106 11:41:06.557418 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 11:41:06.560350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 11:41:06.560450 ==
5109 11:41:06.567257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 11:41:06.573678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5111 11:41:06.577250 [CA 0] Center 38 (8~69) winsize 62
5112 11:41:06.580591 [CA 1] Center 37 (7~68) winsize 62
5113 11:41:06.583545 [CA 2] Center 35 (5~66) winsize 62
5114 11:41:06.586885 [CA 3] Center 34 (4~65) winsize 62
5115 11:41:06.590228 [CA 4] Center 34 (4~64) winsize 61
5116 11:41:06.593432 [CA 5] Center 34 (4~64) winsize 61
5117 11:41:06.593517
5118 11:41:06.596697 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5119 11:41:06.596780
5120 11:41:06.600081 [CATrainingPosCal] consider 1 rank data
5121 11:41:06.603444 u2DelayCellTimex100 = 270/100 ps
5122 11:41:06.607107 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5123 11:41:06.609995 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5124 11:41:06.613490 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5125 11:41:06.617140 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5126 11:41:06.620145 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5127 11:41:06.626671 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5128 11:41:06.626755
5129 11:41:06.630177 CA PerBit enable=1, Macro0, CA PI delay=34
5130 11:41:06.630261
5131 11:41:06.633029 [CBTSetCACLKResult] CA Dly = 34
5132 11:41:06.633114 CS Dly: 6 (0~37)
5133 11:41:06.633182 ==
5134 11:41:06.636605 Dram Type= 6, Freq= 0, CH_0, rank 1
5135 11:41:06.640296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 11:41:06.643215 ==
5137 11:41:06.646644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5138 11:41:06.653151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5139 11:41:06.656549 [CA 0] Center 38 (7~69) winsize 63
5140 11:41:06.660165 [CA 1] Center 38 (7~69) winsize 63
5141 11:41:06.663094 [CA 2] Center 35 (5~66) winsize 62
5142 11:41:06.666546 [CA 3] Center 35 (4~66) winsize 63
5143 11:41:06.670149 [CA 4] Center 34 (3~65) winsize 63
5144 11:41:06.673176 [CA 5] Center 33 (3~64) winsize 62
5145 11:41:06.673260
5146 11:41:06.676607 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5147 11:41:06.676690
5148 11:41:06.680081 [CATrainingPosCal] consider 2 rank data
5149 11:41:06.683510 u2DelayCellTimex100 = 270/100 ps
5150 11:41:06.686365 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5151 11:41:06.689683 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5152 11:41:06.692845 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5153 11:41:06.696055 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5154 11:41:06.702816 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5155 11:41:06.706110 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5156 11:41:06.706194
5157 11:41:06.709429 CA PerBit enable=1, Macro0, CA PI delay=34
5158 11:41:06.709514
5159 11:41:06.712936 [CBTSetCACLKResult] CA Dly = 34
5160 11:41:06.713020 CS Dly: 7 (0~39)
5161 11:41:06.713085
5162 11:41:06.716435 ----->DramcWriteLeveling(PI) begin...
5163 11:41:06.716519 ==
5164 11:41:06.719425 Dram Type= 6, Freq= 0, CH_0, rank 0
5165 11:41:06.726410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5166 11:41:06.726495 ==
5167 11:41:06.729369 Write leveling (Byte 0): 29 => 29
5168 11:41:06.729453 Write leveling (Byte 1): 27 => 27
5169 11:41:06.732980 DramcWriteLeveling(PI) end<-----
5170 11:41:06.733063
5171 11:41:06.736276 ==
5172 11:41:06.736359 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 11:41:06.742882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 11:41:06.742965 ==
5175 11:41:06.746357 [Gating] SW mode calibration
5176 11:41:06.752665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5177 11:41:06.756246 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5178 11:41:06.762521 0 14 0 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
5179 11:41:06.765910 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5180 11:41:06.769496 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 11:41:06.776448 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 11:41:06.779376 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 11:41:06.782965 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 11:41:06.789695 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 11:41:06.793075 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
5186 11:41:06.796382 0 15 0 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (0 0)
5187 11:41:06.802563 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5188 11:41:06.805820 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 11:41:06.809125 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 11:41:06.815848 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 11:41:06.819248 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 11:41:06.822657 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 11:41:06.826225 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 11:41:06.832773 1 0 0 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
5195 11:41:06.835840 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 11:41:06.839334 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 11:41:06.845901 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:41:06.848888 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 11:41:06.852291 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 11:41:06.859353 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 11:41:06.862293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5202 11:41:06.865804 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5203 11:41:06.872695 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5204 11:41:06.875795 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:41:06.879032 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:41:06.885817 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:41:06.888892 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:41:06.892327 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:41:06.898698 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:41:06.902492 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:41:06.905417 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:41:06.912387 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:41:06.916052 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:41:06.918988 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:41:06.925498 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:41:06.928955 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:41:06.932484 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5218 11:41:06.939093 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 11:41:06.939207 Total UI for P1: 0, mck2ui 16
5220 11:41:06.942483 best dqsien dly found for B0: ( 1, 2, 28)
5221 11:41:06.945328 Total UI for P1: 0, mck2ui 16
5222 11:41:06.948912 best dqsien dly found for B1: ( 1, 2, 28)
5223 11:41:06.955381 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5224 11:41:06.958719 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5225 11:41:06.958817
5226 11:41:06.962146 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5227 11:41:06.965525 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5228 11:41:06.968499 [Gating] SW calibration Done
5229 11:41:06.968581 ==
5230 11:41:06.972117 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 11:41:06.975579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 11:41:06.975662 ==
5233 11:41:06.978460 RX Vref Scan: 0
5234 11:41:06.978541
5235 11:41:06.978605 RX Vref 0 -> 0, step: 1
5236 11:41:06.978666
5237 11:41:06.981853 RX Delay -80 -> 252, step: 8
5238 11:41:06.985446 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5239 11:41:06.991867 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5240 11:41:06.994710 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5241 11:41:06.998260 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5242 11:41:07.001775 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5243 11:41:07.004952 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5244 11:41:07.008044 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5245 11:41:07.014724 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5246 11:41:07.018012 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5247 11:41:07.021686 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5248 11:41:07.025063 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5249 11:41:07.028137 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5250 11:41:07.031640 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5251 11:41:07.037868 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5252 11:41:07.041540 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5253 11:41:07.045001 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5254 11:41:07.045120 ==
5255 11:41:07.048500 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 11:41:07.051406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 11:41:07.051492 ==
5258 11:41:07.054988 DQS Delay:
5259 11:41:07.055070 DQS0 = 0, DQS1 = 0
5260 11:41:07.057995 DQM Delay:
5261 11:41:07.058077 DQM0 = 98, DQM1 = 87
5262 11:41:07.058141 DQ Delay:
5263 11:41:07.061610 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =95
5264 11:41:07.064889 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5265 11:41:07.068339 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5266 11:41:07.071380 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5267 11:41:07.071492
5268 11:41:07.071596
5269 11:41:07.075047 ==
5270 11:41:07.078134 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:41:07.081723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:41:07.081804 ==
5273 11:41:07.081896
5274 11:41:07.081972
5275 11:41:07.084581 TX Vref Scan disable
5276 11:41:07.084670 == TX Byte 0 ==
5277 11:41:07.088224 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5278 11:41:07.094655 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5279 11:41:07.094742 == TX Byte 1 ==
5280 11:41:07.098215 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5281 11:41:07.104797 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5282 11:41:07.104872 ==
5283 11:41:07.107827 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 11:41:07.111316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:41:07.111452 ==
5286 11:41:07.111551
5287 11:41:07.111637
5288 11:41:07.114961 TX Vref Scan disable
5289 11:41:07.117978 == TX Byte 0 ==
5290 11:41:07.121279 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5291 11:41:07.124504 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5292 11:41:07.127674 == TX Byte 1 ==
5293 11:41:07.131040 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5294 11:41:07.134773 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5295 11:41:07.134852
5296 11:41:07.137743 [DATLAT]
5297 11:41:07.137814 Freq=933, CH0 RK0
5298 11:41:07.137882
5299 11:41:07.140898 DATLAT Default: 0xd
5300 11:41:07.140965 0, 0xFFFF, sum = 0
5301 11:41:07.144688 1, 0xFFFF, sum = 0
5302 11:41:07.144761 2, 0xFFFF, sum = 0
5303 11:41:07.147839 3, 0xFFFF, sum = 0
5304 11:41:07.147921 4, 0xFFFF, sum = 0
5305 11:41:07.151241 5, 0xFFFF, sum = 0
5306 11:41:07.151388 6, 0xFFFF, sum = 0
5307 11:41:07.154904 7, 0xFFFF, sum = 0
5308 11:41:07.154986 8, 0xFFFF, sum = 0
5309 11:41:07.157774 9, 0xFFFF, sum = 0
5310 11:41:07.157849 10, 0x0, sum = 1
5311 11:41:07.161410 11, 0x0, sum = 2
5312 11:41:07.161482 12, 0x0, sum = 3
5313 11:41:07.164345 13, 0x0, sum = 4
5314 11:41:07.164422 best_step = 11
5315 11:41:07.164480
5316 11:41:07.164536 ==
5317 11:41:07.168093 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 11:41:07.171217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 11:41:07.174168 ==
5320 11:41:07.174271 RX Vref Scan: 1
5321 11:41:07.174330
5322 11:41:07.177653 RX Vref 0 -> 0, step: 1
5323 11:41:07.177724
5324 11:41:07.181133 RX Delay -61 -> 252, step: 4
5325 11:41:07.181203
5326 11:41:07.184294 Set Vref, RX VrefLevel [Byte0]: 54
5327 11:41:07.187662 [Byte1]: 51
5328 11:41:07.187736
5329 11:41:07.191137 Final RX Vref Byte 0 = 54 to rank0
5330 11:41:07.194072 Final RX Vref Byte 1 = 51 to rank0
5331 11:41:07.197570 Final RX Vref Byte 0 = 54 to rank1
5332 11:41:07.201148 Final RX Vref Byte 1 = 51 to rank1==
5333 11:41:07.204031 Dram Type= 6, Freq= 0, CH_0, rank 0
5334 11:41:07.207566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 11:41:07.207678 ==
5336 11:41:07.211174 DQS Delay:
5337 11:41:07.211279 DQS0 = 0, DQS1 = 0
5338 11:41:07.211386 DQM Delay:
5339 11:41:07.214365 DQM0 = 97, DQM1 = 88
5340 11:41:07.214433 DQ Delay:
5341 11:41:07.217328 DQ0 =96, DQ1 =100, DQ2 =94, DQ3 =94
5342 11:41:07.220562 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =102
5343 11:41:07.224172 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5344 11:41:07.227720 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =98
5345 11:41:07.227818
5346 11:41:07.227883
5347 11:41:07.237756 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5348 11:41:07.237872 CH0 RK0: MR19=504, MR18=12FD
5349 11:41:07.244226 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5350 11:41:07.244311
5351 11:41:07.247297 ----->DramcWriteLeveling(PI) begin...
5352 11:41:07.250551 ==
5353 11:41:07.250632 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 11:41:07.257383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 11:41:07.257459 ==
5356 11:41:07.260907 Write leveling (Byte 0): 32 => 32
5357 11:41:07.263915 Write leveling (Byte 1): 31 => 31
5358 11:41:07.263985 DramcWriteLeveling(PI) end<-----
5359 11:41:07.267455
5360 11:41:07.267531 ==
5361 11:41:07.270807 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 11:41:07.274222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 11:41:07.274299 ==
5364 11:41:07.277566 [Gating] SW mode calibration
5365 11:41:07.284005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5366 11:41:07.287443 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5367 11:41:07.293963 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5368 11:41:07.297887 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5369 11:41:07.301137 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 11:41:07.307795 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 11:41:07.310821 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 11:41:07.314398 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 11:41:07.321100 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 11:41:07.324018 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
5375 11:41:07.327503 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5376 11:41:07.334194 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 11:41:07.337188 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 11:41:07.340826 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 11:41:07.347733 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 11:41:07.350995 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 11:41:07.354022 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 11:41:07.361008 0 15 28 | B1->B0 | 2b2b 3636 | 0 1 | (1 1) (0 0)
5383 11:41:07.364337 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5384 11:41:07.367274 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:41:07.371079 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 11:41:07.377456 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 11:41:07.380921 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:41:07.383789 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 11:41:07.390881 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 11:41:07.393921 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5391 11:41:07.397451 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5392 11:41:07.403977 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 11:41:07.407217 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:41:07.410541 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:41:07.417068 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:41:07.420473 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:41:07.423489 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:41:07.430429 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:41:07.434040 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:41:07.436768 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:41:07.443828 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:41:07.446722 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:41:07.450489 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:41:07.456889 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5405 11:41:07.460209 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5406 11:41:07.463520 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5407 11:41:07.466795 Total UI for P1: 0, mck2ui 16
5408 11:41:07.469970 best dqsien dly found for B0: ( 1, 2, 22)
5409 11:41:07.477094 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5410 11:41:07.480193 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5411 11:41:07.483480 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 11:41:07.486714 Total UI for P1: 0, mck2ui 16
5413 11:41:07.490339 best dqsien dly found for B1: ( 1, 3, 0)
5414 11:41:07.493268 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5415 11:41:07.496899 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5416 11:41:07.496982
5417 11:41:07.500377 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5418 11:41:07.506965 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5419 11:41:07.507048 [Gating] SW calibration Done
5420 11:41:07.507113 ==
5421 11:41:07.509828 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 11:41:07.516466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 11:41:07.516549 ==
5424 11:41:07.516614 RX Vref Scan: 0
5425 11:41:07.516675
5426 11:41:07.520005 RX Vref 0 -> 0, step: 1
5427 11:41:07.520087
5428 11:41:07.523530 RX Delay -80 -> 252, step: 8
5429 11:41:07.526441 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5430 11:41:07.529764 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5431 11:41:07.533378 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5432 11:41:07.536320 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5433 11:41:07.543257 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5434 11:41:07.546763 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5435 11:41:07.549698 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5436 11:41:07.552982 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5437 11:41:07.556302 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5438 11:41:07.559634 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5439 11:41:07.566961 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5440 11:41:07.569665 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5441 11:41:07.572958 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5442 11:41:07.576500 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5443 11:41:07.579709 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5444 11:41:07.586636 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5445 11:41:07.586719 ==
5446 11:41:07.589958 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 11:41:07.592939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 11:41:07.593023 ==
5449 11:41:07.593088 DQS Delay:
5450 11:41:07.596501 DQS0 = 0, DQS1 = 0
5451 11:41:07.596583 DQM Delay:
5452 11:41:07.599498 DQM0 = 98, DQM1 = 87
5453 11:41:07.599581 DQ Delay:
5454 11:41:07.603095 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5455 11:41:07.606352 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5456 11:41:07.609388 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5457 11:41:07.613043 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5458 11:41:07.613125
5459 11:41:07.613190
5460 11:41:07.613249 ==
5461 11:41:07.616081 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 11:41:07.619576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 11:41:07.619662 ==
5464 11:41:07.619727
5465 11:41:07.623469
5466 11:41:07.623550 TX Vref Scan disable
5467 11:41:07.626096 == TX Byte 0 ==
5468 11:41:07.629576 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5469 11:41:07.633058 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5470 11:41:07.636021 == TX Byte 1 ==
5471 11:41:07.639553 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5472 11:41:07.642457 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5473 11:41:07.642539 ==
5474 11:41:07.645901 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 11:41:07.652825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 11:41:07.652907 ==
5477 11:41:07.652972
5478 11:41:07.653031
5479 11:41:07.653089 TX Vref Scan disable
5480 11:41:07.657057 == TX Byte 0 ==
5481 11:41:07.660060 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5482 11:41:07.666541 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5483 11:41:07.666624 == TX Byte 1 ==
5484 11:41:07.670579 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5485 11:41:07.676502 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5486 11:41:07.676586
5487 11:41:07.676652 [DATLAT]
5488 11:41:07.676713 Freq=933, CH0 RK1
5489 11:41:07.676771
5490 11:41:07.679848 DATLAT Default: 0xb
5491 11:41:07.679931 0, 0xFFFF, sum = 0
5492 11:41:07.683029 1, 0xFFFF, sum = 0
5493 11:41:07.686678 2, 0xFFFF, sum = 0
5494 11:41:07.686763 3, 0xFFFF, sum = 0
5495 11:41:07.689990 4, 0xFFFF, sum = 0
5496 11:41:07.690075 5, 0xFFFF, sum = 0
5497 11:41:07.693118 6, 0xFFFF, sum = 0
5498 11:41:07.693203 7, 0xFFFF, sum = 0
5499 11:41:07.696915 8, 0xFFFF, sum = 0
5500 11:41:07.697033 9, 0xFFFF, sum = 0
5501 11:41:07.699888 10, 0x0, sum = 1
5502 11:41:07.700004 11, 0x0, sum = 2
5503 11:41:07.703267 12, 0x0, sum = 3
5504 11:41:07.703382 13, 0x0, sum = 4
5505 11:41:07.703451 best_step = 11
5506 11:41:07.706863
5507 11:41:07.706990 ==
5508 11:41:07.709701 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 11:41:07.713299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 11:41:07.713382 ==
5511 11:41:07.713447 RX Vref Scan: 0
5512 11:41:07.713507
5513 11:41:07.716377 RX Vref 0 -> 0, step: 1
5514 11:41:07.716503
5515 11:41:07.719855 RX Delay -61 -> 252, step: 4
5516 11:41:07.723312 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5517 11:41:07.729740 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5518 11:41:07.733384 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5519 11:41:07.736391 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5520 11:41:07.739821 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5521 11:41:07.742786 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5522 11:41:07.746351 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5523 11:41:07.753307 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5524 11:41:07.756087 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5525 11:41:07.759621 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5526 11:41:07.762966 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5527 11:41:07.766114 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5528 11:41:07.772712 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5529 11:41:07.776149 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5530 11:41:07.779804 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5531 11:41:07.782672 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5532 11:41:07.782756 ==
5533 11:41:07.786016 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 11:41:07.789296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 11:41:07.792621 ==
5536 11:41:07.792706 DQS Delay:
5537 11:41:07.792803 DQS0 = 0, DQS1 = 0
5538 11:41:07.796557 DQM Delay:
5539 11:41:07.796641 DQM0 = 95, DQM1 = 87
5540 11:41:07.799632 DQ Delay:
5541 11:41:07.802978 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5542 11:41:07.805911 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =104
5543 11:41:07.805992 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5544 11:41:07.812909 DQ12 =90, DQ13 =92, DQ14 =100, DQ15 =96
5545 11:41:07.813004
5546 11:41:07.813088
5547 11:41:07.819419 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a08, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5548 11:41:07.822427 CH0 RK1: MR19=505, MR18=1A08
5549 11:41:07.829546 CH0_RK1: MR19=0x505, MR18=0x1A08, DQSOSC=413, MR23=63, INC=63, DEC=42
5550 11:41:07.832553 [RxdqsGatingPostProcess] freq 933
5551 11:41:07.836131 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5552 11:41:07.839243 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 11:41:07.842597 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 11:41:07.846208 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 11:41:07.849133 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 11:41:07.852631 best DQS0 dly(2T, 0.5T) = (0, 10)
5557 11:41:07.855983 best DQS1 dly(2T, 0.5T) = (0, 11)
5558 11:41:07.859441 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5559 11:41:07.862437 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5560 11:41:07.865920 Pre-setting of DQS Precalculation
5561 11:41:07.869158 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5562 11:41:07.869246 ==
5563 11:41:07.872452 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 11:41:07.878991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 11:41:07.879073 ==
5566 11:41:07.882226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 11:41:07.888811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5568 11:41:07.892610 [CA 0] Center 36 (6~67) winsize 62
5569 11:41:07.895579 [CA 1] Center 36 (6~67) winsize 62
5570 11:41:07.899230 [CA 2] Center 34 (4~64) winsize 61
5571 11:41:07.902360 [CA 3] Center 34 (4~64) winsize 61
5572 11:41:07.905707 [CA 4] Center 34 (4~64) winsize 61
5573 11:41:07.909067 [CA 5] Center 33 (3~64) winsize 62
5574 11:41:07.909169
5575 11:41:07.911966 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5576 11:41:07.912063
5577 11:41:07.915556 [CATrainingPosCal] consider 1 rank data
5578 11:41:07.918585 u2DelayCellTimex100 = 270/100 ps
5579 11:41:07.922138 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 11:41:07.925867 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5581 11:41:07.931870 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5582 11:41:07.935329 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 11:41:07.939006 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5584 11:41:07.941927 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 11:41:07.942009
5586 11:41:07.945365 CA PerBit enable=1, Macro0, CA PI delay=33
5587 11:41:07.945447
5588 11:41:07.948219 [CBTSetCACLKResult] CA Dly = 33
5589 11:41:07.948300 CS Dly: 5 (0~36)
5590 11:41:07.951914 ==
5591 11:41:07.954893 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 11:41:07.958342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 11:41:07.958451 ==
5594 11:41:07.961773 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5595 11:41:07.968397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5596 11:41:07.971926 [CA 0] Center 36 (6~67) winsize 62
5597 11:41:07.975413 [CA 1] Center 37 (7~67) winsize 61
5598 11:41:07.978332 [CA 2] Center 33 (3~64) winsize 62
5599 11:41:07.981567 [CA 3] Center 33 (3~64) winsize 62
5600 11:41:07.984910 [CA 4] Center 34 (4~65) winsize 62
5601 11:41:07.988587 [CA 5] Center 32 (2~63) winsize 62
5602 11:41:07.988694
5603 11:41:07.991987 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5604 11:41:07.992125
5605 11:41:07.995005 [CATrainingPosCal] consider 2 rank data
5606 11:41:07.998591 u2DelayCellTimex100 = 270/100 ps
5607 11:41:08.001766 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 11:41:08.008163 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5609 11:41:08.011763 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5610 11:41:08.014959 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 11:41:08.018492 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5612 11:41:08.021848 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5613 11:41:08.021930
5614 11:41:08.024828 CA PerBit enable=1, Macro0, CA PI delay=33
5615 11:41:08.024911
5616 11:41:08.028491 [CBTSetCACLKResult] CA Dly = 33
5617 11:41:08.028573 CS Dly: 5 (0~37)
5618 11:41:08.031363
5619 11:41:08.034940 ----->DramcWriteLeveling(PI) begin...
5620 11:41:08.035024 ==
5621 11:41:08.038542 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 11:41:08.041552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 11:41:08.041636 ==
5624 11:41:08.045096 Write leveling (Byte 0): 25 => 25
5625 11:41:08.048608 Write leveling (Byte 1): 29 => 29
5626 11:41:08.051289 DramcWriteLeveling(PI) end<-----
5627 11:41:08.051427
5628 11:41:08.051492 ==
5629 11:41:08.054952 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 11:41:08.057986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 11:41:08.058069 ==
5632 11:41:08.061381 [Gating] SW mode calibration
5633 11:41:08.068206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5634 11:41:08.074649 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5635 11:41:08.078273 0 14 0 | B1->B0 | 2e2e 2f2f | 0 1 | (0 0) (1 1)
5636 11:41:08.081224 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5637 11:41:08.087932 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 11:41:08.090991 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 11:41:08.094847 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 11:41:08.101173 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 11:41:08.104551 0 14 24 | B1->B0 | 3535 3434 | 1 1 | (0 1) (1 0)
5642 11:41:08.107560 0 14 28 | B1->B0 | 3030 3131 | 1 1 | (1 0) (1 0)
5643 11:41:08.114413 0 15 0 | B1->B0 | 2828 2828 | 1 0 | (1 0) (1 0)
5644 11:41:08.117753 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 11:41:08.121093 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5646 11:41:08.127928 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5647 11:41:08.130905 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 11:41:08.134377 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 11:41:08.141004 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 11:41:08.144020 0 15 28 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
5651 11:41:08.147630 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5652 11:41:08.154062 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 11:41:08.157510 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 11:41:08.161090 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 11:41:08.164000 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 11:41:08.170716 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 11:41:08.174144 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 11:41:08.177082 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 11:41:08.183730 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:41:08.187329 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:41:08.190863 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:41:08.197628 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:41:08.200792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:41:08.204170 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:41:08.210974 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:41:08.213566 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 11:41:08.216887 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 11:41:08.223966 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:41:08.226784 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:41:08.230122 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:41:08.236759 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:41:08.240435 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:41:08.243499 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5674 11:41:08.250549 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 11:41:08.250628 Total UI for P1: 0, mck2ui 16
5676 11:41:08.257108 best dqsien dly found for B0: ( 1, 2, 24)
5677 11:41:08.257192 Total UI for P1: 0, mck2ui 16
5678 11:41:08.263791 best dqsien dly found for B1: ( 1, 2, 26)
5679 11:41:08.267258 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5680 11:41:08.270066 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5681 11:41:08.270141
5682 11:41:08.273545 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5683 11:41:08.276998 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5684 11:41:08.279969 [Gating] SW calibration Done
5685 11:41:08.280055 ==
5686 11:41:08.283634 Dram Type= 6, Freq= 0, CH_1, rank 0
5687 11:41:08.286420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5688 11:41:08.286506 ==
5689 11:41:08.290105 RX Vref Scan: 0
5690 11:41:08.290204
5691 11:41:08.290313 RX Vref 0 -> 0, step: 1
5692 11:41:08.290410
5693 11:41:08.293555 RX Delay -80 -> 252, step: 8
5694 11:41:08.297099 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5695 11:41:08.303447 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5696 11:41:08.306431 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5697 11:41:08.310428 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5698 11:41:08.313096 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5699 11:41:08.316204 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5700 11:41:08.319944 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5701 11:41:08.326909 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5702 11:41:08.330098 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5703 11:41:08.332987 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5704 11:41:08.336357 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5705 11:41:08.339362 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5706 11:41:08.346314 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5707 11:41:08.350007 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5708 11:41:08.352892 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5709 11:41:08.356366 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5710 11:41:08.356448 ==
5711 11:41:08.359963 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 11:41:08.362826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 11:41:08.362909 ==
5714 11:41:08.366387 DQS Delay:
5715 11:41:08.366469 DQS0 = 0, DQS1 = 0
5716 11:41:08.369314 DQM Delay:
5717 11:41:08.369395 DQM0 = 96, DQM1 = 89
5718 11:41:08.369460 DQ Delay:
5719 11:41:08.372958 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =99
5720 11:41:08.376496 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5721 11:41:08.379891 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =87
5722 11:41:08.383060 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5723 11:41:08.386151
5724 11:41:08.386328
5725 11:41:08.386419 ==
5726 11:41:08.389839 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 11:41:08.393057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 11:41:08.393517 ==
5729 11:41:08.393856
5730 11:41:08.394163
5731 11:41:08.396804 TX Vref Scan disable
5732 11:41:08.397229 == TX Byte 0 ==
5733 11:41:08.403007 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5734 11:41:08.406568 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5735 11:41:08.406993 == TX Byte 1 ==
5736 11:41:08.413103 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5737 11:41:08.416232 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5738 11:41:08.416658 ==
5739 11:41:08.419473 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 11:41:08.422614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:41:08.423038 ==
5742 11:41:08.423395
5743 11:41:08.423711
5744 11:41:08.426468 TX Vref Scan disable
5745 11:41:08.429398 == TX Byte 0 ==
5746 11:41:08.433075 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5747 11:41:08.436407 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5748 11:41:08.439067 == TX Byte 1 ==
5749 11:41:08.442789 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5750 11:41:08.446025 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5751 11:41:08.446648
5752 11:41:08.449334 [DATLAT]
5753 11:41:08.449996 Freq=933, CH1 RK0
5754 11:41:08.450584
5755 11:41:08.452297 DATLAT Default: 0xd
5756 11:41:08.452955 0, 0xFFFF, sum = 0
5757 11:41:08.455870 1, 0xFFFF, sum = 0
5758 11:41:08.456557 2, 0xFFFF, sum = 0
5759 11:41:08.459538 3, 0xFFFF, sum = 0
5760 11:41:08.460172 4, 0xFFFF, sum = 0
5761 11:41:08.462392 5, 0xFFFF, sum = 0
5762 11:41:08.463034 6, 0xFFFF, sum = 0
5763 11:41:08.465951 7, 0xFFFF, sum = 0
5764 11:41:08.469263 8, 0xFFFF, sum = 0
5765 11:41:08.469923 9, 0xFFFF, sum = 0
5766 11:41:08.470564 10, 0x0, sum = 1
5767 11:41:08.472130 11, 0x0, sum = 2
5768 11:41:08.472759 12, 0x0, sum = 3
5769 11:41:08.475767 13, 0x0, sum = 4
5770 11:41:08.476421 best_step = 11
5771 11:41:08.476907
5772 11:41:08.477303 ==
5773 11:41:08.479108 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 11:41:08.485381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 11:41:08.485717 ==
5776 11:41:08.486057 RX Vref Scan: 1
5777 11:41:08.486362
5778 11:41:08.488861 RX Vref 0 -> 0, step: 1
5779 11:41:08.489123
5780 11:41:08.491879 RX Delay -61 -> 252, step: 4
5781 11:41:08.492118
5782 11:41:08.495339 Set Vref, RX VrefLevel [Byte0]: 58
5783 11:41:08.499053 [Byte1]: 53
5784 11:41:08.499328
5785 11:41:08.502024 Final RX Vref Byte 0 = 58 to rank0
5786 11:41:08.505213 Final RX Vref Byte 1 = 53 to rank0
5787 11:41:08.508656 Final RX Vref Byte 0 = 58 to rank1
5788 11:41:08.512120 Final RX Vref Byte 1 = 53 to rank1==
5789 11:41:08.515335 Dram Type= 6, Freq= 0, CH_1, rank 0
5790 11:41:08.518650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 11:41:08.518735 ==
5792 11:41:08.522357 DQS Delay:
5793 11:41:08.522464 DQS0 = 0, DQS1 = 0
5794 11:41:08.525012 DQM Delay:
5795 11:41:08.525093 DQM0 = 98, DQM1 = 90
5796 11:41:08.525157 DQ Delay:
5797 11:41:08.528673 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98
5798 11:41:08.531917 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5799 11:41:08.535149 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5800 11:41:08.538268 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5801 11:41:08.538374
5802 11:41:08.538464
5803 11:41:08.548720 [DQSOSCAuto] RK0, (LSB)MR18= 0x18f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 414 ps
5804 11:41:08.551950 CH1 RK0: MR19=504, MR18=18F5
5805 11:41:08.558247 CH1_RK0: MR19=0x504, MR18=0x18F5, DQSOSC=414, MR23=63, INC=63, DEC=42
5806 11:41:08.558359
5807 11:41:08.561806 ----->DramcWriteLeveling(PI) begin...
5808 11:41:08.561910 ==
5809 11:41:08.564807 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 11:41:08.568333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 11:41:08.568435 ==
5812 11:41:08.571636 Write leveling (Byte 0): 25 => 25
5813 11:41:08.575128 Write leveling (Byte 1): 31 => 31
5814 11:41:08.578572 DramcWriteLeveling(PI) end<-----
5815 11:41:08.578644
5816 11:41:08.578703 ==
5817 11:41:08.581609 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 11:41:08.585049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 11:41:08.585149 ==
5820 11:41:08.588465 [Gating] SW mode calibration
5821 11:41:08.594901 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5822 11:41:08.601582 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5823 11:41:08.604664 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 11:41:08.608036 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 11:41:08.614860 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 11:41:08.618446 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 11:41:08.621700 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 11:41:08.628091 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 11:41:08.631256 0 14 24 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (1 0)
5830 11:41:08.634695 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5831 11:41:08.641512 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5832 11:41:08.644836 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 11:41:08.648226 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 11:41:08.651441 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 11:41:08.658032 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 11:41:08.661441 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 11:41:08.665088 0 15 24 | B1->B0 | 2a2a 3636 | 0 1 | (1 1) (0 0)
5838 11:41:08.671485 0 15 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5839 11:41:08.674400 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 11:41:08.677976 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 11:41:08.684455 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 11:41:08.687972 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 11:41:08.691492 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 11:41:08.697996 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5845 11:41:08.701008 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5846 11:41:08.704614 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5847 11:41:08.711170 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:41:08.714080 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:41:08.717574 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:41:08.724100 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:41:08.727649 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:41:08.730966 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:41:08.738020 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:41:08.740740 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:41:08.744098 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 11:41:08.750818 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:41:08.754067 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:41:08.757895 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:41:08.763947 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:41:08.767361 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:41:08.770976 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5862 11:41:08.777486 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5863 11:41:08.777567 Total UI for P1: 0, mck2ui 16
5864 11:41:08.784380 best dqsien dly found for B0: ( 1, 2, 24)
5865 11:41:08.787165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 11:41:08.790796 Total UI for P1: 0, mck2ui 16
5867 11:41:08.794309 best dqsien dly found for B1: ( 1, 2, 26)
5868 11:41:08.797228 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5869 11:41:08.800735 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5870 11:41:08.800819
5871 11:41:08.803734 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5872 11:41:08.807244 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5873 11:41:08.810845 [Gating] SW calibration Done
5874 11:41:08.810928 ==
5875 11:41:08.814334 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 11:41:08.817227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 11:41:08.817323 ==
5878 11:41:08.820631 RX Vref Scan: 0
5879 11:41:08.820719
5880 11:41:08.824214 RX Vref 0 -> 0, step: 1
5881 11:41:08.824297
5882 11:41:08.824359 RX Delay -80 -> 252, step: 8
5883 11:41:08.830605 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5884 11:41:08.834124 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5885 11:41:08.837137 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5886 11:41:08.840960 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5887 11:41:08.843752 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5888 11:41:08.847423 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5889 11:41:08.854048 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5890 11:41:08.856904 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5891 11:41:08.860873 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5892 11:41:08.864121 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5893 11:41:08.867072 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5894 11:41:08.873636 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5895 11:41:08.877222 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5896 11:41:08.880116 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5897 11:41:08.883706 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5898 11:41:08.887016 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5899 11:41:08.887090 ==
5900 11:41:08.890570 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 11:41:08.897144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 11:41:08.897230 ==
5903 11:41:08.897296 DQS Delay:
5904 11:41:08.900531 DQS0 = 0, DQS1 = 0
5905 11:41:08.900613 DQM Delay:
5906 11:41:08.900676 DQM0 = 94, DQM1 = 88
5907 11:41:08.903467 DQ Delay:
5908 11:41:08.907047 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5909 11:41:08.909984 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5910 11:41:08.913638 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5911 11:41:08.916548 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5912 11:41:08.916621
5913 11:41:08.916693
5914 11:41:08.916759 ==
5915 11:41:08.920181 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 11:41:08.923526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 11:41:08.923602 ==
5918 11:41:08.923664
5919 11:41:08.923731
5920 11:41:08.926785 TX Vref Scan disable
5921 11:41:08.926857 == TX Byte 0 ==
5922 11:41:08.933262 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5923 11:41:08.936674 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5924 11:41:08.936748 == TX Byte 1 ==
5925 11:41:08.943478 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5926 11:41:08.947114 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5927 11:41:08.947185 ==
5928 11:41:08.950188 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 11:41:08.953930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 11:41:08.954025 ==
5931 11:41:08.954109
5932 11:41:08.956933
5933 11:41:08.957001 TX Vref Scan disable
5934 11:41:08.959838 == TX Byte 0 ==
5935 11:41:08.964112 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5936 11:41:08.967097 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5937 11:41:08.969869 == TX Byte 1 ==
5938 11:41:08.973371 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5939 11:41:08.976515 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5940 11:41:08.979895
5941 11:41:08.979965 [DATLAT]
5942 11:41:08.980027 Freq=933, CH1 RK1
5943 11:41:08.980098
5944 11:41:08.983686 DATLAT Default: 0xb
5945 11:41:08.983766 0, 0xFFFF, sum = 0
5946 11:41:08.986846 1, 0xFFFF, sum = 0
5947 11:41:08.986917 2, 0xFFFF, sum = 0
5948 11:41:08.989811 3, 0xFFFF, sum = 0
5949 11:41:08.989895 4, 0xFFFF, sum = 0
5950 11:41:08.993102 5, 0xFFFF, sum = 0
5951 11:41:08.996766 6, 0xFFFF, sum = 0
5952 11:41:08.996857 7, 0xFFFF, sum = 0
5953 11:41:08.999812 8, 0xFFFF, sum = 0
5954 11:41:08.999894 9, 0xFFFF, sum = 0
5955 11:41:09.003644 10, 0x0, sum = 1
5956 11:41:09.003727 11, 0x0, sum = 2
5957 11:41:09.003791 12, 0x0, sum = 3
5958 11:41:09.006657 13, 0x0, sum = 4
5959 11:41:09.006738 best_step = 11
5960 11:41:09.006801
5961 11:41:09.006862 ==
5962 11:41:09.010239 Dram Type= 6, Freq= 0, CH_1, rank 1
5963 11:41:09.016760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5964 11:41:09.016843 ==
5965 11:41:09.016906 RX Vref Scan: 0
5966 11:41:09.016966
5967 11:41:09.019800 RX Vref 0 -> 0, step: 1
5968 11:41:09.019881
5969 11:41:09.023090 RX Delay -61 -> 252, step: 4
5970 11:41:09.026713 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5971 11:41:09.033590 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5972 11:41:09.036450 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5973 11:41:09.040084 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5974 11:41:09.042904 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5975 11:41:09.046445 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5976 11:41:09.050119 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5977 11:41:09.056363 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5978 11:41:09.059706 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5979 11:41:09.063011 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5980 11:41:09.066260 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5981 11:41:09.069653 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
5982 11:41:09.073513 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5983 11:41:09.079604 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5984 11:41:09.082923 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5985 11:41:09.086144 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5986 11:41:09.086243 ==
5987 11:41:09.089438 Dram Type= 6, Freq= 0, CH_1, rank 1
5988 11:41:09.092915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5989 11:41:09.092998 ==
5990 11:41:09.096231 DQS Delay:
5991 11:41:09.096315 DQS0 = 0, DQS1 = 0
5992 11:41:09.099858 DQM Delay:
5993 11:41:09.099940 DQM0 = 96, DQM1 = 90
5994 11:41:09.100005 DQ Delay:
5995 11:41:09.102825 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5996 11:41:09.106269 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =92
5997 11:41:09.109803 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5998 11:41:09.112719 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5999 11:41:09.112840
6000 11:41:09.112938
6001 11:41:09.122938 [DQSOSCAuto] RK1, (LSB)MR18= 0xc15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
6002 11:41:09.125957 CH1 RK1: MR19=505, MR18=C15
6003 11:41:09.129354 CH1_RK1: MR19=0x505, MR18=0xC15, DQSOSC=415, MR23=63, INC=62, DEC=41
6004 11:41:09.132778 [RxdqsGatingPostProcess] freq 933
6005 11:41:09.139214 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6006 11:41:09.142732 best DQS0 dly(2T, 0.5T) = (0, 10)
6007 11:41:09.146178 best DQS1 dly(2T, 0.5T) = (0, 10)
6008 11:41:09.149245 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6009 11:41:09.152760 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6010 11:41:09.155745 best DQS0 dly(2T, 0.5T) = (0, 10)
6011 11:41:09.159377 best DQS1 dly(2T, 0.5T) = (0, 10)
6012 11:41:09.162319 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6013 11:41:09.165790 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6014 11:41:09.169007 Pre-setting of DQS Precalculation
6015 11:41:09.172977 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6016 11:41:09.178958 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6017 11:41:09.185921 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6018 11:41:09.186036
6019 11:41:09.189204
6020 11:41:09.189303 [Calibration Summary] 1866 Mbps
6021 11:41:09.192120 CH 0, Rank 0
6022 11:41:09.192255 SW Impedance : PASS
6023 11:41:09.195745 DUTY Scan : NO K
6024 11:41:09.198893 ZQ Calibration : PASS
6025 11:41:09.199029 Jitter Meter : NO K
6026 11:41:09.202183 CBT Training : PASS
6027 11:41:09.205695 Write leveling : PASS
6028 11:41:09.205795 RX DQS gating : PASS
6029 11:41:09.208708 RX DQ/DQS(RDDQC) : PASS
6030 11:41:09.212601 TX DQ/DQS : PASS
6031 11:41:09.212685 RX DATLAT : PASS
6032 11:41:09.215816 RX DQ/DQS(Engine): PASS
6033 11:41:09.215924 TX OE : NO K
6034 11:41:09.218800 All Pass.
6035 11:41:09.218883
6036 11:41:09.218967 CH 0, Rank 1
6037 11:41:09.222810 SW Impedance : PASS
6038 11:41:09.223240 DUTY Scan : NO K
6039 11:41:09.226369 ZQ Calibration : PASS
6040 11:41:09.229167 Jitter Meter : NO K
6041 11:41:09.229722 CBT Training : PASS
6042 11:41:09.232629 Write leveling : PASS
6043 11:41:09.236507 RX DQS gating : PASS
6044 11:41:09.236957 RX DQ/DQS(RDDQC) : PASS
6045 11:41:09.239386 TX DQ/DQS : PASS
6046 11:41:09.242780 RX DATLAT : PASS
6047 11:41:09.243194 RX DQ/DQS(Engine): PASS
6048 11:41:09.245872 TX OE : NO K
6049 11:41:09.246293 All Pass.
6050 11:41:09.246621
6051 11:41:09.249403 CH 1, Rank 0
6052 11:41:09.249924 SW Impedance : PASS
6053 11:41:09.252913 DUTY Scan : NO K
6054 11:41:09.255672 ZQ Calibration : PASS
6055 11:41:09.256132 Jitter Meter : NO K
6056 11:41:09.259176 CBT Training : PASS
6057 11:41:09.262678 Write leveling : PASS
6058 11:41:09.263217 RX DQS gating : PASS
6059 11:41:09.265863 RX DQ/DQS(RDDQC) : PASS
6060 11:41:09.269255 TX DQ/DQS : PASS
6061 11:41:09.269780 RX DATLAT : PASS
6062 11:41:09.272345 RX DQ/DQS(Engine): PASS
6063 11:41:09.272798 TX OE : NO K
6064 11:41:09.275525 All Pass.
6065 11:41:09.275599
6066 11:41:09.275662 CH 1, Rank 1
6067 11:41:09.278669 SW Impedance : PASS
6068 11:41:09.278767 DUTY Scan : NO K
6069 11:41:09.281896 ZQ Calibration : PASS
6070 11:41:09.285236 Jitter Meter : NO K
6071 11:41:09.285340 CBT Training : PASS
6072 11:41:09.288625 Write leveling : PASS
6073 11:41:09.291775 RX DQS gating : PASS
6074 11:41:09.291875 RX DQ/DQS(RDDQC) : PASS
6075 11:41:09.295095 TX DQ/DQS : PASS
6076 11:41:09.298972 RX DATLAT : PASS
6077 11:41:09.299080 RX DQ/DQS(Engine): PASS
6078 11:41:09.302114 TX OE : NO K
6079 11:41:09.302214 All Pass.
6080 11:41:09.302301
6081 11:41:09.305296 DramC Write-DBI off
6082 11:41:09.308541 PER_BANK_REFRESH: Hybrid Mode
6083 11:41:09.308688 TX_TRACKING: ON
6084 11:41:09.318543 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6085 11:41:09.322304 [FAST_K] Save calibration result to emmc
6086 11:41:09.325583 dramc_set_vcore_voltage set vcore to 650000
6087 11:41:09.328714 Read voltage for 400, 6
6088 11:41:09.328821 Vio18 = 0
6089 11:41:09.328914 Vcore = 650000
6090 11:41:09.332111 Vdram = 0
6091 11:41:09.332221 Vddq = 0
6092 11:41:09.332317 Vmddr = 0
6093 11:41:09.338695 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6094 11:41:09.342119 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6095 11:41:09.344958 MEM_TYPE=3, freq_sel=20
6096 11:41:09.348406 sv_algorithm_assistance_LP4_800
6097 11:41:09.351865 ============ PULL DRAM RESETB DOWN ============
6098 11:41:09.354744 ========== PULL DRAM RESETB DOWN end =========
6099 11:41:09.361782 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6100 11:41:09.365241 ===================================
6101 11:41:09.365358 LPDDR4 DRAM CONFIGURATION
6102 11:41:09.368452 ===================================
6103 11:41:09.371861 EX_ROW_EN[0] = 0x0
6104 11:41:09.375211 EX_ROW_EN[1] = 0x0
6105 11:41:09.375318 LP4Y_EN = 0x0
6106 11:41:09.378611 WORK_FSP = 0x0
6107 11:41:09.378713 WL = 0x2
6108 11:41:09.381528 RL = 0x2
6109 11:41:09.381635 BL = 0x2
6110 11:41:09.385120 RPST = 0x0
6111 11:41:09.385222 RD_PRE = 0x0
6112 11:41:09.388470 WR_PRE = 0x1
6113 11:41:09.388583 WR_PST = 0x0
6114 11:41:09.391942 DBI_WR = 0x0
6115 11:41:09.392062 DBI_RD = 0x0
6116 11:41:09.394988 OTF = 0x1
6117 11:41:09.398503 ===================================
6118 11:41:09.401948 ===================================
6119 11:41:09.402050 ANA top config
6120 11:41:09.405203 ===================================
6121 11:41:09.408508 DLL_ASYNC_EN = 0
6122 11:41:09.411782 ALL_SLAVE_EN = 1
6123 11:41:09.415025 NEW_RANK_MODE = 1
6124 11:41:09.415147 DLL_IDLE_MODE = 1
6125 11:41:09.418866 LP45_APHY_COMB_EN = 1
6126 11:41:09.421340 TX_ODT_DIS = 1
6127 11:41:09.425032 NEW_8X_MODE = 1
6128 11:41:09.428556 ===================================
6129 11:41:09.431339 ===================================
6130 11:41:09.434982 data_rate = 800
6131 11:41:09.435303 CKR = 1
6132 11:41:09.438140 DQ_P2S_RATIO = 4
6133 11:41:09.441477 ===================================
6134 11:41:09.444523 CA_P2S_RATIO = 4
6135 11:41:09.448444 DQ_CA_OPEN = 0
6136 11:41:09.451331 DQ_SEMI_OPEN = 1
6137 11:41:09.454786 CA_SEMI_OPEN = 1
6138 11:41:09.454874 CA_FULL_RATE = 0
6139 11:41:09.458280 DQ_CKDIV4_EN = 0
6140 11:41:09.461310 CA_CKDIV4_EN = 1
6141 11:41:09.464992 CA_PREDIV_EN = 0
6142 11:41:09.467967 PH8_DLY = 0
6143 11:41:09.471546 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6144 11:41:09.471642 DQ_AAMCK_DIV = 0
6145 11:41:09.474614 CA_AAMCK_DIV = 0
6146 11:41:09.478076 CA_ADMCK_DIV = 4
6147 11:41:09.481250 DQ_TRACK_CA_EN = 0
6148 11:41:09.484326 CA_PICK = 800
6149 11:41:09.488022 CA_MCKIO = 400
6150 11:41:09.488123 MCKIO_SEMI = 400
6151 11:41:09.491176 PLL_FREQ = 3016
6152 11:41:09.494609 DQ_UI_PI_RATIO = 32
6153 11:41:09.497864 CA_UI_PI_RATIO = 32
6154 11:41:09.501178 ===================================
6155 11:41:09.504487 ===================================
6156 11:41:09.507784 memory_type:LPDDR4
6157 11:41:09.507875 GP_NUM : 10
6158 11:41:09.511124 SRAM_EN : 1
6159 11:41:09.514491 MD32_EN : 0
6160 11:41:09.517895 ===================================
6161 11:41:09.517999 [ANA_INIT] >>>>>>>>>>>>>>
6162 11:41:09.521093 <<<<<< [CONFIGURE PHASE]: ANA_TX
6163 11:41:09.524559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6164 11:41:09.527996 ===================================
6165 11:41:09.530948 data_rate = 800,PCW = 0X7400
6166 11:41:09.534380 ===================================
6167 11:41:09.537400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6168 11:41:09.544555 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6169 11:41:09.554584 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 11:41:09.560905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6171 11:41:09.564366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6172 11:41:09.567855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6173 11:41:09.567940 [ANA_INIT] flow start
6174 11:41:09.570872 [ANA_INIT] PLL >>>>>>>>
6175 11:41:09.574397 [ANA_INIT] PLL <<<<<<<<
6176 11:41:09.574481 [ANA_INIT] MIDPI >>>>>>>>
6177 11:41:09.577925 [ANA_INIT] MIDPI <<<<<<<<
6178 11:41:09.581210 [ANA_INIT] DLL >>>>>>>>
6179 11:41:09.581298 [ANA_INIT] flow end
6180 11:41:09.587401 ============ LP4 DIFF to SE enter ============
6181 11:41:09.590960 ============ LP4 DIFF to SE exit ============
6182 11:41:09.591036 [ANA_INIT] <<<<<<<<<<<<<
6183 11:41:09.594617 [Flow] Enable top DCM control >>>>>
6184 11:41:09.598015 [Flow] Enable top DCM control <<<<<
6185 11:41:09.601013 Enable DLL master slave shuffle
6186 11:41:09.607534 ==============================================================
6187 11:41:09.607624 Gating Mode config
6188 11:41:09.614490 ==============================================================
6189 11:41:09.617791 Config description:
6190 11:41:09.627454 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6191 11:41:09.634358 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6192 11:41:09.637296 SELPH_MODE 0: By rank 1: By Phase
6193 11:41:09.643961 ==============================================================
6194 11:41:09.647449 GAT_TRACK_EN = 0
6195 11:41:09.651023 RX_GATING_MODE = 2
6196 11:41:09.651102 RX_GATING_TRACK_MODE = 2
6197 11:41:09.654040 SELPH_MODE = 1
6198 11:41:09.657395 PICG_EARLY_EN = 1
6199 11:41:09.660624 VALID_LAT_VALUE = 1
6200 11:41:09.667601 ==============================================================
6201 11:41:09.670572 Enter into Gating configuration >>>>
6202 11:41:09.674191 Exit from Gating configuration <<<<
6203 11:41:09.677227 Enter into DVFS_PRE_config >>>>>
6204 11:41:09.687131 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6205 11:41:09.690638 Exit from DVFS_PRE_config <<<<<
6206 11:41:09.694140 Enter into PICG configuration >>>>
6207 11:41:09.697063 Exit from PICG configuration <<<<
6208 11:41:09.700750 [RX_INPUT] configuration >>>>>
6209 11:41:09.703688 [RX_INPUT] configuration <<<<<
6210 11:41:09.707102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6211 11:41:09.713719 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6212 11:41:09.720198 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 11:41:09.727184 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 11:41:09.730503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 11:41:09.737090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 11:41:09.740248 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6217 11:41:09.746912 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6218 11:41:09.750348 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6219 11:41:09.753993 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6220 11:41:09.756992 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6221 11:41:09.764093 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6222 11:41:09.766938 ===================================
6223 11:41:09.767036 LPDDR4 DRAM CONFIGURATION
6224 11:41:09.770018 ===================================
6225 11:41:09.773525 EX_ROW_EN[0] = 0x0
6226 11:41:09.776675 EX_ROW_EN[1] = 0x0
6227 11:41:09.776786 LP4Y_EN = 0x0
6228 11:41:09.780166 WORK_FSP = 0x0
6229 11:41:09.780298 WL = 0x2
6230 11:41:09.783836 RL = 0x2
6231 11:41:09.783917 BL = 0x2
6232 11:41:09.786761 RPST = 0x0
6233 11:41:09.786849 RD_PRE = 0x0
6234 11:41:09.790351 WR_PRE = 0x1
6235 11:41:09.790431 WR_PST = 0x0
6236 11:41:09.793175 DBI_WR = 0x0
6237 11:41:09.793250 DBI_RD = 0x0
6238 11:41:09.796788 OTF = 0x1
6239 11:41:09.800334 ===================================
6240 11:41:09.803327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6241 11:41:09.807034 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6242 11:41:09.813391 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6243 11:41:09.816707 ===================================
6244 11:41:09.816797 LPDDR4 DRAM CONFIGURATION
6245 11:41:09.819893 ===================================
6246 11:41:09.823515 EX_ROW_EN[0] = 0x10
6247 11:41:09.826986 EX_ROW_EN[1] = 0x0
6248 11:41:09.827076 LP4Y_EN = 0x0
6249 11:41:09.830230 WORK_FSP = 0x0
6250 11:41:09.830339 WL = 0x2
6251 11:41:09.833597 RL = 0x2
6252 11:41:09.833674 BL = 0x2
6253 11:41:09.836773 RPST = 0x0
6254 11:41:09.836856 RD_PRE = 0x0
6255 11:41:09.840151 WR_PRE = 0x1
6256 11:41:09.840233 WR_PST = 0x0
6257 11:41:09.843538 DBI_WR = 0x0
6258 11:41:09.843621 DBI_RD = 0x0
6259 11:41:09.846817 OTF = 0x1
6260 11:41:09.850114 ===================================
6261 11:41:09.856843 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6262 11:41:09.859889 nWR fixed to 30
6263 11:41:09.859974 [ModeRegInit_LP4] CH0 RK0
6264 11:41:09.863268 [ModeRegInit_LP4] CH0 RK1
6265 11:41:09.866789 [ModeRegInit_LP4] CH1 RK0
6266 11:41:09.869997 [ModeRegInit_LP4] CH1 RK1
6267 11:41:09.870081 match AC timing 19
6268 11:41:09.873425 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6269 11:41:09.880073 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6270 11:41:09.883063 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6271 11:41:09.886504 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6272 11:41:09.893199 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6273 11:41:09.893283 ==
6274 11:41:09.896511 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 11:41:09.899965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 11:41:09.900050 ==
6277 11:41:09.906491 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 11:41:09.912936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6279 11:41:09.913020 [CA 0] Center 36 (8~64) winsize 57
6280 11:41:09.916488 [CA 1] Center 36 (8~64) winsize 57
6281 11:41:09.919536 [CA 2] Center 36 (8~64) winsize 57
6282 11:41:09.923099 [CA 3] Center 36 (8~64) winsize 57
6283 11:41:09.926150 [CA 4] Center 36 (8~64) winsize 57
6284 11:41:09.930047 [CA 5] Center 36 (8~64) winsize 57
6285 11:41:09.930131
6286 11:41:09.933071 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6287 11:41:09.933165
6288 11:41:09.936286 [CATrainingPosCal] consider 1 rank data
6289 11:41:09.939498 u2DelayCellTimex100 = 270/100 ps
6290 11:41:09.943210 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 11:41:09.949436 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 11:41:09.952986 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 11:41:09.956132 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 11:41:09.959554 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 11:41:09.963023 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 11:41:09.963108
6297 11:41:09.966401 CA PerBit enable=1, Macro0, CA PI delay=36
6298 11:41:09.966486
6299 11:41:09.969432 [CBTSetCACLKResult] CA Dly = 36
6300 11:41:09.969516 CS Dly: 1 (0~32)
6301 11:41:09.972884 ==
6302 11:41:09.976218 Dram Type= 6, Freq= 0, CH_0, rank 1
6303 11:41:09.979261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 11:41:09.979392 ==
6305 11:41:09.982884 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6306 11:41:09.989877 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6307 11:41:09.992925 [CA 0] Center 36 (8~64) winsize 57
6308 11:41:09.995772 [CA 1] Center 36 (8~64) winsize 57
6309 11:41:09.999304 [CA 2] Center 36 (8~64) winsize 57
6310 11:41:10.002812 [CA 3] Center 36 (8~64) winsize 57
6311 11:41:10.005759 [CA 4] Center 36 (8~64) winsize 57
6312 11:41:10.009368 [CA 5] Center 36 (8~64) winsize 57
6313 11:41:10.009453
6314 11:41:10.012280 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6315 11:41:10.012363
6316 11:41:10.015799 [CATrainingPosCal] consider 2 rank data
6317 11:41:10.019421 u2DelayCellTimex100 = 270/100 ps
6318 11:41:10.022330 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:41:10.025965 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:41:10.028890 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:41:10.032861 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:41:10.038986 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 11:41:10.042289 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 11:41:10.042403
6325 11:41:10.045732 CA PerBit enable=1, Macro0, CA PI delay=36
6326 11:41:10.045862
6327 11:41:10.049027 [CBTSetCACLKResult] CA Dly = 36
6328 11:41:10.049122 CS Dly: 1 (0~32)
6329 11:41:10.049216
6330 11:41:10.052245 ----->DramcWriteLeveling(PI) begin...
6331 11:41:10.052363 ==
6332 11:41:10.055461 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 11:41:10.061977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 11:41:10.062080 ==
6335 11:41:10.065367 Write leveling (Byte 0): 40 => 8
6336 11:41:10.065476 Write leveling (Byte 1): 32 => 0
6337 11:41:10.068614 DramcWriteLeveling(PI) end<-----
6338 11:41:10.068719
6339 11:41:10.072097 ==
6340 11:41:10.072198 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 11:41:10.078844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 11:41:10.078945 ==
6343 11:41:10.081829 [Gating] SW mode calibration
6344 11:41:10.088407 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6345 11:41:10.092463 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6346 11:41:10.098461 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6347 11:41:10.102020 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 11:41:10.105443 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 11:41:10.111936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 11:41:10.115535 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 11:41:10.118337 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 11:41:10.125405 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 11:41:10.128384 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 11:41:10.131944 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6355 11:41:10.135526 Total UI for P1: 0, mck2ui 16
6356 11:41:10.138436 best dqsien dly found for B0: ( 0, 14, 24)
6357 11:41:10.141786 Total UI for P1: 0, mck2ui 16
6358 11:41:10.144817 best dqsien dly found for B1: ( 0, 14, 24)
6359 11:41:10.148512 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6360 11:41:10.151765 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6361 11:41:10.151870
6362 11:41:10.158265 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6363 11:41:10.161412 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 11:41:10.161538 [Gating] SW calibration Done
6365 11:41:10.165095 ==
6366 11:41:10.168028 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 11:41:10.171304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 11:41:10.171426 ==
6369 11:41:10.171509 RX Vref Scan: 0
6370 11:41:10.171614
6371 11:41:10.175018 RX Vref 0 -> 0, step: 1
6372 11:41:10.175098
6373 11:41:10.178592 RX Delay -410 -> 252, step: 16
6374 11:41:10.181653 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6375 11:41:10.187970 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6376 11:41:10.191542 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6377 11:41:10.194564 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6378 11:41:10.198063 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6379 11:41:10.204713 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6380 11:41:10.208133 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6381 11:41:10.210979 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6382 11:41:10.214590 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6383 11:41:10.218032 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6384 11:41:10.224447 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6385 11:41:10.228076 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6386 11:41:10.231648 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6387 11:41:10.238223 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6388 11:41:10.241110 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6389 11:41:10.244817 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6390 11:41:10.244897 ==
6391 11:41:10.248051 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 11:41:10.251321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 11:41:10.251458 ==
6394 11:41:10.254606 DQS Delay:
6395 11:41:10.254692 DQS0 = 43, DQS1 = 51
6396 11:41:10.258121 DQM Delay:
6397 11:41:10.258228 DQM0 = 14, DQM1 = 10
6398 11:41:10.261222 DQ Delay:
6399 11:41:10.261321 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =8
6400 11:41:10.264259 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6401 11:41:10.267463 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6402 11:41:10.271214 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6403 11:41:10.271330
6404 11:41:10.271475
6405 11:41:10.274228 ==
6406 11:41:10.274361 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 11:41:10.280763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 11:41:10.280870 ==
6409 11:41:10.280961
6410 11:41:10.281056
6411 11:41:10.284613 TX Vref Scan disable
6412 11:41:10.284711 == TX Byte 0 ==
6413 11:41:10.287754 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 11:41:10.294072 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 11:41:10.294183 == TX Byte 1 ==
6416 11:41:10.297651 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6417 11:41:10.304258 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6418 11:41:10.304372 ==
6419 11:41:10.307763 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 11:41:10.310744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:41:10.310860 ==
6422 11:41:10.310954
6423 11:41:10.311045
6424 11:41:10.314146 TX Vref Scan disable
6425 11:41:10.314249 == TX Byte 0 ==
6426 11:41:10.317727 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 11:41:10.324134 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 11:41:10.324267 == TX Byte 1 ==
6429 11:41:10.327083 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6430 11:41:10.333840 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6431 11:41:10.333973
6432 11:41:10.334099 [DATLAT]
6433 11:41:10.334218 Freq=400, CH0 RK0
6434 11:41:10.337283
6435 11:41:10.337385 DATLAT Default: 0xf
6436 11:41:10.340277 0, 0xFFFF, sum = 0
6437 11:41:10.340375 1, 0xFFFF, sum = 0
6438 11:41:10.343815 2, 0xFFFF, sum = 0
6439 11:41:10.343913 3, 0xFFFF, sum = 0
6440 11:41:10.347437 4, 0xFFFF, sum = 0
6441 11:41:10.347508 5, 0xFFFF, sum = 0
6442 11:41:10.350909 6, 0xFFFF, sum = 0
6443 11:41:10.351024 7, 0xFFFF, sum = 0
6444 11:41:10.353740 8, 0xFFFF, sum = 0
6445 11:41:10.353843 9, 0xFFFF, sum = 0
6446 11:41:10.357309 10, 0xFFFF, sum = 0
6447 11:41:10.357407 11, 0xFFFF, sum = 0
6448 11:41:10.360323 12, 0xFFFF, sum = 0
6449 11:41:10.360424 13, 0x0, sum = 1
6450 11:41:10.363941 14, 0x0, sum = 2
6451 11:41:10.364028 15, 0x0, sum = 3
6452 11:41:10.367103 16, 0x0, sum = 4
6453 11:41:10.367210 best_step = 14
6454 11:41:10.367300
6455 11:41:10.367404 ==
6456 11:41:10.370210 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 11:41:10.376694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 11:41:10.376775 ==
6459 11:41:10.376840 RX Vref Scan: 1
6460 11:41:10.376898
6461 11:41:10.380411 RX Vref 0 -> 0, step: 1
6462 11:41:10.380489
6463 11:41:10.383485 RX Delay -343 -> 252, step: 8
6464 11:41:10.383560
6465 11:41:10.386797 Set Vref, RX VrefLevel [Byte0]: 54
6466 11:41:10.390588 [Byte1]: 51
6467 11:41:10.390671
6468 11:41:10.393903 Final RX Vref Byte 0 = 54 to rank0
6469 11:41:10.397209 Final RX Vref Byte 1 = 51 to rank0
6470 11:41:10.400497 Final RX Vref Byte 0 = 54 to rank1
6471 11:41:10.403820 Final RX Vref Byte 1 = 51 to rank1==
6472 11:41:10.406780 Dram Type= 6, Freq= 0, CH_0, rank 0
6473 11:41:10.410308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 11:41:10.413941 ==
6475 11:41:10.414023 DQS Delay:
6476 11:41:10.414088 DQS0 = 44, DQS1 = 60
6477 11:41:10.416850 DQM Delay:
6478 11:41:10.416942 DQM0 = 11, DQM1 = 16
6479 11:41:10.420357 DQ Delay:
6480 11:41:10.420439 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6481 11:41:10.423617 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6482 11:41:10.427068 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6483 11:41:10.430594 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6484 11:41:10.430666
6485 11:41:10.430727
6486 11:41:10.440185 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6487 11:41:10.443791 CH0 RK0: MR19=C0C, MR18=8A59
6488 11:41:10.446785 CH0_RK0: MR19=0xC0C, MR18=0x8A59, DQSOSC=392, MR23=63, INC=384, DEC=256
6489 11:41:10.450469 ==
6490 11:41:10.453922 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 11:41:10.457114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 11:41:10.457205 ==
6493 11:41:10.460143 [Gating] SW mode calibration
6494 11:41:10.467083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6495 11:41:10.470483 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6496 11:41:10.476800 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6497 11:41:10.479976 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 11:41:10.483426 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 11:41:10.489714 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 11:41:10.493236 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 11:41:10.496461 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 11:41:10.503188 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 11:41:10.506862 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 11:41:10.509542 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6505 11:41:10.513168 Total UI for P1: 0, mck2ui 16
6506 11:41:10.516134 best dqsien dly found for B0: ( 0, 14, 24)
6507 11:41:10.520028 Total UI for P1: 0, mck2ui 16
6508 11:41:10.522997 best dqsien dly found for B1: ( 0, 14, 24)
6509 11:41:10.526472 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6510 11:41:10.532932 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6511 11:41:10.533013
6512 11:41:10.536260 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6513 11:41:10.539524 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 11:41:10.542955 [Gating] SW calibration Done
6515 11:41:10.543036 ==
6516 11:41:10.545991 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 11:41:10.549556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 11:41:10.549638 ==
6519 11:41:10.549701 RX Vref Scan: 0
6520 11:41:10.552606
6521 11:41:10.552686 RX Vref 0 -> 0, step: 1
6522 11:41:10.552750
6523 11:41:10.556213 RX Delay -410 -> 252, step: 16
6524 11:41:10.559692 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6525 11:41:10.566188 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6526 11:41:10.569233 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6527 11:41:10.572462 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6528 11:41:10.576059 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6529 11:41:10.583001 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6530 11:41:10.585832 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6531 11:41:10.589205 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6532 11:41:10.592478 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6533 11:41:10.599568 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6534 11:41:10.602814 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6535 11:41:10.606089 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6536 11:41:10.609218 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6537 11:41:10.615790 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6538 11:41:10.619291 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6539 11:41:10.622287 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6540 11:41:10.622382 ==
6541 11:41:10.625681 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 11:41:10.632753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 11:41:10.632835 ==
6544 11:41:10.632898 DQS Delay:
6545 11:41:10.635744 DQS0 = 51, DQS1 = 51
6546 11:41:10.635825 DQM Delay:
6547 11:41:10.635905 DQM0 = 18, DQM1 = 10
6548 11:41:10.639284 DQ Delay:
6549 11:41:10.642186 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6550 11:41:10.645772 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6551 11:41:10.645870 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6552 11:41:10.649418 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6553 11:41:10.652441
6554 11:41:10.652521
6555 11:41:10.652651 ==
6556 11:41:10.655974 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 11:41:10.658936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 11:41:10.659017 ==
6559 11:41:10.659079
6560 11:41:10.659138
6561 11:41:10.662503 TX Vref Scan disable
6562 11:41:10.662584 == TX Byte 0 ==
6563 11:41:10.665894 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6564 11:41:10.672510 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6565 11:41:10.672608 == TX Byte 1 ==
6566 11:41:10.675467 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6567 11:41:10.682214 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6568 11:41:10.682352 ==
6569 11:41:10.685903 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 11:41:10.689163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 11:41:10.689263 ==
6572 11:41:10.689360
6573 11:41:10.689451
6574 11:41:10.692333 TX Vref Scan disable
6575 11:41:10.692482 == TX Byte 0 ==
6576 11:41:10.695890 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6577 11:41:10.702820 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6578 11:41:10.702918 == TX Byte 1 ==
6579 11:41:10.705924 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6580 11:41:10.712357 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6581 11:41:10.712445
6582 11:41:10.712543 [DATLAT]
6583 11:41:10.712634 Freq=400, CH0 RK1
6584 11:41:10.715439
6585 11:41:10.715538 DATLAT Default: 0xe
6586 11:41:10.718847 0, 0xFFFF, sum = 0
6587 11:41:10.718930 1, 0xFFFF, sum = 0
6588 11:41:10.722225 2, 0xFFFF, sum = 0
6589 11:41:10.722324 3, 0xFFFF, sum = 0
6590 11:41:10.725852 4, 0xFFFF, sum = 0
6591 11:41:10.725952 5, 0xFFFF, sum = 0
6592 11:41:10.728632 6, 0xFFFF, sum = 0
6593 11:41:10.728730 7, 0xFFFF, sum = 0
6594 11:41:10.732281 8, 0xFFFF, sum = 0
6595 11:41:10.732381 9, 0xFFFF, sum = 0
6596 11:41:10.735365 10, 0xFFFF, sum = 0
6597 11:41:10.735479 11, 0xFFFF, sum = 0
6598 11:41:10.739073 12, 0xFFFF, sum = 0
6599 11:41:10.739171 13, 0x0, sum = 1
6600 11:41:10.742121 14, 0x0, sum = 2
6601 11:41:10.742220 15, 0x0, sum = 3
6602 11:41:10.745472 16, 0x0, sum = 4
6603 11:41:10.745572 best_step = 14
6604 11:41:10.745667
6605 11:41:10.745741 ==
6606 11:41:10.748467 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 11:41:10.755535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 11:41:10.755617 ==
6609 11:41:10.755681 RX Vref Scan: 0
6610 11:41:10.755752
6611 11:41:10.758609 RX Vref 0 -> 0, step: 1
6612 11:41:10.758739
6613 11:41:10.762238 RX Delay -343 -> 252, step: 8
6614 11:41:10.768633 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6615 11:41:10.771725 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6616 11:41:10.775420 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6617 11:41:10.778732 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6618 11:41:10.785248 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6619 11:41:10.788463 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6620 11:41:10.791864 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6621 11:41:10.795006 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6622 11:41:10.801834 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6623 11:41:10.805098 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6624 11:41:10.808282 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6625 11:41:10.811809 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6626 11:41:10.818311 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6627 11:41:10.821548 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6628 11:41:10.824944 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6629 11:41:10.828415 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6630 11:41:10.831333 ==
6631 11:41:10.834736 Dram Type= 6, Freq= 0, CH_0, rank 1
6632 11:41:10.838118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 11:41:10.838203 ==
6634 11:41:10.838269 DQS Delay:
6635 11:41:10.841713 DQS0 = 48, DQS1 = 56
6636 11:41:10.841796 DQM Delay:
6637 11:41:10.844623 DQM0 = 13, DQM1 = 10
6638 11:41:10.844707 DQ Delay:
6639 11:41:10.848127 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6640 11:41:10.851725 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6641 11:41:10.854707 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6642 11:41:10.858265 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6643 11:41:10.858349
6644 11:41:10.858413
6645 11:41:10.864912 [DQSOSCAuto] RK1, (LSB)MR18= 0x9163, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6646 11:41:10.867941 CH0 RK1: MR19=C0C, MR18=9163
6647 11:41:10.874939 CH0_RK1: MR19=0xC0C, MR18=0x9163, DQSOSC=391, MR23=63, INC=386, DEC=257
6648 11:41:10.878478 [RxdqsGatingPostProcess] freq 400
6649 11:41:10.881235 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6650 11:41:10.884776 best DQS0 dly(2T, 0.5T) = (0, 10)
6651 11:41:10.887849 best DQS1 dly(2T, 0.5T) = (0, 10)
6652 11:41:10.891073 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6653 11:41:10.894828 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6654 11:41:10.898253 best DQS0 dly(2T, 0.5T) = (0, 10)
6655 11:41:10.901029 best DQS1 dly(2T, 0.5T) = (0, 10)
6656 11:41:10.904638 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6657 11:41:10.907682 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6658 11:41:10.910936 Pre-setting of DQS Precalculation
6659 11:41:10.914398 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6660 11:41:10.917848 ==
6661 11:41:10.921241 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 11:41:10.924793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 11:41:10.924909 ==
6664 11:41:10.927679 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 11:41:10.934727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6666 11:41:10.937593 [CA 0] Center 36 (8~64) winsize 57
6667 11:41:10.940981 [CA 1] Center 36 (8~64) winsize 57
6668 11:41:10.944548 [CA 2] Center 36 (8~64) winsize 57
6669 11:41:10.947585 [CA 3] Center 36 (8~64) winsize 57
6670 11:41:10.951157 [CA 4] Center 36 (8~64) winsize 57
6671 11:41:10.954731 [CA 5] Center 36 (8~64) winsize 57
6672 11:41:10.954810
6673 11:41:10.957850 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6674 11:41:10.957952
6675 11:41:10.961229 [CATrainingPosCal] consider 1 rank data
6676 11:41:10.964295 u2DelayCellTimex100 = 270/100 ps
6677 11:41:10.967790 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 11:41:10.970868 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 11:41:10.974719 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 11:41:10.978058 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 11:41:10.981548 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 11:41:10.988126 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 11:41:10.988238
6684 11:41:10.991184 CA PerBit enable=1, Macro0, CA PI delay=36
6685 11:41:10.991270
6686 11:41:10.994719 [CBTSetCACLKResult] CA Dly = 36
6687 11:41:10.994795 CS Dly: 1 (0~32)
6688 11:41:10.994875 ==
6689 11:41:10.997538 Dram Type= 6, Freq= 0, CH_1, rank 1
6690 11:41:11.001090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 11:41:11.004456 ==
6692 11:41:11.007649 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6693 11:41:11.014349 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6694 11:41:11.017348 [CA 0] Center 36 (8~64) winsize 57
6695 11:41:11.021158 [CA 1] Center 36 (8~64) winsize 57
6696 11:41:11.024132 [CA 2] Center 36 (8~64) winsize 57
6697 11:41:11.027572 [CA 3] Center 36 (8~64) winsize 57
6698 11:41:11.030952 [CA 4] Center 36 (8~64) winsize 57
6699 11:41:11.034416 [CA 5] Center 36 (8~64) winsize 57
6700 11:41:11.034500
6701 11:41:11.037699 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6702 11:41:11.037783
6703 11:41:11.040889 [CATrainingPosCal] consider 2 rank data
6704 11:41:11.044196 u2DelayCellTimex100 = 270/100 ps
6705 11:41:11.047707 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:41:11.050711 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:41:11.054116 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:41:11.057812 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:41:11.060785 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 11:41:11.064483 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 11:41:11.064567
6712 11:41:11.067521 CA PerBit enable=1, Macro0, CA PI delay=36
6713 11:41:11.067607
6714 11:41:11.071077 [CBTSetCACLKResult] CA Dly = 36
6715 11:41:11.074056 CS Dly: 1 (0~32)
6716 11:41:11.074140
6717 11:41:11.077707 ----->DramcWriteLeveling(PI) begin...
6718 11:41:11.077797 ==
6719 11:41:11.080955 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 11:41:11.083966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 11:41:11.084058 ==
6722 11:41:11.087271 Write leveling (Byte 0): 40 => 8
6723 11:41:11.091010 Write leveling (Byte 1): 40 => 8
6724 11:41:11.093991 DramcWriteLeveling(PI) end<-----
6725 11:41:11.094074
6726 11:41:11.094140 ==
6727 11:41:11.097463 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 11:41:11.100727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 11:41:11.100813 ==
6730 11:41:11.104206 [Gating] SW mode calibration
6731 11:41:11.110538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6732 11:41:11.117929 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6733 11:41:11.120735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6734 11:41:11.127253 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6735 11:41:11.130767 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 11:41:11.134117 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 11:41:11.137206 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 11:41:11.143833 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 11:41:11.146969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 11:41:11.150329 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 11:41:11.157325 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6742 11:41:11.160291 Total UI for P1: 0, mck2ui 16
6743 11:41:11.163857 best dqsien dly found for B0: ( 0, 14, 24)
6744 11:41:11.167359 Total UI for P1: 0, mck2ui 16
6745 11:41:11.170379 best dqsien dly found for B1: ( 0, 14, 24)
6746 11:41:11.173942 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6747 11:41:11.176914 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6748 11:41:11.177021
6749 11:41:11.180539 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6750 11:41:11.183796 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 11:41:11.187165 [Gating] SW calibration Done
6752 11:41:11.187268 ==
6753 11:41:11.190259 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 11:41:11.193914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 11:41:11.194012 ==
6756 11:41:11.196789 RX Vref Scan: 0
6757 11:41:11.196884
6758 11:41:11.200328 RX Vref 0 -> 0, step: 1
6759 11:41:11.200404
6760 11:41:11.200466 RX Delay -410 -> 252, step: 16
6761 11:41:11.207094 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6762 11:41:11.210474 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6763 11:41:11.213755 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6764 11:41:11.217068 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6765 11:41:11.223741 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6766 11:41:11.226765 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6767 11:41:11.230426 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6768 11:41:11.233249 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6769 11:41:11.240035 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6770 11:41:11.243135 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6771 11:41:11.246629 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6772 11:41:11.253434 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6773 11:41:11.256728 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6774 11:41:11.260192 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6775 11:41:11.263193 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6776 11:41:11.269765 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6777 11:41:11.269866 ==
6778 11:41:11.273456 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 11:41:11.276830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 11:41:11.276936 ==
6781 11:41:11.277036 DQS Delay:
6782 11:41:11.279875 DQS0 = 51, DQS1 = 59
6783 11:41:11.279984 DQM Delay:
6784 11:41:11.283320 DQM0 = 18, DQM1 = 17
6785 11:41:11.283444 DQ Delay:
6786 11:41:11.286796 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6787 11:41:11.289520 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6788 11:41:11.293048 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6789 11:41:11.296651 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6790 11:41:11.296728
6791 11:41:11.296791
6792 11:41:11.296850 ==
6793 11:41:11.299626 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 11:41:11.303160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 11:41:11.303270 ==
6796 11:41:11.303374
6797 11:41:11.306616
6798 11:41:11.306698 TX Vref Scan disable
6799 11:41:11.309846 == TX Byte 0 ==
6800 11:41:11.313126 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 11:41:11.316319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 11:41:11.319775 == TX Byte 1 ==
6803 11:41:11.323297 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 11:41:11.326370 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 11:41:11.326455 ==
6806 11:41:11.329758 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 11:41:11.333073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:41:11.336105 ==
6809 11:41:11.336220
6810 11:41:11.336313
6811 11:41:11.336409 TX Vref Scan disable
6812 11:41:11.339478 == TX Byte 0 ==
6813 11:41:11.343066 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 11:41:11.346032 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 11:41:11.349403 == TX Byte 1 ==
6816 11:41:11.352752 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 11:41:11.355659 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 11:41:11.355743
6819 11:41:11.359076 [DATLAT]
6820 11:41:11.359160 Freq=400, CH1 RK0
6821 11:41:11.359225
6822 11:41:11.362382 DATLAT Default: 0xf
6823 11:41:11.362465 0, 0xFFFF, sum = 0
6824 11:41:11.365937 1, 0xFFFF, sum = 0
6825 11:41:11.366022 2, 0xFFFF, sum = 0
6826 11:41:11.368991 3, 0xFFFF, sum = 0
6827 11:41:11.369076 4, 0xFFFF, sum = 0
6828 11:41:11.372568 5, 0xFFFF, sum = 0
6829 11:41:11.372654 6, 0xFFFF, sum = 0
6830 11:41:11.375727 7, 0xFFFF, sum = 0
6831 11:41:11.375811 8, 0xFFFF, sum = 0
6832 11:41:11.379250 9, 0xFFFF, sum = 0
6833 11:41:11.379367 10, 0xFFFF, sum = 0
6834 11:41:11.382395 11, 0xFFFF, sum = 0
6835 11:41:11.382480 12, 0xFFFF, sum = 0
6836 11:41:11.385921 13, 0x0, sum = 1
6837 11:41:11.386034 14, 0x0, sum = 2
6838 11:41:11.388741 15, 0x0, sum = 3
6839 11:41:11.388826 16, 0x0, sum = 4
6840 11:41:11.392432 best_step = 14
6841 11:41:11.392515
6842 11:41:11.392581 ==
6843 11:41:11.395685 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 11:41:11.398834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 11:41:11.398919 ==
6846 11:41:11.402376 RX Vref Scan: 1
6847 11:41:11.402459
6848 11:41:11.402525 RX Vref 0 -> 0, step: 1
6849 11:41:11.402587
6850 11:41:11.405426 RX Delay -359 -> 252, step: 8
6851 11:41:11.405509
6852 11:41:11.408852 Set Vref, RX VrefLevel [Byte0]: 58
6853 11:41:11.412338 [Byte1]: 53
6854 11:41:11.417121
6855 11:41:11.417205 Final RX Vref Byte 0 = 58 to rank0
6856 11:41:11.420597 Final RX Vref Byte 1 = 53 to rank0
6857 11:41:11.423542 Final RX Vref Byte 0 = 58 to rank1
6858 11:41:11.427299 Final RX Vref Byte 1 = 53 to rank1==
6859 11:41:11.430390 Dram Type= 6, Freq= 0, CH_1, rank 0
6860 11:41:11.437196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 11:41:11.437281 ==
6862 11:41:11.437348 DQS Delay:
6863 11:41:11.440435 DQS0 = 48, DQS1 = 60
6864 11:41:11.440519 DQM Delay:
6865 11:41:11.440584 DQM0 = 12, DQM1 = 13
6866 11:41:11.443399 DQ Delay:
6867 11:41:11.446706 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6868 11:41:11.446790 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6869 11:41:11.450221 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6870 11:41:11.453670 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6871 11:41:11.456769
6872 11:41:11.456852
6873 11:41:11.463764 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a32, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6874 11:41:11.466528 CH1 RK0: MR19=C0C, MR18=8A32
6875 11:41:11.473145 CH1_RK0: MR19=0xC0C, MR18=0x8A32, DQSOSC=392, MR23=63, INC=384, DEC=256
6876 11:41:11.473231 ==
6877 11:41:11.476703 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 11:41:11.479691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 11:41:11.479780 ==
6880 11:41:11.483251 [Gating] SW mode calibration
6881 11:41:11.489728 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6882 11:41:11.496594 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6883 11:41:11.499950 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6884 11:41:11.502911 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 11:41:11.510065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 11:41:11.513025 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 11:41:11.516659 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 11:41:11.523234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 11:41:11.526063 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 11:41:11.529570 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 11:41:11.536269 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6892 11:41:11.536373 Total UI for P1: 0, mck2ui 16
6893 11:41:11.542572 best dqsien dly found for B0: ( 0, 14, 24)
6894 11:41:11.542658 Total UI for P1: 0, mck2ui 16
6895 11:41:11.546042 best dqsien dly found for B1: ( 0, 14, 24)
6896 11:41:11.552930 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6897 11:41:11.555837 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6898 11:41:11.555922
6899 11:41:11.559401 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6900 11:41:11.562805 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 11:41:11.566161 [Gating] SW calibration Done
6902 11:41:11.566246 ==
6903 11:41:11.569250 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 11:41:11.572370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 11:41:11.572457 ==
6906 11:41:11.575891 RX Vref Scan: 0
6907 11:41:11.575975
6908 11:41:11.576044 RX Vref 0 -> 0, step: 1
6909 11:41:11.576123
6910 11:41:11.579047 RX Delay -410 -> 252, step: 16
6911 11:41:11.585950 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6912 11:41:11.589082 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6913 11:41:11.592058 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6914 11:41:11.595698 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6915 11:41:11.601958 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6916 11:41:11.605349 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6917 11:41:11.608934 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6918 11:41:11.611905 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6919 11:41:11.618889 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6920 11:41:11.622299 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6921 11:41:11.625672 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6922 11:41:11.628808 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6923 11:41:11.634915 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6924 11:41:11.638848 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6925 11:41:11.641710 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6926 11:41:11.648512 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6927 11:41:11.648622 ==
6928 11:41:11.651895 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 11:41:11.655319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 11:41:11.655410 ==
6931 11:41:11.655476 DQS Delay:
6932 11:41:11.658244 DQS0 = 43, DQS1 = 59
6933 11:41:11.658351 DQM Delay:
6934 11:41:11.661795 DQM0 = 9, DQM1 = 19
6935 11:41:11.661901 DQ Delay:
6936 11:41:11.665183 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6937 11:41:11.668412 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6938 11:41:11.671833 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6939 11:41:11.675381 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6940 11:41:11.675490
6941 11:41:11.675582
6942 11:41:11.675678 ==
6943 11:41:11.678334 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 11:41:11.681390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 11:41:11.681492 ==
6946 11:41:11.681587
6947 11:41:11.681678
6948 11:41:11.684847 TX Vref Scan disable
6949 11:41:11.684951 == TX Byte 0 ==
6950 11:41:11.691494 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6951 11:41:11.694948 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6952 11:41:11.695050 == TX Byte 1 ==
6953 11:41:11.701397 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6954 11:41:11.704921 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6955 11:41:11.705029 ==
6956 11:41:11.707719 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 11:41:11.711116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 11:41:11.711222 ==
6959 11:41:11.711321
6960 11:41:11.711420
6961 11:41:11.714720 TX Vref Scan disable
6962 11:41:11.717711 == TX Byte 0 ==
6963 11:41:11.721204 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6964 11:41:11.724829 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6965 11:41:11.724941 == TX Byte 1 ==
6966 11:41:11.731065 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6967 11:41:11.734693 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6968 11:41:11.734801
6969 11:41:11.734896 [DATLAT]
6970 11:41:11.737680 Freq=400, CH1 RK1
6971 11:41:11.737783
6972 11:41:11.737875 DATLAT Default: 0xe
6973 11:41:11.741046 0, 0xFFFF, sum = 0
6974 11:41:11.741136 1, 0xFFFF, sum = 0
6975 11:41:11.744440 2, 0xFFFF, sum = 0
6976 11:41:11.744526 3, 0xFFFF, sum = 0
6977 11:41:11.747823 4, 0xFFFF, sum = 0
6978 11:41:11.747909 5, 0xFFFF, sum = 0
6979 11:41:11.751179 6, 0xFFFF, sum = 0
6980 11:41:11.754651 7, 0xFFFF, sum = 0
6981 11:41:11.754737 8, 0xFFFF, sum = 0
6982 11:41:11.758159 9, 0xFFFF, sum = 0
6983 11:41:11.758245 10, 0xFFFF, sum = 0
6984 11:41:11.760865 11, 0xFFFF, sum = 0
6985 11:41:11.760950 12, 0xFFFF, sum = 0
6986 11:41:11.764488 13, 0x0, sum = 1
6987 11:41:11.764574 14, 0x0, sum = 2
6988 11:41:11.767899 15, 0x0, sum = 3
6989 11:41:11.767983 16, 0x0, sum = 4
6990 11:41:11.768050 best_step = 14
6991 11:41:11.768111
6992 11:41:11.771111 ==
6993 11:41:11.774474 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 11:41:11.777766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 11:41:11.777850 ==
6996 11:41:11.777932 RX Vref Scan: 0
6997 11:41:11.778056
6998 11:41:11.781325 RX Vref 0 -> 0, step: 1
6999 11:41:11.781407
7000 11:41:11.784267 RX Delay -359 -> 252, step: 8
7001 11:41:11.791366 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7002 11:41:11.794464 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7003 11:41:11.797894 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
7004 11:41:11.804837 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7005 11:41:11.807930 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7006 11:41:11.811387 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7007 11:41:11.814789 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7008 11:41:11.817707 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7009 11:41:11.824699 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7010 11:41:11.827706 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7011 11:41:11.831177 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7012 11:41:11.838060 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
7013 11:41:11.841215 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7014 11:41:11.844647 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7015 11:41:11.847621 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7016 11:41:11.854530 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7017 11:41:11.854625 ==
7018 11:41:11.857511 Dram Type= 6, Freq= 0, CH_1, rank 1
7019 11:41:11.860861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7020 11:41:11.860974 ==
7021 11:41:11.861083 DQS Delay:
7022 11:41:11.864140 DQS0 = 48, DQS1 = 56
7023 11:41:11.864224 DQM Delay:
7024 11:41:11.867128 DQM0 = 10, DQM1 = 9
7025 11:41:11.867223 DQ Delay:
7026 11:41:11.870733 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7027 11:41:11.873793 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =4
7028 11:41:11.877068 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
7029 11:41:11.880204 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7030 11:41:11.880288
7031 11:41:11.880353
7032 11:41:11.887492 [DQSOSCAuto] RK1, (LSB)MR18= 0x778e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7033 11:41:11.890336 CH1 RK1: MR19=C0C, MR18=778E
7034 11:41:11.896964 CH1_RK1: MR19=0xC0C, MR18=0x778E, DQSOSC=392, MR23=63, INC=384, DEC=256
7035 11:41:11.900514 [RxdqsGatingPostProcess] freq 400
7036 11:41:11.907759 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7037 11:41:11.910436 best DQS0 dly(2T, 0.5T) = (0, 10)
7038 11:41:11.910519 best DQS1 dly(2T, 0.5T) = (0, 10)
7039 11:41:11.913914 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7040 11:41:11.917244 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7041 11:41:11.920209 best DQS0 dly(2T, 0.5T) = (0, 10)
7042 11:41:11.923674 best DQS1 dly(2T, 0.5T) = (0, 10)
7043 11:41:11.927293 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7044 11:41:11.930314 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7045 11:41:11.933684 Pre-setting of DQS Precalculation
7046 11:41:11.940586 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7047 11:41:11.947188 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7048 11:41:11.953852 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7049 11:41:11.953939
7050 11:41:11.954005
7051 11:41:11.957128 [Calibration Summary] 800 Mbps
7052 11:41:11.957213 CH 0, Rank 0
7053 11:41:11.960287 SW Impedance : PASS
7054 11:41:11.964057 DUTY Scan : NO K
7055 11:41:11.964142 ZQ Calibration : PASS
7056 11:41:11.967052 Jitter Meter : NO K
7057 11:41:11.970298 CBT Training : PASS
7058 11:41:11.970380 Write leveling : PASS
7059 11:41:11.973363 RX DQS gating : PASS
7060 11:41:11.976732 RX DQ/DQS(RDDQC) : PASS
7061 11:41:11.976810 TX DQ/DQS : PASS
7062 11:41:11.980098 RX DATLAT : PASS
7063 11:41:11.980173 RX DQ/DQS(Engine): PASS
7064 11:41:11.983417 TX OE : NO K
7065 11:41:11.983491 All Pass.
7066 11:41:11.983552
7067 11:41:11.986811 CH 0, Rank 1
7068 11:41:11.989830 SW Impedance : PASS
7069 11:41:11.989904 DUTY Scan : NO K
7070 11:41:11.993452 ZQ Calibration : PASS
7071 11:41:11.993537 Jitter Meter : NO K
7072 11:41:11.996325 CBT Training : PASS
7073 11:41:11.999975 Write leveling : NO K
7074 11:41:12.000062 RX DQS gating : PASS
7075 11:41:12.002997 RX DQ/DQS(RDDQC) : PASS
7076 11:41:12.006450 TX DQ/DQS : PASS
7077 11:41:12.006528 RX DATLAT : PASS
7078 11:41:12.009909 RX DQ/DQS(Engine): PASS
7079 11:41:12.013639 TX OE : NO K
7080 11:41:12.013746 All Pass.
7081 11:41:12.013838
7082 11:41:12.013934 CH 1, Rank 0
7083 11:41:12.016993 SW Impedance : PASS
7084 11:41:12.019976 DUTY Scan : NO K
7085 11:41:12.020081 ZQ Calibration : PASS
7086 11:41:12.022896 Jitter Meter : NO K
7087 11:41:12.026426 CBT Training : PASS
7088 11:41:12.026503 Write leveling : PASS
7089 11:41:12.029941 RX DQS gating : PASS
7090 11:41:12.032864 RX DQ/DQS(RDDQC) : PASS
7091 11:41:12.032966 TX DQ/DQS : PASS
7092 11:41:12.036823 RX DATLAT : PASS
7093 11:41:12.036929 RX DQ/DQS(Engine): PASS
7094 11:41:12.039820 TX OE : NO K
7095 11:41:12.039930 All Pass.
7096 11:41:12.040024
7097 11:41:12.043404 CH 1, Rank 1
7098 11:41:12.043504 SW Impedance : PASS
7099 11:41:12.046299 DUTY Scan : NO K
7100 11:41:12.049512 ZQ Calibration : PASS
7101 11:41:12.049618 Jitter Meter : NO K
7102 11:41:12.052829 CBT Training : PASS
7103 11:41:12.056381 Write leveling : NO K
7104 11:41:12.056480 RX DQS gating : PASS
7105 11:41:12.059758 RX DQ/DQS(RDDQC) : PASS
7106 11:41:12.063534 TX DQ/DQS : PASS
7107 11:41:12.063642 RX DATLAT : PASS
7108 11:41:12.066764 RX DQ/DQS(Engine): PASS
7109 11:41:12.069758 TX OE : NO K
7110 11:41:12.069863 All Pass.
7111 11:41:12.069931
7112 11:41:12.069992 DramC Write-DBI off
7113 11:41:12.072698 PER_BANK_REFRESH: Hybrid Mode
7114 11:41:12.076226 TX_TRACKING: ON
7115 11:41:12.083004 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7116 11:41:12.089282 [FAST_K] Save calibration result to emmc
7117 11:41:12.092729 dramc_set_vcore_voltage set vcore to 725000
7118 11:41:12.092832 Read voltage for 1600, 0
7119 11:41:12.095784 Vio18 = 0
7120 11:41:12.095859 Vcore = 725000
7121 11:41:12.095930 Vdram = 0
7122 11:41:12.099340 Vddq = 0
7123 11:41:12.099463 Vmddr = 0
7124 11:41:12.102386 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7125 11:41:12.109413 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7126 11:41:12.112509 MEM_TYPE=3, freq_sel=13
7127 11:41:12.116105 sv_algorithm_assistance_LP4_3733
7128 11:41:12.118955 ============ PULL DRAM RESETB DOWN ============
7129 11:41:12.122439 ========== PULL DRAM RESETB DOWN end =========
7130 11:41:12.129287 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7131 11:41:12.132723 ===================================
7132 11:41:12.132837 LPDDR4 DRAM CONFIGURATION
7133 11:41:12.135627 ===================================
7134 11:41:12.139217 EX_ROW_EN[0] = 0x0
7135 11:41:12.139322 EX_ROW_EN[1] = 0x0
7136 11:41:12.142392 LP4Y_EN = 0x0
7137 11:41:12.142469 WORK_FSP = 0x1
7138 11:41:12.145764 WL = 0x5
7139 11:41:12.145876 RL = 0x5
7140 11:41:12.149217 BL = 0x2
7141 11:41:12.152459 RPST = 0x0
7142 11:41:12.152531 RD_PRE = 0x0
7143 11:41:12.155851 WR_PRE = 0x1
7144 11:41:12.155924 WR_PST = 0x1
7145 11:41:12.158822 DBI_WR = 0x0
7146 11:41:12.158896 DBI_RD = 0x0
7147 11:41:12.162093 OTF = 0x1
7148 11:41:12.165448 ===================================
7149 11:41:12.168988 ===================================
7150 11:41:12.169059 ANA top config
7151 11:41:12.172482 ===================================
7152 11:41:12.175444 DLL_ASYNC_EN = 0
7153 11:41:12.178895 ALL_SLAVE_EN = 0
7154 11:41:12.178971 NEW_RANK_MODE = 1
7155 11:41:12.182446 DLL_IDLE_MODE = 1
7156 11:41:12.185221 LP45_APHY_COMB_EN = 1
7157 11:41:12.188515 TX_ODT_DIS = 0
7158 11:41:12.192011 NEW_8X_MODE = 1
7159 11:41:12.195379 ===================================
7160 11:41:12.195456 ===================================
7161 11:41:12.198961 data_rate = 3200
7162 11:41:12.201991 CKR = 1
7163 11:41:12.205677 DQ_P2S_RATIO = 8
7164 11:41:12.208604 ===================================
7165 11:41:12.211937 CA_P2S_RATIO = 8
7166 11:41:12.215516 DQ_CA_OPEN = 0
7167 11:41:12.218532 DQ_SEMI_OPEN = 0
7168 11:41:12.218615 CA_SEMI_OPEN = 0
7169 11:41:12.222040 CA_FULL_RATE = 0
7170 11:41:12.225084 DQ_CKDIV4_EN = 0
7171 11:41:12.228398 CA_CKDIV4_EN = 0
7172 11:41:12.231753 CA_PREDIV_EN = 0
7173 11:41:12.235284 PH8_DLY = 12
7174 11:41:12.235376 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7175 11:41:12.238694 DQ_AAMCK_DIV = 4
7176 11:41:12.241699 CA_AAMCK_DIV = 4
7177 11:41:12.245244 CA_ADMCK_DIV = 4
7178 11:41:12.248518 DQ_TRACK_CA_EN = 0
7179 11:41:12.251608 CA_PICK = 1600
7180 11:41:12.255050 CA_MCKIO = 1600
7181 11:41:12.255133 MCKIO_SEMI = 0
7182 11:41:12.258248 PLL_FREQ = 3068
7183 11:41:12.261751 DQ_UI_PI_RATIO = 32
7184 11:41:12.265044 CA_UI_PI_RATIO = 0
7185 11:41:12.268273 ===================================
7186 11:41:12.271729 ===================================
7187 11:41:12.275197 memory_type:LPDDR4
7188 11:41:12.275278 GP_NUM : 10
7189 11:41:12.278511 SRAM_EN : 1
7190 11:41:12.281445 MD32_EN : 0
7191 11:41:12.281526 ===================================
7192 11:41:12.284875 [ANA_INIT] >>>>>>>>>>>>>>
7193 11:41:12.288333 <<<<<< [CONFIGURE PHASE]: ANA_TX
7194 11:41:12.291736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7195 11:41:12.295063 ===================================
7196 11:41:12.298472 data_rate = 3200,PCW = 0X7600
7197 11:41:12.301371 ===================================
7198 11:41:12.305028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7199 11:41:12.311526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7200 11:41:12.314850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 11:41:12.321376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7202 11:41:12.324392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7203 11:41:12.327758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7204 11:41:12.327839 [ANA_INIT] flow start
7205 11:41:12.331685 [ANA_INIT] PLL >>>>>>>>
7206 11:41:12.334501 [ANA_INIT] PLL <<<<<<<<
7207 11:41:12.334581 [ANA_INIT] MIDPI >>>>>>>>
7208 11:41:12.337977 [ANA_INIT] MIDPI <<<<<<<<
7209 11:41:12.341393 [ANA_INIT] DLL >>>>>>>>
7210 11:41:12.344472 [ANA_INIT] DLL <<<<<<<<
7211 11:41:12.344553 [ANA_INIT] flow end
7212 11:41:12.347858 ============ LP4 DIFF to SE enter ============
7213 11:41:12.354340 ============ LP4 DIFF to SE exit ============
7214 11:41:12.354421 [ANA_INIT] <<<<<<<<<<<<<
7215 11:41:12.357969 [Flow] Enable top DCM control >>>>>
7216 11:41:12.361274 [Flow] Enable top DCM control <<<<<
7217 11:41:12.364696 Enable DLL master slave shuffle
7218 11:41:12.371529 ==============================================================
7219 11:41:12.371610 Gating Mode config
7220 11:41:12.377663 ==============================================================
7221 11:41:12.381564 Config description:
7222 11:41:12.387894 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7223 11:41:12.394846 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7224 11:41:12.400947 SELPH_MODE 0: By rank 1: By Phase
7225 11:41:12.407927 ==============================================================
7226 11:41:12.410951 GAT_TRACK_EN = 1
7227 11:41:12.411032 RX_GATING_MODE = 2
7228 11:41:12.414566 RX_GATING_TRACK_MODE = 2
7229 11:41:12.417821 SELPH_MODE = 1
7230 11:41:12.420876 PICG_EARLY_EN = 1
7231 11:41:12.424467 VALID_LAT_VALUE = 1
7232 11:41:12.430984 ==============================================================
7233 11:41:12.434534 Enter into Gating configuration >>>>
7234 11:41:12.437976 Exit from Gating configuration <<<<
7235 11:41:12.440832 Enter into DVFS_PRE_config >>>>>
7236 11:41:12.450747 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7237 11:41:12.454189 Exit from DVFS_PRE_config <<<<<
7238 11:41:12.457843 Enter into PICG configuration >>>>
7239 11:41:12.460765 Exit from PICG configuration <<<<
7240 11:41:12.464319 [RX_INPUT] configuration >>>>>
7241 11:41:12.467345 [RX_INPUT] configuration <<<<<
7242 11:41:12.470842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7243 11:41:12.477592 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7244 11:41:12.483888 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 11:41:12.487175 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 11:41:12.494021 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 11:41:12.500737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 11:41:12.504151 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7249 11:41:12.507529 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7250 11:41:12.514000 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7251 11:41:12.517519 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7252 11:41:12.520468 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7253 11:41:12.527539 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7254 11:41:12.530514 ===================================
7255 11:41:12.530596 LPDDR4 DRAM CONFIGURATION
7256 11:41:12.534176 ===================================
7257 11:41:12.537116 EX_ROW_EN[0] = 0x0
7258 11:41:12.540753 EX_ROW_EN[1] = 0x0
7259 11:41:12.540859 LP4Y_EN = 0x0
7260 11:41:12.544096 WORK_FSP = 0x1
7261 11:41:12.544187 WL = 0x5
7262 11:41:12.547295 RL = 0x5
7263 11:41:12.547427 BL = 0x2
7264 11:41:12.550440 RPST = 0x0
7265 11:41:12.550545 RD_PRE = 0x0
7266 11:41:12.554161 WR_PRE = 0x1
7267 11:41:12.554250 WR_PST = 0x1
7268 11:41:12.557188 DBI_WR = 0x0
7269 11:41:12.557296 DBI_RD = 0x0
7270 11:41:12.560554 OTF = 0x1
7271 11:41:12.564243 ===================================
7272 11:41:12.567105 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7273 11:41:12.570387 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7274 11:41:12.577048 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7275 11:41:12.577189 ===================================
7276 11:41:12.580356 LPDDR4 DRAM CONFIGURATION
7277 11:41:12.583700 ===================================
7278 11:41:12.587021 EX_ROW_EN[0] = 0x10
7279 11:41:12.587144 EX_ROW_EN[1] = 0x0
7280 11:41:12.590344 LP4Y_EN = 0x0
7281 11:41:12.590485 WORK_FSP = 0x1
7282 11:41:12.593671 WL = 0x5
7283 11:41:12.593793 RL = 0x5
7284 11:41:12.596801 BL = 0x2
7285 11:41:12.600337 RPST = 0x0
7286 11:41:12.600480 RD_PRE = 0x0
7287 11:41:12.603885 WR_PRE = 0x1
7288 11:41:12.604022 WR_PST = 0x1
7289 11:41:12.606773 DBI_WR = 0x0
7290 11:41:12.606928 DBI_RD = 0x0
7291 11:41:12.610112 OTF = 0x1
7292 11:41:12.613577 ===================================
7293 11:41:12.616639 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7294 11:41:12.619946 ==
7295 11:41:12.623704 Dram Type= 6, Freq= 0, CH_0, rank 0
7296 11:41:12.626750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 11:41:12.626857 ==
7298 11:41:12.630367 [Duty_Offset_Calibration]
7299 11:41:12.630464 B0:2 B1:-1 CA:1
7300 11:41:12.630528
7301 11:41:12.633366 [DutyScan_Calibration_Flow] k_type=0
7302 11:41:12.642573
7303 11:41:12.642670 ==CLK 0==
7304 11:41:12.645969 Final CLK duty delay cell = -4
7305 11:41:12.649501 [-4] MAX Duty = 5031%(X100), DQS PI = 4
7306 11:41:12.652827 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7307 11:41:12.656226 [-4] AVG Duty = 4937%(X100)
7308 11:41:12.656301
7309 11:41:12.659195 CH0 CLK Duty spec in!! Max-Min= 187%
7310 11:41:12.662684 [DutyScan_Calibration_Flow] ====Done====
7311 11:41:12.662755
7312 11:41:12.665539 [DutyScan_Calibration_Flow] k_type=1
7313 11:41:12.682004
7314 11:41:12.682084 ==DQS 0 ==
7315 11:41:12.685230 Final DQS duty delay cell = 0
7316 11:41:12.688566 [0] MAX Duty = 5125%(X100), DQS PI = 56
7317 11:41:12.692173 [0] MIN Duty = 5000%(X100), DQS PI = 14
7318 11:41:12.695461 [0] AVG Duty = 5062%(X100)
7319 11:41:12.695536
7320 11:41:12.695605 ==DQS 1 ==
7321 11:41:12.698881 Final DQS duty delay cell = -4
7322 11:41:12.702114 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7323 11:41:12.705494 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7324 11:41:12.708511 [-4] AVG Duty = 5046%(X100)
7325 11:41:12.708595
7326 11:41:12.711843 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7327 11:41:12.711927
7328 11:41:12.715160 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7329 11:41:12.718782 [DutyScan_Calibration_Flow] ====Done====
7330 11:41:12.718866
7331 11:41:12.721760 [DutyScan_Calibration_Flow] k_type=3
7332 11:41:12.739496
7333 11:41:12.739585 ==DQM 0 ==
7334 11:41:12.743034 Final DQM duty delay cell = 0
7335 11:41:12.746620 [0] MAX Duty = 5000%(X100), DQS PI = 20
7336 11:41:12.749825 [0] MIN Duty = 4875%(X100), DQS PI = 4
7337 11:41:12.749909 [0] AVG Duty = 4937%(X100)
7338 11:41:12.753349
7339 11:41:12.753448 ==DQM 1 ==
7340 11:41:12.756194 Final DQM duty delay cell = 0
7341 11:41:12.759567 [0] MAX Duty = 5218%(X100), DQS PI = 58
7342 11:41:12.763182 [0] MIN Duty = 4969%(X100), DQS PI = 18
7343 11:41:12.763286 [0] AVG Duty = 5093%(X100)
7344 11:41:12.766134
7345 11:41:12.769730 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7346 11:41:12.769827
7347 11:41:12.772739 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7348 11:41:12.776252 [DutyScan_Calibration_Flow] ====Done====
7349 11:41:12.776337
7350 11:41:12.779625 [DutyScan_Calibration_Flow] k_type=2
7351 11:41:12.795893
7352 11:41:12.795991 ==DQ 0 ==
7353 11:41:12.799212 Final DQ duty delay cell = -4
7354 11:41:12.802624 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7355 11:41:12.806262 [-4] MIN Duty = 4844%(X100), DQS PI = 28
7356 11:41:12.808976 [-4] AVG Duty = 4922%(X100)
7357 11:41:12.809052
7358 11:41:12.809114 ==DQ 1 ==
7359 11:41:12.812374 Final DQ duty delay cell = 0
7360 11:41:12.815610 [0] MAX Duty = 5000%(X100), DQS PI = 0
7361 11:41:12.819054 [0] MIN Duty = 4907%(X100), DQS PI = 42
7362 11:41:12.819163 [0] AVG Duty = 4953%(X100)
7363 11:41:12.822547
7364 11:41:12.825842 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7365 11:41:12.825924
7366 11:41:12.829022 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7367 11:41:12.832647 [DutyScan_Calibration_Flow] ====Done====
7368 11:41:12.832736 ==
7369 11:41:12.835533 Dram Type= 6, Freq= 0, CH_1, rank 0
7370 11:41:12.839095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7371 11:41:12.839185 ==
7372 11:41:12.842637 [Duty_Offset_Calibration]
7373 11:41:12.842718 B0:1 B1:1 CA:2
7374 11:41:12.842786
7375 11:41:12.845750 [DutyScan_Calibration_Flow] k_type=0
7376 11:41:12.856206
7377 11:41:12.856323 ==CLK 0==
7378 11:41:12.859524 Final CLK duty delay cell = 0
7379 11:41:12.862829 [0] MAX Duty = 5156%(X100), DQS PI = 24
7380 11:41:12.865915 [0] MIN Duty = 4969%(X100), DQS PI = 42
7381 11:41:12.866021 [0] AVG Duty = 5062%(X100)
7382 11:41:12.869483
7383 11:41:12.873085 CH1 CLK Duty spec in!! Max-Min= 187%
7384 11:41:12.876217 [DutyScan_Calibration_Flow] ====Done====
7385 11:41:12.876315
7386 11:41:12.879512 [DutyScan_Calibration_Flow] k_type=1
7387 11:41:12.896032
7388 11:41:12.896118 ==DQS 0 ==
7389 11:41:12.899565 Final DQS duty delay cell = 0
7390 11:41:12.902882 [0] MAX Duty = 5062%(X100), DQS PI = 22
7391 11:41:12.906137 [0] MIN Duty = 4813%(X100), DQS PI = 50
7392 11:41:12.909220 [0] AVG Duty = 4937%(X100)
7393 11:41:12.909295
7394 11:41:12.909357 ==DQS 1 ==
7395 11:41:12.912793 Final DQS duty delay cell = 0
7396 11:41:12.916319 [0] MAX Duty = 5031%(X100), DQS PI = 18
7397 11:41:12.919013 [0] MIN Duty = 4938%(X100), DQS PI = 14
7398 11:41:12.922534 [0] AVG Duty = 4984%(X100)
7399 11:41:12.922618
7400 11:41:12.926079 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7401 11:41:12.926163
7402 11:41:12.929406 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7403 11:41:12.932343 [DutyScan_Calibration_Flow] ====Done====
7404 11:41:12.932449
7405 11:41:12.935854 [DutyScan_Calibration_Flow] k_type=3
7406 11:41:12.953055
7407 11:41:12.953141 ==DQM 0 ==
7408 11:41:12.955959 Final DQM duty delay cell = 0
7409 11:41:12.959550 [0] MAX Duty = 5156%(X100), DQS PI = 20
7410 11:41:12.962636 [0] MIN Duty = 4876%(X100), DQS PI = 48
7411 11:41:12.966389 [0] AVG Duty = 5016%(X100)
7412 11:41:12.966472
7413 11:41:12.966537 ==DQM 1 ==
7414 11:41:12.969946 Final DQM duty delay cell = 0
7415 11:41:12.972975 [0] MAX Duty = 5156%(X100), DQS PI = 60
7416 11:41:12.976019 [0] MIN Duty = 4907%(X100), DQS PI = 20
7417 11:41:12.979601 [0] AVG Duty = 5031%(X100)
7418 11:41:12.979684
7419 11:41:12.983046 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7420 11:41:12.983149
7421 11:41:12.985918 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7422 11:41:12.989284 [DutyScan_Calibration_Flow] ====Done====
7423 11:41:12.989360
7424 11:41:12.992400 [DutyScan_Calibration_Flow] k_type=2
7425 11:41:13.009944
7426 11:41:13.010043 ==DQ 0 ==
7427 11:41:13.013277 Final DQ duty delay cell = 0
7428 11:41:13.016323 [0] MAX Duty = 5156%(X100), DQS PI = 20
7429 11:41:13.019728 [0] MIN Duty = 4938%(X100), DQS PI = 52
7430 11:41:13.019812 [0] AVG Duty = 5047%(X100)
7431 11:41:13.023134
7432 11:41:13.023248 ==DQ 1 ==
7433 11:41:13.026177 Final DQ duty delay cell = 0
7434 11:41:13.030272 [0] MAX Duty = 5093%(X100), DQS PI = 8
7435 11:41:13.033140 [0] MIN Duty = 5031%(X100), DQS PI = 2
7436 11:41:13.033227 [0] AVG Duty = 5062%(X100)
7437 11:41:13.033294
7438 11:41:13.036710 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7439 11:41:13.036794
7440 11:41:13.039722 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7441 11:41:13.046668 [DutyScan_Calibration_Flow] ====Done====
7442 11:41:13.049786 nWR fixed to 30
7443 11:41:13.049874 [ModeRegInit_LP4] CH0 RK0
7444 11:41:13.052736 [ModeRegInit_LP4] CH0 RK1
7445 11:41:13.056333 [ModeRegInit_LP4] CH1 RK0
7446 11:41:13.056420 [ModeRegInit_LP4] CH1 RK1
7447 11:41:13.059859 match AC timing 5
7448 11:41:13.062855 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7449 11:41:13.066197 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7450 11:41:13.072828 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7451 11:41:13.076347 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7452 11:41:13.082866 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7453 11:41:13.082954 [MiockJmeterHQA]
7454 11:41:13.083041
7455 11:41:13.085887 [DramcMiockJmeter] u1RxGatingPI = 0
7456 11:41:13.089527 0 : 4363, 4137
7457 11:41:13.089615 4 : 4252, 4027
7458 11:41:13.089703 8 : 4252, 4027
7459 11:41:13.092800 12 : 4254, 4029
7460 11:41:13.092889 16 : 4252, 4027
7461 11:41:13.095918 20 : 4253, 4026
7462 11:41:13.096006 24 : 4252, 4027
7463 11:41:13.099541 28 : 4365, 4140
7464 11:41:13.099628 32 : 4252, 4027
7465 11:41:13.102829 36 : 4255, 4029
7466 11:41:13.102932 40 : 4252, 4027
7467 11:41:13.103029 44 : 4363, 4137
7468 11:41:13.106175 48 : 4253, 4026
7469 11:41:13.106278 52 : 4360, 4138
7470 11:41:13.108868 56 : 4249, 4027
7471 11:41:13.108986 60 : 4250, 4027
7472 11:41:13.112184 64 : 4250, 4027
7473 11:41:13.112289 68 : 4252, 4029
7474 11:41:13.115765 72 : 4360, 4138
7475 11:41:13.115872 76 : 4250, 4027
7476 11:41:13.115965 80 : 4361, 4137
7477 11:41:13.119233 84 : 4250, 4027
7478 11:41:13.119335 88 : 4249, 4027
7479 11:41:13.122653 92 : 4250, 4027
7480 11:41:13.122731 96 : 4360, 3626
7481 11:41:13.125618 100 : 4250, 0
7482 11:41:13.125721 104 : 4361, 0
7483 11:41:13.125817 108 : 4360, 0
7484 11:41:13.129059 112 : 4248, 0
7485 11:41:13.129161 116 : 4250, 0
7486 11:41:13.132526 120 : 4360, 0
7487 11:41:13.132633 124 : 4361, 0
7488 11:41:13.132726 128 : 4250, 0
7489 11:41:13.135930 132 : 4250, 0
7490 11:41:13.136038 136 : 4250, 0
7491 11:41:13.136137 140 : 4250, 0
7492 11:41:13.138951 144 : 4360, 0
7493 11:41:13.139059 148 : 4250, 0
7494 11:41:13.142440 152 : 4249, 0
7495 11:41:13.142544 156 : 4249, 0
7496 11:41:13.142648 160 : 4360, 0
7497 11:41:13.145998 164 : 4360, 0
7498 11:41:13.146122 168 : 4249, 0
7499 11:41:13.149088 172 : 4250, 0
7500 11:41:13.149204 176 : 4250, 0
7501 11:41:13.149313 180 : 4250, 0
7502 11:41:13.152147 184 : 4250, 0
7503 11:41:13.152268 188 : 4250, 0
7504 11:41:13.155689 192 : 4250, 0
7505 11:41:13.155798 196 : 4360, 0
7506 11:41:13.155910 200 : 4250, 0
7507 11:41:13.159271 204 : 4250, 0
7508 11:41:13.159389 208 : 4249, 0
7509 11:41:13.162193 212 : 4361, 278
7510 11:41:13.162316 216 : 4249, 3927
7511 11:41:13.162427 220 : 4252, 4029
7512 11:41:13.165721 224 : 4252, 4029
7513 11:41:13.165827 228 : 4250, 4027
7514 11:41:13.169196 232 : 4249, 4027
7515 11:41:13.169303 236 : 4252, 4029
7516 11:41:13.172165 240 : 4250, 4027
7517 11:41:13.172289 244 : 4360, 4138
7518 11:41:13.175280 248 : 4360, 4138
7519 11:41:13.175385 252 : 4248, 4024
7520 11:41:13.178907 256 : 4363, 4140
7521 11:41:13.179032 260 : 4360, 4138
7522 11:41:13.182025 264 : 4250, 4027
7523 11:41:13.182133 268 : 4249, 4027
7524 11:41:13.185434 272 : 4252, 4029
7525 11:41:13.185546 276 : 4250, 4027
7526 11:41:13.188579 280 : 4250, 4027
7527 11:41:13.188685 284 : 4250, 4027
7528 11:41:13.188799 288 : 4249, 4027
7529 11:41:13.192022 292 : 4250, 4027
7530 11:41:13.192146 296 : 4360, 4138
7531 11:41:13.195447 300 : 4360, 4138
7532 11:41:13.195553 304 : 4250, 4027
7533 11:41:13.198766 308 : 4363, 4139
7534 11:41:13.198889 312 : 4360, 4138
7535 11:41:13.202194 316 : 4250, 4027
7536 11:41:13.202304 320 : 4249, 4027
7537 11:41:13.205551 324 : 4252, 4029
7538 11:41:13.205662 328 : 4250, 4027
7539 11:41:13.208834 332 : 4250, 2964
7540 11:41:13.208943 336 : 4249, 60
7541 11:41:13.209044
7542 11:41:13.211640 MIOCK jitter meter ch=0
7543 11:41:13.211742
7544 11:41:13.215033 1T = (336-100) = 236 dly cells
7545 11:41:13.218855 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7546 11:41:13.218957 ==
7547 11:41:13.221694 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 11:41:13.228678 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 11:41:13.228782 ==
7550 11:41:13.232009 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7551 11:41:13.238750 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7552 11:41:13.241653 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7553 11:41:13.248027 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7554 11:41:13.256287 [CA 0] Center 44 (14~75) winsize 62
7555 11:41:13.259220 [CA 1] Center 44 (14~74) winsize 61
7556 11:41:13.262859 [CA 2] Center 39 (10~68) winsize 59
7557 11:41:13.266214 [CA 3] Center 39 (10~68) winsize 59
7558 11:41:13.269168 [CA 4] Center 37 (7~67) winsize 61
7559 11:41:13.272896 [CA 5] Center 37 (7~67) winsize 61
7560 11:41:13.272974
7561 11:41:13.276167 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7562 11:41:13.276242
7563 11:41:13.282983 [CATrainingPosCal] consider 1 rank data
7564 11:41:13.283060 u2DelayCellTimex100 = 275/100 ps
7565 11:41:13.288944 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7566 11:41:13.292544 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7567 11:41:13.296208 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7568 11:41:13.299310 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7569 11:41:13.302807 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7570 11:41:13.305632 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7571 11:41:13.305737
7572 11:41:13.308979 CA PerBit enable=1, Macro0, CA PI delay=37
7573 11:41:13.309082
7574 11:41:13.312481 [CBTSetCACLKResult] CA Dly = 37
7575 11:41:13.315755 CS Dly: 10 (0~41)
7576 11:41:13.319075 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7577 11:41:13.322690 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7578 11:41:13.322793 ==
7579 11:41:13.325959 Dram Type= 6, Freq= 0, CH_0, rank 1
7580 11:41:13.332305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 11:41:13.332417 ==
7582 11:41:13.335733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7583 11:41:13.342461 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7584 11:41:13.345465 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7585 11:41:13.352132 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7586 11:41:13.359858 [CA 0] Center 43 (13~74) winsize 62
7587 11:41:13.363598 [CA 1] Center 43 (13~74) winsize 62
7588 11:41:13.366313 [CA 2] Center 39 (10~69) winsize 60
7589 11:41:13.369868 [CA 3] Center 38 (9~68) winsize 60
7590 11:41:13.373180 [CA 4] Center 37 (7~67) winsize 61
7591 11:41:13.377188 [CA 5] Center 37 (7~67) winsize 61
7592 11:41:13.377288
7593 11:41:13.379641 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7594 11:41:13.379739
7595 11:41:13.386708 [CATrainingPosCal] consider 2 rank data
7596 11:41:13.386791 u2DelayCellTimex100 = 275/100 ps
7597 11:41:13.392674 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7598 11:41:13.396315 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7599 11:41:13.399768 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7600 11:41:13.403044 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7601 11:41:13.406373 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7602 11:41:13.409863 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7603 11:41:13.409944
7604 11:41:13.413273 CA PerBit enable=1, Macro0, CA PI delay=37
7605 11:41:13.413354
7606 11:41:13.415850 [CBTSetCACLKResult] CA Dly = 37
7607 11:41:13.419305 CS Dly: 11 (0~44)
7608 11:41:13.422573 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7609 11:41:13.425986 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7610 11:41:13.426068
7611 11:41:13.429327 ----->DramcWriteLeveling(PI) begin...
7612 11:41:13.429410 ==
7613 11:41:13.432847 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 11:41:13.439145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 11:41:13.439231 ==
7616 11:41:13.442934 Write leveling (Byte 0): 31 => 31
7617 11:41:13.445793 Write leveling (Byte 1): 26 => 26
7618 11:41:13.445905 DramcWriteLeveling(PI) end<-----
7619 11:41:13.449343
7620 11:41:13.449429 ==
7621 11:41:13.452785 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 11:41:13.455751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 11:41:13.455826 ==
7624 11:41:13.459310 [Gating] SW mode calibration
7625 11:41:13.465973 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7626 11:41:13.469709 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7627 11:41:13.476023 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 11:41:13.479479 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 11:41:13.482402 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 11:41:13.489412 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 11:41:13.492388 1 4 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7632 11:41:13.495992 1 4 20 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
7633 11:41:13.502542 1 4 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7634 11:41:13.505834 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7635 11:41:13.508992 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 11:41:13.515683 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 11:41:13.519027 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 11:41:13.522512 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 11:41:13.528826 1 5 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7640 11:41:13.532196 1 5 20 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
7641 11:41:13.535714 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7642 11:41:13.541984 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 11:41:13.545738 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 11:41:13.548586 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 11:41:13.555051 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 11:41:13.558492 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7647 11:41:13.562139 1 6 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7648 11:41:13.568559 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7649 11:41:13.571884 1 6 24 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
7650 11:41:13.574967 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 11:41:13.581856 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 11:41:13.584858 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 11:41:13.588429 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 11:41:13.594780 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 11:41:13.598498 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7656 11:41:13.601531 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7657 11:41:13.608107 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7658 11:41:13.611661 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:41:13.614984 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:41:13.621315 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:41:13.624857 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:41:13.627766 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 11:41:13.634370 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 11:41:13.637834 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 11:41:13.641387 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 11:41:13.648368 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:41:13.650842 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:41:13.654348 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:41:13.661330 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:41:13.664401 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:41:13.667920 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7672 11:41:13.670889 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7673 11:41:13.674323 Total UI for P1: 0, mck2ui 16
7674 11:41:13.677851 best dqsien dly found for B0: ( 1, 9, 16)
7675 11:41:13.684546 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 11:41:13.687545 Total UI for P1: 0, mck2ui 16
7677 11:41:13.691171 best dqsien dly found for B1: ( 1, 9, 20)
7678 11:41:13.694112 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7679 11:41:13.698128 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7680 11:41:13.698210
7681 11:41:13.701094 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7682 11:41:13.704027 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7683 11:41:13.707687 [Gating] SW calibration Done
7684 11:41:13.707770 ==
7685 11:41:13.710706 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 11:41:13.714479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 11:41:13.714562 ==
7688 11:41:13.717471 RX Vref Scan: 0
7689 11:41:13.717553
7690 11:41:13.720870 RX Vref 0 -> 0, step: 1
7691 11:41:13.720952
7692 11:41:13.721017 RX Delay 0 -> 252, step: 8
7693 11:41:13.727198 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7694 11:41:13.730589 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7695 11:41:13.733972 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7696 11:41:13.737344 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7697 11:41:13.740849 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7698 11:41:13.747217 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7699 11:41:13.750510 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7700 11:41:13.753946 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7701 11:41:13.757366 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7702 11:41:13.760547 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7703 11:41:13.767083 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7704 11:41:13.770708 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7705 11:41:13.773730 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7706 11:41:13.777233 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7707 11:41:13.783860 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7708 11:41:13.786708 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7709 11:41:13.786790 ==
7710 11:41:13.790208 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 11:41:13.793800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 11:41:13.793884 ==
7713 11:41:13.793949 DQS Delay:
7714 11:41:13.796740 DQS0 = 0, DQS1 = 0
7715 11:41:13.796822 DQM Delay:
7716 11:41:13.800075 DQM0 = 132, DQM1 = 125
7717 11:41:13.800157 DQ Delay:
7718 11:41:13.803586 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7719 11:41:13.806675 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7720 11:41:13.810257 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =123
7721 11:41:13.816687 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7722 11:41:13.816770
7723 11:41:13.816835
7724 11:41:13.816895 ==
7725 11:41:13.820311 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 11:41:13.823533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 11:41:13.823617 ==
7728 11:41:13.823682
7729 11:41:13.823741
7730 11:41:13.826837 TX Vref Scan disable
7731 11:41:13.826919 == TX Byte 0 ==
7732 11:41:13.833771 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7733 11:41:13.836655 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7734 11:41:13.836738 == TX Byte 1 ==
7735 11:41:13.843333 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7736 11:41:13.846711 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7737 11:41:13.846794 ==
7738 11:41:13.850147 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 11:41:13.853399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 11:41:13.853483 ==
7741 11:41:13.868466
7742 11:41:13.872051 TX Vref early break, caculate TX vref
7743 11:41:13.875015 TX Vref=16, minBit 7, minWin=20, winSum=350
7744 11:41:13.878372 TX Vref=18, minBit 1, minWin=21, winSum=361
7745 11:41:13.881971 TX Vref=20, minBit 0, minWin=22, winSum=369
7746 11:41:13.885404 TX Vref=22, minBit 6, minWin=22, winSum=382
7747 11:41:13.888849 TX Vref=24, minBit 4, minWin=23, winSum=395
7748 11:41:13.894879 TX Vref=26, minBit 0, minWin=24, winSum=404
7749 11:41:13.898548 TX Vref=28, minBit 1, minWin=24, winSum=411
7750 11:41:13.901415 TX Vref=30, minBit 0, minWin=25, winSum=412
7751 11:41:13.904958 TX Vref=32, minBit 0, minWin=24, winSum=399
7752 11:41:13.908208 TX Vref=34, minBit 3, minWin=23, winSum=392
7753 11:41:13.911826 TX Vref=36, minBit 4, minWin=23, winSum=382
7754 11:41:13.918412 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 30
7755 11:41:13.918490
7756 11:41:13.921411 Final TX Range 0 Vref 30
7757 11:41:13.921511
7758 11:41:13.921598 ==
7759 11:41:13.925214 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 11:41:13.928151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 11:41:13.928223 ==
7762 11:41:13.928312
7763 11:41:13.928397
7764 11:41:13.931556 TX Vref Scan disable
7765 11:41:13.938383 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7766 11:41:13.938480 == TX Byte 0 ==
7767 11:41:13.941271 u2DelayCellOfst[0]=17 cells (5 PI)
7768 11:41:13.944755 u2DelayCellOfst[1]=21 cells (6 PI)
7769 11:41:13.948072 u2DelayCellOfst[2]=10 cells (3 PI)
7770 11:41:13.951505 u2DelayCellOfst[3]=14 cells (4 PI)
7771 11:41:13.955036 u2DelayCellOfst[4]=10 cells (3 PI)
7772 11:41:13.957806 u2DelayCellOfst[5]=0 cells (0 PI)
7773 11:41:13.961726 u2DelayCellOfst[6]=21 cells (6 PI)
7774 11:41:13.964476 u2DelayCellOfst[7]=21 cells (6 PI)
7775 11:41:13.967848 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7776 11:41:13.971279 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7777 11:41:13.974846 == TX Byte 1 ==
7778 11:41:13.977871 u2DelayCellOfst[8]=0 cells (0 PI)
7779 11:41:13.981485 u2DelayCellOfst[9]=0 cells (0 PI)
7780 11:41:13.984441 u2DelayCellOfst[10]=7 cells (2 PI)
7781 11:41:13.984526 u2DelayCellOfst[11]=0 cells (0 PI)
7782 11:41:13.988062 u2DelayCellOfst[12]=10 cells (3 PI)
7783 11:41:13.991507 u2DelayCellOfst[13]=10 cells (3 PI)
7784 11:41:13.994504 u2DelayCellOfst[14]=14 cells (4 PI)
7785 11:41:13.998112 u2DelayCellOfst[15]=10 cells (3 PI)
7786 11:41:14.004702 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7787 11:41:14.007748 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7788 11:41:14.007832 DramC Write-DBI on
7789 11:41:14.007897 ==
7790 11:41:14.011487 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 11:41:14.018176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 11:41:14.018261 ==
7793 11:41:14.018326
7794 11:41:14.018386
7795 11:41:14.018444 TX Vref Scan disable
7796 11:41:14.022144 == TX Byte 0 ==
7797 11:41:14.025383 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7798 11:41:14.028447 == TX Byte 1 ==
7799 11:41:14.032215 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7800 11:41:14.035056 DramC Write-DBI off
7801 11:41:14.035139
7802 11:41:14.035203 [DATLAT]
7803 11:41:14.035264 Freq=1600, CH0 RK0
7804 11:41:14.035322
7805 11:41:14.038654 DATLAT Default: 0xf
7806 11:41:14.038745 0, 0xFFFF, sum = 0
7807 11:41:14.041939 1, 0xFFFF, sum = 0
7808 11:41:14.042052 2, 0xFFFF, sum = 0
7809 11:41:14.045168 3, 0xFFFF, sum = 0
7810 11:41:14.048426 4, 0xFFFF, sum = 0
7811 11:41:14.048525 5, 0xFFFF, sum = 0
7812 11:41:14.051847 6, 0xFFFF, sum = 0
7813 11:41:14.051934 7, 0xFFFF, sum = 0
7814 11:41:14.055261 8, 0xFFFF, sum = 0
7815 11:41:14.055345 9, 0xFFFF, sum = 0
7816 11:41:14.058726 10, 0xFFFF, sum = 0
7817 11:41:14.058809 11, 0xFFFF, sum = 0
7818 11:41:14.062137 12, 0xFFFF, sum = 0
7819 11:41:14.062221 13, 0xFFFF, sum = 0
7820 11:41:14.065459 14, 0x0, sum = 1
7821 11:41:14.065543 15, 0x0, sum = 2
7822 11:41:14.068767 16, 0x0, sum = 3
7823 11:41:14.068851 17, 0x0, sum = 4
7824 11:41:14.072043 best_step = 15
7825 11:41:14.072125
7826 11:41:14.072189 ==
7827 11:41:14.075015 Dram Type= 6, Freq= 0, CH_0, rank 0
7828 11:41:14.078793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7829 11:41:14.078877 ==
7830 11:41:14.078941 RX Vref Scan: 1
7831 11:41:14.081774
7832 11:41:14.081857 Set Vref Range= 24 -> 127
7833 11:41:14.081922
7834 11:41:14.085167 RX Vref 24 -> 127, step: 1
7835 11:41:14.085250
7836 11:41:14.088807 RX Delay 11 -> 252, step: 4
7837 11:41:14.088889
7838 11:41:14.092106 Set Vref, RX VrefLevel [Byte0]: 24
7839 11:41:14.094943 [Byte1]: 24
7840 11:41:14.095026
7841 11:41:14.098535 Set Vref, RX VrefLevel [Byte0]: 25
7842 11:41:14.102069 [Byte1]: 25
7843 11:41:14.102166
7844 11:41:14.105055 Set Vref, RX VrefLevel [Byte0]: 26
7845 11:41:14.108570 [Byte1]: 26
7846 11:41:14.112084
7847 11:41:14.115529 Set Vref, RX VrefLevel [Byte0]: 27
7848 11:41:14.119323 [Byte1]: 27
7849 11:41:14.119431
7850 11:41:14.121892 Set Vref, RX VrefLevel [Byte0]: 28
7851 11:41:14.125546 [Byte1]: 28
7852 11:41:14.125648
7853 11:41:14.129220 Set Vref, RX VrefLevel [Byte0]: 29
7854 11:41:14.132116 [Byte1]: 29
7855 11:41:14.132191
7856 11:41:14.135346 Set Vref, RX VrefLevel [Byte0]: 30
7857 11:41:14.138776 [Byte1]: 30
7858 11:41:14.142722
7859 11:41:14.142845 Set Vref, RX VrefLevel [Byte0]: 31
7860 11:41:14.146115 [Byte1]: 31
7861 11:41:14.150583
7862 11:41:14.150696 Set Vref, RX VrefLevel [Byte0]: 32
7863 11:41:14.153981 [Byte1]: 32
7864 11:41:14.158132
7865 11:41:14.158250 Set Vref, RX VrefLevel [Byte0]: 33
7866 11:41:14.161398 [Byte1]: 33
7867 11:41:14.165485
7868 11:41:14.165598 Set Vref, RX VrefLevel [Byte0]: 34
7869 11:41:14.168880 [Byte1]: 34
7870 11:41:14.173304
7871 11:41:14.173409 Set Vref, RX VrefLevel [Byte0]: 35
7872 11:41:14.176711 [Byte1]: 35
7873 11:41:14.180993
7874 11:41:14.181104 Set Vref, RX VrefLevel [Byte0]: 36
7875 11:41:14.184111 [Byte1]: 36
7876 11:41:14.188352
7877 11:41:14.188480 Set Vref, RX VrefLevel [Byte0]: 37
7878 11:41:14.191872 [Byte1]: 37
7879 11:41:14.195953
7880 11:41:14.196063 Set Vref, RX VrefLevel [Byte0]: 38
7881 11:41:14.199955 [Byte1]: 38
7882 11:41:14.203670
7883 11:41:14.203776 Set Vref, RX VrefLevel [Byte0]: 39
7884 11:41:14.207262 [Byte1]: 39
7885 11:41:14.211492
7886 11:41:14.211620 Set Vref, RX VrefLevel [Byte0]: 40
7887 11:41:14.214387 [Byte1]: 40
7888 11:41:14.218991
7889 11:41:14.219103 Set Vref, RX VrefLevel [Byte0]: 41
7890 11:41:14.222521 [Byte1]: 41
7891 11:41:14.226787
7892 11:41:14.226891 Set Vref, RX VrefLevel [Byte0]: 42
7893 11:41:14.229782 [Byte1]: 42
7894 11:41:14.234394
7895 11:41:14.234498 Set Vref, RX VrefLevel [Byte0]: 43
7896 11:41:14.237378 [Byte1]: 43
7897 11:41:14.242142
7898 11:41:14.242225 Set Vref, RX VrefLevel [Byte0]: 44
7899 11:41:14.248316 [Byte1]: 44
7900 11:41:14.248397
7901 11:41:14.251662 Set Vref, RX VrefLevel [Byte0]: 45
7902 11:41:14.255109 [Byte1]: 45
7903 11:41:14.255214
7904 11:41:14.257935 Set Vref, RX VrefLevel [Byte0]: 46
7905 11:41:14.261815 [Byte1]: 46
7906 11:41:14.264708
7907 11:41:14.264794 Set Vref, RX VrefLevel [Byte0]: 47
7908 11:41:14.268186 [Byte1]: 47
7909 11:41:14.272260
7910 11:41:14.272337 Set Vref, RX VrefLevel [Byte0]: 48
7911 11:41:14.275749 [Byte1]: 48
7912 11:41:14.280131
7913 11:41:14.280211 Set Vref, RX VrefLevel [Byte0]: 49
7914 11:41:14.283444 [Byte1]: 49
7915 11:41:14.287332
7916 11:41:14.287419 Set Vref, RX VrefLevel [Byte0]: 50
7917 11:41:14.290821 [Byte1]: 50
7918 11:41:14.295117
7919 11:41:14.295198 Set Vref, RX VrefLevel [Byte0]: 51
7920 11:41:14.298678 [Byte1]: 51
7921 11:41:14.302812
7922 11:41:14.302897 Set Vref, RX VrefLevel [Byte0]: 52
7923 11:41:14.305839 [Byte1]: 52
7924 11:41:14.310606
7925 11:41:14.310687 Set Vref, RX VrefLevel [Byte0]: 53
7926 11:41:14.313511 [Byte1]: 53
7927 11:41:14.317777
7928 11:41:14.317859 Set Vref, RX VrefLevel [Byte0]: 54
7929 11:41:14.321265 [Byte1]: 54
7930 11:41:14.325610
7931 11:41:14.325691 Set Vref, RX VrefLevel [Byte0]: 55
7932 11:41:14.329114 [Byte1]: 55
7933 11:41:14.333270
7934 11:41:14.333351 Set Vref, RX VrefLevel [Byte0]: 56
7935 11:41:14.336605 [Byte1]: 56
7936 11:41:14.340801
7937 11:41:14.340881 Set Vref, RX VrefLevel [Byte0]: 57
7938 11:41:14.344420 [Byte1]: 57
7939 11:41:14.348353
7940 11:41:14.348434 Set Vref, RX VrefLevel [Byte0]: 58
7941 11:41:14.351960 [Byte1]: 58
7942 11:41:14.355833
7943 11:41:14.355914 Set Vref, RX VrefLevel [Byte0]: 59
7944 11:41:14.359209 [Byte1]: 59
7945 11:41:14.363642
7946 11:41:14.363723 Set Vref, RX VrefLevel [Byte0]: 60
7947 11:41:14.366670 [Byte1]: 60
7948 11:41:14.371149
7949 11:41:14.371230 Set Vref, RX VrefLevel [Byte0]: 61
7950 11:41:14.374572 [Byte1]: 61
7951 11:41:14.378606
7952 11:41:14.378715 Set Vref, RX VrefLevel [Byte0]: 62
7953 11:41:14.381989 [Byte1]: 62
7954 11:41:14.386576
7955 11:41:14.386657 Set Vref, RX VrefLevel [Byte0]: 63
7956 11:41:14.389713 [Byte1]: 63
7957 11:41:14.394031
7958 11:41:14.394111 Set Vref, RX VrefLevel [Byte0]: 64
7959 11:41:14.397411 [Byte1]: 64
7960 11:41:14.401871
7961 11:41:14.401952 Set Vref, RX VrefLevel [Byte0]: 65
7962 11:41:14.404803 [Byte1]: 65
7963 11:41:14.409555
7964 11:41:14.409637 Set Vref, RX VrefLevel [Byte0]: 66
7965 11:41:14.412613 [Byte1]: 66
7966 11:41:14.417078
7967 11:41:14.417159 Set Vref, RX VrefLevel [Byte0]: 67
7968 11:41:14.420106 [Byte1]: 67
7969 11:41:14.424712
7970 11:41:14.424794 Set Vref, RX VrefLevel [Byte0]: 68
7971 11:41:14.427870 [Byte1]: 68
7972 11:41:14.432419
7973 11:41:14.432500 Set Vref, RX VrefLevel [Byte0]: 69
7974 11:41:14.435358 [Byte1]: 69
7975 11:41:14.440124
7976 11:41:14.440205 Set Vref, RX VrefLevel [Byte0]: 70
7977 11:41:14.443178 [Byte1]: 70
7978 11:41:14.447333
7979 11:41:14.447438 Set Vref, RX VrefLevel [Byte0]: 71
7980 11:41:14.450783 [Byte1]: 71
7981 11:41:14.454759
7982 11:41:14.454840 Set Vref, RX VrefLevel [Byte0]: 72
7983 11:41:14.458155 [Byte1]: 72
7984 11:41:14.462585
7985 11:41:14.462666 Set Vref, RX VrefLevel [Byte0]: 73
7986 11:41:14.465942 [Byte1]: 73
7987 11:41:14.470528
7988 11:41:14.470623 Set Vref, RX VrefLevel [Byte0]: 74
7989 11:41:14.473351 [Byte1]: 74
7990 11:41:14.477738
7991 11:41:14.477810 Set Vref, RX VrefLevel [Byte0]: 75
7992 11:41:14.481234 [Byte1]: 75
7993 11:41:14.485377
7994 11:41:14.485452 Final RX Vref Byte 0 = 64 to rank0
7995 11:41:14.488611 Final RX Vref Byte 1 = 63 to rank0
7996 11:41:14.491964 Final RX Vref Byte 0 = 64 to rank1
7997 11:41:14.495284 Final RX Vref Byte 1 = 63 to rank1==
7998 11:41:14.498897 Dram Type= 6, Freq= 0, CH_0, rank 0
7999 11:41:14.505271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 11:41:14.505354 ==
8001 11:41:14.505419 DQS Delay:
8002 11:41:14.505478 DQS0 = 0, DQS1 = 0
8003 11:41:14.508825 DQM Delay:
8004 11:41:14.508905 DQM0 = 129, DQM1 = 122
8005 11:41:14.511839 DQ Delay:
8006 11:41:14.515327 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
8007 11:41:14.519019 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8008 11:41:14.522013 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8009 11:41:14.525557 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =132
8010 11:41:14.525641
8011 11:41:14.525707
8012 11:41:14.525768
8013 11:41:14.529627 [DramC_TX_OE_Calibration] TA2
8014 11:41:14.531861 Original DQ_B0 (3 6) =30, OEN = 27
8015 11:41:14.535211 Original DQ_B1 (3 6) =30, OEN = 27
8016 11:41:14.538799 24, 0x0, End_B0=24 End_B1=24
8017 11:41:14.538874 25, 0x0, End_B0=25 End_B1=25
8018 11:41:14.541762 26, 0x0, End_B0=26 End_B1=26
8019 11:41:14.545484 27, 0x0, End_B0=27 End_B1=27
8020 11:41:14.548385 28, 0x0, End_B0=28 End_B1=28
8021 11:41:14.548469 29, 0x0, End_B0=29 End_B1=29
8022 11:41:14.551706 30, 0x0, End_B0=30 End_B1=30
8023 11:41:14.555030 31, 0x4141, End_B0=30 End_B1=30
8024 11:41:14.558551 Byte0 end_step=30 best_step=27
8025 11:41:14.561952 Byte1 end_step=30 best_step=27
8026 11:41:14.565113 Byte0 TX OE(2T, 0.5T) = (3, 3)
8027 11:41:14.568501 Byte1 TX OE(2T, 0.5T) = (3, 3)
8028 11:41:14.568584
8029 11:41:14.568648
8030 11:41:14.575266 [DQSOSCAuto] RK0, (LSB)MR18= 0x1105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
8031 11:41:14.578734 CH0 RK0: MR19=303, MR18=1105
8032 11:41:14.585125 CH0_RK0: MR19=0x303, MR18=0x1105, DQSOSC=401, MR23=63, INC=22, DEC=15
8033 11:41:14.585209
8034 11:41:14.588552 ----->DramcWriteLeveling(PI) begin...
8035 11:41:14.588635 ==
8036 11:41:14.591886 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 11:41:14.595290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 11:41:14.595397 ==
8039 11:41:14.598559 Write leveling (Byte 0): 33 => 33
8040 11:41:14.601664 Write leveling (Byte 1): 26 => 26
8041 11:41:14.605030 DramcWriteLeveling(PI) end<-----
8042 11:41:14.605115
8043 11:41:14.605180 ==
8044 11:41:14.608097 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 11:41:14.611656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 11:41:14.611739 ==
8047 11:41:14.614685 [Gating] SW mode calibration
8048 11:41:14.621781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8049 11:41:14.628321 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8050 11:41:14.631278 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 11:41:14.634775 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 11:41:14.641152 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8053 11:41:14.644679 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8054 11:41:14.648191 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8055 11:41:14.654486 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8056 11:41:14.657868 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 11:41:14.661246 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 11:41:14.667579 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 11:41:14.671187 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8060 11:41:14.674592 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8061 11:41:14.680995 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
8062 11:41:14.684305 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8063 11:41:14.687757 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8064 11:41:14.694664 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8065 11:41:14.697537 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 11:41:14.700946 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 11:41:14.707896 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 11:41:14.710846 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8069 11:41:14.714418 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8070 11:41:14.721038 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8071 11:41:14.724585 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8072 11:41:14.727653 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 11:41:14.734838 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 11:41:14.737683 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 11:41:14.741095 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:41:14.747580 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:41:14.750668 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8078 11:41:14.754206 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8079 11:41:14.760794 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8080 11:41:14.764106 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 11:41:14.767088 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 11:41:14.773776 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:41:14.777842 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:41:14.780939 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:41:14.787277 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:41:14.790592 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:41:14.794188 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:41:14.800738 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:41:14.804155 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:41:14.807006 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:41:14.810372 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8092 11:41:14.817372 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8093 11:41:14.820400 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8094 11:41:14.824106 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8095 11:41:14.826976 Total UI for P1: 0, mck2ui 16
8096 11:41:14.830597 best dqsien dly found for B0: ( 1, 9, 8)
8097 11:41:14.837179 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8098 11:41:14.840379 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 11:41:14.843779 Total UI for P1: 0, mck2ui 16
8100 11:41:14.847277 best dqsien dly found for B1: ( 1, 9, 20)
8101 11:41:14.850079 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8102 11:41:14.853474 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8103 11:41:14.853557
8104 11:41:14.857151 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8105 11:41:14.860324 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8106 11:41:14.863470 [Gating] SW calibration Done
8107 11:41:14.863545 ==
8108 11:41:14.866740 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 11:41:14.873550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 11:41:14.873660 ==
8111 11:41:14.873770 RX Vref Scan: 0
8112 11:41:14.873865
8113 11:41:14.876833 RX Vref 0 -> 0, step: 1
8114 11:41:14.876908
8115 11:41:14.880181 RX Delay 0 -> 252, step: 8
8116 11:41:14.883610 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8117 11:41:14.887162 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8118 11:41:14.890146 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8119 11:41:14.893592 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8120 11:41:14.900189 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8121 11:41:14.903303 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8122 11:41:14.906747 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8123 11:41:14.910097 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8124 11:41:14.913141 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8125 11:41:14.919983 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8126 11:41:14.923012 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8127 11:41:14.926745 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8128 11:41:14.929607 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8129 11:41:14.933232 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8130 11:41:14.939739 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8131 11:41:14.942760 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8132 11:41:14.942838 ==
8133 11:41:14.946207 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 11:41:14.949977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 11:41:14.950083 ==
8136 11:41:14.952871 DQS Delay:
8137 11:41:14.952971 DQS0 = 0, DQS1 = 0
8138 11:41:14.953063 DQM Delay:
8139 11:41:14.956368 DQM0 = 131, DQM1 = 125
8140 11:41:14.956472 DQ Delay:
8141 11:41:14.959288 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8142 11:41:14.962926 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8143 11:41:14.969687 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8144 11:41:14.973058 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8145 11:41:14.973158
8146 11:41:14.973261
8147 11:41:14.973350 ==
8148 11:41:14.976468 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 11:41:14.979624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 11:41:14.979711 ==
8151 11:41:14.979815
8152 11:41:14.979874
8153 11:41:14.983121 TX Vref Scan disable
8154 11:41:14.986415 == TX Byte 0 ==
8155 11:41:14.989304 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8156 11:41:14.992646 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8157 11:41:14.996157 == TX Byte 1 ==
8158 11:41:14.999552 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8159 11:41:15.002944 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8160 11:41:15.003042 ==
8161 11:41:15.005855 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 11:41:15.009326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 11:41:15.012707 ==
8164 11:41:15.025836
8165 11:41:15.028841 TX Vref early break, caculate TX vref
8166 11:41:15.032388 TX Vref=16, minBit 1, minWin=22, winSum=365
8167 11:41:15.035275 TX Vref=18, minBit 9, minWin=22, winSum=376
8168 11:41:15.038925 TX Vref=20, minBit 0, minWin=23, winSum=387
8169 11:41:15.042395 TX Vref=22, minBit 8, minWin=23, winSum=392
8170 11:41:15.045356 TX Vref=24, minBit 1, minWin=24, winSum=404
8171 11:41:15.052448 TX Vref=26, minBit 4, minWin=24, winSum=410
8172 11:41:15.055335 TX Vref=28, minBit 2, minWin=25, winSum=413
8173 11:41:15.058397 TX Vref=30, minBit 4, minWin=25, winSum=416
8174 11:41:15.061997 TX Vref=32, minBit 8, minWin=24, winSum=409
8175 11:41:15.065663 TX Vref=34, minBit 0, minWin=24, winSum=398
8176 11:41:15.068630 TX Vref=36, minBit 4, minWin=23, winSum=390
8177 11:41:15.075259 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 30
8178 11:41:15.075382
8179 11:41:15.078773 Final TX Range 0 Vref 30
8180 11:41:15.078845
8181 11:41:15.078905 ==
8182 11:41:15.082156 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 11:41:15.085578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 11:41:15.085661 ==
8185 11:41:15.085726
8186 11:41:15.085785
8187 11:41:15.088997 TX Vref Scan disable
8188 11:41:15.095264 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8189 11:41:15.095356 == TX Byte 0 ==
8190 11:41:15.098940 u2DelayCellOfst[0]=14 cells (4 PI)
8191 11:41:15.101761 u2DelayCellOfst[1]=17 cells (5 PI)
8192 11:41:15.105197 u2DelayCellOfst[2]=10 cells (3 PI)
8193 11:41:15.108796 u2DelayCellOfst[3]=10 cells (3 PI)
8194 11:41:15.111685 u2DelayCellOfst[4]=10 cells (3 PI)
8195 11:41:15.115398 u2DelayCellOfst[5]=0 cells (0 PI)
8196 11:41:15.118659 u2DelayCellOfst[6]=17 cells (5 PI)
8197 11:41:15.121640 u2DelayCellOfst[7]=17 cells (5 PI)
8198 11:41:15.125044 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8199 11:41:15.128648 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8200 11:41:15.131699 == TX Byte 1 ==
8201 11:41:15.135188 u2DelayCellOfst[8]=0 cells (0 PI)
8202 11:41:15.138913 u2DelayCellOfst[9]=0 cells (0 PI)
8203 11:41:15.139037 u2DelayCellOfst[10]=3 cells (1 PI)
8204 11:41:15.142045 u2DelayCellOfst[11]=0 cells (0 PI)
8205 11:41:15.145462 u2DelayCellOfst[12]=10 cells (3 PI)
8206 11:41:15.148393 u2DelayCellOfst[13]=10 cells (3 PI)
8207 11:41:15.151836 u2DelayCellOfst[14]=14 cells (4 PI)
8208 11:41:15.155340 u2DelayCellOfst[15]=10 cells (3 PI)
8209 11:41:15.158873 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8210 11:41:15.165288 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8211 11:41:15.165448 DramC Write-DBI on
8212 11:41:15.165541 ==
8213 11:41:15.168239 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 11:41:15.174758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 11:41:15.174865 ==
8216 11:41:15.174955
8217 11:41:15.175040
8218 11:41:15.175133 TX Vref Scan disable
8219 11:41:15.179192 == TX Byte 0 ==
8220 11:41:15.182698 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8221 11:41:15.185516 == TX Byte 1 ==
8222 11:41:15.189174 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8223 11:41:15.192519 DramC Write-DBI off
8224 11:41:15.192596
8225 11:41:15.192672 [DATLAT]
8226 11:41:15.192734 Freq=1600, CH0 RK1
8227 11:41:15.192792
8228 11:41:15.195812 DATLAT Default: 0xf
8229 11:41:15.195891 0, 0xFFFF, sum = 0
8230 11:41:15.199220 1, 0xFFFF, sum = 0
8231 11:41:15.199318 2, 0xFFFF, sum = 0
8232 11:41:15.202168 3, 0xFFFF, sum = 0
8233 11:41:15.205583 4, 0xFFFF, sum = 0
8234 11:41:15.205698 5, 0xFFFF, sum = 0
8235 11:41:15.208888 6, 0xFFFF, sum = 0
8236 11:41:15.208969 7, 0xFFFF, sum = 0
8237 11:41:15.212424 8, 0xFFFF, sum = 0
8238 11:41:15.212508 9, 0xFFFF, sum = 0
8239 11:41:15.215814 10, 0xFFFF, sum = 0
8240 11:41:15.215899 11, 0xFFFF, sum = 0
8241 11:41:15.219124 12, 0xFFFF, sum = 0
8242 11:41:15.219205 13, 0xFFFF, sum = 0
8243 11:41:15.222507 14, 0x0, sum = 1
8244 11:41:15.222580 15, 0x0, sum = 2
8245 11:41:15.225791 16, 0x0, sum = 3
8246 11:41:15.225865 17, 0x0, sum = 4
8247 11:41:15.229131 best_step = 15
8248 11:41:15.229211
8249 11:41:15.229274 ==
8250 11:41:15.232707 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 11:41:15.235612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 11:41:15.235702 ==
8253 11:41:15.235796 RX Vref Scan: 0
8254 11:41:15.235890
8255 11:41:15.239209 RX Vref 0 -> 0, step: 1
8256 11:41:15.239305
8257 11:41:15.242713 RX Delay 11 -> 252, step: 4
8258 11:41:15.245551 iDelay=191, Bit 0, Center 128 (71 ~ 186) 116
8259 11:41:15.252682 iDelay=191, Bit 1, Center 128 (75 ~ 182) 108
8260 11:41:15.255681 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8261 11:41:15.259211 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8262 11:41:15.262031 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8263 11:41:15.265271 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8264 11:41:15.272467 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8265 11:41:15.275467 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8266 11:41:15.278619 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8267 11:41:15.282458 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8268 11:41:15.285608 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8269 11:41:15.292200 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8270 11:41:15.295598 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8271 11:41:15.299107 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8272 11:41:15.302353 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8273 11:41:15.305249 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8274 11:41:15.308548 ==
8275 11:41:15.312279 Dram Type= 6, Freq= 0, CH_0, rank 1
8276 11:41:15.315244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 11:41:15.315327 ==
8278 11:41:15.315442 DQS Delay:
8279 11:41:15.318652 DQS0 = 0, DQS1 = 0
8280 11:41:15.318734 DQM Delay:
8281 11:41:15.321990 DQM0 = 127, DQM1 = 122
8282 11:41:15.322086 DQ Delay:
8283 11:41:15.325439 DQ0 =128, DQ1 =128, DQ2 =124, DQ3 =126
8284 11:41:15.328670 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8285 11:41:15.332001 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8286 11:41:15.335578 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8287 11:41:15.335660
8288 11:41:15.335725
8289 11:41:15.335785
8290 11:41:15.338634 [DramC_TX_OE_Calibration] TA2
8291 11:41:15.341676 Original DQ_B0 (3 6) =30, OEN = 27
8292 11:41:15.345218 Original DQ_B1 (3 6) =30, OEN = 27
8293 11:41:15.348818 24, 0x0, End_B0=24 End_B1=24
8294 11:41:15.351890 25, 0x0, End_B0=25 End_B1=25
8295 11:41:15.351974 26, 0x0, End_B0=26 End_B1=26
8296 11:41:15.354838 27, 0x0, End_B0=27 End_B1=27
8297 11:41:15.358284 28, 0x0, End_B0=28 End_B1=28
8298 11:41:15.361778 29, 0x0, End_B0=29 End_B1=29
8299 11:41:15.365365 30, 0x0, End_B0=30 End_B1=30
8300 11:41:15.365449 31, 0x4545, End_B0=30 End_B1=30
8301 11:41:15.368638 Byte0 end_step=30 best_step=27
8302 11:41:15.371498 Byte1 end_step=30 best_step=27
8303 11:41:15.374977 Byte0 TX OE(2T, 0.5T) = (3, 3)
8304 11:41:15.378781 Byte1 TX OE(2T, 0.5T) = (3, 3)
8305 11:41:15.378863
8306 11:41:15.378927
8307 11:41:15.384860 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8308 11:41:15.388314 CH0 RK1: MR19=303, MR18=180D
8309 11:41:15.394718 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8310 11:41:15.398239 [RxdqsGatingPostProcess] freq 1600
8311 11:41:15.404950 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8312 11:41:15.405037 best DQS0 dly(2T, 0.5T) = (1, 1)
8313 11:41:15.408241 best DQS1 dly(2T, 0.5T) = (1, 1)
8314 11:41:15.411802 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8315 11:41:15.414640 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8316 11:41:15.418345 best DQS0 dly(2T, 0.5T) = (1, 1)
8317 11:41:15.421369 best DQS1 dly(2T, 0.5T) = (1, 1)
8318 11:41:15.424738 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8319 11:41:15.428143 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8320 11:41:15.431539 Pre-setting of DQS Precalculation
8321 11:41:15.434861 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8322 11:41:15.434944 ==
8323 11:41:15.438356 Dram Type= 6, Freq= 0, CH_1, rank 0
8324 11:41:15.444872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 11:41:15.444955 ==
8326 11:41:15.447923 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 11:41:15.454417 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 11:41:15.458024 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 11:41:15.464482 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 11:41:15.472029 [CA 0] Center 43 (15~72) winsize 58
8331 11:41:15.475304 [CA 1] Center 43 (14~72) winsize 59
8332 11:41:15.478874 [CA 2] Center 38 (9~67) winsize 59
8333 11:41:15.482480 [CA 3] Center 37 (8~66) winsize 59
8334 11:41:15.485403 [CA 4] Center 38 (9~68) winsize 60
8335 11:41:15.488931 [CA 5] Center 37 (8~66) winsize 59
8336 11:41:15.489014
8337 11:41:15.492172 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8338 11:41:15.492280
8339 11:41:15.495316 [CATrainingPosCal] consider 1 rank data
8340 11:41:15.498528 u2DelayCellTimex100 = 275/100 ps
8341 11:41:15.501845 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8342 11:41:15.508608 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8343 11:41:15.512024 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8344 11:41:15.515586 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8345 11:41:15.518922 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8346 11:41:15.522150 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8347 11:41:15.522250
8348 11:41:15.525251 CA PerBit enable=1, Macro0, CA PI delay=37
8349 11:41:15.525325
8350 11:41:15.528505 [CBTSetCACLKResult] CA Dly = 37
8351 11:41:15.531885 CS Dly: 9 (0~40)
8352 11:41:15.535371 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 11:41:15.538211 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 11:41:15.538285 ==
8355 11:41:15.541553 Dram Type= 6, Freq= 0, CH_1, rank 1
8356 11:41:15.545088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 11:41:15.548850 ==
8358 11:41:15.551889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8359 11:41:15.555138 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8360 11:41:15.561716 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8361 11:41:15.564672 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8362 11:41:15.575306 [CA 0] Center 43 (14~73) winsize 60
8363 11:41:15.578527 [CA 1] Center 43 (14~72) winsize 59
8364 11:41:15.581770 [CA 2] Center 38 (9~67) winsize 59
8365 11:41:15.585150 [CA 3] Center 37 (9~66) winsize 58
8366 11:41:15.588753 [CA 4] Center 38 (8~68) winsize 61
8367 11:41:15.591664 [CA 5] Center 36 (7~66) winsize 60
8368 11:41:15.591743
8369 11:41:15.595291 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8370 11:41:15.595404
8371 11:41:15.598846 [CATrainingPosCal] consider 2 rank data
8372 11:41:15.601566 u2DelayCellTimex100 = 275/100 ps
8373 11:41:15.608278 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8374 11:41:15.611753 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8375 11:41:15.615194 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8376 11:41:15.618517 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8377 11:41:15.621913 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8378 11:41:15.624857 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8379 11:41:15.624937
8380 11:41:15.628351 CA PerBit enable=1, Macro0, CA PI delay=37
8381 11:41:15.628433
8382 11:41:15.631723 [CBTSetCACLKResult] CA Dly = 37
8383 11:41:15.635169 CS Dly: 10 (0~43)
8384 11:41:15.638324 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8385 11:41:15.641771 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8386 11:41:15.641852
8387 11:41:15.644549 ----->DramcWriteLeveling(PI) begin...
8388 11:41:15.644630 ==
8389 11:41:15.648182 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 11:41:15.654618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 11:41:15.654698 ==
8392 11:41:15.658022 Write leveling (Byte 0): 25 => 25
8393 11:41:15.658102 Write leveling (Byte 1): 28 => 28
8394 11:41:15.661731 DramcWriteLeveling(PI) end<-----
8395 11:41:15.661810
8396 11:41:15.661871 ==
8397 11:41:15.664688 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 11:41:15.671257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 11:41:15.671336 ==
8400 11:41:15.674697 [Gating] SW mode calibration
8401 11:41:15.681514 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8402 11:41:15.685026 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8403 11:41:15.691566 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 11:41:15.695095 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 11:41:15.698234 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:41:15.704373 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 11:41:15.707864 1 4 16 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
8408 11:41:15.710995 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 11:41:15.717924 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 11:41:15.721081 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 11:41:15.724436 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 11:41:15.731229 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 11:41:15.734585 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 11:41:15.738108 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8415 11:41:15.744284 1 5 16 | B1->B0 | 2c2c 3232 | 0 0 | (1 0) (0 1)
8416 11:41:15.747752 1 5 20 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
8417 11:41:15.751244 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 11:41:15.757858 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 11:41:15.760943 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:41:15.764497 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:41:15.771048 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:41:15.774058 1 6 12 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
8423 11:41:15.777079 1 6 16 | B1->B0 | 3535 2c2c | 0 0 | (0 0) (0 0)
8424 11:41:15.784087 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 11:41:15.787477 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 11:41:15.790561 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 11:41:15.797106 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 11:41:15.800661 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 11:41:15.803663 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:41:15.806919 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 11:41:15.813851 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8432 11:41:15.817071 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8433 11:41:15.820451 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 11:41:15.827029 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 11:41:15.830475 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:41:15.833901 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:41:15.840085 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:41:15.843458 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:41:15.846836 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:41:15.853711 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:41:15.856787 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:41:15.860334 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:41:15.866919 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:41:15.869894 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:41:15.873457 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 11:41:15.879928 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8447 11:41:15.882973 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8448 11:41:15.886355 Total UI for P1: 0, mck2ui 16
8449 11:41:15.889831 best dqsien dly found for B0: ( 1, 9, 12)
8450 11:41:15.892880 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 11:41:15.896444 Total UI for P1: 0, mck2ui 16
8452 11:41:15.899442 best dqsien dly found for B1: ( 1, 9, 16)
8453 11:41:15.903053 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8454 11:41:15.906559 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8455 11:41:15.906644
8456 11:41:15.912771 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8457 11:41:15.916216 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8458 11:41:15.919777 [Gating] SW calibration Done
8459 11:41:15.919859 ==
8460 11:41:15.923139 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 11:41:15.926235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 11:41:15.926324 ==
8463 11:41:15.926436 RX Vref Scan: 0
8464 11:41:15.929646
8465 11:41:15.929727 RX Vref 0 -> 0, step: 1
8466 11:41:15.929802
8467 11:41:15.933025 RX Delay 0 -> 252, step: 8
8468 11:41:15.935952 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8469 11:41:15.939516 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8470 11:41:15.946267 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8471 11:41:15.949741 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8472 11:41:15.952549 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8473 11:41:15.956104 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8474 11:41:15.959070 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8475 11:41:15.966063 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8476 11:41:15.969586 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8477 11:41:15.972491 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8478 11:41:15.976053 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8479 11:41:15.979318 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8480 11:41:15.985927 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8481 11:41:15.989003 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8482 11:41:15.992480 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8483 11:41:15.996013 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8484 11:41:15.996095 ==
8485 11:41:15.998818 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 11:41:16.005463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 11:41:16.005567 ==
8488 11:41:16.005663 DQS Delay:
8489 11:41:16.009162 DQS0 = 0, DQS1 = 0
8490 11:41:16.009245 DQM Delay:
8491 11:41:16.009310 DQM0 = 134, DQM1 = 127
8492 11:41:16.012156 DQ Delay:
8493 11:41:16.015570 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8494 11:41:16.018482 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8495 11:41:16.021819 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8496 11:41:16.025728 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8497 11:41:16.025842
8498 11:41:16.025939
8499 11:41:16.026043 ==
8500 11:41:16.028487 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 11:41:16.035216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 11:41:16.035323 ==
8503 11:41:16.035477
8504 11:41:16.035566
8505 11:41:16.035657 TX Vref Scan disable
8506 11:41:16.038765 == TX Byte 0 ==
8507 11:41:16.042092 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8508 11:41:16.048531 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8509 11:41:16.048665 == TX Byte 1 ==
8510 11:41:16.051921 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8511 11:41:16.058732 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8512 11:41:16.058837 ==
8513 11:41:16.062176 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 11:41:16.065113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 11:41:16.065215 ==
8516 11:41:16.077494
8517 11:41:16.081052 TX Vref early break, caculate TX vref
8518 11:41:16.083942 TX Vref=16, minBit 5, minWin=21, winSum=358
8519 11:41:16.087602 TX Vref=18, minBit 8, minWin=21, winSum=374
8520 11:41:16.090597 TX Vref=20, minBit 8, minWin=22, winSum=381
8521 11:41:16.094633 TX Vref=22, minBit 8, minWin=23, winSum=396
8522 11:41:16.097523 TX Vref=24, minBit 0, minWin=24, winSum=402
8523 11:41:16.104051 TX Vref=26, minBit 8, minWin=24, winSum=413
8524 11:41:16.107643 TX Vref=28, minBit 8, minWin=25, winSum=420
8525 11:41:16.111048 TX Vref=30, minBit 8, minWin=24, winSum=414
8526 11:41:16.113983 TX Vref=32, minBit 11, minWin=24, winSum=407
8527 11:41:16.117358 TX Vref=34, minBit 8, minWin=23, winSum=398
8528 11:41:16.123860 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8529 11:41:16.123944
8530 11:41:16.127267 Final TX Range 0 Vref 28
8531 11:41:16.127413
8532 11:41:16.127504 ==
8533 11:41:16.130709 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 11:41:16.134157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 11:41:16.134257 ==
8536 11:41:16.134346
8537 11:41:16.134432
8538 11:41:16.137597 TX Vref Scan disable
8539 11:41:16.143782 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8540 11:41:16.143891 == TX Byte 0 ==
8541 11:41:16.147318 u2DelayCellOfst[0]=17 cells (5 PI)
8542 11:41:16.150740 u2DelayCellOfst[1]=10 cells (3 PI)
8543 11:41:16.153549 u2DelayCellOfst[2]=0 cells (0 PI)
8544 11:41:16.157125 u2DelayCellOfst[3]=7 cells (2 PI)
8545 11:41:16.160433 u2DelayCellOfst[4]=7 cells (2 PI)
8546 11:41:16.163745 u2DelayCellOfst[5]=21 cells (6 PI)
8547 11:41:16.167082 u2DelayCellOfst[6]=17 cells (5 PI)
8548 11:41:16.167189 u2DelayCellOfst[7]=7 cells (2 PI)
8549 11:41:16.173949 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8550 11:41:16.176892 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8551 11:41:16.176994 == TX Byte 1 ==
8552 11:41:16.180522 u2DelayCellOfst[8]=0 cells (0 PI)
8553 11:41:16.183580 u2DelayCellOfst[9]=3 cells (1 PI)
8554 11:41:16.187092 u2DelayCellOfst[10]=10 cells (3 PI)
8555 11:41:16.190295 u2DelayCellOfst[11]=7 cells (2 PI)
8556 11:41:16.193852 u2DelayCellOfst[12]=14 cells (4 PI)
8557 11:41:16.196860 u2DelayCellOfst[13]=17 cells (5 PI)
8558 11:41:16.200312 u2DelayCellOfst[14]=17 cells (5 PI)
8559 11:41:16.203854 u2DelayCellOfst[15]=17 cells (5 PI)
8560 11:41:16.207463 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8561 11:41:16.213983 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8562 11:41:16.214088 DramC Write-DBI on
8563 11:41:16.214191 ==
8564 11:41:16.216891 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 11:41:16.220444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 11:41:16.220527 ==
8567 11:41:16.223815
8568 11:41:16.223897
8569 11:41:16.223961 TX Vref Scan disable
8570 11:41:16.227198 == TX Byte 0 ==
8571 11:41:16.230007 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8572 11:41:16.233333 == TX Byte 1 ==
8573 11:41:16.237275 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8574 11:41:16.237358 DramC Write-DBI off
8575 11:41:16.240036
8576 11:41:16.240117 [DATLAT]
8577 11:41:16.240181 Freq=1600, CH1 RK0
8578 11:41:16.240241
8579 11:41:16.243333 DATLAT Default: 0xf
8580 11:41:16.243438 0, 0xFFFF, sum = 0
8581 11:41:16.246786 1, 0xFFFF, sum = 0
8582 11:41:16.246869 2, 0xFFFF, sum = 0
8583 11:41:16.250222 3, 0xFFFF, sum = 0
8584 11:41:16.253619 4, 0xFFFF, sum = 0
8585 11:41:16.253701 5, 0xFFFF, sum = 0
8586 11:41:16.257041 6, 0xFFFF, sum = 0
8587 11:41:16.257124 7, 0xFFFF, sum = 0
8588 11:41:16.259947 8, 0xFFFF, sum = 0
8589 11:41:16.260030 9, 0xFFFF, sum = 0
8590 11:41:16.263298 10, 0xFFFF, sum = 0
8591 11:41:16.263404 11, 0xFFFF, sum = 0
8592 11:41:16.266684 12, 0xFFFF, sum = 0
8593 11:41:16.266767 13, 0xFFFF, sum = 0
8594 11:41:16.270107 14, 0x0, sum = 1
8595 11:41:16.270189 15, 0x0, sum = 2
8596 11:41:16.273017 16, 0x0, sum = 3
8597 11:41:16.273099 17, 0x0, sum = 4
8598 11:41:16.276614 best_step = 15
8599 11:41:16.276695
8600 11:41:16.276759 ==
8601 11:41:16.279827 Dram Type= 6, Freq= 0, CH_1, rank 0
8602 11:41:16.283482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8603 11:41:16.283565 ==
8604 11:41:16.286415 RX Vref Scan: 1
8605 11:41:16.286496
8606 11:41:16.286559 Set Vref Range= 24 -> 127
8607 11:41:16.286619
8608 11:41:16.290089 RX Vref 24 -> 127, step: 1
8609 11:41:16.290170
8610 11:41:16.292996 RX Delay 19 -> 252, step: 4
8611 11:41:16.293103
8612 11:41:16.296094 Set Vref, RX VrefLevel [Byte0]: 24
8613 11:41:16.299680 [Byte1]: 24
8614 11:41:16.299761
8615 11:41:16.302694 Set Vref, RX VrefLevel [Byte0]: 25
8616 11:41:16.306109 [Byte1]: 25
8617 11:41:16.309703
8618 11:41:16.309787 Set Vref, RX VrefLevel [Byte0]: 26
8619 11:41:16.312695 [Byte1]: 26
8620 11:41:16.317405
8621 11:41:16.317487 Set Vref, RX VrefLevel [Byte0]: 27
8622 11:41:16.320292 [Byte1]: 27
8623 11:41:16.324754
8624 11:41:16.324837 Set Vref, RX VrefLevel [Byte0]: 28
8625 11:41:16.328124 [Byte1]: 28
8626 11:41:16.332147
8627 11:41:16.332229 Set Vref, RX VrefLevel [Byte0]: 29
8628 11:41:16.335468 [Byte1]: 29
8629 11:41:16.339950
8630 11:41:16.340033 Set Vref, RX VrefLevel [Byte0]: 30
8631 11:41:16.342911 [Byte1]: 30
8632 11:41:16.347295
8633 11:41:16.347433 Set Vref, RX VrefLevel [Byte0]: 31
8634 11:41:16.350625 [Byte1]: 31
8635 11:41:16.355166
8636 11:41:16.355247 Set Vref, RX VrefLevel [Byte0]: 32
8637 11:41:16.358056 [Byte1]: 32
8638 11:41:16.362651
8639 11:41:16.362728 Set Vref, RX VrefLevel [Byte0]: 33
8640 11:41:16.365585 [Byte1]: 33
8641 11:41:16.369915
8642 11:41:16.369995 Set Vref, RX VrefLevel [Byte0]: 34
8643 11:41:16.373279 [Byte1]: 34
8644 11:41:16.377700
8645 11:41:16.377802 Set Vref, RX VrefLevel [Byte0]: 35
8646 11:41:16.381182 [Byte1]: 35
8647 11:41:16.385498
8648 11:41:16.385578 Set Vref, RX VrefLevel [Byte0]: 36
8649 11:41:16.388341 [Byte1]: 36
8650 11:41:16.392650
8651 11:41:16.392730 Set Vref, RX VrefLevel [Byte0]: 37
8652 11:41:16.396196 [Byte1]: 37
8653 11:41:16.400485
8654 11:41:16.400578 Set Vref, RX VrefLevel [Byte0]: 38
8655 11:41:16.404065 [Byte1]: 38
8656 11:41:16.408119
8657 11:41:16.408208 Set Vref, RX VrefLevel [Byte0]: 39
8658 11:41:16.411008 [Byte1]: 39
8659 11:41:16.415863
8660 11:41:16.415944 Set Vref, RX VrefLevel [Byte0]: 40
8661 11:41:16.418819 [Byte1]: 40
8662 11:41:16.422869
8663 11:41:16.422951 Set Vref, RX VrefLevel [Byte0]: 41
8664 11:41:16.426438 [Byte1]: 41
8665 11:41:16.430912
8666 11:41:16.430994 Set Vref, RX VrefLevel [Byte0]: 42
8667 11:41:16.433753 [Byte1]: 42
8668 11:41:16.438342
8669 11:41:16.438424 Set Vref, RX VrefLevel [Byte0]: 43
8670 11:41:16.441559 [Byte1]: 43
8671 11:41:16.445875
8672 11:41:16.445957 Set Vref, RX VrefLevel [Byte0]: 44
8673 11:41:16.449353 [Byte1]: 44
8674 11:41:16.453344
8675 11:41:16.453426 Set Vref, RX VrefLevel [Byte0]: 45
8676 11:41:16.456460 [Byte1]: 45
8677 11:41:16.461118
8678 11:41:16.461200 Set Vref, RX VrefLevel [Byte0]: 46
8679 11:41:16.464458 [Byte1]: 46
8680 11:41:16.468456
8681 11:41:16.468538 Set Vref, RX VrefLevel [Byte0]: 47
8682 11:41:16.471657 [Byte1]: 47
8683 11:41:16.475918
8684 11:41:16.476000 Set Vref, RX VrefLevel [Byte0]: 48
8685 11:41:16.479152 [Byte1]: 48
8686 11:41:16.483617
8687 11:41:16.483700 Set Vref, RX VrefLevel [Byte0]: 49
8688 11:41:16.487087 [Byte1]: 49
8689 11:41:16.491249
8690 11:41:16.491384 Set Vref, RX VrefLevel [Byte0]: 50
8691 11:41:16.494904 [Byte1]: 50
8692 11:41:16.498572
8693 11:41:16.498653 Set Vref, RX VrefLevel [Byte0]: 51
8694 11:41:16.502169 [Byte1]: 51
8695 11:41:16.506410
8696 11:41:16.506518 Set Vref, RX VrefLevel [Byte0]: 52
8697 11:41:16.509779 [Byte1]: 52
8698 11:41:16.514284
8699 11:41:16.514366 Set Vref, RX VrefLevel [Byte0]: 53
8700 11:41:16.517218 [Byte1]: 53
8701 11:41:16.521414
8702 11:41:16.521496 Set Vref, RX VrefLevel [Byte0]: 54
8703 11:41:16.525029 [Byte1]: 54
8704 11:41:16.529384
8705 11:41:16.529466 Set Vref, RX VrefLevel [Byte0]: 55
8706 11:41:16.535254 [Byte1]: 55
8707 11:41:16.535384
8708 11:41:16.539090 Set Vref, RX VrefLevel [Byte0]: 56
8709 11:41:16.542109 [Byte1]: 56
8710 11:41:16.542225
8711 11:41:16.545216 Set Vref, RX VrefLevel [Byte0]: 57
8712 11:41:16.548736 [Byte1]: 57
8713 11:41:16.548820
8714 11:41:16.552223 Set Vref, RX VrefLevel [Byte0]: 58
8715 11:41:16.555493 [Byte1]: 58
8716 11:41:16.559408
8717 11:41:16.559490 Set Vref, RX VrefLevel [Byte0]: 59
8718 11:41:16.562448 [Byte1]: 59
8719 11:41:16.567228
8720 11:41:16.567336 Set Vref, RX VrefLevel [Byte0]: 60
8721 11:41:16.570115 [Byte1]: 60
8722 11:41:16.574463
8723 11:41:16.574545 Set Vref, RX VrefLevel [Byte0]: 61
8724 11:41:16.577942 [Byte1]: 61
8725 11:41:16.581972
8726 11:41:16.582054 Set Vref, RX VrefLevel [Byte0]: 62
8727 11:41:16.585409 [Byte1]: 62
8728 11:41:16.589972
8729 11:41:16.590054 Set Vref, RX VrefLevel [Byte0]: 63
8730 11:41:16.592937 [Byte1]: 63
8731 11:41:16.597086
8732 11:41:16.597167 Set Vref, RX VrefLevel [Byte0]: 64
8733 11:41:16.600660 [Byte1]: 64
8734 11:41:16.604846
8735 11:41:16.604976 Set Vref, RX VrefLevel [Byte0]: 65
8736 11:41:16.607839 [Byte1]: 65
8737 11:41:16.612759
8738 11:41:16.612841 Set Vref, RX VrefLevel [Byte0]: 66
8739 11:41:16.615649 [Byte1]: 66
8740 11:41:16.619757
8741 11:41:16.619839 Set Vref, RX VrefLevel [Byte0]: 67
8742 11:41:16.623248 [Byte1]: 67
8743 11:41:16.627542
8744 11:41:16.627624 Set Vref, RX VrefLevel [Byte0]: 68
8745 11:41:16.631018 [Byte1]: 68
8746 11:41:16.635259
8747 11:41:16.635396 Set Vref, RX VrefLevel [Byte0]: 69
8748 11:41:16.638092 [Byte1]: 69
8749 11:41:16.642662
8750 11:41:16.642744 Set Vref, RX VrefLevel [Byte0]: 70
8751 11:41:16.645966 [Byte1]: 70
8752 11:41:16.650141
8753 11:41:16.650252 Set Vref, RX VrefLevel [Byte0]: 71
8754 11:41:16.653554 [Byte1]: 71
8755 11:41:16.658033
8756 11:41:16.658136 Set Vref, RX VrefLevel [Byte0]: 72
8757 11:41:16.661265 [Byte1]: 72
8758 11:41:16.665332
8759 11:41:16.665433 Set Vref, RX VrefLevel [Byte0]: 73
8760 11:41:16.668334 [Byte1]: 73
8761 11:41:16.672913
8762 11:41:16.673021 Final RX Vref Byte 0 = 60 to rank0
8763 11:41:16.676149 Final RX Vref Byte 1 = 59 to rank0
8764 11:41:16.679681 Final RX Vref Byte 0 = 60 to rank1
8765 11:41:16.683052 Final RX Vref Byte 1 = 59 to rank1==
8766 11:41:16.686015 Dram Type= 6, Freq= 0, CH_1, rank 0
8767 11:41:16.692460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 11:41:16.692566 ==
8769 11:41:16.692661 DQS Delay:
8770 11:41:16.692754 DQS0 = 0, DQS1 = 0
8771 11:41:16.696148 DQM Delay:
8772 11:41:16.696249 DQM0 = 131, DQM1 = 124
8773 11:41:16.699497 DQ Delay:
8774 11:41:16.703053 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =130
8775 11:41:16.705950 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8776 11:41:16.709525 DQ8 =110, DQ9 =114, DQ10 =126, DQ11 =118
8777 11:41:16.712432 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =132
8778 11:41:16.712538
8779 11:41:16.712648
8780 11:41:16.712740
8781 11:41:16.716018 [DramC_TX_OE_Calibration] TA2
8782 11:41:16.719638 Original DQ_B0 (3 6) =30, OEN = 27
8783 11:41:16.722865 Original DQ_B1 (3 6) =30, OEN = 27
8784 11:41:16.725916 24, 0x0, End_B0=24 End_B1=24
8785 11:41:16.726021 25, 0x0, End_B0=25 End_B1=25
8786 11:41:16.729429 26, 0x0, End_B0=26 End_B1=26
8787 11:41:16.732458 27, 0x0, End_B0=27 End_B1=27
8788 11:41:16.735986 28, 0x0, End_B0=28 End_B1=28
8789 11:41:16.739404 29, 0x0, End_B0=29 End_B1=29
8790 11:41:16.739516 30, 0x0, End_B0=30 End_B1=30
8791 11:41:16.742461 31, 0x4141, End_B0=30 End_B1=30
8792 11:41:16.745629 Byte0 end_step=30 best_step=27
8793 11:41:16.749470 Byte1 end_step=30 best_step=27
8794 11:41:16.752434 Byte0 TX OE(2T, 0.5T) = (3, 3)
8795 11:41:16.755890 Byte1 TX OE(2T, 0.5T) = (3, 3)
8796 11:41:16.755994
8797 11:41:16.756086
8798 11:41:16.762607 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8799 11:41:16.765854 CH1 RK0: MR19=302, MR18=12FE
8800 11:41:16.772290 CH1_RK0: MR19=0x302, MR18=0x12FE, DQSOSC=400, MR23=63, INC=23, DEC=15
8801 11:41:16.772397
8802 11:41:16.775663 ----->DramcWriteLeveling(PI) begin...
8803 11:41:16.775776 ==
8804 11:41:16.779316 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 11:41:16.782493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 11:41:16.782598 ==
8807 11:41:16.785765 Write leveling (Byte 0): 26 => 26
8808 11:41:16.789060 Write leveling (Byte 1): 27 => 27
8809 11:41:16.792487 DramcWriteLeveling(PI) end<-----
8810 11:41:16.792594
8811 11:41:16.792687 ==
8812 11:41:16.795951 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 11:41:16.798892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 11:41:16.798998 ==
8815 11:41:16.802441 [Gating] SW mode calibration
8816 11:41:16.809032 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8817 11:41:16.815635 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8818 11:41:16.819095 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 11:41:16.822090 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 11:41:16.829045 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8821 11:41:16.832426 1 4 12 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8822 11:41:16.835441 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 11:41:16.842006 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8824 11:41:16.845737 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8825 11:41:16.849104 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 11:41:16.855759 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 11:41:16.858772 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 11:41:16.862152 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
8829 11:41:16.868508 1 5 12 | B1->B0 | 3232 2424 | 0 0 | (0 1) (1 0)
8830 11:41:16.871867 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8831 11:41:16.875541 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8832 11:41:16.881867 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 11:41:16.885371 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 11:41:16.888807 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 11:41:16.895466 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:41:16.898689 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8837 11:41:16.901677 1 6 12 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
8838 11:41:16.908180 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 11:41:16.911789 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 11:41:16.915341 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 11:41:16.921385 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 11:41:16.925055 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 11:41:16.928531 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 11:41:16.934754 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8845 11:41:16.938339 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8846 11:41:16.941467 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8847 11:41:16.947974 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 11:41:16.951668 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:41:16.954784 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:41:16.961297 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 11:41:16.964729 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 11:41:16.968286 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 11:41:16.974728 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 11:41:16.978089 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 11:41:16.981680 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 11:41:16.984531 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 11:41:16.991509 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 11:41:16.994879 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 11:41:16.998322 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 11:41:17.004926 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8861 11:41:17.007855 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8862 11:41:17.011465 Total UI for P1: 0, mck2ui 16
8863 11:41:17.014451 best dqsien dly found for B0: ( 1, 9, 8)
8864 11:41:17.018060 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8865 11:41:17.024664 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 11:41:17.027648 Total UI for P1: 0, mck2ui 16
8867 11:41:17.031153 best dqsien dly found for B1: ( 1, 9, 14)
8868 11:41:17.034604 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8869 11:41:17.037977 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8870 11:41:17.038081
8871 11:41:17.040944 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8872 11:41:17.044668 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8873 11:41:17.048211 [Gating] SW calibration Done
8874 11:41:17.048318 ==
8875 11:41:17.051129 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 11:41:17.054512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 11:41:17.054598 ==
8878 11:41:17.058067 RX Vref Scan: 0
8879 11:41:17.058314
8880 11:41:17.058463 RX Vref 0 -> 0, step: 1
8881 11:41:17.061054
8882 11:41:17.061162 RX Delay 0 -> 252, step: 8
8883 11:41:17.064468 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8884 11:41:17.071132 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8885 11:41:17.074555 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8886 11:41:17.077835 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8887 11:41:17.081167 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8888 11:41:17.084514 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8889 11:41:17.090682 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8890 11:41:17.094376 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8891 11:41:17.097212 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8892 11:41:17.100563 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8893 11:41:17.103984 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8894 11:41:17.110929 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8895 11:41:17.113772 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8896 11:41:17.117376 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8897 11:41:17.120376 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8898 11:41:17.127024 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8899 11:41:17.127128 ==
8900 11:41:17.130502 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 11:41:17.134188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 11:41:17.134286 ==
8903 11:41:17.134375 DQS Delay:
8904 11:41:17.137777 DQS0 = 0, DQS1 = 0
8905 11:41:17.137873 DQM Delay:
8906 11:41:17.140599 DQM0 = 133, DQM1 = 128
8907 11:41:17.140694 DQ Delay:
8908 11:41:17.144144 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8909 11:41:17.147723 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8910 11:41:17.150507 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8911 11:41:17.154180 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8912 11:41:17.154248
8913 11:41:17.154307
8914 11:41:17.154364 ==
8915 11:41:17.157606 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 11:41:17.164089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 11:41:17.164188 ==
8918 11:41:17.164277
8919 11:41:17.164362
8920 11:41:17.164445 TX Vref Scan disable
8921 11:41:17.167973 == TX Byte 0 ==
8922 11:41:17.171135 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8923 11:41:17.178135 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8924 11:41:17.178233 == TX Byte 1 ==
8925 11:41:17.181069 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8926 11:41:17.187416 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 11:41:17.187516 ==
8928 11:41:17.190729 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 11:41:17.193966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 11:41:17.194068 ==
8931 11:41:17.207663
8932 11:41:17.211045 TX Vref early break, caculate TX vref
8933 11:41:17.214350 TX Vref=16, minBit 6, minWin=22, winSum=379
8934 11:41:17.217338 TX Vref=18, minBit 9, minWin=22, winSum=384
8935 11:41:17.220990 TX Vref=20, minBit 0, minWin=24, winSum=395
8936 11:41:17.224100 TX Vref=22, minBit 6, minWin=24, winSum=401
8937 11:41:17.227772 TX Vref=24, minBit 6, minWin=25, winSum=414
8938 11:41:17.234336 TX Vref=26, minBit 0, minWin=25, winSum=419
8939 11:41:17.237533 TX Vref=28, minBit 0, minWin=24, winSum=420
8940 11:41:17.241136 TX Vref=30, minBit 0, minWin=26, winSum=426
8941 11:41:17.244095 TX Vref=32, minBit 0, minWin=25, winSum=417
8942 11:41:17.247555 TX Vref=34, minBit 0, minWin=24, winSum=407
8943 11:41:17.250800 TX Vref=36, minBit 0, minWin=23, winSum=394
8944 11:41:17.257480 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
8945 11:41:17.257559
8946 11:41:17.260944 Final TX Range 0 Vref 30
8947 11:41:17.261022
8948 11:41:17.261097 ==
8949 11:41:17.263986 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 11:41:17.267507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 11:41:17.267589 ==
8952 11:41:17.267652
8953 11:41:17.267731
8954 11:41:17.270515 TX Vref Scan disable
8955 11:41:17.277156 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8956 11:41:17.277235 == TX Byte 0 ==
8957 11:41:17.280611 u2DelayCellOfst[0]=17 cells (5 PI)
8958 11:41:17.284246 u2DelayCellOfst[1]=14 cells (4 PI)
8959 11:41:17.287303 u2DelayCellOfst[2]=0 cells (0 PI)
8960 11:41:17.290710 u2DelayCellOfst[3]=7 cells (2 PI)
8961 11:41:17.293816 u2DelayCellOfst[4]=10 cells (3 PI)
8962 11:41:17.297246 u2DelayCellOfst[5]=21 cells (6 PI)
8963 11:41:17.300493 u2DelayCellOfst[6]=17 cells (5 PI)
8964 11:41:17.303911 u2DelayCellOfst[7]=7 cells (2 PI)
8965 11:41:17.307325 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8966 11:41:17.310710 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8967 11:41:17.313544 == TX Byte 1 ==
8968 11:41:17.317009 u2DelayCellOfst[8]=0 cells (0 PI)
8969 11:41:17.317090 u2DelayCellOfst[9]=3 cells (1 PI)
8970 11:41:17.320652 u2DelayCellOfst[10]=10 cells (3 PI)
8971 11:41:17.323617 u2DelayCellOfst[11]=7 cells (2 PI)
8972 11:41:17.327168 u2DelayCellOfst[12]=14 cells (4 PI)
8973 11:41:17.330198 u2DelayCellOfst[13]=14 cells (4 PI)
8974 11:41:17.333805 u2DelayCellOfst[14]=17 cells (5 PI)
8975 11:41:17.337299 u2DelayCellOfst[15]=14 cells (4 PI)
8976 11:41:17.340360 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8977 11:41:17.346904 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8978 11:41:17.346986 DramC Write-DBI on
8979 11:41:17.347049 ==
8980 11:41:17.350037 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 11:41:17.356999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 11:41:17.357080 ==
8983 11:41:17.357144
8984 11:41:17.357263
8985 11:41:17.357322 TX Vref Scan disable
8986 11:41:17.361103 == TX Byte 0 ==
8987 11:41:17.364028 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8988 11:41:17.367611 == TX Byte 1 ==
8989 11:41:17.370766 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8990 11:41:17.374271 DramC Write-DBI off
8991 11:41:17.374379
8992 11:41:17.374470 [DATLAT]
8993 11:41:17.374559 Freq=1600, CH1 RK1
8994 11:41:17.374645
8995 11:41:17.377206 DATLAT Default: 0xf
8996 11:41:17.377288 0, 0xFFFF, sum = 0
8997 11:41:17.381107 1, 0xFFFF, sum = 0
8998 11:41:17.384025 2, 0xFFFF, sum = 0
8999 11:41:17.384109 3, 0xFFFF, sum = 0
9000 11:41:17.387278 4, 0xFFFF, sum = 0
9001 11:41:17.387419 5, 0xFFFF, sum = 0
9002 11:41:17.390453 6, 0xFFFF, sum = 0
9003 11:41:17.390588 7, 0xFFFF, sum = 0
9004 11:41:17.394089 8, 0xFFFF, sum = 0
9005 11:41:17.394206 9, 0xFFFF, sum = 0
9006 11:41:17.397614 10, 0xFFFF, sum = 0
9007 11:41:17.397696 11, 0xFFFF, sum = 0
9008 11:41:17.400810 12, 0xFFFF, sum = 0
9009 11:41:17.400891 13, 0xFFFF, sum = 0
9010 11:41:17.404104 14, 0x0, sum = 1
9011 11:41:17.404191 15, 0x0, sum = 2
9012 11:41:17.407464 16, 0x0, sum = 3
9013 11:41:17.407546 17, 0x0, sum = 4
9014 11:41:17.410841 best_step = 15
9015 11:41:17.410922
9016 11:41:17.410986 ==
9017 11:41:17.414104 Dram Type= 6, Freq= 0, CH_1, rank 1
9018 11:41:17.416949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9019 11:41:17.417030 ==
9020 11:41:17.420793 RX Vref Scan: 0
9021 11:41:17.420874
9022 11:41:17.420939 RX Vref 0 -> 0, step: 1
9023 11:41:17.420998
9024 11:41:17.423800 RX Delay 11 -> 252, step: 4
9025 11:41:17.427439 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9026 11:41:17.434099 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9027 11:41:17.436948 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9028 11:41:17.440608 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9029 11:41:17.443464 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9030 11:41:17.447004 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9031 11:41:17.453901 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9032 11:41:17.457204 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9033 11:41:17.460206 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9034 11:41:17.463664 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9035 11:41:17.467397 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9036 11:41:17.473957 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9037 11:41:17.476897 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9038 11:41:17.480493 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9039 11:41:17.483567 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
9040 11:41:17.490586 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9041 11:41:17.490668 ==
9042 11:41:17.493779 Dram Type= 6, Freq= 0, CH_1, rank 1
9043 11:41:17.497069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9044 11:41:17.497152 ==
9045 11:41:17.497216 DQS Delay:
9046 11:41:17.500199 DQS0 = 0, DQS1 = 0
9047 11:41:17.500281 DQM Delay:
9048 11:41:17.503440 DQM0 = 130, DQM1 = 126
9049 11:41:17.503521 DQ Delay:
9050 11:41:17.506616 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =126
9051 11:41:17.509900 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9052 11:41:17.513412 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =118
9053 11:41:17.516598 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
9054 11:41:17.516681
9055 11:41:17.516744
9056 11:41:17.516803
9057 11:41:17.519987 [DramC_TX_OE_Calibration] TA2
9058 11:41:17.523507 Original DQ_B0 (3 6) =30, OEN = 27
9059 11:41:17.526708 Original DQ_B1 (3 6) =30, OEN = 27
9060 11:41:17.529942 24, 0x0, End_B0=24 End_B1=24
9061 11:41:17.533531 25, 0x0, End_B0=25 End_B1=25
9062 11:41:17.533641 26, 0x0, End_B0=26 End_B1=26
9063 11:41:17.536528 27, 0x0, End_B0=27 End_B1=27
9064 11:41:17.540032 28, 0x0, End_B0=28 End_B1=28
9065 11:41:17.543476 29, 0x0, End_B0=29 End_B1=29
9066 11:41:17.546682 30, 0x0, End_B0=30 End_B1=30
9067 11:41:17.546766 31, 0x4141, End_B0=30 End_B1=30
9068 11:41:17.549977 Byte0 end_step=30 best_step=27
9069 11:41:17.553111 Byte1 end_step=30 best_step=27
9070 11:41:17.556805 Byte0 TX OE(2T, 0.5T) = (3, 3)
9071 11:41:17.560077 Byte1 TX OE(2T, 0.5T) = (3, 3)
9072 11:41:17.560159
9073 11:41:17.560223
9074 11:41:17.566468 [DQSOSCAuto] RK1, (LSB)MR18= 0xf15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9075 11:41:17.570001 CH1 RK1: MR19=303, MR18=F15
9076 11:41:17.576363 CH1_RK1: MR19=0x303, MR18=0xF15, DQSOSC=399, MR23=63, INC=23, DEC=15
9077 11:41:17.579325 [RxdqsGatingPostProcess] freq 1600
9078 11:41:17.586536 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9079 11:41:17.586619 best DQS0 dly(2T, 0.5T) = (1, 1)
9080 11:41:17.589486 best DQS1 dly(2T, 0.5T) = (1, 1)
9081 11:41:17.593033 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9082 11:41:17.596203 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9083 11:41:17.599381 best DQS0 dly(2T, 0.5T) = (1, 1)
9084 11:41:17.602877 best DQS1 dly(2T, 0.5T) = (1, 1)
9085 11:41:17.605845 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9086 11:41:17.609303 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9087 11:41:17.613101 Pre-setting of DQS Precalculation
9088 11:41:17.615911 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9089 11:41:17.625924 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9090 11:41:17.632831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9091 11:41:17.632913
9092 11:41:17.632977
9093 11:41:17.635848 [Calibration Summary] 3200 Mbps
9094 11:41:17.635929 CH 0, Rank 0
9095 11:41:17.639199 SW Impedance : PASS
9096 11:41:17.639281 DUTY Scan : NO K
9097 11:41:17.642875 ZQ Calibration : PASS
9098 11:41:17.645877 Jitter Meter : NO K
9099 11:41:17.645957 CBT Training : PASS
9100 11:41:17.648872 Write leveling : PASS
9101 11:41:17.652330 RX DQS gating : PASS
9102 11:41:17.652428 RX DQ/DQS(RDDQC) : PASS
9103 11:41:17.655971 TX DQ/DQS : PASS
9104 11:41:17.658887 RX DATLAT : PASS
9105 11:41:17.658967 RX DQ/DQS(Engine): PASS
9106 11:41:17.662285 TX OE : PASS
9107 11:41:17.662366 All Pass.
9108 11:41:17.662428
9109 11:41:17.665849 CH 0, Rank 1
9110 11:41:17.665929 SW Impedance : PASS
9111 11:41:17.668813 DUTY Scan : NO K
9112 11:41:17.672346 ZQ Calibration : PASS
9113 11:41:17.672428 Jitter Meter : NO K
9114 11:41:17.675279 CBT Training : PASS
9115 11:41:17.678796 Write leveling : PASS
9116 11:41:17.678878 RX DQS gating : PASS
9117 11:41:17.682368 RX DQ/DQS(RDDQC) : PASS
9118 11:41:17.682450 TX DQ/DQS : PASS
9119 11:41:17.685472 RX DATLAT : PASS
9120 11:41:17.688914 RX DQ/DQS(Engine): PASS
9121 11:41:17.688995 TX OE : PASS
9122 11:41:17.691917 All Pass.
9123 11:41:17.691999
9124 11:41:17.692063 CH 1, Rank 0
9125 11:41:17.695502 SW Impedance : PASS
9126 11:41:17.695585 DUTY Scan : NO K
9127 11:41:17.698974 ZQ Calibration : PASS
9128 11:41:17.702336 Jitter Meter : NO K
9129 11:41:17.702428 CBT Training : PASS
9130 11:41:17.705258 Write leveling : PASS
9131 11:41:17.708729 RX DQS gating : PASS
9132 11:41:17.708859 RX DQ/DQS(RDDQC) : PASS
9133 11:41:17.711734 TX DQ/DQS : PASS
9134 11:41:17.715547 RX DATLAT : PASS
9135 11:41:17.715629 RX DQ/DQS(Engine): PASS
9136 11:41:17.718575 TX OE : PASS
9137 11:41:17.718657 All Pass.
9138 11:41:17.718723
9139 11:41:17.721838 CH 1, Rank 1
9140 11:41:17.721951 SW Impedance : PASS
9141 11:41:17.725217 DUTY Scan : NO K
9142 11:41:17.728592 ZQ Calibration : PASS
9143 11:41:17.728669 Jitter Meter : NO K
9144 11:41:17.731802 CBT Training : PASS
9145 11:41:17.731885 Write leveling : PASS
9146 11:41:17.735267 RX DQS gating : PASS
9147 11:41:17.738774 RX DQ/DQS(RDDQC) : PASS
9148 11:41:17.738849 TX DQ/DQS : PASS
9149 11:41:17.741987 RX DATLAT : PASS
9150 11:41:17.745313 RX DQ/DQS(Engine): PASS
9151 11:41:17.745406 TX OE : PASS
9152 11:41:17.749103 All Pass.
9153 11:41:17.749188
9154 11:41:17.749251 DramC Write-DBI on
9155 11:41:17.751917 PER_BANK_REFRESH: Hybrid Mode
9156 11:41:17.755483 TX_TRACKING: ON
9157 11:41:17.762128 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9158 11:41:17.771738 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9159 11:41:17.778572 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9160 11:41:17.782020 [FAST_K] Save calibration result to emmc
9161 11:41:17.785037 sync common calibartion params.
9162 11:41:17.785117 sync cbt_mode0:1, 1:1
9163 11:41:17.788543 dram_init: ddr_geometry: 2
9164 11:41:17.792151 dram_init: ddr_geometry: 2
9165 11:41:17.795059 dram_init: ddr_geometry: 2
9166 11:41:17.795179 0:dram_rank_size:100000000
9167 11:41:17.798670 1:dram_rank_size:100000000
9168 11:41:17.804866 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9169 11:41:17.804949 DFS_SHUFFLE_HW_MODE: ON
9170 11:41:17.808267 dramc_set_vcore_voltage set vcore to 725000
9171 11:41:17.811882 Read voltage for 1600, 0
9172 11:41:17.811974 Vio18 = 0
9173 11:41:17.815361 Vcore = 725000
9174 11:41:17.815451 Vdram = 0
9175 11:41:17.815521 Vddq = 0
9176 11:41:17.818324 Vmddr = 0
9177 11:41:17.818400 switch to 3200 Mbps bootup
9178 11:41:17.822080 [DramcRunTimeConfig]
9179 11:41:17.822200 PHYPLL
9180 11:41:17.824966 DPM_CONTROL_AFTERK: ON
9181 11:41:17.825040 PER_BANK_REFRESH: ON
9182 11:41:17.828335 REFRESH_OVERHEAD_REDUCTION: ON
9183 11:41:17.831529 CMD_PICG_NEW_MODE: OFF
9184 11:41:17.831606 XRTWTW_NEW_MODE: ON
9185 11:41:17.834817 XRTRTR_NEW_MODE: ON
9186 11:41:17.834895 TX_TRACKING: ON
9187 11:41:17.838138 RDSEL_TRACKING: OFF
9188 11:41:17.841467 DQS Precalculation for DVFS: ON
9189 11:41:17.841585 RX_TRACKING: OFF
9190 11:41:17.845021 HW_GATING DBG: ON
9191 11:41:17.845162 ZQCS_ENABLE_LP4: ON
9192 11:41:17.848397 RX_PICG_NEW_MODE: ON
9193 11:41:17.848480 TX_PICG_NEW_MODE: ON
9194 11:41:17.851441 ENABLE_RX_DCM_DPHY: ON
9195 11:41:17.855167 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9196 11:41:17.858123 DUMMY_READ_FOR_TRACKING: OFF
9197 11:41:17.858218 !!! SPM_CONTROL_AFTERK: OFF
9198 11:41:17.861778 !!! SPM could not control APHY
9199 11:41:17.864772 IMPEDANCE_TRACKING: ON
9200 11:41:17.864871 TEMP_SENSOR: ON
9201 11:41:17.868225 HW_SAVE_FOR_SR: OFF
9202 11:41:17.871729 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9203 11:41:17.874539 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9204 11:41:17.878306 Read ODT Tracking: ON
9205 11:41:17.878388 Refresh Rate DeBounce: ON
9206 11:41:17.881148 DFS_NO_QUEUE_FLUSH: ON
9207 11:41:17.884826 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9208 11:41:17.887881 ENABLE_DFS_RUNTIME_MRW: OFF
9209 11:41:17.887962 DDR_RESERVE_NEW_MODE: ON
9210 11:41:17.891365 MR_CBT_SWITCH_FREQ: ON
9211 11:41:17.894459 =========================
9212 11:41:17.912452 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9213 11:41:17.915337 dram_init: ddr_geometry: 2
9214 11:41:17.933718 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9215 11:41:17.936966 dram_init: dram init end (result: 0)
9216 11:41:17.943572 DRAM-K: Full calibration passed in 24552 msecs
9217 11:41:17.946822 MRC: failed to locate region type 0.
9218 11:41:17.946905 DRAM rank0 size:0x100000000,
9219 11:41:17.950162 DRAM rank1 size=0x100000000
9220 11:41:17.960087 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9221 11:41:17.966920 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9222 11:41:17.973524 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9223 11:41:17.979774 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9224 11:41:17.984198 DRAM rank0 size:0x100000000,
9225 11:41:17.986718 DRAM rank1 size=0x100000000
9226 11:41:17.986793 CBMEM:
9227 11:41:17.989761 IMD: root @ 0xfffff000 254 entries.
9228 11:41:17.993200 IMD: root @ 0xffffec00 62 entries.
9229 11:41:17.996334 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9230 11:41:18.003163 WARNING: RO_VPD is uninitialized or empty.
9231 11:41:18.006192 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9232 11:41:18.013864 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9233 11:41:18.026325 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9234 11:41:18.037881 BS: romstage times (exec / console): total (unknown) / 24063 ms
9235 11:41:18.037978
9236 11:41:18.038044
9237 11:41:18.048055 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9238 11:41:18.050914 ARM64: Exception handlers installed.
9239 11:41:18.054221 ARM64: Testing exception
9240 11:41:18.057597 ARM64: Done test exception
9241 11:41:18.057697 Enumerating buses...
9242 11:41:18.060743 Show all devs... Before device enumeration.
9243 11:41:18.064073 Root Device: enabled 1
9244 11:41:18.067288 CPU_CLUSTER: 0: enabled 1
9245 11:41:18.067430 CPU: 00: enabled 1
9246 11:41:18.070796 Compare with tree...
9247 11:41:18.070911 Root Device: enabled 1
9248 11:41:18.074213 CPU_CLUSTER: 0: enabled 1
9249 11:41:18.077256 CPU: 00: enabled 1
9250 11:41:18.077357 Root Device scanning...
9251 11:41:18.080753 scan_static_bus for Root Device
9252 11:41:18.084237 CPU_CLUSTER: 0 enabled
9253 11:41:18.087211 scan_static_bus for Root Device done
9254 11:41:18.090896 scan_bus: bus Root Device finished in 8 msecs
9255 11:41:18.090978 done
9256 11:41:18.097417 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9257 11:41:18.100909 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9258 11:41:18.107306 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9259 11:41:18.110408 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9260 11:41:18.113864 Allocating resources...
9261 11:41:18.116979 Reading resources...
9262 11:41:18.120287 Root Device read_resources bus 0 link: 0
9263 11:41:18.124027 DRAM rank0 size:0x100000000,
9264 11:41:18.124109 DRAM rank1 size=0x100000000
9265 11:41:18.126911 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9266 11:41:18.130335 CPU: 00 missing read_resources
9267 11:41:18.137143 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9268 11:41:18.140564 Root Device read_resources bus 0 link: 0 done
9269 11:41:18.140647 Done reading resources.
9270 11:41:18.146989 Show resources in subtree (Root Device)...After reading.
9271 11:41:18.150332 Root Device child on link 0 CPU_CLUSTER: 0
9272 11:41:18.153826 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 11:41:18.163703 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 11:41:18.163788 CPU: 00
9275 11:41:18.167153 Root Device assign_resources, bus 0 link: 0
9276 11:41:18.170556 CPU_CLUSTER: 0 missing set_resources
9277 11:41:18.176998 Root Device assign_resources, bus 0 link: 0 done
9278 11:41:18.177081 Done setting resources.
9279 11:41:18.184268 Show resources in subtree (Root Device)...After assigning values.
9280 11:41:18.187333 Root Device child on link 0 CPU_CLUSTER: 0
9281 11:41:18.190237 CPU_CLUSTER: 0 child on link 0 CPU: 00
9282 11:41:18.200480 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9283 11:41:18.200564 CPU: 00
9284 11:41:18.203328 Done allocating resources.
9285 11:41:18.209814 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9286 11:41:18.209989 Enabling resources...
9287 11:41:18.210092 done.
9288 11:41:18.216423 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9289 11:41:18.216531 Initializing devices...
9290 11:41:18.219997 Root Device init
9291 11:41:18.220101 init hardware done!
9292 11:41:18.223332 0x00000018: ctrlr->caps
9293 11:41:18.226834 52.000 MHz: ctrlr->f_max
9294 11:41:18.226935 0.400 MHz: ctrlr->f_min
9295 11:41:18.229851 0x40ff8080: ctrlr->voltages
9296 11:41:18.233351 sclk: 390625
9297 11:41:18.233451 Bus Width = 1
9298 11:41:18.233539 sclk: 390625
9299 11:41:18.236416 Bus Width = 1
9300 11:41:18.236521 Early init status = 3
9301 11:41:18.243284 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9302 11:41:18.246593 in-header: 03 fc 00 00 01 00 00 00
9303 11:41:18.246703 in-data: 00
9304 11:41:18.252880 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9305 11:41:18.257081 in-header: 03 fd 00 00 00 00 00 00
9306 11:41:18.259761 in-data:
9307 11:41:18.263260 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9308 11:41:18.266803 in-header: 03 fc 00 00 01 00 00 00
9309 11:41:18.270475 in-data: 00
9310 11:41:18.272942 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9311 11:41:18.278146 in-header: 03 fd 00 00 00 00 00 00
9312 11:41:18.281038 in-data:
9313 11:41:18.284642 [SSUSB] Setting up USB HOST controller...
9314 11:41:18.288189 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9315 11:41:18.291502 [SSUSB] phy power-on done.
9316 11:41:18.294385 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9317 11:41:18.300993 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9318 11:41:18.304600 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9319 11:41:18.311053 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9320 11:41:18.317496 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9321 11:41:18.324079 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9322 11:41:18.330909 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9323 11:41:18.337390 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9324 11:41:18.340903 SPM: binary array size = 0x9dc
9325 11:41:18.343930 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9326 11:41:18.350590 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9327 11:41:18.357226 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9328 11:41:18.363854 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9329 11:41:18.366864 configure_display: Starting display init
9330 11:41:18.401049 anx7625_power_on_init: Init interface.
9331 11:41:18.404088 anx7625_disable_pd_protocol: Disabled PD feature.
9332 11:41:18.407728 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9333 11:41:18.435570 anx7625_start_dp_work: Secure OCM version=00
9334 11:41:18.438938 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9335 11:41:18.453425 sp_tx_get_edid_block: EDID Block = 1
9336 11:41:18.556325 Extracted contents:
9337 11:41:18.559634 header: 00 ff ff ff ff ff ff 00
9338 11:41:18.562969 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9339 11:41:18.565850 version: 01 04
9340 11:41:18.569716 basic params: 95 1f 11 78 0a
9341 11:41:18.572433 chroma info: 76 90 94 55 54 90 27 21 50 54
9342 11:41:18.575811 established: 00 00 00
9343 11:41:18.582352 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9344 11:41:18.585715 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9345 11:41:18.592476 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9346 11:41:18.598954 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9347 11:41:18.605836 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9348 11:41:18.608877 extensions: 00
9349 11:41:18.608977 checksum: fb
9350 11:41:18.609069
9351 11:41:18.612373 Manufacturer: IVO Model 57d Serial Number 0
9352 11:41:18.615328 Made week 0 of 2020
9353 11:41:18.615478 EDID version: 1.4
9354 11:41:18.618888 Digital display
9355 11:41:18.622441 6 bits per primary color channel
9356 11:41:18.622513 DisplayPort interface
9357 11:41:18.625430 Maximum image size: 31 cm x 17 cm
9358 11:41:18.628957 Gamma: 220%
9359 11:41:18.629027 Check DPMS levels
9360 11:41:18.632569 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9361 11:41:18.639057 First detailed timing is preferred timing
9362 11:41:18.639159 Established timings supported:
9363 11:41:18.642499 Standard timings supported:
9364 11:41:18.646018 Detailed timings
9365 11:41:18.648960 Hex of detail: 383680a07038204018303c0035ae10000019
9366 11:41:18.652486 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9367 11:41:18.658983 0780 0798 07c8 0820 hborder 0
9368 11:41:18.662396 0438 043b 0447 0458 vborder 0
9369 11:41:18.665775 -hsync -vsync
9370 11:41:18.665844 Did detailed timing
9371 11:41:18.672402 Hex of detail: 000000000000000000000000000000000000
9372 11:41:18.672522 Manufacturer-specified data, tag 0
9373 11:41:18.678781 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9374 11:41:18.682043 ASCII string: InfoVision
9375 11:41:18.685419 Hex of detail: 000000fe00523134304e574635205248200a
9376 11:41:18.688672 ASCII string: R140NWF5 RH
9377 11:41:18.688743 Checksum
9378 11:41:18.691988 Checksum: 0xfb (valid)
9379 11:41:18.695260 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9380 11:41:18.698619 DSI data_rate: 832800000 bps
9381 11:41:18.705066 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9382 11:41:18.708527 anx7625_parse_edid: pixelclock(138800).
9383 11:41:18.712154 hactive(1920), hsync(48), hfp(24), hbp(88)
9384 11:41:18.715200 vactive(1080), vsync(12), vfp(3), vbp(17)
9385 11:41:18.718637 anx7625_dsi_config: config dsi.
9386 11:41:18.725205 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9387 11:41:18.738228 anx7625_dsi_config: success to config DSI
9388 11:41:18.741214 anx7625_dp_start: MIPI phy setup OK.
9389 11:41:18.744598 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9390 11:41:18.748388 mtk_ddp_mode_set invalid vrefresh 60
9391 11:41:18.751274 main_disp_path_setup
9392 11:41:18.751393 ovl_layer_smi_id_en
9393 11:41:18.754318 ovl_layer_smi_id_en
9394 11:41:18.754461 ccorr_config
9395 11:41:18.754538 aal_config
9396 11:41:18.757896 gamma_config
9397 11:41:18.757978 postmask_config
9398 11:41:18.761425 dither_config
9399 11:41:18.764339 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9400 11:41:18.771306 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9401 11:41:18.774577 Root Device init finished in 551 msecs
9402 11:41:18.777926 CPU_CLUSTER: 0 init
9403 11:41:18.784938 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9404 11:41:18.788274 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9405 11:41:18.791551 APU_MBOX 0x190000b0 = 0x10001
9406 11:41:18.794969 APU_MBOX 0x190001b0 = 0x10001
9407 11:41:18.797791 APU_MBOX 0x190005b0 = 0x10001
9408 11:41:18.801519 APU_MBOX 0x190006b0 = 0x10001
9409 11:41:18.804535 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9410 11:41:18.817483 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9411 11:41:18.829314 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9412 11:41:18.836448 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9413 11:41:18.847721 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9414 11:41:18.857026 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9415 11:41:18.860050 CPU_CLUSTER: 0 init finished in 81 msecs
9416 11:41:18.863637 Devices initialized
9417 11:41:18.867072 Show all devs... After init.
9418 11:41:18.867170 Root Device: enabled 1
9419 11:41:18.870358 CPU_CLUSTER: 0: enabled 1
9420 11:41:18.873728 CPU: 00: enabled 1
9421 11:41:18.876674 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9422 11:41:18.880167 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9423 11:41:18.883295 ELOG: NV offset 0x57f000 size 0x1000
9424 11:41:18.890160 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9425 11:41:18.896873 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9426 11:41:18.900074 ELOG: Event(17) added with size 13 at 2023-06-15 11:41:19 UTC
9427 11:41:18.906670 out: cmd=0x121: 03 db 21 01 00 00 00 00
9428 11:41:18.910099 in-header: 03 ec 00 00 2c 00 00 00
9429 11:41:18.919863 in-data: 73 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9430 11:41:18.926413 ELOG: Event(A1) added with size 10 at 2023-06-15 11:41:19 UTC
9431 11:41:18.933058 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9432 11:41:18.939265 ELOG: Event(A0) added with size 9 at 2023-06-15 11:41:19 UTC
9433 11:41:18.942961 elog_add_boot_reason: Logged dev mode boot
9434 11:41:18.949378 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9435 11:41:18.949461 Finalize devices...
9436 11:41:18.952937 Devices finalized
9437 11:41:18.956224 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9438 11:41:18.959802 Writing coreboot table at 0xffe64000
9439 11:41:18.962758 0. 000000000010a000-0000000000113fff: RAMSTAGE
9440 11:41:18.969250 1. 0000000040000000-00000000400fffff: RAM
9441 11:41:18.972870 2. 0000000040100000-000000004032afff: RAMSTAGE
9442 11:41:18.976234 3. 000000004032b000-00000000545fffff: RAM
9443 11:41:18.979604 4. 0000000054600000-000000005465ffff: BL31
9444 11:41:18.982935 5. 0000000054660000-00000000ffe63fff: RAM
9445 11:41:18.989294 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9446 11:41:18.992775 7. 0000000100000000-000000023fffffff: RAM
9447 11:41:18.996102 Passing 5 GPIOs to payload:
9448 11:41:18.999394 NAME | PORT | POLARITY | VALUE
9449 11:41:19.006291 EC in RW | 0x000000aa | low | undefined
9450 11:41:19.009101 EC interrupt | 0x00000005 | low | undefined
9451 11:41:19.012546 TPM interrupt | 0x000000ab | high | undefined
9452 11:41:19.019094 SD card detect | 0x00000011 | high | undefined
9453 11:41:19.022395 speaker enable | 0x00000093 | high | undefined
9454 11:41:19.025773 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9455 11:41:19.029406 in-header: 03 f9 00 00 02 00 00 00
9456 11:41:19.032371 in-data: 02 00
9457 11:41:19.035940 ADC[4]: Raw value=900959 ID=7
9458 11:41:19.036073 ADC[3]: Raw value=213336 ID=1
9459 11:41:19.039274 RAM Code: 0x71
9460 11:41:19.042816 ADC[6]: Raw value=74557 ID=0
9461 11:41:19.042915 ADC[5]: Raw value=212229 ID=1
9462 11:41:19.045763 SKU Code: 0x1
9463 11:41:19.048778 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9464 11:41:19.052433 coreboot table: 964 bytes.
9465 11:41:19.055891 IMD ROOT 0. 0xfffff000 0x00001000
9466 11:41:19.059216 IMD SMALL 1. 0xffffe000 0x00001000
9467 11:41:19.062685 RO MCACHE 2. 0xffffc000 0x00001104
9468 11:41:19.065646 CONSOLE 3. 0xfff7c000 0x00080000
9469 11:41:19.069181 FMAP 4. 0xfff7b000 0x00000452
9470 11:41:19.072255 TIME STAMP 5. 0xfff7a000 0x00000910
9471 11:41:19.075730 VBOOT WORK 6. 0xfff66000 0x00014000
9472 11:41:19.079018 RAMOOPS 7. 0xffe66000 0x00100000
9473 11:41:19.082752 COREBOOT 8. 0xffe64000 0x00002000
9474 11:41:19.085655 IMD small region:
9475 11:41:19.088714 IMD ROOT 0. 0xffffec00 0x00000400
9476 11:41:19.092037 VPD 1. 0xffffeba0 0x0000004c
9477 11:41:19.095511 MMC STATUS 2. 0xffffeb80 0x00000004
9478 11:41:19.098903 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9479 11:41:19.102207 Probing TPM: done!
9480 11:41:19.105509 Connected to device vid:did:rid of 1ae0:0028:00
9481 11:41:19.116292 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9482 11:41:19.119286 Initialized TPM device CR50 revision 0
9483 11:41:19.122825 Checking cr50 for pending updates
9484 11:41:19.126848 Reading cr50 TPM mode
9485 11:41:19.135133 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9486 11:41:19.142139 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9487 11:41:19.182054 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9488 11:41:19.185293 Checking segment from ROM address 0x40100000
9489 11:41:19.188769 Checking segment from ROM address 0x4010001c
9490 11:41:19.195749 Loading segment from ROM address 0x40100000
9491 11:41:19.195858 code (compression=0)
9492 11:41:19.202123 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9493 11:41:19.212288 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9494 11:41:19.212402 it's not compressed!
9495 11:41:19.218573 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9496 11:41:19.222109 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9497 11:41:19.242280 Loading segment from ROM address 0x4010001c
9498 11:41:19.242402 Entry Point 0x80000000
9499 11:41:19.245859 Loaded segments
9500 11:41:19.248992 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9501 11:41:19.256138 Jumping to boot code at 0x80000000(0xffe64000)
9502 11:41:19.262549 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9503 11:41:19.269239 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9504 11:41:19.277099 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9505 11:41:19.280190 Checking segment from ROM address 0x40100000
9506 11:41:19.283715 Checking segment from ROM address 0x4010001c
9507 11:41:19.290618 Loading segment from ROM address 0x40100000
9508 11:41:19.290726 code (compression=1)
9509 11:41:19.297350 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9510 11:41:19.306821 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9511 11:41:19.306929 using LZMA
9512 11:41:19.315059 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9513 11:41:19.321747 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9514 11:41:19.325237 Loading segment from ROM address 0x4010001c
9515 11:41:19.325343 Entry Point 0x54601000
9516 11:41:19.328828 Loaded segments
9517 11:41:19.331900 NOTICE: MT8192 bl31_setup
9518 11:41:19.338679 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9519 11:41:19.342234 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9520 11:41:19.345354 WARNING: region 0:
9521 11:41:19.348917 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 11:41:19.348996 WARNING: region 1:
9523 11:41:19.355543 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9524 11:41:19.358981 WARNING: region 2:
9525 11:41:19.362003 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9526 11:41:19.365658 WARNING: region 3:
9527 11:41:19.368667 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9528 11:41:19.372026 WARNING: region 4:
9529 11:41:19.379018 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9530 11:41:19.379127 WARNING: region 5:
9531 11:41:19.382117 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 11:41:19.385716 WARNING: region 6:
9533 11:41:19.388876 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 11:41:19.392667 WARNING: region 7:
9535 11:41:19.395697 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 11:41:19.401987 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9537 11:41:19.405746 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9538 11:41:19.408717 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9539 11:41:19.415250 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9540 11:41:19.418752 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9541 11:41:19.422027 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9542 11:41:19.428766 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9543 11:41:19.432376 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9544 11:41:19.438727 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9545 11:41:19.442521 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9546 11:41:19.445492 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9547 11:41:19.452573 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9548 11:41:19.455582 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9549 11:41:19.458955 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9550 11:41:19.465313 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9551 11:41:19.468835 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9552 11:41:19.472386 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9553 11:41:19.478777 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9554 11:41:19.482243 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9555 11:41:19.489001 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9556 11:41:19.492331 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9557 11:41:19.495685 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9558 11:41:19.502138 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9559 11:41:19.505789 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9560 11:41:19.512493 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9561 11:41:19.516129 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9562 11:41:19.519260 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9563 11:41:19.525925 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9564 11:41:19.529270 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9565 11:41:19.532678 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9566 11:41:19.539246 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9567 11:41:19.542464 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9568 11:41:19.546039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9569 11:41:19.552481 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9570 11:41:19.556162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9571 11:41:19.559788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9572 11:41:19.562998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9573 11:41:19.569653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9574 11:41:19.572655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9575 11:41:19.576150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9576 11:41:19.579687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9577 11:41:19.586003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9578 11:41:19.589555 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9579 11:41:19.592538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9580 11:41:19.595988 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9581 11:41:19.602752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9582 11:41:19.606062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9583 11:41:19.609541 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9584 11:41:19.616278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9585 11:41:19.619797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9586 11:41:19.622883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9587 11:41:19.629779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9588 11:41:19.633081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9589 11:41:19.639457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9590 11:41:19.642896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9591 11:41:19.646526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9592 11:41:19.652953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9593 11:41:19.656758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9594 11:41:19.663049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9595 11:41:19.666543 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9596 11:41:19.673079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9597 11:41:19.676080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9598 11:41:19.682736 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9599 11:41:19.686195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9600 11:41:19.689733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9601 11:41:19.696287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9602 11:41:19.699678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9603 11:41:19.706173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9604 11:41:19.709615 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9605 11:41:19.716482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9606 11:41:19.719783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9607 11:41:19.723214 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9608 11:41:19.729587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9609 11:41:19.732945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9610 11:41:19.739712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9611 11:41:19.743142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9612 11:41:19.746640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9613 11:41:19.752761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9614 11:41:19.756166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9615 11:41:19.763262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9616 11:41:19.766203 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9617 11:41:19.773299 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9618 11:41:19.776190 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9619 11:41:19.783040 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9620 11:41:19.786530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9621 11:41:19.789363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9622 11:41:19.796536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9623 11:41:19.799762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9624 11:41:19.806699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9625 11:41:19.810109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9626 11:41:19.813281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9627 11:41:19.819396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9628 11:41:19.822922 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9629 11:41:19.829777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9630 11:41:19.833016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9631 11:41:19.839746 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9632 11:41:19.843227 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9633 11:41:19.846563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9634 11:41:19.853140 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9635 11:41:19.856273 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9636 11:41:19.859713 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9637 11:41:19.862654 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9638 11:41:19.869885 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9639 11:41:19.872837 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9640 11:41:19.879977 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9641 11:41:19.882766 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9642 11:41:19.886324 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9643 11:41:19.892748 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9644 11:41:19.896217 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9645 11:41:19.903102 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9646 11:41:19.906300 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9647 11:41:19.909290 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9648 11:41:19.915835 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9649 11:41:19.919158 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9650 11:41:19.926039 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9651 11:41:19.929410 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9652 11:41:19.932825 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9653 11:41:19.939374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9654 11:41:19.942728 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9655 11:41:19.946374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9656 11:41:19.949389 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9657 11:41:19.955698 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9658 11:41:19.959093 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9659 11:41:19.962679 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9660 11:41:19.969351 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9661 11:41:19.972250 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9662 11:41:19.976194 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9663 11:41:19.982476 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9664 11:41:19.986022 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9665 11:41:19.992546 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9666 11:41:19.996026 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9667 11:41:19.998946 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9668 11:41:20.006044 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9669 11:41:20.009080 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9670 11:41:20.012495 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9671 11:41:20.019502 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9672 11:41:20.022236 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9673 11:41:20.028870 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9674 11:41:20.032297 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9675 11:41:20.035766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9676 11:41:20.042406 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9677 11:41:20.045818 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9678 11:41:20.052457 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9679 11:41:20.055526 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9680 11:41:20.058901 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9681 11:41:20.065467 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9682 11:41:20.069073 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9683 11:41:20.072537 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9684 11:41:20.079071 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9685 11:41:20.082646 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9686 11:41:20.089063 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9687 11:41:20.092226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9688 11:41:20.095729 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9689 11:41:20.102091 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9690 11:41:20.105681 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9691 11:41:20.112079 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9692 11:41:20.115771 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9693 11:41:20.119101 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9694 11:41:20.125531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9695 11:41:20.128905 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9696 11:41:20.132362 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9697 11:41:20.138759 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9698 11:41:20.142307 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9699 11:41:20.149107 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9700 11:41:20.152482 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9701 11:41:20.155268 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9702 11:41:20.161907 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9703 11:41:20.165364 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9704 11:41:20.172385 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9705 11:41:20.175247 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9706 11:41:20.178843 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9707 11:41:20.185483 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9708 11:41:20.189052 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9709 11:41:20.195653 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9710 11:41:20.198630 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9711 11:41:20.202162 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9712 11:41:20.208981 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9713 11:41:20.211988 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9714 11:41:20.218382 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9715 11:41:20.221983 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9716 11:41:20.225332 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9717 11:41:20.232003 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9718 11:41:20.235208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9719 11:41:20.238783 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9720 11:41:20.245247 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9721 11:41:20.248409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9722 11:41:20.255140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9723 11:41:20.258348 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9724 11:41:20.261755 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9725 11:41:20.268466 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9726 11:41:20.271493 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9727 11:41:20.278268 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9728 11:41:20.281317 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9729 11:41:20.287862 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9730 11:41:20.291297 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9731 11:41:20.294823 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9732 11:41:20.301504 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9733 11:41:20.304423 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9734 11:41:20.311328 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9735 11:41:20.314305 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9736 11:41:20.321457 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9737 11:41:20.324286 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9738 11:41:20.327805 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9739 11:41:20.334758 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9740 11:41:20.337730 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9741 11:41:20.344141 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9742 11:41:20.347617 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9743 11:41:20.351174 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9744 11:41:20.357858 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9745 11:41:20.361187 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9746 11:41:20.367715 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9747 11:41:20.371082 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9748 11:41:20.377294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9749 11:41:20.380767 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9750 11:41:20.384505 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9751 11:41:20.391022 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9752 11:41:20.394508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9753 11:41:20.400445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9754 11:41:20.404043 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9755 11:41:20.410634 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9756 11:41:20.414195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9757 11:41:20.417209 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9758 11:41:20.424281 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9759 11:41:20.427263 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9760 11:41:20.434135 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9761 11:41:20.436991 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9762 11:41:20.440335 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9763 11:41:20.447303 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9764 11:41:20.450664 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9765 11:41:20.453977 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9766 11:41:20.460410 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9767 11:41:20.464109 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9768 11:41:20.467414 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9769 11:41:20.470642 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9770 11:41:20.477180 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9771 11:41:20.480685 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9772 11:41:20.487064 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9773 11:41:20.490751 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9774 11:41:20.493638 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9775 11:41:20.500129 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9776 11:41:20.503700 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9777 11:41:20.506736 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9778 11:41:20.513266 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9779 11:41:20.516798 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9780 11:41:20.520173 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9781 11:41:20.526651 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9782 11:41:20.530127 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9783 11:41:20.536390 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9784 11:41:20.539821 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9785 11:41:20.543261 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9786 11:41:20.549702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9787 11:41:20.553597 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9788 11:41:20.556514 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9789 11:41:20.563482 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9790 11:41:20.566883 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9791 11:41:20.570094 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9792 11:41:20.576667 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9793 11:41:20.580051 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9794 11:41:20.586379 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9795 11:41:20.589850 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9796 11:41:20.593410 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9797 11:41:20.599825 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9798 11:41:20.603343 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9799 11:41:20.606404 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9800 11:41:20.612979 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9801 11:41:20.616606 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9802 11:41:20.622899 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9803 11:41:20.626179 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9804 11:41:20.629796 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9805 11:41:20.633415 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9806 11:41:20.639812 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9807 11:41:20.642539 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9808 11:41:20.646348 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9809 11:41:20.649361 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9810 11:41:20.656048 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9811 11:41:20.659830 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9812 11:41:20.662971 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9813 11:41:20.665922 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9814 11:41:20.672569 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9815 11:41:20.675841 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9816 11:41:20.679499 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9817 11:41:20.682605 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9818 11:41:20.689522 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9819 11:41:20.692404 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9820 11:41:20.698986 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9821 11:41:20.702606 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9822 11:41:20.709241 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9823 11:41:20.712227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9824 11:41:20.715875 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9825 11:41:20.722393 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9826 11:41:20.725819 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9827 11:41:20.732495 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9828 11:41:20.735912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9829 11:41:20.739286 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9830 11:41:20.745843 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9831 11:41:20.749034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9832 11:41:20.755636 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9833 11:41:20.758677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9834 11:41:20.762099 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9835 11:41:20.768725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9836 11:41:20.772175 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9837 11:41:20.778986 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9838 11:41:20.782243 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9839 11:41:20.789004 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9840 11:41:20.792552 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9841 11:41:20.796127 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9842 11:41:20.802482 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9843 11:41:20.805501 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9844 11:41:20.809231 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9845 11:41:20.815722 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9846 11:41:20.818750 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9847 11:41:20.826031 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9848 11:41:20.828715 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9849 11:41:20.832607 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9850 11:41:20.839109 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9851 11:41:20.842034 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9852 11:41:20.848544 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9853 11:41:20.852017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9854 11:41:20.858717 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9855 11:41:20.862014 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9856 11:41:20.865614 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9857 11:41:20.871962 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9858 11:41:20.875287 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9859 11:41:20.882239 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9860 11:41:20.885398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9861 11:41:20.888775 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9862 11:41:20.895546 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9863 11:41:20.899104 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9864 11:41:20.905507 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9865 11:41:20.909103 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9866 11:41:20.912101 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9867 11:41:20.918560 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9868 11:41:20.922336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9869 11:41:20.928682 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9870 11:41:20.932257 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9871 11:41:20.935677 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9872 11:41:20.942074 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9873 11:41:20.945568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9874 11:41:20.952212 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9875 11:41:20.955227 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9876 11:41:20.958335 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9877 11:41:20.965172 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9878 11:41:20.968579 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9879 11:41:20.975313 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9880 11:41:20.978437 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9881 11:41:20.981897 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9882 11:41:20.988375 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9883 11:41:20.991872 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9884 11:41:20.998177 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9885 11:41:21.001821 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9886 11:41:21.008623 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9887 11:41:21.011548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9888 11:41:21.015016 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9889 11:41:21.021633 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9890 11:41:21.024719 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9891 11:41:21.031817 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9892 11:41:21.034639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9893 11:41:21.038202 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9894 11:41:21.044876 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9895 11:41:21.048230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9896 11:41:21.054900 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9897 11:41:21.058203 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9898 11:41:21.064938 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9899 11:41:21.068107 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9900 11:41:21.074745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9901 11:41:21.078141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9902 11:41:21.081286 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9903 11:41:21.088053 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9904 11:41:21.091013 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9905 11:41:21.098012 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9906 11:41:21.100981 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9907 11:41:21.108241 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9908 11:41:21.111186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9909 11:41:21.114191 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9910 11:41:21.121183 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9911 11:41:21.124605 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9912 11:41:21.131146 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9913 11:41:21.134480 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9914 11:41:21.141122 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9915 11:41:21.144128 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9916 11:41:21.147942 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9917 11:41:21.154678 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9918 11:41:21.157576 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9919 11:41:21.163992 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9920 11:41:21.168055 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9921 11:41:21.174391 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9922 11:41:21.177352 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9923 11:41:21.184324 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9924 11:41:21.187237 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9925 11:41:21.190484 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9926 11:41:21.197482 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9927 11:41:21.200338 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9928 11:41:21.207175 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9929 11:41:21.210823 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9930 11:41:21.216926 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9931 11:41:21.220433 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9932 11:41:21.226892 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9933 11:41:21.230453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9934 11:41:21.233509 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9935 11:41:21.240668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9936 11:41:21.243730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9937 11:41:21.250197 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9938 11:41:21.253326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9939 11:41:21.256957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9940 11:41:21.263717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9941 11:41:21.267019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9942 11:41:21.273714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9943 11:41:21.277244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9944 11:41:21.283585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9945 11:41:21.286942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9946 11:41:21.293327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9947 11:41:21.296853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9948 11:41:21.303251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9949 11:41:21.306677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9950 11:41:21.313191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9951 11:41:21.316774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9952 11:41:21.323389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9953 11:41:21.326504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9954 11:41:21.332855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9955 11:41:21.336317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9956 11:41:21.343217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9957 11:41:21.346329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9958 11:41:21.352660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9959 11:41:21.356419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9960 11:41:21.362817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9961 11:41:21.366303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9962 11:41:21.372968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9963 11:41:21.376332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9964 11:41:21.382881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9965 11:41:21.385882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9966 11:41:21.392696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9967 11:41:21.395698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9968 11:41:21.402331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9969 11:41:21.405720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9970 11:41:21.409057 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9971 11:41:21.412413 INFO: [APUAPC] vio 0
9972 11:41:21.419370 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9973 11:41:21.422766 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9974 11:41:21.425724 INFO: [APUAPC] D0_APC_0: 0x400510
9975 11:41:21.429241 INFO: [APUAPC] D0_APC_1: 0x0
9976 11:41:21.432341 INFO: [APUAPC] D0_APC_2: 0x1540
9977 11:41:21.435844 INFO: [APUAPC] D0_APC_3: 0x0
9978 11:41:21.438852 INFO: [APUAPC] D1_APC_0: 0xffffffff
9979 11:41:21.442376 INFO: [APUAPC] D1_APC_1: 0xffffffff
9980 11:41:21.445934 INFO: [APUAPC] D1_APC_2: 0x3fffff
9981 11:41:21.448789 INFO: [APUAPC] D1_APC_3: 0x0
9982 11:41:21.452437 INFO: [APUAPC] D2_APC_0: 0xffffffff
9983 11:41:21.455496 INFO: [APUAPC] D2_APC_1: 0xffffffff
9984 11:41:21.458838 INFO: [APUAPC] D2_APC_2: 0x3fffff
9985 11:41:21.458963 INFO: [APUAPC] D2_APC_3: 0x0
9986 11:41:21.465604 INFO: [APUAPC] D3_APC_0: 0xffffffff
9987 11:41:21.469215 INFO: [APUAPC] D3_APC_1: 0xffffffff
9988 11:41:21.472286 INFO: [APUAPC] D3_APC_2: 0x3fffff
9989 11:41:21.472367 INFO: [APUAPC] D3_APC_3: 0x0
9990 11:41:21.476161 INFO: [APUAPC] D4_APC_0: 0xffffffff
9991 11:41:21.478604 INFO: [APUAPC] D4_APC_1: 0xffffffff
9992 11:41:21.481910 INFO: [APUAPC] D4_APC_2: 0x3fffff
9993 11:41:21.485287 INFO: [APUAPC] D4_APC_3: 0x0
9994 11:41:21.488703 INFO: [APUAPC] D5_APC_0: 0xffffffff
9995 11:41:21.492564 INFO: [APUAPC] D5_APC_1: 0xffffffff
9996 11:41:21.495659 INFO: [APUAPC] D5_APC_2: 0x3fffff
9997 11:41:21.498924 INFO: [APUAPC] D5_APC_3: 0x0
9998 11:41:21.502455 INFO: [APUAPC] D6_APC_0: 0xffffffff
9999 11:41:21.505726 INFO: [APUAPC] D6_APC_1: 0xffffffff
10000 11:41:21.509061 INFO: [APUAPC] D6_APC_2: 0x3fffff
10001 11:41:21.512403 INFO: [APUAPC] D6_APC_3: 0x0
10002 11:41:21.515670 INFO: [APUAPC] D7_APC_0: 0xffffffff
10003 11:41:21.518577 INFO: [APUAPC] D7_APC_1: 0xffffffff
10004 11:41:21.521944 INFO: [APUAPC] D7_APC_2: 0x3fffff
10005 11:41:21.525572 INFO: [APUAPC] D7_APC_3: 0x0
10006 11:41:21.528853 INFO: [APUAPC] D8_APC_0: 0xffffffff
10007 11:41:21.532459 INFO: [APUAPC] D8_APC_1: 0xffffffff
10008 11:41:21.535356 INFO: [APUAPC] D8_APC_2: 0x3fffff
10009 11:41:21.539006 INFO: [APUAPC] D8_APC_3: 0x0
10010 11:41:21.542145 INFO: [APUAPC] D9_APC_0: 0xffffffff
10011 11:41:21.545542 INFO: [APUAPC] D9_APC_1: 0xffffffff
10012 11:41:21.548545 INFO: [APUAPC] D9_APC_2: 0x3fffff
10013 11:41:21.552191 INFO: [APUAPC] D9_APC_3: 0x0
10014 11:41:21.555215 INFO: [APUAPC] D10_APC_0: 0xffffffff
10015 11:41:21.558760 INFO: [APUAPC] D10_APC_1: 0xffffffff
10016 11:41:21.561753 INFO: [APUAPC] D10_APC_2: 0x3fffff
10017 11:41:21.565045 INFO: [APUAPC] D10_APC_3: 0x0
10018 11:41:21.569023 INFO: [APUAPC] D11_APC_0: 0xffffffff
10019 11:41:21.571998 INFO: [APUAPC] D11_APC_1: 0xffffffff
10020 11:41:21.574929 INFO: [APUAPC] D11_APC_2: 0x3fffff
10021 11:41:21.578343 INFO: [APUAPC] D11_APC_3: 0x0
10022 11:41:21.581685 INFO: [APUAPC] D12_APC_0: 0xffffffff
10023 11:41:21.584920 INFO: [APUAPC] D12_APC_1: 0xffffffff
10024 11:41:21.588348 INFO: [APUAPC] D12_APC_2: 0x3fffff
10025 11:41:21.591762 INFO: [APUAPC] D12_APC_3: 0x0
10026 11:41:21.595259 INFO: [APUAPC] D13_APC_0: 0xffffffff
10027 11:41:21.598202 INFO: [APUAPC] D13_APC_1: 0xffffffff
10028 11:41:21.601549 INFO: [APUAPC] D13_APC_2: 0x3fffff
10029 11:41:21.605204 INFO: [APUAPC] D13_APC_3: 0x0
10030 11:41:21.608502 INFO: [APUAPC] D14_APC_0: 0xffffffff
10031 11:41:21.611386 INFO: [APUAPC] D14_APC_1: 0xffffffff
10032 11:41:21.614934 INFO: [APUAPC] D14_APC_2: 0x3fffff
10033 11:41:21.618200 INFO: [APUAPC] D14_APC_3: 0x0
10034 11:41:21.621494 INFO: [APUAPC] D15_APC_0: 0xffffffff
10035 11:41:21.624777 INFO: [APUAPC] D15_APC_1: 0xffffffff
10036 11:41:21.628484 INFO: [APUAPC] D15_APC_2: 0x3fffff
10037 11:41:21.631905 INFO: [APUAPC] D15_APC_3: 0x0
10038 11:41:21.634789 INFO: [APUAPC] APC_CON: 0x4
10039 11:41:21.638438 INFO: [NOCDAPC] D0_APC_0: 0x0
10040 11:41:21.641441 INFO: [NOCDAPC] D0_APC_1: 0x0
10041 11:41:21.644790 INFO: [NOCDAPC] D1_APC_0: 0x0
10042 11:41:21.644875 INFO: [NOCDAPC] D1_APC_1: 0xfff
10043 11:41:21.648891 INFO: [NOCDAPC] D2_APC_0: 0x0
10044 11:41:21.651323 INFO: [NOCDAPC] D2_APC_1: 0xfff
10045 11:41:21.654849 INFO: [NOCDAPC] D3_APC_0: 0x0
10046 11:41:21.657904 INFO: [NOCDAPC] D3_APC_1: 0xfff
10047 11:41:21.661487 INFO: [NOCDAPC] D4_APC_0: 0x0
10048 11:41:21.664679 INFO: [NOCDAPC] D4_APC_1: 0xfff
10049 11:41:21.668072 INFO: [NOCDAPC] D5_APC_0: 0x0
10050 11:41:21.671626 INFO: [NOCDAPC] D5_APC_1: 0xfff
10051 11:41:21.675114 INFO: [NOCDAPC] D6_APC_0: 0x0
10052 11:41:21.678068 INFO: [NOCDAPC] D6_APC_1: 0xfff
10053 11:41:21.678153 INFO: [NOCDAPC] D7_APC_0: 0x0
10054 11:41:21.681636 INFO: [NOCDAPC] D7_APC_1: 0xfff
10055 11:41:21.684942 INFO: [NOCDAPC] D8_APC_0: 0x0
10056 11:41:21.688127 INFO: [NOCDAPC] D8_APC_1: 0xfff
10057 11:41:21.691462 INFO: [NOCDAPC] D9_APC_0: 0x0
10058 11:41:21.694721 INFO: [NOCDAPC] D9_APC_1: 0xfff
10059 11:41:21.698006 INFO: [NOCDAPC] D10_APC_0: 0x0
10060 11:41:21.701029 INFO: [NOCDAPC] D10_APC_1: 0xfff
10061 11:41:21.704550 INFO: [NOCDAPC] D11_APC_0: 0x0
10062 11:41:21.707919 INFO: [NOCDAPC] D11_APC_1: 0xfff
10063 11:41:21.711346 INFO: [NOCDAPC] D12_APC_0: 0x0
10064 11:41:21.714679 INFO: [NOCDAPC] D12_APC_1: 0xfff
10065 11:41:21.718083 INFO: [NOCDAPC] D13_APC_0: 0x0
10066 11:41:21.718188 INFO: [NOCDAPC] D13_APC_1: 0xfff
10067 11:41:21.721007 INFO: [NOCDAPC] D14_APC_0: 0x0
10068 11:41:21.724305 INFO: [NOCDAPC] D14_APC_1: 0xfff
10069 11:41:21.727682 INFO: [NOCDAPC] D15_APC_0: 0x0
10070 11:41:21.731174 INFO: [NOCDAPC] D15_APC_1: 0xfff
10071 11:41:21.734202 INFO: [NOCDAPC] APC_CON: 0x4
10072 11:41:21.738126 INFO: [APUAPC] set_apusys_apc done
10073 11:41:21.741031 INFO: [DEVAPC] devapc_init done
10074 11:41:21.744728 INFO: GICv3 without legacy support detected.
10075 11:41:21.747975 INFO: ARM GICv3 driver initialized in EL3
10076 11:41:21.754735 INFO: Maximum SPI INTID supported: 639
10077 11:41:21.757944 INFO: BL31: Initializing runtime services
10078 11:41:21.764553 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10079 11:41:21.764654 INFO: SPM: enable CPC mode
10080 11:41:21.770965 INFO: mcdi ready for mcusys-off-idle and system suspend
10081 11:41:21.774392 INFO: BL31: Preparing for EL3 exit to normal world
10082 11:41:21.777722 INFO: Entry point address = 0x80000000
10083 11:41:21.780706 INFO: SPSR = 0x8
10084 11:41:21.787121
10085 11:41:21.787203
10086 11:41:21.787268
10087 11:41:21.790023 Starting depthcharge on Spherion...
10088 11:41:21.790105
10089 11:41:21.790190 Wipe memory regions:
10090 11:41:21.790290
10091 11:41:21.791087 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10092 11:41:21.791191 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10093 11:41:21.791278 Setting prompt string to ['asurada:']
10094 11:41:21.791621 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10095 11:41:21.793521 [0x00000040000000, 0x00000054600000)
10096 11:41:21.915830
10097 11:41:21.915974 [0x00000054660000, 0x00000080000000)
10098 11:41:22.176212
10099 11:41:22.176350 [0x000000821a7280, 0x000000ffe64000)
10100 11:41:22.920998
10101 11:41:22.921184 [0x00000100000000, 0x00000240000000)
10102 11:41:24.811877
10103 11:41:24.814906 Initializing XHCI USB controller at 0x11200000.
10104 11:41:25.852955
10105 11:41:25.855774 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10106 11:41:25.855863
10107 11:41:25.855928
10108 11:41:25.855987
10109 11:41:25.856290 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10111 11:41:25.956611 asurada: tftpboot 192.168.201.1 10742196/tftp-deploy-dr7wgtj6/kernel/image.itb 10742196/tftp-deploy-dr7wgtj6/kernel/cmdline
10112 11:41:25.956768 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10113 11:41:25.956913 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10114 11:41:25.961244 tftpboot 192.168.201.1 10742196/tftp-deploy-dr7wgtj6/kernel/image.itp-deploy-dr7wgtj6/kernel/cmdline
10115 11:41:25.961330
10116 11:41:25.961394 Waiting for link
10117 11:41:26.122262
10118 11:41:26.122409 R8152: Initializing
10119 11:41:26.122498
10120 11:41:26.124982 Version 6 (ocp_data = 5c30)
10121 11:41:26.125064
10122 11:41:26.128679 R8152: Done initializing
10123 11:41:26.128761
10124 11:41:26.128824 Adding net device
10125 11:41:28.031687
10126 11:41:28.031819 done.
10127 11:41:28.031887
10128 11:41:28.031945 MAC: 00:24:32:30:78:52
10129 11:41:28.032003
10130 11:41:28.034610 Sending DHCP discover... done.
10131 11:41:28.034695
10132 11:41:28.038125 Waiting for reply... done.
10133 11:41:28.038236
10134 11:41:28.040858 Sending DHCP request... done.
10135 11:41:28.040962
10136 11:41:28.046043 Waiting for reply... done.
10137 11:41:28.046150
10138 11:41:28.046220 My ip is 192.168.201.14
10139 11:41:28.046281
10140 11:41:28.049537 The DHCP server ip is 192.168.201.1
10141 11:41:28.049638
10142 11:41:28.056067 TFTP server IP predefined by user: 192.168.201.1
10143 11:41:28.056150
10144 11:41:28.062583 Bootfile predefined by user: 10742196/tftp-deploy-dr7wgtj6/kernel/image.itb
10145 11:41:28.062660
10146 11:41:28.066067 Sending tftp read request... done.
10147 11:41:28.066168
10148 11:41:28.069627 Waiting for the transfer...
10149 11:41:28.069727
10150 11:41:28.611749 00000000 ################################################################
10151 11:41:28.611921
10152 11:41:29.154776 00080000 ################################################################
10153 11:41:29.154958
10154 11:41:29.700482 00100000 ################################################################
10155 11:41:29.700636
10156 11:41:30.255342 00180000 ################################################################
10157 11:41:30.255544
10158 11:41:30.822262 00200000 ################################################################
10159 11:41:30.822409
10160 11:41:31.375465 00280000 ################################################################
10161 11:41:31.375635
10162 11:41:31.911768 00300000 ################################################################
10163 11:41:31.911909
10164 11:41:32.455228 00380000 ################################################################
10165 11:41:32.455375
10166 11:41:32.996017 00400000 ################################################################
10167 11:41:32.996149
10168 11:41:33.548262 00480000 ################################################################
10169 11:41:33.548427
10170 11:41:34.112600 00500000 ################################################################
10171 11:41:34.112753
10172 11:41:34.674927 00580000 ################################################################
10173 11:41:34.675115
10174 11:41:35.228742 00600000 ################################################################
10175 11:41:35.228874
10176 11:41:35.785093 00680000 ################################################################
10177 11:41:35.785270
10178 11:41:36.344413 00700000 ################################################################
10179 11:41:36.344566
10180 11:41:36.889946 00780000 ################################################################
10181 11:41:36.890115
10182 11:41:37.409054 00800000 ################################################################
10183 11:41:37.409208
10184 11:41:37.967070 00880000 ################################################################
10185 11:41:37.967224
10186 11:41:38.539503 00900000 ################################################################
10187 11:41:38.539670
10188 11:41:39.075883 00980000 ################################################################
10189 11:41:39.076040
10190 11:41:39.634944 00a00000 ################################################################
10191 11:41:39.635132
10192 11:41:40.201842 00a80000 ################################################################
10193 11:41:40.202051
10194 11:41:40.789045 00b00000 ################################################################
10195 11:41:40.789564
10196 11:41:41.392017 00b80000 ################################################################
10197 11:41:41.392169
10198 11:41:41.969174 00c00000 ################################################################
10199 11:41:41.969319
10200 11:41:42.575136 00c80000 ################################################################
10201 11:41:42.575853
10202 11:41:43.250266 00d00000 ################################################################
10203 11:41:43.250432
10204 11:41:43.854205 00d80000 ################################################################
10205 11:41:43.854367
10206 11:41:44.408276 00e00000 ################################################################
10207 11:41:44.408834
10208 11:41:45.045567 00e80000 ################################################################
10209 11:41:45.046160
10210 11:41:45.790953 00f00000 ################################################################
10211 11:41:45.791666
10212 11:41:46.527785 00f80000 ################################################################
10213 11:41:46.528339
10214 11:41:47.258567 01000000 ################################################################
10215 11:41:47.259084
10216 11:41:47.923033 01080000 ################################################################
10217 11:41:47.923186
10218 11:41:48.593628 01100000 ################################################################
10219 11:41:48.594144
10220 11:41:49.283218 01180000 ################################################################
10221 11:41:49.283384
10222 11:41:49.915693 01200000 ################################################################
10223 11:41:49.916199
10224 11:41:50.481200 01280000 ################################################################
10225 11:41:50.481380
10226 11:41:51.056957 01300000 ################################################################
10227 11:41:51.057114
10228 11:41:51.629455 01380000 ################################################################
10229 11:41:51.629606
10230 11:41:52.178828 01400000 ################################################################
10231 11:41:52.178989
10232 11:41:52.741502 01480000 ################################################################
10233 11:41:52.741661
10234 11:41:53.313552 01500000 ################################################################
10235 11:41:53.313711
10236 11:41:53.877965 01580000 ################################################################
10237 11:41:53.878109
10238 11:41:54.440397 01600000 ################################################################
10239 11:41:54.440537
10240 11:41:54.991048 01680000 ################################################################
10241 11:41:54.991221
10242 11:41:55.531624 01700000 ################################################################
10243 11:41:55.531811
10244 11:41:56.067203 01780000 ################################################################
10245 11:41:56.067407
10246 11:41:56.603513 01800000 ################################################################
10247 11:41:56.603664
10248 11:41:57.165411 01880000 ################################################################
10249 11:41:57.165604
10250 11:41:57.737380 01900000 ################################################################
10251 11:41:57.737529
10252 11:41:58.265025 01980000 ################################################################
10253 11:41:58.265230
10254 11:41:58.830049 01a00000 ################################################################
10255 11:41:58.830202
10256 11:41:59.200774 01a80000 ########################################### done.
10257 11:41:59.200925
10258 11:41:59.203718 The bootfile was 28132402 bytes long.
10259 11:41:59.203804
10260 11:41:59.207213 Sending tftp read request... done.
10261 11:41:59.207298
10262 11:41:59.210249 Waiting for the transfer...
10263 11:41:59.210333
10264 11:41:59.210399 00000000 # done.
10265 11:41:59.210463
10266 11:41:59.220312 Command line loaded dynamically from TFTP file: 10742196/tftp-deploy-dr7wgtj6/kernel/cmdline
10267 11:41:59.220455
10268 11:41:59.236570 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742196/extract-nfsrootfs-p6y5mcne,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10269 11:41:59.236661
10270 11:41:59.236727 Loading FIT.
10271 11:41:59.236788
10272 11:41:59.240191 Image ramdisk-1 has 17640084 bytes.
10273 11:41:59.240274
10274 11:41:59.243473 Image fdt-1 has 46924 bytes.
10275 11:41:59.243557
10276 11:41:59.246888 Image kernel-1 has 10443363 bytes.
10277 11:41:59.246971
10278 11:41:59.256634 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10279 11:41:59.256719
10280 11:41:59.273082 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10281 11:41:59.273175
10282 11:41:59.276989 Choosing best match conf-1 for compat google,spherion-rev2.
10283 11:41:59.281776
10284 11:41:59.286018 Connected to device vid:did:rid of 1ae0:0028:00
10285 11:41:59.293596
10286 11:41:59.297218 tpm_get_response: command 0x17b, return code 0x0
10287 11:41:59.297304
10288 11:41:59.300681 ec_init: CrosEC protocol v3 supported (256, 248)
10289 11:41:59.304424
10290 11:41:59.307451 tpm_cleanup: add release locality here.
10291 11:41:59.307561
10292 11:41:59.307654 Shutting down all USB controllers.
10293 11:41:59.311060
10294 11:41:59.311159 Removing current net device
10295 11:41:59.311248
10296 11:41:59.317489 Exiting depthcharge with code 4 at timestamp: 66904347
10297 11:41:59.317573
10298 11:41:59.321049 LZMA decompressing kernel-1 to 0x821a6718
10299 11:41:59.321132
10300 11:41:59.323999 LZMA decompressing kernel-1 to 0x40000000
10301 11:42:00.635395
10302 11:42:00.635543 jumping to kernel
10303 11:42:00.635969 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10304 11:42:00.636082 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10305 11:42:00.636163 Setting prompt string to ['Linux version [0-9]']
10306 11:42:00.636234 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10307 11:42:00.636309 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10308 11:42:01.187284
10309 11:42:01.190705 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10310 11:42:01.193870 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10311 11:42:01.194016 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10312 11:42:01.194151 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10313 11:42:01.194261 Using line separator: #'\n'#
10314 11:42:01.194365 No login prompt set.
10315 11:42:01.194460 Parsing kernel messages
10316 11:42:01.194566 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10317 11:42:01.194752 [login-action] Waiting for messages, (timeout 00:03:46)
10318 11:42:01.213738 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10319 11:42:01.216721 [ 0.000000] random: crng init done
10320 11:42:01.223403 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10321 11:42:01.223537 [ 0.000000] efi: UEFI not found.
10322 11:42:01.233304 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10323 11:42:01.239824 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10324 11:42:01.249895 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10325 11:42:01.259988 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10326 11:42:01.262961 [ 0.000000] NUMA: No NUMA configuration found
10327 11:42:01.273092 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10328 11:42:01.276003 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10329 11:42:01.279541 [ 0.000000] Zone ranges:
10330 11:42:01.286098 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10331 11:42:01.289132 [ 0.000000] DMA32 empty
10332 11:42:01.296229 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10333 11:42:01.299214 [ 0.000000] Movable zone start for each node
10334 11:42:01.302846 [ 0.000000] Early memory node ranges
10335 11:42:01.309027 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10336 11:42:01.315384 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10337 11:42:01.322516 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10338 11:42:01.328748 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10339 11:42:01.332078 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10340 11:42:01.342315 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10341 11:42:01.345139 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10342 11:42:01.352279 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10343 11:42:01.358620 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10344 11:42:01.362120 [ 0.000000] psci: probing for conduit method from DT.
10345 11:42:01.368356 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10346 11:42:01.371929 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10347 11:42:01.378423 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10348 11:42:01.381916 [ 0.000000] psci: SMC Calling Convention v1.2
10349 11:42:01.388185 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10350 11:42:01.391887 [ 0.000000] Detected VIPT I-cache on CPU0
10351 11:42:01.398371 [ 0.000000] CPU features: detected: GIC system register CPU interface
10352 11:42:01.404903 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10353 11:42:01.411272 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10354 11:42:01.417853 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10355 11:42:01.427910 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10356 11:42:01.434588 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10357 11:42:01.437671 [ 0.000000] alternatives: applying boot alternatives
10358 11:42:01.441134 [ 0.000000] Fallback order for Node 0: 0
10359 11:42:01.447896 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10360 11:42:01.451248 [ 0.000000] Policy zone: Normal
10361 11:42:01.470835 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742196/extract-nfsrootfs-p6y5mcne,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10362 11:42:01.481335 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10363 11:42:01.487719 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10364 11:42:01.497680 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10365 11:42:01.504048 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10366 11:42:01.507704 [ 0.000000] software IO TLB: area num 8.
10367 11:42:01.514286 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10368 11:42:01.527454 [ 0.000000] Memory: 7953932K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398836K reserved, 32768K cma-reserved)
10369 11:42:01.534209 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10370 11:42:01.540872 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10371 11:42:01.544320 [ 0.000000] rcu: RCU event tracing is enabled.
10372 11:42:01.550591 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10373 11:42:01.557007 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10374 11:42:01.560358 [ 0.000000] Tracing variant of Tasks RCU enabled.
10375 11:42:01.570423 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10376 11:42:01.576799 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10377 11:42:01.580424 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10378 11:42:01.586942 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10379 11:42:01.589939 [ 0.000000] GICv3: 608 SPIs implemented
10380 11:42:01.593405 [ 0.000000] GICv3: 0 Extended SPIs implemented
10381 11:42:01.600452 [ 0.000000] Root IRQ handler: gic_handle_irq
10382 11:42:01.603391 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10383 11:42:01.609962 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10384 11:42:01.623236 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10385 11:42:01.633630 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10386 11:42:01.639763 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10387 11:42:01.646913 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10388 11:42:01.656212 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10389 11:42:01.666568 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10390 11:42:01.670052 [ 0.000944] Console: colour dummy device 80x25
10391 11:42:01.679696 [ 0.001010] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10392 11:42:01.686188 [ 0.001017] pid_max: default: 32768 minimum: 301
10393 11:42:01.689799 [ 0.001059] LSM: Security Framework initializing
10394 11:42:01.696329 [ 0.001164] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 11:42:01.706177 [ 0.001217] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 11:42:01.712836 [ 0.002456] cblist_init_generic: Setting adjustable number of callback queues.
10397 11:42:01.719031 [ 0.002467] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 11:42:01.726003 [ 0.002509] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 11:42:01.729062 [ 0.002613] rcu: Hierarchical SRCU implementation.
10400 11:42:01.735669 [ 0.002615] rcu: Max phase no-delay instances is 1000.
10401 11:42:01.739656 [ 0.004241] EFI services will not be available.
10402 11:42:01.742443 [ 0.004462] smp: Bringing up secondary CPUs ...
10403 11:42:01.749099 [ 0.004752] Detected VIPT I-cache on CPU1
10404 11:42:01.755726 [ 0.004825] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10405 11:42:01.762537 [ 0.004857] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10406 11:42:01.765628 [ 0.005200] Detected VIPT I-cache on CPU2
10407 11:42:01.772604 [ 0.005252] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10408 11:42:01.778848 [ 0.005269] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10409 11:42:01.782182 [ 0.005529] Detected VIPT I-cache on CPU3
10410 11:42:01.788630 [ 0.005576] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10411 11:42:01.795736 [ 0.005590] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10412 11:42:01.802124 [ 0.005896] CPU features: detected: Spectre-v4
10413 11:42:01.805572 [ 0.005903] CPU features: detected: Spectre-BHB
10414 11:42:01.809127 [ 0.005909] Detected PIPT I-cache on CPU4
10415 11:42:01.815118 [ 0.005969] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10416 11:42:01.821767 [ 0.005985] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10417 11:42:01.825234 [ 0.006282] Detected PIPT I-cache on CPU5
10418 11:42:01.834909 [ 0.006346] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10419 11:42:01.841891 [ 0.006363] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10420 11:42:01.845273 [ 0.006645] Detected PIPT I-cache on CPU6
10421 11:42:01.851489 [ 0.006712] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10422 11:42:01.858224 [ 0.006728] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10423 11:42:01.861446 [ 0.007028] Detected PIPT I-cache on CPU7
10424 11:42:01.868107 [ 0.007095] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10425 11:42:01.874860 [ 0.007112] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10426 11:42:01.878192 [ 0.007159] smp: Brought up 1 node, 8 CPUs
10427 11:42:01.884553 [ 0.007165] SMP: Total of 8 processors activated.
10428 11:42:01.887968 [ 0.007168] CPU features: detected: 32-bit EL0 Support
10429 11:42:01.898057 [ 0.007170] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10430 11:42:01.904422 [ 0.007173] CPU features: detected: Common not Private translations
10431 11:42:01.907679 [ 0.007175] CPU features: detected: CRC32 instructions
10432 11:42:01.914533 [ 0.007178] CPU features: detected: RCpc load-acquire (LDAPR)
10433 11:42:01.921011 [ 0.007180] CPU features: detected: LSE atomic instructions
10434 11:42:01.927483 [ 0.007181] CPU features: detected: Privileged Access Never
10435 11:42:01.931031 [ 0.007183] CPU features: detected: RAS Extension Support
10436 11:42:01.937357 [ 0.007186] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10437 11:42:01.943933 [ 0.007255] CPU: All CPU(s) started at EL2
10438 11:42:01.947318 [ 0.007257] alternatives: applying system-wide alternatives
10439 11:42:01.950757 [ 0.012236] devtmpfs: initialized
10440 11:42:01.961133 [ 0.017527] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10441 11:42:01.967141 [ 0.017542] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10442 11:42:01.974174 [ 0.018569] pinctrl core: initialized pinctrl subsystem
10443 11:42:01.977121 [ 0.019926] DMI not present or invalid.
10444 11:42:01.983892 [ 0.020264] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10445 11:42:01.990809 [ 0.021001] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10446 11:42:01.997136 [ 0.021228] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10447 11:42:02.006708 [ 0.021406] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10448 11:42:02.010092 [ 0.021432] audit: initializing netlink subsys (disabled)
10449 11:42:02.020013 [ 0.021503] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10450 11:42:02.026533 [ 0.022248] thermal_sys: Registered thermal governor 'step_wise'
10451 11:42:02.030111 [ 0.022252] thermal_sys: Registered thermal governor 'power_allocator'
10452 11:42:02.036627 [ 0.022281] cpuidle: using governor menu
10453 11:42:02.040170 [ 0.022345] NET: Registered PF_QIPCRTR protocol family
10454 11:42:02.046683 [ 0.022462] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10455 11:42:02.053579 [ 0.022553] ASID allocator initialised with 32768 entries
10456 11:42:02.056884 [ 0.023550] Serial: AMBA PL011 UART driver
10457 11:42:02.063611 [ 0.028289] Trying to register duplicate clock ID: 134
10458 11:42:02.063707 [ 0.083220] KASLR enabled
10459 11:42:02.070412 [ 0.088104] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10460 11:42:02.076577 [ 0.088109] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10461 11:42:02.082962 [ 0.088113] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10462 11:42:02.089865 [ 0.088115] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10463 11:42:02.096533 [ 0.088118] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10464 11:42:02.103158 [ 0.088120] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10465 11:42:02.109716 [ 0.088124] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10466 11:42:02.116228 [ 0.088126] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10467 11:42:02.119718 [ 0.089117] ACPI: Interpreter disabled.
10468 11:42:02.126305 [ 0.091529] iommu: Default domain type: Translated
10469 11:42:02.132868 [ 0.091532] iommu: DMA domain TLB invalidation policy: strict mode
10470 11:42:02.135948 [ 0.091710] SCSI subsystem initialized
10471 11:42:02.139319 [ 0.091902] usbcore: registered new interface driver usbfs
10472 11:42:02.146288 [ 0.091919] usbcore: registered new interface driver hub
10473 11:42:02.153016 [ 0.091932] usbcore: registered new device driver usb
10474 11:42:02.156042 [ 0.092790] pps_core: LinuxPPS API ver. 1 registered
10475 11:42:02.165994 [ 0.092793] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10476 11:42:02.169129 [ 0.092799] PTP clock support registered
10477 11:42:02.172581 [ 0.092884] EDAC MC: Ver: 3.0.0
10478 11:42:02.176035 [ 0.094708] FPGA manager framework
10479 11:42:02.182352 [ 0.094748] Advanced Linux Sound Architecture Driver Initialized.
10480 11:42:02.185850 [ 0.095191] vgaarb: loaded
10481 11:42:02.188765 [ 0.095398] clocksource: Switched to clocksource arch_sys_counter
10482 11:42:02.195626 [ 0.095513] VFS: Disk quotas dquot_6.6.0
10483 11:42:02.202488 [ 0.095541] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10484 11:42:02.205513 [ 0.095647] pnp: PnP ACPI: disabled
10485 11:42:02.209078 [ 0.098342] NET: Registered PF_INET protocol family
10486 11:42:02.218623 [ 0.098881] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10487 11:42:02.225401 [ 0.103424] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10488 11:42:02.231868 [ 0.103498] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10489 11:42:02.241953 [ 0.103511] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10490 11:42:02.248340 [ 0.104084] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10491 11:42:02.255308 [ 0.106225] TCP: Hash tables configured (established 65536 bind 65536)
10492 11:42:02.261978 [ 0.106334] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 11:42:02.268421 [ 0.106526] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 11:42:02.275144 [ 0.106787] NET: Registered PF_UNIX/PF_LOCAL protocol family
10495 11:42:02.281736 [ 0.107075] RPC: Registered named UNIX socket transport module.
10496 11:42:02.284628 [ 0.107080] RPC: Registered udp transport module.
10497 11:42:02.291492 [ 0.107081] RPC: Registered tcp transport module.
10498 11:42:02.298327 [ 0.107083] RPC: Registered tcp NFSv4.1 backchannel transport module.
10499 11:42:02.301653 [ 0.107095] PCI: CLS 0 bytes, default 64
10500 11:42:02.304462 [ 0.107300] Unpacking initramfs...
10501 11:42:02.311074 [ 0.116049] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10502 11:42:02.321225 [ 0.116281] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10503 11:42:02.324572 [ 0.116783] kvm [1]: IPA Size Limit: 40 bits
10504 11:42:02.328029 [ 0.116810] kvm [1]: GICv3: no GICV resource entry
10505 11:42:02.334503 [ 0.116814] kvm [1]: disabling GICv2 emulation
10506 11:42:02.341056 [ 0.116827] kvm [1]: GIC system register CPU interface enabled
10507 11:42:02.344655 [ 0.116915] kvm [1]: vgic interrupt IRQ18
10508 11:42:02.347574 [ 0.117013] kvm [1]: VHE mode initialized successfully
10509 11:42:02.354682 [ 0.117938] Initialise system trusted keyrings
10510 11:42:02.361108 [ 0.118035] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10511 11:42:02.364476 [ 0.121422] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10512 11:42:02.371033 [ 0.121729] NFS: Registering the id_resolver key type
10513 11:42:02.374387 [ 0.121745] Key type id_resolver registered
10514 11:42:02.377445 [ 0.121748] Key type id_legacy registered
10515 11:42:02.384941 [ 0.121786] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10516 11:42:02.394010 [ 0.121790] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10517 11:42:02.397108 [ 0.121874] 9p: Installing v9fs 9p2000 file system support
10518 11:42:02.400843 [ 0.154053] Key type asymmetric registered
10519 11:42:02.407105 [ 0.154058] Asymmetric key parser 'x509' registered
10520 11:42:02.413703 [ 0.154128] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10521 11:42:02.420777 [ 0.154132] io scheduler mq-deadline registered
10522 11:42:02.423529 [ 0.154136] io scheduler kyber registered
10523 11:42:02.427138 [ 0.167406] EINJ: ACPI disabled.
10524 11:42:02.436941 [ 0.190074] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 11:42:02.447133 [ 0.190232] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 11:42:02.453732 [ 0.200482] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10527 11:42:02.457046 [ 0.201891] printk: console [ttyS0] disabled
10528 11:42:02.466690 [ 0.222040] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10529 11:42:02.470183 [ 0.869432] Freeing initrd memory: 17220K
10530 11:42:02.473071 [ 0.870480] printk: console [ttyS0] enabled
10531 11:42:02.480548 [ 1.512519] SuperH (H)SCI(F) driver initialized
10532 11:42:02.483803 [ 1.517550] msm_serial: driver initialized
10533 11:42:02.497799 [ 1.526280] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10534 11:42:02.504563 [ 1.534569] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10535 11:42:02.514331 [ 1.542850] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10536 11:42:02.524435 [ 1.551219] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10537 11:42:02.530801 [ 1.559665] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10538 11:42:02.540941 [ 1.568118] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10539 11:42:02.547433 [ 1.576398] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10540 11:42:02.557498 [ 1.584940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10541 11:42:02.563917 [ 1.593221] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10542 11:42:02.573505 [ 1.608419] loop: module loaded
10543 11:42:02.582172 [ 1.614043] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10544 11:42:02.605033 [ 1.636854] mtk-pmic-keys: Failed to locate of_node [id: -1]
10545 11:42:02.611713 [ 1.643186] megasas: 07.719.03.00-rc1
10546 11:42:02.620899 [ 1.652561] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10547 11:42:02.629048 [ 1.658773] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10548 11:42:02.634361 [ 1.663822] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10549 11:42:02.645364 [ 1.675591] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10550 11:42:02.649572 [ 1.675694] tun: Universal TUN/TAP device driver, 1.6
10551 11:42:02.658508 [ 1.687594] thunder_xcv, ver 1.0
10552 11:42:02.663108 [ 1.690830] thunder_bgx, ver 1.0
10553 11:42:02.663197 [ 1.694065] nicpf, ver 1.0
10554 11:42:02.678543 [ 1.697826] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10555 11:42:02.678908 [ 1.705040] hns3: Copyright (c) 2017 Huawei Corporation.
10556 11:42:02.679021 [ 1.710369] hclge is initializing
10557 11:42:02.684492 [ 1.713690] e1000: Intel(R) PRO/1000 Network Driver
10558 11:42:02.689357 [ 1.718560] e1000: Copyright (c) 1999-2006 Intel Corporation.
10559 11:42:02.695063 [ 1.724312] e1000e: Intel(R) PRO/1000 Network Driver
10560 11:42:02.699838 [ 1.729267] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10561 11:42:02.703759 [ 1.735191] igb: Intel(R) Gigabit Ethernet Network Driver
10562 11:42:02.713455 [ 1.740537] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10563 11:42:02.720149 [ 1.740581] igb: Copyright (c) 2007-2014 Intel Corporation.
10564 11:42:02.727246 [ 1.756920] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10565 11:42:02.733493 [ 1.763177] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10566 11:42:02.736582 [ 1.769382] sky2: driver version 1.30
10567 11:42:02.743296 [ 1.774141] VFIO - User Level meta-driver version: 0.3
10568 11:42:02.750261 [ 1.782139] usbcore: registered new interface driver usb-storage
10569 11:42:02.757221 [ 1.788322] usbcore: registered new device driver onboard-usb-hub
10570 11:42:02.765665 [ 1.797176] mt6397-rtc mt6359-rtc: registered as rtc0
10571 11:42:02.775653 [ 1.802379] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:42:02 UTC (1686829322)
10572 11:42:02.778535 [ 1.811708] i2c_dev: i2c /dev entries driver
10573 11:42:02.795087 [ 1.823269] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10574 11:42:02.801723 [ 1.833244] sdhci: Secure Digital Host Controller Interface driver
10575 11:42:02.808037 [ 1.839421] sdhci: Copyright(c) Pierre Ossman
10576 11:42:02.815044 [ 1.844606] Synopsys Designware Multimedia Card Interface Driver
10577 11:42:02.818099 [ 1.851048] mmc0: CQHCI version 5.10
10578 11:42:02.824745 [ 1.851537] sdhci-pltfm: SDHCI platform and OF driver helper
10579 11:42:02.831662 [ 1.862455] ledtrig-cpu: registered to indicate activity on CPUs
10580 11:42:02.838139 [ 1.869517] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10581 11:42:02.844988 [ 1.876683] usbcore: registered new interface driver usbhid
10582 11:42:02.847870 [ 1.882255] usbhid: USB HID core driver
10583 11:42:02.854952 [ 1.886243] spi_master spi0: will run message pump with realtime priority
10584 11:42:02.898027 [ 1.923133] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10585 11:42:02.912495 [ 1.937813] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10586 11:42:02.920268 [ 1.952255] mmc0: Command Queue Engine enabled
10587 11:42:02.927625 [ 1.952301] cros-ec-spi spi0.0: Chrome EC device registered
10588 11:42:02.930396 [ 1.956718] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10589 11:42:02.937503 [ 1.969392] mmcblk0: mmc0:0001 DA4128 116 GiB
10590 11:42:02.949738 [ 1.978007] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10591 11:42:02.956302 [ 1.983645] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10592 11:42:02.959530 [ 1.989191] NET: Registered PF_PACKET protocol family
10593 11:42:02.966487 [ 1.995222] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10594 11:42:02.969470 [ 1.997873] 9pnet: Installing 9P2000 support
10595 11:42:02.975920 [ 2.003679] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10596 11:42:02.979455 [ 2.007023] Key type dns_resolver registered
10597 11:42:02.985906 [ 2.012733] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10598 11:42:02.989423 [ 2.016726] registered taskstats version 1
10599 11:42:02.995766 [ 2.026599] Loading compiled-in X.509 certificates
10600 11:42:03.028765 [ 2.053849] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10601 11:42:03.038611 [ 2.064291] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 11:42:03.048873 [ 2.076711] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10603 11:42:03.060004 [ 2.092128] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10604 11:42:03.067240 [ 2.098716] xhci-mtk 11200000.usb: xHCI Host Controller
10605 11:42:03.073737 [ 2.103960] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10606 11:42:03.083678 [ 2.111572] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10607 11:42:03.090179 [ 2.120749] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10608 11:42:03.093306 [ 2.126579] xhci-mtk 11200000.usb: xHCI Host Controller
10609 11:42:03.103453 [ 2.131801] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10610 11:42:03.110100 [ 2.139190] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10611 11:42:03.113434 [ 2.146810] hub 1-0:1.0: USB hub found
10612 11:42:03.116591 [ 2.150596] hub 1-0:1.0: 1 port detected
10613 11:42:03.126421 [ 2.154686] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10614 11:42:03.129773 [ 2.163232] hub 2-0:1.0: USB hub found
10615 11:42:03.133686 [ 2.167007] hub 2-0:1.0: 1 port detected
10616 11:42:03.142279 [ 2.174184] mtk-msdc 11f70000.mmc: Got CD GPIO
10617 11:42:03.158868 [ 2.187321] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10618 11:42:03.165833 [ 2.195094] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10619 11:42:03.175776 [ 2.202820] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10620 11:42:03.182351 [ 2.212231] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10621 11:42:03.192055 [ 2.220053] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10622 11:42:03.198714 [ 2.227830] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10623 11:42:03.205260 [ 2.235488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10624 11:42:03.215782 [ 2.243048] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10625 11:42:03.222012 [ 2.250609] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10626 11:42:03.232572 [ 2.261095] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10627 11:42:03.239336 [ 2.269200] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10628 11:42:03.249171 [ 2.277300] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10629 11:42:03.256059 [ 2.285382] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10630 11:42:03.265964 [ 2.293465] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10631 11:42:03.272477 [ 2.301548] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10632 11:42:03.282666 [ 2.309630] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10633 11:42:03.289468 [ 2.317712] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10634 11:42:03.296088 [ 2.325794] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10635 11:42:03.305609 [ 2.333876] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10636 11:42:03.312416 [ 2.341958] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10637 11:42:03.322369 [ 2.350040] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10638 11:42:03.329109 [ 2.358122] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10639 11:42:03.339270 [ 2.366204] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10640 11:42:03.345828 [ 2.374288] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10641 11:42:03.352569 [ 2.383010] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10642 11:42:03.359273 [ 2.390295] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10643 11:42:03.365523 [ 2.397166] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10644 11:42:03.372399 [ 2.404094] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10645 11:42:03.378985 [ 2.411197] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10646 11:42:03.389676 [ 2.417868] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10647 11:42:03.399176 [ 2.426748] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10648 11:42:03.409481 [ 2.435614] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10649 11:42:03.415764 [ 2.444654] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10650 11:42:03.425924 [ 2.453870] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10651 11:42:03.436065 [ 2.463083] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10652 11:42:03.445556 [ 2.471967] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10653 11:42:03.452287 [ 2.481181] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10654 11:42:03.462467 [ 2.490048] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10655 11:42:03.472213 [ 2.499089] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10656 11:42:03.482197 [ 2.508994] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10657 11:42:03.492462 [ 2.520583] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10658 11:42:03.498665 [ 2.530245] Trying to probe devices needed for running init ...
10659 11:42:03.539659 [ 2.571674] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10660 11:42:03.697446 [ 2.729065] hub 1-1:1.0: USB hub found
10661 11:42:03.700868 [ 2.733236] hub 1-1:1.0: 4 ports detected
10662 11:42:03.820310 [ 2.851871] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10663 11:42:03.848417 [ 2.880197] hub 2-1:1.0: USB hub found
10664 11:42:03.851863 [ 2.884388] hub 2-1:1.0: 3 ports detected
10665 11:42:04.016290 [ 3.047670] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10666 11:42:04.151738 [ 3.183587] hub 1-1.4:1.0: USB hub found
10667 11:42:04.154742 [ 3.188002] hub 1-1.4:1.0: 2 ports detected
10668 11:42:04.231186 [ 3.259925] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10669 11:42:04.451301 [ 3.479669] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10670 11:42:04.643238 [ 3.671669] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10671 11:42:15.780495 [ 14.816227] ALSA device list:
10672 11:42:15.783292 [ 14.819201] No soundcards found.
10673 11:42:15.798428 [ 14.831364] Freeing unused kernel memory: 8384K
10674 11:42:15.801803 [ 14.836025] Run /init as init process
10675 11:42:15.812128 Loading, please wait...
10676 11:42:15.831083 Starting version 247.3-7+deb11u2
10677 11:42:16.148421 [ 15.177917] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10678 11:42:16.157585 [ 15.190443] remoteproc remoteproc0: scp is available
10679 11:42:16.167231 [ 15.195850] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10680 11:42:16.174045 [ 15.205456] remoteproc remoteproc0: powering up scp
10681 11:42:16.181167 [ 15.209066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 11:42:16.190317 [ 15.211234] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10683 11:42:16.197306 [ 15.218323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 11:42:16.203596 [ 15.224875] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10685 11:42:16.210537 [ 15.227726] remoteproc remoteproc0: request_firmware failed: -2
10686 11:42:16.217120 [ 15.244076] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10687 11:42:16.227336 [ 15.248957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 11:42:16.233813 [ 15.257520] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10689 11:42:16.240209 [ 15.268436] mc: Linux media interface: v0.10
10690 11:42:16.247173 [ 15.268519] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 11:42:16.253749 [ 15.268541] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 11:42:16.263178 [ 15.268549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 11:42:16.270251 [ 15.268558] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 11:42:16.279940 [ 15.268565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 11:42:16.286451 [ 15.268632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 11:42:16.293270 [ 15.268689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 11:42:16.300364 [ 15.268696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 11:42:16.310819 [ 15.268702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 11:42:16.317005 [ 15.268752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 11:42:16.323447 [ 15.268758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 11:42:16.333685 [ 15.268765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 11:42:16.340320 [ 15.268771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 11:42:16.350364 [ 15.268777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 11:42:16.356699 [ 15.272781] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10705 11:42:16.363087 [ 15.280682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 11:42:16.370153 [ 15.280730] usbcore: registered new interface driver r8152
10707 11:42:16.380100 [ 15.293685] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10708 11:42:16.383448 [ 15.293685] Fallback method does not support PEC.
10709 11:42:16.390197 [ 15.296080] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10710 11:42:16.396616 [ 15.296300] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10711 11:42:16.403685 [ 15.309231] videodev: Linux video capture interface: v2.00
10712 11:42:16.410018 [ 15.335427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10713 11:42:16.416875 [ 15.367803] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10714 11:42:16.423012 [ 15.404767] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10715 11:42:16.433096 [ 15.410792] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10716 11:42:16.443428 [ 15.412637] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10717 11:42:16.449501 [ 15.421437] pci_bus 0000:00: root bus resource [bus 00-ff]
10718 11:42:16.456506 [ 15.421445] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10719 11:42:16.466009 [ 15.421451] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10720 11:42:16.472697 [ 15.421495] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10721 11:42:16.479301 [ 15.421514] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10722 11:42:16.486074 [ 15.428986] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10723 11:42:16.496145 [ 15.435504] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10724 11:42:16.502428 [ 15.435514] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10725 11:42:16.509295 [ 15.435735] pci 0000:00:00.0: supports D1 D2
10726 11:42:16.516109 [ 15.447350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 11:42:16.522630 [ 15.449676] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10728 11:42:16.529170 [ 15.463490] usbcore: registered new interface driver cdc_ether
10729 11:42:16.539270 [ 15.475536] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10730 11:42:16.542349 [ 15.488601] Bluetooth: Core ver 2.22
10731 11:42:16.545495 [ 15.488609] usbcore: registered new interface driver r8153_ecm
10732 11:42:16.552464 [ 15.494559] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10733 11:42:16.558714 [ 15.504140] NET: Registered PF_BLUETOOTH protocol family
10734 11:42:16.565736 [ 15.510086] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10735 11:42:16.572371 [ 15.511199] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10736 11:42:16.585215 [ 15.512633] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10737 11:42:16.588676 [ 15.512905] usbcore: registered new interface driver uvcvideo
10738 11:42:16.595128 [ 15.517275] Bluetooth: HCI device and connection manager initialized
10739 11:42:16.605195 [ 15.526064] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10740 11:42:16.608836 [ 15.526125] r8152 2-1.3:1.0 eth0: v1.12.13
10741 11:42:16.614918 [ 15.534115] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10742 11:42:16.618358 [ 15.534841] Bluetooth: HCI socket layer initialized
10743 11:42:16.625122 [ 15.542676] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10744 11:42:16.632035 [ 15.546932] Bluetooth: L2CAP socket layer initialized
10745 11:42:16.638628 [ 15.547650] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10746 11:42:16.641874 [ 15.555559] pci 0000:01:00.0: supports D1 D2
10747 11:42:16.644892 [ 15.562060] Bluetooth: SCO socket layer initialized
10748 11:42:16.651629 [ 15.567875] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10749 11:42:16.658269 [ 15.611355] usbcore: registered new interface driver btusb
10750 11:42:16.668034 [ 15.612255] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10751 11:42:16.674583 [ 15.612266] Bluetooth: hci0: Failed to load firmware file (-2)
10752 11:42:16.681251 [ 15.612270] Bluetooth: hci0: Failed to set up firmware (-2)
10753 11:42:16.691313 [ 15.612274] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10754 11:42:16.697779 [ 15.631443] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10755 11:42:16.704925 [ 15.734951] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10756 11:42:16.711163 [ 15.742778] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10757 11:42:16.721232 [ 15.750526] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10758 11:42:16.727982 [ 15.758276] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10759 11:42:16.734401 [ 15.766024] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10760 11:42:16.741081 [ 15.773771] pci 0000:00:00.0: PCI bridge to [bus 01]
10761 11:42:16.747883 [ 15.778759] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10762 11:42:16.754189 [ 15.786644] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10763 11:42:16.760820 [ 15.793626] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10764 11:42:16.767653 [ 15.800144] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10765 11:42:16.786251 [ 15.816723] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10766 11:42:16.802362 [ 15.835554] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10767 11:42:16.811906 [ 15.842199] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10768 11:42:16.818503 [ 15.850831] cfg80211: failed to load regulatory.db
10769 11:42:16.863476 [ 15.893218] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10770 11:42:16.866344 [ 15.900487] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10771 11:42:16.893696 [ 15.927034] mt7921e 0000:01:00.0: ASIC revision: 79610010
10772 11:42:17.000236 [ 16.027118] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 11:42:17.014138 Begin: Loading essential drivers ... done.
10774 11:42:17.017545 Begin: Running /scripts/init-premount ... done.
10775 11:42:17.023968 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10776 11:42:17.034209 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10777 11:42:17.037225 Device /sys/class/net/enx002432307852 found
10778 11:42:17.037337 done.
10779 11:42:17.093308 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10780 11:42:17.119065 [ 16.145910] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 11:42:17.238828 [ 16.265258] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 11:42:17.354207 [ 16.381102] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 11:42:17.470376 [ 16.497044] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 11:42:17.586494 [ 16.612919] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 11:42:17.702709 [ 16.729127] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 11:42:17.818981 [ 16.844983] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 11:42:17.934673 [ 16.960952] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 11:42:18.050337 [ 17.076924] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 11:42:18.158073 [ 17.190851] mt7921e 0000:01:00.0: hardware init failed
10790 11:42:18.172498 [ 17.205381] r8152 2-1.3:1.0 enx002432307852: carrier on
10791 11:42:18.269372 IP-Config: no response after 2 secs - giving up
10792 11:42:18.302383 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10793 11:42:18.312516 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10794 11:42:18.319660 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10795 11:42:18.326109 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10796 11:42:18.332431 host : mt8192-asurada-spherion-r0-cbg-3
10797 11:42:18.338930 domain : lava-rack
10798 11:42:18.342738 rootserver: 192.168.201.1 rootpath:
10799 11:42:18.345670 filename :
10800 11:42:18.415478 done.
10801 11:42:18.425634 Begin: Running /scripts/nfs-bottom ... done.
10802 11:42:18.443773 Begin: Running /scripts/init-bottom ... done.
10803 11:42:19.607516 [ 18.640706] NET: Registered PF_INET6 protocol family
10804 11:42:19.614100 [ 18.647129] Segment Routing with IPv6
10805 11:42:19.617390 [ 18.650852] In-situ OAM (IOAM) with IPv6
10806 11:42:19.740577 [ 18.757495] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10807 11:42:19.747690 [ 18.780945] systemd[1]: Detected architecture arm64.
10808 11:42:19.768559
10809 11:42:19.772215 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10810 11:42:19.772648
10811 11:42:19.789418 [ 18.822848] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10812 11:42:20.511626 [ 19.541689] systemd[1]: Queued start job for default target Graphical Interface.
10813 11:42:20.535528 [ 19.568788] systemd[1]: Created slice system-getty.slice.
10814 11:42:20.542170 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10815 11:42:20.558905 [ 19.592427] systemd[1]: Created slice system-modprobe.slice.
10816 11:42:20.565463 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10817 11:42:20.583453 [ 19.617032] systemd[1]: Created slice system-serial\x2dgetty.slice.
10818 11:42:20.593694 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10819 11:42:20.606964 [ 19.640261] systemd[1]: Created slice User and Session Slice.
10820 11:42:20.613304 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10821 11:42:20.633918 [ 19.663921] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10822 11:42:20.640279 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10823 11:42:20.657909 [ 19.687839] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10824 11:42:20.663995 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10825 11:42:20.685356 [ 19.711797] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10826 11:42:20.691532 [ 19.723504] systemd[1]: Reached target Local Encrypted Volumes.
10827 11:42:20.697892 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10828 11:42:20.710797 [ 19.744029] systemd[1]: Reached target Paths.
10829 11:42:20.714367 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10830 11:42:20.730286 [ 19.763732] systemd[1]: Reached target Remote File Systems.
10831 11:42:20.736794 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10832 11:42:20.750648 [ 19.783725] systemd[1]: Reached target Slices.
10833 11:42:20.753476 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10834 11:42:20.770299 [ 19.803736] systemd[1]: Reached target Swap.
10835 11:42:20.773477 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10836 11:42:20.790416 [ 19.824036] systemd[1]: Listening on initctl Compatibility Named Pipe.
10837 11:42:20.800631 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10838 11:42:20.807143 [ 19.839521] systemd[1]: Listening on Journal Audit Socket.
10839 11:42:20.813779 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10840 11:42:20.827280 [ 19.860869] systemd[1]: Listening on Journal Socket (/dev/log).
10841 11:42:20.833860 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10842 11:42:20.850657 [ 19.884486] systemd[1]: Listening on Journal Socket.
10843 11:42:20.857641 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10844 11:42:20.871462 [ 19.905149] systemd[1]: Listening on Network Service Netlink Socket.
10845 11:42:20.881485 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10846 11:42:20.897435 [ 19.930822] systemd[1]: Listening on udev Control Socket.
10847 11:42:20.903858 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10848 11:42:20.918593 [ 19.951985] systemd[1]: Listening on udev Kernel Socket.
10849 11:42:20.925151 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10850 11:42:20.958757 [ 19.992054] systemd[1]: Mounting Huge Pages File System...
10851 11:42:20.965176 Mounting [0;1;39mHuge Pages File System[0m...
10852 11:42:20.981304 [ 20.014524] systemd[1]: Mounting POSIX Message Queue File System...
10853 11:42:20.987504 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10854 11:42:21.004939 [ 20.038137] systemd[1]: Mounting Kernel Debug File System...
10855 11:42:21.011188 Mounting [0;1;39mKernel Debug File System[0m...
10856 11:42:21.029922 [ 20.060078] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10857 11:42:21.043960 [ 20.074229] systemd[1]: Starting Create list of static device nodes for the current kernel...
10858 11:42:21.050450 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10859 11:42:21.068352 [ 20.102499] systemd[1]: Starting Load Kernel Module configfs...
10860 11:42:21.075538 Starting [0;1;39mLoad Kernel Module configfs[0m...
10861 11:42:21.092365 [ 20.126304] systemd[1]: Starting Load Kernel Module drm...
10862 11:42:21.098857 Starting [0;1;39mLoad Kernel Module drm[0m...
10863 11:42:21.116656 [ 20.150253] systemd[1]: Starting Load Kernel Module fuse...
10864 11:42:21.123014 Starting [0;1;39mLoad Kernel Module fuse[0m...
10865 11:42:21.163151 [ 20.193464] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10866 11:42:21.170168 [ 20.203542] fuse: init (API version 7.37)
10867 11:42:21.199026 [ 20.232268] systemd[1]: Starting Journal Service...
10868 11:42:21.201953 Starting [0;1;39mJournal Service[0m...
10869 11:42:21.228418 [ 20.261984] systemd[1]: Starting Load Kernel Modules...
10870 11:42:21.234900 Starting [0;1;39mLoad Kernel Modules[0m...
10871 11:42:21.255968 [ 20.286565] systemd[1]: Starting Remount Root and Kernel File Systems...
10872 11:42:21.262205 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10873 11:42:21.277687 [ 20.311328] systemd[1]: Starting Coldplug All udev Devices...
10874 11:42:21.284126 Starting [0;1;39mColdplug All udev Devices[0m...
10875 11:42:21.300996 [ 20.334795] systemd[1]: Mounted Huge Pages File System.
10876 11:42:21.307471 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10877 11:42:21.321816 [ 20.356066] systemd[1]: Mounted POSIX Message Queue File System.
10878 11:42:21.328814 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10879 11:42:21.345954 [ 20.380116] systemd[1]: Mounted Kernel Debug File System.
10880 11:42:21.352556 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10881 11:42:21.368648 [ 20.399537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 11:42:21.378683 [ 20.409288] systemd[1]: Finished Create list of static device nodes for the current kernel.
10883 11:42:21.385155 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10884 11:42:21.402219 [ 20.432384] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 11:42:21.408677 [ 20.442052] systemd[1]: modprobe@configfs.service: Succeeded.
10886 11:42:21.415227 [ 20.448396] systemd[1]: Finished Load Kernel Module configfs.
10887 11:42:21.421501 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10888 11:42:21.439596 [ 20.472925] systemd[1]: modprobe@drm.service: Succeeded.
10889 11:42:21.449537 [ 20.476416] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 11:42:21.452893 [ 20.478789] systemd[1]: Finished Load Kernel Module drm.
10891 11:42:21.459025 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10892 11:42:21.477053 [ 20.507805] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 11:42:21.483602 [ 20.508610] systemd[1]: modprobe@fuse.service: Succeeded.
10894 11:42:21.490224 [ 20.522655] systemd[1]: Finished Load Kernel Module fuse.
10895 11:42:21.494062 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10896 11:42:21.505896 [ 20.536809] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 11:42:21.512389 [ 20.546574] systemd[1]: Finished Load Kernel Modules.
10898 11:42:21.519231 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10899 11:42:21.534837 [ 20.565389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 11:42:21.541324 [ 20.575170] systemd[1]: Finished Remount Root and Kernel File Systems.
10901 11:42:21.551252 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10902 11:42:21.563766 [ 20.594659] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 11:42:21.594564 [ 20.625158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 11:42:21.606217 [ 20.639655] systemd[1]: Mounting FUSE Control File System...
10905 11:42:21.612472 Mounting [0;1;39mFUSE Control File System[0m...
10906 11:42:21.623344 [ 20.653799] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 11:42:21.631551 [ 20.665595] systemd[1]: Mounting Kernel Configuration File System...
10908 11:42:21.637960 Mounting [0;1;39mKernel Configuration File System[0m...
10909 11:42:21.654414 [ 20.685395] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 11:42:21.670393 [ 20.700611] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10911 11:42:21.680924 [ 20.709295] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10912 11:42:21.687554 [ 20.721488] systemd[1]: Starting Load/Save Random Seed...
10913 11:42:21.693871 Starting [0;1;39mLoad/Save Random Seed[0m...
10914 11:42:21.708241 [ 20.742304] systemd[1]: Starting Apply Kernel Variables...
10915 11:42:21.714795 Starting [0;1;39mApply Kernel Variables[0m...
10916 11:42:21.737911 [ 20.771787] systemd[1]: Starting Create System Users...
10917 11:42:21.744423 Starting [0;1;39mCreate System Users[0m...
10918 11:42:21.763405 [ 20.797357] systemd[1]: Started Journal Service.
10919 11:42:21.769812 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10920 11:42:21.787971 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10921 11:42:21.811400 [ 20.835450] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10922 11:42:21.818522 [ 20.850904] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10923 11:42:21.825087 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10924 11:42:21.843628 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10925 11:42:21.863390 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10926 11:42:21.882081 See 'systemctl status systemd-udev-trigger.service' for details.
10927 11:42:21.903155 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10928 11:42:21.918941 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10929 11:42:21.966920 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10930 11:42:21.989062 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10931 11:42:22.036088 [ 21.066454] systemd-journald[304]: Received client request to flush runtime journal.
10932 11:42:22.805682 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10933 11:42:22.821915 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10934 11:42:22.837559 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10935 11:42:22.889625 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10936 11:42:23.419574 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10937 11:42:23.454787 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10938 11:42:23.530832 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10939 11:42:23.574801 Starting [0;1;39mNetwork Service[0m...
10940 11:42:23.862877 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10941 11:42:23.918669 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10942 11:42:23.942739 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10943 11:42:24.151230 [ 23.185516] remoteproc remoteproc0: powering up scp
10944 11:42:24.176647 [ 23.207787] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10945 11:42:24.183506 [ 23.217396] remoteproc remoteproc0: request_firmware failed: -2
10946 11:42:24.189752 [ 23.223313] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10947 11:42:24.316102 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10948 11:42:24.334482 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10949 11:42:24.350270 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10950 11:42:24.371284 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10951 11:42:24.389365 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10952 11:42:24.430200 Starting [0;1;39mNetwork Name Resolution[0m...
10953 11:42:24.456445 Starting [0;1;39mNetwork Time Synchronization[0m...
10954 11:42:24.472627 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10955 11:42:24.494126 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10956 11:42:24.540800 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10957 11:42:24.554482 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10958 11:42:24.756969 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10959 11:42:24.778159 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10960 11:42:24.797165 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10961 11:42:24.809560 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10962 11:42:24.825782 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10963 11:42:24.918078 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10964 11:42:24.946276 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10965 11:42:24.967277 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10966 11:42:24.993090 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10967 11:42:25.005586 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10968 11:42:25.026877 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10969 11:42:25.041566 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10970 11:42:25.061269 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10971 11:42:25.114177 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10972 11:42:25.148076 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10973 11:42:25.206483 Starting [0;1;39mUser Login Management[0m...
10974 11:42:25.222731 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10975 11:42:25.238274 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10976 11:42:25.256676 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10977 11:42:25.285872 Starting [0;1;39mPermit User Sessions[0m...
10978 11:42:25.401274 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10979 11:42:25.444860 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10980 11:42:25.475437 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10981 11:42:25.491117 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10982 11:42:25.511338 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10983 11:42:25.528020 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10984 11:42:25.550375 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10985 11:42:25.564722 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10986 11:42:25.615389 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10987 11:42:25.659445 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10988 11:42:25.776363
10989 11:42:25.776505
10990 11:42:25.779659 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10991 11:42:25.779742
10992 11:42:25.782802 debian-bullseye-arm64 login: root (automatic login)
10993 11:42:25.782983
10994 11:42:25.783056
10995 11:42:26.065880 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
10996 11:42:26.066030
10997 11:42:26.073092 The programs included with the Debian GNU/Linux system are free software;
10998 11:42:26.079093 the exact distribution terms for each program are described in the
10999 11:42:26.082857 individual files in /usr/share/doc/*/copyright.
11000 11:42:26.082938
11001 11:42:26.089352 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11002 11:42:26.092382 permitted by applicable law.
11003 11:42:26.157913 Matched prompt #10: / #
11005 11:42:26.158154 Setting prompt string to ['/ #']
11006 11:42:26.158249 end: 2.2.5.1 login-action (duration 00:00:25) [common]
11008 11:42:26.158441 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11009 11:42:26.158527 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
11010 11:42:26.158606 Setting prompt string to ['/ #']
11011 11:42:26.158667 Forcing a shell prompt, looking for ['/ #']
11013 11:42:26.208951 / #
11014 11:42:26.209093 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11015 11:42:26.209215 Waiting using forced prompt support (timeout 00:02:30)
11016 11:42:26.214014
11017 11:42:26.214348 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11018 11:42:26.214522 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11020 11:42:26.315168 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742196/extract-nfsrootfs-p6y5mcne'
11021 11:42:26.321362 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742196/extract-nfsrootfs-p6y5mcne'
11023 11:42:26.422736 / # export NFS_SERVER_IP='192.168.201.1'
11024 11:42:26.428844 export NFS_SERVER_IP='192.168.201.1'
11025 11:42:26.429649 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11026 11:42:26.430128 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11027 11:42:26.430603 end: 2 depthcharge-action (duration 00:01:39) [common]
11028 11:42:26.431057 start: 3 lava-test-retry (timeout 00:01:00) [common]
11029 11:42:26.431513 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11030 11:42:26.431889 Using namespace: common
11032 11:42:26.532701 / # #
11033 11:42:26.532902 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11034 11:42:26.537716 #
11035 11:42:26.538007 Using /lava-10742196
11037 11:42:26.638346 / # export SHELL=/bin/sh
11038 11:42:26.643336 export SHELL=/bin/sh
11040 11:42:26.744092 / # . /lava-10742196/environment
11041 11:42:26.749892 . /lava-10742196/environment
11043 11:42:26.855706 / # /lava-10742196/bin/lava-test-runner /lava-10742196/0
11044 11:42:26.856282 Test shell timeout: 10s (minimum of the action and connection timeout)
11045 11:42:26.861466 /lava-10742196/bin/lava-test-runner /lava-10742196/0
11046 11:42:27.099204 + export TESTRUN_ID=0_dmesg
11047 11:42:27.102794 + cd /lava-10742196/0/tests/0_dmesg
11048 11:42:27.106214 + cat uuid
11049 11:42:27.117008 + UUID=10742196_1.[ 26.148352] <LAVA_SIGNAL_STARTRUN 0_dmesg 10742196_1.6.2.3.1>
11050 11:42:27.117093 6.2.3.1
11051 11:42:27.117159 + set +x
11052 11:42:27.117399 Received signal: <STARTRUN> 0_dmesg 10742196_1.6.2.3.1
11053 11:42:27.117470 Starting test lava.0_dmesg (10742196_1.6.2.3.1)
11054 11:42:27.117554 Skipping test definition patterns.
11055 11:42:27.123395 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11056 11:42:27.224861 [ 26.256521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11057 11:42:27.225199 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11059 11:42:27.305686 [ 26.337233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11060 11:42:27.306024 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11062 11:42:27.387481 [ 26.418697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11063 11:42:27.387632 + set +x
11064 11:42:27.387928 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11066 11:42:27.394033 [ 26.427800] <LAVA_SIGNAL_ENDRUN 0_dmesg 10742196_1.6.2.3.1>
11067 11:42:27.394305 Received signal: <ENDRUN> 0_dmesg 10742196_1.6.2.3.1
11068 11:42:27.394401 Ending use of test pattern.
11069 11:42:27.394475 Ending test lava.0_dmesg (10742196_1.6.2.3.1), duration 0.28
11071 11:42:27.399963 <LAVA_TEST_RUNNER EXIT>
11072 11:42:27.400218 ok: lava_test_shell seems to have completed
11073 11:42:27.400341 alert: pass
crit: pass
emerg: pass
11074 11:42:27.400443 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11075 11:42:27.400541 end: 3 lava-test-retry (duration 00:00:01) [common]
11076 11:42:27.400638 start: 4 lava-test-retry (timeout 00:01:00) [common]
11077 11:42:27.400733 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11078 11:42:27.400830 Using namespace: common
11080 11:42:27.501312 / # #
11081 11:42:27.501761 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11082 11:42:27.502131 Using /lava-10742196
11084 11:42:27.602792 export SHELL=/bin/sh
11085 11:42:27.603026 #
11087 11:42:27.703545 / # export SHELL=/bin/sh. /lava-10742196/environment
11088 11:42:27.703770
11090 11:42:27.804368 / # . /lava-10742196/environment/lava-10742196/bin/lava-test-runner /lava-10742196/1
11091 11:42:27.804535 Test shell timeout: 10s (minimum of the action and connection timeout)
11092 11:42:27.804685
11093 11:42:27.809524 / # /lava-10742196/bin/lava-test-runner /lava-10742196/1
11094 11:42:27.937207 + export TESTRUN_ID=1_bootrr
11095 11:42:27.940970 + cd /lava-10742196/1/tests/1_bootrr
11096 11:42:27.943668 + cat uuid
11097 11:42:27.956980 + UUID=10742196_1.[ 26.988563] <LAVA_SIGNAL_STARTRUN 1_bootrr 10742196_1.6.2.3.5>
11098 11:42:27.957084 6.2.3.5
11099 11:42:27.957173 + set +x
11100 11:42:27.957429 Received signal: <STARTRUN> 1_bootrr 10742196_1.6.2.3.5
11101 11:42:27.957533 Starting test lava.1_bootrr (10742196_1.6.2.3.5)
11102 11:42:27.957659 Skipping test definition patterns.
11103 11:42:27.970215 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10742196/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11104 11:42:27.973654 + cd /opt/bootrr/libexec/bootrr
11105 11:42:27.973765 + sh helpers/bootrr-auto
11106 11:42:28.044047 /lava-10742196/1/../bin/lava-test-case
11107 11:42:28.078961 [ 27.110702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11108 11:42:28.079295 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11110 11:42:28.129154 /lava-10742196/1/../bin/lava-test-case
11111 11:42:28.158401 [ 27.190101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11112 11:42:28.158709 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11114 11:42:28.184006 /lava-10742196/1/../bin/lava-test-case
11115 11:42:28.215237 [ 27.246786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11116 11:42:28.215539 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11118 11:42:28.277840 /lava-10742196/1/../bin/lava-test-case
11119 11:42:28.308712 [ 27.340502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11120 11:42:28.309030 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11122 11:42:28.347479 /lava-10742196/1/../bin/lava-test-case
11123 11:42:28.381447 [ 27.412722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11124 11:42:28.382158 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11126 11:42:28.422526 /lava-10742196/1/../bin/lava-test-case
11127 11:42:28.457625 [ 27.489216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11128 11:42:28.457901 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11130 11:42:28.501664 /lava-10742196/1/../bin/lava-test-case
11131 11:42:28.538667 [ 27.569674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11132 11:42:28.539400 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11134 11:42:28.577974 /lava-10742196/1/../bin/lava-test-case
11135 11:42:28.605316 [ 27.637107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11136 11:42:28.605627 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11138 11:42:28.638511 /lava-10742196/1/../bin/lava-test-case
11139 11:42:28.668907 [ 27.700271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11140 11:42:28.669179 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11142 11:42:28.706239 /lava-10742196/1/../bin/lava-test-case
11143 11:42:28.735352 [ 27.767016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11144 11:42:28.735639 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11146 11:42:28.761229 /lava-10742196/1/../bin/lava-test-case
11147 11:42:28.798867 [ 27.830325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11148 11:42:28.799171 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11150 11:42:28.838724 /lava-10742196/1/../bin/lava-test-case
11151 11:42:28.873161 [ 27.904593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11152 11:42:28.873489 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11154 11:42:28.916412 /lava-10742196/1/../bin/lava-test-case
11155 11:42:28.950506 [ 27.982319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11156 11:42:28.950805 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11158 11:42:28.996444 /lava-10742196/1/../bin/lava-test-case
11159 11:42:29.026737 [ 28.058585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11160 11:42:29.027041 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11162 11:42:29.071376 /lava-10742196/1/../bin/lava-test-case
11163 11:42:29.106948 [ 28.138383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11164 11:42:29.107270 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11166 11:42:29.130641 /lava-10742196/1/../bin/lava-test-case
11167 11:42:29.162459 [ 28.194092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11168 11:42:29.162748 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11170 11:42:29.205361 /lava-10742196/1/../bin/lava-test-case
11171 11:42:29.240604 [ 28.272378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11172 11:42:29.240910 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11174 11:42:29.264677 /lava-10742196/1/../bin/lava-test-case
11175 11:42:29.294325 [ 28.325955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11176 11:42:29.294607 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11178 11:42:29.340963 /lava-10742196/1/../bin/lava-test-case
11179 11:42:29.375829 [ 28.407196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11180 11:42:29.376126 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11182 11:42:29.400211 /lava-10742196/1/../bin/lava-test-case
11183 11:42:29.431493 [ 28.463295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11184 11:42:29.431766 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11186 11:42:29.471294 /lava-10742196/1/../bin/lava-test-case
11187 11:42:29.502973 [ 28.534598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11188 11:42:29.503273 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11190 11:42:29.526365 /lava-10742196/1/../bin/lava-test-case
11191 11:42:29.556567 [ 28.588411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11192 11:42:29.556870 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11194 11:42:29.597676 /lava-10742196/1/../bin/lava-test-case
11195 11:42:29.633983 [ 28.665576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11196 11:42:29.634368 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11198 11:42:29.673077 /lava-10742196/1/../bin/lava-test-case
11199 11:42:29.705737 [ 28.737251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11200 11:42:29.706038 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11202 11:42:29.747316 /lava-10742196/1/../bin/lava-test-case
11203 11:42:29.787679 [ 28.819356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11204 11:42:29.788003 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11206 11:42:29.821899 /lava-10742196/1/../bin/lava-test-case
11207 11:42:29.854153 [ 28.885677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11208 11:42:29.854460 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11210 11:42:29.875323 /lava-10742196/1/../bin/lava-test-case
11211 11:42:29.899767 [ 28.931439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11212 11:42:29.900098 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11214 11:42:29.933500 /lava-10742196/1/../bin/lava-test-case
11215 11:42:29.960494 [ 28.992204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11216 11:42:29.960789 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11218 11:42:29.989353 /lava-10742196/1/../bin/lava-test-case
11219 11:42:30.013988 [ 29.045692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11220 11:42:30.014292 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11222 11:42:30.050124 /lava-10742196/1/../bin/lava-test-case
11223 11:42:30.076692 [ 29.108145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11224 11:42:30.076979 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11226 11:42:30.109227 /lava-10742196/1/../bin/lava-test-case
11227 11:42:30.136035 [ 29.167855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11228 11:42:30.136304 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11230 11:42:30.170139 /lava-10742196/1/../bin/lava-test-case
11231 11:42:30.197690 [ 29.229352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11232 11:42:30.197969 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11234 11:42:30.233054 /lava-10742196/1/../bin/lava-test-case
11235 11:42:30.259125 [ 29.291071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11236 11:42:30.259376 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11238 11:42:30.288709 /lava-10742196/1/../bin/lava-test-case
11239 11:42:30.315898 [ 29.347373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11240 11:42:30.316172 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11242 11:42:30.354211 /lava-10742196/1/../bin/lava-test-case
11243 11:42:30.387513 [ 29.419240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11244 11:42:30.387785 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11246 11:42:30.420840 /lava-10742196/1/../bin/lava-test-case
11247 11:42:30.448694 [ 29.480270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11248 11:42:30.448957 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11250 11:42:30.473977 /lava-10742196/1/../bin/lava-test-case
11251 11:42:30.506357 [ 29.537561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11252 11:42:30.506627 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11254 11:42:30.541822 /lava-10742196/1/../bin/lava-test-case
11255 11:42:30.571384 [ 29.603174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11256 11:42:30.571684 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11258 11:42:30.604337 /lava-10742196/1/../bin/lava-test-case
11259 11:42:30.635336 [ 29.667287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11260 11:42:30.635656 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11262 11:42:30.668361 /lava-10742196/1/../bin/lava-test-case
11263 11:42:30.695278 [ 29.726972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11264 11:42:30.695613 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11266 11:42:30.716414 /lava-10742196/1/../bin/lava-test-case
11267 11:42:30.745790 [ 29.777811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11268 11:42:30.746058 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11270 11:42:30.778161 /lava-10742196/1/../bin/lava-test-case
11271 11:42:30.803522 [ 29.835565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11272 11:42:30.803796 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11274 11:42:30.824965 /lava-10742196/1/../bin/lava-test-case
11275 11:42:30.855770 [ 29.887444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11276 11:42:30.856064 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11278 11:42:30.887706 /lava-10742196/1/../bin/lava-test-case
11279 11:42:30.916215 [ 29.947951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11280 11:42:30.916477 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11282 11:42:30.944984 /lava-10742196/1/../bin/lava-test-case
11283 11:42:30.976039 [ 30.007884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11284 11:42:30.976311 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11286 11:42:31.009531 /lava-10742196/1/../bin/lava-test-case
11287 11:42:31.035233 [ 30.067200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11288 11:42:31.035494 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11290 11:42:31.059079 /lava-10742196/1/../bin/lava-test-case
11291 11:42:31.089169 [ 30.120832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11292 11:42:31.089446 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11294 11:42:31.121176 /lava-10742196/1/../bin/lava-test-case
11295 11:42:31.147173 [ 30.179016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11296 11:42:31.147432 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11298 11:42:31.170692 /lava-10742196/1/../bin/lava-test-case
11299 11:42:31.203851 [ 30.235437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11300 11:42:31.204126 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11302 11:42:31.240522 /lava-10742196/1/../bin/lava-test-case
11303 11:42:31.271160 [ 30.302463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11304 11:42:31.271865 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11306 11:42:31.321552 /lava-10742196/1/../bin/lava-test-case
11307 11:42:31.353048 [ 30.384749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11308 11:42:31.353726 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11310 11:42:32.386047 /lava-10742196/1/../bin/lava-test-case
11311 11:42:32.415809 [ 31.448120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11312 11:42:32.416088 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11314 11:42:33.435771 /lava-10742196/1/../bin/lava-test-case
11315 11:42:33.523553 [ 32.555382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11316 11:42:33.523875 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11317 11:42:33.523996 Bad test result: blocked
11318 11:42:33.544190 /lava-10742196/1/../bin/lava-test-case
11319 11:42:33.743125 [ 32.775138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11320 11:42:33.743470 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11322 11:42:33.778516 /lava-10742196/1/../bin/lava-test-case
11323 11:42:34.005038 [ 33.037191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11324 11:42:34.005414 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11326 11:42:34.042133 /lava-10742196/1/../bin/lava-test-case
11327 11:42:34.278429 [ 33.310693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11328 11:42:34.278754 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11330 11:42:34.310429 /lava-10742196/1/../bin/lava-test-case
11331 11:42:34.351716 [ 33.383696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11332 11:42:34.352128 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11334 11:42:34.384825 /lava-10742196/1/../bin/lava-test-case
11335 11:42:34.475838 [ 33.507941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11336 11:42:34.476196 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11338 11:42:34.513582 /lava-10742196/1/../bin/lava-test-case
11339 11:42:34.604491 [ 33.636973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11340 11:42:34.604864 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11342 11:42:34.634554 /lava-10742196/1/../bin/lava-test-case
11343 11:42:34.664632 [ 33.697104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11344 11:42:34.664954 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11346 11:42:34.705342 /lava-10742196/1/../bin/lava-test-case
11347 11:42:34.738938 [ 33.771565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11348 11:42:34.739270 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11350 11:42:34.777970 /lava-10742196/1/../bin/lava-test-case
11351 11:42:34.868829 [ 33.901337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11352 11:42:34.869190 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11354 11:42:34.897712 /lava-10742196/1/../bin/lava-test-case
11355 11:42:34.926763 [ 33.959311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11356 11:42:34.927088 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11358 11:42:34.966609 /lava-10742196/1/../bin/lava-test-case
11359 11:42:34.994518 [ 34.026666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11360 11:42:34.994837 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11362 11:42:35.018909 /lava-10742196/1/../bin/lava-test-case
11363 11:42:35.609419 [ 34.641475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11364 11:42:35.610237 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11366 11:42:35.646299 /lava-10742196/1/../bin/lava-test-case
11367 11:42:36.114634 [ 35.146809] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11368 11:42:36.115016 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11370 11:42:36.139083 /lava-10742196/1/../bin/lava-test-case
11371 11:42:36.284320 [ 35.317173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11372 11:42:36.284654 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11374 11:42:36.324127 /lava-10742196/1/../bin/lava-test-case
11375 11:42:36.355693 [ 35.388242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11376 11:42:36.355998 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11378 11:42:36.395564 /lava-10742196/1/../bin/lava-test-case
11379 11:42:36.894934 [ 35.926977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11380 11:42:36.895778 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11382 11:42:36.940360 /lava-10742196/1/../bin/lava-test-case
11383 11:42:37.505856 [ 36.538149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11384 11:42:37.506664 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11386 11:42:37.545927 /lava-10742196/1/../bin/lava-test-case
11387 11:42:37.574767 [ 36.607036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11388 11:42:37.575056 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11390 11:42:37.611986 /lava-10742196/1/../bin/lava-test-case
11391 11:42:37.643825 [ 36.676484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11392 11:42:37.644103 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11394 11:42:37.678501 /lava-10742196/1/../bin/lava-test-case
11395 11:42:37.707001 [ 36.739232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11396 11:42:37.707536 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11398 11:42:37.746876 /lava-10742196/1/../bin/lava-test-case
11399 11:42:37.774163 [ 36.807211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11400 11:42:37.774423 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11402 11:42:37.816075 /lava-10742196/1/../bin/lava-test-case
11403 11:42:37.843477 [ 36.875737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11404 11:42:37.843751 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11406 11:42:37.885487 /lava-10742196/1/../bin/lava-test-case
11407 11:42:37.923667 [ 36.955902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11408 11:42:37.924415 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11410 11:42:37.965794 /lava-10742196/1/../bin/lava-test-case
11411 11:42:37.998031 [ 37.030430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11412 11:42:37.998943 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11414 11:42:38.042201 /lava-10742196/1/../bin/lava-test-case
11415 11:42:38.076906 [ 37.108785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11416 11:42:38.077700 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11418 11:42:38.120651 /lava-10742196/1/../bin/lava-test-case
11419 11:42:38.150776 [ 37.183343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11420 11:42:38.151090 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11422 11:42:38.195898 /lava-10742196/1/../bin/lava-test-case
11423 11:42:38.229667 [ 37.261909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11424 11:42:38.230082 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11426 11:42:38.270490 /lava-10742196/1/../bin/lava-test-case
11427 11:42:38.301720 [ 37.334095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11428 11:42:38.302056 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11430 11:42:38.342464 /lava-10742196/1/../bin/lava-test-case
11431 11:42:38.373431 [ 37.406230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11432 11:42:38.373733 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11434 11:42:38.396919 /lava-10742196/1/../bin/lava-test-case
11435 11:42:38.425726 [ 37.458309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11436 11:42:38.426008 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11438 11:42:38.464958 /lava-10742196/1/../bin/lava-test-case
11439 11:42:38.501449 [ 37.533975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11440 11:42:38.502204 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11442 11:42:38.535079 /lava-10742196/1/../bin/lava-test-case
11443 11:42:38.571404 [ 37.604005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11444 11:42:38.572114 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11446 11:42:38.611734 /lava-10742196/1/../bin/lava-test-case
11447 11:42:38.643558 [ 37.676193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11448 11:42:38.644329 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11450 11:42:38.670349 /lava-10742196/1/../bin/lava-test-case
11451 11:42:38.700353 [ 37.732896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11452 11:42:38.700672 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11454 11:42:38.733102 /lava-10742196/1/../bin/lava-test-case
11455 11:42:38.760094 [ 37.792796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11456 11:42:38.760369 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11458 11:42:38.784340 /lava-10742196/1/../bin/lava-test-case
11459 11:42:38.813925 [ 37.846769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11460 11:42:38.814211 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11462 11:42:38.846419 /lava-10742196/1/../bin/lava-test-case
11463 11:42:38.873104 [ 37.905660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11464 11:42:38.873414 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11466 11:42:38.900046 /lava-10742196/1/../bin/lava-test-case
11467 11:42:38.924665 [ 37.957611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11468 11:42:38.924946 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11470 11:42:38.957089 /lava-10742196/1/../bin/lava-test-case
11471 11:42:38.982649 [ 38.015358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11472 11:42:38.982917 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11474 11:42:39.002432 /lava-10742196/1/../bin/lava-test-case
11475 11:42:39.029220 [ 38.061744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11476 11:42:39.029566 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11478 11:42:39.062667 /lava-10742196/1/../bin/lava-test-case
11479 11:42:39.092060 [ 38.124483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11480 11:42:39.092414 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11482 11:42:39.126745 /lava-10742196/1/../bin/lava-test-case
11483 11:42:39.152293 [ 38.185073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11484 11:42:39.152573 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11486 11:42:39.174874 /lava-10742196/1/../bin/lava-test-case
11487 11:42:39.205016 [ 38.237386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11488 11:42:39.205374 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11490 11:42:39.249170 /lava-10742196/1/../bin/lava-test-case
11491 11:42:39.281282 [ 38.313792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11492 11:42:39.281668 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11494 11:42:39.309223 /lava-10742196/1/../bin/lava-test-case
11495 11:42:39.338514 [ 38.371106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11496 11:42:39.338870 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11498 11:42:39.374523 /lava-10742196/1/../bin/lava-test-case
11499 11:42:39.410149 [ 38.442750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11500 11:42:39.410846 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11502 11:42:39.438138 /lava-10742196/1/../bin/lava-test-case
11503 11:42:39.476541 [ 38.508545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11504 11:42:39.477263 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11506 11:42:40.527055 /lava-10742196/1/../bin/lava-test-case
11507 11:42:40.575744 [ 39.608191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11508 11:42:40.576477 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11510 11:42:40.604863 /lava-10742196/1/../bin/lava-test-case
11511 11:42:40.644014 [ 39.676308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11512 11:42:40.644712 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11514 11:42:41.691914 /lava-10742196/1/../bin/lava-test-case
11515 11:42:41.727948 [ 40.760598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11516 11:42:41.728632 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11518 11:42:41.755939 /lava-10742196/1/../bin/lava-test-case
11519 11:42:41.793723 [ 40.826309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11520 11:42:41.794416 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11522 11:42:42.849401 /lava-10742196/1/../bin/lava-test-case
11523 11:42:42.888076 [ 41.920801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11524 11:42:42.889008 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11526 11:42:42.919174 /lava-10742196/1/../bin/lava-test-case
11527 11:42:42.954202 [ 41.987077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11528 11:42:42.954958 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11530 11:42:44.010381 /lava-10742196/1/../bin/lava-test-case
11531 11:42:44.052513 [ 43.085446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11532 11:42:44.053278 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11534 11:42:44.084410 /lava-10742196/1/../bin/lava-test-case
11535 11:42:44.121678 [ 43.154271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11536 11:42:44.122469 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11538 11:42:45.175226 /lava-10742196/1/../bin/lava-test-case
11539 11:42:45.217484 [ 44.250371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11540 11:42:45.218300 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11542 11:42:45.243149 /lava-10742196/1/../bin/lava-test-case
11543 11:42:45.278350 [ 44.311284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11544 11:42:45.279044 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11546 11:42:46.332251 /lava-10742196/1/../bin/lava-test-case
11547 11:42:46.377446 [ 45.410424] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11548 11:42:46.378371 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11550 11:42:46.405795 /lava-10742196/1/../bin/lava-test-case
11551 11:42:46.440457 [ 45.473900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11552 11:42:46.441160 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11554 11:42:46.767661 [ 45.807046] vpu: disabling
11555 11:42:46.770313 [ 45.809868] vproc2: disabling
11556 11:42:46.773588 [ 45.812877] vproc1: disabling
11557 11:42:46.776925 [ 45.815875] vaud18: disabling
11558 11:42:46.780372 [ 45.819015] vsram_others: disabling
11559 11:42:46.783824 [ 45.822623] va09: disabling
11560 11:42:46.787216 [ 45.825459] vsram_md: disabling
11561 11:42:46.790236 [ 45.828695] Vgpu: disabling
11562 11:42:47.499234 /lava-10742196/1/../bin/lava-test-case
11563 11:42:47.532339 [ 46.566228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11564 11:42:47.532621 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11566 11:42:47.554684 /lava-10742196/1/../bin/lava-test-case
11567 11:42:47.578867 [ 46.612863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11568 11:42:47.579192 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11570 11:42:47.600866 /lava-10742196/1/../bin/lava-test-case
11571 11:42:47.631534 [ 46.665094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11572 11:42:47.631836 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11574 11:42:48.694333 /lava-10742196/1/../bin/lava-test-case
11575 11:42:48.720779 [ 47.754953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11576 11:42:48.721093 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11578 11:42:48.748700 /lava-10742196/1/../bin/lava-test-case
11579 11:42:48.779312 [ 47.812914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11580 11:42:48.780112 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11582 11:42:48.812749 /lava-10742196/1/../bin/lava-test-case
11583 11:42:48.838905 [ 47.872714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11584 11:42:48.839182 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11586 11:42:48.864561 /lava-10742196/1/../bin/lava-test-case
11587 11:42:48.904155 [ 47.937550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11588 11:42:48.904917 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11590 11:42:48.946951 /lava-10742196/1/../bin/lava-test-case
11591 11:42:48.978503 [ 48.012323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11592 11:42:48.979580 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11594 11:42:49.029269 /lava-10742196/1/../bin/lava-test-case
11595 11:42:49.069926 [ 48.103327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11596 11:42:49.070663 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11598 11:42:49.110135 /lava-10742196/1/../bin/lava-test-case
11599 11:42:49.140399 [ 48.173988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11600 11:42:49.141194 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11602 11:42:49.167889 /lava-10742196/1/../bin/lava-test-case
11603 11:42:49.203298 [ 48.236958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11604 11:42:49.204157 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11606 11:42:49.252699 /lava-10742196/1/../bin/lava-test-case
11607 11:42:49.288675 [ 48.322552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11608 11:42:49.289521 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11610 11:42:49.327994 /lava-10742196/1/../bin/lava-test-case
11611 11:42:49.363957 [ 48.397381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11612 11:42:49.364766 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11614 11:42:49.399538 /lava-10742196/1/../bin/lava-test-case
11615 11:42:49.436469 [ 48.469987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11616 11:42:49.437156 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11618 11:42:49.478450 /lava-10742196/1/../bin/lava-test-case
11619 11:42:49.511435 [ 48.545371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11620 11:42:49.512216 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11622 11:42:49.536865 /lava-10742196/1/../bin/lava-test-case
11623 11:42:49.568825 [ 48.603114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11624 11:42:49.569113 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11626 11:42:49.603237 /lava-10742196/1/../bin/lava-test-case
11627 11:42:49.630870 [ 48.665017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11628 11:42:49.631138 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11630 11:42:49.653275 /lava-10742196/1/../bin/lava-test-case
11631 11:42:49.684970 [ 48.719060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11632 11:42:49.685247 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11634 11:42:49.724724 /lava-10742196/1/../bin/lava-test-case
11635 11:42:49.757221 [ 48.790972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11636 11:42:49.758070 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11638 11:42:49.791870 /lava-10742196/1/../bin/lava-test-case
11639 11:42:49.822433 [ 48.856288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11640 11:42:49.823127 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11642 11:42:49.861505 /lava-10742196/1/../bin/lava-test-case
11643 11:42:49.893269 [ 48.927423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11644 11:42:49.893749 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11646 11:42:49.919242 /lava-10742196/1/../bin/lava-test-case
11647 11:42:49.948630 [ 48.982701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11648 11:42:49.948954 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11650 11:42:49.984276 /lava-10742196/1/../bin/lava-test-case
11651 11:42:50.011743 [ 49.045431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11652 11:42:50.012071 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11654 11:42:50.034732 /lava-10742196/1/../bin/lava-test-case
11655 11:42:50.063805 [ 49.097518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11656 11:42:50.064157 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11658 11:42:51.109492 /lava-10742196/1/../bin/lava-test-case
11659 11:42:51.142823 [ 50.177216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11660 11:42:51.143223 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11662 11:42:52.194465 /lava-10742196/1/../bin/lava-test-case
11663 11:42:52.228581 [ 51.263097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11664 11:42:52.228972 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11666 11:42:52.252347 /lava-10742196/1/../bin/lava-test-case
11667 11:42:52.283799 [ 51.317994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11668 11:42:52.284193 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11670 11:42:52.316933 /lava-10742196/1/../bin/lava-test-case
11671 11:42:52.342878 [ 51.377221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11672 11:42:52.343226 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11674 11:42:52.364830 /lava-10742196/1/../bin/lava-test-case
11675 11:42:52.390399 [ 51.424818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11676 11:42:52.390784 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11678 11:42:52.427346 /lava-10742196/1/../bin/lava-test-case
11679 11:42:52.457794 [ 51.492049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11680 11:42:52.458170 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11682 11:42:52.480302 /lava-10742196/1/../bin/lava-test-case
11683 11:42:52.505789 [ 51.540018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11684 11:42:52.506191 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11686 11:42:52.544275 /lava-10742196/1/../bin/lava-test-case
11687 11:42:52.566308 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11689 11:42:52.569669 [ 51.603769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11690 11:42:52.591336 /lava-10742196/1/../bin/lava-test-case
11691 11:42:52.618494 [ 51.652759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11692 11:42:52.618928 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11694 11:42:52.648825 /lava-10742196/1/../bin/lava-test-case
11695 11:42:52.674280 [ 51.708579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11696 11:42:52.674714 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11698 11:42:52.695933 /lava-10742196/1/../bin/lava-test-case
11699 11:42:53.519515 [ 52.547421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11700 11:42:53.519892 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11702 11:42:53.550393 /lava-10742196/1/../bin/lava-test-case
11703 11:42:54.491111 [ 53.525639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11704 11:42:54.491512 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11706 11:42:54.520380 /lava-10742196/1/../bin/lava-test-case
11707 11:42:55.110924 [ 54.145311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11708 11:42:55.111319 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11710 11:42:55.146003 /lava-10742196/1/../bin/lava-test-case
11711 11:42:56.298546 [ 55.050865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11712 11:42:56.299200 /lava-10742196/1/../bin/lava-test-case
11713 11:42:56.299937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11715 11:42:56.315437 [ 55.350204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11716 11:42:56.316541 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11718 11:42:56.359285 /lava-10742196/1/../bin/lava-test-case
11719 11:42:56.389614 [ 55.424224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11720 11:42:56.390422 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11722 11:42:56.413040 /lava-10742196/1/../bin/lava-test-case
11723 11:42:56.443293 [ 55.478336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11724 11:42:56.443753 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11726 11:42:56.480041 /lava-10742196/1/../bin/lava-test-case
11727 11:42:57.303601 [ 56.332081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11728 11:42:57.304050 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11730 11:42:57.323700 /lava-10742196/1/../bin/lava-test-case
11731 11:42:57.352178 [ 56.387410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11732 11:42:57.352526 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11734 11:42:57.388172 /lava-10742196/1/../bin/lava-test-case
11735 11:42:58.221412 [ 57.232991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11736 11:42:58.221830 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11738 11:42:58.247281 /lava-10742196/1/../bin/lava-test-case
11739 11:42:58.844533 [ 57.880004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11740 11:42:58.844916 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11742 11:42:58.889886 /lava-10742196/1/../bin/lava-test-case
11743 11:42:59.336110 [ 58.371590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11744 11:42:59.336516 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11746 11:43:00.377755 /lava-10742196/1/../bin/lava-test-case
11747 11:43:00.958445 [ 59.994090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11748 11:43:00.958805 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11750 11:43:01.998042 /lava-10742196/1/../bin/lava-test-case
11751 11:43:02.458506 [ 61.494082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11752 11:43:02.458937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11753 11:43:02.459078 Bad test result: blocked
11754 11:43:02.484292 /lava-10742196/1/../bin/lava-test-case
11755 11:43:02.942829 [ 61.978189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11756 11:43:02.943183 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11758 11:43:03.991109 /lava-10742196/1/../bin/lava-test-case
11759 11:43:04.995803 [ 64.031774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11760 11:43:04.996142 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11762 11:43:05.025312 /lava-10742196/1/../bin/lava-test-case
11763 11:43:05.854109 [ 64.889916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11764 11:43:05.854540 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11766 11:43:05.890594 /lava-10742196/1/../bin/lava-test-case
11767 11:43:06.719886 [ 65.755656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11768 11:43:06.720251 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11770 11:43:06.757106 /lava-10742196/1/../bin/lava-test-case
11771 11:43:08.725741 [ 67.762171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11772 11:43:08.726121 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11774 11:43:08.748271 /lava-10742196/1/../bin/lava-test-case
11775 11:43:08.805462 [ 67.841577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11776 11:43:08.805863 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11778 11:43:08.839854 /lava-10742196/1/../bin/lava-test-case
11779 11:43:08.882611 [ 67.918943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11780 11:43:08.882943 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11782 11:43:08.907898 /lava-10742196/1/../bin/lava-test-case
11783 11:43:08.954594 [ 67.990998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11784 11:43:08.955071 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11786 11:43:10.010923 /lava-10742196/1/../bin/lava-test-case
11787 11:43:12.194939 [ 71.232002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11788 11:43:12.195354 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11790 11:43:12.223031 /lava-10742196/1/../bin/lava-test-case
11791 11:43:13.009162 [ 72.046151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11792 11:43:13.009486 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11794 11:43:14.053488 /lava-10742196/1/../bin/lava-test-case
11795 11:43:14.085122 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11797 11:43:14.088162 [ 73.125205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11798 11:43:14.112704 /lava-10742196/1/../bin/lava-test-case
11799 11:43:14.149283 [ 73.185991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11800 11:43:14.149619 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11802 11:43:15.504627 /lava-10742196/1/../bin/lava-test-case
11803 11:43:15.686071 [ 74.723298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11804 11:43:15.686417 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11806 11:43:15.709117 /lava-10742196/1/../bin/lava-test-case
11807 11:43:15.741030 [ 74.778213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11808 11:43:15.741386 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11810 11:43:16.789173 /lava-10742196/1/../bin/lava-test-case
11811 11:43:17.159817 [ 76.197228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11812 11:43:17.160260 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11814 11:43:17.187779 /lava-10742196/1/../bin/lava-test-case
11815 11:43:17.415656 [ 76.452881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11816 11:43:17.416019 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11818 11:43:17.455742 /lava-10742196/1/../bin/lava-test-case
11819 11:43:17.554061 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11821 11:43:17.557160 [ 76.594625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11822 11:43:17.595533 /lava-10742196/1/../bin/lava-test-case
11823 11:43:18.012714 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11825 11:43:18.016190 [ 77.053196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11826 11:43:18.040431 /lava-10742196/1/../bin/lava-test-case
11827 11:43:18.363689 [ 77.401142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11828 11:43:18.364068 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11830 11:43:18.405319 /lava-10742196/1/../bin/lava-test-case
11831 11:43:18.488177 [ 77.525453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11832 11:43:18.488517 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11834 11:43:18.511141 /lava-10742196/1/../bin/lava-test-case
11835 11:43:18.680795 [ 77.718248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11836 11:43:18.681181 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11838 11:43:18.724484 /lava-10742196/1/../bin/lava-test-case
11839 11:43:18.908873 [ 77.946581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11840 11:43:18.909287 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11842 11:43:18.932053 /lava-10742196/1/../bin/lava-test-case
11843 11:43:20.030597 [ 79.068137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11844 11:43:20.031048 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11846 11:43:21.077212 /lava-10742196/1/../bin/lava-test-case
11847 11:43:21.392956 [ 80.430598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11848 11:43:21.393312 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11850 11:43:21.401717 + [ 80.442847] <LAVA_SIGNAL_ENDRUN 1_bootrr 10742196_1.6.2.3.5>
11851 11:43:21.401851 set +x
11852 11:43:21.402118 Received signal: <ENDRUN> 1_bootrr 10742196_1.6.2.3.5
11853 11:43:21.402215 Ending use of test pattern.
11854 11:43:21.402279 Ending test lava.1_bootrr (10742196_1.6.2.3.5), duration 53.44
11856 11:43:22.171950 <LAVA_TEST_RUNNER EXIT>
11857 11:43:22.172720 ok: lava_test_shell seems to have completed
11858 11:43:22.177717 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11859 11:43:22.178439 end: 4.1 lava-test-shell (duration 00:00:55) [common]
11860 11:43:22.178914 end: 4 lava-test-retry (duration 00:00:55) [common]
11861 11:43:22.179593 start: 5 finalize (timeout 00:06:57) [common]
11862 11:43:22.180073 start: 5.1 power-off (timeout 00:00:30) [common]
11863 11:43:22.180829 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11864 11:43:22.350491 >> Command sent successfully.
11865 11:43:22.360670 Returned 0 in 0 seconds
11866 11:43:22.461887 end: 5.1 power-off (duration 00:00:00) [common]
11868 11:43:22.462773 start: 5.2 read-feedback (timeout 00:06:57) [common]
11869 11:43:22.463430 Listened to connection for namespace 'common' for up to 1s
11870 11:43:23.463449 Finalising connection for namespace 'common'
11871 11:43:23.463634 Disconnecting from shell: Finalise
11872 11:43:23.463716 / #
11873 11:43:23.564049 end: 5.2 read-feedback (duration 00:00:01) [common]
11874 11:43:23.564274 end: 5 finalize (duration 00:00:01) [common]
11875 11:43:23.564461 Cleaning after the job
11876 11:43:23.564625 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/ramdisk
11877 11:43:23.567003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/kernel
11878 11:43:23.578161 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/dtb
11879 11:43:23.578441 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/nfsrootfs
11880 11:43:23.637343 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742196/tftp-deploy-dr7wgtj6/modules
11881 11:43:23.642646 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742196
11882 11:43:23.946882 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742196
11883 11:43:23.947104 Job finished correctly