Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 20
- Errors: 0
1 11:46:19.556967 lava-dispatcher, installed at version: 2023.05.1
2 11:46:19.557224 start: 0 validate
3 11:46:19.557381 Start time: 2023-06-15 11:46:19.557374+00:00 (UTC)
4 11:46:19.557507 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:46:19.557634 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 11:46:19.821838 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:46:19.822026 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:46:20.078902 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:46:20.079087 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:46:20.355255 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:46:20.355441 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:46:20.623927 validate duration: 1.07
14 11:46:20.624198 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:46:20.624303 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:46:20.624397 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:46:20.624524 Not decompressing ramdisk as can be used compressed.
18 11:46:20.624611 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230609.0/arm64/rootfs.cpio.gz
19 11:46:20.624677 saving as /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/ramdisk/rootfs.cpio.gz
20 11:46:20.624739 total size: 34417816 (32MB)
21 11:46:20.625804 progress 0% (0MB)
22 11:46:20.634560 progress 5% (1MB)
23 11:46:20.643364 progress 10% (3MB)
24 11:46:20.651982 progress 15% (4MB)
25 11:46:20.660950 progress 20% (6MB)
26 11:46:20.669734 progress 25% (8MB)
27 11:46:20.678624 progress 30% (9MB)
28 11:46:20.687523 progress 35% (11MB)
29 11:46:20.696796 progress 40% (13MB)
30 11:46:20.705958 progress 45% (14MB)
31 11:46:20.714954 progress 50% (16MB)
32 11:46:20.723841 progress 55% (18MB)
33 11:46:20.733042 progress 60% (19MB)
34 11:46:20.742011 progress 65% (21MB)
35 11:46:20.751234 progress 70% (23MB)
36 11:46:20.760716 progress 75% (24MB)
37 11:46:20.770041 progress 80% (26MB)
38 11:46:20.779136 progress 85% (27MB)
39 11:46:20.788243 progress 90% (29MB)
40 11:46:20.797076 progress 95% (31MB)
41 11:46:20.805835 progress 100% (32MB)
42 11:46:20.806005 32MB downloaded in 0.18s (181.08MB/s)
43 11:46:20.806165 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:46:20.806410 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:46:20.806501 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:46:20.806588 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:46:20.806722 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:46:20.806797 saving as /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/kernel/Image
50 11:46:20.806861 total size: 47581696 (45MB)
51 11:46:20.806924 No compression specified
52 11:46:20.808009 progress 0% (0MB)
53 11:46:20.820031 progress 5% (2MB)
54 11:46:20.832225 progress 10% (4MB)
55 11:46:20.844274 progress 15% (6MB)
56 11:46:20.856574 progress 20% (9MB)
57 11:46:20.869059 progress 25% (11MB)
58 11:46:20.881173 progress 30% (13MB)
59 11:46:20.893425 progress 35% (15MB)
60 11:46:20.905420 progress 40% (18MB)
61 11:46:20.917683 progress 45% (20MB)
62 11:46:20.929928 progress 50% (22MB)
63 11:46:20.941894 progress 55% (24MB)
64 11:46:20.953891 progress 60% (27MB)
65 11:46:20.966039 progress 65% (29MB)
66 11:46:20.978297 progress 70% (31MB)
67 11:46:20.990329 progress 75% (34MB)
68 11:46:21.002483 progress 80% (36MB)
69 11:46:21.014680 progress 85% (38MB)
70 11:46:21.026738 progress 90% (40MB)
71 11:46:21.038733 progress 95% (43MB)
72 11:46:21.050510 progress 100% (45MB)
73 11:46:21.050637 45MB downloaded in 0.24s (186.15MB/s)
74 11:46:21.050784 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:46:21.051015 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:46:21.051103 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:46:21.051190 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:46:21.051329 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:46:21.051399 saving as /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/dtb/mt8192-asurada-spherion-r0.dtb
81 11:46:21.051462 total size: 46924 (0MB)
82 11:46:21.051523 No compression specified
83 11:46:21.094661 progress 69% (0MB)
84 11:46:21.094955 progress 100% (0MB)
85 11:46:21.095112 0MB downloaded in 0.04s (1.03MB/s)
86 11:46:21.095243 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:46:21.095468 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:46:21.095555 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:46:21.095639 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:46:21.095756 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:46:21.095826 saving as /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/modules/modules.tar
93 11:46:21.095888 total size: 8555256 (8MB)
94 11:46:21.095949 Using unxz to decompress xz
95 11:46:21.099216 progress 0% (0MB)
96 11:46:21.122023 progress 5% (0MB)
97 11:46:21.146651 progress 10% (0MB)
98 11:46:21.171064 progress 15% (1MB)
99 11:46:21.195788 progress 20% (1MB)
100 11:46:21.220346 progress 25% (2MB)
101 11:46:21.243192 progress 30% (2MB)
102 11:46:21.269225 progress 35% (2MB)
103 11:46:21.293351 progress 40% (3MB)
104 11:46:21.316586 progress 45% (3MB)
105 11:46:21.343931 progress 50% (4MB)
106 11:46:21.369160 progress 55% (4MB)
107 11:46:21.394219 progress 60% (4MB)
108 11:46:21.419260 progress 65% (5MB)
109 11:46:21.444309 progress 70% (5MB)
110 11:46:21.468726 progress 75% (6MB)
111 11:46:21.492145 progress 80% (6MB)
112 11:46:21.516024 progress 85% (6MB)
113 11:46:21.544587 progress 90% (7MB)
114 11:46:21.571939 progress 95% (7MB)
115 11:46:21.596716 progress 100% (8MB)
116 11:46:21.600975 8MB downloaded in 0.51s (16.15MB/s)
117 11:46:21.601255 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:46:21.601551 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:46:21.601661 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:46:21.601786 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:46:21.601886 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:46:21.601994 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:46:21.602269 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl
125 11:46:21.602435 makedir: /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin
126 11:46:21.602577 makedir: /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/tests
127 11:46:21.602722 makedir: /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/results
128 11:46:21.602840 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-add-keys
129 11:46:21.602994 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-add-sources
130 11:46:21.603127 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-background-process-start
131 11:46:21.603269 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-background-process-stop
132 11:46:21.603398 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-common-functions
133 11:46:21.603533 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-echo-ipv4
134 11:46:21.603660 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-install-packages
135 11:46:21.603796 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-installed-packages
136 11:46:21.603919 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-os-build
137 11:46:21.604057 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-probe-channel
138 11:46:21.604180 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-probe-ip
139 11:46:21.604335 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-target-ip
140 11:46:21.604499 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-target-mac
141 11:46:21.604654 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-target-storage
142 11:46:21.604866 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-test-case
143 11:46:21.605026 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-test-event
144 11:46:21.605150 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-test-feedback
145 11:46:21.605284 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-test-raise
146 11:46:21.605410 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-test-reference
147 11:46:21.605547 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-test-runner
148 11:46:21.605673 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-test-set
149 11:46:21.605815 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-test-shell
150 11:46:21.605942 Updating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-install-packages (oe)
151 11:46:21.876960 Updating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/bin/lava-installed-packages (oe)
152 11:46:21.877269 Creating /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/environment
153 11:46:21.877458 LAVA metadata
154 11:46:21.877596 - LAVA_JOB_ID=10742264
155 11:46:21.877728 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:46:21.877925 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:46:21.878051 skipped lava-vland-overlay
158 11:46:21.878195 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:46:21.878341 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:46:21.878465 skipped lava-multinode-overlay
161 11:46:21.878602 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:46:21.878749 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:46:21.878892 Loading test definitions
164 11:46:21.879060 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:46:21.879199 Using /lava-10742264 at stage 0
166 11:46:21.879731 uuid=10742264_1.5.2.3.1 testdef=None
167 11:46:21.879883 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:46:21.880034 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:46:21.880987 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:46:21.881442 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:46:21.882572 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:46:21.883053 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:46:22.997443 runner path: /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/0/tests/0_cros-ec test_uuid 10742264_1.5.2.3.1
176 11:46:23.005928 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:01) [common]
178 11:46:23.008343 Creating lava-test-runner.conf files
179 11:46:23.009028 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742264/lava-overlay-fgg8ixsl/lava-10742264/0 for stage 0
180 11:46:23.009893 - 0_cros-ec
181 11:46:23.010791 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
182 11:46:23.011582 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
183 11:46:23.095430 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:46:23.095879 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
185 11:46:23.096224 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:46:23.096562 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
187 11:46:23.096948 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
188 11:46:24.055205 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:46:24.055582 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 11:46:24.055695 extracting modules file /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742264/extract-overlay-ramdisk-l8d0lq95/ramdisk
191 11:46:24.342123 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:46:24.342325 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 11:46:24.342449 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742264/compress-overlay-ptbgfecr/overlay-1.5.2.4.tar.gz to ramdisk
194 11:46:24.342560 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742264/compress-overlay-ptbgfecr/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742264/extract-overlay-ramdisk-l8d0lq95/ramdisk
195 11:46:24.351679 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:46:24.351798 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 11:46:24.351889 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:46:24.351987 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 11:46:24.352068 Building ramdisk /var/lib/lava/dispatcher/tmp/10742264/extract-overlay-ramdisk-l8d0lq95/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742264/extract-overlay-ramdisk-l8d0lq95/ramdisk
200 11:46:26.702136 >> 269475 blocks
201 11:46:32.112078 rename /var/lib/lava/dispatcher/tmp/10742264/extract-overlay-ramdisk-l8d0lq95/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/ramdisk/ramdisk.cpio.gz
202 11:46:32.112485 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 11:46:32.112609 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 11:46:32.112708 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 11:46:32.112840 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/kernel/Image'
206 11:46:44.486081 Returned 0 in 12 seconds
207 11:46:44.586992 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/kernel/image.itb
208 11:46:47.792877 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:46:47.794386 output: Created: Thu Jun 15 12:46:45 2023
210 11:46:47.794767 output: Image 0 (kernel-1)
211 11:46:47.795114 output: Description:
212 11:46:47.795450 output: Created: Thu Jun 15 12:46:45 2023
213 11:46:47.795780 output: Type: Kernel Image
214 11:46:47.796105 output: Compression: lzma compressed
215 11:46:47.796397 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
216 11:46:47.796701 output: Architecture: AArch64
217 11:46:47.797026 output: OS: Linux
218 11:46:47.797314 output: Load Address: 0x00000000
219 11:46:47.797605 output: Entry Point: 0x00000000
220 11:46:47.797908 output: Hash algo: crc32
221 11:46:47.798197 output: Hash value: cd22d0e5
222 11:46:47.798480 output: Image 1 (fdt-1)
223 11:46:47.798759 output: Description: mt8192-asurada-spherion-r0
224 11:46:47.799040 output: Created: Thu Jun 15 12:46:45 2023
225 11:46:47.799323 output: Type: Flat Device Tree
226 11:46:47.799604 output: Compression: uncompressed
227 11:46:47.799882 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:46:47.800163 output: Architecture: AArch64
229 11:46:47.800440 output: Hash algo: crc32
230 11:46:47.800719 output: Hash value: 1df858fa
231 11:46:47.801020 output: Image 2 (ramdisk-1)
232 11:46:47.801301 output: Description: unavailable
233 11:46:47.801577 output: Created: Thu Jun 15 12:46:45 2023
234 11:46:47.801853 output: Type: RAMDisk Image
235 11:46:47.802134 output: Compression: Unknown Compression
236 11:46:47.802414 output: Data Size: 47386741 Bytes = 46276.11 KiB = 45.19 MiB
237 11:46:47.802692 output: Architecture: AArch64
238 11:46:47.802970 output: OS: Linux
239 11:46:47.803245 output: Load Address: unavailable
240 11:46:47.803586 output: Entry Point: unavailable
241 11:46:47.803877 output: Hash algo: crc32
242 11:46:47.804156 output: Hash value: 5a11bb32
243 11:46:47.804435 output: Default Configuration: 'conf-1'
244 11:46:47.804715 output: Configuration 0 (conf-1)
245 11:46:47.805050 output: Description: mt8192-asurada-spherion-r0
246 11:46:47.805335 output: Kernel: kernel-1
247 11:46:47.805617 output: Init Ramdisk: ramdisk-1
248 11:46:47.805895 output: FDT: fdt-1
249 11:46:47.806372 output: Loadables: kernel-1
250 11:46:47.806684 output:
251 11:46:47.807574 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 11:46:47.808097 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 11:46:47.808657 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 11:46:47.809180 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
255 11:46:47.809581 No LXC device requested
256 11:46:47.810008 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:46:47.810664 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
258 11:46:47.811102 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:46:47.811463 Checking files for TFTP limit of 4294967296 bytes.
260 11:46:47.814468 end: 1 tftp-deploy (duration 00:00:27) [common]
261 11:46:47.814994 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:46:47.815461 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:46:47.816086 substitutions:
264 11:46:47.816442 - {DTB}: 10742264/tftp-deploy-jijrys3y/dtb/mt8192-asurada-spherion-r0.dtb
265 11:46:47.816784 - {INITRD}: 10742264/tftp-deploy-jijrys3y/ramdisk/ramdisk.cpio.gz
266 11:46:47.817145 - {KERNEL}: 10742264/tftp-deploy-jijrys3y/kernel/Image
267 11:46:47.817462 - {LAVA_MAC}: None
268 11:46:47.817762 - {PRESEED_CONFIG}: None
269 11:46:47.818061 - {PRESEED_LOCAL}: None
270 11:46:47.818355 - {RAMDISK}: 10742264/tftp-deploy-jijrys3y/ramdisk/ramdisk.cpio.gz
271 11:46:47.818648 - {ROOT_PART}: None
272 11:46:47.818938 - {ROOT}: None
273 11:46:47.819221 - {SERVER_IP}: 192.168.201.1
274 11:46:47.819504 - {TEE}: None
275 11:46:47.819787 Parsed boot commands:
276 11:46:47.820069 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:46:47.820923 Parsed boot commands: tftpboot 192.168.201.1 10742264/tftp-deploy-jijrys3y/kernel/image.itb 10742264/tftp-deploy-jijrys3y/kernel/cmdline
278 11:46:47.821537 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:46:47.821950 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:46:47.822293 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:46:47.822605 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:46:47.822867 Not connected, no need to disconnect.
283 11:46:47.823145 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:46:47.823453 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:46:47.823826 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
286 11:46:47.832227 Setting prompt string to ['lava-test: # ']
287 11:46:47.833217 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:46:47.833526 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:46:47.833854 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:46:47.834171 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:46:47.834697 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 11:46:53.007249 >> Command sent successfully.
293 11:46:53.017452 Returned 0 in 5 seconds
294 11:46:53.118655 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:46:53.121929 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:46:53.122801 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:46:53.123494 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:46:53.123961 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:46:53.124401 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:46:53.126042 [Enter `^Ec?' for help]
302 11:46:53.285459
303 11:46:53.285647
304 11:46:53.285765 F0: 102B 0000
305 11:46:53.285862
306 11:46:53.288819 F3: 1001 0000 [0200]
307 11:46:53.288912
308 11:46:53.288980 F3: 1001 0000
309 11:46:53.289044
310 11:46:53.289109 F7: 102D 0000
311 11:46:53.289169
312 11:46:53.292444 F1: 0000 0000
313 11:46:53.292563
314 11:46:53.292638 V0: 0000 0000 [0001]
315 11:46:53.292710
316 11:46:53.292788 00: 0007 8000
317 11:46:53.295908
318 11:46:53.296039 01: 0000 0000
319 11:46:53.296144
320 11:46:53.296240 BP: 0C00 0209 [0000]
321 11:46:53.296335
322 11:46:53.299343 G0: 1182 0000
323 11:46:53.299433
324 11:46:53.299500 EC: 0000 0021 [4000]
325 11:46:53.299578
326 11:46:53.303452 S7: 0000 0000 [0000]
327 11:46:53.303600
328 11:46:53.303699 CC: 0000 0000 [0001]
329 11:46:53.303792
330 11:46:53.307057 T0: 0000 0040 [010F]
331 11:46:53.307186
332 11:46:53.307296 Jump to BL
333 11:46:53.307401
334 11:46:53.332512
335 11:46:53.332697
336 11:46:53.332838
337 11:46:53.339851 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:46:53.343799 ARM64: Exception handlers installed.
339 11:46:53.347122 ARM64: Testing exception
340 11:46:53.351476 ARM64: Done test exception
341 11:46:53.358420 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:46:53.365324 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:46:53.372435 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:46:53.382759 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:46:53.389608 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:46:53.399859 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:46:53.410959 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:46:53.417873 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:46:53.435292 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:46:53.438122 WDT: Last reset was cold boot
351 11:46:53.441582 SPI1(PAD0) initialized at 2873684 Hz
352 11:46:53.445264 SPI5(PAD0) initialized at 992727 Hz
353 11:46:53.448512 VBOOT: Loading verstage.
354 11:46:53.455180 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:46:53.459701 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:46:53.462926 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:46:53.466327 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:46:53.472783 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:46:53.479371 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:46:53.490245 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 11:46:53.490508
362 11:46:53.490670
363 11:46:53.500327 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:46:53.503926 ARM64: Exception handlers installed.
365 11:46:53.507248 ARM64: Testing exception
366 11:46:53.507360 ARM64: Done test exception
367 11:46:53.514085 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:46:53.517057 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:46:53.531001 Probing TPM: . done!
370 11:46:53.531187 TPM ready after 0 ms
371 11:46:53.537931 Connected to device vid:did:rid of 1ae0:0028:00
372 11:46:53.544935 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 11:46:53.604688 Initialized TPM device CR50 revision 0
374 11:46:53.615997 tlcl_send_startup: Startup return code is 0
375 11:46:53.616200 TPM: setup succeeded
376 11:46:53.627622 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:46:53.636419 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:46:53.650614 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:46:53.658254 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:46:53.661635 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:46:53.665662 in-header: 03 07 00 00 08 00 00 00
382 11:46:53.668871 in-data: aa e4 47 04 13 02 00 00
383 11:46:53.669168 Chrome EC: UHEPI supported
384 11:46:53.676173 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:46:53.679738 in-header: 03 95 00 00 08 00 00 00
386 11:46:53.683870 in-data: 18 20 20 08 00 00 00 00
387 11:46:53.684076 Phase 1
388 11:46:53.687500 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:46:53.694784 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:46:53.702717 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:46:53.702943 Recovery requested (1009000e)
392 11:46:53.712176 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:46:53.717694 tlcl_extend: response is 0
394 11:46:53.727216 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:46:53.732020 tlcl_extend: response is 0
396 11:46:53.738940 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:46:53.759392 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:46:53.766043 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:46:53.766141
400 11:46:53.766210
401 11:46:53.775576 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:46:53.779166 ARM64: Exception handlers installed.
403 11:46:53.782445 ARM64: Testing exception
404 11:46:53.782533 ARM64: Done test exception
405 11:46:53.804884 pmic_efuse_setting: Set efuses in 11 msecs
406 11:46:53.808344 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:46:53.814561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:46:53.817914 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:46:53.825349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:46:53.829562 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:46:53.832954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:46:53.837024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:46:53.844456 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:46:53.847724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:46:53.851947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:46:53.855388 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:46:53.863125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:46:53.866872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:46:53.870462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:46:53.877919 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:46:53.881731 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:46:53.889126 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:46:53.892425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:46:53.900671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:46:53.904078 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:46:53.911711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:46:53.915065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:46:53.922470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:46:53.926468 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:46:53.933985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:46:53.937513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:46:53.944822 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:46:53.948268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:46:53.955780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:46:53.959084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:46:53.963439 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:46:53.970235 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:46:53.974247 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:46:53.977721 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:46:53.985112 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:46:53.988513 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:46:53.992473 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:46:53.999927 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:46:54.003666 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:46:54.007714 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:46:54.011123 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:46:54.018692 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:46:54.022315 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:46:54.025636 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:46:54.029668 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:46:54.033438 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:46:54.041015 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:46:54.044449 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:46:54.048343 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:46:54.052489 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:46:54.055985 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:46:54.059492 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:46:54.066650 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:46:54.074739 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:46:54.082019 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:46:54.089471 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:46:54.096453 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:46:54.104284 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:46:54.108092 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:46:54.111504 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:46:54.118852 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 11:46:54.122605 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:46:54.129917 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:46:54.133337 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:46:54.142537 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 11:46:54.151550 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 11:46:54.161227 [RTC]rtc_get_frequency_meter,154: input=19, output=849
473 11:46:54.170947 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 11:46:54.180179 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 11:46:54.190056 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 11:46:54.199943 [RTC]rtc_get_frequency_meter,154: input=17, output=803
477 11:46:54.203335 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:46:54.207294 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:46:54.211303 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:46:54.219091 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:46:54.222622 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:46:54.225889 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:46:54.230007 ADC[4]: Raw value=906203 ID=7
484 11:46:54.230102 ADC[3]: Raw value=213441 ID=1
485 11:46:54.234185 RAM Code: 0x71
486 11:46:54.237635 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:46:54.241054 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:46:54.249010 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:46:54.255884 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:46:54.258992 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:46:54.263051 in-header: 03 07 00 00 08 00 00 00
492 11:46:54.267106 in-data: aa e4 47 04 13 02 00 00
493 11:46:54.270575 Chrome EC: UHEPI supported
494 11:46:54.278223 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:46:54.281496 in-header: 03 95 00 00 08 00 00 00
496 11:46:54.281648 in-data: 18 20 20 08 00 00 00 00
497 11:46:54.285507 MRC: failed to locate region type 0.
498 11:46:54.292652 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:46:54.296927 DRAM-K: Running full calibration
500 11:46:54.303800 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:46:54.304066 header.status = 0x0
502 11:46:54.307820 header.version = 0x6 (expected: 0x6)
503 11:46:54.311106 header.size = 0xd00 (expected: 0xd00)
504 11:46:54.311556 header.flags = 0x0
505 11:46:54.318696 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:46:54.337429 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 11:46:54.344897 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:46:54.345340 dram_init: ddr_geometry: 2
509 11:46:54.348357 [EMI] MDL number = 2
510 11:46:54.348786 [EMI] Get MDL freq = 0
511 11:46:54.352659 dram_init: ddr_type: 0
512 11:46:54.356005 is_discrete_lpddr4: 1
513 11:46:54.356439 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:46:54.359874
515 11:46:54.360435
516 11:46:54.360974 [Bian_co] ETT version 0.0.0.1
517 11:46:54.363894 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:46:54.364325
519 11:46:54.367693 dramc_set_vcore_voltage set vcore to 650000
520 11:46:54.371745 Read voltage for 800, 4
521 11:46:54.372218 Vio18 = 0
522 11:46:54.375385 Vcore = 650000
523 11:46:54.375988 Vdram = 0
524 11:46:54.376354 Vddq = 0
525 11:46:54.376680 Vmddr = 0
526 11:46:54.378907 dram_init: config_dvfs: 1
527 11:46:54.382887 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:46:54.390282 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:46:54.393624 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 11:46:54.397744 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 11:46:54.401109 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 11:46:54.404615 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 11:46:54.407908 MEM_TYPE=3, freq_sel=18
534 11:46:54.411486 sv_algorithm_assistance_LP4_1600
535 11:46:54.414640 ============ PULL DRAM RESETB DOWN ============
536 11:46:54.417536 ========== PULL DRAM RESETB DOWN end =========
537 11:46:54.421589 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:46:54.425014 ===================================
539 11:46:54.428883 LPDDR4 DRAM CONFIGURATION
540 11:46:54.432770 ===================================
541 11:46:54.433245 EX_ROW_EN[0] = 0x0
542 11:46:54.436616 EX_ROW_EN[1] = 0x0
543 11:46:54.437097 LP4Y_EN = 0x0
544 11:46:54.440038 WORK_FSP = 0x0
545 11:46:54.440465 WL = 0x2
546 11:46:54.443816 RL = 0x2
547 11:46:54.444242 BL = 0x2
548 11:46:54.446678 RPST = 0x0
549 11:46:54.447104 RD_PRE = 0x0
550 11:46:54.450152 WR_PRE = 0x1
551 11:46:54.450581 WR_PST = 0x0
552 11:46:54.453892 DBI_WR = 0x0
553 11:46:54.454319 DBI_RD = 0x0
554 11:46:54.456887 OTF = 0x1
555 11:46:54.460354 ===================================
556 11:46:54.463680 ===================================
557 11:46:54.464106 ANA top config
558 11:46:54.467762 ===================================
559 11:46:54.471787 DLL_ASYNC_EN = 0
560 11:46:54.472212 ALL_SLAVE_EN = 1
561 11:46:54.475227 NEW_RANK_MODE = 1
562 11:46:54.478271 DLL_IDLE_MODE = 1
563 11:46:54.481581 LP45_APHY_COMB_EN = 1
564 11:46:54.482007 TX_ODT_DIS = 1
565 11:46:54.484947 NEW_8X_MODE = 1
566 11:46:54.489432 ===================================
567 11:46:54.492727 ===================================
568 11:46:54.496098 data_rate = 1600
569 11:46:54.499466 CKR = 1
570 11:46:54.499898 DQ_P2S_RATIO = 8
571 11:46:54.502699 ===================================
572 11:46:54.505909 CA_P2S_RATIO = 8
573 11:46:54.509430 DQ_CA_OPEN = 0
574 11:46:54.512751 DQ_SEMI_OPEN = 0
575 11:46:54.516340 CA_SEMI_OPEN = 0
576 11:46:54.516782 CA_FULL_RATE = 0
577 11:46:54.519493 DQ_CKDIV4_EN = 1
578 11:46:54.522889 CA_CKDIV4_EN = 1
579 11:46:54.526151 CA_PREDIV_EN = 0
580 11:46:54.529802 PH8_DLY = 0
581 11:46:54.533021 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:46:54.533575 DQ_AAMCK_DIV = 4
583 11:46:54.536394 CA_AAMCK_DIV = 4
584 11:46:54.539558 CA_ADMCK_DIV = 4
585 11:46:54.542781 DQ_TRACK_CA_EN = 0
586 11:46:54.546031 CA_PICK = 800
587 11:46:54.549315 CA_MCKIO = 800
588 11:46:54.549923 MCKIO_SEMI = 0
589 11:46:54.553486 PLL_FREQ = 3068
590 11:46:54.557171 DQ_UI_PI_RATIO = 32
591 11:46:54.560525 CA_UI_PI_RATIO = 0
592 11:46:54.564711 ===================================
593 11:46:54.568164 ===================================
594 11:46:54.568601 memory_type:LPDDR4
595 11:46:54.571489 GP_NUM : 10
596 11:46:54.571928 SRAM_EN : 1
597 11:46:54.575689 MD32_EN : 0
598 11:46:54.579204 ===================================
599 11:46:54.579832 [ANA_INIT] >>>>>>>>>>>>>>
600 11:46:54.582965 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:46:54.586917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:46:54.590360 ===================================
603 11:46:54.593893 data_rate = 1600,PCW = 0X7600
604 11:46:54.597421 ===================================
605 11:46:54.599881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:46:54.603370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:46:54.610194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:46:54.616567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:46:54.620112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:46:54.623473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:46:54.624014 [ANA_INIT] flow start
612 11:46:54.626931 [ANA_INIT] PLL >>>>>>>>
613 11:46:54.630391 [ANA_INIT] PLL <<<<<<<<
614 11:46:54.630829 [ANA_INIT] MIDPI >>>>>>>>
615 11:46:54.633149 [ANA_INIT] MIDPI <<<<<<<<
616 11:46:54.636606 [ANA_INIT] DLL >>>>>>>>
617 11:46:54.637204 [ANA_INIT] flow end
618 11:46:54.639994 ============ LP4 DIFF to SE enter ============
619 11:46:54.647169 ============ LP4 DIFF to SE exit ============
620 11:46:54.647729 [ANA_INIT] <<<<<<<<<<<<<
621 11:46:54.649926 [Flow] Enable top DCM control >>>>>
622 11:46:54.653310 [Flow] Enable top DCM control <<<<<
623 11:46:54.656552 Enable DLL master slave shuffle
624 11:46:54.663128 ==============================================================
625 11:46:54.663233 Gating Mode config
626 11:46:54.669897 ==============================================================
627 11:46:54.673197 Config description:
628 11:46:54.683499 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:46:54.689694 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:46:54.693600 SELPH_MODE 0: By rank 1: By Phase
631 11:46:54.699706 ==============================================================
632 11:46:54.703215 GAT_TRACK_EN = 1
633 11:46:54.703318 RX_GATING_MODE = 2
634 11:46:54.706591 RX_GATING_TRACK_MODE = 2
635 11:46:54.710053 SELPH_MODE = 1
636 11:46:54.713294 PICG_EARLY_EN = 1
637 11:46:54.716517 VALID_LAT_VALUE = 1
638 11:46:54.723204 ==============================================================
639 11:46:54.726671 Enter into Gating configuration >>>>
640 11:46:54.729884 Exit from Gating configuration <<<<
641 11:46:54.733328 Enter into DVFS_PRE_config >>>>>
642 11:46:54.743752 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:46:54.746474 Exit from DVFS_PRE_config <<<<<
644 11:46:54.750455 Enter into PICG configuration >>>>
645 11:46:54.753913 Exit from PICG configuration <<<<
646 11:46:54.757164 [RX_INPUT] configuration >>>>>
647 11:46:54.757242 [RX_INPUT] configuration <<<<<
648 11:46:54.763702 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:46:54.770532 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:46:54.773861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:46:54.780535 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:46:54.786606 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:46:54.793739 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:46:54.797166 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:46:54.800407 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:46:54.807246 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:46:54.810158 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:46:54.813463 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:46:54.816838 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:46:54.820447 ===================================
661 11:46:54.823625 LPDDR4 DRAM CONFIGURATION
662 11:46:54.827143 ===================================
663 11:46:54.830573 EX_ROW_EN[0] = 0x0
664 11:46:54.830696 EX_ROW_EN[1] = 0x0
665 11:46:54.833665 LP4Y_EN = 0x0
666 11:46:54.833786 WORK_FSP = 0x0
667 11:46:54.837209 WL = 0x2
668 11:46:54.837330 RL = 0x2
669 11:46:54.840630 BL = 0x2
670 11:46:54.840733 RPST = 0x0
671 11:46:54.843965 RD_PRE = 0x0
672 11:46:54.844092 WR_PRE = 0x1
673 11:46:54.847264 WR_PST = 0x0
674 11:46:54.847380 DBI_WR = 0x0
675 11:46:54.850893 DBI_RD = 0x0
676 11:46:54.850993 OTF = 0x1
677 11:46:54.854292 ===================================
678 11:46:54.857702 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:46:54.864475 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:46:54.867798 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:46:54.871236 ===================================
682 11:46:54.873995 LPDDR4 DRAM CONFIGURATION
683 11:46:54.877415 ===================================
684 11:46:54.877556 EX_ROW_EN[0] = 0x10
685 11:46:54.880782 EX_ROW_EN[1] = 0x0
686 11:46:54.884276 LP4Y_EN = 0x0
687 11:46:54.884447 WORK_FSP = 0x0
688 11:46:54.887741 WL = 0x2
689 11:46:54.887913 RL = 0x2
690 11:46:54.890611 BL = 0x2
691 11:46:54.890798 RPST = 0x0
692 11:46:54.894548 RD_PRE = 0x0
693 11:46:54.894759 WR_PRE = 0x1
694 11:46:54.898153 WR_PST = 0x0
695 11:46:54.898386 DBI_WR = 0x0
696 11:46:54.900779 DBI_RD = 0x0
697 11:46:54.901113 OTF = 0x1
698 11:46:54.904353 ===================================
699 11:46:54.910985 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:46:54.915131 nWR fixed to 40
701 11:46:54.918309 [ModeRegInit_LP4] CH0 RK0
702 11:46:54.918754 [ModeRegInit_LP4] CH0 RK1
703 11:46:54.921885 [ModeRegInit_LP4] CH1 RK0
704 11:46:54.925459 [ModeRegInit_LP4] CH1 RK1
705 11:46:54.925828 match AC timing 13
706 11:46:54.931408 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:46:54.934638 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:46:54.938698 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:46:54.945148 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:46:54.948533 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:46:54.949087 [EMI DOE] emi_dcm 0
712 11:46:54.955216 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:46:54.955695 ==
714 11:46:54.958703 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:46:54.961915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:46:54.962405 ==
717 11:46:54.968855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:46:54.972024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:46:54.981814 [CA 0] Center 36 (6~67) winsize 62
720 11:46:54.985132 [CA 1] Center 36 (6~67) winsize 62
721 11:46:54.988606 [CA 2] Center 34 (4~65) winsize 62
722 11:46:54.992159 [CA 3] Center 34 (4~64) winsize 61
723 11:46:54.995582 [CA 4] Center 33 (2~64) winsize 63
724 11:46:54.998710 [CA 5] Center 32 (2~62) winsize 61
725 11:46:54.998783
726 11:46:55.002312 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:46:55.002388
728 11:46:55.005037 [CATrainingPosCal] consider 1 rank data
729 11:46:55.008995 u2DelayCellTimex100 = 270/100 ps
730 11:46:55.012309 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 11:46:55.015433 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 11:46:55.022059 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 11:46:55.025524 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 11:46:55.029203 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 11:46:55.032017 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 11:46:55.032100
737 11:46:55.035450 CA PerBit enable=1, Macro0, CA PI delay=32
738 11:46:55.035551
739 11:46:55.038684 [CBTSetCACLKResult] CA Dly = 32
740 11:46:55.038775 CS Dly: 4 (0~35)
741 11:46:55.038843 ==
742 11:46:55.042667 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:46:55.048826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:46:55.048924 ==
745 11:46:55.052362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:46:55.059048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:46:55.068534 [CA 0] Center 36 (6~67) winsize 62
748 11:46:55.071833 [CA 1] Center 36 (6~67) winsize 62
749 11:46:55.075133 [CA 2] Center 34 (4~65) winsize 62
750 11:46:55.078499 [CA 3] Center 34 (3~65) winsize 63
751 11:46:55.082084 [CA 4] Center 32 (2~63) winsize 62
752 11:46:55.085408 [CA 5] Center 32 (2~63) winsize 62
753 11:46:55.085496
754 11:46:55.088765 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:46:55.088892
756 11:46:55.091524 [CATrainingPosCal] consider 2 rank data
757 11:46:55.094855 u2DelayCellTimex100 = 270/100 ps
758 11:46:55.098261 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 11:46:55.101838 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 11:46:55.105441 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 11:46:55.112294 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 11:46:55.115102 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 11:46:55.118304 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 11:46:55.118389
765 11:46:55.122242 CA PerBit enable=1, Macro0, CA PI delay=32
766 11:46:55.122343
767 11:46:55.124917 [CBTSetCACLKResult] CA Dly = 32
768 11:46:55.125020 CS Dly: 5 (0~37)
769 11:46:55.125090
770 11:46:55.128857 ----->DramcWriteLeveling(PI) begin...
771 11:46:55.128948 ==
772 11:46:55.132458 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:46:55.136044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:46:55.140283 ==
775 11:46:55.140371 Write leveling (Byte 0): 34 => 34
776 11:46:55.143613 Write leveling (Byte 1): 30 => 30
777 11:46:55.146785 DramcWriteLeveling(PI) end<-----
778 11:46:55.146870
779 11:46:55.146946 ==
780 11:46:55.151094 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:46:55.153623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:46:55.153742 ==
783 11:46:55.157038 [Gating] SW mode calibration
784 11:46:55.163813 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:46:55.171095 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:46:55.174463 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:46:55.177832 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:46:55.184305 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 11:46:55.187659 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 11:46:55.190923 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:46:55.197688 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:46:55.201200 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:46:55.204471 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:46:55.210687 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:46:55.214134 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:46:55.217756 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:46:55.221073 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:46:55.227727 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:46:55.231030 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:46:55.234599 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:46:55.240854 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:46:55.244256 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:46:55.248090 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:46:55.254699 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 11:46:55.257784 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 11:46:55.260853 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:46:55.267554 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:46:55.270976 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:46:55.274413 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:46:55.280936 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:46:55.284162 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:46:55.287538 0 9 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
813 11:46:55.291484 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 11:46:55.298349 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:46:55.301197 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:46:55.310993 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:46:55.311603 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:46:55.314334 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:46:55.317815 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
820 11:46:55.324464 0 10 8 | B1->B0 | 3030 2828 | 0 0 | (0 1) (0 0)
821 11:46:55.327804 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 11:46:55.331160 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:46:55.338322 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:46:55.341564 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:46:55.344957 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:46:55.351188 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:46:55.354737 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 11:46:55.358110 0 11 8 | B1->B0 | 3030 4545 | 0 0 | (0 0) (0 0)
829 11:46:55.364654 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 11:46:55.367786 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:46:55.371049 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:46:55.377897 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:46:55.381537 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:46:55.384366 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:46:55.388116 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:46:55.394506 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 11:46:55.397746 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:46:55.401072 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:46:55.407733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:46:55.411092 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:46:55.414436 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:46:55.421213 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:46:55.424676 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:46:55.428105 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:46:55.434923 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:46:55.438182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:46:55.441312 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:46:55.447580 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:46:55.450945 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:46:55.454479 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:46:55.461269 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:46:55.464641 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 11:46:55.468034 Total UI for P1: 0, mck2ui 16
854 11:46:55.471066 best dqsien dly found for B0: ( 0, 14, 4)
855 11:46:55.474286 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:46:55.477647 Total UI for P1: 0, mck2ui 16
857 11:46:55.481501 best dqsien dly found for B1: ( 0, 14, 10)
858 11:46:55.485493 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 11:46:55.489359 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 11:46:55.489467
861 11:46:55.492624 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 11:46:55.495974 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 11:46:55.499271 [Gating] SW calibration Done
864 11:46:55.499381 ==
865 11:46:55.502443 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:46:55.506366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:46:55.506488 ==
868 11:46:55.509717 RX Vref Scan: 0
869 11:46:55.509850
870 11:46:55.509967 RX Vref 0 -> 0, step: 1
871 11:46:55.510060
872 11:46:55.512641 RX Delay -130 -> 252, step: 16
873 11:46:55.516353 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
874 11:46:55.522536 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 11:46:55.525967 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 11:46:55.529376 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
877 11:46:55.532774 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 11:46:55.536420 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 11:46:55.543111 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 11:46:55.546398 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 11:46:55.549599 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 11:46:55.552617 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
883 11:46:55.556048 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
884 11:46:55.562815 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 11:46:55.566223 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
886 11:46:55.569704 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 11:46:55.573100 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 11:46:55.576201 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 11:46:55.579579 ==
890 11:46:55.579680 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:46:55.586258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:46:55.586357 ==
893 11:46:55.586447 DQS Delay:
894 11:46:55.589613 DQS0 = 0, DQS1 = 0
895 11:46:55.589702 DQM Delay:
896 11:46:55.592944 DQM0 = 90, DQM1 = 86
897 11:46:55.593031 DQ Delay:
898 11:46:55.596190 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
899 11:46:55.599371 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 11:46:55.602782 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
901 11:46:55.606161 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 11:46:55.606261
903 11:46:55.606348
904 11:46:55.606429 ==
905 11:46:55.609934 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:46:55.613206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:46:55.613303 ==
908 11:46:55.613374
909 11:46:55.613437
910 11:46:55.616541 TX Vref Scan disable
911 11:46:55.619904 == TX Byte 0 ==
912 11:46:55.623163 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 11:46:55.626608 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 11:46:55.626694 == TX Byte 1 ==
915 11:46:55.633387 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 11:46:55.636730 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 11:46:55.636821 ==
918 11:46:55.639639 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:46:55.642861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:46:55.642946 ==
921 11:46:55.657457 TX Vref=22, minBit 8, minWin=27, winSum=448
922 11:46:55.661100 TX Vref=24, minBit 8, minWin=27, winSum=451
923 11:46:55.664448 TX Vref=26, minBit 0, minWin=28, winSum=454
924 11:46:55.667832 TX Vref=28, minBit 4, minWin=28, winSum=455
925 11:46:55.671098 TX Vref=30, minBit 5, minWin=28, winSum=458
926 11:46:55.677231 TX Vref=32, minBit 5, minWin=28, winSum=455
927 11:46:55.681074 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
928 11:46:55.681166
929 11:46:55.684451 Final TX Range 1 Vref 30
930 11:46:55.684539
931 11:46:55.684644 ==
932 11:46:55.687704 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:46:55.691046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:46:55.691137 ==
935 11:46:55.691226
936 11:46:55.694071
937 11:46:55.694158 TX Vref Scan disable
938 11:46:55.697891 == TX Byte 0 ==
939 11:46:55.701237 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 11:46:55.704379 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 11:46:55.707561 == TX Byte 1 ==
942 11:46:55.710801 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
943 11:46:55.714175 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
944 11:46:55.717420
945 11:46:55.717506 [DATLAT]
946 11:46:55.717594 Freq=800, CH0 RK0
947 11:46:55.717677
948 11:46:55.720729 DATLAT Default: 0xa
949 11:46:55.720842 0, 0xFFFF, sum = 0
950 11:46:55.724507 1, 0xFFFF, sum = 0
951 11:46:55.724597 2, 0xFFFF, sum = 0
952 11:46:55.727792 3, 0xFFFF, sum = 0
953 11:46:55.727881 4, 0xFFFF, sum = 0
954 11:46:55.731249 5, 0xFFFF, sum = 0
955 11:46:55.731337 6, 0xFFFF, sum = 0
956 11:46:55.734662 7, 0xFFFF, sum = 0
957 11:46:55.738653 8, 0xFFFF, sum = 0
958 11:46:55.738741 9, 0x0, sum = 1
959 11:46:55.738830 10, 0x0, sum = 2
960 11:46:55.741403 11, 0x0, sum = 3
961 11:46:55.741491 12, 0x0, sum = 4
962 11:46:55.744133 best_step = 10
963 11:46:55.744219
964 11:46:55.744305 ==
965 11:46:55.747429 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:46:55.750801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:46:55.750889 ==
968 11:46:55.754112 RX Vref Scan: 1
969 11:46:55.754237
970 11:46:55.754316 Set Vref Range= 32 -> 127
971 11:46:55.754381
972 11:46:55.757508 RX Vref 32 -> 127, step: 1
973 11:46:55.757594
974 11:46:55.760842 RX Delay -79 -> 252, step: 8
975 11:46:55.760967
976 11:46:55.764266 Set Vref, RX VrefLevel [Byte0]: 32
977 11:46:55.767450 [Byte1]: 32
978 11:46:55.767543
979 11:46:55.771264 Set Vref, RX VrefLevel [Byte0]: 33
980 11:46:55.774510 [Byte1]: 33
981 11:46:55.777909
982 11:46:55.777999 Set Vref, RX VrefLevel [Byte0]: 34
983 11:46:55.781254 [Byte1]: 34
984 11:46:55.785371
985 11:46:55.785458 Set Vref, RX VrefLevel [Byte0]: 35
986 11:46:55.788608 [Byte1]: 35
987 11:46:55.792735
988 11:46:55.792880 Set Vref, RX VrefLevel [Byte0]: 36
989 11:46:55.796143 [Byte1]: 36
990 11:46:55.800092
991 11:46:55.804070 Set Vref, RX VrefLevel [Byte0]: 37
992 11:46:55.804157 [Byte1]: 37
993 11:46:55.808249
994 11:46:55.808333 Set Vref, RX VrefLevel [Byte0]: 38
995 11:46:55.812126 [Byte1]: 38
996 11:46:55.815393
997 11:46:55.815480 Set Vref, RX VrefLevel [Byte0]: 39
998 11:46:55.819309 [Byte1]: 39
999 11:46:55.823255
1000 11:46:55.826565 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:46:55.826655 [Byte1]: 40
1002 11:46:55.831051
1003 11:46:55.831139 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:46:55.834346 [Byte1]: 41
1005 11:46:55.838382
1006 11:46:55.838470 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:46:55.841883 [Byte1]: 42
1008 11:46:55.845919
1009 11:46:55.846005 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:46:55.849418 [Byte1]: 43
1011 11:46:55.853316
1012 11:46:55.853402 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:46:55.856779 [Byte1]: 44
1014 11:46:55.860799
1015 11:46:55.860910 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:46:55.864267 [Byte1]: 45
1017 11:46:55.868348
1018 11:46:55.868448 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:46:55.871460 [Byte1]: 46
1020 11:46:55.876029
1021 11:46:55.876117 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:46:55.879185 [Byte1]: 47
1023 11:46:55.883737
1024 11:46:55.883822 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:46:55.887030 [Byte1]: 48
1026 11:46:55.891093
1027 11:46:55.891185 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:46:55.894403 [Byte1]: 49
1029 11:46:55.898493
1030 11:46:55.898565 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:46:55.901990 [Byte1]: 50
1032 11:46:55.905976
1033 11:46:55.906049 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:46:55.909191 [Byte1]: 51
1035 11:46:55.913694
1036 11:46:55.913794 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:46:55.916898 [Byte1]: 52
1038 11:46:55.921007
1039 11:46:55.921092 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:46:55.924771 [Byte1]: 53
1041 11:46:55.928551
1042 11:46:55.928630 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:46:55.931885 [Byte1]: 54
1044 11:46:55.936146
1045 11:46:55.936231 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:46:55.939878 [Byte1]: 55
1047 11:46:55.943769
1048 11:46:55.943857 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:46:55.947228 [Byte1]: 56
1050 11:46:55.951244
1051 11:46:55.951328 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:46:55.954589 [Byte1]: 57
1053 11:46:55.959240
1054 11:46:55.959328 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:46:55.962115 [Byte1]: 58
1056 11:46:55.966814
1057 11:46:55.966917 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:46:55.970132 [Byte1]: 59
1059 11:46:55.974085
1060 11:46:55.974190 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:46:55.977367 [Byte1]: 60
1062 11:46:55.981502
1063 11:46:55.981586 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:46:55.984865 [Byte1]: 61
1065 11:46:55.989366
1066 11:46:55.989442 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:46:55.992656 [Byte1]: 62
1068 11:46:55.996615
1069 11:46:55.996715 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:46:56.000218 [Byte1]: 63
1071 11:46:56.004097
1072 11:46:56.004197 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:46:56.007412 [Byte1]: 64
1074 11:46:56.012224
1075 11:46:56.012306 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:46:56.015026 [Byte1]: 65
1077 11:46:56.019638
1078 11:46:56.019786 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:46:56.022880 [Byte1]: 66
1080 11:46:56.026682
1081 11:46:56.026788 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:46:56.030532 [Byte1]: 67
1083 11:46:56.034319
1084 11:46:56.034427 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:46:56.037580 [Byte1]: 68
1086 11:46:56.041909
1087 11:46:56.042038 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:46:56.045229 [Byte1]: 69
1089 11:46:56.049687
1090 11:46:56.049796 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:46:56.052954 [Byte1]: 70
1092 11:46:56.057038
1093 11:46:56.057141 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:46:56.060310 [Byte1]: 71
1095 11:46:56.064475
1096 11:46:56.064591 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:46:56.067818 [Byte1]: 72
1098 11:46:56.072530
1099 11:46:56.072641 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:46:56.075225 [Byte1]: 73
1101 11:46:56.079722
1102 11:46:56.079831 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:46:56.083126 [Byte1]: 74
1104 11:46:56.087330
1105 11:46:56.087438 Set Vref, RX VrefLevel [Byte0]: 75
1106 11:46:56.090606 [Byte1]: 75
1107 11:46:56.095127
1108 11:46:56.095241 Set Vref, RX VrefLevel [Byte0]: 76
1109 11:46:56.098330 [Byte1]: 76
1110 11:46:56.102460
1111 11:46:56.102587 Set Vref, RX VrefLevel [Byte0]: 77
1112 11:46:56.105754 [Byte1]: 77
1113 11:46:56.109792
1114 11:46:56.109912 Set Vref, RX VrefLevel [Byte0]: 78
1115 11:46:56.113304 [Byte1]: 78
1116 11:46:56.117292
1117 11:46:56.117400 Final RX Vref Byte 0 = 53 to rank0
1118 11:46:56.121156 Final RX Vref Byte 1 = 61 to rank0
1119 11:46:56.123882 Final RX Vref Byte 0 = 53 to rank1
1120 11:46:56.127757 Final RX Vref Byte 1 = 61 to rank1==
1121 11:46:56.131161 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 11:46:56.137546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 11:46:56.137671 ==
1124 11:46:56.137768 DQS Delay:
1125 11:46:56.137857 DQS0 = 0, DQS1 = 0
1126 11:46:56.140834 DQM Delay:
1127 11:46:56.140957 DQM0 = 91, DQM1 = 86
1128 11:46:56.144091 DQ Delay:
1129 11:46:56.147786 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1130 11:46:56.147876 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1131 11:46:56.151118 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1132 11:46:56.158056 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1133 11:46:56.158173
1134 11:46:56.158271
1135 11:46:56.164465 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1136 11:46:56.167887 CH0 RK0: MR19=606, MR18=493F
1137 11:46:56.174638 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1138 11:46:56.174747
1139 11:46:56.177910 ----->DramcWriteLeveling(PI) begin...
1140 11:46:56.178017 ==
1141 11:46:56.181329 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 11:46:56.184592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 11:46:56.184697 ==
1144 11:46:56.188064 Write leveling (Byte 0): 33 => 33
1145 11:46:56.191475 Write leveling (Byte 1): 31 => 31
1146 11:46:56.194610 DramcWriteLeveling(PI) end<-----
1147 11:46:56.194718
1148 11:46:56.194810 ==
1149 11:46:56.197829 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 11:46:56.201206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 11:46:56.201287 ==
1152 11:46:56.204487 [Gating] SW mode calibration
1153 11:46:56.248410 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 11:46:56.248764 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 11:46:56.248879 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 11:46:56.248947 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 11:46:56.249018 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 11:46:56.249895 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1159 11:46:56.249980 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:46:56.250083 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:46:56.250467 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:46:56.292712 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:46:56.292942 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:46:56.293037 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:46:56.293323 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:46:56.293421 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:46:56.293511 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:46:56.293599 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:46:56.293685 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:46:56.293771 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:46:56.294111 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:46:56.296781 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 11:46:56.300192 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1174 11:46:56.303552 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:46:56.310557 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:46:56.313861 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:46:56.317284 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:46:56.323319 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:46:56.327247 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:46:56.330528 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1181 11:46:56.337081 0 9 8 | B1->B0 | 3232 2e2e | 1 1 | (0 0) (1 1)
1182 11:46:56.340394 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:46:56.343799 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:46:56.347299 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:46:56.353853 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:46:56.357092 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:46:56.360293 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:46:56.367372 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1189 11:46:56.370584 0 10 8 | B1->B0 | 2929 2f2f | 0 0 | (0 0) (1 0)
1190 11:46:56.373707 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:46:56.380955 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:46:56.384382 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:46:56.388336 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:46:56.391647 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:46:56.398181 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:46:56.401503 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1197 11:46:56.405717 0 11 8 | B1->B0 | 3737 3a3a | 1 0 | (0 0) (0 0)
1198 11:46:56.409114 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:46:56.416128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:46:56.419201 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:46:56.423054 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:46:56.425788 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:46:56.432984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:46:56.436390 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:46:56.439736 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 11:46:56.445915 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:46:56.449339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:46:56.452623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:46:56.459494 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:46:56.463439 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:46:56.466690 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:46:56.473213 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:46:56.476524 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:46:56.480484 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:46:56.483836 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:46:56.490239 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:46:56.493649 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:46:56.497055 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:46:56.503667 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:46:56.507016 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:46:56.510561 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 11:46:56.516786 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 11:46:56.517232 Total UI for P1: 0, mck2ui 16
1224 11:46:56.523628 best dqsien dly found for B0: ( 0, 14, 8)
1225 11:46:56.524106 Total UI for P1: 0, mck2ui 16
1226 11:46:56.530085 best dqsien dly found for B1: ( 0, 14, 8)
1227 11:46:56.533276 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 11:46:56.536521 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 11:46:56.536997
1230 11:46:56.539901 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 11:46:56.543104 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 11:46:56.546508 [Gating] SW calibration Done
1233 11:46:56.546931 ==
1234 11:46:56.549860 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 11:46:56.553275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 11:46:56.553702 ==
1237 11:46:56.556729 RX Vref Scan: 0
1238 11:46:56.557198
1239 11:46:56.557536 RX Vref 0 -> 0, step: 1
1240 11:46:56.557853
1241 11:46:56.560334 RX Delay -130 -> 252, step: 16
1242 11:46:56.563449 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 11:46:56.569797 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 11:46:56.573178 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1245 11:46:56.576556 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1246 11:46:56.580348 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 11:46:56.583567 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 11:46:56.590179 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 11:46:56.593385 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 11:46:56.596691 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1251 11:46:56.599809 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1252 11:46:56.603894 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 11:46:56.610263 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 11:46:56.613737 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1255 11:46:56.617089 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1256 11:46:56.619819 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 11:46:56.623265 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1258 11:46:56.626585 ==
1259 11:46:56.627008 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:46:56.633195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:46:56.633625 ==
1262 11:46:56.633968 DQS Delay:
1263 11:46:56.636997 DQS0 = 0, DQS1 = 0
1264 11:46:56.637418 DQM Delay:
1265 11:46:56.640368 DQM0 = 93, DQM1 = 84
1266 11:46:56.640959 DQ Delay:
1267 11:46:56.643531 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1268 11:46:56.646708 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1269 11:46:56.650166 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1270 11:46:56.653449 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1271 11:46:56.653958
1272 11:46:56.654440
1273 11:46:56.654889 ==
1274 11:46:56.656953 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:46:56.660575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 11:46:56.661044 ==
1277 11:46:56.661387
1278 11:46:56.661700
1279 11:46:56.663220 TX Vref Scan disable
1280 11:46:56.666666 == TX Byte 0 ==
1281 11:46:56.670144 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1282 11:46:56.673497 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1283 11:46:56.676707 == TX Byte 1 ==
1284 11:46:56.680070 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1285 11:46:56.683353 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1286 11:46:56.683912 ==
1287 11:46:56.687208 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 11:46:56.690186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 11:46:56.690724 ==
1290 11:46:56.704703 TX Vref=22, minBit 15, minWin=27, winSum=449
1291 11:46:56.707892 TX Vref=24, minBit 11, minWin=27, winSum=451
1292 11:46:56.711204 TX Vref=26, minBit 7, minWin=28, winSum=458
1293 11:46:56.714911 TX Vref=28, minBit 4, minWin=28, winSum=457
1294 11:46:56.717725 TX Vref=30, minBit 7, minWin=28, winSum=460
1295 11:46:56.724479 TX Vref=32, minBit 1, minWin=28, winSum=457
1296 11:46:56.727831 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 30
1297 11:46:56.728327
1298 11:46:56.731180 Final TX Range 1 Vref 30
1299 11:46:56.731777
1300 11:46:56.732350 ==
1301 11:46:56.734611 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 11:46:56.737541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 11:46:56.740906 ==
1304 11:46:56.741199
1305 11:46:56.741492
1306 11:46:56.741756 TX Vref Scan disable
1307 11:46:56.744411 == TX Byte 0 ==
1308 11:46:56.747699 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1309 11:46:56.754706 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1310 11:46:56.754905 == TX Byte 1 ==
1311 11:46:56.757502 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1312 11:46:56.761447 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1313 11:46:56.764693
1314 11:46:56.764920 [DATLAT]
1315 11:46:56.765106 Freq=800, CH0 RK1
1316 11:46:56.765274
1317 11:46:56.768117 DATLAT Default: 0xa
1318 11:46:56.768305 0, 0xFFFF, sum = 0
1319 11:46:56.771322 1, 0xFFFF, sum = 0
1320 11:46:56.771507 2, 0xFFFF, sum = 0
1321 11:46:56.774653 3, 0xFFFF, sum = 0
1322 11:46:56.774841 4, 0xFFFF, sum = 0
1323 11:46:56.777942 5, 0xFFFF, sum = 0
1324 11:46:56.778139 6, 0xFFFF, sum = 0
1325 11:46:56.781209 7, 0xFFFF, sum = 0
1326 11:46:56.784452 8, 0xFFFF, sum = 0
1327 11:46:56.784644 9, 0x0, sum = 1
1328 11:46:56.784860 10, 0x0, sum = 2
1329 11:46:56.787691 11, 0x0, sum = 3
1330 11:46:56.787925 12, 0x0, sum = 4
1331 11:46:56.791547 best_step = 10
1332 11:46:56.791797
1333 11:46:56.792032 ==
1334 11:46:56.794705 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 11:46:56.797893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 11:46:56.798209 ==
1337 11:46:56.801319 RX Vref Scan: 0
1338 11:46:56.801739
1339 11:46:56.802107 RX Vref 0 -> 0, step: 1
1340 11:46:56.802460
1341 11:46:56.804539 RX Delay -79 -> 252, step: 8
1342 11:46:56.811475 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 11:46:56.814891 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 11:46:56.818196 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1345 11:46:56.821362 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1346 11:46:56.824688 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1347 11:46:56.828004 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1348 11:46:56.834582 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 11:46:56.838547 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 11:46:56.841306 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1351 11:46:56.845178 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 11:46:56.848306 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 11:46:56.854723 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 11:46:56.858019 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1355 11:46:56.861300 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1356 11:46:56.864616 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 11:46:56.867931 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1358 11:46:56.871796 ==
1359 11:46:56.875208 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 11:46:56.878467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 11:46:56.878570 ==
1362 11:46:56.878660 DQS Delay:
1363 11:46:56.881738 DQS0 = 0, DQS1 = 0
1364 11:46:56.881810 DQM Delay:
1365 11:46:56.885212 DQM0 = 94, DQM1 = 83
1366 11:46:56.885281 DQ Delay:
1367 11:46:56.888301 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =92
1368 11:46:56.891476 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1369 11:46:56.894669 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1370 11:46:56.898395 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1371 11:46:56.898477
1372 11:46:56.898541
1373 11:46:56.904708 [DQSOSCAuto] RK1, (LSB)MR18= 0x4111, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1374 11:46:56.908615 CH0 RK1: MR19=606, MR18=4111
1375 11:46:56.914930 CH0_RK1: MR19=0x606, MR18=0x4111, DQSOSC=393, MR23=63, INC=95, DEC=63
1376 11:46:56.918141 [RxdqsGatingPostProcess] freq 800
1377 11:46:56.921410 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 11:46:56.924618 Pre-setting of DQS Precalculation
1379 11:46:56.931658 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 11:46:56.931804 ==
1381 11:46:56.934984 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 11:46:56.938387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 11:46:56.938522 ==
1384 11:46:56.944957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 11:46:56.951555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 11:46:56.959188 [CA 0] Center 36 (6~67) winsize 62
1387 11:46:56.962473 [CA 1] Center 36 (6~67) winsize 62
1388 11:46:56.966364 [CA 2] Center 34 (4~65) winsize 62
1389 11:46:56.969056 [CA 3] Center 34 (4~65) winsize 62
1390 11:46:56.972840 [CA 4] Center 35 (5~65) winsize 61
1391 11:46:56.976288 [CA 5] Center 34 (4~64) winsize 61
1392 11:46:56.976423
1393 11:46:56.979447 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1394 11:46:56.979584
1395 11:46:56.982820 [CATrainingPosCal] consider 1 rank data
1396 11:46:56.986189 u2DelayCellTimex100 = 270/100 ps
1397 11:46:56.989613 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 11:46:56.996197 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 11:46:56.999344 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 11:46:57.002642 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 11:46:57.006125 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1402 11:46:57.009365 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 11:46:57.009451
1404 11:46:57.012470 CA PerBit enable=1, Macro0, CA PI delay=34
1405 11:46:57.012567
1406 11:46:57.016164 [CBTSetCACLKResult] CA Dly = 34
1407 11:46:57.016249 CS Dly: 6 (0~37)
1408 11:46:57.019248 ==
1409 11:46:57.019332 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 11:46:57.025598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 11:46:57.025686 ==
1412 11:46:57.029343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 11:46:57.035831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 11:46:57.045775 [CA 0] Center 36 (6~67) winsize 62
1415 11:46:57.050359 [CA 1] Center 37 (6~68) winsize 63
1416 11:46:57.053918 [CA 2] Center 35 (5~66) winsize 62
1417 11:46:57.057895 [CA 3] Center 34 (4~65) winsize 62
1418 11:46:57.057984 [CA 4] Center 35 (5~66) winsize 62
1419 11:46:57.061661 [CA 5] Center 34 (4~65) winsize 62
1420 11:46:57.061744
1421 11:46:57.065543 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 11:46:57.065631
1423 11:46:57.068886 [CATrainingPosCal] consider 2 rank data
1424 11:46:57.072760 u2DelayCellTimex100 = 270/100 ps
1425 11:46:57.076850 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 11:46:57.080276 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 11:46:57.083506 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 11:46:57.086687 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 11:46:57.090096 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 11:46:57.093235 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 11:46:57.093327
1432 11:46:57.099899 CA PerBit enable=1, Macro0, CA PI delay=34
1433 11:46:57.099996
1434 11:46:57.103230 [CBTSetCACLKResult] CA Dly = 34
1435 11:46:57.103303 CS Dly: 6 (0~38)
1436 11:46:57.103367
1437 11:46:57.106600 ----->DramcWriteLeveling(PI) begin...
1438 11:46:57.106686 ==
1439 11:46:57.110183 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:46:57.113520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:46:57.113612 ==
1442 11:46:57.117143 Write leveling (Byte 0): 29 => 29
1443 11:46:57.120232 Write leveling (Byte 1): 29 => 29
1444 11:46:57.123297 DramcWriteLeveling(PI) end<-----
1445 11:46:57.123380
1446 11:46:57.123452 ==
1447 11:46:57.126430 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 11:46:57.133501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 11:46:57.133587 ==
1450 11:46:57.133654 [Gating] SW mode calibration
1451 11:46:57.142998 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 11:46:57.146243 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 11:46:57.150194 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 11:46:57.156931 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:46:57.160218 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:46:57.163482 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:46:57.169770 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:46:57.172965 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:46:57.176809 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:46:57.183465 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:46:57.186658 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:46:57.190266 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:46:57.196247 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:46:57.199460 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:46:57.202876 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:46:57.209606 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:46:57.213390 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:46:57.216104 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:46:57.223059 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:46:57.226138 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1471 11:46:57.229440 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1472 11:46:57.236480 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:46:57.239733 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:46:57.242964 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:46:57.246123 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:46:57.253231 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:46:57.256458 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:46:57.259804 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1479 11:46:57.266522 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1480 11:46:57.269690 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:46:57.273014 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:46:57.279765 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:46:57.282897 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:46:57.286276 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:46:57.292710 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 11:46:57.296224 0 10 4 | B1->B0 | 3030 2e2e | 1 0 | (1 0) (0 0)
1487 11:46:57.299509 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1488 11:46:57.306189 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:46:57.309462 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:46:57.312710 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:46:57.319787 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:46:57.323204 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:46:57.326496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:46:57.330153 0 11 4 | B1->B0 | 2929 3232 | 0 0 | (1 1) (0 0)
1495 11:46:57.336371 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1496 11:46:57.340260 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:46:57.343523 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:46:57.349844 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:46:57.353543 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:46:57.356718 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:46:57.363475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:46:57.366746 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 11:46:57.370088 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:46:57.376906 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:46:57.380193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:46:57.383361 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:46:57.390187 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:46:57.393344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:46:57.396580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:46:57.400607 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:46:57.407191 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:46:57.409934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:46:57.413943 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:46:57.420431 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:46:57.423659 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:46:57.426994 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:46:57.433579 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:46:57.437305 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 11:46:57.440260 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 11:46:57.443389 Total UI for P1: 0, mck2ui 16
1521 11:46:57.447066 best dqsien dly found for B0: ( 0, 14, 4)
1522 11:46:57.450347 Total UI for P1: 0, mck2ui 16
1523 11:46:57.453485 best dqsien dly found for B1: ( 0, 14, 4)
1524 11:46:57.457132 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 11:46:57.460592 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1526 11:46:57.460675
1527 11:46:57.463653 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 11:46:57.470066 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1529 11:46:57.470149 [Gating] SW calibration Done
1530 11:46:57.470215 ==
1531 11:46:57.473511 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 11:46:57.480237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 11:46:57.480320 ==
1534 11:46:57.480385 RX Vref Scan: 0
1535 11:46:57.480445
1536 11:46:57.483505 RX Vref 0 -> 0, step: 1
1537 11:46:57.483588
1538 11:46:57.486897 RX Delay -130 -> 252, step: 16
1539 11:46:57.490140 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 11:46:57.493879 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 11:46:57.496898 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1542 11:46:57.503928 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 11:46:57.507400 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 11:46:57.510654 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 11:46:57.514008 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1546 11:46:57.517380 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 11:46:57.520507 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 11:46:57.526878 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 11:46:57.530213 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 11:46:57.533489 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 11:46:57.536884 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 11:46:57.543596 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1553 11:46:57.547337 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 11:46:57.550343 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1555 11:46:57.550426 ==
1556 11:46:57.553495 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 11:46:57.556704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 11:46:57.556817 ==
1559 11:46:57.560556 DQS Delay:
1560 11:46:57.560640 DQS0 = 0, DQS1 = 0
1561 11:46:57.560705 DQM Delay:
1562 11:46:57.563720 DQM0 = 92, DQM1 = 87
1563 11:46:57.563803 DQ Delay:
1564 11:46:57.567064 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1565 11:46:57.570206 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1566 11:46:57.574200 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1567 11:46:57.577372 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1568 11:46:57.577454
1569 11:46:57.577518
1570 11:46:57.577578 ==
1571 11:46:57.580153 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 11:46:57.586908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 11:46:57.586991 ==
1574 11:46:57.587057
1575 11:46:57.587117
1576 11:46:57.587175 TX Vref Scan disable
1577 11:46:57.590907 == TX Byte 0 ==
1578 11:46:57.594308 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1579 11:46:57.597393 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1580 11:46:57.600683 == TX Byte 1 ==
1581 11:46:57.603905 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1582 11:46:57.607792 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1583 11:46:57.611157 ==
1584 11:46:57.614318 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 11:46:57.617752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 11:46:57.617834 ==
1587 11:46:57.629557 TX Vref=22, minBit 3, minWin=26, winSum=436
1588 11:46:57.633550 TX Vref=24, minBit 1, minWin=27, winSum=444
1589 11:46:57.636809 TX Vref=26, minBit 2, minWin=27, winSum=447
1590 11:46:57.639595 TX Vref=28, minBit 1, minWin=27, winSum=446
1591 11:46:57.643477 TX Vref=30, minBit 1, minWin=27, winSum=448
1592 11:46:57.646817 TX Vref=32, minBit 0, minWin=27, winSum=448
1593 11:46:57.653317 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30
1594 11:46:57.653401
1595 11:46:57.657208 Final TX Range 1 Vref 30
1596 11:46:57.657291
1597 11:46:57.657356 ==
1598 11:46:57.660135 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 11:46:57.663645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 11:46:57.663729 ==
1601 11:46:57.663795
1602 11:46:57.663854
1603 11:46:57.666799 TX Vref Scan disable
1604 11:46:57.669836 == TX Byte 0 ==
1605 11:46:57.673361 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 11:46:57.677439 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 11:46:57.680625 == TX Byte 1 ==
1608 11:46:57.683589 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 11:46:57.687427 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 11:46:57.687990
1611 11:46:57.690281 [DATLAT]
1612 11:46:57.690810 Freq=800, CH1 RK0
1613 11:46:57.691316
1614 11:46:57.693639 DATLAT Default: 0xa
1615 11:46:57.694102 0, 0xFFFF, sum = 0
1616 11:46:57.697554 1, 0xFFFF, sum = 0
1617 11:46:57.698126 2, 0xFFFF, sum = 0
1618 11:46:57.700162 3, 0xFFFF, sum = 0
1619 11:46:57.700676 4, 0xFFFF, sum = 0
1620 11:46:57.704085 5, 0xFFFF, sum = 0
1621 11:46:57.704618 6, 0xFFFF, sum = 0
1622 11:46:57.707191 7, 0xFFFF, sum = 0
1623 11:46:57.707789 8, 0xFFFF, sum = 0
1624 11:46:57.710314 9, 0x0, sum = 1
1625 11:46:57.710910 10, 0x0, sum = 2
1626 11:46:57.713423 11, 0x0, sum = 3
1627 11:46:57.714023 12, 0x0, sum = 4
1628 11:46:57.717308 best_step = 10
1629 11:46:57.717768
1630 11:46:57.718144 ==
1631 11:46:57.720703 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 11:46:57.723818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 11:46:57.724373 ==
1634 11:46:57.727275 RX Vref Scan: 1
1635 11:46:57.727872
1636 11:46:57.728419 Set Vref Range= 32 -> 127
1637 11:46:57.728896
1638 11:46:57.730622 RX Vref 32 -> 127, step: 1
1639 11:46:57.731041
1640 11:46:57.734052 RX Delay -79 -> 252, step: 8
1641 11:46:57.734471
1642 11:46:57.737113 Set Vref, RX VrefLevel [Byte0]: 32
1643 11:46:57.740686 [Byte1]: 32
1644 11:46:57.741159
1645 11:46:57.744189 Set Vref, RX VrefLevel [Byte0]: 33
1646 11:46:57.747326 [Byte1]: 33
1647 11:46:57.747748
1648 11:46:57.750685 Set Vref, RX VrefLevel [Byte0]: 34
1649 11:46:57.754057 [Byte1]: 34
1650 11:46:57.757457
1651 11:46:57.757875 Set Vref, RX VrefLevel [Byte0]: 35
1652 11:46:57.760800 [Byte1]: 35
1653 11:46:57.765283
1654 11:46:57.765845 Set Vref, RX VrefLevel [Byte0]: 36
1655 11:46:57.768584 [Byte1]: 36
1656 11:46:57.772982
1657 11:46:57.773403 Set Vref, RX VrefLevel [Byte0]: 37
1658 11:46:57.776085 [Byte1]: 37
1659 11:46:57.780583
1660 11:46:57.781045 Set Vref, RX VrefLevel [Byte0]: 38
1661 11:46:57.783638 [Byte1]: 38
1662 11:46:57.787625
1663 11:46:57.788044 Set Vref, RX VrefLevel [Byte0]: 39
1664 11:46:57.791543 [Byte1]: 39
1665 11:46:57.795385
1666 11:46:57.795800 Set Vref, RX VrefLevel [Byte0]: 40
1667 11:46:57.798636 [Byte1]: 40
1668 11:46:57.803398
1669 11:46:57.803912 Set Vref, RX VrefLevel [Byte0]: 41
1670 11:46:57.806479 [Byte1]: 41
1671 11:46:57.810863
1672 11:46:57.811381 Set Vref, RX VrefLevel [Byte0]: 42
1673 11:46:57.813849 [Byte1]: 42
1674 11:46:57.818286
1675 11:46:57.818740 Set Vref, RX VrefLevel [Byte0]: 43
1676 11:46:57.821343 [Byte1]: 43
1677 11:46:57.825790
1678 11:46:57.826212 Set Vref, RX VrefLevel [Byte0]: 44
1679 11:46:57.829275 [Byte1]: 44
1680 11:46:57.833340
1681 11:46:57.833756 Set Vref, RX VrefLevel [Byte0]: 45
1682 11:46:57.836645 [Byte1]: 45
1683 11:46:57.840532
1684 11:46:57.841010 Set Vref, RX VrefLevel [Byte0]: 46
1685 11:46:57.843856 [Byte1]: 46
1686 11:46:57.848163
1687 11:46:57.848581 Set Vref, RX VrefLevel [Byte0]: 47
1688 11:46:57.851830 [Byte1]: 47
1689 11:46:57.856019
1690 11:46:57.856541 Set Vref, RX VrefLevel [Byte0]: 48
1691 11:46:57.858854 [Byte1]: 48
1692 11:46:57.863758
1693 11:46:57.864179 Set Vref, RX VrefLevel [Byte0]: 49
1694 11:46:57.866908 [Byte1]: 49
1695 11:46:57.870759
1696 11:46:57.871175 Set Vref, RX VrefLevel [Byte0]: 50
1697 11:46:57.873998 [Byte1]: 50
1698 11:46:57.878512
1699 11:46:57.881698 Set Vref, RX VrefLevel [Byte0]: 51
1700 11:46:57.882130 [Byte1]: 51
1701 11:46:57.885912
1702 11:46:57.886408 Set Vref, RX VrefLevel [Byte0]: 52
1703 11:46:57.889338 [Byte1]: 52
1704 11:46:57.893629
1705 11:46:57.894067 Set Vref, RX VrefLevel [Byte0]: 53
1706 11:46:57.896918 [Byte1]: 53
1707 11:46:57.901391
1708 11:46:57.901947 Set Vref, RX VrefLevel [Byte0]: 54
1709 11:46:57.904599 [Byte1]: 54
1710 11:46:57.908589
1711 11:46:57.909046 Set Vref, RX VrefLevel [Byte0]: 55
1712 11:46:57.911929 [Byte1]: 55
1713 11:46:57.916749
1714 11:46:57.917215 Set Vref, RX VrefLevel [Byte0]: 56
1715 11:46:57.919909 [Byte1]: 56
1716 11:46:57.923458
1717 11:46:57.923881 Set Vref, RX VrefLevel [Byte0]: 57
1718 11:46:57.926787 [Byte1]: 57
1719 11:46:57.931011
1720 11:46:57.931432 Set Vref, RX VrefLevel [Byte0]: 58
1721 11:46:57.934543 [Byte1]: 58
1722 11:46:57.939185
1723 11:46:57.939632 Set Vref, RX VrefLevel [Byte0]: 59
1724 11:46:57.942399 [Byte1]: 59
1725 11:46:57.946269
1726 11:46:57.946781 Set Vref, RX VrefLevel [Byte0]: 60
1727 11:46:57.949663 [Byte1]: 60
1728 11:46:57.954338
1729 11:46:57.954758 Set Vref, RX VrefLevel [Byte0]: 61
1730 11:46:57.956921 [Byte1]: 61
1731 11:46:57.961708
1732 11:46:57.962126 Set Vref, RX VrefLevel [Byte0]: 62
1733 11:46:57.964965 [Byte1]: 62
1734 11:46:57.968799
1735 11:46:57.969270 Set Vref, RX VrefLevel [Byte0]: 63
1736 11:46:57.972216 [Byte1]: 63
1737 11:46:57.976918
1738 11:46:57.977338 Set Vref, RX VrefLevel [Byte0]: 64
1739 11:46:57.979658 [Byte1]: 64
1740 11:46:57.984138
1741 11:46:57.984556 Set Vref, RX VrefLevel [Byte0]: 65
1742 11:46:57.987324 [Byte1]: 65
1743 11:46:57.991717
1744 11:46:57.992155 Set Vref, RX VrefLevel [Byte0]: 66
1745 11:46:57.994763 [Byte1]: 66
1746 11:46:57.999187
1747 11:46:57.999603 Set Vref, RX VrefLevel [Byte0]: 67
1748 11:46:58.002477 [Byte1]: 67
1749 11:46:58.006983
1750 11:46:58.007400 Set Vref, RX VrefLevel [Byte0]: 68
1751 11:46:58.010088 [Byte1]: 68
1752 11:46:58.014548
1753 11:46:58.015140 Set Vref, RX VrefLevel [Byte0]: 69
1754 11:46:58.017589 [Byte1]: 69
1755 11:46:58.022096
1756 11:46:58.022515 Set Vref, RX VrefLevel [Byte0]: 70
1757 11:46:58.025338 [Byte1]: 70
1758 11:46:58.029122
1759 11:46:58.029542 Set Vref, RX VrefLevel [Byte0]: 71
1760 11:46:58.032923 [Byte1]: 71
1761 11:46:58.036831
1762 11:46:58.037272 Set Vref, RX VrefLevel [Byte0]: 72
1763 11:46:58.040473 [Byte1]: 72
1764 11:46:58.044277
1765 11:46:58.044701 Final RX Vref Byte 0 = 55 to rank0
1766 11:46:58.047599 Final RX Vref Byte 1 = 55 to rank0
1767 11:46:58.050847 Final RX Vref Byte 0 = 55 to rank1
1768 11:46:58.054785 Final RX Vref Byte 1 = 55 to rank1==
1769 11:46:58.058070 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 11:46:58.061343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 11:46:58.064781 ==
1772 11:46:58.065244 DQS Delay:
1773 11:46:58.065583 DQS0 = 0, DQS1 = 0
1774 11:46:58.068097 DQM Delay:
1775 11:46:58.068517 DQM0 = 95, DQM1 = 90
1776 11:46:58.071598 DQ Delay:
1777 11:46:58.074449 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1778 11:46:58.074936 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1779 11:46:58.078328 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1780 11:46:58.084844 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1781 11:46:58.085273
1782 11:46:58.085606
1783 11:46:58.091160 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1784 11:46:58.094341 CH1 RK0: MR19=606, MR18=2F4B
1785 11:46:58.101328 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1786 11:46:58.101755
1787 11:46:58.104476 ----->DramcWriteLeveling(PI) begin...
1788 11:46:58.104939 ==
1789 11:46:58.108220 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 11:46:58.111463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 11:46:58.111914 ==
1792 11:46:58.114759 Write leveling (Byte 0): 29 => 29
1793 11:46:58.118045 Write leveling (Byte 1): 29 => 29
1794 11:46:58.121247 DramcWriteLeveling(PI) end<-----
1795 11:46:58.121671
1796 11:46:58.122007 ==
1797 11:46:58.124468 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 11:46:58.127871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 11:46:58.128295 ==
1800 11:46:58.131007 [Gating] SW mode calibration
1801 11:46:58.137935 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 11:46:58.144988 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 11:46:58.148235 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 11:46:58.151362 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1805 11:46:58.158166 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1806 11:46:58.161352 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:46:58.164676 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:46:58.171310 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:46:58.174587 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:46:58.178652 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:46:58.181858 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:46:58.187910 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:46:58.191856 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:46:58.195123 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:46:58.201553 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:46:58.204706 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:46:58.208726 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:46:58.214908 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:46:58.218242 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:46:58.221386 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 11:46:58.228524 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1822 11:46:58.231289 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:46:58.235245 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:46:58.241734 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:46:58.244908 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:46:58.248492 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:46:58.255023 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:46:58.258280 0 9 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1829 11:46:58.261374 0 9 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
1830 11:46:58.268508 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 11:46:58.271725 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 11:46:58.274996 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:46:58.278140 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 11:46:58.284904 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 11:46:58.288275 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 11:46:58.291433 0 10 4 | B1->B0 | 2929 2f2f | 0 0 | (1 1) (1 0)
1837 11:46:58.298244 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1838 11:46:58.301530 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:46:58.305111 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:46:58.314472 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:46:58.314934 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:46:58.318514 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:46:58.324752 0 11 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1844 11:46:58.327892 0 11 4 | B1->B0 | 3737 2e2e | 0 0 | (1 1) (0 0)
1845 11:46:58.331250 0 11 8 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
1846 11:46:58.338270 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 11:46:58.341181 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 11:46:58.344376 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 11:46:58.351375 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 11:46:58.354390 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 11:46:58.358293 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 11:46:58.364769 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1853 11:46:58.368051 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:46:58.371179 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:46:58.374360 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:46:58.380859 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:46:58.384097 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:46:58.387427 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:46:58.394551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:46:58.398130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:46:58.401362 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:46:58.407782 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:46:58.411195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:46:58.414928 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:46:58.421123 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:46:58.424736 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:46:58.428131 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:46:58.434457 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1869 11:46:58.438435 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 11:46:58.441742 Total UI for P1: 0, mck2ui 16
1871 11:46:58.444919 best dqsien dly found for B0: ( 0, 14, 4)
1872 11:46:58.448230 Total UI for P1: 0, mck2ui 16
1873 11:46:58.451493 best dqsien dly found for B1: ( 0, 14, 4)
1874 11:46:58.454837 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1875 11:46:58.457954 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1876 11:46:58.458177
1877 11:46:58.461704 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 11:46:58.464959 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 11:46:58.468222 [Gating] SW calibration Done
1880 11:46:58.468516 ==
1881 11:46:58.471468 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 11:46:58.475244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 11:46:58.475578 ==
1884 11:46:58.478255 RX Vref Scan: 0
1885 11:46:58.478556
1886 11:46:58.478795 RX Vref 0 -> 0, step: 1
1887 11:46:58.479018
1888 11:46:58.482157 RX Delay -130 -> 252, step: 16
1889 11:46:58.488228 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1890 11:46:58.491608 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1891 11:46:58.495517 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1892 11:46:58.498771 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1893 11:46:58.501538 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1894 11:46:58.505432 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1895 11:46:58.512253 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1896 11:46:58.515397 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1897 11:46:58.518681 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1898 11:46:58.521982 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1899 11:46:58.524970 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1900 11:46:58.531889 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1901 11:46:58.535539 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1902 11:46:58.538933 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1903 11:46:58.542303 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1904 11:46:58.545231 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1905 11:46:58.548642 ==
1906 11:46:58.552010 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 11:46:58.555301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1908 11:46:58.555730 ==
1909 11:46:58.556233 DQS Delay:
1910 11:46:58.558852 DQS0 = 0, DQS1 = 0
1911 11:46:58.559299 DQM Delay:
1912 11:46:58.562046 DQM0 = 92, DQM1 = 88
1913 11:46:58.562480 DQ Delay:
1914 11:46:58.565395 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1915 11:46:58.568664 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1916 11:46:58.572302 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1917 11:46:58.575461 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1918 11:46:58.575891
1919 11:46:58.576229
1920 11:46:58.576543 ==
1921 11:46:58.578733 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 11:46:58.581851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 11:46:58.582300 ==
1924 11:46:58.582641
1925 11:46:58.582956
1926 11:46:58.585569 TX Vref Scan disable
1927 11:46:58.588624 == TX Byte 0 ==
1928 11:46:58.592055 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1929 11:46:58.595121 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1930 11:46:58.598702 == TX Byte 1 ==
1931 11:46:58.602312 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1932 11:46:58.605684 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1933 11:46:58.606112 ==
1934 11:46:58.608910 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 11:46:58.612234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 11:46:58.615476 ==
1937 11:46:58.626962 TX Vref=22, minBit 2, minWin=27, winSum=447
1938 11:46:58.630157 TX Vref=24, minBit 1, minWin=27, winSum=447
1939 11:46:58.633029 TX Vref=26, minBit 2, minWin=27, winSum=448
1940 11:46:58.636179 TX Vref=28, minBit 2, minWin=27, winSum=449
1941 11:46:58.639466 TX Vref=30, minBit 2, minWin=27, winSum=452
1942 11:46:58.643180 TX Vref=32, minBit 0, minWin=27, winSum=448
1943 11:46:58.649792 [TxChooseVref] Worse bit 2, Min win 27, Win sum 452, Final Vref 30
1944 11:46:58.650224
1945 11:46:58.653434 Final TX Range 1 Vref 30
1946 11:46:58.653864
1947 11:46:58.654199 ==
1948 11:46:58.656906 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 11:46:58.660079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 11:46:58.660509 ==
1951 11:46:58.660908
1952 11:46:58.663455
1953 11:46:58.663988 TX Vref Scan disable
1954 11:46:58.666889 == TX Byte 0 ==
1955 11:46:58.669637 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1956 11:46:58.673465 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1957 11:46:58.676742 == TX Byte 1 ==
1958 11:46:58.679760 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1959 11:46:58.683073 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1960 11:46:58.686230
1961 11:46:58.686652 [DATLAT]
1962 11:46:58.686989 Freq=800, CH1 RK1
1963 11:46:58.687309
1964 11:46:58.689656 DATLAT Default: 0xa
1965 11:46:58.690081 0, 0xFFFF, sum = 0
1966 11:46:58.693449 1, 0xFFFF, sum = 0
1967 11:46:58.694026 2, 0xFFFF, sum = 0
1968 11:46:58.696585 3, 0xFFFF, sum = 0
1969 11:46:58.697071 4, 0xFFFF, sum = 0
1970 11:46:58.699855 5, 0xFFFF, sum = 0
1971 11:46:58.703329 6, 0xFFFF, sum = 0
1972 11:46:58.703777 7, 0xFFFF, sum = 0
1973 11:46:58.706405 8, 0xFFFF, sum = 0
1974 11:46:58.706839 9, 0x0, sum = 1
1975 11:46:58.707185 10, 0x0, sum = 2
1976 11:46:58.709743 11, 0x0, sum = 3
1977 11:46:58.710176 12, 0x0, sum = 4
1978 11:46:58.713094 best_step = 10
1979 11:46:58.713519
1980 11:46:58.713853 ==
1981 11:46:58.716475 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 11:46:58.719930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 11:46:58.720357 ==
1984 11:46:58.723193 RX Vref Scan: 0
1985 11:46:58.723661
1986 11:46:58.723998 RX Vref 0 -> 0, step: 1
1987 11:46:58.724315
1988 11:46:58.726487 RX Delay -79 -> 252, step: 8
1989 11:46:58.733070 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1990 11:46:58.736471 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1991 11:46:58.739532 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1992 11:46:58.743559 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1993 11:46:58.746462 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1994 11:46:58.750032 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1995 11:46:58.756541 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1996 11:46:58.759701 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1997 11:46:58.763388 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1998 11:46:58.766552 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1999 11:46:58.769928 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2000 11:46:58.776537 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2001 11:46:58.779697 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2002 11:46:58.783779 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2003 11:46:58.786749 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2004 11:46:58.790442 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2005 11:46:58.790926 ==
2006 11:46:58.793587 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 11:46:58.800084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 11:46:58.800525 ==
2009 11:46:58.800904 DQS Delay:
2010 11:46:58.803139 DQS0 = 0, DQS1 = 0
2011 11:46:58.803559 DQM Delay:
2012 11:46:58.803892 DQM0 = 97, DQM1 = 91
2013 11:46:58.806993 DQ Delay:
2014 11:46:58.810307 DQ0 =104, DQ1 =88, DQ2 =84, DQ3 =92
2015 11:46:58.813681 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2016 11:46:58.816957 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2017 11:46:58.820239 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2018 11:46:58.820661
2019 11:46:58.821027
2020 11:46:58.826854 [DQSOSCAuto] RK1, (LSB)MR18= 0x4711, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2021 11:46:58.830182 CH1 RK1: MR19=606, MR18=4711
2022 11:46:58.836998 CH1_RK1: MR19=0x606, MR18=0x4711, DQSOSC=392, MR23=63, INC=96, DEC=64
2023 11:46:58.840297 [RxdqsGatingPostProcess] freq 800
2024 11:46:58.843502 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 11:46:58.846849 Pre-setting of DQS Precalculation
2026 11:46:58.853614 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2027 11:46:58.859775 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 11:46:58.866806 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 11:46:58.867342
2030 11:46:58.867736
2031 11:46:58.870086 [Calibration Summary] 1600 Mbps
2032 11:46:58.873416 CH 0, Rank 0
2033 11:46:58.873865 SW Impedance : PASS
2034 11:46:58.876753 DUTY Scan : NO K
2035 11:46:58.877226 ZQ Calibration : PASS
2036 11:46:58.880452 Jitter Meter : NO K
2037 11:46:58.883556 CBT Training : PASS
2038 11:46:58.883970 Write leveling : PASS
2039 11:46:58.887016 RX DQS gating : PASS
2040 11:46:58.890398 RX DQ/DQS(RDDQC) : PASS
2041 11:46:58.890819 TX DQ/DQS : PASS
2042 11:46:58.893506 RX DATLAT : PASS
2043 11:46:58.896674 RX DQ/DQS(Engine): PASS
2044 11:46:58.897147 TX OE : NO K
2045 11:46:58.899961 All Pass.
2046 11:46:58.900375
2047 11:46:58.900701 CH 0, Rank 1
2048 11:46:58.903313 SW Impedance : PASS
2049 11:46:58.903730 DUTY Scan : NO K
2050 11:46:58.906599 ZQ Calibration : PASS
2051 11:46:58.909870 Jitter Meter : NO K
2052 11:46:58.910286 CBT Training : PASS
2053 11:46:58.913500 Write leveling : PASS
2054 11:46:58.913921 RX DQS gating : PASS
2055 11:46:58.916797 RX DQ/DQS(RDDQC) : PASS
2056 11:46:58.919883 TX DQ/DQS : PASS
2057 11:46:58.920301 RX DATLAT : PASS
2058 11:46:58.923337 RX DQ/DQS(Engine): PASS
2059 11:46:58.926667 TX OE : NO K
2060 11:46:58.927087 All Pass.
2061 11:46:58.927414
2062 11:46:58.927725 CH 1, Rank 0
2063 11:46:58.930036 SW Impedance : PASS
2064 11:46:58.933303 DUTY Scan : NO K
2065 11:46:58.933722 ZQ Calibration : PASS
2066 11:46:58.936681 Jitter Meter : NO K
2067 11:46:58.940075 CBT Training : PASS
2068 11:46:58.940492 Write leveling : PASS
2069 11:46:58.943367 RX DQS gating : PASS
2070 11:46:58.946504 RX DQ/DQS(RDDQC) : PASS
2071 11:46:58.946921 TX DQ/DQS : PASS
2072 11:46:58.949723 RX DATLAT : PASS
2073 11:46:58.953248 RX DQ/DQS(Engine): PASS
2074 11:46:58.953668 TX OE : NO K
2075 11:46:58.954002 All Pass.
2076 11:46:58.956575
2077 11:46:58.957043 CH 1, Rank 1
2078 11:46:58.960141 SW Impedance : PASS
2079 11:46:58.960558 DUTY Scan : NO K
2080 11:46:58.963196 ZQ Calibration : PASS
2081 11:46:58.963622 Jitter Meter : NO K
2082 11:46:58.966909 CBT Training : PASS
2083 11:46:58.970036 Write leveling : PASS
2084 11:46:58.970460 RX DQS gating : PASS
2085 11:46:58.973892 RX DQ/DQS(RDDQC) : PASS
2086 11:46:58.976457 TX DQ/DQS : PASS
2087 11:46:58.976927 RX DATLAT : PASS
2088 11:46:58.980582 RX DQ/DQS(Engine): PASS
2089 11:46:58.983474 TX OE : NO K
2090 11:46:58.983902 All Pass.
2091 11:46:58.984237
2092 11:46:58.984551 DramC Write-DBI off
2093 11:46:58.986856 PER_BANK_REFRESH: Hybrid Mode
2094 11:46:58.990543 TX_TRACKING: ON
2095 11:46:58.993817 [GetDramInforAfterCalByMRR] Vendor 6.
2096 11:46:58.996547 [GetDramInforAfterCalByMRR] Revision 606.
2097 11:46:59.000375 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 11:46:59.000835 MR0 0x3b3b
2099 11:46:59.003507 MR8 0x5151
2100 11:46:59.006709 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 11:46:59.007132
2102 11:46:59.007465 MR0 0x3b3b
2103 11:46:59.007797 MR8 0x5151
2104 11:46:59.009705 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 11:46:59.013019
2106 11:46:59.020261 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 11:46:59.023082 [FAST_K] Save calibration result to emmc
2108 11:46:59.026301 [FAST_K] Save calibration result to emmc
2109 11:46:59.030243 dram_init: config_dvfs: 1
2110 11:46:59.032912 dramc_set_vcore_voltage set vcore to 662500
2111 11:46:59.037030 Read voltage for 1200, 2
2112 11:46:59.037112 Vio18 = 0
2113 11:46:59.040215 Vcore = 662500
2114 11:46:59.040296 Vdram = 0
2115 11:46:59.040361 Vddq = 0
2116 11:46:59.040419 Vmddr = 0
2117 11:46:59.046864 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 11:46:59.050283 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 11:46:59.053370 MEM_TYPE=3, freq_sel=15
2120 11:46:59.056692 sv_algorithm_assistance_LP4_1600
2121 11:46:59.060051 ============ PULL DRAM RESETB DOWN ============
2122 11:46:59.066492 ========== PULL DRAM RESETB DOWN end =========
2123 11:46:59.070609 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 11:46:59.073576 ===================================
2125 11:46:59.077144 LPDDR4 DRAM CONFIGURATION
2126 11:46:59.080459 ===================================
2127 11:46:59.080942 EX_ROW_EN[0] = 0x0
2128 11:46:59.083573 EX_ROW_EN[1] = 0x0
2129 11:46:59.084071 LP4Y_EN = 0x0
2130 11:46:59.087612 WORK_FSP = 0x0
2131 11:46:59.088034 WL = 0x4
2132 11:46:59.090646 RL = 0x4
2133 11:46:59.091063 BL = 0x2
2134 11:46:59.093961 RPST = 0x0
2135 11:46:59.094389 RD_PRE = 0x0
2136 11:46:59.097012 WR_PRE = 0x1
2137 11:46:59.097436 WR_PST = 0x0
2138 11:46:59.100141 DBI_WR = 0x0
2139 11:46:59.100568 DBI_RD = 0x0
2140 11:46:59.104139 OTF = 0x1
2141 11:46:59.107457 ===================================
2142 11:46:59.110694 ===================================
2143 11:46:59.111143 ANA top config
2144 11:46:59.114498 ===================================
2145 11:46:59.117431 DLL_ASYNC_EN = 0
2146 11:46:59.120575 ALL_SLAVE_EN = 0
2147 11:46:59.124047 NEW_RANK_MODE = 1
2148 11:46:59.124571 DLL_IDLE_MODE = 1
2149 11:46:59.127197 LP45_APHY_COMB_EN = 1
2150 11:46:59.131193 TX_ODT_DIS = 1
2151 11:46:59.133876 NEW_8X_MODE = 1
2152 11:46:59.137132 ===================================
2153 11:46:59.140507 ===================================
2154 11:46:59.143697 data_rate = 2400
2155 11:46:59.144117 CKR = 1
2156 11:46:59.147725 DQ_P2S_RATIO = 8
2157 11:46:59.150902 ===================================
2158 11:46:59.154309 CA_P2S_RATIO = 8
2159 11:46:59.157425 DQ_CA_OPEN = 0
2160 11:46:59.160856 DQ_SEMI_OPEN = 0
2161 11:46:59.164262 CA_SEMI_OPEN = 0
2162 11:46:59.164927 CA_FULL_RATE = 0
2163 11:46:59.167753 DQ_CKDIV4_EN = 0
2164 11:46:59.170267 CA_CKDIV4_EN = 0
2165 11:46:59.174012 CA_PREDIV_EN = 0
2166 11:46:59.177194 PH8_DLY = 17
2167 11:46:59.177617 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 11:46:59.180278 DQ_AAMCK_DIV = 4
2169 11:46:59.183853 CA_AAMCK_DIV = 4
2170 11:46:59.187028 CA_ADMCK_DIV = 4
2171 11:46:59.190657 DQ_TRACK_CA_EN = 0
2172 11:46:59.193856 CA_PICK = 1200
2173 11:46:59.197139 CA_MCKIO = 1200
2174 11:46:59.197559 MCKIO_SEMI = 0
2175 11:46:59.200227 PLL_FREQ = 2366
2176 11:46:59.203622 DQ_UI_PI_RATIO = 32
2177 11:46:59.207431 CA_UI_PI_RATIO = 0
2178 11:46:59.210668 ===================================
2179 11:46:59.213683 ===================================
2180 11:46:59.216928 memory_type:LPDDR4
2181 11:46:59.217349 GP_NUM : 10
2182 11:46:59.221232 SRAM_EN : 1
2183 11:46:59.223591 MD32_EN : 0
2184 11:46:59.227021 ===================================
2185 11:46:59.227443 [ANA_INIT] >>>>>>>>>>>>>>
2186 11:46:59.230279 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 11:46:59.234223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 11:46:59.237446 ===================================
2189 11:46:59.240373 data_rate = 2400,PCW = 0X5b00
2190 11:46:59.243679 ===================================
2191 11:46:59.247678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 11:46:59.253786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 11:46:59.256886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 11:46:59.263446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 11:46:59.267592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 11:46:59.270154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 11:46:59.270693 [ANA_INIT] flow start
2198 11:46:59.273952 [ANA_INIT] PLL >>>>>>>>
2199 11:46:59.277444 [ANA_INIT] PLL <<<<<<<<
2200 11:46:59.277878 [ANA_INIT] MIDPI >>>>>>>>
2201 11:46:59.280690 [ANA_INIT] MIDPI <<<<<<<<
2202 11:46:59.283480 [ANA_INIT] DLL >>>>>>>>
2203 11:46:59.287387 [ANA_INIT] DLL <<<<<<<<
2204 11:46:59.287849 [ANA_INIT] flow end
2205 11:46:59.290664 ============ LP4 DIFF to SE enter ============
2206 11:46:59.297184 ============ LP4 DIFF to SE exit ============
2207 11:46:59.297640 [ANA_INIT] <<<<<<<<<<<<<
2208 11:46:59.300216 [Flow] Enable top DCM control >>>>>
2209 11:46:59.303931 [Flow] Enable top DCM control <<<<<
2210 11:46:59.307113 Enable DLL master slave shuffle
2211 11:46:59.313629 ==============================================================
2212 11:46:59.314215 Gating Mode config
2213 11:46:59.320552 ==============================================================
2214 11:46:59.323762 Config description:
2215 11:46:59.330340 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 11:46:59.337458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 11:46:59.344162 SELPH_MODE 0: By rank 1: By Phase
2218 11:46:59.347361 ==============================================================
2219 11:46:59.351014 GAT_TRACK_EN = 1
2220 11:46:59.354294 RX_GATING_MODE = 2
2221 11:46:59.357561 RX_GATING_TRACK_MODE = 2
2222 11:46:59.360980 SELPH_MODE = 1
2223 11:46:59.364303 PICG_EARLY_EN = 1
2224 11:46:59.367568 VALID_LAT_VALUE = 1
2225 11:46:59.374000 ==============================================================
2226 11:46:59.377356 Enter into Gating configuration >>>>
2227 11:46:59.380654 Exit from Gating configuration <<<<
2228 11:46:59.381144 Enter into DVFS_PRE_config >>>>>
2229 11:46:59.394516 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 11:46:59.397757 Exit from DVFS_PRE_config <<<<<
2231 11:46:59.400886 Enter into PICG configuration >>>>
2232 11:46:59.404580 Exit from PICG configuration <<<<
2233 11:46:59.405111 [RX_INPUT] configuration >>>>>
2234 11:46:59.407607 [RX_INPUT] configuration <<<<<
2235 11:46:59.414372 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 11:46:59.417615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 11:46:59.424043 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 11:46:59.430560 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 11:46:59.437429 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 11:46:59.444305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 11:46:59.447492 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 11:46:59.450705 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 11:46:59.453945 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 11:46:59.461020 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 11:46:59.463656 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 11:46:59.467180 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 11:46:59.470565 ===================================
2248 11:46:59.474393 LPDDR4 DRAM CONFIGURATION
2249 11:46:59.477720 ===================================
2250 11:46:59.480894 EX_ROW_EN[0] = 0x0
2251 11:46:59.481338 EX_ROW_EN[1] = 0x0
2252 11:46:59.484274 LP4Y_EN = 0x0
2253 11:46:59.484853 WORK_FSP = 0x0
2254 11:46:59.487836 WL = 0x4
2255 11:46:59.488163 RL = 0x4
2256 11:46:59.491058 BL = 0x2
2257 11:46:59.491411 RPST = 0x0
2258 11:46:59.494481 RD_PRE = 0x0
2259 11:46:59.494868 WR_PRE = 0x1
2260 11:46:59.497722 WR_PST = 0x0
2261 11:46:59.498071 DBI_WR = 0x0
2262 11:46:59.500963 DBI_RD = 0x0
2263 11:46:59.501269 OTF = 0x1
2264 11:46:59.504431 ===================================
2265 11:46:59.507526 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 11:46:59.514369 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 11:46:59.517695 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 11:46:59.520764 ===================================
2269 11:46:59.523945 LPDDR4 DRAM CONFIGURATION
2270 11:46:59.527894 ===================================
2271 11:46:59.528193 EX_ROW_EN[0] = 0x10
2272 11:46:59.531188 EX_ROW_EN[1] = 0x0
2273 11:46:59.531486 LP4Y_EN = 0x0
2274 11:46:59.534340 WORK_FSP = 0x0
2275 11:46:59.534654 WL = 0x4
2276 11:46:59.537629 RL = 0x4
2277 11:46:59.537927 BL = 0x2
2278 11:46:59.540766 RPST = 0x0
2279 11:46:59.544462 RD_PRE = 0x0
2280 11:46:59.544976 WR_PRE = 0x1
2281 11:46:59.547464 WR_PST = 0x0
2282 11:46:59.547829 DBI_WR = 0x0
2283 11:46:59.551356 DBI_RD = 0x0
2284 11:46:59.551667 OTF = 0x1
2285 11:46:59.554620 ===================================
2286 11:46:59.561255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 11:46:59.561566 ==
2288 11:46:59.564349 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 11:46:59.567684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 11:46:59.567997 ==
2291 11:46:59.571013 [Duty_Offset_Calibration]
2292 11:46:59.571332 B0:2 B1:1 CA:1
2293 11:46:59.574278
2294 11:46:59.574655 [DutyScan_Calibration_Flow] k_type=0
2295 11:46:59.585237
2296 11:46:59.585614 ==CLK 0==
2297 11:46:59.588568 Final CLK duty delay cell = 0
2298 11:46:59.591946 [0] MAX Duty = 5187%(X100), DQS PI = 24
2299 11:46:59.595487 [0] MIN Duty = 4875%(X100), DQS PI = 0
2300 11:46:59.595781 [0] AVG Duty = 5031%(X100)
2301 11:46:59.598695
2302 11:46:59.598986 CH0 CLK Duty spec in!! Max-Min= 312%
2303 11:46:59.605226 [DutyScan_Calibration_Flow] ====Done====
2304 11:46:59.605519
2305 11:46:59.608547 [DutyScan_Calibration_Flow] k_type=1
2306 11:46:59.624144
2307 11:46:59.624525 ==DQS 0 ==
2308 11:46:59.627377 Final DQS duty delay cell = -4
2309 11:46:59.630786 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2310 11:46:59.634040 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2311 11:46:59.637106 [-4] AVG Duty = 4953%(X100)
2312 11:46:59.637647
2313 11:46:59.638113 ==DQS 1 ==
2314 11:46:59.640285 Final DQS duty delay cell = 0
2315 11:46:59.643728 [0] MAX Duty = 5156%(X100), DQS PI = 0
2316 11:46:59.646943 [0] MIN Duty = 5031%(X100), DQS PI = 32
2317 11:46:59.650260 [0] AVG Duty = 5093%(X100)
2318 11:46:59.650671
2319 11:46:59.653982 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2320 11:46:59.654398
2321 11:46:59.657063 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2322 11:46:59.660505 [DutyScan_Calibration_Flow] ====Done====
2323 11:46:59.661065
2324 11:46:59.663735 [DutyScan_Calibration_Flow] k_type=3
2325 11:46:59.680729
2326 11:46:59.681328 ==DQM 0 ==
2327 11:46:59.683908 Final DQM duty delay cell = 0
2328 11:46:59.687279 [0] MAX Duty = 5156%(X100), DQS PI = 32
2329 11:46:59.690636 [0] MIN Duty = 4906%(X100), DQS PI = 52
2330 11:46:59.693980 [0] AVG Duty = 5031%(X100)
2331 11:46:59.694396
2332 11:46:59.694747 ==DQM 1 ==
2333 11:46:59.697123 Final DQM duty delay cell = 0
2334 11:46:59.700511 [0] MAX Duty = 5093%(X100), DQS PI = 0
2335 11:46:59.704570 [0] MIN Duty = 5031%(X100), DQS PI = 16
2336 11:46:59.705108 [0] AVG Duty = 5062%(X100)
2337 11:46:59.707836
2338 11:46:59.710557 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2339 11:46:59.710975
2340 11:46:59.713753 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2341 11:46:59.717229 [DutyScan_Calibration_Flow] ====Done====
2342 11:46:59.717788
2343 11:46:59.720489 [DutyScan_Calibration_Flow] k_type=2
2344 11:46:59.737046
2345 11:46:59.737669 ==DQ 0 ==
2346 11:46:59.740359 Final DQ duty delay cell = 0
2347 11:46:59.743588 [0] MAX Duty = 5062%(X100), DQS PI = 32
2348 11:46:59.747219 [0] MIN Duty = 4875%(X100), DQS PI = 62
2349 11:46:59.747914 [0] AVG Duty = 4968%(X100)
2350 11:46:59.750536
2351 11:46:59.751092 ==DQ 1 ==
2352 11:46:59.753826 Final DQ duty delay cell = 0
2353 11:46:59.756891 [0] MAX Duty = 5093%(X100), DQS PI = 10
2354 11:46:59.760180 [0] MIN Duty = 4938%(X100), DQS PI = 36
2355 11:46:59.760591 [0] AVG Duty = 5015%(X100)
2356 11:46:59.760950
2357 11:46:59.763808 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2358 11:46:59.766734
2359 11:46:59.770606 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2360 11:46:59.773687 [DutyScan_Calibration_Flow] ====Done====
2361 11:46:59.773976 ==
2362 11:46:59.776825 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 11:46:59.780102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 11:46:59.780377 ==
2365 11:46:59.783568 [Duty_Offset_Calibration]
2366 11:46:59.783811 B0:1 B1:0 CA:0
2367 11:46:59.784023
2368 11:46:59.786833 [DutyScan_Calibration_Flow] k_type=0
2369 11:46:59.796127
2370 11:46:59.796316 ==CLK 0==
2371 11:46:59.799450 Final CLK duty delay cell = -4
2372 11:46:59.802759 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2373 11:46:59.806368 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2374 11:46:59.809489 [-4] AVG Duty = 4969%(X100)
2375 11:46:59.809675
2376 11:46:59.812793 CH1 CLK Duty spec in!! Max-Min= 124%
2377 11:46:59.816140 [DutyScan_Calibration_Flow] ====Done====
2378 11:46:59.816357
2379 11:46:59.819537 [DutyScan_Calibration_Flow] k_type=1
2380 11:46:59.836079
2381 11:46:59.836422 ==DQS 0 ==
2382 11:46:59.839317 Final DQS duty delay cell = 0
2383 11:46:59.842603 [0] MAX Duty = 5094%(X100), DQS PI = 28
2384 11:46:59.846304 [0] MIN Duty = 4875%(X100), DQS PI = 0
2385 11:46:59.846647 [0] AVG Duty = 4984%(X100)
2386 11:46:59.849631
2387 11:46:59.849983 ==DQS 1 ==
2388 11:46:59.852768 Final DQS duty delay cell = 0
2389 11:46:59.855915 [0] MAX Duty = 5218%(X100), DQS PI = 18
2390 11:46:59.859361 [0] MIN Duty = 4969%(X100), DQS PI = 10
2391 11:46:59.859706 [0] AVG Duty = 5093%(X100)
2392 11:46:59.862647
2393 11:46:59.865948 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2394 11:46:59.866351
2395 11:46:59.869259 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2396 11:46:59.872870 [DutyScan_Calibration_Flow] ====Done====
2397 11:46:59.873205
2398 11:46:59.876083 [DutyScan_Calibration_Flow] k_type=3
2399 11:46:59.892388
2400 11:46:59.892984 ==DQM 0 ==
2401 11:46:59.895671 Final DQM duty delay cell = 0
2402 11:46:59.899089 [0] MAX Duty = 5156%(X100), DQS PI = 6
2403 11:46:59.902443 [0] MIN Duty = 5031%(X100), DQS PI = 0
2404 11:46:59.902905 [0] AVG Duty = 5093%(X100)
2405 11:46:59.903347
2406 11:46:59.905701 ==DQM 1 ==
2407 11:46:59.909217 Final DQM duty delay cell = 0
2408 11:46:59.912298 [0] MAX Duty = 5031%(X100), DQS PI = 16
2409 11:46:59.915710 [0] MIN Duty = 4907%(X100), DQS PI = 36
2410 11:46:59.916155 [0] AVG Duty = 4969%(X100)
2411 11:46:59.916552
2412 11:46:59.922393 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2413 11:46:59.922848
2414 11:46:59.925653 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2415 11:46:59.929029 [DutyScan_Calibration_Flow] ====Done====
2416 11:46:59.929521
2417 11:46:59.932319 [DutyScan_Calibration_Flow] k_type=2
2418 11:46:59.948180
2419 11:46:59.948566 ==DQ 0 ==
2420 11:46:59.951580 Final DQ duty delay cell = -4
2421 11:46:59.954772 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2422 11:46:59.958482 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2423 11:46:59.961771 [-4] AVG Duty = 4984%(X100)
2424 11:46:59.962315
2425 11:46:59.962785 ==DQ 1 ==
2426 11:46:59.965222 Final DQ duty delay cell = 0
2427 11:46:59.968395 [0] MAX Duty = 5125%(X100), DQS PI = 20
2428 11:46:59.971547 [0] MIN Duty = 4969%(X100), DQS PI = 12
2429 11:46:59.971971 [0] AVG Duty = 5047%(X100)
2430 11:46:59.974982
2431 11:46:59.978264 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2432 11:46:59.978738
2433 11:46:59.981934 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2434 11:46:59.985091 [DutyScan_Calibration_Flow] ====Done====
2435 11:46:59.988066 nWR fixed to 30
2436 11:46:59.988506 [ModeRegInit_LP4] CH0 RK0
2437 11:46:59.991833 [ModeRegInit_LP4] CH0 RK1
2438 11:46:59.994673 [ModeRegInit_LP4] CH1 RK0
2439 11:46:59.998294 [ModeRegInit_LP4] CH1 RK1
2440 11:46:59.998780 match AC timing 7
2441 11:47:00.001714 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 11:47:00.005128 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 11:47:00.011589 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 11:47:00.015004 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 11:47:00.021655 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 11:47:00.022012 ==
2447 11:47:00.024861 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 11:47:00.028298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 11:47:00.028545 ==
2450 11:47:00.034822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 11:47:00.038026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2452 11:47:00.048407 [CA 0] Center 39 (8~70) winsize 63
2453 11:47:00.051429 [CA 1] Center 39 (8~70) winsize 63
2454 11:47:00.055011 [CA 2] Center 35 (5~66) winsize 62
2455 11:47:00.058301 [CA 3] Center 34 (4~65) winsize 62
2456 11:47:00.061538 [CA 4] Center 33 (3~64) winsize 62
2457 11:47:00.065205 [CA 5] Center 32 (3~62) winsize 60
2458 11:47:00.065319
2459 11:47:00.068302 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2460 11:47:00.068424
2461 11:47:00.071467 [CATrainingPosCal] consider 1 rank data
2462 11:47:00.075327 u2DelayCellTimex100 = 270/100 ps
2463 11:47:00.078134 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 11:47:00.082008 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2465 11:47:00.088388 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2466 11:47:00.091579 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2467 11:47:00.095158 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2468 11:47:00.098503 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2469 11:47:00.098672
2470 11:47:00.101577 CA PerBit enable=1, Macro0, CA PI delay=32
2471 11:47:00.101816
2472 11:47:00.105208 [CBTSetCACLKResult] CA Dly = 32
2473 11:47:00.105411 CS Dly: 6 (0~37)
2474 11:47:00.105558 ==
2475 11:47:00.108359 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 11:47:00.115106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 11:47:00.115370 ==
2478 11:47:00.118447 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 11:47:00.125258 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2480 11:47:00.134641 [CA 0] Center 38 (8~69) winsize 62
2481 11:47:00.137776 [CA 1] Center 38 (8~69) winsize 62
2482 11:47:00.141255 [CA 2] Center 35 (4~66) winsize 63
2483 11:47:00.144490 [CA 3] Center 34 (4~65) winsize 62
2484 11:47:00.147921 [CA 4] Center 33 (3~64) winsize 62
2485 11:47:00.151102 [CA 5] Center 32 (3~62) winsize 60
2486 11:47:00.151642
2487 11:47:00.154446 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 11:47:00.154843
2489 11:47:00.157681 [CATrainingPosCal] consider 2 rank data
2490 11:47:00.160769 u2DelayCellTimex100 = 270/100 ps
2491 11:47:00.164479 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 11:47:00.167508 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2493 11:47:00.174605 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2494 11:47:00.177805 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2495 11:47:00.180919 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2496 11:47:00.184617 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2497 11:47:00.185096
2498 11:47:00.188070 CA PerBit enable=1, Macro0, CA PI delay=32
2499 11:47:00.188493
2500 11:47:00.191567 [CBTSetCACLKResult] CA Dly = 32
2501 11:47:00.191995 CS Dly: 6 (0~38)
2502 11:47:00.192332
2503 11:47:00.194646 ----->DramcWriteLeveling(PI) begin...
2504 11:47:00.197804 ==
2505 11:47:00.198418 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 11:47:00.204214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 11:47:00.204649 ==
2508 11:47:00.207478 Write leveling (Byte 0): 33 => 33
2509 11:47:00.211427 Write leveling (Byte 1): 30 => 30
2510 11:47:00.211899 DramcWriteLeveling(PI) end<-----
2511 11:47:00.214604
2512 11:47:00.215031 ==
2513 11:47:00.217666 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 11:47:00.220777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 11:47:00.221261 ==
2516 11:47:00.224291 [Gating] SW mode calibration
2517 11:47:00.230675 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 11:47:00.234103 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 11:47:00.240618 0 15 0 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
2520 11:47:00.243911 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2521 11:47:00.247441 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 11:47:00.254118 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 11:47:00.257370 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 11:47:00.260654 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 11:47:00.267242 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2526 11:47:00.270862 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2527 11:47:00.274061 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2528 11:47:00.280377 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 11:47:00.283696 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 11:47:00.287654 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 11:47:00.293728 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 11:47:00.297067 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 11:47:00.300870 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2534 11:47:00.307164 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2535 11:47:00.310357 1 1 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
2536 11:47:00.313564 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 11:47:00.320427 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 11:47:00.323718 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 11:47:00.327306 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 11:47:00.334045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 11:47:00.337280 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 11:47:00.340812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 11:47:00.343984 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 11:47:00.350569 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:47:00.353795 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:47:00.357332 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:47:00.363841 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:47:00.367184 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:47:00.370396 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:47:00.377341 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:47:00.380576 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:47:00.383807 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:47:00.390410 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:47:00.394265 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:47:00.397430 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:47:00.404307 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:47:00.407616 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 11:47:00.410853 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 11:47:00.417385 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2560 11:47:00.420622 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 11:47:00.424080 Total UI for P1: 0, mck2ui 16
2562 11:47:00.427913 best dqsien dly found for B0: ( 1, 3, 28)
2563 11:47:00.431054 Total UI for P1: 0, mck2ui 16
2564 11:47:00.434391 best dqsien dly found for B1: ( 1, 4, 0)
2565 11:47:00.437502 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2566 11:47:00.440922 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2567 11:47:00.441370
2568 11:47:00.444169 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2569 11:47:00.447387 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2570 11:47:00.450814 [Gating] SW calibration Done
2571 11:47:00.451243 ==
2572 11:47:00.454253 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 11:47:00.457741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 11:47:00.458170 ==
2575 11:47:00.460931 RX Vref Scan: 0
2576 11:47:00.461559
2577 11:47:00.461948 RX Vref 0 -> 0, step: 1
2578 11:47:00.462511
2579 11:47:00.464324 RX Delay -40 -> 252, step: 8
2580 11:47:00.470804 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2581 11:47:00.474034 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2582 11:47:00.477542 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2583 11:47:00.481335 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2584 11:47:00.484484 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2585 11:47:00.487437 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2586 11:47:00.494444 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2587 11:47:00.497703 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2588 11:47:00.500769 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2589 11:47:00.504623 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2590 11:47:00.507711 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2591 11:47:00.514592 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2592 11:47:00.517794 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2593 11:47:00.520743 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2594 11:47:00.524729 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2595 11:47:00.527986 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2596 11:47:00.531581 ==
2597 11:47:00.534920 Dram Type= 6, Freq= 0, CH_0, rank 0
2598 11:47:00.537453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2599 11:47:00.537877 ==
2600 11:47:00.538207 DQS Delay:
2601 11:47:00.541241 DQS0 = 0, DQS1 = 0
2602 11:47:00.541750 DQM Delay:
2603 11:47:00.544419 DQM0 = 121, DQM1 = 113
2604 11:47:00.544931 DQ Delay:
2605 11:47:00.547700 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2606 11:47:00.551288 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2607 11:47:00.554368 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2608 11:47:00.557473 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2609 11:47:00.557892
2610 11:47:00.558225
2611 11:47:00.558533 ==
2612 11:47:00.560845 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 11:47:00.567634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 11:47:00.568058 ==
2615 11:47:00.568389
2616 11:47:00.568693
2617 11:47:00.569023 TX Vref Scan disable
2618 11:47:00.571511 == TX Byte 0 ==
2619 11:47:00.574195 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2620 11:47:00.577955 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2621 11:47:00.581244 == TX Byte 1 ==
2622 11:47:00.584554 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2623 11:47:00.587681 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2624 11:47:00.590863 ==
2625 11:47:00.594090 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 11:47:00.597518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 11:47:00.597957 ==
2628 11:47:00.609346 TX Vref=22, minBit 14, minWin=24, winSum=403
2629 11:47:00.612405 TX Vref=24, minBit 0, minWin=25, winSum=411
2630 11:47:00.616108 TX Vref=26, minBit 7, minWin=25, winSum=418
2631 11:47:00.619483 TX Vref=28, minBit 0, minWin=26, winSum=422
2632 11:47:00.622616 TX Vref=30, minBit 0, minWin=26, winSum=424
2633 11:47:00.625790 TX Vref=32, minBit 0, minWin=26, winSum=422
2634 11:47:00.632447 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2635 11:47:00.632906
2636 11:47:00.635630 Final TX Range 1 Vref 30
2637 11:47:00.636158
2638 11:47:00.636492 ==
2639 11:47:00.639022 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 11:47:00.642303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 11:47:00.642724 ==
2642 11:47:00.643055
2643 11:47:00.646217
2644 11:47:00.646654 TX Vref Scan disable
2645 11:47:00.649499 == TX Byte 0 ==
2646 11:47:00.652609 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2647 11:47:00.655930 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2648 11:47:00.659104 == TX Byte 1 ==
2649 11:47:00.662549 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2650 11:47:00.665919 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2651 11:47:00.666339
2652 11:47:00.669298 [DATLAT]
2653 11:47:00.669716 Freq=1200, CH0 RK0
2654 11:47:00.670178
2655 11:47:00.672547 DATLAT Default: 0xd
2656 11:47:00.673021 0, 0xFFFF, sum = 0
2657 11:47:00.675861 1, 0xFFFF, sum = 0
2658 11:47:00.676285 2, 0xFFFF, sum = 0
2659 11:47:00.678846 3, 0xFFFF, sum = 0
2660 11:47:00.679271 4, 0xFFFF, sum = 0
2661 11:47:00.682639 5, 0xFFFF, sum = 0
2662 11:47:00.683296 6, 0xFFFF, sum = 0
2663 11:47:00.685565 7, 0xFFFF, sum = 0
2664 11:47:00.688995 8, 0xFFFF, sum = 0
2665 11:47:00.689442 9, 0xFFFF, sum = 0
2666 11:47:00.692633 10, 0xFFFF, sum = 0
2667 11:47:00.693108 11, 0xFFFF, sum = 0
2668 11:47:00.695794 12, 0x0, sum = 1
2669 11:47:00.696295 13, 0x0, sum = 2
2670 11:47:00.696921 14, 0x0, sum = 3
2671 11:47:00.699283 15, 0x0, sum = 4
2672 11:47:00.699707 best_step = 13
2673 11:47:00.700038
2674 11:47:00.702468 ==
2675 11:47:00.702891 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 11:47:00.708751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 11:47:00.709251 ==
2678 11:47:00.709610 RX Vref Scan: 1
2679 11:47:00.709941
2680 11:47:00.712191 Set Vref Range= 32 -> 127
2681 11:47:00.712758
2682 11:47:00.715953 RX Vref 32 -> 127, step: 1
2683 11:47:00.716473
2684 11:47:00.718974 RX Delay -13 -> 252, step: 4
2685 11:47:00.719080
2686 11:47:00.721958 Set Vref, RX VrefLevel [Byte0]: 32
2687 11:47:00.725728 [Byte1]: 32
2688 11:47:00.725812
2689 11:47:00.728760 Set Vref, RX VrefLevel [Byte0]: 33
2690 11:47:00.732030 [Byte1]: 33
2691 11:47:00.732116
2692 11:47:00.735243 Set Vref, RX VrefLevel [Byte0]: 34
2693 11:47:00.738746 [Byte1]: 34
2694 11:47:00.742715
2695 11:47:00.742799 Set Vref, RX VrefLevel [Byte0]: 35
2696 11:47:00.745908 [Byte1]: 35
2697 11:47:00.750432
2698 11:47:00.750518 Set Vref, RX VrefLevel [Byte0]: 36
2699 11:47:00.753888 [Byte1]: 36
2700 11:47:00.758270
2701 11:47:00.758373 Set Vref, RX VrefLevel [Byte0]: 37
2702 11:47:00.762053 [Byte1]: 37
2703 11:47:00.766680
2704 11:47:00.766765 Set Vref, RX VrefLevel [Byte0]: 38
2705 11:47:00.770035 [Byte1]: 38
2706 11:47:00.774107
2707 11:47:00.774194 Set Vref, RX VrefLevel [Byte0]: 39
2708 11:47:00.780787 [Byte1]: 39
2709 11:47:00.780895
2710 11:47:00.784104 Set Vref, RX VrefLevel [Byte0]: 40
2711 11:47:00.787378 [Byte1]: 40
2712 11:47:00.787463
2713 11:47:00.790621 Set Vref, RX VrefLevel [Byte0]: 41
2714 11:47:00.793897 [Byte1]: 41
2715 11:47:00.797790
2716 11:47:00.797874 Set Vref, RX VrefLevel [Byte0]: 42
2717 11:47:00.801227 [Byte1]: 42
2718 11:47:00.805757
2719 11:47:00.805842 Set Vref, RX VrefLevel [Byte0]: 43
2720 11:47:00.809147 [Byte1]: 43
2721 11:47:00.813819
2722 11:47:00.813903 Set Vref, RX VrefLevel [Byte0]: 44
2723 11:47:00.816782 [Byte1]: 44
2724 11:47:00.821895
2725 11:47:00.821980 Set Vref, RX VrefLevel [Byte0]: 45
2726 11:47:00.824906 [Byte1]: 45
2727 11:47:00.829502
2728 11:47:00.829588 Set Vref, RX VrefLevel [Byte0]: 46
2729 11:47:00.833230 [Byte1]: 46
2730 11:47:00.837491
2731 11:47:00.837575 Set Vref, RX VrefLevel [Byte0]: 47
2732 11:47:00.840474 [Byte1]: 47
2733 11:47:00.845513
2734 11:47:00.845597 Set Vref, RX VrefLevel [Byte0]: 48
2735 11:47:00.848618 [Byte1]: 48
2736 11:47:00.853110
2737 11:47:00.853195 Set Vref, RX VrefLevel [Byte0]: 49
2738 11:47:00.856346 [Byte1]: 49
2739 11:47:00.860864
2740 11:47:00.860948 Set Vref, RX VrefLevel [Byte0]: 50
2741 11:47:00.864697 [Byte1]: 50
2742 11:47:00.869117
2743 11:47:00.869202 Set Vref, RX VrefLevel [Byte0]: 51
2744 11:47:00.872566 [Byte1]: 51
2745 11:47:00.876609
2746 11:47:00.876694 Set Vref, RX VrefLevel [Byte0]: 52
2747 11:47:00.879905 [Byte1]: 52
2748 11:47:00.884470
2749 11:47:00.884581 Set Vref, RX VrefLevel [Byte0]: 53
2750 11:47:00.887838 [Byte1]: 53
2751 11:47:00.892895
2752 11:47:00.893001 Set Vref, RX VrefLevel [Byte0]: 54
2753 11:47:00.896162 [Byte1]: 54
2754 11:47:00.900685
2755 11:47:00.900794 Set Vref, RX VrefLevel [Byte0]: 55
2756 11:47:00.904052 [Byte1]: 55
2757 11:47:00.908101
2758 11:47:00.908198 Set Vref, RX VrefLevel [Byte0]: 56
2759 11:47:00.911599 [Byte1]: 56
2760 11:47:00.916219
2761 11:47:00.916316 Set Vref, RX VrefLevel [Byte0]: 57
2762 11:47:00.920030 [Byte1]: 57
2763 11:47:00.924550
2764 11:47:00.924649 Set Vref, RX VrefLevel [Byte0]: 58
2765 11:47:00.927568 [Byte1]: 58
2766 11:47:00.932293
2767 11:47:00.932402 Set Vref, RX VrefLevel [Byte0]: 59
2768 11:47:00.935288 [Byte1]: 59
2769 11:47:00.940266
2770 11:47:00.940373 Set Vref, RX VrefLevel [Byte0]: 60
2771 11:47:00.943401 [Byte1]: 60
2772 11:47:00.947903
2773 11:47:00.948007 Set Vref, RX VrefLevel [Byte0]: 61
2774 11:47:00.951003 [Byte1]: 61
2775 11:47:00.955884
2776 11:47:00.955990 Set Vref, RX VrefLevel [Byte0]: 62
2777 11:47:00.959020 [Byte1]: 62
2778 11:47:00.963372
2779 11:47:00.963483 Set Vref, RX VrefLevel [Byte0]: 63
2780 11:47:00.966745 [Byte1]: 63
2781 11:47:00.971274
2782 11:47:00.971386 Set Vref, RX VrefLevel [Byte0]: 64
2783 11:47:00.975181 [Byte1]: 64
2784 11:47:00.979698
2785 11:47:00.979811 Set Vref, RX VrefLevel [Byte0]: 65
2786 11:47:00.982366 [Byte1]: 65
2787 11:47:00.987056
2788 11:47:00.987177 Set Vref, RX VrefLevel [Byte0]: 66
2789 11:47:00.990378 [Byte1]: 66
2790 11:47:00.994893
2791 11:47:00.995003 Set Vref, RX VrefLevel [Byte0]: 67
2792 11:47:00.998932 [Byte1]: 67
2793 11:47:01.002738
2794 11:47:01.002846 Set Vref, RX VrefLevel [Byte0]: 68
2795 11:47:01.006637 [Byte1]: 68
2796 11:47:01.010790
2797 11:47:01.010894 Set Vref, RX VrefLevel [Byte0]: 69
2798 11:47:01.014042 [Byte1]: 69
2799 11:47:01.018771
2800 11:47:01.018882 Final RX Vref Byte 0 = 55 to rank0
2801 11:47:01.022143 Final RX Vref Byte 1 = 48 to rank0
2802 11:47:01.025569 Final RX Vref Byte 0 = 55 to rank1
2803 11:47:01.028904 Final RX Vref Byte 1 = 48 to rank1==
2804 11:47:01.031916 Dram Type= 6, Freq= 0, CH_0, rank 0
2805 11:47:01.035763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2806 11:47:01.038755 ==
2807 11:47:01.038858 DQS Delay:
2808 11:47:01.038951 DQS0 = 0, DQS1 = 0
2809 11:47:01.042073 DQM Delay:
2810 11:47:01.042174 DQM0 = 120, DQM1 = 111
2811 11:47:01.045499 DQ Delay:
2812 11:47:01.049216 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2813 11:47:01.052352 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2814 11:47:01.055613 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =104
2815 11:47:01.058942 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2816 11:47:01.059047
2817 11:47:01.059140
2818 11:47:01.065636 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2819 11:47:01.068565 CH0 RK0: MR19=404, MR18=140D
2820 11:47:01.075647 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2821 11:47:01.075736
2822 11:47:01.078772 ----->DramcWriteLeveling(PI) begin...
2823 11:47:01.078856 ==
2824 11:47:01.082113 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 11:47:01.085394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 11:47:01.088699 ==
2827 11:47:01.088814 Write leveling (Byte 0): 35 => 35
2828 11:47:01.092148 Write leveling (Byte 1): 29 => 29
2829 11:47:01.095446 DramcWriteLeveling(PI) end<-----
2830 11:47:01.095530
2831 11:47:01.095594 ==
2832 11:47:01.098687 Dram Type= 6, Freq= 0, CH_0, rank 1
2833 11:47:01.105823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2834 11:47:01.105910 ==
2835 11:47:01.105976 [Gating] SW mode calibration
2836 11:47:01.115778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2837 11:47:01.119134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2838 11:47:01.122447 0 15 0 | B1->B0 | 3232 2e2e | 1 0 | (0 0) (1 1)
2839 11:47:01.129017 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 11:47:01.132411 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 11:47:01.135631 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 11:47:01.142541 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 11:47:01.145549 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 11:47:01.148779 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2845 11:47:01.155851 0 15 28 | B1->B0 | 3333 3030 | 1 1 | (1 0) (1 0)
2846 11:47:01.158933 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2847 11:47:01.162631 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 11:47:01.169114 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 11:47:01.172766 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 11:47:01.175963 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 11:47:01.182481 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 11:47:01.185492 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 11:47:01.188930 1 0 28 | B1->B0 | 3737 3938 | 0 1 | (0 0) (0 0)
2854 11:47:01.192289 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2855 11:47:01.199472 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 11:47:01.202811 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 11:47:01.206081 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 11:47:01.212118 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 11:47:01.215429 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 11:47:01.218921 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 11:47:01.226094 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2862 11:47:01.228905 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2863 11:47:01.232660 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:47:01.239230 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:47:01.242490 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:47:01.245636 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:47:01.252420 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:47:01.255702 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:47:01.259540 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:47:01.265768 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:47:01.269066 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:47:01.272775 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:47:01.276062 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:47:01.282504 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:47:01.286331 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:47:01.289584 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:47:01.296161 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2878 11:47:01.299614 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2879 11:47:01.302981 Total UI for P1: 0, mck2ui 16
2880 11:47:01.306185 best dqsien dly found for B1: ( 1, 3, 28)
2881 11:47:01.309442 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 11:47:01.312605 Total UI for P1: 0, mck2ui 16
2883 11:47:01.315996 best dqsien dly found for B0: ( 1, 3, 30)
2884 11:47:01.319435 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2885 11:47:01.322669 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2886 11:47:01.322757
2887 11:47:01.326630 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2888 11:47:01.332692 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2889 11:47:01.332776 [Gating] SW calibration Done
2890 11:47:01.336358 ==
2891 11:47:01.336442 Dram Type= 6, Freq= 0, CH_0, rank 1
2892 11:47:01.343037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 11:47:01.343122 ==
2894 11:47:01.343187 RX Vref Scan: 0
2895 11:47:01.343248
2896 11:47:01.346353 RX Vref 0 -> 0, step: 1
2897 11:47:01.346435
2898 11:47:01.349618 RX Delay -40 -> 252, step: 8
2899 11:47:01.352720 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2900 11:47:01.356156 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2901 11:47:01.360029 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2902 11:47:01.366206 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2903 11:47:01.369533 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2904 11:47:01.373165 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2905 11:47:01.376385 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2906 11:47:01.379997 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2907 11:47:01.383141 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2908 11:47:01.389416 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2909 11:47:01.392706 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2910 11:47:01.396014 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2911 11:47:01.399756 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2912 11:47:01.406464 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2913 11:47:01.409756 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2914 11:47:01.412997 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2915 11:47:01.413116 ==
2916 11:47:01.416220 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 11:47:01.419587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 11:47:01.419705 ==
2919 11:47:01.422864 DQS Delay:
2920 11:47:01.422968 DQS0 = 0, DQS1 = 0
2921 11:47:01.426300 DQM Delay:
2922 11:47:01.426405 DQM0 = 122, DQM1 = 112
2923 11:47:01.426497 DQ Delay:
2924 11:47:01.429497 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2925 11:47:01.432732 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2926 11:47:01.439345 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2927 11:47:01.443286 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2928 11:47:01.443389
2929 11:47:01.443516
2930 11:47:01.443605 ==
2931 11:47:01.446036 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 11:47:01.450106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 11:47:01.450208 ==
2934 11:47:01.450303
2935 11:47:01.450394
2936 11:47:01.453262 TX Vref Scan disable
2937 11:47:01.453357 == TX Byte 0 ==
2938 11:47:01.459923 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2939 11:47:01.463058 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2940 11:47:01.463164 == TX Byte 1 ==
2941 11:47:01.469876 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2942 11:47:01.473160 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2943 11:47:01.473246 ==
2944 11:47:01.476488 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 11:47:01.479673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 11:47:01.479773 ==
2947 11:47:01.493259 TX Vref=22, minBit 3, minWin=24, winSum=407
2948 11:47:01.496419 TX Vref=24, minBit 1, minWin=25, winSum=416
2949 11:47:01.499810 TX Vref=26, minBit 3, minWin=25, winSum=422
2950 11:47:01.502920 TX Vref=28, minBit 1, minWin=25, winSum=422
2951 11:47:01.506570 TX Vref=30, minBit 5, minWin=25, winSum=423
2952 11:47:01.510035 TX Vref=32, minBit 5, minWin=25, winSum=421
2953 11:47:01.516734 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 30
2954 11:47:01.516844
2955 11:47:01.519912 Final TX Range 1 Vref 30
2956 11:47:01.519995
2957 11:47:01.520058 ==
2958 11:47:01.523268 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 11:47:01.526753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 11:47:01.526836 ==
2961 11:47:01.526901
2962 11:47:01.529851
2963 11:47:01.529933 TX Vref Scan disable
2964 11:47:01.533255 == TX Byte 0 ==
2965 11:47:01.536491 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2966 11:47:01.539780 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2967 11:47:01.543078 == TX Byte 1 ==
2968 11:47:01.546208 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2969 11:47:01.550097 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2970 11:47:01.550181
2971 11:47:01.553390 [DATLAT]
2972 11:47:01.553473 Freq=1200, CH0 RK1
2973 11:47:01.553538
2974 11:47:01.556623 DATLAT Default: 0xd
2975 11:47:01.556705 0, 0xFFFF, sum = 0
2976 11:47:01.559847 1, 0xFFFF, sum = 0
2977 11:47:01.559931 2, 0xFFFF, sum = 0
2978 11:47:01.563233 3, 0xFFFF, sum = 0
2979 11:47:01.563317 4, 0xFFFF, sum = 0
2980 11:47:01.566380 5, 0xFFFF, sum = 0
2981 11:47:01.566463 6, 0xFFFF, sum = 0
2982 11:47:01.569563 7, 0xFFFF, sum = 0
2983 11:47:01.573306 8, 0xFFFF, sum = 0
2984 11:47:01.573392 9, 0xFFFF, sum = 0
2985 11:47:01.576551 10, 0xFFFF, sum = 0
2986 11:47:01.576636 11, 0xFFFF, sum = 0
2987 11:47:01.579624 12, 0x0, sum = 1
2988 11:47:01.579707 13, 0x0, sum = 2
2989 11:47:01.582926 14, 0x0, sum = 3
2990 11:47:01.583010 15, 0x0, sum = 4
2991 11:47:01.583076 best_step = 13
2992 11:47:01.583135
2993 11:47:01.586764 ==
2994 11:47:01.586847 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 11:47:01.593482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 11:47:01.593566 ==
2997 11:47:01.593632 RX Vref Scan: 0
2998 11:47:01.593694
2999 11:47:01.596621 RX Vref 0 -> 0, step: 1
3000 11:47:01.596703
3001 11:47:01.599960 RX Delay -13 -> 252, step: 4
3002 11:47:01.602974 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3003 11:47:01.609952 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3004 11:47:01.613188 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3005 11:47:01.616322 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3006 11:47:01.619547 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3007 11:47:01.623387 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3008 11:47:01.626666 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3009 11:47:01.633352 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3010 11:47:01.636816 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3011 11:47:01.640003 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3012 11:47:01.643241 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3013 11:47:01.646415 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3014 11:47:01.653041 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3015 11:47:01.656205 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3016 11:47:01.659796 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3017 11:47:01.663120 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3018 11:47:01.663208 ==
3019 11:47:01.666370 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 11:47:01.673216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 11:47:01.673314 ==
3022 11:47:01.673389 DQS Delay:
3023 11:47:01.673462 DQS0 = 0, DQS1 = 0
3024 11:47:01.676284 DQM Delay:
3025 11:47:01.676382 DQM0 = 121, DQM1 = 110
3026 11:47:01.680060 DQ Delay:
3027 11:47:01.683361 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3028 11:47:01.686353 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3029 11:47:01.690140 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3030 11:47:01.693232 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3031 11:47:01.693369
3032 11:47:01.693477
3033 11:47:01.700222 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3034 11:47:01.703581 CH0 RK1: MR19=403, MR18=CED
3035 11:47:01.710184 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3036 11:47:01.713280 [RxdqsGatingPostProcess] freq 1200
3037 11:47:01.720281 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3038 11:47:01.720590 best DQS0 dly(2T, 0.5T) = (0, 11)
3039 11:47:01.723745 best DQS1 dly(2T, 0.5T) = (0, 12)
3040 11:47:01.726982 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3041 11:47:01.730438 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3042 11:47:01.733713 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 11:47:01.736953 best DQS1 dly(2T, 0.5T) = (0, 11)
3044 11:47:01.740434 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 11:47:01.743677 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3046 11:47:01.746963 Pre-setting of DQS Precalculation
3047 11:47:01.753580 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3048 11:47:01.754026 ==
3049 11:47:01.757497 Dram Type= 6, Freq= 0, CH_1, rank 0
3050 11:47:01.760526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 11:47:01.760995 ==
3052 11:47:01.763910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3053 11:47:01.770553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3054 11:47:01.779628 [CA 0] Center 37 (7~68) winsize 62
3055 11:47:01.782933 [CA 1] Center 37 (7~68) winsize 62
3056 11:47:01.786238 [CA 2] Center 35 (5~65) winsize 61
3057 11:47:01.789439 [CA 3] Center 34 (4~65) winsize 62
3058 11:47:01.793252 [CA 4] Center 34 (4~64) winsize 61
3059 11:47:01.796130 [CA 5] Center 33 (4~63) winsize 60
3060 11:47:01.796761
3061 11:47:01.799135 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3062 11:47:01.799726
3063 11:47:01.803027 [CATrainingPosCal] consider 1 rank data
3064 11:47:01.806221 u2DelayCellTimex100 = 270/100 ps
3065 11:47:01.809329 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3066 11:47:01.813102 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3067 11:47:01.819435 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3068 11:47:01.822627 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3069 11:47:01.825848 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3070 11:47:01.829796 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3071 11:47:01.830263
3072 11:47:01.833190 CA PerBit enable=1, Macro0, CA PI delay=33
3073 11:47:01.833607
3074 11:47:01.835711 [CBTSetCACLKResult] CA Dly = 33
3075 11:47:01.836171 CS Dly: 7 (0~38)
3076 11:47:01.839107 ==
3077 11:47:01.839621 Dram Type= 6, Freq= 0, CH_1, rank 1
3078 11:47:01.846286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 11:47:01.846769 ==
3080 11:47:01.849387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3081 11:47:01.856026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3082 11:47:01.865164 [CA 0] Center 37 (7~68) winsize 62
3083 11:47:01.868611 [CA 1] Center 37 (7~68) winsize 62
3084 11:47:01.871831 [CA 2] Center 35 (5~65) winsize 61
3085 11:47:01.875579 [CA 3] Center 34 (4~65) winsize 62
3086 11:47:01.878418 [CA 4] Center 34 (4~65) winsize 62
3087 11:47:01.882518 [CA 5] Center 34 (4~64) winsize 61
3088 11:47:01.883095
3089 11:47:01.885575 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3090 11:47:01.886144
3091 11:47:01.888374 [CATrainingPosCal] consider 2 rank data
3092 11:47:01.891586 u2DelayCellTimex100 = 270/100 ps
3093 11:47:01.895078 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3094 11:47:01.898355 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3095 11:47:01.902193 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3096 11:47:01.908356 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3097 11:47:01.911999 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3098 11:47:01.915074 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3099 11:47:01.915745
3100 11:47:01.918792 CA PerBit enable=1, Macro0, CA PI delay=33
3101 11:47:01.919442
3102 11:47:01.921823 [CBTSetCACLKResult] CA Dly = 33
3103 11:47:01.922514 CS Dly: 8 (0~41)
3104 11:47:01.923121
3105 11:47:01.925674 ----->DramcWriteLeveling(PI) begin...
3106 11:47:01.926369 ==
3107 11:47:01.928765 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 11:47:01.935302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 11:47:01.935872 ==
3110 11:47:01.938398 Write leveling (Byte 0): 27 => 27
3111 11:47:01.942225 Write leveling (Byte 1): 27 => 27
3112 11:47:01.942888 DramcWriteLeveling(PI) end<-----
3113 11:47:01.945563
3114 11:47:01.946220 ==
3115 11:47:01.948299 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 11:47:01.952283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 11:47:01.952954 ==
3118 11:47:01.955486 [Gating] SW mode calibration
3119 11:47:01.961654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3120 11:47:01.965123 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3121 11:47:01.971498 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3122 11:47:01.974949 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 11:47:01.978368 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 11:47:01.985059 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 11:47:01.988448 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 11:47:01.991766 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 11:47:01.998314 0 15 24 | B1->B0 | 3232 2b2b | 0 0 | (0 1) (0 1)
3128 11:47:02.001574 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3129 11:47:02.005097 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 11:47:02.011382 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 11:47:02.014829 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 11:47:02.018177 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 11:47:02.025167 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 11:47:02.028100 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 11:47:02.031993 1 0 24 | B1->B0 | 2d2d 3b3b | 0 0 | (0 0) (0 0)
3136 11:47:02.035009 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 11:47:02.042102 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 11:47:02.045328 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 11:47:02.048365 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 11:47:02.055083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:47:02.058330 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 11:47:02.061731 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 11:47:02.068567 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 11:47:02.071870 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3145 11:47:02.075661 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:47:02.082399 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:47:02.085761 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:47:02.089076 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:47:02.092570 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:47:02.099311 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:47:02.102432 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:47:02.105827 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:47:02.112454 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:47:02.115837 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:47:02.118820 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:47:02.125729 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:47:02.128939 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:47:02.132306 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:47:02.138466 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3160 11:47:02.142341 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3161 11:47:02.145504 Total UI for P1: 0, mck2ui 16
3162 11:47:02.148624 best dqsien dly found for B0: ( 1, 3, 24)
3163 11:47:02.152425 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 11:47:02.155381 Total UI for P1: 0, mck2ui 16
3165 11:47:02.158649 best dqsien dly found for B1: ( 1, 3, 26)
3166 11:47:02.162408 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3167 11:47:02.165763 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3168 11:47:02.165865
3169 11:47:02.169126 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3170 11:47:02.175821 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3171 11:47:02.175917 [Gating] SW calibration Done
3172 11:47:02.175984 ==
3173 11:47:02.179066 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 11:47:02.185468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 11:47:02.185573 ==
3176 11:47:02.185676 RX Vref Scan: 0
3177 11:47:02.185770
3178 11:47:02.188682 RX Vref 0 -> 0, step: 1
3179 11:47:02.188785
3180 11:47:02.192198 RX Delay -40 -> 252, step: 8
3181 11:47:02.195482 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3182 11:47:02.198708 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3183 11:47:02.202115 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3184 11:47:02.208794 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3185 11:47:02.212028 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3186 11:47:02.216122 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3187 11:47:02.218837 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3188 11:47:02.222006 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3189 11:47:02.225831 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3190 11:47:02.232259 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3191 11:47:02.235785 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3192 11:47:02.238973 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3193 11:47:02.242067 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3194 11:47:02.249086 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3195 11:47:02.252320 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3196 11:47:02.255593 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3197 11:47:02.255678 ==
3198 11:47:02.259443 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 11:47:02.262041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 11:47:02.262128 ==
3201 11:47:02.265643 DQS Delay:
3202 11:47:02.265722 DQS0 = 0, DQS1 = 0
3203 11:47:02.268824 DQM Delay:
3204 11:47:02.268900 DQM0 = 120, DQM1 = 116
3205 11:47:02.268964 DQ Delay:
3206 11:47:02.272096 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3207 11:47:02.275769 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3208 11:47:02.282360 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3209 11:47:02.285720 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3210 11:47:02.285805
3211 11:47:02.285869
3212 11:47:02.285929 ==
3213 11:47:02.289094 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 11:47:02.292467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 11:47:02.292558 ==
3216 11:47:02.292624
3217 11:47:02.292685
3218 11:47:02.295742 TX Vref Scan disable
3219 11:47:02.295826 == TX Byte 0 ==
3220 11:47:02.302584 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3221 11:47:02.305873 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3222 11:47:02.305979 == TX Byte 1 ==
3223 11:47:02.312511 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3224 11:47:02.315778 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3225 11:47:02.315874 ==
3226 11:47:02.319065 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 11:47:02.322438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 11:47:02.322548 ==
3229 11:47:02.335040 TX Vref=22, minBit 9, minWin=24, winSum=409
3230 11:47:02.338341 TX Vref=24, minBit 9, minWin=25, winSum=418
3231 11:47:02.341492 TX Vref=26, minBit 11, minWin=25, winSum=422
3232 11:47:02.345190 TX Vref=28, minBit 2, minWin=26, winSum=426
3233 11:47:02.348352 TX Vref=30, minBit 2, minWin=26, winSum=429
3234 11:47:02.352114 TX Vref=32, minBit 2, minWin=26, winSum=433
3235 11:47:02.358338 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 32
3236 11:47:02.358441
3237 11:47:02.362051 Final TX Range 1 Vref 32
3238 11:47:02.362166
3239 11:47:02.362289 ==
3240 11:47:02.365043 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 11:47:02.368158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 11:47:02.368279 ==
3243 11:47:02.368400
3244 11:47:02.372106
3245 11:47:02.372222 TX Vref Scan disable
3246 11:47:02.375176 == TX Byte 0 ==
3247 11:47:02.378388 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3248 11:47:02.381577 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3249 11:47:02.385243 == TX Byte 1 ==
3250 11:47:02.388661 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3251 11:47:02.392062 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3252 11:47:02.392164
3253 11:47:02.395390 [DATLAT]
3254 11:47:02.395492 Freq=1200, CH1 RK0
3255 11:47:02.395583
3256 11:47:02.398856 DATLAT Default: 0xd
3257 11:47:02.398953 0, 0xFFFF, sum = 0
3258 11:47:02.401982 1, 0xFFFF, sum = 0
3259 11:47:02.402085 2, 0xFFFF, sum = 0
3260 11:47:02.405026 3, 0xFFFF, sum = 0
3261 11:47:02.405103 4, 0xFFFF, sum = 0
3262 11:47:02.408384 5, 0xFFFF, sum = 0
3263 11:47:02.408489 6, 0xFFFF, sum = 0
3264 11:47:02.411735 7, 0xFFFF, sum = 0
3265 11:47:02.411836 8, 0xFFFF, sum = 0
3266 11:47:02.415256 9, 0xFFFF, sum = 0
3267 11:47:02.415360 10, 0xFFFF, sum = 0
3268 11:47:02.418468 11, 0xFFFF, sum = 0
3269 11:47:02.418567 12, 0x0, sum = 1
3270 11:47:02.421768 13, 0x0, sum = 2
3271 11:47:02.421842 14, 0x0, sum = 3
3272 11:47:02.425252 15, 0x0, sum = 4
3273 11:47:02.425353 best_step = 13
3274 11:47:02.425423
3275 11:47:02.425482 ==
3276 11:47:02.428977 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 11:47:02.435707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 11:47:02.435818 ==
3279 11:47:02.435914 RX Vref Scan: 1
3280 11:47:02.436014
3281 11:47:02.439086 Set Vref Range= 32 -> 127
3282 11:47:02.439195
3283 11:47:02.441864 RX Vref 32 -> 127, step: 1
3284 11:47:02.441968
3285 11:47:02.442062 RX Delay -5 -> 252, step: 4
3286 11:47:02.442166
3287 11:47:02.445155 Set Vref, RX VrefLevel [Byte0]: 32
3288 11:47:02.448423 [Byte1]: 32
3289 11:47:02.452819
3290 11:47:02.452894 Set Vref, RX VrefLevel [Byte0]: 33
3291 11:47:02.456426 [Byte1]: 33
3292 11:47:02.460680
3293 11:47:02.460791 Set Vref, RX VrefLevel [Byte0]: 34
3294 11:47:02.464406 [Byte1]: 34
3295 11:47:02.468872
3296 11:47:02.468955 Set Vref, RX VrefLevel [Byte0]: 35
3297 11:47:02.471916 [Byte1]: 35
3298 11:47:02.476796
3299 11:47:02.476892 Set Vref, RX VrefLevel [Byte0]: 36
3300 11:47:02.479983 [Byte1]: 36
3301 11:47:02.484650
3302 11:47:02.484733 Set Vref, RX VrefLevel [Byte0]: 37
3303 11:47:02.487674 [Byte1]: 37
3304 11:47:02.492481
3305 11:47:02.492568 Set Vref, RX VrefLevel [Byte0]: 38
3306 11:47:02.495673 [Byte1]: 38
3307 11:47:02.500229
3308 11:47:02.500312 Set Vref, RX VrefLevel [Byte0]: 39
3309 11:47:02.503537 [Byte1]: 39
3310 11:47:02.508162
3311 11:47:02.508237 Set Vref, RX VrefLevel [Byte0]: 40
3312 11:47:02.511448 [Byte1]: 40
3313 11:47:02.516116
3314 11:47:02.516187 Set Vref, RX VrefLevel [Byte0]: 41
3315 11:47:02.519419 [Byte1]: 41
3316 11:47:02.523961
3317 11:47:02.524031 Set Vref, RX VrefLevel [Byte0]: 42
3318 11:47:02.527407 [Byte1]: 42
3319 11:47:02.531259
3320 11:47:02.531358 Set Vref, RX VrefLevel [Byte0]: 43
3321 11:47:02.535096 [Byte1]: 43
3322 11:47:02.539627
3323 11:47:02.539726 Set Vref, RX VrefLevel [Byte0]: 44
3324 11:47:02.542968 [Byte1]: 44
3325 11:47:02.547520
3326 11:47:02.547631 Set Vref, RX VrefLevel [Byte0]: 45
3327 11:47:02.550792 [Byte1]: 45
3328 11:47:02.555538
3329 11:47:02.555637 Set Vref, RX VrefLevel [Byte0]: 46
3330 11:47:02.558577 [Byte1]: 46
3331 11:47:02.563091
3332 11:47:02.563191 Set Vref, RX VrefLevel [Byte0]: 47
3333 11:47:02.566104 [Byte1]: 47
3334 11:47:02.571112
3335 11:47:02.571211 Set Vref, RX VrefLevel [Byte0]: 48
3336 11:47:02.574258 [Byte1]: 48
3337 11:47:02.578711
3338 11:47:02.578790 Set Vref, RX VrefLevel [Byte0]: 49
3339 11:47:02.581834 [Byte1]: 49
3340 11:47:02.586342
3341 11:47:02.586424 Set Vref, RX VrefLevel [Byte0]: 50
3342 11:47:02.590313 [Byte1]: 50
3343 11:47:02.594143
3344 11:47:02.594244 Set Vref, RX VrefLevel [Byte0]: 51
3345 11:47:02.598164 [Byte1]: 51
3346 11:47:02.602230
3347 11:47:02.602311 Set Vref, RX VrefLevel [Byte0]: 52
3348 11:47:02.605414 [Byte1]: 52
3349 11:47:02.610003
3350 11:47:02.610085 Set Vref, RX VrefLevel [Byte0]: 53
3351 11:47:02.613302 [Byte1]: 53
3352 11:47:02.617958
3353 11:47:02.618037 Set Vref, RX VrefLevel [Byte0]: 54
3354 11:47:02.621158 [Byte1]: 54
3355 11:47:02.625830
3356 11:47:02.625910 Set Vref, RX VrefLevel [Byte0]: 55
3357 11:47:02.629035 [Byte1]: 55
3358 11:47:02.633782
3359 11:47:02.633862 Set Vref, RX VrefLevel [Byte0]: 56
3360 11:47:02.637100 [Byte1]: 56
3361 11:47:02.641651
3362 11:47:02.641733 Set Vref, RX VrefLevel [Byte0]: 57
3363 11:47:02.645083 [Byte1]: 57
3364 11:47:02.649646
3365 11:47:02.649727 Set Vref, RX VrefLevel [Byte0]: 58
3366 11:47:02.652949 [Byte1]: 58
3367 11:47:02.657608
3368 11:47:02.657688 Set Vref, RX VrefLevel [Byte0]: 59
3369 11:47:02.660697 [Byte1]: 59
3370 11:47:02.665284
3371 11:47:02.665401 Set Vref, RX VrefLevel [Byte0]: 60
3372 11:47:02.668481 [Byte1]: 60
3373 11:47:02.672788
3374 11:47:02.672894 Set Vref, RX VrefLevel [Byte0]: 61
3375 11:47:02.675931 [Byte1]: 61
3376 11:47:02.680450
3377 11:47:02.680558 Set Vref, RX VrefLevel [Byte0]: 62
3378 11:47:02.684306 [Byte1]: 62
3379 11:47:02.688654
3380 11:47:02.688764 Set Vref, RX VrefLevel [Byte0]: 63
3381 11:47:02.691890 [Byte1]: 63
3382 11:47:02.696291
3383 11:47:02.696405 Set Vref, RX VrefLevel [Byte0]: 64
3384 11:47:02.700016 [Byte1]: 64
3385 11:47:02.704581
3386 11:47:02.704693 Set Vref, RX VrefLevel [Byte0]: 65
3387 11:47:02.707598 [Byte1]: 65
3388 11:47:02.712038
3389 11:47:02.712130 Set Vref, RX VrefLevel [Byte0]: 66
3390 11:47:02.715212 [Byte1]: 66
3391 11:47:02.720317
3392 11:47:02.720392 Set Vref, RX VrefLevel [Byte0]: 67
3393 11:47:02.722994 [Byte1]: 67
3394 11:47:02.727594
3395 11:47:02.727676 Set Vref, RX VrefLevel [Byte0]: 68
3396 11:47:02.730846 [Byte1]: 68
3397 11:47:02.735593
3398 11:47:02.735675 Set Vref, RX VrefLevel [Byte0]: 69
3399 11:47:02.738964 [Byte1]: 69
3400 11:47:02.743688
3401 11:47:02.743817 Final RX Vref Byte 0 = 54 to rank0
3402 11:47:02.746844 Final RX Vref Byte 1 = 49 to rank0
3403 11:47:02.750179 Final RX Vref Byte 0 = 54 to rank1
3404 11:47:02.753416 Final RX Vref Byte 1 = 49 to rank1==
3405 11:47:02.756685 Dram Type= 6, Freq= 0, CH_1, rank 0
3406 11:47:02.760265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3407 11:47:02.763389 ==
3408 11:47:02.763489 DQS Delay:
3409 11:47:02.763578 DQS0 = 0, DQS1 = 0
3410 11:47:02.766783 DQM Delay:
3411 11:47:02.766852 DQM0 = 119, DQM1 = 116
3412 11:47:02.770048 DQ Delay:
3413 11:47:02.773321 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3414 11:47:02.777094 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3415 11:47:02.780378 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3416 11:47:02.783462 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3417 11:47:02.783534
3418 11:47:02.783594
3419 11:47:02.790595 [DQSOSCAuto] RK0, (LSB)MR18= 0x214, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3420 11:47:02.793667 CH1 RK0: MR19=404, MR18=214
3421 11:47:02.800193 CH1_RK0: MR19=0x404, MR18=0x214, DQSOSC=402, MR23=63, INC=40, DEC=27
3422 11:47:02.800299
3423 11:47:02.803785 ----->DramcWriteLeveling(PI) begin...
3424 11:47:02.803917 ==
3425 11:47:02.807351 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 11:47:02.810656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 11:47:02.810739 ==
3428 11:47:02.813691 Write leveling (Byte 0): 26 => 26
3429 11:47:02.817103 Write leveling (Byte 1): 28 => 28
3430 11:47:02.820280 DramcWriteLeveling(PI) end<-----
3431 11:47:02.820387
3432 11:47:02.820479 ==
3433 11:47:02.824033 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 11:47:02.827384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 11:47:02.830581 ==
3436 11:47:02.830663 [Gating] SW mode calibration
3437 11:47:02.837334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3438 11:47:02.844134 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3439 11:47:02.847438 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 11:47:02.854020 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 11:47:02.857369 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 11:47:02.860662 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 11:47:02.867323 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 11:47:02.870543 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3445 11:47:02.873746 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (1 0) (1 0)
3446 11:47:02.880424 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3447 11:47:02.884114 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 11:47:02.887375 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 11:47:02.893692 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 11:47:02.897008 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 11:47:02.900269 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 11:47:02.903880 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3453 11:47:02.910303 1 0 24 | B1->B0 | 4242 2a2a | 0 0 | (1 1) (0 0)
3454 11:47:02.913405 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3455 11:47:02.916731 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 11:47:02.923834 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 11:47:02.926819 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 11:47:02.930041 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 11:47:02.937058 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 11:47:02.940245 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 11:47:02.943498 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3462 11:47:02.950062 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3463 11:47:02.953320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:47:02.957360 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:47:02.963832 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:47:02.967084 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:47:02.969863 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:47:02.976969 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:47:02.980191 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:47:02.983548 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:47:02.990210 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:47:02.993210 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:47:02.997004 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:47:03.003297 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:47:03.006524 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:47:03.010339 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3477 11:47:03.016603 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3478 11:47:03.019824 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3479 11:47:03.023073 Total UI for P1: 0, mck2ui 16
3480 11:47:03.026477 best dqsien dly found for B1: ( 1, 3, 22)
3481 11:47:03.029695 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 11:47:03.033017 Total UI for P1: 0, mck2ui 16
3483 11:47:03.036257 best dqsien dly found for B0: ( 1, 3, 26)
3484 11:47:03.040027 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3485 11:47:03.043205 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3486 11:47:03.043289
3487 11:47:03.046439 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3488 11:47:03.053071 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3489 11:47:03.053154 [Gating] SW calibration Done
3490 11:47:03.056229 ==
3491 11:47:03.056326 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 11:47:03.062898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 11:47:03.062983 ==
3494 11:47:03.063048 RX Vref Scan: 0
3495 11:47:03.063111
3496 11:47:03.066182 RX Vref 0 -> 0, step: 1
3497 11:47:03.066265
3498 11:47:03.069408 RX Delay -40 -> 252, step: 8
3499 11:47:03.072736 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3500 11:47:03.076170 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3501 11:47:03.079423 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3502 11:47:03.086147 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3503 11:47:03.089369 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3504 11:47:03.092667 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3505 11:47:03.095890 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3506 11:47:03.099391 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3507 11:47:03.105893 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3508 11:47:03.109670 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3509 11:47:03.112882 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3510 11:47:03.116121 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3511 11:47:03.119090 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3512 11:47:03.126251 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3513 11:47:03.129458 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3514 11:47:03.132776 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3515 11:47:03.132880 ==
3516 11:47:03.136161 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 11:47:03.139437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 11:47:03.142538 ==
3519 11:47:03.142621 DQS Delay:
3520 11:47:03.142687 DQS0 = 0, DQS1 = 0
3521 11:47:03.145751 DQM Delay:
3522 11:47:03.145833 DQM0 = 121, DQM1 = 118
3523 11:47:03.149439 DQ Delay:
3524 11:47:03.152685 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3525 11:47:03.156011 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3526 11:47:03.159247 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3527 11:47:03.162494 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3528 11:47:03.162577
3529 11:47:03.162642
3530 11:47:03.162711 ==
3531 11:47:03.165746 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 11:47:03.169057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 11:47:03.169140 ==
3534 11:47:03.169205
3535 11:47:03.172526
3536 11:47:03.172624 TX Vref Scan disable
3537 11:47:03.175615 == TX Byte 0 ==
3538 11:47:03.179159 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3539 11:47:03.182390 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3540 11:47:03.185700 == TX Byte 1 ==
3541 11:47:03.189049 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3542 11:47:03.192510 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3543 11:47:03.192612 ==
3544 11:47:03.195688 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 11:47:03.202278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 11:47:03.202382 ==
3547 11:47:03.212392 TX Vref=22, minBit 9, minWin=25, winSum=416
3548 11:47:03.215800 TX Vref=24, minBit 1, minWin=25, winSum=424
3549 11:47:03.219067 TX Vref=26, minBit 2, minWin=26, winSum=428
3550 11:47:03.222942 TX Vref=28, minBit 10, minWin=26, winSum=433
3551 11:47:03.226088 TX Vref=30, minBit 9, minWin=26, winSum=436
3552 11:47:03.229360 TX Vref=32, minBit 9, minWin=26, winSum=435
3553 11:47:03.236128 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3554 11:47:03.236237
3555 11:47:03.239465 Final TX Range 1 Vref 30
3556 11:47:03.239538
3557 11:47:03.239602 ==
3558 11:47:03.242745 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 11:47:03.246046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 11:47:03.246122 ==
3561 11:47:03.246184
3562 11:47:03.249296
3563 11:47:03.249364 TX Vref Scan disable
3564 11:47:03.252512 == TX Byte 0 ==
3565 11:47:03.255826 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3566 11:47:03.259641 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3567 11:47:03.262990 == TX Byte 1 ==
3568 11:47:03.266096 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3569 11:47:03.269475 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3570 11:47:03.269559
3571 11:47:03.272736 [DATLAT]
3572 11:47:03.272844 Freq=1200, CH1 RK1
3573 11:47:03.272912
3574 11:47:03.276221 DATLAT Default: 0xd
3575 11:47:03.276304 0, 0xFFFF, sum = 0
3576 11:47:03.279495 1, 0xFFFF, sum = 0
3577 11:47:03.279580 2, 0xFFFF, sum = 0
3578 11:47:03.282798 3, 0xFFFF, sum = 0
3579 11:47:03.282883 4, 0xFFFF, sum = 0
3580 11:47:03.286062 5, 0xFFFF, sum = 0
3581 11:47:03.286146 6, 0xFFFF, sum = 0
3582 11:47:03.289415 7, 0xFFFF, sum = 0
3583 11:47:03.292629 8, 0xFFFF, sum = 0
3584 11:47:03.292714 9, 0xFFFF, sum = 0
3585 11:47:03.296073 10, 0xFFFF, sum = 0
3586 11:47:03.296157 11, 0xFFFF, sum = 0
3587 11:47:03.299347 12, 0x0, sum = 1
3588 11:47:03.299431 13, 0x0, sum = 2
3589 11:47:03.302773 14, 0x0, sum = 3
3590 11:47:03.302857 15, 0x0, sum = 4
3591 11:47:03.302923 best_step = 13
3592 11:47:03.302984
3593 11:47:03.306070 ==
3594 11:47:03.309298 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 11:47:03.312399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 11:47:03.312483 ==
3597 11:47:03.312547 RX Vref Scan: 0
3598 11:47:03.312608
3599 11:47:03.315355 RX Vref 0 -> 0, step: 1
3600 11:47:03.315438
3601 11:47:03.318991 RX Delay -5 -> 252, step: 4
3602 11:47:03.322301 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3603 11:47:03.328667 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3604 11:47:03.332574 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3605 11:47:03.335696 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3606 11:47:03.339018 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3607 11:47:03.342071 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3608 11:47:03.345937 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3609 11:47:03.352408 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3610 11:47:03.355546 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3611 11:47:03.358820 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3612 11:47:03.361962 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3613 11:47:03.365844 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3614 11:47:03.372289 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3615 11:47:03.375499 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3616 11:47:03.379025 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3617 11:47:03.382299 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3618 11:47:03.385846 ==
3619 11:47:03.385944 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 11:47:03.392325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 11:47:03.392409 ==
3622 11:47:03.392475 DQS Delay:
3623 11:47:03.395065 DQS0 = 0, DQS1 = 0
3624 11:47:03.395148 DQM Delay:
3625 11:47:03.399068 DQM0 = 120, DQM1 = 116
3626 11:47:03.399151 DQ Delay:
3627 11:47:03.401658 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3628 11:47:03.405066 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3629 11:47:03.408342 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3630 11:47:03.411850 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3631 11:47:03.411933
3632 11:47:03.411997
3633 11:47:03.422169 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3634 11:47:03.425214 CH1 RK1: MR19=403, MR18=11EE
3635 11:47:03.428634 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3636 11:47:03.431818 [RxdqsGatingPostProcess] freq 1200
3637 11:47:03.438651 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3638 11:47:03.441720 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 11:47:03.445436 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 11:47:03.448435 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 11:47:03.451825 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 11:47:03.455190 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 11:47:03.458554 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 11:47:03.461802 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 11:47:03.464768 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 11:47:03.464884 Pre-setting of DQS Precalculation
3647 11:47:03.472013 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3648 11:47:03.478296 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3649 11:47:03.484855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3650 11:47:03.484936
3651 11:47:03.485012
3652 11:47:03.488204 [Calibration Summary] 2400 Mbps
3653 11:47:03.491560 CH 0, Rank 0
3654 11:47:03.491633 SW Impedance : PASS
3655 11:47:03.494960 DUTY Scan : NO K
3656 11:47:03.498155 ZQ Calibration : PASS
3657 11:47:03.498228 Jitter Meter : NO K
3658 11:47:03.501470 CBT Training : PASS
3659 11:47:03.504712 Write leveling : PASS
3660 11:47:03.504784 RX DQS gating : PASS
3661 11:47:03.508016 RX DQ/DQS(RDDQC) : PASS
3662 11:47:03.511480 TX DQ/DQS : PASS
3663 11:47:03.511552 RX DATLAT : PASS
3664 11:47:03.514815 RX DQ/DQS(Engine): PASS
3665 11:47:03.514889 TX OE : NO K
3666 11:47:03.518069 All Pass.
3667 11:47:03.518140
3668 11:47:03.518200 CH 0, Rank 1
3669 11:47:03.521417 SW Impedance : PASS
3670 11:47:03.521484 DUTY Scan : NO K
3671 11:47:03.524698 ZQ Calibration : PASS
3672 11:47:03.527974 Jitter Meter : NO K
3673 11:47:03.528042 CBT Training : PASS
3674 11:47:03.531864 Write leveling : PASS
3675 11:47:03.535089 RX DQS gating : PASS
3676 11:47:03.535161 RX DQ/DQS(RDDQC) : PASS
3677 11:47:03.538154 TX DQ/DQS : PASS
3678 11:47:03.541349 RX DATLAT : PASS
3679 11:47:03.541450 RX DQ/DQS(Engine): PASS
3680 11:47:03.544489 TX OE : NO K
3681 11:47:03.544572 All Pass.
3682 11:47:03.544637
3683 11:47:03.548062 CH 1, Rank 0
3684 11:47:03.548140 SW Impedance : PASS
3685 11:47:03.551180 DUTY Scan : NO K
3686 11:47:03.554924 ZQ Calibration : PASS
3687 11:47:03.555001 Jitter Meter : NO K
3688 11:47:03.558062 CBT Training : PASS
3689 11:47:03.561250 Write leveling : PASS
3690 11:47:03.561325 RX DQS gating : PASS
3691 11:47:03.564710 RX DQ/DQS(RDDQC) : PASS
3692 11:47:03.564779 TX DQ/DQS : PASS
3693 11:47:03.567878 RX DATLAT : PASS
3694 11:47:03.571444 RX DQ/DQS(Engine): PASS
3695 11:47:03.571521 TX OE : NO K
3696 11:47:03.574719 All Pass.
3697 11:47:03.574788
3698 11:47:03.574847 CH 1, Rank 1
3699 11:47:03.578045 SW Impedance : PASS
3700 11:47:03.578124 DUTY Scan : NO K
3701 11:47:03.581340 ZQ Calibration : PASS
3702 11:47:03.584418 Jitter Meter : NO K
3703 11:47:03.584492 CBT Training : PASS
3704 11:47:03.587748 Write leveling : PASS
3705 11:47:03.591014 RX DQS gating : PASS
3706 11:47:03.591098 RX DQ/DQS(RDDQC) : PASS
3707 11:47:03.594413 TX DQ/DQS : PASS
3708 11:47:03.597657 RX DATLAT : PASS
3709 11:47:03.597729 RX DQ/DQS(Engine): PASS
3710 11:47:03.601035 TX OE : NO K
3711 11:47:03.601107 All Pass.
3712 11:47:03.601167
3713 11:47:03.604272 DramC Write-DBI off
3714 11:47:03.607688 PER_BANK_REFRESH: Hybrid Mode
3715 11:47:03.607755 TX_TRACKING: ON
3716 11:47:03.617740 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3717 11:47:03.620987 [FAST_K] Save calibration result to emmc
3718 11:47:03.624414 dramc_set_vcore_voltage set vcore to 650000
3719 11:47:03.627599 Read voltage for 600, 5
3720 11:47:03.627671 Vio18 = 0
3721 11:47:03.627732 Vcore = 650000
3722 11:47:03.630843 Vdram = 0
3723 11:47:03.630928 Vddq = 0
3724 11:47:03.630992 Vmddr = 0
3725 11:47:03.637833 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3726 11:47:03.641068 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3727 11:47:03.644213 MEM_TYPE=3, freq_sel=19
3728 11:47:03.647223 sv_algorithm_assistance_LP4_1600
3729 11:47:03.650903 ============ PULL DRAM RESETB DOWN ============
3730 11:47:03.654151 ========== PULL DRAM RESETB DOWN end =========
3731 11:47:03.660600 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3732 11:47:03.664260 ===================================
3733 11:47:03.664330 LPDDR4 DRAM CONFIGURATION
3734 11:47:03.667435 ===================================
3735 11:47:03.670756 EX_ROW_EN[0] = 0x0
3736 11:47:03.673927 EX_ROW_EN[1] = 0x0
3737 11:47:03.673995 LP4Y_EN = 0x0
3738 11:47:03.677728 WORK_FSP = 0x0
3739 11:47:03.677812 WL = 0x2
3740 11:47:03.680778 RL = 0x2
3741 11:47:03.680917 BL = 0x2
3742 11:47:03.684154 RPST = 0x0
3743 11:47:03.684223 RD_PRE = 0x0
3744 11:47:03.687359 WR_PRE = 0x1
3745 11:47:03.687426 WR_PST = 0x0
3746 11:47:03.690591 DBI_WR = 0x0
3747 11:47:03.690659 DBI_RD = 0x0
3748 11:47:03.693762 OTF = 0x1
3749 11:47:03.697118 ===================================
3750 11:47:03.700470 ===================================
3751 11:47:03.700539 ANA top config
3752 11:47:03.703685 ===================================
3753 11:47:03.707133 DLL_ASYNC_EN = 0
3754 11:47:03.710959 ALL_SLAVE_EN = 1
3755 11:47:03.714169 NEW_RANK_MODE = 1
3756 11:47:03.714272 DLL_IDLE_MODE = 1
3757 11:47:03.717567 LP45_APHY_COMB_EN = 1
3758 11:47:03.720713 TX_ODT_DIS = 1
3759 11:47:03.724055 NEW_8X_MODE = 1
3760 11:47:03.726812 ===================================
3761 11:47:03.730685 ===================================
3762 11:47:03.734127 data_rate = 1200
3763 11:47:03.734207 CKR = 1
3764 11:47:03.737410 DQ_P2S_RATIO = 8
3765 11:47:03.740648 ===================================
3766 11:47:03.743372 CA_P2S_RATIO = 8
3767 11:47:03.747161 DQ_CA_OPEN = 0
3768 11:47:03.750129 DQ_SEMI_OPEN = 0
3769 11:47:03.753397 CA_SEMI_OPEN = 0
3770 11:47:03.753475 CA_FULL_RATE = 0
3771 11:47:03.756659 DQ_CKDIV4_EN = 1
3772 11:47:03.760439 CA_CKDIV4_EN = 1
3773 11:47:03.763648 CA_PREDIV_EN = 0
3774 11:47:03.766840 PH8_DLY = 0
3775 11:47:03.769974 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3776 11:47:03.770070 DQ_AAMCK_DIV = 4
3777 11:47:03.773332 CA_AAMCK_DIV = 4
3778 11:47:03.776428 CA_ADMCK_DIV = 4
3779 11:47:03.779863 DQ_TRACK_CA_EN = 0
3780 11:47:03.783057 CA_PICK = 600
3781 11:47:03.786798 CA_MCKIO = 600
3782 11:47:03.790043 MCKIO_SEMI = 0
3783 11:47:03.790147 PLL_FREQ = 2288
3784 11:47:03.793202 DQ_UI_PI_RATIO = 32
3785 11:47:03.796419 CA_UI_PI_RATIO = 0
3786 11:47:03.799659 ===================================
3787 11:47:03.803051 ===================================
3788 11:47:03.806255 memory_type:LPDDR4
3789 11:47:03.806329 GP_NUM : 10
3790 11:47:03.809656 SRAM_EN : 1
3791 11:47:03.812947 MD32_EN : 0
3792 11:47:03.816848 ===================================
3793 11:47:03.816949 [ANA_INIT] >>>>>>>>>>>>>>
3794 11:47:03.819576 <<<<<< [CONFIGURE PHASE]: ANA_TX
3795 11:47:03.823469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3796 11:47:03.826270 ===================================
3797 11:47:03.830093 data_rate = 1200,PCW = 0X5800
3798 11:47:03.833445 ===================================
3799 11:47:03.836181 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3800 11:47:03.843530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 11:47:03.846654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 11:47:03.853430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3803 11:47:03.856611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3804 11:47:03.859768 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3805 11:47:03.863030 [ANA_INIT] flow start
3806 11:47:03.863105 [ANA_INIT] PLL >>>>>>>>
3807 11:47:03.866292 [ANA_INIT] PLL <<<<<<<<
3808 11:47:03.869960 [ANA_INIT] MIDPI >>>>>>>>
3809 11:47:03.870031 [ANA_INIT] MIDPI <<<<<<<<
3810 11:47:03.872987 [ANA_INIT] DLL >>>>>>>>
3811 11:47:03.876758 [ANA_INIT] flow end
3812 11:47:03.880024 ============ LP4 DIFF to SE enter ============
3813 11:47:03.883378 ============ LP4 DIFF to SE exit ============
3814 11:47:03.886005 [ANA_INIT] <<<<<<<<<<<<<
3815 11:47:03.890004 [Flow] Enable top DCM control >>>>>
3816 11:47:03.893222 [Flow] Enable top DCM control <<<<<
3817 11:47:03.896338 Enable DLL master slave shuffle
3818 11:47:03.899548 ==============================================================
3819 11:47:03.902673 Gating Mode config
3820 11:47:03.906008 ==============================================================
3821 11:47:03.909843 Config description:
3822 11:47:03.919699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3823 11:47:03.926571 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3824 11:47:03.929847 SELPH_MODE 0: By rank 1: By Phase
3825 11:47:03.936424 ==============================================================
3826 11:47:03.939559 GAT_TRACK_EN = 1
3827 11:47:03.942856 RX_GATING_MODE = 2
3828 11:47:03.946030 RX_GATING_TRACK_MODE = 2
3829 11:47:03.949364 SELPH_MODE = 1
3830 11:47:03.953152 PICG_EARLY_EN = 1
3831 11:47:03.953236 VALID_LAT_VALUE = 1
3832 11:47:03.959721 ==============================================================
3833 11:47:03.963075 Enter into Gating configuration >>>>
3834 11:47:03.966246 Exit from Gating configuration <<<<
3835 11:47:03.969631 Enter into DVFS_PRE_config >>>>>
3836 11:47:03.979008 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3837 11:47:03.982855 Exit from DVFS_PRE_config <<<<<
3838 11:47:03.985907 Enter into PICG configuration >>>>
3839 11:47:03.989280 Exit from PICG configuration <<<<
3840 11:47:03.992705 [RX_INPUT] configuration >>>>>
3841 11:47:03.995864 [RX_INPUT] configuration <<<<<
3842 11:47:04.002303 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3843 11:47:04.006086 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3844 11:47:04.012500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 11:47:04.018993 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 11:47:04.025521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 11:47:04.032143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 11:47:04.035535 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3849 11:47:04.038783 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3850 11:47:04.042182 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3851 11:47:04.048698 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3852 11:47:04.052486 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3853 11:47:04.055695 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3854 11:47:04.058942 ===================================
3855 11:47:04.062128 LPDDR4 DRAM CONFIGURATION
3856 11:47:04.065496 ===================================
3857 11:47:04.065579 EX_ROW_EN[0] = 0x0
3858 11:47:04.068835 EX_ROW_EN[1] = 0x0
3859 11:47:04.068908 LP4Y_EN = 0x0
3860 11:47:04.072023 WORK_FSP = 0x0
3861 11:47:04.075401 WL = 0x2
3862 11:47:04.075524 RL = 0x2
3863 11:47:04.079197 BL = 0x2
3864 11:47:04.079279 RPST = 0x0
3865 11:47:04.082249 RD_PRE = 0x0
3866 11:47:04.082338 WR_PRE = 0x1
3867 11:47:04.085524 WR_PST = 0x0
3868 11:47:04.085597 DBI_WR = 0x0
3869 11:47:04.088657 DBI_RD = 0x0
3870 11:47:04.088759 OTF = 0x1
3871 11:47:04.092345 ===================================
3872 11:47:04.094998 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3873 11:47:04.101750 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3874 11:47:04.105053 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 11:47:04.108770 ===================================
3876 11:47:04.112014 LPDDR4 DRAM CONFIGURATION
3877 11:47:04.115171 ===================================
3878 11:47:04.115246 EX_ROW_EN[0] = 0x10
3879 11:47:04.118355 EX_ROW_EN[1] = 0x0
3880 11:47:04.118456 LP4Y_EN = 0x0
3881 11:47:04.121746 WORK_FSP = 0x0
3882 11:47:04.124822 WL = 0x2
3883 11:47:04.124944 RL = 0x2
3884 11:47:04.128682 BL = 0x2
3885 11:47:04.128796 RPST = 0x0
3886 11:47:04.132065 RD_PRE = 0x0
3887 11:47:04.132165 WR_PRE = 0x1
3888 11:47:04.135466 WR_PST = 0x0
3889 11:47:04.135612 DBI_WR = 0x0
3890 11:47:04.138810 DBI_RD = 0x0
3891 11:47:04.138928 OTF = 0x1
3892 11:47:04.142108 ===================================
3893 11:47:04.148503 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3894 11:47:04.152501 nWR fixed to 30
3895 11:47:04.155709 [ModeRegInit_LP4] CH0 RK0
3896 11:47:04.155868 [ModeRegInit_LP4] CH0 RK1
3897 11:47:04.159083 [ModeRegInit_LP4] CH1 RK0
3898 11:47:04.162160 [ModeRegInit_LP4] CH1 RK1
3899 11:47:04.162259 match AC timing 17
3900 11:47:04.168835 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3901 11:47:04.172098 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3902 11:47:04.175461 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3903 11:47:04.182423 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3904 11:47:04.185673 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3905 11:47:04.185796 ==
3906 11:47:04.188637 Dram Type= 6, Freq= 0, CH_0, rank 0
3907 11:47:04.192306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3908 11:47:04.192406 ==
3909 11:47:04.198496 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3910 11:47:04.205162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3911 11:47:04.209040 [CA 0] Center 35 (5~66) winsize 62
3912 11:47:04.212372 [CA 1] Center 35 (5~66) winsize 62
3913 11:47:04.215578 [CA 2] Center 33 (3~64) winsize 62
3914 11:47:04.218807 [CA 3] Center 33 (2~64) winsize 63
3915 11:47:04.222074 [CA 4] Center 33 (2~64) winsize 63
3916 11:47:04.225309 [CA 5] Center 32 (2~63) winsize 62
3917 11:47:04.225439
3918 11:47:04.228621 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3919 11:47:04.228753
3920 11:47:04.232424 [CATrainingPosCal] consider 1 rank data
3921 11:47:04.235097 u2DelayCellTimex100 = 270/100 ps
3922 11:47:04.239139 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3923 11:47:04.242410 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3924 11:47:04.245093 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3925 11:47:04.248395 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3926 11:47:04.251739 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3927 11:47:04.258240 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3928 11:47:04.258362
3929 11:47:04.261521 CA PerBit enable=1, Macro0, CA PI delay=32
3930 11:47:04.261604
3931 11:47:04.265423 [CBTSetCACLKResult] CA Dly = 32
3932 11:47:04.265527 CS Dly: 3 (0~34)
3933 11:47:04.265631 ==
3934 11:47:04.268724 Dram Type= 6, Freq= 0, CH_0, rank 1
3935 11:47:04.272072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 11:47:04.272185 ==
3937 11:47:04.278103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 11:47:04.284739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3939 11:47:04.288516 [CA 0] Center 36 (5~67) winsize 63
3940 11:47:04.291737 [CA 1] Center 36 (5~67) winsize 63
3941 11:47:04.294938 [CA 2] Center 34 (3~65) winsize 63
3942 11:47:04.298456 [CA 3] Center 33 (3~64) winsize 62
3943 11:47:04.301689 [CA 4] Center 33 (2~64) winsize 63
3944 11:47:04.304769 [CA 5] Center 32 (2~63) winsize 62
3945 11:47:04.304901
3946 11:47:04.308085 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3947 11:47:04.308173
3948 11:47:04.312003 [CATrainingPosCal] consider 2 rank data
3949 11:47:04.315228 u2DelayCellTimex100 = 270/100 ps
3950 11:47:04.318601 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3951 11:47:04.322007 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3952 11:47:04.325112 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3953 11:47:04.328396 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3954 11:47:04.331545 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3955 11:47:04.338663 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3956 11:47:04.338774
3957 11:47:04.341790 CA PerBit enable=1, Macro0, CA PI delay=32
3958 11:47:04.341911
3959 11:47:04.345312 [CBTSetCACLKResult] CA Dly = 32
3960 11:47:04.345424 CS Dly: 3 (0~35)
3961 11:47:04.345530
3962 11:47:04.348526 ----->DramcWriteLeveling(PI) begin...
3963 11:47:04.348629 ==
3964 11:47:04.351870 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 11:47:04.358427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 11:47:04.358540 ==
3967 11:47:04.361710 Write leveling (Byte 0): 36 => 36
3968 11:47:04.361818 Write leveling (Byte 1): 31 => 31
3969 11:47:04.365036 DramcWriteLeveling(PI) end<-----
3970 11:47:04.365146
3971 11:47:04.365260 ==
3972 11:47:04.368349 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 11:47:04.374754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 11:47:04.374837 ==
3975 11:47:04.378196 [Gating] SW mode calibration
3976 11:47:04.384780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3977 11:47:04.388268 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3978 11:47:04.395158 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 11:47:04.398354 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 11:47:04.401620 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 11:47:04.405452 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
3982 11:47:04.411717 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
3983 11:47:04.415066 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 11:47:04.418320 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 11:47:04.424594 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 11:47:04.428013 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 11:47:04.431822 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 11:47:04.437977 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 11:47:04.441327 0 10 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
3990 11:47:04.445138 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3991 11:47:04.451665 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:47:04.455111 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 11:47:04.458414 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 11:47:04.464991 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 11:47:04.468204 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 11:47:04.471410 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 11:47:04.478035 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 11:47:04.481376 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3999 11:47:04.484693 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:47:04.491387 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:47:04.494667 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:47:04.497954 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:47:04.504919 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:47:04.507991 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:47:04.511250 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:47:04.518084 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:47:04.521374 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:47:04.524591 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:47:04.531171 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:47:04.534387 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:47:04.537634 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:47:04.544196 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:47:04.547470 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4014 11:47:04.551368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 11:47:04.554479 Total UI for P1: 0, mck2ui 16
4016 11:47:04.557776 best dqsien dly found for B0: ( 0, 13, 12)
4017 11:47:04.561084 Total UI for P1: 0, mck2ui 16
4018 11:47:04.564353 best dqsien dly found for B1: ( 0, 13, 14)
4019 11:47:04.567648 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4020 11:47:04.570926 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4021 11:47:04.571031
4022 11:47:04.574374 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4023 11:47:04.580939 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4024 11:47:04.581034 [Gating] SW calibration Done
4025 11:47:04.581103 ==
4026 11:47:04.584320 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 11:47:04.591149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 11:47:04.591262 ==
4029 11:47:04.591358 RX Vref Scan: 0
4030 11:47:04.591450
4031 11:47:04.594362 RX Vref 0 -> 0, step: 1
4032 11:47:04.594448
4033 11:47:04.597688 RX Delay -230 -> 252, step: 16
4034 11:47:04.601060 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4035 11:47:04.604145 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4036 11:47:04.607434 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4037 11:47:04.614141 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4038 11:47:04.617281 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4039 11:47:04.621047 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4040 11:47:04.624456 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4041 11:47:04.631042 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4042 11:47:04.634143 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4043 11:47:04.637358 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4044 11:47:04.640512 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4045 11:47:04.647508 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4046 11:47:04.650760 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4047 11:47:04.653939 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4048 11:47:04.657302 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4049 11:47:04.663588 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4050 11:47:04.663699 ==
4051 11:47:04.667030 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 11:47:04.670264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 11:47:04.670379 ==
4054 11:47:04.670484 DQS Delay:
4055 11:47:04.673687 DQS0 = 0, DQS1 = 0
4056 11:47:04.673791 DQM Delay:
4057 11:47:04.676919 DQM0 = 48, DQM1 = 45
4058 11:47:04.677004 DQ Delay:
4059 11:47:04.680864 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4060 11:47:04.684022 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4061 11:47:04.687404 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4062 11:47:04.690632 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4063 11:47:04.690751
4064 11:47:04.690850
4065 11:47:04.690948 ==
4066 11:47:04.693811 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 11:47:04.697102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 11:47:04.697206 ==
4069 11:47:04.697299
4070 11:47:04.697394
4071 11:47:04.700432 TX Vref Scan disable
4072 11:47:04.703817 == TX Byte 0 ==
4073 11:47:04.707100 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4074 11:47:04.710366 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4075 11:47:04.713606 == TX Byte 1 ==
4076 11:47:04.717241 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4077 11:47:04.720335 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4078 11:47:04.720442 ==
4079 11:47:04.723775 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 11:47:04.730199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 11:47:04.730311 ==
4082 11:47:04.730410
4083 11:47:04.730502
4084 11:47:04.730590 TX Vref Scan disable
4085 11:47:04.734708 == TX Byte 0 ==
4086 11:47:04.737998 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4087 11:47:04.744354 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4088 11:47:04.744467 == TX Byte 1 ==
4089 11:47:04.748308 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 11:47:04.754807 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 11:47:04.754918
4092 11:47:04.755016 [DATLAT]
4093 11:47:04.755108 Freq=600, CH0 RK0
4094 11:47:04.755200
4095 11:47:04.758125 DATLAT Default: 0x9
4096 11:47:04.758227 0, 0xFFFF, sum = 0
4097 11:47:04.761303 1, 0xFFFF, sum = 0
4098 11:47:04.761379 2, 0xFFFF, sum = 0
4099 11:47:04.764652 3, 0xFFFF, sum = 0
4100 11:47:04.764757 4, 0xFFFF, sum = 0
4101 11:47:04.767877 5, 0xFFFF, sum = 0
4102 11:47:04.770942 6, 0xFFFF, sum = 0
4103 11:47:04.771051 7, 0xFFFF, sum = 0
4104 11:47:04.771147 8, 0x0, sum = 1
4105 11:47:04.774301 9, 0x0, sum = 2
4106 11:47:04.774417 10, 0x0, sum = 3
4107 11:47:04.777636 11, 0x0, sum = 4
4108 11:47:04.777751 best_step = 9
4109 11:47:04.777859
4110 11:47:04.777958 ==
4111 11:47:04.781200 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 11:47:04.787749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 11:47:04.787857 ==
4114 11:47:04.787927 RX Vref Scan: 1
4115 11:47:04.787998
4116 11:47:04.791012 RX Vref 0 -> 0, step: 1
4117 11:47:04.791118
4118 11:47:04.794390 RX Delay -163 -> 252, step: 8
4119 11:47:04.794496
4120 11:47:04.797719 Set Vref, RX VrefLevel [Byte0]: 55
4121 11:47:04.801042 [Byte1]: 48
4122 11:47:04.801143
4123 11:47:04.804371 Final RX Vref Byte 0 = 55 to rank0
4124 11:47:04.807759 Final RX Vref Byte 1 = 48 to rank0
4125 11:47:04.811117 Final RX Vref Byte 0 = 55 to rank1
4126 11:47:04.814355 Final RX Vref Byte 1 = 48 to rank1==
4127 11:47:04.817755 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 11:47:04.820994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 11:47:04.821105 ==
4130 11:47:04.824324 DQS Delay:
4131 11:47:04.824432 DQS0 = 0, DQS1 = 0
4132 11:47:04.824540 DQM Delay:
4133 11:47:04.827967 DQM0 = 53, DQM1 = 46
4134 11:47:04.828063 DQ Delay:
4135 11:47:04.831599 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4136 11:47:04.834642 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4137 11:47:04.837672 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4138 11:47:04.841385 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =56
4139 11:47:04.841489
4140 11:47:04.841586
4141 11:47:04.851054 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4142 11:47:04.851173 CH0 RK0: MR19=808, MR18=6E61
4143 11:47:04.857598 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4144 11:47:04.857707
4145 11:47:04.861585 ----->DramcWriteLeveling(PI) begin...
4146 11:47:04.864696 ==
4147 11:47:04.864773 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 11:47:04.871107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 11:47:04.871194 ==
4150 11:47:04.874171 Write leveling (Byte 0): 34 => 34
4151 11:47:04.878008 Write leveling (Byte 1): 32 => 32
4152 11:47:04.881318 DramcWriteLeveling(PI) end<-----
4153 11:47:04.881435
4154 11:47:04.881530 ==
4155 11:47:04.884649 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 11:47:04.888029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 11:47:04.888130 ==
4158 11:47:04.891321 [Gating] SW mode calibration
4159 11:47:04.897877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4160 11:47:04.901170 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4161 11:47:04.907744 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 11:47:04.911153 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 11:47:04.914358 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 11:47:04.921210 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4165 11:47:04.924401 0 9 16 | B1->B0 | 2b2b 2828 | 0 0 | (1 1) (0 0)
4166 11:47:04.927531 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 11:47:04.934182 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 11:47:04.937335 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 11:47:04.940965 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 11:47:04.947097 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 11:47:04.950915 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 11:47:04.953986 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
4173 11:47:04.960957 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4174 11:47:04.964334 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:47:04.967434 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 11:47:04.973792 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 11:47:04.977584 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 11:47:04.980781 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 11:47:04.987192 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 11:47:04.990475 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4181 11:47:04.993800 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4182 11:47:05.000654 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:47:05.004112 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:47:05.007291 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:47:05.013836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:47:05.017176 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:47:05.020403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:47:05.023876 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:47:05.030411 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:47:05.033730 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:47:05.037147 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:47:05.044264 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:47:05.047453 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:47:05.050672 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:47:05.056989 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:47:05.060896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4197 11:47:05.063969 Total UI for P1: 0, mck2ui 16
4198 11:47:05.067153 best dqsien dly found for B1: ( 0, 13, 10)
4199 11:47:05.070342 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 11:47:05.073638 Total UI for P1: 0, mck2ui 16
4201 11:47:05.076871 best dqsien dly found for B0: ( 0, 13, 12)
4202 11:47:05.080789 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4203 11:47:05.084091 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4204 11:47:05.084209
4205 11:47:05.090284 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4206 11:47:05.093566 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4207 11:47:05.096962 [Gating] SW calibration Done
4208 11:47:05.097049 ==
4209 11:47:05.100035 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 11:47:05.104092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:47:05.104206 ==
4212 11:47:05.104324 RX Vref Scan: 0
4213 11:47:05.104406
4214 11:47:05.107350 RX Vref 0 -> 0, step: 1
4215 11:47:05.107431
4216 11:47:05.110173 RX Delay -230 -> 252, step: 16
4217 11:47:05.113912 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4218 11:47:05.117329 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4219 11:47:05.123438 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4220 11:47:05.127284 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4221 11:47:05.130050 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4222 11:47:05.133431 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4223 11:47:05.139927 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4224 11:47:05.143272 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4225 11:47:05.147080 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4226 11:47:05.150269 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4227 11:47:05.153471 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4228 11:47:05.159918 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4229 11:47:05.163514 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4230 11:47:05.166771 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4231 11:47:05.170033 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4232 11:47:05.176922 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4233 11:47:05.177036 ==
4234 11:47:05.180330 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 11:47:05.183565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 11:47:05.183650 ==
4237 11:47:05.183740 DQS Delay:
4238 11:47:05.186639 DQS0 = 0, DQS1 = 0
4239 11:47:05.186726 DQM Delay:
4240 11:47:05.189960 DQM0 = 54, DQM1 = 46
4241 11:47:05.190045 DQ Delay:
4242 11:47:05.193169 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4243 11:47:05.196965 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4244 11:47:05.200475 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =41
4245 11:47:05.203595 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4246 11:47:05.203675
4247 11:47:05.203761
4248 11:47:05.203823 ==
4249 11:47:05.206888 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 11:47:05.210107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 11:47:05.210186 ==
4252 11:47:05.210251
4253 11:47:05.213448
4254 11:47:05.213538 TX Vref Scan disable
4255 11:47:05.216745 == TX Byte 0 ==
4256 11:47:05.220066 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4257 11:47:05.223246 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4258 11:47:05.226640 == TX Byte 1 ==
4259 11:47:05.230095 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4260 11:47:05.233341 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4261 11:47:05.233420 ==
4262 11:47:05.236657 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 11:47:05.243266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 11:47:05.243367 ==
4265 11:47:05.243434
4266 11:47:05.243495
4267 11:47:05.246478 TX Vref Scan disable
4268 11:47:05.246557 == TX Byte 0 ==
4269 11:47:05.252926 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4270 11:47:05.256686 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4271 11:47:05.256793 == TX Byte 1 ==
4272 11:47:05.263249 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4273 11:47:05.266344 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4274 11:47:05.266452
4275 11:47:05.266546 [DATLAT]
4276 11:47:05.269556 Freq=600, CH0 RK1
4277 11:47:05.269662
4278 11:47:05.269759 DATLAT Default: 0x9
4279 11:47:05.272894 0, 0xFFFF, sum = 0
4280 11:47:05.273006 1, 0xFFFF, sum = 0
4281 11:47:05.276726 2, 0xFFFF, sum = 0
4282 11:47:05.276846 3, 0xFFFF, sum = 0
4283 11:47:05.279937 4, 0xFFFF, sum = 0
4284 11:47:05.280054 5, 0xFFFF, sum = 0
4285 11:47:05.282904 6, 0xFFFF, sum = 0
4286 11:47:05.283019 7, 0xFFFF, sum = 0
4287 11:47:05.286780 8, 0x0, sum = 1
4288 11:47:05.286894 9, 0x0, sum = 2
4289 11:47:05.289905 10, 0x0, sum = 3
4290 11:47:05.290021 11, 0x0, sum = 4
4291 11:47:05.292944 best_step = 9
4292 11:47:05.293055
4293 11:47:05.293165 ==
4294 11:47:05.296159 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 11:47:05.299912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 11:47:05.300021 ==
4297 11:47:05.303007 RX Vref Scan: 0
4298 11:47:05.303109
4299 11:47:05.303206 RX Vref 0 -> 0, step: 1
4300 11:47:05.303295
4301 11:47:05.306154 RX Delay -147 -> 252, step: 8
4302 11:47:05.313089 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4303 11:47:05.316382 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4304 11:47:05.319786 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4305 11:47:05.323034 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4306 11:47:05.326656 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4307 11:47:05.333253 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4308 11:47:05.336411 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4309 11:47:05.339669 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4310 11:47:05.343074 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4311 11:47:05.346429 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4312 11:47:05.352933 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4313 11:47:05.356661 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4314 11:47:05.359950 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4315 11:47:05.363123 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4316 11:47:05.369589 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4317 11:47:05.372717 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4318 11:47:05.372835 ==
4319 11:47:05.376550 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 11:47:05.379809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 11:47:05.379927 ==
4322 11:47:05.379996 DQS Delay:
4323 11:47:05.383077 DQS0 = 0, DQS1 = 0
4324 11:47:05.383196 DQM Delay:
4325 11:47:05.386455 DQM0 = 52, DQM1 = 46
4326 11:47:05.386559 DQ Delay:
4327 11:47:05.389563 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4328 11:47:05.393467 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4329 11:47:05.396649 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4330 11:47:05.399566 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4331 11:47:05.399669
4332 11:47:05.399767
4333 11:47:05.409658 [DQSOSCAuto] RK1, (LSB)MR18= 0x6324, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4334 11:47:05.409771 CH0 RK1: MR19=808, MR18=6324
4335 11:47:05.416521 CH0_RK1: MR19=0x808, MR18=0x6324, DQSOSC=391, MR23=63, INC=171, DEC=114
4336 11:47:05.419614 [RxdqsGatingPostProcess] freq 600
4337 11:47:05.426356 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 11:47:05.429868 Pre-setting of DQS Precalculation
4339 11:47:05.433077 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 11:47:05.433200 ==
4341 11:47:05.436405 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 11:47:05.439674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 11:47:05.439783 ==
4344 11:47:05.446291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 11:47:05.452847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4346 11:47:05.456207 [CA 0] Center 36 (5~67) winsize 63
4347 11:47:05.459413 [CA 1] Center 36 (5~67) winsize 63
4348 11:47:05.463195 [CA 2] Center 34 (4~65) winsize 62
4349 11:47:05.466005 [CA 3] Center 34 (4~65) winsize 62
4350 11:47:05.469834 [CA 4] Center 34 (4~65) winsize 62
4351 11:47:05.473109 [CA 5] Center 34 (3~65) winsize 63
4352 11:47:05.473225
4353 11:47:05.476312 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4354 11:47:05.476415
4355 11:47:05.479525 [CATrainingPosCal] consider 1 rank data
4356 11:47:05.482636 u2DelayCellTimex100 = 270/100 ps
4357 11:47:05.485902 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4358 11:47:05.489246 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4359 11:47:05.492562 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 11:47:05.496409 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 11:47:05.502952 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 11:47:05.506188 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4363 11:47:05.506302
4364 11:47:05.509362 CA PerBit enable=1, Macro0, CA PI delay=34
4365 11:47:05.509493
4366 11:47:05.512609 [CBTSetCACLKResult] CA Dly = 34
4367 11:47:05.512729 CS Dly: 6 (0~37)
4368 11:47:05.512841 ==
4369 11:47:05.515749 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 11:47:05.519554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 11:47:05.522826 ==
4372 11:47:05.525782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 11:47:05.532442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4374 11:47:05.535758 [CA 0] Center 36 (5~67) winsize 63
4375 11:47:05.539156 [CA 1] Center 36 (5~67) winsize 63
4376 11:47:05.542524 [CA 2] Center 34 (4~65) winsize 62
4377 11:47:05.545893 [CA 3] Center 34 (4~65) winsize 62
4378 11:47:05.549018 [CA 4] Center 34 (4~65) winsize 62
4379 11:47:05.552393 [CA 5] Center 34 (3~65) winsize 63
4380 11:47:05.552497
4381 11:47:05.556300 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4382 11:47:05.556404
4383 11:47:05.559088 [CATrainingPosCal] consider 2 rank data
4384 11:47:05.562980 u2DelayCellTimex100 = 270/100 ps
4385 11:47:05.566097 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4386 11:47:05.569507 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4387 11:47:05.572726 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 11:47:05.579351 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 11:47:05.582643 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 11:47:05.585911 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4391 11:47:05.586035
4392 11:47:05.589084 CA PerBit enable=1, Macro0, CA PI delay=34
4393 11:47:05.589198
4394 11:47:05.592261 [CBTSetCACLKResult] CA Dly = 34
4395 11:47:05.592393 CS Dly: 6 (0~37)
4396 11:47:05.592496
4397 11:47:05.596087 ----->DramcWriteLeveling(PI) begin...
4398 11:47:05.596204 ==
4399 11:47:05.599206 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 11:47:05.605694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 11:47:05.605831 ==
4402 11:47:05.609030 Write leveling (Byte 0): 30 => 30
4403 11:47:05.612253 Write leveling (Byte 1): 30 => 30
4404 11:47:05.612385 DramcWriteLeveling(PI) end<-----
4405 11:47:05.615573
4406 11:47:05.615692 ==
4407 11:47:05.619344 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 11:47:05.622492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 11:47:05.622614 ==
4410 11:47:05.625708 [Gating] SW mode calibration
4411 11:47:05.632482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 11:47:05.635819 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 11:47:05.642355 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 11:47:05.645756 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 11:47:05.649225 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 11:47:05.655755 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (0 0) (0 1)
4417 11:47:05.658976 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 11:47:05.662316 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:47:05.669038 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 11:47:05.672066 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 11:47:05.675359 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 11:47:05.681996 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 11:47:05.685342 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4424 11:47:05.689093 0 10 12 | B1->B0 | 3636 3b3b | 1 0 | (0 0) (0 0)
4425 11:47:05.695433 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:47:05.698584 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:47:05.702301 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:47:05.709110 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 11:47:05.712364 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 11:47:05.715617 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:47:05.722074 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:47:05.725225 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4433 11:47:05.728513 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:47:05.732280 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:47:05.738710 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:47:05.741870 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:47:05.745228 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:47:05.751763 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:47:05.755284 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:47:05.759068 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:47:05.765571 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:47:05.768791 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:47:05.772121 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:47:05.778544 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:47:05.782359 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:47:05.785247 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:47:05.792315 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4448 11:47:05.795598 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4449 11:47:05.798710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 11:47:05.801981 Total UI for P1: 0, mck2ui 16
4451 11:47:05.805221 best dqsien dly found for B0: ( 0, 13, 10)
4452 11:47:05.808762 Total UI for P1: 0, mck2ui 16
4453 11:47:05.812169 best dqsien dly found for B1: ( 0, 13, 12)
4454 11:47:05.815235 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4455 11:47:05.818740 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4456 11:47:05.818855
4457 11:47:05.825229 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4458 11:47:05.828381 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 11:47:05.828496 [Gating] SW calibration Done
4460 11:47:05.832288 ==
4461 11:47:05.835365 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 11:47:05.838573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 11:47:05.838681 ==
4464 11:47:05.838779 RX Vref Scan: 0
4465 11:47:05.838868
4466 11:47:05.841762 RX Vref 0 -> 0, step: 1
4467 11:47:05.841868
4468 11:47:05.844945 RX Delay -230 -> 252, step: 16
4469 11:47:05.848223 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4470 11:47:05.852183 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4471 11:47:05.858816 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4472 11:47:05.862069 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4473 11:47:05.865396 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4474 11:47:05.868668 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4475 11:47:05.871997 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4476 11:47:05.878532 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4477 11:47:05.881797 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4478 11:47:05.885173 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4479 11:47:05.888455 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4480 11:47:05.895221 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4481 11:47:05.898512 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4482 11:47:05.901603 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4483 11:47:05.904718 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4484 11:47:05.911760 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4485 11:47:05.911872 ==
4486 11:47:05.914788 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 11:47:05.918534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 11:47:05.918644 ==
4489 11:47:05.918739 DQS Delay:
4490 11:47:05.921837 DQS0 = 0, DQS1 = 0
4491 11:47:05.921944 DQM Delay:
4492 11:47:05.925403 DQM0 = 50, DQM1 = 46
4493 11:47:05.925515 DQ Delay:
4494 11:47:05.928385 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4495 11:47:05.931636 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4496 11:47:05.934784 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4497 11:47:05.938069 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4498 11:47:05.938176
4499 11:47:05.938269
4500 11:47:05.938363 ==
4501 11:47:05.941838 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 11:47:05.945010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 11:47:05.945117 ==
4504 11:47:05.945224
4505 11:47:05.945319
4506 11:47:05.948139 TX Vref Scan disable
4507 11:47:05.951822 == TX Byte 0 ==
4508 11:47:05.955098 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 11:47:05.958476 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 11:47:05.961750 == TX Byte 1 ==
4511 11:47:05.964972 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4512 11:47:05.968085 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4513 11:47:05.968199 ==
4514 11:47:05.971264 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 11:47:05.978139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 11:47:05.978222 ==
4517 11:47:05.978288
4518 11:47:05.978349
4519 11:47:05.978409 TX Vref Scan disable
4520 11:47:05.982647 == TX Byte 0 ==
4521 11:47:05.985958 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 11:47:05.989039 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 11:47:05.992424 == TX Byte 1 ==
4524 11:47:05.995879 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4525 11:47:06.002315 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4526 11:47:06.002413
4527 11:47:06.002483 [DATLAT]
4528 11:47:06.002546 Freq=600, CH1 RK0
4529 11:47:06.002607
4530 11:47:06.005591 DATLAT Default: 0x9
4531 11:47:06.005676 0, 0xFFFF, sum = 0
4532 11:47:06.008946 1, 0xFFFF, sum = 0
4533 11:47:06.012156 2, 0xFFFF, sum = 0
4534 11:47:06.012246 3, 0xFFFF, sum = 0
4535 11:47:06.016066 4, 0xFFFF, sum = 0
4536 11:47:06.016158 5, 0xFFFF, sum = 0
4537 11:47:06.019316 6, 0xFFFF, sum = 0
4538 11:47:06.019411 7, 0xFFFF, sum = 0
4539 11:47:06.022367 8, 0x0, sum = 1
4540 11:47:06.022456 9, 0x0, sum = 2
4541 11:47:06.022525 10, 0x0, sum = 3
4542 11:47:06.025512 11, 0x0, sum = 4
4543 11:47:06.025601 best_step = 9
4544 11:47:06.025670
4545 11:47:06.025732 ==
4546 11:47:06.028627 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 11:47:06.035980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 11:47:06.036070 ==
4549 11:47:06.036138 RX Vref Scan: 1
4550 11:47:06.036201
4551 11:47:06.038952 RX Vref 0 -> 0, step: 1
4552 11:47:06.039037
4553 11:47:06.042108 RX Delay -163 -> 252, step: 8
4554 11:47:06.042195
4555 11:47:06.045256 Set Vref, RX VrefLevel [Byte0]: 54
4556 11:47:06.048516 [Byte1]: 49
4557 11:47:06.048597
4558 11:47:06.052386 Final RX Vref Byte 0 = 54 to rank0
4559 11:47:06.055567 Final RX Vref Byte 1 = 49 to rank0
4560 11:47:06.058787 Final RX Vref Byte 0 = 54 to rank1
4561 11:47:06.062095 Final RX Vref Byte 1 = 49 to rank1==
4562 11:47:06.065480 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 11:47:06.068916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 11:47:06.069003 ==
4565 11:47:06.072214 DQS Delay:
4566 11:47:06.072298 DQS0 = 0, DQS1 = 0
4567 11:47:06.072366 DQM Delay:
4568 11:47:06.075392 DQM0 = 48, DQM1 = 45
4569 11:47:06.075485 DQ Delay:
4570 11:47:06.079370 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4571 11:47:06.082030 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4572 11:47:06.085301 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4573 11:47:06.089156 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4574 11:47:06.089249
4575 11:47:06.089350
4576 11:47:06.099027 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
4577 11:47:06.102454 CH1 RK0: MR19=808, MR18=4A6F
4578 11:47:06.105221 CH1_RK0: MR19=0x808, MR18=0x4A6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4579 11:47:06.105314
4580 11:47:06.109046 ----->DramcWriteLeveling(PI) begin...
4581 11:47:06.111731 ==
4582 11:47:06.115540 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 11:47:06.118760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 11:47:06.118849 ==
4585 11:47:06.121782 Write leveling (Byte 0): 30 => 30
4586 11:47:06.125472 Write leveling (Byte 1): 33 => 33
4587 11:47:06.128700 DramcWriteLeveling(PI) end<-----
4588 11:47:06.128830
4589 11:47:06.128912 ==
4590 11:47:06.131881 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 11:47:06.135060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 11:47:06.135151 ==
4593 11:47:06.138264 [Gating] SW mode calibration
4594 11:47:06.145061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 11:47:06.151722 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 11:47:06.155487 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 11:47:06.158654 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 11:47:06.165141 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 11:47:06.168432 0 9 12 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 1)
4600 11:47:06.171813 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 11:47:06.175052 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 11:47:06.181505 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 11:47:06.185383 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 11:47:06.188790 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 11:47:06.195384 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 11:47:06.198226 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4607 11:47:06.201403 0 10 12 | B1->B0 | 3636 3837 | 1 1 | (0 0) (0 0)
4608 11:47:06.208130 0 10 16 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
4609 11:47:06.211370 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 11:47:06.214689 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 11:47:06.222099 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 11:47:06.225053 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 11:47:06.228291 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 11:47:06.235294 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4615 11:47:06.238527 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4616 11:47:06.241654 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:47:06.248796 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:47:06.252034 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:47:06.255155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:47:06.261496 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:47:06.265370 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:47:06.268487 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:47:06.271616 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:47:06.278391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:47:06.281744 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:47:06.285079 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:47:06.291462 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:47:06.294741 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:47:06.298492 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:47:06.305187 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:47:06.308443 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4632 11:47:06.311705 Total UI for P1: 0, mck2ui 16
4633 11:47:06.315138 best dqsien dly found for B1: ( 0, 13, 10)
4634 11:47:06.318379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 11:47:06.321762 Total UI for P1: 0, mck2ui 16
4636 11:47:06.325091 best dqsien dly found for B0: ( 0, 13, 12)
4637 11:47:06.328324 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4638 11:47:06.331631 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4639 11:47:06.334760
4640 11:47:06.338502 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4641 11:47:06.341703 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4642 11:47:06.345041 [Gating] SW calibration Done
4643 11:47:06.345121 ==
4644 11:47:06.347959 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 11:47:06.351144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 11:47:06.351228 ==
4647 11:47:06.351295 RX Vref Scan: 0
4648 11:47:06.351355
4649 11:47:06.355063 RX Vref 0 -> 0, step: 1
4650 11:47:06.355176
4651 11:47:06.358308 RX Delay -230 -> 252, step: 16
4652 11:47:06.361434 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4653 11:47:06.367958 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4654 11:47:06.371305 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4655 11:47:06.374450 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4656 11:47:06.377996 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4657 11:47:06.381119 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4658 11:47:06.387736 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4659 11:47:06.390927 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4660 11:47:06.394355 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4661 11:47:06.397657 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4662 11:47:06.404177 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4663 11:47:06.407453 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4664 11:47:06.410754 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4665 11:47:06.414076 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4666 11:47:06.420672 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4667 11:47:06.423993 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4668 11:47:06.424084 ==
4669 11:47:06.427246 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 11:47:06.430718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 11:47:06.430804 ==
4672 11:47:06.434108 DQS Delay:
4673 11:47:06.434194 DQS0 = 0, DQS1 = 0
4674 11:47:06.434262 DQM Delay:
4675 11:47:06.437423 DQM0 = 48, DQM1 = 47
4676 11:47:06.437508 DQ Delay:
4677 11:47:06.440679 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4678 11:47:06.444409 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4679 11:47:06.447693 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4680 11:47:06.451142 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4681 11:47:06.451259
4682 11:47:06.451355
4683 11:47:06.451450 ==
4684 11:47:06.454300 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 11:47:06.457364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 11:47:06.461041 ==
4687 11:47:06.461154
4688 11:47:06.461252
4689 11:47:06.461346 TX Vref Scan disable
4690 11:47:06.464280 == TX Byte 0 ==
4691 11:47:06.467461 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4692 11:47:06.474079 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4693 11:47:06.474193 == TX Byte 1 ==
4694 11:47:06.477417 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4695 11:47:06.484113 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4696 11:47:06.484219 ==
4697 11:47:06.487223 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 11:47:06.491027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 11:47:06.491119 ==
4700 11:47:06.491185
4701 11:47:06.491253
4702 11:47:06.494113 TX Vref Scan disable
4703 11:47:06.497581 == TX Byte 0 ==
4704 11:47:06.500763 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 11:47:06.503963 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 11:47:06.507393 == TX Byte 1 ==
4707 11:47:06.510753 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4708 11:47:06.514035 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4709 11:47:06.514120
4710 11:47:06.514187 [DATLAT]
4711 11:47:06.517314 Freq=600, CH1 RK1
4712 11:47:06.517398
4713 11:47:06.517463 DATLAT Default: 0x9
4714 11:47:06.520660 0, 0xFFFF, sum = 0
4715 11:47:06.524001 1, 0xFFFF, sum = 0
4716 11:47:06.524091 2, 0xFFFF, sum = 0
4717 11:47:06.527323 3, 0xFFFF, sum = 0
4718 11:47:06.527428 4, 0xFFFF, sum = 0
4719 11:47:06.530654 5, 0xFFFF, sum = 0
4720 11:47:06.530759 6, 0xFFFF, sum = 0
4721 11:47:06.533914 7, 0xFFFF, sum = 0
4722 11:47:06.533988 8, 0x0, sum = 1
4723 11:47:06.537277 9, 0x0, sum = 2
4724 11:47:06.537350 10, 0x0, sum = 3
4725 11:47:06.537411 11, 0x0, sum = 4
4726 11:47:06.540676 best_step = 9
4727 11:47:06.540771
4728 11:47:06.540851 ==
4729 11:47:06.544015 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 11:47:06.547132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 11:47:06.547243 ==
4732 11:47:06.550292 RX Vref Scan: 0
4733 11:47:06.550410
4734 11:47:06.550519 RX Vref 0 -> 0, step: 1
4735 11:47:06.553463
4736 11:47:06.553582 RX Delay -163 -> 252, step: 8
4737 11:47:06.561407 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4738 11:47:06.564592 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4739 11:47:06.567948 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4740 11:47:06.570850 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4741 11:47:06.574530 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4742 11:47:06.581029 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4743 11:47:06.584745 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4744 11:47:06.587997 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4745 11:47:06.591151 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4746 11:47:06.594341 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4747 11:47:06.601091 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4748 11:47:06.604490 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4749 11:47:06.607559 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4750 11:47:06.610660 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4751 11:47:06.617754 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4752 11:47:06.621131 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4753 11:47:06.621247 ==
4754 11:47:06.624362 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 11:47:06.627687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 11:47:06.627803 ==
4757 11:47:06.630965 DQS Delay:
4758 11:47:06.631095 DQS0 = 0, DQS1 = 0
4759 11:47:06.631201 DQM Delay:
4760 11:47:06.634319 DQM0 = 49, DQM1 = 45
4761 11:47:06.634441 DQ Delay:
4762 11:47:06.637622 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4763 11:47:06.641163 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4764 11:47:06.644277 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4765 11:47:06.647572 DQ12 =56, DQ13 =52, DQ14 =48, DQ15 =52
4766 11:47:06.647696
4767 11:47:06.647790
4768 11:47:06.657430 [DQSOSCAuto] RK1, (LSB)MR18= 0x661e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4769 11:47:06.660819 CH1 RK1: MR19=808, MR18=661E
4770 11:47:06.664236 CH1_RK1: MR19=0x808, MR18=0x661E, DQSOSC=390, MR23=63, INC=172, DEC=114
4771 11:47:06.667435 [RxdqsGatingPostProcess] freq 600
4772 11:47:06.673952 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4773 11:47:06.676971 Pre-setting of DQS Precalculation
4774 11:47:06.680373 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4775 11:47:06.690512 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4776 11:47:06.697061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4777 11:47:06.697166
4778 11:47:06.697234
4779 11:47:06.700111 [Calibration Summary] 1200 Mbps
4780 11:47:06.700184 CH 0, Rank 0
4781 11:47:06.703249 SW Impedance : PASS
4782 11:47:06.703362 DUTY Scan : NO K
4783 11:47:06.706987 ZQ Calibration : PASS
4784 11:47:06.710197 Jitter Meter : NO K
4785 11:47:06.710273 CBT Training : PASS
4786 11:47:06.713322 Write leveling : PASS
4787 11:47:06.716625 RX DQS gating : PASS
4788 11:47:06.716737 RX DQ/DQS(RDDQC) : PASS
4789 11:47:06.719925 TX DQ/DQS : PASS
4790 11:47:06.723277 RX DATLAT : PASS
4791 11:47:06.723393 RX DQ/DQS(Engine): PASS
4792 11:47:06.726617 TX OE : NO K
4793 11:47:06.726750 All Pass.
4794 11:47:06.726862
4795 11:47:06.729925 CH 0, Rank 1
4796 11:47:06.730036 SW Impedance : PASS
4797 11:47:06.733296 DUTY Scan : NO K
4798 11:47:06.736807 ZQ Calibration : PASS
4799 11:47:06.736926 Jitter Meter : NO K
4800 11:47:06.740087 CBT Training : PASS
4801 11:47:06.740199 Write leveling : PASS
4802 11:47:06.743426 RX DQS gating : PASS
4803 11:47:06.746811 RX DQ/DQS(RDDQC) : PASS
4804 11:47:06.746902 TX DQ/DQS : PASS
4805 11:47:06.750035 RX DATLAT : PASS
4806 11:47:06.753343 RX DQ/DQS(Engine): PASS
4807 11:47:06.753419 TX OE : NO K
4808 11:47:06.756823 All Pass.
4809 11:47:06.756896
4810 11:47:06.756959 CH 1, Rank 0
4811 11:47:06.759915 SW Impedance : PASS
4812 11:47:06.759983 DUTY Scan : NO K
4813 11:47:06.763088 ZQ Calibration : PASS
4814 11:47:06.766352 Jitter Meter : NO K
4815 11:47:06.766465 CBT Training : PASS
4816 11:47:06.769732 Write leveling : PASS
4817 11:47:06.773069 RX DQS gating : PASS
4818 11:47:06.773175 RX DQ/DQS(RDDQC) : PASS
4819 11:47:06.776260 TX DQ/DQS : PASS
4820 11:47:06.779675 RX DATLAT : PASS
4821 11:47:06.779786 RX DQ/DQS(Engine): PASS
4822 11:47:06.783501 TX OE : NO K
4823 11:47:06.783620 All Pass.
4824 11:47:06.783716
4825 11:47:06.786725 CH 1, Rank 1
4826 11:47:06.786839 SW Impedance : PASS
4827 11:47:06.789740 DUTY Scan : NO K
4828 11:47:06.789835 ZQ Calibration : PASS
4829 11:47:06.792980 Jitter Meter : NO K
4830 11:47:06.796290 CBT Training : PASS
4831 11:47:06.796366 Write leveling : PASS
4832 11:47:06.799533 RX DQS gating : PASS
4833 11:47:06.802777 RX DQ/DQS(RDDQC) : PASS
4834 11:47:06.802866 TX DQ/DQS : PASS
4835 11:47:06.806479 RX DATLAT : PASS
4836 11:47:06.809700 RX DQ/DQS(Engine): PASS
4837 11:47:06.809816 TX OE : NO K
4838 11:47:06.812778 All Pass.
4839 11:47:06.812880
4840 11:47:06.812971 DramC Write-DBI off
4841 11:47:06.816551 PER_BANK_REFRESH: Hybrid Mode
4842 11:47:06.816667 TX_TRACKING: ON
4843 11:47:06.826213 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4844 11:47:06.829577 [FAST_K] Save calibration result to emmc
4845 11:47:06.832864 dramc_set_vcore_voltage set vcore to 662500
4846 11:47:06.836245 Read voltage for 933, 3
4847 11:47:06.836353 Vio18 = 0
4848 11:47:06.839353 Vcore = 662500
4849 11:47:06.839480 Vdram = 0
4850 11:47:06.839575 Vddq = 0
4851 11:47:06.842612 Vmddr = 0
4852 11:47:06.846041 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4853 11:47:06.852600 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4854 11:47:06.852735 MEM_TYPE=3, freq_sel=17
4855 11:47:06.855934 sv_algorithm_assistance_LP4_1600
4856 11:47:06.859390 ============ PULL DRAM RESETB DOWN ============
4857 11:47:06.866010 ========== PULL DRAM RESETB DOWN end =========
4858 11:47:06.869781 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4859 11:47:06.873047 ===================================
4860 11:47:06.876383 LPDDR4 DRAM CONFIGURATION
4861 11:47:06.879745 ===================================
4862 11:47:06.879832 EX_ROW_EN[0] = 0x0
4863 11:47:06.883131 EX_ROW_EN[1] = 0x0
4864 11:47:06.886283 LP4Y_EN = 0x0
4865 11:47:06.886369 WORK_FSP = 0x0
4866 11:47:06.889299 WL = 0x3
4867 11:47:06.889410 RL = 0x3
4868 11:47:06.892497 BL = 0x2
4869 11:47:06.892599 RPST = 0x0
4870 11:47:06.896258 RD_PRE = 0x0
4871 11:47:06.896344 WR_PRE = 0x1
4872 11:47:06.899342 WR_PST = 0x0
4873 11:47:06.899459 DBI_WR = 0x0
4874 11:47:06.902606 DBI_RD = 0x0
4875 11:47:06.902716 OTF = 0x1
4876 11:47:06.905849 ===================================
4877 11:47:06.910031 ===================================
4878 11:47:06.912981 ANA top config
4879 11:47:06.916191 ===================================
4880 11:47:06.916277 DLL_ASYNC_EN = 0
4881 11:47:06.919601 ALL_SLAVE_EN = 1
4882 11:47:06.922675 NEW_RANK_MODE = 1
4883 11:47:06.925797 DLL_IDLE_MODE = 1
4884 11:47:06.925891 LP45_APHY_COMB_EN = 1
4885 11:47:06.929509 TX_ODT_DIS = 1
4886 11:47:06.932775 NEW_8X_MODE = 1
4887 11:47:06.936104 ===================================
4888 11:47:06.939364 ===================================
4889 11:47:06.942600 data_rate = 1866
4890 11:47:06.945935 CKR = 1
4891 11:47:06.949245 DQ_P2S_RATIO = 8
4892 11:47:06.952455 ===================================
4893 11:47:06.952559 CA_P2S_RATIO = 8
4894 11:47:06.955788 DQ_CA_OPEN = 0
4895 11:47:06.959236 DQ_SEMI_OPEN = 0
4896 11:47:06.962426 CA_SEMI_OPEN = 0
4897 11:47:06.965646 CA_FULL_RATE = 0
4898 11:47:06.969043 DQ_CKDIV4_EN = 1
4899 11:47:06.969138 CA_CKDIV4_EN = 1
4900 11:47:06.972942 CA_PREDIV_EN = 0
4901 11:47:06.976128 PH8_DLY = 0
4902 11:47:06.979349 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4903 11:47:06.982669 DQ_AAMCK_DIV = 4
4904 11:47:06.982781 CA_AAMCK_DIV = 4
4905 11:47:06.986076 CA_ADMCK_DIV = 4
4906 11:47:06.989405 DQ_TRACK_CA_EN = 0
4907 11:47:06.992622 CA_PICK = 933
4908 11:47:06.995976 CA_MCKIO = 933
4909 11:47:06.999061 MCKIO_SEMI = 0
4910 11:47:07.002232 PLL_FREQ = 3732
4911 11:47:07.006003 DQ_UI_PI_RATIO = 32
4912 11:47:07.006106 CA_UI_PI_RATIO = 0
4913 11:47:07.009482 ===================================
4914 11:47:07.012485 ===================================
4915 11:47:07.015696 memory_type:LPDDR4
4916 11:47:07.018863 GP_NUM : 10
4917 11:47:07.018969 SRAM_EN : 1
4918 11:47:07.022792 MD32_EN : 0
4919 11:47:07.025752 ===================================
4920 11:47:07.028935 [ANA_INIT] >>>>>>>>>>>>>>
4921 11:47:07.029017 <<<<<< [CONFIGURE PHASE]: ANA_TX
4922 11:47:07.032150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4923 11:47:07.036175 ===================================
4924 11:47:07.039347 data_rate = 1866,PCW = 0X8f00
4925 11:47:07.042750 ===================================
4926 11:47:07.046015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4927 11:47:07.052553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 11:47:07.059342 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 11:47:07.062621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4930 11:47:07.065970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4931 11:47:07.069278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4932 11:47:07.072585 [ANA_INIT] flow start
4933 11:47:07.072692 [ANA_INIT] PLL >>>>>>>>
4934 11:47:07.076205 [ANA_INIT] PLL <<<<<<<<
4935 11:47:07.079424 [ANA_INIT] MIDPI >>>>>>>>
4936 11:47:07.079530 [ANA_INIT] MIDPI <<<<<<<<
4937 11:47:07.082507 [ANA_INIT] DLL >>>>>>>>
4938 11:47:07.085783 [ANA_INIT] flow end
4939 11:47:07.089158 ============ LP4 DIFF to SE enter ============
4940 11:47:07.092528 ============ LP4 DIFF to SE exit ============
4941 11:47:07.095788 [ANA_INIT] <<<<<<<<<<<<<
4942 11:47:07.098948 [Flow] Enable top DCM control >>>>>
4943 11:47:07.102705 [Flow] Enable top DCM control <<<<<
4944 11:47:07.105937 Enable DLL master slave shuffle
4945 11:47:07.109049 ==============================================================
4946 11:47:07.112356 Gating Mode config
4947 11:47:07.119226 ==============================================================
4948 11:47:07.119339 Config description:
4949 11:47:07.128921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4950 11:47:07.135934 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4951 11:47:07.139043 SELPH_MODE 0: By rank 1: By Phase
4952 11:47:07.145363 ==============================================================
4953 11:47:07.148707 GAT_TRACK_EN = 1
4954 11:47:07.151927 RX_GATING_MODE = 2
4955 11:47:07.155356 RX_GATING_TRACK_MODE = 2
4956 11:47:07.158625 SELPH_MODE = 1
4957 11:47:07.161950 PICG_EARLY_EN = 1
4958 11:47:07.165325 VALID_LAT_VALUE = 1
4959 11:47:07.168556 ==============================================================
4960 11:47:07.171914 Enter into Gating configuration >>>>
4961 11:47:07.175210 Exit from Gating configuration <<<<
4962 11:47:07.178555 Enter into DVFS_PRE_config >>>>>
4963 11:47:07.191615 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4964 11:47:07.195455 Exit from DVFS_PRE_config <<<<<
4965 11:47:07.195573 Enter into PICG configuration >>>>
4966 11:47:07.198227 Exit from PICG configuration <<<<
4967 11:47:07.202145 [RX_INPUT] configuration >>>>>
4968 11:47:07.205403 [RX_INPUT] configuration <<<<<
4969 11:47:07.211735 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4970 11:47:07.215017 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4971 11:47:07.222086 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 11:47:07.228415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 11:47:07.234815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 11:47:07.241995 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 11:47:07.245171 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4976 11:47:07.248226 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4977 11:47:07.251966 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4978 11:47:07.258459 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4979 11:47:07.261732 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4980 11:47:07.265125 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4981 11:47:07.268471 ===================================
4982 11:47:07.271802 LPDDR4 DRAM CONFIGURATION
4983 11:47:07.275246 ===================================
4984 11:47:07.275332 EX_ROW_EN[0] = 0x0
4985 11:47:07.278448 EX_ROW_EN[1] = 0x0
4986 11:47:07.281748 LP4Y_EN = 0x0
4987 11:47:07.281839 WORK_FSP = 0x0
4988 11:47:07.285112 WL = 0x3
4989 11:47:07.285228 RL = 0x3
4990 11:47:07.288455 BL = 0x2
4991 11:47:07.288568 RPST = 0x0
4992 11:47:07.291698 RD_PRE = 0x0
4993 11:47:07.291804 WR_PRE = 0x1
4994 11:47:07.294921 WR_PST = 0x0
4995 11:47:07.295023 DBI_WR = 0x0
4996 11:47:07.298117 DBI_RD = 0x0
4997 11:47:07.298220 OTF = 0x1
4998 11:47:07.301771 ===================================
4999 11:47:07.305046 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5000 11:47:07.311661 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5001 11:47:07.314873 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 11:47:07.318573 ===================================
5003 11:47:07.321728 LPDDR4 DRAM CONFIGURATION
5004 11:47:07.324992 ===================================
5005 11:47:07.325111 EX_ROW_EN[0] = 0x10
5006 11:47:07.328001 EX_ROW_EN[1] = 0x0
5007 11:47:07.331287 LP4Y_EN = 0x0
5008 11:47:07.331372 WORK_FSP = 0x0
5009 11:47:07.335140 WL = 0x3
5010 11:47:07.335219 RL = 0x3
5011 11:47:07.338431 BL = 0x2
5012 11:47:07.338521 RPST = 0x0
5013 11:47:07.341473 RD_PRE = 0x0
5014 11:47:07.341558 WR_PRE = 0x1
5015 11:47:07.344554 WR_PST = 0x0
5016 11:47:07.344673 DBI_WR = 0x0
5017 11:47:07.348347 DBI_RD = 0x0
5018 11:47:07.348503 OTF = 0x1
5019 11:47:07.351470 ===================================
5020 11:47:07.357814 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5021 11:47:07.362270 nWR fixed to 30
5022 11:47:07.365552 [ModeRegInit_LP4] CH0 RK0
5023 11:47:07.365634 [ModeRegInit_LP4] CH0 RK1
5024 11:47:07.369028 [ModeRegInit_LP4] CH1 RK0
5025 11:47:07.372323 [ModeRegInit_LP4] CH1 RK1
5026 11:47:07.372412 match AC timing 9
5027 11:47:07.378942 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5028 11:47:07.382460 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5029 11:47:07.385667 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5030 11:47:07.392003 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5031 11:47:07.395242 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5032 11:47:07.395319 ==
5033 11:47:07.399101 Dram Type= 6, Freq= 0, CH_0, rank 0
5034 11:47:07.402376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5035 11:47:07.402455 ==
5036 11:47:07.408643 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5037 11:47:07.415681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5038 11:47:07.418985 [CA 0] Center 37 (6~68) winsize 63
5039 11:47:07.422247 [CA 1] Center 37 (6~68) winsize 63
5040 11:47:07.425310 [CA 2] Center 34 (4~65) winsize 62
5041 11:47:07.428570 [CA 3] Center 33 (3~64) winsize 62
5042 11:47:07.431918 [CA 4] Center 33 (3~63) winsize 61
5043 11:47:07.435427 [CA 5] Center 32 (2~62) winsize 61
5044 11:47:07.435549
5045 11:47:07.438728 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5046 11:47:07.438862
5047 11:47:07.442063 [CATrainingPosCal] consider 1 rank data
5048 11:47:07.445223 u2DelayCellTimex100 = 270/100 ps
5049 11:47:07.448237 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5050 11:47:07.451986 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5051 11:47:07.455012 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5052 11:47:07.458737 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5053 11:47:07.461719 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5054 11:47:07.465089 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5055 11:47:07.468237
5056 11:47:07.471468 CA PerBit enable=1, Macro0, CA PI delay=32
5057 11:47:07.471579
5058 11:47:07.475387 [CBTSetCACLKResult] CA Dly = 32
5059 11:47:07.475491 CS Dly: 5 (0~36)
5060 11:47:07.475596 ==
5061 11:47:07.478683 Dram Type= 6, Freq= 0, CH_0, rank 1
5062 11:47:07.481370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 11:47:07.481483 ==
5064 11:47:07.487996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 11:47:07.494657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5066 11:47:07.498013 [CA 0] Center 37 (7~68) winsize 62
5067 11:47:07.501433 [CA 1] Center 37 (7~68) winsize 62
5068 11:47:07.504753 [CA 2] Center 34 (4~65) winsize 62
5069 11:47:07.508032 [CA 3] Center 34 (3~65) winsize 63
5070 11:47:07.511376 [CA 4] Center 33 (3~63) winsize 61
5071 11:47:07.514672 [CA 5] Center 32 (2~62) winsize 61
5072 11:47:07.514779
5073 11:47:07.517810 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5074 11:47:07.517915
5075 11:47:07.521112 [CATrainingPosCal] consider 2 rank data
5076 11:47:07.524986 u2DelayCellTimex100 = 270/100 ps
5077 11:47:07.527668 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 11:47:07.531404 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5079 11:47:07.534577 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5080 11:47:07.537931 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5081 11:47:07.544261 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5082 11:47:07.547679 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5083 11:47:07.547768
5084 11:47:07.551309 CA PerBit enable=1, Macro0, CA PI delay=32
5085 11:47:07.551398
5086 11:47:07.554756 [CBTSetCACLKResult] CA Dly = 32
5087 11:47:07.554845 CS Dly: 5 (0~37)
5088 11:47:07.554932
5089 11:47:07.557831 ----->DramcWriteLeveling(PI) begin...
5090 11:47:07.557921 ==
5091 11:47:07.561058 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 11:47:07.568023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 11:47:07.568121 ==
5094 11:47:07.571115 Write leveling (Byte 0): 34 => 34
5095 11:47:07.574224 Write leveling (Byte 1): 28 => 28
5096 11:47:07.574314 DramcWriteLeveling(PI) end<-----
5097 11:47:07.574401
5098 11:47:07.577925 ==
5099 11:47:07.581114 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 11:47:07.584397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 11:47:07.584540 ==
5102 11:47:07.587797 [Gating] SW mode calibration
5103 11:47:07.594405 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5104 11:47:07.597810 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5105 11:47:07.604522 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5106 11:47:07.607739 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 11:47:07.610923 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 11:47:07.617327 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 11:47:07.620578 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 11:47:07.623821 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 11:47:07.630399 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5112 11:47:07.634195 0 14 28 | B1->B0 | 3333 2828 | 1 0 | (1 0) (1 0)
5113 11:47:07.637269 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5114 11:47:07.643776 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 11:47:07.647707 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 11:47:07.650736 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 11:47:07.657150 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 11:47:07.660406 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 11:47:07.663762 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5120 11:47:07.670897 0 15 28 | B1->B0 | 2727 3e3e | 0 1 | (1 1) (0 0)
5121 11:47:07.674028 1 0 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
5122 11:47:07.677135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 11:47:07.684107 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 11:47:07.687296 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 11:47:07.690504 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 11:47:07.693855 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 11:47:07.700397 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5128 11:47:07.703628 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5129 11:47:07.707026 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:47:07.713706 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:47:07.716989 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:47:07.720708 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:47:07.727438 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:47:07.730426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:47:07.733651 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:47:07.740437 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:47:07.743925 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:47:07.747283 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:47:07.753399 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:47:07.757227 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:47:07.760413 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:47:07.766654 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:47:07.770382 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5144 11:47:07.773763 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5145 11:47:07.780029 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5146 11:47:07.780142 Total UI for P1: 0, mck2ui 16
5147 11:47:07.786774 best dqsien dly found for B0: ( 1, 2, 26)
5148 11:47:07.789933 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 11:47:07.793249 Total UI for P1: 0, mck2ui 16
5150 11:47:07.796601 best dqsien dly found for B1: ( 1, 3, 0)
5151 11:47:07.800113 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5152 11:47:07.803447 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5153 11:47:07.803556
5154 11:47:07.806711 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5155 11:47:07.810194 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5156 11:47:07.813518 [Gating] SW calibration Done
5157 11:47:07.813636 ==
5158 11:47:07.816706 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 11:47:07.819932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 11:47:07.820040 ==
5161 11:47:07.823262 RX Vref Scan: 0
5162 11:47:07.823380
5163 11:47:07.826437 RX Vref 0 -> 0, step: 1
5164 11:47:07.826549
5165 11:47:07.826648 RX Delay -80 -> 252, step: 8
5166 11:47:07.833120 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5167 11:47:07.836395 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5168 11:47:07.840029 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5169 11:47:07.843402 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5170 11:47:07.846625 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5171 11:47:07.853494 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5172 11:47:07.856662 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5173 11:47:07.859968 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5174 11:47:07.863321 iDelay=208, Bit 8, Center 83 (0 ~ 167) 168
5175 11:47:07.866451 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5176 11:47:07.869615 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5177 11:47:07.876370 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5178 11:47:07.879491 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5179 11:47:07.883301 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5180 11:47:07.886446 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5181 11:47:07.889662 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5182 11:47:07.889751 ==
5183 11:47:07.892752 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 11:47:07.899560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 11:47:07.899650 ==
5186 11:47:07.899719 DQS Delay:
5187 11:47:07.899783 DQS0 = 0, DQS1 = 0
5188 11:47:07.902912 DQM Delay:
5189 11:47:07.902989 DQM0 = 105, DQM1 = 93
5190 11:47:07.906138 DQ Delay:
5191 11:47:07.909471 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5192 11:47:07.912776 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5193 11:47:07.916072 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =91
5194 11:47:07.919397 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5195 11:47:07.919483
5196 11:47:07.919551
5197 11:47:07.919614 ==
5198 11:47:07.922621 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 11:47:07.926032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 11:47:07.926120 ==
5201 11:47:07.926198
5202 11:47:07.926271
5203 11:47:07.929254 TX Vref Scan disable
5204 11:47:07.932530 == TX Byte 0 ==
5205 11:47:07.935865 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5206 11:47:07.939241 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5207 11:47:07.943067 == TX Byte 1 ==
5208 11:47:07.946097 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5209 11:47:07.949277 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5210 11:47:07.949382 ==
5211 11:47:07.952705 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 11:47:07.955855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 11:47:07.955965 ==
5214 11:47:07.959603
5215 11:47:07.959706
5216 11:47:07.959797 TX Vref Scan disable
5217 11:47:07.962776 == TX Byte 0 ==
5218 11:47:07.966143 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5219 11:47:07.972622 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5220 11:47:07.972711 == TX Byte 1 ==
5221 11:47:07.975715 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5222 11:47:07.982247 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5223 11:47:07.982346
5224 11:47:07.982415 [DATLAT]
5225 11:47:07.982478 Freq=933, CH0 RK0
5226 11:47:07.982539
5227 11:47:07.985552 DATLAT Default: 0xd
5228 11:47:07.989175 0, 0xFFFF, sum = 0
5229 11:47:07.989285 1, 0xFFFF, sum = 0
5230 11:47:07.992466 2, 0xFFFF, sum = 0
5231 11:47:07.992550 3, 0xFFFF, sum = 0
5232 11:47:07.995815 4, 0xFFFF, sum = 0
5233 11:47:07.995916 5, 0xFFFF, sum = 0
5234 11:47:07.998911 6, 0xFFFF, sum = 0
5235 11:47:07.998989 7, 0xFFFF, sum = 0
5236 11:47:08.002711 8, 0xFFFF, sum = 0
5237 11:47:08.002784 9, 0xFFFF, sum = 0
5238 11:47:08.005787 10, 0x0, sum = 1
5239 11:47:08.005874 11, 0x0, sum = 2
5240 11:47:08.009076 12, 0x0, sum = 3
5241 11:47:08.009163 13, 0x0, sum = 4
5242 11:47:08.009231 best_step = 11
5243 11:47:08.009294
5244 11:47:08.012404 ==
5245 11:47:08.015622 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 11:47:08.019003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 11:47:08.019109 ==
5248 11:47:08.019204 RX Vref Scan: 1
5249 11:47:08.019294
5250 11:47:08.022328 RX Vref 0 -> 0, step: 1
5251 11:47:08.022413
5252 11:47:08.025631 RX Delay -53 -> 252, step: 4
5253 11:47:08.025749
5254 11:47:08.028989 Set Vref, RX VrefLevel [Byte0]: 55
5255 11:47:08.032279 [Byte1]: 48
5256 11:47:08.032396
5257 11:47:08.036206 Final RX Vref Byte 0 = 55 to rank0
5258 11:47:08.038970 Final RX Vref Byte 1 = 48 to rank0
5259 11:47:08.042343 Final RX Vref Byte 0 = 55 to rank1
5260 11:47:08.045755 Final RX Vref Byte 1 = 48 to rank1==
5261 11:47:08.049004 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 11:47:08.052892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 11:47:08.053016 ==
5264 11:47:08.056119 DQS Delay:
5265 11:47:08.056224 DQS0 = 0, DQS1 = 0
5266 11:47:08.059375 DQM Delay:
5267 11:47:08.059480 DQM0 = 104, DQM1 = 95
5268 11:47:08.062449 DQ Delay:
5269 11:47:08.065597 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5270 11:47:08.068979 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5271 11:47:08.072358 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5272 11:47:08.075616 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =104
5273 11:47:08.075725
5274 11:47:08.075826
5275 11:47:08.082531 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5276 11:47:08.085613 CH0 RK0: MR19=505, MR18=2E25
5277 11:47:08.092117 CH0_RK0: MR19=0x505, MR18=0x2E25, DQSOSC=407, MR23=63, INC=65, DEC=43
5278 11:47:08.092201
5279 11:47:08.095424 ----->DramcWriteLeveling(PI) begin...
5280 11:47:08.095514 ==
5281 11:47:08.098601 Dram Type= 6, Freq= 0, CH_0, rank 1
5282 11:47:08.101938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 11:47:08.102031 ==
5284 11:47:08.105649 Write leveling (Byte 0): 34 => 34
5285 11:47:08.108775 Write leveling (Byte 1): 31 => 31
5286 11:47:08.111908 DramcWriteLeveling(PI) end<-----
5287 11:47:08.112017
5288 11:47:08.112116 ==
5289 11:47:08.115298 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 11:47:08.118432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 11:47:08.122463 ==
5292 11:47:08.122577 [Gating] SW mode calibration
5293 11:47:08.129075 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5294 11:47:08.135580 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5295 11:47:08.138981 0 14 0 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5296 11:47:08.145579 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 11:47:08.149031 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 11:47:08.152362 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 11:47:08.158649 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 11:47:08.161905 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 11:47:08.165247 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 11:47:08.171717 0 14 28 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
5303 11:47:08.175476 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (1 0) (0 0)
5304 11:47:08.178704 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 11:47:08.185315 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 11:47:08.188523 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 11:47:08.191626 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 11:47:08.198968 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 11:47:08.201579 0 15 24 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
5310 11:47:08.205163 0 15 28 | B1->B0 | 3f3f 3a3a | 0 1 | (0 0) (0 0)
5311 11:47:08.212013 1 0 0 | B1->B0 | 4646 4342 | 0 1 | (0 0) (0 0)
5312 11:47:08.215237 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 11:47:08.218367 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 11:47:08.224657 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 11:47:08.227972 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 11:47:08.231314 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 11:47:08.234664 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:47:08.241949 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5319 11:47:08.245208 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5320 11:47:08.248049 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:47:08.254632 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:47:08.258210 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:47:08.261348 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:47:08.268217 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:47:08.271503 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:47:08.274802 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:47:08.281710 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:47:08.285074 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:47:08.288370 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:47:08.295092 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:47:08.298286 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:47:08.301409 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:47:08.308574 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:47:08.311680 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5335 11:47:08.314818 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 11:47:08.318007 Total UI for P1: 0, mck2ui 16
5337 11:47:08.321678 best dqsien dly found for B0: ( 1, 2, 28)
5338 11:47:08.324747 Total UI for P1: 0, mck2ui 16
5339 11:47:08.327917 best dqsien dly found for B1: ( 1, 2, 30)
5340 11:47:08.331220 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5341 11:47:08.335287 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5342 11:47:08.335406
5343 11:47:08.338425 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5344 11:47:08.344920 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5345 11:47:08.345024 [Gating] SW calibration Done
5346 11:47:08.345123 ==
5347 11:47:08.348243 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 11:47:08.355026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 11:47:08.355136 ==
5350 11:47:08.355240 RX Vref Scan: 0
5351 11:47:08.355343
5352 11:47:08.358148 RX Vref 0 -> 0, step: 1
5353 11:47:08.358252
5354 11:47:08.361528 RX Delay -80 -> 252, step: 8
5355 11:47:08.364924 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5356 11:47:08.368020 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5357 11:47:08.371827 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5358 11:47:08.374805 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5359 11:47:08.381363 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5360 11:47:08.385275 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5361 11:47:08.388431 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5362 11:47:08.391479 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5363 11:47:08.394731 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5364 11:47:08.398029 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5365 11:47:08.405039 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5366 11:47:08.408120 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5367 11:47:08.411357 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5368 11:47:08.414621 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5369 11:47:08.417903 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5370 11:47:08.421600 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5371 11:47:08.424932 ==
5372 11:47:08.425018 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 11:47:08.431784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 11:47:08.431873 ==
5375 11:47:08.431941 DQS Delay:
5376 11:47:08.434831 DQS0 = 0, DQS1 = 0
5377 11:47:08.434948 DQM Delay:
5378 11:47:08.438123 DQM0 = 105, DQM1 = 93
5379 11:47:08.438232 DQ Delay:
5380 11:47:08.441356 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5381 11:47:08.444672 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5382 11:47:08.447984 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5383 11:47:08.451295 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5384 11:47:08.451400
5385 11:47:08.451499
5386 11:47:08.451604 ==
5387 11:47:08.454548 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 11:47:08.457918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 11:47:08.458029 ==
5390 11:47:08.458124
5391 11:47:08.461290
5392 11:47:08.461391 TX Vref Scan disable
5393 11:47:08.464822 == TX Byte 0 ==
5394 11:47:08.468163 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5395 11:47:08.471332 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5396 11:47:08.474604 == TX Byte 1 ==
5397 11:47:08.477895 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5398 11:47:08.481045 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5399 11:47:08.481148 ==
5400 11:47:08.484250 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 11:47:08.490807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 11:47:08.490894 ==
5403 11:47:08.490961
5404 11:47:08.491021
5405 11:47:08.491080 TX Vref Scan disable
5406 11:47:08.495168 == TX Byte 0 ==
5407 11:47:08.499024 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5408 11:47:08.505490 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5409 11:47:08.505580 == TX Byte 1 ==
5410 11:47:08.508906 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5411 11:47:08.512106 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5412 11:47:08.515255
5413 11:47:08.515343 [DATLAT]
5414 11:47:08.515409 Freq=933, CH0 RK1
5415 11:47:08.515473
5416 11:47:08.519003 DATLAT Default: 0xb
5417 11:47:08.519083 0, 0xFFFF, sum = 0
5418 11:47:08.522346 1, 0xFFFF, sum = 0
5419 11:47:08.522429 2, 0xFFFF, sum = 0
5420 11:47:08.525327 3, 0xFFFF, sum = 0
5421 11:47:08.525409 4, 0xFFFF, sum = 0
5422 11:47:08.528381 5, 0xFFFF, sum = 0
5423 11:47:08.532303 6, 0xFFFF, sum = 0
5424 11:47:08.532391 7, 0xFFFF, sum = 0
5425 11:47:08.535373 8, 0xFFFF, sum = 0
5426 11:47:08.535458 9, 0xFFFF, sum = 0
5427 11:47:08.538499 10, 0x0, sum = 1
5428 11:47:08.538581 11, 0x0, sum = 2
5429 11:47:08.538647 12, 0x0, sum = 3
5430 11:47:08.542167 13, 0x0, sum = 4
5431 11:47:08.542258 best_step = 11
5432 11:47:08.542329
5433 11:47:08.545349 ==
5434 11:47:08.545448 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 11:47:08.552159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 11:47:08.552271 ==
5437 11:47:08.552379 RX Vref Scan: 0
5438 11:47:08.552482
5439 11:47:08.555476 RX Vref 0 -> 0, step: 1
5440 11:47:08.555588
5441 11:47:08.558741 RX Delay -53 -> 252, step: 4
5442 11:47:08.562194 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5443 11:47:08.568696 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5444 11:47:08.572021 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5445 11:47:08.575476 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5446 11:47:08.578176 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5447 11:47:08.581424 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5448 11:47:08.588344 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5449 11:47:08.591527 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5450 11:47:08.594892 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5451 11:47:08.598202 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5452 11:47:08.602079 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5453 11:47:08.605150 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5454 11:47:08.611697 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5455 11:47:08.615205 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5456 11:47:08.618306 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5457 11:47:08.621523 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5458 11:47:08.621611 ==
5459 11:47:08.625348 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 11:47:08.631777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 11:47:08.631866 ==
5462 11:47:08.631935 DQS Delay:
5463 11:47:08.634932 DQS0 = 0, DQS1 = 0
5464 11:47:08.635018 DQM Delay:
5465 11:47:08.635085 DQM0 = 104, DQM1 = 93
5466 11:47:08.638043 DQ Delay:
5467 11:47:08.641835 DQ0 =100, DQ1 =108, DQ2 =102, DQ3 =102
5468 11:47:08.644985 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5469 11:47:08.648069 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5470 11:47:08.651652 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5471 11:47:08.651740
5472 11:47:08.651808
5473 11:47:08.658025 [DQSOSCAuto] RK1, (LSB)MR18= 0x26fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5474 11:47:08.661385 CH0 RK1: MR19=504, MR18=26FE
5475 11:47:08.668097 CH0_RK1: MR19=0x504, MR18=0x26FE, DQSOSC=409, MR23=63, INC=64, DEC=43
5476 11:47:08.671444 [RxdqsGatingPostProcess] freq 933
5477 11:47:08.678038 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5478 11:47:08.681363 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 11:47:08.681449 best DQS1 dly(2T, 0.5T) = (0, 11)
5480 11:47:08.684617 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 11:47:08.688108 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5482 11:47:08.691770 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 11:47:08.694926 best DQS1 dly(2T, 0.5T) = (0, 10)
5484 11:47:08.698123 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 11:47:08.701313 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5486 11:47:08.704550 Pre-setting of DQS Precalculation
5487 11:47:08.711146 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5488 11:47:08.711253 ==
5489 11:47:08.714387 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 11:47:08.717653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 11:47:08.717738 ==
5492 11:47:08.724442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5493 11:47:08.728375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5494 11:47:08.732288 [CA 0] Center 36 (6~67) winsize 62
5495 11:47:08.735549 [CA 1] Center 37 (6~68) winsize 63
5496 11:47:08.738603 [CA 2] Center 35 (5~65) winsize 61
5497 11:47:08.742264 [CA 3] Center 34 (4~65) winsize 62
5498 11:47:08.744963 [CA 4] Center 34 (4~64) winsize 61
5499 11:47:08.748601 [CA 5] Center 33 (3~64) winsize 62
5500 11:47:08.748710
5501 11:47:08.751948 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5502 11:47:08.752061
5503 11:47:08.755069 [CATrainingPosCal] consider 1 rank data
5504 11:47:08.758867 u2DelayCellTimex100 = 270/100 ps
5505 11:47:08.762024 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5506 11:47:08.768475 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5507 11:47:08.771863 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5508 11:47:08.775212 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 11:47:08.778584 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5510 11:47:08.781841 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5511 11:47:08.781929
5512 11:47:08.785201 CA PerBit enable=1, Macro0, CA PI delay=33
5513 11:47:08.785319
5514 11:47:08.788422 [CBTSetCACLKResult] CA Dly = 33
5515 11:47:08.788509 CS Dly: 6 (0~37)
5516 11:47:08.791779 ==
5517 11:47:08.795152 Dram Type= 6, Freq= 0, CH_1, rank 1
5518 11:47:08.798451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 11:47:08.798538 ==
5520 11:47:08.801480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5521 11:47:08.808536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5522 11:47:08.811826 [CA 0] Center 36 (6~67) winsize 62
5523 11:47:08.815548 [CA 1] Center 37 (7~68) winsize 62
5524 11:47:08.818666 [CA 2] Center 35 (5~65) winsize 61
5525 11:47:08.822121 [CA 3] Center 34 (4~65) winsize 62
5526 11:47:08.825312 [CA 4] Center 34 (4~65) winsize 62
5527 11:47:08.828550 [CA 5] Center 33 (3~64) winsize 62
5528 11:47:08.828621
5529 11:47:08.831862 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5530 11:47:08.831933
5531 11:47:08.835257 [CATrainingPosCal] consider 2 rank data
5532 11:47:08.838459 u2DelayCellTimex100 = 270/100 ps
5533 11:47:08.841644 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 11:47:08.848651 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5535 11:47:08.852091 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5536 11:47:08.855177 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5537 11:47:08.858284 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5538 11:47:08.862053 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5539 11:47:08.862140
5540 11:47:08.865245 CA PerBit enable=1, Macro0, CA PI delay=33
5541 11:47:08.865330
5542 11:47:08.868383 [CBTSetCACLKResult] CA Dly = 33
5543 11:47:08.868468 CS Dly: 7 (0~40)
5544 11:47:08.872013
5545 11:47:08.875191 ----->DramcWriteLeveling(PI) begin...
5546 11:47:08.875278 ==
5547 11:47:08.878532 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 11:47:08.881794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 11:47:08.881886 ==
5550 11:47:08.885067 Write leveling (Byte 0): 26 => 26
5551 11:47:08.888439 Write leveling (Byte 1): 27 => 27
5552 11:47:08.891803 DramcWriteLeveling(PI) end<-----
5553 11:47:08.891888
5554 11:47:08.891956 ==
5555 11:47:08.895000 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 11:47:08.898376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 11:47:08.898463 ==
5558 11:47:08.901671 [Gating] SW mode calibration
5559 11:47:08.908123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5560 11:47:08.915307 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5561 11:47:08.918422 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 11:47:08.921596 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 11:47:08.928113 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 11:47:08.931276 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 11:47:08.934548 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 11:47:08.941277 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 11:47:08.944547 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 1)
5568 11:47:08.948264 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5569 11:47:08.954915 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 11:47:08.958013 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 11:47:08.961552 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 11:47:08.967939 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 11:47:08.971556 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 11:47:08.974699 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 11:47:08.977768 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
5576 11:47:08.984213 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5577 11:47:08.988128 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:47:08.990976 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:47:08.997528 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 11:47:09.000908 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 11:47:09.004712 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 11:47:09.011240 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5583 11:47:09.014568 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5584 11:47:09.017931 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5585 11:47:09.024390 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:47:09.027516 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:47:09.031170 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:47:09.037712 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:47:09.041000 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:47:09.044441 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:47:09.050941 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:47:09.054099 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:47:09.057437 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:47:09.064414 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:47:09.067498 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:47:09.070776 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:47:09.077457 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:47:09.080704 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:47:09.084497 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5600 11:47:09.090740 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5601 11:47:09.090831 Total UI for P1: 0, mck2ui 16
5602 11:47:09.094091 best dqsien dly found for B0: ( 1, 2, 24)
5603 11:47:09.100753 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 11:47:09.104109 Total UI for P1: 0, mck2ui 16
5605 11:47:09.107343 best dqsien dly found for B1: ( 1, 2, 28)
5606 11:47:09.110818 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5607 11:47:09.114078 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5608 11:47:09.114185
5609 11:47:09.117337 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5610 11:47:09.120737 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5611 11:47:09.123935 [Gating] SW calibration Done
5612 11:47:09.124037 ==
5613 11:47:09.127731 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 11:47:09.131071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 11:47:09.131180 ==
5616 11:47:09.133735 RX Vref Scan: 0
5617 11:47:09.133853
5618 11:47:09.137482 RX Vref 0 -> 0, step: 1
5619 11:47:09.137601
5620 11:47:09.137699 RX Delay -80 -> 252, step: 8
5621 11:47:09.144136 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5622 11:47:09.146968 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5623 11:47:09.150312 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5624 11:47:09.154290 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5625 11:47:09.156972 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5626 11:47:09.160338 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5627 11:47:09.167052 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5628 11:47:09.171080 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5629 11:47:09.173708 iDelay=208, Bit 8, Center 91 (8 ~ 175) 168
5630 11:47:09.176972 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5631 11:47:09.180706 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5632 11:47:09.183873 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5633 11:47:09.190788 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5634 11:47:09.193862 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5635 11:47:09.197092 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5636 11:47:09.200364 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5637 11:47:09.200470 ==
5638 11:47:09.204069 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 11:47:09.210806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 11:47:09.210920 ==
5641 11:47:09.211016 DQS Delay:
5642 11:47:09.213987 DQS0 = 0, DQS1 = 0
5643 11:47:09.214088 DQM Delay:
5644 11:47:09.214189 DQM0 = 103, DQM1 = 99
5645 11:47:09.217171 DQ Delay:
5646 11:47:09.220391 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5647 11:47:09.223749 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5648 11:47:09.227002 DQ8 =91, DQ9 =87, DQ10 =99, DQ11 =95
5649 11:47:09.230225 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5650 11:47:09.230326
5651 11:47:09.230416
5652 11:47:09.230510 ==
5653 11:47:09.233374 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 11:47:09.236703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 11:47:09.236815 ==
5656 11:47:09.236910
5657 11:47:09.236998
5658 11:47:09.240644 TX Vref Scan disable
5659 11:47:09.243768 == TX Byte 0 ==
5660 11:47:09.246910 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5661 11:47:09.250302 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5662 11:47:09.253399 == TX Byte 1 ==
5663 11:47:09.256708 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5664 11:47:09.259951 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5665 11:47:09.260080 ==
5666 11:47:09.263175 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 11:47:09.269974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 11:47:09.270083 ==
5669 11:47:09.270153
5670 11:47:09.270216
5671 11:47:09.270276 TX Vref Scan disable
5672 11:47:09.273897 == TX Byte 0 ==
5673 11:47:09.277036 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5674 11:47:09.280933 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5675 11:47:09.284334 == TX Byte 1 ==
5676 11:47:09.287537 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5677 11:47:09.290721 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5678 11:47:09.293985
5679 11:47:09.294105 [DATLAT]
5680 11:47:09.294202 Freq=933, CH1 RK0
5681 11:47:09.294301
5682 11:47:09.297032 DATLAT Default: 0xd
5683 11:47:09.297144 0, 0xFFFF, sum = 0
5684 11:47:09.300881 1, 0xFFFF, sum = 0
5685 11:47:09.300999 2, 0xFFFF, sum = 0
5686 11:47:09.304065 3, 0xFFFF, sum = 0
5687 11:47:09.304172 4, 0xFFFF, sum = 0
5688 11:47:09.307341 5, 0xFFFF, sum = 0
5689 11:47:09.310464 6, 0xFFFF, sum = 0
5690 11:47:09.310573 7, 0xFFFF, sum = 0
5691 11:47:09.314097 8, 0xFFFF, sum = 0
5692 11:47:09.314207 9, 0xFFFF, sum = 0
5693 11:47:09.317419 10, 0x0, sum = 1
5694 11:47:09.317531 11, 0x0, sum = 2
5695 11:47:09.317629 12, 0x0, sum = 3
5696 11:47:09.320608 13, 0x0, sum = 4
5697 11:47:09.320717 best_step = 11
5698 11:47:09.320818
5699 11:47:09.323965 ==
5700 11:47:09.324062 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 11:47:09.330766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 11:47:09.330877 ==
5703 11:47:09.330979 RX Vref Scan: 1
5704 11:47:09.331072
5705 11:47:09.334052 RX Vref 0 -> 0, step: 1
5706 11:47:09.334170
5707 11:47:09.337204 RX Delay -45 -> 252, step: 4
5708 11:47:09.337308
5709 11:47:09.340287 Set Vref, RX VrefLevel [Byte0]: 54
5710 11:47:09.343572 [Byte1]: 49
5711 11:47:09.343674
5712 11:47:09.346882 Final RX Vref Byte 0 = 54 to rank0
5713 11:47:09.350490 Final RX Vref Byte 1 = 49 to rank0
5714 11:47:09.353692 Final RX Vref Byte 0 = 54 to rank1
5715 11:47:09.357047 Final RX Vref Byte 1 = 49 to rank1==
5716 11:47:09.360217 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 11:47:09.363539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 11:47:09.363656 ==
5719 11:47:09.366786 DQS Delay:
5720 11:47:09.366903 DQS0 = 0, DQS1 = 0
5721 11:47:09.370109 DQM Delay:
5722 11:47:09.370215 DQM0 = 103, DQM1 = 99
5723 11:47:09.370317 DQ Delay:
5724 11:47:09.373565 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5725 11:47:09.376722 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5726 11:47:09.383366 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =96
5727 11:47:09.386637 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =108
5728 11:47:09.386742
5729 11:47:09.386828
5730 11:47:09.393611 [DQSOSCAuto] RK0, (LSB)MR18= 0x142b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5731 11:47:09.397017 CH1 RK0: MR19=505, MR18=142B
5732 11:47:09.403637 CH1_RK0: MR19=0x505, MR18=0x142B, DQSOSC=408, MR23=63, INC=65, DEC=43
5733 11:47:09.403742
5734 11:47:09.406760 ----->DramcWriteLeveling(PI) begin...
5735 11:47:09.406841 ==
5736 11:47:09.409833 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 11:47:09.413660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 11:47:09.413757 ==
5739 11:47:09.416759 Write leveling (Byte 0): 28 => 28
5740 11:47:09.419889 Write leveling (Byte 1): 28 => 28
5741 11:47:09.423083 DramcWriteLeveling(PI) end<-----
5742 11:47:09.423170
5743 11:47:09.423236 ==
5744 11:47:09.426734 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 11:47:09.430116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 11:47:09.430195 ==
5747 11:47:09.433378 [Gating] SW mode calibration
5748 11:47:09.439984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5749 11:47:09.446297 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5750 11:47:09.449655 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 11:47:09.456890 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 11:47:09.460029 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 11:47:09.463086 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 11:47:09.470337 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 11:47:09.473553 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5756 11:47:09.476895 0 14 24 | B1->B0 | 2f2f 3232 | 0 1 | (1 0) (1 0)
5757 11:47:09.480267 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
5758 11:47:09.486644 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 11:47:09.489951 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 11:47:09.493355 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 11:47:09.499711 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 11:47:09.503026 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 11:47:09.506368 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 11:47:09.512922 0 15 24 | B1->B0 | 3636 2d2d | 1 1 | (0 0) (0 0)
5765 11:47:09.516647 0 15 28 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
5766 11:47:09.519791 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 11:47:09.526460 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 11:47:09.529640 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 11:47:09.533322 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 11:47:09.539419 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 11:47:09.542737 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:47:09.546043 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5773 11:47:09.553164 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:47:09.556415 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:47:09.559723 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:47:09.566202 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:47:09.569827 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:47:09.573025 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:47:09.579489 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:47:09.582795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:47:09.586310 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:47:09.592704 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:47:09.596009 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:47:09.599433 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:47:09.606404 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:47:09.609684 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:47:09.612520 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5788 11:47:09.619499 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5789 11:47:09.622876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5790 11:47:09.625918 Total UI for P1: 0, mck2ui 16
5791 11:47:09.629863 best dqsien dly found for B0: ( 1, 2, 24)
5792 11:47:09.632999 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 11:47:09.636057 Total UI for P1: 0, mck2ui 16
5794 11:47:09.639297 best dqsien dly found for B1: ( 1, 2, 24)
5795 11:47:09.642417 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5796 11:47:09.646560 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5797 11:47:09.646647
5798 11:47:09.649216 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5799 11:47:09.652448 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5800 11:47:09.655891 [Gating] SW calibration Done
5801 11:47:09.655977 ==
5802 11:47:09.659457 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 11:47:09.666275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 11:47:09.666370 ==
5805 11:47:09.666438 RX Vref Scan: 0
5806 11:47:09.666502
5807 11:47:09.669583 RX Vref 0 -> 0, step: 1
5808 11:47:09.669669
5809 11:47:09.672711 RX Delay -80 -> 252, step: 8
5810 11:47:09.675798 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5811 11:47:09.679639 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5812 11:47:09.682786 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5813 11:47:09.685993 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5814 11:47:09.689292 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5815 11:47:09.695939 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5816 11:47:09.699168 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5817 11:47:09.702451 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5818 11:47:09.705735 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5819 11:47:09.709039 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5820 11:47:09.712429 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5821 11:47:09.718975 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5822 11:47:09.722740 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5823 11:47:09.725922 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5824 11:47:09.729292 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5825 11:47:09.732623 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5826 11:47:09.735660 ==
5827 11:47:09.739498 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 11:47:09.742622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 11:47:09.742735 ==
5830 11:47:09.742839 DQS Delay:
5831 11:47:09.745712 DQS0 = 0, DQS1 = 0
5832 11:47:09.745826 DQM Delay:
5833 11:47:09.749067 DQM0 = 102, DQM1 = 98
5834 11:47:09.749178 DQ Delay:
5835 11:47:09.752380 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5836 11:47:09.755691 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5837 11:47:09.759024 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5838 11:47:09.762354 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5839 11:47:09.762462
5840 11:47:09.762562
5841 11:47:09.762659 ==
5842 11:47:09.765423 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 11:47:09.768618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 11:47:09.771970 ==
5845 11:47:09.772097
5846 11:47:09.772210
5847 11:47:09.772308 TX Vref Scan disable
5848 11:47:09.775238 == TX Byte 0 ==
5849 11:47:09.779304 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5850 11:47:09.782440 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5851 11:47:09.785552 == TX Byte 1 ==
5852 11:47:09.788728 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5853 11:47:09.791922 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5854 11:47:09.795797 ==
5855 11:47:09.795876 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 11:47:09.802562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 11:47:09.802672 ==
5858 11:47:09.802767
5859 11:47:09.802856
5860 11:47:09.805691 TX Vref Scan disable
5861 11:47:09.805760 == TX Byte 0 ==
5862 11:47:09.812235 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5863 11:47:09.815534 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5864 11:47:09.815653 == TX Byte 1 ==
5865 11:47:09.822480 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5866 11:47:09.825055 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5867 11:47:09.825174
5868 11:47:09.825244 [DATLAT]
5869 11:47:09.828739 Freq=933, CH1 RK1
5870 11:47:09.828873
5871 11:47:09.828974 DATLAT Default: 0xb
5872 11:47:09.832106 0, 0xFFFF, sum = 0
5873 11:47:09.832221 1, 0xFFFF, sum = 0
5874 11:47:09.835318 2, 0xFFFF, sum = 0
5875 11:47:09.835440 3, 0xFFFF, sum = 0
5876 11:47:09.838657 4, 0xFFFF, sum = 0
5877 11:47:09.838785 5, 0xFFFF, sum = 0
5878 11:47:09.842019 6, 0xFFFF, sum = 0
5879 11:47:09.842134 7, 0xFFFF, sum = 0
5880 11:47:09.845104 8, 0xFFFF, sum = 0
5881 11:47:09.845225 9, 0xFFFF, sum = 0
5882 11:47:09.848319 10, 0x0, sum = 1
5883 11:47:09.848443 11, 0x0, sum = 2
5884 11:47:09.852089 12, 0x0, sum = 3
5885 11:47:09.852201 13, 0x0, sum = 4
5886 11:47:09.855102 best_step = 11
5887 11:47:09.855188
5888 11:47:09.855255 ==
5889 11:47:09.858572 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 11:47:09.861821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 11:47:09.861908 ==
5892 11:47:09.865043 RX Vref Scan: 0
5893 11:47:09.865129
5894 11:47:09.865197 RX Vref 0 -> 0, step: 1
5895 11:47:09.865259
5896 11:47:09.868266 RX Delay -45 -> 252, step: 4
5897 11:47:09.875278 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5898 11:47:09.878593 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5899 11:47:09.881915 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5900 11:47:09.885244 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5901 11:47:09.888528 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5902 11:47:09.895250 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5903 11:47:09.899085 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5904 11:47:09.902194 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5905 11:47:09.905622 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5906 11:47:09.908716 iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176
5907 11:47:09.915275 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5908 11:47:09.918519 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5909 11:47:09.921740 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5910 11:47:09.925011 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5911 11:47:09.928349 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5912 11:47:09.934919 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5913 11:47:09.935011 ==
5914 11:47:09.938361 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 11:47:09.941577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 11:47:09.941671 ==
5917 11:47:09.941740 DQS Delay:
5918 11:47:09.945008 DQS0 = 0, DQS1 = 0
5919 11:47:09.945094 DQM Delay:
5920 11:47:09.948322 DQM0 = 105, DQM1 = 98
5921 11:47:09.948407 DQ Delay:
5922 11:47:09.952100 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5923 11:47:09.955295 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5924 11:47:09.958554 DQ8 =90, DQ9 =86, DQ10 =98, DQ11 =92
5925 11:47:09.961741 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5926 11:47:09.961827
5927 11:47:09.961895
5928 11:47:09.971639 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5929 11:47:09.974914 CH1 RK1: MR19=505, MR18=2E02
5930 11:47:09.978096 CH1_RK1: MR19=0x505, MR18=0x2E02, DQSOSC=407, MR23=63, INC=65, DEC=43
5931 11:47:09.981327 [RxdqsGatingPostProcess] freq 933
5932 11:47:09.987923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5933 11:47:09.991292 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 11:47:09.994626 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 11:47:09.998376 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 11:47:10.001499 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 11:47:10.004489 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 11:47:10.008247 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 11:47:10.011360 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 11:47:10.014617 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 11:47:10.018392 Pre-setting of DQS Precalculation
5942 11:47:10.021570 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5943 11:47:10.028252 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5944 11:47:10.034774 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5945 11:47:10.034895
5946 11:47:10.035000
5947 11:47:10.037915 [Calibration Summary] 1866 Mbps
5948 11:47:10.041252 CH 0, Rank 0
5949 11:47:10.041378 SW Impedance : PASS
5950 11:47:10.044580 DUTY Scan : NO K
5951 11:47:10.048116 ZQ Calibration : PASS
5952 11:47:10.048243 Jitter Meter : NO K
5953 11:47:10.051363 CBT Training : PASS
5954 11:47:10.051473 Write leveling : PASS
5955 11:47:10.054533 RX DQS gating : PASS
5956 11:47:10.058290 RX DQ/DQS(RDDQC) : PASS
5957 11:47:10.058375 TX DQ/DQS : PASS
5958 11:47:10.061469 RX DATLAT : PASS
5959 11:47:10.064624 RX DQ/DQS(Engine): PASS
5960 11:47:10.064759 TX OE : NO K
5961 11:47:10.067884 All Pass.
5962 11:47:10.067967
5963 11:47:10.068076 CH 0, Rank 1
5964 11:47:10.071258 SW Impedance : PASS
5965 11:47:10.071365 DUTY Scan : NO K
5966 11:47:10.074636 ZQ Calibration : PASS
5967 11:47:10.077980 Jitter Meter : NO K
5968 11:47:10.078085 CBT Training : PASS
5969 11:47:10.081104 Write leveling : PASS
5970 11:47:10.084822 RX DQS gating : PASS
5971 11:47:10.084924 RX DQ/DQS(RDDQC) : PASS
5972 11:47:10.087866 TX DQ/DQS : PASS
5973 11:47:10.091032 RX DATLAT : PASS
5974 11:47:10.091143 RX DQ/DQS(Engine): PASS
5975 11:47:10.094354 TX OE : NO K
5976 11:47:10.094461 All Pass.
5977 11:47:10.094555
5978 11:47:10.097730 CH 1, Rank 0
5979 11:47:10.097836 SW Impedance : PASS
5980 11:47:10.101126 DUTY Scan : NO K
5981 11:47:10.104351 ZQ Calibration : PASS
5982 11:47:10.104454 Jitter Meter : NO K
5983 11:47:10.107603 CBT Training : PASS
5984 11:47:10.107709 Write leveling : PASS
5985 11:47:10.111167 RX DQS gating : PASS
5986 11:47:10.114300 RX DQ/DQS(RDDQC) : PASS
5987 11:47:10.114410 TX DQ/DQS : PASS
5988 11:47:10.117926 RX DATLAT : PASS
5989 11:47:10.121021 RX DQ/DQS(Engine): PASS
5990 11:47:10.121103 TX OE : NO K
5991 11:47:10.124276 All Pass.
5992 11:47:10.124400
5993 11:47:10.124505 CH 1, Rank 1
5994 11:47:10.128112 SW Impedance : PASS
5995 11:47:10.128201 DUTY Scan : NO K
5996 11:47:10.131371 ZQ Calibration : PASS
5997 11:47:10.134765 Jitter Meter : NO K
5998 11:47:10.134844 CBT Training : PASS
5999 11:47:10.137983 Write leveling : PASS
6000 11:47:10.141357 RX DQS gating : PASS
6001 11:47:10.141451 RX DQ/DQS(RDDQC) : PASS
6002 11:47:10.144569 TX DQ/DQS : PASS
6003 11:47:10.147938 RX DATLAT : PASS
6004 11:47:10.148017 RX DQ/DQS(Engine): PASS
6005 11:47:10.151247 TX OE : NO K
6006 11:47:10.151337 All Pass.
6007 11:47:10.151403
6008 11:47:10.154029 DramC Write-DBI off
6009 11:47:10.157930 PER_BANK_REFRESH: Hybrid Mode
6010 11:47:10.158018 TX_TRACKING: ON
6011 11:47:10.167430 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6012 11:47:10.171288 [FAST_K] Save calibration result to emmc
6013 11:47:10.174319 dramc_set_vcore_voltage set vcore to 650000
6014 11:47:10.177675 Read voltage for 400, 6
6015 11:47:10.177808 Vio18 = 0
6016 11:47:10.177914 Vcore = 650000
6017 11:47:10.181023 Vdram = 0
6018 11:47:10.181131 Vddq = 0
6019 11:47:10.181244 Vmddr = 0
6020 11:47:10.187458 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6021 11:47:10.190573 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6022 11:47:10.193767 MEM_TYPE=3, freq_sel=20
6023 11:47:10.197589 sv_algorithm_assistance_LP4_800
6024 11:47:10.200769 ============ PULL DRAM RESETB DOWN ============
6025 11:47:10.204189 ========== PULL DRAM RESETB DOWN end =========
6026 11:47:10.210745 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6027 11:47:10.214040 ===================================
6028 11:47:10.214135 LPDDR4 DRAM CONFIGURATION
6029 11:47:10.217115 ===================================
6030 11:47:10.220303 EX_ROW_EN[0] = 0x0
6031 11:47:10.223663 EX_ROW_EN[1] = 0x0
6032 11:47:10.223751 LP4Y_EN = 0x0
6033 11:47:10.227308 WORK_FSP = 0x0
6034 11:47:10.227395 WL = 0x2
6035 11:47:10.230399 RL = 0x2
6036 11:47:10.230486 BL = 0x2
6037 11:47:10.233924 RPST = 0x0
6038 11:47:10.234007 RD_PRE = 0x0
6039 11:47:10.237035 WR_PRE = 0x1
6040 11:47:10.237133 WR_PST = 0x0
6041 11:47:10.240355 DBI_WR = 0x0
6042 11:47:10.240441 DBI_RD = 0x0
6043 11:47:10.243773 OTF = 0x1
6044 11:47:10.247049 ===================================
6045 11:47:10.250182 ===================================
6046 11:47:10.250267 ANA top config
6047 11:47:10.253510 ===================================
6048 11:47:10.256765 DLL_ASYNC_EN = 0
6049 11:47:10.260167 ALL_SLAVE_EN = 1
6050 11:47:10.263364 NEW_RANK_MODE = 1
6051 11:47:10.263458 DLL_IDLE_MODE = 1
6052 11:47:10.266783 LP45_APHY_COMB_EN = 1
6053 11:47:10.270011 TX_ODT_DIS = 1
6054 11:47:10.273656 NEW_8X_MODE = 1
6055 11:47:10.276700 ===================================
6056 11:47:10.280329 ===================================
6057 11:47:10.283517 data_rate = 800
6058 11:47:10.283606 CKR = 1
6059 11:47:10.286914 DQ_P2S_RATIO = 4
6060 11:47:10.290183 ===================================
6061 11:47:10.293317 CA_P2S_RATIO = 4
6062 11:47:10.297024 DQ_CA_OPEN = 0
6063 11:47:10.300160 DQ_SEMI_OPEN = 1
6064 11:47:10.303417 CA_SEMI_OPEN = 1
6065 11:47:10.303526 CA_FULL_RATE = 0
6066 11:47:10.306695 DQ_CKDIV4_EN = 0
6067 11:47:10.310010 CA_CKDIV4_EN = 1
6068 11:47:10.313294 CA_PREDIV_EN = 0
6069 11:47:10.316566 PH8_DLY = 0
6070 11:47:10.320025 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6071 11:47:10.320133 DQ_AAMCK_DIV = 0
6072 11:47:10.323069 CA_AAMCK_DIV = 0
6073 11:47:10.326358 CA_ADMCK_DIV = 4
6074 11:47:10.330210 DQ_TRACK_CA_EN = 0
6075 11:47:10.333515 CA_PICK = 800
6076 11:47:10.336526 CA_MCKIO = 400
6077 11:47:10.336635 MCKIO_SEMI = 400
6078 11:47:10.340109 PLL_FREQ = 3016
6079 11:47:10.343246 DQ_UI_PI_RATIO = 32
6080 11:47:10.346434 CA_UI_PI_RATIO = 32
6081 11:47:10.349738 ===================================
6082 11:47:10.352941 ===================================
6083 11:47:10.356905 memory_type:LPDDR4
6084 11:47:10.356990 GP_NUM : 10
6085 11:47:10.360044 SRAM_EN : 1
6086 11:47:10.363374 MD32_EN : 0
6087 11:47:10.366662 ===================================
6088 11:47:10.366740 [ANA_INIT] >>>>>>>>>>>>>>
6089 11:47:10.370003 <<<<<< [CONFIGURE PHASE]: ANA_TX
6090 11:47:10.373493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6091 11:47:10.376715 ===================================
6092 11:47:10.379853 data_rate = 800,PCW = 0X7400
6093 11:47:10.383169 ===================================
6094 11:47:10.386400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6095 11:47:10.393356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 11:47:10.402901 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 11:47:10.409979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6098 11:47:10.413245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6099 11:47:10.416005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6100 11:47:10.416085 [ANA_INIT] flow start
6101 11:47:10.419956 [ANA_INIT] PLL >>>>>>>>
6102 11:47:10.423257 [ANA_INIT] PLL <<<<<<<<
6103 11:47:10.423366 [ANA_INIT] MIDPI >>>>>>>>
6104 11:47:10.426457 [ANA_INIT] MIDPI <<<<<<<<
6105 11:47:10.429906 [ANA_INIT] DLL >>>>>>>>
6106 11:47:10.430012 [ANA_INIT] flow end
6107 11:47:10.436312 ============ LP4 DIFF to SE enter ============
6108 11:47:10.439518 ============ LP4 DIFF to SE exit ============
6109 11:47:10.439641 [ANA_INIT] <<<<<<<<<<<<<
6110 11:47:10.442647 [Flow] Enable top DCM control >>>>>
6111 11:47:10.446507 [Flow] Enable top DCM control <<<<<
6112 11:47:10.449537 Enable DLL master slave shuffle
6113 11:47:10.455976 ==============================================================
6114 11:47:10.459674 Gating Mode config
6115 11:47:10.462736 ==============================================================
6116 11:47:10.466040 Config description:
6117 11:47:10.476101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6118 11:47:10.482717 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6119 11:47:10.486009 SELPH_MODE 0: By rank 1: By Phase
6120 11:47:10.492498 ==============================================================
6121 11:47:10.495598 GAT_TRACK_EN = 0
6122 11:47:10.498929 RX_GATING_MODE = 2
6123 11:47:10.502195 RX_GATING_TRACK_MODE = 2
6124 11:47:10.502283 SELPH_MODE = 1
6125 11:47:10.505565 PICG_EARLY_EN = 1
6126 11:47:10.508948 VALID_LAT_VALUE = 1
6127 11:47:10.515804 ==============================================================
6128 11:47:10.519140 Enter into Gating configuration >>>>
6129 11:47:10.522527 Exit from Gating configuration <<<<
6130 11:47:10.525710 Enter into DVFS_PRE_config >>>>>
6131 11:47:10.535703 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6132 11:47:10.538968 Exit from DVFS_PRE_config <<<<<
6133 11:47:10.542374 Enter into PICG configuration >>>>
6134 11:47:10.545766 Exit from PICG configuration <<<<
6135 11:47:10.548968 [RX_INPUT] configuration >>>>>
6136 11:47:10.552157 [RX_INPUT] configuration <<<<<
6137 11:47:10.555160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6138 11:47:10.562446 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6139 11:47:10.568699 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 11:47:10.575693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 11:47:10.582385 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 11:47:10.585810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 11:47:10.591629 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6144 11:47:10.595600 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6145 11:47:10.598950 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6146 11:47:10.602191 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6147 11:47:10.608724 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6148 11:47:10.612122 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 11:47:10.615548 ===================================
6150 11:47:10.618550 LPDDR4 DRAM CONFIGURATION
6151 11:47:10.621631 ===================================
6152 11:47:10.621723 EX_ROW_EN[0] = 0x0
6153 11:47:10.625016 EX_ROW_EN[1] = 0x0
6154 11:47:10.625120 LP4Y_EN = 0x0
6155 11:47:10.628313 WORK_FSP = 0x0
6156 11:47:10.628400 WL = 0x2
6157 11:47:10.631780 RL = 0x2
6158 11:47:10.631885 BL = 0x2
6159 11:47:10.634996 RPST = 0x0
6160 11:47:10.635082 RD_PRE = 0x0
6161 11:47:10.638317 WR_PRE = 0x1
6162 11:47:10.638403 WR_PST = 0x0
6163 11:47:10.641711 DBI_WR = 0x0
6164 11:47:10.641796 DBI_RD = 0x0
6165 11:47:10.645091 OTF = 0x1
6166 11:47:10.648460 ===================================
6167 11:47:10.651963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6168 11:47:10.655241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6169 11:47:10.661695 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 11:47:10.664721 ===================================
6171 11:47:10.668479 LPDDR4 DRAM CONFIGURATION
6172 11:47:10.671583 ===================================
6173 11:47:10.671700 EX_ROW_EN[0] = 0x10
6174 11:47:10.674878 EX_ROW_EN[1] = 0x0
6175 11:47:10.674997 LP4Y_EN = 0x0
6176 11:47:10.678629 WORK_FSP = 0x0
6177 11:47:10.678745 WL = 0x2
6178 11:47:10.681987 RL = 0x2
6179 11:47:10.682098 BL = 0x2
6180 11:47:10.684718 RPST = 0x0
6181 11:47:10.684833 RD_PRE = 0x0
6182 11:47:10.688107 WR_PRE = 0x1
6183 11:47:10.688218 WR_PST = 0x0
6184 11:47:10.691277 DBI_WR = 0x0
6185 11:47:10.691385 DBI_RD = 0x0
6186 11:47:10.694632 OTF = 0x1
6187 11:47:10.697934 ===================================
6188 11:47:10.704501 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6189 11:47:10.708645 nWR fixed to 30
6190 11:47:10.711184 [ModeRegInit_LP4] CH0 RK0
6191 11:47:10.711294 [ModeRegInit_LP4] CH0 RK1
6192 11:47:10.714491 [ModeRegInit_LP4] CH1 RK0
6193 11:47:10.717762 [ModeRegInit_LP4] CH1 RK1
6194 11:47:10.717880 match AC timing 19
6195 11:47:10.724306 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6196 11:47:10.728166 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6197 11:47:10.731196 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6198 11:47:10.738045 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6199 11:47:10.741307 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6200 11:47:10.741417 ==
6201 11:47:10.744617 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 11:47:10.747924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 11:47:10.748003 ==
6204 11:47:10.754662 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 11:47:10.761375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6206 11:47:10.764707 [CA 0] Center 36 (8~64) winsize 57
6207 11:47:10.768059 [CA 1] Center 36 (8~64) winsize 57
6208 11:47:10.771285 [CA 2] Center 36 (8~64) winsize 57
6209 11:47:10.771401 [CA 3] Center 36 (8~64) winsize 57
6210 11:47:10.774747 [CA 4] Center 36 (8~64) winsize 57
6211 11:47:10.777917 [CA 5] Center 36 (8~64) winsize 57
6212 11:47:10.778041
6213 11:47:10.784679 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6214 11:47:10.784793
6215 11:47:10.787913 [CATrainingPosCal] consider 1 rank data
6216 11:47:10.790953 u2DelayCellTimex100 = 270/100 ps
6217 11:47:10.794244 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:47:10.797450 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 11:47:10.800738 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 11:47:10.804068 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 11:47:10.808002 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 11:47:10.811247 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:47:10.811370
6224 11:47:10.813932 CA PerBit enable=1, Macro0, CA PI delay=36
6225 11:47:10.814042
6226 11:47:10.817734 [CBTSetCACLKResult] CA Dly = 36
6227 11:47:10.820964 CS Dly: 1 (0~32)
6228 11:47:10.821077 ==
6229 11:47:10.824205 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 11:47:10.827613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 11:47:10.827737 ==
6232 11:47:10.834056 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 11:47:10.837383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6234 11:47:10.840700 [CA 0] Center 36 (8~64) winsize 57
6235 11:47:10.843763 [CA 1] Center 36 (8~64) winsize 57
6236 11:47:10.847301 [CA 2] Center 36 (8~64) winsize 57
6237 11:47:10.850577 [CA 3] Center 36 (8~64) winsize 57
6238 11:47:10.853906 [CA 4] Center 36 (8~64) winsize 57
6239 11:47:10.857313 [CA 5] Center 36 (8~64) winsize 57
6240 11:47:10.857428
6241 11:47:10.860585 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6242 11:47:10.860697
6243 11:47:10.863958 [CATrainingPosCal] consider 2 rank data
6244 11:47:10.867328 u2DelayCellTimex100 = 270/100 ps
6245 11:47:10.870695 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:47:10.873997 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 11:47:10.880463 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:47:10.884172 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:47:10.887350 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:47:10.890347 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:47:10.890458
6252 11:47:10.894053 CA PerBit enable=1, Macro0, CA PI delay=36
6253 11:47:10.894175
6254 11:47:10.897144 [CBTSetCACLKResult] CA Dly = 36
6255 11:47:10.897254 CS Dly: 1 (0~32)
6256 11:47:10.897355
6257 11:47:10.900486 ----->DramcWriteLeveling(PI) begin...
6258 11:47:10.904280 ==
6259 11:47:10.904407 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 11:47:10.910920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 11:47:10.911036 ==
6262 11:47:10.914255 Write leveling (Byte 0): 40 => 8
6263 11:47:10.917630 Write leveling (Byte 1): 40 => 8
6264 11:47:10.917740 DramcWriteLeveling(PI) end<-----
6265 11:47:10.917836
6266 11:47:10.920991 ==
6267 11:47:10.923994 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 11:47:10.927235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 11:47:10.927341 ==
6270 11:47:10.930848 [Gating] SW mode calibration
6271 11:47:10.937419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 11:47:10.940578 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6273 11:47:10.947258 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 11:47:10.950394 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 11:47:10.954262 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 11:47:10.960609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 11:47:10.964028 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 11:47:10.967171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 11:47:10.974022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 11:47:10.977281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 11:47:10.980629 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 11:47:10.983930 Total UI for P1: 0, mck2ui 16
6283 11:47:10.986901 best dqsien dly found for B0: ( 0, 14, 24)
6284 11:47:10.990770 Total UI for P1: 0, mck2ui 16
6285 11:47:10.993935 best dqsien dly found for B1: ( 0, 14, 24)
6286 11:47:10.997113 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6287 11:47:11.000196 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6288 11:47:11.000306
6289 11:47:11.006792 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 11:47:11.010609 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 11:47:11.010720 [Gating] SW calibration Done
6292 11:47:11.013760 ==
6293 11:47:11.016910 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 11:47:11.020163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 11:47:11.020249 ==
6296 11:47:11.020342 RX Vref Scan: 0
6297 11:47:11.020435
6298 11:47:11.023570 RX Vref 0 -> 0, step: 1
6299 11:47:11.023673
6300 11:47:11.026929 RX Delay -410 -> 252, step: 16
6301 11:47:11.030563 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6302 11:47:11.033890 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6303 11:47:11.040528 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6304 11:47:11.044030 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6305 11:47:11.047099 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6306 11:47:11.050359 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6307 11:47:11.057066 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6308 11:47:11.060214 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6309 11:47:11.063951 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6310 11:47:11.067022 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6311 11:47:11.073581 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6312 11:47:11.077098 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6313 11:47:11.080359 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6314 11:47:11.083756 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6315 11:47:11.090395 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6316 11:47:11.093140 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6317 11:47:11.093247 ==
6318 11:47:11.096327 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 11:47:11.100342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 11:47:11.100452 ==
6321 11:47:11.103539 DQS Delay:
6322 11:47:11.103649 DQS0 = 19, DQS1 = 27
6323 11:47:11.106807 DQM Delay:
6324 11:47:11.106910 DQM0 = 5, DQM1 = 7
6325 11:47:11.107001 DQ Delay:
6326 11:47:11.109970 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6327 11:47:11.113215 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6328 11:47:11.116757 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6329 11:47:11.119837 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6330 11:47:11.119920
6331 11:47:11.119991
6332 11:47:11.120055 ==
6333 11:47:11.122979 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 11:47:11.126670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 11:47:11.130043 ==
6336 11:47:11.130118
6337 11:47:11.130179
6338 11:47:11.130238 TX Vref Scan disable
6339 11:47:11.133432 == TX Byte 0 ==
6340 11:47:11.136633 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 11:47:11.139812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 11:47:11.142921 == TX Byte 1 ==
6343 11:47:11.146222 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 11:47:11.149510 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 11:47:11.149613 ==
6346 11:47:11.153013 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 11:47:11.156305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 11:47:11.159621 ==
6349 11:47:11.159715
6350 11:47:11.159815
6351 11:47:11.159906 TX Vref Scan disable
6352 11:47:11.163080 == TX Byte 0 ==
6353 11:47:11.166153 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 11:47:11.169452 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 11:47:11.172586 == TX Byte 1 ==
6356 11:47:11.176265 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 11:47:11.179459 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 11:47:11.179565
6359 11:47:11.182783 [DATLAT]
6360 11:47:11.182886 Freq=400, CH0 RK0
6361 11:47:11.182986
6362 11:47:11.186261 DATLAT Default: 0xf
6363 11:47:11.186365 0, 0xFFFF, sum = 0
6364 11:47:11.189494 1, 0xFFFF, sum = 0
6365 11:47:11.189628 2, 0xFFFF, sum = 0
6366 11:47:11.192909 3, 0xFFFF, sum = 0
6367 11:47:11.193042 4, 0xFFFF, sum = 0
6368 11:47:11.196269 5, 0xFFFF, sum = 0
6369 11:47:11.196398 6, 0xFFFF, sum = 0
6370 11:47:11.199607 7, 0xFFFF, sum = 0
6371 11:47:11.199734 8, 0xFFFF, sum = 0
6372 11:47:11.203114 9, 0xFFFF, sum = 0
6373 11:47:11.203233 10, 0xFFFF, sum = 0
6374 11:47:11.206267 11, 0xFFFF, sum = 0
6375 11:47:11.206377 12, 0xFFFF, sum = 0
6376 11:47:11.209536 13, 0x0, sum = 1
6377 11:47:11.209668 14, 0x0, sum = 2
6378 11:47:11.212729 15, 0x0, sum = 3
6379 11:47:11.212866 16, 0x0, sum = 4
6380 11:47:11.215880 best_step = 14
6381 11:47:11.216012
6382 11:47:11.216113 ==
6383 11:47:11.219608 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 11:47:11.222716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 11:47:11.222828 ==
6386 11:47:11.226263 RX Vref Scan: 1
6387 11:47:11.226344
6388 11:47:11.226410 RX Vref 0 -> 0, step: 1
6389 11:47:11.226471
6390 11:47:11.229466 RX Delay -295 -> 252, step: 8
6391 11:47:11.229535
6392 11:47:11.232678 Set Vref, RX VrefLevel [Byte0]: 55
6393 11:47:11.236030 [Byte1]: 48
6394 11:47:11.240758
6395 11:47:11.240889 Final RX Vref Byte 0 = 55 to rank0
6396 11:47:11.243937 Final RX Vref Byte 1 = 48 to rank0
6397 11:47:11.247151 Final RX Vref Byte 0 = 55 to rank1
6398 11:47:11.250189 Final RX Vref Byte 1 = 48 to rank1==
6399 11:47:11.254174 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 11:47:11.260729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 11:47:11.260853 ==
6402 11:47:11.260970 DQS Delay:
6403 11:47:11.261071 DQS0 = 28, DQS1 = 36
6404 11:47:11.263971 DQM Delay:
6405 11:47:11.264083 DQM0 = 10, DQM1 = 12
6406 11:47:11.267394 DQ Delay:
6407 11:47:11.270632 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6408 11:47:11.270748 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =12
6409 11:47:11.273878 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6410 11:47:11.277160 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6411 11:47:11.277280
6412 11:47:11.280472
6413 11:47:11.287402 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6414 11:47:11.290747 CH0 RK0: MR19=C0C, MR18=CBB8
6415 11:47:11.297246 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6416 11:47:11.297386 ==
6417 11:47:11.300596 Dram Type= 6, Freq= 0, CH_0, rank 1
6418 11:47:11.303999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 11:47:11.304084 ==
6420 11:47:11.307425 [Gating] SW mode calibration
6421 11:47:11.314055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6422 11:47:11.316763 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6423 11:47:11.324137 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 11:47:11.327099 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 11:47:11.330204 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 11:47:11.336866 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 11:47:11.340522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 11:47:11.343615 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 11:47:11.350352 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 11:47:11.353543 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 11:47:11.357381 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 11:47:11.360620 Total UI for P1: 0, mck2ui 16
6433 11:47:11.364029 best dqsien dly found for B0: ( 0, 14, 24)
6434 11:47:11.367406 Total UI for P1: 0, mck2ui 16
6435 11:47:11.370033 best dqsien dly found for B1: ( 0, 14, 24)
6436 11:47:11.374062 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6437 11:47:11.377166 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6438 11:47:11.377258
6439 11:47:11.383793 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 11:47:11.386980 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 11:47:11.390033 [Gating] SW calibration Done
6442 11:47:11.390140 ==
6443 11:47:11.393253 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 11:47:11.396547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 11:47:11.396670 ==
6446 11:47:11.396784 RX Vref Scan: 0
6447 11:47:11.396879
6448 11:47:11.400032 RX Vref 0 -> 0, step: 1
6449 11:47:11.400163
6450 11:47:11.403314 RX Delay -410 -> 252, step: 16
6451 11:47:11.406572 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6452 11:47:11.413697 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6453 11:47:11.416955 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6454 11:47:11.420291 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6455 11:47:11.423612 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6456 11:47:11.430309 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6457 11:47:11.433473 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6458 11:47:11.436639 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6459 11:47:11.440257 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6460 11:47:11.443424 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6461 11:47:11.449929 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6462 11:47:11.453692 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6463 11:47:11.456985 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6464 11:47:11.460226 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6465 11:47:11.466661 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6466 11:47:11.470422 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6467 11:47:11.470509 ==
6468 11:47:11.473192 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 11:47:11.476477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 11:47:11.476584 ==
6471 11:47:11.480279 DQS Delay:
6472 11:47:11.480370 DQS0 = 19, DQS1 = 35
6473 11:47:11.483379 DQM Delay:
6474 11:47:11.483467 DQM0 = 5, DQM1 = 12
6475 11:47:11.483550 DQ Delay:
6476 11:47:11.486753 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6477 11:47:11.490091 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6478 11:47:11.493346 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6479 11:47:11.496456 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6480 11:47:11.496572
6481 11:47:11.496666
6482 11:47:11.496769 ==
6483 11:47:11.500273 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 11:47:11.506731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 11:47:11.506844 ==
6486 11:47:11.506968
6487 11:47:11.507074
6488 11:47:11.507171 TX Vref Scan disable
6489 11:47:11.510172 == TX Byte 0 ==
6490 11:47:11.513330 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6491 11:47:11.516582 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6492 11:47:11.519780 == TX Byte 1 ==
6493 11:47:11.523038 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6494 11:47:11.526346 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6495 11:47:11.526464 ==
6496 11:47:11.529713 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 11:47:11.536267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 11:47:11.536402 ==
6499 11:47:11.536513
6500 11:47:11.536636
6501 11:47:11.536742 TX Vref Scan disable
6502 11:47:11.539575 == TX Byte 0 ==
6503 11:47:11.543347 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6504 11:47:11.546581 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6505 11:47:11.549582 == TX Byte 1 ==
6506 11:47:11.553447 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6507 11:47:11.556687 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6508 11:47:11.556800
6509 11:47:11.559894 [DATLAT]
6510 11:47:11.559981 Freq=400, CH0 RK1
6511 11:47:11.560047
6512 11:47:11.563045 DATLAT Default: 0xe
6513 11:47:11.563131 0, 0xFFFF, sum = 0
6514 11:47:11.566087 1, 0xFFFF, sum = 0
6515 11:47:11.566173 2, 0xFFFF, sum = 0
6516 11:47:11.569590 3, 0xFFFF, sum = 0
6517 11:47:11.569675 4, 0xFFFF, sum = 0
6518 11:47:11.573368 5, 0xFFFF, sum = 0
6519 11:47:11.573454 6, 0xFFFF, sum = 0
6520 11:47:11.576667 7, 0xFFFF, sum = 0
6521 11:47:11.576783 8, 0xFFFF, sum = 0
6522 11:47:11.579755 9, 0xFFFF, sum = 0
6523 11:47:11.579866 10, 0xFFFF, sum = 0
6524 11:47:11.583029 11, 0xFFFF, sum = 0
6525 11:47:11.585889 12, 0xFFFF, sum = 0
6526 11:47:11.585974 13, 0x0, sum = 1
6527 11:47:11.589486 14, 0x0, sum = 2
6528 11:47:11.589573 15, 0x0, sum = 3
6529 11:47:11.589641 16, 0x0, sum = 4
6530 11:47:11.592790 best_step = 14
6531 11:47:11.592884
6532 11:47:11.592951 ==
6533 11:47:11.596292 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 11:47:11.599476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 11:47:11.599579 ==
6536 11:47:11.602741 RX Vref Scan: 0
6537 11:47:11.602850
6538 11:47:11.602948 RX Vref 0 -> 0, step: 1
6539 11:47:11.605812
6540 11:47:11.605887 RX Delay -311 -> 252, step: 8
6541 11:47:11.614399 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6542 11:47:11.617660 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6543 11:47:11.621011 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6544 11:47:11.627441 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6545 11:47:11.630881 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6546 11:47:11.634154 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6547 11:47:11.637522 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6548 11:47:11.640775 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6549 11:47:11.647337 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6550 11:47:11.650660 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6551 11:47:11.653867 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6552 11:47:11.657393 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6553 11:47:11.664267 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6554 11:47:11.667288 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6555 11:47:11.670421 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6556 11:47:11.677517 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6557 11:47:11.677606 ==
6558 11:47:11.680778 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 11:47:11.683944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 11:47:11.684031 ==
6561 11:47:11.684097 DQS Delay:
6562 11:47:11.687107 DQS0 = 24, DQS1 = 32
6563 11:47:11.687194 DQM Delay:
6564 11:47:11.690986 DQM0 = 8, DQM1 = 10
6565 11:47:11.691075 DQ Delay:
6566 11:47:11.693610 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6567 11:47:11.697426 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6568 11:47:11.700797 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6569 11:47:11.704191 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6570 11:47:11.704278
6571 11:47:11.704350
6572 11:47:11.710659 [DQSOSCAuto] RK1, (LSB)MR18= 0xb554, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6573 11:47:11.713978 CH0 RK1: MR19=C0C, MR18=B554
6574 11:47:11.720410 CH0_RK1: MR19=0xC0C, MR18=0xB554, DQSOSC=387, MR23=63, INC=394, DEC=262
6575 11:47:11.723648 [RxdqsGatingPostProcess] freq 400
6576 11:47:11.730093 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6577 11:47:11.730183 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 11:47:11.734187 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 11:47:11.736743 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 11:47:11.740798 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 11:47:11.743385 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 11:47:11.747421 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 11:47:11.750191 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 11:47:11.753419 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 11:47:11.756611 Pre-setting of DQS Precalculation
6586 11:47:11.760684 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6587 11:47:11.763834 ==
6588 11:47:11.767039 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 11:47:11.770626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 11:47:11.770720 ==
6591 11:47:11.773706 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 11:47:11.780100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6593 11:47:11.784010 [CA 0] Center 36 (8~64) winsize 57
6594 11:47:11.787314 [CA 1] Center 36 (8~64) winsize 57
6595 11:47:11.790391 [CA 2] Center 36 (8~64) winsize 57
6596 11:47:11.793524 [CA 3] Center 36 (8~64) winsize 57
6597 11:47:11.796964 [CA 4] Center 36 (8~64) winsize 57
6598 11:47:11.800013 [CA 5] Center 36 (8~64) winsize 57
6599 11:47:11.800120
6600 11:47:11.803194 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6601 11:47:11.803298
6602 11:47:11.807144 [CATrainingPosCal] consider 1 rank data
6603 11:47:11.809952 u2DelayCellTimex100 = 270/100 ps
6604 11:47:11.813340 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:47:11.816542 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 11:47:11.819873 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 11:47:11.823142 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 11:47:11.829688 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 11:47:11.833566 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:47:11.833690
6611 11:47:11.836973 CA PerBit enable=1, Macro0, CA PI delay=36
6612 11:47:11.837083
6613 11:47:11.840152 [CBTSetCACLKResult] CA Dly = 36
6614 11:47:11.840274 CS Dly: 1 (0~32)
6615 11:47:11.840370 ==
6616 11:47:11.843504 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 11:47:11.850006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 11:47:11.850112 ==
6619 11:47:11.853436 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 11:47:11.860067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6621 11:47:11.863454 [CA 0] Center 36 (8~64) winsize 57
6622 11:47:11.866689 [CA 1] Center 36 (8~64) winsize 57
6623 11:47:11.869928 [CA 2] Center 36 (8~64) winsize 57
6624 11:47:11.873067 [CA 3] Center 36 (8~64) winsize 57
6625 11:47:11.876204 [CA 4] Center 36 (8~64) winsize 57
6626 11:47:11.880047 [CA 5] Center 36 (8~64) winsize 57
6627 11:47:11.880158
6628 11:47:11.883201 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6629 11:47:11.883288
6630 11:47:11.886291 [CATrainingPosCal] consider 2 rank data
6631 11:47:11.890077 u2DelayCellTimex100 = 270/100 ps
6632 11:47:11.893318 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:47:11.896479 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 11:47:11.899696 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:47:11.902991 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:47:11.906322 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:47:11.910052 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:47:11.910162
6639 11:47:11.916438 CA PerBit enable=1, Macro0, CA PI delay=36
6640 11:47:11.916554
6641 11:47:11.916652 [CBTSetCACLKResult] CA Dly = 36
6642 11:47:11.919805 CS Dly: 1 (0~32)
6643 11:47:11.919908
6644 11:47:11.923118 ----->DramcWriteLeveling(PI) begin...
6645 11:47:11.923222 ==
6646 11:47:11.926297 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 11:47:11.929567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 11:47:11.929685 ==
6649 11:47:11.932729 Write leveling (Byte 0): 40 => 8
6650 11:47:11.935997 Write leveling (Byte 1): 40 => 8
6651 11:47:11.939256 DramcWriteLeveling(PI) end<-----
6652 11:47:11.939359
6653 11:47:11.939459 ==
6654 11:47:11.942547 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 11:47:11.946668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 11:47:11.946752 ==
6657 11:47:11.949384 [Gating] SW mode calibration
6658 11:47:11.956009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6659 11:47:11.962678 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6660 11:47:11.965901 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 11:47:11.973062 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 11:47:11.976406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 11:47:11.979580 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 11:47:11.986458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 11:47:11.989639 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 11:47:11.992894 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 11:47:11.999406 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 11:47:12.002720 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 11:47:12.005932 Total UI for P1: 0, mck2ui 16
6670 11:47:12.009416 best dqsien dly found for B0: ( 0, 14, 24)
6671 11:47:12.012653 Total UI for P1: 0, mck2ui 16
6672 11:47:12.015902 best dqsien dly found for B1: ( 0, 14, 24)
6673 11:47:12.019488 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6674 11:47:12.022764 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6675 11:47:12.022848
6676 11:47:12.026083 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 11:47:12.029390 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 11:47:12.032681 [Gating] SW calibration Done
6679 11:47:12.032798 ==
6680 11:47:12.036643 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 11:47:12.039140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 11:47:12.039246 ==
6683 11:47:12.043013 RX Vref Scan: 0
6684 11:47:12.043112
6685 11:47:12.045701 RX Vref 0 -> 0, step: 1
6686 11:47:12.045794
6687 11:47:12.045859 RX Delay -410 -> 252, step: 16
6688 11:47:12.053057 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6689 11:47:12.056331 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6690 11:47:12.059710 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6691 11:47:12.063073 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6692 11:47:12.069663 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6693 11:47:12.073085 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6694 11:47:12.076327 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6695 11:47:12.079628 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6696 11:47:12.086285 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6697 11:47:12.089422 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6698 11:47:12.092668 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6699 11:47:12.096375 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6700 11:47:12.102633 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6701 11:47:12.106039 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6702 11:47:12.109036 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6703 11:47:12.116236 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6704 11:47:12.116354 ==
6705 11:47:12.119691 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 11:47:12.122941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 11:47:12.123053 ==
6708 11:47:12.123150 DQS Delay:
6709 11:47:12.126159 DQS0 = 35, DQS1 = 35
6710 11:47:12.126280 DQM Delay:
6711 11:47:12.129402 DQM0 = 17, DQM1 = 13
6712 11:47:12.129510 DQ Delay:
6713 11:47:12.132552 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6714 11:47:12.135857 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6715 11:47:12.139197 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6716 11:47:12.142327 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6717 11:47:12.142435
6718 11:47:12.142530
6719 11:47:12.142624 ==
6720 11:47:12.145664 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 11:47:12.149437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 11:47:12.149542 ==
6723 11:47:12.149634
6724 11:47:12.149727
6725 11:47:12.152789 TX Vref Scan disable
6726 11:47:12.152898 == TX Byte 0 ==
6727 11:47:12.159335 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 11:47:12.162612 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 11:47:12.162722 == TX Byte 1 ==
6730 11:47:12.169230 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 11:47:12.172491 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 11:47:12.172612 ==
6733 11:47:12.175774 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 11:47:12.178976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 11:47:12.179083 ==
6736 11:47:12.179195
6737 11:47:12.179294
6738 11:47:12.182506 TX Vref Scan disable
6739 11:47:12.182614 == TX Byte 0 ==
6740 11:47:12.189081 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 11:47:12.192276 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 11:47:12.192401 == TX Byte 1 ==
6743 11:47:12.199326 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 11:47:12.202404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 11:47:12.202520
6746 11:47:12.202636 [DATLAT]
6747 11:47:12.206001 Freq=400, CH1 RK0
6748 11:47:12.206085
6749 11:47:12.206161 DATLAT Default: 0xf
6750 11:47:12.208999 0, 0xFFFF, sum = 0
6751 11:47:12.209089 1, 0xFFFF, sum = 0
6752 11:47:12.212312 2, 0xFFFF, sum = 0
6753 11:47:12.212417 3, 0xFFFF, sum = 0
6754 11:47:12.216165 4, 0xFFFF, sum = 0
6755 11:47:12.216279 5, 0xFFFF, sum = 0
6756 11:47:12.219216 6, 0xFFFF, sum = 0
6757 11:47:12.219334 7, 0xFFFF, sum = 0
6758 11:47:12.222491 8, 0xFFFF, sum = 0
6759 11:47:12.225867 9, 0xFFFF, sum = 0
6760 11:47:12.225995 10, 0xFFFF, sum = 0
6761 11:47:12.229064 11, 0xFFFF, sum = 0
6762 11:47:12.229186 12, 0xFFFF, sum = 0
6763 11:47:12.232181 13, 0x0, sum = 1
6764 11:47:12.232304 14, 0x0, sum = 2
6765 11:47:12.235404 15, 0x0, sum = 3
6766 11:47:12.235518 16, 0x0, sum = 4
6767 11:47:12.235623 best_step = 14
6768 11:47:12.235717
6769 11:47:12.239331 ==
6770 11:47:12.242588 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 11:47:12.245636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 11:47:12.245759 ==
6773 11:47:12.245857 RX Vref Scan: 1
6774 11:47:12.245953
6775 11:47:12.248873 RX Vref 0 -> 0, step: 1
6776 11:47:12.248984
6777 11:47:12.251951 RX Delay -311 -> 252, step: 8
6778 11:47:12.252053
6779 11:47:12.255705 Set Vref, RX VrefLevel [Byte0]: 54
6780 11:47:12.259170 [Byte1]: 49
6781 11:47:12.262339
6782 11:47:12.262426 Final RX Vref Byte 0 = 54 to rank0
6783 11:47:12.265728 Final RX Vref Byte 1 = 49 to rank0
6784 11:47:12.268996 Final RX Vref Byte 0 = 54 to rank1
6785 11:47:12.272417 Final RX Vref Byte 1 = 49 to rank1==
6786 11:47:12.275818 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 11:47:12.282336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 11:47:12.282422 ==
6789 11:47:12.282489 DQS Delay:
6790 11:47:12.285778 DQS0 = 32, DQS1 = 32
6791 11:47:12.285862 DQM Delay:
6792 11:47:12.285929 DQM0 = 13, DQM1 = 11
6793 11:47:12.289027 DQ Delay:
6794 11:47:12.292420 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6795 11:47:12.295742 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6796 11:47:12.295849 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6797 11:47:12.299118 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6798 11:47:12.299223
6799 11:47:12.302314
6800 11:47:12.309263 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc5, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6801 11:47:12.312362 CH1 RK0: MR19=C0C, MR18=8DC5
6802 11:47:12.319051 CH1_RK0: MR19=0xC0C, MR18=0x8DC5, DQSOSC=385, MR23=63, INC=398, DEC=265
6803 11:47:12.319166 ==
6804 11:47:12.322141 Dram Type= 6, Freq= 0, CH_1, rank 1
6805 11:47:12.325332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 11:47:12.325412 ==
6807 11:47:12.328737 [Gating] SW mode calibration
6808 11:47:12.335149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6809 11:47:12.341930 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6810 11:47:12.345760 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 11:47:12.349012 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 11:47:12.355605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 11:47:12.358587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 11:47:12.362382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 11:47:12.365644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 11:47:12.371877 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 11:47:12.375709 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 11:47:12.378366 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 11:47:12.381729 Total UI for P1: 0, mck2ui 16
6820 11:47:12.385056 best dqsien dly found for B0: ( 0, 14, 24)
6821 11:47:12.388305 Total UI for P1: 0, mck2ui 16
6822 11:47:12.392315 best dqsien dly found for B1: ( 0, 14, 24)
6823 11:47:12.394903 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6824 11:47:12.402188 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6825 11:47:12.402322
6826 11:47:12.405486 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 11:47:12.408786 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 11:47:12.412034 [Gating] SW calibration Done
6829 11:47:12.412121 ==
6830 11:47:12.415081 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 11:47:12.418319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 11:47:12.418414 ==
6833 11:47:12.422098 RX Vref Scan: 0
6834 11:47:12.422173
6835 11:47:12.422255 RX Vref 0 -> 0, step: 1
6836 11:47:12.422317
6837 11:47:12.425268 RX Delay -410 -> 252, step: 16
6838 11:47:12.428499 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6839 11:47:12.434886 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6840 11:47:12.438232 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6841 11:47:12.441919 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6842 11:47:12.444668 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6843 11:47:12.451791 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6844 11:47:12.454952 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6845 11:47:12.458118 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6846 11:47:12.461945 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6847 11:47:12.468554 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6848 11:47:12.471502 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6849 11:47:12.474924 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6850 11:47:12.478275 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6851 11:47:12.484903 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6852 11:47:12.488428 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6853 11:47:12.491610 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6854 11:47:12.491695 ==
6855 11:47:12.495010 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 11:47:12.501549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 11:47:12.501651 ==
6858 11:47:12.501721 DQS Delay:
6859 11:47:12.504946 DQS0 = 27, DQS1 = 27
6860 11:47:12.505039 DQM Delay:
6861 11:47:12.505103 DQM0 = 10, DQM1 = 8
6862 11:47:12.508239 DQ Delay:
6863 11:47:12.508353 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6864 11:47:12.511583 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6865 11:47:12.514971 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6866 11:47:12.518229 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6867 11:47:12.518309
6868 11:47:12.518374
6869 11:47:12.518446 ==
6870 11:47:12.521311 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 11:47:12.527902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 11:47:12.527984 ==
6873 11:47:12.528064
6874 11:47:12.528143
6875 11:47:12.528203 TX Vref Scan disable
6876 11:47:12.531665 == TX Byte 0 ==
6877 11:47:12.534949 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6878 11:47:12.538293 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6879 11:47:12.541615 == TX Byte 1 ==
6880 11:47:12.544686 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6881 11:47:12.548115 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6882 11:47:12.548233 ==
6883 11:47:12.551417 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 11:47:12.557769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 11:47:12.557854 ==
6886 11:47:12.557929
6887 11:47:12.557991
6888 11:47:12.558049 TX Vref Scan disable
6889 11:47:12.561748 == TX Byte 0 ==
6890 11:47:12.565035 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6891 11:47:12.568381 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6892 11:47:12.571615 == TX Byte 1 ==
6893 11:47:12.574714 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6894 11:47:12.577697 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6895 11:47:12.577811
6896 11:47:12.581412 [DATLAT]
6897 11:47:12.581520 Freq=400, CH1 RK1
6898 11:47:12.581613
6899 11:47:12.584621 DATLAT Default: 0xe
6900 11:47:12.584729 0, 0xFFFF, sum = 0
6901 11:47:12.588027 1, 0xFFFF, sum = 0
6902 11:47:12.588109 2, 0xFFFF, sum = 0
6903 11:47:12.591385 3, 0xFFFF, sum = 0
6904 11:47:12.591501 4, 0xFFFF, sum = 0
6905 11:47:12.594761 5, 0xFFFF, sum = 0
6906 11:47:12.594874 6, 0xFFFF, sum = 0
6907 11:47:12.598030 7, 0xFFFF, sum = 0
6908 11:47:12.598141 8, 0xFFFF, sum = 0
6909 11:47:12.601319 9, 0xFFFF, sum = 0
6910 11:47:12.604717 10, 0xFFFF, sum = 0
6911 11:47:12.604830 11, 0xFFFF, sum = 0
6912 11:47:12.608140 12, 0xFFFF, sum = 0
6913 11:47:12.608220 13, 0x0, sum = 1
6914 11:47:12.611370 14, 0x0, sum = 2
6915 11:47:12.611482 15, 0x0, sum = 3
6916 11:47:12.614807 16, 0x0, sum = 4
6917 11:47:12.614913 best_step = 14
6918 11:47:12.615006
6919 11:47:12.615099 ==
6920 11:47:12.618032 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 11:47:12.621276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 11:47:12.621382 ==
6923 11:47:12.624408 RX Vref Scan: 0
6924 11:47:12.624507
6925 11:47:12.624604 RX Vref 0 -> 0, step: 1
6926 11:47:12.627487
6927 11:47:12.627596 RX Delay -295 -> 252, step: 8
6928 11:47:12.636017 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6929 11:47:12.639070 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6930 11:47:12.643048 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6931 11:47:12.645745 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6932 11:47:12.652786 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6933 11:47:12.656086 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6934 11:47:12.659417 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6935 11:47:12.662476 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6936 11:47:12.669040 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6937 11:47:12.672304 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6938 11:47:12.675645 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6939 11:47:12.678973 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6940 11:47:12.686058 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6941 11:47:12.688997 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6942 11:47:12.692821 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6943 11:47:12.699308 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6944 11:47:12.699396 ==
6945 11:47:12.702730 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 11:47:12.705978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 11:47:12.706097 ==
6948 11:47:12.706194 DQS Delay:
6949 11:47:12.709242 DQS0 = 28, DQS1 = 36
6950 11:47:12.709317 DQM Delay:
6951 11:47:12.712574 DQM0 = 11, DQM1 = 15
6952 11:47:12.712673 DQ Delay:
6953 11:47:12.715903 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6954 11:47:12.719327 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6955 11:47:12.722571 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6956 11:47:12.725886 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6957 11:47:12.725988
6958 11:47:12.726084
6959 11:47:12.732562 [DQSOSCAuto] RK1, (LSB)MR18= 0xc354, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6960 11:47:12.735982 CH1 RK1: MR19=C0C, MR18=C354
6961 11:47:12.742530 CH1_RK1: MR19=0xC0C, MR18=0xC354, DQSOSC=385, MR23=63, INC=398, DEC=265
6962 11:47:12.745782 [RxdqsGatingPostProcess] freq 400
6963 11:47:12.749245 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6964 11:47:12.752411 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 11:47:12.755597 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 11:47:12.758917 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 11:47:12.762180 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 11:47:12.765325 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 11:47:12.769206 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 11:47:12.772253 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 11:47:12.775478 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 11:47:12.778666 Pre-setting of DQS Precalculation
6973 11:47:12.782544 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6974 11:47:12.792405 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6975 11:47:12.798669 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6976 11:47:12.798756
6977 11:47:12.798823
6978 11:47:12.802595 [Calibration Summary] 800 Mbps
6979 11:47:12.802680 CH 0, Rank 0
6980 11:47:12.805818 SW Impedance : PASS
6981 11:47:12.805901 DUTY Scan : NO K
6982 11:47:12.809126 ZQ Calibration : PASS
6983 11:47:12.812411 Jitter Meter : NO K
6984 11:47:12.812485 CBT Training : PASS
6985 11:47:12.815821 Write leveling : PASS
6986 11:47:12.819017 RX DQS gating : PASS
6987 11:47:12.819101 RX DQ/DQS(RDDQC) : PASS
6988 11:47:12.822357 TX DQ/DQS : PASS
6989 11:47:12.825818 RX DATLAT : PASS
6990 11:47:12.825901 RX DQ/DQS(Engine): PASS
6991 11:47:12.829001 TX OE : NO K
6992 11:47:12.829085 All Pass.
6993 11:47:12.829150
6994 11:47:12.832226 CH 0, Rank 1
6995 11:47:12.832309 SW Impedance : PASS
6996 11:47:12.835284 DUTY Scan : NO K
6997 11:47:12.835399 ZQ Calibration : PASS
6998 11:47:12.839147 Jitter Meter : NO K
6999 11:47:12.841906 CBT Training : PASS
7000 11:47:12.841991 Write leveling : NO K
7001 11:47:12.845804 RX DQS gating : PASS
7002 11:47:12.849184 RX DQ/DQS(RDDQC) : PASS
7003 11:47:12.849267 TX DQ/DQS : PASS
7004 11:47:12.852363 RX DATLAT : PASS
7005 11:47:12.855453 RX DQ/DQS(Engine): PASS
7006 11:47:12.855553 TX OE : NO K
7007 11:47:12.858772 All Pass.
7008 11:47:12.858873
7009 11:47:12.858941 CH 1, Rank 0
7010 11:47:12.862035 SW Impedance : PASS
7011 11:47:12.862118 DUTY Scan : NO K
7012 11:47:12.865700 ZQ Calibration : PASS
7013 11:47:12.869027 Jitter Meter : NO K
7014 11:47:12.869127 CBT Training : PASS
7015 11:47:12.872389 Write leveling : PASS
7016 11:47:12.875841 RX DQS gating : PASS
7017 11:47:12.875956 RX DQ/DQS(RDDQC) : PASS
7018 11:47:12.878879 TX DQ/DQS : PASS
7019 11:47:12.882250 RX DATLAT : PASS
7020 11:47:12.882336 RX DQ/DQS(Engine): PASS
7021 11:47:12.885360 TX OE : NO K
7022 11:47:12.885467 All Pass.
7023 11:47:12.885541
7024 11:47:12.889034 CH 1, Rank 1
7025 11:47:12.889159 SW Impedance : PASS
7026 11:47:12.892127 DUTY Scan : NO K
7027 11:47:12.892239 ZQ Calibration : PASS
7028 11:47:12.895357 Jitter Meter : NO K
7029 11:47:12.898792 CBT Training : PASS
7030 11:47:12.898907 Write leveling : NO K
7031 11:47:12.901724 RX DQS gating : PASS
7032 11:47:12.905393 RX DQ/DQS(RDDQC) : PASS
7033 11:47:12.905477 TX DQ/DQS : PASS
7034 11:47:12.908658 RX DATLAT : PASS
7035 11:47:12.912021 RX DQ/DQS(Engine): PASS
7036 11:47:12.912106 TX OE : NO K
7037 11:47:12.915334 All Pass.
7038 11:47:12.915428
7039 11:47:12.915529 DramC Write-DBI off
7040 11:47:12.918607 PER_BANK_REFRESH: Hybrid Mode
7041 11:47:12.918693 TX_TRACKING: ON
7042 11:47:12.928739 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7043 11:47:12.932046 [FAST_K] Save calibration result to emmc
7044 11:47:12.935325 dramc_set_vcore_voltage set vcore to 725000
7045 11:47:12.938533 Read voltage for 1600, 0
7046 11:47:12.938619 Vio18 = 0
7047 11:47:12.941552 Vcore = 725000
7048 11:47:12.941633 Vdram = 0
7049 11:47:12.941700 Vddq = 0
7050 11:47:12.944703 Vmddr = 0
7051 11:47:12.948218 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7052 11:47:12.954757 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7053 11:47:12.954846 MEM_TYPE=3, freq_sel=13
7054 11:47:12.958650 sv_algorithm_assistance_LP4_3733
7055 11:47:12.965033 ============ PULL DRAM RESETB DOWN ============
7056 11:47:12.968272 ========== PULL DRAM RESETB DOWN end =========
7057 11:47:12.971667 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7058 11:47:12.974782 ===================================
7059 11:47:12.978033 LPDDR4 DRAM CONFIGURATION
7060 11:47:12.981435 ===================================
7061 11:47:12.984694 EX_ROW_EN[0] = 0x0
7062 11:47:12.984840 EX_ROW_EN[1] = 0x0
7063 11:47:12.987936 LP4Y_EN = 0x0
7064 11:47:12.988044 WORK_FSP = 0x1
7065 11:47:12.991144 WL = 0x5
7066 11:47:12.991255 RL = 0x5
7067 11:47:12.994411 BL = 0x2
7068 11:47:12.994530 RPST = 0x0
7069 11:47:12.998254 RD_PRE = 0x0
7070 11:47:12.998341 WR_PRE = 0x1
7071 11:47:13.001529 WR_PST = 0x1
7072 11:47:13.001605 DBI_WR = 0x0
7073 11:47:13.004088 DBI_RD = 0x0
7074 11:47:13.004174 OTF = 0x1
7075 11:47:13.008035 ===================================
7076 11:47:13.011165 ===================================
7077 11:47:13.014344 ANA top config
7078 11:47:13.017707 ===================================
7079 11:47:13.020981 DLL_ASYNC_EN = 0
7080 11:47:13.021066 ALL_SLAVE_EN = 0
7081 11:47:13.024168 NEW_RANK_MODE = 1
7082 11:47:13.027659 DLL_IDLE_MODE = 1
7083 11:47:13.030976 LP45_APHY_COMB_EN = 1
7084 11:47:13.031057 TX_ODT_DIS = 0
7085 11:47:13.034231 NEW_8X_MODE = 1
7086 11:47:13.037441 ===================================
7087 11:47:13.040764 ===================================
7088 11:47:13.044033 data_rate = 3200
7089 11:47:13.047199 CKR = 1
7090 11:47:13.050668 DQ_P2S_RATIO = 8
7091 11:47:13.054102 ===================================
7092 11:47:13.057266 CA_P2S_RATIO = 8
7093 11:47:13.057390 DQ_CA_OPEN = 0
7094 11:47:13.061228 DQ_SEMI_OPEN = 0
7095 11:47:13.064213 CA_SEMI_OPEN = 0
7096 11:47:13.067428 CA_FULL_RATE = 0
7097 11:47:13.070682 DQ_CKDIV4_EN = 0
7098 11:47:13.074003 CA_CKDIV4_EN = 0
7099 11:47:13.074091 CA_PREDIV_EN = 0
7100 11:47:13.077597 PH8_DLY = 12
7101 11:47:13.080978 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7102 11:47:13.084275 DQ_AAMCK_DIV = 4
7103 11:47:13.087648 CA_AAMCK_DIV = 4
7104 11:47:13.090690 CA_ADMCK_DIV = 4
7105 11:47:13.090776 DQ_TRACK_CA_EN = 0
7106 11:47:13.093919 CA_PICK = 1600
7107 11:47:13.097726 CA_MCKIO = 1600
7108 11:47:13.100828 MCKIO_SEMI = 0
7109 11:47:13.104022 PLL_FREQ = 3068
7110 11:47:13.107191 DQ_UI_PI_RATIO = 32
7111 11:47:13.110944 CA_UI_PI_RATIO = 0
7112 11:47:13.114283 ===================================
7113 11:47:13.117504 ===================================
7114 11:47:13.117627 memory_type:LPDDR4
7115 11:47:13.120663 GP_NUM : 10
7116 11:47:13.123791 SRAM_EN : 1
7117 11:47:13.123902 MD32_EN : 0
7118 11:47:13.127233 ===================================
7119 11:47:13.130630 [ANA_INIT] >>>>>>>>>>>>>>
7120 11:47:13.133965 <<<<<< [CONFIGURE PHASE]: ANA_TX
7121 11:47:13.137346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7122 11:47:13.140657 ===================================
7123 11:47:13.143936 data_rate = 3200,PCW = 0X7600
7124 11:47:13.147220 ===================================
7125 11:47:13.150427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7126 11:47:13.153692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 11:47:13.160306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 11:47:13.163660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7129 11:47:13.166904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7130 11:47:13.170658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7131 11:47:13.173758 [ANA_INIT] flow start
7132 11:47:13.176948 [ANA_INIT] PLL >>>>>>>>
7133 11:47:13.177032 [ANA_INIT] PLL <<<<<<<<
7134 11:47:13.180333 [ANA_INIT] MIDPI >>>>>>>>
7135 11:47:13.184031 [ANA_INIT] MIDPI <<<<<<<<
7136 11:47:13.184125 [ANA_INIT] DLL >>>>>>>>
7137 11:47:13.186784 [ANA_INIT] DLL <<<<<<<<
7138 11:47:13.190161 [ANA_INIT] flow end
7139 11:47:13.193560 ============ LP4 DIFF to SE enter ============
7140 11:47:13.196975 ============ LP4 DIFF to SE exit ============
7141 11:47:13.200422 [ANA_INIT] <<<<<<<<<<<<<
7142 11:47:13.203502 [Flow] Enable top DCM control >>>>>
7143 11:47:13.206704 [Flow] Enable top DCM control <<<<<
7144 11:47:13.210387 Enable DLL master slave shuffle
7145 11:47:13.216507 ==============================================================
7146 11:47:13.216621 Gating Mode config
7147 11:47:13.223237 ==============================================================
7148 11:47:13.223348 Config description:
7149 11:47:13.233679 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7150 11:47:13.240355 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7151 11:47:13.246993 SELPH_MODE 0: By rank 1: By Phase
7152 11:47:13.250262 ==============================================================
7153 11:47:13.253577 GAT_TRACK_EN = 1
7154 11:47:13.256901 RX_GATING_MODE = 2
7155 11:47:13.260241 RX_GATING_TRACK_MODE = 2
7156 11:47:13.263735 SELPH_MODE = 1
7157 11:47:13.266876 PICG_EARLY_EN = 1
7158 11:47:13.270199 VALID_LAT_VALUE = 1
7159 11:47:13.273607 ==============================================================
7160 11:47:13.276689 Enter into Gating configuration >>>>
7161 11:47:13.279995 Exit from Gating configuration <<<<
7162 11:47:13.283392 Enter into DVFS_PRE_config >>>>>
7163 11:47:13.297195 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7164 11:47:13.300293 Exit from DVFS_PRE_config <<<<<
7165 11:47:13.300415 Enter into PICG configuration >>>>
7166 11:47:13.303147 Exit from PICG configuration <<<<
7167 11:47:13.307135 [RX_INPUT] configuration >>>>>
7168 11:47:13.309757 [RX_INPUT] configuration <<<<<
7169 11:47:13.316766 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7170 11:47:13.320037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7171 11:47:13.326773 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 11:47:13.333020 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 11:47:13.339871 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 11:47:13.346539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 11:47:13.349736 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7176 11:47:13.353149 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7177 11:47:13.356504 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7178 11:47:13.363043 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7179 11:47:13.366351 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7180 11:47:13.369796 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 11:47:13.373145 ===================================
7182 11:47:13.376379 LPDDR4 DRAM CONFIGURATION
7183 11:47:13.379570 ===================================
7184 11:47:13.379686 EX_ROW_EN[0] = 0x0
7185 11:47:13.383370 EX_ROW_EN[1] = 0x0
7186 11:47:13.386413 LP4Y_EN = 0x0
7187 11:47:13.386524 WORK_FSP = 0x1
7188 11:47:13.389650 WL = 0x5
7189 11:47:13.389756 RL = 0x5
7190 11:47:13.392963 BL = 0x2
7191 11:47:13.393054 RPST = 0x0
7192 11:47:13.396194 RD_PRE = 0x0
7193 11:47:13.396307 WR_PRE = 0x1
7194 11:47:13.399358 WR_PST = 0x1
7195 11:47:13.399469 DBI_WR = 0x0
7196 11:47:13.402729 DBI_RD = 0x0
7197 11:47:13.402854 OTF = 0x1
7198 11:47:13.406581 ===================================
7199 11:47:13.410068 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7200 11:47:13.416058 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7201 11:47:13.419905 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 11:47:13.422551 ===================================
7203 11:47:13.425981 LPDDR4 DRAM CONFIGURATION
7204 11:47:13.429709 ===================================
7205 11:47:13.429820 EX_ROW_EN[0] = 0x10
7206 11:47:13.432708 EX_ROW_EN[1] = 0x0
7207 11:47:13.435914 LP4Y_EN = 0x0
7208 11:47:13.436038 WORK_FSP = 0x1
7209 11:47:13.439119 WL = 0x5
7210 11:47:13.439225 RL = 0x5
7211 11:47:13.443000 BL = 0x2
7212 11:47:13.443109 RPST = 0x0
7213 11:47:13.446069 RD_PRE = 0x0
7214 11:47:13.446178 WR_PRE = 0x1
7215 11:47:13.449563 WR_PST = 0x1
7216 11:47:13.449660 DBI_WR = 0x0
7217 11:47:13.452739 DBI_RD = 0x0
7218 11:47:13.452846 OTF = 0x1
7219 11:47:13.456189 ===================================
7220 11:47:13.462808 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7221 11:47:13.462926 ==
7222 11:47:13.466094 Dram Type= 6, Freq= 0, CH_0, rank 0
7223 11:47:13.469464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7224 11:47:13.472636 ==
7225 11:47:13.472746 [Duty_Offset_Calibration]
7226 11:47:13.475905 B0:2 B1:1 CA:1
7227 11:47:13.475989
7228 11:47:13.479257 [DutyScan_Calibration_Flow] k_type=0
7229 11:47:13.487811
7230 11:47:13.487919 ==CLK 0==
7231 11:47:13.491560 Final CLK duty delay cell = 0
7232 11:47:13.494642 [0] MAX Duty = 5156%(X100), DQS PI = 22
7233 11:47:13.497895 [0] MIN Duty = 4907%(X100), DQS PI = 0
7234 11:47:13.498014 [0] AVG Duty = 5031%(X100)
7235 11:47:13.501667
7236 11:47:13.504700 CH0 CLK Duty spec in!! Max-Min= 249%
7237 11:47:13.508031 [DutyScan_Calibration_Flow] ====Done====
7238 11:47:13.508127
7239 11:47:13.511254 [DutyScan_Calibration_Flow] k_type=1
7240 11:47:13.527211
7241 11:47:13.527327 ==DQS 0 ==
7242 11:47:13.530584 Final DQS duty delay cell = -4
7243 11:47:13.533821 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7244 11:47:13.537068 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7245 11:47:13.540237 [-4] AVG Duty = 4906%(X100)
7246 11:47:13.540345
7247 11:47:13.540446 ==DQS 1 ==
7248 11:47:13.544083 Final DQS duty delay cell = 0
7249 11:47:13.547208 [0] MAX Duty = 5187%(X100), DQS PI = 20
7250 11:47:13.550474 [0] MIN Duty = 5031%(X100), DQS PI = 32
7251 11:47:13.553550 [0] AVG Duty = 5109%(X100)
7252 11:47:13.553656
7253 11:47:13.556669 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7254 11:47:13.556774
7255 11:47:13.560404 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7256 11:47:13.563439 [DutyScan_Calibration_Flow] ====Done====
7257 11:47:13.563551
7258 11:47:13.566739 [DutyScan_Calibration_Flow] k_type=3
7259 11:47:13.584046
7260 11:47:13.584159 ==DQM 0 ==
7261 11:47:13.587363 Final DQM duty delay cell = 0
7262 11:47:13.590635 [0] MAX Duty = 5218%(X100), DQS PI = 34
7263 11:47:13.593955 [0] MIN Duty = 4907%(X100), DQS PI = 56
7264 11:47:13.597138 [0] AVG Duty = 5062%(X100)
7265 11:47:13.597258
7266 11:47:13.597370 ==DQM 1 ==
7267 11:47:13.600765 Final DQM duty delay cell = -4
7268 11:47:13.603882 [-4] MAX Duty = 4969%(X100), DQS PI = 58
7269 11:47:13.607174 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7270 11:47:13.610914 [-4] AVG Duty = 4906%(X100)
7271 11:47:13.611004
7272 11:47:13.614179 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7273 11:47:13.614265
7274 11:47:13.617339 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7275 11:47:13.620734 [DutyScan_Calibration_Flow] ====Done====
7276 11:47:13.620840
7277 11:47:13.624030 [DutyScan_Calibration_Flow] k_type=2
7278 11:47:13.641651
7279 11:47:13.641788 ==DQ 0 ==
7280 11:47:13.644919 Final DQ duty delay cell = 0
7281 11:47:13.648281 [0] MAX Duty = 5062%(X100), DQS PI = 26
7282 11:47:13.651209 [0] MIN Duty = 4907%(X100), DQS PI = 0
7283 11:47:13.651328 [0] AVG Duty = 4984%(X100)
7284 11:47:13.651432
7285 11:47:13.654493 ==DQ 1 ==
7286 11:47:13.658339 Final DQ duty delay cell = 0
7287 11:47:13.661596 [0] MAX Duty = 5125%(X100), DQS PI = 6
7288 11:47:13.664791 [0] MIN Duty = 4938%(X100), DQS PI = 32
7289 11:47:13.664877 [0] AVG Duty = 5031%(X100)
7290 11:47:13.664961
7291 11:47:13.668441 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7292 11:47:13.668516
7293 11:47:13.671451 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7294 11:47:13.678097 [DutyScan_Calibration_Flow] ====Done====
7295 11:47:13.678185 ==
7296 11:47:13.681303 Dram Type= 6, Freq= 0, CH_1, rank 0
7297 11:47:13.684604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 11:47:13.684686 ==
7299 11:47:13.688025 [Duty_Offset_Calibration]
7300 11:47:13.688107 B0:1 B1:0 CA:0
7301 11:47:13.688171
7302 11:47:13.691314 [DutyScan_Calibration_Flow] k_type=0
7303 11:47:13.700793
7304 11:47:13.700895 ==CLK 0==
7305 11:47:13.703900 Final CLK duty delay cell = -4
7306 11:47:13.707154 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7307 11:47:13.710987 [-4] MIN Duty = 4875%(X100), DQS PI = 50
7308 11:47:13.714025 [-4] AVG Duty = 4937%(X100)
7309 11:47:13.714101
7310 11:47:13.717261 CH1 CLK Duty spec in!! Max-Min= 125%
7311 11:47:13.720540 [DutyScan_Calibration_Flow] ====Done====
7312 11:47:13.720660
7313 11:47:13.723621 [DutyScan_Calibration_Flow] k_type=1
7314 11:47:13.740622
7315 11:47:13.740756 ==DQS 0 ==
7316 11:47:13.743783 Final DQS duty delay cell = 0
7317 11:47:13.747097 [0] MAX Duty = 5094%(X100), DQS PI = 14
7318 11:47:13.750476 [0] MIN Duty = 4844%(X100), DQS PI = 50
7319 11:47:13.753752 [0] AVG Duty = 4969%(X100)
7320 11:47:13.753877
7321 11:47:13.753971 ==DQS 1 ==
7322 11:47:13.756988 Final DQS duty delay cell = 0
7323 11:47:13.760894 [0] MAX Duty = 5249%(X100), DQS PI = 16
7324 11:47:13.764061 [0] MIN Duty = 4938%(X100), DQS PI = 10
7325 11:47:13.767476 [0] AVG Duty = 5093%(X100)
7326 11:47:13.767579
7327 11:47:13.770651 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7328 11:47:13.770735
7329 11:47:13.773885 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7330 11:47:13.777462 [DutyScan_Calibration_Flow] ====Done====
7331 11:47:13.777544
7332 11:47:13.780699 [DutyScan_Calibration_Flow] k_type=3
7333 11:47:13.797926
7334 11:47:13.798038 ==DQM 0 ==
7335 11:47:13.800695 Final DQM duty delay cell = 0
7336 11:47:13.804657 [0] MAX Duty = 5218%(X100), DQS PI = 20
7337 11:47:13.807491 [0] MIN Duty = 4969%(X100), DQS PI = 48
7338 11:47:13.810690 [0] AVG Duty = 5093%(X100)
7339 11:47:13.810772
7340 11:47:13.810835 ==DQM 1 ==
7341 11:47:13.813960 Final DQM duty delay cell = 0
7342 11:47:13.817773 [0] MAX Duty = 5093%(X100), DQS PI = 14
7343 11:47:13.820905 [0] MIN Duty = 4938%(X100), DQS PI = 6
7344 11:47:13.824133 [0] AVG Duty = 5015%(X100)
7345 11:47:13.824244
7346 11:47:13.827400 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7347 11:47:13.827475
7348 11:47:13.830719 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7349 11:47:13.834638 [DutyScan_Calibration_Flow] ====Done====
7350 11:47:13.834724
7351 11:47:13.837746 [DutyScan_Calibration_Flow] k_type=2
7352 11:47:13.853517
7353 11:47:13.853617 ==DQ 0 ==
7354 11:47:13.857659 Final DQ duty delay cell = -4
7355 11:47:13.860894 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7356 11:47:13.864029 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7357 11:47:13.867226 [-4] AVG Duty = 4968%(X100)
7358 11:47:13.867311
7359 11:47:13.867377 ==DQ 1 ==
7360 11:47:13.870390 Final DQ duty delay cell = 0
7361 11:47:13.873638 [0] MAX Duty = 5124%(X100), DQS PI = 18
7362 11:47:13.876955 [0] MIN Duty = 4938%(X100), DQS PI = 10
7363 11:47:13.877041 [0] AVG Duty = 5031%(X100)
7364 11:47:13.880779
7365 11:47:13.883872 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7366 11:47:13.883954
7367 11:47:13.886886 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7368 11:47:13.890769 [DutyScan_Calibration_Flow] ====Done====
7369 11:47:13.893472 nWR fixed to 30
7370 11:47:13.893587 [ModeRegInit_LP4] CH0 RK0
7371 11:47:13.896874 [ModeRegInit_LP4] CH0 RK1
7372 11:47:13.900210 [ModeRegInit_LP4] CH1 RK0
7373 11:47:13.903535 [ModeRegInit_LP4] CH1 RK1
7374 11:47:13.903664 match AC timing 5
7375 11:47:13.910127 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7376 11:47:13.913372 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7377 11:47:13.916730 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7378 11:47:13.923959 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7379 11:47:13.926748 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7380 11:47:13.926855 [MiockJmeterHQA]
7381 11:47:13.926921
7382 11:47:13.929978 [DramcMiockJmeter] u1RxGatingPI = 0
7383 11:47:13.933940 0 : 4252, 4027
7384 11:47:13.934032 4 : 4253, 4027
7385 11:47:13.937008 8 : 4252, 4027
7386 11:47:13.937110 12 : 4366, 4139
7387 11:47:13.937185 16 : 4253, 4027
7388 11:47:13.940227 20 : 4250, 4026
7389 11:47:13.940316 24 : 4252, 4027
7390 11:47:13.943290 28 : 4362, 4137
7391 11:47:13.943377 32 : 4253, 4026
7392 11:47:13.946649 36 : 4363, 4138
7393 11:47:13.946740 40 : 4253, 4026
7394 11:47:13.949815 44 : 4252, 4027
7395 11:47:13.949929 48 : 4250, 4027
7396 11:47:13.950027 52 : 4255, 4029
7397 11:47:13.953648 56 : 4361, 4137
7398 11:47:13.953734 60 : 4250, 4026
7399 11:47:13.957030 64 : 4361, 4137
7400 11:47:13.957116 68 : 4249, 4027
7401 11:47:13.959752 72 : 4250, 4027
7402 11:47:13.959838 76 : 4249, 4027
7403 11:47:13.963172 80 : 4360, 4137
7404 11:47:13.963260 84 : 4250, 4026
7405 11:47:13.963329 88 : 4361, 106
7406 11:47:13.966376 92 : 4252, 0
7407 11:47:13.966463 96 : 4253, 0
7408 11:47:13.969711 100 : 4252, 0
7409 11:47:13.969798 104 : 4250, 0
7410 11:47:13.969866 108 : 4252, 0
7411 11:47:13.973572 112 : 4361, 0
7412 11:47:13.973659 116 : 4360, 0
7413 11:47:13.973728 120 : 4363, 0
7414 11:47:13.976666 124 : 4250, 0
7415 11:47:13.976752 128 : 4249, 0
7416 11:47:13.979811 132 : 4250, 0
7417 11:47:13.979898 136 : 4250, 0
7418 11:47:13.979968 140 : 4252, 0
7419 11:47:13.983109 144 : 4249, 0
7420 11:47:13.983196 148 : 4253, 0
7421 11:47:13.986430 152 : 4250, 0
7422 11:47:13.986517 156 : 4250, 0
7423 11:47:13.986586 160 : 4252, 0
7424 11:47:13.989651 164 : 4361, 0
7425 11:47:13.989738 168 : 4360, 0
7426 11:47:13.993215 172 : 4250, 0
7427 11:47:13.993333 176 : 4250, 0
7428 11:47:13.993435 180 : 4250, 0
7429 11:47:13.996432 184 : 4360, 0
7430 11:47:13.996519 188 : 4250, 0
7431 11:47:13.996588 192 : 4250, 0
7432 11:47:13.999633 196 : 4250, 0
7433 11:47:13.999720 200 : 4253, 0
7434 11:47:14.003145 204 : 4250, 1649
7435 11:47:14.003232 208 : 4250, 4019
7436 11:47:14.006388 212 : 4361, 4137
7437 11:47:14.006475 216 : 4250, 4027
7438 11:47:14.009759 220 : 4249, 4027
7439 11:47:14.009846 224 : 4250, 4026
7440 11:47:14.013036 228 : 4253, 4029
7441 11:47:14.013122 232 : 4250, 4027
7442 11:47:14.016421 236 : 4249, 4027
7443 11:47:14.016507 240 : 4253, 4026
7444 11:47:14.016576 244 : 4253, 4029
7445 11:47:14.019795 248 : 4250, 4027
7446 11:47:14.019882 252 : 4360, 4138
7447 11:47:14.023050 256 : 4360, 4137
7448 11:47:14.023137 260 : 4250, 4026
7449 11:47:14.026501 264 : 4363, 4140
7450 11:47:14.026588 268 : 4360, 4137
7451 11:47:14.029640 272 : 4252, 4027
7452 11:47:14.029727 276 : 4250, 4026
7453 11:47:14.032975 280 : 4253, 4029
7454 11:47:14.033072 284 : 4250, 4027
7455 11:47:14.035933 288 : 4249, 4027
7456 11:47:14.036014 292 : 4250, 4026
7457 11:47:14.039655 296 : 4253, 4029
7458 11:47:14.039766 300 : 4250, 4027
7459 11:47:14.039863 304 : 4360, 4138
7460 11:47:14.042900 308 : 4360, 4082
7461 11:47:14.043008 312 : 4250, 1907
7462 11:47:14.043102
7463 11:47:14.046251 MIOCK jitter meter ch=0
7464 11:47:14.046354
7465 11:47:14.049452 1T = (312-88) = 224 dly cells
7466 11:47:14.055921 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7467 11:47:14.056016 ==
7468 11:47:14.059155 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 11:47:14.062456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7470 11:47:14.062560 ==
7471 11:47:14.069002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7472 11:47:14.072437 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7473 11:47:14.075742 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7474 11:47:14.082209 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7475 11:47:14.091734 [CA 0] Center 42 (12~73) winsize 62
7476 11:47:14.094887 [CA 1] Center 42 (12~73) winsize 62
7477 11:47:14.098159 [CA 2] Center 37 (8~67) winsize 60
7478 11:47:14.101273 [CA 3] Center 37 (7~67) winsize 61
7479 11:47:14.105123 [CA 4] Center 36 (6~66) winsize 61
7480 11:47:14.108372 [CA 5] Center 35 (6~64) winsize 59
7481 11:47:14.108490
7482 11:47:14.111184 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7483 11:47:14.111284
7484 11:47:14.115017 [CATrainingPosCal] consider 1 rank data
7485 11:47:14.118302 u2DelayCellTimex100 = 290/100 ps
7486 11:47:14.121608 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7487 11:47:14.128282 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7488 11:47:14.131553 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7489 11:47:14.134408 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7490 11:47:14.138256 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7491 11:47:14.141049 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7492 11:47:14.141147
7493 11:47:14.144598 CA PerBit enable=1, Macro0, CA PI delay=35
7494 11:47:14.144709
7495 11:47:14.147709 [CBTSetCACLKResult] CA Dly = 35
7496 11:47:14.151089 CS Dly: 9 (0~40)
7497 11:47:14.154702 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7498 11:47:14.158056 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7499 11:47:14.158165 ==
7500 11:47:14.161130 Dram Type= 6, Freq= 0, CH_0, rank 1
7501 11:47:14.164382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 11:47:14.164464 ==
7503 11:47:14.171050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 11:47:14.174578 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 11:47:14.181099 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 11:47:14.184327 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 11:47:14.194652 [CA 0] Center 42 (12~73) winsize 62
7508 11:47:14.198321 [CA 1] Center 42 (12~73) winsize 62
7509 11:47:14.201460 [CA 2] Center 37 (8~67) winsize 60
7510 11:47:14.204473 [CA 3] Center 37 (7~68) winsize 62
7511 11:47:14.208182 [CA 4] Center 35 (5~65) winsize 61
7512 11:47:14.211469 [CA 5] Center 35 (5~65) winsize 61
7513 11:47:14.211586
7514 11:47:14.214834 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7515 11:47:14.214937
7516 11:47:14.218066 [CATrainingPosCal] consider 2 rank data
7517 11:47:14.221434 u2DelayCellTimex100 = 290/100 ps
7518 11:47:14.224660 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7519 11:47:14.231241 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7520 11:47:14.234480 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7521 11:47:14.237936 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7522 11:47:14.241170 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7523 11:47:14.244417 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7524 11:47:14.244503
7525 11:47:14.248225 CA PerBit enable=1, Macro0, CA PI delay=35
7526 11:47:14.248310
7527 11:47:14.251448 [CBTSetCACLKResult] CA Dly = 35
7528 11:47:14.254570 CS Dly: 10 (0~42)
7529 11:47:14.257757 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 11:47:14.260876 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 11:47:14.260986
7532 11:47:14.264553 ----->DramcWriteLeveling(PI) begin...
7533 11:47:14.264647 ==
7534 11:47:14.267765 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 11:47:14.271316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 11:47:14.274577 ==
7537 11:47:14.274657 Write leveling (Byte 0): 36 => 36
7538 11:47:14.278019 Write leveling (Byte 1): 26 => 26
7539 11:47:14.281223 DramcWriteLeveling(PI) end<-----
7540 11:47:14.281308
7541 11:47:14.281384 ==
7542 11:47:14.284585 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 11:47:14.291362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 11:47:14.291474 ==
7545 11:47:14.291580 [Gating] SW mode calibration
7546 11:47:14.301096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7547 11:47:14.304265 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7548 11:47:14.307777 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 11:47:14.314427 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 11:47:14.317656 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 11:47:14.320868 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7552 11:47:14.327900 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7553 11:47:14.331248 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7554 11:47:14.334453 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 11:47:14.341032 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 11:47:14.344390 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7557 11:47:14.347697 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 11:47:14.354223 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7559 11:47:14.358000 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7560 11:47:14.361259 1 5 16 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
7561 11:47:14.367689 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7562 11:47:14.371115 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 11:47:14.374324 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 11:47:14.380962 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7565 11:47:14.384221 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:47:14.387559 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7567 11:47:14.394104 1 6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)
7568 11:47:14.397506 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7569 11:47:14.400856 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7570 11:47:14.407405 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 11:47:14.411344 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 11:47:14.414470 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 11:47:14.420756 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 11:47:14.423911 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 11:47:14.427600 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 11:47:14.430824 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7577 11:47:14.437587 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 11:47:14.440617 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 11:47:14.444120 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 11:47:14.450630 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:47:14.454190 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 11:47:14.460567 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:47:14.463663 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:47:14.467396 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:47:14.470598 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:47:14.477081 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:47:14.480211 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:47:14.484132 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:47:14.490676 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:47:14.493989 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 11:47:14.497307 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 11:47:14.504099 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 11:47:14.507441 Total UI for P1: 0, mck2ui 16
7594 11:47:14.510349 best dqsien dly found for B0: ( 1, 9, 10)
7595 11:47:14.513785 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 11:47:14.517101 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 11:47:14.520283 Total UI for P1: 0, mck2ui 16
7598 11:47:14.523499 best dqsien dly found for B1: ( 1, 9, 18)
7599 11:47:14.526778 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7600 11:47:14.530460 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7601 11:47:14.530547
7602 11:47:14.537444 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7603 11:47:14.540578 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7604 11:47:14.543789 [Gating] SW calibration Done
7605 11:47:14.543876 ==
7606 11:47:14.547178 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 11:47:14.550383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 11:47:14.550468 ==
7609 11:47:14.550535 RX Vref Scan: 0
7610 11:47:14.550597
7611 11:47:14.553647 RX Vref 0 -> 0, step: 1
7612 11:47:14.553731
7613 11:47:14.556956 RX Delay 0 -> 252, step: 8
7614 11:47:14.560479 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7615 11:47:14.563719 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7616 11:47:14.570146 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7617 11:47:14.573658 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7618 11:47:14.576701 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7619 11:47:14.579782 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7620 11:47:14.583466 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7621 11:47:14.586691 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7622 11:47:14.593029 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7623 11:47:14.596746 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7624 11:47:14.600058 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7625 11:47:14.603514 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7626 11:47:14.609389 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7627 11:47:14.612727 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7628 11:47:14.616480 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7629 11:47:14.619990 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7630 11:47:14.620074 ==
7631 11:47:14.623305 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 11:47:14.626558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 11:47:14.629409 ==
7634 11:47:14.629522 DQS Delay:
7635 11:47:14.629632 DQS0 = 0, DQS1 = 0
7636 11:47:14.633099 DQM Delay:
7637 11:47:14.633205 DQM0 = 136, DQM1 = 129
7638 11:47:14.636197 DQ Delay:
7639 11:47:14.639403 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7640 11:47:14.642663 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7641 11:47:14.646253 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7642 11:47:14.649499 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7643 11:47:14.649617
7644 11:47:14.649725
7645 11:47:14.649829 ==
7646 11:47:14.652706 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 11:47:14.655986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 11:47:14.656095 ==
7649 11:47:14.659366
7650 11:47:14.659478
7651 11:47:14.659583 TX Vref Scan disable
7652 11:47:14.662690 == TX Byte 0 ==
7653 11:47:14.665952 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7654 11:47:14.669272 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7655 11:47:14.672541 == TX Byte 1 ==
7656 11:47:14.676354 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7657 11:47:14.679690 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7658 11:47:14.679795 ==
7659 11:47:14.682860 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 11:47:14.689569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 11:47:14.689691 ==
7662 11:47:14.702179
7663 11:47:14.705324 TX Vref early break, caculate TX vref
7664 11:47:14.708773 TX Vref=16, minBit 7, minWin=22, winSum=375
7665 11:47:14.712305 TX Vref=18, minBit 1, minWin=23, winSum=389
7666 11:47:14.715526 TX Vref=20, minBit 0, minWin=24, winSum=400
7667 11:47:14.718903 TX Vref=22, minBit 0, minWin=24, winSum=407
7668 11:47:14.722112 TX Vref=24, minBit 0, minWin=25, winSum=416
7669 11:47:14.728666 TX Vref=26, minBit 2, minWin=24, winSum=423
7670 11:47:14.732377 TX Vref=28, minBit 2, minWin=25, winSum=422
7671 11:47:14.735129 TX Vref=30, minBit 1, minWin=24, winSum=413
7672 11:47:14.738348 TX Vref=32, minBit 1, minWin=24, winSum=407
7673 11:47:14.742233 TX Vref=34, minBit 6, minWin=23, winSum=396
7674 11:47:14.748668 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 28
7675 11:47:14.748779
7676 11:47:14.752004 Final TX Range 0 Vref 28
7677 11:47:14.752111
7678 11:47:14.752207 ==
7679 11:47:14.755002 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 11:47:14.758694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 11:47:14.758801 ==
7682 11:47:14.758897
7683 11:47:14.759008
7684 11:47:14.762063 TX Vref Scan disable
7685 11:47:14.768655 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7686 11:47:14.768765 == TX Byte 0 ==
7687 11:47:14.772174 u2DelayCellOfst[0]=10 cells (3 PI)
7688 11:47:14.775376 u2DelayCellOfst[1]=13 cells (4 PI)
7689 11:47:14.778700 u2DelayCellOfst[2]=10 cells (3 PI)
7690 11:47:14.782132 u2DelayCellOfst[3]=10 cells (3 PI)
7691 11:47:14.785295 u2DelayCellOfst[4]=6 cells (2 PI)
7692 11:47:14.788312 u2DelayCellOfst[5]=0 cells (0 PI)
7693 11:47:14.791443 u2DelayCellOfst[6]=16 cells (5 PI)
7694 11:47:14.795108 u2DelayCellOfst[7]=16 cells (5 PI)
7695 11:47:14.798102 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7696 11:47:14.801936 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7697 11:47:14.805049 == TX Byte 1 ==
7698 11:47:14.805157 u2DelayCellOfst[8]=3 cells (1 PI)
7699 11:47:14.808145 u2DelayCellOfst[9]=0 cells (0 PI)
7700 11:47:14.811769 u2DelayCellOfst[10]=10 cells (3 PI)
7701 11:47:14.815028 u2DelayCellOfst[11]=6 cells (2 PI)
7702 11:47:14.818430 u2DelayCellOfst[12]=10 cells (3 PI)
7703 11:47:14.821635 u2DelayCellOfst[13]=10 cells (3 PI)
7704 11:47:14.824856 u2DelayCellOfst[14]=13 cells (4 PI)
7705 11:47:14.828123 u2DelayCellOfst[15]=10 cells (3 PI)
7706 11:47:14.831576 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7707 11:47:14.838024 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7708 11:47:14.838151 DramC Write-DBI on
7709 11:47:14.838251 ==
7710 11:47:14.841441 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 11:47:14.845260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 11:47:14.845377 ==
7713 11:47:14.848154
7714 11:47:14.848272
7715 11:47:14.848394 TX Vref Scan disable
7716 11:47:14.851902 == TX Byte 0 ==
7717 11:47:14.854952 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7718 11:47:14.858250 == TX Byte 1 ==
7719 11:47:14.861629 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7720 11:47:14.864866 DramC Write-DBI off
7721 11:47:14.865000
7722 11:47:14.865111 [DATLAT]
7723 11:47:14.865221 Freq=1600, CH0 RK0
7724 11:47:14.865317
7725 11:47:14.868478 DATLAT Default: 0xf
7726 11:47:14.868595 0, 0xFFFF, sum = 0
7727 11:47:14.871898 1, 0xFFFF, sum = 0
7728 11:47:14.874608 2, 0xFFFF, sum = 0
7729 11:47:14.874729 3, 0xFFFF, sum = 0
7730 11:47:14.878380 4, 0xFFFF, sum = 0
7731 11:47:14.878501 5, 0xFFFF, sum = 0
7732 11:47:14.881689 6, 0xFFFF, sum = 0
7733 11:47:14.881811 7, 0xFFFF, sum = 0
7734 11:47:14.884942 8, 0xFFFF, sum = 0
7735 11:47:14.885077 9, 0xFFFF, sum = 0
7736 11:47:14.888315 10, 0xFFFF, sum = 0
7737 11:47:14.888447 11, 0xFFFF, sum = 0
7738 11:47:14.891624 12, 0xFFFF, sum = 0
7739 11:47:14.891737 13, 0xFFFF, sum = 0
7740 11:47:14.894919 14, 0x0, sum = 1
7741 11:47:14.895035 15, 0x0, sum = 2
7742 11:47:14.898074 16, 0x0, sum = 3
7743 11:47:14.898190 17, 0x0, sum = 4
7744 11:47:14.901197 best_step = 15
7745 11:47:14.901302
7746 11:47:14.901404 ==
7747 11:47:14.904933 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 11:47:14.908301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 11:47:14.908413 ==
7750 11:47:14.911457 RX Vref Scan: 1
7751 11:47:14.911567
7752 11:47:14.911668 Set Vref Range= 24 -> 127
7753 11:47:14.911764
7754 11:47:14.914755 RX Vref 24 -> 127, step: 1
7755 11:47:14.914863
7756 11:47:14.917980 RX Delay 19 -> 252, step: 4
7757 11:47:14.918084
7758 11:47:14.921237 Set Vref, RX VrefLevel [Byte0]: 24
7759 11:47:14.925115 [Byte1]: 24
7760 11:47:14.925225
7761 11:47:14.928353 Set Vref, RX VrefLevel [Byte0]: 25
7762 11:47:14.931537 [Byte1]: 25
7763 11:47:14.931643
7764 11:47:14.934990 Set Vref, RX VrefLevel [Byte0]: 26
7765 11:47:14.937625 [Byte1]: 26
7766 11:47:14.941678
7767 11:47:14.941789 Set Vref, RX VrefLevel [Byte0]: 27
7768 11:47:14.945055 [Byte1]: 27
7769 11:47:14.949747
7770 11:47:14.949853 Set Vref, RX VrefLevel [Byte0]: 28
7771 11:47:14.952957 [Byte1]: 28
7772 11:47:14.956899
7773 11:47:14.957011 Set Vref, RX VrefLevel [Byte0]: 29
7774 11:47:14.960671 [Byte1]: 29
7775 11:47:14.964434
7776 11:47:14.964544 Set Vref, RX VrefLevel [Byte0]: 30
7777 11:47:14.968318 [Byte1]: 30
7778 11:47:14.972248
7779 11:47:14.972352 Set Vref, RX VrefLevel [Byte0]: 31
7780 11:47:14.975263 [Byte1]: 31
7781 11:47:14.979979
7782 11:47:14.980056 Set Vref, RX VrefLevel [Byte0]: 32
7783 11:47:14.983250 [Byte1]: 32
7784 11:47:14.987318
7785 11:47:14.987421 Set Vref, RX VrefLevel [Byte0]: 33
7786 11:47:14.990585 [Byte1]: 33
7787 11:47:14.994709
7788 11:47:14.994821 Set Vref, RX VrefLevel [Byte0]: 34
7789 11:47:14.997980 [Byte1]: 34
7790 11:47:15.002702
7791 11:47:15.002819 Set Vref, RX VrefLevel [Byte0]: 35
7792 11:47:15.005638 [Byte1]: 35
7793 11:47:15.010108
7794 11:47:15.010219 Set Vref, RX VrefLevel [Byte0]: 36
7795 11:47:15.013197 [Byte1]: 36
7796 11:47:15.017772
7797 11:47:15.017880 Set Vref, RX VrefLevel [Byte0]: 37
7798 11:47:15.020910 [Byte1]: 37
7799 11:47:15.025336
7800 11:47:15.025442 Set Vref, RX VrefLevel [Byte0]: 38
7801 11:47:15.028347 [Byte1]: 38
7802 11:47:15.032857
7803 11:47:15.032940 Set Vref, RX VrefLevel [Byte0]: 39
7804 11:47:15.036194 [Byte1]: 39
7805 11:47:15.040735
7806 11:47:15.040863 Set Vref, RX VrefLevel [Byte0]: 40
7807 11:47:15.044105 [Byte1]: 40
7808 11:47:15.047860
7809 11:47:15.047977 Set Vref, RX VrefLevel [Byte0]: 41
7810 11:47:15.051147 [Byte1]: 41
7811 11:47:15.055673
7812 11:47:15.055789 Set Vref, RX VrefLevel [Byte0]: 42
7813 11:47:15.059133 [Byte1]: 42
7814 11:47:15.063046
7815 11:47:15.063155 Set Vref, RX VrefLevel [Byte0]: 43
7816 11:47:15.066198 [Byte1]: 43
7817 11:47:15.070604
7818 11:47:15.070716 Set Vref, RX VrefLevel [Byte0]: 44
7819 11:47:15.073980 [Byte1]: 44
7820 11:47:15.078449
7821 11:47:15.078540 Set Vref, RX VrefLevel [Byte0]: 45
7822 11:47:15.081555 [Byte1]: 45
7823 11:47:15.086157
7824 11:47:15.086237 Set Vref, RX VrefLevel [Byte0]: 46
7825 11:47:15.088888 [Byte1]: 46
7826 11:47:15.093551
7827 11:47:15.093656 Set Vref, RX VrefLevel [Byte0]: 47
7828 11:47:15.096949 [Byte1]: 47
7829 11:47:15.101008
7830 11:47:15.101139 Set Vref, RX VrefLevel [Byte0]: 48
7831 11:47:15.104451 [Byte1]: 48
7832 11:47:15.108709
7833 11:47:15.108835 Set Vref, RX VrefLevel [Byte0]: 49
7834 11:47:15.111985 [Byte1]: 49
7835 11:47:15.116208
7836 11:47:15.116334 Set Vref, RX VrefLevel [Byte0]: 50
7837 11:47:15.119471 [Byte1]: 50
7838 11:47:15.124107
7839 11:47:15.124226 Set Vref, RX VrefLevel [Byte0]: 51
7840 11:47:15.127343 [Byte1]: 51
7841 11:47:15.131015
7842 11:47:15.131130 Set Vref, RX VrefLevel [Byte0]: 52
7843 11:47:15.134692 [Byte1]: 52
7844 11:47:15.139284
7845 11:47:15.139406 Set Vref, RX VrefLevel [Byte0]: 53
7846 11:47:15.142455 [Byte1]: 53
7847 11:47:15.146375
7848 11:47:15.146495 Set Vref, RX VrefLevel [Byte0]: 54
7849 11:47:15.149455 [Byte1]: 54
7850 11:47:15.153944
7851 11:47:15.154066 Set Vref, RX VrefLevel [Byte0]: 55
7852 11:47:15.157240 [Byte1]: 55
7853 11:47:15.161786
7854 11:47:15.161895 Set Vref, RX VrefLevel [Byte0]: 56
7855 11:47:15.165132 [Byte1]: 56
7856 11:47:15.169118
7857 11:47:15.169201 Set Vref, RX VrefLevel [Byte0]: 57
7858 11:47:15.172235 [Byte1]: 57
7859 11:47:15.176747
7860 11:47:15.176848 Set Vref, RX VrefLevel [Byte0]: 58
7861 11:47:15.179906 [Byte1]: 58
7862 11:47:15.184561
7863 11:47:15.184669 Set Vref, RX VrefLevel [Byte0]: 59
7864 11:47:15.187706 [Byte1]: 59
7865 11:47:15.191581
7866 11:47:15.191706 Set Vref, RX VrefLevel [Byte0]: 60
7867 11:47:15.194964 [Byte1]: 60
7868 11:47:15.199622
7869 11:47:15.199757 Set Vref, RX VrefLevel [Byte0]: 61
7870 11:47:15.202969 [Byte1]: 61
7871 11:47:15.207087
7872 11:47:15.207199 Set Vref, RX VrefLevel [Byte0]: 62
7873 11:47:15.210182 [Byte1]: 62
7874 11:47:15.214682
7875 11:47:15.214808 Set Vref, RX VrefLevel [Byte0]: 63
7876 11:47:15.218029 [Byte1]: 63
7877 11:47:15.222400
7878 11:47:15.222514 Set Vref, RX VrefLevel [Byte0]: 64
7879 11:47:15.225719 [Byte1]: 64
7880 11:47:15.229575
7881 11:47:15.229695 Set Vref, RX VrefLevel [Byte0]: 65
7882 11:47:15.232792 [Byte1]: 65
7883 11:47:15.237390
7884 11:47:15.237509 Set Vref, RX VrefLevel [Byte0]: 66
7885 11:47:15.240448 [Byte1]: 66
7886 11:47:15.245041
7887 11:47:15.245149 Set Vref, RX VrefLevel [Byte0]: 67
7888 11:47:15.248338 [Byte1]: 67
7889 11:47:15.252119
7890 11:47:15.252228 Set Vref, RX VrefLevel [Byte0]: 68
7891 11:47:15.255989 [Byte1]: 68
7892 11:47:15.259894
7893 11:47:15.260008 Set Vref, RX VrefLevel [Byte0]: 69
7894 11:47:15.263310 [Byte1]: 69
7895 11:47:15.267987
7896 11:47:15.268107 Set Vref, RX VrefLevel [Byte0]: 70
7897 11:47:15.271284 [Byte1]: 70
7898 11:47:15.275190
7899 11:47:15.275309 Set Vref, RX VrefLevel [Byte0]: 71
7900 11:47:15.278455 [Byte1]: 71
7901 11:47:15.282913
7902 11:47:15.283020 Set Vref, RX VrefLevel [Byte0]: 72
7903 11:47:15.286096 [Byte1]: 72
7904 11:47:15.290078
7905 11:47:15.290188 Set Vref, RX VrefLevel [Byte0]: 73
7906 11:47:15.293437 [Byte1]: 73
7907 11:47:15.297734
7908 11:47:15.297847 Set Vref, RX VrefLevel [Byte0]: 74
7909 11:47:15.300929 [Byte1]: 74
7910 11:47:15.305486
7911 11:47:15.305595 Set Vref, RX VrefLevel [Byte0]: 75
7912 11:47:15.308699 [Byte1]: 75
7913 11:47:15.313409
7914 11:47:15.313493 Final RX Vref Byte 0 = 54 to rank0
7915 11:47:15.316228 Final RX Vref Byte 1 = 60 to rank0
7916 11:47:15.320126 Final RX Vref Byte 0 = 54 to rank1
7917 11:47:15.322743 Final RX Vref Byte 1 = 60 to rank1==
7918 11:47:15.326531 Dram Type= 6, Freq= 0, CH_0, rank 0
7919 11:47:15.332749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7920 11:47:15.332861 ==
7921 11:47:15.332931 DQS Delay:
7922 11:47:15.332995 DQS0 = 0, DQS1 = 0
7923 11:47:15.336524 DQM Delay:
7924 11:47:15.336609 DQM0 = 133, DQM1 = 127
7925 11:47:15.339680 DQ Delay:
7926 11:47:15.342802 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7927 11:47:15.346564 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7928 11:47:15.349751 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7929 11:47:15.353052 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7930 11:47:15.353138
7931 11:47:15.353220
7932 11:47:15.353283
7933 11:47:15.356155 [DramC_TX_OE_Calibration] TA2
7934 11:47:15.359352 Original DQ_B0 (3 6) =30, OEN = 27
7935 11:47:15.363177 Original DQ_B1 (3 6) =30, OEN = 27
7936 11:47:15.365860 24, 0x0, End_B0=24 End_B1=24
7937 11:47:15.365952 25, 0x0, End_B0=25 End_B1=25
7938 11:47:15.369343 26, 0x0, End_B0=26 End_B1=26
7939 11:47:15.372585 27, 0x0, End_B0=27 End_B1=27
7940 11:47:15.375890 28, 0x0, End_B0=28 End_B1=28
7941 11:47:15.379347 29, 0x0, End_B0=29 End_B1=29
7942 11:47:15.379459 30, 0x0, End_B0=30 End_B1=30
7943 11:47:15.382516 31, 0x4141, End_B0=30 End_B1=30
7944 11:47:15.386458 Byte0 end_step=30 best_step=27
7945 11:47:15.389551 Byte1 end_step=30 best_step=27
7946 11:47:15.392920 Byte0 TX OE(2T, 0.5T) = (3, 3)
7947 11:47:15.396270 Byte1 TX OE(2T, 0.5T) = (3, 3)
7948 11:47:15.396374
7949 11:47:15.396470
7950 11:47:15.402574 [DQSOSCAuto] RK0, (LSB)MR18= 0x2520, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7951 11:47:15.406244 CH0 RK0: MR19=303, MR18=2520
7952 11:47:15.413070 CH0_RK0: MR19=0x303, MR18=0x2520, DQSOSC=391, MR23=63, INC=24, DEC=16
7953 11:47:15.413191
7954 11:47:15.416244 ----->DramcWriteLeveling(PI) begin...
7955 11:47:15.416363 ==
7956 11:47:15.419452 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 11:47:15.422768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 11:47:15.422890 ==
7959 11:47:15.425568 Write leveling (Byte 0): 36 => 36
7960 11:47:15.429351 Write leveling (Byte 1): 29 => 29
7961 11:47:15.432504 DramcWriteLeveling(PI) end<-----
7962 11:47:15.432603
7963 11:47:15.432698 ==
7964 11:47:15.435737 Dram Type= 6, Freq= 0, CH_0, rank 1
7965 11:47:15.438908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 11:47:15.439046 ==
7967 11:47:15.442194 [Gating] SW mode calibration
7968 11:47:15.449294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7969 11:47:15.455482 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7970 11:47:15.458677 1 4 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7971 11:47:15.462356 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 11:47:15.469286 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 11:47:15.472494 1 4 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7974 11:47:15.479030 1 4 16 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7975 11:47:15.481712 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7976 11:47:15.485031 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7977 11:47:15.492181 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7978 11:47:15.495228 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 11:47:15.498360 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7980 11:47:15.501595 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7981 11:47:15.508745 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
7982 11:47:15.511894 1 5 16 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
7983 11:47:15.515263 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 11:47:15.522044 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7985 11:47:15.525361 1 5 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7986 11:47:15.528749 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 11:47:15.535324 1 6 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7988 11:47:15.538599 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7989 11:47:15.541923 1 6 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7990 11:47:15.548449 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
7991 11:47:15.552069 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 11:47:15.555137 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 11:47:15.561817 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 11:47:15.565034 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 11:47:15.568639 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 11:47:15.574960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 11:47:15.578680 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7998 11:47:15.581782 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7999 11:47:15.588430 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 11:47:15.591840 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 11:47:15.595020 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:47:15.601561 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:47:15.605131 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:47:15.608378 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:47:15.614904 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:47:15.618228 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 11:47:15.621639 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 11:47:15.624735 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 11:47:15.631362 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 11:47:15.634692 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 11:47:15.638102 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:47:15.644712 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:47:15.648080 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8014 11:47:15.651368 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 11:47:15.658492 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 11:47:15.661662 Total UI for P1: 0, mck2ui 16
8017 11:47:15.664572 best dqsien dly found for B0: ( 1, 9, 14)
8018 11:47:15.664687 Total UI for P1: 0, mck2ui 16
8019 11:47:15.671335 best dqsien dly found for B1: ( 1, 9, 14)
8020 11:47:15.674621 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8021 11:47:15.678317 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8022 11:47:15.678429
8023 11:47:15.681562 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8024 11:47:15.684796 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8025 11:47:15.688018 [Gating] SW calibration Done
8026 11:47:15.688137 ==
8027 11:47:15.691185 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 11:47:15.694584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 11:47:15.694712 ==
8030 11:47:15.697981 RX Vref Scan: 0
8031 11:47:15.698095
8032 11:47:15.698209 RX Vref 0 -> 0, step: 1
8033 11:47:15.698318
8034 11:47:15.701213 RX Delay 0 -> 252, step: 8
8035 11:47:15.704575 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8036 11:47:15.711732 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8037 11:47:15.714774 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8038 11:47:15.717708 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8039 11:47:15.721546 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8040 11:47:15.724532 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8041 11:47:15.731143 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8042 11:47:15.734346 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8043 11:47:15.737620 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8044 11:47:15.740930 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8045 11:47:15.744259 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8046 11:47:15.750982 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8047 11:47:15.754289 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8048 11:47:15.757571 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8049 11:47:15.760983 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8050 11:47:15.767993 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8051 11:47:15.768103 ==
8052 11:47:15.771143 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 11:47:15.774248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 11:47:15.774372 ==
8055 11:47:15.774477 DQS Delay:
8056 11:47:15.777463 DQS0 = 0, DQS1 = 0
8057 11:47:15.777574 DQM Delay:
8058 11:47:15.781174 DQM0 = 137, DQM1 = 128
8059 11:47:15.781283 DQ Delay:
8060 11:47:15.784367 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8061 11:47:15.787483 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8062 11:47:15.791280 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8063 11:47:15.794431 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8064 11:47:15.794537
8065 11:47:15.794645
8066 11:47:15.797562 ==
8067 11:47:15.797680 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 11:47:15.804219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 11:47:15.804328 ==
8070 11:47:15.804421
8071 11:47:15.804514
8072 11:47:15.804604 TX Vref Scan disable
8073 11:47:15.808101 == TX Byte 0 ==
8074 11:47:15.811380 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8075 11:47:15.814607 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8076 11:47:15.817899 == TX Byte 1 ==
8077 11:47:15.821708 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8078 11:47:15.824952 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8079 11:47:15.828080 ==
8080 11:47:15.831323 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 11:47:15.834457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 11:47:15.834561 ==
8083 11:47:15.847803
8084 11:47:15.851068 TX Vref early break, caculate TX vref
8085 11:47:15.854429 TX Vref=16, minBit 1, minWin=23, winSum=386
8086 11:47:15.857702 TX Vref=18, minBit 1, minWin=23, winSum=394
8087 11:47:15.860984 TX Vref=20, minBit 1, minWin=23, winSum=403
8088 11:47:15.864261 TX Vref=22, minBit 1, minWin=24, winSum=412
8089 11:47:15.867618 TX Vref=24, minBit 1, minWin=25, winSum=419
8090 11:47:15.874655 TX Vref=26, minBit 3, minWin=25, winSum=427
8091 11:47:15.877773 TX Vref=28, minBit 1, minWin=25, winSum=423
8092 11:47:15.881043 TX Vref=30, minBit 0, minWin=25, winSum=420
8093 11:47:15.884337 TX Vref=32, minBit 4, minWin=24, winSum=411
8094 11:47:15.887594 TX Vref=34, minBit 0, minWin=24, winSum=397
8095 11:47:15.893988 [TxChooseVref] Worse bit 3, Min win 25, Win sum 427, Final Vref 26
8096 11:47:15.894099
8097 11:47:15.897932 Final TX Range 0 Vref 26
8098 11:47:15.898042
8099 11:47:15.898174 ==
8100 11:47:15.901037 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 11:47:15.904052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 11:47:15.904158 ==
8103 11:47:15.904254
8104 11:47:15.904345
8105 11:47:15.907337 TX Vref Scan disable
8106 11:47:15.914047 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8107 11:47:15.914156 == TX Byte 0 ==
8108 11:47:15.917360 u2DelayCellOfst[0]=13 cells (4 PI)
8109 11:47:15.920670 u2DelayCellOfst[1]=13 cells (4 PI)
8110 11:47:15.924012 u2DelayCellOfst[2]=10 cells (3 PI)
8111 11:47:15.927942 u2DelayCellOfst[3]=6 cells (2 PI)
8112 11:47:15.930999 u2DelayCellOfst[4]=6 cells (2 PI)
8113 11:47:15.934147 u2DelayCellOfst[5]=0 cells (0 PI)
8114 11:47:15.937423 u2DelayCellOfst[6]=13 cells (4 PI)
8115 11:47:15.940575 u2DelayCellOfst[7]=13 cells (4 PI)
8116 11:47:15.943772 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8117 11:47:15.947745 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8118 11:47:15.951093 == TX Byte 1 ==
8119 11:47:15.951204 u2DelayCellOfst[8]=3 cells (1 PI)
8120 11:47:15.954299 u2DelayCellOfst[9]=0 cells (0 PI)
8121 11:47:15.957590 u2DelayCellOfst[10]=6 cells (2 PI)
8122 11:47:15.961067 u2DelayCellOfst[11]=3 cells (1 PI)
8123 11:47:15.964147 u2DelayCellOfst[12]=10 cells (3 PI)
8124 11:47:15.967549 u2DelayCellOfst[13]=10 cells (3 PI)
8125 11:47:15.970766 u2DelayCellOfst[14]=13 cells (4 PI)
8126 11:47:15.974044 u2DelayCellOfst[15]=10 cells (3 PI)
8127 11:47:15.977267 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8128 11:47:15.984249 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8129 11:47:15.984333 DramC Write-DBI on
8130 11:47:15.984399 ==
8131 11:47:15.987427 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 11:47:15.990774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 11:47:15.993726 ==
8134 11:47:15.993812
8135 11:47:15.993878
8136 11:47:15.993939 TX Vref Scan disable
8137 11:47:15.997482 == TX Byte 0 ==
8138 11:47:16.000712 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8139 11:47:16.004046 == TX Byte 1 ==
8140 11:47:16.007202 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8141 11:47:16.010433 DramC Write-DBI off
8142 11:47:16.010544
8143 11:47:16.010639 [DATLAT]
8144 11:47:16.010731 Freq=1600, CH0 RK1
8145 11:47:16.010819
8146 11:47:16.013627 DATLAT Default: 0xf
8147 11:47:16.017060 0, 0xFFFF, sum = 0
8148 11:47:16.017136 1, 0xFFFF, sum = 0
8149 11:47:16.020291 2, 0xFFFF, sum = 0
8150 11:47:16.020393 3, 0xFFFF, sum = 0
8151 11:47:16.023634 4, 0xFFFF, sum = 0
8152 11:47:16.023735 5, 0xFFFF, sum = 0
8153 11:47:16.026946 6, 0xFFFF, sum = 0
8154 11:47:16.027045 7, 0xFFFF, sum = 0
8155 11:47:16.030327 8, 0xFFFF, sum = 0
8156 11:47:16.030426 9, 0xFFFF, sum = 0
8157 11:47:16.033670 10, 0xFFFF, sum = 0
8158 11:47:16.033744 11, 0xFFFF, sum = 0
8159 11:47:16.036925 12, 0xFFFF, sum = 0
8160 11:47:16.037004 13, 0xFFFF, sum = 0
8161 11:47:16.040099 14, 0x0, sum = 1
8162 11:47:16.040200 15, 0x0, sum = 2
8163 11:47:16.043989 16, 0x0, sum = 3
8164 11:47:16.044061 17, 0x0, sum = 4
8165 11:47:16.047133 best_step = 15
8166 11:47:16.047232
8167 11:47:16.047321 ==
8168 11:47:16.050369 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 11:47:16.053623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 11:47:16.053721 ==
8171 11:47:16.057000 RX Vref Scan: 0
8172 11:47:16.057096
8173 11:47:16.057172 RX Vref 0 -> 0, step: 1
8174 11:47:16.057234
8175 11:47:16.060313 RX Delay 19 -> 252, step: 4
8176 11:47:16.063592 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8177 11:47:16.070223 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8178 11:47:16.073616 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8179 11:47:16.076960 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8180 11:47:16.080219 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8181 11:47:16.083324 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8182 11:47:16.090171 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8183 11:47:16.093300 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8184 11:47:16.096598 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8185 11:47:16.100361 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8186 11:47:16.103529 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8187 11:47:16.109759 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8188 11:47:16.113394 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8189 11:47:16.116897 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8190 11:47:16.119990 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8191 11:47:16.123366 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8192 11:47:16.126736 ==
8193 11:47:16.130050 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 11:47:16.133231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 11:47:16.133309 ==
8196 11:47:16.133374 DQS Delay:
8197 11:47:16.136529 DQS0 = 0, DQS1 = 0
8198 11:47:16.136627 DQM Delay:
8199 11:47:16.139853 DQM0 = 134, DQM1 = 127
8200 11:47:16.139953 DQ Delay:
8201 11:47:16.143192 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =132
8202 11:47:16.146257 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =142
8203 11:47:16.150248 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8204 11:47:16.153268 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8205 11:47:16.153342
8206 11:47:16.153404
8207 11:47:16.153464
8208 11:47:16.156370 [DramC_TX_OE_Calibration] TA2
8209 11:47:16.159694 Original DQ_B0 (3 6) =30, OEN = 27
8210 11:47:16.162962 Original DQ_B1 (3 6) =30, OEN = 27
8211 11:47:16.166321 24, 0x0, End_B0=24 End_B1=24
8212 11:47:16.169600 25, 0x0, End_B0=25 End_B1=25
8213 11:47:16.169703 26, 0x0, End_B0=26 End_B1=26
8214 11:47:16.173013 27, 0x0, End_B0=27 End_B1=27
8215 11:47:16.176372 28, 0x0, End_B0=28 End_B1=28
8216 11:47:16.179632 29, 0x0, End_B0=29 End_B1=29
8217 11:47:16.183057 30, 0x0, End_B0=30 End_B1=30
8218 11:47:16.183143 31, 0x4141, End_B0=30 End_B1=30
8219 11:47:16.186379 Byte0 end_step=30 best_step=27
8220 11:47:16.189667 Byte1 end_step=30 best_step=27
8221 11:47:16.193083 Byte0 TX OE(2T, 0.5T) = (3, 3)
8222 11:47:16.196090 Byte1 TX OE(2T, 0.5T) = (3, 3)
8223 11:47:16.196176
8224 11:47:16.196243
8225 11:47:16.202985 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8226 11:47:16.206111 CH0 RK1: MR19=303, MR18=2008
8227 11:47:16.213202 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8228 11:47:16.216399 [RxdqsGatingPostProcess] freq 1600
8229 11:47:16.222790 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8230 11:47:16.222879 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 11:47:16.226477 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 11:47:16.229897 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 11:47:16.233182 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 11:47:16.236396 best DQS0 dly(2T, 0.5T) = (1, 1)
8235 11:47:16.239669 best DQS1 dly(2T, 0.5T) = (1, 1)
8236 11:47:16.242925 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8237 11:47:16.246386 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8238 11:47:16.249534 Pre-setting of DQS Precalculation
8239 11:47:16.252779 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8240 11:47:16.252892 ==
8241 11:47:16.255984 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 11:47:16.262899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8243 11:47:16.263010 ==
8244 11:47:16.266177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8245 11:47:16.273073 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8246 11:47:16.276205 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8247 11:47:16.282932 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8248 11:47:16.290274 [CA 0] Center 42 (12~72) winsize 61
8249 11:47:16.293565 [CA 1] Center 42 (12~72) winsize 61
8250 11:47:16.296933 [CA 2] Center 38 (9~68) winsize 60
8251 11:47:16.300259 [CA 3] Center 38 (9~67) winsize 59
8252 11:47:16.303234 [CA 4] Center 38 (9~68) winsize 60
8253 11:47:16.307030 [CA 5] Center 37 (8~67) winsize 60
8254 11:47:16.307133
8255 11:47:16.310100 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8256 11:47:16.310209
8257 11:47:16.313294 [CATrainingPosCal] consider 1 rank data
8258 11:47:16.316453 u2DelayCellTimex100 = 290/100 ps
8259 11:47:16.320257 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8260 11:47:16.326617 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8261 11:47:16.330262 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8262 11:47:16.333415 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8263 11:47:16.336772 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8264 11:47:16.340187 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8265 11:47:16.340311
8266 11:47:16.343206 CA PerBit enable=1, Macro0, CA PI delay=37
8267 11:47:16.343334
8268 11:47:16.346416 [CBTSetCACLKResult] CA Dly = 37
8269 11:47:16.349882 CS Dly: 11 (0~42)
8270 11:47:16.353177 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8271 11:47:16.356958 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8272 11:47:16.357048 ==
8273 11:47:16.360156 Dram Type= 6, Freq= 0, CH_1, rank 1
8274 11:47:16.363462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 11:47:16.363543 ==
8276 11:47:16.369968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8277 11:47:16.373303 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8278 11:47:16.379832 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8279 11:47:16.383189 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8280 11:47:16.393733 [CA 0] Center 42 (12~72) winsize 61
8281 11:47:16.396952 [CA 1] Center 42 (13~72) winsize 60
8282 11:47:16.400464 [CA 2] Center 39 (9~69) winsize 61
8283 11:47:16.403708 [CA 3] Center 38 (9~68) winsize 60
8284 11:47:16.406848 [CA 4] Center 39 (9~69) winsize 61
8285 11:47:16.410481 [CA 5] Center 38 (9~67) winsize 59
8286 11:47:16.410580
8287 11:47:16.413687 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8288 11:47:16.413765
8289 11:47:16.416704 [CATrainingPosCal] consider 2 rank data
8290 11:47:16.419857 u2DelayCellTimex100 = 290/100 ps
8291 11:47:16.423654 CA0 delay=42 (12~72),Diff = 4 PI (13 cell)
8292 11:47:16.430664 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8293 11:47:16.433844 CA2 delay=38 (9~68),Diff = 0 PI (0 cell)
8294 11:47:16.436852 CA3 delay=38 (9~67),Diff = 0 PI (0 cell)
8295 11:47:16.440040 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8296 11:47:16.443383 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8297 11:47:16.443466
8298 11:47:16.446743 CA PerBit enable=1, Macro0, CA PI delay=38
8299 11:47:16.446825
8300 11:47:16.450032 [CBTSetCACLKResult] CA Dly = 38
8301 11:47:16.450134 CS Dly: 12 (0~45)
8302 11:47:16.456794 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8303 11:47:16.460147 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8304 11:47:16.460230
8305 11:47:16.463391 ----->DramcWriteLeveling(PI) begin...
8306 11:47:16.463472 ==
8307 11:47:16.467035 Dram Type= 6, Freq= 0, CH_1, rank 0
8308 11:47:16.470285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8309 11:47:16.473294 ==
8310 11:47:16.473375 Write leveling (Byte 0): 24 => 24
8311 11:47:16.476681 Write leveling (Byte 1): 27 => 27
8312 11:47:16.480020 DramcWriteLeveling(PI) end<-----
8313 11:47:16.480102
8314 11:47:16.480167 ==
8315 11:47:16.483218 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 11:47:16.489807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 11:47:16.489913 ==
8318 11:47:16.490012 [Gating] SW mode calibration
8319 11:47:16.499775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8320 11:47:16.503132 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8321 11:47:16.509751 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 11:47:16.512708 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 11:47:16.516045 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
8324 11:47:16.519980 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8325 11:47:16.526282 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 11:47:16.529986 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 11:47:16.533189 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 11:47:16.539597 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 11:47:16.542783 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 11:47:16.545898 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 11:47:16.552511 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
8332 11:47:16.556360 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8333 11:47:16.559676 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 11:47:16.566350 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 11:47:16.569490 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 11:47:16.572613 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 11:47:16.579492 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 11:47:16.582740 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 11:47:16.586098 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8340 11:47:16.592702 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8341 11:47:16.596046 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 11:47:16.599493 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 11:47:16.606068 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 11:47:16.609436 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 11:47:16.612223 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 11:47:16.619338 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 11:47:16.622444 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 11:47:16.625728 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8349 11:47:16.632114 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8350 11:47:16.635991 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:47:16.639150 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:47:16.645591 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:47:16.648720 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:47:16.652629 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:47:16.658990 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:47:16.662274 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 11:47:16.665730 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 11:47:16.672280 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 11:47:16.675738 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:47:16.678891 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:47:16.685669 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:47:16.688931 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:47:16.692114 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8364 11:47:16.695373 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 11:47:16.702150 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 11:47:16.705343 Total UI for P1: 0, mck2ui 16
8367 11:47:16.708763 best dqsien dly found for B0: ( 1, 9, 10)
8368 11:47:16.711920 Total UI for P1: 0, mck2ui 16
8369 11:47:16.715239 best dqsien dly found for B1: ( 1, 9, 12)
8370 11:47:16.718587 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8371 11:47:16.721875 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8372 11:47:16.721990
8373 11:47:16.725168 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8374 11:47:16.728973 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8375 11:47:16.731795 [Gating] SW calibration Done
8376 11:47:16.731907 ==
8377 11:47:16.735518 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 11:47:16.738679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 11:47:16.738784 ==
8380 11:47:16.741822 RX Vref Scan: 0
8381 11:47:16.741922
8382 11:47:16.745555 RX Vref 0 -> 0, step: 1
8383 11:47:16.745635
8384 11:47:16.745719 RX Delay 0 -> 252, step: 8
8385 11:47:16.751974 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8386 11:47:16.755212 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8387 11:47:16.758352 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8388 11:47:16.761682 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8389 11:47:16.764948 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8390 11:47:16.771896 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8391 11:47:16.775179 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8392 11:47:16.778417 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8393 11:47:16.781771 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8394 11:47:16.785011 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8395 11:47:16.788241 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8396 11:47:16.795117 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8397 11:47:16.798342 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8398 11:47:16.801620 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8399 11:47:16.805227 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8400 11:47:16.811764 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8401 11:47:16.811877 ==
8402 11:47:16.815141 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 11:47:16.818383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 11:47:16.818469 ==
8405 11:47:16.818537 DQS Delay:
8406 11:47:16.821711 DQS0 = 0, DQS1 = 0
8407 11:47:16.821796 DQM Delay:
8408 11:47:16.825190 DQM0 = 136, DQM1 = 132
8409 11:47:16.825275 DQ Delay:
8410 11:47:16.828422 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8411 11:47:16.831675 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8412 11:47:16.834618 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8413 11:47:16.838398 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8414 11:47:16.838484
8415 11:47:16.838551
8416 11:47:16.841470 ==
8417 11:47:16.845184 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 11:47:16.848364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 11:47:16.848450 ==
8420 11:47:16.848517
8421 11:47:16.848588
8422 11:47:16.851653 TX Vref Scan disable
8423 11:47:16.851739 == TX Byte 0 ==
8424 11:47:16.854660 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8425 11:47:16.861583 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8426 11:47:16.861669 == TX Byte 1 ==
8427 11:47:16.864651 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8428 11:47:16.871568 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8429 11:47:16.871654 ==
8430 11:47:16.874779 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 11:47:16.878016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 11:47:16.878119 ==
8433 11:47:16.891166
8434 11:47:16.894432 TX Vref early break, caculate TX vref
8435 11:47:16.897455 TX Vref=16, minBit 0, minWin=22, winSum=379
8436 11:47:16.901450 TX Vref=18, minBit 0, minWin=23, winSum=386
8437 11:47:16.904606 TX Vref=20, minBit 1, minWin=23, winSum=395
8438 11:47:16.907895 TX Vref=22, minBit 1, minWin=24, winSum=405
8439 11:47:16.911219 TX Vref=24, minBit 1, minWin=24, winSum=416
8440 11:47:16.917354 TX Vref=26, minBit 0, minWin=26, winSum=428
8441 11:47:16.920663 TX Vref=28, minBit 0, minWin=26, winSum=430
8442 11:47:16.923996 TX Vref=30, minBit 0, minWin=25, winSum=424
8443 11:47:16.927356 TX Vref=32, minBit 0, minWin=25, winSum=415
8444 11:47:16.930674 TX Vref=34, minBit 0, minWin=24, winSum=401
8445 11:47:16.937416 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8446 11:47:16.937501
8447 11:47:16.940647 Final TX Range 0 Vref 28
8448 11:47:16.940732
8449 11:47:16.940798 ==
8450 11:47:16.944471 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 11:47:16.947598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 11:47:16.947682 ==
8453 11:47:16.947749
8454 11:47:16.947811
8455 11:47:16.951028 TX Vref Scan disable
8456 11:47:16.957171 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8457 11:47:16.957256 == TX Byte 0 ==
8458 11:47:16.960921 u2DelayCellOfst[0]=16 cells (5 PI)
8459 11:47:16.964057 u2DelayCellOfst[1]=10 cells (3 PI)
8460 11:47:16.967250 u2DelayCellOfst[2]=0 cells (0 PI)
8461 11:47:16.971006 u2DelayCellOfst[3]=6 cells (2 PI)
8462 11:47:16.974134 u2DelayCellOfst[4]=6 cells (2 PI)
8463 11:47:16.977368 u2DelayCellOfst[5]=20 cells (6 PI)
8464 11:47:16.977472 u2DelayCellOfst[6]=16 cells (5 PI)
8465 11:47:16.980596 u2DelayCellOfst[7]=6 cells (2 PI)
8466 11:47:16.987288 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8467 11:47:16.990599 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8468 11:47:16.990707 == TX Byte 1 ==
8469 11:47:16.994073 u2DelayCellOfst[8]=0 cells (0 PI)
8470 11:47:16.997320 u2DelayCellOfst[9]=6 cells (2 PI)
8471 11:47:17.000625 u2DelayCellOfst[10]=13 cells (4 PI)
8472 11:47:17.004337 u2DelayCellOfst[11]=3 cells (1 PI)
8473 11:47:17.007644 u2DelayCellOfst[12]=16 cells (5 PI)
8474 11:47:17.011013 u2DelayCellOfst[13]=16 cells (5 PI)
8475 11:47:17.014136 u2DelayCellOfst[14]=16 cells (5 PI)
8476 11:47:17.017552 u2DelayCellOfst[15]=16 cells (5 PI)
8477 11:47:17.020865 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8478 11:47:17.027501 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8479 11:47:17.027590 DramC Write-DBI on
8480 11:47:17.027686 ==
8481 11:47:17.030788 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 11:47:17.034250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 11:47:17.034341 ==
8484 11:47:17.034405
8485 11:47:17.037388
8486 11:47:17.037522 TX Vref Scan disable
8487 11:47:17.040708 == TX Byte 0 ==
8488 11:47:17.043869 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8489 11:47:17.047142 == TX Byte 1 ==
8490 11:47:17.050168 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8491 11:47:17.050255 DramC Write-DBI off
8492 11:47:17.050316
8493 11:47:17.053983 [DATLAT]
8494 11:47:17.054105 Freq=1600, CH1 RK0
8495 11:47:17.054170
8496 11:47:17.056668 DATLAT Default: 0xf
8497 11:47:17.056751 0, 0xFFFF, sum = 0
8498 11:47:17.060483 1, 0xFFFF, sum = 0
8499 11:47:17.060567 2, 0xFFFF, sum = 0
8500 11:47:17.063734 3, 0xFFFF, sum = 0
8501 11:47:17.063820 4, 0xFFFF, sum = 0
8502 11:47:17.066918 5, 0xFFFF, sum = 0
8503 11:47:17.070717 6, 0xFFFF, sum = 0
8504 11:47:17.070832 7, 0xFFFF, sum = 0
8505 11:47:17.073900 8, 0xFFFF, sum = 0
8506 11:47:17.074029 9, 0xFFFF, sum = 0
8507 11:47:17.077132 10, 0xFFFF, sum = 0
8508 11:47:17.077215 11, 0xFFFF, sum = 0
8509 11:47:17.080274 12, 0xFFFF, sum = 0
8510 11:47:17.080357 13, 0xFFFF, sum = 0
8511 11:47:17.083442 14, 0x0, sum = 1
8512 11:47:17.083536 15, 0x0, sum = 2
8513 11:47:17.086764 16, 0x0, sum = 3
8514 11:47:17.086848 17, 0x0, sum = 4
8515 11:47:17.090037 best_step = 15
8516 11:47:17.090118
8517 11:47:17.090182 ==
8518 11:47:17.093584 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 11:47:17.096680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 11:47:17.096756 ==
8521 11:47:17.096844 RX Vref Scan: 1
8522 11:47:17.100048
8523 11:47:17.100131 Set Vref Range= 24 -> 127
8524 11:47:17.100195
8525 11:47:17.103338 RX Vref 24 -> 127, step: 1
8526 11:47:17.103421
8527 11:47:17.106604 RX Delay 27 -> 252, step: 4
8528 11:47:17.106690
8529 11:47:17.109708 Set Vref, RX VrefLevel [Byte0]: 24
8530 11:47:17.113395 [Byte1]: 24
8531 11:47:17.113477
8532 11:47:17.116636 Set Vref, RX VrefLevel [Byte0]: 25
8533 11:47:17.120056 [Byte1]: 25
8534 11:47:17.120132
8535 11:47:17.123316 Set Vref, RX VrefLevel [Byte0]: 26
8536 11:47:17.126727 [Byte1]: 26
8537 11:47:17.130677
8538 11:47:17.130754 Set Vref, RX VrefLevel [Byte0]: 27
8539 11:47:17.133955 [Byte1]: 27
8540 11:47:17.138015
8541 11:47:17.138119 Set Vref, RX VrefLevel [Byte0]: 28
8542 11:47:17.141309 [Byte1]: 28
8543 11:47:17.145455
8544 11:47:17.145557 Set Vref, RX VrefLevel [Byte0]: 29
8545 11:47:17.148634 [Byte1]: 29
8546 11:47:17.153188
8547 11:47:17.153272 Set Vref, RX VrefLevel [Byte0]: 30
8548 11:47:17.156285 [Byte1]: 30
8549 11:47:17.160535
8550 11:47:17.160645 Set Vref, RX VrefLevel [Byte0]: 31
8551 11:47:17.163896 [Byte1]: 31
8552 11:47:17.168361
8553 11:47:17.168447 Set Vref, RX VrefLevel [Byte0]: 32
8554 11:47:17.171385 [Byte1]: 32
8555 11:47:17.175349
8556 11:47:17.175434 Set Vref, RX VrefLevel [Byte0]: 33
8557 11:47:17.178632 [Byte1]: 33
8558 11:47:17.183017
8559 11:47:17.183104 Set Vref, RX VrefLevel [Byte0]: 34
8560 11:47:17.186522 [Byte1]: 34
8561 11:47:17.190336
8562 11:47:17.190421 Set Vref, RX VrefLevel [Byte0]: 35
8563 11:47:17.193687 [Byte1]: 35
8564 11:47:17.198357
8565 11:47:17.198440 Set Vref, RX VrefLevel [Byte0]: 36
8566 11:47:17.201535 [Byte1]: 36
8567 11:47:17.205584
8568 11:47:17.205697 Set Vref, RX VrefLevel [Byte0]: 37
8569 11:47:17.208908 [Byte1]: 37
8570 11:47:17.213279
8571 11:47:17.213377 Set Vref, RX VrefLevel [Byte0]: 38
8572 11:47:17.216468 [Byte1]: 38
8573 11:47:17.220690
8574 11:47:17.220812 Set Vref, RX VrefLevel [Byte0]: 39
8575 11:47:17.224360 [Byte1]: 39
8576 11:47:17.228248
8577 11:47:17.228375 Set Vref, RX VrefLevel [Byte0]: 40
8578 11:47:17.231598 [Byte1]: 40
8579 11:47:17.235562
8580 11:47:17.235684 Set Vref, RX VrefLevel [Byte0]: 41
8581 11:47:17.238962 [Byte1]: 41
8582 11:47:17.243579
8583 11:47:17.243687 Set Vref, RX VrefLevel [Byte0]: 42
8584 11:47:17.246353 [Byte1]: 42
8585 11:47:17.251125
8586 11:47:17.251242 Set Vref, RX VrefLevel [Byte0]: 43
8587 11:47:17.254321 [Byte1]: 43
8588 11:47:17.258560
8589 11:47:17.258678 Set Vref, RX VrefLevel [Byte0]: 44
8590 11:47:17.261560 [Byte1]: 44
8591 11:47:17.265916
8592 11:47:17.266024 Set Vref, RX VrefLevel [Byte0]: 45
8593 11:47:17.268939 [Byte1]: 45
8594 11:47:17.273273
8595 11:47:17.273389 Set Vref, RX VrefLevel [Byte0]: 46
8596 11:47:17.277057 [Byte1]: 46
8597 11:47:17.281515
8598 11:47:17.281628 Set Vref, RX VrefLevel [Byte0]: 47
8599 11:47:17.284581 [Byte1]: 47
8600 11:47:17.288400
8601 11:47:17.288512 Set Vref, RX VrefLevel [Byte0]: 48
8602 11:47:17.291549 [Byte1]: 48
8603 11:47:17.295987
8604 11:47:17.296085 Set Vref, RX VrefLevel [Byte0]: 49
8605 11:47:17.299348 [Byte1]: 49
8606 11:47:17.303349
8607 11:47:17.303427 Set Vref, RX VrefLevel [Byte0]: 50
8608 11:47:17.306739 [Byte1]: 50
8609 11:47:17.311449
8610 11:47:17.311526 Set Vref, RX VrefLevel [Byte0]: 51
8611 11:47:17.314698 [Byte1]: 51
8612 11:47:17.318703
8613 11:47:17.318788 Set Vref, RX VrefLevel [Byte0]: 52
8614 11:47:17.322231 [Byte1]: 52
8615 11:47:17.326313
8616 11:47:17.326398 Set Vref, RX VrefLevel [Byte0]: 53
8617 11:47:17.329487 [Byte1]: 53
8618 11:47:17.333709
8619 11:47:17.333804 Set Vref, RX VrefLevel [Byte0]: 54
8620 11:47:17.336940 [Byte1]: 54
8621 11:47:17.341003
8622 11:47:17.341081 Set Vref, RX VrefLevel [Byte0]: 55
8623 11:47:17.344331 [Byte1]: 55
8624 11:47:17.349106
8625 11:47:17.349182 Set Vref, RX VrefLevel [Byte0]: 56
8626 11:47:17.352297 [Byte1]: 56
8627 11:47:17.356384
8628 11:47:17.356458 Set Vref, RX VrefLevel [Byte0]: 57
8629 11:47:17.359634 [Byte1]: 57
8630 11:47:17.363550
8631 11:47:17.363625 Set Vref, RX VrefLevel [Byte0]: 58
8632 11:47:17.367371 [Byte1]: 58
8633 11:47:17.371144
8634 11:47:17.371233 Set Vref, RX VrefLevel [Byte0]: 59
8635 11:47:17.374950 [Byte1]: 59
8636 11:47:17.378821
8637 11:47:17.378932 Set Vref, RX VrefLevel [Byte0]: 60
8638 11:47:17.381948 [Byte1]: 60
8639 11:47:17.386460
8640 11:47:17.386565 Set Vref, RX VrefLevel [Byte0]: 61
8641 11:47:17.389641 [Byte1]: 61
8642 11:47:17.394111
8643 11:47:17.394204 Set Vref, RX VrefLevel [Byte0]: 62
8644 11:47:17.397155 [Byte1]: 62
8645 11:47:17.401721
8646 11:47:17.401811 Set Vref, RX VrefLevel [Byte0]: 63
8647 11:47:17.405006 [Byte1]: 63
8648 11:47:17.408911
8649 11:47:17.408994 Set Vref, RX VrefLevel [Byte0]: 64
8650 11:47:17.412270 [Byte1]: 64
8651 11:47:17.416271
8652 11:47:17.416357 Set Vref, RX VrefLevel [Byte0]: 65
8653 11:47:17.419665 [Byte1]: 65
8654 11:47:17.424155
8655 11:47:17.424241 Set Vref, RX VrefLevel [Byte0]: 66
8656 11:47:17.427226 [Byte1]: 66
8657 11:47:17.431997
8658 11:47:17.432084 Set Vref, RX VrefLevel [Byte0]: 67
8659 11:47:17.435170 [Byte1]: 67
8660 11:47:17.438930
8661 11:47:17.439016 Set Vref, RX VrefLevel [Byte0]: 68
8662 11:47:17.442757 [Byte1]: 68
8663 11:47:17.446612
8664 11:47:17.446698 Set Vref, RX VrefLevel [Byte0]: 69
8665 11:47:17.449984 [Byte1]: 69
8666 11:47:17.454015
8667 11:47:17.454100 Set Vref, RX VrefLevel [Byte0]: 70
8668 11:47:17.457339 [Byte1]: 70
8669 11:47:17.461983
8670 11:47:17.462067 Set Vref, RX VrefLevel [Byte0]: 71
8671 11:47:17.465366 [Byte1]: 71
8672 11:47:17.469313
8673 11:47:17.469392 Set Vref, RX VrefLevel [Byte0]: 72
8674 11:47:17.472498 [Byte1]: 72
8675 11:47:17.476991
8676 11:47:17.477097 Set Vref, RX VrefLevel [Byte0]: 73
8677 11:47:17.480108 [Byte1]: 73
8678 11:47:17.484529
8679 11:47:17.484636 Set Vref, RX VrefLevel [Byte0]: 74
8680 11:47:17.487916 [Byte1]: 74
8681 11:47:17.492149
8682 11:47:17.492262 Set Vref, RX VrefLevel [Byte0]: 75
8683 11:47:17.495254 [Byte1]: 75
8684 11:47:17.499683
8685 11:47:17.499800 Set Vref, RX VrefLevel [Byte0]: 76
8686 11:47:17.502744 [Byte1]: 76
8687 11:47:17.506807
8688 11:47:17.506920 Set Vref, RX VrefLevel [Byte0]: 77
8689 11:47:17.510345 [Byte1]: 77
8690 11:47:17.514268
8691 11:47:17.514389 Set Vref, RX VrefLevel [Byte0]: 78
8692 11:47:17.517712 [Byte1]: 78
8693 11:47:17.522302
8694 11:47:17.522414 Final RX Vref Byte 0 = 56 to rank0
8695 11:47:17.525663 Final RX Vref Byte 1 = 56 to rank0
8696 11:47:17.528761 Final RX Vref Byte 0 = 56 to rank1
8697 11:47:17.532174 Final RX Vref Byte 1 = 56 to rank1==
8698 11:47:17.535403 Dram Type= 6, Freq= 0, CH_1, rank 0
8699 11:47:17.542007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8700 11:47:17.542123 ==
8701 11:47:17.542224 DQS Delay:
8702 11:47:17.545276 DQS0 = 0, DQS1 = 0
8703 11:47:17.545382 DQM Delay:
8704 11:47:17.545478 DQM0 = 134, DQM1 = 131
8705 11:47:17.548363 DQ Delay:
8706 11:47:17.552168 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8707 11:47:17.555557 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =132
8708 11:47:17.558765 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8709 11:47:17.562301 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8710 11:47:17.562412
8711 11:47:17.562510
8712 11:47:17.562603
8713 11:47:17.565467 [DramC_TX_OE_Calibration] TA2
8714 11:47:17.568877 Original DQ_B0 (3 6) =30, OEN = 27
8715 11:47:17.572133 Original DQ_B1 (3 6) =30, OEN = 27
8716 11:47:17.574876 24, 0x0, End_B0=24 End_B1=24
8717 11:47:17.574985 25, 0x0, End_B0=25 End_B1=25
8718 11:47:17.578774 26, 0x0, End_B0=26 End_B1=26
8719 11:47:17.581857 27, 0x0, End_B0=27 End_B1=27
8720 11:47:17.585066 28, 0x0, End_B0=28 End_B1=28
8721 11:47:17.585175 29, 0x0, End_B0=29 End_B1=29
8722 11:47:17.588301 30, 0x0, End_B0=30 End_B1=30
8723 11:47:17.591998 31, 0x4141, End_B0=30 End_B1=30
8724 11:47:17.595114 Byte0 end_step=30 best_step=27
8725 11:47:17.598339 Byte1 end_step=30 best_step=27
8726 11:47:17.601991 Byte0 TX OE(2T, 0.5T) = (3, 3)
8727 11:47:17.602109 Byte1 TX OE(2T, 0.5T) = (3, 3)
8728 11:47:17.605154
8729 11:47:17.605265
8730 11:47:17.612002 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8731 11:47:17.615046 CH1 RK0: MR19=303, MR18=1623
8732 11:47:17.621677 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8733 11:47:17.621784
8734 11:47:17.625003 ----->DramcWriteLeveling(PI) begin...
8735 11:47:17.625085 ==
8736 11:47:17.628303 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 11:47:17.631703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 11:47:17.631827 ==
8739 11:47:17.635046 Write leveling (Byte 0): 27 => 27
8740 11:47:17.638267 Write leveling (Byte 1): 27 => 27
8741 11:47:17.641415 DramcWriteLeveling(PI) end<-----
8742 11:47:17.641527
8743 11:47:17.641638 ==
8744 11:47:17.644752 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 11:47:17.648060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 11:47:17.648160 ==
8747 11:47:17.651336 [Gating] SW mode calibration
8748 11:47:17.658290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8749 11:47:17.664911 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8750 11:47:17.668393 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 11:47:17.671745 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 11:47:17.678257 1 4 8 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0)
8753 11:47:17.681668 1 4 12 | B1->B0 | 3434 2f2e | 1 1 | (1 1) (0 0)
8754 11:47:17.684862 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 11:47:17.691106 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 11:47:17.694939 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 11:47:17.698063 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 11:47:17.704470 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8759 11:47:17.708235 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8760 11:47:17.711299 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
8761 11:47:17.717655 1 5 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 1)
8762 11:47:17.720913 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8763 11:47:17.724766 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 11:47:17.731343 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 11:47:17.734676 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 11:47:17.737972 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 11:47:17.744477 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 11:47:17.747693 1 6 8 | B1->B0 | 3b3b 2424 | 0 0 | (0 0) (0 0)
8769 11:47:17.750981 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 11:47:17.757609 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 11:47:17.760876 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 11:47:17.764645 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 11:47:17.770959 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 11:47:17.774315 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 11:47:17.777635 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 11:47:17.784381 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8777 11:47:17.787600 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8778 11:47:17.790719 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 11:47:17.797697 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 11:47:17.801000 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 11:47:17.804264 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:47:17.811116 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:47:17.814207 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:47:17.817405 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:47:17.820467 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:47:17.827504 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:47:17.830673 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:47:17.833961 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:47:17.840423 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:47:17.843693 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:47:17.847579 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8792 11:47:17.853992 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8793 11:47:17.857386 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8794 11:47:17.860664 Total UI for P1: 0, mck2ui 16
8795 11:47:17.863935 best dqsien dly found for B1: ( 1, 9, 6)
8796 11:47:17.867243 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8797 11:47:17.874194 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 11:47:17.874281 Total UI for P1: 0, mck2ui 16
8799 11:47:17.880671 best dqsien dly found for B0: ( 1, 9, 14)
8800 11:47:17.884115 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8801 11:47:17.886773 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8802 11:47:17.886879
8803 11:47:17.890091 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8804 11:47:17.894001 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8805 11:47:17.897268 [Gating] SW calibration Done
8806 11:47:17.897352 ==
8807 11:47:17.900388 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 11:47:17.903467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 11:47:17.903548 ==
8810 11:47:17.907216 RX Vref Scan: 0
8811 11:47:17.907294
8812 11:47:17.907360 RX Vref 0 -> 0, step: 1
8813 11:47:17.907422
8814 11:47:17.910338 RX Delay 0 -> 252, step: 8
8815 11:47:17.913562 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8816 11:47:17.920297 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8817 11:47:17.923415 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8818 11:47:17.926597 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8819 11:47:17.930235 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8820 11:47:17.933330 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8821 11:47:17.940045 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8822 11:47:17.943341 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8823 11:47:17.946735 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8824 11:47:17.949981 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8825 11:47:17.956658 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8826 11:47:17.959741 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8827 11:47:17.963205 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8828 11:47:17.966324 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8829 11:47:17.969598 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8830 11:47:17.976327 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8831 11:47:17.976452 ==
8832 11:47:17.979575 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 11:47:17.982702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 11:47:17.982817 ==
8835 11:47:17.982927 DQS Delay:
8836 11:47:17.985964 DQS0 = 0, DQS1 = 0
8837 11:47:17.986075 DQM Delay:
8838 11:47:17.989883 DQM0 = 136, DQM1 = 133
8839 11:47:17.990007 DQ Delay:
8840 11:47:17.992636 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8841 11:47:17.996006 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8842 11:47:17.999476 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8843 11:47:18.002651 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8844 11:47:18.002741
8845 11:47:18.002817
8846 11:47:18.006491 ==
8847 11:47:18.009646 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 11:47:18.012870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 11:47:18.012950 ==
8850 11:47:18.013030
8851 11:47:18.013094
8852 11:47:18.016028 TX Vref Scan disable
8853 11:47:18.016114 == TX Byte 0 ==
8854 11:47:18.019824 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8855 11:47:18.026101 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8856 11:47:18.026212 == TX Byte 1 ==
8857 11:47:18.029992 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8858 11:47:18.036140 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8859 11:47:18.036256 ==
8860 11:47:18.040011 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 11:47:18.043124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 11:47:18.043235 ==
8863 11:47:18.057032
8864 11:47:18.059756 TX Vref early break, caculate TX vref
8865 11:47:18.063616 TX Vref=16, minBit 0, minWin=23, winSum=383
8866 11:47:18.066938 TX Vref=18, minBit 0, minWin=23, winSum=393
8867 11:47:18.070269 TX Vref=20, minBit 0, minWin=24, winSum=404
8868 11:47:18.073416 TX Vref=22, minBit 0, minWin=25, winSum=412
8869 11:47:18.076673 TX Vref=24, minBit 0, minWin=25, winSum=417
8870 11:47:18.083274 TX Vref=26, minBit 0, minWin=25, winSum=423
8871 11:47:18.086479 TX Vref=28, minBit 0, minWin=26, winSum=427
8872 11:47:18.090295 TX Vref=30, minBit 1, minWin=25, winSum=422
8873 11:47:18.093451 TX Vref=32, minBit 0, minWin=25, winSum=414
8874 11:47:18.097007 TX Vref=34, minBit 0, minWin=24, winSum=407
8875 11:47:18.099763 TX Vref=36, minBit 1, minWin=23, winSum=398
8876 11:47:18.107101 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8877 11:47:18.107192
8878 11:47:18.110269 Final TX Range 0 Vref 28
8879 11:47:18.110387
8880 11:47:18.110490 ==
8881 11:47:18.113579 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 11:47:18.116684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 11:47:18.116809 ==
8884 11:47:18.116881
8885 11:47:18.116946
8886 11:47:18.119573 TX Vref Scan disable
8887 11:47:18.126673 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8888 11:47:18.126784 == TX Byte 0 ==
8889 11:47:18.129809 u2DelayCellOfst[0]=13 cells (4 PI)
8890 11:47:18.132855 u2DelayCellOfst[1]=10 cells (3 PI)
8891 11:47:18.136441 u2DelayCellOfst[2]=0 cells (0 PI)
8892 11:47:18.139530 u2DelayCellOfst[3]=3 cells (1 PI)
8893 11:47:18.143293 u2DelayCellOfst[4]=6 cells (2 PI)
8894 11:47:18.146534 u2DelayCellOfst[5]=16 cells (5 PI)
8895 11:47:18.149682 u2DelayCellOfst[6]=13 cells (4 PI)
8896 11:47:18.152974 u2DelayCellOfst[7]=3 cells (1 PI)
8897 11:47:18.156342 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8898 11:47:18.159603 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8899 11:47:18.162993 == TX Byte 1 ==
8900 11:47:18.166357 u2DelayCellOfst[8]=0 cells (0 PI)
8901 11:47:18.166475 u2DelayCellOfst[9]=0 cells (0 PI)
8902 11:47:18.169648 u2DelayCellOfst[10]=10 cells (3 PI)
8903 11:47:18.173429 u2DelayCellOfst[11]=3 cells (1 PI)
8904 11:47:18.176708 u2DelayCellOfst[12]=13 cells (4 PI)
8905 11:47:18.179964 u2DelayCellOfst[13]=16 cells (5 PI)
8906 11:47:18.183164 u2DelayCellOfst[14]=16 cells (5 PI)
8907 11:47:18.186438 u2DelayCellOfst[15]=16 cells (5 PI)
8908 11:47:18.189938 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8909 11:47:18.196314 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8910 11:47:18.196427 DramC Write-DBI on
8911 11:47:18.196537 ==
8912 11:47:18.199524 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 11:47:18.206069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 11:47:18.206192 ==
8915 11:47:18.206301
8916 11:47:18.206415
8917 11:47:18.206519 TX Vref Scan disable
8918 11:47:18.210036 == TX Byte 0 ==
8919 11:47:18.213329 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8920 11:47:18.216720 == TX Byte 1 ==
8921 11:47:18.220025 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8922 11:47:18.220147 DramC Write-DBI off
8923 11:47:18.223251
8924 11:47:18.223359 [DATLAT]
8925 11:47:18.223462 Freq=1600, CH1 RK1
8926 11:47:18.223579
8927 11:47:18.226400 DATLAT Default: 0xf
8928 11:47:18.226511 0, 0xFFFF, sum = 0
8929 11:47:18.230029 1, 0xFFFF, sum = 0
8930 11:47:18.230140 2, 0xFFFF, sum = 0
8931 11:47:18.233248 3, 0xFFFF, sum = 0
8932 11:47:18.236385 4, 0xFFFF, sum = 0
8933 11:47:18.236494 5, 0xFFFF, sum = 0
8934 11:47:18.240014 6, 0xFFFF, sum = 0
8935 11:47:18.240133 7, 0xFFFF, sum = 0
8936 11:47:18.243217 8, 0xFFFF, sum = 0
8937 11:47:18.243344 9, 0xFFFF, sum = 0
8938 11:47:18.246387 10, 0xFFFF, sum = 0
8939 11:47:18.246511 11, 0xFFFF, sum = 0
8940 11:47:18.249648 12, 0xFFFF, sum = 0
8941 11:47:18.249758 13, 0xFFFF, sum = 0
8942 11:47:18.252859 14, 0x0, sum = 1
8943 11:47:18.252953 15, 0x0, sum = 2
8944 11:47:18.256657 16, 0x0, sum = 3
8945 11:47:18.256774 17, 0x0, sum = 4
8946 11:47:18.259938 best_step = 15
8947 11:47:18.260053
8948 11:47:18.260152 ==
8949 11:47:18.263178 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 11:47:18.266548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 11:47:18.266656 ==
8952 11:47:18.269803 RX Vref Scan: 0
8953 11:47:18.269910
8954 11:47:18.270004 RX Vref 0 -> 0, step: 1
8955 11:47:18.270110
8956 11:47:18.273300 RX Delay 19 -> 252, step: 4
8957 11:47:18.276415 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8958 11:47:18.282810 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8959 11:47:18.286159 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8960 11:47:18.289584 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8961 11:47:18.292999 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8962 11:47:18.296262 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8963 11:47:18.299363 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8964 11:47:18.306544 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8965 11:47:18.309731 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8966 11:47:18.312999 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8967 11:47:18.316269 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8968 11:47:18.319639 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8969 11:47:18.326334 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8970 11:47:18.329590 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8971 11:47:18.332721 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8972 11:47:18.336388 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8973 11:47:18.336510 ==
8974 11:47:18.339292 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 11:47:18.346269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 11:47:18.346433 ==
8977 11:47:18.346544 DQS Delay:
8978 11:47:18.349302 DQS0 = 0, DQS1 = 0
8979 11:47:18.349407 DQM Delay:
8980 11:47:18.349556 DQM0 = 134, DQM1 = 130
8981 11:47:18.353225 DQ Delay:
8982 11:47:18.356281 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8983 11:47:18.359506 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8984 11:47:18.362580 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8985 11:47:18.366006 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8986 11:47:18.366111
8987 11:47:18.366236
8988 11:47:18.366330
8989 11:47:18.369228 [DramC_TX_OE_Calibration] TA2
8990 11:47:18.372584 Original DQ_B0 (3 6) =30, OEN = 27
8991 11:47:18.376006 Original DQ_B1 (3 6) =30, OEN = 27
8992 11:47:18.379245 24, 0x0, End_B0=24 End_B1=24
8993 11:47:18.379350 25, 0x0, End_B0=25 End_B1=25
8994 11:47:18.382654 26, 0x0, End_B0=26 End_B1=26
8995 11:47:18.386392 27, 0x0, End_B0=27 End_B1=27
8996 11:47:18.389599 28, 0x0, End_B0=28 End_B1=28
8997 11:47:18.392712 29, 0x0, End_B0=29 End_B1=29
8998 11:47:18.392866 30, 0x0, End_B0=30 End_B1=30
8999 11:47:18.396024 31, 0x4141, End_B0=30 End_B1=30
9000 11:47:18.399510 Byte0 end_step=30 best_step=27
9001 11:47:18.402721 Byte1 end_step=30 best_step=27
9002 11:47:18.406064 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 11:47:18.409230 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 11:47:18.409348
9005 11:47:18.409447
9006 11:47:18.415675 [DQSOSCAuto] RK1, (LSB)MR18= 0x2006, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9007 11:47:18.419658 CH1 RK1: MR19=303, MR18=2006
9008 11:47:18.426298 CH1_RK1: MR19=0x303, MR18=0x2006, DQSOSC=393, MR23=63, INC=23, DEC=15
9009 11:47:18.429708 [RxdqsGatingPostProcess] freq 1600
9010 11:47:18.432997 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 11:47:18.436392 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 11:47:18.439552 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 11:47:18.442580 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 11:47:18.445706 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 11:47:18.449501 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 11:47:18.452616 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 11:47:18.455733 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 11:47:18.459450 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 11:47:18.462797 Pre-setting of DQS Precalculation
9020 11:47:18.465915 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 11:47:18.472974 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 11:47:18.479386 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 11:47:18.479466
9024 11:47:18.482684
9025 11:47:18.482759 [Calibration Summary] 3200 Mbps
9026 11:47:18.486161 CH 0, Rank 0
9027 11:47:18.486236 SW Impedance : PASS
9028 11:47:18.489223 DUTY Scan : NO K
9029 11:47:18.492307 ZQ Calibration : PASS
9030 11:47:18.492411 Jitter Meter : NO K
9031 11:47:18.496023 CBT Training : PASS
9032 11:47:18.499377 Write leveling : PASS
9033 11:47:18.499489 RX DQS gating : PASS
9034 11:47:18.502611 RX DQ/DQS(RDDQC) : PASS
9035 11:47:18.505986 TX DQ/DQS : PASS
9036 11:47:18.506072 RX DATLAT : PASS
9037 11:47:18.509251 RX DQ/DQS(Engine): PASS
9038 11:47:18.512532 TX OE : PASS
9039 11:47:18.512641 All Pass.
9040 11:47:18.512736
9041 11:47:18.512831 CH 0, Rank 1
9042 11:47:18.515711 SW Impedance : PASS
9043 11:47:18.518898 DUTY Scan : NO K
9044 11:47:18.518982 ZQ Calibration : PASS
9045 11:47:18.522119 Jitter Meter : NO K
9046 11:47:18.525328 CBT Training : PASS
9047 11:47:18.525412 Write leveling : PASS
9048 11:47:18.528790 RX DQS gating : PASS
9049 11:47:18.528882 RX DQ/DQS(RDDQC) : PASS
9050 11:47:18.532239 TX DQ/DQS : PASS
9051 11:47:18.535392 RX DATLAT : PASS
9052 11:47:18.535475 RX DQ/DQS(Engine): PASS
9053 11:47:18.539304 TX OE : PASS
9054 11:47:18.539388 All Pass.
9055 11:47:18.539454
9056 11:47:18.542730 CH 1, Rank 0
9057 11:47:18.542815 SW Impedance : PASS
9058 11:47:18.545863 DUTY Scan : NO K
9059 11:47:18.549079 ZQ Calibration : PASS
9060 11:47:18.549164 Jitter Meter : NO K
9061 11:47:18.552261 CBT Training : PASS
9062 11:47:18.555255 Write leveling : PASS
9063 11:47:18.555359 RX DQS gating : PASS
9064 11:47:18.559064 RX DQ/DQS(RDDQC) : PASS
9065 11:47:18.562254 TX DQ/DQS : PASS
9066 11:47:18.562338 RX DATLAT : PASS
9067 11:47:18.565362 RX DQ/DQS(Engine): PASS
9068 11:47:18.569161 TX OE : PASS
9069 11:47:18.569284 All Pass.
9070 11:47:18.569380
9071 11:47:18.569476 CH 1, Rank 1
9072 11:47:18.572359 SW Impedance : PASS
9073 11:47:18.575223 DUTY Scan : NO K
9074 11:47:18.575338 ZQ Calibration : PASS
9075 11:47:18.578511 Jitter Meter : NO K
9076 11:47:18.578618 CBT Training : PASS
9077 11:47:18.582160 Write leveling : PASS
9078 11:47:18.585641 RX DQS gating : PASS
9079 11:47:18.585748 RX DQ/DQS(RDDQC) : PASS
9080 11:47:18.589006 TX DQ/DQS : PASS
9081 11:47:18.592234 RX DATLAT : PASS
9082 11:47:18.592341 RX DQ/DQS(Engine): PASS
9083 11:47:18.595522 TX OE : PASS
9084 11:47:18.595633 All Pass.
9085 11:47:18.595744
9086 11:47:18.598633 DramC Write-DBI on
9087 11:47:18.601896 PER_BANK_REFRESH: Hybrid Mode
9088 11:47:18.602009 TX_TRACKING: ON
9089 11:47:18.612375 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 11:47:18.619051 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 11:47:18.625373 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 11:47:18.628483 [FAST_K] Save calibration result to emmc
9093 11:47:18.632021 sync common calibartion params.
9094 11:47:18.635275 sync cbt_mode0:1, 1:1
9095 11:47:18.638597 dram_init: ddr_geometry: 2
9096 11:47:18.638682 dram_init: ddr_geometry: 2
9097 11:47:18.641993 dram_init: ddr_geometry: 2
9098 11:47:18.645374 0:dram_rank_size:100000000
9099 11:47:18.648550 1:dram_rank_size:100000000
9100 11:47:18.651929 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 11:47:18.654554 DFS_SHUFFLE_HW_MODE: ON
9102 11:47:18.658420 dramc_set_vcore_voltage set vcore to 725000
9103 11:47:18.661546 Read voltage for 1600, 0
9104 11:47:18.661675 Vio18 = 0
9105 11:47:18.664717 Vcore = 725000
9106 11:47:18.664846 Vdram = 0
9107 11:47:18.664956 Vddq = 0
9108 11:47:18.665067 Vmddr = 0
9109 11:47:18.668352 switch to 3200 Mbps bootup
9110 11:47:18.671370 [DramcRunTimeConfig]
9111 11:47:18.671478 PHYPLL
9112 11:47:18.671595 DPM_CONTROL_AFTERK: ON
9113 11:47:18.675192 PER_BANK_REFRESH: ON
9114 11:47:18.678398 REFRESH_OVERHEAD_REDUCTION: ON
9115 11:47:18.678482 CMD_PICG_NEW_MODE: OFF
9116 11:47:18.681452 XRTWTW_NEW_MODE: ON
9117 11:47:18.685188 XRTRTR_NEW_MODE: ON
9118 11:47:18.685273 TX_TRACKING: ON
9119 11:47:18.688464 RDSEL_TRACKING: OFF
9120 11:47:18.688574 DQS Precalculation for DVFS: ON
9121 11:47:18.691650 RX_TRACKING: OFF
9122 11:47:18.691768 HW_GATING DBG: ON
9123 11:47:18.695059 ZQCS_ENABLE_LP4: ON
9124 11:47:18.695169 RX_PICG_NEW_MODE: ON
9125 11:47:18.698428 TX_PICG_NEW_MODE: ON
9126 11:47:18.701616 ENABLE_RX_DCM_DPHY: ON
9127 11:47:18.704625 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 11:47:18.704741 DUMMY_READ_FOR_TRACKING: OFF
9129 11:47:18.707737 !!! SPM_CONTROL_AFTERK: OFF
9130 11:47:18.711641 !!! SPM could not control APHY
9131 11:47:18.714977 IMPEDANCE_TRACKING: ON
9132 11:47:18.715098 TEMP_SENSOR: ON
9133 11:47:18.718291 HW_SAVE_FOR_SR: OFF
9134 11:47:18.718411 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 11:47:18.724928 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 11:47:18.725023 Read ODT Tracking: ON
9137 11:47:18.728100 Refresh Rate DeBounce: ON
9138 11:47:18.731181 DFS_NO_QUEUE_FLUSH: ON
9139 11:47:18.734454 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 11:47:18.734538 ENABLE_DFS_RUNTIME_MRW: OFF
9141 11:47:18.737735 DDR_RESERVE_NEW_MODE: ON
9142 11:47:18.741160 MR_CBT_SWITCH_FREQ: ON
9143 11:47:18.741249 =========================
9144 11:47:18.761282 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 11:47:18.764512 dram_init: ddr_geometry: 2
9146 11:47:18.782612 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 11:47:18.785751 dram_init: dram init end (result: 0)
9148 11:47:18.792106 DRAM-K: Full calibration passed in 24484 msecs
9149 11:47:18.795962 MRC: failed to locate region type 0.
9150 11:47:18.796078 DRAM rank0 size:0x100000000,
9151 11:47:18.799214 DRAM rank1 size=0x100000000
9152 11:47:18.809011 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 11:47:18.815527 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 11:47:18.822292 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 11:47:18.828914 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 11:47:18.832154 DRAM rank0 size:0x100000000,
9157 11:47:18.835330 DRAM rank1 size=0x100000000
9158 11:47:18.835415 CBMEM:
9159 11:47:18.839048 IMD: root @ 0xfffff000 254 entries.
9160 11:47:18.842513 IMD: root @ 0xffffec00 62 entries.
9161 11:47:18.845624 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 11:47:18.848942 WARNING: RO_VPD is uninitialized or empty.
9163 11:47:18.855510 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 11:47:18.862738 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 11:47:18.875330 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9166 11:47:18.886727 BS: romstage times (exec / console): total (unknown) / 24013 ms
9167 11:47:18.886828
9168 11:47:18.886914
9169 11:47:18.896866 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 11:47:18.900060 ARM64: Exception handlers installed.
9171 11:47:18.903261 ARM64: Testing exception
9172 11:47:18.906325 ARM64: Done test exception
9173 11:47:18.906437 Enumerating buses...
9174 11:47:18.910238 Show all devs... Before device enumeration.
9175 11:47:18.913452 Root Device: enabled 1
9176 11:47:18.916709 CPU_CLUSTER: 0: enabled 1
9177 11:47:18.916817 CPU: 00: enabled 1
9178 11:47:18.920015 Compare with tree...
9179 11:47:18.920090 Root Device: enabled 1
9180 11:47:18.923389 CPU_CLUSTER: 0: enabled 1
9181 11:47:18.926519 CPU: 00: enabled 1
9182 11:47:18.926629 Root Device scanning...
9183 11:47:18.929633 scan_static_bus for Root Device
9184 11:47:18.933406 CPU_CLUSTER: 0 enabled
9185 11:47:18.936950 scan_static_bus for Root Device done
9186 11:47:18.940285 scan_bus: bus Root Device finished in 8 msecs
9187 11:47:18.940387 done
9188 11:47:18.946613 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 11:47:18.949884 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 11:47:18.956531 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 11:47:18.959758 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 11:47:18.963195 Allocating resources...
9193 11:47:18.966358 Reading resources...
9194 11:47:18.969583 Root Device read_resources bus 0 link: 0
9195 11:47:18.969688 DRAM rank0 size:0x100000000,
9196 11:47:18.972961 DRAM rank1 size=0x100000000
9197 11:47:18.976301 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 11:47:18.979445 CPU: 00 missing read_resources
9199 11:47:18.982788 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 11:47:18.989719 Root Device read_resources bus 0 link: 0 done
9201 11:47:18.989826 Done reading resources.
9202 11:47:18.995993 Show resources in subtree (Root Device)...After reading.
9203 11:47:18.999748 Root Device child on link 0 CPU_CLUSTER: 0
9204 11:47:19.003018 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 11:47:19.013316 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 11:47:19.013416 CPU: 00
9207 11:47:19.016385 Root Device assign_resources, bus 0 link: 0
9208 11:47:19.019742 CPU_CLUSTER: 0 missing set_resources
9209 11:47:19.023030 Root Device assign_resources, bus 0 link: 0 done
9210 11:47:19.026220 Done setting resources.
9211 11:47:19.032723 Show resources in subtree (Root Device)...After assigning values.
9212 11:47:19.035996 Root Device child on link 0 CPU_CLUSTER: 0
9213 11:47:19.039517 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 11:47:19.049584 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 11:47:19.049684 CPU: 00
9216 11:47:19.052682 Done allocating resources.
9217 11:47:19.056125 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 11:47:19.059329 Enabling resources...
9219 11:47:19.059412 done.
9220 11:47:19.066483 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 11:47:19.066632 Initializing devices...
9222 11:47:19.069741 Root Device init
9223 11:47:19.069857 init hardware done!
9224 11:47:19.073110 0x00000018: ctrlr->caps
9225 11:47:19.073256 52.000 MHz: ctrlr->f_max
9226 11:47:19.076260 0.400 MHz: ctrlr->f_min
9227 11:47:19.079519 0x40ff8080: ctrlr->voltages
9228 11:47:19.079657 sclk: 390625
9229 11:47:19.082687 Bus Width = 1
9230 11:47:19.082805 sclk: 390625
9231 11:47:19.082910 Bus Width = 1
9232 11:47:19.086161 Early init status = 3
9233 11:47:19.089975 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 11:47:19.094984 in-header: 03 fc 00 00 01 00 00 00
9235 11:47:19.098753 in-data: 00
9236 11:47:19.101845 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9237 11:47:19.107498 in-header: 03 fd 00 00 00 00 00 00
9238 11:47:19.110626 in-data:
9239 11:47:19.113829 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9240 11:47:19.118351 in-header: 03 fc 00 00 01 00 00 00
9241 11:47:19.121625 in-data: 00
9242 11:47:19.124887 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9243 11:47:19.130617 in-header: 03 fd 00 00 00 00 00 00
9244 11:47:19.133938 in-data:
9245 11:47:19.137269 [SSUSB] Setting up USB HOST controller...
9246 11:47:19.140574 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9247 11:47:19.143681 [SSUSB] phy power-on done.
9248 11:47:19.147615 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9249 11:47:19.153556 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9250 11:47:19.157297 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9251 11:47:19.163776 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9252 11:47:19.170936 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9253 11:47:19.177052 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9254 11:47:19.183703 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9255 11:47:19.190323 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9256 11:47:19.190440 SPM: binary array size = 0x9dc
9257 11:47:19.196946 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9258 11:47:19.203906 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9259 11:47:19.210632 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9260 11:47:19.213785 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9261 11:47:19.216897 configure_display: Starting display init
9262 11:47:19.253998 anx7625_power_on_init: Init interface.
9263 11:47:19.257297 anx7625_disable_pd_protocol: Disabled PD feature.
9264 11:47:19.260563 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9265 11:47:19.288267 anx7625_start_dp_work: Secure OCM version=00
9266 11:47:19.291522 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9267 11:47:19.306352 sp_tx_get_edid_block: EDID Block = 1
9268 11:47:19.408903 Extracted contents:
9269 11:47:19.411977 header: 00 ff ff ff ff ff ff 00
9270 11:47:19.415285 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9271 11:47:19.418884 version: 01 04
9272 11:47:19.422050 basic params: 95 1f 11 78 0a
9273 11:47:19.425273 chroma info: 76 90 94 55 54 90 27 21 50 54
9274 11:47:19.428570 established: 00 00 00
9275 11:47:19.435463 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9276 11:47:19.438622 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9277 11:47:19.445144 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9278 11:47:19.451976 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9279 11:47:19.458423 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9280 11:47:19.461664 extensions: 00
9281 11:47:19.461772 checksum: fb
9282 11:47:19.461867
9283 11:47:19.464752 Manufacturer: IVO Model 57d Serial Number 0
9284 11:47:19.468180 Made week 0 of 2020
9285 11:47:19.468282 EDID version: 1.4
9286 11:47:19.471589 Digital display
9287 11:47:19.475175 6 bits per primary color channel
9288 11:47:19.475279 DisplayPort interface
9289 11:47:19.478294 Maximum image size: 31 cm x 17 cm
9290 11:47:19.481451 Gamma: 220%
9291 11:47:19.481554 Check DPMS levels
9292 11:47:19.484868 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9293 11:47:19.491586 First detailed timing is preferred timing
9294 11:47:19.491730 Established timings supported:
9295 11:47:19.495034 Standard timings supported:
9296 11:47:19.498233 Detailed timings
9297 11:47:19.501660 Hex of detail: 383680a07038204018303c0035ae10000019
9298 11:47:19.505029 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9299 11:47:19.511631 0780 0798 07c8 0820 hborder 0
9300 11:47:19.514954 0438 043b 0447 0458 vborder 0
9301 11:47:19.518253 -hsync -vsync
9302 11:47:19.518336 Did detailed timing
9303 11:47:19.525221 Hex of detail: 000000000000000000000000000000000000
9304 11:47:19.525304 Manufacturer-specified data, tag 0
9305 11:47:19.531547 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9306 11:47:19.534659 ASCII string: InfoVision
9307 11:47:19.537945 Hex of detail: 000000fe00523134304e574635205248200a
9308 11:47:19.541709 ASCII string: R140NWF5 RH
9309 11:47:19.541790 Checksum
9310 11:47:19.544980 Checksum: 0xfb (valid)
9311 11:47:19.548231 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9312 11:47:19.551387 DSI data_rate: 832800000 bps
9313 11:47:19.555072 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9314 11:47:19.561620 anx7625_parse_edid: pixelclock(138800).
9315 11:47:19.564933 hactive(1920), hsync(48), hfp(24), hbp(88)
9316 11:47:19.568168 vactive(1080), vsync(12), vfp(3), vbp(17)
9317 11:47:19.571446 anx7625_dsi_config: config dsi.
9318 11:47:19.578166 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9319 11:47:19.590894 anx7625_dsi_config: success to config DSI
9320 11:47:19.594278 anx7625_dp_start: MIPI phy setup OK.
9321 11:47:19.597541 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9322 11:47:19.600758 mtk_ddp_mode_set invalid vrefresh 60
9323 11:47:19.604058 main_disp_path_setup
9324 11:47:19.604184 ovl_layer_smi_id_en
9325 11:47:19.607336 ovl_layer_smi_id_en
9326 11:47:19.607459 ccorr_config
9327 11:47:19.607556 aal_config
9328 11:47:19.610659 gamma_config
9329 11:47:19.610772 postmask_config
9330 11:47:19.614169 dither_config
9331 11:47:19.617353 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9332 11:47:19.623986 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9333 11:47:19.627198 Root Device init finished in 555 msecs
9334 11:47:19.627280 CPU_CLUSTER: 0 init
9335 11:47:19.637528 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9336 11:47:19.640753 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9337 11:47:19.643959 APU_MBOX 0x190000b0 = 0x10001
9338 11:47:19.647599 APU_MBOX 0x190001b0 = 0x10001
9339 11:47:19.650877 APU_MBOX 0x190005b0 = 0x10001
9340 11:47:19.654161 APU_MBOX 0x190006b0 = 0x10001
9341 11:47:19.657172 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9342 11:47:19.669629 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9343 11:47:19.682013 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9344 11:47:19.689006 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9345 11:47:19.700308 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9346 11:47:19.709584 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9347 11:47:19.712942 CPU_CLUSTER: 0 init finished in 81 msecs
9348 11:47:19.716298 Devices initialized
9349 11:47:19.719612 Show all devs... After init.
9350 11:47:19.719723 Root Device: enabled 1
9351 11:47:19.723074 CPU_CLUSTER: 0: enabled 1
9352 11:47:19.726347 CPU: 00: enabled 1
9353 11:47:19.729564 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9354 11:47:19.732717 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9355 11:47:19.736076 ELOG: NV offset 0x57f000 size 0x1000
9356 11:47:19.742449 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9357 11:47:19.749542 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9358 11:47:19.752638 ELOG: Event(17) added with size 13 at 2023-06-15 11:47:04 UTC
9359 11:47:19.759560 out: cmd=0x121: 03 db 21 01 00 00 00 00
9360 11:47:19.762859 in-header: 03 bb 00 00 2c 00 00 00
9361 11:47:19.772338 in-data: a4 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 11:47:19.779485 ELOG: Event(A1) added with size 10 at 2023-06-15 11:47:04 UTC
9363 11:47:19.785982 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9364 11:47:19.792602 ELOG: Event(A0) added with size 9 at 2023-06-15 11:47:04 UTC
9365 11:47:19.795897 elog_add_boot_reason: Logged dev mode boot
9366 11:47:19.799083 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9367 11:47:19.802864 Finalize devices...
9368 11:47:19.802951 Devices finalized
9369 11:47:19.809339 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9370 11:47:19.812628 Writing coreboot table at 0xffe64000
9371 11:47:19.815948 0. 000000000010a000-0000000000113fff: RAMSTAGE
9372 11:47:19.819361 1. 0000000040000000-00000000400fffff: RAM
9373 11:47:19.826019 2. 0000000040100000-000000004032afff: RAMSTAGE
9374 11:47:19.829413 3. 000000004032b000-00000000545fffff: RAM
9375 11:47:19.832599 4. 0000000054600000-000000005465ffff: BL31
9376 11:47:19.835766 5. 0000000054660000-00000000ffe63fff: RAM
9377 11:47:19.842340 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9378 11:47:19.845762 7. 0000000100000000-000000023fffffff: RAM
9379 11:47:19.849024 Passing 5 GPIOs to payload:
9380 11:47:19.852610 NAME | PORT | POLARITY | VALUE
9381 11:47:19.855757 EC in RW | 0x000000aa | low | undefined
9382 11:47:19.862260 EC interrupt | 0x00000005 | low | undefined
9383 11:47:19.866165 TPM interrupt | 0x000000ab | high | undefined
9384 11:47:19.872427 SD card detect | 0x00000011 | high | undefined
9385 11:47:19.875700 speaker enable | 0x00000093 | high | undefined
9386 11:47:19.879024 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9387 11:47:19.882365 in-header: 03 f9 00 00 02 00 00 00
9388 11:47:19.885564 in-data: 02 00
9389 11:47:19.885654 ADC[4]: Raw value=905096 ID=7
9390 11:47:19.888683 ADC[3]: Raw value=213441 ID=1
9391 11:47:19.891997 RAM Code: 0x71
9392 11:47:19.892082 ADC[6]: Raw value=75701 ID=0
9393 11:47:19.895365 ADC[5]: Raw value=212703 ID=1
9394 11:47:19.898809 SKU Code: 0x1
9395 11:47:19.901989 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9396 11:47:19.905267 coreboot table: 964 bytes.
9397 11:47:19.909135 IMD ROOT 0. 0xfffff000 0x00001000
9398 11:47:19.912136 IMD SMALL 1. 0xffffe000 0x00001000
9399 11:47:19.915699 RO MCACHE 2. 0xffffc000 0x00001104
9400 11:47:19.919119 CONSOLE 3. 0xfff7c000 0x00080000
9401 11:47:19.922451 FMAP 4. 0xfff7b000 0x00000452
9402 11:47:19.925636 TIME STAMP 5. 0xfff7a000 0x00000910
9403 11:47:19.929034 VBOOT WORK 6. 0xfff66000 0x00014000
9404 11:47:19.932237 RAMOOPS 7. 0xffe66000 0x00100000
9405 11:47:19.935592 COREBOOT 8. 0xffe64000 0x00002000
9406 11:47:19.935681 IMD small region:
9407 11:47:19.939014 IMD ROOT 0. 0xffffec00 0x00000400
9408 11:47:19.942236 VPD 1. 0xffffeba0 0x0000004c
9409 11:47:19.949002 MMC STATUS 2. 0xffffeb80 0x00000004
9410 11:47:19.952218 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9411 11:47:19.955541 Probing TPM: done!
9412 11:47:19.958716 Connected to device vid:did:rid of 1ae0:0028:00
9413 11:47:19.969226 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9414 11:47:19.972382 Initialized TPM device CR50 revision 0
9415 11:47:19.975604 Checking cr50 for pending updates
9416 11:47:19.979474 Reading cr50 TPM mode
9417 11:47:19.988627 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9418 11:47:19.994895 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 11:47:20.035088 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9420 11:47:20.038567 Checking segment from ROM address 0x40100000
9421 11:47:20.041639 Checking segment from ROM address 0x4010001c
9422 11:47:20.048199 Loading segment from ROM address 0x40100000
9423 11:47:20.048285 code (compression=0)
9424 11:47:20.055392 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 11:47:20.065202 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 11:47:20.065290 it's not compressed!
9427 11:47:20.071923 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 11:47:20.075038 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 11:47:20.095227 Loading segment from ROM address 0x4010001c
9430 11:47:20.095332 Entry Point 0x80000000
9431 11:47:20.098590 Loaded segments
9432 11:47:20.101837 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9433 11:47:20.108995 Jumping to boot code at 0x80000000(0xffe64000)
9434 11:47:20.115381 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 11:47:20.122104 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 11:47:20.129625 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9437 11:47:20.133425 Checking segment from ROM address 0x40100000
9438 11:47:20.136188 Checking segment from ROM address 0x4010001c
9439 11:47:20.142900 Loading segment from ROM address 0x40100000
9440 11:47:20.143006 code (compression=1)
9441 11:47:20.149754 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 11:47:20.159778 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 11:47:20.159881 using LZMA
9444 11:47:20.168349 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 11:47:20.174888 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 11:47:20.178577 Loading segment from ROM address 0x4010001c
9447 11:47:20.178688 Entry Point 0x54601000
9448 11:47:20.181605 Loaded segments
9449 11:47:20.184719 NOTICE: MT8192 bl31_setup
9450 11:47:20.191738 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 11:47:20.194918 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 11:47:20.198210 WARNING: region 0:
9453 11:47:20.201544 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 11:47:20.201664 WARNING: region 1:
9455 11:47:20.207962 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 11:47:20.211880 WARNING: region 2:
9457 11:47:20.215179 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 11:47:20.218317 WARNING: region 3:
9459 11:47:20.221661 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 11:47:20.225018 WARNING: region 4:
9461 11:47:20.231517 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 11:47:20.231601 WARNING: region 5:
9463 11:47:20.234769 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 11:47:20.238431 WARNING: region 6:
9465 11:47:20.241756 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 11:47:20.245007 WARNING: region 7:
9467 11:47:20.248451 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 11:47:20.254982 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 11:47:20.258202 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 11:47:20.261694 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 11:47:20.268435 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 11:47:20.271711 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 11:47:20.275117 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 11:47:20.281625 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 11:47:20.284926 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 11:47:20.288708 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 11:47:20.294953 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 11:47:20.298760 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 11:47:20.305159 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 11:47:20.308454 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 11:47:20.312199 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 11:47:20.318742 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 11:47:20.322007 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 11:47:20.325302 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 11:47:20.331977 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 11:47:20.335297 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 11:47:20.338528 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 11:47:20.345398 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 11:47:20.348707 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 11:47:20.355330 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 11:47:20.358408 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 11:47:20.361700 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 11:47:20.368381 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 11:47:20.371716 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 11:47:20.378279 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 11:47:20.381691 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 11:47:20.385004 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 11:47:20.392039 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 11:47:20.395813 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 11:47:20.398888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 11:47:20.405408 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 11:47:20.408777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 11:47:20.411958 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 11:47:20.415764 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 11:47:20.422172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 11:47:20.425353 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 11:47:20.428981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 11:47:20.432135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 11:47:20.438974 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 11:47:20.442177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 11:47:20.445391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 11:47:20.449433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 11:47:20.455793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 11:47:20.459110 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 11:47:20.462203 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 11:47:20.468705 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 11:47:20.472029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 11:47:20.475463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 11:47:20.482608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 11:47:20.486020 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 11:47:20.492696 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 11:47:20.496029 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 11:47:20.499263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 11:47:20.505628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 11:47:20.509036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 11:47:20.515731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 11:47:20.519409 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 11:47:20.525912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 11:47:20.529033 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 11:47:20.532446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 11:47:20.539081 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 11:47:20.542462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 11:47:20.549085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 11:47:20.552452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 11:47:20.559319 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 11:47:20.562587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 11:47:20.565854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 11:47:20.572368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 11:47:20.575731 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 11:47:20.582945 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 11:47:20.586292 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 11:47:20.592873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 11:47:20.596256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 11:47:20.599575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 11:47:20.606057 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 11:47:20.609304 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 11:47:20.615718 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 11:47:20.619500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 11:47:20.625575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 11:47:20.629258 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 11:47:20.635775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 11:47:20.639111 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 11:47:20.642844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 11:47:20.649250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 11:47:20.652945 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 11:47:20.659516 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 11:47:20.662920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 11:47:20.666128 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 11:47:20.672476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 11:47:20.676278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 11:47:20.682983 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 11:47:20.686289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 11:47:20.692873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 11:47:20.696306 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 11:47:20.699584 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 11:47:20.702926 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 11:47:20.709844 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 11:47:20.712607 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 11:47:20.715936 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 11:47:20.723073 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 11:47:20.726231 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 11:47:20.732980 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 11:47:20.736117 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 11:47:20.739287 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 11:47:20.746306 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 11:47:20.749705 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 11:47:20.752663 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 11:47:20.759981 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 11:47:20.763081 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 11:47:20.769648 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 11:47:20.773449 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 11:47:20.776639 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 11:47:20.783110 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 11:47:20.786490 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 11:47:20.789627 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 11:47:20.796394 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 11:47:20.799966 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 11:47:20.803188 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 11:47:20.806688 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 11:47:20.809902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 11:47:20.816661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 11:47:20.819940 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 11:47:20.826354 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 11:47:20.830286 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 11:47:20.833531 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 11:47:20.839882 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 11:47:20.843606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 11:47:20.846890 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 11:47:20.853542 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 11:47:20.856729 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 11:47:20.863196 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 11:47:20.866496 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 11:47:20.870060 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 11:47:20.876665 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 11:47:20.879791 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 11:47:20.886707 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 11:47:20.889981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 11:47:20.893314 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 11:47:20.899913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 11:47:20.903257 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 11:47:20.906780 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 11:47:20.913285 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 11:47:20.916653 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 11:47:20.923339 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 11:47:20.926488 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 11:47:20.929898 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 11:47:20.937183 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 11:47:20.940334 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 11:47:20.943578 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 11:47:20.950082 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 11:47:20.953747 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 11:47:20.960222 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 11:47:20.963318 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 11:47:20.967233 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 11:47:20.973763 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 11:47:20.976937 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 11:47:20.983698 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 11:47:20.986846 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 11:47:20.990497 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 11:47:20.996751 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 11:47:21.000082 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 11:47:21.006668 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 11:47:21.010000 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 11:47:21.013333 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 11:47:21.020512 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 11:47:21.023876 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 11:47:21.026563 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 11:47:21.033693 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 11:47:21.037026 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 11:47:21.043606 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 11:47:21.046977 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 11:47:21.050149 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 11:47:21.056528 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 11:47:21.059685 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 11:47:21.066344 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 11:47:21.070164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 11:47:21.073366 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 11:47:21.080122 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 11:47:21.083156 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 11:47:21.089379 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 11:47:21.092981 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 11:47:21.096097 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 11:47:21.103070 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 11:47:21.106330 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 11:47:21.113186 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 11:47:21.116353 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 11:47:21.119605 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 11:47:21.126299 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 11:47:21.129509 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 11:47:21.135977 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 11:47:21.139235 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 11:47:21.142568 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 11:47:21.149319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 11:47:21.152619 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 11:47:21.159421 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 11:47:21.162614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 11:47:21.169109 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 11:47:21.172387 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 11:47:21.176262 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 11:47:21.182561 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 11:47:21.186046 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 11:47:21.192511 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 11:47:21.195778 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 11:47:21.198994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 11:47:21.206076 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 11:47:21.209115 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 11:47:21.215719 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 11:47:21.219052 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 11:47:21.225622 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 11:47:21.228946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 11:47:21.232337 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 11:47:21.238923 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 11:47:21.242256 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 11:47:21.249050 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 11:47:21.252336 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 11:47:21.255512 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 11:47:21.262632 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 11:47:21.265610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 11:47:21.272639 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 11:47:21.275761 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 11:47:21.279149 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 11:47:21.285592 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 11:47:21.289395 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 11:47:21.295900 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 11:47:21.299273 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 11:47:21.305570 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 11:47:21.309373 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 11:47:21.312472 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 11:47:21.315576 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 11:47:21.318911 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 11:47:21.325479 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 11:47:21.328859 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 11:47:21.332198 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 11:47:21.339285 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 11:47:21.342556 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 11:47:21.345759 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 11:47:21.352359 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 11:47:21.355222 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 11:47:21.362365 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 11:47:21.365816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 11:47:21.369052 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 11:47:21.375104 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 11:47:21.378974 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 11:47:21.382202 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 11:47:21.388592 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 11:47:21.391984 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 11:47:21.395057 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 11:47:21.402132 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 11:47:21.405446 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 11:47:21.411826 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 11:47:21.414873 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 11:47:21.418553 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 11:47:21.424967 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 11:47:21.428287 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 11:47:21.434975 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 11:47:21.438182 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 11:47:21.441563 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 11:47:21.448619 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 11:47:21.451502 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 11:47:21.455326 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 11:47:21.462220 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 11:47:21.464930 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 11:47:21.468202 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 11:47:21.475226 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 11:47:21.478543 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 11:47:21.481621 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 11:47:21.488267 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 11:47:21.491490 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 11:47:21.494742 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 11:47:21.498415 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 11:47:21.501698 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 11:47:21.508191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 11:47:21.511345 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 11:47:21.515064 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 11:47:21.521392 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 11:47:21.524568 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 11:47:21.528336 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 11:47:21.531542 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 11:47:21.538048 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 11:47:21.541227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 11:47:21.544571 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 11:47:21.551278 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 11:47:21.554564 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 11:47:21.561244 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 11:47:21.564427 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 11:47:21.571670 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 11:47:21.574314 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 11:47:21.577646 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 11:47:21.584218 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 11:47:21.588053 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 11:47:21.594645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 11:47:21.597931 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 11:47:21.601181 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 11:47:21.608207 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 11:47:21.611205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 11:47:21.618154 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 11:47:21.621231 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 11:47:21.624472 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 11:47:21.631281 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 11:47:21.634534 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 11:47:21.640904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 11:47:21.644656 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 11:47:21.648030 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 11:47:21.654540 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 11:47:21.657674 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 11:47:21.664419 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 11:47:21.667894 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 11:47:21.674464 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 11:47:21.677292 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 11:47:21.680689 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 11:47:21.687967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 11:47:21.690606 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 11:47:21.693937 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 11:47:21.700910 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 11:47:21.703893 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 11:47:21.710409 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 11:47:21.714012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 11:47:21.720413 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 11:47:21.724394 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 11:47:21.727433 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 11:47:21.733701 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 11:47:21.737430 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 11:47:21.743710 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 11:47:21.746868 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 11:47:21.753996 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 11:47:21.757322 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 11:47:21.760458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 11:47:21.767149 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 11:47:21.770414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 11:47:21.776945 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 11:47:21.780360 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 11:47:21.783655 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 11:47:21.790291 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 11:47:21.793870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 11:47:21.800280 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 11:47:21.803629 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 11:47:21.807029 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 11:47:21.813065 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 11:47:21.816990 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 11:47:21.823446 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 11:47:21.826716 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 11:47:21.829914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 11:47:21.836898 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 11:47:21.840059 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 11:47:21.846710 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 11:47:21.849853 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 11:47:21.853265 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 11:47:21.859816 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 11:47:21.863140 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 11:47:21.870301 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 11:47:21.873563 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 11:47:21.876999 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 11:47:21.883656 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 11:47:21.886929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 11:47:21.893688 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 11:47:21.896961 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 11:47:21.903503 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 11:47:21.906905 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 11:47:21.910306 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 11:47:21.916672 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 11:47:21.920535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 11:47:21.926769 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 11:47:21.929968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 11:47:21.936597 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 11:47:21.940342 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 11:47:21.946660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 11:47:21.950415 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 11:47:21.953593 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 11:47:21.959928 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 11:47:21.963284 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 11:47:21.969905 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 11:47:21.973037 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 11:47:21.979677 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 11:47:21.983177 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 11:47:21.986292 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 11:47:21.993066 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 11:47:21.996293 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 11:47:22.002998 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 11:47:22.006355 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 11:47:22.013084 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 11:47:22.016318 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 11:47:22.019603 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 11:47:22.026336 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 11:47:22.029929 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 11:47:22.036266 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 11:47:22.039499 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 11:47:22.046373 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 11:47:22.049818 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 11:47:22.056557 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 11:47:22.059865 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 11:47:22.063042 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 11:47:22.069376 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 11:47:22.072542 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 11:47:22.079340 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 11:47:22.082482 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 11:47:22.089160 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 11:47:22.092634 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 11:47:22.096040 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 11:47:22.102684 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 11:47:22.106076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 11:47:22.109369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 11:47:22.115991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 11:47:22.119210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 11:47:22.125903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 11:47:22.129118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 11:47:22.135862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 11:47:22.139575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 11:47:22.145884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 11:47:22.149093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 11:47:22.156241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 11:47:22.159313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 11:47:22.166057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 11:47:22.169241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 11:47:22.175740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 11:47:22.179074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 11:47:22.185936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 11:47:22.188931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 11:47:22.195618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 11:47:22.198971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 11:47:22.205710 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 11:47:22.209022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 11:47:22.215541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 11:47:22.218961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 11:47:22.225400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 11:47:22.228758 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 11:47:22.235883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 11:47:22.239248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 11:47:22.245752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 11:47:22.249038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 11:47:22.255230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 11:47:22.258959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 11:47:22.262130 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 11:47:22.265408 INFO: [APUAPC] vio 0
9904 11:47:22.272324 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 11:47:22.275513 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 11:47:22.278691 INFO: [APUAPC] D0_APC_0: 0x400510
9907 11:47:22.282286 INFO: [APUAPC] D0_APC_1: 0x0
9908 11:47:22.285401 INFO: [APUAPC] D0_APC_2: 0x1540
9909 11:47:22.288900 INFO: [APUAPC] D0_APC_3: 0x0
9910 11:47:22.291917 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 11:47:22.295082 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 11:47:22.298870 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 11:47:22.298990 INFO: [APUAPC] D1_APC_3: 0x0
9914 11:47:22.304997 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 11:47:22.308363 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 11:47:22.312257 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 11:47:22.312372 INFO: [APUAPC] D2_APC_3: 0x0
9918 11:47:22.315038 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 11:47:22.318925 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 11:47:22.322281 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 11:47:22.325580 INFO: [APUAPC] D3_APC_3: 0x0
9922 11:47:22.328783 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 11:47:22.332240 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 11:47:22.335386 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 11:47:22.338695 INFO: [APUAPC] D4_APC_3: 0x0
9926 11:47:22.342120 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 11:47:22.345260 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 11:47:22.348344 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 11:47:22.351781 INFO: [APUAPC] D5_APC_3: 0x0
9930 11:47:22.355061 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 11:47:22.358967 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 11:47:22.361527 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 11:47:22.365310 INFO: [APUAPC] D6_APC_3: 0x0
9934 11:47:22.368444 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 11:47:22.371598 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 11:47:22.374878 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 11:47:22.378664 INFO: [APUAPC] D7_APC_3: 0x0
9938 11:47:22.381876 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 11:47:22.385213 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 11:47:22.388243 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 11:47:22.391734 INFO: [APUAPC] D8_APC_3: 0x0
9942 11:47:22.395494 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 11:47:22.398570 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 11:47:22.401623 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 11:47:22.404854 INFO: [APUAPC] D9_APC_3: 0x0
9946 11:47:22.408692 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 11:47:22.411387 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 11:47:22.415258 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 11:47:22.418041 INFO: [APUAPC] D10_APC_3: 0x0
9950 11:47:22.421428 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 11:47:22.425337 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 11:47:22.428136 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 11:47:22.431519 INFO: [APUAPC] D11_APC_3: 0x0
9954 11:47:22.434689 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 11:47:22.437968 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 11:47:22.441788 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 11:47:22.445074 INFO: [APUAPC] D12_APC_3: 0x0
9958 11:47:22.448310 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 11:47:22.451615 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 11:47:22.454948 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 11:47:22.458156 INFO: [APUAPC] D13_APC_3: 0x0
9962 11:47:22.461441 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 11:47:22.464552 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 11:47:22.468469 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 11:47:22.471666 INFO: [APUAPC] D14_APC_3: 0x0
9966 11:47:22.474856 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 11:47:22.478010 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 11:47:22.481202 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 11:47:22.484471 INFO: [APUAPC] D15_APC_3: 0x0
9970 11:47:22.488230 INFO: [APUAPC] APC_CON: 0x4
9971 11:47:22.491488 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 11:47:22.494744 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 11:47:22.494830 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 11:47:22.497917 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 11:47:22.501135 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 11:47:22.504763 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 11:47:22.507986 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 11:47:22.511179 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 11:47:22.514842 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 11:47:22.518137 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 11:47:22.521253 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 11:47:22.524534 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 11:47:22.528057 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 11:47:22.528135 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 11:47:22.531251 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 11:47:22.534153 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 11:47:22.537867 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 11:47:22.541306 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 11:47:22.544477 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 11:47:22.547896 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 11:47:22.551192 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 11:47:22.554588 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 11:47:22.558072 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 11:47:22.561285 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 11:47:22.564610 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 11:47:22.567375 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 11:47:22.567483 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 11:47:22.571155 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 11:47:22.574214 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 11:47:22.577493 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 11:47:22.580614 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 11:47:22.583916 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 11:47:22.587243 INFO: [NOCDAPC] APC_CON: 0x4
10004 11:47:22.590983 INFO: [APUAPC] set_apusys_apc done
10005 11:47:22.594085 INFO: [DEVAPC] devapc_init done
10006 11:47:22.597227 INFO: GICv3 without legacy support detected.
10007 11:47:22.600523 INFO: ARM GICv3 driver initialized in EL3
10008 11:47:22.607178 INFO: Maximum SPI INTID supported: 639
10009 11:47:22.610937 INFO: BL31: Initializing runtime services
10010 11:47:22.617048 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 11:47:22.617136 INFO: SPM: enable CPC mode
10012 11:47:22.623919 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 11:47:22.626873 INFO: BL31: Preparing for EL3 exit to normal world
10014 11:47:22.630346 INFO: Entry point address = 0x80000000
10015 11:47:22.633598 INFO: SPSR = 0x8
10016 11:47:22.639828
10017 11:47:22.639917
10018 11:47:22.640008
10019 11:47:22.642900 Starting depthcharge on Spherion...
10020 11:47:22.642989
10021 11:47:22.643076 Wipe memory regions:
10022 11:47:22.643163
10023 11:47:22.643967 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10024 11:47:22.644106 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10025 11:47:22.644200 Setting prompt string to ['asurada:']
10026 11:47:22.644296 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10027 11:47:22.646224 [0x00000040000000, 0x00000054600000)
10028 11:47:22.768296
10029 11:47:22.768461 [0x00000054660000, 0x00000080000000)
10030 11:47:23.028936
10031 11:47:23.029128 [0x000000821a7280, 0x000000ffe64000)
10032 11:47:23.774007
10033 11:47:23.774216 [0x00000100000000, 0x00000240000000)
10034 11:47:25.664437
10035 11:47:25.667592 Initializing XHCI USB controller at 0x11200000.
10036 11:47:26.705429
10037 11:47:26.708676 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 11:47:26.708815
10039 11:47:26.708890
10040 11:47:26.708955
10041 11:47:26.709241 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 11:47:26.809622 asurada: tftpboot 192.168.201.1 10742264/tftp-deploy-jijrys3y/kernel/image.itb 10742264/tftp-deploy-jijrys3y/kernel/cmdline
10044 11:47:26.809794 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 11:47:26.809891 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10046 11:47:26.814381 tftpboot 192.168.201.1 10742264/tftp-deploy-jijrys3y/kernel/image.itbtp-deploy-jijrys3y/kernel/cmdline
10047 11:47:26.814504
10048 11:47:26.814601 Waiting for link
10049 11:47:26.974343
10050 11:47:26.974483 R8152: Initializing
10051 11:47:26.974584
10052 11:47:26.977612 Version 9 (ocp_data = 6010)
10053 11:47:26.977698
10054 11:47:26.980966 R8152: Done initializing
10055 11:47:26.981041
10056 11:47:26.981105 Adding net device
10057 11:47:28.853451
10058 11:47:28.853609 done.
10059 11:47:28.853679
10060 11:47:28.853743 MAC: 00:e0:4c:78:7a:aa
10061 11:47:28.853806
10062 11:47:28.856619 Sending DHCP discover... done.
10063 11:47:28.856728
10064 11:47:28.859956 Waiting for reply... done.
10065 11:47:28.860047
10066 11:47:28.863734 Sending DHCP request... done.
10067 11:47:28.863840
10068 11:47:28.863957 Waiting for reply... done.
10069 11:47:28.864025
10070 11:47:28.867094 My ip is 192.168.201.12
10071 11:47:28.867168
10072 11:47:28.870409 The DHCP server ip is 192.168.201.1
10073 11:47:28.870495
10074 11:47:28.873681 TFTP server IP predefined by user: 192.168.201.1
10075 11:47:28.873767
10076 11:47:28.880387 Bootfile predefined by user: 10742264/tftp-deploy-jijrys3y/kernel/image.itb
10077 11:47:28.880507
10078 11:47:28.883771 Sending tftp read request... done.
10079 11:47:28.883883
10080 11:47:28.886855 Waiting for the transfer...
10081 11:47:28.886940
10082 11:47:29.210945 00000000 ################################################################
10083 11:47:29.211094
10084 11:47:29.511884 00080000 ################################################################
10085 11:47:29.512050
10086 11:47:29.845327 00100000 ################################################################
10087 11:47:29.845478
10088 11:47:30.179683 00180000 ################################################################
10089 11:47:30.179890
10090 11:47:30.500963 00200000 ################################################################
10091 11:47:30.501107
10092 11:47:30.818944 00280000 ################################################################
10093 11:47:30.819142
10094 11:47:31.161871 00300000 ################################################################
10095 11:47:31.162045
10096 11:47:31.425133 00380000 ################################################################
10097 11:47:31.425298
10098 11:47:31.688267 00400000 ################################################################
10099 11:47:31.688434
10100 11:47:32.003783 00480000 ################################################################
10101 11:47:32.003946
10102 11:47:32.352918 00500000 ################################################################
10103 11:47:32.353058
10104 11:47:32.696812 00580000 ################################################################
10105 11:47:32.696956
10106 11:47:33.049522 00600000 ################################################################
10107 11:47:33.049700
10108 11:47:33.390590 00680000 ################################################################
10109 11:47:33.390778
10110 11:47:33.735284 00700000 ################################################################
10111 11:47:33.735433
10112 11:47:34.077326 00780000 ################################################################
10113 11:47:34.077501
10114 11:47:34.419554 00800000 ################################################################
10115 11:47:34.419722
10116 11:47:34.743992 00880000 ################################################################
10117 11:47:34.744229
10118 11:47:35.070410 00900000 ################################################################
10119 11:47:35.070569
10120 11:47:35.417233 00980000 ################################################################
10121 11:47:35.417390
10122 11:47:35.768222 00a00000 ################################################################
10123 11:47:35.768402
10124 11:47:36.087430 00a80000 ################################################################
10125 11:47:36.087598
10126 11:47:36.356741 00b00000 ################################################################
10127 11:47:36.356912
10128 11:47:36.625178 00b80000 ################################################################
10129 11:47:36.625324
10130 11:47:36.896996 00c00000 ################################################################
10131 11:47:36.897131
10132 11:47:37.156484 00c80000 ################################################################
10133 11:47:37.156646
10134 11:47:37.428256 00d00000 ################################################################
10135 11:47:37.428417
10136 11:47:37.701822 00d80000 ################################################################
10137 11:47:37.701976
10138 11:47:37.975922 00e00000 ################################################################
10139 11:47:37.976085
10140 11:47:38.248310 00e80000 ################################################################
10141 11:47:38.248501
10142 11:47:38.523716 00f00000 ################################################################
10143 11:47:38.523866
10144 11:47:38.799105 00f80000 ################################################################
10145 11:47:38.799257
10146 11:47:39.083548 01000000 ################################################################
10147 11:47:39.083767
10148 11:47:39.366515 01080000 ################################################################
10149 11:47:39.366700
10150 11:47:39.642223 01100000 ################################################################
10151 11:47:39.642392
10152 11:47:39.917350 01180000 ################################################################
10153 11:47:39.917520
10154 11:47:40.194483 01200000 ################################################################
10155 11:47:40.194649
10156 11:47:40.476530 01280000 ################################################################
10157 11:47:40.476722
10158 11:47:40.763851 01300000 ################################################################
10159 11:47:40.764030
10160 11:47:41.037670 01380000 ################################################################
10161 11:47:41.037849
10162 11:47:41.311023 01400000 ################################################################
10163 11:47:41.311202
10164 11:47:41.590346 01480000 ################################################################
10165 11:47:41.590505
10166 11:47:41.858803 01500000 ################################################################
10167 11:47:41.858968
10168 11:47:42.139184 01580000 ################################################################
10169 11:47:42.139338
10170 11:47:42.404894 01600000 ################################################################
10171 11:47:42.405077
10172 11:47:42.677884 01680000 ################################################################
10173 11:47:42.678065
10174 11:47:42.946344 01700000 ################################################################
10175 11:47:42.946503
10176 11:47:43.219141 01780000 ################################################################
10177 11:47:43.219319
10178 11:47:43.484622 01800000 ################################################################
10179 11:47:43.484808
10180 11:47:43.754674 01880000 ################################################################
10181 11:47:43.754821
10182 11:47:44.020886 01900000 ################################################################
10183 11:47:44.021036
10184 11:47:44.287564 01980000 ################################################################
10185 11:47:44.287746
10186 11:47:44.544685 01a00000 ################################################################
10187 11:47:44.544869
10188 11:47:44.823319 01a80000 ################################################################
10189 11:47:44.823494
10190 11:47:45.090389 01b00000 ################################################################
10191 11:47:45.090549
10192 11:47:45.370996 01b80000 ################################################################
10193 11:47:45.371166
10194 11:47:45.638000 01c00000 ################################################################
10195 11:47:45.638179
10196 11:47:45.911467 01c80000 ################################################################
10197 11:47:45.911614
10198 11:47:46.194354 01d00000 ################################################################
10199 11:47:46.194500
10200 11:47:46.462367 01d80000 ################################################################
10201 11:47:46.462521
10202 11:47:46.733560 01e00000 ################################################################
10203 11:47:46.733729
10204 11:47:46.999926 01e80000 ################################################################
10205 11:47:47.000088
10206 11:47:47.270019 01f00000 ################################################################
10207 11:47:47.270167
10208 11:47:47.523864 01f80000 ################################################################
10209 11:47:47.524025
10210 11:47:47.783936 02000000 ################################################################
10211 11:47:47.784092
10212 11:47:48.046260 02080000 ################################################################
10213 11:47:48.046411
10214 11:47:48.311827 02100000 ################################################################
10215 11:47:48.312006
10216 11:47:48.581864 02180000 ################################################################
10217 11:47:48.582060
10218 11:47:48.882924 02200000 ################################################################
10219 11:47:48.883101
10220 11:47:49.158527 02280000 ################################################################
10221 11:47:49.158703
10222 11:47:49.426321 02300000 ################################################################
10223 11:47:49.426511
10224 11:47:49.697779 02380000 ################################################################
10225 11:47:49.697932
10226 11:47:49.972769 02400000 ################################################################
10227 11:47:49.972918
10228 11:47:50.255526 02480000 ################################################################
10229 11:47:50.255704
10230 11:47:50.536850 02500000 ################################################################
10231 11:47:50.537004
10232 11:47:50.806319 02580000 ################################################################
10233 11:47:50.806476
10234 11:47:51.075392 02600000 ################################################################
10235 11:47:51.075547
10236 11:47:51.341480 02680000 ################################################################
10237 11:47:51.341643
10238 11:47:51.602879 02700000 ################################################################
10239 11:47:51.603015
10240 11:47:51.897671 02780000 ################################################################
10241 11:47:51.897864
10242 11:47:52.158122 02800000 ################################################################
10243 11:47:52.158306
10244 11:47:52.420539 02880000 ################################################################
10245 11:47:52.420728
10246 11:47:52.683958 02900000 ################################################################
10247 11:47:52.684114
10248 11:47:52.953509 02980000 ################################################################
10249 11:47:52.953685
10250 11:47:53.217211 02a00000 ################################################################
10251 11:47:53.217366
10252 11:47:53.477549 02a80000 ################################################################
10253 11:47:53.477695
10254 11:47:53.741396 02b00000 ################################################################
10255 11:47:53.741562
10256 11:47:54.016918 02b80000 ################################################################
10257 11:47:54.017055
10258 11:47:54.279566 02c00000 ################################################################
10259 11:47:54.279706
10260 11:47:54.547292 02c80000 ################################################################
10261 11:47:54.547436
10262 11:47:54.815319 02d00000 ################################################################
10263 11:47:54.815457
10264 11:47:55.135579 02d80000 ################################################################
10265 11:47:55.135717
10266 11:47:55.467566 02e00000 ################################################################
10267 11:47:55.467728
10268 11:47:55.805200 02e80000 ################################################################
10269 11:47:55.805340
10270 11:47:56.138739 02f00000 ################################################################
10271 11:47:56.138876
10272 11:47:56.473999 02f80000 ################################################################
10273 11:47:56.474143
10274 11:47:56.816532 03000000 ################################################################
10275 11:47:56.816706
10276 11:47:57.151318 03080000 ################################################################
10277 11:47:57.151493
10278 11:47:57.484729 03100000 ################################################################
10279 11:47:57.484901
10280 11:47:57.824558 03180000 ################################################################
10281 11:47:57.824767
10282 11:47:58.161133 03200000 ################################################################
10283 11:47:58.161283
10284 11:47:58.489675 03280000 ################################################################
10285 11:47:58.489864
10286 11:47:58.803362 03300000 ################################################################
10287 11:47:58.803552
10288 11:47:59.121347 03380000 ################################################################
10289 11:47:59.121503
10290 11:47:59.432991 03400000 ################################################################
10291 11:47:59.433166
10292 11:47:59.745868 03480000 ################################################################
10293 11:47:59.746053
10294 11:48:00.021998 03500000 ################################################################
10295 11:48:00.022151
10296 11:48:00.271513 03580000 ################################################################
10297 11:48:00.271699
10298 11:48:00.543282 03600000 ################################################################
10299 11:48:00.543457
10300 11:48:00.827823 03680000 ################################################################
10301 11:48:00.827988
10302 11:48:00.930181 03700000 ########################## done.
10303 11:48:00.930364
10304 11:48:00.933490 The bootfile was 57879062 bytes long.
10305 11:48:00.933597
10306 11:48:00.936798 Sending tftp read request... done.
10307 11:48:00.936897
10308 11:48:00.940052 Waiting for the transfer...
10309 11:48:00.940163
10310 11:48:00.940267 00000000 # done.
10311 11:48:00.940364
10312 11:48:00.949910 Command line loaded dynamically from TFTP file: 10742264/tftp-deploy-jijrys3y/kernel/cmdline
10313 11:48:00.950026
10314 11:48:00.959795 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10315 11:48:00.959910
10316 11:48:00.960008 Loading FIT.
10317 11:48:00.963253
10318 11:48:00.963364 Image ramdisk-1 has 47386741 bytes.
10319 11:48:00.963466
10320 11:48:00.966437 Image fdt-1 has 46924 bytes.
10321 11:48:00.966547
10322 11:48:00.969740 Image kernel-1 has 10443363 bytes.
10323 11:48:00.969850
10324 11:48:00.980189 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10325 11:48:00.980314
10326 11:48:00.996349 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10327 11:48:00.996487
10328 11:48:01.003178 Choosing best match conf-1 for compat google,spherion-rev2.
10329 11:48:01.003298
10330 11:48:01.010938 Connected to device vid:did:rid of 1ae0:0028:00
10331 11:48:01.018950
10332 11:48:01.022699 tpm_get_response: command 0x17b, return code 0x0
10333 11:48:01.022810
10334 11:48:01.025943 ec_init: CrosEC protocol v3 supported (256, 248)
10335 11:48:01.029774
10336 11:48:01.033061 tpm_cleanup: add release locality here.
10337 11:48:01.033168
10338 11:48:01.033269 Shutting down all USB controllers.
10339 11:48:01.036300
10340 11:48:01.036406 Removing current net device
10341 11:48:01.036508
10342 11:48:01.042947 Exiting depthcharge with code 4 at timestamp: 67707289
10343 11:48:01.043061
10344 11:48:01.046316 LZMA decompressing kernel-1 to 0x821a6718
10345 11:48:01.046444
10346 11:48:01.049674 LZMA decompressing kernel-1 to 0x40000000
10347 11:48:02.360854
10348 11:48:02.361037 jumping to kernel
10349 11:48:02.361781 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10350 11:48:02.361915 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10351 11:48:02.362026 Setting prompt string to ['Linux version [0-9]']
10352 11:48:02.362132 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10353 11:48:02.362236 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10354 11:48:02.441940
10355 11:48:02.445489 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10356 11:48:02.448977 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10357 11:48:02.449100 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10358 11:48:02.449204 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10359 11:48:02.449286 Using line separator: #'\n'#
10360 11:48:02.449365 No login prompt set.
10361 11:48:02.449430 Parsing kernel messages
10362 11:48:02.449488 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10363 11:48:02.449603 [login-action] Waiting for messages, (timeout 00:03:45)
10364 11:48:02.468550 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10365 11:48:02.471888 [ 0.000000] random: crng init done
10366 11:48:02.475239 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10367 11:48:02.478404 [ 0.000000] efi: UEFI not found.
10368 11:48:02.488390 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10369 11:48:02.495093 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10370 11:48:02.505268 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10371 11:48:02.514936 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10372 11:48:02.521655 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10373 11:48:02.524741 [ 0.000000] printk: bootconsole [mtk8250] enabled
10374 11:48:02.533266 [ 0.000000] NUMA: No NUMA configuration found
10375 11:48:02.540180 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10376 11:48:02.547202 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10377 11:48:02.547291 [ 0.000000] Zone ranges:
10378 11:48:02.553863 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10379 11:48:02.557136 [ 0.000000] DMA32 empty
10380 11:48:02.563454 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10381 11:48:02.566912 [ 0.000000] Movable zone start for each node
10382 11:48:02.570296 [ 0.000000] Early memory node ranges
10383 11:48:02.576286 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10384 11:48:02.583337 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10385 11:48:02.590318 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10386 11:48:02.596731 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10387 11:48:02.603297 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10388 11:48:02.610156 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10389 11:48:02.665929 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10390 11:48:02.672594 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10391 11:48:02.679215 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10392 11:48:02.682607 [ 0.000000] psci: probing for conduit method from DT.
10393 11:48:02.689164 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10394 11:48:02.692346 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10395 11:48:02.698858 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10396 11:48:02.702085 [ 0.000000] psci: SMC Calling Convention v1.2
10397 11:48:02.709025 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10398 11:48:02.712317 [ 0.000000] Detected VIPT I-cache on CPU0
10399 11:48:02.719117 [ 0.000000] CPU features: detected: GIC system register CPU interface
10400 11:48:02.725626 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10401 11:48:02.732640 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10402 11:48:02.739151 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10403 11:48:02.745757 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10404 11:48:02.755283 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10405 11:48:02.758552 [ 0.000000] alternatives: applying boot alternatives
10406 11:48:02.765525 [ 0.000000] Fallback order for Node 0: 0
10407 11:48:02.772055 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10408 11:48:02.775390 [ 0.000000] Policy zone: Normal
10409 11:48:02.785457 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10410 11:48:02.795228 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10411 11:48:02.807979 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10412 11:48:02.817899 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10413 11:48:02.824842 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10414 11:48:02.828043 <6>[ 0.000000] software IO TLB: area num 8.
10415 11:48:02.884671 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10416 11:48:03.033389 <6>[ 0.000000] Memory: 7924880K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 427888K reserved, 32768K cma-reserved)
10417 11:48:03.040349 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10418 11:48:03.046937 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10419 11:48:03.050193 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10420 11:48:03.056569 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10421 11:48:03.063107 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10422 11:48:03.066294 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10423 11:48:03.076313 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10424 11:48:03.083209 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10425 11:48:03.089769 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10426 11:48:03.096056 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10427 11:48:03.099393 <6>[ 0.000000] GICv3: 608 SPIs implemented
10428 11:48:03.102561 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10429 11:48:03.109250 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10430 11:48:03.112385 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10431 11:48:03.119332 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10432 11:48:03.132425 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10433 11:48:03.145613 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10434 11:48:03.152810 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10435 11:48:03.160267 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10436 11:48:03.173437 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10437 11:48:03.180234 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10438 11:48:03.186555 <6>[ 0.009175] Console: colour dummy device 80x25
10439 11:48:03.196392 <6>[ 0.013891] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10440 11:48:03.202928 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10441 11:48:03.206731 <6>[ 0.029302] LSM: Security Framework initializing
10442 11:48:03.213465 <6>[ 0.034241] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 11:48:03.223483 <6>[ 0.042056] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 11:48:03.230012 <6>[ 0.051484] cblist_init_generic: Setting adjustable number of callback queues.
10445 11:48:03.236579 <6>[ 0.058936] cblist_init_generic: Setting shift to 3 and lim to 1.
10446 11:48:03.243156 <6>[ 0.065313] cblist_init_generic: Setting shift to 3 and lim to 1.
10447 11:48:03.249623 <6>[ 0.071758] rcu: Hierarchical SRCU implementation.
10448 11:48:03.252919 <6>[ 0.076771] rcu: Max phase no-delay instances is 1000.
10449 11:48:03.261492 <6>[ 0.083787] EFI services will not be available.
10450 11:48:03.264828 <6>[ 0.088759] smp: Bringing up secondary CPUs ...
10451 11:48:03.273612 <6>[ 0.093842] Detected VIPT I-cache on CPU1
10452 11:48:03.280213 <6>[ 0.093915] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10453 11:48:03.286863 <6>[ 0.093945] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10454 11:48:03.290477 <6>[ 0.094274] Detected VIPT I-cache on CPU2
10455 11:48:03.297410 <6>[ 0.094322] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10456 11:48:03.303617 <6>[ 0.094337] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10457 11:48:03.310060 <6>[ 0.094595] Detected VIPT I-cache on CPU3
10458 11:48:03.317485 <6>[ 0.094642] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10459 11:48:03.323916 <6>[ 0.094656] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10460 11:48:03.327329 <6>[ 0.094963] CPU features: detected: Spectre-v4
10461 11:48:03.333301 <6>[ 0.094970] CPU features: detected: Spectre-BHB
10462 11:48:03.336695 <6>[ 0.094976] Detected PIPT I-cache on CPU4
10463 11:48:03.343745 <6>[ 0.095034] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10464 11:48:03.350510 <6>[ 0.095050] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10465 11:48:03.353824 <6>[ 0.095347] Detected PIPT I-cache on CPU5
10466 11:48:03.363547 <6>[ 0.095409] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10467 11:48:03.370049 <6>[ 0.095425] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10468 11:48:03.373186 <6>[ 0.095708] Detected PIPT I-cache on CPU6
10469 11:48:03.379799 <6>[ 0.095774] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10470 11:48:03.386467 <6>[ 0.095790] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10471 11:48:03.390482 <6>[ 0.096090] Detected PIPT I-cache on CPU7
10472 11:48:03.399809 <6>[ 0.096154] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10473 11:48:03.406403 <6>[ 0.096170] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10474 11:48:03.410748 <6>[ 0.096218] smp: Brought up 1 node, 8 CPUs
10475 11:48:03.413245 <6>[ 0.237544] SMP: Total of 8 processors activated.
10476 11:48:03.419681 <6>[ 0.242465] CPU features: detected: 32-bit EL0 Support
10477 11:48:03.429501 <6>[ 0.247828] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10478 11:48:03.436105 <6>[ 0.256682] CPU features: detected: Common not Private translations
10479 11:48:03.439637 <6>[ 0.263158] CPU features: detected: CRC32 instructions
10480 11:48:03.446296 <6>[ 0.268542] CPU features: detected: RCpc load-acquire (LDAPR)
10481 11:48:03.452795 <6>[ 0.274539] CPU features: detected: LSE atomic instructions
10482 11:48:03.459580 <6>[ 0.280320] CPU features: detected: Privileged Access Never
10483 11:48:03.463063 <6>[ 0.286135] CPU features: detected: RAS Extension Support
10484 11:48:03.472559 <6>[ 0.291744] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10485 11:48:03.475915 <6>[ 0.298955] CPU: All CPU(s) started at EL2
10486 11:48:03.482933 <6>[ 0.303298] alternatives: applying system-wide alternatives
10487 11:48:03.491468 <6>[ 0.314009] devtmpfs: initialized
10488 11:48:03.507056 <6>[ 0.322904] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10489 11:48:03.513528 <6>[ 0.332864] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10490 11:48:03.520261 <6>[ 0.341069] pinctrl core: initialized pinctrl subsystem
10491 11:48:03.523503 <6>[ 0.347737] DMI not present or invalid.
10492 11:48:03.529880 <6>[ 0.352146] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10493 11:48:03.539709 <6>[ 0.359030] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10494 11:48:03.546326 <6>[ 0.366606] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10495 11:48:03.556354 <6>[ 0.374826] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10496 11:48:03.559746 <6>[ 0.383066] audit: initializing netlink subsys (disabled)
10497 11:48:03.570221 <5>[ 0.388759] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10498 11:48:03.576769 <6>[ 0.389465] thermal_sys: Registered thermal governor 'step_wise'
10499 11:48:03.583492 <6>[ 0.396725] thermal_sys: Registered thermal governor 'power_allocator'
10500 11:48:03.586321 <6>[ 0.402977] cpuidle: using governor menu
10501 11:48:03.593513 <6>[ 0.413934] NET: Registered PF_QIPCRTR protocol family
10502 11:48:03.600226 <6>[ 0.419414] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10503 11:48:03.603492 <6>[ 0.426515] ASID allocator initialised with 32768 entries
10504 11:48:03.610445 <6>[ 0.433078] Serial: AMBA PL011 UART driver
10505 11:48:03.619141 <4>[ 0.441767] Trying to register duplicate clock ID: 134
10506 11:48:03.673264 <6>[ 0.499385] KASLR enabled
10507 11:48:03.687697 <6>[ 0.507210] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10508 11:48:03.694739 <6>[ 0.514227] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10509 11:48:03.701071 <6>[ 0.520720] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10510 11:48:03.707730 <6>[ 0.527724] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10511 11:48:03.714778 <6>[ 0.534211] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10512 11:48:03.721091 <6>[ 0.541217] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10513 11:48:03.728010 <6>[ 0.547705] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10514 11:48:03.734303 <6>[ 0.554708] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10515 11:48:03.737367 <6>[ 0.562223] ACPI: Interpreter disabled.
10516 11:48:03.745864 <6>[ 0.568611] iommu: Default domain type: Translated
10517 11:48:03.752632 <6>[ 0.573724] iommu: DMA domain TLB invalidation policy: strict mode
10518 11:48:03.755866 <5>[ 0.580382] SCSI subsystem initialized
10519 11:48:03.762498 <6>[ 0.584547] usbcore: registered new interface driver usbfs
10520 11:48:03.769209 <6>[ 0.590283] usbcore: registered new interface driver hub
10521 11:48:03.772496 <6>[ 0.595837] usbcore: registered new device driver usb
10522 11:48:03.779110 <6>[ 0.601926] pps_core: LinuxPPS API ver. 1 registered
10523 11:48:03.789082 <6>[ 0.607119] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10524 11:48:03.792330 <6>[ 0.616464] PTP clock support registered
10525 11:48:03.796063 <6>[ 0.620706] EDAC MC: Ver: 3.0.0
10526 11:48:03.803063 <6>[ 0.625853] FPGA manager framework
10527 11:48:03.806256 <6>[ 0.629534] Advanced Linux Sound Architecture Driver Initialized.
10528 11:48:03.810243 <6>[ 0.636315] vgaarb: loaded
10529 11:48:03.816715 <6>[ 0.639474] clocksource: Switched to clocksource arch_sys_counter
10530 11:48:03.823267 <5>[ 0.645917] VFS: Disk quotas dquot_6.6.0
10531 11:48:03.829761 <6>[ 0.650103] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10532 11:48:03.832987 <6>[ 0.657292] pnp: PnP ACPI: disabled
10533 11:48:03.841040 <6>[ 0.663989] NET: Registered PF_INET protocol family
10534 11:48:03.848339 <6>[ 0.669573] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10535 11:48:03.862188 <6>[ 0.681871] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10536 11:48:03.872322 <6>[ 0.690684] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10537 11:48:03.879006 <6>[ 0.698658] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10538 11:48:03.885584 <6>[ 0.707357] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10539 11:48:03.898133 <6>[ 0.717118] TCP: Hash tables configured (established 65536 bind 65536)
10540 11:48:03.904522 <6>[ 0.723974] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10541 11:48:03.910894 <6>[ 0.731172] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 11:48:03.917504 <6>[ 0.738876] NET: Registered PF_UNIX/PF_LOCAL protocol family
10543 11:48:03.924198 <6>[ 0.745018] RPC: Registered named UNIX socket transport module.
10544 11:48:03.928079 <6>[ 0.751169] RPC: Registered udp transport module.
10545 11:48:03.934285 <6>[ 0.756099] RPC: Registered tcp transport module.
10546 11:48:03.941091 <6>[ 0.761033] RPC: Registered tcp NFSv4.1 backchannel transport module.
10547 11:48:03.944331 <6>[ 0.767699] PCI: CLS 0 bytes, default 64
10548 11:48:03.947587 <6>[ 0.771994] Unpacking initramfs...
10549 11:48:03.964785 <6>[ 0.784048] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10550 11:48:03.974897 <6>[ 0.792685] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10551 11:48:03.978260 <6>[ 0.801471] kvm [1]: IPA Size Limit: 40 bits
10552 11:48:03.984908 <6>[ 0.805994] kvm [1]: GICv3: no GICV resource entry
10553 11:48:03.988112 <6>[ 0.811012] kvm [1]: disabling GICv2 emulation
10554 11:48:03.994859 <6>[ 0.815700] kvm [1]: GIC system register CPU interface enabled
10555 11:48:03.997576 <6>[ 0.821860] kvm [1]: vgic interrupt IRQ18
10556 11:48:04.004771 <6>[ 0.827572] kvm [1]: VHE mode initialized successfully
10557 11:48:04.011673 <5>[ 0.833964] Initialise system trusted keyrings
10558 11:48:04.018221 <6>[ 0.838793] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10559 11:48:04.026310 <6>[ 0.848803] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10560 11:48:04.032359 <5>[ 0.855180] NFS: Registering the id_resolver key type
10561 11:48:04.035619 <5>[ 0.860482] Key type id_resolver registered
10562 11:48:04.042677 <5>[ 0.864899] Key type id_legacy registered
10563 11:48:04.049017 <6>[ 0.869175] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10564 11:48:04.055799 <6>[ 0.876096] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10565 11:48:04.062354 <6>[ 0.883831] 9p: Installing v9fs 9p2000 file system support
10566 11:48:04.099184 <5>[ 0.922070] Key type asymmetric registered
10567 11:48:04.102470 <5>[ 0.926402] Asymmetric key parser 'x509' registered
10568 11:48:04.112806 <6>[ 0.931553] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10569 11:48:04.115561 <6>[ 0.939164] io scheduler mq-deadline registered
10570 11:48:04.119242 <6>[ 0.943922] io scheduler kyber registered
10571 11:48:04.137688 <6>[ 0.960606] EINJ: ACPI disabled.
10572 11:48:04.169253 <4>[ 0.985085] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 11:48:04.178810 <4>[ 0.995697] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 11:48:04.193251 <6>[ 1.016058] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10575 11:48:04.201218 <6>[ 1.023975] printk: console [ttyS0] disabled
10576 11:48:04.229430 <6>[ 1.048617] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10577 11:48:04.236009 <6>[ 1.058089] printk: console [ttyS0] enabled
10578 11:48:04.239286 <6>[ 1.058089] printk: console [ttyS0] enabled
10579 11:48:04.246118 <6>[ 1.066985] printk: bootconsole [mtk8250] disabled
10580 11:48:04.249322 <6>[ 1.066985] printk: bootconsole [mtk8250] disabled
10581 11:48:04.256367 <6>[ 1.077998] SuperH (H)SCI(F) driver initialized
10582 11:48:04.259260 <6>[ 1.083257] msm_serial: driver initialized
10583 11:48:04.272375 <6>[ 1.092057] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10584 11:48:04.282578 <6>[ 1.100600] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10585 11:48:04.289094 <6>[ 1.109142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10586 11:48:04.299175 <6>[ 1.117769] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10587 11:48:04.305838 <6>[ 1.126475] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10588 11:48:04.315930 <6>[ 1.135192] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10589 11:48:04.325752 <6>[ 1.143731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10590 11:48:04.332197 <6>[ 1.152524] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10591 11:48:04.342492 <6>[ 1.161065] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10592 11:48:04.353557 <6>[ 1.176329] loop: module loaded
10593 11:48:04.360075 <6>[ 1.182310] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10594 11:48:04.382790 <4>[ 1.205496] mtk-pmic-keys: Failed to locate of_node [id: -1]
10595 11:48:04.389093 <6>[ 1.212155] megasas: 07.719.03.00-rc1
10596 11:48:04.398579 <6>[ 1.221531] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10597 11:48:04.408125 <6>[ 1.230842] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10598 11:48:04.424011 <6>[ 1.246642] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10599 11:48:04.479556 <6>[ 1.295948] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10600 11:48:05.929404 <6>[ 2.752220] Freeing initrd memory: 46272K
10601 11:48:05.939275 <6>[ 2.762336] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10602 11:48:05.950012 <6>[ 2.773131] tun: Universal TUN/TAP device driver, 1.6
10603 11:48:05.953267 <6>[ 2.779172] thunder_xcv, ver 1.0
10604 11:48:05.956629 <6>[ 2.782676] thunder_bgx, ver 1.0
10605 11:48:05.960050 <6>[ 2.786170] nicpf, ver 1.0
10606 11:48:05.970748 <6>[ 2.790164] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10607 11:48:05.974032 <6>[ 2.797640] hns3: Copyright (c) 2017 Huawei Corporation.
10608 11:48:05.980317 <6>[ 2.803225] hclge is initializing
10609 11:48:05.983556 <6>[ 2.806801] e1000: Intel(R) PRO/1000 Network Driver
10610 11:48:05.990641 <6>[ 2.811929] e1000: Copyright (c) 1999-2006 Intel Corporation.
10611 11:48:05.993902 <6>[ 2.817943] e1000e: Intel(R) PRO/1000 Network Driver
10612 11:48:06.000464 <6>[ 2.823159] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10613 11:48:06.006889 <6>[ 2.829342] igb: Intel(R) Gigabit Ethernet Network Driver
10614 11:48:06.013557 <6>[ 2.834993] igb: Copyright (c) 2007-2014 Intel Corporation.
10615 11:48:06.020174 <6>[ 2.840831] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10616 11:48:06.026919 <6>[ 2.847350] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10617 11:48:06.030230 <6>[ 2.853806] sky2: driver version 1.30
10618 11:48:06.036601 <6>[ 2.858779] VFIO - User Level meta-driver version: 0.3
10619 11:48:06.044337 <6>[ 2.866964] usbcore: registered new interface driver usb-storage
10620 11:48:06.050837 <6>[ 2.873415] usbcore: registered new device driver onboard-usb-hub
10621 11:48:06.059684 <6>[ 2.882501] mt6397-rtc mt6359-rtc: registered as rtc0
10622 11:48:06.069602 <6>[ 2.887972] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:47:50 UTC (1686829670)
10623 11:48:06.072899 <6>[ 2.897547] i2c_dev: i2c /dev entries driver
10624 11:48:06.089731 <6>[ 2.909120] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10625 11:48:06.096739 <6>[ 2.919302] sdhci: Secure Digital Host Controller Interface driver
10626 11:48:06.103278 <6>[ 2.925739] sdhci: Copyright(c) Pierre Ossman
10627 11:48:06.109312 <6>[ 2.931146] Synopsys Designware Multimedia Card Interface Driver
10628 11:48:06.113189 <6>[ 2.937741] mmc0: CQHCI version 5.10
10629 11:48:06.119565 <6>[ 2.938291] sdhci-pltfm: SDHCI platform and OF driver helper
10630 11:48:06.126923 <6>[ 2.949899] ledtrig-cpu: registered to indicate activity on CPUs
10631 11:48:06.137682 <6>[ 2.957348] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 11:48:06.144118 <6>[ 2.964757] usbcore: registered new interface driver usbhid
10633 11:48:06.147828 <6>[ 2.970591] usbhid: USB HID core driver
10634 11:48:06.154180 <6>[ 2.974851] spi_master spi0: will run message pump with realtime priority
10635 11:48:06.200839 <6>[ 3.017355] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 11:48:06.220040 <6>[ 3.032561] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 11:48:06.223296 <6>[ 3.046199] mmc0: Command Queue Engine enabled
10638 11:48:06.230377 <6>[ 3.048266] cros-ec-spi spi0.0: Chrome EC device registered
10639 11:48:06.233860 <6>[ 3.050930] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10640 11:48:06.241128 <6>[ 3.064017] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 11:48:06.251139 <6>[ 3.074143] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 11:48:06.261127 <6>[ 3.074259] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10643 11:48:06.267611 <6>[ 3.080934] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10644 11:48:06.270930 <6>[ 3.091604] NET: Registered PF_PACKET protocol family
10645 11:48:06.277477 <6>[ 3.095236] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10646 11:48:06.280857 <6>[ 3.100037] 9pnet: Installing 9P2000 support
10647 11:48:06.287586 <6>[ 3.105701] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10648 11:48:06.294087 <5>[ 3.109699] Key type dns_resolver registered
10649 11:48:06.297358 <6>[ 3.121345] registered taskstats version 1
10650 11:48:06.303709 <5>[ 3.125739] Loading compiled-in X.509 certificates
10651 11:48:06.335918 <4>[ 3.152391] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 11:48:06.345974 <4>[ 3.163092] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 11:48:06.356392 <3>[ 3.176185] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10654 11:48:06.369280 <6>[ 3.192178] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10655 11:48:06.376202 <6>[ 3.198917] xhci-mtk 11200000.usb: xHCI Host Controller
10656 11:48:06.382176 <6>[ 3.204415] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10657 11:48:06.392897 <6>[ 3.212265] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10658 11:48:06.399443 <6>[ 3.221697] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10659 11:48:06.406093 <6>[ 3.227782] xhci-mtk 11200000.usb: xHCI Host Controller
10660 11:48:06.412764 <6>[ 3.233404] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10661 11:48:06.419134 <6>[ 3.241093] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10662 11:48:06.426139 <6>[ 3.248936] hub 1-0:1.0: USB hub found
10663 11:48:06.429376 <6>[ 3.252973] hub 1-0:1.0: 1 port detected
10664 11:48:06.436275 <6>[ 3.257329] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10665 11:48:06.443199 <6>[ 3.265944] hub 2-0:1.0: USB hub found
10666 11:48:06.445894 <6>[ 3.269961] hub 2-0:1.0: 1 port detected
10667 11:48:06.454013 <6>[ 3.277082] mtk-msdc 11f70000.mmc: Got CD GPIO
10668 11:48:06.471686 <6>[ 3.291231] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10669 11:48:06.478276 <6>[ 3.299285] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10670 11:48:06.488447 <4>[ 3.307260] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10671 11:48:06.498452 <6>[ 3.316932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10672 11:48:06.504603 <6>[ 3.325013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10673 11:48:06.511295 <6>[ 3.333045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10674 11:48:06.521454 <6>[ 3.340969] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10675 11:48:06.528214 <6>[ 3.348789] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10676 11:48:06.537798 <6>[ 3.356624] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10677 11:48:06.547929 <6>[ 3.367236] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10678 11:48:06.554443 <6>[ 3.375632] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10679 11:48:06.564291 <6>[ 3.383986] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10680 11:48:06.571532 <6>[ 3.392330] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10681 11:48:06.581267 <6>[ 3.400673] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10682 11:48:06.587702 <6>[ 3.409016] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10683 11:48:06.597500 <6>[ 3.417360] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10684 11:48:06.604731 <6>[ 3.425703] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10685 11:48:06.614148 <6>[ 3.434045] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10686 11:48:06.624082 <6>[ 3.442388] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10687 11:48:06.630977 <6>[ 3.450731] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10688 11:48:06.641085 <6>[ 3.459073] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10689 11:48:06.647612 <6>[ 3.467416] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10690 11:48:06.657585 <6>[ 3.475763] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10691 11:48:06.664328 <6>[ 3.484112] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10692 11:48:06.670701 <6>[ 3.493094] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10693 11:48:06.677304 <6>[ 3.500397] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10694 11:48:06.684356 <6>[ 3.507514] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10695 11:48:06.694779 <6>[ 3.514669] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10696 11:48:06.701399 <6>[ 3.522034] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10697 11:48:06.711366 <6>[ 3.528947] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10698 11:48:06.718088 <6>[ 3.538088] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10699 11:48:06.728150 <6>[ 3.547215] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10700 11:48:06.737736 <6>[ 3.556516] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10701 11:48:06.747834 <6>[ 3.565991] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10702 11:48:06.758258 <6>[ 3.575464] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10703 11:48:06.764397 <6>[ 3.584592] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10704 11:48:06.774797 <6>[ 3.594067] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10705 11:48:06.784285 <6>[ 3.603193] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10706 11:48:06.794483 <6>[ 3.612502] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10707 11:48:06.804094 <6>[ 3.622669] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10708 11:48:06.814821 <6>[ 3.634708] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10709 11:48:06.835974 <6>[ 3.655811] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10710 11:48:06.863459 <6>[ 3.686258] hub 2-1:1.0: USB hub found
10711 11:48:06.866543 <6>[ 3.690662] hub 2-1:1.0: 3 ports detected
10712 11:48:06.988024 <6>[ 3.807582] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10713 11:48:07.142420 <6>[ 3.965432] hub 1-1:1.0: USB hub found
10714 11:48:07.145775 <6>[ 3.969882] hub 1-1:1.0: 4 ports detected
10715 11:48:07.223918 <6>[ 4.043988] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10716 11:48:07.467517 <6>[ 4.287641] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10717 11:48:07.601149 <6>[ 4.424038] hub 1-1.4:1.0: USB hub found
10718 11:48:07.603938 <6>[ 4.428698] hub 1-1.4:1.0: 2 ports detected
10719 11:48:07.903664 <6>[ 4.723749] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10720 11:48:08.095617 <6>[ 4.915779] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10721 11:48:19.088346 <6>[ 15.916289] ALSA device list:
10722 11:48:19.094783 <6>[ 15.919546] No soundcards found.
10723 11:48:19.107842 <6>[ 15.931971] Freeing unused kernel memory: 8384K
10724 11:48:19.110827 <6>[ 15.936892] Run /init as init process
10725 11:48:19.140864 <6>[ 15.965378] NET: Registered PF_INET6 protocol family
10726 11:48:19.147954 <6>[ 15.971908] Segment Routing with IPv6
10727 11:48:19.151078 <6>[ 15.975897] In-situ OAM (IOAM) with IPv6
10728 11:48:19.186185 <30>[ 15.990464] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10729 11:48:19.189376 <30>[ 16.014389] systemd[1]: Detected architecture arm64.
10730 11:48:19.189504
10731 11:48:19.195901 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10732 11:48:19.196012
10733 11:48:19.211283 <30>[ 16.035952] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10734 11:48:19.363396 <30>[ 16.184526] systemd[1]: Queued start job for default target Graphical Interface.
10735 11:48:19.388375 <30>[ 16.213061] systemd[1]: Created slice system-getty.slice.
10736 11:48:19.395226 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10737 11:48:19.411783 <30>[ 16.236334] systemd[1]: Created slice system-modprobe.slice.
10738 11:48:19.418441 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10739 11:48:19.436429 <30>[ 16.260880] systemd[1]: Created slice system-serial\x2dgetty.slice.
10740 11:48:19.446313 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10741 11:48:19.459952 <30>[ 16.284249] systemd[1]: Created slice User and Session Slice.
10742 11:48:19.466170 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10743 11:48:19.487064 <30>[ 16.308307] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10744 11:48:19.496767 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10745 11:48:19.515213 <30>[ 16.336261] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10746 11:48:19.521811 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10747 11:48:19.541785 <30>[ 16.359852] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10748 11:48:19.548375 <30>[ 16.371891] systemd[1]: Reached target Local Encrypted Volumes.
10749 11:48:19.555055 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10750 11:48:19.571640 <30>[ 16.396164] systemd[1]: Reached target Paths.
10751 11:48:19.575313 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10752 11:48:19.591530 <30>[ 16.415863] systemd[1]: Reached target Remote File Systems.
10753 11:48:19.598248 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10754 11:48:19.615479 <30>[ 16.440013] systemd[1]: Reached target Slices.
10755 11:48:19.622113 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10756 11:48:19.635337 <30>[ 16.459816] systemd[1]: Reached target Swap.
10757 11:48:19.638890 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10758 11:48:19.658922 <30>[ 16.480132] systemd[1]: Listening on initctl Compatibility Named Pipe.
10759 11:48:19.665704 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10760 11:48:19.671898 <30>[ 16.494838] systemd[1]: Listening on Journal Audit Socket.
10761 11:48:19.678886 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10762 11:48:19.691532 <30>[ 16.516063] systemd[1]: Listening on Journal Socket (/dev/log).
10763 11:48:19.698081 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10764 11:48:19.716269 <30>[ 16.540534] systemd[1]: Listening on Journal Socket.
10765 11:48:19.722362 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10766 11:48:19.739023 <30>[ 16.560184] systemd[1]: Listening on Network Service Netlink Socket.
10767 11:48:19.745675 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10768 11:48:19.760229 <30>[ 16.584521] systemd[1]: Listening on udev Control Socket.
10769 11:48:19.766848 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10770 11:48:19.783720 <30>[ 16.608468] systemd[1]: Listening on udev Kernel Socket.
10771 11:48:19.790513 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10772 11:48:19.819680 <30>[ 16.644025] systemd[1]: Mounting Huge Pages File System...
10773 11:48:19.826306 Mounting [0;1;39mHuge Pages File System[0m...
10774 11:48:19.841036 <30>[ 16.665711] systemd[1]: Mounting POSIX Message Queue File System...
10775 11:48:19.848330 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10776 11:48:19.895630 <30>[ 16.719999] systemd[1]: Mounting Kernel Debug File System...
10777 11:48:19.901919 Mounting [0;1;39mKernel Debug File System[0m...
10778 11:48:19.918761 <30>[ 16.740077] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10779 11:48:19.929850 <30>[ 16.750876] systemd[1]: Starting Create list of static device nodes for the current kernel...
10780 11:48:19.936137 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10781 11:48:19.963682 <30>[ 16.788128] systemd[1]: Starting Load Kernel Module configfs...
10782 11:48:19.970458 Starting [0;1;39mLoad Kernel Module configfs[0m...
10783 11:48:19.985198 <30>[ 16.810020] systemd[1]: Starting Load Kernel Module drm...
10784 11:48:19.992011 Starting [0;1;39mLoad Kernel Module drm[0m...
10785 11:48:20.011029 <30>[ 16.832018] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10786 11:48:20.021161 <30>[ 16.845645] systemd[1]: Starting Journal Service...
10787 11:48:20.024362 Starting [0;1;39mJournal Service[0m...
10788 11:48:20.041846 <30>[ 16.866289] systemd[1]: Starting Load Kernel Modules...
10789 11:48:20.048150 Starting [0;1;39mLoad Kernel Modules[0m...
10790 11:48:20.069413 <30>[ 16.890301] systemd[1]: Starting Remount Root and Kernel File Systems...
10791 11:48:20.075994 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10792 11:48:20.090104 <30>[ 16.914298] systemd[1]: Starting Coldplug All udev Devices...
10793 11:48:20.096531 Starting [0;1;39mColdplug All udev Devices[0m...
10794 11:48:20.114709 <30>[ 16.938866] systemd[1]: Mounted Huge Pages File System.
10795 11:48:20.121180 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10796 11:48:20.135923 <30>[ 16.960240] systemd[1]: Started Journal Service.
10797 11:48:20.142233 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10798 11:48:20.156584 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10799 11:48:20.172929 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10800 11:48:20.192063 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10801 11:48:20.208978 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10802 11:48:20.225177 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10803 11:48:20.240490 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10804 11:48:20.260027 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10805 11:48:20.279170 See 'systemctl status systemd-remount-fs.service' for details.
10806 11:48:20.328667 Mounting [0;1;39mKernel Configuration File System[0m...
10807 11:48:20.349953 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10808 11:48:20.367161 <46>[ 17.188607] systemd-journald[175]: Received client request to flush runtime journal.
10809 11:48:20.376039 Starting [0;1;39mLoad/Save Random Seed[0m...
10810 11:48:20.398214 Starting [0;1;39mApply Kernel Variables[0m...
10811 11:48:20.417866 Starting [0;1;39mCreate System Users[0m...
10812 11:48:20.433845 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10813 11:48:20.459763 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10814 11:48:20.472468 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10815 11:48:20.488439 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10816 11:48:20.503881 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10817 11:48:20.520025 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10818 11:48:20.555794 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10819 11:48:20.577776 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10820 11:48:20.592073 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10821 11:48:20.611174 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10822 11:48:20.647764 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10823 11:48:20.675553 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10824 11:48:20.696089 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10825 11:48:20.716151 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10826 11:48:20.760937 Starting [0;1;39mNetwork Service[0m...
10827 11:48:20.787227 Starting [0;1;39mNetwork Time Synchronization[0m...
10828 11:48:20.806537 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10829 11:48:20.842912 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10830 11:48:20.861636 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10831 11:48:20.931215 Starting [0;1;39mNetwo<6>[ 17.752083] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10832 11:48:20.931352 rk Name Resolution[0m...
10833 11:48:20.949963 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10834 11:48:20.956257 <6>[ 17.780886] remoteproc remoteproc0: scp is available
10835 11:48:20.966724 <4>[ 17.786448] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10836 11:48:20.972888 <6>[ 17.796506] remoteproc remoteproc0: powering up scp
10837 11:48:20.982944 <4>[ 17.801709] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10838 11:48:20.990007 <3>[ 17.811554] remoteproc remoteproc0: request_firmware failed: -2
10839 11:48:20.996214 <3>[ 17.817988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 11:48:21.006389 [[0;32m OK [<3>[ 17.826283] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10841 11:48:21.016044 0m] Found device<6>[ 17.831855] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10842 11:48:21.022847 <3>[ 17.835823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10843 11:48:21.032991 <6>[ 17.844686] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10844 11:48:21.042885 [0;1;39m/dev/t<6>[ 17.861491] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10845 11:48:21.043059 tyS0[0m.
10846 11:48:21.052458 <3>[ 17.863080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10847 11:48:21.058923 <6>[ 17.863345] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10848 11:48:21.065832 <3>[ 17.888247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 11:48:21.076032 <3>[ 17.896407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10850 11:48:21.082790 <4>[ 17.897568] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10851 11:48:21.089349 <4>[ 17.897568] Fallback method does not support PEC.
10852 11:48:21.095791 <3>[ 17.904769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10853 11:48:21.102826 <6>[ 17.921263] mc: Linux media interface: v0.10
10854 11:48:21.106705 <6>[ 17.921287] usbcore: registered new interface driver r8152
10855 11:48:21.116131 <3>[ 17.926363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 11:48:21.122784 <3>[ 17.937560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 11:48:21.129374 <4>[ 17.945461] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10858 11:48:21.140217 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10859 11:48:21.150482 <3>[ 17.970307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 11:48:21.157199 <4>[ 17.970354] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10861 11:48:21.163332 <3>[ 17.979385] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 11:48:21.170382 <6>[ 17.993212] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10863 11:48:21.180198 <3>[ 17.994494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 11:48:21.190252 <6>[ 18.000386] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10865 11:48:21.196635 <6>[ 18.000874] pci_bus 0000:00: root bus resource [bus 00-ff]
10866 11:48:21.203559 <6>[ 18.010533] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10867 11:48:21.209861 <6>[ 18.012707] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10868 11:48:21.220111 <3>[ 18.013750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10869 11:48:21.226474 <3>[ 18.013856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 11:48:21.236493 <3>[ 18.013865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10871 11:48:21.243200 <3>[ 18.013872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 11:48:21.253312 <3>[ 18.013882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 11:48:21.259359 <3>[ 18.013889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 11:48:21.269465 <3>[ 18.013936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 11:48:21.275970 <6>[ 18.019644] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10876 11:48:21.282926 <6>[ 18.051873] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10877 11:48:21.292540 <6>[ 18.057514] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10878 11:48:21.299676 <6>[ 18.094637] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10879 11:48:21.306225 <6>[ 18.097805] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10880 11:48:21.312485 <6>[ 18.131269] usbcore: registered new interface driver cdc_ether
10881 11:48:21.319632 <6>[ 18.137235] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10882 11:48:21.325983 <6>[ 18.138194] videodev: Linux video capture interface: v2.00
10883 11:48:21.333375 <6>[ 18.143405] r8152 2-1.3:1.0 eth0: v1.12.13
10884 11:48:21.335867 <6>[ 18.151834] pci 0000:00:00.0: supports D1 D2
10885 11:48:21.342635 <6>[ 18.152344] usbcore: registered new interface driver r8153_ecm
10886 11:48:21.349124 <3>[ 18.157807] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 11:48:21.355844 <6>[ 18.158143] Bluetooth: Core ver 2.22
10888 11:48:21.359224 <6>[ 18.158254] NET: Registered PF_BLUETOOTH protocol family
10889 11:48:21.365986 <6>[ 18.158259] Bluetooth: HCI device and connection manager initialized
10890 11:48:21.372618 <6>[ 18.158279] Bluetooth: HCI socket layer initialized
10891 11:48:21.375781 <6>[ 18.158288] Bluetooth: L2CAP socket layer initialized
10892 11:48:21.382303 <6>[ 18.158337] Bluetooth: SCO socket layer initialized
10893 11:48:21.390192 <3>[ 18.160084] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10894 11:48:21.397778 <6>[ 18.160996] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10895 11:48:21.405385 <6>[ 18.171834] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10896 11:48:21.411840 <6>[ 18.182333] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10897 11:48:21.418877 <6>[ 18.184470] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10898 11:48:21.425295 <6>[ 18.185702] usbcore: registered new interface driver btusb
10899 11:48:21.435232 <4>[ 18.186219] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10900 11:48:21.442177 <3>[ 18.186229] Bluetooth: hci0: Failed to load firmware file (-2)
10901 11:48:21.448145 <3>[ 18.186233] Bluetooth: hci0: Failed to set up firmware (-2)
10902 11:48:21.458902 <4>[ 18.186236] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10903 11:48:21.463167 <6>[ 18.189967] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10904 11:48:21.477099 <6>[ 18.197807] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10905 11:48:21.483270 <6>[ 18.201587] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10906 11:48:21.489915 <6>[ 18.202263] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10907 11:48:21.496491 <6>[ 18.206220] remoteproc remoteproc0: powering up scp
10908 11:48:21.503284 <4>[ 18.206272] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10909 11:48:21.511348 <3>[ 18.206280] remoteproc remoteproc0: request_firmware failed: -2
10910 11:48:21.517853 <3>[ 18.206283] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10911 11:48:21.524179 <6>[ 18.207180] usbcore: registered new interface driver uvcvideo
10912 11:48:21.531704 <6>[ 18.212012] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10913 11:48:21.541086 <3>[ 18.225888] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10914 11:48:21.548152 <6>[ 18.227136] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10915 11:48:21.558729 <3>[ 18.240230] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:48:21.562023 <6>[ 18.241569] pci 0000:01:00.0: supports D1 D2
10917 11:48:21.572160 <3>[ 18.301361] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 11:48:21.578881 <3>[ 18.302114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10919 11:48:21.585406 <6>[ 18.305746] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10920 11:48:21.592459 <6>[ 18.315629] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10921 11:48:21.602504 <3>[ 18.343576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 11:48:21.613128 <3>[ 18.344395] power_supply sbs-5-000b: driver failed to report `constant_charge_voltage_max' property: -6
10923 11:48:21.620065 <6>[ 18.348482] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10924 11:48:21.627176 <3>[ 18.358129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:48:21.636919 <6>[ 18.361936] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10926 11:48:21.644494 <6>[ 18.361954] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10927 11:48:21.650785 <6>[ 18.474018] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10928 11:48:21.661664 <6>[ 18.482033] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10929 11:48:21.664943 <6>[ 18.490044] pci 0000:00:00.0: PCI bridge to [bus 01]
10930 11:48:21.674839 [[0;32m OK [<6>[ 18.495267] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10931 11:48:21.681611 0m] Reached targ<6>[ 18.504879] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10932 11:48:21.691485 et [0;1;39mSyst<6>[ 18.513329] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10933 11:48:21.698107 em Time Set[0m.<6>[ 18.520433] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10934 11:48:21.698264
10935 11:48:21.717885 <5>[ 18.538775] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10936 11:48:21.723906 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10937 11:48:21.737228 <5>[ 18.558860] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10938 11:48:21.743744 <4>[ 18.565823] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10939 11:48:21.750654 <6>[ 18.574718] cfg80211: failed to load regulatory.db
10940 11:48:21.779851 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10941 11:48:21.799720 <6>[ 18.620864] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10942 11:48:21.806400 <6>[ 18.628444] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10943 11:48:21.809074 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10944 11:48:21.832032 [[0;32m OK [0m] Finished [0<6>[ 18.655300] mt7921e 0000:01:00.0: ASIC revision: 79610010
10945 11:48:21.838215 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10946 11:48:21.937564 <4>[ 18.755513] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10947 11:48:22.012943 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10948 11:48:22.027282 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10949 11:48:22.057849 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Nam<4>[ 18.874962] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10950 11:48:22.058004 e Lookups[0m.
10951 11:48:22.072475 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10952 11:48:22.090916 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10953 11:48:22.106947 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10954 11:48:22.119465 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10955 11:48:22.138720 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10956 11:48:22.151372 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10957 11:48:22.177773 [[0;32m OK [0m] Reached targ<4>[ 18.994237] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 11:48:22.181218 et [0;1;39mBasic System[0m.
10959 11:48:22.200112 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10960 11:48:22.255422 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10961 11:48:22.298696 Starting [0;1;39mUser <4>[ 19.115367] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10962 11:48:22.298843 Login Management[0m...
10963 11:48:22.320422 Starting [0;1;39mPermit User Sessions[0m...
10964 11:48:22.336524 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10965 11:48:22.353754 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10966 11:48:22.370124 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10967 11:48:22.387809 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10968 11:48:22.420689 Startin<4>[ 19.238896] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 11:48:22.427124 g [0;1;39mLoad/Save RF Kill Switch Status[0m...
10970 11:48:22.444377 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10971 11:48:22.460437 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10972 11:48:22.476067 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10973 11:48:22.491158 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10974 11:48:22.540049 <4>[ 19.358269] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 11:48:22.546588 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10976 11:48:22.577747 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10977 11:48:22.593350
10978 11:48:22.593486
10979 11:48:22.596671 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10980 11:48:22.596764
10981 11:48:22.599850 debian-bullseye-arm64 login: root (automatic login)
10982 11:48:22.599934
10983 11:48:22.600000
10984 11:48:22.617081 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
10985 11:48:22.617202
10986 11:48:22.624075 The programs included with the Debian GNU/Linux system are free software;
10987 11:48:22.630530 the exact distribution terms for each program are described in the
10988 11:48:22.633719 individual files in /usr/share/doc/*/copyright.
10989 11:48:22.633835
10990 11:48:22.640453 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10991 11:48:22.640562 permitted by applicable law.
10992 11:48:22.644129 Matched prompt #10: / #
10994 11:48:22.644423 Setting prompt string to ['/ #']
10995 11:48:22.644549 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10997 11:48:22.644859 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10998 11:48:22.644956 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10999 11:48:22.645045 Setting prompt string to ['/ #']
11000 11:48:22.645109 Forcing a shell prompt, looking for ['/ #']
11002 11:48:22.695330 / #
11003 11:48:22.695513 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11004 11:48:22.695623 Waiting using forced prompt support (timeout 00:02:30)
11005 11:48:22.695764 <4>[ 19.482272] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 11:48:22.700280
11007 11:48:22.700585 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11008 11:48:22.700708 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
11009 11:48:22.700837 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11010 11:48:22.700928 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
11011 11:48:22.701013 end: 2 depthcharge-action (duration 00:01:35) [common]
11012 11:48:22.701099 start: 3 lava-test-retry (timeout 00:05:00) [common]
11013 11:48:22.701191 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11014 11:48:22.701263 Using namespace: common
11016 11:48:22.801550 / # #
11017 11:48:22.801752 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11018 11:48:22.801909 #<4>[ 19.601748] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 11:48:22.806786
11020 11:48:22.807048 Using /lava-10742264
11022 11:48:22.907338 / # export SHELL=/bin/sh
11023 11:48:22.907540 export SHELL=/bin/sh<4>[ 19.721582] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11024 11:48:22.912455
11026 11:48:23.012938 / # . /lava-10742264/environment
11027 11:48:23.013135 <6>[ 19.765662] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11028 11:48:23.013213 <6>[ 19.773585] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11029 11:48:23.023534 . /lava-10742264/environment<4>[ 19.841796] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11030 11:48:23.023672
11032 11:48:23.128252 / # /lava-10742264/bin/lava-test-runner /lava-10742264/0
11033 11:48:23.128446 Test shell timeout: 10s (minimum of the action and connection timeout)
11034 11:48:23.135138 /lava-10742264/bin/lava-test-runner /lava-10742264/0<3>[ 19.960131] mt7921e 0000:01:00.0: hardware init failed
11035 11:48:23.135225
11036 11:48:23.157496 + export TESTRUN_ID=0_cros-ec
11037 11:48:23.164607 +<8>[ 19.987907] <LAVA_SIGNAL_STARTRUN 0_cros-ec 10742264_1.5.2.3.1>
11038 11:48:23.164912 Received signal: <STARTRUN> 0_cros-ec 10742264_1.5.2.3.1
11039 11:48:23.165034 Starting test lava.0_cros-ec (10742264_1.5.2.3.1)
11040 11:48:23.165156 Skipping test definition patterns.
11041 11:48:23.167798 cd /lava-10742264/0/tests/0_cros-ec
11042 11:48:23.171050 + cat uuid
11043 11:48:23.171132 + UUID=10742264_1.5.2.3.1
11044 11:48:23.171200 + set +x
11045 11:48:23.177848 + python3 -m cros.runners.lava_runner -v
11046 11:48:23.880052 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11047 11:48:23.887348 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11048 11:48:23.890679
11049 11:48:23.893983 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11051 11:48:23.897012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11052 11:48:23.903763 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11053 11:48:23.910187 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11054 11:48:23.910301
11055 11:48:23.920000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11056 11:48:23.920289 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11058 11:48:23.927082 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11059 11:48:23.933787 Checks the cros-ec gyros<8>[ 20.756145] <LAVA_SIGNAL_ENDRUN 0_cros-ec 10742264_1.5.2.3.1>
11060 11:48:23.934082 Received signal: <ENDRUN> 0_cros-ec 10742264_1.5.2.3.1
11061 11:48:23.934199 Ending use of test pattern.
11062 11:48:23.934297 Ending test lava.0_cros-ec (10742264_1.5.2.3.1), duration 0.77
11064 11:48:23.937123 cope IIO ABI. ... skipped 'No cros-ec-gyro found'
11065 11:48:23.937229
11066 11:48:23.943086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11067 11:48:23.943368 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11069 11:48:23.950451 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11070 11:48:23.956485 Checks the standard ABI for the main Embedded Controller. ... ok
11071 11:48:23.956592
11072 11:48:23.959815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11073 11:48:23.960088 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11075 11:48:23.966747 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11076 11:48:23.973431 Checks the main Embedded controller character device. ... ok
11077 11:48:23.973514
11078 11:48:23.976863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11079 11:48:23.977143 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11081 11:48:23.982980 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11082 11:48:23.989677 Checks basic comunication with the main Embedded controller. ... ok
11083 11:48:23.989782
11084 11:48:23.996798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11085 11:48:23.997057 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11087 11:48:23.999993 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11088 11:48:24.006623 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11089 11:48:24.006733
11090 11:48:24.013042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11091 11:48:24.013361 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11093 11:48:24.019795 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11094 11:48:24.026220 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11095 11:48:24.026305
11096 11:48:24.033088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11097 11:48:24.033368 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11099 11:48:24.039482 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11100 11:48:24.045947 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11101 11:48:24.046031
11102 11:48:24.049396 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11104 11:48:24.052650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11105 11:48:24.055934 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11106 11:48:24.062759 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11107 11:48:24.066331
11108 11:48:24.069474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11109 11:48:24.069723 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11111 11:48:24.075710 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11112 11:48:24.082175 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11113 11:48:24.082276
11114 11:48:24.088939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11115 11:48:24.089188 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11117 11:48:24.095617 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11118 11:48:24.102042 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11119 11:48:24.102149
11120 11:48:24.109380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11121 11:48:24.109652 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11123 11:48:24.112345 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11124 11:48:24.122115 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11125 11:48:24.122232
11126 11:48:24.128858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11127 11:48:24.129118 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11129 11:48:24.132039 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11130 11:48:24.141709 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11131 11:48:24.141821
11132 11:48:24.148657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11133 11:48:24.148937 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11135 11:48:24.155385 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11136 11:48:24.158846 Check the cros battery ABI. ... skipped 'No BAT found'
11137 11:48:24.158951
11138 11:48:24.165003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11139 11:48:24.165297 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11141 11:48:24.171930 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11142 11:48:24.178731 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11143 11:48:24.178832
11144 11:48:24.185346 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11146 11:48:24.188665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11147 11:48:24.191388 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11148 11:48:24.198063 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11149 11:48:24.198164
11150 11:48:24.205236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11151 11:48:24.205516 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11153 11:48:24.211692 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11154 11:48:24.218388 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11155 11:48:24.218502
11156 11:48:24.224823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11157 11:48:24.224905
11158 11:48:24.225154 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11160 11:48:24.231539 ----------------------------------------------------------------------
11161 11:48:24.231647 Ran 18 tests in 0.011s
11162 11:48:24.235036
11163 11:48:24.235135 OK (skipped=15)
11164 11:48:24.235227 + set +x
11165 11:48:24.238209 <LAVA_TEST_RUNNER EXIT>
11166 11:48:24.238465 ok: lava_test_shell seems to have completed
11167 11:48:24.238644 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11168 11:48:24.238743 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11169 11:48:24.238829 end: 3 lava-test-retry (duration 00:00:02) [common]
11170 11:48:24.238915 start: 4 finalize (timeout 00:07:56) [common]
11171 11:48:24.239007 start: 4.1 power-off (timeout 00:00:30) [common]
11172 11:48:24.239162 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11173 11:48:24.320951 >> Command sent successfully.
11174 11:48:24.323299 Returned 0 in 0 seconds
11175 11:48:24.423705 end: 4.1 power-off (duration 00:00:00) [common]
11177 11:48:24.424073 start: 4.2 read-feedback (timeout 00:07:56) [common]
11178 11:48:24.424348 Listened to connection for namespace 'common' for up to 1s
11179 11:48:25.424867 Finalising connection for namespace 'common'
11180 11:48:25.425064 Disconnecting from shell: Finalise
11181 11:48:25.425171 / #
11182 11:48:25.525500 end: 4.2 read-feedback (duration 00:00:01) [common]
11183 11:48:25.525698 end: 4 finalize (duration 00:00:01) [common]
11184 11:48:25.525847 Cleaning after the job
11185 11:48:25.525973 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/ramdisk
11186 11:48:25.530778 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/kernel
11187 11:48:25.536528 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/dtb
11188 11:48:25.536723 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742264/tftp-deploy-jijrys3y/modules
11189 11:48:25.541718 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742264
11190 11:48:25.640950 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742264
11191 11:48:25.641138 Job finished correctly