Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
1 11:43:51.865032 lava-dispatcher, installed at version: 2023.05.1
2 11:43:51.865290 start: 0 validate
3 11:43:51.865464 Start time: 2023-06-15 11:43:51.865456+00:00 (UTC)
4 11:43:51.865648 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:43:51.865847 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 11:43:52.125959 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:43:52.126150 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:43:52.392269 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:43:52.392461 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:43:52.643020 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:43:52.643204 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:43:53.123226 validate duration: 1.26
14 11:43:53.123485 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:43:53.123586 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:43:53.123672 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:43:53.123798 Not decompressing ramdisk as can be used compressed.
18 11:43:53.123882 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230609.0/arm64/rootfs.cpio.gz
19 11:43:53.123948 saving as /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/ramdisk/rootfs.cpio.gz
20 11:43:53.124011 total size: 43386660 (41MB)
21 11:43:53.125093 progress 0% (0MB)
22 11:43:53.153767 progress 5% (2MB)
23 11:43:53.188497 progress 10% (4MB)
24 11:43:53.213184 progress 15% (6MB)
25 11:43:53.242160 progress 20% (8MB)
26 11:43:53.281273 progress 25% (10MB)
27 11:43:53.329275 progress 30% (12MB)
28 11:43:53.358108 progress 35% (14MB)
29 11:43:53.396852 progress 40% (16MB)
30 11:43:53.431522 progress 45% (18MB)
31 11:43:53.470239 progress 50% (20MB)
32 11:43:53.508928 progress 55% (22MB)
33 11:43:53.533613 progress 60% (24MB)
34 11:43:53.559100 progress 65% (26MB)
35 11:43:53.590000 progress 70% (28MB)
36 11:43:53.619740 progress 75% (31MB)
37 11:43:53.650403 progress 80% (33MB)
38 11:43:53.685078 progress 85% (35MB)
39 11:43:53.715513 progress 90% (37MB)
40 11:43:53.742233 progress 95% (39MB)
41 11:43:53.773129 progress 100% (41MB)
42 11:43:53.773300 41MB downloaded in 0.65s (63.73MB/s)
43 11:43:53.773459 end: 1.1.1 http-download (duration 00:00:01) [common]
45 11:43:53.773697 end: 1.1 download-retry (duration 00:00:01) [common]
46 11:43:53.773783 start: 1.2 download-retry (timeout 00:09:59) [common]
47 11:43:53.773953 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 11:43:53.774108 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:43:53.774184 saving as /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/kernel/Image
50 11:43:53.774248 total size: 47581696 (45MB)
51 11:43:53.774350 No compression specified
52 11:43:53.775480 progress 0% (0MB)
53 11:43:53.808842 progress 5% (2MB)
54 11:43:53.836522 progress 10% (4MB)
55 11:43:53.868156 progress 15% (6MB)
56 11:43:53.881504 progress 20% (9MB)
57 11:43:53.911983 progress 25% (11MB)
58 11:43:53.949358 progress 30% (13MB)
59 11:43:53.963313 progress 35% (15MB)
60 11:43:53.991080 progress 40% (18MB)
61 11:43:54.024979 progress 45% (20MB)
62 11:43:54.037769 progress 50% (22MB)
63 11:43:54.063278 progress 55% (24MB)
64 11:43:54.092405 progress 60% (27MB)
65 11:43:54.105203 progress 65% (29MB)
66 11:43:54.137476 progress 70% (31MB)
67 11:43:54.167172 progress 75% (34MB)
68 11:43:54.179370 progress 80% (36MB)
69 11:43:54.204714 progress 85% (38MB)
70 11:43:54.234282 progress 90% (40MB)
71 11:43:54.246306 progress 95% (43MB)
72 11:43:54.280084 progress 100% (45MB)
73 11:43:54.280253 45MB downloaded in 0.51s (89.68MB/s)
74 11:43:54.280407 end: 1.2.1 http-download (duration 00:00:01) [common]
76 11:43:54.280706 end: 1.2 download-retry (duration 00:00:01) [common]
77 11:43:54.280798 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:43:54.280890 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:43:54.281021 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:43:54.281099 saving as /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/dtb/mt8192-asurada-spherion-r0.dtb
81 11:43:54.281169 total size: 46924 (0MB)
82 11:43:54.281247 No compression specified
83 11:43:54.282464 progress 69% (0MB)
84 11:43:54.282736 progress 100% (0MB)
85 11:43:54.282891 0MB downloaded in 0.00s (26.01MB/s)
86 11:43:54.283013 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:43:54.283239 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:43:54.283325 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:43:54.283409 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:43:54.283523 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:43:54.283593 saving as /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/modules/modules.tar
93 11:43:54.283654 total size: 8555256 (8MB)
94 11:43:54.283715 Using unxz to decompress xz
95 11:43:54.287400 progress 0% (0MB)
96 11:43:54.312373 progress 5% (0MB)
97 11:43:54.342114 progress 10% (0MB)
98 11:43:54.371288 progress 15% (1MB)
99 11:43:54.400478 progress 20% (1MB)
100 11:43:54.427294 progress 25% (2MB)
101 11:43:54.451778 progress 30% (2MB)
102 11:43:54.478551 progress 35% (2MB)
103 11:43:54.505155 progress 40% (3MB)
104 11:43:54.530443 progress 45% (3MB)
105 11:43:54.559997 progress 50% (4MB)
106 11:43:54.586700 progress 55% (4MB)
107 11:43:54.614134 progress 60% (4MB)
108 11:43:54.641540 progress 65% (5MB)
109 11:43:54.668827 progress 70% (5MB)
110 11:43:54.695360 progress 75% (6MB)
111 11:43:54.720114 progress 80% (6MB)
112 11:43:54.745821 progress 85% (6MB)
113 11:43:54.777253 progress 90% (7MB)
114 11:43:54.807499 progress 95% (7MB)
115 11:43:54.835095 progress 100% (8MB)
116 11:43:54.840085 8MB downloaded in 0.56s (14.66MB/s)
117 11:43:54.840439 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:43:54.840851 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:43:54.840979 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 11:43:54.841106 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 11:43:54.841224 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:43:54.841345 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 11:43:54.841619 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb
125 11:43:54.841789 makedir: /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin
126 11:43:54.841925 makedir: /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/tests
127 11:43:54.842055 makedir: /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/results
128 11:43:54.842198 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-add-keys
129 11:43:54.842377 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-add-sources
130 11:43:54.842547 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-background-process-start
131 11:43:54.842730 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-background-process-stop
132 11:43:54.842888 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-common-functions
133 11:43:54.843066 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-echo-ipv4
134 11:43:54.843237 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-install-packages
135 11:43:54.843393 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-installed-packages
136 11:43:54.843547 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-os-build
137 11:43:54.843702 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-probe-channel
138 11:43:54.843858 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-probe-ip
139 11:43:54.844017 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-target-ip
140 11:43:54.844184 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-target-mac
141 11:43:54.844338 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-target-storage
142 11:43:54.844495 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-test-case
143 11:43:54.844650 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-test-event
144 11:43:54.844802 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-test-feedback
145 11:43:54.844945 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-test-raise
146 11:43:54.845069 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-test-reference
147 11:43:54.845191 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-test-runner
148 11:43:54.845312 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-test-set
149 11:43:54.845435 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-test-shell
150 11:43:54.845560 Updating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-install-packages (oe)
151 11:43:54.850666 Updating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/bin/lava-installed-packages (oe)
152 11:43:54.850811 Creating /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/environment
153 11:43:54.850918 LAVA metadata
154 11:43:54.850996 - LAVA_JOB_ID=10742252
155 11:43:54.851066 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:43:54.851175 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 11:43:54.851245 skipped lava-vland-overlay
158 11:43:54.851322 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:43:54.851406 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 11:43:54.851470 skipped lava-multinode-overlay
161 11:43:54.851549 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:43:54.851635 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 11:43:54.851711 Loading test definitions
164 11:43:54.851804 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:58) [common]
165 11:43:54.851882 Using /lava-10742252 at stage 0
166 11:43:54.852355 uuid=10742252_1.5.2.3.1 testdef=None
167 11:43:54.852526 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:43:54.852707 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
169 11:43:54.853700 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:43:54.854219 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
172 11:43:54.855246 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:43:54.855624 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
175 11:43:54.904409 runner path: /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/0/tests/0_igt-gpu-panfrost test_uuid 10742252_1.5.2.3.1
176 11:43:54.904618 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:43:54.904840 Creating lava-test-runner.conf files
179 11:43:54.904906 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742252/lava-overlay-8umcu4sb/lava-10742252/0 for stage 0
180 11:43:54.905000 - 0_igt-gpu-panfrost
181 11:43:54.905100 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:43:54.905187 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
183 11:43:54.913308 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:43:54.913452 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
185 11:43:54.913546 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:43:54.913638 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:43:54.913732 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
188 11:43:56.793918 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 11:43:56.794318 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
190 11:43:56.794465 extracting modules file /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742252/extract-overlay-ramdisk-m7cbg1oh/ramdisk
191 11:43:57.069865 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:43:57.070071 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 11:43:57.070197 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742252/compress-overlay-gfpjcz01/overlay-1.5.2.4.tar.gz to ramdisk
194 11:43:57.070300 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742252/compress-overlay-gfpjcz01/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742252/extract-overlay-ramdisk-m7cbg1oh/ramdisk
195 11:43:57.078726 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:43:57.078906 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 11:43:57.079031 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:43:57.079153 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 11:43:57.079267 Building ramdisk /var/lib/lava/dispatcher/tmp/10742252/extract-overlay-ramdisk-m7cbg1oh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742252/extract-overlay-ramdisk-m7cbg1oh/ramdisk
200 11:43:58.779922 >> 369088 blocks
201 11:44:04.674268 rename /var/lib/lava/dispatcher/tmp/10742252/extract-overlay-ramdisk-m7cbg1oh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/ramdisk/ramdisk.cpio.gz
202 11:44:04.674712 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 11:44:04.674874 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
204 11:44:04.675006 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
205 11:44:04.675150 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/kernel/Image'
206 11:44:17.887124 Returned 0 in 13 seconds
207 11:44:17.987714 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/kernel/image.itb
208 11:44:18.756356 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:44:18.756717 output: Created: Thu Jun 15 12:44:18 2023
210 11:44:18.756814 output: Image 0 (kernel-1)
211 11:44:18.756913 output: Description:
212 11:44:18.757007 output: Created: Thu Jun 15 12:44:18 2023
213 11:44:18.757084 output: Type: Kernel Image
214 11:44:18.757175 output: Compression: lzma compressed
215 11:44:18.757272 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
216 11:44:18.757368 output: Architecture: AArch64
217 11:44:18.757433 output: OS: Linux
218 11:44:18.757492 output: Load Address: 0x00000000
219 11:44:18.757549 output: Entry Point: 0x00000000
220 11:44:18.757605 output: Hash algo: crc32
221 11:44:18.757661 output: Hash value: cd22d0e5
222 11:44:18.757728 output: Image 1 (fdt-1)
223 11:44:18.757815 output: Description: mt8192-asurada-spherion-r0
224 11:44:18.757899 output: Created: Thu Jun 15 12:44:18 2023
225 11:44:18.757983 output: Type: Flat Device Tree
226 11:44:18.758066 output: Compression: uncompressed
227 11:44:18.758150 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:44:18.758237 output: Architecture: AArch64
229 11:44:18.758322 output: Hash algo: crc32
230 11:44:18.758405 output: Hash value: 1df858fa
231 11:44:18.758489 output: Image 2 (ramdisk-1)
232 11:44:18.758572 output: Description: unavailable
233 11:44:18.758656 output: Created: Thu Jun 15 12:44:18 2023
234 11:44:18.758743 output: Type: RAMDisk Image
235 11:44:18.758827 output: Compression: Unknown Compression
236 11:44:18.758910 output: Data Size: 56373404 Bytes = 55052.15 KiB = 53.76 MiB
237 11:44:18.758994 output: Architecture: AArch64
238 11:44:18.759077 output: OS: Linux
239 11:44:18.759203 output: Load Address: unavailable
240 11:44:18.759277 output: Entry Point: unavailable
241 11:44:18.759331 output: Hash algo: crc32
242 11:44:18.759411 output: Hash value: 7e4ed679
243 11:44:18.759490 output: Default Configuration: 'conf-1'
244 11:44:18.759544 output: Configuration 0 (conf-1)
245 11:44:18.759597 output: Description: mt8192-asurada-spherion-r0
246 11:44:18.759650 output: Kernel: kernel-1
247 11:44:18.759703 output: Init Ramdisk: ramdisk-1
248 11:44:18.759788 output: FDT: fdt-1
249 11:44:18.759872 output: Loadables: kernel-1
250 11:44:18.759955 output:
251 11:44:18.760241 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:44:18.760373 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:44:18.760478 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 11:44:18.760603 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 11:44:18.760681 No LXC device requested
256 11:44:18.760800 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:44:18.760912 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 11:44:18.760988 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:44:18.761061 Checking files for TFTP limit of 4294967296 bytes.
260 11:44:18.761818 end: 1 tftp-deploy (duration 00:00:26) [common]
261 11:44:18.761963 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:44:18.762090 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:44:18.762286 substitutions:
264 11:44:18.762383 - {DTB}: 10742252/tftp-deploy-48ix2pz_/dtb/mt8192-asurada-spherion-r0.dtb
265 11:44:18.762479 - {INITRD}: 10742252/tftp-deploy-48ix2pz_/ramdisk/ramdisk.cpio.gz
266 11:44:18.762569 - {KERNEL}: 10742252/tftp-deploy-48ix2pz_/kernel/Image
267 11:44:18.762657 - {LAVA_MAC}: None
268 11:44:18.762748 - {PRESEED_CONFIG}: None
269 11:44:18.762836 - {PRESEED_LOCAL}: None
270 11:44:18.762922 - {RAMDISK}: 10742252/tftp-deploy-48ix2pz_/ramdisk/ramdisk.cpio.gz
271 11:44:18.763008 - {ROOT_PART}: None
272 11:44:18.763107 - {ROOT}: None
273 11:44:18.763191 - {SERVER_IP}: 192.168.201.1
274 11:44:18.763266 - {TEE}: None
275 11:44:18.763323 Parsed boot commands:
276 11:44:18.763377 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:44:18.763544 Parsed boot commands: tftpboot 192.168.201.1 10742252/tftp-deploy-48ix2pz_/kernel/image.itb 10742252/tftp-deploy-48ix2pz_/kernel/cmdline
278 11:44:18.763631 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:44:18.763733 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:44:18.763858 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:44:18.763974 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:44:18.764092 Not connected, no need to disconnect.
283 11:44:18.764231 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:44:18.764316 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:44:18.764382 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
286 11:44:18.767898 Setting prompt string to ['lava-test: # ']
287 11:44:18.768275 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:44:18.768392 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:44:18.768491 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:44:18.768585 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:44:18.768778 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 11:44:23.901768 >> Command sent successfully.
293 11:44:23.904611 Returned 0 in 5 seconds
294 11:44:24.004999 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:44:24.005587 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:44:24.005688 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:44:24.005777 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:44:24.005847 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:44:24.005917 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:44:24.006163 [Enter `^Ec?' for help]
302 11:44:24.177434
303 11:44:24.177610
304 11:44:24.177736 F0: 102B 0000
305 11:44:24.177801
306 11:44:24.177861 F3: 1001 0000 [0200]
307 11:44:24.177921
308 11:44:24.180609 F3: 1001 0000
309 11:44:24.180693
310 11:44:24.180759 F7: 102D 0000
311 11:44:24.180821
312 11:44:24.180880 F1: 0000 0000
313 11:44:24.184628
314 11:44:24.184712 V0: 0000 0000 [0001]
315 11:44:24.184782
316 11:44:24.184843 00: 0007 8000
317 11:44:24.184907
318 11:44:24.187910 01: 0000 0000
319 11:44:24.187997
320 11:44:24.188088 BP: 0C00 0209 [0000]
321 11:44:24.188152
322 11:44:24.191122 G0: 1182 0000
323 11:44:24.191340
324 11:44:24.191473 EC: 0000 0021 [4000]
325 11:44:24.191572
326 11:44:24.194998 S7: 0000 0000 [0000]
327 11:44:24.195112
328 11:44:24.195208 CC: 0000 0000 [0001]
329 11:44:24.195306
330 11:44:24.198258 T0: 0000 0040 [010F]
331 11:44:24.198364
332 11:44:24.198460 Jump to BL
333 11:44:24.198551
334 11:44:24.223822
335 11:44:24.223955
336 11:44:24.224073
337 11:44:24.230812 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:44:24.235197 ARM64: Exception handlers installed.
339 11:44:24.238355 ARM64: Testing exception
340 11:44:24.242076 ARM64: Done test exception
341 11:44:24.249181 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:44:24.256972 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:44:24.264016 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:44:24.274187 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:44:24.280823 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:44:24.291658 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:44:24.302126 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:44:24.308515 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:44:24.326659 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:44:24.329819 WDT: Last reset was cold boot
351 11:44:24.332971 SPI1(PAD0) initialized at 2873684 Hz
352 11:44:24.336349 SPI5(PAD0) initialized at 992727 Hz
353 11:44:24.340060 VBOOT: Loading verstage.
354 11:44:24.346298 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:44:24.349591 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:44:24.353615 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:44:24.356156 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:44:24.364064 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:44:24.370529 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:44:24.381336 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
361 11:44:24.381434
362 11:44:24.381540
363 11:44:24.391773 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:44:24.394995 ARM64: Exception handlers installed.
365 11:44:24.398199 ARM64: Testing exception
366 11:44:24.398288 ARM64: Done test exception
367 11:44:24.405332 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:44:24.408508 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:44:24.422420 Probing TPM: . done!
370 11:44:24.422518 TPM ready after 0 ms
371 11:44:24.429285 Connected to device vid:did:rid of 1ae0:0028:00
372 11:44:24.436312 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 11:44:24.495077 Initialized TPM device CR50 revision 0
374 11:44:24.506314 tlcl_send_startup: Startup return code is 0
375 11:44:24.506415 TPM: setup succeeded
376 11:44:24.518232 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:44:24.527061 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:44:24.538068 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:44:24.547760 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:44:24.550962 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:44:24.558832 in-header: 03 07 00 00 08 00 00 00
382 11:44:24.562887 in-data: aa e4 47 04 13 02 00 00
383 11:44:24.566148 Chrome EC: UHEPI supported
384 11:44:24.573747 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:44:24.577722 in-header: 03 95 00 00 08 00 00 00
386 11:44:24.580749 in-data: 18 20 20 08 00 00 00 00
387 11:44:24.580831 Phase 1
388 11:44:24.584568 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:44:24.592195 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:44:24.595488 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:44:24.599477 Recovery requested (1009000e)
392 11:44:24.607637 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:44:24.612944 tlcl_extend: response is 0
394 11:44:24.622603 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:44:24.628056 tlcl_extend: response is 0
396 11:44:24.634919 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:44:24.654667 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 11:44:24.661647 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:44:24.661766
400 11:44:24.661852
401 11:44:24.671897 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:44:24.675150 ARM64: Exception handlers installed.
403 11:44:24.678350 ARM64: Testing exception
404 11:44:24.678450 ARM64: Done test exception
405 11:44:24.700273 pmic_efuse_setting: Set efuses in 11 msecs
406 11:44:24.703545 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:44:24.710243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:44:24.713559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:44:24.720427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:44:24.724239 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:44:24.727891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:44:24.735264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:44:24.738942 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:44:24.742417 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:44:24.746006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:44:24.753315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:44:24.757028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:44:24.761492 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:44:24.764563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:44:24.772201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:44:24.779734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:44:24.782869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:44:24.790279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:44:24.794009 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:44:24.801287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:44:24.805071 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:44:24.812143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:44:24.815923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:44:24.822860 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:44:24.830369 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:44:24.834055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:44:24.841397 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:44:24.844474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:44:24.848755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:44:24.855404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:44:24.859786 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:44:24.862934 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:44:24.870495 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:44:24.873677 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:44:24.881218 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:44:24.884395 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:44:24.888247 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:44:24.895104 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:44:24.899383 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:44:24.903314 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:44:24.906280 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:44:24.913752 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:44:24.917553 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:44:24.920715 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:44:24.924391 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:44:24.928234 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:44:24.935746 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:44:24.939398 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:44:24.943114 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:44:24.946776 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:44:24.950321 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:44:24.954018 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:44:24.965110 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:44:24.971942 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:44:24.975782 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:44:24.983239 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:44:24.994145 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:44:24.997711 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:44:25.001584 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:44:25.005324 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:44:25.013451 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x24
467 11:44:25.017257 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:44:25.025556 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 11:44:25.028751 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:44:25.037590 [RTC]rtc_get_frequency_meter,154: input=15, output=851
471 11:44:25.047419 [RTC]rtc_get_frequency_meter,154: input=7, output=724
472 11:44:25.056564 [RTC]rtc_get_frequency_meter,154: input=11, output=788
473 11:44:25.066138 [RTC]rtc_get_frequency_meter,154: input=13, output=820
474 11:44:25.075494 [RTC]rtc_get_frequency_meter,154: input=12, output=804
475 11:44:25.085672 [RTC]rtc_get_frequency_meter,154: input=11, output=788
476 11:44:25.095147 [RTC]rtc_get_frequency_meter,154: input=12, output=804
477 11:44:25.099012 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 11:44:25.102668 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 11:44:25.106353 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:44:25.113695 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:44:25.117372 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:44:25.121249 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:44:25.125082 ADC[4]: Raw value=904064 ID=7
484 11:44:25.125163 ADC[3]: Raw value=213916 ID=1
485 11:44:25.128171 RAM Code: 0x71
486 11:44:25.132012 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:44:25.139672 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:44:25.147204 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:44:25.154401 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:44:25.154527 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:44:25.158650 in-header: 03 07 00 00 08 00 00 00
492 11:44:25.162305 in-data: aa e4 47 04 13 02 00 00
493 11:44:25.165422 Chrome EC: UHEPI supported
494 11:44:25.173185 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:44:25.176750 in-header: 03 95 00 00 08 00 00 00
496 11:44:25.181071 in-data: 18 20 20 08 00 00 00 00
497 11:44:25.181159 MRC: failed to locate region type 0.
498 11:44:25.188052 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:44:25.191915 DRAM-K: Running full calibration
500 11:44:25.199048 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:44:25.199136 header.status = 0x0
502 11:44:25.202832 header.version = 0x6 (expected: 0x6)
503 11:44:25.206754 header.size = 0xd00 (expected: 0xd00)
504 11:44:25.206864 header.flags = 0x0
505 11:44:25.214066 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:44:25.232867 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
507 11:44:25.239996 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:44:25.243695 dram_init: ddr_geometry: 2
509 11:44:25.243807 [EMI] MDL number = 2
510 11:44:25.247596 [EMI] Get MDL freq = 0
511 11:44:25.247681 dram_init: ddr_type: 0
512 11:44:25.251169 is_discrete_lpddr4: 1
513 11:44:25.254927 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:44:25.255011
515 11:44:25.255077
516 11:44:25.255138 [Bian_co] ETT version 0.0.0.1
517 11:44:25.262198 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:44:25.262281
519 11:44:25.265800 dramc_set_vcore_voltage set vcore to 650000
520 11:44:25.265883 Read voltage for 800, 4
521 11:44:25.269338 Vio18 = 0
522 11:44:25.269420 Vcore = 650000
523 11:44:25.269489 Vdram = 0
524 11:44:25.269551 Vddq = 0
525 11:44:25.273117 Vmddr = 0
526 11:44:25.273200 dram_init: config_dvfs: 1
527 11:44:25.280087 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:44:25.283756 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:44:25.286945 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:44:25.293155 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:44:25.296918 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:44:25.300722 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:44:25.300806 MEM_TYPE=3, freq_sel=18
534 11:44:25.304066 sv_algorithm_assistance_LP4_1600
535 11:44:25.307841 ============ PULL DRAM RESETB DOWN ============
536 11:44:25.311663 ========== PULL DRAM RESETB DOWN end =========
537 11:44:25.318825 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:44:25.322434 ===================================
539 11:44:25.322520 LPDDR4 DRAM CONFIGURATION
540 11:44:25.325667 ===================================
541 11:44:25.328847 EX_ROW_EN[0] = 0x0
542 11:44:25.332692 EX_ROW_EN[1] = 0x0
543 11:44:25.332775 LP4Y_EN = 0x0
544 11:44:25.336360 WORK_FSP = 0x0
545 11:44:25.336443 WL = 0x2
546 11:44:25.339515 RL = 0x2
547 11:44:25.339597 BL = 0x2
548 11:44:25.339663 RPST = 0x0
549 11:44:25.343286 RD_PRE = 0x0
550 11:44:25.343370 WR_PRE = 0x1
551 11:44:25.346992 WR_PST = 0x0
552 11:44:25.347102 DBI_WR = 0x0
553 11:44:25.350218 DBI_RD = 0x0
554 11:44:25.350301 OTF = 0x1
555 11:44:25.353397 ===================================
556 11:44:25.357041 ===================================
557 11:44:25.359976 ANA top config
558 11:44:25.363117 ===================================
559 11:44:25.366789 DLL_ASYNC_EN = 0
560 11:44:25.366872 ALL_SLAVE_EN = 1
561 11:44:25.369662 NEW_RANK_MODE = 1
562 11:44:25.373177 DLL_IDLE_MODE = 1
563 11:44:25.376778 LP45_APHY_COMB_EN = 1
564 11:44:25.379785 TX_ODT_DIS = 1
565 11:44:25.379869 NEW_8X_MODE = 1
566 11:44:25.383482 ===================================
567 11:44:25.386440 ===================================
568 11:44:25.390257 data_rate = 1600
569 11:44:25.393395 CKR = 1
570 11:44:25.396581 DQ_P2S_RATIO = 8
571 11:44:25.400279 ===================================
572 11:44:25.403495 CA_P2S_RATIO = 8
573 11:44:25.403578 DQ_CA_OPEN = 0
574 11:44:25.407264 DQ_SEMI_OPEN = 0
575 11:44:25.410945 CA_SEMI_OPEN = 0
576 11:44:25.414185 CA_FULL_RATE = 0
577 11:44:25.417243 DQ_CKDIV4_EN = 1
578 11:44:25.417353 CA_CKDIV4_EN = 1
579 11:44:25.420932 CA_PREDIV_EN = 0
580 11:44:25.424154 PH8_DLY = 0
581 11:44:25.427276 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:44:25.430967 DQ_AAMCK_DIV = 4
583 11:44:25.434079 CA_AAMCK_DIV = 4
584 11:44:25.434163 CA_ADMCK_DIV = 4
585 11:44:25.437218 DQ_TRACK_CA_EN = 0
586 11:44:25.440353 CA_PICK = 800
587 11:44:25.443634 CA_MCKIO = 800
588 11:44:25.447387 MCKIO_SEMI = 0
589 11:44:25.451202 PLL_FREQ = 3068
590 11:44:25.451280 DQ_UI_PI_RATIO = 32
591 11:44:25.454941 CA_UI_PI_RATIO = 0
592 11:44:25.458059 ===================================
593 11:44:25.461773 ===================================
594 11:44:25.465357 memory_type:LPDDR4
595 11:44:25.465441 GP_NUM : 10
596 11:44:25.469093 SRAM_EN : 1
597 11:44:25.469171 MD32_EN : 0
598 11:44:25.472530 ===================================
599 11:44:25.476067 [ANA_INIT] >>>>>>>>>>>>>>
600 11:44:25.480196 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:44:25.483552 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:44:25.487195 ===================================
603 11:44:25.487294 data_rate = 1600,PCW = 0X7600
604 11:44:25.490198 ===================================
605 11:44:25.493812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:44:25.500190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:44:25.507031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:44:25.510052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:44:25.513141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:44:25.517057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:44:25.520130 [ANA_INIT] flow start
612 11:44:25.520220 [ANA_INIT] PLL >>>>>>>>
613 11:44:25.523200 [ANA_INIT] PLL <<<<<<<<
614 11:44:25.526979 [ANA_INIT] MIDPI >>>>>>>>
615 11:44:25.530036 [ANA_INIT] MIDPI <<<<<<<<
616 11:44:25.530124 [ANA_INIT] DLL >>>>>>>>
617 11:44:25.533028 [ANA_INIT] flow end
618 11:44:25.536833 ============ LP4 DIFF to SE enter ============
619 11:44:25.539950 ============ LP4 DIFF to SE exit ============
620 11:44:25.543006 [ANA_INIT] <<<<<<<<<<<<<
621 11:44:25.546915 [Flow] Enable top DCM control >>>>>
622 11:44:25.549992 [Flow] Enable top DCM control <<<<<
623 11:44:25.553126 Enable DLL master slave shuffle
624 11:44:25.560072 ==============================================================
625 11:44:25.560159 Gating Mode config
626 11:44:25.566232 ==============================================================
627 11:44:25.566319 Config description:
628 11:44:25.576198 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:44:25.582831 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:44:25.589410 SELPH_MODE 0: By rank 1: By Phase
631 11:44:25.593054 ==============================================================
632 11:44:25.596014 GAT_TRACK_EN = 1
633 11:44:25.599481 RX_GATING_MODE = 2
634 11:44:25.602636 RX_GATING_TRACK_MODE = 2
635 11:44:25.606414 SELPH_MODE = 1
636 11:44:25.609625 PICG_EARLY_EN = 1
637 11:44:25.612812 VALID_LAT_VALUE = 1
638 11:44:25.619692 ==============================================================
639 11:44:25.622806 Enter into Gating configuration >>>>
640 11:44:25.626027 Exit from Gating configuration <<<<
641 11:44:25.629614 Enter into DVFS_PRE_config >>>>>
642 11:44:25.639586 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:44:25.642743 Exit from DVFS_PRE_config <<<<<
644 11:44:25.646067 Enter into PICG configuration >>>>
645 11:44:25.649180 Exit from PICG configuration <<<<
646 11:44:25.652311 [RX_INPUT] configuration >>>>>
647 11:44:25.652394 [RX_INPUT] configuration <<<<<
648 11:44:25.659183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:44:25.665540 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:44:25.669139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:44:25.675882 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:44:25.682063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:44:25.688622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:44:25.692168 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:44:25.695894 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:44:25.702344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:44:25.705450 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:44:25.709133 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:44:25.715534 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:44:25.718614 ===================================
661 11:44:25.718697 LPDDR4 DRAM CONFIGURATION
662 11:44:25.722578 ===================================
663 11:44:25.725787 EX_ROW_EN[0] = 0x0
664 11:44:25.725871 EX_ROW_EN[1] = 0x0
665 11:44:25.728873 LP4Y_EN = 0x0
666 11:44:25.728961 WORK_FSP = 0x0
667 11:44:25.731923 WL = 0x2
668 11:44:25.732036 RL = 0x2
669 11:44:25.735434 BL = 0x2
670 11:44:25.738559 RPST = 0x0
671 11:44:25.738643 RD_PRE = 0x0
672 11:44:25.742264 WR_PRE = 0x1
673 11:44:25.742346 WR_PST = 0x0
674 11:44:25.745505 DBI_WR = 0x0
675 11:44:25.745588 DBI_RD = 0x0
676 11:44:25.748613 OTF = 0x1
677 11:44:25.751790 ===================================
678 11:44:25.755535 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:44:25.758683 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:44:25.761856 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:44:25.765031 ===================================
682 11:44:25.768242 LPDDR4 DRAM CONFIGURATION
683 11:44:25.772000 ===================================
684 11:44:25.775047 EX_ROW_EN[0] = 0x10
685 11:44:25.775129 EX_ROW_EN[1] = 0x0
686 11:44:25.778530 LP4Y_EN = 0x0
687 11:44:25.778613 WORK_FSP = 0x0
688 11:44:25.781514 WL = 0x2
689 11:44:25.781597 RL = 0x2
690 11:44:25.785220 BL = 0x2
691 11:44:25.785303 RPST = 0x0
692 11:44:25.788296 RD_PRE = 0x0
693 11:44:25.791879 WR_PRE = 0x1
694 11:44:25.791990 WR_PST = 0x0
695 11:44:25.794929 DBI_WR = 0x0
696 11:44:25.795011 DBI_RD = 0x0
697 11:44:25.798588 OTF = 0x1
698 11:44:25.801695 ===================================
699 11:44:25.805240 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:44:25.810121 nWR fixed to 40
701 11:44:25.813910 [ModeRegInit_LP4] CH0 RK0
702 11:44:25.813992 [ModeRegInit_LP4] CH0 RK1
703 11:44:25.817027 [ModeRegInit_LP4] CH1 RK0
704 11:44:25.820151 [ModeRegInit_LP4] CH1 RK1
705 11:44:25.820234 match AC timing 13
706 11:44:25.826651 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:44:25.830330 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:44:25.833462 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:44:25.840223 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:44:25.843230 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:44:25.846938 [EMI DOE] emi_dcm 0
712 11:44:25.850058 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:44:25.850144 ==
714 11:44:25.853132 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:44:25.856276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:44:25.856363 ==
717 11:44:25.863299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:44:25.869723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:44:25.877881 [CA 0] Center 37 (7~68) winsize 62
720 11:44:25.880890 [CA 1] Center 37 (7~68) winsize 62
721 11:44:25.884396 [CA 2] Center 35 (5~65) winsize 61
722 11:44:25.888028 [CA 3] Center 34 (4~65) winsize 62
723 11:44:25.891161 [CA 4] Center 33 (3~64) winsize 62
724 11:44:25.894236 [CA 5] Center 33 (3~64) winsize 62
725 11:44:25.894325
726 11:44:25.897811 [CmdBusTrainingLP45] Vref(ca) range 1: 30
727 11:44:25.897897
728 11:44:25.900856 [CATrainingPosCal] consider 1 rank data
729 11:44:25.904604 u2DelayCellTimex100 = 270/100 ps
730 11:44:25.907694 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:44:25.911240 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 11:44:25.918050 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
733 11:44:25.921212 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:44:25.924343 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 11:44:25.927674 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:44:25.927777
737 11:44:25.930814 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:44:25.930894
739 11:44:25.934526 [CBTSetCACLKResult] CA Dly = 33
740 11:44:25.934619 CS Dly: 5 (0~36)
741 11:44:25.937719 ==
742 11:44:25.940831 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:44:25.943934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:44:25.944073 ==
745 11:44:25.947690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:44:25.953925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:44:25.964020 [CA 0] Center 38 (7~69) winsize 63
748 11:44:25.967177 [CA 1] Center 37 (7~68) winsize 62
749 11:44:25.970969 [CA 2] Center 35 (4~66) winsize 63
750 11:44:25.974219 [CA 3] Center 34 (4~65) winsize 62
751 11:44:25.977264 [CA 4] Center 34 (3~65) winsize 63
752 11:44:25.980511 [CA 5] Center 33 (3~64) winsize 62
753 11:44:25.980594
754 11:44:25.984026 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:44:25.984153
756 11:44:25.987201 [CATrainingPosCal] consider 2 rank data
757 11:44:25.990787 u2DelayCellTimex100 = 270/100 ps
758 11:44:25.994296 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:44:25.997559 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:44:26.004143 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
761 11:44:26.007783 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:44:26.010757 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 11:44:26.013840 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:44:26.013923
765 11:44:26.017532 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:44:26.017616
767 11:44:26.020570 [CBTSetCACLKResult] CA Dly = 33
768 11:44:26.020654 CS Dly: 6 (0~38)
769 11:44:26.023691
770 11:44:26.027498 ----->DramcWriteLeveling(PI) begin...
771 11:44:26.027612 ==
772 11:44:26.031373 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:44:26.034571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:44:26.034655 ==
775 11:44:26.038321 Write leveling (Byte 0): 32 => 32
776 11:44:26.038441 Write leveling (Byte 1): 29 => 29
777 11:44:26.041543 DramcWriteLeveling(PI) end<-----
778 11:44:26.041626
779 11:44:26.041693 ==
780 11:44:26.045298 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:44:26.048942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:44:26.051960 ==
783 11:44:26.052065 [Gating] SW mode calibration
784 11:44:26.059621 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:44:26.066339 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:44:26.069492 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:44:26.072649 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 11:44:26.079531 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 11:44:26.082716 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 11:44:26.086330 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:44:26.092998 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:44:26.096120 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:44:26.099814 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:44:26.105998 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:44:26.109675 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:44:26.112827 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:44:26.119822 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:44:26.122880 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:44:26.126166 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:44:26.133132 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:44:26.136338 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:44:26.139551 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:44:26.146561 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:44:26.149980 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 11:44:26.152982 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
806 11:44:26.159590 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:44:26.162733 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:44:26.165838 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:44:26.169737 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:44:26.175938 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:44:26.179231 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:44:26.185680 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
813 11:44:26.189363 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
814 11:44:26.192477 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:44:26.196166 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:44:26.202621 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:44:26.205864 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:44:26.209095 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:44:26.215641 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
820 11:44:26.219271 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (1 0)
821 11:44:26.222405 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
822 11:44:26.228989 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:44:26.232155 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:44:26.235218 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:44:26.242327 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:44:26.244957 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:44:26.251539 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
828 11:44:26.254996 0 11 8 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (0 0)
829 11:44:26.258107 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
830 11:44:26.261793 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:44:26.268497 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:44:26.271705 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:44:26.274811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:44:26.281740 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:44:26.284870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:44:26.288236 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 11:44:26.294629 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:44:26.297791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:44:26.301380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:44:26.308000 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:44:26.311101 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:44:26.314757 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:44:26.321244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:44:26.324398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:44:26.327612 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:44:26.334347 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:44:26.337672 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:44:26.340811 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:44:26.347805 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:44:26.350980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:44:26.354134 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 11:44:26.360925 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 11:44:26.363933 Total UI for P1: 0, mck2ui 16
854 11:44:26.367658 best dqsien dly found for B0: ( 0, 14, 4)
855 11:44:26.370887 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:44:26.373971 Total UI for P1: 0, mck2ui 16
857 11:44:26.377734 best dqsien dly found for B1: ( 0, 14, 8)
858 11:44:26.380859 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 11:44:26.383962 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:44:26.384070
861 11:44:26.387112 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 11:44:26.390732 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:44:26.393853 [Gating] SW calibration Done
864 11:44:26.393936 ==
865 11:44:26.397560 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:44:26.401282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:44:26.401394 ==
868 11:44:26.404962 RX Vref Scan: 0
869 11:44:26.405037
870 11:44:26.408061 RX Vref 0 -> 0, step: 1
871 11:44:26.408149
872 11:44:26.408211 RX Delay -130 -> 252, step: 16
873 11:44:26.414951 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:44:26.418075 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 11:44:26.421151 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:44:26.424820 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:44:26.427707 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 11:44:26.434718 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 11:44:26.437664 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:44:26.440964 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 11:44:26.444677 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 11:44:26.447697 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 11:44:26.454689 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 11:44:26.457857 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:44:26.461064 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:44:26.464713 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 11:44:26.470813 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 11:44:26.474529 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 11:44:26.474613 ==
890 11:44:26.477664 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:44:26.480768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:44:26.480868 ==
893 11:44:26.480964 DQS Delay:
894 11:44:26.484562 DQS0 = 0, DQS1 = 0
895 11:44:26.484645 DQM Delay:
896 11:44:26.487708 DQM0 = 88, DQM1 = 75
897 11:44:26.487808 DQ Delay:
898 11:44:26.490854 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 11:44:26.493951 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 11:44:26.497581 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
901 11:44:26.500765 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 11:44:26.500850
903 11:44:26.500917
904 11:44:26.500980 ==
905 11:44:26.503863 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:44:26.510755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:44:26.510845 ==
908 11:44:26.510933
909 11:44:26.511015
910 11:44:26.511095 TX Vref Scan disable
911 11:44:26.514160 == TX Byte 0 ==
912 11:44:26.517270 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 11:44:26.523779 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 11:44:26.523897 == TX Byte 1 ==
915 11:44:26.527463 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 11:44:26.530562 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 11:44:26.534171 ==
918 11:44:26.537202 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:44:26.540236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:44:26.540347 ==
921 11:44:26.553520 TX Vref=22, minBit 1, minWin=26, winSum=439
922 11:44:26.556757 TX Vref=24, minBit 5, minWin=26, winSum=443
923 11:44:26.559931 TX Vref=26, minBit 2, minWin=27, winSum=443
924 11:44:26.563004 TX Vref=28, minBit 7, minWin=27, winSum=454
925 11:44:26.566748 TX Vref=30, minBit 0, minWin=28, winSum=453
926 11:44:26.572993 TX Vref=32, minBit 1, minWin=27, winSum=447
927 11:44:26.576146 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
928 11:44:26.576233
929 11:44:26.579898 Final TX Range 1 Vref 30
930 11:44:26.580009
931 11:44:26.580093 ==
932 11:44:26.583241 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:44:26.586456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:44:26.586542 ==
935 11:44:26.589519
936 11:44:26.589631
937 11:44:26.589727 TX Vref Scan disable
938 11:44:26.593319 == TX Byte 0 ==
939 11:44:26.596437 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 11:44:26.602818 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 11:44:26.602931 == TX Byte 1 ==
942 11:44:26.606655 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 11:44:26.613392 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 11:44:26.613477
945 11:44:26.613544 [DATLAT]
946 11:44:26.613605 Freq=800, CH0 RK0
947 11:44:26.613665
948 11:44:26.616542 DATLAT Default: 0xa
949 11:44:26.616627 0, 0xFFFF, sum = 0
950 11:44:26.619621 1, 0xFFFF, sum = 0
951 11:44:26.619709 2, 0xFFFF, sum = 0
952 11:44:26.623239 3, 0xFFFF, sum = 0
953 11:44:26.623325 4, 0xFFFF, sum = 0
954 11:44:26.626243 5, 0xFFFF, sum = 0
955 11:44:26.629898 6, 0xFFFF, sum = 0
956 11:44:26.629983 7, 0xFFFF, sum = 0
957 11:44:26.633011 8, 0xFFFF, sum = 0
958 11:44:26.633097 9, 0x0, sum = 1
959 11:44:26.633165 10, 0x0, sum = 2
960 11:44:26.636616 11, 0x0, sum = 3
961 11:44:26.636702 12, 0x0, sum = 4
962 11:44:26.639518 best_step = 10
963 11:44:26.639602
964 11:44:26.639668 ==
965 11:44:26.642553 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:44:26.646122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:44:26.646207 ==
968 11:44:26.649223 RX Vref Scan: 1
969 11:44:26.649308
970 11:44:26.652486 Set Vref Range= 32 -> 127
971 11:44:26.652570
972 11:44:26.652636 RX Vref 32 -> 127, step: 1
973 11:44:26.652697
974 11:44:26.656279 RX Delay -111 -> 252, step: 8
975 11:44:26.656362
976 11:44:26.659488 Set Vref, RX VrefLevel [Byte0]: 32
977 11:44:26.662648 [Byte1]: 32
978 11:44:26.665913
979 11:44:26.665996 Set Vref, RX VrefLevel [Byte0]: 33
980 11:44:26.669653 [Byte1]: 33
981 11:44:26.673897
982 11:44:26.673981 Set Vref, RX VrefLevel [Byte0]: 34
983 11:44:26.677138 [Byte1]: 34
984 11:44:26.681193
985 11:44:26.681278 Set Vref, RX VrefLevel [Byte0]: 35
986 11:44:26.684358 [Byte1]: 35
987 11:44:26.688812
988 11:44:26.688926 Set Vref, RX VrefLevel [Byte0]: 36
989 11:44:26.692653 [Byte1]: 36
990 11:44:26.696971
991 11:44:26.697055 Set Vref, RX VrefLevel [Byte0]: 37
992 11:44:26.700249 [Byte1]: 37
993 11:44:26.704694
994 11:44:26.704777 Set Vref, RX VrefLevel [Byte0]: 38
995 11:44:26.707915 [Byte1]: 38
996 11:44:26.712548
997 11:44:26.712644 Set Vref, RX VrefLevel [Byte0]: 39
998 11:44:26.715697 [Byte1]: 39
999 11:44:26.719938
1000 11:44:26.720067 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:44:26.723784 [Byte1]: 40
1002 11:44:26.727222
1003 11:44:26.727304 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:44:26.730851 [Byte1]: 41
1005 11:44:26.734520
1006 11:44:26.734603 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:44:26.737826 [Byte1]: 42
1008 11:44:26.742785
1009 11:44:26.742868 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:44:26.745825 [Byte1]: 43
1011 11:44:26.750124
1012 11:44:26.750206 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:44:26.753187 [Byte1]: 44
1014 11:44:26.757475
1015 11:44:26.757557 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:44:26.760694 [Byte1]: 45
1017 11:44:26.765336
1018 11:44:26.765419 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:44:26.768400 [Byte1]: 46
1020 11:44:26.772880
1021 11:44:26.772961 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:44:26.776064 [Byte1]: 47
1023 11:44:26.780499
1024 11:44:26.780582 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:44:26.784072 [Byte1]: 48
1026 11:44:26.788535
1027 11:44:26.788621 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:44:26.791644 [Byte1]: 49
1029 11:44:26.795956
1030 11:44:26.796062 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:44:26.799136 [Byte1]: 50
1032 11:44:26.803805
1033 11:44:26.803889 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:44:26.806837 [Byte1]: 51
1035 11:44:26.811298
1036 11:44:26.811379 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:44:26.814556 [Byte1]: 52
1038 11:44:26.818907
1039 11:44:26.818988 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:44:26.822079 [Byte1]: 53
1041 11:44:26.826350
1042 11:44:26.826430 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:44:26.829939 [Byte1]: 54
1044 11:44:26.834270
1045 11:44:26.834350 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:44:26.837256 [Byte1]: 55
1047 11:44:26.841584
1048 11:44:26.841666 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:44:26.845277 [Byte1]: 56
1050 11:44:26.849650
1051 11:44:26.849731 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:44:26.852717 [Byte1]: 57
1053 11:44:26.857111
1054 11:44:26.857192 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:44:26.860242 [Byte1]: 58
1056 11:44:26.864805
1057 11:44:26.864886 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:44:26.868002 [Byte1]: 59
1059 11:44:26.872337
1060 11:44:26.872417 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:44:26.875572 [Byte1]: 60
1062 11:44:26.879845
1063 11:44:26.879926 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:44:26.883336 [Byte1]: 61
1065 11:44:26.887645
1066 11:44:26.887725 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:44:26.890847 [Byte1]: 62
1068 11:44:26.895193
1069 11:44:26.895273 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:44:26.898349 [Byte1]: 63
1071 11:44:26.903030
1072 11:44:26.903111 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:44:26.906013 [Byte1]: 64
1074 11:44:26.910948
1075 11:44:26.911045 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:44:26.914030 [Byte1]: 65
1077 11:44:26.917916
1078 11:44:26.917997 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:44:26.921648 [Byte1]: 66
1080 11:44:26.926043
1081 11:44:26.926166 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:44:26.929317 [Byte1]: 67
1083 11:44:26.933867
1084 11:44:26.933966 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:44:26.936966 [Byte1]: 68
1086 11:44:26.941136
1087 11:44:26.941291 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:44:26.944778 [Byte1]: 69
1089 11:44:26.949107
1090 11:44:26.949227 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:44:26.952190 [Byte1]: 70
1092 11:44:26.956357
1093 11:44:26.956465 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:44:26.959872 [Byte1]: 71
1095 11:44:26.964232
1096 11:44:26.964337 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:44:26.967322 [Byte1]: 72
1098 11:44:26.971677
1099 11:44:26.971805 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:44:26.974787 [Byte1]: 73
1101 11:44:26.979436
1102 11:44:26.979566 Final RX Vref Byte 0 = 56 to rank0
1103 11:44:26.982553 Final RX Vref Byte 1 = 61 to rank0
1104 11:44:26.986216 Final RX Vref Byte 0 = 56 to rank1
1105 11:44:26.989334 Final RX Vref Byte 1 = 61 to rank1==
1106 11:44:26.992468 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 11:44:26.999364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 11:44:26.999473 ==
1109 11:44:26.999614 DQS Delay:
1110 11:44:26.999717 DQS0 = 0, DQS1 = 0
1111 11:44:27.002549 DQM Delay:
1112 11:44:27.002665 DQM0 = 88, DQM1 = 76
1113 11:44:27.006297 DQ Delay:
1114 11:44:27.009451 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1115 11:44:27.009559 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1116 11:44:27.012527 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
1117 11:44:27.019513 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1118 11:44:27.019625
1119 11:44:27.019728
1120 11:44:27.025823 [DQSOSCAuto] RK0, (LSB)MR18= 0x2922, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1121 11:44:27.029021 CH0 RK0: MR19=606, MR18=2922
1122 11:44:27.035801 CH0_RK0: MR19=0x606, MR18=0x2922, DQSOSC=399, MR23=63, INC=92, DEC=61
1123 11:44:27.035912
1124 11:44:27.038787 ----->DramcWriteLeveling(PI) begin...
1125 11:44:27.038897 ==
1126 11:44:27.042350 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 11:44:27.045917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 11:44:27.046028 ==
1129 11:44:27.048919 Write leveling (Byte 0): 31 => 31
1130 11:44:27.052488 Write leveling (Byte 1): 25 => 25
1131 11:44:27.056013 DramcWriteLeveling(PI) end<-----
1132 11:44:27.056103
1133 11:44:27.056168 ==
1134 11:44:27.059070 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 11:44:27.062143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 11:44:27.062229 ==
1137 11:44:27.065654 [Gating] SW mode calibration
1138 11:44:27.072430 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 11:44:27.078806 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 11:44:27.081906 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1141 11:44:27.085728 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1142 11:44:27.133241 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1143 11:44:27.133369 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 11:44:27.133894 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 11:44:27.134520 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 11:44:27.134799 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 11:44:27.134887 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 11:44:27.134954 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:44:27.135077 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:44:27.135161 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:44:27.135244 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:44:27.166431 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:44:27.166547 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:44:27.167202 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:44:27.167467 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:44:27.167539 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:44:27.167603 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1158 11:44:27.167664 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1159 11:44:27.167734 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:44:27.170691 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:44:27.174257 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:44:27.180704 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:44:27.184509 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:44:27.187509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:44:27.194382 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1166 11:44:27.197531 0 9 8 | B1->B0 | 2322 3131 | 1 0 | (0 0) (0 0)
1167 11:44:27.201015 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1168 11:44:27.204272 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 11:44:27.210620 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 11:44:27.214355 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 11:44:27.217583 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 11:44:27.224198 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 11:44:27.227478 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 0) (0 1)
1174 11:44:27.230647 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
1175 11:44:27.237631 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1176 11:44:27.240820 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:44:27.243793 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:44:27.250720 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:44:27.253822 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:44:27.257360 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:44:27.263830 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1182 11:44:27.266858 0 11 8 | B1->B0 | 2d2d 4444 | 0 1 | (0 0) (0 0)
1183 11:44:27.270398 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1184 11:44:27.277733 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 11:44:27.281069 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 11:44:27.284311 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 11:44:27.288857 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 11:44:27.295139 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 11:44:27.298417 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1190 11:44:27.301871 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1191 11:44:27.306316 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 11:44:27.312569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 11:44:27.315602 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 11:44:27.318788 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 11:44:27.325796 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:44:27.328969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:44:27.332192 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:44:27.339004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:44:27.342216 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:44:27.345477 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:44:27.352415 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:44:27.355606 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:44:27.359347 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:44:27.362307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:44:27.368790 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1206 11:44:27.372382 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1207 11:44:27.375380 Total UI for P1: 0, mck2ui 16
1208 11:44:27.378987 best dqsien dly found for B0: ( 0, 14, 4)
1209 11:44:27.382102 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 11:44:27.385610 Total UI for P1: 0, mck2ui 16
1211 11:44:27.388664 best dqsien dly found for B1: ( 0, 14, 8)
1212 11:44:27.392505 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1213 11:44:27.395577 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1214 11:44:27.398813
1215 11:44:27.402003 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1216 11:44:27.405626 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1217 11:44:27.408594 [Gating] SW calibration Done
1218 11:44:27.408711 ==
1219 11:44:27.412277 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 11:44:27.415476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 11:44:27.415587 ==
1222 11:44:27.415682 RX Vref Scan: 0
1223 11:44:27.415774
1224 11:44:27.418543 RX Vref 0 -> 0, step: 1
1225 11:44:27.418649
1226 11:44:27.421679 RX Delay -130 -> 252, step: 16
1227 11:44:27.425588 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1228 11:44:27.428741 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1229 11:44:27.435576 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1230 11:44:27.438702 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1231 11:44:27.441856 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1232 11:44:27.445017 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1233 11:44:27.448872 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1234 11:44:27.455184 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1235 11:44:27.458224 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1236 11:44:27.462230 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1237 11:44:27.465381 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1238 11:44:27.468558 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1239 11:44:27.475224 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1240 11:44:27.478228 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1241 11:44:27.481890 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1242 11:44:27.484899 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1243 11:44:27.484982 ==
1244 11:44:27.488471 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 11:44:27.494796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 11:44:27.494880 ==
1247 11:44:27.494946 DQS Delay:
1248 11:44:27.498329 DQS0 = 0, DQS1 = 0
1249 11:44:27.498411 DQM Delay:
1250 11:44:27.498476 DQM0 = 90, DQM1 = 77
1251 11:44:27.501471 DQ Delay:
1252 11:44:27.504594 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
1253 11:44:27.508300 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1254 11:44:27.511575 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1255 11:44:27.514565 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1256 11:44:27.514666
1257 11:44:27.514760
1258 11:44:27.514847 ==
1259 11:44:27.518268 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:44:27.521699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:44:27.521774 ==
1262 11:44:27.521836
1263 11:44:27.521894
1264 11:44:27.524882 TX Vref Scan disable
1265 11:44:27.527926 == TX Byte 0 ==
1266 11:44:27.531094 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1267 11:44:27.534889 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1268 11:44:27.538162 == TX Byte 1 ==
1269 11:44:27.541247 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1270 11:44:27.544335 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1271 11:44:27.544418 ==
1272 11:44:27.547590 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 11:44:27.551334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 11:44:27.554458 ==
1275 11:44:27.566459 TX Vref=22, minBit 0, minWin=27, winSum=441
1276 11:44:27.569581 TX Vref=24, minBit 1, minWin=27, winSum=443
1277 11:44:27.572710 TX Vref=26, minBit 2, minWin=27, winSum=449
1278 11:44:27.576397 TX Vref=28, minBit 1, minWin=27, winSum=447
1279 11:44:27.579425 TX Vref=30, minBit 1, minWin=27, winSum=448
1280 11:44:27.583316 TX Vref=32, minBit 0, minWin=28, winSum=454
1281 11:44:27.589478 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1282 11:44:27.589561
1283 11:44:27.592513 Final TX Range 1 Vref 32
1284 11:44:27.592595
1285 11:44:27.592659 ==
1286 11:44:27.596103 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 11:44:27.599586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 11:44:27.599670 ==
1289 11:44:27.602492
1290 11:44:27.602574
1291 11:44:27.602656 TX Vref Scan disable
1292 11:44:27.606095 == TX Byte 0 ==
1293 11:44:27.609319 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1294 11:44:27.616173 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1295 11:44:27.616257 == TX Byte 1 ==
1296 11:44:27.619710 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1297 11:44:27.625869 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1298 11:44:27.625948
1299 11:44:27.626011 [DATLAT]
1300 11:44:27.626069 Freq=800, CH0 RK1
1301 11:44:27.626126
1302 11:44:27.629596 DATLAT Default: 0xa
1303 11:44:27.629675 0, 0xFFFF, sum = 0
1304 11:44:27.632869 1, 0xFFFF, sum = 0
1305 11:44:27.636000 2, 0xFFFF, sum = 0
1306 11:44:27.636122 3, 0xFFFF, sum = 0
1307 11:44:27.639223 4, 0xFFFF, sum = 0
1308 11:44:27.639305 5, 0xFFFF, sum = 0
1309 11:44:27.642409 6, 0xFFFF, sum = 0
1310 11:44:27.642489 7, 0xFFFF, sum = 0
1311 11:44:27.646119 8, 0xFFFF, sum = 0
1312 11:44:27.646199 9, 0x0, sum = 1
1313 11:44:27.649183 10, 0x0, sum = 2
1314 11:44:27.649262 11, 0x0, sum = 3
1315 11:44:27.652213 12, 0x0, sum = 4
1316 11:44:27.652294 best_step = 10
1317 11:44:27.652357
1318 11:44:27.652415 ==
1319 11:44:27.655948 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 11:44:27.659111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 11:44:27.659192 ==
1322 11:44:27.662373 RX Vref Scan: 0
1323 11:44:27.662477
1324 11:44:27.665604 RX Vref 0 -> 0, step: 1
1325 11:44:27.665684
1326 11:44:27.665747 RX Delay -95 -> 252, step: 8
1327 11:44:27.673148 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1328 11:44:27.676425 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1329 11:44:27.679487 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1330 11:44:27.682610 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1331 11:44:27.686270 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1332 11:44:27.693145 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1333 11:44:27.696138 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1334 11:44:27.699773 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1335 11:44:27.702828 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1336 11:44:27.705751 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1337 11:44:27.712546 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1338 11:44:27.716216 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1339 11:44:27.719334 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1340 11:44:27.722377 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1341 11:44:27.729120 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1342 11:44:27.732746 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1343 11:44:27.732827 ==
1344 11:44:27.735908 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 11:44:27.739011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 11:44:27.739127 ==
1347 11:44:27.739197 DQS Delay:
1348 11:44:27.742734 DQS0 = 0, DQS1 = 0
1349 11:44:27.742813 DQM Delay:
1350 11:44:27.745995 DQM0 = 86, DQM1 = 76
1351 11:44:27.746074 DQ Delay:
1352 11:44:27.749051 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1353 11:44:27.752223 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1354 11:44:27.756029 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1355 11:44:27.758622 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1356 11:44:27.758712
1357 11:44:27.758796
1358 11:44:27.768812 [DQSOSCAuto] RK1, (LSB)MR18= 0x221f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
1359 11:44:27.768920 CH0 RK1: MR19=606, MR18=221F
1360 11:44:27.775911 CH0_RK1: MR19=0x606, MR18=0x221F, DQSOSC=401, MR23=63, INC=91, DEC=61
1361 11:44:27.779096 [RxdqsGatingPostProcess] freq 800
1362 11:44:27.785379 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 11:44:27.789232 Pre-setting of DQS Precalculation
1364 11:44:27.792298 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1365 11:44:27.792387 ==
1366 11:44:27.795577 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 11:44:27.802116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:44:27.802230 ==
1369 11:44:27.805610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 11:44:27.812293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 11:44:27.821240 [CA 0] Center 36 (6~67) winsize 62
1372 11:44:27.824356 [CA 1] Center 37 (6~68) winsize 63
1373 11:44:27.827946 [CA 2] Center 35 (5~65) winsize 61
1374 11:44:27.830986 [CA 3] Center 34 (4~65) winsize 62
1375 11:44:27.834158 [CA 4] Center 34 (4~65) winsize 62
1376 11:44:27.837814 [CA 5] Center 33 (3~64) winsize 62
1377 11:44:27.837896
1378 11:44:27.841054 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 11:44:27.841138
1380 11:44:27.844149 [CATrainingPosCal] consider 1 rank data
1381 11:44:27.847319 u2DelayCellTimex100 = 270/100 ps
1382 11:44:27.851018 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1383 11:44:27.857398 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1384 11:44:27.860543 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1385 11:44:27.864211 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 11:44:27.867319 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 11:44:27.870607 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 11:44:27.870689
1389 11:44:27.873664 CA PerBit enable=1, Macro0, CA PI delay=33
1390 11:44:27.873775
1391 11:44:27.876860 [CBTSetCACLKResult] CA Dly = 33
1392 11:44:27.880825 CS Dly: 4 (0~35)
1393 11:44:27.880906 ==
1394 11:44:27.883833 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 11:44:27.887039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 11:44:27.887122 ==
1397 11:44:27.893961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 11:44:27.897158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 11:44:27.907165 [CA 0] Center 36 (6~67) winsize 62
1400 11:44:27.910649 [CA 1] Center 36 (6~67) winsize 62
1401 11:44:27.914146 [CA 2] Center 34 (4~65) winsize 62
1402 11:44:27.917559 [CA 3] Center 34 (4~64) winsize 61
1403 11:44:27.920412 [CA 4] Center 34 (3~65) winsize 63
1404 11:44:27.923844 [CA 5] Center 33 (3~64) winsize 62
1405 11:44:27.923964
1406 11:44:27.927303 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1407 11:44:27.927394
1408 11:44:27.930751 [CATrainingPosCal] consider 2 rank data
1409 11:44:27.933745 u2DelayCellTimex100 = 270/100 ps
1410 11:44:27.937210 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 11:44:27.940723 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1412 11:44:27.944372 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1413 11:44:27.948291 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1414 11:44:27.951428 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 11:44:27.955288 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 11:44:27.959060
1417 11:44:27.962238 CA PerBit enable=1, Macro0, CA PI delay=33
1418 11:44:27.962321
1419 11:44:27.962387 [CBTSetCACLKResult] CA Dly = 33
1420 11:44:27.965930 CS Dly: 5 (0~37)
1421 11:44:27.966014
1422 11:44:27.969765 ----->DramcWriteLeveling(PI) begin...
1423 11:44:27.969850 ==
1424 11:44:27.973396 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 11:44:27.977235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 11:44:27.977320 ==
1427 11:44:27.980431 Write leveling (Byte 0): 26 => 26
1428 11:44:27.983611 Write leveling (Byte 1): 27 => 27
1429 11:44:27.986697 DramcWriteLeveling(PI) end<-----
1430 11:44:27.986781
1431 11:44:27.986847 ==
1432 11:44:27.990616 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 11:44:27.993737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 11:44:27.993822 ==
1435 11:44:27.996943 [Gating] SW mode calibration
1436 11:44:28.003985 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 11:44:28.010478 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 11:44:28.013577 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1439 11:44:28.017305 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1440 11:44:28.023817 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1441 11:44:28.026764 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 11:44:28.030280 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 11:44:28.033665 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 11:44:28.040122 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 11:44:28.043598 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:44:28.047198 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 11:44:28.053865 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:44:28.056971 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:44:28.060197 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:44:28.066545 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:44:28.070231 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:44:28.073190 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:44:28.080117 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:44:28.083233 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1455 11:44:28.086434 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1456 11:44:28.093496 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:44:28.096673 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:44:28.100316 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:44:28.106767 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:44:28.109912 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:44:28.113087 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:44:28.119820 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:44:28.123461 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1464 11:44:28.126685 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1465 11:44:28.133416 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 11:44:28.136948 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 11:44:28.139960 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 11:44:28.146655 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 11:44:28.149627 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 11:44:28.153270 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 11:44:28.156977 0 10 4 | B1->B0 | 3333 3131 | 0 1 | (0 0) (1 0)
1472 11:44:28.163377 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1473 11:44:28.166659 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:44:28.169836 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:44:28.176681 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:44:28.179877 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:44:28.183033 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:44:28.189335 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:44:28.192631 0 11 4 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (1 1)
1480 11:44:28.199574 0 11 8 | B1->B0 | 3737 4343 | 0 0 | (0 0) (0 0)
1481 11:44:28.202740 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 11:44:28.205957 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 11:44:28.209123 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 11:44:28.216159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 11:44:28.219127 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 11:44:28.222350 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 11:44:28.229160 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1488 11:44:28.232310 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1489 11:44:28.236005 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 11:44:28.242317 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 11:44:28.245793 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 11:44:28.248852 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 11:44:28.255354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:44:28.258938 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:44:28.265476 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:44:28.268656 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:44:28.271767 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:44:28.278728 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:44:28.282055 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:44:28.285127 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:44:28.291824 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:44:28.294937 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:44:28.298062 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:44:28.301848 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:44:28.305079 Total UI for P1: 0, mck2ui 16
1506 11:44:28.308321 best dqsien dly found for B0: ( 0, 14, 6)
1507 11:44:28.311448 Total UI for P1: 0, mck2ui 16
1508 11:44:28.314654 best dqsien dly found for B1: ( 0, 14, 6)
1509 11:44:28.318449 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1510 11:44:28.324798 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1511 11:44:28.324880
1512 11:44:28.327969 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1513 11:44:28.331324 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1514 11:44:28.334513 [Gating] SW calibration Done
1515 11:44:28.334594 ==
1516 11:44:28.338209 Dram Type= 6, Freq= 0, CH_1, rank 0
1517 11:44:28.341357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1518 11:44:28.341440 ==
1519 11:44:28.341506 RX Vref Scan: 0
1520 11:44:28.344352
1521 11:44:28.344434 RX Vref 0 -> 0, step: 1
1522 11:44:28.344563
1523 11:44:28.347715 RX Delay -130 -> 252, step: 16
1524 11:44:28.351170 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1525 11:44:28.354797 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1526 11:44:28.361328 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1527 11:44:28.364815 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1528 11:44:28.367706 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1529 11:44:28.371289 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1530 11:44:28.377654 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1531 11:44:28.380780 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1532 11:44:28.384679 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1533 11:44:28.387759 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1534 11:44:28.390776 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1535 11:44:28.397808 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1536 11:44:28.401024 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1537 11:44:28.404194 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1538 11:44:28.407493 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1539 11:44:28.410589 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1540 11:44:28.414300 ==
1541 11:44:28.417414 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 11:44:28.420515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 11:44:28.420604 ==
1544 11:44:28.420671 DQS Delay:
1545 11:44:28.424362 DQS0 = 0, DQS1 = 0
1546 11:44:28.424446 DQM Delay:
1547 11:44:28.427595 DQM0 = 88, DQM1 = 81
1548 11:44:28.427679 DQ Delay:
1549 11:44:28.430774 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1550 11:44:28.433819 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1551 11:44:28.437323 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1552 11:44:28.440556 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1553 11:44:28.440639
1554 11:44:28.440705
1555 11:44:28.440767 ==
1556 11:44:28.443672 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 11:44:28.446908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 11:44:28.447024 ==
1559 11:44:28.447122
1560 11:44:28.450489
1561 11:44:28.450566 TX Vref Scan disable
1562 11:44:28.453497 == TX Byte 0 ==
1563 11:44:28.457222 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1564 11:44:28.460126 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1565 11:44:28.463590 == TX Byte 1 ==
1566 11:44:28.467182 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1567 11:44:28.470039 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1568 11:44:28.470123 ==
1569 11:44:28.473665 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 11:44:28.479982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 11:44:28.480095 ==
1572 11:44:28.492269 TX Vref=22, minBit 4, minWin=27, winSum=444
1573 11:44:28.495554 TX Vref=24, minBit 0, minWin=27, winSum=445
1574 11:44:28.498668 TX Vref=26, minBit 2, minWin=27, winSum=449
1575 11:44:28.501793 TX Vref=28, minBit 4, minWin=27, winSum=453
1576 11:44:28.504969 TX Vref=30, minBit 0, minWin=27, winSum=452
1577 11:44:28.511816 TX Vref=32, minBit 1, minWin=27, winSum=451
1578 11:44:28.515079 [TxChooseVref] Worse bit 4, Min win 27, Win sum 453, Final Vref 28
1579 11:44:28.515163
1580 11:44:28.518385 Final TX Range 1 Vref 28
1581 11:44:28.518469
1582 11:44:28.518535 ==
1583 11:44:28.521555 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 11:44:28.525369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 11:44:28.525454 ==
1586 11:44:28.525520
1587 11:44:28.528574
1588 11:44:28.528656 TX Vref Scan disable
1589 11:44:28.531716 == TX Byte 0 ==
1590 11:44:28.534859 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1591 11:44:28.541562 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1592 11:44:28.541654 == TX Byte 1 ==
1593 11:44:28.545378 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1594 11:44:28.551701 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1595 11:44:28.551785
1596 11:44:28.551851 [DATLAT]
1597 11:44:28.551914 Freq=800, CH1 RK0
1598 11:44:28.551973
1599 11:44:28.554777 DATLAT Default: 0xa
1600 11:44:28.554861 0, 0xFFFF, sum = 0
1601 11:44:28.558543 1, 0xFFFF, sum = 0
1602 11:44:28.561798 2, 0xFFFF, sum = 0
1603 11:44:28.561882 3, 0xFFFF, sum = 0
1604 11:44:28.564698 4, 0xFFFF, sum = 0
1605 11:44:28.564783 5, 0xFFFF, sum = 0
1606 11:44:28.568307 6, 0xFFFF, sum = 0
1607 11:44:28.568392 7, 0xFFFF, sum = 0
1608 11:44:28.571768 8, 0xFFFF, sum = 0
1609 11:44:28.571853 9, 0x0, sum = 1
1610 11:44:28.574642 10, 0x0, sum = 2
1611 11:44:28.574727 11, 0x0, sum = 3
1612 11:44:28.574794 12, 0x0, sum = 4
1613 11:44:28.578232 best_step = 10
1614 11:44:28.578315
1615 11:44:28.578381 ==
1616 11:44:28.581662 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 11:44:28.584730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 11:44:28.584814 ==
1619 11:44:28.587832 RX Vref Scan: 1
1620 11:44:28.587914
1621 11:44:28.591352 Set Vref Range= 32 -> 127
1622 11:44:28.591464
1623 11:44:28.591565 RX Vref 32 -> 127, step: 1
1624 11:44:28.591658
1625 11:44:28.594430 RX Delay -95 -> 252, step: 8
1626 11:44:28.594543
1627 11:44:28.598156 Set Vref, RX VrefLevel [Byte0]: 32
1628 11:44:28.601383 [Byte1]: 32
1629 11:44:28.604554
1630 11:44:28.604657 Set Vref, RX VrefLevel [Byte0]: 33
1631 11:44:28.607609 [Byte1]: 33
1632 11:44:28.612113
1633 11:44:28.612252 Set Vref, RX VrefLevel [Byte0]: 34
1634 11:44:28.615123 [Byte1]: 34
1635 11:44:28.619676
1636 11:44:28.619793 Set Vref, RX VrefLevel [Byte0]: 35
1637 11:44:28.622718 [Byte1]: 35
1638 11:44:28.627175
1639 11:44:28.627284 Set Vref, RX VrefLevel [Byte0]: 36
1640 11:44:28.630946 [Byte1]: 36
1641 11:44:28.634693
1642 11:44:28.634800 Set Vref, RX VrefLevel [Byte0]: 37
1643 11:44:28.638471 [Byte1]: 37
1644 11:44:28.642776
1645 11:44:28.642881 Set Vref, RX VrefLevel [Byte0]: 38
1646 11:44:28.645957 [Byte1]: 38
1647 11:44:28.650423
1648 11:44:28.650528 Set Vref, RX VrefLevel [Byte0]: 39
1649 11:44:28.653568 [Byte1]: 39
1650 11:44:28.657874
1651 11:44:28.657976 Set Vref, RX VrefLevel [Byte0]: 40
1652 11:44:28.660844 [Byte1]: 40
1653 11:44:28.665254
1654 11:44:28.665360 Set Vref, RX VrefLevel [Byte0]: 41
1655 11:44:28.668930 [Byte1]: 41
1656 11:44:28.672731
1657 11:44:28.672817 Set Vref, RX VrefLevel [Byte0]: 42
1658 11:44:28.676493 [Byte1]: 42
1659 11:44:28.680778
1660 11:44:28.680850 Set Vref, RX VrefLevel [Byte0]: 43
1661 11:44:28.683667 [Byte1]: 43
1662 11:44:28.688266
1663 11:44:28.688339 Set Vref, RX VrefLevel [Byte0]: 44
1664 11:44:28.691256 [Byte1]: 44
1665 11:44:28.696027
1666 11:44:28.696148 Set Vref, RX VrefLevel [Byte0]: 45
1667 11:44:28.699000 [Byte1]: 45
1668 11:44:28.703236
1669 11:44:28.703351 Set Vref, RX VrefLevel [Byte0]: 46
1670 11:44:28.706835 [Byte1]: 46
1671 11:44:28.711072
1672 11:44:28.711157 Set Vref, RX VrefLevel [Byte0]: 47
1673 11:44:28.714365 [Byte1]: 47
1674 11:44:28.718654
1675 11:44:28.718805 Set Vref, RX VrefLevel [Byte0]: 48
1676 11:44:28.721709 [Byte1]: 48
1677 11:44:28.726228
1678 11:44:28.726309 Set Vref, RX VrefLevel [Byte0]: 49
1679 11:44:28.729245 [Byte1]: 49
1680 11:44:28.733632
1681 11:44:28.733713 Set Vref, RX VrefLevel [Byte0]: 50
1682 11:44:28.736763 [Byte1]: 50
1683 11:44:28.741186
1684 11:44:28.741268 Set Vref, RX VrefLevel [Byte0]: 51
1685 11:44:28.744922 [Byte1]: 51
1686 11:44:28.749225
1687 11:44:28.749307 Set Vref, RX VrefLevel [Byte0]: 52
1688 11:44:28.752289 [Byte1]: 52
1689 11:44:28.756705
1690 11:44:28.756786 Set Vref, RX VrefLevel [Byte0]: 53
1691 11:44:28.759747 [Byte1]: 53
1692 11:44:28.763961
1693 11:44:28.764090 Set Vref, RX VrefLevel [Byte0]: 54
1694 11:44:28.767121 [Byte1]: 54
1695 11:44:28.771558
1696 11:44:28.771647 Set Vref, RX VrefLevel [Byte0]: 55
1697 11:44:28.774701 [Byte1]: 55
1698 11:44:28.779556
1699 11:44:28.779637 Set Vref, RX VrefLevel [Byte0]: 56
1700 11:44:28.782647 [Byte1]: 56
1701 11:44:28.787007
1702 11:44:28.787092 Set Vref, RX VrefLevel [Byte0]: 57
1703 11:44:28.790048 [Byte1]: 57
1704 11:44:28.794305
1705 11:44:28.794387 Set Vref, RX VrefLevel [Byte0]: 58
1706 11:44:28.798042 [Byte1]: 58
1707 11:44:28.802309
1708 11:44:28.802459 Set Vref, RX VrefLevel [Byte0]: 59
1709 11:44:28.805323 [Byte1]: 59
1710 11:44:28.809618
1711 11:44:28.809700 Set Vref, RX VrefLevel [Byte0]: 60
1712 11:44:28.813209 [Byte1]: 60
1713 11:44:28.817439
1714 11:44:28.817520 Set Vref, RX VrefLevel [Byte0]: 61
1715 11:44:28.820588 [Byte1]: 61
1716 11:44:28.824918
1717 11:44:28.824999 Set Vref, RX VrefLevel [Byte0]: 62
1718 11:44:28.828127 [Byte1]: 62
1719 11:44:28.832487
1720 11:44:28.832568 Set Vref, RX VrefLevel [Byte0]: 63
1721 11:44:28.835623 [Byte1]: 63
1722 11:44:28.839992
1723 11:44:28.840122 Set Vref, RX VrefLevel [Byte0]: 64
1724 11:44:28.843341 [Byte1]: 64
1725 11:44:28.847690
1726 11:44:28.847771 Set Vref, RX VrefLevel [Byte0]: 65
1727 11:44:28.850651 [Byte1]: 65
1728 11:44:28.855089
1729 11:44:28.855171 Set Vref, RX VrefLevel [Byte0]: 66
1730 11:44:28.858288 [Byte1]: 66
1731 11:44:28.862814
1732 11:44:28.862895 Set Vref, RX VrefLevel [Byte0]: 67
1733 11:44:28.865957 [Byte1]: 67
1734 11:44:28.870332
1735 11:44:28.870413 Set Vref, RX VrefLevel [Byte0]: 68
1736 11:44:28.873494 [Byte1]: 68
1737 11:44:28.877950
1738 11:44:28.878030 Set Vref, RX VrefLevel [Byte0]: 69
1739 11:44:28.881104 [Byte1]: 69
1740 11:44:28.885891
1741 11:44:28.885971 Set Vref, RX VrefLevel [Byte0]: 70
1742 11:44:28.889086 [Byte1]: 70
1743 11:44:28.893492
1744 11:44:28.893573 Set Vref, RX VrefLevel [Byte0]: 71
1745 11:44:28.896743 [Byte1]: 71
1746 11:44:28.900687
1747 11:44:28.900768 Set Vref, RX VrefLevel [Byte0]: 72
1748 11:44:28.904278 [Byte1]: 72
1749 11:44:28.908705
1750 11:44:28.908787 Set Vref, RX VrefLevel [Byte0]: 73
1751 11:44:28.911732 [Byte1]: 73
1752 11:44:28.916214
1753 11:44:28.916295 Final RX Vref Byte 0 = 56 to rank0
1754 11:44:28.919059 Final RX Vref Byte 1 = 59 to rank0
1755 11:44:28.922941 Final RX Vref Byte 0 = 56 to rank1
1756 11:44:28.926122 Final RX Vref Byte 1 = 59 to rank1==
1757 11:44:28.929432 Dram Type= 6, Freq= 0, CH_1, rank 0
1758 11:44:28.935755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1759 11:44:28.935865 ==
1760 11:44:28.935979 DQS Delay:
1761 11:44:28.939556 DQS0 = 0, DQS1 = 0
1762 11:44:28.939667 DQM Delay:
1763 11:44:28.939760 DQM0 = 85, DQM1 = 81
1764 11:44:28.942584 DQ Delay:
1765 11:44:28.945752 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1766 11:44:28.948921 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =84
1767 11:44:28.952701 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1768 11:44:28.955771 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1769 11:44:28.955877
1770 11:44:28.955986
1771 11:44:28.962595 [DQSOSCAuto] RK0, (LSB)MR18= 0x162a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1772 11:44:28.965762 CH1 RK0: MR19=606, MR18=162A
1773 11:44:28.972579 CH1_RK0: MR19=0x606, MR18=0x162A, DQSOSC=399, MR23=63, INC=92, DEC=61
1774 11:44:28.972662
1775 11:44:28.975620 ----->DramcWriteLeveling(PI) begin...
1776 11:44:28.975703 ==
1777 11:44:28.979373 Dram Type= 6, Freq= 0, CH_1, rank 1
1778 11:44:28.982615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1779 11:44:28.982697 ==
1780 11:44:28.985865 Write leveling (Byte 0): 26 => 26
1781 11:44:28.988744 Write leveling (Byte 1): 27 => 27
1782 11:44:28.992367 DramcWriteLeveling(PI) end<-----
1783 11:44:28.992449
1784 11:44:28.992544 ==
1785 11:44:28.995679 Dram Type= 6, Freq= 0, CH_1, rank 1
1786 11:44:28.998783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 11:44:28.998865 ==
1788 11:44:29.002543 [Gating] SW mode calibration
1789 11:44:29.009212 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1790 11:44:29.015461 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1791 11:44:29.018599 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1792 11:44:29.025147 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1793 11:44:29.028777 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1794 11:44:29.031870 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1795 11:44:29.035632 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1796 11:44:29.042038 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1797 11:44:29.045186 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1798 11:44:29.048891 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 11:44:29.055263 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 11:44:29.058355 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 11:44:29.062054 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 11:44:29.068430 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 11:44:29.071651 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 11:44:29.075335 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 11:44:29.081484 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:44:29.085236 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:44:29.088419 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1808 11:44:29.094599 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1809 11:44:29.098272 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:44:29.101320 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:44:29.107770 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:44:29.110926 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:44:29.114780 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:44:29.121385 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:44:29.124190 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:44:29.127761 0 9 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1817 11:44:29.134309 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1818 11:44:29.137553 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1819 11:44:29.140730 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1820 11:44:29.147651 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1821 11:44:29.150990 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1822 11:44:29.154190 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1823 11:44:29.160677 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 11:44:29.164229 0 10 4 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 0)
1825 11:44:29.167404 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1826 11:44:29.173980 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:44:29.177732 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:44:29.180783 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:44:29.187643 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:44:29.190903 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:44:29.193952 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1832 11:44:29.200614 0 11 4 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
1833 11:44:29.203825 0 11 8 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1834 11:44:29.207529 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1835 11:44:29.213666 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1836 11:44:29.217368 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1837 11:44:29.220567 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1838 11:44:29.227390 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1839 11:44:29.230313 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1840 11:44:29.233937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1841 11:44:29.240347 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1842 11:44:29.243999 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1843 11:44:29.247051 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1844 11:44:29.253924 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1845 11:44:29.257117 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1846 11:44:29.260276 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 11:44:29.267097 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 11:44:29.270181 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 11:44:29.273958 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 11:44:29.280270 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 11:44:29.283870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 11:44:29.286732 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 11:44:29.289953 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:44:29.296929 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:44:29.299943 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1856 11:44:29.303576 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1857 11:44:29.306587 Total UI for P1: 0, mck2ui 16
1858 11:44:29.309783 best dqsien dly found for B0: ( 0, 14, 0)
1859 11:44:29.316664 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1860 11:44:29.319786 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 11:44:29.323014 Total UI for P1: 0, mck2ui 16
1862 11:44:29.326122 best dqsien dly found for B1: ( 0, 14, 6)
1863 11:44:29.329862 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1864 11:44:29.332896 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1865 11:44:29.333012
1866 11:44:29.336076 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1867 11:44:29.342945 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1868 11:44:29.343071 [Gating] SW calibration Done
1869 11:44:29.343168 ==
1870 11:44:29.346442 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 11:44:29.352654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 11:44:29.352736 ==
1873 11:44:29.352802 RX Vref Scan: 0
1874 11:44:29.352862
1875 11:44:29.356306 RX Vref 0 -> 0, step: 1
1876 11:44:29.356426
1877 11:44:29.359810 RX Delay -130 -> 252, step: 16
1878 11:44:29.363042 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1879 11:44:29.366101 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1880 11:44:29.369836 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1881 11:44:29.373448 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1882 11:44:29.379972 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1883 11:44:29.383139 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1884 11:44:29.386322 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1885 11:44:29.389517 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1886 11:44:29.393124 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1887 11:44:29.399491 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1888 11:44:29.402513 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1889 11:44:29.406129 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1890 11:44:29.409108 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1891 11:44:29.416106 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1892 11:44:29.419175 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1893 11:44:29.422929 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1894 11:44:29.423009 ==
1895 11:44:29.426071 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 11:44:29.429146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 11:44:29.429240 ==
1898 11:44:29.432775 DQS Delay:
1899 11:44:29.432854 DQS0 = 0, DQS1 = 0
1900 11:44:29.435946 DQM Delay:
1901 11:44:29.436056 DQM0 = 83, DQM1 = 80
1902 11:44:29.436123 DQ Delay:
1903 11:44:29.439129 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1904 11:44:29.442375 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1905 11:44:29.445667 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1906 11:44:29.448803 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1907 11:44:29.448881
1908 11:44:29.448945
1909 11:44:29.452341 ==
1910 11:44:29.455926 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 11:44:29.458798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 11:44:29.458902 ==
1913 11:44:29.458971
1914 11:44:29.459033
1915 11:44:29.462275 TX Vref Scan disable
1916 11:44:29.462371 == TX Byte 0 ==
1917 11:44:29.465362 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1918 11:44:29.472110 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1919 11:44:29.472229 == TX Byte 1 ==
1920 11:44:29.478867 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1921 11:44:29.481918 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1922 11:44:29.482027 ==
1923 11:44:29.485097 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 11:44:29.488276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 11:44:29.488362 ==
1926 11:44:29.501984 TX Vref=22, minBit 1, minWin=27, winSum=443
1927 11:44:29.505644 TX Vref=24, minBit 1, minWin=27, winSum=448
1928 11:44:29.508731 TX Vref=26, minBit 5, minWin=27, winSum=452
1929 11:44:29.512205 TX Vref=28, minBit 0, minWin=27, winSum=451
1930 11:44:29.515206 TX Vref=30, minBit 2, minWin=27, winSum=458
1931 11:44:29.518800 TX Vref=32, minBit 3, minWin=27, winSum=455
1932 11:44:29.525661 [TxChooseVref] Worse bit 2, Min win 27, Win sum 458, Final Vref 30
1933 11:44:29.525780
1934 11:44:29.528770 Final TX Range 1 Vref 30
1935 11:44:29.528903
1936 11:44:29.529002 ==
1937 11:44:29.531938 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 11:44:29.535062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 11:44:29.535170 ==
1940 11:44:29.538750
1941 11:44:29.538859
1942 11:44:29.538956 TX Vref Scan disable
1943 11:44:29.541859 == TX Byte 0 ==
1944 11:44:29.545703 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1945 11:44:29.552006 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1946 11:44:29.552135 == TX Byte 1 ==
1947 11:44:29.555322 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1948 11:44:29.561880 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1949 11:44:29.561999
1950 11:44:29.562102 [DATLAT]
1951 11:44:29.562195 Freq=800, CH1 RK1
1952 11:44:29.562291
1953 11:44:29.565338 DATLAT Default: 0xa
1954 11:44:29.565442 0, 0xFFFF, sum = 0
1955 11:44:29.568273 1, 0xFFFF, sum = 0
1956 11:44:29.568383 2, 0xFFFF, sum = 0
1957 11:44:29.571836 3, 0xFFFF, sum = 0
1958 11:44:29.574963 4, 0xFFFF, sum = 0
1959 11:44:29.575109 5, 0xFFFF, sum = 0
1960 11:44:29.578697 6, 0xFFFF, sum = 0
1961 11:44:29.578814 7, 0xFFFF, sum = 0
1962 11:44:29.581836 8, 0xFFFF, sum = 0
1963 11:44:29.581946 9, 0x0, sum = 1
1964 11:44:29.584947 10, 0x0, sum = 2
1965 11:44:29.585053 11, 0x0, sum = 3
1966 11:44:29.585165 12, 0x0, sum = 4
1967 11:44:29.588724 best_step = 10
1968 11:44:29.588842
1969 11:44:29.588940 ==
1970 11:44:29.591776 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 11:44:29.594960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 11:44:29.595059 ==
1973 11:44:29.598749 RX Vref Scan: 0
1974 11:44:29.598918
1975 11:44:29.599041 RX Vref 0 -> 0, step: 1
1976 11:44:29.601671
1977 11:44:29.601754 RX Delay -95 -> 252, step: 8
1978 11:44:29.608581 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1979 11:44:29.611753 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1980 11:44:29.615477 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1981 11:44:29.618376 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1982 11:44:29.622034 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1983 11:44:29.628820 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1984 11:44:29.631966 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1985 11:44:29.635091 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1986 11:44:29.638160 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1987 11:44:29.641329 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1988 11:44:29.648225 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
1989 11:44:29.651928 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
1990 11:44:29.655067 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1991 11:44:29.658168 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1992 11:44:29.665136 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1993 11:44:29.668334 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1994 11:44:29.668443 ==
1995 11:44:29.671492 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 11:44:29.675035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 11:44:29.675128 ==
1998 11:44:29.677937 DQS Delay:
1999 11:44:29.678061 DQS0 = 0, DQS1 = 0
2000 11:44:29.678169 DQM Delay:
2001 11:44:29.681420 DQM0 = 86, DQM1 = 83
2002 11:44:29.681529 DQ Delay:
2003 11:44:29.684595 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2004 11:44:29.687992 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2005 11:44:29.691170 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
2006 11:44:29.695074 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2007 11:44:29.695158
2008 11:44:29.695224
2009 11:44:29.704498 [DQSOSCAuto] RK1, (LSB)MR18= 0x1934, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2010 11:44:29.704582 CH1 RK1: MR19=606, MR18=1934
2011 11:44:29.711302 CH1_RK1: MR19=0x606, MR18=0x1934, DQSOSC=396, MR23=63, INC=94, DEC=62
2012 11:44:29.714561 [RxdqsGatingPostProcess] freq 800
2013 11:44:29.721246 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2014 11:44:29.724254 Pre-setting of DQS Precalculation
2015 11:44:29.727870 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2016 11:44:29.737827 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2017 11:44:29.744566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2018 11:44:29.744662
2019 11:44:29.744729
2020 11:44:29.747641 [Calibration Summary] 1600 Mbps
2021 11:44:29.747755 CH 0, Rank 0
2022 11:44:29.750939 SW Impedance : PASS
2023 11:44:29.751020 DUTY Scan : NO K
2024 11:44:29.754664 ZQ Calibration : PASS
2025 11:44:29.757993 Jitter Meter : NO K
2026 11:44:29.758075 CBT Training : PASS
2027 11:44:29.761118 Write leveling : PASS
2028 11:44:29.761200 RX DQS gating : PASS
2029 11:44:29.764237 RX DQ/DQS(RDDQC) : PASS
2030 11:44:29.768011 TX DQ/DQS : PASS
2031 11:44:29.768140 RX DATLAT : PASS
2032 11:44:29.771236 RX DQ/DQS(Engine): PASS
2033 11:44:29.774326 TX OE : NO K
2034 11:44:29.774408 All Pass.
2035 11:44:29.774473
2036 11:44:29.774533 CH 0, Rank 1
2037 11:44:29.778001 SW Impedance : PASS
2038 11:44:29.780956 DUTY Scan : NO K
2039 11:44:29.781038 ZQ Calibration : PASS
2040 11:44:29.784699 Jitter Meter : NO K
2041 11:44:29.787540 CBT Training : PASS
2042 11:44:29.787647 Write leveling : PASS
2043 11:44:29.791075 RX DQS gating : PASS
2044 11:44:29.794594 RX DQ/DQS(RDDQC) : PASS
2045 11:44:29.794674 TX DQ/DQS : PASS
2046 11:44:29.797719 RX DATLAT : PASS
2047 11:44:29.800794 RX DQ/DQS(Engine): PASS
2048 11:44:29.800870 TX OE : NO K
2049 11:44:29.800935 All Pass.
2050 11:44:29.804515
2051 11:44:29.804587 CH 1, Rank 0
2052 11:44:29.807599 SW Impedance : PASS
2053 11:44:29.807686 DUTY Scan : NO K
2054 11:44:29.811235 ZQ Calibration : PASS
2055 11:44:29.811318 Jitter Meter : NO K
2056 11:44:29.814346 CBT Training : PASS
2057 11:44:29.817479 Write leveling : PASS
2058 11:44:29.817562 RX DQS gating : PASS
2059 11:44:29.821191 RX DQ/DQS(RDDQC) : PASS
2060 11:44:29.824223 TX DQ/DQS : PASS
2061 11:44:29.824305 RX DATLAT : PASS
2062 11:44:29.827385 RX DQ/DQS(Engine): PASS
2063 11:44:29.830881 TX OE : NO K
2064 11:44:29.830965 All Pass.
2065 11:44:29.831031
2066 11:44:29.831092 CH 1, Rank 1
2067 11:44:29.834518 SW Impedance : PASS
2068 11:44:29.837721 DUTY Scan : NO K
2069 11:44:29.837809 ZQ Calibration : PASS
2070 11:44:29.840828 Jitter Meter : NO K
2071 11:44:29.843936 CBT Training : PASS
2072 11:44:29.844020 Write leveling : PASS
2073 11:44:29.847093 RX DQS gating : PASS
2074 11:44:29.850940 RX DQ/DQS(RDDQC) : PASS
2075 11:44:29.851044 TX DQ/DQS : PASS
2076 11:44:29.854020 RX DATLAT : PASS
2077 11:44:29.857119 RX DQ/DQS(Engine): PASS
2078 11:44:29.857224 TX OE : NO K
2079 11:44:29.857327 All Pass.
2080 11:44:29.857419
2081 11:44:29.860813 DramC Write-DBI off
2082 11:44:29.863977 PER_BANK_REFRESH: Hybrid Mode
2083 11:44:29.864082 TX_TRACKING: ON
2084 11:44:29.867173 [GetDramInforAfterCalByMRR] Vendor 6.
2085 11:44:29.871020 [GetDramInforAfterCalByMRR] Revision 606.
2086 11:44:29.877347 [GetDramInforAfterCalByMRR] Revision 2 0.
2087 11:44:29.877441 MR0 0x3b3b
2088 11:44:29.877509 MR8 0x5151
2089 11:44:29.880597 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2090 11:44:29.880681
2091 11:44:29.883719 MR0 0x3b3b
2092 11:44:29.883828 MR8 0x5151
2093 11:44:29.887225 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 11:44:29.887311
2095 11:44:29.897148 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2096 11:44:29.900081 [FAST_K] Save calibration result to emmc
2097 11:44:29.903659 [FAST_K] Save calibration result to emmc
2098 11:44:29.906822 dram_init: config_dvfs: 1
2099 11:44:29.910464 dramc_set_vcore_voltage set vcore to 662500
2100 11:44:29.913484 Read voltage for 1200, 2
2101 11:44:29.913599 Vio18 = 0
2102 11:44:29.913712 Vcore = 662500
2103 11:44:29.917202 Vdram = 0
2104 11:44:29.917309 Vddq = 0
2105 11:44:29.917419 Vmddr = 0
2106 11:44:29.923242 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2107 11:44:29.927274 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2108 11:44:29.930379 MEM_TYPE=3, freq_sel=15
2109 11:44:29.933305 sv_algorithm_assistance_LP4_1600
2110 11:44:29.936910 ============ PULL DRAM RESETB DOWN ============
2111 11:44:29.939895 ========== PULL DRAM RESETB DOWN end =========
2112 11:44:29.946772 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2113 11:44:29.949965 ===================================
2114 11:44:29.950072 LPDDR4 DRAM CONFIGURATION
2115 11:44:29.953272 ===================================
2116 11:44:29.956452 EX_ROW_EN[0] = 0x0
2117 11:44:29.960191 EX_ROW_EN[1] = 0x0
2118 11:44:29.960272 LP4Y_EN = 0x0
2119 11:44:29.963331 WORK_FSP = 0x0
2120 11:44:29.963437 WL = 0x4
2121 11:44:29.966512 RL = 0x4
2122 11:44:29.966615 BL = 0x2
2123 11:44:29.970250 RPST = 0x0
2124 11:44:29.970353 RD_PRE = 0x0
2125 11:44:29.973453 WR_PRE = 0x1
2126 11:44:29.973557 WR_PST = 0x0
2127 11:44:29.976588 DBI_WR = 0x0
2128 11:44:29.976668 DBI_RD = 0x0
2129 11:44:29.979752 OTF = 0x1
2130 11:44:29.982885 ===================================
2131 11:44:29.986618 ===================================
2132 11:44:29.986720 ANA top config
2133 11:44:29.989822 ===================================
2134 11:44:29.993498 DLL_ASYNC_EN = 0
2135 11:44:29.996642 ALL_SLAVE_EN = 0
2136 11:44:29.999966 NEW_RANK_MODE = 1
2137 11:44:30.000079 DLL_IDLE_MODE = 1
2138 11:44:30.003107 LP45_APHY_COMB_EN = 1
2139 11:44:30.006699 TX_ODT_DIS = 1
2140 11:44:30.009660 NEW_8X_MODE = 1
2141 11:44:30.013247 ===================================
2142 11:44:30.016253 ===================================
2143 11:44:30.019775 data_rate = 2400
2144 11:44:30.019938 CKR = 1
2145 11:44:30.022873 DQ_P2S_RATIO = 8
2146 11:44:30.026578 ===================================
2147 11:44:30.029714 CA_P2S_RATIO = 8
2148 11:44:30.032941 DQ_CA_OPEN = 0
2149 11:44:30.036039 DQ_SEMI_OPEN = 0
2150 11:44:30.039781 CA_SEMI_OPEN = 0
2151 11:44:30.039865 CA_FULL_RATE = 0
2152 11:44:30.042802 DQ_CKDIV4_EN = 0
2153 11:44:30.046024 CA_CKDIV4_EN = 0
2154 11:44:30.049676 CA_PREDIV_EN = 0
2155 11:44:30.052821 PH8_DLY = 17
2156 11:44:30.055988 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2157 11:44:30.056074 DQ_AAMCK_DIV = 4
2158 11:44:30.059684 CA_AAMCK_DIV = 4
2159 11:44:30.062736 CA_ADMCK_DIV = 4
2160 11:44:30.065904 DQ_TRACK_CA_EN = 0
2161 11:44:30.069654 CA_PICK = 1200
2162 11:44:30.072819 CA_MCKIO = 1200
2163 11:44:30.076008 MCKIO_SEMI = 0
2164 11:44:30.076103 PLL_FREQ = 2366
2165 11:44:30.079155 DQ_UI_PI_RATIO = 32
2166 11:44:30.082998 CA_UI_PI_RATIO = 0
2167 11:44:30.086052 ===================================
2168 11:44:30.089189 ===================================
2169 11:44:30.092938 memory_type:LPDDR4
2170 11:44:30.093022 GP_NUM : 10
2171 11:44:30.096176 SRAM_EN : 1
2172 11:44:30.099181 MD32_EN : 0
2173 11:44:30.102884 ===================================
2174 11:44:30.102965 [ANA_INIT] >>>>>>>>>>>>>>
2175 11:44:30.105805 <<<<<< [CONFIGURE PHASE]: ANA_TX
2176 11:44:30.109405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2177 11:44:30.112438 ===================================
2178 11:44:30.115914 data_rate = 2400,PCW = 0X5b00
2179 11:44:30.118954 ===================================
2180 11:44:30.122340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2181 11:44:30.128841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2182 11:44:30.135610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2183 11:44:30.138739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2184 11:44:30.142402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2185 11:44:30.145545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2186 11:44:30.148948 [ANA_INIT] flow start
2187 11:44:30.149028 [ANA_INIT] PLL >>>>>>>>
2188 11:44:30.152027 [ANA_INIT] PLL <<<<<<<<
2189 11:44:30.155803 [ANA_INIT] MIDPI >>>>>>>>
2190 11:44:30.155890 [ANA_INIT] MIDPI <<<<<<<<
2191 11:44:30.158847 [ANA_INIT] DLL >>>>>>>>
2192 11:44:30.162038 [ANA_INIT] DLL <<<<<<<<
2193 11:44:30.162151 [ANA_INIT] flow end
2194 11:44:30.168958 ============ LP4 DIFF to SE enter ============
2195 11:44:30.172238 ============ LP4 DIFF to SE exit ============
2196 11:44:30.175282 [ANA_INIT] <<<<<<<<<<<<<
2197 11:44:30.178329 [Flow] Enable top DCM control >>>>>
2198 11:44:30.182133 [Flow] Enable top DCM control <<<<<
2199 11:44:30.182226 Enable DLL master slave shuffle
2200 11:44:30.188491 ==============================================================
2201 11:44:30.192142 Gating Mode config
2202 11:44:30.195217 ==============================================================
2203 11:44:30.198342 Config description:
2204 11:44:30.208180 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2205 11:44:30.215093 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2206 11:44:30.218650 SELPH_MODE 0: By rank 1: By Phase
2207 11:44:30.225250 ==============================================================
2208 11:44:30.228197 GAT_TRACK_EN = 1
2209 11:44:30.231827 RX_GATING_MODE = 2
2210 11:44:30.235222 RX_GATING_TRACK_MODE = 2
2211 11:44:30.235422 SELPH_MODE = 1
2212 11:44:30.238153 PICG_EARLY_EN = 1
2213 11:44:30.241832 VALID_LAT_VALUE = 1
2214 11:44:30.248468 ==============================================================
2215 11:44:30.251557 Enter into Gating configuration >>>>
2216 11:44:30.255062 Exit from Gating configuration <<<<
2217 11:44:30.258063 Enter into DVFS_PRE_config >>>>>
2218 11:44:30.268327 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2219 11:44:30.271657 Exit from DVFS_PRE_config <<<<<
2220 11:44:30.274727 Enter into PICG configuration >>>>
2221 11:44:30.278583 Exit from PICG configuration <<<<
2222 11:44:30.281762 [RX_INPUT] configuration >>>>>
2223 11:44:30.284795 [RX_INPUT] configuration <<<<<
2224 11:44:30.287972 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2225 11:44:30.294885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2226 11:44:30.301268 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2227 11:44:30.308152 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2228 11:44:30.315012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2229 11:44:30.318087 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2230 11:44:30.324800 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2231 11:44:30.327743 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2232 11:44:30.331315 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2233 11:44:30.334392 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2234 11:44:30.341287 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2235 11:44:30.344844 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2236 11:44:30.347719 ===================================
2237 11:44:30.350844 LPDDR4 DRAM CONFIGURATION
2238 11:44:30.354563 ===================================
2239 11:44:30.354649 EX_ROW_EN[0] = 0x0
2240 11:44:30.357642 EX_ROW_EN[1] = 0x0
2241 11:44:30.357728 LP4Y_EN = 0x0
2242 11:44:30.361224 WORK_FSP = 0x0
2243 11:44:30.361311 WL = 0x4
2244 11:44:30.364275 RL = 0x4
2245 11:44:30.364360 BL = 0x2
2246 11:44:30.367906 RPST = 0x0
2247 11:44:30.367993 RD_PRE = 0x0
2248 11:44:30.371138 WR_PRE = 0x1
2249 11:44:30.371223 WR_PST = 0x0
2250 11:44:30.374232 DBI_WR = 0x0
2251 11:44:30.377365 DBI_RD = 0x0
2252 11:44:30.377450 OTF = 0x1
2253 11:44:30.381147 ===================================
2254 11:44:30.384188 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2255 11:44:30.387326 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2256 11:44:30.394342 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 11:44:30.397469 ===================================
2258 11:44:30.400552 LPDDR4 DRAM CONFIGURATION
2259 11:44:30.404358 ===================================
2260 11:44:30.404443 EX_ROW_EN[0] = 0x10
2261 11:44:30.407513 EX_ROW_EN[1] = 0x0
2262 11:44:30.407597 LP4Y_EN = 0x0
2263 11:44:30.410512 WORK_FSP = 0x0
2264 11:44:30.410612 WL = 0x4
2265 11:44:30.414260 RL = 0x4
2266 11:44:30.414343 BL = 0x2
2267 11:44:30.417245 RPST = 0x0
2268 11:44:30.417334 RD_PRE = 0x0
2269 11:44:30.420966 WR_PRE = 0x1
2270 11:44:30.421074 WR_PST = 0x0
2271 11:44:30.424151 DBI_WR = 0x0
2272 11:44:30.424234 DBI_RD = 0x0
2273 11:44:30.427204 OTF = 0x1
2274 11:44:30.430958 ===================================
2275 11:44:30.437316 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2276 11:44:30.437401 ==
2277 11:44:30.440762 Dram Type= 6, Freq= 0, CH_0, rank 0
2278 11:44:30.443651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2279 11:44:30.443782 ==
2280 11:44:30.447234 [Duty_Offset_Calibration]
2281 11:44:30.447317 B0:2 B1:0 CA:4
2282 11:44:30.447400
2283 11:44:30.450224 [DutyScan_Calibration_Flow] k_type=0
2284 11:44:30.460706
2285 11:44:30.460787 ==CLK 0==
2286 11:44:30.463776 Final CLK duty delay cell = -4
2287 11:44:30.467210 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2288 11:44:30.470865 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2289 11:44:30.474132 [-4] AVG Duty = 4953%(X100)
2290 11:44:30.474237
2291 11:44:30.477232 CH0 CLK Duty spec in!! Max-Min= 218%
2292 11:44:30.480499 [DutyScan_Calibration_Flow] ====Done====
2293 11:44:30.480599
2294 11:44:30.483470 [DutyScan_Calibration_Flow] k_type=1
2295 11:44:30.500507
2296 11:44:30.500591 ==DQS 0 ==
2297 11:44:30.503562 Final DQS duty delay cell = 0
2298 11:44:30.506703 [0] MAX Duty = 5156%(X100), DQS PI = 18
2299 11:44:30.509963 [0] MIN Duty = 5093%(X100), DQS PI = 0
2300 11:44:30.510044 [0] AVG Duty = 5124%(X100)
2301 11:44:30.513784
2302 11:44:30.513887 ==DQS 1 ==
2303 11:44:30.517014 Final DQS duty delay cell = 0
2304 11:44:30.520117 [0] MAX Duty = 5125%(X100), DQS PI = 4
2305 11:44:30.523624 [0] MIN Duty = 4969%(X100), DQS PI = 16
2306 11:44:30.523751 [0] AVG Duty = 5047%(X100)
2307 11:44:30.526857
2308 11:44:30.530061 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2309 11:44:30.530214
2310 11:44:30.533271 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2311 11:44:30.537002 [DutyScan_Calibration_Flow] ====Done====
2312 11:44:30.537081
2313 11:44:30.539968 [DutyScan_Calibration_Flow] k_type=3
2314 11:44:30.556607
2315 11:44:30.556698 ==DQM 0 ==
2316 11:44:30.560036 Final DQM duty delay cell = 0
2317 11:44:30.563104 [0] MAX Duty = 5125%(X100), DQS PI = 20
2318 11:44:30.566722 [0] MIN Duty = 4844%(X100), DQS PI = 54
2319 11:44:30.569626 [0] AVG Duty = 4984%(X100)
2320 11:44:30.569705
2321 11:44:30.569768 ==DQM 1 ==
2322 11:44:30.573145 Final DQM duty delay cell = 0
2323 11:44:30.576675 [0] MAX Duty = 4969%(X100), DQS PI = 2
2324 11:44:30.579846 [0] MIN Duty = 4875%(X100), DQS PI = 20
2325 11:44:30.583043 [0] AVG Duty = 4922%(X100)
2326 11:44:30.583122
2327 11:44:30.586122 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2328 11:44:30.586202
2329 11:44:30.589894 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2330 11:44:30.593154 [DutyScan_Calibration_Flow] ====Done====
2331 11:44:30.593234
2332 11:44:30.596204 [DutyScan_Calibration_Flow] k_type=2
2333 11:44:30.613074
2334 11:44:30.613155 ==DQ 0 ==
2335 11:44:30.616237 Final DQ duty delay cell = 0
2336 11:44:30.619290 [0] MAX Duty = 5125%(X100), DQS PI = 18
2337 11:44:30.623033 [0] MIN Duty = 4969%(X100), DQS PI = 52
2338 11:44:30.623113 [0] AVG Duty = 5047%(X100)
2339 11:44:30.623176
2340 11:44:30.626298 ==DQ 1 ==
2341 11:44:30.629496 Final DQ duty delay cell = 0
2342 11:44:30.632590 [0] MAX Duty = 5125%(X100), DQS PI = 6
2343 11:44:30.636366 [0] MIN Duty = 4938%(X100), DQS PI = 14
2344 11:44:30.636446 [0] AVG Duty = 5031%(X100)
2345 11:44:30.636510
2346 11:44:30.639626 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2347 11:44:30.642582
2348 11:44:30.645748 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2349 11:44:30.649458 [DutyScan_Calibration_Flow] ====Done====
2350 11:44:30.649539 ==
2351 11:44:30.652420 Dram Type= 6, Freq= 0, CH_1, rank 0
2352 11:44:30.655938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 11:44:30.656054 ==
2354 11:44:30.659319 [Duty_Offset_Calibration]
2355 11:44:30.659428 B0:0 B1:-1 CA:3
2356 11:44:30.659534
2357 11:44:30.662335 [DutyScan_Calibration_Flow] k_type=0
2358 11:44:30.672581
2359 11:44:30.672693 ==CLK 0==
2360 11:44:30.675538 Final CLK duty delay cell = -4
2361 11:44:30.678932 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2362 11:44:30.682057 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2363 11:44:30.685575 [-4] AVG Duty = 4938%(X100)
2364 11:44:30.685679
2365 11:44:30.688459 CH1 CLK Duty spec in!! Max-Min= 124%
2366 11:44:30.692274 [DutyScan_Calibration_Flow] ====Done====
2367 11:44:30.692378
2368 11:44:30.695256 [DutyScan_Calibration_Flow] k_type=1
2369 11:44:30.711042
2370 11:44:30.711123 ==DQS 0 ==
2371 11:44:30.714169 Final DQS duty delay cell = 0
2372 11:44:30.717228 [0] MAX Duty = 5187%(X100), DQS PI = 18
2373 11:44:30.721036 [0] MIN Duty = 4907%(X100), DQS PI = 38
2374 11:44:30.724057 [0] AVG Duty = 5047%(X100)
2375 11:44:30.724140
2376 11:44:30.724206 ==DQS 1 ==
2377 11:44:30.727908 Final DQS duty delay cell = -4
2378 11:44:30.730859 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2379 11:44:30.734002 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2380 11:44:30.737245 [-4] AVG Duty = 4937%(X100)
2381 11:44:30.737326
2382 11:44:30.740551 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2383 11:44:30.740632
2384 11:44:30.744072 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2385 11:44:30.747063 [DutyScan_Calibration_Flow] ====Done====
2386 11:44:30.747144
2387 11:44:30.750664 [DutyScan_Calibration_Flow] k_type=3
2388 11:44:30.767554
2389 11:44:30.767638 ==DQM 0 ==
2390 11:44:30.771063 Final DQM duty delay cell = 0
2391 11:44:30.774549 [0] MAX Duty = 5031%(X100), DQS PI = 28
2392 11:44:30.777462 [0] MIN Duty = 4813%(X100), DQS PI = 38
2393 11:44:30.780935 [0] AVG Duty = 4922%(X100)
2394 11:44:30.781016
2395 11:44:30.781081 ==DQM 1 ==
2396 11:44:30.783883 Final DQM duty delay cell = 0
2397 11:44:30.787498 [0] MAX Duty = 5000%(X100), DQS PI = 34
2398 11:44:30.790867 [0] MIN Duty = 4844%(X100), DQS PI = 0
2399 11:44:30.794322 [0] AVG Duty = 4922%(X100)
2400 11:44:30.794404
2401 11:44:30.797305 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2402 11:44:30.797386
2403 11:44:30.800921 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2404 11:44:30.804236 [DutyScan_Calibration_Flow] ====Done====
2405 11:44:30.804317
2406 11:44:30.807444 [DutyScan_Calibration_Flow] k_type=2
2407 11:44:30.823239
2408 11:44:30.823320 ==DQ 0 ==
2409 11:44:30.826940 Final DQ duty delay cell = -4
2410 11:44:30.830053 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2411 11:44:30.833237 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2412 11:44:30.836834 [-4] AVG Duty = 4937%(X100)
2413 11:44:30.836916
2414 11:44:30.836981 ==DQ 1 ==
2415 11:44:30.840001 Final DQ duty delay cell = 0
2416 11:44:30.843158 [0] MAX Duty = 5031%(X100), DQS PI = 34
2417 11:44:30.846334 [0] MIN Duty = 4844%(X100), DQS PI = 62
2418 11:44:30.850160 [0] AVG Duty = 4937%(X100)
2419 11:44:30.850242
2420 11:44:30.853164 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2421 11:44:30.853260
2422 11:44:30.856341 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2423 11:44:30.859449 [DutyScan_Calibration_Flow] ====Done====
2424 11:44:30.863312 nWR fixed to 30
2425 11:44:30.866547 [ModeRegInit_LP4] CH0 RK0
2426 11:44:30.866628 [ModeRegInit_LP4] CH0 RK1
2427 11:44:30.869622 [ModeRegInit_LP4] CH1 RK0
2428 11:44:30.873400 [ModeRegInit_LP4] CH1 RK1
2429 11:44:30.873482 match AC timing 7
2430 11:44:30.879588 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2431 11:44:30.883147 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2432 11:44:30.886019 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2433 11:44:30.893032 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2434 11:44:30.895975 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2435 11:44:30.896107 ==
2436 11:44:30.899556 Dram Type= 6, Freq= 0, CH_0, rank 0
2437 11:44:30.902547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2438 11:44:30.902631 ==
2439 11:44:30.909527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2440 11:44:30.915876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2441 11:44:30.923506 [CA 0] Center 39 (9~70) winsize 62
2442 11:44:30.927325 [CA 1] Center 39 (9~70) winsize 62
2443 11:44:30.930643 [CA 2] Center 35 (5~66) winsize 62
2444 11:44:30.933776 [CA 3] Center 35 (5~66) winsize 62
2445 11:44:30.937012 [CA 4] Center 33 (3~64) winsize 62
2446 11:44:30.940124 [CA 5] Center 33 (3~64) winsize 62
2447 11:44:30.940198
2448 11:44:30.943979 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2449 11:44:30.944066
2450 11:44:30.947151 [CATrainingPosCal] consider 1 rank data
2451 11:44:30.950327 u2DelayCellTimex100 = 270/100 ps
2452 11:44:30.953506 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2453 11:44:30.960192 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2454 11:44:30.963232 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2455 11:44:30.966969 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2456 11:44:30.970202 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2457 11:44:30.973204 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2458 11:44:30.973285
2459 11:44:30.976522 CA PerBit enable=1, Macro0, CA PI delay=33
2460 11:44:30.976624
2461 11:44:30.980256 [CBTSetCACLKResult] CA Dly = 33
2462 11:44:30.980329 CS Dly: 7 (0~38)
2463 11:44:30.983204 ==
2464 11:44:30.986961 Dram Type= 6, Freq= 0, CH_0, rank 1
2465 11:44:30.990049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 11:44:30.990130 ==
2467 11:44:30.993001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 11:44:30.999602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2469 11:44:31.009433 [CA 0] Center 39 (9~70) winsize 62
2470 11:44:31.012837 [CA 1] Center 39 (9~70) winsize 62
2471 11:44:31.016284 [CA 2] Center 35 (5~66) winsize 62
2472 11:44:31.019487 [CA 3] Center 35 (5~66) winsize 62
2473 11:44:31.022623 [CA 4] Center 34 (4~65) winsize 62
2474 11:44:31.026403 [CA 5] Center 33 (3~63) winsize 61
2475 11:44:31.026507
2476 11:44:31.029596 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2477 11:44:31.029685
2478 11:44:31.032760 [CATrainingPosCal] consider 2 rank data
2479 11:44:31.035908 u2DelayCellTimex100 = 270/100 ps
2480 11:44:31.039172 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2481 11:44:31.046139 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2482 11:44:31.049284 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2483 11:44:31.052305 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 11:44:31.056072 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2485 11:44:31.059133 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2486 11:44:31.059248
2487 11:44:31.062210 CA PerBit enable=1, Macro0, CA PI delay=33
2488 11:44:31.062343
2489 11:44:31.066031 [CBTSetCACLKResult] CA Dly = 33
2490 11:44:31.069124 CS Dly: 8 (0~41)
2491 11:44:31.069263
2492 11:44:31.072302 ----->DramcWriteLeveling(PI) begin...
2493 11:44:31.072448 ==
2494 11:44:31.075496 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 11:44:31.078681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 11:44:31.078824 ==
2497 11:44:31.082324 Write leveling (Byte 0): 33 => 33
2498 11:44:31.085488 Write leveling (Byte 1): 27 => 27
2499 11:44:31.088714 DramcWriteLeveling(PI) end<-----
2500 11:44:31.088822
2501 11:44:31.088917 ==
2502 11:44:31.092523 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 11:44:31.095575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 11:44:31.095682 ==
2505 11:44:31.098457 [Gating] SW mode calibration
2506 11:44:31.105212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2507 11:44:31.111768 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2508 11:44:31.115329 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2509 11:44:31.118309 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2510 11:44:31.124957 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2511 11:44:31.128806 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2512 11:44:31.132057 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2513 11:44:31.138230 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2514 11:44:31.141569 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 11:44:31.145354 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2516 11:44:31.151520 1 0 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2517 11:44:31.155139 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2518 11:44:31.158305 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 11:44:31.165016 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 11:44:31.168674 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 11:44:31.171783 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 11:44:31.178018 1 0 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2523 11:44:31.181764 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2524 11:44:31.184911 1 1 0 | B1->B0 | 2827 4646 | 1 0 | (0 0) (0 0)
2525 11:44:31.191169 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2526 11:44:31.194379 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2527 11:44:31.198218 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2528 11:44:31.204857 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2529 11:44:31.207812 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 11:44:31.211089 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2531 11:44:31.217687 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2532 11:44:31.221167 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2533 11:44:31.224204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2534 11:44:31.231254 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2535 11:44:31.234476 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2536 11:44:31.237635 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2537 11:44:31.243974 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 11:44:31.247656 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 11:44:31.250852 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 11:44:31.257724 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 11:44:31.260930 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 11:44:31.264011 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 11:44:31.267768 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 11:44:31.273930 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:44:31.277686 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:44:31.280868 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2547 11:44:31.287719 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2548 11:44:31.290909 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2549 11:44:31.294079 Total UI for P1: 0, mck2ui 16
2550 11:44:31.297161 best dqsien dly found for B0: ( 1, 3, 26)
2551 11:44:31.300876 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 11:44:31.303966 Total UI for P1: 0, mck2ui 16
2553 11:44:31.307130 best dqsien dly found for B1: ( 1, 4, 0)
2554 11:44:31.310825 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2555 11:44:31.313885 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2556 11:44:31.317492
2557 11:44:31.320448 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2558 11:44:31.323953 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2559 11:44:31.327041 [Gating] SW calibration Done
2560 11:44:31.327164 ==
2561 11:44:31.330408 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 11:44:31.333816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 11:44:31.333935 ==
2564 11:44:31.334031 RX Vref Scan: 0
2565 11:44:31.336733
2566 11:44:31.336846 RX Vref 0 -> 0, step: 1
2567 11:44:31.336940
2568 11:44:31.340499 RX Delay -40 -> 252, step: 8
2569 11:44:31.343649 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2570 11:44:31.346853 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2571 11:44:31.353631 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2572 11:44:31.356675 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2573 11:44:31.360541 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2574 11:44:31.363604 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2575 11:44:31.366932 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2576 11:44:31.373417 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2577 11:44:31.376955 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2578 11:44:31.380050 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2579 11:44:31.383193 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2580 11:44:31.386919 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2581 11:44:31.393099 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2582 11:44:31.396351 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2583 11:44:31.400122 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2584 11:44:31.403216 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2585 11:44:31.403340 ==
2586 11:44:31.406205 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 11:44:31.413053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 11:44:31.413196 ==
2589 11:44:31.413272 DQS Delay:
2590 11:44:31.416244 DQS0 = 0, DQS1 = 0
2591 11:44:31.416371 DQM Delay:
2592 11:44:31.419486 DQM0 = 117, DQM1 = 108
2593 11:44:31.419602 DQ Delay:
2594 11:44:31.423189 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2595 11:44:31.426176 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2596 11:44:31.429737 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2597 11:44:31.432718 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2598 11:44:31.432842
2599 11:44:31.432958
2600 11:44:31.433056 ==
2601 11:44:31.436263 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 11:44:31.439803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 11:44:31.442747 ==
2604 11:44:31.442886
2605 11:44:31.442962
2606 11:44:31.443025 TX Vref Scan disable
2607 11:44:31.446385 == TX Byte 0 ==
2608 11:44:31.449576 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2609 11:44:31.452772 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2610 11:44:31.455978 == TX Byte 1 ==
2611 11:44:31.459607 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2612 11:44:31.463150 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2613 11:44:31.532746 ==
2614 11:44:31.533155 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 11:44:31.533438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 11:44:31.533680 ==
2617 11:44:31.533939 TX Vref=22, minBit 4, minWin=25, winSum=415
2618 11:44:31.534167 TX Vref=24, minBit 4, minWin=25, winSum=419
2619 11:44:31.534363 TX Vref=26, minBit 13, minWin=25, winSum=425
2620 11:44:31.534555 TX Vref=28, minBit 5, minWin=26, winSum=429
2621 11:44:31.534743 TX Vref=30, minBit 5, minWin=26, winSum=433
2622 11:44:31.534930 TX Vref=32, minBit 5, minWin=26, winSum=430
2623 11:44:31.535127 [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 30
2624 11:44:31.535333
2625 11:44:31.535518 Final TX Range 1 Vref 30
2626 11:44:31.535701
2627 11:44:31.535941 ==
2628 11:44:31.536169 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 11:44:31.536387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 11:44:31.536594 ==
2631 11:44:31.536854
2632 11:44:31.537095
2633 11:44:31.537355 TX Vref Scan disable
2634 11:44:31.537621 == TX Byte 0 ==
2635 11:44:31.537843 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2636 11:44:31.538064 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2637 11:44:31.538530 == TX Byte 1 ==
2638 11:44:31.538769 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2639 11:44:31.544010 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2640 11:44:31.544354
2641 11:44:31.544641 [DATLAT]
2642 11:44:31.544868 Freq=1200, CH0 RK0
2643 11:44:31.545076
2644 11:44:31.547676 DATLAT Default: 0xd
2645 11:44:31.547954 0, 0xFFFF, sum = 0
2646 11:44:31.550661 1, 0xFFFF, sum = 0
2647 11:44:31.554377 2, 0xFFFF, sum = 0
2648 11:44:31.554671 3, 0xFFFF, sum = 0
2649 11:44:31.557431 4, 0xFFFF, sum = 0
2650 11:44:31.557649 5, 0xFFFF, sum = 0
2651 11:44:31.560756 6, 0xFFFF, sum = 0
2652 11:44:31.561049 7, 0xFFFF, sum = 0
2653 11:44:31.563818 8, 0xFFFF, sum = 0
2654 11:44:31.564163 9, 0xFFFF, sum = 0
2655 11:44:31.567476 10, 0xFFFF, sum = 0
2656 11:44:31.567695 11, 0xFFFF, sum = 0
2657 11:44:31.570672 12, 0x0, sum = 1
2658 11:44:31.570957 13, 0x0, sum = 2
2659 11:44:31.573791 14, 0x0, sum = 3
2660 11:44:31.574008 15, 0x0, sum = 4
2661 11:44:31.576958 best_step = 13
2662 11:44:31.577173
2663 11:44:31.577346 ==
2664 11:44:31.580586 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 11:44:31.583632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 11:44:31.583849 ==
2667 11:44:31.584023 RX Vref Scan: 1
2668 11:44:31.587170
2669 11:44:31.587486 Set Vref Range= 32 -> 127
2670 11:44:31.587793
2671 11:44:31.590118 RX Vref 32 -> 127, step: 1
2672 11:44:31.590478
2673 11:44:31.593853 RX Delay -21 -> 252, step: 4
2674 11:44:31.594175
2675 11:44:31.597118 Set Vref, RX VrefLevel [Byte0]: 32
2676 11:44:31.600134 [Byte1]: 32
2677 11:44:31.600425
2678 11:44:31.603901 Set Vref, RX VrefLevel [Byte0]: 33
2679 11:44:31.607020 [Byte1]: 33
2680 11:44:31.610701
2681 11:44:31.610931 Set Vref, RX VrefLevel [Byte0]: 34
2682 11:44:31.613876 [Byte1]: 34
2683 11:44:31.618860
2684 11:44:31.619095 Set Vref, RX VrefLevel [Byte0]: 35
2685 11:44:31.622113 [Byte1]: 35
2686 11:44:31.626240
2687 11:44:31.626423 Set Vref, RX VrefLevel [Byte0]: 36
2688 11:44:31.630077 [Byte1]: 36
2689 11:44:31.634572
2690 11:44:31.634841 Set Vref, RX VrefLevel [Byte0]: 37
2691 11:44:31.637683 [Byte1]: 37
2692 11:44:31.642098
2693 11:44:31.642371 Set Vref, RX VrefLevel [Byte0]: 38
2694 11:44:31.645694 [Byte1]: 38
2695 11:44:31.650593
2696 11:44:31.650944 Set Vref, RX VrefLevel [Byte0]: 39
2697 11:44:31.653524 [Byte1]: 39
2698 11:44:31.658178
2699 11:44:31.658454 Set Vref, RX VrefLevel [Byte0]: 40
2700 11:44:31.661288 [Byte1]: 40
2701 11:44:31.666279
2702 11:44:31.666522 Set Vref, RX VrefLevel [Byte0]: 41
2703 11:44:31.669426 [Byte1]: 41
2704 11:44:31.673663
2705 11:44:31.673780 Set Vref, RX VrefLevel [Byte0]: 42
2706 11:44:31.677528 [Byte1]: 42
2707 11:44:31.681790
2708 11:44:31.681909 Set Vref, RX VrefLevel [Byte0]: 43
2709 11:44:31.684917 [Byte1]: 43
2710 11:44:31.689885
2711 11:44:31.690056 Set Vref, RX VrefLevel [Byte0]: 44
2712 11:44:31.692829 [Byte1]: 44
2713 11:44:31.697780
2714 11:44:31.697948 Set Vref, RX VrefLevel [Byte0]: 45
2715 11:44:31.700954 [Byte1]: 45
2716 11:44:31.705346
2717 11:44:31.705494 Set Vref, RX VrefLevel [Byte0]: 46
2718 11:44:31.709084 [Byte1]: 46
2719 11:44:31.713347
2720 11:44:31.713480 Set Vref, RX VrefLevel [Byte0]: 47
2721 11:44:31.717110 [Byte1]: 47
2722 11:44:31.721621
2723 11:44:31.721757 Set Vref, RX VrefLevel [Byte0]: 48
2724 11:44:31.724615 [Byte1]: 48
2725 11:44:31.729544
2726 11:44:31.729722 Set Vref, RX VrefLevel [Byte0]: 49
2727 11:44:31.732766 [Byte1]: 49
2728 11:44:31.737081
2729 11:44:31.737236 Set Vref, RX VrefLevel [Byte0]: 50
2730 11:44:31.740933 [Byte1]: 50
2731 11:44:31.745483
2732 11:44:31.745703 Set Vref, RX VrefLevel [Byte0]: 51
2733 11:44:31.748660 [Byte1]: 51
2734 11:44:31.753514
2735 11:44:31.753677 Set Vref, RX VrefLevel [Byte0]: 52
2736 11:44:31.756357 [Byte1]: 52
2737 11:44:31.761158
2738 11:44:31.761275 Set Vref, RX VrefLevel [Byte0]: 53
2739 11:44:31.764170 [Byte1]: 53
2740 11:44:31.769346
2741 11:44:31.769425 Set Vref, RX VrefLevel [Byte0]: 54
2742 11:44:31.772559 [Byte1]: 54
2743 11:44:31.776826
2744 11:44:31.776930 Set Vref, RX VrefLevel [Byte0]: 55
2745 11:44:31.780534 [Byte1]: 55
2746 11:44:31.784873
2747 11:44:31.784957 Set Vref, RX VrefLevel [Byte0]: 56
2748 11:44:31.788073 [Byte1]: 56
2749 11:44:31.793075
2750 11:44:31.793158 Set Vref, RX VrefLevel [Byte0]: 57
2751 11:44:31.796153 [Byte1]: 57
2752 11:44:31.800960
2753 11:44:31.801050 Set Vref, RX VrefLevel [Byte0]: 58
2754 11:44:31.804163 [Byte1]: 58
2755 11:44:31.808562
2756 11:44:31.808645 Set Vref, RX VrefLevel [Byte0]: 59
2757 11:44:31.811739 [Byte1]: 59
2758 11:44:31.816574
2759 11:44:31.816708 Set Vref, RX VrefLevel [Byte0]: 60
2760 11:44:31.820193 [Byte1]: 60
2761 11:44:31.824557
2762 11:44:31.824684 Set Vref, RX VrefLevel [Byte0]: 61
2763 11:44:31.827665 [Byte1]: 61
2764 11:44:31.832648
2765 11:44:31.832774 Set Vref, RX VrefLevel [Byte0]: 62
2766 11:44:31.835728 [Byte1]: 62
2767 11:44:31.840256
2768 11:44:31.840383 Set Vref, RX VrefLevel [Byte0]: 63
2769 11:44:31.843517 [Byte1]: 63
2770 11:44:31.848589
2771 11:44:31.848695 Set Vref, RX VrefLevel [Byte0]: 64
2772 11:44:31.851618 [Byte1]: 64
2773 11:44:31.855988
2774 11:44:31.856114 Set Vref, RX VrefLevel [Byte0]: 65
2775 11:44:31.859714 [Byte1]: 65
2776 11:44:31.864292
2777 11:44:31.864452 Set Vref, RX VrefLevel [Byte0]: 66
2778 11:44:31.867279 [Byte1]: 66
2779 11:44:31.871932
2780 11:44:31.872052 Set Vref, RX VrefLevel [Byte0]: 67
2781 11:44:31.875514 [Byte1]: 67
2782 11:44:31.880321
2783 11:44:31.880420 Set Vref, RX VrefLevel [Byte0]: 68
2784 11:44:31.883240 [Byte1]: 68
2785 11:44:31.887708
2786 11:44:31.887872 Final RX Vref Byte 0 = 51 to rank0
2787 11:44:31.891498 Final RX Vref Byte 1 = 49 to rank0
2788 11:44:31.894640 Final RX Vref Byte 0 = 51 to rank1
2789 11:44:31.897786 Final RX Vref Byte 1 = 49 to rank1==
2790 11:44:31.900994 Dram Type= 6, Freq= 0, CH_0, rank 0
2791 11:44:31.907790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2792 11:44:31.907938 ==
2793 11:44:31.908075 DQS Delay:
2794 11:44:31.908158 DQS0 = 0, DQS1 = 0
2795 11:44:31.910857 DQM Delay:
2796 11:44:31.910940 DQM0 = 117, DQM1 = 104
2797 11:44:31.914685 DQ Delay:
2798 11:44:31.917664 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2799 11:44:31.920897 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
2800 11:44:31.923961 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =98
2801 11:44:31.927847 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =110
2802 11:44:31.928006
2803 11:44:31.928152
2804 11:44:31.934728 [DQSOSCAuto] RK0, (LSB)MR18= 0xfb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2805 11:44:31.937732 CH0 RK0: MR19=403, MR18=FB
2806 11:44:31.944624 CH0_RK0: MR19=0x403, MR18=0xFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2807 11:44:31.944826
2808 11:44:31.947762 ----->DramcWriteLeveling(PI) begin...
2809 11:44:31.947932 ==
2810 11:44:31.950958 Dram Type= 6, Freq= 0, CH_0, rank 1
2811 11:44:31.954113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2812 11:44:31.954220 ==
2813 11:44:31.957365 Write leveling (Byte 0): 31 => 31
2814 11:44:31.960647 Write leveling (Byte 1): 29 => 29
2815 11:44:31.964436 DramcWriteLeveling(PI) end<-----
2816 11:44:31.964540
2817 11:44:31.964613 ==
2818 11:44:31.967378 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 11:44:31.974074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 11:44:31.974175 ==
2821 11:44:31.974244 [Gating] SW mode calibration
2822 11:44:31.983926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2823 11:44:31.987426 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2824 11:44:31.990318 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2825 11:44:31.996958 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2826 11:44:32.000129 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2827 11:44:32.003995 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2828 11:44:32.010093 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2829 11:44:32.013812 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2830 11:44:32.016939 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2831 11:44:32.023851 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
2832 11:44:32.027064 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2833 11:44:32.030205 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2834 11:44:32.037114 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2835 11:44:32.040140 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2836 11:44:32.043230 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2837 11:44:32.050270 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2838 11:44:32.053523 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2839 11:44:32.056622 1 0 28 | B1->B0 | 2828 4242 | 0 0 | (0 0) (0 0)
2840 11:44:32.063579 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2841 11:44:32.066623 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2842 11:44:32.069827 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2843 11:44:32.076710 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2844 11:44:32.079704 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2845 11:44:32.083312 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2846 11:44:32.089681 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2847 11:44:32.093280 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2848 11:44:32.096214 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2849 11:44:32.102861 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2850 11:44:32.106748 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2851 11:44:32.110002 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2852 11:44:32.116145 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2853 11:44:32.119959 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2854 11:44:32.123065 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2855 11:44:32.129568 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2856 11:44:32.132807 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 11:44:32.135983 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 11:44:32.143003 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 11:44:32.145996 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 11:44:32.149308 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 11:44:32.156155 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 11:44:32.159327 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2863 11:44:32.162515 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2864 11:44:32.166273 Total UI for P1: 0, mck2ui 16
2865 11:44:32.169432 best dqsien dly found for B0: ( 1, 3, 24)
2866 11:44:32.175751 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 11:44:32.175830 Total UI for P1: 0, mck2ui 16
2868 11:44:32.179348 best dqsien dly found for B1: ( 1, 3, 28)
2869 11:44:32.186028 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2870 11:44:32.188891 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2871 11:44:32.188971
2872 11:44:32.192474 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2873 11:44:32.196012 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2874 11:44:32.198971 [Gating] SW calibration Done
2875 11:44:32.199056 ==
2876 11:44:32.202529 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 11:44:32.205607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 11:44:32.205714 ==
2879 11:44:32.209269 RX Vref Scan: 0
2880 11:44:32.209346
2881 11:44:32.209440 RX Vref 0 -> 0, step: 1
2882 11:44:32.209517
2883 11:44:32.212306 RX Delay -40 -> 252, step: 8
2884 11:44:32.215446 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
2885 11:44:32.222010 iDelay=192, Bit 1, Center 119 (48 ~ 191) 144
2886 11:44:32.225789 iDelay=192, Bit 2, Center 111 (40 ~ 183) 144
2887 11:44:32.228959 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
2888 11:44:32.232120 iDelay=192, Bit 4, Center 119 (48 ~ 191) 144
2889 11:44:32.235230 iDelay=192, Bit 5, Center 107 (40 ~ 175) 136
2890 11:44:32.242239 iDelay=192, Bit 6, Center 123 (56 ~ 191) 136
2891 11:44:32.245336 iDelay=192, Bit 7, Center 119 (48 ~ 191) 144
2892 11:44:32.248642 iDelay=192, Bit 8, Center 95 (24 ~ 167) 144
2893 11:44:32.251863 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
2894 11:44:32.255615 iDelay=192, Bit 10, Center 107 (40 ~ 175) 136
2895 11:44:32.261859 iDelay=192, Bit 11, Center 99 (32 ~ 167) 136
2896 11:44:32.265594 iDelay=192, Bit 12, Center 111 (40 ~ 183) 144
2897 11:44:32.268622 iDelay=192, Bit 13, Center 111 (40 ~ 183) 144
2898 11:44:32.271798 iDelay=192, Bit 14, Center 115 (48 ~ 183) 136
2899 11:44:32.274968 iDelay=192, Bit 15, Center 115 (48 ~ 183) 136
2900 11:44:32.278720 ==
2901 11:44:32.281963 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 11:44:32.285179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 11:44:32.285262 ==
2904 11:44:32.285342 DQS Delay:
2905 11:44:32.288268 DQS0 = 0, DQS1 = 0
2906 11:44:32.288365 DQM Delay:
2907 11:44:32.291767 DQM0 = 115, DQM1 = 106
2908 11:44:32.291841 DQ Delay:
2909 11:44:32.295318 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2910 11:44:32.298353 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =119
2911 11:44:32.301934 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2912 11:44:32.304926 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
2913 11:44:32.305008
2914 11:44:32.305087
2915 11:44:32.305161 ==
2916 11:44:32.308490 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 11:44:32.314604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 11:44:32.314684 ==
2919 11:44:32.314776
2920 11:44:32.314853
2921 11:44:32.314948 TX Vref Scan disable
2922 11:44:32.318279 == TX Byte 0 ==
2923 11:44:32.321766 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2924 11:44:32.328318 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2925 11:44:32.328408 == TX Byte 1 ==
2926 11:44:32.331558 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2927 11:44:32.338483 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2928 11:44:32.338582 ==
2929 11:44:32.341565 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 11:44:32.344636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 11:44:32.344743 ==
2932 11:44:32.355998 TX Vref=22, minBit 1, minWin=25, winSum=417
2933 11:44:32.359237 TX Vref=24, minBit 1, minWin=25, winSum=421
2934 11:44:32.362953 TX Vref=26, minBit 2, minWin=26, winSum=424
2935 11:44:32.366124 TX Vref=28, minBit 5, minWin=25, winSum=423
2936 11:44:32.369271 TX Vref=30, minBit 2, minWin=26, winSum=428
2937 11:44:32.372946 TX Vref=32, minBit 4, minWin=26, winSum=426
2938 11:44:32.379288 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 30
2939 11:44:32.379401
2940 11:44:32.382982 Final TX Range 1 Vref 30
2941 11:44:32.383090
2942 11:44:32.383169 ==
2943 11:44:32.386099 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 11:44:32.389226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 11:44:32.389364 ==
2946 11:44:32.392537
2947 11:44:32.392679
2948 11:44:32.392812 TX Vref Scan disable
2949 11:44:32.396151 == TX Byte 0 ==
2950 11:44:32.398925 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2951 11:44:32.405717 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2952 11:44:32.405832 == TX Byte 1 ==
2953 11:44:32.409167 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2954 11:44:32.415595 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2955 11:44:32.415681
2956 11:44:32.415758 [DATLAT]
2957 11:44:32.415828 Freq=1200, CH0 RK1
2958 11:44:32.415889
2959 11:44:32.418916 DATLAT Default: 0xd
2960 11:44:32.419020 0, 0xFFFF, sum = 0
2961 11:44:32.422423 1, 0xFFFF, sum = 0
2962 11:44:32.425514 2, 0xFFFF, sum = 0
2963 11:44:32.425593 3, 0xFFFF, sum = 0
2964 11:44:32.429078 4, 0xFFFF, sum = 0
2965 11:44:32.429183 5, 0xFFFF, sum = 0
2966 11:44:32.432570 6, 0xFFFF, sum = 0
2967 11:44:32.432648 7, 0xFFFF, sum = 0
2968 11:44:32.435495 8, 0xFFFF, sum = 0
2969 11:44:32.435599 9, 0xFFFF, sum = 0
2970 11:44:32.439043 10, 0xFFFF, sum = 0
2971 11:44:32.439152 11, 0xFFFF, sum = 0
2972 11:44:32.442016 12, 0x0, sum = 1
2973 11:44:32.442120 13, 0x0, sum = 2
2974 11:44:32.445814 14, 0x0, sum = 3
2975 11:44:32.445925 15, 0x0, sum = 4
2976 11:44:32.448879 best_step = 13
2977 11:44:32.448991
2978 11:44:32.449087 ==
2979 11:44:32.452197 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 11:44:32.455219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 11:44:32.455297 ==
2982 11:44:32.455371 RX Vref Scan: 0
2983 11:44:32.458974
2984 11:44:32.459078 RX Vref 0 -> 0, step: 1
2985 11:44:32.459161
2986 11:44:32.462112 RX Delay -21 -> 252, step: 4
2987 11:44:32.468469 iDelay=191, Bit 0, Center 114 (51 ~ 178) 128
2988 11:44:32.472133 iDelay=191, Bit 1, Center 116 (47 ~ 186) 140
2989 11:44:32.475428 iDelay=191, Bit 2, Center 110 (43 ~ 178) 136
2990 11:44:32.478584 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
2991 11:44:32.481641 iDelay=191, Bit 4, Center 118 (51 ~ 186) 136
2992 11:44:32.488576 iDelay=191, Bit 5, Center 108 (43 ~ 174) 132
2993 11:44:32.491704 iDelay=191, Bit 6, Center 126 (63 ~ 190) 128
2994 11:44:32.495521 iDelay=191, Bit 7, Center 122 (59 ~ 186) 128
2995 11:44:32.498639 iDelay=191, Bit 8, Center 94 (27 ~ 162) 136
2996 11:44:32.501872 iDelay=191, Bit 9, Center 92 (23 ~ 162) 140
2997 11:44:32.504945 iDelay=191, Bit 10, Center 106 (39 ~ 174) 136
2998 11:44:32.511919 iDelay=191, Bit 11, Center 96 (31 ~ 162) 132
2999 11:44:32.515412 iDelay=191, Bit 12, Center 110 (47 ~ 174) 128
3000 11:44:32.518325 iDelay=191, Bit 13, Center 108 (43 ~ 174) 132
3001 11:44:32.521879 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3002 11:44:32.528196 iDelay=191, Bit 15, Center 112 (47 ~ 178) 132
3003 11:44:32.528282 ==
3004 11:44:32.531731 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 11:44:32.534885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 11:44:32.534969 ==
3007 11:44:32.535035 DQS Delay:
3008 11:44:32.538437 DQS0 = 0, DQS1 = 0
3009 11:44:32.538520 DQM Delay:
3010 11:44:32.541423 DQM0 = 115, DQM1 = 104
3011 11:44:32.541507 DQ Delay:
3012 11:44:32.544485 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3013 11:44:32.548028 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3014 11:44:32.551597 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3015 11:44:32.554709 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =112
3016 11:44:32.554793
3017 11:44:32.554860
3018 11:44:32.564630 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3019 11:44:32.567864 CH0 RK1: MR19=303, MR18=FDFA
3020 11:44:32.571687 CH0_RK1: MR19=0x303, MR18=0xFDFA, DQSOSC=411, MR23=63, INC=38, DEC=25
3021 11:44:32.574880 [RxdqsGatingPostProcess] freq 1200
3022 11:44:32.581244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3023 11:44:32.584455 best DQS0 dly(2T, 0.5T) = (0, 11)
3024 11:44:32.588332 best DQS1 dly(2T, 0.5T) = (0, 12)
3025 11:44:32.591525 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3026 11:44:32.594609 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3027 11:44:32.597724 best DQS0 dly(2T, 0.5T) = (0, 11)
3028 11:44:32.601413 best DQS1 dly(2T, 0.5T) = (0, 11)
3029 11:44:32.604646 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3030 11:44:32.607829 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3031 11:44:32.611050 Pre-setting of DQS Precalculation
3032 11:44:32.614672 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3033 11:44:32.614813 ==
3034 11:44:32.617647 Dram Type= 6, Freq= 0, CH_1, rank 0
3035 11:44:32.621403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 11:44:32.621610 ==
3037 11:44:32.627929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3038 11:44:32.634348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3039 11:44:32.641769 [CA 0] Center 38 (8~68) winsize 61
3040 11:44:32.645326 [CA 1] Center 37 (7~68) winsize 62
3041 11:44:32.648444 [CA 2] Center 35 (6~65) winsize 60
3042 11:44:32.651920 [CA 3] Center 34 (4~64) winsize 61
3043 11:44:32.655624 [CA 4] Center 35 (5~65) winsize 61
3044 11:44:32.658579 [CA 5] Center 33 (3~63) winsize 61
3045 11:44:32.658658
3046 11:44:32.662094 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3047 11:44:32.662201
3048 11:44:32.665363 [CATrainingPosCal] consider 1 rank data
3049 11:44:32.668441 u2DelayCellTimex100 = 270/100 ps
3050 11:44:32.671597 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3051 11:44:32.678421 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3052 11:44:32.681577 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3053 11:44:32.684812 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3054 11:44:32.688016 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3055 11:44:32.691661 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3056 11:44:32.691780
3057 11:44:32.694844 CA PerBit enable=1, Macro0, CA PI delay=33
3058 11:44:32.694944
3059 11:44:32.698035 [CBTSetCACLKResult] CA Dly = 33
3060 11:44:32.701706 CS Dly: 5 (0~36)
3061 11:44:32.701781 ==
3062 11:44:32.704791 Dram Type= 6, Freq= 0, CH_1, rank 1
3063 11:44:32.707890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 11:44:32.707989 ==
3065 11:44:32.714386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 11:44:32.718085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3067 11:44:32.727879 [CA 0] Center 37 (7~68) winsize 62
3068 11:44:32.730900 [CA 1] Center 38 (8~68) winsize 61
3069 11:44:32.734511 [CA 2] Center 34 (4~65) winsize 62
3070 11:44:32.737446 [CA 3] Center 33 (3~64) winsize 62
3071 11:44:32.741108 [CA 4] Center 34 (4~64) winsize 61
3072 11:44:32.744019 [CA 5] Center 33 (3~63) winsize 61
3073 11:44:32.744136
3074 11:44:32.747695 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3075 11:44:32.747812
3076 11:44:32.750555 [CATrainingPosCal] consider 2 rank data
3077 11:44:32.754219 u2DelayCellTimex100 = 270/100 ps
3078 11:44:32.757938 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3079 11:44:32.761010 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3080 11:44:32.767558 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3081 11:44:32.770787 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3082 11:44:32.774051 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3083 11:44:32.777121 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3084 11:44:32.777246
3085 11:44:32.780859 CA PerBit enable=1, Macro0, CA PI delay=33
3086 11:44:32.780988
3087 11:44:32.783972 [CBTSetCACLKResult] CA Dly = 33
3088 11:44:32.784095 CS Dly: 6 (0~39)
3089 11:44:32.787137
3090 11:44:32.790247 ----->DramcWriteLeveling(PI) begin...
3091 11:44:32.790354 ==
3092 11:44:32.793921 Dram Type= 6, Freq= 0, CH_1, rank 0
3093 11:44:32.796979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 11:44:32.797097 ==
3095 11:44:32.800219 Write leveling (Byte 0): 24 => 24
3096 11:44:32.803979 Write leveling (Byte 1): 26 => 26
3097 11:44:32.807238 DramcWriteLeveling(PI) end<-----
3098 11:44:32.807361
3099 11:44:32.807462 ==
3100 11:44:32.810459 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 11:44:32.813608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 11:44:32.813726 ==
3103 11:44:32.816732 [Gating] SW mode calibration
3104 11:44:32.823398 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3105 11:44:32.829897 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3106 11:44:32.833800 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3107 11:44:32.836938 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3108 11:44:32.843630 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3109 11:44:32.846736 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3110 11:44:32.850264 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3111 11:44:32.856741 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3112 11:44:32.859769 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
3113 11:44:32.863451 0 15 28 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (1 0)
3114 11:44:32.870036 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3115 11:44:32.873592 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3116 11:44:32.876807 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3117 11:44:32.883197 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3118 11:44:32.886381 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3119 11:44:32.890219 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3120 11:44:32.896490 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3121 11:44:32.899631 1 0 28 | B1->B0 | 3d3d 4545 | 0 0 | (1 1) (0 0)
3122 11:44:32.903339 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3123 11:44:32.909728 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3124 11:44:32.912901 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3125 11:44:32.916604 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3126 11:44:32.923074 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3127 11:44:32.926298 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3128 11:44:32.929320 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3129 11:44:32.935995 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3130 11:44:32.939756 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3131 11:44:32.942943 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3132 11:44:32.949470 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3133 11:44:32.952590 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3134 11:44:32.956176 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3135 11:44:32.959082 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3136 11:44:32.966192 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3137 11:44:32.969295 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3138 11:44:32.972967 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 11:44:32.979564 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 11:44:32.982586 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 11:44:32.985828 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 11:44:32.992684 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 11:44:32.995869 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 11:44:32.999057 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:44:33.005978 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3146 11:44:33.009191 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 11:44:33.012348 Total UI for P1: 0, mck2ui 16
3148 11:44:33.016152 best dqsien dly found for B0: ( 1, 3, 28)
3149 11:44:33.019249 Total UI for P1: 0, mck2ui 16
3150 11:44:33.022501 best dqsien dly found for B1: ( 1, 3, 28)
3151 11:44:33.025542 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3152 11:44:33.028756 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3153 11:44:33.028869
3154 11:44:33.032379 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3155 11:44:33.035765 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3156 11:44:33.038819 [Gating] SW calibration Done
3157 11:44:33.038933 ==
3158 11:44:33.042577 Dram Type= 6, Freq= 0, CH_1, rank 0
3159 11:44:33.048848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 11:44:33.048973 ==
3161 11:44:33.049071 RX Vref Scan: 0
3162 11:44:33.049174
3163 11:44:33.051855 RX Vref 0 -> 0, step: 1
3164 11:44:33.051982
3165 11:44:33.055522 RX Delay -40 -> 252, step: 8
3166 11:44:33.059125 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3167 11:44:33.062045 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3168 11:44:33.065469 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3169 11:44:33.069052 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3170 11:44:33.075573 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3171 11:44:33.078537 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3172 11:44:33.082241 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3173 11:44:33.085215 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3174 11:44:33.088723 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3175 11:44:33.095586 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3176 11:44:33.098597 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3177 11:44:33.101687 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3178 11:44:33.105389 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3179 11:44:33.108580 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3180 11:44:33.115511 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3181 11:44:33.118768 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3182 11:44:33.118852 ==
3183 11:44:33.121873 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 11:44:33.125020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 11:44:33.125170 ==
3186 11:44:33.128917 DQS Delay:
3187 11:44:33.129013 DQS0 = 0, DQS1 = 0
3188 11:44:33.129081 DQM Delay:
3189 11:44:33.131953 DQM0 = 114, DQM1 = 112
3190 11:44:33.132044 DQ Delay:
3191 11:44:33.135073 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3192 11:44:33.138769 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3193 11:44:33.141717 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3194 11:44:33.148594 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3195 11:44:33.148679
3196 11:44:33.148747
3197 11:44:33.148808 ==
3198 11:44:33.151669 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 11:44:33.155504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 11:44:33.155587 ==
3201 11:44:33.155654
3202 11:44:33.155715
3203 11:44:33.158596 TX Vref Scan disable
3204 11:44:33.158722 == TX Byte 0 ==
3205 11:44:33.165283 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3206 11:44:33.168856 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3207 11:44:33.169037 == TX Byte 1 ==
3208 11:44:33.175012 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3209 11:44:33.178594 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3210 11:44:33.178735 ==
3211 11:44:33.181858 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 11:44:33.184804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 11:44:33.184947 ==
3214 11:44:33.197976 TX Vref=22, minBit 9, minWin=23, winSum=405
3215 11:44:33.201280 TX Vref=24, minBit 9, minWin=24, winSum=411
3216 11:44:33.204440 TX Vref=26, minBit 8, minWin=24, winSum=418
3217 11:44:33.207578 TX Vref=28, minBit 9, minWin=24, winSum=419
3218 11:44:33.211417 TX Vref=30, minBit 9, minWin=24, winSum=425
3219 11:44:33.217620 TX Vref=32, minBit 9, minWin=24, winSum=425
3220 11:44:33.220792 [TxChooseVref] Worse bit 9, Min win 24, Win sum 425, Final Vref 30
3221 11:44:33.220992
3222 11:44:33.223980 Final TX Range 1 Vref 30
3223 11:44:33.224133
3224 11:44:33.224253 ==
3225 11:44:33.227787 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 11:44:33.230925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 11:44:33.234107 ==
3228 11:44:33.234245
3229 11:44:33.234333
3230 11:44:33.234410 TX Vref Scan disable
3231 11:44:33.237279 == TX Byte 0 ==
3232 11:44:33.240955 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3233 11:44:33.247589 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3234 11:44:33.247733 == TX Byte 1 ==
3235 11:44:33.250814 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3236 11:44:33.257202 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3237 11:44:33.257318
3238 11:44:33.257410 [DATLAT]
3239 11:44:33.257494 Freq=1200, CH1 RK0
3240 11:44:33.257577
3241 11:44:33.261104 DATLAT Default: 0xd
3242 11:44:33.261230 0, 0xFFFF, sum = 0
3243 11:44:33.264320 1, 0xFFFF, sum = 0
3244 11:44:33.267378 2, 0xFFFF, sum = 0
3245 11:44:33.267519 3, 0xFFFF, sum = 0
3246 11:44:33.270438 4, 0xFFFF, sum = 0
3247 11:44:33.270585 5, 0xFFFF, sum = 0
3248 11:44:33.274061 6, 0xFFFF, sum = 0
3249 11:44:33.274226 7, 0xFFFF, sum = 0
3250 11:44:33.277615 8, 0xFFFF, sum = 0
3251 11:44:33.277805 9, 0xFFFF, sum = 0
3252 11:44:33.280489 10, 0xFFFF, sum = 0
3253 11:44:33.280682 11, 0xFFFF, sum = 0
3254 11:44:33.283976 12, 0x0, sum = 1
3255 11:44:33.284227 13, 0x0, sum = 2
3256 11:44:33.287151 14, 0x0, sum = 3
3257 11:44:33.287421 15, 0x0, sum = 4
3258 11:44:33.290615 best_step = 13
3259 11:44:33.290880
3260 11:44:33.291147 ==
3261 11:44:33.293734 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 11:44:33.297226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 11:44:33.297312 ==
3264 11:44:33.297399 RX Vref Scan: 1
3265 11:44:33.300798
3266 11:44:33.300883 Set Vref Range= 32 -> 127
3267 11:44:33.300972
3268 11:44:33.303849 RX Vref 32 -> 127, step: 1
3269 11:44:33.303951
3270 11:44:33.307104 RX Delay -13 -> 252, step: 4
3271 11:44:33.307188
3272 11:44:33.310180 Set Vref, RX VrefLevel [Byte0]: 32
3273 11:44:33.313890 [Byte1]: 32
3274 11:44:33.313974
3275 11:44:33.317156 Set Vref, RX VrefLevel [Byte0]: 33
3276 11:44:33.320252 [Byte1]: 33
3277 11:44:33.324023
3278 11:44:33.324154 Set Vref, RX VrefLevel [Byte0]: 34
3279 11:44:33.327200 [Byte1]: 34
3280 11:44:33.331556
3281 11:44:33.331646 Set Vref, RX VrefLevel [Byte0]: 35
3282 11:44:33.335447 [Byte1]: 35
3283 11:44:33.339743
3284 11:44:33.339856 Set Vref, RX VrefLevel [Byte0]: 36
3285 11:44:33.342832 [Byte1]: 36
3286 11:44:33.347792
3287 11:44:33.347961 Set Vref, RX VrefLevel [Byte0]: 37
3288 11:44:33.350648 [Byte1]: 37
3289 11:44:33.355610
3290 11:44:33.355795 Set Vref, RX VrefLevel [Byte0]: 38
3291 11:44:33.358755 [Byte1]: 38
3292 11:44:33.363034
3293 11:44:33.363226 Set Vref, RX VrefLevel [Byte0]: 39
3294 11:44:33.366878 [Byte1]: 39
3295 11:44:33.371464
3296 11:44:33.371633 Set Vref, RX VrefLevel [Byte0]: 40
3297 11:44:33.374641 [Byte1]: 40
3298 11:44:33.378835
3299 11:44:33.378918 Set Vref, RX VrefLevel [Byte0]: 41
3300 11:44:33.382667 [Byte1]: 41
3301 11:44:33.387349
3302 11:44:33.387442 Set Vref, RX VrefLevel [Byte0]: 42
3303 11:44:33.390270 [Byte1]: 42
3304 11:44:33.394889
3305 11:44:33.394989 Set Vref, RX VrefLevel [Byte0]: 43
3306 11:44:33.398614 [Byte1]: 43
3307 11:44:33.402752
3308 11:44:33.402871 Set Vref, RX VrefLevel [Byte0]: 44
3309 11:44:33.405771 [Byte1]: 44
3310 11:44:33.410698
3311 11:44:33.410861 Set Vref, RX VrefLevel [Byte0]: 45
3312 11:44:33.417226 [Byte1]: 45
3313 11:44:33.417398
3314 11:44:33.420478 Set Vref, RX VrefLevel [Byte0]: 46
3315 11:44:33.424083 [Byte1]: 46
3316 11:44:33.424321
3317 11:44:33.427296 Set Vref, RX VrefLevel [Byte0]: 47
3318 11:44:33.430342 [Byte1]: 47
3319 11:44:33.434708
3320 11:44:33.434890 Set Vref, RX VrefLevel [Byte0]: 48
3321 11:44:33.437797 [Byte1]: 48
3322 11:44:33.442301
3323 11:44:33.442483 Set Vref, RX VrefLevel [Byte0]: 49
3324 11:44:33.445436 [Byte1]: 49
3325 11:44:33.450394
3326 11:44:33.450662 Set Vref, RX VrefLevel [Byte0]: 50
3327 11:44:33.453289 [Byte1]: 50
3328 11:44:33.458065
3329 11:44:33.458248 Set Vref, RX VrefLevel [Byte0]: 51
3330 11:44:33.461048 [Byte1]: 51
3331 11:44:33.466049
3332 11:44:33.466264 Set Vref, RX VrefLevel [Byte0]: 52
3333 11:44:33.469168 [Byte1]: 52
3334 11:44:33.473601
3335 11:44:33.473774 Set Vref, RX VrefLevel [Byte0]: 53
3336 11:44:33.477308 [Byte1]: 53
3337 11:44:33.481758
3338 11:44:33.481841 Set Vref, RX VrefLevel [Byte0]: 54
3339 11:44:33.484882 [Byte1]: 54
3340 11:44:33.489054
3341 11:44:33.489137 Set Vref, RX VrefLevel [Byte0]: 55
3342 11:44:33.492644 [Byte1]: 55
3343 11:44:33.497592
3344 11:44:33.497674 Set Vref, RX VrefLevel [Byte0]: 56
3345 11:44:33.500529 [Byte1]: 56
3346 11:44:33.505407
3347 11:44:33.505513 Set Vref, RX VrefLevel [Byte0]: 57
3348 11:44:33.508489 [Byte1]: 57
3349 11:44:33.513225
3350 11:44:33.513332 Set Vref, RX VrefLevel [Byte0]: 58
3351 11:44:33.516411 [Byte1]: 58
3352 11:44:33.520910
3353 11:44:33.520990 Set Vref, RX VrefLevel [Byte0]: 59
3354 11:44:33.524175 [Byte1]: 59
3355 11:44:33.529129
3356 11:44:33.529208 Set Vref, RX VrefLevel [Byte0]: 60
3357 11:44:33.532276 [Byte1]: 60
3358 11:44:33.536598
3359 11:44:33.536689 Set Vref, RX VrefLevel [Byte0]: 61
3360 11:44:33.540184 [Byte1]: 61
3361 11:44:33.544547
3362 11:44:33.544625 Set Vref, RX VrefLevel [Byte0]: 62
3363 11:44:33.547628 [Byte1]: 62
3364 11:44:33.552771
3365 11:44:33.552851 Set Vref, RX VrefLevel [Byte0]: 63
3366 11:44:33.555805 [Byte1]: 63
3367 11:44:33.560382
3368 11:44:33.560463 Set Vref, RX VrefLevel [Byte0]: 64
3369 11:44:33.563503 [Byte1]: 64
3370 11:44:33.568418
3371 11:44:33.568497 Set Vref, RX VrefLevel [Byte0]: 65
3372 11:44:33.571667 [Byte1]: 65
3373 11:44:33.576155
3374 11:44:33.576235 Final RX Vref Byte 0 = 53 to rank0
3375 11:44:33.579168 Final RX Vref Byte 1 = 49 to rank0
3376 11:44:33.582947 Final RX Vref Byte 0 = 53 to rank1
3377 11:44:33.586060 Final RX Vref Byte 1 = 49 to rank1==
3378 11:44:33.589205 Dram Type= 6, Freq= 0, CH_1, rank 0
3379 11:44:33.595941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3380 11:44:33.596056 ==
3381 11:44:33.596125 DQS Delay:
3382 11:44:33.596188 DQS0 = 0, DQS1 = 0
3383 11:44:33.599507 DQM Delay:
3384 11:44:33.599588 DQM0 = 115, DQM1 = 112
3385 11:44:33.602460 DQ Delay:
3386 11:44:33.606086 DQ0 =122, DQ1 =110, DQ2 =106, DQ3 =114
3387 11:44:33.609172 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3388 11:44:33.612717 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
3389 11:44:33.615754 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3390 11:44:33.615836
3391 11:44:33.615901
3392 11:44:33.626115 [DQSOSCAuto] RK0, (LSB)MR18= 0xf501, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 414 ps
3393 11:44:33.626199 CH1 RK0: MR19=304, MR18=F501
3394 11:44:33.632261 CH1_RK0: MR19=0x304, MR18=0xF501, DQSOSC=409, MR23=63, INC=39, DEC=26
3395 11:44:33.632343
3396 11:44:33.636061 ----->DramcWriteLeveling(PI) begin...
3397 11:44:33.636159 ==
3398 11:44:33.639279 Dram Type= 6, Freq= 0, CH_1, rank 1
3399 11:44:33.645553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3400 11:44:33.645636 ==
3401 11:44:33.648675 Write leveling (Byte 0): 25 => 25
3402 11:44:33.648787 Write leveling (Byte 1): 30 => 30
3403 11:44:33.652596 DramcWriteLeveling(PI) end<-----
3404 11:44:33.652678
3405 11:44:33.655578 ==
3406 11:44:33.658791 Dram Type= 6, Freq= 0, CH_1, rank 1
3407 11:44:33.662556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 11:44:33.662638 ==
3409 11:44:33.665388 [Gating] SW mode calibration
3410 11:44:33.672136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3411 11:44:33.675159 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3412 11:44:33.682105 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3413 11:44:33.685332 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3414 11:44:33.688433 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3415 11:44:33.695338 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3416 11:44:33.698597 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3417 11:44:33.701680 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3418 11:44:33.708252 0 15 24 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
3419 11:44:33.711842 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
3420 11:44:33.714784 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3421 11:44:33.721895 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3422 11:44:33.725011 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3423 11:44:33.728518 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3424 11:44:33.734991 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3425 11:44:33.738064 1 0 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
3426 11:44:33.741846 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3427 11:44:33.748165 1 0 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3428 11:44:33.751856 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3429 11:44:33.755010 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3430 11:44:33.761313 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3431 11:44:33.765037 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3432 11:44:33.768080 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3433 11:44:33.774865 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3434 11:44:33.778055 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3435 11:44:33.781080 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3436 11:44:33.787936 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3437 11:44:33.791085 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3438 11:44:33.794310 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3439 11:44:33.801145 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3440 11:44:33.804242 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3441 11:44:33.807553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3442 11:44:33.814271 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3443 11:44:33.817645 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3444 11:44:33.821025 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3445 11:44:33.827632 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 11:44:33.830570 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 11:44:33.834219 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 11:44:33.840759 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 11:44:33.843945 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3450 11:44:33.847773 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3451 11:44:33.850801 Total UI for P1: 0, mck2ui 16
3452 11:44:33.853937 best dqsien dly found for B0: ( 1, 3, 20)
3453 11:44:33.857094 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3454 11:44:33.863858 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 11:44:33.866953 Total UI for P1: 0, mck2ui 16
3456 11:44:33.870601 best dqsien dly found for B1: ( 1, 3, 28)
3457 11:44:33.873625 best DQS0 dly(MCK, UI, PI) = (1, 3, 20)
3458 11:44:33.876783 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3459 11:44:33.876917
3460 11:44:33.880427 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 20)
3461 11:44:33.883698 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3462 11:44:33.886725 [Gating] SW calibration Done
3463 11:44:33.886920 ==
3464 11:44:33.889912 Dram Type= 6, Freq= 0, CH_1, rank 1
3465 11:44:33.893634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3466 11:44:33.896699 ==
3467 11:44:33.896889 RX Vref Scan: 0
3468 11:44:33.896980
3469 11:44:33.899827 RX Vref 0 -> 0, step: 1
3470 11:44:33.900024
3471 11:44:33.903004 RX Delay -40 -> 252, step: 8
3472 11:44:33.906808 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3473 11:44:33.909998 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3474 11:44:33.913055 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3475 11:44:33.916277 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3476 11:44:33.923036 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3477 11:44:33.926127 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3478 11:44:33.929737 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3479 11:44:33.933025 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3480 11:44:33.935865 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3481 11:44:33.943107 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3482 11:44:33.946068 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3483 11:44:33.949620 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3484 11:44:33.952624 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3485 11:44:33.955868 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3486 11:44:33.962876 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3487 11:44:33.966048 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3488 11:44:33.966132 ==
3489 11:44:33.969220 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 11:44:33.972402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 11:44:33.972510 ==
3492 11:44:33.975393 DQS Delay:
3493 11:44:33.975501 DQS0 = 0, DQS1 = 0
3494 11:44:33.975604 DQM Delay:
3495 11:44:33.978973 DQM0 = 115, DQM1 = 111
3496 11:44:33.979083 DQ Delay:
3497 11:44:33.982137 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3498 11:44:33.989060 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3499 11:44:33.992249 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3500 11:44:33.995338 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3501 11:44:33.995455
3502 11:44:33.995523
3503 11:44:33.995596 ==
3504 11:44:33.998512 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 11:44:34.002203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 11:44:34.002285 ==
3507 11:44:34.002372
3508 11:44:34.002437
3509 11:44:34.005342 TX Vref Scan disable
3510 11:44:34.008419 == TX Byte 0 ==
3511 11:44:34.012204 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3512 11:44:34.015299 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3513 11:44:34.018534 == TX Byte 1 ==
3514 11:44:34.021715 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3515 11:44:34.024899 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3516 11:44:34.025030 ==
3517 11:44:34.028611 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 11:44:34.034888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 11:44:34.035104 ==
3520 11:44:34.045669 TX Vref=22, minBit 3, minWin=25, winSum=418
3521 11:44:34.048568 TX Vref=24, minBit 1, minWin=26, winSum=424
3522 11:44:34.052164 TX Vref=26, minBit 3, minWin=26, winSum=428
3523 11:44:34.055111 TX Vref=28, minBit 3, minWin=26, winSum=430
3524 11:44:34.058669 TX Vref=30, minBit 3, minWin=26, winSum=433
3525 11:44:34.065215 TX Vref=32, minBit 9, minWin=26, winSum=434
3526 11:44:34.068364 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32
3527 11:44:34.068519
3528 11:44:34.072091 Final TX Range 1 Vref 32
3529 11:44:34.072247
3530 11:44:34.072353 ==
3531 11:44:34.075085 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 11:44:34.078337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 11:44:34.081999 ==
3534 11:44:34.082162
3535 11:44:34.082286
3536 11:44:34.082397 TX Vref Scan disable
3537 11:44:34.085036 == TX Byte 0 ==
3538 11:44:34.088628 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3539 11:44:34.094893 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3540 11:44:34.095008 == TX Byte 1 ==
3541 11:44:34.098659 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3542 11:44:34.104897 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3543 11:44:34.104983
3544 11:44:34.105050 [DATLAT]
3545 11:44:34.105112 Freq=1200, CH1 RK1
3546 11:44:34.105174
3547 11:44:34.108587 DATLAT Default: 0xd
3548 11:44:34.111765 0, 0xFFFF, sum = 0
3549 11:44:34.111851 1, 0xFFFF, sum = 0
3550 11:44:34.114871 2, 0xFFFF, sum = 0
3551 11:44:34.114957 3, 0xFFFF, sum = 0
3552 11:44:34.118048 4, 0xFFFF, sum = 0
3553 11:44:34.118134 5, 0xFFFF, sum = 0
3554 11:44:34.121188 6, 0xFFFF, sum = 0
3555 11:44:34.121273 7, 0xFFFF, sum = 0
3556 11:44:34.124342 8, 0xFFFF, sum = 0
3557 11:44:34.124496 9, 0xFFFF, sum = 0
3558 11:44:34.128168 10, 0xFFFF, sum = 0
3559 11:44:34.128256 11, 0xFFFF, sum = 0
3560 11:44:34.131157 12, 0x0, sum = 1
3561 11:44:34.131243 13, 0x0, sum = 2
3562 11:44:34.134249 14, 0x0, sum = 3
3563 11:44:34.134335 15, 0x0, sum = 4
3564 11:44:34.137451 best_step = 13
3565 11:44:34.137536
3566 11:44:34.137603 ==
3567 11:44:34.141231 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 11:44:34.144106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 11:44:34.144195 ==
3570 11:44:34.147788 RX Vref Scan: 0
3571 11:44:34.147872
3572 11:44:34.147974 RX Vref 0 -> 0, step: 1
3573 11:44:34.148075
3574 11:44:34.150753 RX Delay -13 -> 252, step: 4
3575 11:44:34.157305 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3576 11:44:34.160421 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3577 11:44:34.164023 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3578 11:44:34.166977 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3579 11:44:34.173811 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3580 11:44:34.177044 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3581 11:44:34.180162 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3582 11:44:34.183920 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3583 11:44:34.186864 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3584 11:44:34.193704 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3585 11:44:34.196799 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3586 11:44:34.199851 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3587 11:44:34.203035 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3588 11:44:34.210092 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3589 11:44:34.213267 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3590 11:44:34.216486 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3591 11:44:34.216573 ==
3592 11:44:34.219613 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 11:44:34.222782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 11:44:34.222923 ==
3595 11:44:34.226048 DQS Delay:
3596 11:44:34.226165 DQS0 = 0, DQS1 = 0
3597 11:44:34.229719 DQM Delay:
3598 11:44:34.229805 DQM0 = 115, DQM1 = 111
3599 11:44:34.229871 DQ Delay:
3600 11:44:34.236462 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3601 11:44:34.239642 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =114
3602 11:44:34.242866 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3603 11:44:34.246052 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3604 11:44:34.246140
3605 11:44:34.246212
3606 11:44:34.252650 [DQSOSCAuto] RK1, (LSB)MR18= 0xf305, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3607 11:44:34.256106 CH1 RK1: MR19=304, MR18=F305
3608 11:44:34.262753 CH1_RK1: MR19=0x304, MR18=0xF305, DQSOSC=408, MR23=63, INC=39, DEC=26
3609 11:44:34.265922 [RxdqsGatingPostProcess] freq 1200
3610 11:44:34.272452 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3611 11:44:34.275577 best DQS0 dly(2T, 0.5T) = (0, 11)
3612 11:44:34.278653 best DQS1 dly(2T, 0.5T) = (0, 11)
3613 11:44:34.282434 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3614 11:44:34.285668 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3615 11:44:34.285752 best DQS0 dly(2T, 0.5T) = (0, 11)
3616 11:44:34.288619 best DQS1 dly(2T, 0.5T) = (0, 11)
3617 11:44:34.292368 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3618 11:44:34.295371 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3619 11:44:34.298469 Pre-setting of DQS Precalculation
3620 11:44:34.305276 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3621 11:44:34.312173 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3622 11:44:34.318534 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3623 11:44:34.318618
3624 11:44:34.318685
3625 11:44:34.321687 [Calibration Summary] 2400 Mbps
3626 11:44:34.324888 CH 0, Rank 0
3627 11:44:34.324972 SW Impedance : PASS
3628 11:44:34.327960 DUTY Scan : NO K
3629 11:44:34.328073 ZQ Calibration : PASS
3630 11:44:34.331808 Jitter Meter : NO K
3631 11:44:34.335002 CBT Training : PASS
3632 11:44:34.335085 Write leveling : PASS
3633 11:44:34.338092 RX DQS gating : PASS
3634 11:44:34.341210 RX DQ/DQS(RDDQC) : PASS
3635 11:44:34.341319 TX DQ/DQS : PASS
3636 11:44:34.345039 RX DATLAT : PASS
3637 11:44:34.348130 RX DQ/DQS(Engine): PASS
3638 11:44:34.348222 TX OE : NO K
3639 11:44:34.351235 All Pass.
3640 11:44:34.351372
3641 11:44:34.351463 CH 0, Rank 1
3642 11:44:34.354364 SW Impedance : PASS
3643 11:44:34.354525 DUTY Scan : NO K
3644 11:44:34.357678 ZQ Calibration : PASS
3645 11:44:34.361190 Jitter Meter : NO K
3646 11:44:34.361351 CBT Training : PASS
3647 11:44:34.364793 Write leveling : PASS
3648 11:44:34.367640 RX DQS gating : PASS
3649 11:44:34.367810 RX DQ/DQS(RDDQC) : PASS
3650 11:44:34.371274 TX DQ/DQS : PASS
3651 11:44:34.374211 RX DATLAT : PASS
3652 11:44:34.374413 RX DQ/DQS(Engine): PASS
3653 11:44:34.377811 TX OE : NO K
3654 11:44:34.378020 All Pass.
3655 11:44:34.378213
3656 11:44:34.380750 CH 1, Rank 0
3657 11:44:34.380996 SW Impedance : PASS
3658 11:44:34.383761 DUTY Scan : NO K
3659 11:44:34.387443 ZQ Calibration : PASS
3660 11:44:34.387550 Jitter Meter : NO K
3661 11:44:34.390540 CBT Training : PASS
3662 11:44:34.393637 Write leveling : PASS
3663 11:44:34.393751 RX DQS gating : PASS
3664 11:44:34.397320 RX DQ/DQS(RDDQC) : PASS
3665 11:44:34.400458 TX DQ/DQS : PASS
3666 11:44:34.400541 RX DATLAT : PASS
3667 11:44:34.403610 RX DQ/DQS(Engine): PASS
3668 11:44:34.407175 TX OE : NO K
3669 11:44:34.407270 All Pass.
3670 11:44:34.407346
3671 11:44:34.407416 CH 1, Rank 1
3672 11:44:34.410376 SW Impedance : PASS
3673 11:44:34.413812 DUTY Scan : NO K
3674 11:44:34.413914 ZQ Calibration : PASS
3675 11:44:34.416818 Jitter Meter : NO K
3676 11:44:34.420043 CBT Training : PASS
3677 11:44:34.420126 Write leveling : PASS
3678 11:44:34.423804 RX DQS gating : PASS
3679 11:44:34.423886 RX DQ/DQS(RDDQC) : PASS
3680 11:44:34.427016 TX DQ/DQS : PASS
3681 11:44:34.430177 RX DATLAT : PASS
3682 11:44:34.430259 RX DQ/DQS(Engine): PASS
3683 11:44:34.433305 TX OE : NO K
3684 11:44:34.433387 All Pass.
3685 11:44:34.433453
3686 11:44:34.436488 DramC Write-DBI off
3687 11:44:34.440250 PER_BANK_REFRESH: Hybrid Mode
3688 11:44:34.440372 TX_TRACKING: ON
3689 11:44:34.449803 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3690 11:44:34.453094 [FAST_K] Save calibration result to emmc
3691 11:44:34.456325 dramc_set_vcore_voltage set vcore to 650000
3692 11:44:34.459939 Read voltage for 600, 5
3693 11:44:34.460086 Vio18 = 0
3694 11:44:34.463140 Vcore = 650000
3695 11:44:34.463245 Vdram = 0
3696 11:44:34.463317 Vddq = 0
3697 11:44:34.463407 Vmddr = 0
3698 11:44:34.469730 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3699 11:44:34.476249 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3700 11:44:34.476428 MEM_TYPE=3, freq_sel=19
3701 11:44:34.479258 sv_algorithm_assistance_LP4_1600
3702 11:44:34.482913 ============ PULL DRAM RESETB DOWN ============
3703 11:44:34.489507 ========== PULL DRAM RESETB DOWN end =========
3704 11:44:34.492336 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3705 11:44:34.496048 ===================================
3706 11:44:34.498896 LPDDR4 DRAM CONFIGURATION
3707 11:44:34.502567 ===================================
3708 11:44:34.502648 EX_ROW_EN[0] = 0x0
3709 11:44:34.505753 EX_ROW_EN[1] = 0x0
3710 11:44:34.508819 LP4Y_EN = 0x0
3711 11:44:34.508900 WORK_FSP = 0x0
3712 11:44:34.511966 WL = 0x2
3713 11:44:34.512094 RL = 0x2
3714 11:44:34.515147 BL = 0x2
3715 11:44:34.515216 RPST = 0x0
3716 11:44:34.518967 RD_PRE = 0x0
3717 11:44:34.519065 WR_PRE = 0x1
3718 11:44:34.522159 WR_PST = 0x0
3719 11:44:34.522240 DBI_WR = 0x0
3720 11:44:34.525373 DBI_RD = 0x0
3721 11:44:34.525454 OTF = 0x1
3722 11:44:34.528604 ===================================
3723 11:44:34.531650 ===================================
3724 11:44:34.534887 ANA top config
3725 11:44:34.538654 ===================================
3726 11:44:34.541860 DLL_ASYNC_EN = 0
3727 11:44:34.541941 ALL_SLAVE_EN = 1
3728 11:44:34.544957 NEW_RANK_MODE = 1
3729 11:44:34.548501 DLL_IDLE_MODE = 1
3730 11:44:34.551661 LP45_APHY_COMB_EN = 1
3731 11:44:34.554831 TX_ODT_DIS = 1
3732 11:44:34.554912 NEW_8X_MODE = 1
3733 11:44:34.557915 ===================================
3734 11:44:34.561709 ===================================
3735 11:44:34.564781 data_rate = 1200
3736 11:44:34.567943 CKR = 1
3737 11:44:34.570979 DQ_P2S_RATIO = 8
3738 11:44:34.574668 ===================================
3739 11:44:34.577700 CA_P2S_RATIO = 8
3740 11:44:34.581098 DQ_CA_OPEN = 0
3741 11:44:34.581180 DQ_SEMI_OPEN = 0
3742 11:44:34.584069 CA_SEMI_OPEN = 0
3743 11:44:34.587640 CA_FULL_RATE = 0
3744 11:44:34.590638 DQ_CKDIV4_EN = 1
3745 11:44:34.594286 CA_CKDIV4_EN = 1
3746 11:44:34.597859 CA_PREDIV_EN = 0
3747 11:44:34.597940 PH8_DLY = 0
3748 11:44:34.600816 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3749 11:44:34.603935 DQ_AAMCK_DIV = 4
3750 11:44:34.607426 CA_AAMCK_DIV = 4
3751 11:44:34.610584 CA_ADMCK_DIV = 4
3752 11:44:34.614179 DQ_TRACK_CA_EN = 0
3753 11:44:34.617490 CA_PICK = 600
3754 11:44:34.617601 CA_MCKIO = 600
3755 11:44:34.620605 MCKIO_SEMI = 0
3756 11:44:34.623745 PLL_FREQ = 2288
3757 11:44:34.626842 DQ_UI_PI_RATIO = 32
3758 11:44:34.630475 CA_UI_PI_RATIO = 0
3759 11:44:34.633637 ===================================
3760 11:44:34.636783 ===================================
3761 11:44:34.640014 memory_type:LPDDR4
3762 11:44:34.640136 GP_NUM : 10
3763 11:44:34.643758 SRAM_EN : 1
3764 11:44:34.643839 MD32_EN : 0
3765 11:44:34.646891 ===================================
3766 11:44:34.650053 [ANA_INIT] >>>>>>>>>>>>>>
3767 11:44:34.653620 <<<<<< [CONFIGURE PHASE]: ANA_TX
3768 11:44:34.656836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3769 11:44:34.659911 ===================================
3770 11:44:34.663105 data_rate = 1200,PCW = 0X5800
3771 11:44:34.666298 ===================================
3772 11:44:34.670090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3773 11:44:34.676364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3774 11:44:34.679520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3775 11:44:34.686114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3776 11:44:34.689698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3777 11:44:34.692589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3778 11:44:34.692670 [ANA_INIT] flow start
3779 11:44:34.696212 [ANA_INIT] PLL >>>>>>>>
3780 11:44:34.699220 [ANA_INIT] PLL <<<<<<<<
3781 11:44:34.702904 [ANA_INIT] MIDPI >>>>>>>>
3782 11:44:34.703003 [ANA_INIT] MIDPI <<<<<<<<
3783 11:44:34.705957 [ANA_INIT] DLL >>>>>>>>
3784 11:44:34.708931 [ANA_INIT] flow end
3785 11:44:34.712486 ============ LP4 DIFF to SE enter ============
3786 11:44:34.716153 ============ LP4 DIFF to SE exit ============
3787 11:44:34.719041 [ANA_INIT] <<<<<<<<<<<<<
3788 11:44:34.722222 [Flow] Enable top DCM control >>>>>
3789 11:44:34.726128 [Flow] Enable top DCM control <<<<<
3790 11:44:34.729369 Enable DLL master slave shuffle
3791 11:44:34.732607 ==============================================================
3792 11:44:34.735729 Gating Mode config
3793 11:44:34.742087 ==============================================================
3794 11:44:34.742169 Config description:
3795 11:44:34.752089 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3796 11:44:34.758670 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3797 11:44:34.764947 SELPH_MODE 0: By rank 1: By Phase
3798 11:44:34.768781 ==============================================================
3799 11:44:34.771888 GAT_TRACK_EN = 1
3800 11:44:34.775197 RX_GATING_MODE = 2
3801 11:44:34.778270 RX_GATING_TRACK_MODE = 2
3802 11:44:34.781453 SELPH_MODE = 1
3803 11:44:34.784641 PICG_EARLY_EN = 1
3804 11:44:34.788339 VALID_LAT_VALUE = 1
3805 11:44:34.791426 ==============================================================
3806 11:44:34.795014 Enter into Gating configuration >>>>
3807 11:44:34.797930 Exit from Gating configuration <<<<
3808 11:44:34.801533 Enter into DVFS_PRE_config >>>>>
3809 11:44:34.814733 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3810 11:44:34.817742 Exit from DVFS_PRE_config <<<<<
3811 11:44:34.821148 Enter into PICG configuration >>>>
3812 11:44:34.824798 Exit from PICG configuration <<<<
3813 11:44:34.824896 [RX_INPUT] configuration >>>>>
3814 11:44:34.827818 [RX_INPUT] configuration <<<<<
3815 11:44:34.834629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3816 11:44:34.837810 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3817 11:44:34.844159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3818 11:44:34.851151 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3819 11:44:34.857567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3820 11:44:34.864299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3821 11:44:34.867473 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3822 11:44:34.870660 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3823 11:44:34.876979 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3824 11:44:34.880178 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3825 11:44:34.884060 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3826 11:44:34.890309 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3827 11:44:34.893514 ===================================
3828 11:44:34.893599 LPDDR4 DRAM CONFIGURATION
3829 11:44:34.896657 ===================================
3830 11:44:34.900295 EX_ROW_EN[0] = 0x0
3831 11:44:34.900379 EX_ROW_EN[1] = 0x0
3832 11:44:34.903269 LP4Y_EN = 0x0
3833 11:44:34.906892 WORK_FSP = 0x0
3834 11:44:34.906979 WL = 0x2
3835 11:44:34.910000 RL = 0x2
3836 11:44:34.910117 BL = 0x2
3837 11:44:34.913531 RPST = 0x0
3838 11:44:34.913646 RD_PRE = 0x0
3839 11:44:34.916518 WR_PRE = 0x1
3840 11:44:34.916628 WR_PST = 0x0
3841 11:44:34.920278 DBI_WR = 0x0
3842 11:44:34.920440 DBI_RD = 0x0
3843 11:44:34.923140 OTF = 0x1
3844 11:44:34.926655 ===================================
3845 11:44:34.929617 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3846 11:44:34.933074 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3847 11:44:34.939885 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 11:44:34.943122 ===================================
3849 11:44:34.943223 LPDDR4 DRAM CONFIGURATION
3850 11:44:34.946276 ===================================
3851 11:44:34.950054 EX_ROW_EN[0] = 0x10
3852 11:44:34.950154 EX_ROW_EN[1] = 0x0
3853 11:44:34.953224 LP4Y_EN = 0x0
3854 11:44:34.956267 WORK_FSP = 0x0
3855 11:44:34.956351 WL = 0x2
3856 11:44:34.959557 RL = 0x2
3857 11:44:34.959641 BL = 0x2
3858 11:44:34.962653 RPST = 0x0
3859 11:44:34.962738 RD_PRE = 0x0
3860 11:44:34.966242 WR_PRE = 0x1
3861 11:44:34.966323 WR_PST = 0x0
3862 11:44:34.969147 DBI_WR = 0x0
3863 11:44:34.969228 DBI_RD = 0x0
3864 11:44:34.973067 OTF = 0x1
3865 11:44:34.976181 ===================================
3866 11:44:34.982451 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3867 11:44:34.985589 nWR fixed to 30
3868 11:44:34.985674 [ModeRegInit_LP4] CH0 RK0
3869 11:44:34.989395 [ModeRegInit_LP4] CH0 RK1
3870 11:44:34.992614 [ModeRegInit_LP4] CH1 RK0
3871 11:44:34.995751 [ModeRegInit_LP4] CH1 RK1
3872 11:44:34.995835 match AC timing 17
3873 11:44:35.002081 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3874 11:44:35.005901 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3875 11:44:35.008828 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3876 11:44:35.015560 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3877 11:44:35.018557 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3878 11:44:35.018642 ==
3879 11:44:35.022052 Dram Type= 6, Freq= 0, CH_0, rank 0
3880 11:44:35.025072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3881 11:44:35.025157 ==
3882 11:44:35.032112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3883 11:44:35.038681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3884 11:44:35.041634 [CA 0] Center 36 (6~67) winsize 62
3885 11:44:35.044782 [CA 1] Center 35 (5~66) winsize 62
3886 11:44:35.048550 [CA 2] Center 34 (4~65) winsize 62
3887 11:44:35.051727 [CA 3] Center 34 (4~65) winsize 62
3888 11:44:35.054886 [CA 4] Center 33 (3~64) winsize 62
3889 11:44:35.058083 [CA 5] Center 33 (3~64) winsize 62
3890 11:44:35.058168
3891 11:44:35.061826 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3892 11:44:35.061911
3893 11:44:35.065050 [CATrainingPosCal] consider 1 rank data
3894 11:44:35.068251 u2DelayCellTimex100 = 270/100 ps
3895 11:44:35.071686 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3896 11:44:35.074837 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3897 11:44:35.077887 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3898 11:44:35.081775 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3899 11:44:35.084877 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3900 11:44:35.091194 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3901 11:44:35.091279
3902 11:44:35.094277 CA PerBit enable=1, Macro0, CA PI delay=33
3903 11:44:35.094362
3904 11:44:35.098012 [CBTSetCACLKResult] CA Dly = 33
3905 11:44:35.098096 CS Dly: 4 (0~35)
3906 11:44:35.098181 ==
3907 11:44:35.101210 Dram Type= 6, Freq= 0, CH_0, rank 1
3908 11:44:35.107547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3909 11:44:35.107639 ==
3910 11:44:35.111229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3911 11:44:35.117297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3912 11:44:35.120752 [CA 0] Center 36 (6~67) winsize 62
3913 11:44:35.124386 [CA 1] Center 36 (6~67) winsize 62
3914 11:44:35.127384 [CA 2] Center 34 (4~65) winsize 62
3915 11:44:35.130334 [CA 3] Center 34 (4~65) winsize 62
3916 11:44:35.133974 [CA 4] Center 34 (3~65) winsize 63
3917 11:44:35.137508 [CA 5] Center 33 (3~64) winsize 62
3918 11:44:35.137593
3919 11:44:35.140421 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3920 11:44:35.140511
3921 11:44:35.144120 [CATrainingPosCal] consider 2 rank data
3922 11:44:35.147070 u2DelayCellTimex100 = 270/100 ps
3923 11:44:35.150209 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3924 11:44:35.156905 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3925 11:44:35.159935 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3926 11:44:35.163785 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3927 11:44:35.166963 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3928 11:44:35.170131 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3929 11:44:35.170216
3930 11:44:35.173242 CA PerBit enable=1, Macro0, CA PI delay=33
3931 11:44:35.173326
3932 11:44:35.176829 [CBTSetCACLKResult] CA Dly = 33
3933 11:44:35.180162 CS Dly: 5 (0~37)
3934 11:44:35.180246
3935 11:44:35.183129 ----->DramcWriteLeveling(PI) begin...
3936 11:44:35.183257 ==
3937 11:44:35.186281 Dram Type= 6, Freq= 0, CH_0, rank 0
3938 11:44:35.190003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3939 11:44:35.190116 ==
3940 11:44:35.193184 Write leveling (Byte 0): 33 => 33
3941 11:44:35.196247 Write leveling (Byte 1): 32 => 32
3942 11:44:35.199496 DramcWriteLeveling(PI) end<-----
3943 11:44:35.199580
3944 11:44:35.199665 ==
3945 11:44:35.203158 Dram Type= 6, Freq= 0, CH_0, rank 0
3946 11:44:35.206228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3947 11:44:35.206313 ==
3948 11:44:35.209505 [Gating] SW mode calibration
3949 11:44:35.216332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3950 11:44:35.222652 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3951 11:44:35.226108 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3952 11:44:35.229451 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3953 11:44:35.236174 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3954 11:44:35.238997 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3955 11:44:35.242711 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3956 11:44:35.249038 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3957 11:44:35.252053 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3958 11:44:35.255810 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3959 11:44:35.262383 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3960 11:44:35.265493 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3961 11:44:35.268509 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3962 11:44:35.275432 0 10 12 | B1->B0 | 2a2a 2d2d | 0 0 | (1 1) (0 0)
3963 11:44:35.278627 0 10 16 | B1->B0 | 3838 4141 | 0 0 | (0 0) (0 0)
3964 11:44:35.281536 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3965 11:44:35.288357 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3966 11:44:35.291657 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3967 11:44:35.298026 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3968 11:44:35.301785 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3969 11:44:35.304894 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3970 11:44:35.311801 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3971 11:44:35.314794 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3972 11:44:35.317886 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3973 11:44:35.324840 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3974 11:44:35.328049 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3975 11:44:35.331056 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3976 11:44:35.338032 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3977 11:44:35.340881 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3978 11:44:35.344514 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3979 11:44:35.350881 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3980 11:44:35.354667 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 11:44:35.357471 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 11:44:35.364195 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 11:44:35.367670 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 11:44:35.370737 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 11:44:35.377511 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 11:44:35.380831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 11:44:35.383820 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3988 11:44:35.387407 Total UI for P1: 0, mck2ui 16
3989 11:44:35.390365 best dqsien dly found for B0: ( 0, 13, 14)
3990 11:44:35.393547 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 11:44:35.396805 Total UI for P1: 0, mck2ui 16
3992 11:44:35.400455 best dqsien dly found for B1: ( 0, 13, 16)
3993 11:44:35.406745 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
3994 11:44:35.410536 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
3995 11:44:35.410638
3996 11:44:35.413578 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
3997 11:44:35.416754 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
3998 11:44:35.419838 [Gating] SW calibration Done
3999 11:44:35.419935 ==
4000 11:44:35.423654 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 11:44:35.426906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 11:44:35.427007 ==
4003 11:44:35.429980 RX Vref Scan: 0
4004 11:44:35.430076
4005 11:44:35.430165 RX Vref 0 -> 0, step: 1
4006 11:44:35.430255
4007 11:44:35.433189 RX Delay -230 -> 252, step: 16
4008 11:44:35.439917 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4009 11:44:35.443079 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4010 11:44:35.446088 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4011 11:44:35.449473 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4012 11:44:35.456626 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4013 11:44:35.459489 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4014 11:44:35.462665 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4015 11:44:35.466262 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4016 11:44:35.469113 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4017 11:44:35.476137 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4018 11:44:35.479107 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4019 11:44:35.482733 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4020 11:44:35.485980 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4021 11:44:35.492497 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4022 11:44:35.495614 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4023 11:44:35.499310 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4024 11:44:35.499408 ==
4025 11:44:35.502494 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 11:44:35.505691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 11:44:35.508840 ==
4028 11:44:35.508922 DQS Delay:
4029 11:44:35.508987 DQS0 = 0, DQS1 = 0
4030 11:44:35.512598 DQM Delay:
4031 11:44:35.512680 DQM0 = 42, DQM1 = 36
4032 11:44:35.515711 DQ Delay:
4033 11:44:35.518816 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4034 11:44:35.518914 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4035 11:44:35.522597 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4036 11:44:35.529030 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4037 11:44:35.529113
4038 11:44:35.529178
4039 11:44:35.529239 ==
4040 11:44:35.532242 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 11:44:35.535418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 11:44:35.535536 ==
4043 11:44:35.535601
4044 11:44:35.535661
4045 11:44:35.538595 TX Vref Scan disable
4046 11:44:35.538692 == TX Byte 0 ==
4047 11:44:35.545573 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4048 11:44:35.548681 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4049 11:44:35.548763 == TX Byte 1 ==
4050 11:44:35.555116 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4051 11:44:35.558628 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4052 11:44:35.558712 ==
4053 11:44:35.561646 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 11:44:35.565206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 11:44:35.565288 ==
4056 11:44:35.568026
4057 11:44:35.568143
4058 11:44:35.568208 TX Vref Scan disable
4059 11:44:35.571771 == TX Byte 0 ==
4060 11:44:35.575418 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4061 11:44:35.582165 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4062 11:44:35.582287 == TX Byte 1 ==
4063 11:44:35.584884 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4064 11:44:35.591837 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4065 11:44:35.591916
4066 11:44:35.591998 [DATLAT]
4067 11:44:35.592095 Freq=600, CH0 RK0
4068 11:44:35.592183
4069 11:44:35.594813 DATLAT Default: 0x9
4070 11:44:35.598675 0, 0xFFFF, sum = 0
4071 11:44:35.598804 1, 0xFFFF, sum = 0
4072 11:44:35.601712 2, 0xFFFF, sum = 0
4073 11:44:35.601795 3, 0xFFFF, sum = 0
4074 11:44:35.604829 4, 0xFFFF, sum = 0
4075 11:44:35.604912 5, 0xFFFF, sum = 0
4076 11:44:35.607906 6, 0xFFFF, sum = 0
4077 11:44:35.608016 7, 0xFFFF, sum = 0
4078 11:44:35.611669 8, 0x0, sum = 1
4079 11:44:35.611752 9, 0x0, sum = 2
4080 11:44:35.614859 10, 0x0, sum = 3
4081 11:44:35.614943 11, 0x0, sum = 4
4082 11:44:35.615011 best_step = 9
4083 11:44:35.615073
4084 11:44:35.618070 ==
4085 11:44:35.621145 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 11:44:35.624852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 11:44:35.624934 ==
4088 11:44:35.625000 RX Vref Scan: 1
4089 11:44:35.625061
4090 11:44:35.627910 RX Vref 0 -> 0, step: 1
4091 11:44:35.628012
4092 11:44:35.631043 RX Delay -179 -> 252, step: 8
4093 11:44:35.631117
4094 11:44:35.634194 Set Vref, RX VrefLevel [Byte0]: 51
4095 11:44:35.637926 [Byte1]: 49
4096 11:44:35.637998
4097 11:44:35.641114 Final RX Vref Byte 0 = 51 to rank0
4098 11:44:35.644231 Final RX Vref Byte 1 = 49 to rank0
4099 11:44:35.647523 Final RX Vref Byte 0 = 51 to rank1
4100 11:44:35.651247 Final RX Vref Byte 1 = 49 to rank1==
4101 11:44:35.654332 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 11:44:35.657584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 11:44:35.660767 ==
4104 11:44:35.660838 DQS Delay:
4105 11:44:35.660900 DQS0 = 0, DQS1 = 0
4106 11:44:35.664267 DQM Delay:
4107 11:44:35.664341 DQM0 = 42, DQM1 = 33
4108 11:44:35.667666 DQ Delay:
4109 11:44:35.667747 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4110 11:44:35.670669 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4111 11:44:35.674134 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4112 11:44:35.677134 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4113 11:44:35.680854
4114 11:44:35.680934
4115 11:44:35.687363 [DQSOSCAuto] RK0, (LSB)MR18= 0x473e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4116 11:44:35.690351 CH0 RK0: MR19=808, MR18=473E
4117 11:44:35.696952 CH0_RK0: MR19=0x808, MR18=0x473E, DQSOSC=396, MR23=63, INC=167, DEC=111
4118 11:44:35.697032
4119 11:44:35.700344 ----->DramcWriteLeveling(PI) begin...
4120 11:44:35.700419 ==
4121 11:44:35.703827 Dram Type= 6, Freq= 0, CH_0, rank 1
4122 11:44:35.707292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 11:44:35.707370 ==
4124 11:44:35.710402 Write leveling (Byte 0): 34 => 34
4125 11:44:35.713988 Write leveling (Byte 1): 29 => 29
4126 11:44:35.717082 DramcWriteLeveling(PI) end<-----
4127 11:44:35.717159
4128 11:44:35.717230 ==
4129 11:44:35.720454 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 11:44:35.723601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 11:44:35.723674 ==
4132 11:44:35.726907 [Gating] SW mode calibration
4133 11:44:35.733254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4134 11:44:35.739744 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4135 11:44:35.743455 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4136 11:44:35.749643 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4137 11:44:35.752856 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4138 11:44:35.755898 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4139 11:44:35.762869 0 9 16 | B1->B0 | 2b2b 2525 | 1 0 | (1 0) (0 0)
4140 11:44:35.766049 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4141 11:44:35.769154 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4142 11:44:35.776260 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4143 11:44:35.779192 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4144 11:44:35.782525 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4145 11:44:35.789072 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4146 11:44:35.792816 0 10 12 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
4147 11:44:35.795782 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4148 11:44:35.802433 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4149 11:44:35.805961 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4150 11:44:35.808906 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4151 11:44:35.815713 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4152 11:44:35.818567 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4153 11:44:35.822250 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4154 11:44:35.828581 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4155 11:44:35.831784 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4156 11:44:35.835565 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4157 11:44:35.841821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4158 11:44:35.844993 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4159 11:44:35.848152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4160 11:44:35.855150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4161 11:44:35.858336 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4162 11:44:35.861514 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4163 11:44:35.868343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4164 11:44:35.871512 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 11:44:35.874631 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 11:44:35.881663 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 11:44:35.884681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 11:44:35.887713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 11:44:35.894565 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4170 11:44:35.897615 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4171 11:44:35.901165 Total UI for P1: 0, mck2ui 16
4172 11:44:35.904741 best dqsien dly found for B0: ( 0, 13, 8)
4173 11:44:35.907656 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4174 11:44:35.914111 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:44:35.917681 Total UI for P1: 0, mck2ui 16
4176 11:44:35.920634 best dqsien dly found for B1: ( 0, 13, 14)
4177 11:44:35.924038 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4178 11:44:35.927209 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4179 11:44:35.927280
4180 11:44:35.930473 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4181 11:44:35.933658 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4182 11:44:35.937459 [Gating] SW calibration Done
4183 11:44:35.937541 ==
4184 11:44:35.940578 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 11:44:35.943643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 11:44:35.943725 ==
4187 11:44:35.947358 RX Vref Scan: 0
4188 11:44:35.947440
4189 11:44:35.950621 RX Vref 0 -> 0, step: 1
4190 11:44:35.950702
4191 11:44:35.950768 RX Delay -230 -> 252, step: 16
4192 11:44:35.956805 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4193 11:44:35.960480 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4194 11:44:35.963582 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4195 11:44:35.967049 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4196 11:44:35.973214 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4197 11:44:35.976513 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4198 11:44:35.980162 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4199 11:44:35.983258 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4200 11:44:35.989741 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4201 11:44:35.993435 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4202 11:44:35.996437 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4203 11:44:35.999454 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4204 11:44:36.006302 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4205 11:44:36.009386 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4206 11:44:36.012834 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4207 11:44:36.015791 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4208 11:44:36.015874 ==
4209 11:44:36.019238 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 11:44:36.026013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:44:36.026096 ==
4212 11:44:36.026162 DQS Delay:
4213 11:44:36.029412 DQS0 = 0, DQS1 = 0
4214 11:44:36.029494 DQM Delay:
4215 11:44:36.032241 DQM0 = 44, DQM1 = 34
4216 11:44:36.032323 DQ Delay:
4217 11:44:36.035729 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4218 11:44:36.038909 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =49
4219 11:44:36.042241 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4220 11:44:36.045326 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4221 11:44:36.045408
4222 11:44:36.045473
4223 11:44:36.045533 ==
4224 11:44:36.049159 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 11:44:36.052189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 11:44:36.052276 ==
4227 11:44:36.052342
4228 11:44:36.052402
4229 11:44:36.055399 TX Vref Scan disable
4230 11:44:36.058535 == TX Byte 0 ==
4231 11:44:36.062189 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4232 11:44:36.065428 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4233 11:44:36.068570 == TX Byte 1 ==
4234 11:44:36.071696 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4235 11:44:36.075484 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4236 11:44:36.075566 ==
4237 11:44:36.078670 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 11:44:36.084823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 11:44:36.084905 ==
4240 11:44:36.084970
4241 11:44:36.085030
4242 11:44:36.085087 TX Vref Scan disable
4243 11:44:36.090004 == TX Byte 0 ==
4244 11:44:36.093154 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4245 11:44:36.099924 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4246 11:44:36.100006 == TX Byte 1 ==
4247 11:44:36.103092 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4248 11:44:36.109621 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4249 11:44:36.109720
4250 11:44:36.109799 [DATLAT]
4251 11:44:36.109858 Freq=600, CH0 RK1
4252 11:44:36.109917
4253 11:44:36.112475 DATLAT Default: 0x9
4254 11:44:36.116265 0, 0xFFFF, sum = 0
4255 11:44:36.116353 1, 0xFFFF, sum = 0
4256 11:44:36.119385 2, 0xFFFF, sum = 0
4257 11:44:36.119466 3, 0xFFFF, sum = 0
4258 11:44:36.122565 4, 0xFFFF, sum = 0
4259 11:44:36.122676 5, 0xFFFF, sum = 0
4260 11:44:36.126027 6, 0xFFFF, sum = 0
4261 11:44:36.126100 7, 0xFFFF, sum = 0
4262 11:44:36.129021 8, 0x0, sum = 1
4263 11:44:36.129091 9, 0x0, sum = 2
4264 11:44:36.132121 10, 0x0, sum = 3
4265 11:44:36.132200 11, 0x0, sum = 4
4266 11:44:36.132266 best_step = 9
4267 11:44:36.132325
4268 11:44:36.135676 ==
4269 11:44:36.139180 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 11:44:36.142318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 11:44:36.142400 ==
4272 11:44:36.142465 RX Vref Scan: 0
4273 11:44:36.142526
4274 11:44:36.145399 RX Vref 0 -> 0, step: 1
4275 11:44:36.145481
4276 11:44:36.149090 RX Delay -195 -> 252, step: 8
4277 11:44:36.155625 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4278 11:44:36.158607 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4279 11:44:36.161776 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4280 11:44:36.165448 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4281 11:44:36.171775 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4282 11:44:36.175143 iDelay=197, Bit 5, Center 32 (-115 ~ 180) 296
4283 11:44:36.178725 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4284 11:44:36.181835 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4285 11:44:36.184993 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4286 11:44:36.191925 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4287 11:44:36.195082 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4288 11:44:36.198306 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4289 11:44:36.201401 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4290 11:44:36.207948 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4291 11:44:36.211175 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4292 11:44:36.214859 iDelay=197, Bit 15, Center 44 (-107 ~ 196) 304
4293 11:44:36.214954 ==
4294 11:44:36.217928 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 11:44:36.221320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 11:44:36.224444 ==
4297 11:44:36.224523 DQS Delay:
4298 11:44:36.224586 DQS0 = 0, DQS1 = 0
4299 11:44:36.228180 DQM Delay:
4300 11:44:36.228259 DQM0 = 41, DQM1 = 34
4301 11:44:36.231198 DQ Delay:
4302 11:44:36.234440 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4303 11:44:36.234524 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4304 11:44:36.238173 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4305 11:44:36.244689 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4306 11:44:36.244768
4307 11:44:36.244830
4308 11:44:36.251353 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4309 11:44:36.254582 CH0 RK1: MR19=808, MR18=3E3A
4310 11:44:36.260787 CH0_RK1: MR19=0x808, MR18=0x3E3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4311 11:44:36.264561 [RxdqsGatingPostProcess] freq 600
4312 11:44:36.267740 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4313 11:44:36.270819 Pre-setting of DQS Precalculation
4314 11:44:36.277163 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4315 11:44:36.277243 ==
4316 11:44:36.280944 Dram Type= 6, Freq= 0, CH_1, rank 0
4317 11:44:36.284080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 11:44:36.284160 ==
4319 11:44:36.290279 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4320 11:44:36.297334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4321 11:44:36.300511 [CA 0] Center 36 (6~66) winsize 61
4322 11:44:36.303695 [CA 1] Center 36 (6~66) winsize 61
4323 11:44:36.307329 [CA 2] Center 35 (5~65) winsize 61
4324 11:44:36.310232 [CA 3] Center 34 (4~64) winsize 61
4325 11:44:36.313416 [CA 4] Center 34 (4~65) winsize 62
4326 11:44:36.316559 [CA 5] Center 33 (3~64) winsize 62
4327 11:44:36.316638
4328 11:44:36.320337 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4329 11:44:36.320417
4330 11:44:36.323533 [CATrainingPosCal] consider 1 rank data
4331 11:44:36.326413 u2DelayCellTimex100 = 270/100 ps
4332 11:44:36.329898 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4333 11:44:36.333454 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4334 11:44:36.336568 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4335 11:44:36.340021 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4336 11:44:36.343268 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4337 11:44:36.346173 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4338 11:44:36.349713
4339 11:44:36.353169 CA PerBit enable=1, Macro0, CA PI delay=33
4340 11:44:36.353250
4341 11:44:36.356125 [CBTSetCACLKResult] CA Dly = 33
4342 11:44:36.356243 CS Dly: 3 (0~34)
4343 11:44:36.356347 ==
4344 11:44:36.359888 Dram Type= 6, Freq= 0, CH_1, rank 1
4345 11:44:36.363085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 11:44:36.363196 ==
4347 11:44:36.369369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 11:44:36.376335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4349 11:44:36.379524 [CA 0] Center 36 (6~66) winsize 61
4350 11:44:36.382621 [CA 1] Center 35 (5~66) winsize 62
4351 11:44:36.386227 [CA 2] Center 34 (4~65) winsize 62
4352 11:44:36.389387 [CA 3] Center 33 (3~64) winsize 62
4353 11:44:36.392693 [CA 4] Center 33 (3~64) winsize 62
4354 11:44:36.395891 [CA 5] Center 33 (3~64) winsize 62
4355 11:44:36.396002
4356 11:44:36.399587 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4357 11:44:36.399672
4358 11:44:36.402671 [CATrainingPosCal] consider 2 rank data
4359 11:44:36.405758 u2DelayCellTimex100 = 270/100 ps
4360 11:44:36.409025 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4361 11:44:36.412635 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4362 11:44:36.415715 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4363 11:44:36.422557 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4364 11:44:36.425644 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4365 11:44:36.428789 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 11:44:36.428875
4367 11:44:36.432572 CA PerBit enable=1, Macro0, CA PI delay=33
4368 11:44:36.432657
4369 11:44:36.435581 [CBTSetCACLKResult] CA Dly = 33
4370 11:44:36.435666 CS Dly: 4 (0~36)
4371 11:44:36.435769
4372 11:44:36.438595 ----->DramcWriteLeveling(PI) begin...
4373 11:44:36.442168 ==
4374 11:44:36.445681 Dram Type= 6, Freq= 0, CH_1, rank 0
4375 11:44:36.448666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 11:44:36.448752 ==
4377 11:44:36.452286 Write leveling (Byte 0): 29 => 29
4378 11:44:36.455223 Write leveling (Byte 1): 30 => 30
4379 11:44:36.458631 DramcWriteLeveling(PI) end<-----
4380 11:44:36.458721
4381 11:44:36.458805 ==
4382 11:44:36.462047 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 11:44:36.464976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 11:44:36.465062 ==
4385 11:44:36.468465 [Gating] SW mode calibration
4386 11:44:36.474788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4387 11:44:36.481756 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4388 11:44:36.484860 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4389 11:44:36.488004 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4390 11:44:36.495190 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4391 11:44:36.498306 0 9 12 | B1->B0 | 3030 3131 | 1 0 | (1 0) (0 1)
4392 11:44:36.501335 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4393 11:44:36.508344 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4394 11:44:36.511572 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4395 11:44:36.514678 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4396 11:44:36.521273 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4397 11:44:36.524470 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4398 11:44:36.527517 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4399 11:44:36.534572 0 10 12 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
4400 11:44:36.537606 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4401 11:44:36.540776 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4402 11:44:36.547551 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4403 11:44:36.550613 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4404 11:44:36.553996 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 11:44:36.560654 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4406 11:44:36.563575 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4407 11:44:36.567153 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4408 11:44:36.573637 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4409 11:44:36.577157 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4410 11:44:36.580296 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4411 11:44:36.587147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4412 11:44:36.590499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4413 11:44:36.593550 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4414 11:44:36.600283 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4415 11:44:36.603487 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4416 11:44:36.606693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4417 11:44:36.613125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 11:44:36.616296 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 11:44:36.619420 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 11:44:36.626307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 11:44:36.629423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 11:44:36.632501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:44:36.639454 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4424 11:44:36.642628 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:44:36.645755 Total UI for P1: 0, mck2ui 16
4426 11:44:36.648924 best dqsien dly found for B0: ( 0, 13, 12)
4427 11:44:36.652723 Total UI for P1: 0, mck2ui 16
4428 11:44:36.655908 best dqsien dly found for B1: ( 0, 13, 12)
4429 11:44:36.658815 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4430 11:44:36.662322 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4431 11:44:36.662420
4432 11:44:36.665422 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4433 11:44:36.672455 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4434 11:44:36.672530 [Gating] SW calibration Done
4435 11:44:36.672593 ==
4436 11:44:36.675463 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 11:44:36.681794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 11:44:36.681875 ==
4439 11:44:36.681939 RX Vref Scan: 0
4440 11:44:36.681999
4441 11:44:36.685157 RX Vref 0 -> 0, step: 1
4442 11:44:36.685228
4443 11:44:36.688946 RX Delay -230 -> 252, step: 16
4444 11:44:36.692003 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4445 11:44:36.695142 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4446 11:44:36.701552 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4447 11:44:36.705325 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4448 11:44:36.708509 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4449 11:44:36.711692 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4450 11:44:36.714997 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4451 11:44:36.721327 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4452 11:44:36.725144 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4453 11:44:36.728093 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4454 11:44:36.731116 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4455 11:44:36.738057 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4456 11:44:36.741185 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4457 11:44:36.744943 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4458 11:44:36.748104 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4459 11:44:36.754355 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4460 11:44:36.754473 ==
4461 11:44:36.757600 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 11:44:36.761330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 11:44:36.761409 ==
4464 11:44:36.761472 DQS Delay:
4465 11:44:36.764380 DQS0 = 0, DQS1 = 0
4466 11:44:36.764448 DQM Delay:
4467 11:44:36.767345 DQM0 = 42, DQM1 = 38
4468 11:44:36.767426 DQ Delay:
4469 11:44:36.770950 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4470 11:44:36.774029 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4471 11:44:36.777700 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4472 11:44:36.780496 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4473 11:44:36.780570
4474 11:44:36.780632
4475 11:44:36.780690 ==
4476 11:44:36.783976 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 11:44:36.790703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 11:44:36.790781 ==
4479 11:44:36.790845
4480 11:44:36.790903
4481 11:44:36.790959 TX Vref Scan disable
4482 11:44:36.793970 == TX Byte 0 ==
4483 11:44:36.797539 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4484 11:44:36.803798 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4485 11:44:36.803920 == TX Byte 1 ==
4486 11:44:36.806866 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4487 11:44:36.813717 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4488 11:44:36.813828 ==
4489 11:44:36.817023 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 11:44:36.820146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 11:44:36.820221 ==
4492 11:44:36.820293
4493 11:44:36.820352
4494 11:44:36.823637 TX Vref Scan disable
4495 11:44:36.826784 == TX Byte 0 ==
4496 11:44:36.829785 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4497 11:44:36.833483 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4498 11:44:36.836508 == TX Byte 1 ==
4499 11:44:36.840240 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4500 11:44:36.843412 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4501 11:44:36.843489
4502 11:44:36.846572 [DATLAT]
4503 11:44:36.846673 Freq=600, CH1 RK0
4504 11:44:36.846764
4505 11:44:36.849757 DATLAT Default: 0x9
4506 11:44:36.849855 0, 0xFFFF, sum = 0
4507 11:44:36.852803 1, 0xFFFF, sum = 0
4508 11:44:36.852909 2, 0xFFFF, sum = 0
4509 11:44:36.856610 3, 0xFFFF, sum = 0
4510 11:44:36.856718 4, 0xFFFF, sum = 0
4511 11:44:36.859695 5, 0xFFFF, sum = 0
4512 11:44:36.859805 6, 0xFFFF, sum = 0
4513 11:44:36.862835 7, 0xFFFF, sum = 0
4514 11:44:36.862910 8, 0x0, sum = 1
4515 11:44:36.866031 9, 0x0, sum = 2
4516 11:44:36.866115 10, 0x0, sum = 3
4517 11:44:36.869825 11, 0x0, sum = 4
4518 11:44:36.869909 best_step = 9
4519 11:44:36.869975
4520 11:44:36.870038 ==
4521 11:44:36.872954 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 11:44:36.875999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 11:44:36.879667 ==
4524 11:44:36.879769 RX Vref Scan: 1
4525 11:44:36.879862
4526 11:44:36.882682 RX Vref 0 -> 0, step: 1
4527 11:44:36.882762
4528 11:44:36.886339 RX Delay -179 -> 252, step: 8
4529 11:44:36.886414
4530 11:44:36.889369 Set Vref, RX VrefLevel [Byte0]: 53
4531 11:44:36.892460 [Byte1]: 49
4532 11:44:36.892534
4533 11:44:36.896141 Final RX Vref Byte 0 = 53 to rank0
4534 11:44:36.899055 Final RX Vref Byte 1 = 49 to rank0
4535 11:44:36.902642 Final RX Vref Byte 0 = 53 to rank1
4536 11:44:36.905623 Final RX Vref Byte 1 = 49 to rank1==
4537 11:44:36.909323 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 11:44:36.912526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 11:44:36.912611 ==
4540 11:44:36.915759 DQS Delay:
4541 11:44:36.915858 DQS0 = 0, DQS1 = 0
4542 11:44:36.915960 DQM Delay:
4543 11:44:36.918829 DQM0 = 41, DQM1 = 34
4544 11:44:36.918928 DQ Delay:
4545 11:44:36.921900 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4546 11:44:36.925560 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4547 11:44:36.928665 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4548 11:44:36.932420 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4549 11:44:36.932502
4550 11:44:36.932567
4551 11:44:36.941983 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4552 11:44:36.945074 CH1 RK0: MR19=808, MR18=2D47
4553 11:44:36.948838 CH1_RK0: MR19=0x808, MR18=0x2D47, DQSOSC=396, MR23=63, INC=167, DEC=111
4554 11:44:36.951823
4555 11:44:36.954968 ----->DramcWriteLeveling(PI) begin...
4556 11:44:36.955053 ==
4557 11:44:36.958706 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 11:44:36.961854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 11:44:36.961937 ==
4560 11:44:36.965069 Write leveling (Byte 0): 29 => 29
4561 11:44:36.968313 Write leveling (Byte 1): 29 => 29
4562 11:44:36.971558 DramcWriteLeveling(PI) end<-----
4563 11:44:36.971665
4564 11:44:36.971840 ==
4565 11:44:36.974597 Dram Type= 6, Freq= 0, CH_1, rank 1
4566 11:44:36.978480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 11:44:36.978562 ==
4568 11:44:36.981603 [Gating] SW mode calibration
4569 11:44:36.988203 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4570 11:44:36.994831 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4571 11:44:36.997953 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4572 11:44:37.000993 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4573 11:44:37.008199 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4574 11:44:37.011048 0 9 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4575 11:44:37.014114 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4576 11:44:37.021169 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4577 11:44:37.024312 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4578 11:44:37.027172 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4579 11:44:37.034053 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4580 11:44:37.037234 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4581 11:44:37.040401 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4582 11:44:37.047104 0 10 12 | B1->B0 | 3232 4040 | 0 0 | (1 1) (0 0)
4583 11:44:37.050266 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4584 11:44:37.054058 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4585 11:44:37.060296 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4586 11:44:37.063597 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4587 11:44:37.066899 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4588 11:44:37.073331 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4589 11:44:37.076991 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4590 11:44:37.080009 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4591 11:44:37.086467 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4592 11:44:37.090259 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4593 11:44:37.093277 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4594 11:44:37.099672 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4595 11:44:37.103024 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4596 11:44:37.106504 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4597 11:44:37.112934 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4598 11:44:37.116461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4599 11:44:37.119740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4600 11:44:37.126449 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 11:44:37.129606 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 11:44:37.132858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 11:44:37.139159 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 11:44:37.142818 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 11:44:37.145810 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4606 11:44:37.152537 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4607 11:44:37.155701 Total UI for P1: 0, mck2ui 16
4608 11:44:37.159353 best dqsien dly found for B0: ( 0, 13, 8)
4609 11:44:37.162475 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4610 11:44:37.165644 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 11:44:37.168818 Total UI for P1: 0, mck2ui 16
4612 11:44:37.172588 best dqsien dly found for B1: ( 0, 13, 16)
4613 11:44:37.175743 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4614 11:44:37.181886 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4615 11:44:37.181969
4616 11:44:37.185674 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4617 11:44:37.188854 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4618 11:44:37.191908 [Gating] SW calibration Done
4619 11:44:37.191990 ==
4620 11:44:37.195166 Dram Type= 6, Freq= 0, CH_1, rank 1
4621 11:44:37.198165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 11:44:37.198247 ==
4623 11:44:37.201958 RX Vref Scan: 0
4624 11:44:37.202040
4625 11:44:37.202105 RX Vref 0 -> 0, step: 1
4626 11:44:37.202165
4627 11:44:37.204971 RX Delay -230 -> 252, step: 16
4628 11:44:37.208504 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4629 11:44:37.214835 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4630 11:44:37.217905 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4631 11:44:37.221457 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4632 11:44:37.224929 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4633 11:44:37.231456 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4634 11:44:37.234592 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4635 11:44:37.238189 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4636 11:44:37.241253 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4637 11:44:37.247492 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4638 11:44:37.251106 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4639 11:44:37.254307 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4640 11:44:37.257507 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4641 11:44:37.264476 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4642 11:44:37.267635 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4643 11:44:37.270736 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4644 11:44:37.270859 ==
4645 11:44:37.273881 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 11:44:37.277658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 11:44:37.280867 ==
4648 11:44:37.280980 DQS Delay:
4649 11:44:37.281080 DQS0 = 0, DQS1 = 0
4650 11:44:37.283922 DQM Delay:
4651 11:44:37.284039 DQM0 = 44, DQM1 = 40
4652 11:44:37.287629 DQ Delay:
4653 11:44:37.287728 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4654 11:44:37.290731 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4655 11:44:37.293993 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4656 11:44:37.297188 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =57
4657 11:44:37.300302
4658 11:44:37.300412
4659 11:44:37.300507 ==
4660 11:44:37.303513 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 11:44:37.307234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 11:44:37.307340 ==
4663 11:44:37.307454
4664 11:44:37.307546
4665 11:44:37.310280 TX Vref Scan disable
4666 11:44:37.310396 == TX Byte 0 ==
4667 11:44:37.317113 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4668 11:44:37.320164 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4669 11:44:37.320274 == TX Byte 1 ==
4670 11:44:37.326820 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4671 11:44:37.329697 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4672 11:44:37.329802 ==
4673 11:44:37.333186 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 11:44:37.336633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 11:44:37.336750 ==
4676 11:44:37.339630
4677 11:44:37.339745
4678 11:44:37.339841 TX Vref Scan disable
4679 11:44:37.343336 == TX Byte 0 ==
4680 11:44:37.346567 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4681 11:44:37.353289 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4682 11:44:37.353396 == TX Byte 1 ==
4683 11:44:37.356343 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4684 11:44:37.363221 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4685 11:44:37.363357
4686 11:44:37.363461 [DATLAT]
4687 11:44:37.363559 Freq=600, CH1 RK1
4688 11:44:37.363653
4689 11:44:37.366275 DATLAT Default: 0x9
4690 11:44:37.369380 0, 0xFFFF, sum = 0
4691 11:44:37.369488 1, 0xFFFF, sum = 0
4692 11:44:37.372659 2, 0xFFFF, sum = 0
4693 11:44:37.372769 3, 0xFFFF, sum = 0
4694 11:44:37.376422 4, 0xFFFF, sum = 0
4695 11:44:37.376532 5, 0xFFFF, sum = 0
4696 11:44:37.379517 6, 0xFFFF, sum = 0
4697 11:44:37.379628 7, 0xFFFF, sum = 0
4698 11:44:37.382677 8, 0x0, sum = 1
4699 11:44:37.382784 9, 0x0, sum = 2
4700 11:44:37.386360 10, 0x0, sum = 3
4701 11:44:37.386469 11, 0x0, sum = 4
4702 11:44:37.386568 best_step = 9
4703 11:44:37.386659
4704 11:44:37.389385 ==
4705 11:44:37.392438 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 11:44:37.396243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 11:44:37.396348 ==
4708 11:44:37.396444 RX Vref Scan: 0
4709 11:44:37.396538
4710 11:44:37.399343 RX Vref 0 -> 0, step: 1
4711 11:44:37.399444
4712 11:44:37.402443 RX Delay -179 -> 252, step: 8
4713 11:44:37.409500 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4714 11:44:37.412584 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4715 11:44:37.415756 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4716 11:44:37.419466 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4717 11:44:37.422550 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4718 11:44:37.429162 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4719 11:44:37.432292 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4720 11:44:37.435982 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4721 11:44:37.438910 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4722 11:44:37.445557 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4723 11:44:37.448455 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4724 11:44:37.452244 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4725 11:44:37.455195 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4726 11:44:37.461881 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4727 11:44:37.465567 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4728 11:44:37.468673 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4729 11:44:37.468756 ==
4730 11:44:37.471882 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 11:44:37.475042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 11:44:37.478170 ==
4733 11:44:37.478252 DQS Delay:
4734 11:44:37.478317 DQS0 = 0, DQS1 = 0
4735 11:44:37.481948 DQM Delay:
4736 11:44:37.482029 DQM0 = 38, DQM1 = 35
4737 11:44:37.485047 DQ Delay:
4738 11:44:37.488239 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4739 11:44:37.488321 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4740 11:44:37.491426 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4741 11:44:37.498229 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4742 11:44:37.498311
4743 11:44:37.498376
4744 11:44:37.504478 [DQSOSCAuto] RK1, (LSB)MR18= 0x3257, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4745 11:44:37.507635 CH1 RK1: MR19=808, MR18=3257
4746 11:44:37.514642 CH1_RK1: MR19=0x808, MR18=0x3257, DQSOSC=393, MR23=63, INC=169, DEC=113
4747 11:44:37.517881 [RxdqsGatingPostProcess] freq 600
4748 11:44:37.520996 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4749 11:44:37.524503 Pre-setting of DQS Precalculation
4750 11:44:37.530986 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4751 11:44:37.537595 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4752 11:44:37.544359 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4753 11:44:37.544450
4754 11:44:37.544518
4755 11:44:37.547563 [Calibration Summary] 1200 Mbps
4756 11:44:37.547670 CH 0, Rank 0
4757 11:44:37.550559 SW Impedance : PASS
4758 11:44:37.554161 DUTY Scan : NO K
4759 11:44:37.554274 ZQ Calibration : PASS
4760 11:44:37.557236 Jitter Meter : NO K
4761 11:44:37.560306 CBT Training : PASS
4762 11:44:37.560381 Write leveling : PASS
4763 11:44:37.563896 RX DQS gating : PASS
4764 11:44:37.566796 RX DQ/DQS(RDDQC) : PASS
4765 11:44:37.566872 TX DQ/DQS : PASS
4766 11:44:37.570416 RX DATLAT : PASS
4767 11:44:37.573583 RX DQ/DQS(Engine): PASS
4768 11:44:37.573658 TX OE : NO K
4769 11:44:37.576846 All Pass.
4770 11:44:37.576924
4771 11:44:37.576998 CH 0, Rank 1
4772 11:44:37.579956 SW Impedance : PASS
4773 11:44:37.580085 DUTY Scan : NO K
4774 11:44:37.583745 ZQ Calibration : PASS
4775 11:44:37.586978 Jitter Meter : NO K
4776 11:44:37.587053 CBT Training : PASS
4777 11:44:37.590051 Write leveling : PASS
4778 11:44:37.593275 RX DQS gating : PASS
4779 11:44:37.593352 RX DQ/DQS(RDDQC) : PASS
4780 11:44:37.596431 TX DQ/DQS : PASS
4781 11:44:37.600213 RX DATLAT : PASS
4782 11:44:37.600328 RX DQ/DQS(Engine): PASS
4783 11:44:37.603317 TX OE : NO K
4784 11:44:37.603400 All Pass.
4785 11:44:37.603466
4786 11:44:37.606599 CH 1, Rank 0
4787 11:44:37.606687 SW Impedance : PASS
4788 11:44:37.609741 DUTY Scan : NO K
4789 11:44:37.613599 ZQ Calibration : PASS
4790 11:44:37.613724 Jitter Meter : NO K
4791 11:44:37.616715 CBT Training : PASS
4792 11:44:37.619844 Write leveling : PASS
4793 11:44:37.620013 RX DQS gating : PASS
4794 11:44:37.623118 RX DQ/DQS(RDDQC) : PASS
4795 11:44:37.623254 TX DQ/DQS : PASS
4796 11:44:37.626070 RX DATLAT : PASS
4797 11:44:37.629773 RX DQ/DQS(Engine): PASS
4798 11:44:37.629897 TX OE : NO K
4799 11:44:37.633060 All Pass.
4800 11:44:37.633164
4801 11:44:37.633241 CH 1, Rank 1
4802 11:44:37.636117 SW Impedance : PASS
4803 11:44:37.636227 DUTY Scan : NO K
4804 11:44:37.639850 ZQ Calibration : PASS
4805 11:44:37.642932 Jitter Meter : NO K
4806 11:44:37.643090 CBT Training : PASS
4807 11:44:37.645954 Write leveling : PASS
4808 11:44:37.649518 RX DQS gating : PASS
4809 11:44:37.649668 RX DQ/DQS(RDDQC) : PASS
4810 11:44:37.652562 TX DQ/DQS : PASS
4811 11:44:37.655867 RX DATLAT : PASS
4812 11:44:37.656131 RX DQ/DQS(Engine): PASS
4813 11:44:37.659487 TX OE : NO K
4814 11:44:37.659698 All Pass.
4815 11:44:37.659811
4816 11:44:37.662537 DramC Write-DBI off
4817 11:44:37.665573 PER_BANK_REFRESH: Hybrid Mode
4818 11:44:37.665747 TX_TRACKING: ON
4819 11:44:37.675802 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4820 11:44:37.678845 [FAST_K] Save calibration result to emmc
4821 11:44:37.682122 dramc_set_vcore_voltage set vcore to 662500
4822 11:44:37.685317 Read voltage for 933, 3
4823 11:44:37.685404 Vio18 = 0
4824 11:44:37.688477 Vcore = 662500
4825 11:44:37.688562 Vdram = 0
4826 11:44:37.688637 Vddq = 0
4827 11:44:37.688701 Vmddr = 0
4828 11:44:37.695312 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4829 11:44:37.701589 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4830 11:44:37.701772 MEM_TYPE=3, freq_sel=17
4831 11:44:37.705269 sv_algorithm_assistance_LP4_1600
4832 11:44:37.708457 ============ PULL DRAM RESETB DOWN ============
4833 11:44:37.714674 ========== PULL DRAM RESETB DOWN end =========
4834 11:44:37.718356 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4835 11:44:37.721561 ===================================
4836 11:44:37.724730 LPDDR4 DRAM CONFIGURATION
4837 11:44:37.727902 ===================================
4838 11:44:37.727994 EX_ROW_EN[0] = 0x0
4839 11:44:37.731625 EX_ROW_EN[1] = 0x0
4840 11:44:37.731761 LP4Y_EN = 0x0
4841 11:44:37.734556 WORK_FSP = 0x0
4842 11:44:37.737616 WL = 0x3
4843 11:44:37.737781 RL = 0x3
4844 11:44:37.741542 BL = 0x2
4845 11:44:37.741761 RPST = 0x0
4846 11:44:37.744652 RD_PRE = 0x0
4847 11:44:37.744856 WR_PRE = 0x1
4848 11:44:37.747859 WR_PST = 0x0
4849 11:44:37.748153 DBI_WR = 0x0
4850 11:44:37.750921 DBI_RD = 0x0
4851 11:44:37.751124 OTF = 0x1
4852 11:44:37.754663 ===================================
4853 11:44:37.757626 ===================================
4854 11:44:37.761290 ANA top config
4855 11:44:37.764210 ===================================
4856 11:44:37.764435 DLL_ASYNC_EN = 0
4857 11:44:37.767697 ALL_SLAVE_EN = 1
4858 11:44:37.770586 NEW_RANK_MODE = 1
4859 11:44:37.774329 DLL_IDLE_MODE = 1
4860 11:44:37.777363 LP45_APHY_COMB_EN = 1
4861 11:44:37.777585 TX_ODT_DIS = 1
4862 11:44:37.781064 NEW_8X_MODE = 1
4863 11:44:37.784181 ===================================
4864 11:44:37.787169 ===================================
4865 11:44:37.790357 data_rate = 1866
4866 11:44:37.793517 CKR = 1
4867 11:44:37.796666 DQ_P2S_RATIO = 8
4868 11:44:37.800459 ===================================
4869 11:44:37.803612 CA_P2S_RATIO = 8
4870 11:44:37.803689 DQ_CA_OPEN = 0
4871 11:44:37.806595 DQ_SEMI_OPEN = 0
4872 11:44:37.810341 CA_SEMI_OPEN = 0
4873 11:44:37.813415 CA_FULL_RATE = 0
4874 11:44:37.816578 DQ_CKDIV4_EN = 1
4875 11:44:37.819823 CA_CKDIV4_EN = 1
4876 11:44:37.822979 CA_PREDIV_EN = 0
4877 11:44:37.823076 PH8_DLY = 0
4878 11:44:37.826637 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4879 11:44:37.829871 DQ_AAMCK_DIV = 4
4880 11:44:37.833110 CA_AAMCK_DIV = 4
4881 11:44:37.836253 CA_ADMCK_DIV = 4
4882 11:44:37.839721 DQ_TRACK_CA_EN = 0
4883 11:44:37.839896 CA_PICK = 933
4884 11:44:37.842842 CA_MCKIO = 933
4885 11:44:37.846621 MCKIO_SEMI = 0
4886 11:44:37.849843 PLL_FREQ = 3732
4887 11:44:37.853052 DQ_UI_PI_RATIO = 32
4888 11:44:37.856194 CA_UI_PI_RATIO = 0
4889 11:44:37.859225 ===================================
4890 11:44:37.862798 ===================================
4891 11:44:37.865812 memory_type:LPDDR4
4892 11:44:37.865959 GP_NUM : 10
4893 11:44:37.869338 SRAM_EN : 1
4894 11:44:37.869487 MD32_EN : 0
4895 11:44:37.872810 ===================================
4896 11:44:37.875656 [ANA_INIT] >>>>>>>>>>>>>>
4897 11:44:37.879235 <<<<<< [CONFIGURE PHASE]: ANA_TX
4898 11:44:37.882761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4899 11:44:37.885615 ===================================
4900 11:44:37.889206 data_rate = 1866,PCW = 0X8f00
4901 11:44:37.892375 ===================================
4902 11:44:37.895579 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4903 11:44:37.902499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4904 11:44:37.905639 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4905 11:44:37.911883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4906 11:44:37.915593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4907 11:44:37.918741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4908 11:44:37.918817 [ANA_INIT] flow start
4909 11:44:37.921870 [ANA_INIT] PLL >>>>>>>>
4910 11:44:37.925022 [ANA_INIT] PLL <<<<<<<<
4911 11:44:37.925107 [ANA_INIT] MIDPI >>>>>>>>
4912 11:44:37.928729 [ANA_INIT] MIDPI <<<<<<<<
4913 11:44:37.931781 [ANA_INIT] DLL >>>>>>>>
4914 11:44:37.931899 [ANA_INIT] flow end
4915 11:44:37.938198 ============ LP4 DIFF to SE enter ============
4916 11:44:37.941872 ============ LP4 DIFF to SE exit ============
4917 11:44:37.944837 [ANA_INIT] <<<<<<<<<<<<<
4918 11:44:37.948101 [Flow] Enable top DCM control >>>>>
4919 11:44:37.951842 [Flow] Enable top DCM control <<<<<
4920 11:44:37.951955 Enable DLL master slave shuffle
4921 11:44:37.958106 ==============================================================
4922 11:44:37.961304 Gating Mode config
4923 11:44:37.964977 ==============================================================
4924 11:44:37.967971 Config description:
4925 11:44:37.978101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4926 11:44:37.984775 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4927 11:44:37.987775 SELPH_MODE 0: By rank 1: By Phase
4928 11:44:37.994495 ==============================================================
4929 11:44:37.997780 GAT_TRACK_EN = 1
4930 11:44:38.000824 RX_GATING_MODE = 2
4931 11:44:38.004703 RX_GATING_TRACK_MODE = 2
4932 11:44:38.007735 SELPH_MODE = 1
4933 11:44:38.010921 PICG_EARLY_EN = 1
4934 11:44:38.014079 VALID_LAT_VALUE = 1
4935 11:44:38.017654 ==============================================================
4936 11:44:38.020625 Enter into Gating configuration >>>>
4937 11:44:38.023853 Exit from Gating configuration <<<<
4938 11:44:38.027047 Enter into DVFS_PRE_config >>>>>
4939 11:44:38.040265 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4940 11:44:38.040399 Exit from DVFS_PRE_config <<<<<
4941 11:44:38.043858 Enter into PICG configuration >>>>
4942 11:44:38.046881 Exit from PICG configuration <<<<
4943 11:44:38.050689 [RX_INPUT] configuration >>>>>
4944 11:44:38.053850 [RX_INPUT] configuration <<<<<
4945 11:44:38.060167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4946 11:44:38.063955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4947 11:44:38.070390 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4948 11:44:38.076575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4949 11:44:38.083145 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4950 11:44:38.089733 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4951 11:44:38.093332 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4952 11:44:38.096200 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4953 11:44:38.103261 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4954 11:44:38.106386 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4955 11:44:38.109626 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4956 11:44:38.112852 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4957 11:44:38.116546 ===================================
4958 11:44:38.119735 LPDDR4 DRAM CONFIGURATION
4959 11:44:38.122796 ===================================
4960 11:44:38.126341 EX_ROW_EN[0] = 0x0
4961 11:44:38.126425 EX_ROW_EN[1] = 0x0
4962 11:44:38.129453 LP4Y_EN = 0x0
4963 11:44:38.129537 WORK_FSP = 0x0
4964 11:44:38.132722 WL = 0x3
4965 11:44:38.132806 RL = 0x3
4966 11:44:38.135737 BL = 0x2
4967 11:44:38.135821 RPST = 0x0
4968 11:44:38.138877 RD_PRE = 0x0
4969 11:44:38.142664 WR_PRE = 0x1
4970 11:44:38.142747 WR_PST = 0x0
4971 11:44:38.145753 DBI_WR = 0x0
4972 11:44:38.145837 DBI_RD = 0x0
4973 11:44:38.149012 OTF = 0x1
4974 11:44:38.151990 ===================================
4975 11:44:38.155121 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4976 11:44:38.158715 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4977 11:44:38.165092 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4978 11:44:38.168263 ===================================
4979 11:44:38.168347 LPDDR4 DRAM CONFIGURATION
4980 11:44:38.172015 ===================================
4981 11:44:38.175307 EX_ROW_EN[0] = 0x10
4982 11:44:38.178435 EX_ROW_EN[1] = 0x0
4983 11:44:38.178523 LP4Y_EN = 0x0
4984 11:44:38.181444 WORK_FSP = 0x0
4985 11:44:38.181555 WL = 0x3
4986 11:44:38.185076 RL = 0x3
4987 11:44:38.185160 BL = 0x2
4988 11:44:38.188150 RPST = 0x0
4989 11:44:38.188234 RD_PRE = 0x0
4990 11:44:38.191591 WR_PRE = 0x1
4991 11:44:38.191678 WR_PST = 0x0
4992 11:44:38.195087 DBI_WR = 0x0
4993 11:44:38.195171 DBI_RD = 0x0
4994 11:44:38.198089 OTF = 0x1
4995 11:44:38.201655 ===================================
4996 11:44:38.208154 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4997 11:44:38.211609 nWR fixed to 30
4998 11:44:38.211692 [ModeRegInit_LP4] CH0 RK0
4999 11:44:38.214686 [ModeRegInit_LP4] CH0 RK1
5000 11:44:38.218029 [ModeRegInit_LP4] CH1 RK0
5001 11:44:38.221236 [ModeRegInit_LP4] CH1 RK1
5002 11:44:38.221318 match AC timing 9
5003 11:44:38.227591 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5004 11:44:38.231176 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5005 11:44:38.234314 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5006 11:44:38.240729 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5007 11:44:38.244501 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5008 11:44:38.244589 ==
5009 11:44:38.247618 Dram Type= 6, Freq= 0, CH_0, rank 0
5010 11:44:38.250671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5011 11:44:38.250753 ==
5012 11:44:38.257304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5013 11:44:38.263930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5014 11:44:38.267067 [CA 0] Center 37 (7~68) winsize 62
5015 11:44:38.271106 [CA 1] Center 37 (7~68) winsize 62
5016 11:44:38.273630 [CA 2] Center 34 (4~64) winsize 61
5017 11:44:38.277390 [CA 3] Center 34 (3~65) winsize 63
5018 11:44:38.280523 [CA 4] Center 33 (3~64) winsize 62
5019 11:44:38.283529 [CA 5] Center 32 (2~63) winsize 62
5020 11:44:38.283608
5021 11:44:38.287182 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5022 11:44:38.287253
5023 11:44:38.290395 [CATrainingPosCal] consider 1 rank data
5024 11:44:38.293586 u2DelayCellTimex100 = 270/100 ps
5025 11:44:38.297354 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5026 11:44:38.300339 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5027 11:44:38.303837 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5028 11:44:38.306852 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5029 11:44:38.310352 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5030 11:44:38.316970 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5031 11:44:38.317052
5032 11:44:38.319745 CA PerBit enable=1, Macro0, CA PI delay=32
5033 11:44:38.319827
5034 11:44:38.322874 [CBTSetCACLKResult] CA Dly = 32
5035 11:44:38.322957 CS Dly: 5 (0~36)
5036 11:44:38.323024 ==
5037 11:44:38.326628 Dram Type= 6, Freq= 0, CH_0, rank 1
5038 11:44:38.332963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5039 11:44:38.333046 ==
5040 11:44:38.336579 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5041 11:44:38.343027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5042 11:44:38.346089 [CA 0] Center 38 (8~68) winsize 61
5043 11:44:38.349862 [CA 1] Center 37 (7~68) winsize 62
5044 11:44:38.352928 [CA 2] Center 34 (4~65) winsize 62
5045 11:44:38.356007 [CA 3] Center 34 (4~65) winsize 62
5046 11:44:38.359253 [CA 4] Center 33 (3~64) winsize 62
5047 11:44:38.362882 [CA 5] Center 32 (2~63) winsize 62
5048 11:44:38.362964
5049 11:44:38.366057 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5050 11:44:38.366143
5051 11:44:38.369134 [CATrainingPosCal] consider 2 rank data
5052 11:44:38.372267 u2DelayCellTimex100 = 270/100 ps
5053 11:44:38.376126 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5054 11:44:38.379305 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5055 11:44:38.385762 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5056 11:44:38.388877 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5057 11:44:38.392588 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5058 11:44:38.395836 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5059 11:44:38.395944
5060 11:44:38.398926 CA PerBit enable=1, Macro0, CA PI delay=32
5061 11:44:38.399008
5062 11:44:38.402032 [CBTSetCACLKResult] CA Dly = 32
5063 11:44:38.405735 CS Dly: 6 (0~39)
5064 11:44:38.405817
5065 11:44:38.408816 ----->DramcWriteLeveling(PI) begin...
5066 11:44:38.408917 ==
5067 11:44:38.411774 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 11:44:38.415033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 11:44:38.415135 ==
5070 11:44:38.418435 Write leveling (Byte 0): 31 => 31
5071 11:44:38.422049 Write leveling (Byte 1): 30 => 30
5072 11:44:38.424974 DramcWriteLeveling(PI) end<-----
5073 11:44:38.425057
5074 11:44:38.425122 ==
5075 11:44:38.428492 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 11:44:38.431983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 11:44:38.432123 ==
5078 11:44:38.435029 [Gating] SW mode calibration
5079 11:44:38.441815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5080 11:44:38.448156 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5081 11:44:38.451186 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5082 11:44:38.454945 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5083 11:44:38.461057 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5084 11:44:38.465002 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5085 11:44:38.467868 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5086 11:44:38.474798 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5087 11:44:38.477928 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5088 11:44:38.481023 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
5089 11:44:38.487928 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5090 11:44:38.491022 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5091 11:44:38.497746 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5092 11:44:38.500901 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5093 11:44:38.504162 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5094 11:44:38.510321 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5095 11:44:38.514053 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5096 11:44:38.517206 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5097 11:44:38.523733 1 0 0 | B1->B0 | 3939 4646 | 1 0 | (1 1) (0 0)
5098 11:44:38.527138 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5099 11:44:38.530174 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5100 11:44:38.537101 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5101 11:44:38.539874 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5102 11:44:38.543470 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5103 11:44:38.550187 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5104 11:44:38.553262 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5105 11:44:38.556564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5106 11:44:38.562748 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5107 11:44:38.566516 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5108 11:44:38.569570 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5109 11:44:38.575894 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5110 11:44:38.579727 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5111 11:44:38.582808 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5112 11:44:38.589208 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5113 11:44:38.592955 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5114 11:44:38.596054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5115 11:44:38.602687 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 11:44:38.605955 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 11:44:38.609131 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 11:44:38.615316 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 11:44:38.619178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:44:38.622440 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5121 11:44:38.628835 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5122 11:44:38.628952 Total UI for P1: 0, mck2ui 16
5123 11:44:38.635396 best dqsien dly found for B0: ( 1, 2, 28)
5124 11:44:38.638772 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 11:44:38.641898 Total UI for P1: 0, mck2ui 16
5126 11:44:38.645322 best dqsien dly found for B1: ( 1, 3, 0)
5127 11:44:38.648764 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5128 11:44:38.651740 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5129 11:44:38.651852
5130 11:44:38.655349 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5131 11:44:38.658467 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5132 11:44:38.661492 [Gating] SW calibration Done
5133 11:44:38.661603 ==
5134 11:44:38.665180 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 11:44:38.668266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 11:44:38.671434 ==
5137 11:44:38.671532 RX Vref Scan: 0
5138 11:44:38.671613
5139 11:44:38.674984 RX Vref 0 -> 0, step: 1
5140 11:44:38.675094
5141 11:44:38.678053 RX Delay -80 -> 252, step: 8
5142 11:44:38.681835 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5143 11:44:38.684988 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5144 11:44:38.688126 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5145 11:44:38.691255 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5146 11:44:38.694361 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5147 11:44:38.701228 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5148 11:44:38.704267 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5149 11:44:38.707914 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5150 11:44:38.711022 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5151 11:44:38.714173 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5152 11:44:38.721048 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5153 11:44:38.724228 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5154 11:44:38.727422 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5155 11:44:38.730565 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5156 11:44:38.734195 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5157 11:44:38.740836 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5158 11:44:38.740957 ==
5159 11:44:38.743894 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 11:44:38.747338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 11:44:38.747498 ==
5162 11:44:38.747608 DQS Delay:
5163 11:44:38.750741 DQS0 = 0, DQS1 = 0
5164 11:44:38.750853 DQM Delay:
5165 11:44:38.753621 DQM0 = 100, DQM1 = 90
5166 11:44:38.753732 DQ Delay:
5167 11:44:38.757056 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5168 11:44:38.760565 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5169 11:44:38.763549 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5170 11:44:38.767175 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5171 11:44:38.767295
5172 11:44:38.767402
5173 11:44:38.767528 ==
5174 11:44:38.770157 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 11:44:38.777122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 11:44:38.777254 ==
5177 11:44:38.777387
5178 11:44:38.777511
5179 11:44:38.777642 TX Vref Scan disable
5180 11:44:38.780049 == TX Byte 0 ==
5181 11:44:38.783834 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5182 11:44:38.787055 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5183 11:44:38.790062 == TX Byte 1 ==
5184 11:44:38.793213 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5185 11:44:38.800059 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5186 11:44:38.800146 ==
5187 11:44:38.803162 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 11:44:38.806398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 11:44:38.806488 ==
5190 11:44:38.806574
5191 11:44:38.806655
5192 11:44:38.809467 TX Vref Scan disable
5193 11:44:38.809553 == TX Byte 0 ==
5194 11:44:38.816347 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5195 11:44:38.819371 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5196 11:44:38.823187 == TX Byte 1 ==
5197 11:44:38.826528 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5198 11:44:38.829542 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5199 11:44:38.829621
5200 11:44:38.829687 [DATLAT]
5201 11:44:38.832684 Freq=933, CH0 RK0
5202 11:44:38.832758
5203 11:44:38.832834 DATLAT Default: 0xd
5204 11:44:38.835938 0, 0xFFFF, sum = 0
5205 11:44:38.839186 1, 0xFFFF, sum = 0
5206 11:44:38.839280 2, 0xFFFF, sum = 0
5207 11:44:38.842874 3, 0xFFFF, sum = 0
5208 11:44:38.842962 4, 0xFFFF, sum = 0
5209 11:44:38.845844 5, 0xFFFF, sum = 0
5210 11:44:38.845922 6, 0xFFFF, sum = 0
5211 11:44:38.849055 7, 0xFFFF, sum = 0
5212 11:44:38.849135 8, 0xFFFF, sum = 0
5213 11:44:38.852776 9, 0xFFFF, sum = 0
5214 11:44:38.852858 10, 0x0, sum = 1
5215 11:44:38.855774 11, 0x0, sum = 2
5216 11:44:38.855885 12, 0x0, sum = 3
5217 11:44:38.859178 13, 0x0, sum = 4
5218 11:44:38.859258 best_step = 11
5219 11:44:38.859324
5220 11:44:38.859401 ==
5221 11:44:38.862613 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 11:44:38.865556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 11:44:38.865637 ==
5224 11:44:38.869145 RX Vref Scan: 1
5225 11:44:38.869221
5226 11:44:38.872651 RX Vref 0 -> 0, step: 1
5227 11:44:38.872768
5228 11:44:38.872860 RX Delay -61 -> 252, step: 4
5229 11:44:38.875542
5230 11:44:38.875655 Set Vref, RX VrefLevel [Byte0]: 51
5231 11:44:38.878616 [Byte1]: 49
5232 11:44:38.884150
5233 11:44:38.884301 Final RX Vref Byte 0 = 51 to rank0
5234 11:44:38.887313 Final RX Vref Byte 1 = 49 to rank0
5235 11:44:38.890562 Final RX Vref Byte 0 = 51 to rank1
5236 11:44:38.893805 Final RX Vref Byte 1 = 49 to rank1==
5237 11:44:38.896766 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 11:44:38.903853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 11:44:38.903976 ==
5240 11:44:38.904142 DQS Delay:
5241 11:44:38.906968 DQS0 = 0, DQS1 = 0
5242 11:44:38.907066 DQM Delay:
5243 11:44:38.907136 DQM0 = 99, DQM1 = 88
5244 11:44:38.910088 DQ Delay:
5245 11:44:38.913797 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5246 11:44:38.916827 DQ4 =98, DQ5 =90, DQ6 =110, DQ7 =106
5247 11:44:38.919936 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =84
5248 11:44:38.923666 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =94
5249 11:44:38.923748
5250 11:44:38.923815
5251 11:44:38.929927 [DQSOSCAuto] RK0, (LSB)MR18= 0x140e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
5252 11:44:38.933148 CH0 RK0: MR19=505, MR18=140E
5253 11:44:38.940028 CH0_RK0: MR19=0x505, MR18=0x140E, DQSOSC=415, MR23=63, INC=62, DEC=41
5254 11:44:38.940127
5255 11:44:38.943259 ----->DramcWriteLeveling(PI) begin...
5256 11:44:38.943333 ==
5257 11:44:38.946410 Dram Type= 6, Freq= 0, CH_0, rank 1
5258 11:44:38.949904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:44:38.949986 ==
5260 11:44:38.953068 Write leveling (Byte 0): 32 => 32
5261 11:44:38.956120 Write leveling (Byte 1): 31 => 31
5262 11:44:38.959391 DramcWriteLeveling(PI) end<-----
5263 11:44:38.959475
5264 11:44:38.959539 ==
5265 11:44:38.963013 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 11:44:38.969463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:44:38.969547 ==
5268 11:44:38.969651 [Gating] SW mode calibration
5269 11:44:38.979174 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5270 11:44:38.982742 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5271 11:44:38.989274 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5272 11:44:38.992219 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5273 11:44:38.995925 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5274 11:44:39.002296 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5275 11:44:39.005541 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5276 11:44:39.008656 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5277 11:44:39.014928 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5278 11:44:39.018513 0 14 28 | B1->B0 | 3333 2929 | 1 0 | (1 0) (0 0)
5279 11:44:39.021686 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5280 11:44:39.028595 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5281 11:44:39.031827 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5282 11:44:39.035040 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5283 11:44:39.041468 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5284 11:44:39.044515 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5285 11:44:39.048317 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5286 11:44:39.054466 0 15 28 | B1->B0 | 2a2a 4343 | 0 0 | (1 1) (0 0)
5287 11:44:39.058224 1 0 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5288 11:44:39.061285 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5289 11:44:39.067521 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5290 11:44:39.071127 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5291 11:44:39.074191 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5292 11:44:39.080672 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5293 11:44:39.084294 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5294 11:44:39.087291 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5295 11:44:39.093869 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5296 11:44:39.097053 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5297 11:44:39.100145 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5298 11:44:39.106951 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5299 11:44:39.110198 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5300 11:44:39.114099 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5301 11:44:39.120267 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5302 11:44:39.123485 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5303 11:44:39.127133 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5304 11:44:39.133389 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 11:44:39.136650 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 11:44:39.143366 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 11:44:39.146606 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 11:44:39.149687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 11:44:39.156475 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 11:44:39.159452 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5311 11:44:39.162639 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5312 11:44:39.169464 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 11:44:39.169543 Total UI for P1: 0, mck2ui 16
5314 11:44:39.175996 best dqsien dly found for B0: ( 1, 2, 30)
5315 11:44:39.176100 Total UI for P1: 0, mck2ui 16
5316 11:44:39.182103 best dqsien dly found for B1: ( 1, 3, 2)
5317 11:44:39.185795 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5318 11:44:39.188808 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5319 11:44:39.188912
5320 11:44:39.192367 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5321 11:44:39.195197 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5322 11:44:39.199343 [Gating] SW calibration Done
5323 11:44:39.199455 ==
5324 11:44:39.202305 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 11:44:39.205339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 11:44:39.205452 ==
5327 11:44:39.208535 RX Vref Scan: 0
5328 11:44:39.208644
5329 11:44:39.208750 RX Vref 0 -> 0, step: 1
5330 11:44:39.208843
5331 11:44:39.212188 RX Delay -80 -> 252, step: 8
5332 11:44:39.215432 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5333 11:44:39.221855 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5334 11:44:39.225041 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5335 11:44:39.228717 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5336 11:44:39.231823 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5337 11:44:39.234992 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5338 11:44:39.238761 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5339 11:44:39.244968 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5340 11:44:39.248326 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5341 11:44:39.251460 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5342 11:44:39.255202 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5343 11:44:39.258287 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5344 11:44:39.264653 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5345 11:44:39.267799 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5346 11:44:39.271447 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5347 11:44:39.274606 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5348 11:44:39.274706 ==
5349 11:44:39.277675 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 11:44:39.281225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 11:44:39.284333 ==
5352 11:44:39.284410 DQS Delay:
5353 11:44:39.284474 DQS0 = 0, DQS1 = 0
5354 11:44:39.287945 DQM Delay:
5355 11:44:39.288091 DQM0 = 99, DQM1 = 88
5356 11:44:39.290996 DQ Delay:
5357 11:44:39.294723 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5358 11:44:39.297644 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5359 11:44:39.301416 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5360 11:44:39.304371 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5361 11:44:39.304483
5362 11:44:39.304579
5363 11:44:39.304684 ==
5364 11:44:39.307817 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 11:44:39.310908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 11:44:39.311027 ==
5367 11:44:39.311124
5368 11:44:39.311234
5369 11:44:39.314562 TX Vref Scan disable
5370 11:44:39.314678 == TX Byte 0 ==
5371 11:44:39.320975 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5372 11:44:39.324113 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5373 11:44:39.324246 == TX Byte 1 ==
5374 11:44:39.330451 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5375 11:44:39.334170 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5376 11:44:39.334352 ==
5377 11:44:39.337149 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 11:44:39.340321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 11:44:39.340434 ==
5380 11:44:39.343523
5381 11:44:39.343637
5382 11:44:39.343773 TX Vref Scan disable
5383 11:44:39.347327 == TX Byte 0 ==
5384 11:44:39.350438 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5385 11:44:39.356731 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5386 11:44:39.356841 == TX Byte 1 ==
5387 11:44:39.360448 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5388 11:44:39.366614 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5389 11:44:39.366757
5390 11:44:39.366871 [DATLAT]
5391 11:44:39.366967 Freq=933, CH0 RK1
5392 11:44:39.367059
5393 11:44:39.370304 DATLAT Default: 0xb
5394 11:44:39.370406 0, 0xFFFF, sum = 0
5395 11:44:39.373457 1, 0xFFFF, sum = 0
5396 11:44:39.376522 2, 0xFFFF, sum = 0
5397 11:44:39.376634 3, 0xFFFF, sum = 0
5398 11:44:39.380288 4, 0xFFFF, sum = 0
5399 11:44:39.380409 5, 0xFFFF, sum = 0
5400 11:44:39.383225 6, 0xFFFF, sum = 0
5401 11:44:39.383354 7, 0xFFFF, sum = 0
5402 11:44:39.386869 8, 0xFFFF, sum = 0
5403 11:44:39.386955 9, 0xFFFF, sum = 0
5404 11:44:39.390005 10, 0x0, sum = 1
5405 11:44:39.390147 11, 0x0, sum = 2
5406 11:44:39.393172 12, 0x0, sum = 3
5407 11:44:39.393255 13, 0x0, sum = 4
5408 11:44:39.393336 best_step = 11
5409 11:44:39.396287
5410 11:44:39.396372 ==
5411 11:44:39.399503 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 11:44:39.403208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 11:44:39.403293 ==
5414 11:44:39.403360 RX Vref Scan: 0
5415 11:44:39.406161
5416 11:44:39.406245 RX Vref 0 -> 0, step: 1
5417 11:44:39.406312
5418 11:44:39.409591 RX Delay -61 -> 252, step: 4
5419 11:44:39.416218 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5420 11:44:39.419230 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5421 11:44:39.422951 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5422 11:44:39.426167 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5423 11:44:39.429299 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5424 11:44:39.432470 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5425 11:44:39.439334 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5426 11:44:39.442407 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5427 11:44:39.446112 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5428 11:44:39.449303 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5429 11:44:39.452447 iDelay=195, Bit 10, Center 86 (-5 ~ 178) 184
5430 11:44:39.458721 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5431 11:44:39.462332 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5432 11:44:39.465633 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5433 11:44:39.468676 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5434 11:44:39.472380 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5435 11:44:39.475498 ==
5436 11:44:39.475597 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 11:44:39.482314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 11:44:39.482422 ==
5439 11:44:39.482520 DQS Delay:
5440 11:44:39.485518 DQS0 = 0, DQS1 = 0
5441 11:44:39.485634 DQM Delay:
5442 11:44:39.488607 DQM0 = 97, DQM1 = 87
5443 11:44:39.488683 DQ Delay:
5444 11:44:39.491585 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5445 11:44:39.495243 DQ4 =102, DQ5 =86, DQ6 =106, DQ7 =106
5446 11:44:39.498384 DQ8 =80, DQ9 =76, DQ10 =86, DQ11 =82
5447 11:44:39.501563 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =94
5448 11:44:39.501638
5449 11:44:39.501700
5450 11:44:39.508447 [DQSOSCAuto] RK1, (LSB)MR18= 0x120e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5451 11:44:39.511457 CH0 RK1: MR19=505, MR18=120E
5452 11:44:39.518031 CH0_RK1: MR19=0x505, MR18=0x120E, DQSOSC=416, MR23=63, INC=62, DEC=41
5453 11:44:39.521747 [RxdqsGatingPostProcess] freq 933
5454 11:44:39.528440 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5455 11:44:39.531562 best DQS0 dly(2T, 0.5T) = (0, 10)
5456 11:44:39.534606 best DQS1 dly(2T, 0.5T) = (0, 11)
5457 11:44:39.537823 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5458 11:44:39.541668 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5459 11:44:39.541750 best DQS0 dly(2T, 0.5T) = (0, 10)
5460 11:44:39.544703 best DQS1 dly(2T, 0.5T) = (0, 11)
5461 11:44:39.547799 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5462 11:44:39.550916 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5463 11:44:39.554747 Pre-setting of DQS Precalculation
5464 11:44:39.561160 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5465 11:44:39.561277 ==
5466 11:44:39.564289 Dram Type= 6, Freq= 0, CH_1, rank 0
5467 11:44:39.567530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 11:44:39.567614 ==
5469 11:44:39.574489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5470 11:44:39.580685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5471 11:44:39.583867 [CA 0] Center 36 (6~67) winsize 62
5472 11:44:39.587445 [CA 1] Center 36 (6~67) winsize 62
5473 11:44:39.590699 [CA 2] Center 34 (4~65) winsize 62
5474 11:44:39.593850 [CA 3] Center 34 (4~65) winsize 62
5475 11:44:39.597428 [CA 4] Center 34 (4~65) winsize 62
5476 11:44:39.600604 [CA 5] Center 33 (3~64) winsize 62
5477 11:44:39.600688
5478 11:44:39.603768 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5479 11:44:39.603853
5480 11:44:39.606830 [CATrainingPosCal] consider 1 rank data
5481 11:44:39.610505 u2DelayCellTimex100 = 270/100 ps
5482 11:44:39.613569 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5483 11:44:39.616682 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5484 11:44:39.620263 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5485 11:44:39.623294 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5486 11:44:39.626989 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5487 11:44:39.629993 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5488 11:44:39.633609
5489 11:44:39.636688 CA PerBit enable=1, Macro0, CA PI delay=33
5490 11:44:39.636774
5491 11:44:39.639836 [CBTSetCACLKResult] CA Dly = 33
5492 11:44:39.639921 CS Dly: 4 (0~35)
5493 11:44:39.639988 ==
5494 11:44:39.642925 Dram Type= 6, Freq= 0, CH_1, rank 1
5495 11:44:39.646671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 11:44:39.649732 ==
5497 11:44:39.652832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5498 11:44:39.659637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5499 11:44:39.662810 [CA 0] Center 36 (6~67) winsize 62
5500 11:44:39.666675 [CA 1] Center 36 (6~67) winsize 62
5501 11:44:39.669784 [CA 2] Center 34 (4~64) winsize 61
5502 11:44:39.672845 [CA 3] Center 33 (3~64) winsize 62
5503 11:44:39.675912 [CA 4] Center 33 (3~64) winsize 62
5504 11:44:39.679610 [CA 5] Center 33 (3~64) winsize 62
5505 11:44:39.679694
5506 11:44:39.682770 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5507 11:44:39.682854
5508 11:44:39.685822 [CATrainingPosCal] consider 2 rank data
5509 11:44:39.688946 u2DelayCellTimex100 = 270/100 ps
5510 11:44:39.692781 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5511 11:44:39.696016 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5512 11:44:39.699129 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5513 11:44:39.705691 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5514 11:44:39.708955 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5515 11:44:39.712001 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5516 11:44:39.712127
5517 11:44:39.715785 CA PerBit enable=1, Macro0, CA PI delay=33
5518 11:44:39.715892
5519 11:44:39.718987 [CBTSetCACLKResult] CA Dly = 33
5520 11:44:39.719090 CS Dly: 5 (0~38)
5521 11:44:39.719194
5522 11:44:39.722143 ----->DramcWriteLeveling(PI) begin...
5523 11:44:39.725170 ==
5524 11:44:39.728871 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 11:44:39.731884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 11:44:39.731991 ==
5527 11:44:39.735537 Write leveling (Byte 0): 25 => 25
5528 11:44:39.738528 Write leveling (Byte 1): 27 => 27
5529 11:44:39.742034 DramcWriteLeveling(PI) end<-----
5530 11:44:39.742138
5531 11:44:39.742230 ==
5532 11:44:39.745189 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 11:44:39.748279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 11:44:39.748354 ==
5535 11:44:39.752096 [Gating] SW mode calibration
5536 11:44:39.758123 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5537 11:44:39.765157 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5538 11:44:39.768279 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5539 11:44:39.771485 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5540 11:44:39.778369 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 11:44:39.781609 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 11:44:39.784511 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 11:44:39.791438 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 11:44:39.794537 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (0 0) (0 0)
5545 11:44:39.797667 0 14 28 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
5546 11:44:39.804462 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5547 11:44:39.807775 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 11:44:39.810788 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 11:44:39.817733 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 11:44:39.820877 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 11:44:39.824017 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5552 11:44:39.830966 0 15 24 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5553 11:44:39.833953 0 15 28 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5554 11:44:39.837322 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 11:44:39.844018 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 11:44:39.847162 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 11:44:39.850081 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 11:44:39.856899 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 11:44:39.859911 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5560 11:44:39.863615 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5561 11:44:39.869926 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 11:44:39.873067 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:44:39.876829 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:44:39.883099 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:44:39.886319 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:44:39.890305 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 11:44:39.896271 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 11:44:39.899375 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 11:44:39.903035 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 11:44:39.909320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 11:44:39.913075 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 11:44:39.916114 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 11:44:39.922516 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 11:44:39.925583 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 11:44:39.929345 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 11:44:39.935614 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5577 11:44:39.939225 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5578 11:44:39.942154 Total UI for P1: 0, mck2ui 16
5579 11:44:39.945600 best dqsien dly found for B0: ( 1, 2, 24)
5580 11:44:39.948607 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5581 11:44:39.955742 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 11:44:39.958756 Total UI for P1: 0, mck2ui 16
5583 11:44:39.962286 best dqsien dly found for B1: ( 1, 2, 30)
5584 11:44:39.965276 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5585 11:44:39.968958 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5586 11:44:39.969068
5587 11:44:39.972027 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5588 11:44:39.975330 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5589 11:44:39.978432 [Gating] SW calibration Done
5590 11:44:39.978527 ==
5591 11:44:39.981578 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 11:44:39.984707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 11:44:39.984790 ==
5594 11:44:39.988431 RX Vref Scan: 0
5595 11:44:39.988547
5596 11:44:39.991445 RX Vref 0 -> 0, step: 1
5597 11:44:39.991583
5598 11:44:39.991676 RX Delay -80 -> 252, step: 8
5599 11:44:39.998697 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5600 11:44:40.001955 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5601 11:44:40.005121 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5602 11:44:40.008193 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5603 11:44:40.011314 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5604 11:44:40.018068 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5605 11:44:40.021246 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5606 11:44:40.024490 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5607 11:44:40.028245 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5608 11:44:40.031368 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5609 11:44:40.034606 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5610 11:44:40.041334 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5611 11:44:40.044502 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5612 11:44:40.047492 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5613 11:44:40.051172 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5614 11:44:40.054208 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5615 11:44:40.057774 ==
5616 11:44:40.060585 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 11:44:40.064329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 11:44:40.064440 ==
5619 11:44:40.064542 DQS Delay:
5620 11:44:40.067193 DQS0 = 0, DQS1 = 0
5621 11:44:40.067296 DQM Delay:
5622 11:44:40.070804 DQM0 = 99, DQM1 = 95
5623 11:44:40.070908 DQ Delay:
5624 11:44:40.073743 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5625 11:44:40.077217 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5626 11:44:40.080448 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5627 11:44:40.083559 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5628 11:44:40.083668
5629 11:44:40.083763
5630 11:44:40.083862 ==
5631 11:44:40.086704 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 11:44:40.090498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 11:44:40.093600 ==
5634 11:44:40.093726
5635 11:44:40.093827
5636 11:44:40.093940 TX Vref Scan disable
5637 11:44:40.096692 == TX Byte 0 ==
5638 11:44:40.100424 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5639 11:44:40.103511 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5640 11:44:40.106663 == TX Byte 1 ==
5641 11:44:40.110451 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5642 11:44:40.113605 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5643 11:44:40.116589 ==
5644 11:44:40.120160 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 11:44:40.123851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 11:44:40.123935 ==
5647 11:44:40.124003
5648 11:44:40.124081
5649 11:44:40.127032 TX Vref Scan disable
5650 11:44:40.127115 == TX Byte 0 ==
5651 11:44:40.133328 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5652 11:44:40.136497 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5653 11:44:40.136581 == TX Byte 1 ==
5654 11:44:40.143459 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5655 11:44:40.146676 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5656 11:44:40.146796
5657 11:44:40.146903 [DATLAT]
5658 11:44:40.149745 Freq=933, CH1 RK0
5659 11:44:40.149872
5660 11:44:40.149969 DATLAT Default: 0xd
5661 11:44:40.152897 0, 0xFFFF, sum = 0
5662 11:44:40.156011 1, 0xFFFF, sum = 0
5663 11:44:40.156129 2, 0xFFFF, sum = 0
5664 11:44:40.159742 3, 0xFFFF, sum = 0
5665 11:44:40.159828 4, 0xFFFF, sum = 0
5666 11:44:40.162929 5, 0xFFFF, sum = 0
5667 11:44:40.163013 6, 0xFFFF, sum = 0
5668 11:44:40.166027 7, 0xFFFF, sum = 0
5669 11:44:40.166102 8, 0xFFFF, sum = 0
5670 11:44:40.169495 9, 0xFFFF, sum = 0
5671 11:44:40.169583 10, 0x0, sum = 1
5672 11:44:40.173181 11, 0x0, sum = 2
5673 11:44:40.173269 12, 0x0, sum = 3
5674 11:44:40.176084 13, 0x0, sum = 4
5675 11:44:40.176171 best_step = 11
5676 11:44:40.176257
5677 11:44:40.176337 ==
5678 11:44:40.179161 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 11:44:40.182698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 11:44:40.182785 ==
5681 11:44:40.186182 RX Vref Scan: 1
5682 11:44:40.186268
5683 11:44:40.189415 RX Vref 0 -> 0, step: 1
5684 11:44:40.189501
5685 11:44:40.189587 RX Delay -53 -> 252, step: 4
5686 11:44:40.189668
5687 11:44:40.192493 Set Vref, RX VrefLevel [Byte0]: 53
5688 11:44:40.195641 [Byte1]: 49
5689 11:44:40.200811
5690 11:44:40.200899 Final RX Vref Byte 0 = 53 to rank0
5691 11:44:40.203890 Final RX Vref Byte 1 = 49 to rank0
5692 11:44:40.207564 Final RX Vref Byte 0 = 53 to rank1
5693 11:44:40.210716 Final RX Vref Byte 1 = 49 to rank1==
5694 11:44:40.213842 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 11:44:40.220715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 11:44:40.220800 ==
5697 11:44:40.220866 DQS Delay:
5698 11:44:40.223660 DQS0 = 0, DQS1 = 0
5699 11:44:40.223741 DQM Delay:
5700 11:44:40.223806 DQM0 = 98, DQM1 = 94
5701 11:44:40.227196 DQ Delay:
5702 11:44:40.230205 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =98
5703 11:44:40.233259 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5704 11:44:40.237052 DQ8 =78, DQ9 =84, DQ10 =94, DQ11 =88
5705 11:44:40.240249 DQ12 =104, DQ13 =104, DQ14 =100, DQ15 =102
5706 11:44:40.240322
5707 11:44:40.240384
5708 11:44:40.246489 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5709 11:44:40.250258 CH1 RK0: MR19=505, MR18=818
5710 11:44:40.256305 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5711 11:44:40.256388
5712 11:44:40.260051 ----->DramcWriteLeveling(PI) begin...
5713 11:44:40.260155 ==
5714 11:44:40.263182 Dram Type= 6, Freq= 0, CH_1, rank 1
5715 11:44:40.266244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 11:44:40.266343 ==
5717 11:44:40.269998 Write leveling (Byte 0): 26 => 26
5718 11:44:40.273104 Write leveling (Byte 1): 28 => 28
5719 11:44:40.276206 DramcWriteLeveling(PI) end<-----
5720 11:44:40.276288
5721 11:44:40.276352 ==
5722 11:44:40.279742 Dram Type= 6, Freq= 0, CH_1, rank 1
5723 11:44:40.286189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 11:44:40.286272 ==
5725 11:44:40.286338 [Gating] SW mode calibration
5726 11:44:40.295770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5727 11:44:40.299584 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5728 11:44:40.305779 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5729 11:44:40.309523 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5730 11:44:40.312617 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5731 11:44:40.318874 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5732 11:44:40.322138 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5733 11:44:40.325824 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5734 11:44:40.332426 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5735 11:44:40.335465 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
5736 11:44:40.338665 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5737 11:44:40.345565 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5738 11:44:40.348761 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5739 11:44:40.351917 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5740 11:44:40.358635 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5741 11:44:40.361638 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5742 11:44:40.365296 0 15 24 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
5743 11:44:40.371639 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5744 11:44:40.374958 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5745 11:44:40.378085 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5746 11:44:40.384925 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5747 11:44:40.388050 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5748 11:44:40.391105 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5749 11:44:40.397799 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5750 11:44:40.401246 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5751 11:44:40.404392 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5752 11:44:40.411014 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5753 11:44:40.414075 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5754 11:44:40.417808 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5755 11:44:40.424130 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5756 11:44:40.427298 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5757 11:44:40.431008 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5758 11:44:40.437694 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 11:44:40.440727 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 11:44:40.443860 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 11:44:40.450769 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 11:44:40.453862 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 11:44:40.457073 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 11:44:40.463832 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 11:44:40.466859 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 11:44:40.470472 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 11:44:40.476987 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5768 11:44:40.477105 Total UI for P1: 0, mck2ui 16
5769 11:44:40.483417 best dqsien dly found for B0: ( 1, 2, 26)
5770 11:44:40.487021 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 11:44:40.490188 Total UI for P1: 0, mck2ui 16
5772 11:44:40.493253 best dqsien dly found for B1: ( 1, 2, 28)
5773 11:44:40.496448 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5774 11:44:40.500122 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5775 11:44:40.500242
5776 11:44:40.503072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5777 11:44:40.506542 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5778 11:44:40.509968 [Gating] SW calibration Done
5779 11:44:40.510090 ==
5780 11:44:40.513038 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 11:44:40.519703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 11:44:40.519818 ==
5783 11:44:40.519935 RX Vref Scan: 0
5784 11:44:40.520053
5785 11:44:40.522659 RX Vref 0 -> 0, step: 1
5786 11:44:40.522769
5787 11:44:40.526435 RX Delay -80 -> 252, step: 8
5788 11:44:40.529567 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5789 11:44:40.532784 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5790 11:44:40.535901 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5791 11:44:40.539579 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5792 11:44:40.545881 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5793 11:44:40.548969 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5794 11:44:40.552654 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5795 11:44:40.555800 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5796 11:44:40.558990 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5797 11:44:40.562187 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5798 11:44:40.568855 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5799 11:44:40.572473 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5800 11:44:40.575446 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5801 11:44:40.578518 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5802 11:44:40.582182 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5803 11:44:40.588687 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5804 11:44:40.588770 ==
5805 11:44:40.591749 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 11:44:40.595429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 11:44:40.595512 ==
5808 11:44:40.595579 DQS Delay:
5809 11:44:40.598691 DQS0 = 0, DQS1 = 0
5810 11:44:40.598773 DQM Delay:
5811 11:44:40.601859 DQM0 = 97, DQM1 = 94
5812 11:44:40.601941 DQ Delay:
5813 11:44:40.605049 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5814 11:44:40.608213 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5815 11:44:40.611905 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5816 11:44:40.614783 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5817 11:44:40.614866
5818 11:44:40.614931
5819 11:44:40.614991 ==
5820 11:44:40.618409 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 11:44:40.624953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 11:44:40.625055 ==
5823 11:44:40.625124
5824 11:44:40.625185
5825 11:44:40.625243 TX Vref Scan disable
5826 11:44:40.628460 == TX Byte 0 ==
5827 11:44:40.631533 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5828 11:44:40.638316 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5829 11:44:40.638400 == TX Byte 1 ==
5830 11:44:40.641301 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5831 11:44:40.648146 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5832 11:44:40.648242 ==
5833 11:44:40.651265 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 11:44:40.654383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 11:44:40.654466 ==
5836 11:44:40.654532
5837 11:44:40.654593
5838 11:44:40.658067 TX Vref Scan disable
5839 11:44:40.661239 == TX Byte 0 ==
5840 11:44:40.664374 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5841 11:44:40.667543 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5842 11:44:40.670770 == TX Byte 1 ==
5843 11:44:40.674445 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5844 11:44:40.677473 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5845 11:44:40.677555
5846 11:44:40.677620 [DATLAT]
5847 11:44:40.680527 Freq=933, CH1 RK1
5848 11:44:40.680609
5849 11:44:40.684321 DATLAT Default: 0xb
5850 11:44:40.684403 0, 0xFFFF, sum = 0
5851 11:44:40.687458 1, 0xFFFF, sum = 0
5852 11:44:40.687541 2, 0xFFFF, sum = 0
5853 11:44:40.690647 3, 0xFFFF, sum = 0
5854 11:44:40.690730 4, 0xFFFF, sum = 0
5855 11:44:40.693783 5, 0xFFFF, sum = 0
5856 11:44:40.693866 6, 0xFFFF, sum = 0
5857 11:44:40.697484 7, 0xFFFF, sum = 0
5858 11:44:40.697567 8, 0xFFFF, sum = 0
5859 11:44:40.700471 9, 0xFFFF, sum = 0
5860 11:44:40.700554 10, 0x0, sum = 1
5861 11:44:40.704211 11, 0x0, sum = 2
5862 11:44:40.704294 12, 0x0, sum = 3
5863 11:44:40.707431 13, 0x0, sum = 4
5864 11:44:40.707514 best_step = 11
5865 11:44:40.707580
5866 11:44:40.707641 ==
5867 11:44:40.710588 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 11:44:40.716786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 11:44:40.716869 ==
5870 11:44:40.716936 RX Vref Scan: 0
5871 11:44:40.716998
5872 11:44:40.720405 RX Vref 0 -> 0, step: 1
5873 11:44:40.720515
5874 11:44:40.723476 RX Delay -53 -> 252, step: 4
5875 11:44:40.726602 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5876 11:44:40.730184 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5877 11:44:40.736829 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5878 11:44:40.739761 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5879 11:44:40.743447 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5880 11:44:40.746508 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5881 11:44:40.749424 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5882 11:44:40.756411 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5883 11:44:40.759475 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5884 11:44:40.762681 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5885 11:44:40.766262 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5886 11:44:40.769360 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5887 11:44:40.776280 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5888 11:44:40.779468 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5889 11:44:40.782483 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5890 11:44:40.786042 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5891 11:44:40.786154 ==
5892 11:44:40.789369 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 11:44:40.795807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 11:44:40.795923 ==
5895 11:44:40.796026 DQS Delay:
5896 11:44:40.799020 DQS0 = 0, DQS1 = 0
5897 11:44:40.799178 DQM Delay:
5898 11:44:40.799272 DQM0 = 97, DQM1 = 92
5899 11:44:40.802037 DQ Delay:
5900 11:44:40.805489 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =92
5901 11:44:40.808561 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5902 11:44:40.812364 DQ8 =78, DQ9 =82, DQ10 =94, DQ11 =84
5903 11:44:40.815533 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =100
5904 11:44:40.815614
5905 11:44:40.815679
5906 11:44:40.821795 [DQSOSCAuto] RK1, (LSB)MR18= 0xa20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5907 11:44:40.825479 CH1 RK1: MR19=505, MR18=A20
5908 11:44:40.831803 CH1_RK1: MR19=0x505, MR18=0xA20, DQSOSC=411, MR23=63, INC=64, DEC=42
5909 11:44:40.834838 [RxdqsGatingPostProcess] freq 933
5910 11:44:40.841357 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5911 11:44:40.844953 best DQS0 dly(2T, 0.5T) = (0, 10)
5912 11:44:40.845050 best DQS1 dly(2T, 0.5T) = (0, 10)
5913 11:44:40.848464 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5914 11:44:40.851437 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5915 11:44:40.854950 best DQS0 dly(2T, 0.5T) = (0, 10)
5916 11:44:40.858132 best DQS1 dly(2T, 0.5T) = (0, 10)
5917 11:44:40.861265 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5918 11:44:40.864294 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5919 11:44:40.868216 Pre-setting of DQS Precalculation
5920 11:44:40.874429 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5921 11:44:40.881437 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5922 11:44:40.887437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5923 11:44:40.887549
5924 11:44:40.887644
5925 11:44:40.891287 [Calibration Summary] 1866 Mbps
5926 11:44:40.891368 CH 0, Rank 0
5927 11:44:40.894381 SW Impedance : PASS
5928 11:44:40.897553 DUTY Scan : NO K
5929 11:44:40.897635 ZQ Calibration : PASS
5930 11:44:40.900619 Jitter Meter : NO K
5931 11:44:40.904303 CBT Training : PASS
5932 11:44:40.904386 Write leveling : PASS
5933 11:44:40.907370 RX DQS gating : PASS
5934 11:44:40.911035 RX DQ/DQS(RDDQC) : PASS
5935 11:44:40.911119 TX DQ/DQS : PASS
5936 11:44:40.914163 RX DATLAT : PASS
5937 11:44:40.917311 RX DQ/DQS(Engine): PASS
5938 11:44:40.917395 TX OE : NO K
5939 11:44:40.920544 All Pass.
5940 11:44:40.920626
5941 11:44:40.920692 CH 0, Rank 1
5942 11:44:40.923655 SW Impedance : PASS
5943 11:44:40.923739 DUTY Scan : NO K
5944 11:44:40.927561 ZQ Calibration : PASS
5945 11:44:40.930779 Jitter Meter : NO K
5946 11:44:40.930862 CBT Training : PASS
5947 11:44:40.933835 Write leveling : PASS
5948 11:44:40.937333 RX DQS gating : PASS
5949 11:44:40.937416 RX DQ/DQS(RDDQC) : PASS
5950 11:44:40.940249 TX DQ/DQS : PASS
5951 11:44:40.943664 RX DATLAT : PASS
5952 11:44:40.943746 RX DQ/DQS(Engine): PASS
5953 11:44:40.946716 TX OE : NO K
5954 11:44:40.946805 All Pass.
5955 11:44:40.946874
5956 11:44:40.950253 CH 1, Rank 0
5957 11:44:40.950364 SW Impedance : PASS
5958 11:44:40.953255 DUTY Scan : NO K
5959 11:44:40.953367 ZQ Calibration : PASS
5960 11:44:40.956985 Jitter Meter : NO K
5961 11:44:40.960408 CBT Training : PASS
5962 11:44:40.960535 Write leveling : PASS
5963 11:44:40.963394 RX DQS gating : PASS
5964 11:44:40.966456 RX DQ/DQS(RDDQC) : PASS
5965 11:44:40.966564 TX DQ/DQS : PASS
5966 11:44:40.969745 RX DATLAT : PASS
5967 11:44:40.972932 RX DQ/DQS(Engine): PASS
5968 11:44:40.973009 TX OE : NO K
5969 11:44:40.976805 All Pass.
5970 11:44:40.976876
5971 11:44:40.976938 CH 1, Rank 1
5972 11:44:40.979845 SW Impedance : PASS
5973 11:44:40.979951 DUTY Scan : NO K
5974 11:44:40.982998 ZQ Calibration : PASS
5975 11:44:40.986044 Jitter Meter : NO K
5976 11:44:40.986143 CBT Training : PASS
5977 11:44:40.989899 Write leveling : PASS
5978 11:44:40.992978 RX DQS gating : PASS
5979 11:44:40.993077 RX DQ/DQS(RDDQC) : PASS
5980 11:44:40.996176 TX DQ/DQS : PASS
5981 11:44:40.999297 RX DATLAT : PASS
5982 11:44:40.999393 RX DQ/DQS(Engine): PASS
5983 11:44:41.002518 TX OE : NO K
5984 11:44:41.002619 All Pass.
5985 11:44:41.002714
5986 11:44:41.005782 DramC Write-DBI off
5987 11:44:41.009432 PER_BANK_REFRESH: Hybrid Mode
5988 11:44:41.009507 TX_TRACKING: ON
5989 11:44:41.019391 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5990 11:44:41.022473 [FAST_K] Save calibration result to emmc
5991 11:44:41.025449 dramc_set_vcore_voltage set vcore to 650000
5992 11:44:41.029128 Read voltage for 400, 6
5993 11:44:41.029208 Vio18 = 0
5994 11:44:41.032400 Vcore = 650000
5995 11:44:41.032478 Vdram = 0
5996 11:44:41.032549 Vddq = 0
5997 11:44:41.032611 Vmddr = 0
5998 11:44:41.038763 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5999 11:44:41.045381 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6000 11:44:41.045471 MEM_TYPE=3, freq_sel=20
6001 11:44:41.048448 sv_algorithm_assistance_LP4_800
6002 11:44:41.052034 ============ PULL DRAM RESETB DOWN ============
6003 11:44:41.058548 ========== PULL DRAM RESETB DOWN end =========
6004 11:44:41.062105 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6005 11:44:41.065134 ===================================
6006 11:44:41.068511 LPDDR4 DRAM CONFIGURATION
6007 11:44:41.071493 ===================================
6008 11:44:41.071576 EX_ROW_EN[0] = 0x0
6009 11:44:41.075209 EX_ROW_EN[1] = 0x0
6010 11:44:41.075302 LP4Y_EN = 0x0
6011 11:44:41.078318 WORK_FSP = 0x0
6012 11:44:41.078424 WL = 0x2
6013 11:44:41.081442 RL = 0x2
6014 11:44:41.084629 BL = 0x2
6015 11:44:41.084712 RPST = 0x0
6016 11:44:41.088411 RD_PRE = 0x0
6017 11:44:41.088486 WR_PRE = 0x1
6018 11:44:41.091551 WR_PST = 0x0
6019 11:44:41.091653 DBI_WR = 0x0
6020 11:44:41.094620 DBI_RD = 0x0
6021 11:44:41.094703 OTF = 0x1
6022 11:44:41.098123 ===================================
6023 11:44:41.101447 ===================================
6024 11:44:41.104593 ANA top config
6025 11:44:41.107688 ===================================
6026 11:44:41.107805 DLL_ASYNC_EN = 0
6027 11:44:41.111505 ALL_SLAVE_EN = 1
6028 11:44:41.114832 NEW_RANK_MODE = 1
6029 11:44:41.117758 DLL_IDLE_MODE = 1
6030 11:44:41.120956 LP45_APHY_COMB_EN = 1
6031 11:44:41.121041 TX_ODT_DIS = 1
6032 11:44:41.124636 NEW_8X_MODE = 1
6033 11:44:41.127580 ===================================
6034 11:44:41.131230 ===================================
6035 11:44:41.134385 data_rate = 800
6036 11:44:41.137532 CKR = 1
6037 11:44:41.140646 DQ_P2S_RATIO = 4
6038 11:44:41.143838 ===================================
6039 11:44:41.143941 CA_P2S_RATIO = 4
6040 11:44:41.147623 DQ_CA_OPEN = 0
6041 11:44:41.150661 DQ_SEMI_OPEN = 1
6042 11:44:41.153791 CA_SEMI_OPEN = 1
6043 11:44:41.157607 CA_FULL_RATE = 0
6044 11:44:41.160711 DQ_CKDIV4_EN = 0
6045 11:44:41.163743 CA_CKDIV4_EN = 1
6046 11:44:41.163866 CA_PREDIV_EN = 0
6047 11:44:41.167476 PH8_DLY = 0
6048 11:44:41.170489 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6049 11:44:41.173569 DQ_AAMCK_DIV = 0
6050 11:44:41.177121 CA_AAMCK_DIV = 0
6051 11:44:41.180046 CA_ADMCK_DIV = 4
6052 11:44:41.180150 DQ_TRACK_CA_EN = 0
6053 11:44:41.183902 CA_PICK = 800
6054 11:44:41.187171 CA_MCKIO = 400
6055 11:44:41.190462 MCKIO_SEMI = 400
6056 11:44:41.193510 PLL_FREQ = 3016
6057 11:44:41.196885 DQ_UI_PI_RATIO = 32
6058 11:44:41.199882 CA_UI_PI_RATIO = 32
6059 11:44:41.203721 ===================================
6060 11:44:41.206897 ===================================
6061 11:44:41.206983 memory_type:LPDDR4
6062 11:44:41.210105 GP_NUM : 10
6063 11:44:41.213159 SRAM_EN : 1
6064 11:44:41.213245 MD32_EN : 0
6065 11:44:41.216438 ===================================
6066 11:44:41.219569 [ANA_INIT] >>>>>>>>>>>>>>
6067 11:44:41.223277 <<<<<< [CONFIGURE PHASE]: ANA_TX
6068 11:44:41.226349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6069 11:44:41.230120 ===================================
6070 11:44:41.233210 data_rate = 800,PCW = 0X7400
6071 11:44:41.236433 ===================================
6072 11:44:41.239467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6073 11:44:41.243274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6074 11:44:41.256357 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6075 11:44:41.259483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6076 11:44:41.262676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6077 11:44:41.265884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6078 11:44:41.269550 [ANA_INIT] flow start
6079 11:44:41.272563 [ANA_INIT] PLL >>>>>>>>
6080 11:44:41.272647 [ANA_INIT] PLL <<<<<<<<
6081 11:44:41.276145 [ANA_INIT] MIDPI >>>>>>>>
6082 11:44:41.279183 [ANA_INIT] MIDPI <<<<<<<<
6083 11:44:41.282640 [ANA_INIT] DLL >>>>>>>>
6084 11:44:41.282726 [ANA_INIT] flow end
6085 11:44:41.285671 ============ LP4 DIFF to SE enter ============
6086 11:44:41.292405 ============ LP4 DIFF to SE exit ============
6087 11:44:41.292489 [ANA_INIT] <<<<<<<<<<<<<
6088 11:44:41.295651 [Flow] Enable top DCM control >>>>>
6089 11:44:41.298851 [Flow] Enable top DCM control <<<<<
6090 11:44:41.301987 Enable DLL master slave shuffle
6091 11:44:41.308772 ==============================================================
6092 11:44:41.308854 Gating Mode config
6093 11:44:41.315150 ==============================================================
6094 11:44:41.318422 Config description:
6095 11:44:41.328212 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6096 11:44:41.334932 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6097 11:44:41.338143 SELPH_MODE 0: By rank 1: By Phase
6098 11:44:41.345121 ==============================================================
6099 11:44:41.348309 GAT_TRACK_EN = 0
6100 11:44:41.351530 RX_GATING_MODE = 2
6101 11:44:41.354707 RX_GATING_TRACK_MODE = 2
6102 11:44:41.354806 SELPH_MODE = 1
6103 11:44:41.358369 PICG_EARLY_EN = 1
6104 11:44:41.361151 VALID_LAT_VALUE = 1
6105 11:44:41.368015 ==============================================================
6106 11:44:41.371272 Enter into Gating configuration >>>>
6107 11:44:41.374341 Exit from Gating configuration <<<<
6108 11:44:41.377504 Enter into DVFS_PRE_config >>>>>
6109 11:44:41.387718 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6110 11:44:41.390566 Exit from DVFS_PRE_config <<<<<
6111 11:44:41.393802 Enter into PICG configuration >>>>
6112 11:44:41.397253 Exit from PICG configuration <<<<
6113 11:44:41.400918 [RX_INPUT] configuration >>>>>
6114 11:44:41.403982 [RX_INPUT] configuration <<<<<
6115 11:44:41.410270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6116 11:44:41.414052 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6117 11:44:41.420232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6118 11:44:41.427100 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6119 11:44:41.433244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6120 11:44:41.440170 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6121 11:44:41.443319 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6122 11:44:41.446485 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6123 11:44:41.449682 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6124 11:44:41.456695 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6125 11:44:41.459756 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6126 11:44:41.462708 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6127 11:44:41.466482 ===================================
6128 11:44:41.469515 LPDDR4 DRAM CONFIGURATION
6129 11:44:41.472775 ===================================
6130 11:44:41.475924 EX_ROW_EN[0] = 0x0
6131 11:44:41.476027 EX_ROW_EN[1] = 0x0
6132 11:44:41.479133 LP4Y_EN = 0x0
6133 11:44:41.479230 WORK_FSP = 0x0
6134 11:44:41.483064 WL = 0x2
6135 11:44:41.483141 RL = 0x2
6136 11:44:41.486186 BL = 0x2
6137 11:44:41.486299 RPST = 0x0
6138 11:44:41.489209 RD_PRE = 0x0
6139 11:44:41.489316 WR_PRE = 0x1
6140 11:44:41.492776 WR_PST = 0x0
6141 11:44:41.492883 DBI_WR = 0x0
6142 11:44:41.495631 DBI_RD = 0x0
6143 11:44:41.495728 OTF = 0x1
6144 11:44:41.499123 ===================================
6145 11:44:41.505446 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6146 11:44:41.509042 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6147 11:44:41.512548 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 11:44:41.515635 ===================================
6149 11:44:41.518782 LPDDR4 DRAM CONFIGURATION
6150 11:44:41.521926 ===================================
6151 11:44:41.525797 EX_ROW_EN[0] = 0x10
6152 11:44:41.525881 EX_ROW_EN[1] = 0x0
6153 11:44:41.528917 LP4Y_EN = 0x0
6154 11:44:41.528993 WORK_FSP = 0x0
6155 11:44:41.531989 WL = 0x2
6156 11:44:41.532089 RL = 0x2
6157 11:44:41.535089 BL = 0x2
6158 11:44:41.535171 RPST = 0x0
6159 11:44:41.538820 RD_PRE = 0x0
6160 11:44:41.538899 WR_PRE = 0x1
6161 11:44:41.541979 WR_PST = 0x0
6162 11:44:41.542102 DBI_WR = 0x0
6163 11:44:41.545149 DBI_RD = 0x0
6164 11:44:41.548243 OTF = 0x1
6165 11:44:41.548323 ===================================
6166 11:44:41.555072 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6167 11:44:41.560206 nWR fixed to 30
6168 11:44:41.563391 [ModeRegInit_LP4] CH0 RK0
6169 11:44:41.563513 [ModeRegInit_LP4] CH0 RK1
6170 11:44:41.566515 [ModeRegInit_LP4] CH1 RK0
6171 11:44:41.570068 [ModeRegInit_LP4] CH1 RK1
6172 11:44:41.570179 match AC timing 19
6173 11:44:41.576803 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6174 11:44:41.579946 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6175 11:44:41.583168 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6176 11:44:41.589529 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6177 11:44:41.593294 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6178 11:44:41.593402 ==
6179 11:44:41.596335 Dram Type= 6, Freq= 0, CH_0, rank 0
6180 11:44:41.599399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6181 11:44:41.599500 ==
6182 11:44:41.606020 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6183 11:44:41.612588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6184 11:44:41.616328 [CA 0] Center 36 (8~64) winsize 57
6185 11:44:41.619225 [CA 1] Center 36 (8~64) winsize 57
6186 11:44:41.622813 [CA 2] Center 36 (8~64) winsize 57
6187 11:44:41.625974 [CA 3] Center 36 (8~64) winsize 57
6188 11:44:41.629162 [CA 4] Center 36 (8~64) winsize 57
6189 11:44:41.632326 [CA 5] Center 36 (8~64) winsize 57
6190 11:44:41.632413
6191 11:44:41.636050 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6192 11:44:41.636134
6193 11:44:41.639104 [CATrainingPosCal] consider 1 rank data
6194 11:44:41.642290 u2DelayCellTimex100 = 270/100 ps
6195 11:44:41.646007 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6196 11:44:41.649180 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6197 11:44:41.652351 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6198 11:44:41.655594 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6199 11:44:41.658669 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6200 11:44:41.661791 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6201 11:44:41.661870
6202 11:44:41.668539 CA PerBit enable=1, Macro0, CA PI delay=36
6203 11:44:41.668654
6204 11:44:41.671615 [CBTSetCACLKResult] CA Dly = 36
6205 11:44:41.671722 CS Dly: 1 (0~32)
6206 11:44:41.671817 ==
6207 11:44:41.675286 Dram Type= 6, Freq= 0, CH_0, rank 1
6208 11:44:41.678211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6209 11:44:41.678321 ==
6210 11:44:41.685223 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6211 11:44:41.691499 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6212 11:44:41.695198 [CA 0] Center 36 (8~64) winsize 57
6213 11:44:41.698277 [CA 1] Center 36 (8~64) winsize 57
6214 11:44:41.701384 [CA 2] Center 36 (8~64) winsize 57
6215 11:44:41.704567 [CA 3] Center 36 (8~64) winsize 57
6216 11:44:41.708178 [CA 4] Center 36 (8~64) winsize 57
6217 11:44:41.711164 [CA 5] Center 36 (8~64) winsize 57
6218 11:44:41.711238
6219 11:44:41.714716 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6220 11:44:41.714824
6221 11:44:41.717626 [CATrainingPosCal] consider 2 rank data
6222 11:44:41.721211 u2DelayCellTimex100 = 270/100 ps
6223 11:44:41.724252 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:44:41.727856 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:44:41.730948 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:44:41.734169 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:44:41.737395 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 11:44:41.741154 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 11:44:41.741265
6230 11:44:41.747355 CA PerBit enable=1, Macro0, CA PI delay=36
6231 11:44:41.747480
6232 11:44:41.747564 [CBTSetCACLKResult] CA Dly = 36
6233 11:44:41.750555 CS Dly: 1 (0~32)
6234 11:44:41.750642
6235 11:44:41.754417 ----->DramcWriteLeveling(PI) begin...
6236 11:44:41.754533 ==
6237 11:44:41.757666 Dram Type= 6, Freq= 0, CH_0, rank 0
6238 11:44:41.760865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 11:44:41.760971 ==
6240 11:44:41.763929 Write leveling (Byte 0): 40 => 8
6241 11:44:41.767065 Write leveling (Byte 1): 40 => 8
6242 11:44:41.770880 DramcWriteLeveling(PI) end<-----
6243 11:44:41.770992
6244 11:44:41.771090 ==
6245 11:44:41.774046 Dram Type= 6, Freq= 0, CH_0, rank 0
6246 11:44:41.777178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 11:44:41.780790 ==
6248 11:44:41.780872 [Gating] SW mode calibration
6249 11:44:41.790238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6250 11:44:41.793541 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6251 11:44:41.796695 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6252 11:44:41.803460 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6253 11:44:41.806515 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6254 11:44:41.810237 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6255 11:44:41.816930 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6256 11:44:41.819934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6257 11:44:41.822931 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6258 11:44:41.830089 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6259 11:44:41.833069 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 11:44:41.836711 Total UI for P1: 0, mck2ui 16
6261 11:44:41.839882 best dqsien dly found for B0: ( 0, 14, 24)
6262 11:44:41.842979 Total UI for P1: 0, mck2ui 16
6263 11:44:41.846058 best dqsien dly found for B1: ( 0, 14, 24)
6264 11:44:41.849289 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6265 11:44:41.852851 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6266 11:44:41.852933
6267 11:44:41.855986 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6268 11:44:41.862911 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6269 11:44:41.862997 [Gating] SW calibration Done
6270 11:44:41.866081 ==
6271 11:44:41.869201 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 11:44:41.872306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 11:44:41.872395 ==
6274 11:44:41.872463 RX Vref Scan: 0
6275 11:44:41.872532
6276 11:44:41.876084 RX Vref 0 -> 0, step: 1
6277 11:44:41.876172
6278 11:44:41.879209 RX Delay -410 -> 252, step: 16
6279 11:44:41.882305 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6280 11:44:41.888969 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6281 11:44:41.892116 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6282 11:44:41.895271 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6283 11:44:41.899051 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6284 11:44:41.905222 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6285 11:44:41.908794 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6286 11:44:41.911926 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6287 11:44:41.915018 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6288 11:44:41.921487 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6289 11:44:41.925041 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6290 11:44:41.928612 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6291 11:44:41.931608 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6292 11:44:41.938021 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6293 11:44:41.941563 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6294 11:44:41.944598 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6295 11:44:41.944703 ==
6296 11:44:41.947882 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 11:44:41.954683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 11:44:41.954794 ==
6299 11:44:41.954896 DQS Delay:
6300 11:44:41.957662 DQS0 = 35, DQS1 = 51
6301 11:44:41.957767 DQM Delay:
6302 11:44:41.960897 DQM0 = 5, DQM1 = 10
6303 11:44:41.961004 DQ Delay:
6304 11:44:41.964659 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6305 11:44:41.967821 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6306 11:44:41.967897 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6307 11:44:41.970988 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6308 11:44:41.971069
6309 11:44:41.974672
6310 11:44:41.974753 ==
6311 11:44:41.977805 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 11:44:41.980961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 11:44:41.981044 ==
6314 11:44:41.981109
6315 11:44:41.981169
6316 11:44:41.984058 TX Vref Scan disable
6317 11:44:41.984140 == TX Byte 0 ==
6318 11:44:41.987710 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6319 11:44:41.993887 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6320 11:44:41.993970 == TX Byte 1 ==
6321 11:44:41.997673 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6322 11:44:42.003874 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6323 11:44:42.003957 ==
6324 11:44:42.007590 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 11:44:42.010733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 11:44:42.010816 ==
6327 11:44:42.010881
6328 11:44:42.010942
6329 11:44:42.013730 TX Vref Scan disable
6330 11:44:42.013839 == TX Byte 0 ==
6331 11:44:42.020742 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6332 11:44:42.023865 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6333 11:44:42.023976 == TX Byte 1 ==
6334 11:44:42.030012 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6335 11:44:42.033526 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6336 11:44:42.033651
6337 11:44:42.033768 [DATLAT]
6338 11:44:42.037201 Freq=400, CH0 RK0
6339 11:44:42.037312
6340 11:44:42.037412 DATLAT Default: 0xf
6341 11:44:42.040182 0, 0xFFFF, sum = 0
6342 11:44:42.040288 1, 0xFFFF, sum = 0
6343 11:44:42.043164 2, 0xFFFF, sum = 0
6344 11:44:42.043271 3, 0xFFFF, sum = 0
6345 11:44:42.046686 4, 0xFFFF, sum = 0
6346 11:44:42.046798 5, 0xFFFF, sum = 0
6347 11:44:42.050059 6, 0xFFFF, sum = 0
6348 11:44:42.050161 7, 0xFFFF, sum = 0
6349 11:44:42.053103 8, 0xFFFF, sum = 0
6350 11:44:42.053204 9, 0xFFFF, sum = 0
6351 11:44:42.056818 10, 0xFFFF, sum = 0
6352 11:44:42.059911 11, 0xFFFF, sum = 0
6353 11:44:42.059986 12, 0xFFFF, sum = 0
6354 11:44:42.063123 13, 0x0, sum = 1
6355 11:44:42.063231 14, 0x0, sum = 2
6356 11:44:42.066201 15, 0x0, sum = 3
6357 11:44:42.066304 16, 0x0, sum = 4
6358 11:44:42.066403 best_step = 14
6359 11:44:42.066494
6360 11:44:42.069973 ==
6361 11:44:42.073134 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 11:44:42.076158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 11:44:42.076261 ==
6364 11:44:42.076361 RX Vref Scan: 1
6365 11:44:42.076455
6366 11:44:42.079860 RX Vref 0 -> 0, step: 1
6367 11:44:42.079961
6368 11:44:42.082976 RX Delay -343 -> 252, step: 8
6369 11:44:42.083083
6370 11:44:42.086000 Set Vref, RX VrefLevel [Byte0]: 51
6371 11:44:42.089179 [Byte1]: 49
6372 11:44:42.093465
6373 11:44:42.093585 Final RX Vref Byte 0 = 51 to rank0
6374 11:44:42.096571 Final RX Vref Byte 1 = 49 to rank0
6375 11:44:42.099690 Final RX Vref Byte 0 = 51 to rank1
6376 11:44:42.103583 Final RX Vref Byte 1 = 49 to rank1==
6377 11:44:42.106700 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 11:44:42.112965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 11:44:42.113088 ==
6380 11:44:42.113191 DQS Delay:
6381 11:44:42.116564 DQS0 = 44, DQS1 = 56
6382 11:44:42.116676 DQM Delay:
6383 11:44:42.116795 DQM0 = 10, DQM1 = 14
6384 11:44:42.119624 DQ Delay:
6385 11:44:42.122805 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6386 11:44:42.125911 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6387 11:44:42.129717 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6388 11:44:42.132803 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6389 11:44:42.132921
6390 11:44:42.133031
6391 11:44:42.139500 [DQSOSCAuto] RK0, (LSB)MR18= 0x9589, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6392 11:44:42.142386 CH0 RK0: MR19=C0C, MR18=9589
6393 11:44:42.149104 CH0_RK0: MR19=0xC0C, MR18=0x9589, DQSOSC=391, MR23=63, INC=386, DEC=257
6394 11:44:42.149194 ==
6395 11:44:42.152621 Dram Type= 6, Freq= 0, CH_0, rank 1
6396 11:44:42.155961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 11:44:42.156074 ==
6398 11:44:42.158970 [Gating] SW mode calibration
6399 11:44:42.165842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6400 11:44:42.172559 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6401 11:44:42.175660 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6402 11:44:42.178739 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6403 11:44:42.185746 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 11:44:42.188938 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6405 11:44:42.192048 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 11:44:42.198874 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 11:44:42.202046 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 11:44:42.205164 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 11:44:42.212211 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 11:44:42.215471 Total UI for P1: 0, mck2ui 16
6411 11:44:42.218567 best dqsien dly found for B0: ( 0, 14, 24)
6412 11:44:42.221707 Total UI for P1: 0, mck2ui 16
6413 11:44:42.224717 best dqsien dly found for B1: ( 0, 14, 24)
6414 11:44:42.228564 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6415 11:44:42.231669 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6416 11:44:42.231742
6417 11:44:42.234987 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6418 11:44:42.238203 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6419 11:44:42.241381 [Gating] SW calibration Done
6420 11:44:42.241498 ==
6421 11:44:42.244902 Dram Type= 6, Freq= 0, CH_0, rank 1
6422 11:44:42.247899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 11:44:42.248003 ==
6424 11:44:42.251619 RX Vref Scan: 0
6425 11:44:42.251703
6426 11:44:42.254548 RX Vref 0 -> 0, step: 1
6427 11:44:42.254660
6428 11:44:42.258203 RX Delay -410 -> 252, step: 16
6429 11:44:42.261102 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6430 11:44:42.264535 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6431 11:44:42.267981 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6432 11:44:42.274663 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6433 11:44:42.277813 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6434 11:44:42.281033 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6435 11:44:42.284715 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6436 11:44:42.291280 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6437 11:44:42.294367 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6438 11:44:42.297553 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6439 11:44:42.300829 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6440 11:44:42.307059 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6441 11:44:42.310777 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6442 11:44:42.313926 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6443 11:44:42.320777 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6444 11:44:42.324135 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6445 11:44:42.324222 ==
6446 11:44:42.327285 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 11:44:42.330428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 11:44:42.330514 ==
6449 11:44:42.333549 DQS Delay:
6450 11:44:42.333633 DQS0 = 35, DQS1 = 59
6451 11:44:42.336608 DQM Delay:
6452 11:44:42.336692 DQM0 = 7, DQM1 = 17
6453 11:44:42.336759 DQ Delay:
6454 11:44:42.339868 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6455 11:44:42.343632 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6456 11:44:42.346792 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6457 11:44:42.350368 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6458 11:44:42.350453
6459 11:44:42.350521
6460 11:44:42.350582 ==
6461 11:44:42.353324 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 11:44:42.356565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 11:44:42.359663 ==
6464 11:44:42.359747
6465 11:44:42.359813
6466 11:44:42.359875 TX Vref Scan disable
6467 11:44:42.363418 == TX Byte 0 ==
6468 11:44:42.366355 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6469 11:44:42.369953 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6470 11:44:42.372837 == TX Byte 1 ==
6471 11:44:42.376378 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6472 11:44:42.379444 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6473 11:44:42.379553 ==
6474 11:44:42.382982 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 11:44:42.389787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 11:44:42.389902 ==
6477 11:44:42.390010
6478 11:44:42.390107
6479 11:44:42.390201 TX Vref Scan disable
6480 11:44:42.392908 == TX Byte 0 ==
6481 11:44:42.396025 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6482 11:44:42.399127 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6483 11:44:42.402909 == TX Byte 1 ==
6484 11:44:42.405983 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6485 11:44:42.409019 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6486 11:44:42.409107
6487 11:44:42.412848 [DATLAT]
6488 11:44:42.412932 Freq=400, CH0 RK1
6489 11:44:42.412999
6490 11:44:42.415988 DATLAT Default: 0xe
6491 11:44:42.416095 0, 0xFFFF, sum = 0
6492 11:44:42.419149 1, 0xFFFF, sum = 0
6493 11:44:42.419247 2, 0xFFFF, sum = 0
6494 11:44:42.422209 3, 0xFFFF, sum = 0
6495 11:44:42.422315 4, 0xFFFF, sum = 0
6496 11:44:42.425318 5, 0xFFFF, sum = 0
6497 11:44:42.429132 6, 0xFFFF, sum = 0
6498 11:44:42.429217 7, 0xFFFF, sum = 0
6499 11:44:42.432247 8, 0xFFFF, sum = 0
6500 11:44:42.432333 9, 0xFFFF, sum = 0
6501 11:44:42.435408 10, 0xFFFF, sum = 0
6502 11:44:42.435494 11, 0xFFFF, sum = 0
6503 11:44:42.438503 12, 0xFFFF, sum = 0
6504 11:44:42.438619 13, 0x0, sum = 1
6505 11:44:42.442227 14, 0x0, sum = 2
6506 11:44:42.442337 15, 0x0, sum = 3
6507 11:44:42.445330 16, 0x0, sum = 4
6508 11:44:42.445433 best_step = 14
6509 11:44:42.445526
6510 11:44:42.445618 ==
6511 11:44:42.448443 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 11:44:42.451634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 11:44:42.455243 ==
6514 11:44:42.455325 RX Vref Scan: 0
6515 11:44:42.455390
6516 11:44:42.458236 RX Vref 0 -> 0, step: 1
6517 11:44:42.458338
6518 11:44:42.462105 RX Delay -359 -> 252, step: 8
6519 11:44:42.465170 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6520 11:44:42.472020 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6521 11:44:42.474979 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6522 11:44:42.478546 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6523 11:44:42.484985 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6524 11:44:42.487951 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6525 11:44:42.491500 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6526 11:44:42.494605 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6527 11:44:42.501570 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6528 11:44:42.504706 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6529 11:44:42.507800 iDelay=209, Bit 10, Center -40 (-279 ~ 200) 480
6530 11:44:42.511372 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6531 11:44:42.517526 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6532 11:44:42.520821 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6533 11:44:42.524464 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6534 11:44:42.527567 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6535 11:44:42.530816 ==
6536 11:44:42.533960 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 11:44:42.537576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 11:44:42.537689 ==
6539 11:44:42.537798 DQS Delay:
6540 11:44:42.540816 DQS0 = 44, DQS1 = 60
6541 11:44:42.540929 DQM Delay:
6542 11:44:42.543925 DQM0 = 9, DQM1 = 14
6543 11:44:42.544042 DQ Delay:
6544 11:44:42.547263 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6545 11:44:42.550463 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6546 11:44:42.554201 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6547 11:44:42.557369 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6548 11:44:42.557452
6549 11:44:42.557518
6550 11:44:42.564112 [DQSOSCAuto] RK1, (LSB)MR18= 0x817a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6551 11:44:42.567103 CH0 RK1: MR19=C0C, MR18=817A
6552 11:44:42.573483 CH0_RK1: MR19=0xC0C, MR18=0x817A, DQSOSC=393, MR23=63, INC=382, DEC=254
6553 11:44:42.577058 [RxdqsGatingPostProcess] freq 400
6554 11:44:42.583686 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6555 11:44:42.583796 best DQS0 dly(2T, 0.5T) = (0, 10)
6556 11:44:42.586618 best DQS1 dly(2T, 0.5T) = (0, 10)
6557 11:44:42.590206 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6558 11:44:42.593836 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6559 11:44:42.596956 best DQS0 dly(2T, 0.5T) = (0, 10)
6560 11:44:42.599960 best DQS1 dly(2T, 0.5T) = (0, 10)
6561 11:44:42.603709 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6562 11:44:42.606804 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6563 11:44:42.610039 Pre-setting of DQS Precalculation
6564 11:44:42.616679 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6565 11:44:42.616766 ==
6566 11:44:42.619698 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 11:44:42.623391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 11:44:42.623475 ==
6569 11:44:42.629622 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6570 11:44:42.632849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6571 11:44:42.636588 [CA 0] Center 36 (8~64) winsize 57
6572 11:44:42.639645 [CA 1] Center 36 (8~64) winsize 57
6573 11:44:42.642803 [CA 2] Center 36 (8~64) winsize 57
6574 11:44:42.646444 [CA 3] Center 36 (8~64) winsize 57
6575 11:44:42.649612 [CA 4] Center 36 (8~64) winsize 57
6576 11:44:42.652857 [CA 5] Center 36 (8~64) winsize 57
6577 11:44:42.652962
6578 11:44:42.655976 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6579 11:44:42.656077
6580 11:44:42.659034 [CATrainingPosCal] consider 1 rank data
6581 11:44:42.662859 u2DelayCellTimex100 = 270/100 ps
6582 11:44:42.665877 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6583 11:44:42.672569 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6584 11:44:42.675747 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6585 11:44:42.678918 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6586 11:44:42.682581 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6587 11:44:42.685629 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6588 11:44:42.685714
6589 11:44:42.688665 CA PerBit enable=1, Macro0, CA PI delay=36
6590 11:44:42.688749
6591 11:44:42.692117 [CBTSetCACLKResult] CA Dly = 36
6592 11:44:42.695619 CS Dly: 1 (0~32)
6593 11:44:42.695703 ==
6594 11:44:42.698595 Dram Type= 6, Freq= 0, CH_1, rank 1
6595 11:44:42.701997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 11:44:42.702082 ==
6597 11:44:42.708906 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6598 11:44:42.712098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6599 11:44:42.715192 [CA 0] Center 36 (8~64) winsize 57
6600 11:44:42.718900 [CA 1] Center 36 (8~64) winsize 57
6601 11:44:42.721943 [CA 2] Center 36 (8~64) winsize 57
6602 11:44:42.725013 [CA 3] Center 36 (8~64) winsize 57
6603 11:44:42.728716 [CA 4] Center 36 (8~64) winsize 57
6604 11:44:42.731881 [CA 5] Center 36 (8~64) winsize 57
6605 11:44:42.731966
6606 11:44:42.734897 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6607 11:44:42.734982
6608 11:44:42.738061 [CATrainingPosCal] consider 2 rank data
6609 11:44:42.741986 u2DelayCellTimex100 = 270/100 ps
6610 11:44:42.744910 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:44:42.751189 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:44:42.754971 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:44:42.757988 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:44:42.761080 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 11:44:42.764313 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 11:44:42.764408
6617 11:44:42.768018 CA PerBit enable=1, Macro0, CA PI delay=36
6618 11:44:42.768132
6619 11:44:42.771036 [CBTSetCACLKResult] CA Dly = 36
6620 11:44:42.774512 CS Dly: 1 (0~32)
6621 11:44:42.774636
6622 11:44:42.777805 ----->DramcWriteLeveling(PI) begin...
6623 11:44:42.777899 ==
6624 11:44:42.780856 Dram Type= 6, Freq= 0, CH_1, rank 0
6625 11:44:42.784040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 11:44:42.784121 ==
6627 11:44:42.787798 Write leveling (Byte 0): 40 => 8
6628 11:44:42.790782 Write leveling (Byte 1): 40 => 8
6629 11:44:42.794288 DramcWriteLeveling(PI) end<-----
6630 11:44:42.794399
6631 11:44:42.794469 ==
6632 11:44:42.797272 Dram Type= 6, Freq= 0, CH_1, rank 0
6633 11:44:42.800762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 11:44:42.800843 ==
6635 11:44:42.803797 [Gating] SW mode calibration
6636 11:44:42.810380 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6637 11:44:42.817284 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6638 11:44:42.820416 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6639 11:44:42.823632 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6640 11:44:42.830235 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6641 11:44:42.833344 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6642 11:44:42.837100 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6643 11:44:42.843426 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6644 11:44:42.847287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6645 11:44:42.850217 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6646 11:44:42.856764 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 11:44:42.859832 Total UI for P1: 0, mck2ui 16
6648 11:44:42.863574 best dqsien dly found for B0: ( 0, 14, 24)
6649 11:44:42.863695 Total UI for P1: 0, mck2ui 16
6650 11:44:42.869867 best dqsien dly found for B1: ( 0, 14, 24)
6651 11:44:42.873064 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6652 11:44:42.876682 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6653 11:44:42.876767
6654 11:44:42.879739 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6655 11:44:42.882917 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6656 11:44:42.886164 [Gating] SW calibration Done
6657 11:44:42.886249 ==
6658 11:44:42.889219 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 11:44:42.893018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 11:44:42.893103 ==
6661 11:44:42.896128 RX Vref Scan: 0
6662 11:44:42.896243
6663 11:44:42.899134 RX Vref 0 -> 0, step: 1
6664 11:44:42.899216
6665 11:44:42.902676 RX Delay -410 -> 252, step: 16
6666 11:44:42.905677 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6667 11:44:42.909210 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6668 11:44:42.912224 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6669 11:44:42.918905 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6670 11:44:42.922070 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6671 11:44:42.925731 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6672 11:44:42.928746 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6673 11:44:42.935649 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6674 11:44:42.938736 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6675 11:44:42.941889 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6676 11:44:42.945643 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6677 11:44:42.951971 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6678 11:44:42.955710 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6679 11:44:42.958876 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6680 11:44:42.965215 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6681 11:44:42.968836 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6682 11:44:42.968968 ==
6683 11:44:42.971957 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 11:44:42.975209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 11:44:42.975286 ==
6686 11:44:42.978758 DQS Delay:
6687 11:44:42.978869 DQS0 = 35, DQS1 = 51
6688 11:44:42.978964 DQM Delay:
6689 11:44:42.981692 DQM0 = 6, DQM1 = 13
6690 11:44:42.981802 DQ Delay:
6691 11:44:42.984682 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6692 11:44:42.988499 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6693 11:44:42.991627 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6694 11:44:42.994772 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6695 11:44:42.994882
6696 11:44:42.994978
6697 11:44:42.995074 ==
6698 11:44:42.997801 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 11:44:43.001623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 11:44:43.004732 ==
6701 11:44:43.004854
6702 11:44:43.004964
6703 11:44:43.005077 TX Vref Scan disable
6704 11:44:43.007729 == TX Byte 0 ==
6705 11:44:43.011320 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6706 11:44:43.014246 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6707 11:44:43.017845 == TX Byte 1 ==
6708 11:44:43.021266 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6709 11:44:43.024312 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6710 11:44:43.024427 ==
6711 11:44:43.027821 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 11:44:43.034042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 11:44:43.034129 ==
6714 11:44:43.034198
6715 11:44:43.034261
6716 11:44:43.034321 TX Vref Scan disable
6717 11:44:43.037609 == TX Byte 0 ==
6718 11:44:43.040894 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6719 11:44:43.043986 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6720 11:44:43.047212 == TX Byte 1 ==
6721 11:44:43.050473 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6722 11:44:43.054239 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6723 11:44:43.054335
6724 11:44:43.057259 [DATLAT]
6725 11:44:43.057355 Freq=400, CH1 RK0
6726 11:44:43.057432
6727 11:44:43.060482 DATLAT Default: 0xf
6728 11:44:43.060579 0, 0xFFFF, sum = 0
6729 11:44:43.064056 1, 0xFFFF, sum = 0
6730 11:44:43.064139 2, 0xFFFF, sum = 0
6731 11:44:43.067182 3, 0xFFFF, sum = 0
6732 11:44:43.067265 4, 0xFFFF, sum = 0
6733 11:44:43.070420 5, 0xFFFF, sum = 0
6734 11:44:43.070561 6, 0xFFFF, sum = 0
6735 11:44:43.074167 7, 0xFFFF, sum = 0
6736 11:44:43.077345 8, 0xFFFF, sum = 0
6737 11:44:43.077476 9, 0xFFFF, sum = 0
6738 11:44:43.080537 10, 0xFFFF, sum = 0
6739 11:44:43.080674 11, 0xFFFF, sum = 0
6740 11:44:43.083522 12, 0xFFFF, sum = 0
6741 11:44:43.083603 13, 0x0, sum = 1
6742 11:44:43.087108 14, 0x0, sum = 2
6743 11:44:43.087231 15, 0x0, sum = 3
6744 11:44:43.090198 16, 0x0, sum = 4
6745 11:44:43.090280 best_step = 14
6746 11:44:43.090361
6747 11:44:43.090443 ==
6748 11:44:43.093898 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 11:44:43.097027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 11:44:43.097129 ==
6751 11:44:43.100167 RX Vref Scan: 1
6752 11:44:43.100270
6753 11:44:43.103431 RX Vref 0 -> 0, step: 1
6754 11:44:43.103522
6755 11:44:43.106493 RX Delay -343 -> 252, step: 8
6756 11:44:43.106607
6757 11:44:43.109717 Set Vref, RX VrefLevel [Byte0]: 53
6758 11:44:43.113341 [Byte1]: 49
6759 11:44:43.113514
6760 11:44:43.116399 Final RX Vref Byte 0 = 53 to rank0
6761 11:44:43.119952 Final RX Vref Byte 1 = 49 to rank0
6762 11:44:43.123046 Final RX Vref Byte 0 = 53 to rank1
6763 11:44:43.126561 Final RX Vref Byte 1 = 49 to rank1==
6764 11:44:43.129559 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 11:44:43.132649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 11:44:43.132767 ==
6767 11:44:43.136265 DQS Delay:
6768 11:44:43.136388 DQS0 = 44, DQS1 = 56
6769 11:44:43.139405 DQM Delay:
6770 11:44:43.139512 DQM0 = 10, DQM1 = 13
6771 11:44:43.143035 DQ Delay:
6772 11:44:43.143146 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6773 11:44:43.146138 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6774 11:44:43.149382 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6775 11:44:43.152578 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6776 11:44:43.152694
6777 11:44:43.152791
6778 11:44:43.162588 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6779 11:44:43.165832 CH1 RK0: MR19=C0C, MR18=6A90
6780 11:44:43.172165 CH1_RK0: MR19=0xC0C, MR18=0x6A90, DQSOSC=391, MR23=63, INC=386, DEC=257
6781 11:44:43.172280 ==
6782 11:44:43.175479 Dram Type= 6, Freq= 0, CH_1, rank 1
6783 11:44:43.179150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 11:44:43.179260 ==
6785 11:44:43.182255 [Gating] SW mode calibration
6786 11:44:43.188488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6787 11:44:43.195262 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6788 11:44:43.199049 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6789 11:44:43.202105 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6790 11:44:43.208423 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 11:44:43.212049 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6792 11:44:43.215392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 11:44:43.218606 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 11:44:43.225386 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 11:44:43.228202 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 11:44:43.231757 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 11:44:43.234729 Total UI for P1: 0, mck2ui 16
6798 11:44:43.238375 best dqsien dly found for B0: ( 0, 14, 24)
6799 11:44:43.241360 Total UI for P1: 0, mck2ui 16
6800 11:44:43.244939 best dqsien dly found for B1: ( 0, 14, 24)
6801 11:44:43.251735 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6802 11:44:43.254964 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6803 11:44:43.255042
6804 11:44:43.258197 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6805 11:44:43.261323 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6806 11:44:43.264475 [Gating] SW calibration Done
6807 11:44:43.264564 ==
6808 11:44:43.267540 Dram Type= 6, Freq= 0, CH_1, rank 1
6809 11:44:43.271243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 11:44:43.271330 ==
6811 11:44:43.274275 RX Vref Scan: 0
6812 11:44:43.274361
6813 11:44:43.274447 RX Vref 0 -> 0, step: 1
6814 11:44:43.274528
6815 11:44:43.277511 RX Delay -410 -> 252, step: 16
6816 11:44:43.284528 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6817 11:44:43.287631 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6818 11:44:43.290688 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6819 11:44:43.293805 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6820 11:44:43.300791 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6821 11:44:43.303986 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6822 11:44:43.307235 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6823 11:44:43.310371 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6824 11:44:43.317238 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6825 11:44:43.320448 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6826 11:44:43.323626 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6827 11:44:43.329862 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6828 11:44:43.333375 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6829 11:44:43.336919 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6830 11:44:43.339794 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6831 11:44:43.346284 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6832 11:44:43.346391 ==
6833 11:44:43.349834 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 11:44:43.353355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 11:44:43.353442 ==
6836 11:44:43.353528 DQS Delay:
6837 11:44:43.356398 DQS0 = 43, DQS1 = 51
6838 11:44:43.356483 DQM Delay:
6839 11:44:43.359490 DQM0 = 11, DQM1 = 14
6840 11:44:43.359575 DQ Delay:
6841 11:44:43.362771 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6842 11:44:43.366519 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6843 11:44:43.369545 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6844 11:44:43.372543 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6845 11:44:43.372671
6846 11:44:43.372776
6847 11:44:43.372869 ==
6848 11:44:43.375708 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 11:44:43.379449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 11:44:43.379562 ==
6851 11:44:43.382595
6852 11:44:43.382673
6853 11:44:43.382751 TX Vref Scan disable
6854 11:44:43.385741 == TX Byte 0 ==
6855 11:44:43.388851 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6856 11:44:43.392659 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6857 11:44:43.395673 == TX Byte 1 ==
6858 11:44:43.399237 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6859 11:44:43.402404 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6860 11:44:43.402482 ==
6861 11:44:43.405456 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 11:44:43.408614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 11:44:43.412370 ==
6864 11:44:43.412447
6865 11:44:43.412533
6866 11:44:43.412598 TX Vref Scan disable
6867 11:44:43.415459 == TX Byte 0 ==
6868 11:44:43.419115 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6869 11:44:43.422177 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6870 11:44:43.425461 == TX Byte 1 ==
6871 11:44:43.428629 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6872 11:44:43.432443 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6873 11:44:43.432520
6874 11:44:43.435509 [DATLAT]
6875 11:44:43.435626 Freq=400, CH1 RK1
6876 11:44:43.435722
6877 11:44:43.438549 DATLAT Default: 0xe
6878 11:44:43.438627 0, 0xFFFF, sum = 0
6879 11:44:43.442097 1, 0xFFFF, sum = 0
6880 11:44:43.442175 2, 0xFFFF, sum = 0
6881 11:44:43.445032 3, 0xFFFF, sum = 0
6882 11:44:43.445169 4, 0xFFFF, sum = 0
6883 11:44:43.448645 5, 0xFFFF, sum = 0
6884 11:44:43.448731 6, 0xFFFF, sum = 0
6885 11:44:43.451984 7, 0xFFFF, sum = 0
6886 11:44:43.452123 8, 0xFFFF, sum = 0
6887 11:44:43.454967 9, 0xFFFF, sum = 0
6888 11:44:43.455054 10, 0xFFFF, sum = 0
6889 11:44:43.458451 11, 0xFFFF, sum = 0
6890 11:44:43.462079 12, 0xFFFF, sum = 0
6891 11:44:43.462173 13, 0x0, sum = 1
6892 11:44:43.462245 14, 0x0, sum = 2
6893 11:44:43.465109 15, 0x0, sum = 3
6894 11:44:43.465204 16, 0x0, sum = 4
6895 11:44:43.468204 best_step = 14
6896 11:44:43.468283
6897 11:44:43.468370 ==
6898 11:44:43.471356 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 11:44:43.475076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 11:44:43.475163 ==
6901 11:44:43.478212 RX Vref Scan: 0
6902 11:44:43.478320
6903 11:44:43.478388 RX Vref 0 -> 0, step: 1
6904 11:44:43.481208
6905 11:44:43.481286 RX Delay -343 -> 252, step: 8
6906 11:44:43.489566 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6907 11:44:43.493380 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6908 11:44:43.496485 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6909 11:44:43.502819 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6910 11:44:43.506499 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6911 11:44:43.509601 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6912 11:44:43.512805 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6913 11:44:43.519673 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6914 11:44:43.522734 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6915 11:44:43.525896 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6916 11:44:43.529004 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6917 11:44:43.536001 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6918 11:44:43.539155 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6919 11:44:43.542329 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6920 11:44:43.548876 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6921 11:44:43.551977 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6922 11:44:43.552076 ==
6923 11:44:43.555726 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 11:44:43.558647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 11:44:43.558722 ==
6926 11:44:43.562091 DQS Delay:
6927 11:44:43.562168 DQS0 = 48, DQS1 = 56
6928 11:44:43.562233 DQM Delay:
6929 11:44:43.565605 DQM0 = 11, DQM1 = 14
6930 11:44:43.565692 DQ Delay:
6931 11:44:43.568648 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6932 11:44:43.571459 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6933 11:44:43.575065 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6934 11:44:43.578059 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6935 11:44:43.578136
6936 11:44:43.578201
6937 11:44:43.588174 [DQSOSCAuto] RK1, (LSB)MR18= 0x6fa7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6938 11:44:43.591255 CH1 RK1: MR19=C0C, MR18=6FA7
6939 11:44:43.595078 CH1_RK1: MR19=0xC0C, MR18=0x6FA7, DQSOSC=389, MR23=63, INC=390, DEC=260
6940 11:44:43.598242 [RxdqsGatingPostProcess] freq 400
6941 11:44:43.604589 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6942 11:44:43.608133 best DQS0 dly(2T, 0.5T) = (0, 10)
6943 11:44:43.611164 best DQS1 dly(2T, 0.5T) = (0, 10)
6944 11:44:43.614362 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6945 11:44:43.618120 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6946 11:44:43.621246 best DQS0 dly(2T, 0.5T) = (0, 10)
6947 11:44:43.624477 best DQS1 dly(2T, 0.5T) = (0, 10)
6948 11:44:43.628045 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6949 11:44:43.631195 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6950 11:44:43.634459 Pre-setting of DQS Precalculation
6951 11:44:43.637534 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6952 11:44:43.643921 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6953 11:44:43.654285 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6954 11:44:43.654377
6955 11:44:43.654444
6956 11:44:43.654521 [Calibration Summary] 800 Mbps
6957 11:44:43.657419 CH 0, Rank 0
6958 11:44:43.657493 SW Impedance : PASS
6959 11:44:43.660698 DUTY Scan : NO K
6960 11:44:43.663736 ZQ Calibration : PASS
6961 11:44:43.663822 Jitter Meter : NO K
6962 11:44:43.666904 CBT Training : PASS
6963 11:44:43.670272 Write leveling : PASS
6964 11:44:43.670362 RX DQS gating : PASS
6965 11:44:43.673624 RX DQ/DQS(RDDQC) : PASS
6966 11:44:43.677163 TX DQ/DQS : PASS
6967 11:44:43.677272 RX DATLAT : PASS
6968 11:44:43.680236 RX DQ/DQS(Engine): PASS
6969 11:44:43.683798 TX OE : NO K
6970 11:44:43.683911 All Pass.
6971 11:44:43.684011
6972 11:44:43.684091 CH 0, Rank 1
6973 11:44:43.687065 SW Impedance : PASS
6974 11:44:43.690123 DUTY Scan : NO K
6975 11:44:43.690207 ZQ Calibration : PASS
6976 11:44:43.693746 Jitter Meter : NO K
6977 11:44:43.696852 CBT Training : PASS
6978 11:44:43.696935 Write leveling : NO K
6979 11:44:43.699965 RX DQS gating : PASS
6980 11:44:43.703143 RX DQ/DQS(RDDQC) : PASS
6981 11:44:43.703226 TX DQ/DQS : PASS
6982 11:44:43.706763 RX DATLAT : PASS
6983 11:44:43.709863 RX DQ/DQS(Engine): PASS
6984 11:44:43.709946 TX OE : NO K
6985 11:44:43.713654 All Pass.
6986 11:44:43.713737
6987 11:44:43.713803 CH 1, Rank 0
6988 11:44:43.716767 SW Impedance : PASS
6989 11:44:43.716850 DUTY Scan : NO K
6990 11:44:43.719887 ZQ Calibration : PASS
6991 11:44:43.722936 Jitter Meter : NO K
6992 11:44:43.723051 CBT Training : PASS
6993 11:44:43.726153 Write leveling : PASS
6994 11:44:43.729858 RX DQS gating : PASS
6995 11:44:43.729975 RX DQ/DQS(RDDQC) : PASS
6996 11:44:43.733110 TX DQ/DQS : PASS
6997 11:44:43.733238 RX DATLAT : PASS
6998 11:44:43.736219 RX DQ/DQS(Engine): PASS
6999 11:44:43.739405 TX OE : NO K
7000 11:44:43.739493 All Pass.
7001 11:44:43.739565
7002 11:44:43.742606 CH 1, Rank 1
7003 11:44:43.742680 SW Impedance : PASS
7004 11:44:43.745835 DUTY Scan : NO K
7005 11:44:43.745910 ZQ Calibration : PASS
7006 11:44:43.749593 Jitter Meter : NO K
7007 11:44:43.752735 CBT Training : PASS
7008 11:44:43.752855 Write leveling : NO K
7009 11:44:43.755941 RX DQS gating : PASS
7010 11:44:43.758938 RX DQ/DQS(RDDQC) : PASS
7011 11:44:43.759051 TX DQ/DQS : PASS
7012 11:44:43.762750 RX DATLAT : PASS
7013 11:44:43.765897 RX DQ/DQS(Engine): PASS
7014 11:44:43.766014 TX OE : NO K
7015 11:44:43.769015 All Pass.
7016 11:44:43.769094
7017 11:44:43.769163 DramC Write-DBI off
7018 11:44:43.772159 PER_BANK_REFRESH: Hybrid Mode
7019 11:44:43.775831 TX_TRACKING: ON
7020 11:44:43.782391 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7021 11:44:43.785392 [FAST_K] Save calibration result to emmc
7022 11:44:43.788938 dramc_set_vcore_voltage set vcore to 725000
7023 11:44:43.791839 Read voltage for 1600, 0
7024 11:44:43.791947 Vio18 = 0
7025 11:44:43.795492 Vcore = 725000
7026 11:44:43.795605 Vdram = 0
7027 11:44:43.795702 Vddq = 0
7028 11:44:43.798456 Vmddr = 0
7029 11:44:43.802052 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7030 11:44:43.808404 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7031 11:44:43.811531 MEM_TYPE=3, freq_sel=13
7032 11:44:43.811642 sv_algorithm_assistance_LP4_3733
7033 11:44:43.818082 ============ PULL DRAM RESETB DOWN ============
7034 11:44:43.821696 ========== PULL DRAM RESETB DOWN end =========
7035 11:44:43.824848 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7036 11:44:43.827931 ===================================
7037 11:44:43.831688 LPDDR4 DRAM CONFIGURATION
7038 11:44:43.834834 ===================================
7039 11:44:43.837937 EX_ROW_EN[0] = 0x0
7040 11:44:43.838015 EX_ROW_EN[1] = 0x0
7041 11:44:43.841646 LP4Y_EN = 0x0
7042 11:44:43.841726 WORK_FSP = 0x1
7043 11:44:43.844827 WL = 0x5
7044 11:44:43.844956 RL = 0x5
7045 11:44:43.847871 BL = 0x2
7046 11:44:43.847991 RPST = 0x0
7047 11:44:43.851128 RD_PRE = 0x0
7048 11:44:43.854188 WR_PRE = 0x1
7049 11:44:43.854304 WR_PST = 0x1
7050 11:44:43.857907 DBI_WR = 0x0
7051 11:44:43.858014 DBI_RD = 0x0
7052 11:44:43.860962 OTF = 0x1
7053 11:44:43.864369 ===================================
7054 11:44:43.867513 ===================================
7055 11:44:43.867603 ANA top config
7056 11:44:43.870696 ===================================
7057 11:44:43.874452 DLL_ASYNC_EN = 0
7058 11:44:43.877398 ALL_SLAVE_EN = 0
7059 11:44:43.877475 NEW_RANK_MODE = 1
7060 11:44:43.881059 DLL_IDLE_MODE = 1
7061 11:44:43.884133 LP45_APHY_COMB_EN = 1
7062 11:44:43.887216 TX_ODT_DIS = 0
7063 11:44:43.890748 NEW_8X_MODE = 1
7064 11:44:43.893782 ===================================
7065 11:44:43.897606 ===================================
7066 11:44:43.897720 data_rate = 3200
7067 11:44:43.900054 CKR = 1
7068 11:44:43.903642 DQ_P2S_RATIO = 8
7069 11:44:43.907177 ===================================
7070 11:44:43.910341 CA_P2S_RATIO = 8
7071 11:44:43.913485 DQ_CA_OPEN = 0
7072 11:44:43.916479 DQ_SEMI_OPEN = 0
7073 11:44:43.920064 CA_SEMI_OPEN = 0
7074 11:44:43.920178 CA_FULL_RATE = 0
7075 11:44:43.923174 DQ_CKDIV4_EN = 0
7076 11:44:43.926803 CA_CKDIV4_EN = 0
7077 11:44:43.929970 CA_PREDIV_EN = 0
7078 11:44:43.933228 PH8_DLY = 12
7079 11:44:43.936357 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7080 11:44:43.936438 DQ_AAMCK_DIV = 4
7081 11:44:43.940051 CA_AAMCK_DIV = 4
7082 11:44:43.943254 CA_ADMCK_DIV = 4
7083 11:44:43.946454 DQ_TRACK_CA_EN = 0
7084 11:44:43.949623 CA_PICK = 1600
7085 11:44:43.952773 CA_MCKIO = 1600
7086 11:44:43.956617 MCKIO_SEMI = 0
7087 11:44:43.959675 PLL_FREQ = 3068
7088 11:44:43.959781 DQ_UI_PI_RATIO = 32
7089 11:44:43.962839 CA_UI_PI_RATIO = 0
7090 11:44:43.965833 ===================================
7091 11:44:43.969394 ===================================
7092 11:44:43.972447 memory_type:LPDDR4
7093 11:44:43.975679 GP_NUM : 10
7094 11:44:43.975800 SRAM_EN : 1
7095 11:44:43.979484 MD32_EN : 0
7096 11:44:43.982526 ===================================
7097 11:44:43.985538 [ANA_INIT] >>>>>>>>>>>>>>
7098 11:44:43.985657 <<<<<< [CONFIGURE PHASE]: ANA_TX
7099 11:44:43.992435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7100 11:44:43.995496 ===================================
7101 11:44:43.995609 data_rate = 3200,PCW = 0X7600
7102 11:44:43.998993 ===================================
7103 11:44:44.001957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7104 11:44:44.008629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7105 11:44:44.015226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7106 11:44:44.018350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7107 11:44:44.022080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7108 11:44:44.024962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7109 11:44:44.028612 [ANA_INIT] flow start
7110 11:44:44.028695 [ANA_INIT] PLL >>>>>>>>
7111 11:44:44.031652 [ANA_INIT] PLL <<<<<<<<
7112 11:44:44.034861 [ANA_INIT] MIDPI >>>>>>>>
7113 11:44:44.038574 [ANA_INIT] MIDPI <<<<<<<<
7114 11:44:44.038681 [ANA_INIT] DLL >>>>>>>>
7115 11:44:44.041572 [ANA_INIT] DLL <<<<<<<<
7116 11:44:44.044732 [ANA_INIT] flow end
7117 11:44:44.047952 ============ LP4 DIFF to SE enter ============
7118 11:44:44.051556 ============ LP4 DIFF to SE exit ============
7119 11:44:44.054852 [ANA_INIT] <<<<<<<<<<<<<
7120 11:44:44.057977 [Flow] Enable top DCM control >>>>>
7121 11:44:44.061000 [Flow] Enable top DCM control <<<<<
7122 11:44:44.064727 Enable DLL master slave shuffle
7123 11:44:44.067916 ==============================================================
7124 11:44:44.070915 Gating Mode config
7125 11:44:44.077595 ==============================================================
7126 11:44:44.077708 Config description:
7127 11:44:44.087691 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7128 11:44:44.093814 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7129 11:44:44.100588 SELPH_MODE 0: By rank 1: By Phase
7130 11:44:44.104256 ==============================================================
7131 11:44:44.107370 GAT_TRACK_EN = 1
7132 11:44:44.110422 RX_GATING_MODE = 2
7133 11:44:44.114075 RX_GATING_TRACK_MODE = 2
7134 11:44:44.117082 SELPH_MODE = 1
7135 11:44:44.120657 PICG_EARLY_EN = 1
7136 11:44:44.123729 VALID_LAT_VALUE = 1
7137 11:44:44.130469 ==============================================================
7138 11:44:44.133429 Enter into Gating configuration >>>>
7139 11:44:44.137000 Exit from Gating configuration <<<<
7140 11:44:44.137084 Enter into DVFS_PRE_config >>>>>
7141 11:44:44.150436 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7142 11:44:44.153535 Exit from DVFS_PRE_config <<<<<
7143 11:44:44.156759 Enter into PICG configuration >>>>
7144 11:44:44.159956 Exit from PICG configuration <<<<
7145 11:44:44.163009 [RX_INPUT] configuration >>>>>
7146 11:44:44.163097 [RX_INPUT] configuration <<<<<
7147 11:44:44.169829 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7148 11:44:44.176662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7149 11:44:44.179659 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7150 11:44:44.186479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7151 11:44:44.192760 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7152 11:44:44.199662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7153 11:44:44.202874 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7154 11:44:44.205990 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7155 11:44:44.212882 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7156 11:44:44.215962 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7157 11:44:44.219005 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7158 11:44:44.225739 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7159 11:44:44.228708 ===================================
7160 11:44:44.228794 LPDDR4 DRAM CONFIGURATION
7161 11:44:44.232501 ===================================
7162 11:44:44.235629 EX_ROW_EN[0] = 0x0
7163 11:44:44.238504 EX_ROW_EN[1] = 0x0
7164 11:44:44.238589 LP4Y_EN = 0x0
7165 11:44:44.242162 WORK_FSP = 0x1
7166 11:44:44.242246 WL = 0x5
7167 11:44:44.245360 RL = 0x5
7168 11:44:44.245445 BL = 0x2
7169 11:44:44.248519 RPST = 0x0
7170 11:44:44.248602 RD_PRE = 0x0
7171 11:44:44.251740 WR_PRE = 0x1
7172 11:44:44.251824 WR_PST = 0x1
7173 11:44:44.255454 DBI_WR = 0x0
7174 11:44:44.255538 DBI_RD = 0x0
7175 11:44:44.258630 OTF = 0x1
7176 11:44:44.261778 ===================================
7177 11:44:44.265578 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7178 11:44:44.268631 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7179 11:44:44.275112 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 11:44:44.278369 ===================================
7181 11:44:44.278474 LPDDR4 DRAM CONFIGURATION
7182 11:44:44.281394 ===================================
7183 11:44:44.284988 EX_ROW_EN[0] = 0x10
7184 11:44:44.288122 EX_ROW_EN[1] = 0x0
7185 11:44:44.288207 LP4Y_EN = 0x0
7186 11:44:44.291279 WORK_FSP = 0x1
7187 11:44:44.291363 WL = 0x5
7188 11:44:44.294957 RL = 0x5
7189 11:44:44.295041 BL = 0x2
7190 11:44:44.298051 RPST = 0x0
7191 11:44:44.298136 RD_PRE = 0x0
7192 11:44:44.301679 WR_PRE = 0x1
7193 11:44:44.301766 WR_PST = 0x1
7194 11:44:44.304873 DBI_WR = 0x0
7195 11:44:44.304964 DBI_RD = 0x0
7196 11:44:44.308038 OTF = 0x1
7197 11:44:44.311240 ===================================
7198 11:44:44.317468 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7199 11:44:44.317555 ==
7200 11:44:44.321031 Dram Type= 6, Freq= 0, CH_0, rank 0
7201 11:44:44.324167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7202 11:44:44.324253 ==
7203 11:44:44.327808 [Duty_Offset_Calibration]
7204 11:44:44.327891 B0:2 B1:0 CA:4
7205 11:44:44.327989
7206 11:44:44.330857 [DutyScan_Calibration_Flow] k_type=0
7207 11:44:44.341150
7208 11:44:44.341243 ==CLK 0==
7209 11:44:44.344806 Final CLK duty delay cell = -4
7210 11:44:44.347797 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7211 11:44:44.351505 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7212 11:44:44.354637 [-4] AVG Duty = 4922%(X100)
7213 11:44:44.354737
7214 11:44:44.357664 CH0 CLK Duty spec in!! Max-Min= 218%
7215 11:44:44.361419 [DutyScan_Calibration_Flow] ====Done====
7216 11:44:44.361521
7217 11:44:44.364499 [DutyScan_Calibration_Flow] k_type=1
7218 11:44:44.381442
7219 11:44:44.381565 ==DQS 0 ==
7220 11:44:44.385079 Final DQS duty delay cell = 0
7221 11:44:44.388183 [0] MAX Duty = 5249%(X100), DQS PI = 38
7222 11:44:44.391379 [0] MIN Duty = 5093%(X100), DQS PI = 12
7223 11:44:44.394991 [0] AVG Duty = 5171%(X100)
7224 11:44:44.395089
7225 11:44:44.395156 ==DQS 1 ==
7226 11:44:44.398110 Final DQS duty delay cell = 0
7227 11:44:44.401171 [0] MAX Duty = 5187%(X100), DQS PI = 0
7228 11:44:44.404673 [0] MIN Duty = 4969%(X100), DQS PI = 10
7229 11:44:44.407699 [0] AVG Duty = 5078%(X100)
7230 11:44:44.407774
7231 11:44:44.410925 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7232 11:44:44.411049
7233 11:44:44.414651 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7234 11:44:44.417877 [DutyScan_Calibration_Flow] ====Done====
7235 11:44:44.417990
7236 11:44:44.421036 [DutyScan_Calibration_Flow] k_type=3
7237 11:44:44.438662
7238 11:44:44.438754 ==DQM 0 ==
7239 11:44:44.441662 Final DQM duty delay cell = 0
7240 11:44:44.445228 [0] MAX Duty = 5124%(X100), DQS PI = 20
7241 11:44:44.448434 [0] MIN Duty = 4875%(X100), DQS PI = 56
7242 11:44:44.451873 [0] AVG Duty = 4999%(X100)
7243 11:44:44.451982
7244 11:44:44.452082 ==DQM 1 ==
7245 11:44:44.454909 Final DQM duty delay cell = 0
7246 11:44:44.458204 [0] MAX Duty = 4969%(X100), DQS PI = 0
7247 11:44:44.461864 [0] MIN Duty = 4844%(X100), DQS PI = 16
7248 11:44:44.465054 [0] AVG Duty = 4906%(X100)
7249 11:44:44.465138
7250 11:44:44.468216 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7251 11:44:44.468302
7252 11:44:44.471417 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7253 11:44:44.475052 [DutyScan_Calibration_Flow] ====Done====
7254 11:44:44.475135
7255 11:44:44.478321 [DutyScan_Calibration_Flow] k_type=2
7256 11:44:44.495743
7257 11:44:44.495832 ==DQ 0 ==
7258 11:44:44.499369 Final DQ duty delay cell = 0
7259 11:44:44.502492 [0] MAX Duty = 5124%(X100), DQS PI = 20
7260 11:44:44.505496 [0] MIN Duty = 4938%(X100), DQS PI = 12
7261 11:44:44.505580 [0] AVG Duty = 5031%(X100)
7262 11:44:44.509127
7263 11:44:44.509239 ==DQ 1 ==
7264 11:44:44.511936 Final DQ duty delay cell = 0
7265 11:44:44.515802 [0] MAX Duty = 5187%(X100), DQS PI = 2
7266 11:44:44.518799 [0] MIN Duty = 4938%(X100), DQS PI = 14
7267 11:44:44.518914 [0] AVG Duty = 5062%(X100)
7268 11:44:44.521955
7269 11:44:44.525123 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7270 11:44:44.525225
7271 11:44:44.528385 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7272 11:44:44.532252 [DutyScan_Calibration_Flow] ====Done====
7273 11:44:44.532336 ==
7274 11:44:44.534989 Dram Type= 6, Freq= 0, CH_1, rank 0
7275 11:44:44.538704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7276 11:44:44.538789 ==
7277 11:44:44.542146 [Duty_Offset_Calibration]
7278 11:44:44.542229 B0:0 B1:-1 CA:3
7279 11:44:44.542296
7280 11:44:44.545204 [DutyScan_Calibration_Flow] k_type=0
7281 11:44:44.555004
7282 11:44:44.555092 ==CLK 0==
7283 11:44:44.558655 Final CLK duty delay cell = -4
7284 11:44:44.561624 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7285 11:44:44.565338 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7286 11:44:44.568487 [-4] AVG Duty = 4937%(X100)
7287 11:44:44.568612
7288 11:44:44.571744 CH1 CLK Duty spec in!! Max-Min= 187%
7289 11:44:44.574939 [DutyScan_Calibration_Flow] ====Done====
7290 11:44:44.575056
7291 11:44:44.577999 [DutyScan_Calibration_Flow] k_type=1
7292 11:44:44.594283
7293 11:44:44.594443 ==DQS 0 ==
7294 11:44:44.597915 Final DQS duty delay cell = 0
7295 11:44:44.601039 [0] MAX Duty = 5218%(X100), DQS PI = 28
7296 11:44:44.604186 [0] MIN Duty = 4907%(X100), DQS PI = 40
7297 11:44:44.607961 [0] AVG Duty = 5062%(X100)
7298 11:44:44.608084
7299 11:44:44.608169 ==DQS 1 ==
7300 11:44:44.611121 Final DQS duty delay cell = -4
7301 11:44:44.614182 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7302 11:44:44.617847 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7303 11:44:44.621100 [-4] AVG Duty = 4906%(X100)
7304 11:44:44.621193
7305 11:44:44.624374 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7306 11:44:44.624461
7307 11:44:44.627566 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7308 11:44:44.630851 [DutyScan_Calibration_Flow] ====Done====
7309 11:44:44.630966
7310 11:44:44.634011 [DutyScan_Calibration_Flow] k_type=3
7311 11:44:44.651523
7312 11:44:44.651621 ==DQM 0 ==
7313 11:44:44.655160 Final DQM duty delay cell = 0
7314 11:44:44.658635 [0] MAX Duty = 5031%(X100), DQS PI = 28
7315 11:44:44.661427 [0] MIN Duty = 4782%(X100), DQS PI = 40
7316 11:44:44.665052 [0] AVG Duty = 4906%(X100)
7317 11:44:44.665136
7318 11:44:44.665201 ==DQM 1 ==
7319 11:44:44.667988 Final DQM duty delay cell = 0
7320 11:44:44.671535 [0] MAX Duty = 5000%(X100), DQS PI = 32
7321 11:44:44.674570 [0] MIN Duty = 4813%(X100), DQS PI = 0
7322 11:44:44.677800 [0] AVG Duty = 4906%(X100)
7323 11:44:44.677880
7324 11:44:44.681557 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7325 11:44:44.681660
7326 11:44:44.684857 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7327 11:44:44.687981 [DutyScan_Calibration_Flow] ====Done====
7328 11:44:44.688080
7329 11:44:44.691191 [DutyScan_Calibration_Flow] k_type=2
7330 11:44:44.707980
7331 11:44:44.708106 ==DQ 0 ==
7332 11:44:44.711056 Final DQ duty delay cell = -4
7333 11:44:44.714143 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7334 11:44:44.717319 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7335 11:44:44.720889 [-4] AVG Duty = 4891%(X100)
7336 11:44:44.720962
7337 11:44:44.721028 ==DQ 1 ==
7338 11:44:44.724059 Final DQ duty delay cell = 0
7339 11:44:44.727873 [0] MAX Duty = 5062%(X100), DQS PI = 30
7340 11:44:44.731021 [0] MIN Duty = 4875%(X100), DQS PI = 0
7341 11:44:44.734151 [0] AVG Duty = 4968%(X100)
7342 11:44:44.734226
7343 11:44:44.737397 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7344 11:44:44.737495
7345 11:44:44.740502 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7346 11:44:44.743623 [DutyScan_Calibration_Flow] ====Done====
7347 11:44:44.747435 nWR fixed to 30
7348 11:44:44.750291 [ModeRegInit_LP4] CH0 RK0
7349 11:44:44.750365 [ModeRegInit_LP4] CH0 RK1
7350 11:44:44.754087 [ModeRegInit_LP4] CH1 RK0
7351 11:44:44.757149 [ModeRegInit_LP4] CH1 RK1
7352 11:44:44.757247 match AC timing 5
7353 11:44:44.763679 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7354 11:44:44.766790 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7355 11:44:44.769895 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7356 11:44:44.777075 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7357 11:44:44.780011 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7358 11:44:44.783701 [MiockJmeterHQA]
7359 11:44:44.783827
7360 11:44:44.786890 [DramcMiockJmeter] u1RxGatingPI = 0
7361 11:44:44.787013 0 : 4252, 4027
7362 11:44:44.787117 4 : 4254, 4027
7363 11:44:44.790072 8 : 4258, 4030
7364 11:44:44.790196 12 : 4252, 4027
7365 11:44:44.793398 16 : 4252, 4027
7366 11:44:44.793489 20 : 4253, 4027
7367 11:44:44.796505 24 : 4363, 4137
7368 11:44:44.796591 28 : 4257, 4029
7369 11:44:44.796677 32 : 4250, 4026
7370 11:44:44.799718 36 : 4366, 4140
7371 11:44:44.799832 40 : 4366, 4139
7372 11:44:44.803204 44 : 4362, 4137
7373 11:44:44.803293 48 : 4250, 4027
7374 11:44:44.806379 52 : 4363, 4137
7375 11:44:44.806474 56 : 4253, 4026
7376 11:44:44.809513 60 : 4250, 4027
7377 11:44:44.809610 64 : 4253, 4029
7378 11:44:44.809698 68 : 4250, 4027
7379 11:44:44.812774 72 : 4250, 4027
7380 11:44:44.812868 76 : 4250, 4026
7381 11:44:44.816589 80 : 4250, 4027
7382 11:44:44.816680 84 : 4255, 4029
7383 11:44:44.819793 88 : 4363, 4139
7384 11:44:44.819918 92 : 4249, 4027
7385 11:44:44.822821 96 : 4253, 2851
7386 11:44:44.822909 100 : 4250, 0
7387 11:44:44.822998 104 : 4250, 0
7388 11:44:44.825823 108 : 4252, 0
7389 11:44:44.825912 112 : 4250, 0
7390 11:44:44.829584 116 : 4250, 0
7391 11:44:44.829700 120 : 4252, 0
7392 11:44:44.829823 124 : 4252, 0
7393 11:44:44.832634 128 : 4250, 0
7394 11:44:44.832766 132 : 4250, 0
7395 11:44:44.835926 136 : 4253, 0
7396 11:44:44.836071 140 : 4361, 0
7397 11:44:44.836180 144 : 4362, 0
7398 11:44:44.839050 148 : 4255, 0
7399 11:44:44.839139 152 : 4252, 0
7400 11:44:44.842718 156 : 4255, 0
7401 11:44:44.842816 160 : 4253, 0
7402 11:44:44.842922 164 : 4252, 0
7403 11:44:44.845979 168 : 4255, 0
7404 11:44:44.846072 172 : 4254, 0
7405 11:44:44.846159 176 : 4250, 0
7406 11:44:44.849103 180 : 4249, 0
7407 11:44:44.849210 184 : 4250, 0
7408 11:44:44.852360 188 : 4253, 0
7409 11:44:44.852452 192 : 4361, 0
7410 11:44:44.852544 196 : 4363, 0
7411 11:44:44.855935 200 : 4250, 0
7412 11:44:44.856066 204 : 4252, 0
7413 11:44:44.858996 208 : 4255, 0
7414 11:44:44.859108 212 : 4253, 0
7415 11:44:44.859197 216 : 4252, 0
7416 11:44:44.862209 220 : 4255, 622
7417 11:44:44.862291 224 : 4360, 4107
7418 11:44:44.865379 228 : 4253, 4027
7419 11:44:44.865467 232 : 4361, 4137
7420 11:44:44.869108 236 : 4363, 4140
7421 11:44:44.869196 240 : 4361, 4137
7422 11:44:44.871910 244 : 4249, 4027
7423 11:44:44.871987 248 : 4249, 4027
7424 11:44:44.875569 252 : 4250, 4026
7425 11:44:44.875671 256 : 4250, 4027
7426 11:44:44.878604 260 : 4360, 4138
7427 11:44:44.878690 264 : 4249, 4027
7428 11:44:44.881612 268 : 4250, 4026
7429 11:44:44.881698 272 : 4250, 4027
7430 11:44:44.881767 276 : 4250, 4027
7431 11:44:44.885378 280 : 4360, 4137
7432 11:44:44.885465 284 : 4250, 4026
7433 11:44:44.888748 288 : 4361, 4137
7434 11:44:44.888834 292 : 4250, 4027
7435 11:44:44.891808 296 : 4250, 4027
7436 11:44:44.891894 300 : 4250, 4026
7437 11:44:44.894899 304 : 4250, 4026
7438 11:44:44.894984 308 : 4255, 4029
7439 11:44:44.898760 312 : 4360, 4138
7440 11:44:44.898845 316 : 4249, 4027
7441 11:44:44.901471 320 : 4250, 4026
7442 11:44:44.901555 324 : 4255, 4029
7443 11:44:44.905196 328 : 4250, 4027
7444 11:44:44.905282 332 : 4362, 4108
7445 11:44:44.908082 336 : 4250, 1932
7446 11:44:44.908167
7447 11:44:44.908234 MIOCK jitter meter ch=0
7448 11:44:44.908296
7449 11:44:44.911831 1T = (336-100) = 236 dly cells
7450 11:44:44.918116 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7451 11:44:44.918203 ==
7452 11:44:44.921269 Dram Type= 6, Freq= 0, CH_0, rank 0
7453 11:44:44.925055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7454 11:44:44.925135 ==
7455 11:44:44.931263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7456 11:44:44.934445 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7457 11:44:44.937604 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7458 11:44:44.944663 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7459 11:44:44.954225 [CA 0] Center 43 (13~74) winsize 62
7460 11:44:44.957918 [CA 1] Center 42 (12~73) winsize 62
7461 11:44:44.961038 [CA 2] Center 37 (8~67) winsize 60
7462 11:44:44.964010 [CA 3] Center 37 (8~67) winsize 60
7463 11:44:44.967143 [CA 4] Center 36 (6~66) winsize 61
7464 11:44:44.970883 [CA 5] Center 35 (5~66) winsize 62
7465 11:44:44.970970
7466 11:44:44.974085 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7467 11:44:44.974161
7468 11:44:44.980742 [CATrainingPosCal] consider 1 rank data
7469 11:44:44.980857 u2DelayCellTimex100 = 275/100 ps
7470 11:44:44.987149 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7471 11:44:44.990242 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7472 11:44:44.993889 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7473 11:44:44.996895 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7474 11:44:45.000531 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7475 11:44:45.003696 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7476 11:44:45.003798
7477 11:44:45.006893 CA PerBit enable=1, Macro0, CA PI delay=35
7478 11:44:45.006978
7479 11:44:45.009908 [CBTSetCACLKResult] CA Dly = 35
7480 11:44:45.013692 CS Dly: 11 (0~42)
7481 11:44:45.016683 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7482 11:44:45.019828 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7483 11:44:45.019939 ==
7484 11:44:45.023540 Dram Type= 6, Freq= 0, CH_0, rank 1
7485 11:44:45.029841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 11:44:45.029927 ==
7487 11:44:45.032974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 11:44:45.039832 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 11:44:45.043176 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 11:44:45.049514 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 11:44:45.057697 [CA 0] Center 44 (14~75) winsize 62
7492 11:44:45.060899 [CA 1] Center 44 (14~74) winsize 61
7493 11:44:45.064589 [CA 2] Center 39 (10~69) winsize 60
7494 11:44:45.067629 [CA 3] Center 39 (10~68) winsize 59
7495 11:44:45.071175 [CA 4] Center 37 (7~67) winsize 61
7496 11:44:45.074348 [CA 5] Center 36 (6~66) winsize 61
7497 11:44:45.074434
7498 11:44:45.077501 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 11:44:45.077586
7500 11:44:45.083803 [CATrainingPosCal] consider 2 rank data
7501 11:44:45.083888 u2DelayCellTimex100 = 275/100 ps
7502 11:44:45.090494 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7503 11:44:45.094175 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7504 11:44:45.097091 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7505 11:44:45.100727 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7506 11:44:45.103692 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7507 11:44:45.107197 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7508 11:44:45.107277
7509 11:44:45.110416 CA PerBit enable=1, Macro0, CA PI delay=36
7510 11:44:45.110501
7511 11:44:45.113509 [CBTSetCACLKResult] CA Dly = 36
7512 11:44:45.117072 CS Dly: 11 (0~43)
7513 11:44:45.120013 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 11:44:45.123828 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 11:44:45.123936
7516 11:44:45.126780 ----->DramcWriteLeveling(PI) begin...
7517 11:44:45.129995 ==
7518 11:44:45.133265 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 11:44:45.136829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 11:44:45.136915 ==
7521 11:44:45.140001 Write leveling (Byte 0): 34 => 34
7522 11:44:45.143225 Write leveling (Byte 1): 27 => 27
7523 11:44:45.146457 DramcWriteLeveling(PI) end<-----
7524 11:44:45.146541
7525 11:44:45.146608 ==
7526 11:44:45.149645 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 11:44:45.153478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 11:44:45.153563 ==
7529 11:44:45.156636 [Gating] SW mode calibration
7530 11:44:45.162861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7531 11:44:45.169674 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7532 11:44:45.173287 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7533 11:44:45.176439 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7534 11:44:45.182979 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7535 11:44:45.186193 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7536 11:44:45.189303 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7537 11:44:45.195986 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7538 11:44:45.199690 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7539 11:44:45.202707 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7540 11:44:45.208973 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7541 11:44:45.212417 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7542 11:44:45.215483 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7543 11:44:45.222190 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7544 11:44:45.225829 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7545 11:44:45.228945 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7546 11:44:45.235243 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 11:44:45.238898 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 11:44:45.241867 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 11:44:45.248710 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 11:44:45.251819 1 6 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
7551 11:44:45.254942 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7552 11:44:45.261419 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7553 11:44:45.265182 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7554 11:44:45.268407 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7555 11:44:45.274631 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7556 11:44:45.278361 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7557 11:44:45.281409 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 11:44:45.287824 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7559 11:44:45.290982 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7560 11:44:45.294716 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7561 11:44:45.301326 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7562 11:44:45.304505 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7563 11:44:45.307578 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7564 11:44:45.314316 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 11:44:45.317378 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 11:44:45.320898 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 11:44:45.327488 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 11:44:45.331110 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 11:44:45.334270 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 11:44:45.340514 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 11:44:45.344149 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 11:44:45.347208 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 11:44:45.354063 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7574 11:44:45.357180 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7575 11:44:45.360343 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7576 11:44:45.366730 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7577 11:44:45.370010 Total UI for P1: 0, mck2ui 16
7578 11:44:45.373197 best dqsien dly found for B0: ( 1, 9, 8)
7579 11:44:45.377050 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7580 11:44:45.380110 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7581 11:44:45.386851 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 11:44:45.390038 Total UI for P1: 0, mck2ui 16
7583 11:44:45.393243 best dqsien dly found for B1: ( 1, 9, 22)
7584 11:44:45.396339 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7585 11:44:45.399440 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7586 11:44:45.399545
7587 11:44:45.403027 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7588 11:44:45.406224 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7589 11:44:45.409975 [Gating] SW calibration Done
7590 11:44:45.410079 ==
7591 11:44:45.413108 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 11:44:45.416158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 11:44:45.416266 ==
7594 11:44:45.419838 RX Vref Scan: 0
7595 11:44:45.419941
7596 11:44:45.422773 RX Vref 0 -> 0, step: 1
7597 11:44:45.422880
7598 11:44:45.422975 RX Delay 0 -> 252, step: 8
7599 11:44:45.429303 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7600 11:44:45.432878 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7601 11:44:45.435835 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7602 11:44:45.439402 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7603 11:44:45.442456 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7604 11:44:45.449113 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7605 11:44:45.452199 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7606 11:44:45.456115 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7607 11:44:45.459322 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7608 11:44:45.462554 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7609 11:44:45.468748 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7610 11:44:45.471934 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7611 11:44:45.475727 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7612 11:44:45.478802 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7613 11:44:45.485591 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7614 11:44:45.488749 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7615 11:44:45.488832 ==
7616 11:44:45.491874 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 11:44:45.495099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 11:44:45.495215 ==
7619 11:44:45.498179 DQS Delay:
7620 11:44:45.498293 DQS0 = 0, DQS1 = 0
7621 11:44:45.498388 DQM Delay:
7622 11:44:45.501921 DQM0 = 131, DQM1 = 127
7623 11:44:45.502023 DQ Delay:
7624 11:44:45.504974 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7625 11:44:45.508028 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7626 11:44:45.515016 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7627 11:44:45.518154 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7628 11:44:45.518283
7629 11:44:45.518393
7630 11:44:45.518494 ==
7631 11:44:45.521355 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 11:44:45.524582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 11:44:45.524701 ==
7634 11:44:45.524799
7635 11:44:45.524910
7636 11:44:45.528396 TX Vref Scan disable
7637 11:44:45.531213 == TX Byte 0 ==
7638 11:44:45.534877 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7639 11:44:45.537864 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7640 11:44:45.541312 == TX Byte 1 ==
7641 11:44:45.544220 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7642 11:44:45.547877 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7643 11:44:45.547998 ==
7644 11:44:45.551024 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 11:44:45.554102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 11:44:45.557844 ==
7647 11:44:45.570507
7648 11:44:45.573712 TX Vref early break, caculate TX vref
7649 11:44:45.577385 TX Vref=16, minBit 8, minWin=22, winSum=371
7650 11:44:45.580459 TX Vref=18, minBit 0, minWin=23, winSum=378
7651 11:44:45.583592 TX Vref=20, minBit 1, minWin=23, winSum=392
7652 11:44:45.587274 TX Vref=22, minBit 6, minWin=24, winSum=399
7653 11:44:45.590329 TX Vref=24, minBit 1, minWin=24, winSum=406
7654 11:44:45.597158 TX Vref=26, minBit 1, minWin=25, winSum=419
7655 11:44:45.599831 TX Vref=28, minBit 1, minWin=24, winSum=419
7656 11:44:45.603566 TX Vref=30, minBit 1, minWin=25, winSum=419
7657 11:44:45.606744 TX Vref=32, minBit 4, minWin=24, winSum=412
7658 11:44:45.609919 TX Vref=34, minBit 1, minWin=24, winSum=403
7659 11:44:45.616499 TX Vref=36, minBit 6, minWin=23, winSum=386
7660 11:44:45.619804 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 26
7661 11:44:45.619911
7662 11:44:45.622911 Final TX Range 0 Vref 26
7663 11:44:45.622986
7664 11:44:45.623058 ==
7665 11:44:45.626094 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 11:44:45.629883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 11:44:45.632957 ==
7668 11:44:45.633035
7669 11:44:45.633101
7670 11:44:45.633176 TX Vref Scan disable
7671 11:44:45.639609 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7672 11:44:45.639691 == TX Byte 0 ==
7673 11:44:45.643187 u2DelayCellOfst[0]=14 cells (4 PI)
7674 11:44:45.646729 u2DelayCellOfst[1]=17 cells (5 PI)
7675 11:44:45.649547 u2DelayCellOfst[2]=14 cells (4 PI)
7676 11:44:45.652953 u2DelayCellOfst[3]=14 cells (4 PI)
7677 11:44:45.656603 u2DelayCellOfst[4]=10 cells (3 PI)
7678 11:44:45.659653 u2DelayCellOfst[5]=0 cells (0 PI)
7679 11:44:45.662833 u2DelayCellOfst[6]=21 cells (6 PI)
7680 11:44:45.665888 u2DelayCellOfst[7]=17 cells (5 PI)
7681 11:44:45.669623 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7682 11:44:45.672876 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7683 11:44:45.675949 == TX Byte 1 ==
7684 11:44:45.679312 u2DelayCellOfst[8]=0 cells (0 PI)
7685 11:44:45.682384 u2DelayCellOfst[9]=0 cells (0 PI)
7686 11:44:45.686100 u2DelayCellOfst[10]=3 cells (1 PI)
7687 11:44:45.689348 u2DelayCellOfst[11]=0 cells (0 PI)
7688 11:44:45.692367 u2DelayCellOfst[12]=10 cells (3 PI)
7689 11:44:45.695886 u2DelayCellOfst[13]=10 cells (3 PI)
7690 11:44:45.699052 u2DelayCellOfst[14]=14 cells (4 PI)
7691 11:44:45.702052 u2DelayCellOfst[15]=10 cells (3 PI)
7692 11:44:45.705740 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7693 11:44:45.708854 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7694 11:44:45.711983 DramC Write-DBI on
7695 11:44:45.712079 ==
7696 11:44:45.715644 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 11:44:45.718750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 11:44:45.718837 ==
7699 11:44:45.718906
7700 11:44:45.718968
7701 11:44:45.721919 TX Vref Scan disable
7702 11:44:45.725060 == TX Byte 0 ==
7703 11:44:45.728735 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7704 11:44:45.728819 == TX Byte 1 ==
7705 11:44:45.735080 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7706 11:44:45.735162 DramC Write-DBI off
7707 11:44:45.735231
7708 11:44:45.735294 [DATLAT]
7709 11:44:45.738173 Freq=1600, CH0 RK0
7710 11:44:45.738259
7711 11:44:45.741678 DATLAT Default: 0xf
7712 11:44:45.741754 0, 0xFFFF, sum = 0
7713 11:44:45.744800 1, 0xFFFF, sum = 0
7714 11:44:45.744875 2, 0xFFFF, sum = 0
7715 11:44:45.747946 3, 0xFFFF, sum = 0
7716 11:44:45.748066 4, 0xFFFF, sum = 0
7717 11:44:45.751430 5, 0xFFFF, sum = 0
7718 11:44:45.751539 6, 0xFFFF, sum = 0
7719 11:44:45.755026 7, 0xFFFF, sum = 0
7720 11:44:45.755140 8, 0xFFFF, sum = 0
7721 11:44:45.757999 9, 0xFFFF, sum = 0
7722 11:44:45.758085 10, 0xFFFF, sum = 0
7723 11:44:45.761493 11, 0xFFFF, sum = 0
7724 11:44:45.764500 12, 0xFFFF, sum = 0
7725 11:44:45.764577 13, 0xFFFF, sum = 0
7726 11:44:45.768158 14, 0x0, sum = 1
7727 11:44:45.768287 15, 0x0, sum = 2
7728 11:44:45.768410 16, 0x0, sum = 3
7729 11:44:45.771338 17, 0x0, sum = 4
7730 11:44:45.771428 best_step = 15
7731 11:44:45.771505
7732 11:44:45.774446 ==
7733 11:44:45.774518 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 11:44:45.781476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 11:44:45.781569 ==
7736 11:44:45.781637 RX Vref Scan: 1
7737 11:44:45.781699
7738 11:44:45.784568 Set Vref Range= 24 -> 127
7739 11:44:45.784643
7740 11:44:45.787655 RX Vref 24 -> 127, step: 1
7741 11:44:45.787734
7742 11:44:45.790750 RX Delay 19 -> 252, step: 4
7743 11:44:45.790835
7744 11:44:45.794501 Set Vref, RX VrefLevel [Byte0]: 24
7745 11:44:45.797738 [Byte1]: 24
7746 11:44:45.797825
7747 11:44:45.800819 Set Vref, RX VrefLevel [Byte0]: 25
7748 11:44:45.803879 [Byte1]: 25
7749 11:44:45.803988
7750 11:44:45.807760 Set Vref, RX VrefLevel [Byte0]: 26
7751 11:44:45.810257 [Byte1]: 26
7752 11:44:45.814167
7753 11:44:45.814269 Set Vref, RX VrefLevel [Byte0]: 27
7754 11:44:45.817459 [Byte1]: 27
7755 11:44:45.821730
7756 11:44:45.821832 Set Vref, RX VrefLevel [Byte0]: 28
7757 11:44:45.825391 [Byte1]: 28
7758 11:44:45.829738
7759 11:44:45.829839 Set Vref, RX VrefLevel [Byte0]: 29
7760 11:44:45.832950 [Byte1]: 29
7761 11:44:45.836739
7762 11:44:45.836839 Set Vref, RX VrefLevel [Byte0]: 30
7763 11:44:45.840569 [Byte1]: 30
7764 11:44:45.844888
7765 11:44:45.844995 Set Vref, RX VrefLevel [Byte0]: 31
7766 11:44:45.847841 [Byte1]: 31
7767 11:44:45.852278
7768 11:44:45.852361 Set Vref, RX VrefLevel [Byte0]: 32
7769 11:44:45.855427 [Byte1]: 32
7770 11:44:45.859674
7771 11:44:45.859762 Set Vref, RX VrefLevel [Byte0]: 33
7772 11:44:45.863289 [Byte1]: 33
7773 11:44:45.867402
7774 11:44:45.867480 Set Vref, RX VrefLevel [Byte0]: 34
7775 11:44:45.870376 [Byte1]: 34
7776 11:44:45.874572
7777 11:44:45.874662 Set Vref, RX VrefLevel [Byte0]: 35
7778 11:44:45.878176 [Byte1]: 35
7779 11:44:45.882669
7780 11:44:45.882753 Set Vref, RX VrefLevel [Byte0]: 36
7781 11:44:45.885849 [Byte1]: 36
7782 11:44:45.890208
7783 11:44:45.890296 Set Vref, RX VrefLevel [Byte0]: 37
7784 11:44:45.893491 [Byte1]: 37
7785 11:44:45.897392
7786 11:44:45.897469 Set Vref, RX VrefLevel [Byte0]: 38
7787 11:44:45.901170 [Byte1]: 38
7788 11:44:45.905415
7789 11:44:45.905494 Set Vref, RX VrefLevel [Byte0]: 39
7790 11:44:45.908451 [Byte1]: 39
7791 11:44:45.912798
7792 11:44:45.912879 Set Vref, RX VrefLevel [Byte0]: 40
7793 11:44:45.915844 [Byte1]: 40
7794 11:44:45.920249
7795 11:44:45.920328 Set Vref, RX VrefLevel [Byte0]: 41
7796 11:44:45.923448 [Byte1]: 41
7797 11:44:45.927752
7798 11:44:45.927871 Set Vref, RX VrefLevel [Byte0]: 42
7799 11:44:45.930988 [Byte1]: 42
7800 11:44:45.935492
7801 11:44:45.935610 Set Vref, RX VrefLevel [Byte0]: 43
7802 11:44:45.938584 [Byte1]: 43
7803 11:44:45.943036
7804 11:44:45.943141 Set Vref, RX VrefLevel [Byte0]: 44
7805 11:44:45.946164 [Byte1]: 44
7806 11:44:45.950528
7807 11:44:45.950644 Set Vref, RX VrefLevel [Byte0]: 45
7808 11:44:45.953603 [Byte1]: 45
7809 11:44:45.958530
7810 11:44:45.958652 Set Vref, RX VrefLevel [Byte0]: 46
7811 11:44:45.961604 [Byte1]: 46
7812 11:44:45.965872
7813 11:44:45.965993 Set Vref, RX VrefLevel [Byte0]: 47
7814 11:44:45.968921 [Byte1]: 47
7815 11:44:45.973150
7816 11:44:45.973235 Set Vref, RX VrefLevel [Byte0]: 48
7817 11:44:45.976579 [Byte1]: 48
7818 11:44:45.980817
7819 11:44:45.980901 Set Vref, RX VrefLevel [Byte0]: 49
7820 11:44:45.983858 [Byte1]: 49
7821 11:44:45.988286
7822 11:44:45.988394 Set Vref, RX VrefLevel [Byte0]: 50
7823 11:44:45.991467 [Byte1]: 50
7824 11:44:45.995915
7825 11:44:45.996020 Set Vref, RX VrefLevel [Byte0]: 51
7826 11:44:45.999041 [Byte1]: 51
7827 11:44:46.003386
7828 11:44:46.006613 Set Vref, RX VrefLevel [Byte0]: 52
7829 11:44:46.010279 [Byte1]: 52
7830 11:44:46.010392
7831 11:44:46.013393 Set Vref, RX VrefLevel [Byte0]: 53
7832 11:44:46.016423 [Byte1]: 53
7833 11:44:46.016500
7834 11:44:46.020209 Set Vref, RX VrefLevel [Byte0]: 54
7835 11:44:46.023310 [Byte1]: 54
7836 11:44:46.023388
7837 11:44:46.026464 Set Vref, RX VrefLevel [Byte0]: 55
7838 11:44:46.029562 [Byte1]: 55
7839 11:44:46.033875
7840 11:44:46.033954 Set Vref, RX VrefLevel [Byte0]: 56
7841 11:44:46.037093 [Byte1]: 56
7842 11:44:46.041572
7843 11:44:46.041655 Set Vref, RX VrefLevel [Byte0]: 57
7844 11:44:46.044873 [Byte1]: 57
7845 11:44:46.049172
7846 11:44:46.049258 Set Vref, RX VrefLevel [Byte0]: 58
7847 11:44:46.052357 [Byte1]: 58
7848 11:44:46.056802
7849 11:44:46.056877 Set Vref, RX VrefLevel [Byte0]: 59
7850 11:44:46.059923 [Byte1]: 59
7851 11:44:46.064391
7852 11:44:46.064475 Set Vref, RX VrefLevel [Byte0]: 60
7853 11:44:46.067544 [Byte1]: 60
7854 11:44:46.071867
7855 11:44:46.071952 Set Vref, RX VrefLevel [Byte0]: 61
7856 11:44:46.074808 [Byte1]: 61
7857 11:44:46.079592
7858 11:44:46.079684 Set Vref, RX VrefLevel [Byte0]: 62
7859 11:44:46.082488 [Byte1]: 62
7860 11:44:46.086653
7861 11:44:46.086742 Set Vref, RX VrefLevel [Byte0]: 63
7862 11:44:46.090217 [Byte1]: 63
7863 11:44:46.094493
7864 11:44:46.094597 Set Vref, RX VrefLevel [Byte0]: 64
7865 11:44:46.097739 [Byte1]: 64
7866 11:44:46.102178
7867 11:44:46.102263 Set Vref, RX VrefLevel [Byte0]: 65
7868 11:44:46.105236 [Byte1]: 65
7869 11:44:46.109592
7870 11:44:46.109727 Set Vref, RX VrefLevel [Byte0]: 66
7871 11:44:46.113247 [Byte1]: 66
7872 11:44:46.117401
7873 11:44:46.117536 Set Vref, RX VrefLevel [Byte0]: 67
7874 11:44:46.120587 [Byte1]: 67
7875 11:44:46.124427
7876 11:44:46.124543 Set Vref, RX VrefLevel [Byte0]: 68
7877 11:44:46.128280 [Byte1]: 68
7878 11:44:46.132107
7879 11:44:46.132214 Set Vref, RX VrefLevel [Byte0]: 69
7880 11:44:46.135701 [Byte1]: 69
7881 11:44:46.140183
7882 11:44:46.140275 Set Vref, RX VrefLevel [Byte0]: 70
7883 11:44:46.143381 [Byte1]: 70
7884 11:44:46.147709
7885 11:44:46.147816 Set Vref, RX VrefLevel [Byte0]: 71
7886 11:44:46.150932 [Byte1]: 71
7887 11:44:46.155281
7888 11:44:46.155391 Set Vref, RX VrefLevel [Byte0]: 72
7889 11:44:46.158507 [Byte1]: 72
7890 11:44:46.162636
7891 11:44:46.162743 Set Vref, RX VrefLevel [Byte0]: 73
7892 11:44:46.165775 [Byte1]: 73
7893 11:44:46.170146
7894 11:44:46.170269 Set Vref, RX VrefLevel [Byte0]: 74
7895 11:44:46.173195 [Byte1]: 74
7896 11:44:46.177529
7897 11:44:46.177646 Set Vref, RX VrefLevel [Byte0]: 75
7898 11:44:46.181082 [Byte1]: 75
7899 11:44:46.185515
7900 11:44:46.185628 Final RX Vref Byte 0 = 55 to rank0
7901 11:44:46.188541 Final RX Vref Byte 1 = 62 to rank0
7902 11:44:46.192060 Final RX Vref Byte 0 = 55 to rank1
7903 11:44:46.195095 Final RX Vref Byte 1 = 62 to rank1==
7904 11:44:46.198564 Dram Type= 6, Freq= 0, CH_0, rank 0
7905 11:44:46.205331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7906 11:44:46.205455 ==
7907 11:44:46.205571 DQS Delay:
7908 11:44:46.208510 DQS0 = 0, DQS1 = 0
7909 11:44:46.208618 DQM Delay:
7910 11:44:46.208729 DQM0 = 128, DQM1 = 123
7911 11:44:46.211630 DQ Delay:
7912 11:44:46.215330 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7913 11:44:46.218378 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7914 11:44:46.221427 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7915 11:44:46.225060 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =128
7916 11:44:46.225153
7917 11:44:46.225224
7918 11:44:46.225300
7919 11:44:46.228258 [DramC_TX_OE_Calibration] TA2
7920 11:44:46.231480 Original DQ_B0 (3 6) =30, OEN = 27
7921 11:44:46.234631 Original DQ_B1 (3 6) =30, OEN = 27
7922 11:44:46.238447 24, 0x0, End_B0=24 End_B1=24
7923 11:44:46.241481 25, 0x0, End_B0=25 End_B1=25
7924 11:44:46.241600 26, 0x0, End_B0=26 End_B1=26
7925 11:44:46.244629 27, 0x0, End_B0=27 End_B1=27
7926 11:44:46.247776 28, 0x0, End_B0=28 End_B1=28
7927 11:44:46.251004 29, 0x0, End_B0=29 End_B1=29
7928 11:44:46.251090 30, 0x0, End_B0=30 End_B1=30
7929 11:44:46.254762 31, 0x4141, End_B0=30 End_B1=30
7930 11:44:46.258029 Byte0 end_step=30 best_step=27
7931 11:44:46.261032 Byte1 end_step=30 best_step=27
7932 11:44:46.264177 Byte0 TX OE(2T, 0.5T) = (3, 3)
7933 11:44:46.267809 Byte1 TX OE(2T, 0.5T) = (3, 3)
7934 11:44:46.267921
7935 11:44:46.268016
7936 11:44:46.274097 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7937 11:44:46.277210 CH0 RK0: MR19=303, MR18=1916
7938 11:44:46.284160 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
7939 11:44:46.284272
7940 11:44:46.287196 ----->DramcWriteLeveling(PI) begin...
7941 11:44:46.287342 ==
7942 11:44:46.290509 Dram Type= 6, Freq= 0, CH_0, rank 1
7943 11:44:46.294053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 11:44:46.294155 ==
7945 11:44:46.297000 Write leveling (Byte 0): 34 => 34
7946 11:44:46.300496 Write leveling (Byte 1): 27 => 27
7947 11:44:46.303945 DramcWriteLeveling(PI) end<-----
7948 11:44:46.304085
7949 11:44:46.304174 ==
7950 11:44:46.306886 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 11:44:46.313632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 11:44:46.313722 ==
7953 11:44:46.313792 [Gating] SW mode calibration
7954 11:44:46.323670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7955 11:44:46.326769 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7956 11:44:46.333002 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7957 11:44:46.336846 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7958 11:44:46.339898 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7959 11:44:46.346154 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7960 11:44:46.349900 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
7961 11:44:46.353020 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7962 11:44:46.359331 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7963 11:44:46.363064 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7964 11:44:46.366184 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7965 11:44:46.372450 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7966 11:44:46.375657 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7967 11:44:46.379444 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7968 11:44:46.385639 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7969 11:44:46.388807 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7970 11:44:46.392591 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 11:44:46.398607 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 11:44:46.402060 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 11:44:46.405402 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7974 11:44:46.412123 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7975 11:44:46.415174 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7976 11:44:46.418825 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7977 11:44:46.425122 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7978 11:44:46.428801 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 11:44:46.431854 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 11:44:46.438203 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 11:44:46.441362 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7982 11:44:46.445065 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7983 11:44:46.451723 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7984 11:44:46.454839 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7985 11:44:46.458003 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7986 11:44:46.464825 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 11:44:46.467970 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 11:44:46.471099 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 11:44:46.477829 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 11:44:46.481052 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 11:44:46.484155 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 11:44:46.491129 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 11:44:46.494330 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 11:44:46.497461 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 11:44:46.503985 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 11:44:46.507746 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 11:44:46.510869 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7998 11:44:46.517160 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7999 11:44:46.520633 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8000 11:44:46.524000 Total UI for P1: 0, mck2ui 16
8001 11:44:46.526850 best dqsien dly found for B0: ( 1, 9, 6)
8002 11:44:46.530366 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8003 11:44:46.537129 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8004 11:44:46.540248 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 11:44:46.543401 Total UI for P1: 0, mck2ui 16
8006 11:44:46.547179 best dqsien dly found for B1: ( 1, 9, 18)
8007 11:44:46.550317 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8008 11:44:46.553485 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8009 11:44:46.553574
8010 11:44:46.557249 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8011 11:44:46.560419 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8012 11:44:46.563484 [Gating] SW calibration Done
8013 11:44:46.563571 ==
8014 11:44:46.566732 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 11:44:46.573673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 11:44:46.573796 ==
8017 11:44:46.573903 RX Vref Scan: 0
8018 11:44:46.574004
8019 11:44:46.576892 RX Vref 0 -> 0, step: 1
8020 11:44:46.577003
8021 11:44:46.579879 RX Delay 0 -> 252, step: 8
8022 11:44:46.583603 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8023 11:44:46.586739 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8024 11:44:46.589948 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8025 11:44:46.593059 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8026 11:44:46.599416 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8027 11:44:46.603149 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8028 11:44:46.606141 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8029 11:44:46.609814 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8030 11:44:46.616145 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8031 11:44:46.619217 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8032 11:44:46.622346 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8033 11:44:46.625907 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8034 11:44:46.629150 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8035 11:44:46.635790 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8036 11:44:46.639268 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8037 11:44:46.642360 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8038 11:44:46.642465 ==
8039 11:44:46.645338 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 11:44:46.648496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 11:44:46.652190 ==
8042 11:44:46.652275 DQS Delay:
8043 11:44:46.652402 DQS0 = 0, DQS1 = 0
8044 11:44:46.655359 DQM Delay:
8045 11:44:46.655463 DQM0 = 132, DQM1 = 127
8046 11:44:46.658900 DQ Delay:
8047 11:44:46.662044 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8048 11:44:46.665210 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8049 11:44:46.668420 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8050 11:44:46.671506 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8051 11:44:46.671616
8052 11:44:46.671711
8053 11:44:46.671802 ==
8054 11:44:46.674758 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 11:44:46.678596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 11:44:46.681753 ==
8057 11:44:46.681838
8058 11:44:46.681914
8059 11:44:46.681978 TX Vref Scan disable
8060 11:44:46.684745 == TX Byte 0 ==
8061 11:44:46.688542 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8062 11:44:46.691681 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8063 11:44:46.694859 == TX Byte 1 ==
8064 11:44:46.697933 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8065 11:44:46.701694 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8066 11:44:46.704808 ==
8067 11:44:46.707960 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 11:44:46.711050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 11:44:46.711166 ==
8070 11:44:46.725502
8071 11:44:46.728641 TX Vref early break, caculate TX vref
8072 11:44:46.731780 TX Vref=16, minBit 1, minWin=23, winSum=380
8073 11:44:46.735162 TX Vref=18, minBit 0, minWin=24, winSum=392
8074 11:44:46.738599 TX Vref=20, minBit 2, minWin=24, winSum=401
8075 11:44:46.742005 TX Vref=22, minBit 2, minWin=24, winSum=407
8076 11:44:46.744995 TX Vref=24, minBit 2, minWin=25, winSum=416
8077 11:44:46.751573 TX Vref=26, minBit 3, minWin=25, winSum=419
8078 11:44:46.755415 TX Vref=28, minBit 4, minWin=25, winSum=422
8079 11:44:46.758521 TX Vref=30, minBit 1, minWin=25, winSum=417
8080 11:44:46.761545 TX Vref=32, minBit 7, minWin=24, winSum=405
8081 11:44:46.765123 TX Vref=34, minBit 0, minWin=24, winSum=402
8082 11:44:46.771428 TX Vref=36, minBit 8, minWin=23, winSum=396
8083 11:44:46.774568 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
8084 11:44:46.774682
8085 11:44:46.777944 Final TX Range 0 Vref 28
8086 11:44:46.778050
8087 11:44:46.778150 ==
8088 11:44:46.781062 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 11:44:46.784925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 11:44:46.788049 ==
8091 11:44:46.788131
8092 11:44:46.788216
8093 11:44:46.788281 TX Vref Scan disable
8094 11:44:46.794890 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8095 11:44:46.795014 == TX Byte 0 ==
8096 11:44:46.798098 u2DelayCellOfst[0]=14 cells (4 PI)
8097 11:44:46.801226 u2DelayCellOfst[1]=17 cells (5 PI)
8098 11:44:46.804468 u2DelayCellOfst[2]=10 cells (3 PI)
8099 11:44:46.808221 u2DelayCellOfst[3]=14 cells (4 PI)
8100 11:44:46.811248 u2DelayCellOfst[4]=10 cells (3 PI)
8101 11:44:46.814423 u2DelayCellOfst[5]=0 cells (0 PI)
8102 11:44:46.818032 u2DelayCellOfst[6]=17 cells (5 PI)
8103 11:44:46.821117 u2DelayCellOfst[7]=17 cells (5 PI)
8104 11:44:46.824269 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8105 11:44:46.828071 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8106 11:44:46.831213 == TX Byte 1 ==
8107 11:44:46.834463 u2DelayCellOfst[8]=3 cells (1 PI)
8108 11:44:46.837500 u2DelayCellOfst[9]=0 cells (0 PI)
8109 11:44:46.840656 u2DelayCellOfst[10]=7 cells (2 PI)
8110 11:44:46.844412 u2DelayCellOfst[11]=3 cells (1 PI)
8111 11:44:46.847349 u2DelayCellOfst[12]=10 cells (3 PI)
8112 11:44:46.850872 u2DelayCellOfst[13]=10 cells (3 PI)
8113 11:44:46.854352 u2DelayCellOfst[14]=17 cells (5 PI)
8114 11:44:46.854478 u2DelayCellOfst[15]=10 cells (3 PI)
8115 11:44:46.860941 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8116 11:44:46.863843 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8117 11:44:46.867393 DramC Write-DBI on
8118 11:44:46.867517 ==
8119 11:44:46.870471 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 11:44:46.874022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 11:44:46.874157 ==
8122 11:44:46.874254
8123 11:44:46.874384
8124 11:44:46.877245 TX Vref Scan disable
8125 11:44:46.877324 == TX Byte 0 ==
8126 11:44:46.883686 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8127 11:44:46.883811 == TX Byte 1 ==
8128 11:44:46.889919 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8129 11:44:46.890030 DramC Write-DBI off
8130 11:44:46.890152
8131 11:44:46.890250 [DATLAT]
8132 11:44:46.893560 Freq=1600, CH0 RK1
8133 11:44:46.893656
8134 11:44:46.896687 DATLAT Default: 0xf
8135 11:44:46.896780 0, 0xFFFF, sum = 0
8136 11:44:46.899795 1, 0xFFFF, sum = 0
8137 11:44:46.899900 2, 0xFFFF, sum = 0
8138 11:44:46.903515 3, 0xFFFF, sum = 0
8139 11:44:46.903639 4, 0xFFFF, sum = 0
8140 11:44:46.906689 5, 0xFFFF, sum = 0
8141 11:44:46.906818 6, 0xFFFF, sum = 0
8142 11:44:46.909761 7, 0xFFFF, sum = 0
8143 11:44:46.909881 8, 0xFFFF, sum = 0
8144 11:44:46.912980 9, 0xFFFF, sum = 0
8145 11:44:46.913058 10, 0xFFFF, sum = 0
8146 11:44:46.916713 11, 0xFFFF, sum = 0
8147 11:44:46.916818 12, 0xFFFF, sum = 0
8148 11:44:46.919780 13, 0xFFFF, sum = 0
8149 11:44:46.919874 14, 0x0, sum = 1
8150 11:44:46.922784 15, 0x0, sum = 2
8151 11:44:46.922875 16, 0x0, sum = 3
8152 11:44:46.926535 17, 0x0, sum = 4
8153 11:44:46.926631 best_step = 15
8154 11:44:46.926701
8155 11:44:46.926765 ==
8156 11:44:46.929659 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 11:44:46.936045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 11:44:46.936129 ==
8159 11:44:46.936208 RX Vref Scan: 0
8160 11:44:46.936274
8161 11:44:46.939197 RX Vref 0 -> 0, step: 1
8162 11:44:46.939272
8163 11:44:46.942825 RX Delay 11 -> 252, step: 4
8164 11:44:46.945943 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8165 11:44:46.949587 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8166 11:44:46.955611 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8167 11:44:46.959313 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8168 11:44:46.962436 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8169 11:44:46.966045 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8170 11:44:46.968969 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8171 11:44:46.975768 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8172 11:44:46.978773 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8173 11:44:46.981918 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8174 11:44:46.985597 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8175 11:44:46.992416 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8176 11:44:46.995577 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8177 11:44:46.998591 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8178 11:44:47.001812 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8179 11:44:47.005033 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8180 11:44:47.008191 ==
8181 11:44:47.011833 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 11:44:47.015073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 11:44:47.015194 ==
8184 11:44:47.015306 DQS Delay:
8185 11:44:47.018214 DQS0 = 0, DQS1 = 0
8186 11:44:47.018325 DQM Delay:
8187 11:44:47.021406 DQM0 = 128, DQM1 = 124
8188 11:44:47.021517 DQ Delay:
8189 11:44:47.025166 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8190 11:44:47.028184 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8191 11:44:47.031245 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8192 11:44:47.034983 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8193 11:44:47.035103
8194 11:44:47.035205
8195 11:44:47.035316
8196 11:44:47.038083 [DramC_TX_OE_Calibration] TA2
8197 11:44:47.041390 Original DQ_B0 (3 6) =30, OEN = 27
8198 11:44:47.044517 Original DQ_B1 (3 6) =30, OEN = 27
8199 11:44:47.048314 24, 0x0, End_B0=24 End_B1=24
8200 11:44:47.051417 25, 0x0, End_B0=25 End_B1=25
8201 11:44:47.051528 26, 0x0, End_B0=26 End_B1=26
8202 11:44:47.054451 27, 0x0, End_B0=27 End_B1=27
8203 11:44:47.058048 28, 0x0, End_B0=28 End_B1=28
8204 11:44:47.061019 29, 0x0, End_B0=29 End_B1=29
8205 11:44:47.064195 30, 0x0, End_B0=30 End_B1=30
8206 11:44:47.067887 31, 0x4141, End_B0=30 End_B1=30
8207 11:44:47.067974 Byte0 end_step=30 best_step=27
8208 11:44:47.070834 Byte1 end_step=30 best_step=27
8209 11:44:47.074428 Byte0 TX OE(2T, 0.5T) = (3, 3)
8210 11:44:47.077877 Byte1 TX OE(2T, 0.5T) = (3, 3)
8211 11:44:47.077986
8212 11:44:47.078098
8213 11:44:47.087522 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8214 11:44:47.087655 CH0 RK1: MR19=303, MR18=1412
8215 11:44:47.093808 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8216 11:44:47.097583 [RxdqsGatingPostProcess] freq 1600
8217 11:44:47.103795 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8218 11:44:47.106938 best DQS0 dly(2T, 0.5T) = (1, 1)
8219 11:44:47.110668 best DQS1 dly(2T, 0.5T) = (1, 1)
8220 11:44:47.113785 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8221 11:44:47.117032 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8222 11:44:47.117137 best DQS0 dly(2T, 0.5T) = (1, 1)
8223 11:44:47.120108 best DQS1 dly(2T, 0.5T) = (1, 1)
8224 11:44:47.123304 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8225 11:44:47.127078 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8226 11:44:47.130219 Pre-setting of DQS Precalculation
8227 11:44:47.136971 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8228 11:44:47.137058 ==
8229 11:44:47.140038 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 11:44:47.143343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 11:44:47.143459 ==
8232 11:44:47.149582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8233 11:44:47.152798 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8234 11:44:47.156529 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8235 11:44:47.162555 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8236 11:44:47.172012 [CA 0] Center 42 (13~72) winsize 60
8237 11:44:47.175098 [CA 1] Center 42 (12~73) winsize 62
8238 11:44:47.178630 [CA 2] Center 38 (9~68) winsize 60
8239 11:44:47.182087 [CA 3] Center 37 (8~67) winsize 60
8240 11:44:47.185727 [CA 4] Center 38 (8~69) winsize 62
8241 11:44:47.188685 [CA 5] Center 37 (7~67) winsize 61
8242 11:44:47.188760
8243 11:44:47.191697 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8244 11:44:47.191779
8245 11:44:47.195512 [CATrainingPosCal] consider 1 rank data
8246 11:44:47.198599 u2DelayCellTimex100 = 275/100 ps
8247 11:44:47.201712 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8248 11:44:47.208610 CA1 delay=42 (12~73),Diff = 5 PI (17 cell)
8249 11:44:47.211732 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8250 11:44:47.214839 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8251 11:44:47.218546 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8252 11:44:47.221626 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8253 11:44:47.221702
8254 11:44:47.224894 CA PerBit enable=1, Macro0, CA PI delay=37
8255 11:44:47.224969
8256 11:44:47.228035 [CBTSetCACLKResult] CA Dly = 37
8257 11:44:47.231710 CS Dly: 7 (0~38)
8258 11:44:47.234796 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8259 11:44:47.238503 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8260 11:44:47.238590 ==
8261 11:44:47.241775 Dram Type= 6, Freq= 0, CH_1, rank 1
8262 11:44:47.244971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 11:44:47.247987 ==
8264 11:44:47.251820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8265 11:44:47.254866 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8266 11:44:47.261240 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8267 11:44:47.267837 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8268 11:44:47.275425 [CA 0] Center 42 (12~72) winsize 61
8269 11:44:47.278412 [CA 1] Center 42 (13~72) winsize 60
8270 11:44:47.281997 [CA 2] Center 38 (8~68) winsize 61
8271 11:44:47.285005 [CA 3] Center 37 (8~67) winsize 60
8272 11:44:47.288677 [CA 4] Center 37 (8~67) winsize 60
8273 11:44:47.291795 [CA 5] Center 37 (7~67) winsize 61
8274 11:44:47.291911
8275 11:44:47.294922 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8276 11:44:47.295035
8277 11:44:47.301610 [CATrainingPosCal] consider 2 rank data
8278 11:44:47.301720 u2DelayCellTimex100 = 275/100 ps
8279 11:44:47.307952 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8280 11:44:47.311538 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8281 11:44:47.314816 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8282 11:44:47.317888 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8283 11:44:47.321085 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8284 11:44:47.324791 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8285 11:44:47.324902
8286 11:44:47.327925 CA PerBit enable=1, Macro0, CA PI delay=37
8287 11:44:47.328036
8288 11:44:47.331078 [CBTSetCACLKResult] CA Dly = 37
8289 11:44:47.334141 CS Dly: 9 (0~42)
8290 11:44:47.337925 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8291 11:44:47.340984 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8292 11:44:47.341101
8293 11:44:47.344511 ----->DramcWriteLeveling(PI) begin...
8294 11:44:47.344624 ==
8295 11:44:47.347746 Dram Type= 6, Freq= 0, CH_1, rank 0
8296 11:44:47.354415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 11:44:47.354533 ==
8298 11:44:47.357619 Write leveling (Byte 0): 25 => 25
8299 11:44:47.360849 Write leveling (Byte 1): 27 => 27
8300 11:44:47.360974 DramcWriteLeveling(PI) end<-----
8301 11:44:47.363888
8302 11:44:47.363990 ==
8303 11:44:47.367030 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 11:44:47.370707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 11:44:47.370824 ==
8306 11:44:47.373820 [Gating] SW mode calibration
8307 11:44:47.380716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8308 11:44:47.386781 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8309 11:44:47.390359 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8310 11:44:47.393355 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 11:44:47.399968 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8312 11:44:47.403683 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8313 11:44:47.406741 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 11:44:47.413065 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 11:44:47.416646 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 11:44:47.419808 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 11:44:47.426744 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 11:44:47.429894 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 11:44:47.433032 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 11:44:47.439333 1 5 12 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
8321 11:44:47.442590 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8322 11:44:47.446365 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 11:44:47.452481 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 11:44:47.455715 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 11:44:47.459440 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 11:44:47.465765 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 11:44:47.468942 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8328 11:44:47.472749 1 6 12 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8329 11:44:47.478776 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 11:44:47.482006 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 11:44:47.485904 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 11:44:47.492205 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 11:44:47.495218 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 11:44:47.498807 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 11:44:47.505316 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 11:44:47.508266 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8337 11:44:47.511869 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8338 11:44:47.518217 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 11:44:47.521430 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 11:44:47.525181 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 11:44:47.531510 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 11:44:47.534573 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 11:44:47.537692 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 11:44:47.544718 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 11:44:47.547889 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 11:44:47.550994 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 11:44:47.557817 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 11:44:47.561025 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 11:44:47.564249 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 11:44:47.570580 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:44:47.574395 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8352 11:44:47.577549 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8353 11:44:47.584345 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 11:44:47.587525 Total UI for P1: 0, mck2ui 16
8355 11:44:47.590633 best dqsien dly found for B0: ( 1, 9, 10)
8356 11:44:47.593764 Total UI for P1: 0, mck2ui 16
8357 11:44:47.597500 best dqsien dly found for B1: ( 1, 9, 12)
8358 11:44:47.600689 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8359 11:44:47.603848 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8360 11:44:47.603978
8361 11:44:47.606833 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8362 11:44:47.610358 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8363 11:44:47.613687 [Gating] SW calibration Done
8364 11:44:47.613774 ==
8365 11:44:47.616722 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 11:44:47.620185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 11:44:47.620282 ==
8368 11:44:47.623712 RX Vref Scan: 0
8369 11:44:47.623830
8370 11:44:47.626767 RX Vref 0 -> 0, step: 1
8371 11:44:47.626849
8372 11:44:47.626928 RX Delay 0 -> 252, step: 8
8373 11:44:47.633338 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8374 11:44:47.637116 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8375 11:44:47.640368 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8376 11:44:47.643483 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8377 11:44:47.646758 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8378 11:44:47.653140 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8379 11:44:47.656588 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8380 11:44:47.659740 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8381 11:44:47.662946 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8382 11:44:47.666064 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8383 11:44:47.672859 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8384 11:44:47.675893 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8385 11:44:47.679663 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8386 11:44:47.682827 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8387 11:44:47.689167 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8388 11:44:47.692934 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8389 11:44:47.693021 ==
8390 11:44:47.696134 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 11:44:47.699358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 11:44:47.699444 ==
8393 11:44:47.702460 DQS Delay:
8394 11:44:47.702548 DQS0 = 0, DQS1 = 0
8395 11:44:47.702619 DQM Delay:
8396 11:44:47.705562 DQM0 = 135, DQM1 = 130
8397 11:44:47.705647 DQ Delay:
8398 11:44:47.709406 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8399 11:44:47.712498 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8400 11:44:47.719198 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8401 11:44:47.722035 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8402 11:44:47.722121
8403 11:44:47.722189
8404 11:44:47.722252 ==
8405 11:44:47.725616 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 11:44:47.728657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 11:44:47.728742 ==
8408 11:44:47.728810
8409 11:44:47.728873
8410 11:44:47.732125 TX Vref Scan disable
8411 11:44:47.735583 == TX Byte 0 ==
8412 11:44:47.738620 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8413 11:44:47.742083 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8414 11:44:47.745196 == TX Byte 1 ==
8415 11:44:47.748896 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8416 11:44:47.752099 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8417 11:44:47.752176 ==
8418 11:44:47.755206 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 11:44:47.758303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 11:44:47.761918 ==
8421 11:44:47.773135
8422 11:44:47.776196 TX Vref early break, caculate TX vref
8423 11:44:47.779405 TX Vref=16, minBit 8, minWin=21, winSum=367
8424 11:44:47.782430 TX Vref=18, minBit 3, minWin=23, winSum=378
8425 11:44:47.786230 TX Vref=20, minBit 8, minWin=23, winSum=385
8426 11:44:47.789179 TX Vref=22, minBit 8, minWin=23, winSum=396
8427 11:44:47.792432 TX Vref=24, minBit 9, minWin=23, winSum=407
8428 11:44:47.799416 TX Vref=26, minBit 6, minWin=25, winSum=415
8429 11:44:47.802530 TX Vref=28, minBit 0, minWin=25, winSum=416
8430 11:44:47.805740 TX Vref=30, minBit 0, minWin=25, winSum=415
8431 11:44:47.808818 TX Vref=32, minBit 0, minWin=24, winSum=404
8432 11:44:47.811965 TX Vref=34, minBit 9, minWin=22, winSum=392
8433 11:44:47.818926 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
8434 11:44:47.819057
8435 11:44:47.822053 Final TX Range 0 Vref 28
8436 11:44:47.822162
8437 11:44:47.822260 ==
8438 11:44:47.825548 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 11:44:47.828460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 11:44:47.828574 ==
8441 11:44:47.828672
8442 11:44:47.828791
8443 11:44:47.831759 TX Vref Scan disable
8444 11:44:47.838382 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8445 11:44:47.838464 == TX Byte 0 ==
8446 11:44:47.842042 u2DelayCellOfst[0]=14 cells (4 PI)
8447 11:44:47.845699 u2DelayCellOfst[1]=10 cells (3 PI)
8448 11:44:47.848603 u2DelayCellOfst[2]=0 cells (0 PI)
8449 11:44:47.852134 u2DelayCellOfst[3]=7 cells (2 PI)
8450 11:44:47.855200 u2DelayCellOfst[4]=10 cells (3 PI)
8451 11:44:47.858521 u2DelayCellOfst[5]=17 cells (5 PI)
8452 11:44:47.861621 u2DelayCellOfst[6]=17 cells (5 PI)
8453 11:44:47.865221 u2DelayCellOfst[7]=7 cells (2 PI)
8454 11:44:47.868175 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8455 11:44:47.871283 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8456 11:44:47.875110 == TX Byte 1 ==
8457 11:44:47.878216 u2DelayCellOfst[8]=0 cells (0 PI)
8458 11:44:47.881344 u2DelayCellOfst[9]=3 cells (1 PI)
8459 11:44:47.884566 u2DelayCellOfst[10]=14 cells (4 PI)
8460 11:44:47.884654 u2DelayCellOfst[11]=3 cells (1 PI)
8461 11:44:47.888272 u2DelayCellOfst[12]=14 cells (4 PI)
8462 11:44:47.891314 u2DelayCellOfst[13]=14 cells (4 PI)
8463 11:44:47.894291 u2DelayCellOfst[14]=17 cells (5 PI)
8464 11:44:47.897523 u2DelayCellOfst[15]=17 cells (5 PI)
8465 11:44:47.904435 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8466 11:44:47.907553 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8467 11:44:47.907659 DramC Write-DBI on
8468 11:44:47.911096 ==
8469 11:44:47.914241 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 11:44:47.917438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 11:44:47.917548 ==
8472 11:44:47.917633
8473 11:44:47.917714
8474 11:44:47.920654 TX Vref Scan disable
8475 11:44:47.920748 == TX Byte 0 ==
8476 11:44:47.927610 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8477 11:44:47.927698 == TX Byte 1 ==
8478 11:44:47.930794 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8479 11:44:47.933797 DramC Write-DBI off
8480 11:44:47.933883
8481 11:44:47.933970 [DATLAT]
8482 11:44:47.937229 Freq=1600, CH1 RK0
8483 11:44:47.937316
8484 11:44:47.937403 DATLAT Default: 0xf
8485 11:44:47.940755 0, 0xFFFF, sum = 0
8486 11:44:47.940843 1, 0xFFFF, sum = 0
8487 11:44:47.943690 2, 0xFFFF, sum = 0
8488 11:44:47.943807 3, 0xFFFF, sum = 0
8489 11:44:47.947331 4, 0xFFFF, sum = 0
8490 11:44:47.950341 5, 0xFFFF, sum = 0
8491 11:44:47.950434 6, 0xFFFF, sum = 0
8492 11:44:47.954043 7, 0xFFFF, sum = 0
8493 11:44:47.954156 8, 0xFFFF, sum = 0
8494 11:44:47.956849 9, 0xFFFF, sum = 0
8495 11:44:47.956966 10, 0xFFFF, sum = 0
8496 11:44:47.960268 11, 0xFFFF, sum = 0
8497 11:44:47.960355 12, 0xFFFF, sum = 0
8498 11:44:47.963798 13, 0xFFFF, sum = 0
8499 11:44:47.963907 14, 0x0, sum = 1
8500 11:44:47.966972 15, 0x0, sum = 2
8501 11:44:47.967057 16, 0x0, sum = 3
8502 11:44:47.969883 17, 0x0, sum = 4
8503 11:44:47.969968 best_step = 15
8504 11:44:47.970033
8505 11:44:47.970095 ==
8506 11:44:47.973496 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 11:44:47.979843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 11:44:47.979931 ==
8509 11:44:47.979999 RX Vref Scan: 1
8510 11:44:47.980073
8511 11:44:47.983652 Set Vref Range= 24 -> 127
8512 11:44:47.983774
8513 11:44:47.986769 RX Vref 24 -> 127, step: 1
8514 11:44:47.986852
8515 11:44:47.986920 RX Delay 19 -> 252, step: 4
8516 11:44:47.986983
8517 11:44:47.990032 Set Vref, RX VrefLevel [Byte0]: 24
8518 11:44:47.993200 [Byte1]: 24
8519 11:44:47.997330
8520 11:44:47.997413 Set Vref, RX VrefLevel [Byte0]: 25
8521 11:44:48.000462 [Byte1]: 25
8522 11:44:48.004926
8523 11:44:48.005009 Set Vref, RX VrefLevel [Byte0]: 26
8524 11:44:48.008073 [Byte1]: 26
8525 11:44:48.012628
8526 11:44:48.012711 Set Vref, RX VrefLevel [Byte0]: 27
8527 11:44:48.015775 [Byte1]: 27
8528 11:44:48.020212
8529 11:44:48.020297 Set Vref, RX VrefLevel [Byte0]: 28
8530 11:44:48.023322 [Byte1]: 28
8531 11:44:48.027765
8532 11:44:48.027849 Set Vref, RX VrefLevel [Byte0]: 29
8533 11:44:48.030990 [Byte1]: 29
8534 11:44:48.034790
8535 11:44:48.034873 Set Vref, RX VrefLevel [Byte0]: 30
8536 11:44:48.038576 [Byte1]: 30
8537 11:44:48.042886
8538 11:44:48.042970 Set Vref, RX VrefLevel [Byte0]: 31
8539 11:44:48.046087 [Byte1]: 31
8540 11:44:48.050299
8541 11:44:48.050414 Set Vref, RX VrefLevel [Byte0]: 32
8542 11:44:48.053342 [Byte1]: 32
8543 11:44:48.057732
8544 11:44:48.057816 Set Vref, RX VrefLevel [Byte0]: 33
8545 11:44:48.061390 [Byte1]: 33
8546 11:44:48.065557
8547 11:44:48.065642 Set Vref, RX VrefLevel [Byte0]: 34
8548 11:44:48.068619 [Byte1]: 34
8549 11:44:48.072977
8550 11:44:48.073066 Set Vref, RX VrefLevel [Byte0]: 35
8551 11:44:48.075994 [Byte1]: 35
8552 11:44:48.080514
8553 11:44:48.080599 Set Vref, RX VrefLevel [Byte0]: 36
8554 11:44:48.083618 [Byte1]: 36
8555 11:44:48.087816
8556 11:44:48.087923 Set Vref, RX VrefLevel [Byte0]: 37
8557 11:44:48.091632 [Byte1]: 37
8558 11:44:48.095358
8559 11:44:48.095460 Set Vref, RX VrefLevel [Byte0]: 38
8560 11:44:48.099033 [Byte1]: 38
8561 11:44:48.103470
8562 11:44:48.103551 Set Vref, RX VrefLevel [Byte0]: 39
8563 11:44:48.106559 [Byte1]: 39
8564 11:44:48.110984
8565 11:44:48.111099 Set Vref, RX VrefLevel [Byte0]: 40
8566 11:44:48.114069 [Byte1]: 40
8567 11:44:48.118481
8568 11:44:48.118590 Set Vref, RX VrefLevel [Byte0]: 41
8569 11:44:48.121581 [Byte1]: 41
8570 11:44:48.125975
8571 11:44:48.126074 Set Vref, RX VrefLevel [Byte0]: 42
8572 11:44:48.129149 [Byte1]: 42
8573 11:44:48.133476
8574 11:44:48.133572 Set Vref, RX VrefLevel [Byte0]: 43
8575 11:44:48.136685 [Byte1]: 43
8576 11:44:48.140985
8577 11:44:48.141067 Set Vref, RX VrefLevel [Byte0]: 44
8578 11:44:48.144051 [Byte1]: 44
8579 11:44:48.148421
8580 11:44:48.148504 Set Vref, RX VrefLevel [Byte0]: 45
8581 11:44:48.152099 [Byte1]: 45
8582 11:44:48.156203
8583 11:44:48.156299 Set Vref, RX VrefLevel [Byte0]: 46
8584 11:44:48.159451 [Byte1]: 46
8585 11:44:48.163725
8586 11:44:48.163806 Set Vref, RX VrefLevel [Byte0]: 47
8587 11:44:48.167243 [Byte1]: 47
8588 11:44:48.171318
8589 11:44:48.171408 Set Vref, RX VrefLevel [Byte0]: 48
8590 11:44:48.174932 [Byte1]: 48
8591 11:44:48.179046
8592 11:44:48.179166 Set Vref, RX VrefLevel [Byte0]: 49
8593 11:44:48.182054 [Byte1]: 49
8594 11:44:48.186320
8595 11:44:48.186429 Set Vref, RX VrefLevel [Byte0]: 50
8596 11:44:48.189498 [Byte1]: 50
8597 11:44:48.193975
8598 11:44:48.194132 Set Vref, RX VrefLevel [Byte0]: 51
8599 11:44:48.197218 [Byte1]: 51
8600 11:44:48.201662
8601 11:44:48.201749 Set Vref, RX VrefLevel [Byte0]: 52
8602 11:44:48.208261 [Byte1]: 52
8603 11:44:48.208345
8604 11:44:48.211481 Set Vref, RX VrefLevel [Byte0]: 53
8605 11:44:48.214612 [Byte1]: 53
8606 11:44:48.214697
8607 11:44:48.217831 Set Vref, RX VrefLevel [Byte0]: 54
8608 11:44:48.220993 [Byte1]: 54
8609 11:44:48.224869
8610 11:44:48.224956 Set Vref, RX VrefLevel [Byte0]: 55
8611 11:44:48.227982 [Byte1]: 55
8612 11:44:48.231777
8613 11:44:48.231883 Set Vref, RX VrefLevel [Byte0]: 56
8614 11:44:48.235600 [Byte1]: 56
8615 11:44:48.239347
8616 11:44:48.239430 Set Vref, RX VrefLevel [Byte0]: 57
8617 11:44:48.242538 [Byte1]: 57
8618 11:44:48.246838
8619 11:44:48.246952 Set Vref, RX VrefLevel [Byte0]: 58
8620 11:44:48.250420 [Byte1]: 58
8621 11:44:48.254864
8622 11:44:48.254977 Set Vref, RX VrefLevel [Byte0]: 59
8623 11:44:48.257935 [Byte1]: 59
8624 11:44:48.262165
8625 11:44:48.262249 Set Vref, RX VrefLevel [Byte0]: 60
8626 11:44:48.265732 [Byte1]: 60
8627 11:44:48.270055
8628 11:44:48.270168 Set Vref, RX VrefLevel [Byte0]: 61
8629 11:44:48.272948 [Byte1]: 61
8630 11:44:48.277102
8631 11:44:48.277216 Set Vref, RX VrefLevel [Byte0]: 62
8632 11:44:48.280716 [Byte1]: 62
8633 11:44:48.284881
8634 11:44:48.284998 Set Vref, RX VrefLevel [Byte0]: 63
8635 11:44:48.287988 [Byte1]: 63
8636 11:44:48.292783
8637 11:44:48.292898 Set Vref, RX VrefLevel [Byte0]: 64
8638 11:44:48.295987 [Byte1]: 64
8639 11:44:48.299803
8640 11:44:48.299912 Set Vref, RX VrefLevel [Byte0]: 65
8641 11:44:48.306526 [Byte1]: 65
8642 11:44:48.306635
8643 11:44:48.309518 Set Vref, RX VrefLevel [Byte0]: 66
8644 11:44:48.313139 [Byte1]: 66
8645 11:44:48.313247
8646 11:44:48.316389 Set Vref, RX VrefLevel [Byte0]: 67
8647 11:44:48.319543 [Byte1]: 67
8648 11:44:48.319654
8649 11:44:48.323333 Set Vref, RX VrefLevel [Byte0]: 68
8650 11:44:48.326532 [Byte1]: 68
8651 11:44:48.330351
8652 11:44:48.330454 Set Vref, RX VrefLevel [Byte0]: 69
8653 11:44:48.333385 [Byte1]: 69
8654 11:44:48.337692
8655 11:44:48.337795 Set Vref, RX VrefLevel [Byte0]: 70
8656 11:44:48.340942 [Byte1]: 70
8657 11:44:48.345396
8658 11:44:48.345497 Final RX Vref Byte 0 = 57 to rank0
8659 11:44:48.349086 Final RX Vref Byte 1 = 61 to rank0
8660 11:44:48.352019 Final RX Vref Byte 0 = 57 to rank1
8661 11:44:48.355576 Final RX Vref Byte 1 = 61 to rank1==
8662 11:44:48.358626 Dram Type= 6, Freq= 0, CH_1, rank 0
8663 11:44:48.365628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8664 11:44:48.365739 ==
8665 11:44:48.365840 DQS Delay:
8666 11:44:48.368764 DQS0 = 0, DQS1 = 0
8667 11:44:48.368872 DQM Delay:
8668 11:44:48.368977 DQM0 = 132, DQM1 = 128
8669 11:44:48.372325 DQ Delay:
8670 11:44:48.375171 DQ0 =140, DQ1 =130, DQ2 =118, DQ3 =132
8671 11:44:48.378797 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8672 11:44:48.381917 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8673 11:44:48.384888 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8674 11:44:48.384966
8675 11:44:48.385033
8676 11:44:48.385094
8677 11:44:48.388394 [DramC_TX_OE_Calibration] TA2
8678 11:44:48.391976 Original DQ_B0 (3 6) =30, OEN = 27
8679 11:44:48.394937 Original DQ_B1 (3 6) =30, OEN = 27
8680 11:44:48.397999 24, 0x0, End_B0=24 End_B1=24
8681 11:44:48.401859 25, 0x0, End_B0=25 End_B1=25
8682 11:44:48.401947 26, 0x0, End_B0=26 End_B1=26
8683 11:44:48.404793 27, 0x0, End_B0=27 End_B1=27
8684 11:44:48.407977 28, 0x0, End_B0=28 End_B1=28
8685 11:44:48.411735 29, 0x0, End_B0=29 End_B1=29
8686 11:44:48.411820 30, 0x0, End_B0=30 End_B1=30
8687 11:44:48.414786 31, 0x4141, End_B0=30 End_B1=30
8688 11:44:48.418436 Byte0 end_step=30 best_step=27
8689 11:44:48.421403 Byte1 end_step=30 best_step=27
8690 11:44:48.424699 Byte0 TX OE(2T, 0.5T) = (3, 3)
8691 11:44:48.428401 Byte1 TX OE(2T, 0.5T) = (3, 3)
8692 11:44:48.428483
8693 11:44:48.428585
8694 11:44:48.434715 [DQSOSCAuto] RK0, (LSB)MR18= 0x913, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8695 11:44:48.437975 CH1 RK0: MR19=303, MR18=913
8696 11:44:48.444314 CH1_RK0: MR19=0x303, MR18=0x913, DQSOSC=400, MR23=63, INC=23, DEC=15
8697 11:44:48.444401
8698 11:44:48.447529 ----->DramcWriteLeveling(PI) begin...
8699 11:44:48.447633 ==
8700 11:44:48.450757 Dram Type= 6, Freq= 0, CH_1, rank 1
8701 11:44:48.454455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 11:44:48.454562 ==
8703 11:44:48.457377 Write leveling (Byte 0): 24 => 24
8704 11:44:48.461042 Write leveling (Byte 1): 26 => 26
8705 11:44:48.464266 DramcWriteLeveling(PI) end<-----
8706 11:44:48.464371
8707 11:44:48.464468 ==
8708 11:44:48.467383 Dram Type= 6, Freq= 0, CH_1, rank 1
8709 11:44:48.470529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 11:44:48.473720 ==
8711 11:44:48.473811 [Gating] SW mode calibration
8712 11:44:48.483833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8713 11:44:48.487004 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8714 11:44:48.490558 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8715 11:44:48.497206 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8716 11:44:48.500012 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8717 11:44:48.503630 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8718 11:44:48.510054 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8719 11:44:48.513353 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8720 11:44:48.516529 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8721 11:44:48.523229 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8722 11:44:48.526546 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8723 11:44:48.529636 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8724 11:44:48.536610 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8725 11:44:48.539698 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8726 11:44:48.543231 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8727 11:44:48.549595 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 11:44:48.552754 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 11:44:48.555838 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 11:44:48.562726 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 11:44:48.566305 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8732 11:44:48.569552 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8733 11:44:48.575691 1 6 12 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
8734 11:44:48.579421 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8735 11:44:48.582640 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8736 11:44:48.589365 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8737 11:44:48.592231 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8738 11:44:48.595922 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8739 11:44:48.601925 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8740 11:44:48.605437 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8741 11:44:48.611778 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8742 11:44:48.615386 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8743 11:44:48.618554 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8744 11:44:48.624803 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8745 11:44:48.628449 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8746 11:44:48.631537 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8747 11:44:48.638455 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8748 11:44:48.641507 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8749 11:44:48.644619 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8750 11:44:48.651595 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8751 11:44:48.654802 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 11:44:48.657951 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 11:44:48.664888 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 11:44:48.667979 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 11:44:48.670941 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8756 11:44:48.677758 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8757 11:44:48.680944 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8758 11:44:48.684825 Total UI for P1: 0, mck2ui 16
8759 11:44:48.687996 best dqsien dly found for B0: ( 1, 9, 6)
8760 11:44:48.691109 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8761 11:44:48.694294 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 11:44:48.697925 Total UI for P1: 0, mck2ui 16
8763 11:44:48.700945 best dqsien dly found for B1: ( 1, 9, 14)
8764 11:44:48.704555 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8765 11:44:48.711276 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8766 11:44:48.711364
8767 11:44:48.714195 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8768 11:44:48.717796 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8769 11:44:48.720687 [Gating] SW calibration Done
8770 11:44:48.720773 ==
8771 11:44:48.723828 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 11:44:48.727535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 11:44:48.727647 ==
8774 11:44:48.730545 RX Vref Scan: 0
8775 11:44:48.730654
8776 11:44:48.730750 RX Vref 0 -> 0, step: 1
8777 11:44:48.730844
8778 11:44:48.733602 RX Delay 0 -> 252, step: 8
8779 11:44:48.737374 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8780 11:44:48.743568 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8781 11:44:48.746718 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8782 11:44:48.750508 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8783 11:44:48.753605 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8784 11:44:48.756836 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8785 11:44:48.763296 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8786 11:44:48.767025 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8787 11:44:48.770174 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8788 11:44:48.773374 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8789 11:44:48.776895 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8790 11:44:48.783122 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8791 11:44:48.786309 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8792 11:44:48.789478 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8793 11:44:48.793182 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8794 11:44:48.799609 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8795 11:44:48.799696 ==
8796 11:44:48.802773 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 11:44:48.806404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 11:44:48.806489 ==
8799 11:44:48.806557 DQS Delay:
8800 11:44:48.809485 DQS0 = 0, DQS1 = 0
8801 11:44:48.809596 DQM Delay:
8802 11:44:48.812958 DQM0 = 133, DQM1 = 131
8803 11:44:48.813072 DQ Delay:
8804 11:44:48.815970 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8805 11:44:48.819550 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8806 11:44:48.822505 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8807 11:44:48.826072 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8808 11:44:48.826164
8809 11:44:48.829196
8810 11:44:48.829306 ==
8811 11:44:48.832304 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 11:44:48.835997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 11:44:48.836089 ==
8814 11:44:48.836156
8815 11:44:48.836218
8816 11:44:48.838966 TX Vref Scan disable
8817 11:44:48.839052 == TX Byte 0 ==
8818 11:44:48.845377 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8819 11:44:48.849104 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8820 11:44:48.849191 == TX Byte 1 ==
8821 11:44:48.855407 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8822 11:44:48.858581 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8823 11:44:48.858668 ==
8824 11:44:48.862251 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 11:44:48.865387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 11:44:48.865474 ==
8827 11:44:48.881351
8828 11:44:48.884310 TX Vref early break, caculate TX vref
8829 11:44:48.887471 TX Vref=16, minBit 9, minWin=21, winSum=377
8830 11:44:48.890735 TX Vref=18, minBit 9, minWin=22, winSum=389
8831 11:44:48.894543 TX Vref=20, minBit 9, minWin=23, winSum=394
8832 11:44:48.897744 TX Vref=22, minBit 9, minWin=22, winSum=400
8833 11:44:48.901689 TX Vref=24, minBit 9, minWin=23, winSum=409
8834 11:44:48.907923 TX Vref=26, minBit 9, minWin=24, winSum=415
8835 11:44:48.911053 TX Vref=28, minBit 1, minWin=25, winSum=418
8836 11:44:48.914004 TX Vref=30, minBit 0, minWin=25, winSum=414
8837 11:44:48.917836 TX Vref=32, minBit 0, minWin=24, winSum=409
8838 11:44:48.920758 TX Vref=34, minBit 8, minWin=23, winSum=399
8839 11:44:48.924409 TX Vref=36, minBit 0, minWin=23, winSum=397
8840 11:44:48.930411 TX Vref=38, minBit 5, minWin=23, winSum=386
8841 11:44:48.934008 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8842 11:44:48.934091
8843 11:44:48.937576 Final TX Range 0 Vref 28
8844 11:44:48.937699
8845 11:44:48.937822 ==
8846 11:44:48.940558 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 11:44:48.946956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 11:44:48.947067 ==
8849 11:44:48.947169
8850 11:44:48.947264
8851 11:44:48.947370 TX Vref Scan disable
8852 11:44:48.954326 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8853 11:44:48.954439 == TX Byte 0 ==
8854 11:44:48.957569 u2DelayCellOfst[0]=14 cells (4 PI)
8855 11:44:48.960673 u2DelayCellOfst[1]=10 cells (3 PI)
8856 11:44:48.964510 u2DelayCellOfst[2]=0 cells (0 PI)
8857 11:44:48.967090 u2DelayCellOfst[3]=7 cells (2 PI)
8858 11:44:48.970827 u2DelayCellOfst[4]=10 cells (3 PI)
8859 11:44:48.973928 u2DelayCellOfst[5]=14 cells (4 PI)
8860 11:44:48.977100 u2DelayCellOfst[6]=14 cells (4 PI)
8861 11:44:48.980871 u2DelayCellOfst[7]=7 cells (2 PI)
8862 11:44:48.983883 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8863 11:44:48.987515 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8864 11:44:48.990504 == TX Byte 1 ==
8865 11:44:48.993743 u2DelayCellOfst[8]=0 cells (0 PI)
8866 11:44:48.997011 u2DelayCellOfst[9]=3 cells (1 PI)
8867 11:44:49.000123 u2DelayCellOfst[10]=10 cells (3 PI)
8868 11:44:49.003890 u2DelayCellOfst[11]=3 cells (1 PI)
8869 11:44:49.006970 u2DelayCellOfst[12]=14 cells (4 PI)
8870 11:44:49.010161 u2DelayCellOfst[13]=14 cells (4 PI)
8871 11:44:49.013437 u2DelayCellOfst[14]=17 cells (5 PI)
8872 11:44:49.016544 u2DelayCellOfst[15]=17 cells (5 PI)
8873 11:44:49.020021 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8874 11:44:49.023161 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8875 11:44:49.026808 DramC Write-DBI on
8876 11:44:49.026913 ==
8877 11:44:49.029780 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 11:44:49.033408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 11:44:49.033510 ==
8880 11:44:49.033578
8881 11:44:49.033641
8882 11:44:49.036492 TX Vref Scan disable
8883 11:44:49.036594 == TX Byte 0 ==
8884 11:44:49.043122 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8885 11:44:49.043235 == TX Byte 1 ==
8886 11:44:49.049700 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8887 11:44:49.049831 DramC Write-DBI off
8888 11:44:49.049951
8889 11:44:49.050049 [DATLAT]
8890 11:44:49.052808 Freq=1600, CH1 RK1
8891 11:44:49.052922
8892 11:44:49.056585 DATLAT Default: 0xf
8893 11:44:49.056701 0, 0xFFFF, sum = 0
8894 11:44:49.059736 1, 0xFFFF, sum = 0
8895 11:44:49.059869 2, 0xFFFF, sum = 0
8896 11:44:49.062887 3, 0xFFFF, sum = 0
8897 11:44:49.063003 4, 0xFFFF, sum = 0
8898 11:44:49.065938 5, 0xFFFF, sum = 0
8899 11:44:49.066055 6, 0xFFFF, sum = 0
8900 11:44:49.069120 7, 0xFFFF, sum = 0
8901 11:44:49.069234 8, 0xFFFF, sum = 0
8902 11:44:49.072411 9, 0xFFFF, sum = 0
8903 11:44:49.072520 10, 0xFFFF, sum = 0
8904 11:44:49.075615 11, 0xFFFF, sum = 0
8905 11:44:49.075745 12, 0xFFFF, sum = 0
8906 11:44:49.079287 13, 0xFFFF, sum = 0
8907 11:44:49.079400 14, 0x0, sum = 1
8908 11:44:49.082448 15, 0x0, sum = 2
8909 11:44:49.082561 16, 0x0, sum = 3
8910 11:44:49.085627 17, 0x0, sum = 4
8911 11:44:49.085759 best_step = 15
8912 11:44:49.085858
8913 11:44:49.085970 ==
8914 11:44:49.089329 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 11:44:49.095480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 11:44:49.095595 ==
8917 11:44:49.095692 RX Vref Scan: 0
8918 11:44:49.095783
8919 11:44:49.099186 RX Vref 0 -> 0, step: 1
8920 11:44:49.099270
8921 11:44:49.102229 RX Delay 19 -> 252, step: 4
8922 11:44:49.105362 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8923 11:44:49.109013 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8924 11:44:49.115137 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8925 11:44:49.118386 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8926 11:44:49.122115 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8927 11:44:49.125075 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8928 11:44:49.128643 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8929 11:44:49.135189 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8930 11:44:49.138134 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8931 11:44:49.141777 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8932 11:44:49.144757 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8933 11:44:49.151384 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8934 11:44:49.154741 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8935 11:44:49.157974 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8936 11:44:49.161166 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8937 11:44:49.164473 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8938 11:44:49.167556 ==
8939 11:44:49.170692 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 11:44:49.174393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 11:44:49.174511 ==
8942 11:44:49.174610 DQS Delay:
8943 11:44:49.177506 DQS0 = 0, DQS1 = 0
8944 11:44:49.177609 DQM Delay:
8945 11:44:49.180546 DQM0 = 131, DQM1 = 128
8946 11:44:49.180646 DQ Delay:
8947 11:44:49.183814 DQ0 =134, DQ1 =128, DQ2 =120, DQ3 =128
8948 11:44:49.187673 DQ4 =130, DQ5 =144, DQ6 =140, DQ7 =128
8949 11:44:49.190827 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8950 11:44:49.194025 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8951 11:44:49.194131
8952 11:44:49.194224
8953 11:44:49.197072
8954 11:44:49.197177 [DramC_TX_OE_Calibration] TA2
8955 11:44:49.200304 Original DQ_B0 (3 6) =30, OEN = 27
8956 11:44:49.203462 Original DQ_B1 (3 6) =30, OEN = 27
8957 11:44:49.207217 24, 0x0, End_B0=24 End_B1=24
8958 11:44:49.210469 25, 0x0, End_B0=25 End_B1=25
8959 11:44:49.213544 26, 0x0, End_B0=26 End_B1=26
8960 11:44:49.213647 27, 0x0, End_B0=27 End_B1=27
8961 11:44:49.216698 28, 0x0, End_B0=28 End_B1=28
8962 11:44:49.219928 29, 0x0, End_B0=29 End_B1=29
8963 11:44:49.223660 30, 0x0, End_B0=30 End_B1=30
8964 11:44:49.226869 31, 0x4141, End_B0=30 End_B1=30
8965 11:44:49.226971 Byte0 end_step=30 best_step=27
8966 11:44:49.229937 Byte1 end_step=30 best_step=27
8967 11:44:49.233499 Byte0 TX OE(2T, 0.5T) = (3, 3)
8968 11:44:49.236601 Byte1 TX OE(2T, 0.5T) = (3, 3)
8969 11:44:49.236716
8970 11:44:49.236824
8971 11:44:49.246629 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8972 11:44:49.246761 CH1 RK1: MR19=303, MR18=F1C
8973 11:44:49.253277 CH1_RK1: MR19=0x303, MR18=0xF1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8974 11:44:49.256177 [RxdqsGatingPostProcess] freq 1600
8975 11:44:49.262583 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8976 11:44:49.266306 best DQS0 dly(2T, 0.5T) = (1, 1)
8977 11:44:49.269351 best DQS1 dly(2T, 0.5T) = (1, 1)
8978 11:44:49.272473 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8979 11:44:49.276202 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8980 11:44:49.276333 best DQS0 dly(2T, 0.5T) = (1, 1)
8981 11:44:49.279057 best DQS1 dly(2T, 0.5T) = (1, 1)
8982 11:44:49.282226 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8983 11:44:49.286072 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8984 11:44:49.289156 Pre-setting of DQS Precalculation
8985 11:44:49.295429 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8986 11:44:49.302099 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8987 11:44:49.308907 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8988 11:44:49.308988
8989 11:44:49.309054
8990 11:44:49.312085 [Calibration Summary] 3200 Mbps
8991 11:44:49.312157 CH 0, Rank 0
8992 11:44:49.315245 SW Impedance : PASS
8993 11:44:49.318405 DUTY Scan : NO K
8994 11:44:49.318505 ZQ Calibration : PASS
8995 11:44:49.322204 Jitter Meter : NO K
8996 11:44:49.325378 CBT Training : PASS
8997 11:44:49.325460 Write leveling : PASS
8998 11:44:49.328453 RX DQS gating : PASS
8999 11:44:49.331587 RX DQ/DQS(RDDQC) : PASS
9000 11:44:49.331686 TX DQ/DQS : PASS
9001 11:44:49.335257 RX DATLAT : PASS
9002 11:44:49.338163 RX DQ/DQS(Engine): PASS
9003 11:44:49.338277 TX OE : PASS
9004 11:44:49.341882 All Pass.
9005 11:44:49.341969
9006 11:44:49.342039 CH 0, Rank 1
9007 11:44:49.344768 SW Impedance : PASS
9008 11:44:49.344865 DUTY Scan : NO K
9009 11:44:49.347921 ZQ Calibration : PASS
9010 11:44:49.351617 Jitter Meter : NO K
9011 11:44:49.351727 CBT Training : PASS
9012 11:44:49.354657 Write leveling : PASS
9013 11:44:49.358324 RX DQS gating : PASS
9014 11:44:49.358432 RX DQ/DQS(RDDQC) : PASS
9015 11:44:49.361349 TX DQ/DQS : PASS
9016 11:44:49.364328 RX DATLAT : PASS
9017 11:44:49.364433 RX DQ/DQS(Engine): PASS
9018 11:44:49.367768 TX OE : PASS
9019 11:44:49.367865 All Pass.
9020 11:44:49.367957
9021 11:44:49.371523 CH 1, Rank 0
9022 11:44:49.371617 SW Impedance : PASS
9023 11:44:49.374660 DUTY Scan : NO K
9024 11:44:49.377880 ZQ Calibration : PASS
9025 11:44:49.378002 Jitter Meter : NO K
9026 11:44:49.381088 CBT Training : PASS
9027 11:44:49.384767 Write leveling : PASS
9028 11:44:49.384851 RX DQS gating : PASS
9029 11:44:49.388016 RX DQ/DQS(RDDQC) : PASS
9030 11:44:49.388116 TX DQ/DQS : PASS
9031 11:44:49.391267 RX DATLAT : PASS
9032 11:44:49.394401 RX DQ/DQS(Engine): PASS
9033 11:44:49.394486 TX OE : PASS
9034 11:44:49.397529 All Pass.
9035 11:44:49.397613
9036 11:44:49.397679 CH 1, Rank 1
9037 11:44:49.400689 SW Impedance : PASS
9038 11:44:49.400772 DUTY Scan : NO K
9039 11:44:49.404451 ZQ Calibration : PASS
9040 11:44:49.407424 Jitter Meter : NO K
9041 11:44:49.407507 CBT Training : PASS
9042 11:44:49.410926 Write leveling : PASS
9043 11:44:49.414151 RX DQS gating : PASS
9044 11:44:49.414265 RX DQ/DQS(RDDQC) : PASS
9045 11:44:49.417168 TX DQ/DQS : PASS
9046 11:44:49.420402 RX DATLAT : PASS
9047 11:44:49.420521 RX DQ/DQS(Engine): PASS
9048 11:44:49.424174 TX OE : PASS
9049 11:44:49.424277 All Pass.
9050 11:44:49.424370
9051 11:44:49.427240 DramC Write-DBI on
9052 11:44:49.430277 PER_BANK_REFRESH: Hybrid Mode
9053 11:44:49.430361 TX_TRACKING: ON
9054 11:44:49.440236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9055 11:44:49.446954 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9056 11:44:49.453706 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9057 11:44:49.460312 [FAST_K] Save calibration result to emmc
9058 11:44:49.460427 sync common calibartion params.
9059 11:44:49.463177 sync cbt_mode0:1, 1:1
9060 11:44:49.466674 dram_init: ddr_geometry: 2
9061 11:44:49.469676 dram_init: ddr_geometry: 2
9062 11:44:49.469784 dram_init: ddr_geometry: 2
9063 11:44:49.473147 0:dram_rank_size:100000000
9064 11:44:49.476278 1:dram_rank_size:100000000
9065 11:44:49.479466 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9066 11:44:49.483332 DFS_SHUFFLE_HW_MODE: ON
9067 11:44:49.486550 dramc_set_vcore_voltage set vcore to 725000
9068 11:44:49.489662 Read voltage for 1600, 0
9069 11:44:49.489765 Vio18 = 0
9070 11:44:49.492825 Vcore = 725000
9071 11:44:49.492940 Vdram = 0
9072 11:44:49.493044 Vddq = 0
9073 11:44:49.495927 Vmddr = 0
9074 11:44:49.496049 switch to 3200 Mbps bootup
9075 11:44:49.499686 [DramcRunTimeConfig]
9076 11:44:49.499804 PHYPLL
9077 11:44:49.502715 DPM_CONTROL_AFTERK: ON
9078 11:44:49.502821 PER_BANK_REFRESH: ON
9079 11:44:49.505902 REFRESH_OVERHEAD_REDUCTION: ON
9080 11:44:49.509474 CMD_PICG_NEW_MODE: OFF
9081 11:44:49.509590 XRTWTW_NEW_MODE: ON
9082 11:44:49.512533 XRTRTR_NEW_MODE: ON
9083 11:44:49.512651 TX_TRACKING: ON
9084 11:44:49.516410 RDSEL_TRACKING: OFF
9085 11:44:49.518931 DQS Precalculation for DVFS: ON
9086 11:44:49.519049 RX_TRACKING: OFF
9087 11:44:49.522645 HW_GATING DBG: ON
9088 11:44:49.522749 ZQCS_ENABLE_LP4: ON
9089 11:44:49.525758 RX_PICG_NEW_MODE: ON
9090 11:44:49.525841 TX_PICG_NEW_MODE: ON
9091 11:44:49.528933 ENABLE_RX_DCM_DPHY: ON
9092 11:44:49.532746 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9093 11:44:49.535798 DUMMY_READ_FOR_TRACKING: OFF
9094 11:44:49.535882 !!! SPM_CONTROL_AFTERK: OFF
9095 11:44:49.538916 !!! SPM could not control APHY
9096 11:44:49.542059 IMPEDANCE_TRACKING: ON
9097 11:44:49.542143 TEMP_SENSOR: ON
9098 11:44:49.545929 HW_SAVE_FOR_SR: OFF
9099 11:44:49.548981 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9100 11:44:49.552081 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9101 11:44:49.555585 Read ODT Tracking: ON
9102 11:44:49.555695 Refresh Rate DeBounce: ON
9103 11:44:49.558511 DFS_NO_QUEUE_FLUSH: ON
9104 11:44:49.562250 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9105 11:44:49.565418 ENABLE_DFS_RUNTIME_MRW: OFF
9106 11:44:49.565522 DDR_RESERVE_NEW_MODE: ON
9107 11:44:49.568312 MR_CBT_SWITCH_FREQ: ON
9108 11:44:49.571772 =========================
9109 11:44:49.589294 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9110 11:44:49.592427 dram_init: ddr_geometry: 2
9111 11:44:49.611241 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9112 11:44:49.614346 dram_init: dram init end (result: 0)
9113 11:44:49.621048 DRAM-K: Full calibration passed in 24417 msecs
9114 11:44:49.624189 MRC: failed to locate region type 0.
9115 11:44:49.624295 DRAM rank0 size:0x100000000,
9116 11:44:49.627404 DRAM rank1 size=0x100000000
9117 11:44:49.637483 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9118 11:44:49.643797 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9119 11:44:49.650812 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9120 11:44:49.660792 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9121 11:44:49.660908 DRAM rank0 size:0x100000000,
9122 11:44:49.663648 DRAM rank1 size=0x100000000
9123 11:44:49.663721 CBMEM:
9124 11:44:49.667106 IMD: root @ 0xfffff000 254 entries.
9125 11:44:49.670373 IMD: root @ 0xffffec00 62 entries.
9126 11:44:49.673528 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9127 11:44:49.680062 WARNING: RO_VPD is uninitialized or empty.
9128 11:44:49.683499 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9129 11:44:49.691051 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9130 11:44:49.703491 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9131 11:44:49.715421 BS: romstage times (exec / console): total (unknown) / 23952 ms
9132 11:44:49.715517
9133 11:44:49.715587
9134 11:44:49.725337 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9135 11:44:49.728319 ARM64: Exception handlers installed.
9136 11:44:49.731526 ARM64: Testing exception
9137 11:44:49.735302 ARM64: Done test exception
9138 11:44:49.735424 Enumerating buses...
9139 11:44:49.738477 Show all devs... Before device enumeration.
9140 11:44:49.741686 Root Device: enabled 1
9141 11:44:49.744823 CPU_CLUSTER: 0: enabled 1
9142 11:44:49.744908 CPU: 00: enabled 1
9143 11:44:49.748076 Compare with tree...
9144 11:44:49.748166 Root Device: enabled 1
9145 11:44:49.751185 CPU_CLUSTER: 0: enabled 1
9146 11:44:49.755005 CPU: 00: enabled 1
9147 11:44:49.755103 Root Device scanning...
9148 11:44:49.758177 scan_static_bus for Root Device
9149 11:44:49.761378 CPU_CLUSTER: 0 enabled
9150 11:44:49.764462 scan_static_bus for Root Device done
9151 11:44:49.767566 scan_bus: bus Root Device finished in 8 msecs
9152 11:44:49.767669 done
9153 11:44:49.774295 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9154 11:44:49.777909 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9155 11:44:49.784044 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9156 11:44:49.790505 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9157 11:44:49.790592 Allocating resources...
9158 11:44:49.794027 Reading resources...
9159 11:44:49.797442 Root Device read_resources bus 0 link: 0
9160 11:44:49.800728 DRAM rank0 size:0x100000000,
9161 11:44:49.800836 DRAM rank1 size=0x100000000
9162 11:44:49.807039 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9163 11:44:49.807158 CPU: 00 missing read_resources
9164 11:44:49.813739 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9165 11:44:49.816955 Root Device read_resources bus 0 link: 0 done
9166 11:44:49.820634 Done reading resources.
9167 11:44:49.823806 Show resources in subtree (Root Device)...After reading.
9168 11:44:49.826744 Root Device child on link 0 CPU_CLUSTER: 0
9169 11:44:49.830597 CPU_CLUSTER: 0 child on link 0 CPU: 00
9170 11:44:49.839958 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9171 11:44:49.840055 CPU: 00
9172 11:44:49.846783 Root Device assign_resources, bus 0 link: 0
9173 11:44:49.849882 CPU_CLUSTER: 0 missing set_resources
9174 11:44:49.853662 Root Device assign_resources, bus 0 link: 0 done
9175 11:44:49.856703 Done setting resources.
9176 11:44:49.859833 Show resources in subtree (Root Device)...After assigning values.
9177 11:44:49.863006 Root Device child on link 0 CPU_CLUSTER: 0
9178 11:44:49.869987 CPU_CLUSTER: 0 child on link 0 CPU: 00
9179 11:44:49.876157 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9180 11:44:49.879352 CPU: 00
9181 11:44:49.879458 Done allocating resources.
9182 11:44:49.886072 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9183 11:44:49.886182 Enabling resources...
9184 11:44:49.889679 done.
9185 11:44:49.892732 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9186 11:44:49.896222 Initializing devices...
9187 11:44:49.896305 Root Device init
9188 11:44:49.899356 init hardware done!
9189 11:44:49.899433 0x00000018: ctrlr->caps
9190 11:44:49.902947 52.000 MHz: ctrlr->f_max
9191 11:44:49.905924 0.400 MHz: ctrlr->f_min
9192 11:44:49.909342 0x40ff8080: ctrlr->voltages
9193 11:44:49.909430 sclk: 390625
9194 11:44:49.909498 Bus Width = 1
9195 11:44:49.912780 sclk: 390625
9196 11:44:49.912867 Bus Width = 1
9197 11:44:49.915825 Early init status = 3
9198 11:44:49.918953 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9199 11:44:49.922733 in-header: 03 fc 00 00 01 00 00 00
9200 11:44:49.925846 in-data: 00
9201 11:44:49.928897 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9202 11:44:49.933705 in-header: 03 fd 00 00 00 00 00 00
9203 11:44:49.937016 in-data:
9204 11:44:49.940726 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9205 11:44:49.943910 in-header: 03 fc 00 00 01 00 00 00
9206 11:44:49.947056 in-data: 00
9207 11:44:49.950728 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9208 11:44:49.955105 in-header: 03 fd 00 00 00 00 00 00
9209 11:44:49.958235 in-data:
9210 11:44:49.962067 [SSUSB] Setting up USB HOST controller...
9211 11:44:49.965136 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9212 11:44:49.968391 [SSUSB] phy power-on done.
9213 11:44:49.971364 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9214 11:44:49.978130 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9215 11:44:49.981289 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9216 11:44:49.987954 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9217 11:44:49.994759 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9218 11:44:50.001270 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9219 11:44:50.008005 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9220 11:44:50.014629 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9221 11:44:50.017626 SPM: binary array size = 0x9dc
9222 11:44:50.021023 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9223 11:44:50.027999 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9224 11:44:50.034351 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9225 11:44:50.041238 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9226 11:44:50.044364 configure_display: Starting display init
9227 11:44:50.078599 anx7625_power_on_init: Init interface.
9228 11:44:50.081786 anx7625_disable_pd_protocol: Disabled PD feature.
9229 11:44:50.084955 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9230 11:44:50.112567 anx7625_start_dp_work: Secure OCM version=00
9231 11:44:50.116050 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9232 11:44:50.131090 sp_tx_get_edid_block: EDID Block = 1
9233 11:44:50.233691 Extracted contents:
9234 11:44:50.236652 header: 00 ff ff ff ff ff ff 00
9235 11:44:50.240050 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9236 11:44:50.243177 version: 01 04
9237 11:44:50.246873 basic params: 95 1f 11 78 0a
9238 11:44:50.249849 chroma info: 76 90 94 55 54 90 27 21 50 54
9239 11:44:50.253007 established: 00 00 00
9240 11:44:50.259895 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9241 11:44:50.266444 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9242 11:44:50.269526 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9243 11:44:50.276580 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9244 11:44:50.282883 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9245 11:44:50.286115 extensions: 00
9246 11:44:50.286226 checksum: fb
9247 11:44:50.286325
9248 11:44:50.289228 Manufacturer: IVO Model 57d Serial Number 0
9249 11:44:50.293075 Made week 0 of 2020
9250 11:44:50.296098 EDID version: 1.4
9251 11:44:50.296216 Digital display
9252 11:44:50.299298 6 bits per primary color channel
9253 11:44:50.299435 DisplayPort interface
9254 11:44:50.302473 Maximum image size: 31 cm x 17 cm
9255 11:44:50.306293 Gamma: 220%
9256 11:44:50.306418 Check DPMS levels
9257 11:44:50.312337 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9258 11:44:50.315914 First detailed timing is preferred timing
9259 11:44:50.316028 Established timings supported:
9260 11:44:50.318973 Standard timings supported:
9261 11:44:50.322561 Detailed timings
9262 11:44:50.325586 Hex of detail: 383680a07038204018303c0035ae10000019
9263 11:44:50.332302 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9264 11:44:50.335864 0780 0798 07c8 0820 hborder 0
9265 11:44:50.338740 0438 043b 0447 0458 vborder 0
9266 11:44:50.342410 -hsync -vsync
9267 11:44:50.342521 Did detailed timing
9268 11:44:50.349036 Hex of detail: 000000000000000000000000000000000000
9269 11:44:50.352193 Manufacturer-specified data, tag 0
9270 11:44:50.355391 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9271 11:44:50.358555 ASCII string: InfoVision
9272 11:44:50.361769 Hex of detail: 000000fe00523134304e574635205248200a
9273 11:44:50.365471 ASCII string: R140NWF5 RH
9274 11:44:50.365578 Checksum
9275 11:44:50.368750 Checksum: 0xfb (valid)
9276 11:44:50.371987 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9277 11:44:50.375152 DSI data_rate: 832800000 bps
9278 11:44:50.381810 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9279 11:44:50.385023 anx7625_parse_edid: pixelclock(138800).
9280 11:44:50.388049 hactive(1920), hsync(48), hfp(24), hbp(88)
9281 11:44:50.391312 vactive(1080), vsync(12), vfp(3), vbp(17)
9282 11:44:50.394526 anx7625_dsi_config: config dsi.
9283 11:44:50.401421 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9284 11:44:50.415725 anx7625_dsi_config: success to config DSI
9285 11:44:50.418978 anx7625_dp_start: MIPI phy setup OK.
9286 11:44:50.422069 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9287 11:44:50.425615 mtk_ddp_mode_set invalid vrefresh 60
9288 11:44:50.428452 main_disp_path_setup
9289 11:44:50.428582 ovl_layer_smi_id_en
9290 11:44:50.431805 ovl_layer_smi_id_en
9291 11:44:50.431927 ccorr_config
9292 11:44:50.432039 aal_config
9293 11:44:50.435317 gamma_config
9294 11:44:50.435411 postmask_config
9295 11:44:50.438155 dither_config
9296 11:44:50.441696 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9297 11:44:50.448666 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9298 11:44:50.451664 Root Device init finished in 551 msecs
9299 11:44:50.455165 CPU_CLUSTER: 0 init
9300 11:44:50.461907 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9301 11:44:50.468331 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9302 11:44:50.468415 APU_MBOX 0x190000b0 = 0x10001
9303 11:44:50.471503 APU_MBOX 0x190001b0 = 0x10001
9304 11:44:50.474656 APU_MBOX 0x190005b0 = 0x10001
9305 11:44:50.477861 APU_MBOX 0x190006b0 = 0x10001
9306 11:44:50.484888 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9307 11:44:50.494427 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9308 11:44:50.506927 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9309 11:44:50.513202 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9310 11:44:50.525197 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9311 11:44:50.534451 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9312 11:44:50.537335 CPU_CLUSTER: 0 init finished in 81 msecs
9313 11:44:50.541015 Devices initialized
9314 11:44:50.543986 Show all devs... After init.
9315 11:44:50.544129 Root Device: enabled 1
9316 11:44:50.547629 CPU_CLUSTER: 0: enabled 1
9317 11:44:50.550572 CPU: 00: enabled 1
9318 11:44:50.554209 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9319 11:44:50.557178 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9320 11:44:50.560756 ELOG: NV offset 0x57f000 size 0x1000
9321 11:44:50.567175 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9322 11:44:50.574220 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9323 11:44:50.577207 ELOG: Event(17) added with size 13 at 2023-06-15 11:44:50 UTC
9324 11:44:50.583626 out: cmd=0x121: 03 db 21 01 00 00 00 00
9325 11:44:50.587386 in-header: 03 34 00 00 2c 00 00 00
9326 11:44:50.596789 in-data: 2b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9327 11:44:50.603649 ELOG: Event(A1) added with size 10 at 2023-06-15 11:44:50 UTC
9328 11:44:50.610416 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9329 11:44:50.616766 ELOG: Event(A0) added with size 9 at 2023-06-15 11:44:50 UTC
9330 11:44:50.623114 ELOG: Event(16) added with size 11 at 2023-06-15 11:44:50 UTC
9331 11:44:50.697232 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9332 11:44:50.700385 elog_add_boot_reason: Logged dev mode boot
9333 11:44:50.706661 BS: BS_POST_DEVICE entry times (exec / console): 72 / 74 ms
9334 11:44:50.706748 Finalize devices...
9335 11:44:50.710492 Devices finalized
9336 11:44:50.713645 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9337 11:44:50.716813 Writing coreboot table at 0xffe64000
9338 11:44:50.723194 0. 000000000010a000-0000000000113fff: RAMSTAGE
9339 11:44:50.726847 1. 0000000040000000-00000000400fffff: RAM
9340 11:44:50.729997 2. 0000000040100000-000000004032afff: RAMSTAGE
9341 11:44:50.733109 3. 000000004032b000-00000000545fffff: RAM
9342 11:44:50.736385 4. 0000000054600000-000000005465ffff: BL31
9343 11:44:50.742745 5. 0000000054660000-00000000ffe63fff: RAM
9344 11:44:50.746440 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9345 11:44:50.749480 7. 0000000100000000-000000023fffffff: RAM
9346 11:44:50.753157 Passing 5 GPIOs to payload:
9347 11:44:50.756324 NAME | PORT | POLARITY | VALUE
9348 11:44:50.762969 EC in RW | 0x000000aa | low | undefined
9349 11:44:50.765997 EC interrupt | 0x00000005 | low | undefined
9350 11:44:50.772534 TPM interrupt | 0x000000ab | high | undefined
9351 11:44:50.775642 SD card detect | 0x00000011 | high | undefined
9352 11:44:50.782143 speaker enable | 0x00000093 | high | undefined
9353 11:44:50.786117 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9354 11:44:50.789358 in-header: 03 f9 00 00 02 00 00 00
9355 11:44:50.789443 in-data: 02 00
9356 11:44:50.792555 ADC[4]: Raw value=902586 ID=7
9357 11:44:50.795757 ADC[3]: Raw value=213546 ID=1
9358 11:44:50.795852 RAM Code: 0x71
9359 11:44:50.798853 ADC[6]: Raw value=75000 ID=0
9360 11:44:50.802012 ADC[5]: Raw value=213546 ID=1
9361 11:44:50.802089 SKU Code: 0x1
9362 11:44:50.808913 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 951a
9363 11:44:50.812087 coreboot table: 964 bytes.
9364 11:44:50.815142 IMD ROOT 0. 0xfffff000 0x00001000
9365 11:44:50.818841 IMD SMALL 1. 0xffffe000 0x00001000
9366 11:44:50.822044 RO MCACHE 2. 0xffffc000 0x00001104
9367 11:44:50.825345 CONSOLE 3. 0xfff7c000 0x00080000
9368 11:44:50.828503 FMAP 4. 0xfff7b000 0x00000452
9369 11:44:50.831737 TIME STAMP 5. 0xfff7a000 0x00000910
9370 11:44:50.834884 VBOOT WORK 6. 0xfff66000 0x00014000
9371 11:44:50.838658 RAMOOPS 7. 0xffe66000 0x00100000
9372 11:44:50.841764 COREBOOT 8. 0xffe64000 0x00002000
9373 11:44:50.841853 IMD small region:
9374 11:44:50.844885 IMD ROOT 0. 0xffffec00 0x00000400
9375 11:44:50.847942 VPD 1. 0xffffeba0 0x0000004c
9376 11:44:50.851469 MMC STATUS 2. 0xffffeb80 0x00000004
9377 11:44:50.858335 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9378 11:44:50.858442 Probing TPM: done!
9379 11:44:50.865056 Connected to device vid:did:rid of 1ae0:0028:00
9380 11:44:50.871589 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9381 11:44:50.878285 Initialized TPM device CR50 revision 0
9382 11:44:50.878397 Checking cr50 for pending updates
9383 11:44:50.884728 Reading cr50 TPM mode
9384 11:44:50.893146 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9385 11:44:50.900162 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9386 11:44:50.940159 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9387 11:44:50.943256 Checking segment from ROM address 0x40100000
9388 11:44:50.946521 Checking segment from ROM address 0x4010001c
9389 11:44:50.953493 Loading segment from ROM address 0x40100000
9390 11:44:50.953588 code (compression=0)
9391 11:44:50.963203 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9392 11:44:50.969564 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9393 11:44:50.969651 it's not compressed!
9394 11:44:50.976229 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9395 11:44:50.982825 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9396 11:44:51.001528 Loading segment from ROM address 0x4010001c
9397 11:44:51.001670 Entry Point 0x80000000
9398 11:44:51.004714 Loaded segments
9399 11:44:51.008458 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9400 11:44:51.014778 Jumping to boot code at 0x80000000(0xffe64000)
9401 11:44:51.021247 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9402 11:44:51.027707 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9403 11:44:51.035959 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9404 11:44:51.039219 Checking segment from ROM address 0x40100000
9405 11:44:51.042315 Checking segment from ROM address 0x4010001c
9406 11:44:51.049104 Loading segment from ROM address 0x40100000
9407 11:44:51.049214 code (compression=1)
9408 11:44:51.056023 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9409 11:44:51.065962 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9410 11:44:51.066057 using LZMA
9411 11:44:51.074137 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9412 11:44:51.080558 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9413 11:44:51.084171 Loading segment from ROM address 0x4010001c
9414 11:44:51.084293 Entry Point 0x54601000
9415 11:44:51.087616 Loaded segments
9416 11:44:51.090644 NOTICE: MT8192 bl31_setup
9417 11:44:51.098139 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9418 11:44:51.101042 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9419 11:44:51.104577 WARNING: region 0:
9420 11:44:51.107444 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9421 11:44:51.107529 WARNING: region 1:
9422 11:44:51.114154 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9423 11:44:51.117861 WARNING: region 2:
9424 11:44:51.121014 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9425 11:44:51.124155 WARNING: region 3:
9426 11:44:51.127812 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9427 11:44:51.130840 WARNING: region 4:
9428 11:44:51.137417 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9429 11:44:51.137506 WARNING: region 5:
9430 11:44:51.141216 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9431 11:44:51.144441 WARNING: region 6:
9432 11:44:51.147582 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 11:44:51.150671 WARNING: region 7:
9434 11:44:51.154450 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 11:44:51.160825 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9436 11:44:51.164498 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9437 11:44:51.167612 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9438 11:44:51.174421 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9439 11:44:51.177668 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9440 11:44:51.184058 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9441 11:44:51.187139 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9442 11:44:51.191034 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9443 11:44:51.197058 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9444 11:44:51.200629 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9445 11:44:51.203609 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9446 11:44:51.210578 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9447 11:44:51.213658 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9448 11:44:51.220293 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9449 11:44:51.223414 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9450 11:44:51.227169 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9451 11:44:51.233961 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9452 11:44:51.237142 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9453 11:44:51.240392 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9454 11:44:51.247399 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9455 11:44:51.250494 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9456 11:44:51.256877 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9457 11:44:51.259974 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9458 11:44:51.263723 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9459 11:44:51.270656 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9460 11:44:51.273695 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9461 11:44:51.280504 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9462 11:44:51.283621 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9463 11:44:51.286762 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9464 11:44:51.293564 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9465 11:44:51.297103 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9466 11:44:51.303401 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9467 11:44:51.307015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9468 11:44:51.309888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9469 11:44:51.313382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9470 11:44:51.320087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9471 11:44:51.323607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9472 11:44:51.327133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9473 11:44:51.329824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9474 11:44:51.336825 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9475 11:44:51.339888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9476 11:44:51.343097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9477 11:44:51.346877 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9478 11:44:51.353040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9479 11:44:51.356758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9480 11:44:51.359949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9481 11:44:51.366296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9482 11:44:51.369414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9483 11:44:51.373062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9484 11:44:51.379838 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9485 11:44:51.382995 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9486 11:44:51.386167 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9487 11:44:51.392561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9488 11:44:51.395786 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9489 11:44:51.402544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9490 11:44:51.406310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9491 11:44:51.412610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9492 11:44:51.415770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9493 11:44:51.422729 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9494 11:44:51.425632 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9495 11:44:51.429059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9496 11:44:51.436006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9497 11:44:51.438940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9498 11:44:51.445718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9499 11:44:51.448811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9500 11:44:51.455665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9501 11:44:51.458757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9502 11:44:51.465950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9503 11:44:51.469094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9504 11:44:51.472207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9505 11:44:51.479217 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9506 11:44:51.482166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9507 11:44:51.489132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9508 11:44:51.492286 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9509 11:44:51.498527 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9510 11:44:51.502277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9511 11:44:51.508519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9512 11:44:51.512222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9513 11:44:51.515452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9514 11:44:51.521792 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9515 11:44:51.525440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9516 11:44:51.531923 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9517 11:44:51.534931 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9518 11:44:51.541487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9519 11:44:51.545043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9520 11:44:51.551459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9521 11:44:51.555065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9522 11:44:51.558176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9523 11:44:51.564626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9524 11:44:51.568439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9525 11:44:51.575204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9526 11:44:51.578311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9527 11:44:51.584630 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9528 11:44:51.588325 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9529 11:44:51.594444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9530 11:44:51.598280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9531 11:44:51.601463 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9532 11:44:51.604566 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9533 11:44:51.611334 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9534 11:44:51.614481 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9535 11:44:51.618251 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9536 11:44:51.625051 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9537 11:44:51.628153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9538 11:44:51.631412 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9539 11:44:51.638198 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9540 11:44:51.641125 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9541 11:44:51.647841 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9542 11:44:51.651272 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9543 11:44:51.654573 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9544 11:44:51.661100 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9545 11:44:51.664918 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9546 11:44:51.671068 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9547 11:44:51.674825 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9548 11:44:51.678049 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9549 11:44:51.684937 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9550 11:44:51.688170 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9551 11:44:51.691278 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9552 11:44:51.698120 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9553 11:44:51.701319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9554 11:44:51.704610 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9555 11:44:51.711476 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9556 11:44:51.714560 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9557 11:44:51.717716 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9558 11:44:51.721545 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9559 11:44:51.727893 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9560 11:44:51.730988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9561 11:44:51.734675 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9562 11:44:51.741485 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9563 11:44:51.744516 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9564 11:44:51.750963 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9565 11:44:51.754594 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9566 11:44:51.757468 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9567 11:44:51.763921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9568 11:44:51.767470 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9569 11:44:51.774502 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9570 11:44:51.777620 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9571 11:44:51.780685 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9572 11:44:51.787690 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9573 11:44:51.790871 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9574 11:44:51.797065 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9575 11:44:51.800817 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9576 11:44:51.803989 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9577 11:44:51.810375 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9578 11:44:51.813626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9579 11:44:51.820462 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9580 11:44:51.823622 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9581 11:44:51.826815 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9582 11:44:51.833197 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9583 11:44:51.836995 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9584 11:44:51.843160 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9585 11:44:51.846430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9586 11:44:51.850212 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9587 11:44:51.856838 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9588 11:44:51.859733 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9589 11:44:51.866697 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9590 11:44:51.869654 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9591 11:44:51.873024 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9592 11:44:51.880053 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9593 11:44:51.882989 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9594 11:44:51.889828 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9595 11:44:51.892874 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9596 11:44:51.896592 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9597 11:44:51.903273 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9598 11:44:51.906383 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9599 11:44:51.912779 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9600 11:44:51.915864 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9601 11:44:51.919647 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9602 11:44:51.925981 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9603 11:44:51.929063 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9604 11:44:51.935956 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9605 11:44:51.939221 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9606 11:44:51.942367 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9607 11:44:51.949069 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9608 11:44:51.952315 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9609 11:44:51.959288 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9610 11:44:51.962438 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9611 11:44:51.965447 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9612 11:44:51.972291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9613 11:44:51.975285 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9614 11:44:51.982218 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9615 11:44:51.985598 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9616 11:44:51.988507 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9617 11:44:51.995542 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9618 11:44:51.998678 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9619 11:44:52.004881 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9620 11:44:52.008569 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9621 11:44:52.011681 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9622 11:44:52.018133 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9623 11:44:52.021890 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9624 11:44:52.027978 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9625 11:44:52.031124 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9626 11:44:52.038093 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9627 11:44:52.041471 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9628 11:44:52.044513 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9629 11:44:52.050969 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9630 11:44:52.054087 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9631 11:44:52.061044 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9632 11:44:52.064155 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9633 11:44:52.070517 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9634 11:44:52.074346 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9635 11:44:52.077376 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9636 11:44:52.083885 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9637 11:44:52.087520 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9638 11:44:52.093890 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9639 11:44:52.097174 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9640 11:44:52.103705 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9641 11:44:52.106775 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9642 11:44:52.110491 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9643 11:44:52.116710 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9644 11:44:52.120470 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9645 11:44:52.126864 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9646 11:44:52.129895 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9647 11:44:52.136578 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9648 11:44:52.139613 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9649 11:44:52.143367 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9650 11:44:52.149674 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9651 11:44:52.153451 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9652 11:44:52.159639 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9653 11:44:52.162887 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9654 11:44:52.169857 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9655 11:44:52.172921 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9656 11:44:52.176027 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9657 11:44:52.182801 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9658 11:44:52.185913 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9659 11:44:52.192570 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9660 11:44:52.195581 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9661 11:44:52.202644 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9662 11:44:52.205509 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9663 11:44:52.209232 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9664 11:44:52.215392 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9665 11:44:52.218915 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9666 11:44:52.222069 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9667 11:44:52.225348 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9668 11:44:52.232298 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9669 11:44:52.235394 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9670 11:44:52.238384 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9671 11:44:52.245356 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9672 11:44:52.248540 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9673 11:44:52.251828 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9674 11:44:52.258095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9675 11:44:52.262004 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9676 11:44:52.268237 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9677 11:44:52.271394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9678 11:44:52.274515 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9679 11:44:52.281609 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9680 11:44:52.284520 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9681 11:44:52.290906 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9682 11:44:52.294587 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9683 11:44:52.297523 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9684 11:44:52.304261 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9685 11:44:52.307649 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9686 11:44:52.311366 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9687 11:44:52.317316 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9688 11:44:52.320920 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9689 11:44:52.327669 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9690 11:44:52.330833 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9691 11:44:52.333987 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9692 11:44:52.340472 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9693 11:44:52.343927 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9694 11:44:52.347136 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9695 11:44:52.353833 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9696 11:44:52.357026 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9697 11:44:52.363298 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9698 11:44:52.366488 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9699 11:44:52.370348 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9700 11:44:52.376548 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9701 11:44:52.380344 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9702 11:44:52.386567 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9703 11:44:52.389514 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9704 11:44:52.393127 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9705 11:44:52.396322 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9706 11:44:52.403065 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9707 11:44:52.406138 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9708 11:44:52.409724 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9709 11:44:52.412824 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9710 11:44:52.419434 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9711 11:44:52.422367 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9712 11:44:52.425989 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9713 11:44:52.429479 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9714 11:44:52.435713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9715 11:44:52.438825 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9716 11:44:52.442699 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9717 11:44:52.448851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9718 11:44:52.452057 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9719 11:44:52.458505 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9720 11:44:52.462295 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9721 11:44:52.465372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9722 11:44:52.472458 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9723 11:44:52.475517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9724 11:44:52.481758 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9725 11:44:52.485563 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9726 11:44:52.488746 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9727 11:44:52.495023 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9728 11:44:52.498248 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9729 11:44:52.505056 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9730 11:44:52.508154 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9731 11:44:52.514779 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9732 11:44:52.518170 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9733 11:44:52.521185 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9734 11:44:52.527677 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9735 11:44:52.531418 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9736 11:44:52.537500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9737 11:44:52.541051 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9738 11:44:52.547430 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9739 11:44:52.550532 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9740 11:44:52.554244 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9741 11:44:52.560536 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9742 11:44:52.563639 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9743 11:44:52.570586 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9744 11:44:52.573758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9745 11:44:52.580184 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9746 11:44:52.583325 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9747 11:44:52.586568 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9748 11:44:52.593649 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9749 11:44:52.596799 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9750 11:44:52.602959 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9751 11:44:52.606754 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9752 11:44:52.613159 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9753 11:44:52.616234 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9754 11:44:52.619367 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9755 11:44:52.626433 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9756 11:44:52.629385 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9757 11:44:52.636284 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9758 11:44:52.639167 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9759 11:44:52.645846 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9760 11:44:52.648990 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9761 11:44:52.652762 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9762 11:44:52.658839 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9763 11:44:52.662620 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9764 11:44:52.668976 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9765 11:44:52.672156 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9766 11:44:52.675365 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9767 11:44:52.682319 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9768 11:44:52.685493 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9769 11:44:52.691680 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9770 11:44:52.695461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9771 11:44:52.701780 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9772 11:44:52.705273 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9773 11:44:52.708292 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9774 11:44:52.714643 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9775 11:44:52.718381 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9776 11:44:52.724587 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9777 11:44:52.728326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9778 11:44:52.734831 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9779 11:44:52.737810 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9780 11:44:52.741375 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9781 11:44:52.747766 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9782 11:44:52.750805 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9783 11:44:52.757679 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9784 11:44:52.760736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9785 11:44:52.767677 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9786 11:44:52.770835 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9787 11:44:52.773956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9788 11:44:52.780939 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9789 11:44:52.784016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9790 11:44:52.790939 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9791 11:44:52.794119 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9792 11:44:52.800363 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9793 11:44:52.803520 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9794 11:44:52.807207 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9795 11:44:52.813652 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9796 11:44:52.816762 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9797 11:44:52.823914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9798 11:44:52.827031 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9799 11:44:52.833320 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9800 11:44:52.836401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9801 11:44:52.843440 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9802 11:44:52.846397 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9803 11:44:52.849939 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9804 11:44:52.856508 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9805 11:44:52.859530 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9806 11:44:52.866325 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9807 11:44:52.869447 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9808 11:44:52.876380 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9809 11:44:52.879480 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9810 11:44:52.886316 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9811 11:44:52.889437 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9812 11:44:52.892530 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9813 11:44:52.898958 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9814 11:44:52.902781 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9815 11:44:52.909310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9816 11:44:52.912108 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9817 11:44:52.918662 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9818 11:44:52.922374 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9819 11:44:52.928762 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9820 11:44:52.931882 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9821 11:44:52.935635 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9822 11:44:52.941990 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9823 11:44:52.945036 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9824 11:44:52.951564 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9825 11:44:52.955229 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9826 11:44:52.961703 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9827 11:44:52.965187 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9828 11:44:52.971806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9829 11:44:52.974643 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9830 11:44:52.981480 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9831 11:44:52.984614 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9832 11:44:52.987710 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9833 11:44:52.994608 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9834 11:44:52.997707 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9835 11:44:53.004445 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9836 11:44:53.007553 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9837 11:44:53.013909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9838 11:44:53.017487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9839 11:44:53.020509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9840 11:44:53.027356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9841 11:44:53.030487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9842 11:44:53.037452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9843 11:44:53.040681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9844 11:44:53.047171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9845 11:44:53.050297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9846 11:44:53.056816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9847 11:44:53.060378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9848 11:44:53.066991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9849 11:44:53.069905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9850 11:44:53.076936 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9851 11:44:53.079876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9852 11:44:53.086471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9853 11:44:53.090254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9854 11:44:53.096480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9855 11:44:53.099609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9856 11:44:53.106035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9857 11:44:53.109805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9858 11:44:53.115960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9859 11:44:53.119705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9860 11:44:53.125756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9861 11:44:53.129408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9862 11:44:53.135655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9863 11:44:53.139452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9864 11:44:53.145829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9865 11:44:53.152154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9866 11:44:53.156020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9867 11:44:53.162379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9868 11:44:53.165804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9869 11:44:53.168700 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9870 11:44:53.172079 INFO: [APUAPC] vio 0
9871 11:44:53.175630 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9872 11:44:53.182365 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9873 11:44:53.185394 INFO: [APUAPC] D0_APC_0: 0x400510
9874 11:44:53.188747 INFO: [APUAPC] D0_APC_1: 0x0
9875 11:44:53.191758 INFO: [APUAPC] D0_APC_2: 0x1540
9876 11:44:53.191880 INFO: [APUAPC] D0_APC_3: 0x0
9877 11:44:53.198276 INFO: [APUAPC] D1_APC_0: 0xffffffff
9878 11:44:53.202059 INFO: [APUAPC] D1_APC_1: 0xffffffff
9879 11:44:53.205193 INFO: [APUAPC] D1_APC_2: 0x3fffff
9880 11:44:53.205316 INFO: [APUAPC] D1_APC_3: 0x0
9881 11:44:53.208389 INFO: [APUAPC] D2_APC_0: 0xffffffff
9882 11:44:53.215321 INFO: [APUAPC] D2_APC_1: 0xffffffff
9883 11:44:53.218468 INFO: [APUAPC] D2_APC_2: 0x3fffff
9884 11:44:53.218586 INFO: [APUAPC] D2_APC_3: 0x0
9885 11:44:53.221761 INFO: [APUAPC] D3_APC_0: 0xffffffff
9886 11:44:53.224855 INFO: [APUAPC] D3_APC_1: 0xffffffff
9887 11:44:53.227923 INFO: [APUAPC] D3_APC_2: 0x3fffff
9888 11:44:53.231410 INFO: [APUAPC] D3_APC_3: 0x0
9889 11:44:53.234564 INFO: [APUAPC] D4_APC_0: 0xffffffff
9890 11:44:53.238366 INFO: [APUAPC] D4_APC_1: 0xffffffff
9891 11:44:53.241562 INFO: [APUAPC] D4_APC_2: 0x3fffff
9892 11:44:53.244655 INFO: [APUAPC] D4_APC_3: 0x0
9893 11:44:53.248001 INFO: [APUAPC] D5_APC_0: 0xffffffff
9894 11:44:53.251155 INFO: [APUAPC] D5_APC_1: 0xffffffff
9895 11:44:53.254366 INFO: [APUAPC] D5_APC_2: 0x3fffff
9896 11:44:53.258156 INFO: [APUAPC] D5_APC_3: 0x0
9897 11:44:53.261276 INFO: [APUAPC] D6_APC_0: 0xffffffff
9898 11:44:53.264453 INFO: [APUAPC] D6_APC_1: 0xffffffff
9899 11:44:53.267665 INFO: [APUAPC] D6_APC_2: 0x3fffff
9900 11:44:53.271271 INFO: [APUAPC] D6_APC_3: 0x0
9901 11:44:53.274083 INFO: [APUAPC] D7_APC_0: 0xffffffff
9902 11:44:53.277707 INFO: [APUAPC] D7_APC_1: 0xffffffff
9903 11:44:53.280784 INFO: [APUAPC] D7_APC_2: 0x3fffff
9904 11:44:53.284281 INFO: [APUAPC] D7_APC_3: 0x0
9905 11:44:53.287750 INFO: [APUAPC] D8_APC_0: 0xffffffff
9906 11:44:53.290760 INFO: [APUAPC] D8_APC_1: 0xffffffff
9907 11:44:53.294312 INFO: [APUAPC] D8_APC_2: 0x3fffff
9908 11:44:53.297161 INFO: [APUAPC] D8_APC_3: 0x0
9909 11:44:53.300745 INFO: [APUAPC] D9_APC_0: 0xffffffff
9910 11:44:53.303778 INFO: [APUAPC] D9_APC_1: 0xffffffff
9911 11:44:53.306903 INFO: [APUAPC] D9_APC_2: 0x3fffff
9912 11:44:53.310715 INFO: [APUAPC] D9_APC_3: 0x0
9913 11:44:53.313960 INFO: [APUAPC] D10_APC_0: 0xffffffff
9914 11:44:53.317116 INFO: [APUAPC] D10_APC_1: 0xffffffff
9915 11:44:53.320379 INFO: [APUAPC] D10_APC_2: 0x3fffff
9916 11:44:53.323529 INFO: [APUAPC] D10_APC_3: 0x0
9917 11:44:53.327209 INFO: [APUAPC] D11_APC_0: 0xffffffff
9918 11:44:53.330387 INFO: [APUAPC] D11_APC_1: 0xffffffff
9919 11:44:53.333363 INFO: [APUAPC] D11_APC_2: 0x3fffff
9920 11:44:53.336966 INFO: [APUAPC] D11_APC_3: 0x0
9921 11:44:53.339968 INFO: [APUAPC] D12_APC_0: 0xffffffff
9922 11:44:53.343804 INFO: [APUAPC] D12_APC_1: 0xffffffff
9923 11:44:53.346990 INFO: [APUAPC] D12_APC_2: 0x3fffff
9924 11:44:53.350108 INFO: [APUAPC] D12_APC_3: 0x0
9925 11:44:53.353420 INFO: [APUAPC] D13_APC_0: 0xffffffff
9926 11:44:53.356578 INFO: [APUAPC] D13_APC_1: 0xffffffff
9927 11:44:53.359650 INFO: [APUAPC] D13_APC_2: 0x3fffff
9928 11:44:53.363503 INFO: [APUAPC] D13_APC_3: 0x0
9929 11:44:53.366680 INFO: [APUAPC] D14_APC_0: 0xffffffff
9930 11:44:53.369784 INFO: [APUAPC] D14_APC_1: 0xffffffff
9931 11:44:53.372918 INFO: [APUAPC] D14_APC_2: 0x3fffff
9932 11:44:53.376404 INFO: [APUAPC] D14_APC_3: 0x0
9933 11:44:53.379424 INFO: [APUAPC] D15_APC_0: 0xffffffff
9934 11:44:53.383226 INFO: [APUAPC] D15_APC_1: 0xffffffff
9935 11:44:53.386401 INFO: [APUAPC] D15_APC_2: 0x3fffff
9936 11:44:53.389539 INFO: [APUAPC] D15_APC_3: 0x0
9937 11:44:53.393050 INFO: [APUAPC] APC_CON: 0x4
9938 11:44:53.395813 INFO: [NOCDAPC] D0_APC_0: 0x0
9939 11:44:53.399547 INFO: [NOCDAPC] D0_APC_1: 0x0
9940 11:44:53.402528 INFO: [NOCDAPC] D1_APC_0: 0x0
9941 11:44:53.406163 INFO: [NOCDAPC] D1_APC_1: 0xfff
9942 11:44:53.409129 INFO: [NOCDAPC] D2_APC_0: 0x0
9943 11:44:53.412825 INFO: [NOCDAPC] D2_APC_1: 0xfff
9944 11:44:53.415691 INFO: [NOCDAPC] D3_APC_0: 0x0
9945 11:44:53.418920 INFO: [NOCDAPC] D3_APC_1: 0xfff
9946 11:44:53.419036 INFO: [NOCDAPC] D4_APC_0: 0x0
9947 11:44:53.422689 INFO: [NOCDAPC] D4_APC_1: 0xfff
9948 11:44:53.425862 INFO: [NOCDAPC] D5_APC_0: 0x0
9949 11:44:53.428923 INFO: [NOCDAPC] D5_APC_1: 0xfff
9950 11:44:53.432126 INFO: [NOCDAPC] D6_APC_0: 0x0
9951 11:44:53.435786 INFO: [NOCDAPC] D6_APC_1: 0xfff
9952 11:44:53.438911 INFO: [NOCDAPC] D7_APC_0: 0x0
9953 11:44:53.441988 INFO: [NOCDAPC] D7_APC_1: 0xfff
9954 11:44:53.445512 INFO: [NOCDAPC] D8_APC_0: 0x0
9955 11:44:53.448653 INFO: [NOCDAPC] D8_APC_1: 0xfff
9956 11:44:53.451852 INFO: [NOCDAPC] D9_APC_0: 0x0
9957 11:44:53.455053 INFO: [NOCDAPC] D9_APC_1: 0xfff
9958 11:44:53.455188 INFO: [NOCDAPC] D10_APC_0: 0x0
9959 11:44:53.458920 INFO: [NOCDAPC] D10_APC_1: 0xfff
9960 11:44:53.462036 INFO: [NOCDAPC] D11_APC_0: 0x0
9961 11:44:53.465282 INFO: [NOCDAPC] D11_APC_1: 0xfff
9962 11:44:53.468504 INFO: [NOCDAPC] D12_APC_0: 0x0
9963 11:44:53.471704 INFO: [NOCDAPC] D12_APC_1: 0xfff
9964 11:44:53.474827 INFO: [NOCDAPC] D13_APC_0: 0x0
9965 11:44:53.478647 INFO: [NOCDAPC] D13_APC_1: 0xfff
9966 11:44:53.481671 INFO: [NOCDAPC] D14_APC_0: 0x0
9967 11:44:53.484686 INFO: [NOCDAPC] D14_APC_1: 0xfff
9968 11:44:53.488372 INFO: [NOCDAPC] D15_APC_0: 0x0
9969 11:44:53.491740 INFO: [NOCDAPC] D15_APC_1: 0xfff
9970 11:44:53.494828 INFO: [NOCDAPC] APC_CON: 0x4
9971 11:44:53.497853 INFO: [APUAPC] set_apusys_apc done
9972 11:44:53.501420 INFO: [DEVAPC] devapc_init done
9973 11:44:53.504424 INFO: GICv3 without legacy support detected.
9974 11:44:53.508082 INFO: ARM GICv3 driver initialized in EL3
9975 11:44:53.511236 INFO: Maximum SPI INTID supported: 639
9976 11:44:53.517403 INFO: BL31: Initializing runtime services
9977 11:44:53.520913 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9978 11:44:53.524028 INFO: SPM: enable CPC mode
9979 11:44:53.530911 INFO: mcdi ready for mcusys-off-idle and system suspend
9980 11:44:53.533947 INFO: BL31: Preparing for EL3 exit to normal world
9981 11:44:53.537116 INFO: Entry point address = 0x80000000
9982 11:44:53.540899 INFO: SPSR = 0x8
9983 11:44:53.545739
9984 11:44:53.545830
9985 11:44:53.545902
9986 11:44:53.549389 Starting depthcharge on Spherion...
9987 11:44:53.549472
9988 11:44:53.549538 Wipe memory regions:
9989 11:44:53.549600
9990 11:44:53.550387 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
9991 11:44:53.550506 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9992 11:44:53.550592 Setting prompt string to ['asurada:']
9993 11:44:53.550673 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9994 11:44:53.552552 [0x00000040000000, 0x00000054600000)
9995 11:44:53.675118
9996 11:44:53.675265 [0x00000054660000, 0x00000080000000)
9997 11:44:53.934212
9998 11:44:53.934389 [0x000000821a7280, 0x000000ffe64000)
9999 11:44:54.678501
10000 11:44:54.678683 [0x00000100000000, 0x00000240000000)
10001 11:44:56.566780
10002 11:44:56.570442 Initializing XHCI USB controller at 0x11200000.
10003 11:44:57.607465
10004 11:44:57.611119 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10005 11:44:57.611253
10006 11:44:57.611359
10007 11:44:57.611453
10008 11:44:57.611772 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10010 11:44:57.712161 asurada: tftpboot 192.168.201.1 10742252/tftp-deploy-48ix2pz_/kernel/image.itb 10742252/tftp-deploy-48ix2pz_/kernel/cmdline
10011 11:44:57.712372 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10012 11:44:57.712518 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10013 11:44:57.717256 tftpboot 192.168.201.1 10742252/tftp-deploy-48ix2pz_/kernel/image.ittp-deploy-48ix2pz_/kernel/cmdline
10014 11:44:57.717374
10015 11:44:57.717486 Waiting for link
10016 11:44:57.877253
10017 11:44:57.877423 R8152: Initializing
10018 11:44:57.877524
10019 11:44:57.880822 Version 6 (ocp_data = 5c30)
10020 11:44:57.880932
10021 11:44:57.883972 R8152: Done initializing
10022 11:44:57.884097
10023 11:44:57.884184 Adding net device
10024 11:44:59.849140
10025 11:44:59.849316 done.
10026 11:44:59.849417
10027 11:44:59.849555 MAC: 00:24:32:30:7c:7b
10028 11:44:59.849659
10029 11:44:59.852199 Sending DHCP discover... done.
10030 11:44:59.852319
10031 11:45:12.290348 Waiting for reply... done.
10032 11:45:12.290856
10033 11:45:12.291192 Sending DHCP request... done.
10034 11:45:12.293478
10035 11:45:12.299001 Waiting for reply... done.
10036 11:45:12.299505
10037 11:45:12.299915 My ip is 192.168.201.14
10038 11:45:12.300343
10039 11:45:12.302363 The DHCP server ip is 192.168.201.1
10040 11:45:12.302809
10041 11:45:12.308669 TFTP server IP predefined by user: 192.168.201.1
10042 11:45:12.309141
10043 11:45:12.315436 Bootfile predefined by user: 10742252/tftp-deploy-48ix2pz_/kernel/image.itb
10044 11:45:12.315989
10045 11:45:12.318565 Sending tftp read request... done.
10046 11:45:12.319178
10047 11:45:12.324529 Waiting for the transfer...
10048 11:45:12.325215
10049 11:45:12.875687 00000000 ################################################################
10050 11:45:12.875838
10051 11:45:13.482328 00080000 ################################################################
10052 11:45:13.482478
10053 11:45:14.135686 00100000 ################################################################
10054 11:45:14.136448
10055 11:45:14.766662 00180000 ################################################################
10056 11:45:14.767148
10057 11:45:15.365845 00200000 ################################################################
10058 11:45:15.365987
10059 11:45:15.955850 00280000 ################################################################
10060 11:45:15.956001
10061 11:45:16.563245 00300000 ################################################################
10062 11:45:16.563447
10063 11:45:17.160503 00380000 ################################################################
10064 11:45:17.160701
10065 11:45:17.762234 00400000 ################################################################
10066 11:45:17.762407
10067 11:45:18.368274 00480000 ################################################################
10068 11:45:18.368427
10069 11:45:18.964193 00500000 ################################################################
10070 11:45:18.964345
10071 11:45:19.557827 00580000 ################################################################
10072 11:45:19.557976
10073 11:45:20.159357 00600000 ################################################################
10074 11:45:20.159540
10075 11:45:20.770559 00680000 ################################################################
10076 11:45:20.770739
10077 11:45:21.373660 00700000 ################################################################
10078 11:45:21.373839
10079 11:45:21.972922 00780000 ################################################################
10080 11:45:21.973082
10081 11:45:22.571620 00800000 ################################################################
10082 11:45:22.571757
10083 11:45:23.180998 00880000 ################################################################
10084 11:45:23.181155
10085 11:45:23.785279 00900000 ################################################################
10086 11:45:23.785433
10087 11:45:24.390938 00980000 ################################################################
10088 11:45:24.391117
10089 11:45:25.009255 00a00000 ################################################################
10090 11:45:25.009427
10091 11:45:25.629744 00a80000 ################################################################
10092 11:45:25.629928
10093 11:45:26.233985 00b00000 ################################################################
10094 11:45:26.234165
10095 11:45:26.848988 00b80000 ################################################################
10096 11:45:26.849143
10097 11:45:27.454216 00c00000 ################################################################
10098 11:45:27.454390
10099 11:45:28.075737 00c80000 ################################################################
10100 11:45:28.075918
10101 11:45:28.689960 00d00000 ################################################################
10102 11:45:28.690108
10103 11:45:29.303473 00d80000 ################################################################
10104 11:45:29.303645
10105 11:45:29.923334 00e00000 ################################################################
10106 11:45:29.923511
10107 11:45:30.526700 00e80000 ################################################################
10108 11:45:30.526900
10109 11:45:31.121213 00f00000 ################################################################
10110 11:45:31.121363
10111 11:45:31.735576 00f80000 ################################################################
10112 11:45:31.735756
10113 11:45:32.350283 01000000 ################################################################
10114 11:45:32.350451
10115 11:45:32.964002 01080000 ################################################################
10116 11:45:32.964178
10117 11:45:33.560002 01100000 ################################################################
10118 11:45:33.560159
10119 11:45:34.157369 01180000 ################################################################
10120 11:45:34.157556
10121 11:45:34.739720 01200000 ################################################################
10122 11:45:34.739900
10123 11:45:35.309935 01280000 ################################################################
10124 11:45:35.310120
10125 11:45:35.893199 01300000 ################################################################
10126 11:45:35.893361
10127 11:45:36.474966 01380000 ################################################################
10128 11:45:36.475125
10129 11:45:37.051452 01400000 ################################################################
10130 11:45:37.051624
10131 11:45:37.613623 01480000 ################################################################
10132 11:45:37.613835
10133 11:45:38.191143 01500000 ################################################################
10134 11:45:38.191304
10135 11:45:38.739194 01580000 ################################################################
10136 11:45:38.739347
10137 11:45:39.302930 01600000 ################################################################
10138 11:45:39.303091
10139 11:45:39.878303 01680000 ################################################################
10140 11:45:39.878461
10141 11:45:40.434596 01700000 ################################################################
10142 11:45:40.434753
10143 11:45:40.988186 01780000 ################################################################
10144 11:45:40.988349
10145 11:45:41.569857 01800000 ################################################################
10146 11:45:41.570050
10147 11:45:42.124304 01880000 ################################################################
10148 11:45:42.124458
10149 11:45:42.697867 01900000 ################################################################
10150 11:45:42.698034
10151 11:45:43.257627 01980000 ################################################################
10152 11:45:43.257793
10153 11:45:43.826305 01a00000 ################################################################
10154 11:45:43.826481
10155 11:45:44.410244 01a80000 ################################################################
10156 11:45:44.410393
10157 11:45:45.000723 01b00000 ################################################################
10158 11:45:45.000883
10159 11:45:45.569806 01b80000 ################################################################
10160 11:45:45.570009
10161 11:45:46.119731 01c00000 ################################################################
10162 11:45:46.119922
10163 11:45:46.664110 01c80000 ################################################################
10164 11:45:46.664334
10165 11:45:47.235951 01d00000 ################################################################
10166 11:45:47.236149
10167 11:45:47.766624 01d80000 ################################################################
10168 11:45:47.766778
10169 11:45:48.315199 01e00000 ################################################################
10170 11:45:48.315335
10171 11:45:48.857396 01e80000 ################################################################
10172 11:45:48.857606
10173 11:45:49.427234 01f00000 ################################################################
10174 11:45:49.427387
10175 11:45:50.014413 01f80000 ################################################################
10176 11:45:50.014563
10177 11:45:50.598843 02000000 ################################################################
10178 11:45:50.599053
10179 11:45:51.154043 02080000 ################################################################
10180 11:45:51.154190
10181 11:45:51.711721 02100000 ################################################################
10182 11:45:51.711898
10183 11:45:52.284722 02180000 ################################################################
10184 11:45:52.284864
10185 11:45:52.848558 02200000 ################################################################
10186 11:45:52.848733
10187 11:45:53.418460 02280000 ################################################################
10188 11:45:53.418612
10189 11:45:53.982830 02300000 ################################################################
10190 11:45:53.983038
10191 11:45:54.540782 02380000 ################################################################
10192 11:45:54.540974
10193 11:45:55.117020 02400000 ################################################################
10194 11:45:55.117200
10195 11:45:55.694876 02480000 ################################################################
10196 11:45:55.695016
10197 11:45:56.262196 02500000 ################################################################
10198 11:45:56.262347
10199 11:45:56.840792 02580000 ################################################################
10200 11:45:56.840941
10201 11:45:57.406358 02600000 ################################################################
10202 11:45:57.406539
10203 11:45:57.975345 02680000 ################################################################
10204 11:45:57.975511
10205 11:45:58.539279 02700000 ################################################################
10206 11:45:58.539457
10207 11:45:59.102319 02780000 ################################################################
10208 11:45:59.102463
10209 11:45:59.670446 02800000 ################################################################
10210 11:45:59.670638
10211 11:46:00.241606 02880000 ################################################################
10212 11:46:00.241782
10213 11:46:00.809827 02900000 ################################################################
10214 11:46:00.810009
10215 11:46:01.374992 02980000 ################################################################
10216 11:46:01.375150
10217 11:46:01.945947 02a00000 ################################################################
10218 11:46:01.946125
10219 11:46:02.511694 02a80000 ################################################################
10220 11:46:02.511875
10221 11:46:03.073187 02b00000 ################################################################
10222 11:46:03.073361
10223 11:46:03.624273 02b80000 ################################################################
10224 11:46:03.624433
10225 11:46:04.172045 02c00000 ################################################################
10226 11:46:04.172239
10227 11:46:04.721336 02c80000 ################################################################
10228 11:46:04.721489
10229 11:46:05.275225 02d00000 ################################################################
10230 11:46:05.275396
10231 11:46:05.836627 02d80000 ################################################################
10232 11:46:05.836813
10233 11:46:06.408569 02e00000 ################################################################
10234 11:46:06.408728
10235 11:46:06.971914 02e80000 ################################################################
10236 11:46:06.972099
10237 11:46:07.558970 02f00000 ################################################################
10238 11:46:07.559125
10239 11:46:08.101050 02f80000 ################################################################
10240 11:46:08.101219
10241 11:46:08.671929 03000000 ################################################################
10242 11:46:08.672111
10243 11:46:09.243866 03080000 ################################################################
10244 11:46:09.244055
10245 11:46:09.787620 03100000 ################################################################
10246 11:46:09.787774
10247 11:46:10.337474 03180000 ################################################################
10248 11:46:10.337627
10249 11:46:10.888913 03200000 ################################################################
10250 11:46:10.889069
10251 11:46:11.479640 03280000 ################################################################
10252 11:46:11.479793
10253 11:46:12.099787 03300000 ################################################################
10254 11:46:12.099948
10255 11:46:12.742546 03380000 ################################################################
10256 11:46:12.742703
10257 11:46:13.350955 03400000 ################################################################
10258 11:46:13.351109
10259 11:46:13.899944 03480000 ################################################################
10260 11:46:13.900153
10261 11:46:14.445867 03500000 ################################################################
10262 11:46:14.446051
10263 11:46:14.983714 03580000 ################################################################
10264 11:46:14.983894
10265 11:46:15.504971 03600000 ################################################################
10266 11:46:15.505162
10267 11:46:16.020055 03680000 ################################################################
10268 11:46:16.020232
10269 11:46:16.537584 03700000 ################################################################
10270 11:46:16.537735
10271 11:46:17.077911 03780000 ################################################################
10272 11:46:17.078062
10273 11:46:17.620621 03800000 ################################################################
10274 11:46:17.620800
10275 11:46:18.144951 03880000 ################################################################
10276 11:46:18.145097
10277 11:46:18.687143 03900000 ################################################################
10278 11:46:18.687278
10279 11:46:19.235857 03980000 ################################################################
10280 11:46:19.236007
10281 11:46:19.756932 03a00000 ################################################################
10282 11:46:19.757115
10283 11:46:20.283888 03a80000 ################################################################
10284 11:46:20.284026
10285 11:46:20.812798 03b00000 ################################################################
10286 11:46:20.812939
10287 11:46:21.351609 03b80000 ################################################################
10288 11:46:21.351775
10289 11:46:21.882928 03c00000 ################################################################
10290 11:46:21.883075
10291 11:46:22.426380 03c80000 ################################################################
10292 11:46:22.426547
10293 11:46:22.962044 03d00000 ################################################################
10294 11:46:22.962175
10295 11:46:23.496366 03d80000 ################################################################
10296 11:46:23.496497
10297 11:46:24.048968 03e00000 ################################################################
10298 11:46:24.049106
10299 11:46:24.598039 03e80000 ################################################################
10300 11:46:24.598184
10301 11:46:25.125329 03f00000 ################################################################
10302 11:46:25.125480
10303 11:46:25.414928 03f80000 ################################### done.
10304 11:46:25.418245
10305 11:46:25.421448 The bootfile was 66865722 bytes long.
10306 11:46:25.421532
10307 11:46:25.421596 Sending tftp read request... done.
10308 11:46:25.424721
10309 11:46:25.424801 Waiting for the transfer...
10310 11:46:25.424866
10311 11:46:25.427888 00000000 # done.
10312 11:46:25.427972
10313 11:46:25.434707 Command line loaded dynamically from TFTP file: 10742252/tftp-deploy-48ix2pz_/kernel/cmdline
10314 11:46:25.434789
10315 11:46:25.447838 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10316 11:46:25.447935
10317 11:46:25.448054 Loading FIT.
10318 11:46:25.448140
10319 11:46:25.450890 Image ramdisk-1 has 56373404 bytes.
10320 11:46:25.450973
10321 11:46:25.454450 Image fdt-1 has 46924 bytes.
10322 11:46:25.454532
10323 11:46:25.457443 Image kernel-1 has 10443363 bytes.
10324 11:46:25.457525
10325 11:46:25.464262 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10326 11:46:25.464345
10327 11:46:25.483574 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10328 11:46:25.483682
10329 11:46:25.486957 Choosing best match conf-1 for compat google,spherion-rev2.
10330 11:46:25.492191
10331 11:46:25.496705 Connected to device vid:did:rid of 1ae0:0028:00
10332 11:46:25.503767
10333 11:46:25.506853 tpm_get_response: command 0x17b, return code 0x0
10334 11:46:25.506937
10335 11:46:25.510130 ec_init: CrosEC protocol v3 supported (256, 248)
10336 11:46:25.513976
10337 11:46:25.517969 tpm_cleanup: add release locality here.
10338 11:46:25.518052
10339 11:46:25.518127 Shutting down all USB controllers.
10340 11:46:25.521209
10341 11:46:25.521290 Removing current net device
10342 11:46:25.521356
10343 11:46:25.527653 Exiting depthcharge with code 4 at timestamp: 121300214
10344 11:46:25.527737
10345 11:46:25.530890 LZMA decompressing kernel-1 to 0x821a6718
10346 11:46:25.530972
10347 11:46:25.534170 LZMA decompressing kernel-1 to 0x40000000
10348 11:46:26.845336
10349 11:46:26.845496 jumping to kernel
10350 11:46:26.845952 end: 2.2.4 bootloader-commands (duration 00:01:33) [common]
10351 11:46:26.846051 start: 2.2.5 auto-login-action (timeout 00:02:52) [common]
10352 11:46:26.846133 Setting prompt string to ['Linux version [0-9]']
10353 11:46:26.846203 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10354 11:46:26.846273 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10355 11:46:26.928079
10356 11:46:26.931277 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10357 11:46:26.934721 start: 2.2.5.1 login-action (timeout 00:02:52) [common]
10358 11:46:26.934819 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10359 11:46:26.934906 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10360 11:46:26.934983 Using line separator: #'\n'#
10361 11:46:26.935045 No login prompt set.
10362 11:46:26.935108 Parsing kernel messages
10363 11:46:26.935164 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10364 11:46:26.935295 [login-action] Waiting for messages, (timeout 00:02:52)
10365 11:46:26.954687 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10366 11:46:26.957710 [ 0.000000] random: crng init done
10367 11:46:26.961536 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10368 11:46:26.964329 [ 0.000000] efi: UEFI not found.
10369 11:46:26.974269 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10370 11:46:26.981024 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10371 11:46:26.991008 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10372 11:46:27.000790 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10373 11:46:27.007193 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10374 11:46:27.010568 [ 0.000000] printk: bootconsole [mtk8250] enabled
10375 11:46:27.019635 [ 0.000000] NUMA: No NUMA configuration found
10376 11:46:27.026103 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10377 11:46:27.032386 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10378 11:46:27.032470 [ 0.000000] Zone ranges:
10379 11:46:27.039511 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10380 11:46:27.042673 [ 0.000000] DMA32 empty
10381 11:46:27.048846 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10382 11:46:27.052139 [ 0.000000] Movable zone start for each node
10383 11:46:27.055338 [ 0.000000] Early memory node ranges
10384 11:46:27.062150 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10385 11:46:27.068794 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10386 11:46:27.075239 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10387 11:46:27.082139 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10388 11:46:27.088301 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10389 11:46:27.095281 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10390 11:46:27.151406 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10391 11:46:27.158392 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10392 11:46:27.164810 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10393 11:46:27.168528 [ 0.000000] psci: probing for conduit method from DT.
10394 11:46:27.174516 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10395 11:46:27.178198 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10396 11:46:27.184882 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10397 11:46:27.187989 [ 0.000000] psci: SMC Calling Convention v1.2
10398 11:46:27.194929 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10399 11:46:27.198080 [ 0.000000] Detected VIPT I-cache on CPU0
10400 11:46:27.204332 [ 0.000000] CPU features: detected: GIC system register CPU interface
10401 11:46:27.211310 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10402 11:46:27.217928 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10403 11:46:27.224257 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10404 11:46:27.230699 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10405 11:46:27.240983 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10406 11:46:27.244194 [ 0.000000] alternatives: applying boot alternatives
10407 11:46:27.250571 [ 0.000000] Fallback order for Node 0: 0
10408 11:46:27.257302 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10409 11:46:27.260484 [ 0.000000] Policy zone: Normal
10410 11:46:27.270133 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10411 11:46:27.283626 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10412 11:46:27.293481 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10413 11:46:27.303345 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10414 11:46:27.309655 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10415 11:46:27.312939 <6>[ 0.000000] software IO TLB: area num 8.
10416 11:46:27.369776 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10417 11:46:27.518916 <6>[ 0.000000] Memory: 7916104K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 436664K reserved, 32768K cma-reserved)
10418 11:46:27.526027 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10419 11:46:27.532521 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10420 11:46:27.535701 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10421 11:46:27.541970 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10422 11:46:27.549106 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10423 11:46:27.552296 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10424 11:46:27.561702 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10425 11:46:27.568671 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10426 11:46:27.574906 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10427 11:46:27.581833 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10428 11:46:27.585090 <6>[ 0.000000] GICv3: 608 SPIs implemented
10429 11:46:27.588287 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10430 11:46:27.594574 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10431 11:46:27.598328 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10432 11:46:27.604482 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10433 11:46:27.617899 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10434 11:46:27.631308 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10435 11:46:27.637773 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10436 11:46:27.645317 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10437 11:46:27.658576 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10438 11:46:27.665476 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10439 11:46:27.671863 <6>[ 0.009224] Console: colour dummy device 80x25
10440 11:46:27.682169 <6>[ 0.013952] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10441 11:46:27.688486 <6>[ 0.024394] pid_max: default: 32768 minimum: 301
10442 11:46:27.691662 <6>[ 0.029268] LSM: Security Framework initializing
10443 11:46:27.698791 <6>[ 0.034209] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10444 11:46:27.708327 <6>[ 0.042024] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10445 11:46:27.718124 <6>[ 0.051450] cblist_init_generic: Setting adjustable number of callback queues.
10446 11:46:27.721818 <6>[ 0.058902] cblist_init_generic: Setting shift to 3 and lim to 1.
10447 11:46:27.728102 <6>[ 0.065280] cblist_init_generic: Setting shift to 3 and lim to 1.
10448 11:46:27.734789 <6>[ 0.071687] rcu: Hierarchical SRCU implementation.
10449 11:46:27.741252 <6>[ 0.076700] rcu: Max phase no-delay instances is 1000.
10450 11:46:27.747681 <6>[ 0.083718] EFI services will not be available.
10451 11:46:27.750942 <6>[ 0.088723] smp: Bringing up secondary CPUs ...
10452 11:46:27.759412 <6>[ 0.093776] Detected VIPT I-cache on CPU1
10453 11:46:27.765702 <6>[ 0.093849] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10454 11:46:27.772224 <6>[ 0.093879] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10455 11:46:27.775363 <6>[ 0.094218] Detected VIPT I-cache on CPU2
10456 11:46:27.785414 <6>[ 0.094272] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10457 11:46:27.791779 <6>[ 0.094289] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10458 11:46:27.795513 <6>[ 0.094549] Detected VIPT I-cache on CPU3
10459 11:46:27.802026 <6>[ 0.094598] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10460 11:46:27.808390 <6>[ 0.094612] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10461 11:46:27.811539 <6>[ 0.094920] CPU features: detected: Spectre-v4
10462 11:46:27.818326 <6>[ 0.094927] CPU features: detected: Spectre-BHB
10463 11:46:27.821971 <6>[ 0.094932] Detected PIPT I-cache on CPU4
10464 11:46:27.827959 <6>[ 0.094991] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10465 11:46:27.834866 <6>[ 0.095007] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10466 11:46:27.841673 <6>[ 0.095297] Detected PIPT I-cache on CPU5
10467 11:46:27.847662 <6>[ 0.095361] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10468 11:46:27.854637 <6>[ 0.095377] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10469 11:46:27.857938 <6>[ 0.095660] Detected PIPT I-cache on CPU6
10470 11:46:27.867388 <6>[ 0.095726] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10471 11:46:27.874399 <6>[ 0.095742] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10472 11:46:27.877586 <6>[ 0.096042] Detected PIPT I-cache on CPU7
10473 11:46:27.884340 <6>[ 0.096108] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10474 11:46:27.890838 <6>[ 0.096124] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10475 11:46:27.894004 <6>[ 0.096170] smp: Brought up 1 node, 8 CPUs
10476 11:46:27.900525 <6>[ 0.237534] SMP: Total of 8 processors activated.
10477 11:46:27.906972 <6>[ 0.242455] CPU features: detected: 32-bit EL0 Support
10478 11:46:27.913987 <6>[ 0.247818] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10479 11:46:27.920774 <6>[ 0.256618] CPU features: detected: Common not Private translations
10480 11:46:27.927408 <6>[ 0.263133] CPU features: detected: CRC32 instructions
10481 11:46:27.933640 <6>[ 0.268484] CPU features: detected: RCpc load-acquire (LDAPR)
10482 11:46:27.936745 <6>[ 0.274444] CPU features: detected: LSE atomic instructions
10483 11:46:27.943523 <6>[ 0.280225] CPU features: detected: Privileged Access Never
10484 11:46:27.950110 <6>[ 0.286005] CPU features: detected: RAS Extension Support
10485 11:46:27.956583 <6>[ 0.291613] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10486 11:46:27.959823 <6>[ 0.298834] CPU: All CPU(s) started at EL2
10487 11:46:27.966358 <6>[ 0.303151] alternatives: applying system-wide alternatives
10488 11:46:27.976670 <6>[ 0.313856] devtmpfs: initialized
10489 11:46:27.989232 <6>[ 0.322767] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10490 11:46:27.998861 <6>[ 0.332731] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10491 11:46:28.005225 <6>[ 0.340957] pinctrl core: initialized pinctrl subsystem
10492 11:46:28.009200 <6>[ 0.347626] DMI not present or invalid.
10493 11:46:28.015596 <6>[ 0.352031] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10494 11:46:28.025137 <6>[ 0.358911] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10495 11:46:28.031746 <6>[ 0.366492] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10496 11:46:28.041705 <6>[ 0.374718] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10497 11:46:28.045347 <6>[ 0.382959] audit: initializing netlink subsys (disabled)
10498 11:46:28.054955 <5>[ 0.388655] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10499 11:46:28.061972 <6>[ 0.389363] thermal_sys: Registered thermal governor 'step_wise'
10500 11:46:28.068460 <6>[ 0.396619] thermal_sys: Registered thermal governor 'power_allocator'
10501 11:46:28.071593 <6>[ 0.402875] cpuidle: using governor menu
10502 11:46:28.078034 <6>[ 0.413835] NET: Registered PF_QIPCRTR protocol family
10503 11:46:28.085112 <6>[ 0.419312] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10504 11:46:28.091496 <6>[ 0.426410] ASID allocator initialised with 32768 entries
10505 11:46:28.094958 <6>[ 0.432979] Serial: AMBA PL011 UART driver
10506 11:46:28.104741 <4>[ 0.441726] Trying to register duplicate clock ID: 134
10507 11:46:28.160505 <6>[ 0.501220] KASLR enabled
10508 11:46:28.175001 <6>[ 0.508997] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10509 11:46:28.181529 <6>[ 0.516011] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10510 11:46:28.187929 <6>[ 0.522500] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10511 11:46:28.194513 <6>[ 0.529503] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10512 11:46:28.201322 <6>[ 0.535991] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10513 11:46:28.207859 <6>[ 0.542997] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10514 11:46:28.214316 <6>[ 0.549483] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10515 11:46:28.221408 <6>[ 0.556486] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10516 11:46:28.224746 <6>[ 0.564009] ACPI: Interpreter disabled.
10517 11:46:28.233536 <6>[ 0.570398] iommu: Default domain type: Translated
10518 11:46:28.239622 <6>[ 0.575510] iommu: DMA domain TLB invalidation policy: strict mode
10519 11:46:28.243373 <5>[ 0.582168] SCSI subsystem initialized
10520 11:46:28.249613 <6>[ 0.586337] usbcore: registered new interface driver usbfs
10521 11:46:28.255969 <6>[ 0.592068] usbcore: registered new interface driver hub
10522 11:46:28.259623 <6>[ 0.597620] usbcore: registered new device driver usb
10523 11:46:28.266414 <6>[ 0.603707] pps_core: LinuxPPS API ver. 1 registered
10524 11:46:28.276168 <6>[ 0.608900] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10525 11:46:28.280008 <6>[ 0.618244] PTP clock support registered
10526 11:46:28.283196 <6>[ 0.622486] EDAC MC: Ver: 3.0.0
10527 11:46:28.290806 <6>[ 0.627639] FPGA manager framework
10528 11:46:28.297230 <6>[ 0.631319] Advanced Linux Sound Architecture Driver Initialized.
10529 11:46:28.300403 <6>[ 0.638097] vgaarb: loaded
10530 11:46:28.307100 <6>[ 0.641259] clocksource: Switched to clocksource arch_sys_counter
10531 11:46:28.310317 <5>[ 0.647703] VFS: Disk quotas dquot_6.6.0
10532 11:46:28.316773 <6>[ 0.651886] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10533 11:46:28.320010 <6>[ 0.659077] pnp: PnP ACPI: disabled
10534 11:46:28.328413 <6>[ 0.665828] NET: Registered PF_INET protocol family
10535 11:46:28.338241 <6>[ 0.671426] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10536 11:46:28.349968 <6>[ 0.683748] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10537 11:46:28.359839 <6>[ 0.692563] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10538 11:46:28.366427 <6>[ 0.700530] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10539 11:46:28.376134 <6>[ 0.709228] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10540 11:46:28.382914 <6>[ 0.718964] TCP: Hash tables configured (established 65536 bind 65536)
10541 11:46:28.389319 <6>[ 0.725819] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 11:46:28.399590 <6>[ 0.733017] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10543 11:46:28.405969 <6>[ 0.740718] NET: Registered PF_UNIX/PF_LOCAL protocol family
10544 11:46:28.412170 <6>[ 0.746883] RPC: Registered named UNIX socket transport module.
10545 11:46:28.415523 <6>[ 0.753039] RPC: Registered udp transport module.
10546 11:46:28.419313 <6>[ 0.757970] RPC: Registered tcp transport module.
10547 11:46:28.428969 <6>[ 0.762900] RPC: Registered tcp NFSv4.1 backchannel transport module.
10548 11:46:28.432261 <6>[ 0.769571] PCI: CLS 0 bytes, default 64
10549 11:46:28.435499 <6>[ 0.773913] Unpacking initramfs...
10550 11:46:28.445836 <6>[ 0.778023] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10551 11:46:28.452042 <6>[ 0.786682] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10552 11:46:28.458956 <6>[ 0.795525] kvm [1]: IPA Size Limit: 40 bits
10553 11:46:28.462108 <6>[ 0.800052] kvm [1]: GICv3: no GICV resource entry
10554 11:46:28.468874 <6>[ 0.805073] kvm [1]: disabling GICv2 emulation
10555 11:46:28.475564 <6>[ 0.809765] kvm [1]: GIC system register CPU interface enabled
10556 11:46:28.478544 <6>[ 0.815929] kvm [1]: vgic interrupt IRQ18
10557 11:46:28.482050 <6>[ 0.820282] kvm [1]: VHE mode initialized successfully
10558 11:46:28.489317 <5>[ 0.826697] Initialise system trusted keyrings
10559 11:46:28.496138 <6>[ 0.831502] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10560 11:46:28.504462 <6>[ 0.841639] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10561 11:46:28.510829 <5>[ 0.848049] NFS: Registering the id_resolver key type
10562 11:46:28.514507 <5>[ 0.853347] Key type id_resolver registered
10563 11:46:28.520987 <5>[ 0.857763] Key type id_legacy registered
10564 11:46:28.527523 <6>[ 0.862040] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10565 11:46:28.533993 <6>[ 0.868963] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10566 11:46:28.540547 <6>[ 0.876699] 9p: Installing v9fs 9p2000 file system support
10567 11:46:28.578201 <5>[ 0.915123] Key type asymmetric registered
10568 11:46:28.581320 <5>[ 0.919456] Asymmetric key parser 'x509' registered
10569 11:46:28.590995 <6>[ 0.924603] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10570 11:46:28.594121 <6>[ 0.932217] io scheduler mq-deadline registered
10571 11:46:28.597930 <6>[ 0.936977] io scheduler kyber registered
10572 11:46:28.616849 <6>[ 0.954066] EINJ: ACPI disabled.
10573 11:46:28.649114 <4>[ 0.979647] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 11:46:28.658535 <4>[ 0.990284] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10575 11:46:28.673910 <6>[ 1.011103] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10576 11:46:28.681796 <6>[ 1.019119] printk: console [ttyS0] disabled
10577 11:46:28.709607 <6>[ 1.043765] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10578 11:46:28.716349 <6>[ 1.053236] printk: console [ttyS0] enabled
10579 11:46:28.719623 <6>[ 1.053236] printk: console [ttyS0] enabled
10580 11:46:28.726575 <6>[ 1.062130] printk: bootconsole [mtk8250] disabled
10581 11:46:28.729818 <6>[ 1.062130] printk: bootconsole [mtk8250] disabled
10582 11:46:28.736318 <6>[ 1.073186] SuperH (H)SCI(F) driver initialized
10583 11:46:28.739588 <6>[ 1.078451] msm_serial: driver initialized
10584 11:46:28.753894 <6>[ 1.087328] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10585 11:46:28.763467 <6>[ 1.095873] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10586 11:46:28.769796 <6>[ 1.104414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10587 11:46:28.780251 <6>[ 1.113042] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10588 11:46:28.790155 <6>[ 1.121747] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10589 11:46:28.796812 <6>[ 1.130461] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10590 11:46:28.806561 <6>[ 1.139002] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10591 11:46:28.813249 <6>[ 1.147789] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10592 11:46:28.822863 <6>[ 1.156331] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10593 11:46:28.834387 <6>[ 1.171855] loop: module loaded
10594 11:46:28.840965 <6>[ 1.177754] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10595 11:46:28.863525 <4>[ 1.201016] mtk-pmic-keys: Failed to locate of_node [id: -1]
10596 11:46:28.870445 <6>[ 1.207736] megasas: 07.719.03.00-rc1
10597 11:46:28.880059 <6>[ 1.217169] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10598 11:46:28.887662 <6>[ 1.224655] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10599 11:46:28.904195 <6>[ 1.241388] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10600 11:46:28.960975 <6>[ 1.291410] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10601 11:46:30.873568 <6>[ 3.210778] Freeing initrd memory: 55048K
10602 11:46:30.883174 <6>[ 3.221009] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10603 11:46:30.894416 <6>[ 3.232138] tun: Universal TUN/TAP device driver, 1.6
10604 11:46:30.898066 <6>[ 3.238220] thunder_xcv, ver 1.0
10605 11:46:30.901241 <6>[ 3.241725] thunder_bgx, ver 1.0
10606 11:46:30.904588 <6>[ 3.245214] nicpf, ver 1.0
10607 11:46:30.914942 <6>[ 3.249242] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10608 11:46:30.918719 <6>[ 3.256723] hns3: Copyright (c) 2017 Huawei Corporation.
10609 11:46:30.925083 <6>[ 3.262311] hclge is initializing
10610 11:46:30.928385 <6>[ 3.265892] e1000: Intel(R) PRO/1000 Network Driver
10611 11:46:30.934902 <6>[ 3.271020] e1000: Copyright (c) 1999-2006 Intel Corporation.
10612 11:46:30.938256 <6>[ 3.277035] e1000e: Intel(R) PRO/1000 Network Driver
10613 11:46:30.945294 <6>[ 3.282252] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10614 11:46:30.951772 <6>[ 3.288441] igb: Intel(R) Gigabit Ethernet Network Driver
10615 11:46:30.958198 <6>[ 3.294096] igb: Copyright (c) 2007-2014 Intel Corporation.
10616 11:46:30.964509 <6>[ 3.299932] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10617 11:46:30.971513 <6>[ 3.306451] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10618 11:46:30.974551 <6>[ 3.312911] sky2: driver version 1.30
10619 11:46:30.981151 <6>[ 3.317912] VFIO - User Level meta-driver version: 0.3
10620 11:46:30.988583 <6>[ 3.326134] usbcore: registered new interface driver usb-storage
10621 11:46:30.994983 <6>[ 3.332580] usbcore: registered new device driver onboard-usb-hub
10622 11:46:31.004624 <6>[ 3.341704] mt6397-rtc mt6359-rtc: registered as rtc0
10623 11:46:31.014519 <6>[ 3.347193] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:46:30 UTC (1686829590)
10624 11:46:31.017693 <6>[ 3.356782] i2c_dev: i2c /dev entries driver
10625 11:46:31.034122 <6>[ 3.368537] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10626 11:46:31.041126 <6>[ 3.378775] sdhci: Secure Digital Host Controller Interface driver
10627 11:46:31.048149 <6>[ 3.385212] sdhci: Copyright(c) Pierre Ossman
10628 11:46:31.054450 <6>[ 3.390604] Synopsys Designware Multimedia Card Interface Driver
10629 11:46:31.057759 <6>[ 3.397200] mmc0: CQHCI version 5.10
10630 11:46:31.064096 <6>[ 3.397757] sdhci-pltfm: SDHCI platform and OF driver helper
10631 11:46:31.071191 <6>[ 3.409041] ledtrig-cpu: registered to indicate activity on CPUs
10632 11:46:31.082118 <6>[ 3.416408] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10633 11:46:31.088922 <6>[ 3.423800] usbcore: registered new interface driver usbhid
10634 11:46:31.091994 <6>[ 3.429633] usbhid: USB HID core driver
10635 11:46:31.098871 <6>[ 3.433882] spi_master spi0: will run message pump with realtime priority
10636 11:46:31.143196 <6>[ 3.473867] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10637 11:46:31.162405 <6>[ 3.489484] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10638 11:46:31.165702 <6>[ 3.503066] mmc0: Command Queue Engine enabled
10639 11:46:31.172867 <6>[ 3.504852] cros-ec-spi spi0.0: Chrome EC device registered
10640 11:46:31.179189 <6>[ 3.507835] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10641 11:46:31.182519 <6>[ 3.521089] mmcblk0: mmc0:0001 DA4128 116 GiB
10642 11:46:31.192771 <6>[ 3.530319] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10643 11:46:31.202934 <6>[ 3.532126] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10644 11:46:31.209181 <6>[ 3.537494] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10645 11:46:31.212720 <6>[ 3.547724] NET: Registered PF_PACKET protocol family
10646 11:46:31.219215 <6>[ 3.551621] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10647 11:46:31.222836 <6>[ 3.556247] 9pnet: Installing 9P2000 support
10648 11:46:31.229059 <6>[ 3.562202] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10649 11:46:31.235924 <5>[ 3.565927] Key type dns_resolver registered
10650 11:46:31.239288 <6>[ 3.577523] registered taskstats version 1
10651 11:46:31.245628 <5>[ 3.581940] Loading compiled-in X.509 certificates
10652 11:46:31.279359 <4>[ 3.610145] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 11:46:31.288938 <4>[ 3.620864] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10654 11:46:31.299837 <3>[ 3.633921] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10655 11:46:31.312198 <6>[ 3.649764] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10656 11:46:31.318848 <6>[ 3.656547] xhci-mtk 11200000.usb: xHCI Host Controller
10657 11:46:31.325363 <6>[ 3.662051] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10658 11:46:31.335384 <6>[ 3.669902] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10659 11:46:31.342207 <6>[ 3.679329] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10660 11:46:31.348691 <6>[ 3.685573] xhci-mtk 11200000.usb: xHCI Host Controller
10661 11:46:31.355338 <6>[ 3.691075] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10662 11:46:31.362222 <6>[ 3.698739] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10663 11:46:31.369223 <6>[ 3.706621] hub 1-0:1.0: USB hub found
10664 11:46:31.372332 <6>[ 3.710667] hub 1-0:1.0: 1 port detected
10665 11:46:31.382505 <6>[ 3.715014] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10666 11:46:31.385866 <6>[ 3.723827] hub 2-0:1.0: USB hub found
10667 11:46:31.389035 <6>[ 3.727871] hub 2-0:1.0: 1 port detected
10668 11:46:31.397413 <6>[ 3.735103] mtk-msdc 11f70000.mmc: Got CD GPIO
10669 11:46:31.415896 <6>[ 3.749706] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10670 11:46:31.422000 <6>[ 3.757738] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10671 11:46:31.432076 <4>[ 3.765715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10672 11:46:31.441832 <6>[ 3.775377] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10673 11:46:31.448581 <6>[ 3.783457] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10674 11:46:31.458365 <6>[ 3.791477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10675 11:46:31.465240 <6>[ 3.799398] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10676 11:46:31.471380 <6>[ 3.807220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10677 11:46:31.481618 <6>[ 3.815060] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10678 11:46:31.491400 <6>[ 3.825829] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10679 11:46:31.501590 <6>[ 3.834230] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10680 11:46:31.508460 <6>[ 3.842576] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10681 11:46:31.518355 <6>[ 3.850920] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10682 11:46:31.524604 <6>[ 3.859263] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10683 11:46:31.534379 <6>[ 3.867606] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10684 11:46:31.541481 <6>[ 3.875949] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10685 11:46:31.551134 <6>[ 3.884292] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10686 11:46:31.557814 <6>[ 3.892634] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10687 11:46:31.567460 <6>[ 3.900977] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10688 11:46:31.574428 <6>[ 3.909323] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10689 11:46:31.584184 <6>[ 3.917667] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10690 11:46:31.590627 <6>[ 3.926010] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10691 11:46:31.600363 <6>[ 3.934357] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10692 11:46:31.607373 <6>[ 3.942707] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10693 11:46:31.614179 <6>[ 3.951602] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10694 11:46:31.621274 <6>[ 3.959029] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10695 11:46:31.628324 <6>[ 3.966064] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10696 11:46:31.638993 <6>[ 3.973171] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10697 11:46:31.645565 <6>[ 3.980458] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10698 11:46:31.655584 <6>[ 3.987397] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10699 11:46:31.662332 <6>[ 3.996538] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10700 11:46:31.671896 <6>[ 4.005665] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10701 11:46:31.681977 <6>[ 4.014968] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10702 11:46:31.691618 <6>[ 4.024442] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10703 11:46:31.701947 <6>[ 4.033916] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10704 11:46:31.708218 <6>[ 4.043043] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10705 11:46:31.718432 <6>[ 4.052516] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10706 11:46:31.728147 <6>[ 4.061643] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10707 11:46:31.738452 <6>[ 4.070950] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10708 11:46:31.747913 <6>[ 4.081118] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10709 11:46:31.758879 <6>[ 4.093097] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10710 11:46:31.779419 <6>[ 4.113590] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10711 11:46:31.806318 <6>[ 4.144013] hub 2-1:1.0: USB hub found
10712 11:46:31.809585 <6>[ 4.148419] hub 2-1:1.0: 3 ports detected
10713 11:46:31.931350 <6>[ 4.265537] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10714 11:46:32.085841 <6>[ 4.423194] hub 1-1:1.0: USB hub found
10715 11:46:32.088864 <6>[ 4.427660] hub 1-1:1.0: 4 ports detected
10716 11:46:32.163462 <6>[ 4.497773] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10717 11:46:32.410858 <6>[ 4.745531] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10718 11:46:32.543765 <6>[ 4.881131] hub 1-1.4:1.0: USB hub found
10719 11:46:32.546425 <6>[ 4.885779] hub 1-1.4:1.0: 2 ports detected
10720 11:46:32.843042 <6>[ 5.177547] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10721 11:46:33.034885 <6>[ 5.369530] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10722 11:46:44.051833 <6>[ 16.394158] ALSA device list:
10723 11:46:44.058108 <6>[ 16.397417] No soundcards found.
10724 11:46:44.070932 <6>[ 16.409865] Freeing unused kernel memory: 8384K
10725 11:46:44.074107 <6>[ 16.414768] Run /init as init process
10726 11:46:44.104887 <6>[ 16.443665] NET: Registered PF_INET6 protocol family
10727 11:46:44.111776 <6>[ 16.450549] Segment Routing with IPv6
10728 11:46:44.114669 <6>[ 16.454518] In-situ OAM (IOAM) with IPv6
10729 11:46:44.149963 <30>[ 16.469063] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10730 11:46:44.153080 <30>[ 16.493106] systemd[1]: Detected architecture arm64.
10731 11:46:44.156359
10732 11:46:44.159536 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10733 11:46:44.159662
10734 11:46:44.174378 <30>[ 16.513709] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10735 11:46:44.321081 <30>[ 16.657106] systemd[1]: Queued start job for default target Graphical Interface.
10736 11:46:44.372043 <30>[ 16.710733] systemd[1]: Created slice system-getty.slice.
10737 11:46:44.377950 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10738 11:46:44.395327 <30>[ 16.734131] systemd[1]: Created slice system-modprobe.slice.
10739 11:46:44.401858 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10740 11:46:44.418910 <30>[ 16.758011] systemd[1]: Created slice system-serial\x2dgetty.slice.
10741 11:46:44.428860 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10742 11:46:44.443751 <30>[ 16.782573] systemd[1]: Created slice User and Session Slice.
10743 11:46:44.449878 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10744 11:46:44.470369 <30>[ 16.806072] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10745 11:46:44.480005 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10746 11:46:44.498100 <30>[ 16.834063] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10747 11:46:44.505252 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10748 11:46:44.525292 <30>[ 16.857625] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10749 11:46:44.531977 <30>[ 16.869663] systemd[1]: Reached target Local Encrypted Volumes.
10750 11:46:44.538198 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10751 11:46:44.555070 <30>[ 16.893890] systemd[1]: Reached target Paths.
10752 11:46:44.557992 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10753 11:46:44.574325 <30>[ 16.913621] systemd[1]: Reached target Remote File Systems.
10754 11:46:44.581225 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10755 11:46:44.594865 <30>[ 16.933555] systemd[1]: Reached target Slices.
10756 11:46:44.598134 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10757 11:46:44.614355 <30>[ 16.953576] systemd[1]: Reached target Swap.
10758 11:46:44.618118 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10759 11:46:44.638309 <30>[ 16.973856] systemd[1]: Listening on initctl Compatibility Named Pipe.
10760 11:46:44.644969 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10761 11:46:44.651557 <30>[ 16.988557] systemd[1]: Listening on Journal Audit Socket.
10762 11:46:44.657844 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10763 11:46:44.671052 <30>[ 17.009845] systemd[1]: Listening on Journal Socket (/dev/log).
10764 11:46:44.677352 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10765 11:46:44.695812 <30>[ 17.034321] systemd[1]: Listening on Journal Socket.
10766 11:46:44.702181 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10767 11:46:44.714583 <30>[ 17.053867] systemd[1]: Listening on udev Control Socket.
10768 11:46:44.721437 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10769 11:46:44.738991 <30>[ 17.078206] systemd[1]: Listening on udev Kernel Socket.
10770 11:46:44.745798 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10771 11:46:44.782698 <30>[ 17.121890] systemd[1]: Mounting Huge Pages File System...
10772 11:46:44.789133 Mounting [0;1;39mHuge Pages File System[0m...
10773 11:46:44.804935 <30>[ 17.143701] systemd[1]: Mounting POSIX Message Queue File System...
10774 11:46:44.811295 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10775 11:46:44.828482 <30>[ 17.167709] systemd[1]: Mounting Kernel Debug File System...
10776 11:46:44.835214 Mounting [0;1;39mKernel Debug File System[0m...
10777 11:46:44.854066 <30>[ 17.189898] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10778 11:46:44.894361 <30>[ 17.229851] systemd[1]: Starting Create list of static device nodes for the current kernel...
10779 11:46:44.900905 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10780 11:46:44.920902 <30>[ 17.259813] systemd[1]: Starting Load Kernel Module configfs...
10781 11:46:44.927257 Starting [0;1;39mLoad Kernel Module configfs[0m...
10782 11:46:44.944936 <30>[ 17.283906] systemd[1]: Starting Load Kernel Module drm...
10783 11:46:44.951213 Starting [0;1;39mLoad Kernel Module drm[0m...
10784 11:46:44.970103 <30>[ 17.305791] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10785 11:46:45.006911 <30>[ 17.346242] systemd[1]: Starting Journal Service...
10786 11:46:45.010137 Starting [0;1;39mJournal Service[0m...
10787 11:46:45.029529 <30>[ 17.368264] systemd[1]: Starting Load Kernel Modules...
10788 11:46:45.035726 Starting [0;1;39mLoad Kernel Modules[0m...
10789 11:46:45.056458 <30>[ 17.392123] systemd[1]: Starting Remount Root and Kernel File Systems...
10790 11:46:45.062653 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10791 11:46:45.077342 <30>[ 17.416014] systemd[1]: Starting Coldplug All udev Devices...
10792 11:46:45.083551 Starting [0;1;39mColdplug All udev Devices[0m...
10793 11:46:45.101506 <30>[ 17.440134] systemd[1]: Mounted Huge Pages File System.
10794 11:46:45.107875 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10795 11:46:45.123205 <30>[ 17.461999] systemd[1]: Started Journal Service.
10796 11:46:45.129632 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10797 11:46:45.144309 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10798 11:46:45.159255 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10799 11:46:45.179196 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10800 11:46:45.200456 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10801 11:46:45.220360 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10802 11:46:45.239654 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10803 11:46:45.263491 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10804 11:46:45.282396 See 'systemctl status systemd-remount-fs.service' for details.
10805 11:46:45.324202 Mounting [0;1;39mKernel Configuration File System[0m...
10806 11:46:45.344781 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10807 11:46:45.361807 <46>[ 17.697710] systemd-journald[176]: Received client request to flush runtime journal.
10808 11:46:45.370426 Starting [0;1;39mLoad/Save Random Seed[0m...
10809 11:46:45.389767 Starting [0;1;39mApply Kernel Variables[0m...
10810 11:46:45.406188 Starting [0;1;39mCreate System Users[0m...
10811 11:46:45.426861 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10812 11:46:45.446885 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10813 11:46:45.459509 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10814 11:46:45.475123 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10815 11:46:45.491574 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10816 11:46:45.507538 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10817 11:46:45.551232 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10818 11:46:45.574122 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10819 11:46:45.590540 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10820 11:46:45.610511 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10821 11:46:45.662873 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10822 11:46:45.690145 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10823 11:46:45.715661 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10824 11:46:45.735183 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10825 11:46:45.784880 Starting [0;1;39mNetwork Time Synchronization[0m...
10826 11:46:45.807579 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10827 11:46:45.848370 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10828 11:46:45.896898 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10829 11:46:45.928737 <6>[ 18.264743] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10830 11:46:45.937712 <6>[ 18.277076] remoteproc remoteproc0: scp is available
10831 11:46:45.947848 <4>[ 18.282796] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10832 11:46:45.957547 <6>[ 18.283696] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10833 11:46:45.961397 <6>[ 18.292670] remoteproc remoteproc0: powering up scp
10834 11:46:45.970693 <4>[ 18.292705] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10835 11:46:45.977745 <6>[ 18.293643] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10836 11:46:45.987649 <6>[ 18.293669] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10837 11:46:45.997655 <6>[ 18.293678] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10838 11:46:46.003966 <4>[ 18.324118] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10839 11:46:46.010484 <3>[ 18.331788] remoteproc remoteproc0: request_firmware failed: -2
10840 11:46:46.017259 <4>[ 18.340666] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10841 11:46:46.023719 <6>[ 18.348806] usbcore: registered new interface driver r8152
10842 11:46:46.026925 <6>[ 18.361536] mc: Linux media interface: v0.10
10843 11:46:46.040299 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd<3>[ 18.376936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 11:46:46.050347 _backlight[0m..<4>[ 18.377493] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10845 11:46:46.056893 <4>[ 18.377493] Fallback method does not support PEC.
10846 11:46:46.056976 .
10847 11:46:46.063403 <3>[ 18.385882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 11:46:46.073133 <3>[ 18.409103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10849 11:46:46.080358 <6>[ 18.410894] videodev: Linux video capture interface: v2.00
10850 11:46:46.087310 <3>[ 18.417443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 11:46:46.093847 <6>[ 18.423410] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10852 11:46:46.103833 <3>[ 18.431091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10853 11:46:46.110048 <3>[ 18.431100] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10854 11:46:46.116570 <3>[ 18.431114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10855 11:46:46.127239 <3>[ 18.431122] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10856 11:46:46.134373 <3>[ 18.431185] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 11:46:46.140813 <6>[ 18.438696] pci_bus 0000:00: root bus resource [bus 00-ff]
10858 11:46:46.147052 <3>[ 18.438880] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 11:46:46.156949 <3>[ 18.451345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 11:46:46.164096 <6>[ 18.453671] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10861 11:46:46.170759 <6>[ 18.454323] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10862 11:46:46.180645 <3>[ 18.462355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10863 11:46:46.190128 <6>[ 18.462520] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10864 11:46:46.200360 <6>[ 18.469867] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10865 11:46:46.210117 <6>[ 18.470898] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10866 11:46:46.216567 <6>[ 18.472009] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10867 11:46:46.226634 <3>[ 18.474488] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10868 11:46:46.236826 <3>[ 18.475308] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10869 11:46:46.243222 <3>[ 18.479174] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10870 11:46:46.249996 <6>[ 18.484485] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10871 11:46:46.257540 <3>[ 18.493352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10872 11:46:46.263865 <6>[ 18.501934] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10873 11:46:46.274669 <3>[ 18.508353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10874 11:46:46.281046 <3>[ 18.508373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10875 11:46:46.291771 <3>[ 18.508386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10876 11:46:46.298217 <3>[ 18.508395] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10877 11:46:46.301390 <6>[ 18.515722] pci 0000:00:00.0: supports D1 D2
10878 11:46:46.311320 <4>[ 18.517222] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10879 11:46:46.318373 <4>[ 18.517234] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10880 11:46:46.328455 <3>[ 18.524834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10881 11:46:46.335541 <6>[ 18.532965] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10882 11:46:46.341945 <6>[ 18.533497] usbcore: registered new interface driver cdc_ether
10883 11:46:46.345113 <6>[ 18.554141] usbcore: registered new interface driver r8153_ecm
10884 11:46:46.351669 <6>[ 18.554148] Bluetooth: Core ver 2.22
10885 11:46:46.355329 <6>[ 18.554227] NET: Registered PF_BLUETOOTH protocol family
10886 11:46:46.362163 <6>[ 18.554230] Bluetooth: HCI device and connection manager initialized
10887 11:46:46.369325 <6>[ 18.554242] Bluetooth: HCI socket layer initialized
10888 11:46:46.372325 <6>[ 18.554247] Bluetooth: L2CAP socket layer initialized
10889 11:46:46.378697 <6>[ 18.554259] Bluetooth: SCO socket layer initialized
10890 11:46:46.386020 <6>[ 18.563843] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10891 11:46:46.389358 <6>[ 18.570917] r8152 2-1.3:1.0 eth0: v1.12.13
10892 11:46:46.399503 <6>[ 18.572480] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10893 11:46:46.409617 <6>[ 18.573715] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10894 11:46:46.415779 <6>[ 18.573902] usbcore: registered new interface driver uvcvideo
10895 11:46:46.422687 <6>[ 18.580264] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10896 11:46:46.429091 <6>[ 18.595637] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10897 11:46:46.436223 <6>[ 18.602428] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10898 11:46:46.442716 <6>[ 18.604498] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10899 11:46:46.449847 <3>[ 18.607231] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 11:46:46.460209 <3>[ 18.607935] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10901 11:46:46.463974 <6>[ 18.610915] usbcore: registered new interface driver btusb
10902 11:46:46.474162 <4>[ 18.611373] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10903 11:46:46.480588 <3>[ 18.611385] Bluetooth: hci0: Failed to load firmware file (-2)
10904 11:46:46.487800 <3>[ 18.611389] Bluetooth: hci0: Failed to set up firmware (-2)
10905 11:46:46.498116 <4>[ 18.611393] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10906 11:46:46.504846 <6>[ 18.614337] remoteproc remoteproc0: powering up scp
10907 11:46:46.511180 <4>[ 18.614380] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10908 11:46:46.518047 <3>[ 18.614387] remoteproc remoteproc0: request_firmware failed: -2
10909 11:46:46.527738 <3>[ 18.614391] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10910 11:46:46.534118 <3>[ 18.617412] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 11:46:46.544225 <6>[ 18.617992] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10912 11:46:46.551235 <3>[ 18.638071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 11:46:46.557565 <6>[ 18.642236] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10914 11:46:46.567592 <3>[ 18.672875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 11:46:46.573880 <6>[ 18.678907] pci 0000:01:00.0: supports D1 D2
10916 11:46:46.580787 <3>[ 18.706136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 11:46:46.587307 <6>[ 18.706953] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10918 11:46:46.597064 <3>[ 18.736242] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 11:46:46.603545 <6>[ 18.753486] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10920 11:46:46.610496 <6>[ 18.948055] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10921 11:46:46.619989 <6>[ 18.956177] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10922 11:46:46.629851 [[0;32m OK [<6>[ 18.964378] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10923 11:46:46.640022 0m] Started [0;<6>[ 18.973648] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10924 11:46:46.646365 <6>[ 18.983032] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10925 11:46:46.653570 <6>[ 18.991042] pci 0000:00:00.0: PCI bridge to [bus 01]
10926 11:46:46.659875 <6>[ 18.996267] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10927 11:46:46.666309 1;39mNetwork Tim<6>[ 19.004483] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10928 11:46:46.676194 e Synchronizatio<6>[ 19.013098] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10929 11:46:46.676278 n[0m.
10930 11:46:46.683081 <6>[ 19.020320] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10931 11:46:46.704134 [[0;32m OK [0m] Finished [0<5>[ 19.038846] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10932 11:46:46.707294 ;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10933 11:46:46.722219 <5>[ 19.057930] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10934 11:46:46.728318 <4>[ 19.064831] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10935 11:46:46.735407 <6>[ 19.073736] cfg80211: failed to load regulatory.db
10936 11:46:46.741906 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10937 11:46:46.782744 <6>[ 19.118347] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10938 11:46:46.789298 <6>[ 19.125855] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10939 11:46:46.810021 <6>[ 19.149405] mt7921e 0000:01:00.0: ASIC revision: 79610010
10940 11:46:46.916301 <4>[ 19.249074] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10941 11:46:46.923332 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10942 11:46:46.938297 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10943 11:46:46.958038 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10944 11:46:46.974270 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10945 11:46:46.990377 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10946 11:46:47.010171 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10947 11:46:47.024304 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10948 11:46:47.034241 <4>[ 19.368365] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10949 11:46:47.045839 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10950 11:46:47.058746 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10951 11:46:47.074645 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10952 11:46:47.093642 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10953 11:46:47.155217 <4>[ 19.487913] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10954 11:46:47.161537 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10955 11:46:47.188972 Starting [0;1;39mUser Login Management[0m...
10956 11:46:47.204700 Starting [0;1;39mPermit User Sessions[0m...
10957 11:46:47.222205 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10958 11:46:47.238835 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10959 11:46:47.260824 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10960 11:46:47.273991 <4>[ 19.606694] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10961 11:46:47.307882 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10962 11:46:47.325341 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10963 11:46:47.342616 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10964 11:46:47.359958 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10965 11:46:47.366558 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10966 11:46:47.395017 [[0;32m OK [0m] Reached target [0;1;39mGrap<4>[ 19.728774] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 11:46:47.398697 hical Interface[0m.
10968 11:46:47.462788 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10969 11:46:47.487777 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10970 11:46:47.517270 <4>[ 19.850139] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10971 11:46:47.517380
10972 11:46:47.517446
10973 11:46:47.523725 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10974 11:46:47.523808
10975 11:46:47.526935 debian-bullseye-arm64 login: root (automatic login)
10976 11:46:47.527017
10977 11:46:47.527082
10978 11:46:47.552563 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
10979 11:46:47.552667
10980 11:46:47.558684 The programs included with the Debian GNU/Linux system are free software;
10981 11:46:47.565602 the exact distribution terms for each program are described in the
10982 11:46:47.568730 individual files in /usr/share/doc/*/copyright.
10983 11:46:47.568814
10984 11:46:47.575708 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10985 11:46:47.575791 permitted by applicable law.
10986 11:46:47.579316 Matched prompt #10: / #
10988 11:46:47.579578 Setting prompt string to ['/ #']
10989 11:46:47.579716 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10991 11:46:47.579956 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10992 11:46:47.580051 start: 2.2.6 expect-shell-connection (timeout 00:02:31) [common]
10993 11:46:47.580138 Setting prompt string to ['/ #']
10994 11:46:47.580199 Forcing a shell prompt, looking for ['/ #']
10996 11:46:47.630427 / #
10997 11:46:47.630564 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 11:46:47.630653 Waiting using forced prompt support (timeout 00:02:30)
10999 11:46:47.680115 <4>[ 19.972012] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11000 11:46:47.680228
11001 11:46:47.680496 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11002 11:46:47.680593 start: 2.2.7 export-device-env (timeout 00:02:31) [common]
11003 11:46:47.680688 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11004 11:46:47.680779 end: 2.2 depthcharge-retry (duration 00:02:29) [common]
11005 11:46:47.680860 end: 2 depthcharge-action (duration 00:02:29) [common]
11006 11:46:47.680950 start: 3 lava-test-retry (timeout 00:07:05) [common]
11007 11:46:47.681089 start: 3.1 lava-test-shell (timeout 00:07:05) [common]
11008 11:46:47.681207 Using namespace: common
11010 11:46:47.781488 / # #
11011 11:46:47.781665 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11012 11:46:47.781836 #<4>[ 20.092076] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11013 11:46:47.786994
11014 11:46:47.787287 Using /lava-10742252
11016 11:46:47.887599 / # export SHELL=/bin/sh
11017 11:46:47.887831 export SHELL=/bin/sh<4>[ 20.211703] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11018 11:46:47.893371
11020 11:46:47.993954 / # . /lava-10742252/environment
11021 11:46:48.036125 . /lava-10742252/environment<4>[ 20.331357] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11022 11:46:48.036259
11024 11:46:48.136797 / # /lava-10742252/bin/lava-test-runner /lava-10742252/0
11025 11:46:48.136982 Test shell timeout: 10s (minimum of the action and connection timeout)
11026 11:46:48.137537 /lava-10742252/bin/lava-test-runner /lava-10742252/0<3>[ 20.449507] mt7921e 0000:01:00.0: hardware init failed
11027 11:46:48.141774
11028 11:46:48.184109 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.506230] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10742252_1.5.2.3.1>
11029 11:46:48.184281 nfrost
11030 11:46:48.184390 + cd /lava-10742252/0/tests/0_igt-gpu-panfrost
11031 11:46:48.184486 + cat uuid
11032 11:46:48.184774 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10742252_1.5.2.3.1
11033 11:46:48.184884 Starting test lava.0_igt-gpu-panfrost (10742252_1.5.2.3.1)
11034 11:46:48.185008 Skipping test definition patterns.
11035 11:46:48.185155 + UUID=10742252_1.5.2.3.1
11036 11:46:48.185255 + set +x
11037 11:46:48.187705 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11038 11:46:48.197889 <8>[ 20.537083] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11039 11:46:48.198201 Received signal: <TESTSET> START panfrost_gem_new
11040 11:46:48.198324 Starting test_set panfrost_gem_new
11041 11:46:48.221434 <14>[ 20.560812] [IGT] panfrost_gem_new: executing
11042 11:46:48.231053 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.569083] [IGT] panfrost_gem_new: exiting, ret=77
11043 11:46:48.231168 .1.31 aarch64)
11044 11:46:48.244278 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.580992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11045 11:46:48.244540 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11047 11:46:48.247447 b/drmtest.c:621:
11048 11:46:48.247530 Test requirement: !(fd<0)
11049 11:46:48.254584 No known gpu found for chipset flags 0x32 (panfrost)
11050 11:46:48.257734 Last errno: 2, No such file or directory
11051 11:46:48.260907 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11052 11:46:48.268171 <14>[ 20.607499] [IGT] panfrost_gem_new: executing
11053 11:46:48.278187 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.615777] [IGT] panfrost_gem_new: exiting, ret=77
11054 11:46:48.278295 .1.31 aarch64)
11055 11:46:48.291471 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.627642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11056 11:46:48.291602 b/drmtest.c:621:
11057 11:46:48.291883 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11059 11:46:48.294541 Test requirement: !(fd<0)
11060 11:46:48.300861 No known gpu found for chipset flags 0x32 (panfrost)
11061 11:46:48.304127 Last errno: 2, No such file or directory
11062 11:46:48.308010 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11063 11:46:48.314372 <14>[ 20.653209] [IGT] panfrost_gem_new: executing
11064 11:46:48.323984 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.661276] [IGT] panfrost_gem_new: exiting, ret=77
11065 11:46:48.324090 .1.31 aarch64)
11066 11:46:48.337749 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.673344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11067 11:46:48.337841 b/drmtest.c:621:
11068 11:46:48.338087 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11070 11:46:48.344074 Test requireme<8>[ 20.683396] <LAVA_SIGNAL_TESTSET STOP>
11071 11:46:48.344167 nt: !(fd<0)
11072 11:46:48.344402 Received signal: <TESTSET> STOP
11073 11:46:48.344472 Closing test_set panfrost_gem_new
11074 11:46:48.350800 No known gpu found for chipset flags 0x32 (panfrost)
11075 11:46:48.354021 Last errno: 2, No such file or directory
11076 11:46:48.357331 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11077 11:46:48.370302 <8>[ 20.709719] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11078 11:46:48.370588 Received signal: <TESTSET> START panfrost_get_param
11079 11:46:48.370689 Starting test_set panfrost_get_param
11080 11:46:48.393971 <14>[ 20.733366] [IGT] panfrost_get_param: executing
11081 11:46:48.404114 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.741690] [IGT] panfrost_get_param: exiting, ret=77
11082 11:46:48.404208 .1.31 aarch64)
11083 11:46:48.416950 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.754091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11084 11:46:48.417237 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11086 11:46:48.420117 b/drmtest.c:621:
11087 11:46:48.420192 Test requirement: !(fd<0)
11088 11:46:48.427245 No known gpu found for chipset flags 0x32 (panfrost)
11089 11:46:48.430569 Last errno: 2, No such file or directory
11090 11:46:48.433260 [1mSubtest base-params: SKIP (0.000s)[0m
11091 11:46:48.441082 <14>[ 20.780352] [IGT] panfrost_get_param: executing
11092 11:46:48.450413 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.788744] [IGT] panfrost_get_param: exiting, ret=77
11093 11:46:48.450523 .1.31 aarch64)
11094 11:46:48.464197 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.801207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11095 11:46:48.464489 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11097 11:46:48.466945 b/drmtest.c:621:
11098 11:46:48.467053 Test requirement: !(fd<0)
11099 11:46:48.474240 No known gpu found for chipset flags 0x32 (panfrost)
11100 11:46:48.476886 Last errno: 2, No such file or directory
11101 11:46:48.480576 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11102 11:46:48.488268 <14>[ 20.827746] [IGT] panfrost_get_param: executing
11103 11:46:48.497843 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.836272] [IGT] panfrost_get_param: exiting, ret=77
11104 11:46:48.497957 .1.31 aarch64)
11105 11:46:48.511418 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.848243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11106 11:46:48.511712 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11108 11:46:48.514615 b/drmtest.c:621:
11109 11:46:48.517917 Test requireme<8>[ 20.858118] <LAVA_SIGNAL_TESTSET STOP>
11110 11:46:48.518189 Received signal: <TESTSET> STOP
11111 11:46:48.518282 Closing test_set panfrost_get_param
11112 11:46:48.521087 nt: !(fd<0)
11113 11:46:48.524821 No known gpu found for chipset flags 0x32 (panfrost)
11114 11:46:48.528087 Last errno: 2, No such file or directory
11115 11:46:48.531357 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11116 11:46:48.545666 <8>[ 20.885077] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11117 11:46:48.545926 Received signal: <TESTSET> START panfrost_prime
11118 11:46:48.546000 Starting test_set panfrost_prime
11119 11:46:48.569539 <14>[ 20.908757] [IGT] panfrost_prime: executing
11120 11:46:48.579205 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.916808] [IGT] panfrost_prime: exiting, ret=77
11121 11:46:48.579317 .1.31 aarch64)
11122 11:46:48.592604 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.928518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11123 11:46:48.592881 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11125 11:46:48.595883 b/drmtest.c:621:
11126 11:46:48.598913 Test requireme<8>[ 20.938795] <LAVA_SIGNAL_TESTSET STOP>
11127 11:46:48.599193 Received signal: <TESTSET> STOP
11128 11:46:48.599290 Closing test_set panfrost_prime
11129 11:46:48.601978 nt: !(fd<0)
11130 11:46:48.605741 No known gpu found for chipset flags 0x32 (panfrost)
11131 11:46:48.608875 Last errno: 2, No such file or directory
11132 11:46:48.612174 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11133 11:46:48.626118 <8>[ 20.965570] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11134 11:46:48.626374 Received signal: <TESTSET> START panfrost_submit
11135 11:46:48.626453 Starting test_set panfrost_submit
11136 11:46:48.649272 <14>[ 20.988996] [IGT] panfrost_submit: executing
11137 11:46:48.659727 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.997033] [IGT] panfrost_submit: exiting, ret=77
11138 11:46:48.659836 .1.31 aarch64)
11139 11:46:48.672278 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.009044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11140 11:46:48.672361 b/drmtest.c:621:
11141 11:46:48.672600 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11143 11:46:48.676184 Test requirement: !(fd<0)
11144 11:46:48.682756 No known gpu found for chipset flags 0x32 (panfrost)
11145 11:46:48.685903 Last errno: 2, No such file or directory
11146 11:46:48.689001 [1mSubtest pan-submit: SKIP (0.000s)[0m
11147 11:46:48.695512 <14>[ 21.035170] [IGT] panfrost_submit: executing
11148 11:46:48.705639 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 21.043426] [IGT] panfrost_submit: exiting, ret=77
11149 11:46:48.705727 .1.31 aarch64)
11150 11:46:48.718798 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.055271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11151 11:46:48.719060 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11153 11:46:48.722064 b/drmtest.c:621:
11154 11:46:48.722139 Test requirement: !(fd<0)
11155 11:46:48.729069 No known gpu found for chipset flags 0x32 (panfrost)
11156 11:46:48.732222 Last errno: 2, No such file or directory
11157 11:46:48.735387 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11158 11:46:48.742474 <14>[ 21.082083] [IGT] panfrost_submit: executing
11159 11:46:48.752769 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 21.090240] [IGT] panfrost_submit: exiting, ret=77
11160 11:46:48.752856 .1.31 aarch64)
11161 11:46:48.765455 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.102290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11162 11:46:48.765752 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11164 11:46:48.768693 b/drmtest.c:621:
11165 11:46:48.772024 Test requirement: !(fd<0)
11166 11:46:48.775388 No known gpu found for chipset flags 0x32 (panfrost)
11167 11:46:48.778720 Last errno: 2, No such file or directory
11168 11:46:48.785869 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11169 11:46:48.788723 <14>[ 21.130231] [IGT] panfrost_submit: executing
11170 11:46:48.798827 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 21.138371] [IGT] panfrost_submit: exiting, ret=77
11171 11:46:48.802215 .1.31 aarch64)
11172 11:46:48.815324 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.150316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11173 11:46:48.815413 b/drmtest.c:621:
11174 11:46:48.815657 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11176 11:46:48.818467 Test requirement: !(fd<0)
11177 11:46:48.825586 No known gpu found for chipset flags 0x32 (panfrost)
11178 11:46:48.828930 Last errno: 2, No such file or directory
11179 11:46:48.832112 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11180 11:46:48.838489 <14>[ 21.178231] [IGT] panfrost_submit: executing
11181 11:46:48.848727 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 21.186702] [IGT] panfrost_submit: exiting, ret=77
11182 11:46:48.848817 .1.31 aarch64)
11183 11:46:48.861782 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11185 11:46:48.864913 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.198299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11186 11:46:48.865041 b/drmtest.c:621:
11187 11:46:48.868748 Test requirement: !(fd<0)
11188 11:46:48.871888 No known gpu found for chipset flags 0x32 (panfrost)
11189 11:46:48.875123 Last errno: 2, No such file or directory
11190 11:46:48.881729 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11191 11:46:48.885030 <14>[ 21.226091] [IGT] panfrost_submit: executing
11192 11:46:48.894948 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 21.234174] [IGT] panfrost_submit: exiting, ret=77
11193 11:46:48.898119 .1.31 aarch64)
11194 11:46:48.911018 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.246097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11195 11:46:48.911147 b/drmtest.c:621:
11196 11:46:48.911434 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11198 11:46:48.914849 Test requirement: !(fd<0)
11199 11:46:48.921407 No known gpu found for chipset flags 0x32 (panfrost)
11200 11:46:48.924544 Last errno: 2, No such file or directory
11201 11:46:48.927926 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11202 11:46:48.934315 <14>[ 21.273786] [IGT] panfrost_submit: executing
11203 11:46:48.944516 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 21.281984] [IGT] panfrost_submit: exiting, ret=77
11204 11:46:48.944631 .1.31 aarch64)
11205 11:46:48.957475 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.294170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11206 11:46:48.957593 b/drmtest.c:621:
11207 11:46:48.957875 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11209 11:46:48.960706 Test requirement: !(fd<0)
11210 11:46:48.967651 No known gpu found for chipset flags 0x32 (panfrost)
11211 11:46:48.970925 Last errno: 2, No such file or directory
11212 11:46:48.974102 [1mSubtest pan-reset: SKIP (0.000s)[0m
11213 11:46:48.980750 <14>[ 21.319703] [IGT] panfrost_submit: executing
11214 11:46:48.990693 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 21.327965] [IGT] panfrost_submit: exiting, ret=77
11215 11:46:48.990820 .1.31 aarch64)
11216 11:46:49.003768 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.340018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11217 11:46:49.004057 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11219 11:46:49.006973 b/drmtest.c:621:
11220 11:46:49.007082 Test requirement: !(fd<0)
11221 11:46:49.013524 No known gpu found for chipset flags 0x32 (panfrost)
11222 11:46:49.016687 Last errno: 2, No such file or directory
11223 11:46:49.019756 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11224 11:46:49.027148 <14>[ 21.366601] [IGT] panfrost_submit: executing
11225 11:46:49.037182 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 21.374923] [IGT] panfrost_submit: exiting, ret=77
11226 11:46:49.037288 .1.31 aarch64)
11227 11:46:49.050410 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.386568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11228 11:46:49.050714 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11230 11:46:49.053646 b/drmtest.c:621:
11231 11:46:49.056830 Test requireme<8>[ 21.397088] <LAVA_SIGNAL_TESTSET STOP>
11232 11:46:49.057085 Received signal: <TESTSET> STOP
11233 11:46:49.057159 Closing test_set panfrost_submit
11234 11:46:49.059942 nt: !(fd<0)
11235 11:46:49.066763 No <8>[ 21.403115] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10742252_1.5.2.3.1>
11236 11:46:49.067018 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10742252_1.5.2.3.1
11237 11:46:49.067101 Ending use of test pattern.
11238 11:46:49.067163 Ending test lava.0_igt-gpu-panfrost (10742252_1.5.2.3.1), duration 0.88
11240 11:46:49.069916 known gpu found for chipset flags 0x32 (panfrost)
11241 11:46:49.073035 Last errno: 2, No such file or directory
11242 11:46:49.079992 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11243 11:46:49.080095 + set +x
11244 11:46:49.083298 <LAVA_TEST_RUNNER EXIT>
11245 11:46:49.083551 ok: lava_test_shell seems to have completed
11246 11:46:49.083865 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11247 11:46:49.083967 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11248 11:46:49.084058 end: 3 lava-test-retry (duration 00:00:01) [common]
11249 11:46:49.084146 start: 4 finalize (timeout 00:07:04) [common]
11250 11:46:49.084233 start: 4.1 power-off (timeout 00:00:30) [common]
11251 11:46:49.084391 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11252 11:46:49.160897 >> Command sent successfully.
11253 11:46:49.163267 Returned 0 in 0 seconds
11254 11:46:49.263660 end: 4.1 power-off (duration 00:00:00) [common]
11256 11:46:49.264114 start: 4.2 read-feedback (timeout 00:07:04) [common]
11257 11:46:49.264443 Listened to connection for namespace 'common' for up to 1s
11258 11:46:50.265341 Finalising connection for namespace 'common'
11259 11:46:50.265540 Disconnecting from shell: Finalise
11260 11:46:50.265656 / #
11261 11:46:50.365991 end: 4.2 read-feedback (duration 00:00:01) [common]
11262 11:46:50.366165 end: 4 finalize (duration 00:00:01) [common]
11263 11:46:50.366286 Cleaning after the job
11264 11:46:50.366385 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/ramdisk
11265 11:46:50.372470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/kernel
11266 11:46:50.378849 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/dtb
11267 11:46:50.379073 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742252/tftp-deploy-48ix2pz_/modules
11268 11:46:50.385018 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742252
11269 11:46:50.486960 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742252
11270 11:46:50.487137 Job finished correctly