Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
- Errors: 0
1 11:44:16.130622 lava-dispatcher, installed at version: 2023.05.1
2 11:44:16.130842 start: 0 validate
3 11:44:16.130981 Start time: 2023-06-15 11:44:16.130974+00:00 (UTC)
4 11:44:16.131116 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:44:16.131247 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 11:44:16.405024 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:44:16.405401 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:44:16.659060 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:44:16.659525 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:44:16.922166 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:44:16.923021 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:44:17.259247 validate duration: 1.13
14 11:44:17.260294 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:44:17.260780 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:44:17.261196 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:44:17.261737 Not decompressing ramdisk as can be used compressed.
18 11:44:17.262205 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230609.0/arm64/rootfs.cpio.gz
19 11:44:17.262542 saving as /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/ramdisk/rootfs.cpio.gz
20 11:44:17.262911 total size: 43386660 (41MB)
21 11:44:17.267842 progress 0% (0MB)
22 11:44:17.303323 progress 5% (2MB)
23 11:44:17.353130 progress 10% (4MB)
24 11:44:17.403726 progress 15% (6MB)
25 11:44:17.476335 progress 20% (8MB)
26 11:44:17.529137 progress 25% (10MB)
27 11:44:17.591837 progress 30% (12MB)
28 11:44:17.641844 progress 35% (14MB)
29 11:44:17.711877 progress 40% (16MB)
30 11:44:17.766582 progress 45% (18MB)
31 11:44:17.832947 progress 50% (20MB)
32 11:44:17.903433 progress 55% (22MB)
33 11:44:17.954505 progress 60% (24MB)
34 11:44:18.025328 progress 65% (26MB)
35 11:44:18.100264 progress 70% (28MB)
36 11:44:18.171925 progress 75% (31MB)
37 11:44:18.243284 progress 80% (33MB)
38 11:44:18.315102 progress 85% (35MB)
39 11:44:18.383084 progress 90% (37MB)
40 11:44:18.443097 progress 95% (39MB)
41 11:44:18.499412 progress 100% (41MB)
42 11:44:18.499582 41MB downloaded in 1.24s (33.46MB/s)
43 11:44:18.499759 end: 1.1.1 http-download (duration 00:00:01) [common]
45 11:44:18.500005 end: 1.1 download-retry (duration 00:00:01) [common]
46 11:44:18.500093 start: 1.2 download-retry (timeout 00:09:59) [common]
47 11:44:18.500186 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 11:44:18.500323 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:44:18.500408 saving as /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/kernel/Image
50 11:44:18.500471 total size: 47581696 (45MB)
51 11:44:18.500533 No compression specified
52 11:44:18.501696 progress 0% (0MB)
53 11:44:18.564708 progress 5% (2MB)
54 11:44:18.602876 progress 10% (4MB)
55 11:44:18.665793 progress 15% (6MB)
56 11:44:18.726380 progress 20% (9MB)
57 11:44:18.787309 progress 25% (11MB)
58 11:44:18.828195 progress 30% (13MB)
59 11:44:18.878083 progress 35% (15MB)
60 11:44:18.952129 progress 40% (18MB)
61 11:44:18.987438 progress 45% (20MB)
62 11:44:19.068285 progress 50% (22MB)
63 11:44:19.126650 progress 55% (24MB)
64 11:44:19.198968 progress 60% (27MB)
65 11:44:19.262387 progress 65% (29MB)
66 11:44:19.339376 progress 70% (31MB)
67 11:44:19.403294 progress 75% (34MB)
68 11:44:19.482124 progress 80% (36MB)
69 11:44:19.537410 progress 85% (38MB)
70 11:44:19.599943 progress 90% (40MB)
71 11:44:19.649777 progress 95% (43MB)
72 11:44:19.713025 progress 100% (45MB)
73 11:44:19.713234 45MB downloaded in 1.21s (37.42MB/s)
74 11:44:19.713491 end: 1.2.1 http-download (duration 00:00:01) [common]
76 11:44:19.713855 end: 1.2 download-retry (duration 00:00:01) [common]
77 11:44:19.713969 start: 1.3 download-retry (timeout 00:09:58) [common]
78 11:44:19.714083 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 11:44:19.714256 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:44:19.714359 saving as /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/dtb/mt8192-asurada-spherion-r0.dtb
81 11:44:19.714449 total size: 46924 (0MB)
82 11:44:19.714536 No compression specified
83 11:44:19.716443 progress 69% (0MB)
84 11:44:19.716739 progress 100% (0MB)
85 11:44:19.716917 0MB downloaded in 0.00s (18.15MB/s)
86 11:44:19.717083 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:44:19.717490 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:44:19.717603 start: 1.4 download-retry (timeout 00:09:58) [common]
90 11:44:19.717714 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 11:44:19.717854 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:44:19.717946 saving as /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/modules/modules.tar
93 11:44:19.718033 total size: 8555256 (8MB)
94 11:44:19.718118 Using unxz to decompress xz
95 11:44:19.721776 progress 0% (0MB)
96 11:44:19.761974 progress 5% (0MB)
97 11:44:19.802460 progress 10% (0MB)
98 11:44:19.848855 progress 15% (1MB)
99 11:44:19.906922 progress 20% (1MB)
100 11:44:19.950484 progress 25% (2MB)
101 11:44:19.975800 progress 30% (2MB)
102 11:44:20.017211 progress 35% (2MB)
103 11:44:20.055739 progress 40% (3MB)
104 11:44:20.094584 progress 45% (3MB)
105 11:44:20.156835 progress 50% (4MB)
106 11:44:20.234219 progress 55% (4MB)
107 11:44:20.260208 progress 60% (4MB)
108 11:44:20.305115 progress 65% (5MB)
109 11:44:20.345681 progress 70% (5MB)
110 11:44:20.383912 progress 75% (6MB)
111 11:44:20.421881 progress 80% (6MB)
112 11:44:20.458795 progress 85% (6MB)
113 11:44:20.533617 progress 90% (7MB)
114 11:44:20.596281 progress 95% (7MB)
115 11:44:20.622477 progress 100% (8MB)
116 11:44:20.626884 8MB downloaded in 0.91s (8.98MB/s)
117 11:44:20.627177 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:44:20.627446 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:44:20.627541 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 11:44:20.627634 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 11:44:20.627720 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:44:20.627814 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 11:44:20.628036 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h
125 11:44:20.628170 makedir: /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin
126 11:44:20.628273 makedir: /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/tests
127 11:44:20.628373 makedir: /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/results
128 11:44:20.628492 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-add-keys
129 11:44:20.628638 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-add-sources
130 11:44:20.628772 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-background-process-start
131 11:44:20.628904 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-background-process-stop
132 11:44:20.629028 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-common-functions
133 11:44:20.629150 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-echo-ipv4
134 11:44:20.629273 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-install-packages
135 11:44:20.629396 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-installed-packages
136 11:44:20.629518 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-os-build
137 11:44:20.629642 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-probe-channel
138 11:44:20.629764 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-probe-ip
139 11:44:20.629885 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-target-ip
140 11:44:20.630008 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-target-mac
141 11:44:20.630129 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-target-storage
142 11:44:20.630255 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-test-case
143 11:44:20.630382 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-test-event
144 11:44:20.630503 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-test-feedback
145 11:44:20.630626 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-test-raise
146 11:44:20.630753 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-test-reference
147 11:44:20.630887 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-test-runner
148 11:44:20.631011 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-test-set
149 11:44:20.631137 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-test-shell
150 11:44:20.631268 Updating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-install-packages (oe)
151 11:44:20.643776 Updating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/bin/lava-installed-packages (oe)
152 11:44:20.657508 Creating /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/environment
153 11:44:20.657683 LAVA metadata
154 11:44:20.657771 - LAVA_JOB_ID=10742256
155 11:44:20.657840 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:44:20.657967 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:57) [common]
157 11:44:20.658038 skipped lava-vland-overlay
158 11:44:20.658115 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:44:20.658199 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:57) [common]
160 11:44:20.658262 skipped lava-multinode-overlay
161 11:44:20.658338 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:44:20.658422 start: 1.5.2.3 test-definition (timeout 00:09:57) [common]
163 11:44:20.658524 Loading test definitions
164 11:44:20.658621 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:57) [common]
165 11:44:20.658697 Using /lava-10742256 at stage 0
166 11:44:20.659051 uuid=10742256_1.5.2.3.1 testdef=None
167 11:44:20.659142 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:44:20.659228 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
169 11:44:20.659751 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:44:20.659973 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
172 11:44:20.683480 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:44:20.683962 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
175 11:44:20.721449 runner path: /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/0/tests/0_igt-kms-mediatek test_uuid 10742256_1.5.2.3.1
176 11:44:20.721725 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:44:20.722041 Creating lava-test-runner.conf files
179 11:44:20.722149 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742256/lava-overlay-_4_7h36h/lava-10742256/0 for stage 0
180 11:44:20.722275 - 0_igt-kms-mediatek
181 11:44:20.722412 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:44:20.722535 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
183 11:44:20.731102 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:44:20.731249 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
185 11:44:20.731373 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:44:20.731498 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:44:20.731625 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
188 11:44:25.877405 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:05) [common]
189 11:44:25.877798 start: 1.5.4 extract-modules (timeout 00:09:51) [common]
190 11:44:25.877944 extracting modules file /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742256/extract-overlay-ramdisk-ar6yijeh/ramdisk
191 11:44:26.979459 end: 1.5.4 extract-modules (duration 00:00:01) [common]
192 11:44:26.979641 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
193 11:44:26.979783 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742256/compress-overlay-k7_0vcqz/overlay-1.5.2.4.tar.gz to ramdisk
194 11:44:26.979892 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742256/compress-overlay-k7_0vcqz/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742256/extract-overlay-ramdisk-ar6yijeh/ramdisk
195 11:44:26.986699 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:44:26.986862 start: 1.5.6 configure-preseed-file (timeout 00:09:50) [common]
197 11:44:26.986978 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:44:26.987094 start: 1.5.7 compress-ramdisk (timeout 00:09:50) [common]
199 11:44:26.987190 Building ramdisk /var/lib/lava/dispatcher/tmp/10742256/extract-overlay-ramdisk-ar6yijeh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742256/extract-overlay-ramdisk-ar6yijeh/ramdisk
200 11:44:34.476782 >> 369088 blocks
201 11:44:42.995713 rename /var/lib/lava/dispatcher/tmp/10742256/extract-overlay-ramdisk-ar6yijeh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/ramdisk/ramdisk.cpio.gz
202 11:44:42.996214 end: 1.5.7 compress-ramdisk (duration 00:00:16) [common]
203 11:44:42.996369 start: 1.5.8 prepare-kernel (timeout 00:09:34) [common]
204 11:44:42.996497 start: 1.5.8.1 prepare-fit (timeout 00:09:34) [common]
205 11:44:42.996637 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/kernel/Image'
206 11:45:03.081360 Returned 0 in 20 seconds
207 11:45:03.181962 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/kernel/image.itb
208 11:45:15.203219 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:45:15.203604 output: Created: Thu Jun 15 12:45:11 2023
210 11:45:15.203698 output: Image 0 (kernel-1)
211 11:45:15.203764 output: Description:
212 11:45:15.203856 output: Created: Thu Jun 15 12:45:11 2023
213 11:45:15.203945 output: Type: Kernel Image
214 11:45:15.204005 output: Compression: lzma compressed
215 11:45:15.204064 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
216 11:45:15.204121 output: Architecture: AArch64
217 11:45:15.204191 output: OS: Linux
218 11:45:15.204276 output: Load Address: 0x00000000
219 11:45:15.204329 output: Entry Point: 0x00000000
220 11:45:15.204383 output: Hash algo: crc32
221 11:45:15.204478 output: Hash value: cd22d0e5
222 11:45:15.204572 output: Image 1 (fdt-1)
223 11:45:15.204639 output: Description: mt8192-asurada-spherion-r0
224 11:45:15.204692 output: Created: Thu Jun 15 12:45:11 2023
225 11:45:15.204745 output: Type: Flat Device Tree
226 11:45:15.204797 output: Compression: uncompressed
227 11:45:15.204849 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:45:15.204901 output: Architecture: AArch64
229 11:45:15.204981 output: Hash algo: crc32
230 11:45:15.205060 output: Hash value: 1df858fa
231 11:45:15.205112 output: Image 2 (ramdisk-1)
232 11:45:15.205164 output: Description: unavailable
233 11:45:15.205244 output: Created: Thu Jun 15 12:45:11 2023
234 11:45:15.205297 output: Type: RAMDisk Image
235 11:45:15.205377 output: Compression: Unknown Compression
236 11:45:15.205429 output: Data Size: 56364637 Bytes = 55043.59 KiB = 53.75 MiB
237 11:45:15.205482 output: Architecture: AArch64
238 11:45:15.205534 output: OS: Linux
239 11:45:15.205585 output: Load Address: unavailable
240 11:45:15.205652 output: Entry Point: unavailable
241 11:45:15.205703 output: Hash algo: crc32
242 11:45:15.205782 output: Hash value: 5361f80c
243 11:45:15.205833 output: Default Configuration: 'conf-1'
244 11:45:15.205883 output: Configuration 0 (conf-1)
245 11:45:15.205963 output: Description: mt8192-asurada-spherion-r0
246 11:45:15.206014 output: Kernel: kernel-1
247 11:45:15.206065 output: Init Ramdisk: ramdisk-1
248 11:45:15.206132 output: FDT: fdt-1
249 11:45:15.206197 output: Loadables: kernel-1
250 11:45:15.206248 output:
251 11:45:15.206448 end: 1.5.8.1 prepare-fit (duration 00:00:32) [common]
252 11:45:15.206555 end: 1.5.8 prepare-kernel (duration 00:00:32) [common]
253 11:45:15.206660 end: 1.5 prepare-tftp-overlay (duration 00:00:55) [common]
254 11:45:15.206763 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:02) [common]
255 11:45:15.206853 No LXC device requested
256 11:45:15.206941 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:45:15.207034 start: 1.7 deploy-device-env (timeout 00:09:02) [common]
258 11:45:15.207116 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:45:15.207189 Checking files for TFTP limit of 4294967296 bytes.
260 11:45:15.207694 end: 1 tftp-deploy (duration 00:00:58) [common]
261 11:45:15.207802 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:45:15.207898 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:45:15.208023 substitutions:
264 11:45:15.208092 - {DTB}: 10742256/tftp-deploy-35vbjk6z/dtb/mt8192-asurada-spherion-r0.dtb
265 11:45:15.208160 - {INITRD}: 10742256/tftp-deploy-35vbjk6z/ramdisk/ramdisk.cpio.gz
266 11:45:15.208221 - {KERNEL}: 10742256/tftp-deploy-35vbjk6z/kernel/Image
267 11:45:15.208281 - {LAVA_MAC}: None
268 11:45:15.208339 - {PRESEED_CONFIG}: None
269 11:45:15.208396 - {PRESEED_LOCAL}: None
270 11:45:15.208452 - {RAMDISK}: 10742256/tftp-deploy-35vbjk6z/ramdisk/ramdisk.cpio.gz
271 11:45:15.208508 - {ROOT_PART}: None
272 11:45:15.208564 - {ROOT}: None
273 11:45:15.208619 - {SERVER_IP}: 192.168.201.1
274 11:45:15.208674 - {TEE}: None
275 11:45:15.208729 Parsed boot commands:
276 11:45:15.208784 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:45:15.208965 Parsed boot commands: tftpboot 192.168.201.1 10742256/tftp-deploy-35vbjk6z/kernel/image.itb 10742256/tftp-deploy-35vbjk6z/kernel/cmdline
278 11:45:15.209059 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:45:15.209151 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:45:15.209246 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:45:15.209339 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:45:15.209411 Not connected, no need to disconnect.
283 11:45:15.209487 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:45:15.209570 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:45:15.209641 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 11:45:15.212749 Setting prompt string to ['lava-test: # ']
287 11:45:15.213105 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:45:15.213220 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:45:15.213320 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:45:15.213417 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:45:15.213620 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 11:45:20.369788 >> Command sent successfully.
293 11:45:20.379897 Returned 0 in 5 seconds
294 11:45:20.481171 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:45:20.483858 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:45:20.484364 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:45:20.484818 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:45:20.485155 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:45:20.485495 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:45:20.486643 [Enter `^Ec?' for help]
302 11:45:20.644679
303 11:45:20.645257
304 11:45:20.645642 F0: 102B 0000
305 11:45:20.645988
306 11:45:20.646313 F3: 1001 0000 [0200]
307 11:45:20.647632
308 11:45:20.648093 F3: 1001 0000
309 11:45:20.648464
310 11:45:20.648803 F7: 102D 0000
311 11:45:20.649130
312 11:45:20.650809 F1: 0000 0000
313 11:45:20.651316
314 11:45:20.651718 V0: 0000 0000 [0001]
315 11:45:20.652088
316 11:45:20.654604 00: 0007 8000
317 11:45:20.655185
318 11:45:20.655574 01: 0000 0000
319 11:45:20.655970
320 11:45:20.657475 BP: 0C00 0209 [0000]
321 11:45:20.657945
322 11:45:20.658360 G0: 1182 0000
323 11:45:20.658711
324 11:45:20.660906 EC: 0000 0021 [4000]
325 11:45:20.661317
326 11:45:20.661656 S7: 0000 0000 [0000]
327 11:45:20.661975
328 11:45:20.664727 CC: 0000 0000 [0001]
329 11:45:20.665208
330 11:45:20.665578 T0: 0000 0040 [010F]
331 11:45:20.665932
332 11:45:20.666230 Jump to BL
333 11:45:20.667750
334 11:45:20.691417
335 11:45:20.691888
336 11:45:20.692253
337 11:45:20.698444 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:45:20.702067 ARM64: Exception handlers installed.
339 11:45:20.705391 ARM64: Testing exception
340 11:45:20.709189 ARM64: Done test exception
341 11:45:20.715593 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:45:20.725345 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:45:20.732318 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:45:20.742520 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:45:20.749324 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:45:20.759230 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:45:20.769660 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:45:20.775830 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:45:20.794068 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:45:20.797364 WDT: Last reset was cold boot
351 11:45:20.800605 SPI1(PAD0) initialized at 2873684 Hz
352 11:45:20.804655 SPI5(PAD0) initialized at 992727 Hz
353 11:45:20.807576 VBOOT: Loading verstage.
354 11:45:20.814014 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:45:20.817925 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:45:20.821327 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:45:20.824447 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:45:20.832041 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:45:20.838347 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:45:20.849614 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 11:45:20.850089
362 11:45:20.850455
363 11:45:20.858932 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:45:20.862620 ARM64: Exception handlers installed.
365 11:45:20.865842 ARM64: Testing exception
366 11:45:20.866408 ARM64: Done test exception
367 11:45:20.873255 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:45:20.877014 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:45:20.889930 Probing TPM: . done!
370 11:45:20.890524 TPM ready after 0 ms
371 11:45:20.897066 Connected to device vid:did:rid of 1ae0:0028:00
372 11:45:20.945904 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 11:45:20.946501 Initialized TPM device CR50 revision 0
374 11:45:20.957609 tlcl_send_startup: Startup return code is 0
375 11:45:20.958231 TPM: setup succeeded
376 11:45:20.969184 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:45:20.977931 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:45:20.989585 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:45:20.998438 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:45:21.001503 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:45:21.005678 in-header: 03 07 00 00 08 00 00 00
382 11:45:21.009324 in-data: aa e4 47 04 13 02 00 00
383 11:45:21.012828 Chrome EC: UHEPI supported
384 11:45:21.019583 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:45:21.023390 in-header: 03 9d 00 00 08 00 00 00
386 11:45:21.027091 in-data: 10 20 20 08 00 00 00 00
387 11:45:21.027527 Phase 1
388 11:45:21.030920 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:45:21.037777 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:45:21.044764 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:45:21.048504 Recovery requested (1009000e)
392 11:45:21.054922 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:45:21.059731 tlcl_extend: response is 0
394 11:45:21.067950 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:45:21.073226 tlcl_extend: response is 0
396 11:45:21.079984 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:45:21.101306 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 11:45:21.108487 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:45:21.109042
400 11:45:21.109411
401 11:45:21.116025 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:45:21.119445 ARM64: Exception handlers installed.
403 11:45:21.123096 ARM64: Testing exception
404 11:45:21.126224 ARM64: Done test exception
405 11:45:21.145857 pmic_efuse_setting: Set efuses in 11 msecs
406 11:45:21.149679 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:45:21.156760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:45:21.160669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:45:21.164412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:45:21.171449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:45:21.175110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:45:21.178956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:45:21.182395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:45:21.189708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:45:21.192876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:45:21.199587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:45:21.202436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:45:21.206322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:45:21.212667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:45:21.219316 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:45:21.222741 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:45:21.229453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:45:21.236287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:45:21.239241 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:45:21.246206 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:45:21.253572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:45:21.257570 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:45:21.264690 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:45:21.267855 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:45:21.274572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:45:21.277681 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:45:21.284915 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:45:21.292210 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:45:21.295493 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:45:21.299319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:45:21.305418 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:45:21.309009 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:45:21.316623 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:45:21.319953 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:45:21.323486 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:45:21.331316 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:45:21.334812 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:45:21.341681 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:45:21.344801 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:45:21.347959 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:45:21.354687 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:45:21.357756 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:45:21.361787 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:45:21.368185 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:45:21.371303 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:45:21.374461 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:45:21.381584 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:45:21.384823 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:45:21.387913 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:45:21.391021 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:45:21.397892 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:45:21.401088 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:45:21.407391 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:45:21.417954 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:45:21.421234 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:45:21.431081 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:45:21.437633 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:45:21.443774 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:45:21.447505 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:45:21.450373 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:45:21.458249 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2b
467 11:45:21.465123 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:45:21.468369 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:45:21.475234 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:45:21.483347 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 11:45:21.486454 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 11:45:21.493042 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 11:45:21.496771 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 11:45:21.499841 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 11:45:21.502939 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 11:45:21.506615 ADC[4]: Raw value=897410 ID=7
477 11:45:21.509750 ADC[3]: Raw value=213070 ID=1
478 11:45:21.513020 RAM Code: 0x71
479 11:45:21.516634 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 11:45:21.519567 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 11:45:21.530227 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 11:45:21.536579 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 11:45:21.540485 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 11:45:21.543357 in-header: 03 07 00 00 08 00 00 00
485 11:45:21.547124 in-data: aa e4 47 04 13 02 00 00
486 11:45:21.550104 Chrome EC: UHEPI supported
487 11:45:21.557131 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 11:45:21.560979 in-header: 03 d5 00 00 08 00 00 00
489 11:45:21.564128 in-data: 98 20 60 08 00 00 00 00
490 11:45:21.568071 MRC: failed to locate region type 0.
491 11:45:21.571722 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 11:45:21.574951 DRAM-K: Running full calibration
493 11:45:21.581932 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 11:45:21.584810 header.status = 0x0
495 11:45:21.588743 header.version = 0x6 (expected: 0x6)
496 11:45:21.592101 header.size = 0xd00 (expected: 0xd00)
497 11:45:21.592527 header.flags = 0x0
498 11:45:21.599303 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 11:45:21.616322 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
500 11:45:21.622661 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 11:45:21.626260 dram_init: ddr_geometry: 2
502 11:45:21.630129 [EMI] MDL number = 2
503 11:45:21.630598 [EMI] Get MDL freq = 0
504 11:45:21.633279 dram_init: ddr_type: 0
505 11:45:21.633745 is_discrete_lpddr4: 1
506 11:45:21.636539 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 11:45:21.637010
508 11:45:21.637376
509 11:45:21.639547 [Bian_co] ETT version 0.0.0.1
510 11:45:21.646413 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 11:45:21.647035
512 11:45:21.649237 dramc_set_vcore_voltage set vcore to 650000
513 11:45:21.652819 Read voltage for 800, 4
514 11:45:21.653292 Vio18 = 0
515 11:45:21.653662 Vcore = 650000
516 11:45:21.654008 Vdram = 0
517 11:45:21.656023 Vddq = 0
518 11:45:21.656488 Vmddr = 0
519 11:45:21.659858 dram_init: config_dvfs: 1
520 11:45:21.662795 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 11:45:21.669642 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 11:45:21.672943 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 11:45:21.675960 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 11:45:21.679487 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 11:45:21.682615 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 11:45:21.685796 MEM_TYPE=3, freq_sel=18
527 11:45:21.689432 sv_algorithm_assistance_LP4_1600
528 11:45:21.692582 ============ PULL DRAM RESETB DOWN ============
529 11:45:21.699078 ========== PULL DRAM RESETB DOWN end =========
530 11:45:21.702690 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 11:45:21.705872 ===================================
532 11:45:21.709415 LPDDR4 DRAM CONFIGURATION
533 11:45:21.712446 ===================================
534 11:45:21.712873 EX_ROW_EN[0] = 0x0
535 11:45:21.715537 EX_ROW_EN[1] = 0x0
536 11:45:21.715961 LP4Y_EN = 0x0
537 11:45:21.718727 WORK_FSP = 0x0
538 11:45:21.719140 WL = 0x2
539 11:45:21.722706 RL = 0x2
540 11:45:21.723180 BL = 0x2
541 11:45:21.725880 RPST = 0x0
542 11:45:21.726307 RD_PRE = 0x0
543 11:45:21.728973 WR_PRE = 0x1
544 11:45:21.732583 WR_PST = 0x0
545 11:45:21.733025 DBI_WR = 0x0
546 11:45:21.735785 DBI_RD = 0x0
547 11:45:21.736208 OTF = 0x1
548 11:45:21.738977 ===================================
549 11:45:21.742167 ===================================
550 11:45:21.742591 ANA top config
551 11:45:21.745618 ===================================
552 11:45:21.748671 DLL_ASYNC_EN = 0
553 11:45:21.752720 ALL_SLAVE_EN = 1
554 11:45:21.755581 NEW_RANK_MODE = 1
555 11:45:21.758996 DLL_IDLE_MODE = 1
556 11:45:21.759421 LP45_APHY_COMB_EN = 1
557 11:45:21.762583 TX_ODT_DIS = 1
558 11:45:21.766330 NEW_8X_MODE = 1
559 11:45:21.769378 ===================================
560 11:45:21.773192 ===================================
561 11:45:21.773623 data_rate = 1600
562 11:45:21.777135 CKR = 1
563 11:45:21.780317 DQ_P2S_RATIO = 8
564 11:45:21.783981 ===================================
565 11:45:21.787919 CA_P2S_RATIO = 8
566 11:45:21.788388 DQ_CA_OPEN = 0
567 11:45:21.791535 DQ_SEMI_OPEN = 0
568 11:45:21.795212 CA_SEMI_OPEN = 0
569 11:45:21.798941 CA_FULL_RATE = 0
570 11:45:21.799368 DQ_CKDIV4_EN = 1
571 11:45:21.802811 CA_CKDIV4_EN = 1
572 11:45:21.806509 CA_PREDIV_EN = 0
573 11:45:21.809855 PH8_DLY = 0
574 11:45:21.810323 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 11:45:21.813493 DQ_AAMCK_DIV = 4
576 11:45:21.817047 CA_AAMCK_DIV = 4
577 11:45:21.820912 CA_ADMCK_DIV = 4
578 11:45:21.821338 DQ_TRACK_CA_EN = 0
579 11:45:21.824100 CA_PICK = 800
580 11:45:21.827871 CA_MCKIO = 800
581 11:45:21.831733 MCKIO_SEMI = 0
582 11:45:21.835843 PLL_FREQ = 3068
583 11:45:21.836270 DQ_UI_PI_RATIO = 32
584 11:45:21.839115 CA_UI_PI_RATIO = 0
585 11:45:21.843055 ===================================
586 11:45:21.846870 ===================================
587 11:45:21.850000 memory_type:LPDDR4
588 11:45:21.850429 GP_NUM : 10
589 11:45:21.853208 SRAM_EN : 1
590 11:45:21.853631 MD32_EN : 0
591 11:45:21.856447 ===================================
592 11:45:21.860228 [ANA_INIT] >>>>>>>>>>>>>>
593 11:45:21.863085 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 11:45:21.866880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 11:45:21.869793 ===================================
596 11:45:21.873274 data_rate = 1600,PCW = 0X7600
597 11:45:21.876404 ===================================
598 11:45:21.879571 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:45:21.883396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 11:45:21.889604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 11:45:21.893190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 11:45:21.900040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 11:45:21.900484 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 11:45:21.903850 [ANA_INIT] flow start
605 11:45:21.906940 [ANA_INIT] PLL >>>>>>>>
606 11:45:21.907378 [ANA_INIT] PLL <<<<<<<<
607 11:45:21.910881 [ANA_INIT] MIDPI >>>>>>>>
608 11:45:21.914621 [ANA_INIT] MIDPI <<<<<<<<
609 11:45:21.915132 [ANA_INIT] DLL >>>>>>>>
610 11:45:21.917888 [ANA_INIT] flow end
611 11:45:21.921729 ============ LP4 DIFF to SE enter ============
612 11:45:21.925466 ============ LP4 DIFF to SE exit ============
613 11:45:21.929146 [ANA_INIT] <<<<<<<<<<<<<
614 11:45:21.933051 [Flow] Enable top DCM control >>>>>
615 11:45:21.933478 [Flow] Enable top DCM control <<<<<
616 11:45:21.936154 Enable DLL master slave shuffle
617 11:45:21.943536 ==============================================================
618 11:45:21.943965 Gating Mode config
619 11:45:21.949873 ==============================================================
620 11:45:21.953574 Config description:
621 11:45:21.959946 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 11:45:21.966752 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 11:45:21.973430 SELPH_MODE 0: By rank 1: By Phase
624 11:45:21.979937 ==============================================================
625 11:45:21.980364 GAT_TRACK_EN = 1
626 11:45:21.983086 RX_GATING_MODE = 2
627 11:45:21.986328 RX_GATING_TRACK_MODE = 2
628 11:45:21.990004 SELPH_MODE = 1
629 11:45:21.993267 PICG_EARLY_EN = 1
630 11:45:21.996527 VALID_LAT_VALUE = 1
631 11:45:22.002951 ==============================================================
632 11:45:22.006772 Enter into Gating configuration >>>>
633 11:45:22.009847 Exit from Gating configuration <<<<
634 11:45:22.013080 Enter into DVFS_PRE_config >>>>>
635 11:45:22.023085 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 11:45:22.026141 Exit from DVFS_PRE_config <<<<<
637 11:45:22.029851 Enter into PICG configuration >>>>
638 11:45:22.033046 Exit from PICG configuration <<<<
639 11:45:22.036254 [RX_INPUT] configuration >>>>>
640 11:45:22.036676 [RX_INPUT] configuration <<<<<
641 11:45:22.043180 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 11:45:22.049987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 11:45:22.056551 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 11:45:22.059752 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 11:45:22.066275 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 11:45:22.073074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 11:45:22.076103 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 11:45:22.079236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 11:45:22.086404 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 11:45:22.089696 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 11:45:22.092725 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 11:45:22.099640 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 11:45:22.102658 ===================================
654 11:45:22.103258 LPDDR4 DRAM CONFIGURATION
655 11:45:22.106463 ===================================
656 11:45:22.109549 EX_ROW_EN[0] = 0x0
657 11:45:22.110098 EX_ROW_EN[1] = 0x0
658 11:45:22.113289 LP4Y_EN = 0x0
659 11:45:22.113760 WORK_FSP = 0x0
660 11:45:22.116405 WL = 0x2
661 11:45:22.119662 RL = 0x2
662 11:45:22.120277 BL = 0x2
663 11:45:22.122727 RPST = 0x0
664 11:45:22.123257 RD_PRE = 0x0
665 11:45:22.125837 WR_PRE = 0x1
666 11:45:22.126311 WR_PST = 0x0
667 11:45:22.129604 DBI_WR = 0x0
668 11:45:22.130022 DBI_RD = 0x0
669 11:45:22.132805 OTF = 0x1
670 11:45:22.136429 ===================================
671 11:45:22.139595 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 11:45:22.142892 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 11:45:22.149148 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 11:45:22.149572 ===================================
675 11:45:22.152912 LPDDR4 DRAM CONFIGURATION
676 11:45:22.155862 ===================================
677 11:45:22.159027 EX_ROW_EN[0] = 0x10
678 11:45:22.159495 EX_ROW_EN[1] = 0x0
679 11:45:22.162569 LP4Y_EN = 0x0
680 11:45:22.163109 WORK_FSP = 0x0
681 11:45:22.165965 WL = 0x2
682 11:45:22.166442 RL = 0x2
683 11:45:22.169118 BL = 0x2
684 11:45:22.172508 RPST = 0x0
685 11:45:22.172938 RD_PRE = 0x0
686 11:45:22.175660 WR_PRE = 0x1
687 11:45:22.176157 WR_PST = 0x0
688 11:45:22.178766 DBI_WR = 0x0
689 11:45:22.179238 DBI_RD = 0x0
690 11:45:22.182437 OTF = 0x1
691 11:45:22.185431 ===================================
692 11:45:22.191945 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 11:45:22.195331 nWR fixed to 40
694 11:45:22.195808 [ModeRegInit_LP4] CH0 RK0
695 11:45:22.199106 [ModeRegInit_LP4] CH0 RK1
696 11:45:22.202056 [ModeRegInit_LP4] CH1 RK0
697 11:45:22.202486 [ModeRegInit_LP4] CH1 RK1
698 11:45:22.205419 match AC timing 13
699 11:45:22.208515 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 11:45:22.212376 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 11:45:22.218538 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 11:45:22.222204 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 11:45:22.228739 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 11:45:22.229228 [EMI DOE] emi_dcm 0
705 11:45:22.231926 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 11:45:22.235538 ==
707 11:45:22.238755 Dram Type= 6, Freq= 0, CH_0, rank 0
708 11:45:22.241854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 11:45:22.242334 ==
710 11:45:22.248801 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 11:45:22.251918 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 11:45:22.262249 [CA 0] Center 38 (7~69) winsize 63
713 11:45:22.265426 [CA 1] Center 37 (7~68) winsize 62
714 11:45:22.268661 [CA 2] Center 35 (5~66) winsize 62
715 11:45:22.271808 [CA 3] Center 35 (5~66) winsize 62
716 11:45:22.275426 [CA 4] Center 34 (4~65) winsize 62
717 11:45:22.278509 [CA 5] Center 34 (4~65) winsize 62
718 11:45:22.279140
719 11:45:22.281580 [CmdBusTrainingLP45] Vref(ca) range 1: 30
720 11:45:22.282062
721 11:45:22.285385 [CATrainingPosCal] consider 1 rank data
722 11:45:22.288527 u2DelayCellTimex100 = 270/100 ps
723 11:45:22.292137 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 11:45:22.298596 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 11:45:22.301856 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 11:45:22.304990 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 11:45:22.308254 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 11:45:22.311466 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 11:45:22.311882
730 11:45:22.314608 CA PerBit enable=1, Macro0, CA PI delay=34
731 11:45:22.314994
732 11:45:22.318464 [CBTSetCACLKResult] CA Dly = 34
733 11:45:22.321388 CS Dly: 6 (0~37)
734 11:45:22.321895 ==
735 11:45:22.324612 Dram Type= 6, Freq= 0, CH_0, rank 1
736 11:45:22.328275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 11:45:22.328737 ==
738 11:45:22.334458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 11:45:22.338185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 11:45:22.348783 [CA 0] Center 38 (7~69) winsize 63
741 11:45:22.352589 [CA 1] Center 38 (7~69) winsize 63
742 11:45:22.355766 [CA 2] Center 35 (5~66) winsize 62
743 11:45:22.359732 [CA 3] Center 35 (5~66) winsize 62
744 11:45:22.363064 [CA 4] Center 34 (4~65) winsize 62
745 11:45:22.366812 [CA 5] Center 34 (4~65) winsize 62
746 11:45:22.367391
747 11:45:22.370562 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 11:45:22.370989
749 11:45:22.373660 [CATrainingPosCal] consider 2 rank data
750 11:45:22.377495 u2DelayCellTimex100 = 270/100 ps
751 11:45:22.381348 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 11:45:22.384793 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 11:45:22.388531 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 11:45:22.391871 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 11:45:22.395550 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 11:45:22.399088 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 11:45:22.399505
758 11:45:22.402627 CA PerBit enable=1, Macro0, CA PI delay=34
759 11:45:22.403082
760 11:45:22.406899 [CBTSetCACLKResult] CA Dly = 34
761 11:45:22.407317 CS Dly: 6 (0~37)
762 11:45:22.407643
763 11:45:22.410038 ----->DramcWriteLeveling(PI) begin...
764 11:45:22.410470 ==
765 11:45:22.413249 Dram Type= 6, Freq= 0, CH_0, rank 0
766 11:45:22.416907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 11:45:22.417460 ==
768 11:45:22.420119 Write leveling (Byte 0): 33 => 33
769 11:45:22.423872 Write leveling (Byte 1): 28 => 28
770 11:45:22.427064 DramcWriteLeveling(PI) end<-----
771 11:45:22.427445
772 11:45:22.427776 ==
773 11:45:22.430721 Dram Type= 6, Freq= 0, CH_0, rank 0
774 11:45:22.434585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 11:45:22.435072 ==
776 11:45:22.438290 [Gating] SW mode calibration
777 11:45:22.445857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 11:45:22.449551 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 11:45:22.453184 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 11:45:22.460909 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 11:45:22.464070 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 11:45:22.468312 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
783 11:45:22.471925 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 11:45:22.475072 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 11:45:22.478909 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 11:45:22.486477 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:45:22.490345 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:45:22.493711 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:45:22.497545 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:45:22.501186 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:45:22.508484 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:45:22.512108 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:45:22.515771 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:45:22.519241 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:45:22.523009 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:45:22.530079 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
797 11:45:22.533703 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 11:45:22.537565 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:45:22.541397 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
800 11:45:22.544983 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:45:22.552306 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:45:22.555547 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:45:22.559441 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:45:22.562518 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:45:22.570202 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:45:22.573936 0 9 12 | B1->B0 | 2625 3232 | 1 1 | (0 0) (1 1)
807 11:45:22.577465 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 11:45:22.581352 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 11:45:22.585244 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 11:45:22.588625 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 11:45:22.596429 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:45:22.600118 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:45:22.603989 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
814 11:45:22.607035 0 10 12 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
815 11:45:22.610595 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:45:22.618061 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:45:22.621979 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:45:22.625649 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:45:22.629203 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:45:22.632839 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:45:22.640155 0 11 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
822 11:45:22.643232 0 11 12 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
823 11:45:22.647127 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 11:45:22.650940 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 11:45:22.657722 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 11:45:22.661375 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 11:45:22.664984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:45:22.668863 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:45:22.675309 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 11:45:22.678460 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 11:45:22.682216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 11:45:22.688767 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 11:45:22.691848 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 11:45:22.695158 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:45:22.698380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:45:22.705286 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:45:22.708436 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:45:22.711787 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:45:22.718192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:45:22.721757 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:45:22.725458 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:45:22.731776 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:45:22.734909 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:45:22.738604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:45:22.745214 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 11:45:22.748374 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 11:45:22.751364 Total UI for P1: 0, mck2ui 16
848 11:45:22.754483 best dqsien dly found for B0: ( 0, 14, 8)
849 11:45:22.758649 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:45:22.761814 Total UI for P1: 0, mck2ui 16
851 11:45:22.764714 best dqsien dly found for B1: ( 0, 14, 12)
852 11:45:22.767871 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 11:45:22.771436 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 11:45:22.774442
855 11:45:22.778265 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 11:45:22.781376 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 11:45:22.784437 [Gating] SW calibration Done
858 11:45:22.784944 ==
859 11:45:22.787617 Dram Type= 6, Freq= 0, CH_0, rank 0
860 11:45:22.791428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 11:45:22.791933 ==
862 11:45:22.792438 RX Vref Scan: 0
863 11:45:22.792933
864 11:45:22.794800 RX Vref 0 -> 0, step: 1
865 11:45:22.795329
866 11:45:22.797990 RX Delay -130 -> 252, step: 16
867 11:45:22.801202 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 11:45:22.804396 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 11:45:22.811673 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 11:45:22.814904 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 11:45:22.817889 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 11:45:22.821025 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 11:45:22.824613 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 11:45:22.830897 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 11:45:22.834468 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 11:45:22.837590 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 11:45:22.840899 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 11:45:22.844679 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 11:45:22.850745 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 11:45:22.854252 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 11:45:22.857813 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 11:45:22.860945 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 11:45:22.861460 ==
884 11:45:22.864005 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:45:22.871061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 11:45:22.871580 ==
887 11:45:22.872048 DQS Delay:
888 11:45:22.874092 DQS0 = 0, DQS1 = 0
889 11:45:22.874574 DQM Delay:
890 11:45:22.875067 DQM0 = 82, DQM1 = 69
891 11:45:22.877076 DQ Delay:
892 11:45:22.880774 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 11:45:22.883675 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 11:45:22.887504 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 11:45:22.890914 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 11:45:22.891409
897 11:45:22.891861
898 11:45:22.892301 ==
899 11:45:22.894073 Dram Type= 6, Freq= 0, CH_0, rank 0
900 11:45:22.897343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 11:45:22.897813 ==
902 11:45:22.898155
903 11:45:22.898468
904 11:45:22.901114 TX Vref Scan disable
905 11:45:22.901541 == TX Byte 0 ==
906 11:45:22.907508 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
907 11:45:22.910723 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
908 11:45:22.911192 == TX Byte 1 ==
909 11:45:22.917936 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
910 11:45:22.921026 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
911 11:45:22.921489 ==
912 11:45:22.924284 Dram Type= 6, Freq= 0, CH_0, rank 0
913 11:45:22.927443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 11:45:22.927869 ==
915 11:45:22.942226 TX Vref=22, minBit 11, minWin=26, winSum=436
916 11:45:22.945266 TX Vref=24, minBit 0, minWin=27, winSum=445
917 11:45:22.948493 TX Vref=26, minBit 7, minWin=27, winSum=447
918 11:45:22.952277 TX Vref=28, minBit 5, minWin=27, winSum=448
919 11:45:22.955547 TX Vref=30, minBit 11, minWin=27, winSum=447
920 11:45:22.962096 TX Vref=32, minBit 2, minWin=27, winSum=441
921 11:45:22.965046 [TxChooseVref] Worse bit 5, Min win 27, Win sum 448, Final Vref 28
922 11:45:22.965475
923 11:45:22.968366 Final TX Range 1 Vref 28
924 11:45:22.968791
925 11:45:22.969122 ==
926 11:45:22.972268 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:45:22.975326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:45:22.978491 ==
929 11:45:22.978929
930 11:45:22.979170
931 11:45:22.979394 TX Vref Scan disable
932 11:45:22.982086 == TX Byte 0 ==
933 11:45:22.985249 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
934 11:45:22.992122 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
935 11:45:22.992396 == TX Byte 1 ==
936 11:45:22.995189 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
937 11:45:23.001856 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
938 11:45:23.002058
939 11:45:23.002170 [DATLAT]
940 11:45:23.002267 Freq=800, CH0 RK0
941 11:45:23.002363
942 11:45:23.005033 DATLAT Default: 0xa
943 11:45:23.005192 0, 0xFFFF, sum = 0
944 11:45:23.008858 1, 0xFFFF, sum = 0
945 11:45:23.008993 2, 0xFFFF, sum = 0
946 11:45:23.011956 3, 0xFFFF, sum = 0
947 11:45:23.015156 4, 0xFFFF, sum = 0
948 11:45:23.015268 5, 0xFFFF, sum = 0
949 11:45:23.018417 6, 0xFFFF, sum = 0
950 11:45:23.018538 7, 0xFFFF, sum = 0
951 11:45:23.021634 8, 0xFFFF, sum = 0
952 11:45:23.021773 9, 0x0, sum = 1
953 11:45:23.021874 10, 0x0, sum = 2
954 11:45:23.025436 11, 0x0, sum = 3
955 11:45:23.025556 12, 0x0, sum = 4
956 11:45:23.028655 best_step = 10
957 11:45:23.028772
958 11:45:23.028841 ==
959 11:45:23.031937 Dram Type= 6, Freq= 0, CH_0, rank 0
960 11:45:23.035450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 11:45:23.035636 ==
962 11:45:23.038518 RX Vref Scan: 1
963 11:45:23.038669
964 11:45:23.038765 Set Vref Range= 32 -> 127
965 11:45:23.038891
966 11:45:23.041878 RX Vref 32 -> 127, step: 1
967 11:45:23.041988
968 11:45:23.045192 RX Delay -111 -> 252, step: 8
969 11:45:23.045275
970 11:45:23.048855 Set Vref, RX VrefLevel [Byte0]: 32
971 11:45:23.051905 [Byte1]: 32
972 11:45:23.051987
973 11:45:23.055361 Set Vref, RX VrefLevel [Byte0]: 33
974 11:45:23.059057 [Byte1]: 33
975 11:45:23.062901
976 11:45:23.063515 Set Vref, RX VrefLevel [Byte0]: 34
977 11:45:23.066275 [Byte1]: 34
978 11:45:23.070571
979 11:45:23.071224 Set Vref, RX VrefLevel [Byte0]: 35
980 11:45:23.073706 [Byte1]: 35
981 11:45:23.078149
982 11:45:23.078632 Set Vref, RX VrefLevel [Byte0]: 36
983 11:45:23.081259 [Byte1]: 36
984 11:45:23.085731
985 11:45:23.086194 Set Vref, RX VrefLevel [Byte0]: 37
986 11:45:23.088939 [Byte1]: 37
987 11:45:23.093164
988 11:45:23.093627 Set Vref, RX VrefLevel [Byte0]: 38
989 11:45:23.096409 [Byte1]: 38
990 11:45:23.100777
991 11:45:23.101260 Set Vref, RX VrefLevel [Byte0]: 39
992 11:45:23.104286 [Byte1]: 39
993 11:45:23.108944
994 11:45:23.109364 Set Vref, RX VrefLevel [Byte0]: 40
995 11:45:23.112180 [Byte1]: 40
996 11:45:23.116621
997 11:45:23.117042 Set Vref, RX VrefLevel [Byte0]: 41
998 11:45:23.119740 [Byte1]: 41
999 11:45:23.124602
1000 11:45:23.125162 Set Vref, RX VrefLevel [Byte0]: 42
1001 11:45:23.127402 [Byte1]: 42
1002 11:45:23.131665
1003 11:45:23.132129 Set Vref, RX VrefLevel [Byte0]: 43
1004 11:45:23.134760 [Byte1]: 43
1005 11:45:23.139596
1006 11:45:23.140156 Set Vref, RX VrefLevel [Byte0]: 44
1007 11:45:23.142533 [Byte1]: 44
1008 11:45:23.147066
1009 11:45:23.147535 Set Vref, RX VrefLevel [Byte0]: 45
1010 11:45:23.150386 [Byte1]: 45
1011 11:45:23.154737
1012 11:45:23.155261 Set Vref, RX VrefLevel [Byte0]: 46
1013 11:45:23.157891 [Byte1]: 46
1014 11:45:23.162625
1015 11:45:23.163190 Set Vref, RX VrefLevel [Byte0]: 47
1016 11:45:23.165679 [Byte1]: 47
1017 11:45:23.170016
1018 11:45:23.170529 Set Vref, RX VrefLevel [Byte0]: 48
1019 11:45:23.172970 [Byte1]: 48
1020 11:45:23.177697
1021 11:45:23.178166 Set Vref, RX VrefLevel [Byte0]: 49
1022 11:45:23.180793 [Byte1]: 49
1023 11:45:23.185296
1024 11:45:23.185757 Set Vref, RX VrefLevel [Byte0]: 50
1025 11:45:23.188420 [Byte1]: 50
1026 11:45:23.192770
1027 11:45:23.193253 Set Vref, RX VrefLevel [Byte0]: 51
1028 11:45:23.196054 [Byte1]: 51
1029 11:45:23.200462
1030 11:45:23.200856 Set Vref, RX VrefLevel [Byte0]: 52
1031 11:45:23.203581 [Byte1]: 52
1032 11:45:23.208174
1033 11:45:23.208522 Set Vref, RX VrefLevel [Byte0]: 53
1034 11:45:23.211181 [Byte1]: 53
1035 11:45:23.215969
1036 11:45:23.216375 Set Vref, RX VrefLevel [Byte0]: 54
1037 11:45:23.219032 [Byte1]: 54
1038 11:45:23.223482
1039 11:45:23.223826 Set Vref, RX VrefLevel [Byte0]: 55
1040 11:45:23.226781 [Byte1]: 55
1041 11:45:23.231205
1042 11:45:23.231540 Set Vref, RX VrefLevel [Byte0]: 56
1043 11:45:23.234359 [Byte1]: 56
1044 11:45:23.238111
1045 11:45:23.241861 Set Vref, RX VrefLevel [Byte0]: 57
1046 11:45:23.244919 [Byte1]: 57
1047 11:45:23.245273
1048 11:45:23.248001 Set Vref, RX VrefLevel [Byte0]: 58
1049 11:45:23.251470 [Byte1]: 58
1050 11:45:23.251819
1051 11:45:23.255041 Set Vref, RX VrefLevel [Byte0]: 59
1052 11:45:23.257910 [Byte1]: 59
1053 11:45:23.261739
1054 11:45:23.262152 Set Vref, RX VrefLevel [Byte0]: 60
1055 11:45:23.264612 [Byte1]: 60
1056 11:45:23.269080
1057 11:45:23.269452 Set Vref, RX VrefLevel [Byte0]: 61
1058 11:45:23.272369 [Byte1]: 61
1059 11:45:23.276717
1060 11:45:23.277071 Set Vref, RX VrefLevel [Byte0]: 62
1061 11:45:23.279862 [Byte1]: 62
1062 11:45:23.284418
1063 11:45:23.284778 Set Vref, RX VrefLevel [Byte0]: 63
1064 11:45:23.287893 [Byte1]: 63
1065 11:45:23.292317
1066 11:45:23.292641 Set Vref, RX VrefLevel [Byte0]: 64
1067 11:45:23.295587 [Byte1]: 64
1068 11:45:23.299893
1069 11:45:23.300316 Set Vref, RX VrefLevel [Byte0]: 65
1070 11:45:23.302933 [Byte1]: 65
1071 11:45:23.307672
1072 11:45:23.308094 Set Vref, RX VrefLevel [Byte0]: 66
1073 11:45:23.310945 [Byte1]: 66
1074 11:45:23.315361
1075 11:45:23.315782 Set Vref, RX VrefLevel [Byte0]: 67
1076 11:45:23.318362 [Byte1]: 67
1077 11:45:23.322364
1078 11:45:23.322787 Set Vref, RX VrefLevel [Byte0]: 68
1079 11:45:23.326140 [Byte1]: 68
1080 11:45:23.330660
1081 11:45:23.331123 Set Vref, RX VrefLevel [Byte0]: 69
1082 11:45:23.333764 [Byte1]: 69
1083 11:45:23.337767
1084 11:45:23.338189 Set Vref, RX VrefLevel [Byte0]: 70
1085 11:45:23.341606 [Byte1]: 70
1086 11:45:23.345458
1087 11:45:23.345880 Set Vref, RX VrefLevel [Byte0]: 71
1088 11:45:23.349345 [Byte1]: 71
1089 11:45:23.353569
1090 11:45:23.354091 Set Vref, RX VrefLevel [Byte0]: 72
1091 11:45:23.356351 [Byte1]: 72
1092 11:45:23.360717
1093 11:45:23.361186 Set Vref, RX VrefLevel [Byte0]: 73
1094 11:45:23.364333 [Byte1]: 73
1095 11:45:23.368648
1096 11:45:23.369339 Set Vref, RX VrefLevel [Byte0]: 74
1097 11:45:23.371521 [Byte1]: 74
1098 11:45:23.376547
1099 11:45:23.377098 Set Vref, RX VrefLevel [Byte0]: 75
1100 11:45:23.379718 [Byte1]: 75
1101 11:45:23.383551
1102 11:45:23.384017 Set Vref, RX VrefLevel [Byte0]: 76
1103 11:45:23.387234 [Byte1]: 76
1104 11:45:23.391294
1105 11:45:23.391764 Set Vref, RX VrefLevel [Byte0]: 77
1106 11:45:23.394955 [Byte1]: 77
1107 11:45:23.399070
1108 11:45:23.399676 Set Vref, RX VrefLevel [Byte0]: 78
1109 11:45:23.402693 [Byte1]: 78
1110 11:45:23.406584
1111 11:45:23.407171 Set Vref, RX VrefLevel [Byte0]: 79
1112 11:45:23.410294 [Byte1]: 79
1113 11:45:23.414028
1114 11:45:23.414284 Set Vref, RX VrefLevel [Byte0]: 80
1115 11:45:23.417815 [Byte1]: 80
1116 11:45:23.421736
1117 11:45:23.421978 Set Vref, RX VrefLevel [Byte0]: 81
1118 11:45:23.425395 [Byte1]: 81
1119 11:45:23.429672
1120 11:45:23.429826 Final RX Vref Byte 0 = 59 to rank0
1121 11:45:23.433055 Final RX Vref Byte 1 = 55 to rank0
1122 11:45:23.436225 Final RX Vref Byte 0 = 59 to rank1
1123 11:45:23.439457 Final RX Vref Byte 1 = 55 to rank1==
1124 11:45:23.442617 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 11:45:23.449157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 11:45:23.449258 ==
1127 11:45:23.449325 DQS Delay:
1128 11:45:23.452306 DQS0 = 0, DQS1 = 0
1129 11:45:23.452390 DQM Delay:
1130 11:45:23.452458 DQM0 = 82, DQM1 = 68
1131 11:45:23.456206 DQ Delay:
1132 11:45:23.459236 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1133 11:45:23.462983 DQ4 =84, DQ5 =68, DQ6 =88, DQ7 =92
1134 11:45:23.465811 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1135 11:45:23.469388 DQ12 =72, DQ13 =76, DQ14 =76, DQ15 =76
1136 11:45:23.469836
1137 11:45:23.470470
1138 11:45:23.476175 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1139 11:45:23.479056 CH0 RK0: MR19=606, MR18=2525
1140 11:45:23.485927 CH0_RK0: MR19=0x606, MR18=0x2525, DQSOSC=400, MR23=63, INC=92, DEC=61
1141 11:45:23.486652
1142 11:45:23.489308 ----->DramcWriteLeveling(PI) begin...
1143 11:45:23.489873 ==
1144 11:45:23.492603 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 11:45:23.495915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 11:45:23.496526 ==
1147 11:45:23.499375 Write leveling (Byte 0): 32 => 32
1148 11:45:23.502383 Write leveling (Byte 1): 31 => 31
1149 11:45:23.505878 DramcWriteLeveling(PI) end<-----
1150 11:45:23.506607
1151 11:45:23.507290 ==
1152 11:45:23.508924 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 11:45:23.512908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 11:45:23.513523 ==
1155 11:45:23.515780 [Gating] SW mode calibration
1156 11:45:23.522058 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 11:45:23.529180 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 11:45:23.532140 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 11:45:23.539015 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 11:45:23.541989 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1161 11:45:23.545258 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:45:23.552200 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:45:23.555472 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:45:23.558720 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:45:23.564995 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:45:23.568906 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:45:23.611153 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:45:23.612098 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:45:23.612463 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:45:23.612777 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:45:23.613147 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:45:23.613520 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:45:23.613978 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:45:23.614309 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:45:23.614632 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1176 11:45:23.615127 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1177 11:45:23.618481 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:45:23.621639 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:45:23.625486 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:45:23.628778 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:45:23.635188 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:45:23.639070 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:45:23.642116 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:45:23.648476 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1185 11:45:23.652194 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1186 11:45:23.655502 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:45:23.661832 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:45:23.665058 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 11:45:23.668452 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 11:45:23.674722 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 11:45:23.678315 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1192 11:45:23.681454 0 10 8 | B1->B0 | 3030 2424 | 1 1 | (1 1) (1 0)
1193 11:45:23.688050 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1194 11:45:23.691560 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:45:23.694775 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:45:23.701804 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:45:23.704921 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:45:23.708042 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:45:23.714726 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1200 11:45:23.717824 0 11 8 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (1 1)
1201 11:45:23.721770 0 11 12 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1202 11:45:23.728532 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:45:23.731669 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:45:23.735644 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:45:23.739481 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 11:45:23.742479 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 11:45:23.749327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:45:23.752437 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1209 11:45:23.756256 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1210 11:45:23.762566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:45:23.765612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:45:23.768931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:45:23.775782 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:45:23.778876 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:45:23.782048 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:45:23.788859 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:45:23.791988 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:45:23.795560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:45:23.802145 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:45:23.805079 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:45:23.809010 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 11:45:23.815089 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 11:45:23.818703 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1224 11:45:23.821802 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1225 11:45:23.828202 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1226 11:45:23.828286 Total UI for P1: 0, mck2ui 16
1227 11:45:23.832013 best dqsien dly found for B0: ( 0, 14, 6)
1228 11:45:23.838797 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 11:45:23.842041 Total UI for P1: 0, mck2ui 16
1230 11:45:23.845099 best dqsien dly found for B1: ( 0, 14, 12)
1231 11:45:23.848256 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1232 11:45:23.851536 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1233 11:45:23.851619
1234 11:45:23.855177 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1235 11:45:23.858381 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1236 11:45:23.861470 [Gating] SW calibration Done
1237 11:45:23.861551 ==
1238 11:45:23.865253 Dram Type= 6, Freq= 0, CH_0, rank 1
1239 11:45:23.868494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1240 11:45:23.868578 ==
1241 11:45:23.871671 RX Vref Scan: 0
1242 11:45:23.871754
1243 11:45:23.875102 RX Vref 0 -> 0, step: 1
1244 11:45:23.875184
1245 11:45:23.875249 RX Delay -130 -> 252, step: 16
1246 11:45:23.881431 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1247 11:45:23.884695 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1248 11:45:23.888680 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1249 11:45:23.891679 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1250 11:45:23.895238 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1251 11:45:23.901798 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1252 11:45:23.904902 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1253 11:45:23.908536 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1254 11:45:23.911535 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1255 11:45:23.914712 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1256 11:45:23.921704 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1257 11:45:23.924681 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1258 11:45:23.927830 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1259 11:45:23.931622 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1260 11:45:23.937990 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1261 11:45:23.941036 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1262 11:45:23.941119 ==
1263 11:45:23.944506 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 11:45:23.947663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 11:45:23.947754 ==
1266 11:45:23.951336 DQS Delay:
1267 11:45:23.951418 DQS0 = 0, DQS1 = 0
1268 11:45:23.951482 DQM Delay:
1269 11:45:23.954587 DQM0 = 79, DQM1 = 72
1270 11:45:23.954660 DQ Delay:
1271 11:45:23.957806 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1272 11:45:23.961048 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =85
1273 11:45:23.964525 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1274 11:45:23.968101 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1275 11:45:23.968212
1276 11:45:23.968305
1277 11:45:23.968393 ==
1278 11:45:23.971219 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 11:45:23.977731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 11:45:23.977816 ==
1281 11:45:23.977882
1282 11:45:23.977942
1283 11:45:23.978000 TX Vref Scan disable
1284 11:45:23.980792 == TX Byte 0 ==
1285 11:45:23.984014 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1286 11:45:23.990937 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1287 11:45:23.991021 == TX Byte 1 ==
1288 11:45:23.994276 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1289 11:45:24.000906 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1290 11:45:24.000991 ==
1291 11:45:24.003914 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 11:45:24.007564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 11:45:24.007647 ==
1294 11:45:24.019686 TX Vref=22, minBit 9, minWin=26, winSum=432
1295 11:45:24.023562 TX Vref=24, minBit 1, minWin=27, winSum=437
1296 11:45:24.026726 TX Vref=26, minBit 1, minWin=27, winSum=440
1297 11:45:24.029871 TX Vref=28, minBit 3, minWin=27, winSum=442
1298 11:45:24.033032 TX Vref=30, minBit 10, minWin=27, winSum=445
1299 11:45:24.039943 TX Vref=32, minBit 1, minWin=27, winSum=440
1300 11:45:24.043158 [TxChooseVref] Worse bit 10, Min win 27, Win sum 445, Final Vref 30
1301 11:45:24.043262
1302 11:45:24.046123 Final TX Range 1 Vref 30
1303 11:45:24.046221
1304 11:45:24.046314 ==
1305 11:45:24.049784 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 11:45:24.052901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 11:45:24.056452 ==
1308 11:45:24.056536
1309 11:45:24.056626
1310 11:45:24.056687 TX Vref Scan disable
1311 11:45:24.060204 == TX Byte 0 ==
1312 11:45:24.063277 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1313 11:45:24.070175 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1314 11:45:24.070275 == TX Byte 1 ==
1315 11:45:24.073322 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1316 11:45:24.079851 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1317 11:45:24.079933
1318 11:45:24.079996 [DATLAT]
1319 11:45:24.080054 Freq=800, CH0 RK1
1320 11:45:24.080111
1321 11:45:24.082978 DATLAT Default: 0xa
1322 11:45:24.083070 0, 0xFFFF, sum = 0
1323 11:45:24.086352 1, 0xFFFF, sum = 0
1324 11:45:24.086434 2, 0xFFFF, sum = 0
1325 11:45:24.090152 3, 0xFFFF, sum = 0
1326 11:45:24.093232 4, 0xFFFF, sum = 0
1327 11:45:24.093311 5, 0xFFFF, sum = 0
1328 11:45:24.096517 6, 0xFFFF, sum = 0
1329 11:45:24.096597 7, 0xFFFF, sum = 0
1330 11:45:24.099742 8, 0xFFFF, sum = 0
1331 11:45:24.099839 9, 0x0, sum = 1
1332 11:45:24.102938 10, 0x0, sum = 2
1333 11:45:24.103020 11, 0x0, sum = 3
1334 11:45:24.103084 12, 0x0, sum = 4
1335 11:45:24.106699 best_step = 10
1336 11:45:24.106781
1337 11:45:24.106853 ==
1338 11:45:24.109705 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 11:45:24.113281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 11:45:24.113362 ==
1341 11:45:24.116439 RX Vref Scan: 0
1342 11:45:24.116519
1343 11:45:24.116582 RX Vref 0 -> 0, step: 1
1344 11:45:24.116641
1345 11:45:24.120056 RX Delay -111 -> 252, step: 8
1346 11:45:24.126923 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1347 11:45:24.130048 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1348 11:45:24.133697 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1349 11:45:24.136912 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1350 11:45:24.140288 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1351 11:45:24.146480 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1352 11:45:24.150184 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1353 11:45:24.153076 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1354 11:45:24.156715 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1355 11:45:24.159763 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1356 11:45:24.166767 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1357 11:45:24.169903 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1358 11:45:24.173177 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1359 11:45:24.176309 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1360 11:45:24.183051 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1361 11:45:24.186222 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1362 11:45:24.186302 ==
1363 11:45:24.189487 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 11:45:24.193231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 11:45:24.193310 ==
1366 11:45:24.196443 DQS Delay:
1367 11:45:24.196525 DQS0 = 0, DQS1 = 0
1368 11:45:24.196591 DQM Delay:
1369 11:45:24.199667 DQM0 = 80, DQM1 = 70
1370 11:45:24.199749 DQ Delay:
1371 11:45:24.202697 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1372 11:45:24.206539 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =92
1373 11:45:24.209207 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1374 11:45:24.212864 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
1375 11:45:24.212946
1376 11:45:24.213011
1377 11:45:24.222414 [DQSOSCAuto] RK1, (LSB)MR18= 0x441f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1378 11:45:24.226116 CH0 RK1: MR19=606, MR18=441F
1379 11:45:24.229211 CH0_RK1: MR19=0x606, MR18=0x441F, DQSOSC=392, MR23=63, INC=96, DEC=64
1380 11:45:24.232993 [RxdqsGatingPostProcess] freq 800
1381 11:45:24.239010 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1382 11:45:24.242658 Pre-setting of DQS Precalculation
1383 11:45:24.245909 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1384 11:45:24.245992 ==
1385 11:45:24.249031 Dram Type= 6, Freq= 0, CH_1, rank 0
1386 11:45:24.255497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 11:45:24.255581 ==
1388 11:45:24.259315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1389 11:45:24.265622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1390 11:45:24.275268 [CA 0] Center 36 (6~66) winsize 61
1391 11:45:24.278288 [CA 1] Center 36 (6~67) winsize 62
1392 11:45:24.281517 [CA 2] Center 34 (4~64) winsize 61
1393 11:45:24.285153 [CA 3] Center 34 (4~64) winsize 61
1394 11:45:24.288217 [CA 4] Center 34 (4~64) winsize 61
1395 11:45:24.291445 [CA 5] Center 33 (3~64) winsize 62
1396 11:45:24.291523
1397 11:45:24.295376 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1398 11:45:24.295457
1399 11:45:24.298570 [CATrainingPosCal] consider 1 rank data
1400 11:45:24.301746 u2DelayCellTimex100 = 270/100 ps
1401 11:45:24.304973 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1402 11:45:24.312012 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1403 11:45:24.315273 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1404 11:45:24.318610 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1405 11:45:24.321567 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1406 11:45:24.325286 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1407 11:45:24.325388
1408 11:45:24.328135 CA PerBit enable=1, Macro0, CA PI delay=33
1409 11:45:24.328240
1410 11:45:24.331804 [CBTSetCACLKResult] CA Dly = 33
1411 11:45:24.331887 CS Dly: 5 (0~36)
1412 11:45:24.334778 ==
1413 11:45:24.334868 Dram Type= 6, Freq= 0, CH_1, rank 1
1414 11:45:24.341484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 11:45:24.341579 ==
1416 11:45:24.344612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1417 11:45:24.351432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1418 11:45:24.361531 [CA 0] Center 36 (6~66) winsize 61
1419 11:45:24.364702 [CA 1] Center 36 (6~67) winsize 62
1420 11:45:24.368085 [CA 2] Center 34 (4~65) winsize 62
1421 11:45:24.371342 [CA 3] Center 33 (3~64) winsize 62
1422 11:45:24.374403 [CA 4] Center 34 (4~65) winsize 62
1423 11:45:24.377443 [CA 5] Center 33 (3~64) winsize 62
1424 11:45:24.377549
1425 11:45:24.381034 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1426 11:45:24.381135
1427 11:45:24.384744 [CATrainingPosCal] consider 2 rank data
1428 11:45:24.388803 u2DelayCellTimex100 = 270/100 ps
1429 11:45:24.391973 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1430 11:45:24.396235 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1431 11:45:24.399384 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1432 11:45:24.403123 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1433 11:45:24.406415 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1434 11:45:24.410365 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1435 11:45:24.410446
1436 11:45:24.413800 CA PerBit enable=1, Macro0, CA PI delay=33
1437 11:45:24.413902
1438 11:45:24.417727 [CBTSetCACLKResult] CA Dly = 33
1439 11:45:24.421374 CS Dly: 6 (0~38)
1440 11:45:24.421457
1441 11:45:24.421522 ----->DramcWriteLeveling(PI) begin...
1442 11:45:24.424498 ==
1443 11:45:24.427671 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 11:45:24.430633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 11:45:24.430737 ==
1446 11:45:24.434234 Write leveling (Byte 0): 28 => 28
1447 11:45:24.437300 Write leveling (Byte 1): 29 => 29
1448 11:45:24.441006 DramcWriteLeveling(PI) end<-----
1449 11:45:24.441084
1450 11:45:24.441149 ==
1451 11:45:24.444079 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 11:45:24.447737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 11:45:24.447822 ==
1454 11:45:24.450714 [Gating] SW mode calibration
1455 11:45:24.457603 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1456 11:45:24.463803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1457 11:45:24.467662 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1458 11:45:24.470340 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1459 11:45:24.477483 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1460 11:45:24.480554 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1461 11:45:24.483592 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:45:24.490492 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:45:24.493697 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:45:24.497524 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:45:24.503822 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:45:24.506947 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:45:24.510120 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:45:24.517197 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:45:24.520366 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:45:24.523553 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:45:24.530399 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:45:24.533690 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:45:24.536746 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:45:24.540374 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1475 11:45:24.546542 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:45:24.550091 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:45:24.553213 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:45:24.559882 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:45:24.563162 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:45:24.567006 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:45:24.573251 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:45:24.846607 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:45:24.846817 0 9 8 | B1->B0 | 2d2d 2727 | 1 0 | (1 1) (0 0)
1484 11:45:24.846955 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:45:24.847037 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 11:45:24.847127 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 11:45:24.847205 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 11:45:24.847278 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 11:45:24.847382 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 11:45:24.847478 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1491 11:45:24.847576 0 10 8 | B1->B0 | 2929 2929 | 0 0 | (1 0) (1 0)
1492 11:45:24.847705 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:45:24.847813 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:45:24.847909 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:45:24.847999 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:45:24.848090 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:45:24.848183 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:45:24.848273 0 11 4 | B1->B0 | 2b2b 2c2c | 0 1 | (1 1) (1 1)
1499 11:45:24.848365 0 11 8 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
1500 11:45:24.848455 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:45:24.848545 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:45:24.848639 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 11:45:24.848728 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 11:45:24.848818 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:45:24.848910 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 11:45:24.849000 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1507 11:45:24.849092 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1508 11:45:24.849182 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:45:24.849270 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:45:24.849362 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:45:24.849453 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:45:24.849545 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:45:24.849634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:45:24.849722 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:45:24.849814 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:45:24.849903 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:45:24.849991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:45:24.850082 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 11:45:24.850171 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:45:24.850259 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:45:24.850350 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 11:45:24.850438 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1523 11:45:24.850529 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1524 11:45:24.850619 Total UI for P1: 0, mck2ui 16
1525 11:45:24.850732 best dqsien dly found for B1: ( 0, 14, 4)
1526 11:45:24.850831 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 11:45:24.850936 Total UI for P1: 0, mck2ui 16
1528 11:45:24.851071 best dqsien dly found for B0: ( 0, 14, 8)
1529 11:45:24.851163 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1530 11:45:24.851260 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1531 11:45:24.851350
1532 11:45:24.851469 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1533 11:45:24.851563 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1534 11:45:24.851652 [Gating] SW calibration Done
1535 11:45:24.851741 ==
1536 11:45:24.851833 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 11:45:24.851922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1538 11:45:24.852016 ==
1539 11:45:24.852105 RX Vref Scan: 0
1540 11:45:24.852204
1541 11:45:24.852308 RX Vref 0 -> 0, step: 1
1542 11:45:24.852399
1543 11:45:24.852496 RX Delay -130 -> 252, step: 16
1544 11:45:24.852588 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1545 11:45:24.852678 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1546 11:45:24.852771 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1547 11:45:24.852860 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1548 11:45:24.852949 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1549 11:45:24.853040 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1550 11:45:24.853129 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1551 11:45:24.853241 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1552 11:45:24.853378 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1553 11:45:24.853500 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1554 11:45:24.853795 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1555 11:45:24.854464 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1556 11:45:24.857704 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1557 11:45:24.861435 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1558 11:45:24.867941 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1559 11:45:24.870918 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1560 11:45:24.871661 ==
1561 11:45:24.874580 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 11:45:24.878153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 11:45:24.878606 ==
1564 11:45:24.881192 DQS Delay:
1565 11:45:24.881878 DQS0 = 0, DQS1 = 0
1566 11:45:24.882475 DQM Delay:
1567 11:45:24.884573 DQM0 = 81, DQM1 = 76
1568 11:45:24.885169 DQ Delay:
1569 11:45:24.887586 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1570 11:45:24.891364 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1571 11:45:24.894570 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1572 11:45:24.897637 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1573 11:45:24.898241
1574 11:45:24.898811
1575 11:45:24.899427 ==
1576 11:45:24.901221 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 11:45:24.907418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 11:45:24.907966 ==
1579 11:45:24.908448
1580 11:45:24.908903
1581 11:45:24.909256 TX Vref Scan disable
1582 11:45:24.911216 == TX Byte 0 ==
1583 11:45:24.914296 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1584 11:45:24.920867 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1585 11:45:24.921146 == TX Byte 1 ==
1586 11:45:24.924010 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1587 11:45:24.930621 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1588 11:45:24.930804 ==
1589 11:45:24.934226 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 11:45:24.937309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 11:45:24.937423 ==
1592 11:45:24.949823 TX Vref=22, minBit 9, minWin=27, winSum=446
1593 11:45:24.952986 TX Vref=24, minBit 8, minWin=27, winSum=449
1594 11:45:24.956096 TX Vref=26, minBit 1, minWin=28, winSum=452
1595 11:45:24.959965 TX Vref=28, minBit 1, minWin=28, winSum=456
1596 11:45:24.962985 TX Vref=30, minBit 11, minWin=27, winSum=458
1597 11:45:24.966718 TX Vref=32, minBit 9, minWin=27, winSum=455
1598 11:45:24.973647 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 28
1599 11:45:24.973770
1600 11:45:24.976981 Final TX Range 1 Vref 28
1601 11:45:24.977057
1602 11:45:24.977119 ==
1603 11:45:24.979971 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 11:45:24.983332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 11:45:24.983419 ==
1606 11:45:24.983483
1607 11:45:24.983546
1608 11:45:24.986812 TX Vref Scan disable
1609 11:45:24.990236 == TX Byte 0 ==
1610 11:45:24.993166 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1611 11:45:24.996730 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1612 11:45:24.999875 == TX Byte 1 ==
1613 11:45:25.003435 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1614 11:45:25.006565 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1615 11:45:25.006642
1616 11:45:25.009726 [DATLAT]
1617 11:45:25.009800 Freq=800, CH1 RK0
1618 11:45:25.009870
1619 11:45:25.013516 DATLAT Default: 0xa
1620 11:45:25.013596 0, 0xFFFF, sum = 0
1621 11:45:25.016644 1, 0xFFFF, sum = 0
1622 11:45:25.016725 2, 0xFFFF, sum = 0
1623 11:45:25.019833 3, 0xFFFF, sum = 0
1624 11:45:25.019907 4, 0xFFFF, sum = 0
1625 11:45:25.023421 5, 0xFFFF, sum = 0
1626 11:45:25.023502 6, 0xFFFF, sum = 0
1627 11:45:25.026460 7, 0xFFFF, sum = 0
1628 11:45:25.029543 8, 0xFFFF, sum = 0
1629 11:45:25.029653 9, 0x0, sum = 1
1630 11:45:25.029746 10, 0x0, sum = 2
1631 11:45:25.033121 11, 0x0, sum = 3
1632 11:45:25.033197 12, 0x0, sum = 4
1633 11:45:25.036675 best_step = 10
1634 11:45:25.036754
1635 11:45:25.036818 ==
1636 11:45:25.039877 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 11:45:25.043285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 11:45:25.043362 ==
1639 11:45:25.046796 RX Vref Scan: 1
1640 11:45:25.046897
1641 11:45:25.046965 Set Vref Range= 32 -> 127
1642 11:45:25.047025
1643 11:45:25.049901 RX Vref 32 -> 127, step: 1
1644 11:45:25.050005
1645 11:45:25.053042 RX Delay -111 -> 252, step: 8
1646 11:45:25.053122
1647 11:45:25.056040 Set Vref, RX VrefLevel [Byte0]: 32
1648 11:45:25.059397 [Byte1]: 32
1649 11:45:25.059473
1650 11:45:25.062978 Set Vref, RX VrefLevel [Byte0]: 33
1651 11:45:25.066088 [Byte1]: 33
1652 11:45:25.069929
1653 11:45:25.070040 Set Vref, RX VrefLevel [Byte0]: 34
1654 11:45:25.073565 [Byte1]: 34
1655 11:45:25.077890
1656 11:45:25.078004 Set Vref, RX VrefLevel [Byte0]: 35
1657 11:45:25.080766 [Byte1]: 35
1658 11:45:25.085655
1659 11:45:25.085762 Set Vref, RX VrefLevel [Byte0]: 36
1660 11:45:25.088604 [Byte1]: 36
1661 11:45:25.093025
1662 11:45:25.093130 Set Vref, RX VrefLevel [Byte0]: 37
1663 11:45:25.096097 [Byte1]: 37
1664 11:45:25.100797
1665 11:45:25.100887 Set Vref, RX VrefLevel [Byte0]: 38
1666 11:45:25.103813 [Byte1]: 38
1667 11:45:25.108909
1668 11:45:25.109017 Set Vref, RX VrefLevel [Byte0]: 39
1669 11:45:25.111684 [Byte1]: 39
1670 11:45:25.115965
1671 11:45:25.116071 Set Vref, RX VrefLevel [Byte0]: 40
1672 11:45:25.119095 [Byte1]: 40
1673 11:45:25.123449
1674 11:45:25.123525 Set Vref, RX VrefLevel [Byte0]: 41
1675 11:45:25.127122 [Byte1]: 41
1676 11:45:25.131471
1677 11:45:25.131545 Set Vref, RX VrefLevel [Byte0]: 42
1678 11:45:25.134839 [Byte1]: 42
1679 11:45:25.138863
1680 11:45:25.138939 Set Vref, RX VrefLevel [Byte0]: 43
1681 11:45:25.142480 [Byte1]: 43
1682 11:45:25.146771
1683 11:45:25.146882 Set Vref, RX VrefLevel [Byte0]: 44
1684 11:45:25.149977 [Byte1]: 44
1685 11:45:25.154237
1686 11:45:25.154314 Set Vref, RX VrefLevel [Byte0]: 45
1687 11:45:25.157448 [Byte1]: 45
1688 11:45:25.161743
1689 11:45:25.161814 Set Vref, RX VrefLevel [Byte0]: 46
1690 11:45:25.164910 [Byte1]: 46
1691 11:45:25.169330
1692 11:45:25.169417 Set Vref, RX VrefLevel [Byte0]: 47
1693 11:45:25.173103 [Byte1]: 47
1694 11:45:25.177402
1695 11:45:25.177545 Set Vref, RX VrefLevel [Byte0]: 48
1696 11:45:25.180443 [Byte1]: 48
1697 11:45:25.184780
1698 11:45:25.184914 Set Vref, RX VrefLevel [Byte0]: 49
1699 11:45:25.187916 [Byte1]: 49
1700 11:45:25.192263
1701 11:45:25.192339 Set Vref, RX VrefLevel [Byte0]: 50
1702 11:45:25.195876 [Byte1]: 50
1703 11:45:25.199915
1704 11:45:25.200049 Set Vref, RX VrefLevel [Byte0]: 51
1705 11:45:25.203488 [Byte1]: 51
1706 11:45:25.207565
1707 11:45:25.207643 Set Vref, RX VrefLevel [Byte0]: 52
1708 11:45:25.211057 [Byte1]: 52
1709 11:45:25.215763
1710 11:45:25.215893 Set Vref, RX VrefLevel [Byte0]: 53
1711 11:45:25.218681 [Byte1]: 53
1712 11:45:25.222955
1713 11:45:25.223029 Set Vref, RX VrefLevel [Byte0]: 54
1714 11:45:25.226730 [Byte1]: 54
1715 11:45:25.230514
1716 11:45:25.230607 Set Vref, RX VrefLevel [Byte0]: 55
1717 11:45:25.234233 [Byte1]: 55
1718 11:45:25.238494
1719 11:45:25.238566 Set Vref, RX VrefLevel [Byte0]: 56
1720 11:45:25.241611 [Byte1]: 56
1721 11:45:25.245972
1722 11:45:25.246044 Set Vref, RX VrefLevel [Byte0]: 57
1723 11:45:25.249473 [Byte1]: 57
1724 11:45:25.253991
1725 11:45:25.254075 Set Vref, RX VrefLevel [Byte0]: 58
1726 11:45:25.257103 [Byte1]: 58
1727 11:45:25.261505
1728 11:45:25.261594 Set Vref, RX VrefLevel [Byte0]: 59
1729 11:45:25.264692 [Byte1]: 59
1730 11:45:25.269274
1731 11:45:25.269387 Set Vref, RX VrefLevel [Byte0]: 60
1732 11:45:25.272322 [Byte1]: 60
1733 11:45:25.276802
1734 11:45:25.276884 Set Vref, RX VrefLevel [Byte0]: 61
1735 11:45:25.279958 [Byte1]: 61
1736 11:45:25.284917
1737 11:45:25.284991 Set Vref, RX VrefLevel [Byte0]: 62
1738 11:45:25.287849 [Byte1]: 62
1739 11:45:25.292163
1740 11:45:25.292242 Set Vref, RX VrefLevel [Byte0]: 63
1741 11:45:25.295223 [Byte1]: 63
1742 11:45:25.299578
1743 11:45:25.299657 Set Vref, RX VrefLevel [Byte0]: 64
1744 11:45:25.303159 [Byte1]: 64
1745 11:45:25.307166
1746 11:45:25.307239 Set Vref, RX VrefLevel [Byte0]: 65
1747 11:45:25.310661 [Byte1]: 65
1748 11:45:25.314793
1749 11:45:25.314885 Set Vref, RX VrefLevel [Byte0]: 66
1750 11:45:25.317876 [Byte1]: 66
1751 11:45:25.322333
1752 11:45:25.322409 Set Vref, RX VrefLevel [Byte0]: 67
1753 11:45:25.325798 [Byte1]: 67
1754 11:45:25.330041
1755 11:45:25.330115 Set Vref, RX VrefLevel [Byte0]: 68
1756 11:45:25.333145 [Byte1]: 68
1757 11:45:25.337652
1758 11:45:25.337726 Set Vref, RX VrefLevel [Byte0]: 69
1759 11:45:25.341387 [Byte1]: 69
1760 11:45:25.345646
1761 11:45:25.345732 Set Vref, RX VrefLevel [Byte0]: 70
1762 11:45:25.348742 [Byte1]: 70
1763 11:45:25.353227
1764 11:45:25.353317 Set Vref, RX VrefLevel [Byte0]: 71
1765 11:45:25.356477 [Byte1]: 71
1766 11:45:25.360754
1767 11:45:25.360842 Set Vref, RX VrefLevel [Byte0]: 72
1768 11:45:25.363910 [Byte1]: 72
1769 11:45:25.368294
1770 11:45:25.368395 Set Vref, RX VrefLevel [Byte0]: 73
1771 11:45:25.371536 [Byte1]: 73
1772 11:45:25.376200
1773 11:45:25.376303 Set Vref, RX VrefLevel [Byte0]: 74
1774 11:45:25.379364 [Byte1]: 74
1775 11:45:25.383737
1776 11:45:25.383811 Set Vref, RX VrefLevel [Byte0]: 75
1777 11:45:25.386939 [Byte1]: 75
1778 11:45:25.391548
1779 11:45:25.391646 Set Vref, RX VrefLevel [Byte0]: 76
1780 11:45:25.394894 [Byte1]: 76
1781 11:45:25.399445
1782 11:45:25.399550 Final RX Vref Byte 0 = 54 to rank0
1783 11:45:25.402384 Final RX Vref Byte 1 = 53 to rank0
1784 11:45:25.405413 Final RX Vref Byte 0 = 54 to rank1
1785 11:45:25.408665 Final RX Vref Byte 1 = 53 to rank1==
1786 11:45:25.412350 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 11:45:25.418861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 11:45:25.418986 ==
1789 11:45:25.419084 DQS Delay:
1790 11:45:25.419173 DQS0 = 0, DQS1 = 0
1791 11:45:25.422317 DQM Delay:
1792 11:45:25.422402 DQM0 = 80, DQM1 = 71
1793 11:45:25.425749 DQ Delay:
1794 11:45:25.428693 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1795 11:45:25.432069 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1796 11:45:25.435310 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1797 11:45:25.438628 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1798 11:45:25.438722
1799 11:45:25.438788
1800 11:45:25.445724 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1801 11:45:25.448854 CH1 RK0: MR19=606, MR18=131D
1802 11:45:25.455133 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1803 11:45:25.455218
1804 11:45:25.458843 ----->DramcWriteLeveling(PI) begin...
1805 11:45:25.458927 ==
1806 11:45:25.461926 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 11:45:25.465206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 11:45:25.465291 ==
1809 11:45:25.468364 Write leveling (Byte 0): 29 => 29
1810 11:45:25.471629 Write leveling (Byte 1): 29 => 29
1811 11:45:25.475354 DramcWriteLeveling(PI) end<-----
1812 11:45:25.475438
1813 11:45:25.475503 ==
1814 11:45:25.478493 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 11:45:25.482136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 11:45:25.482219 ==
1817 11:45:25.485388 [Gating] SW mode calibration
1818 11:45:25.491710 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 11:45:25.498568 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 11:45:25.501634 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1821 11:45:25.508551 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1822 11:45:25.511537 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1823 11:45:25.515522 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:45:25.521614 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:45:25.524843 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:45:25.528485 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:45:25.531392 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:45:25.538238 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:45:25.541665 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:45:25.545094 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:45:25.551381 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:45:25.554946 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:45:25.558072 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:45:25.564960 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:45:25.567925 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:45:25.571691 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:45:25.577752 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1838 11:45:25.581063 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:45:25.584752 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:45:25.591523 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:45:25.594718 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:45:25.597916 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:45:25.604606 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:45:25.607992 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:45:25.610814 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1846 11:45:25.617704 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1847 11:45:25.621431 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 11:45:25.624635 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 11:45:25.630787 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 11:45:25.634572 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 11:45:25.637717 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 11:45:25.644543 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1853 11:45:25.647648 0 10 4 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (0 0)
1854 11:45:25.650716 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1855 11:45:25.657832 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:45:25.661140 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:45:25.664008 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:45:25.670710 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:45:25.674418 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:45:25.677641 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1861 11:45:25.684364 0 11 4 | B1->B0 | 2f2f 3838 | 0 0 | (0 0) (0 0)
1862 11:45:25.687550 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 11:45:25.690666 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 11:45:25.693816 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 11:45:25.700849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 11:45:25.704302 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 11:45:25.706982 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 11:45:25.713884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 11:45:25.717049 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1870 11:45:25.723811 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:45:25.727030 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:45:25.730210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:45:25.733389 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:45:25.740231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:45:25.743332 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:45:25.747099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:45:25.753559 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:45:25.756885 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 11:45:25.759930 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 11:45:25.766795 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 11:45:25.769732 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 11:45:25.773136 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 11:45:25.779837 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 11:45:25.783023 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 11:45:25.786818 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 11:45:25.792965 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1887 11:45:25.797026 Total UI for P1: 0, mck2ui 16
1888 11:45:25.799934 best dqsien dly found for B0: ( 0, 14, 6)
1889 11:45:25.803249 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 11:45:25.806326 Total UI for P1: 0, mck2ui 16
1891 11:45:25.809504 best dqsien dly found for B1: ( 0, 14, 8)
1892 11:45:25.813199 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1893 11:45:25.816518 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1894 11:45:25.816599
1895 11:45:25.819709 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 11:45:25.822741 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1897 11:45:25.826401 [Gating] SW calibration Done
1898 11:45:25.826481 ==
1899 11:45:25.829524 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 11:45:25.832768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 11:45:25.836459 ==
1902 11:45:25.836594 RX Vref Scan: 0
1903 11:45:25.836692
1904 11:45:25.839534 RX Vref 0 -> 0, step: 1
1905 11:45:25.839635
1906 11:45:25.842786 RX Delay -130 -> 252, step: 16
1907 11:45:25.845903 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1908 11:45:25.849677 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1909 11:45:25.852840 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1910 11:45:25.856291 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1911 11:45:25.862492 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1912 11:45:25.865750 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1913 11:45:25.869357 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1914 11:45:25.872865 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1915 11:45:25.875870 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1916 11:45:25.882339 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1917 11:45:25.885824 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1918 11:45:25.889395 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1919 11:45:25.892787 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1920 11:45:25.898982 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1921 11:45:25.902141 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1922 11:45:25.905824 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1923 11:45:25.905912 ==
1924 11:45:25.909048 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 11:45:25.912020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 11:45:25.912102 ==
1927 11:45:25.915724 DQS Delay:
1928 11:45:25.915803 DQS0 = 0, DQS1 = 0
1929 11:45:25.918973 DQM Delay:
1930 11:45:25.919053 DQM0 = 79, DQM1 = 74
1931 11:45:25.919116 DQ Delay:
1932 11:45:25.922075 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1933 11:45:25.925746 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1934 11:45:25.928755 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1935 11:45:25.931881 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1936 11:45:25.931961
1937 11:45:25.932024
1938 11:45:25.935669 ==
1939 11:45:25.935749 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 11:45:25.942224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 11:45:25.942304 ==
1942 11:45:25.942368
1943 11:45:25.942426
1944 11:45:25.945300 TX Vref Scan disable
1945 11:45:25.945380 == TX Byte 0 ==
1946 11:45:25.948500 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1947 11:45:25.955289 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1948 11:45:25.955369 == TX Byte 1 ==
1949 11:45:25.958460 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1950 11:45:25.965431 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1951 11:45:25.965511 ==
1952 11:45:25.968393 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 11:45:25.971866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 11:45:25.971946 ==
1955 11:45:25.985185 TX Vref=22, minBit 9, minWin=27, winSum=450
1956 11:45:25.988414 TX Vref=24, minBit 9, minWin=27, winSum=452
1957 11:45:25.991668 TX Vref=26, minBit 0, minWin=28, winSum=457
1958 11:45:25.995239 TX Vref=28, minBit 13, minWin=28, winSum=462
1959 11:45:25.998138 TX Vref=30, minBit 9, minWin=28, winSum=462
1960 11:45:26.004842 TX Vref=32, minBit 2, minWin=28, winSum=459
1961 11:45:26.008050 [TxChooseVref] Worse bit 13, Min win 28, Win sum 462, Final Vref 28
1962 11:45:26.008138
1963 11:45:26.011183 Final TX Range 1 Vref 28
1964 11:45:26.011254
1965 11:45:26.011313 ==
1966 11:45:26.014980 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 11:45:26.017913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 11:45:26.021003 ==
1969 11:45:26.021105
1970 11:45:26.021194
1971 11:45:26.021278 TX Vref Scan disable
1972 11:45:26.024864 == TX Byte 0 ==
1973 11:45:26.028018 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1974 11:45:26.034628 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1975 11:45:26.034701 == TX Byte 1 ==
1976 11:45:26.038491 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1977 11:45:26.044675 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1978 11:45:26.044757
1979 11:45:26.044817 [DATLAT]
1980 11:45:26.044874 Freq=800, CH1 RK1
1981 11:45:26.044941
1982 11:45:26.048218 DATLAT Default: 0xa
1983 11:45:26.048313 0, 0xFFFF, sum = 0
1984 11:45:26.051251 1, 0xFFFF, sum = 0
1985 11:45:26.055138 2, 0xFFFF, sum = 0
1986 11:45:26.055249 3, 0xFFFF, sum = 0
1987 11:45:26.058224 4, 0xFFFF, sum = 0
1988 11:45:26.058338 5, 0xFFFF, sum = 0
1989 11:45:26.061293 6, 0xFFFF, sum = 0
1990 11:45:26.061402 7, 0xFFFF, sum = 0
1991 11:45:26.064413 8, 0xFFFF, sum = 0
1992 11:45:26.064518 9, 0x0, sum = 1
1993 11:45:26.068164 10, 0x0, sum = 2
1994 11:45:26.068262 11, 0x0, sum = 3
1995 11:45:26.071326 12, 0x0, sum = 4
1996 11:45:26.071424 best_step = 10
1997 11:45:26.071516
1998 11:45:26.071603 ==
1999 11:45:26.074347 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 11:45:26.077906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 11:45:26.077993 ==
2002 11:45:26.081261 RX Vref Scan: 0
2003 11:45:26.081359
2004 11:45:26.084328 RX Vref 0 -> 0, step: 1
2005 11:45:26.084436
2006 11:45:26.084534 RX Delay -111 -> 252, step: 8
2007 11:45:26.091856 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2008 11:45:26.095220 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2009 11:45:26.098789 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2010 11:45:26.101758 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2011 11:45:26.104987 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2012 11:45:26.111484 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2013 11:45:26.115064 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2014 11:45:26.118113 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2015 11:45:26.122046 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2016 11:45:26.125208 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2017 11:45:26.131543 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2018 11:45:26.135178 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2019 11:45:26.138019 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2020 11:45:26.141782 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2021 11:45:26.148073 iDelay=209, Bit 14, Center 76 (-47 ~ 200) 248
2022 11:45:26.151639 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2023 11:45:26.151730 ==
2024 11:45:26.154732 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 11:45:26.157844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 11:45:26.157957 ==
2027 11:45:26.161097 DQS Delay:
2028 11:45:26.161203 DQS0 = 0, DQS1 = 0
2029 11:45:26.161293 DQM Delay:
2030 11:45:26.164783 DQM0 = 77, DQM1 = 73
2031 11:45:26.164864 DQ Delay:
2032 11:45:26.167945 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2033 11:45:26.171150 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2034 11:45:26.174373 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =64
2035 11:45:26.177536 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
2036 11:45:26.177641
2037 11:45:26.177732
2038 11:45:26.187775 [DQSOSCAuto] RK1, (LSB)MR18= 0x243b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2039 11:45:26.187858 CH1 RK1: MR19=606, MR18=243B
2040 11:45:26.194306 CH1_RK1: MR19=0x606, MR18=0x243B, DQSOSC=394, MR23=63, INC=95, DEC=63
2041 11:45:26.197975 [RxdqsGatingPostProcess] freq 800
2042 11:45:26.204363 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 11:45:26.207662 Pre-setting of DQS Precalculation
2044 11:45:26.211297 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 11:45:26.217914 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 11:45:26.227543 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 11:45:26.227625
2048 11:45:26.227689
2049 11:45:26.230591 [Calibration Summary] 1600 Mbps
2050 11:45:26.230673 CH 0, Rank 0
2051 11:45:26.234314 SW Impedance : PASS
2052 11:45:26.234396 DUTY Scan : NO K
2053 11:45:26.237380 ZQ Calibration : PASS
2054 11:45:26.240862 Jitter Meter : NO K
2055 11:45:26.240967 CBT Training : PASS
2056 11:45:26.244051 Write leveling : PASS
2057 11:45:26.247198 RX DQS gating : PASS
2058 11:45:26.247309 RX DQ/DQS(RDDQC) : PASS
2059 11:45:26.251080 TX DQ/DQS : PASS
2060 11:45:26.251161 RX DATLAT : PASS
2061 11:45:26.254135 RX DQ/DQS(Engine): PASS
2062 11:45:26.257277 TX OE : NO K
2063 11:45:26.257389 All Pass.
2064 11:45:26.257480
2065 11:45:26.257574 CH 0, Rank 1
2066 11:45:26.261033 SW Impedance : PASS
2067 11:45:26.264096 DUTY Scan : NO K
2068 11:45:26.264185 ZQ Calibration : PASS
2069 11:45:26.267250 Jitter Meter : NO K
2070 11:45:26.270244 CBT Training : PASS
2071 11:45:26.270341 Write leveling : PASS
2072 11:45:26.273970 RX DQS gating : PASS
2073 11:45:26.277283 RX DQ/DQS(RDDQC) : PASS
2074 11:45:26.277364 TX DQ/DQS : PASS
2075 11:45:26.280423 RX DATLAT : PASS
2076 11:45:26.283543 RX DQ/DQS(Engine): PASS
2077 11:45:26.283641 TX OE : NO K
2078 11:45:26.287309 All Pass.
2079 11:45:26.287389
2080 11:45:26.287452 CH 1, Rank 0
2081 11:45:26.290294 SW Impedance : PASS
2082 11:45:26.290375 DUTY Scan : NO K
2083 11:45:26.293853 ZQ Calibration : PASS
2084 11:45:26.297759 Jitter Meter : NO K
2085 11:45:26.297853 CBT Training : PASS
2086 11:45:26.300440 Write leveling : PASS
2087 11:45:26.303586 RX DQS gating : PASS
2088 11:45:26.303671 RX DQ/DQS(RDDQC) : PASS
2089 11:45:26.307535 TX DQ/DQS : PASS
2090 11:45:26.307608 RX DATLAT : PASS
2091 11:45:26.310345 RX DQ/DQS(Engine): PASS
2092 11:45:26.314029 TX OE : NO K
2093 11:45:26.314103 All Pass.
2094 11:45:26.314172
2095 11:45:26.314230 CH 1, Rank 1
2096 11:45:26.317089 SW Impedance : PASS
2097 11:45:26.320268 DUTY Scan : NO K
2098 11:45:26.320338 ZQ Calibration : PASS
2099 11:45:26.323907 Jitter Meter : NO K
2100 11:45:26.327022 CBT Training : PASS
2101 11:45:26.327098 Write leveling : PASS
2102 11:45:26.330243 RX DQS gating : PASS
2103 11:45:26.333492 RX DQ/DQS(RDDQC) : PASS
2104 11:45:26.333563 TX DQ/DQS : PASS
2105 11:45:26.336772 RX DATLAT : PASS
2106 11:45:26.340608 RX DQ/DQS(Engine): PASS
2107 11:45:26.340676 TX OE : NO K
2108 11:45:26.343605 All Pass.
2109 11:45:26.343673
2110 11:45:26.343738 DramC Write-DBI off
2111 11:45:26.346573 PER_BANK_REFRESH: Hybrid Mode
2112 11:45:26.346648 TX_TRACKING: ON
2113 11:45:26.349976 [GetDramInforAfterCalByMRR] Vendor 6.
2114 11:45:26.356482 [GetDramInforAfterCalByMRR] Revision 606.
2115 11:45:26.360491 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 11:45:26.360572 MR0 0x3b3b
2117 11:45:26.360634 MR8 0x5151
2118 11:45:26.363487 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 11:45:26.363563
2120 11:45:26.366565 MR0 0x3b3b
2121 11:45:26.366635 MR8 0x5151
2122 11:45:26.369708 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 11:45:26.369780
2124 11:45:26.379985 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 11:45:26.383234 [FAST_K] Save calibration result to emmc
2126 11:45:26.386404 [FAST_K] Save calibration result to emmc
2127 11:45:26.389749 dram_init: config_dvfs: 1
2128 11:45:26.392951 dramc_set_vcore_voltage set vcore to 662500
2129 11:45:26.396729 Read voltage for 1200, 2
2130 11:45:26.396810 Vio18 = 0
2131 11:45:26.396872 Vcore = 662500
2132 11:45:26.399682 Vdram = 0
2133 11:45:26.399765 Vddq = 0
2134 11:45:26.399828 Vmddr = 0
2135 11:45:26.406478 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 11:45:26.410013 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 11:45:26.412989 MEM_TYPE=3, freq_sel=15
2138 11:45:26.416602 sv_algorithm_assistance_LP4_1600
2139 11:45:26.419445 ============ PULL DRAM RESETB DOWN ============
2140 11:45:26.422817 ========== PULL DRAM RESETB DOWN end =========
2141 11:45:26.429419 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 11:45:26.432905 ===================================
2143 11:45:26.435964 LPDDR4 DRAM CONFIGURATION
2144 11:45:26.439598 ===================================
2145 11:45:26.439670 EX_ROW_EN[0] = 0x0
2146 11:45:26.442612 EX_ROW_EN[1] = 0x0
2147 11:45:26.442707 LP4Y_EN = 0x0
2148 11:45:26.446289 WORK_FSP = 0x0
2149 11:45:26.446361 WL = 0x4
2150 11:45:26.449260 RL = 0x4
2151 11:45:26.449330 BL = 0x2
2152 11:45:26.452402 RPST = 0x0
2153 11:45:26.452471 RD_PRE = 0x0
2154 11:45:26.456134 WR_PRE = 0x1
2155 11:45:26.456207 WR_PST = 0x0
2156 11:45:26.459417 DBI_WR = 0x0
2157 11:45:26.459489 DBI_RD = 0x0
2158 11:45:26.462522 OTF = 0x1
2159 11:45:26.465754 ===================================
2160 11:45:26.468903 ===================================
2161 11:45:26.468976 ANA top config
2162 11:45:26.472509 ===================================
2163 11:45:26.475853 DLL_ASYNC_EN = 0
2164 11:45:26.479223 ALL_SLAVE_EN = 0
2165 11:45:26.482517 NEW_RANK_MODE = 1
2166 11:45:26.485551 DLL_IDLE_MODE = 1
2167 11:45:26.485624 LP45_APHY_COMB_EN = 1
2168 11:45:26.488784 TX_ODT_DIS = 1
2169 11:45:26.492606 NEW_8X_MODE = 1
2170 11:45:26.495734 ===================================
2171 11:45:26.499400 ===================================
2172 11:45:26.502516 data_rate = 2400
2173 11:45:26.505386 CKR = 1
2174 11:45:26.505462 DQ_P2S_RATIO = 8
2175 11:45:26.509345 ===================================
2176 11:45:26.512610 CA_P2S_RATIO = 8
2177 11:45:26.515791 DQ_CA_OPEN = 0
2178 11:45:26.519140 DQ_SEMI_OPEN = 0
2179 11:45:26.522205 CA_SEMI_OPEN = 0
2180 11:45:26.525281 CA_FULL_RATE = 0
2181 11:45:26.525376 DQ_CKDIV4_EN = 0
2182 11:45:26.528811 CA_CKDIV4_EN = 0
2183 11:45:26.532284 CA_PREDIV_EN = 0
2184 11:45:26.535358 PH8_DLY = 17
2185 11:45:26.538973 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 11:45:26.542272 DQ_AAMCK_DIV = 4
2187 11:45:26.542368 CA_AAMCK_DIV = 4
2188 11:45:26.545973 CA_ADMCK_DIV = 4
2189 11:45:26.549089 DQ_TRACK_CA_EN = 0
2190 11:45:26.552168 CA_PICK = 1200
2191 11:45:26.555311 CA_MCKIO = 1200
2192 11:45:26.559089 MCKIO_SEMI = 0
2193 11:45:26.562292 PLL_FREQ = 2366
2194 11:45:26.562373 DQ_UI_PI_RATIO = 32
2195 11:45:26.565476 CA_UI_PI_RATIO = 0
2196 11:45:26.568722 ===================================
2197 11:45:26.572509 ===================================
2198 11:45:26.575150 memory_type:LPDDR4
2199 11:45:26.578839 GP_NUM : 10
2200 11:45:26.578960 SRAM_EN : 1
2201 11:45:26.582107 MD32_EN : 0
2202 11:45:26.585420 ===================================
2203 11:45:26.588930 [ANA_INIT] >>>>>>>>>>>>>>
2204 11:45:26.589010 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 11:45:26.591915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 11:45:26.595093 ===================================
2207 11:45:26.598380 data_rate = 2400,PCW = 0X5b00
2208 11:45:26.601962 ===================================
2209 11:45:26.605220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 11:45:26.611610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 11:45:26.618581 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 11:45:26.621679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 11:45:26.625182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 11:45:26.628220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 11:45:26.631913 [ANA_INIT] flow start
2216 11:45:26.631992 [ANA_INIT] PLL >>>>>>>>
2217 11:45:26.635229 [ANA_INIT] PLL <<<<<<<<
2218 11:45:26.638158 [ANA_INIT] MIDPI >>>>>>>>
2219 11:45:26.641844 [ANA_INIT] MIDPI <<<<<<<<
2220 11:45:26.641923 [ANA_INIT] DLL >>>>>>>>
2221 11:45:26.644898 [ANA_INIT] DLL <<<<<<<<
2222 11:45:26.644978 [ANA_INIT] flow end
2223 11:45:26.651342 ============ LP4 DIFF to SE enter ============
2224 11:45:26.654835 ============ LP4 DIFF to SE exit ============
2225 11:45:26.657873 [ANA_INIT] <<<<<<<<<<<<<
2226 11:45:26.661403 [Flow] Enable top DCM control >>>>>
2227 11:45:26.664763 [Flow] Enable top DCM control <<<<<
2228 11:45:26.667941 Enable DLL master slave shuffle
2229 11:45:26.671128 ==============================================================
2230 11:45:26.674693 Gating Mode config
2231 11:45:26.677729 ==============================================================
2232 11:45:26.680994 Config description:
2233 11:45:26.691206 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 11:45:26.697911 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 11:45:26.701047 SELPH_MODE 0: By rank 1: By Phase
2236 11:45:26.707529 ==============================================================
2237 11:45:26.711128 GAT_TRACK_EN = 1
2238 11:45:26.714103 RX_GATING_MODE = 2
2239 11:45:26.717280 RX_GATING_TRACK_MODE = 2
2240 11:45:26.720419 SELPH_MODE = 1
2241 11:45:26.724175 PICG_EARLY_EN = 1
2242 11:45:26.727434 VALID_LAT_VALUE = 1
2243 11:45:26.730426 ==============================================================
2244 11:45:26.734231 Enter into Gating configuration >>>>
2245 11:45:26.737312 Exit from Gating configuration <<<<
2246 11:45:26.740768 Enter into DVFS_PRE_config >>>>>
2247 11:45:26.753975 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 11:45:26.754057 Exit from DVFS_PRE_config <<<<<
2249 11:45:26.757072 Enter into PICG configuration >>>>
2250 11:45:26.760657 Exit from PICG configuration <<<<
2251 11:45:26.763740 [RX_INPUT] configuration >>>>>
2252 11:45:26.766815 [RX_INPUT] configuration <<<<<
2253 11:45:26.773225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 11:45:26.777086 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 11:45:26.783255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 11:45:26.790007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 11:45:26.796974 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 11:45:26.803207 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 11:45:26.806811 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 11:45:26.809877 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 11:45:26.813035 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 11:45:26.819744 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 11:45:26.823493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 11:45:26.826518 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 11:45:26.829591 ===================================
2266 11:45:26.833195 LPDDR4 DRAM CONFIGURATION
2267 11:45:26.836338 ===================================
2268 11:45:26.840111 EX_ROW_EN[0] = 0x0
2269 11:45:26.840199 EX_ROW_EN[1] = 0x0
2270 11:45:26.842954 LP4Y_EN = 0x0
2271 11:45:26.843033 WORK_FSP = 0x0
2272 11:45:26.846058 WL = 0x4
2273 11:45:26.846137 RL = 0x4
2274 11:45:26.849584 BL = 0x2
2275 11:45:26.849663 RPST = 0x0
2276 11:45:26.853080 RD_PRE = 0x0
2277 11:45:26.853159 WR_PRE = 0x1
2278 11:45:26.856499 WR_PST = 0x0
2279 11:45:26.856578 DBI_WR = 0x0
2280 11:45:26.859570 DBI_RD = 0x0
2281 11:45:26.859649 OTF = 0x1
2282 11:45:26.863175 ===================================
2283 11:45:26.869743 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 11:45:26.872757 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 11:45:26.876211 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 11:45:26.879684 ===================================
2287 11:45:26.883093 LPDDR4 DRAM CONFIGURATION
2288 11:45:26.886234 ===================================
2289 11:45:26.889299 EX_ROW_EN[0] = 0x10
2290 11:45:26.889382 EX_ROW_EN[1] = 0x0
2291 11:45:26.893102 LP4Y_EN = 0x0
2292 11:45:26.893184 WORK_FSP = 0x0
2293 11:45:26.896273 WL = 0x4
2294 11:45:26.896378 RL = 0x4
2295 11:45:26.899601 BL = 0x2
2296 11:45:26.899680 RPST = 0x0
2297 11:45:26.902695 RD_PRE = 0x0
2298 11:45:26.902812 WR_PRE = 0x1
2299 11:45:26.906563 WR_PST = 0x0
2300 11:45:26.906667 DBI_WR = 0x0
2301 11:45:26.909477 DBI_RD = 0x0
2302 11:45:26.909555 OTF = 0x1
2303 11:45:26.912733 ===================================
2304 11:45:26.919536 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 11:45:26.919615 ==
2306 11:45:26.923019 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 11:45:26.926135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 11:45:26.929370 ==
2309 11:45:26.929449 [Duty_Offset_Calibration]
2310 11:45:26.932524 B0:2 B1:0 CA:3
2311 11:45:26.932601
2312 11:45:26.935646 [DutyScan_Calibration_Flow] k_type=0
2313 11:45:26.944438
2314 11:45:26.944543 ==CLK 0==
2315 11:45:26.947933 Final CLK duty delay cell = 0
2316 11:45:26.951092 [0] MAX Duty = 5031%(X100), DQS PI = 12
2317 11:45:26.954751 [0] MIN Duty = 4906%(X100), DQS PI = 54
2318 11:45:26.954839 [0] AVG Duty = 4968%(X100)
2319 11:45:26.957680
2320 11:45:26.961286 CH0 CLK Duty spec in!! Max-Min= 125%
2321 11:45:26.964325 [DutyScan_Calibration_Flow] ====Done====
2322 11:45:26.964404
2323 11:45:26.967993 [DutyScan_Calibration_Flow] k_type=1
2324 11:45:26.984051
2325 11:45:26.984176 ==DQS 0 ==
2326 11:45:26.987232 Final DQS duty delay cell = 0
2327 11:45:26.990352 [0] MAX Duty = 5093%(X100), DQS PI = 12
2328 11:45:26.993678 [0] MIN Duty = 4907%(X100), DQS PI = 2
2329 11:45:26.997132 [0] AVG Duty = 5000%(X100)
2330 11:45:26.997201
2331 11:45:26.997260 ==DQS 1 ==
2332 11:45:27.000214 Final DQS duty delay cell = 0
2333 11:45:27.003963 [0] MAX Duty = 5125%(X100), DQS PI = 26
2334 11:45:27.007120 [0] MIN Duty = 5031%(X100), DQS PI = 0
2335 11:45:27.010243 [0] AVG Duty = 5078%(X100)
2336 11:45:27.010310
2337 11:45:27.013359 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2338 11:45:27.013429
2339 11:45:27.016861 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2340 11:45:27.020032 [DutyScan_Calibration_Flow] ====Done====
2341 11:45:27.020099
2342 11:45:27.023158 [DutyScan_Calibration_Flow] k_type=3
2343 11:45:27.041175
2344 11:45:27.041245 ==DQM 0 ==
2345 11:45:27.044142 Final DQM duty delay cell = 0
2346 11:45:27.047802 [0] MAX Duty = 5124%(X100), DQS PI = 28
2347 11:45:27.050949 [0] MIN Duty = 4876%(X100), DQS PI = 0
2348 11:45:27.053982 [0] AVG Duty = 5000%(X100)
2349 11:45:27.054049
2350 11:45:27.054114 ==DQM 1 ==
2351 11:45:27.057218 Final DQM duty delay cell = 4
2352 11:45:27.060691 [4] MAX Duty = 5124%(X100), DQS PI = 0
2353 11:45:27.063807 [4] MIN Duty = 5000%(X100), DQS PI = 30
2354 11:45:27.067475 [4] AVG Duty = 5062%(X100)
2355 11:45:27.067570
2356 11:45:27.070580 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2357 11:45:27.070681
2358 11:45:27.074223 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2359 11:45:27.077305 [DutyScan_Calibration_Flow] ====Done====
2360 11:45:27.077386
2361 11:45:27.080930 [DutyScan_Calibration_Flow] k_type=2
2362 11:45:27.095800
2363 11:45:27.095911 ==DQ 0 ==
2364 11:45:27.099239 Final DQ duty delay cell = -4
2365 11:45:27.102019 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2366 11:45:27.105620 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2367 11:45:27.108625 [-4] AVG Duty = 4969%(X100)
2368 11:45:27.108695
2369 11:45:27.108755 ==DQ 1 ==
2370 11:45:27.112337 Final DQ duty delay cell = -4
2371 11:45:27.115478 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2372 11:45:27.118633 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2373 11:45:27.121785 [-4] AVG Duty = 4938%(X100)
2374 11:45:27.121860
2375 11:45:27.125041 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2376 11:45:27.125109
2377 11:45:27.128827 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2378 11:45:27.131860 [DutyScan_Calibration_Flow] ====Done====
2379 11:45:27.131954 ==
2380 11:45:27.134949 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 11:45:27.138673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 11:45:27.138758 ==
2383 11:45:27.141937 [Duty_Offset_Calibration]
2384 11:45:27.145038 B0:1 B1:-2 CA:0
2385 11:45:27.145119
2386 11:45:27.148047 [DutyScan_Calibration_Flow] k_type=0
2387 11:45:27.156497
2388 11:45:27.156577 ==CLK 0==
2389 11:45:27.159595 Final CLK duty delay cell = 0
2390 11:45:27.162707 [0] MAX Duty = 5031%(X100), DQS PI = 16
2391 11:45:27.166342 [0] MIN Duty = 4876%(X100), DQS PI = 58
2392 11:45:27.169401 [0] AVG Duty = 4953%(X100)
2393 11:45:27.169482
2394 11:45:27.172618 CH1 CLK Duty spec in!! Max-Min= 155%
2395 11:45:27.175811 [DutyScan_Calibration_Flow] ====Done====
2396 11:45:27.175892
2397 11:45:27.179422 [DutyScan_Calibration_Flow] k_type=1
2398 11:45:27.195009
2399 11:45:27.195090 ==DQS 0 ==
2400 11:45:27.197870 Final DQS duty delay cell = -4
2401 11:45:27.201501 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2402 11:45:27.204641 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2403 11:45:27.208061 [-4] AVG Duty = 4938%(X100)
2404 11:45:27.208143
2405 11:45:27.208226 ==DQS 1 ==
2406 11:45:27.211556 Final DQS duty delay cell = 0
2407 11:45:27.214599 [0] MAX Duty = 5062%(X100), DQS PI = 0
2408 11:45:27.218209 [0] MIN Duty = 4875%(X100), DQS PI = 26
2409 11:45:27.221289 [0] AVG Duty = 4968%(X100)
2410 11:45:27.221368
2411 11:45:27.224479 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2412 11:45:27.224549
2413 11:45:27.228168 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2414 11:45:27.231234 [DutyScan_Calibration_Flow] ====Done====
2415 11:45:27.231304
2416 11:45:27.234237 [DutyScan_Calibration_Flow] k_type=3
2417 11:45:27.251810
2418 11:45:27.251888 ==DQM 0 ==
2419 11:45:27.254716 Final DQM duty delay cell = 0
2420 11:45:27.258469 [0] MAX Duty = 5031%(X100), DQS PI = 24
2421 11:45:27.261461 [0] MIN Duty = 4844%(X100), DQS PI = 54
2422 11:45:27.264526 [0] AVG Duty = 4937%(X100)
2423 11:45:27.264607
2424 11:45:27.264671 ==DQM 1 ==
2425 11:45:27.268099 Final DQM duty delay cell = 0
2426 11:45:27.271158 [0] MAX Duty = 5031%(X100), DQS PI = 36
2427 11:45:27.274970 [0] MIN Duty = 4907%(X100), DQS PI = 4
2428 11:45:27.278102 [0] AVG Duty = 4969%(X100)
2429 11:45:27.278182
2430 11:45:27.281271 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2431 11:45:27.281351
2432 11:45:27.284660 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2433 11:45:27.287782 [DutyScan_Calibration_Flow] ====Done====
2434 11:45:27.287863
2435 11:45:27.291423 [DutyScan_Calibration_Flow] k_type=2
2436 11:45:27.307877
2437 11:45:27.307957 ==DQ 0 ==
2438 11:45:27.311495 Final DQ duty delay cell = 0
2439 11:45:27.314585 [0] MAX Duty = 5062%(X100), DQS PI = 12
2440 11:45:27.317835 [0] MIN Duty = 4938%(X100), DQS PI = 54
2441 11:45:27.317917 [0] AVG Duty = 5000%(X100)
2442 11:45:27.321278
2443 11:45:27.321358 ==DQ 1 ==
2444 11:45:27.324313 Final DQ duty delay cell = 0
2445 11:45:27.328063 [0] MAX Duty = 5125%(X100), DQS PI = 36
2446 11:45:27.331178 [0] MIN Duty = 4969%(X100), DQS PI = 26
2447 11:45:27.331258 [0] AVG Duty = 5047%(X100)
2448 11:45:27.334129
2449 11:45:27.337783 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2450 11:45:27.337863
2451 11:45:27.341224 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2452 11:45:27.344216 [DutyScan_Calibration_Flow] ====Done====
2453 11:45:27.347396 nWR fixed to 30
2454 11:45:27.347476 [ModeRegInit_LP4] CH0 RK0
2455 11:45:27.351235 [ModeRegInit_LP4] CH0 RK1
2456 11:45:27.354148 [ModeRegInit_LP4] CH1 RK0
2457 11:45:27.357904 [ModeRegInit_LP4] CH1 RK1
2458 11:45:27.357984 match AC timing 7
2459 11:45:27.360983 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 11:45:27.367591 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 11:45:27.370699 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 11:45:27.377484 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 11:45:27.381154 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 11:45:27.381234 ==
2465 11:45:27.384158 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 11:45:27.387839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 11:45:27.387920 ==
2468 11:45:27.394010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 11:45:27.400590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2470 11:45:27.408131 [CA 0] Center 40 (10~71) winsize 62
2471 11:45:27.411124 [CA 1] Center 39 (9~70) winsize 62
2472 11:45:27.414760 [CA 2] Center 36 (6~66) winsize 61
2473 11:45:27.417721 [CA 3] Center 35 (5~66) winsize 62
2474 11:45:27.421162 [CA 4] Center 34 (4~65) winsize 62
2475 11:45:27.424522 [CA 5] Center 33 (3~64) winsize 62
2476 11:45:27.424602
2477 11:45:27.428090 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 11:45:27.428170
2479 11:45:27.431023 [CATrainingPosCal] consider 1 rank data
2480 11:45:27.434520 u2DelayCellTimex100 = 270/100 ps
2481 11:45:27.437870 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2482 11:45:27.444449 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2483 11:45:27.447501 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2484 11:45:27.451189 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2485 11:45:27.454260 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2486 11:45:27.457851 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2487 11:45:27.457931
2488 11:45:27.460896 CA PerBit enable=1, Macro0, CA PI delay=33
2489 11:45:27.460976
2490 11:45:27.463990 [CBTSetCACLKResult] CA Dly = 33
2491 11:45:27.467895 CS Dly: 7 (0~38)
2492 11:45:27.467975 ==
2493 11:45:27.470989 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 11:45:27.474091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 11:45:27.474172 ==
2496 11:45:27.480568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 11:45:27.484280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2498 11:45:27.494286 [CA 0] Center 40 (10~70) winsize 61
2499 11:45:27.497229 [CA 1] Center 39 (9~70) winsize 62
2500 11:45:27.500436 [CA 2] Center 36 (6~66) winsize 61
2501 11:45:27.504257 [CA 3] Center 35 (5~66) winsize 62
2502 11:45:27.506958 [CA 4] Center 34 (4~65) winsize 62
2503 11:45:27.510760 [CA 5] Center 33 (3~64) winsize 62
2504 11:45:27.510862
2505 11:45:27.513982 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2506 11:45:27.514065
2507 11:45:27.516993 [CATrainingPosCal] consider 2 rank data
2508 11:45:27.520657 u2DelayCellTimex100 = 270/100 ps
2509 11:45:27.523787 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2510 11:45:27.530521 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2511 11:45:27.533476 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2512 11:45:27.536894 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2513 11:45:27.540318 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2514 11:45:27.543385 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2515 11:45:27.543509
2516 11:45:27.547045 CA PerBit enable=1, Macro0, CA PI delay=33
2517 11:45:27.547183
2518 11:45:27.549995 [CBTSetCACLKResult] CA Dly = 33
2519 11:45:27.553656 CS Dly: 8 (0~40)
2520 11:45:27.553836
2521 11:45:27.556809 ----->DramcWriteLeveling(PI) begin...
2522 11:45:27.556989 ==
2523 11:45:27.560532 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 11:45:27.563410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 11:45:27.563620 ==
2526 11:45:27.566645 Write leveling (Byte 0): 31 => 31
2527 11:45:27.570376 Write leveling (Byte 1): 30 => 30
2528 11:45:27.573263 DramcWriteLeveling(PI) end<-----
2529 11:45:27.573584
2530 11:45:27.573870 ==
2531 11:45:27.577198 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 11:45:27.580253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 11:45:27.580773 ==
2534 11:45:27.583289 [Gating] SW mode calibration
2535 11:45:27.590337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 11:45:27.596594 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 11:45:27.600113 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:45:27.603288 0 15 4 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
2539 11:45:27.610168 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 11:45:27.613029 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 11:45:27.616855 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 11:45:27.623067 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 11:45:27.626529 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 11:45:27.629749 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2545 11:45:27.636598 1 0 0 | B1->B0 | 3131 2626 | 1 0 | (1 0) (1 0)
2546 11:45:27.639636 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2547 11:45:27.643176 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 11:45:27.649882 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 11:45:27.652839 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 11:45:27.656617 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 11:45:27.663277 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 11:45:27.666316 1 0 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2553 11:45:27.670177 1 1 0 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
2554 11:45:27.676257 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2555 11:45:27.679729 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 11:45:27.682794 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 11:45:27.689505 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 11:45:27.692583 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 11:45:27.695732 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 11:45:27.702700 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 11:45:27.705988 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2562 11:45:27.709148 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2563 11:45:27.715675 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:45:27.719226 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:45:27.722821 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:45:27.729139 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:45:27.732659 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:45:27.735835 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 11:45:27.742612 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 11:45:27.746102 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 11:45:27.749188 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 11:45:27.755768 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 11:45:27.759346 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 11:45:27.762484 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 11:45:27.769271 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 11:45:27.772384 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 11:45:27.775460 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 11:45:27.779246 Total UI for P1: 0, mck2ui 16
2579 11:45:27.782167 best dqsien dly found for B0: ( 1, 3, 28)
2580 11:45:27.785256 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2581 11:45:27.791987 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 11:45:27.795821 Total UI for P1: 0, mck2ui 16
2583 11:45:27.798893 best dqsien dly found for B1: ( 1, 4, 2)
2584 11:45:27.802083 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2585 11:45:27.805683 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2586 11:45:27.806096
2587 11:45:27.808810 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2588 11:45:27.811851 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2589 11:45:27.815495 [Gating] SW calibration Done
2590 11:45:27.815906 ==
2591 11:45:27.818561 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 11:45:27.821728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 11:45:27.822145 ==
2594 11:45:27.825441 RX Vref Scan: 0
2595 11:45:27.825852
2596 11:45:27.828349 RX Vref 0 -> 0, step: 1
2597 11:45:27.828759
2598 11:45:27.829082 RX Delay -40 -> 252, step: 8
2599 11:45:27.835233 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2600 11:45:27.838222 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2601 11:45:27.841970 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2602 11:45:27.845012 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2603 11:45:27.848635 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2604 11:45:27.855119 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2605 11:45:27.858032 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2606 11:45:27.861560 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2607 11:45:27.865170 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2608 11:45:27.868301 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2609 11:45:27.874440 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2610 11:45:27.878008 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2611 11:45:27.881963 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2612 11:45:27.884809 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2613 11:45:27.887897 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2614 11:45:27.894438 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2615 11:45:27.894876 ==
2616 11:45:27.898078 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 11:45:27.901301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 11:45:27.901718 ==
2619 11:45:27.902043 DQS Delay:
2620 11:45:27.904387 DQS0 = 0, DQS1 = 0
2621 11:45:27.904798 DQM Delay:
2622 11:45:27.908077 DQM0 = 113, DQM1 = 102
2623 11:45:27.908491 DQ Delay:
2624 11:45:27.911263 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2625 11:45:27.914267 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2626 11:45:27.917415 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2627 11:45:27.921264 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2628 11:45:27.921677
2629 11:45:27.921999
2630 11:45:27.924406 ==
2631 11:45:27.927986 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 11:45:27.931164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 11:45:27.931581 ==
2634 11:45:27.931909
2635 11:45:27.932209
2636 11:45:27.934035 TX Vref Scan disable
2637 11:45:27.934445 == TX Byte 0 ==
2638 11:45:27.937227 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2639 11:45:27.943941 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2640 11:45:27.944463 == TX Byte 1 ==
2641 11:45:27.947508 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2642 11:45:27.954235 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2643 11:45:27.954649 ==
2644 11:45:27.957127 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 11:45:27.960584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 11:45:27.960999 ==
2647 11:45:27.972972 TX Vref=22, minBit 4, minWin=25, winSum=422
2648 11:45:27.976179 TX Vref=24, minBit 1, minWin=26, winSum=428
2649 11:45:27.979324 TX Vref=26, minBit 7, minWin=26, winSum=437
2650 11:45:27.982857 TX Vref=28, minBit 4, minWin=26, winSum=440
2651 11:45:27.985901 TX Vref=30, minBit 1, minWin=27, winSum=439
2652 11:45:27.992572 TX Vref=32, minBit 5, minWin=26, winSum=435
2653 11:45:27.995773 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 30
2654 11:45:27.996191
2655 11:45:27.999317 Final TX Range 1 Vref 30
2656 11:45:27.999731
2657 11:45:28.000053 ==
2658 11:45:28.002818 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 11:45:28.006012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 11:45:28.009202 ==
2661 11:45:28.009613
2662 11:45:28.009936
2663 11:45:28.010238 TX Vref Scan disable
2664 11:45:28.013037 == TX Byte 0 ==
2665 11:45:28.016067 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2666 11:45:28.022211 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2667 11:45:28.022624 == TX Byte 1 ==
2668 11:45:28.025913 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2669 11:45:28.032293 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2670 11:45:28.032707
2671 11:45:28.033030 [DATLAT]
2672 11:45:28.033333 Freq=1200, CH0 RK0
2673 11:45:28.033631
2674 11:45:28.035517 DATLAT Default: 0xd
2675 11:45:28.035929 0, 0xFFFF, sum = 0
2676 11:45:28.039207 1, 0xFFFF, sum = 0
2677 11:45:28.042023 2, 0xFFFF, sum = 0
2678 11:45:28.042440 3, 0xFFFF, sum = 0
2679 11:45:28.045803 4, 0xFFFF, sum = 0
2680 11:45:28.046163 5, 0xFFFF, sum = 0
2681 11:45:28.048948 6, 0xFFFF, sum = 0
2682 11:45:28.049365 7, 0xFFFF, sum = 0
2683 11:45:28.052585 8, 0xFFFF, sum = 0
2684 11:45:28.053003 9, 0xFFFF, sum = 0
2685 11:45:28.055363 10, 0xFFFF, sum = 0
2686 11:45:28.055806 11, 0xFFFF, sum = 0
2687 11:45:28.058815 12, 0x0, sum = 1
2688 11:45:28.059260 13, 0x0, sum = 2
2689 11:45:28.062335 14, 0x0, sum = 3
2690 11:45:28.062750 15, 0x0, sum = 4
2691 11:45:28.065840 best_step = 13
2692 11:45:28.066245
2693 11:45:28.066565 ==
2694 11:45:28.068850 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 11:45:28.072457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 11:45:28.072873 ==
2697 11:45:28.073200 RX Vref Scan: 1
2698 11:45:28.073502
2699 11:45:28.075345 Set Vref Range= 32 -> 127
2700 11:45:28.075850
2701 11:45:28.078402 RX Vref 32 -> 127, step: 1
2702 11:45:28.079031
2703 11:45:28.082262 RX Delay -37 -> 252, step: 4
2704 11:45:28.082759
2705 11:45:28.085242 Set Vref, RX VrefLevel [Byte0]: 32
2706 11:45:28.088968 [Byte1]: 32
2707 11:45:28.089544
2708 11:45:28.092248 Set Vref, RX VrefLevel [Byte0]: 33
2709 11:45:28.095231 [Byte1]: 33
2710 11:45:28.098929
2711 11:45:28.099427 Set Vref, RX VrefLevel [Byte0]: 34
2712 11:45:28.102672 [Byte1]: 34
2713 11:45:28.107391
2714 11:45:28.107875 Set Vref, RX VrefLevel [Byte0]: 35
2715 11:45:28.110509 [Byte1]: 35
2716 11:45:28.115527
2717 11:45:28.115991 Set Vref, RX VrefLevel [Byte0]: 36
2718 11:45:28.118631 [Byte1]: 36
2719 11:45:28.123274
2720 11:45:28.123871 Set Vref, RX VrefLevel [Byte0]: 37
2721 11:45:28.126442 [Byte1]: 37
2722 11:45:28.131392
2723 11:45:28.131946 Set Vref, RX VrefLevel [Byte0]: 38
2724 11:45:28.134593 [Byte1]: 38
2725 11:45:28.139073
2726 11:45:28.142334 Set Vref, RX VrefLevel [Byte0]: 39
2727 11:45:28.142969 [Byte1]: 39
2728 11:45:28.146929
2729 11:45:28.147432 Set Vref, RX VrefLevel [Byte0]: 40
2730 11:45:28.150520 [Byte1]: 40
2731 11:45:28.154928
2732 11:45:28.155481 Set Vref, RX VrefLevel [Byte0]: 41
2733 11:45:28.158419 [Byte1]: 41
2734 11:45:28.163224
2735 11:45:28.163832 Set Vref, RX VrefLevel [Byte0]: 42
2736 11:45:28.166811 [Byte1]: 42
2737 11:45:28.170962
2738 11:45:28.171371 Set Vref, RX VrefLevel [Byte0]: 43
2739 11:45:28.174615 [Byte1]: 43
2740 11:45:28.179192
2741 11:45:28.179603 Set Vref, RX VrefLevel [Byte0]: 44
2742 11:45:28.182169 [Byte1]: 44
2743 11:45:28.187331
2744 11:45:28.187874 Set Vref, RX VrefLevel [Byte0]: 45
2745 11:45:28.190346 [Byte1]: 45
2746 11:45:28.195289
2747 11:45:28.195699 Set Vref, RX VrefLevel [Byte0]: 46
2748 11:45:28.198385 [Byte1]: 46
2749 11:45:28.203234
2750 11:45:28.203808 Set Vref, RX VrefLevel [Byte0]: 47
2751 11:45:28.206257 [Byte1]: 47
2752 11:45:28.211161
2753 11:45:28.211641 Set Vref, RX VrefLevel [Byte0]: 48
2754 11:45:28.214248 [Byte1]: 48
2755 11:45:28.219233
2756 11:45:28.219690 Set Vref, RX VrefLevel [Byte0]: 49
2757 11:45:28.222328 [Byte1]: 49
2758 11:45:28.227130
2759 11:45:28.227586 Set Vref, RX VrefLevel [Byte0]: 50
2760 11:45:28.231062 [Byte1]: 50
2761 11:45:28.235168
2762 11:45:28.235623 Set Vref, RX VrefLevel [Byte0]: 51
2763 11:45:28.241590 [Byte1]: 51
2764 11:45:28.242049
2765 11:45:28.244790 Set Vref, RX VrefLevel [Byte0]: 52
2766 11:45:28.248550 [Byte1]: 52
2767 11:45:28.249146
2768 11:45:28.251615 Set Vref, RX VrefLevel [Byte0]: 53
2769 11:45:28.254535 [Byte1]: 53
2770 11:45:28.258877
2771 11:45:28.259288 Set Vref, RX VrefLevel [Byte0]: 54
2772 11:45:28.262511 [Byte1]: 54
2773 11:45:28.267430
2774 11:45:28.267842 Set Vref, RX VrefLevel [Byte0]: 55
2775 11:45:28.270435 [Byte1]: 55
2776 11:45:28.275105
2777 11:45:28.275560 Set Vref, RX VrefLevel [Byte0]: 56
2778 11:45:28.278641 [Byte1]: 56
2779 11:45:28.283466
2780 11:45:28.283875 Set Vref, RX VrefLevel [Byte0]: 57
2781 11:45:28.286193 [Byte1]: 57
2782 11:45:28.290799
2783 11:45:28.291248 Set Vref, RX VrefLevel [Byte0]: 58
2784 11:45:28.294611 [Byte1]: 58
2785 11:45:28.298936
2786 11:45:28.299488 Set Vref, RX VrefLevel [Byte0]: 59
2787 11:45:28.302537 [Byte1]: 59
2788 11:45:28.306817
2789 11:45:28.307395 Set Vref, RX VrefLevel [Byte0]: 60
2790 11:45:28.310478 [Byte1]: 60
2791 11:45:28.315283
2792 11:45:28.315730 Set Vref, RX VrefLevel [Byte0]: 61
2793 11:45:28.318256 [Byte1]: 61
2794 11:45:28.323080
2795 11:45:28.323503 Set Vref, RX VrefLevel [Byte0]: 62
2796 11:45:28.326297 [Byte1]: 62
2797 11:45:28.331193
2798 11:45:28.331595 Set Vref, RX VrefLevel [Byte0]: 63
2799 11:45:28.334298 [Byte1]: 63
2800 11:45:28.339287
2801 11:45:28.339855 Set Vref, RX VrefLevel [Byte0]: 64
2802 11:45:28.342386 [Byte1]: 64
2803 11:45:28.347343
2804 11:45:28.347707 Set Vref, RX VrefLevel [Byte0]: 65
2805 11:45:28.350624 [Byte1]: 65
2806 11:45:28.354890
2807 11:45:28.355408 Set Vref, RX VrefLevel [Byte0]: 66
2808 11:45:28.358378 [Byte1]: 66
2809 11:45:28.363073
2810 11:45:28.363584 Set Vref, RX VrefLevel [Byte0]: 67
2811 11:45:28.366181 [Byte1]: 67
2812 11:45:28.371118
2813 11:45:28.371706 Set Vref, RX VrefLevel [Byte0]: 68
2814 11:45:28.374710 [Byte1]: 68
2815 11:45:28.379033
2816 11:45:28.379548 Set Vref, RX VrefLevel [Byte0]: 69
2817 11:45:28.382398 [Byte1]: 69
2818 11:45:28.387068
2819 11:45:28.387614 Set Vref, RX VrefLevel [Byte0]: 70
2820 11:45:28.390442 [Byte1]: 70
2821 11:45:28.395469
2822 11:45:28.396026 Set Vref, RX VrefLevel [Byte0]: 71
2823 11:45:28.398208 [Byte1]: 71
2824 11:45:28.403123
2825 11:45:28.403653 Set Vref, RX VrefLevel [Byte0]: 72
2826 11:45:28.406179 [Byte1]: 72
2827 11:45:28.410891
2828 11:45:28.411433 Set Vref, RX VrefLevel [Byte0]: 73
2829 11:45:28.414672 [Byte1]: 73
2830 11:45:28.418746
2831 11:45:28.419203 Set Vref, RX VrefLevel [Byte0]: 74
2832 11:45:28.422361 [Byte1]: 74
2833 11:45:28.426908
2834 11:45:28.427424 Final RX Vref Byte 0 = 60 to rank0
2835 11:45:28.430335 Final RX Vref Byte 1 = 47 to rank0
2836 11:45:28.433396 Final RX Vref Byte 0 = 60 to rank1
2837 11:45:28.436563 Final RX Vref Byte 1 = 47 to rank1==
2838 11:45:28.440099 Dram Type= 6, Freq= 0, CH_0, rank 0
2839 11:45:28.446979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 11:45:28.447391 ==
2841 11:45:28.447713 DQS Delay:
2842 11:45:28.450003 DQS0 = 0, DQS1 = 0
2843 11:45:28.450408 DQM Delay:
2844 11:45:28.450726 DQM0 = 112, DQM1 = 98
2845 11:45:28.453214 DQ Delay:
2846 11:45:28.457054 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =106
2847 11:45:28.460231 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2848 11:45:28.463232 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2849 11:45:28.467002 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2850 11:45:28.467409
2851 11:45:28.467728
2852 11:45:28.476632 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2853 11:45:28.477046 CH0 RK0: MR19=303, MR18=FEFE
2854 11:45:28.483402 CH0_RK0: MR19=0x303, MR18=0xFEFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2855 11:45:28.483942
2856 11:45:28.486194 ----->DramcWriteLeveling(PI) begin...
2857 11:45:28.486611 ==
2858 11:45:28.489626 Dram Type= 6, Freq= 0, CH_0, rank 1
2859 11:45:28.496612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2860 11:45:28.497043 ==
2861 11:45:28.499697 Write leveling (Byte 0): 31 => 31
2862 11:45:28.502697 Write leveling (Byte 1): 31 => 31
2863 11:45:28.503161 DramcWriteLeveling(PI) end<-----
2864 11:45:28.503487
2865 11:45:28.506143 ==
2866 11:45:28.509134 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 11:45:28.512719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 11:45:28.513243 ==
2869 11:45:28.515745 [Gating] SW mode calibration
2870 11:45:28.522930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2871 11:45:28.525952 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2872 11:45:28.532802 0 15 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2873 11:45:28.536058 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2874 11:45:28.539046 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 11:45:28.545587 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 11:45:28.548724 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 11:45:28.552644 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 11:45:28.558785 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 11:45:28.561944 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2880 11:45:28.565705 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2881 11:45:28.572421 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 11:45:28.575480 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 11:45:28.579033 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 11:45:28.585334 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 11:45:28.589010 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 11:45:28.591904 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2887 11:45:28.598953 1 0 28 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
2888 11:45:28.601979 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2889 11:45:28.605550 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 11:45:28.612069 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 11:45:28.615544 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 11:45:28.618789 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 11:45:28.625025 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 11:45:28.628609 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 11:45:28.631828 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2896 11:45:28.638585 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 11:45:28.641836 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 11:45:28.645040 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 11:45:28.651656 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 11:45:28.654700 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 11:45:28.657792 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 11:45:28.664649 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 11:45:28.667589 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 11:45:28.671310 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 11:45:28.677507 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 11:45:28.681095 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 11:45:28.684218 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 11:45:28.690894 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 11:45:28.694039 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 11:45:28.697698 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2911 11:45:28.704116 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2912 11:45:28.707580 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2913 11:45:28.710637 Total UI for P1: 0, mck2ui 16
2914 11:45:28.714459 best dqsien dly found for B0: ( 1, 3, 26)
2915 11:45:28.717395 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 11:45:28.720909 Total UI for P1: 0, mck2ui 16
2917 11:45:28.724282 best dqsien dly found for B1: ( 1, 4, 0)
2918 11:45:28.727196 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2919 11:45:28.730673 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2920 11:45:28.730808
2921 11:45:28.733668 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2922 11:45:28.740693 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2923 11:45:28.740866 [Gating] SW calibration Done
2924 11:45:28.741001 ==
2925 11:45:28.743833 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 11:45:28.750616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 11:45:28.750958 ==
2928 11:45:28.751215 RX Vref Scan: 0
2929 11:45:28.751397
2930 11:45:28.753638 RX Vref 0 -> 0, step: 1
2931 11:45:28.753921
2932 11:45:28.757513 RX Delay -40 -> 252, step: 8
2933 11:45:28.760789 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2934 11:45:28.763846 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2935 11:45:28.766920 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2936 11:45:28.773689 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2937 11:45:28.776851 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2938 11:45:28.779962 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2939 11:45:28.783729 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2940 11:45:28.786897 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
2941 11:45:28.793621 iDelay=200, Bit 8, Center 87 (16 ~ 159) 144
2942 11:45:28.796753 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2943 11:45:28.800416 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2944 11:45:28.803374 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2945 11:45:28.806956 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2946 11:45:28.813301 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2947 11:45:28.816835 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2948 11:45:28.819670 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2949 11:45:28.819997 ==
2950 11:45:28.823347 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 11:45:28.826217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 11:45:28.829704 ==
2953 11:45:28.829907 DQS Delay:
2954 11:45:28.830056 DQS0 = 0, DQS1 = 0
2955 11:45:28.833090 DQM Delay:
2956 11:45:28.833261 DQM0 = 112, DQM1 = 100
2957 11:45:28.836447 DQ Delay:
2958 11:45:28.839984 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2959 11:45:28.842818 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =119
2960 11:45:28.846451 DQ8 =87, DQ9 =83, DQ10 =103, DQ11 =95
2961 11:45:28.849553 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2962 11:45:28.849687
2963 11:45:28.849791
2964 11:45:28.849888 ==
2965 11:45:28.852773 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 11:45:28.856322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 11:45:28.856512 ==
2968 11:45:28.856699
2969 11:45:28.856863
2970 11:45:28.859445 TX Vref Scan disable
2971 11:45:28.862575 == TX Byte 0 ==
2972 11:45:28.866286 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2973 11:45:28.869393 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2974 11:45:28.872558 == TX Byte 1 ==
2975 11:45:28.876193 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2976 11:45:28.879308 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2977 11:45:28.879476 ==
2978 11:45:28.882515 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 11:45:28.889335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 11:45:28.889518 ==
2981 11:45:28.899791 TX Vref=22, minBit 0, minWin=27, winSum=432
2982 11:45:28.902805 TX Vref=24, minBit 5, minWin=26, winSum=434
2983 11:45:28.906390 TX Vref=26, minBit 0, minWin=26, winSum=440
2984 11:45:28.909596 TX Vref=28, minBit 5, minWin=26, winSum=442
2985 11:45:28.913401 TX Vref=30, minBit 1, minWin=27, winSum=444
2986 11:45:28.919424 TX Vref=32, minBit 1, minWin=27, winSum=442
2987 11:45:28.922947 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
2988 11:45:28.923406
2989 11:45:28.926627 Final TX Range 1 Vref 30
2990 11:45:28.927276
2991 11:45:28.927647 ==
2992 11:45:28.929590 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 11:45:28.932637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 11:45:28.936218 ==
2995 11:45:28.936776
2996 11:45:28.937292
2997 11:45:28.937819 TX Vref Scan disable
2998 11:45:28.939781 == TX Byte 0 ==
2999 11:45:28.943062 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3000 11:45:28.949219 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3001 11:45:28.949820 == TX Byte 1 ==
3002 11:45:28.952577 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3003 11:45:28.959475 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3004 11:45:28.959937
3005 11:45:28.960292 [DATLAT]
3006 11:45:28.960628 Freq=1200, CH0 RK1
3007 11:45:28.960954
3008 11:45:28.963146 DATLAT Default: 0xd
3009 11:45:28.963604 0, 0xFFFF, sum = 0
3010 11:45:28.965609 1, 0xFFFF, sum = 0
3011 11:45:28.969331 2, 0xFFFF, sum = 0
3012 11:45:28.969795 3, 0xFFFF, sum = 0
3013 11:45:28.972583 4, 0xFFFF, sum = 0
3014 11:45:28.973047 5, 0xFFFF, sum = 0
3015 11:45:28.975598 6, 0xFFFF, sum = 0
3016 11:45:28.976062 7, 0xFFFF, sum = 0
3017 11:45:28.979409 8, 0xFFFF, sum = 0
3018 11:45:28.979874 9, 0xFFFF, sum = 0
3019 11:45:28.982586 10, 0xFFFF, sum = 0
3020 11:45:28.983137 11, 0xFFFF, sum = 0
3021 11:45:28.985533 12, 0x0, sum = 1
3022 11:45:28.986050 13, 0x0, sum = 2
3023 11:45:28.989265 14, 0x0, sum = 3
3024 11:45:28.989689 15, 0x0, sum = 4
3025 11:45:28.992336 best_step = 13
3026 11:45:28.992875
3027 11:45:28.993208 ==
3028 11:45:28.995426 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 11:45:28.999043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 11:45:28.999459 ==
3031 11:45:29.002010 RX Vref Scan: 0
3032 11:45:29.002533
3033 11:45:29.002915 RX Vref 0 -> 0, step: 1
3034 11:45:29.003237
3035 11:45:29.005361 RX Delay -37 -> 252, step: 4
3036 11:45:29.011670 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3037 11:45:29.015371 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3038 11:45:29.018326 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3039 11:45:29.022190 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3040 11:45:29.025187 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3041 11:45:29.031972 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3042 11:45:29.035081 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3043 11:45:29.038040 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3044 11:45:29.041575 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3045 11:45:29.045388 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3046 11:45:29.051820 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3047 11:45:29.054759 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3048 11:45:29.058240 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3049 11:45:29.061608 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3050 11:45:29.068047 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3051 11:45:29.071700 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3052 11:45:29.072157 ==
3053 11:45:29.074917 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 11:45:29.077963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 11:45:29.078465 ==
3056 11:45:29.078855 DQS Delay:
3057 11:45:29.081593 DQS0 = 0, DQS1 = 0
3058 11:45:29.082053 DQM Delay:
3059 11:45:29.084790 DQM0 = 110, DQM1 = 99
3060 11:45:29.085200 DQ Delay:
3061 11:45:29.087864 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3062 11:45:29.091180 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3063 11:45:29.094390 DQ8 =90, DQ9 =80, DQ10 =100, DQ11 =90
3064 11:45:29.098170 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3065 11:45:29.101167
3066 11:45:29.101572
3067 11:45:29.107898 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3068 11:45:29.110899 CH0 RK1: MR19=403, MR18=14FC
3069 11:45:29.117802 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3070 11:45:29.120891 [RxdqsGatingPostProcess] freq 1200
3071 11:45:29.124283 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3072 11:45:29.127770 best DQS0 dly(2T, 0.5T) = (0, 11)
3073 11:45:29.130666 best DQS1 dly(2T, 0.5T) = (0, 12)
3074 11:45:29.134369 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3075 11:45:29.137440 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3076 11:45:29.140546 best DQS0 dly(2T, 0.5T) = (0, 11)
3077 11:45:29.143786 best DQS1 dly(2T, 0.5T) = (0, 12)
3078 11:45:29.147432 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3079 11:45:29.150947 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3080 11:45:29.153963 Pre-setting of DQS Precalculation
3081 11:45:29.157478 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3082 11:45:29.157937 ==
3083 11:45:29.160360 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 11:45:29.166997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 11:45:29.167454 ==
3086 11:45:29.170363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 11:45:29.176895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3088 11:45:29.185465 [CA 0] Center 37 (7~67) winsize 61
3089 11:45:29.188706 [CA 1] Center 37 (7~68) winsize 62
3090 11:45:29.192545 [CA 2] Center 34 (4~64) winsize 61
3091 11:45:29.195495 [CA 3] Center 34 (4~64) winsize 61
3092 11:45:29.198674 [CA 4] Center 34 (4~64) winsize 61
3093 11:45:29.202040 [CA 5] Center 33 (3~63) winsize 61
3094 11:45:29.202528
3095 11:45:29.205608 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3096 11:45:29.206217
3097 11:45:29.208723 [CATrainingPosCal] consider 1 rank data
3098 11:45:29.211861 u2DelayCellTimex100 = 270/100 ps
3099 11:45:29.215699 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3100 11:45:29.222340 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3101 11:45:29.225357 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3102 11:45:29.229138 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3103 11:45:29.232076 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 11:45:29.235506 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3105 11:45:29.236167
3106 11:45:29.238678 CA PerBit enable=1, Macro0, CA PI delay=33
3107 11:45:29.239157
3108 11:45:29.241757 [CBTSetCACLKResult] CA Dly = 33
3109 11:45:29.242167 CS Dly: 5 (0~36)
3110 11:45:29.245561 ==
3111 11:45:29.248772 Dram Type= 6, Freq= 0, CH_1, rank 1
3112 11:45:29.251772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 11:45:29.252227 ==
3114 11:45:29.255489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 11:45:29.262059 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3116 11:45:29.271160 [CA 0] Center 37 (7~67) winsize 61
3117 11:45:29.274505 [CA 1] Center 37 (7~68) winsize 62
3118 11:45:29.278169 [CA 2] Center 34 (4~65) winsize 62
3119 11:45:29.281103 [CA 3] Center 33 (3~64) winsize 62
3120 11:45:29.284751 [CA 4] Center 34 (4~65) winsize 62
3121 11:45:29.287992 [CA 5] Center 33 (3~63) winsize 61
3122 11:45:29.288503
3123 11:45:29.291892 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3124 11:45:29.292466
3125 11:45:29.294693 [CATrainingPosCal] consider 2 rank data
3126 11:45:29.297725 u2DelayCellTimex100 = 270/100 ps
3127 11:45:29.300977 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3128 11:45:29.304620 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 11:45:29.310943 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3130 11:45:29.314714 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 11:45:29.317696 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 11:45:29.320740 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3133 11:45:29.321373
3134 11:45:29.324703 CA PerBit enable=1, Macro0, CA PI delay=33
3135 11:45:29.325303
3136 11:45:29.327523 [CBTSetCACLKResult] CA Dly = 33
3137 11:45:29.327980 CS Dly: 6 (0~39)
3138 11:45:29.331112
3139 11:45:29.334281 ----->DramcWriteLeveling(PI) begin...
3140 11:45:29.334694 ==
3141 11:45:29.337316 Dram Type= 6, Freq= 0, CH_1, rank 0
3142 11:45:29.340872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 11:45:29.341303 ==
3144 11:45:29.344097 Write leveling (Byte 0): 25 => 25
3145 11:45:29.347704 Write leveling (Byte 1): 31 => 31
3146 11:45:29.350867 DramcWriteLeveling(PI) end<-----
3147 11:45:29.351274
3148 11:45:29.351596 ==
3149 11:45:29.353979 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 11:45:29.357617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 11:45:29.358034 ==
3152 11:45:29.360736 [Gating] SW mode calibration
3153 11:45:29.367400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3154 11:45:29.373885 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3155 11:45:29.377591 0 15 0 | B1->B0 | 2c2c 2424 | 1 0 | (1 1) (0 0)
3156 11:45:29.380529 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3157 11:45:29.387458 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 11:45:29.390523 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 11:45:29.394073 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 11:45:29.400386 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 11:45:29.404141 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 11:45:29.407332 0 15 28 | B1->B0 | 3131 3131 | 1 0 | (1 1) (0 0)
3163 11:45:29.413590 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3164 11:45:29.416858 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 11:45:29.420609 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 11:45:29.426733 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 11:45:29.430431 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 11:45:29.433203 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 11:45:29.440490 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 11:45:29.443468 1 0 28 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
3171 11:45:29.447035 1 1 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
3172 11:45:29.450173 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 11:45:29.457230 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 11:45:29.460468 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 11:45:29.463434 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 11:45:29.470363 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 11:45:29.473240 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 11:45:29.476876 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3179 11:45:29.483258 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3180 11:45:29.487005 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 11:45:29.490269 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 11:45:29.497135 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 11:45:29.499813 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 11:45:29.503417 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 11:45:29.509922 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 11:45:29.512890 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 11:45:29.516722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 11:45:29.522953 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 11:45:29.526618 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 11:45:29.530034 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 11:45:29.536610 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 11:45:29.539753 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 11:45:29.542983 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 11:45:29.550026 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3195 11:45:29.552973 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 11:45:29.556554 Total UI for P1: 0, mck2ui 16
3197 11:45:29.559565 best dqsien dly found for B0: ( 1, 3, 28)
3198 11:45:29.563775 Total UI for P1: 0, mck2ui 16
3199 11:45:29.566499 best dqsien dly found for B1: ( 1, 3, 28)
3200 11:45:29.569546 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3201 11:45:29.572688 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3202 11:45:29.573005
3203 11:45:29.645867 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3204 11:45:29.646951 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3205 11:45:29.647454 [Gating] SW calibration Done
3206 11:45:29.647870 ==
3207 11:45:29.648223 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 11:45:29.648587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 11:45:29.649119 ==
3210 11:45:29.649639 RX Vref Scan: 0
3211 11:45:29.650136
3212 11:45:29.650490 RX Vref 0 -> 0, step: 1
3213 11:45:29.650921
3214 11:45:29.651290 RX Delay -40 -> 252, step: 8
3215 11:45:29.651646 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3216 11:45:29.652006 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3217 11:45:29.652349 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3218 11:45:29.652700 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3219 11:45:29.653132 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3220 11:45:29.653656 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3221 11:45:29.654183 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3222 11:45:29.654755 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3223 11:45:29.655345 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3224 11:45:29.655936 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3225 11:45:29.656509 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3226 11:45:29.657109 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3227 11:45:29.657789 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3228 11:45:29.658375 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3229 11:45:29.659367 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3230 11:45:29.662596 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3231 11:45:29.663198 ==
3232 11:45:29.665601 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 11:45:29.668786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 11:45:29.669424 ==
3235 11:45:29.672420 DQS Delay:
3236 11:45:29.672910 DQS0 = 0, DQS1 = 0
3237 11:45:29.673271 DQM Delay:
3238 11:45:29.675276 DQM0 = 115, DQM1 = 105
3239 11:45:29.675597 DQ Delay:
3240 11:45:29.678453 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =115
3241 11:45:29.681611 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3242 11:45:29.685269 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3243 11:45:29.691770 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3244 11:45:29.692011
3245 11:45:29.692199
3246 11:45:29.692372 ==
3247 11:45:29.695338 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 11:45:29.698400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 11:45:29.698638 ==
3250 11:45:29.698823
3251 11:45:29.699031
3252 11:45:29.702070 TX Vref Scan disable
3253 11:45:29.702306 == TX Byte 0 ==
3254 11:45:29.708516 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3255 11:45:29.712120 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3256 11:45:29.712357 == TX Byte 1 ==
3257 11:45:29.718299 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3258 11:45:29.722017 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3259 11:45:29.722254 ==
3260 11:45:29.725191 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 11:45:29.728314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 11:45:29.728551 ==
3263 11:45:29.741514 TX Vref=22, minBit 8, minWin=25, winSum=416
3264 11:45:29.745136 TX Vref=24, minBit 8, minWin=25, winSum=419
3265 11:45:29.748593 TX Vref=26, minBit 1, minWin=26, winSum=430
3266 11:45:29.751658 TX Vref=28, minBit 1, minWin=26, winSum=427
3267 11:45:29.755330 TX Vref=30, minBit 3, minWin=26, winSum=432
3268 11:45:29.761450 TX Vref=32, minBit 0, minWin=26, winSum=428
3269 11:45:29.764962 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 30
3270 11:45:29.765430
3271 11:45:29.768255 Final TX Range 1 Vref 30
3272 11:45:29.768709
3273 11:45:29.769138 ==
3274 11:45:29.771608 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 11:45:29.775034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 11:45:29.775607 ==
3277 11:45:29.778054
3278 11:45:29.778655
3279 11:45:29.779276 TX Vref Scan disable
3280 11:45:29.781780 == TX Byte 0 ==
3281 11:45:29.784850 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3282 11:45:29.791549 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3283 11:45:29.792098 == TX Byte 1 ==
3284 11:45:29.794626 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3285 11:45:29.801155 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3286 11:45:29.801671
3287 11:45:29.802091 [DATLAT]
3288 11:45:29.802486 Freq=1200, CH1 RK0
3289 11:45:29.802995
3290 11:45:29.804848 DATLAT Default: 0xd
3291 11:45:29.805266 0, 0xFFFF, sum = 0
3292 11:45:29.807637 1, 0xFFFF, sum = 0
3293 11:45:29.811203 2, 0xFFFF, sum = 0
3294 11:45:29.811704 3, 0xFFFF, sum = 0
3295 11:45:29.814788 4, 0xFFFF, sum = 0
3296 11:45:29.815343 5, 0xFFFF, sum = 0
3297 11:45:29.817993 6, 0xFFFF, sum = 0
3298 11:45:29.818487 7, 0xFFFF, sum = 0
3299 11:45:29.821049 8, 0xFFFF, sum = 0
3300 11:45:29.821525 9, 0xFFFF, sum = 0
3301 11:45:29.824837 10, 0xFFFF, sum = 0
3302 11:45:29.825322 11, 0xFFFF, sum = 0
3303 11:45:29.827860 12, 0x0, sum = 1
3304 11:45:29.828357 13, 0x0, sum = 2
3305 11:45:29.830775 14, 0x0, sum = 3
3306 11:45:29.831163 15, 0x0, sum = 4
3307 11:45:29.834702 best_step = 13
3308 11:45:29.835072
3309 11:45:29.835354 ==
3310 11:45:29.837669 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 11:45:29.840864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 11:45:29.841269 ==
3313 11:45:29.841643 RX Vref Scan: 1
3314 11:45:29.841991
3315 11:45:29.844574 Set Vref Range= 32 -> 127
3316 11:45:29.844955
3317 11:45:29.847688 RX Vref 32 -> 127, step: 1
3318 11:45:29.848060
3319 11:45:29.850790 RX Delay -21 -> 252, step: 4
3320 11:45:29.851196
3321 11:45:29.854307 Set Vref, RX VrefLevel [Byte0]: 32
3322 11:45:29.857406 [Byte1]: 32
3323 11:45:29.857778
3324 11:45:29.860630 Set Vref, RX VrefLevel [Byte0]: 33
3325 11:45:29.864332 [Byte1]: 33
3326 11:45:29.867473
3327 11:45:29.867847 Set Vref, RX VrefLevel [Byte0]: 34
3328 11:45:29.871205 [Byte1]: 34
3329 11:45:29.875899
3330 11:45:29.876283 Set Vref, RX VrefLevel [Byte0]: 35
3331 11:45:29.879122 [Byte1]: 35
3332 11:45:29.883689
3333 11:45:29.884077 Set Vref, RX VrefLevel [Byte0]: 36
3334 11:45:29.887104 [Byte1]: 36
3335 11:45:29.891261
3336 11:45:29.894867 Set Vref, RX VrefLevel [Byte0]: 37
3337 11:45:29.895245 [Byte1]: 37
3338 11:45:29.899706
3339 11:45:29.900081 Set Vref, RX VrefLevel [Byte0]: 38
3340 11:45:29.902659 [Byte1]: 38
3341 11:45:29.907222
3342 11:45:29.907588 Set Vref, RX VrefLevel [Byte0]: 39
3343 11:45:29.910779 [Byte1]: 39
3344 11:45:29.915478
3345 11:45:29.915836 Set Vref, RX VrefLevel [Byte0]: 40
3346 11:45:29.918385 [Byte1]: 40
3347 11:45:29.923160
3348 11:45:29.923454 Set Vref, RX VrefLevel [Byte0]: 41
3349 11:45:29.926222 [Byte1]: 41
3350 11:45:29.931283
3351 11:45:29.931673 Set Vref, RX VrefLevel [Byte0]: 42
3352 11:45:29.934259 [Byte1]: 42
3353 11:45:29.939425
3354 11:45:29.939896 Set Vref, RX VrefLevel [Byte0]: 43
3355 11:45:29.942474 [Byte1]: 43
3356 11:45:29.946892
3357 11:45:29.947360 Set Vref, RX VrefLevel [Byte0]: 44
3358 11:45:29.950068 [Byte1]: 44
3359 11:45:29.955086
3360 11:45:29.955594 Set Vref, RX VrefLevel [Byte0]: 45
3361 11:45:29.958149 [Byte1]: 45
3362 11:45:29.963107
3363 11:45:29.963614 Set Vref, RX VrefLevel [Byte0]: 46
3364 11:45:29.966218 [Byte1]: 46
3365 11:45:29.970781
3366 11:45:29.971322 Set Vref, RX VrefLevel [Byte0]: 47
3367 11:45:29.974504 [Byte1]: 47
3368 11:45:29.978997
3369 11:45:29.979565 Set Vref, RX VrefLevel [Byte0]: 48
3370 11:45:29.981911 [Byte1]: 48
3371 11:45:29.986916
3372 11:45:29.987453 Set Vref, RX VrefLevel [Byte0]: 49
3373 11:45:29.989784 [Byte1]: 49
3374 11:45:29.994636
3375 11:45:29.995168 Set Vref, RX VrefLevel [Byte0]: 50
3376 11:45:29.997550 [Byte1]: 50
3377 11:45:30.002283
3378 11:45:30.002804 Set Vref, RX VrefLevel [Byte0]: 51
3379 11:45:30.005960 [Byte1]: 51
3380 11:45:30.010664
3381 11:45:30.011219 Set Vref, RX VrefLevel [Byte0]: 52
3382 11:45:30.013507 [Byte1]: 52
3383 11:45:30.018213
3384 11:45:30.018723 Set Vref, RX VrefLevel [Byte0]: 53
3385 11:45:30.021708 [Byte1]: 53
3386 11:45:30.026273
3387 11:45:30.026805 Set Vref, RX VrefLevel [Byte0]: 54
3388 11:45:30.029270 [Byte1]: 54
3389 11:45:30.034378
3390 11:45:30.034816 Set Vref, RX VrefLevel [Byte0]: 55
3391 11:45:30.037560 [Byte1]: 55
3392 11:45:30.041927
3393 11:45:30.042382 Set Vref, RX VrefLevel [Byte0]: 56
3394 11:45:30.045705 [Byte1]: 56
3395 11:45:30.050123
3396 11:45:30.050684 Set Vref, RX VrefLevel [Byte0]: 57
3397 11:45:30.053211 [Byte1]: 57
3398 11:45:30.058235
3399 11:45:30.058803 Set Vref, RX VrefLevel [Byte0]: 58
3400 11:45:30.061393 [Byte1]: 58
3401 11:45:30.065717
3402 11:45:30.066280 Set Vref, RX VrefLevel [Byte0]: 59
3403 11:45:30.069267 [Byte1]: 59
3404 11:45:30.073568
3405 11:45:30.074150 Set Vref, RX VrefLevel [Byte0]: 60
3406 11:45:30.077363 [Byte1]: 60
3407 11:45:30.081532
3408 11:45:30.082097 Set Vref, RX VrefLevel [Byte0]: 61
3409 11:45:30.085171 [Byte1]: 61
3410 11:45:30.089564
3411 11:45:30.090122 Set Vref, RX VrefLevel [Byte0]: 62
3412 11:45:30.093117 [Byte1]: 62
3413 11:45:30.097262
3414 11:45:30.097785 Set Vref, RX VrefLevel [Byte0]: 63
3415 11:45:30.100827 [Byte1]: 63
3416 11:45:30.105475
3417 11:45:30.105990 Set Vref, RX VrefLevel [Byte0]: 64
3418 11:45:30.108623 [Byte1]: 64
3419 11:45:30.113487
3420 11:45:30.114002 Set Vref, RX VrefLevel [Byte0]: 65
3421 11:45:30.116480 [Byte1]: 65
3422 11:45:30.120993
3423 11:45:30.121501 Set Vref, RX VrefLevel [Byte0]: 66
3424 11:45:30.124560 [Byte1]: 66
3425 11:45:30.129339
3426 11:45:30.129898 Final RX Vref Byte 0 = 54 to rank0
3427 11:45:30.132827 Final RX Vref Byte 1 = 48 to rank0
3428 11:45:30.135799 Final RX Vref Byte 0 = 54 to rank1
3429 11:45:30.139561 Final RX Vref Byte 1 = 48 to rank1==
3430 11:45:30.142637 Dram Type= 6, Freq= 0, CH_1, rank 0
3431 11:45:30.148912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 11:45:30.149364 ==
3433 11:45:30.149735 DQS Delay:
3434 11:45:30.152668 DQS0 = 0, DQS1 = 0
3435 11:45:30.153114 DQM Delay:
3436 11:45:30.153473 DQM0 = 114, DQM1 = 104
3437 11:45:30.155752 DQ Delay:
3438 11:45:30.159210 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3439 11:45:30.162571 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =112
3440 11:45:30.165621 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3441 11:45:30.169319 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3442 11:45:30.169776
3443 11:45:30.170243
3444 11:45:30.179122 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3445 11:45:30.179564 CH1 RK0: MR19=303, MR18=F0F7
3446 11:45:30.185655 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3447 11:45:30.186110
3448 11:45:30.188738 ----->DramcWriteLeveling(PI) begin...
3449 11:45:30.189271 ==
3450 11:45:30.192497 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 11:45:30.198743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 11:45:30.199212 ==
3453 11:45:30.202349 Write leveling (Byte 0): 24 => 24
3454 11:45:30.202760 Write leveling (Byte 1): 26 => 26
3455 11:45:30.205316 DramcWriteLeveling(PI) end<-----
3456 11:45:30.205724
3457 11:45:30.206046 ==
3458 11:45:30.208819 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 11:45:30.215144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 11:45:30.215563 ==
3461 11:45:30.218763 [Gating] SW mode calibration
3462 11:45:30.225180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3463 11:45:30.228568 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3464 11:45:30.235050 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 11:45:30.238466 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 11:45:30.242130 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 11:45:30.248891 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 11:45:30.252009 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 11:45:30.255169 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3470 11:45:30.261708 0 15 24 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 0)
3471 11:45:30.265214 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3472 11:45:30.268475 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 11:45:30.275370 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 11:45:30.278420 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 11:45:30.281448 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 11:45:30.288283 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 11:45:30.291942 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3478 11:45:30.294974 1 0 24 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
3479 11:45:30.301202 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3480 11:45:30.305271 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 11:45:30.308071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 11:45:30.314691 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 11:45:30.317632 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 11:45:30.321189 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 11:45:30.328012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 11:45:30.330970 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3487 11:45:30.334344 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3488 11:45:30.341170 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 11:45:30.344076 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 11:45:30.347626 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 11:45:30.354317 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 11:45:30.357349 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 11:45:30.360499 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 11:45:30.367360 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 11:45:30.370420 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 11:45:30.374176 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 11:45:30.380405 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 11:45:30.384062 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 11:45:30.387240 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 11:45:30.393845 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 11:45:30.396932 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 11:45:30.399959 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3503 11:45:30.406769 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3504 11:45:30.407235 Total UI for P1: 0, mck2ui 16
3505 11:45:30.413638 best dqsien dly found for B0: ( 1, 3, 24)
3506 11:45:30.416808 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 11:45:30.419865 Total UI for P1: 0, mck2ui 16
3508 11:45:30.423304 best dqsien dly found for B1: ( 1, 3, 26)
3509 11:45:30.426654 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3510 11:45:30.430331 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3511 11:45:30.430749
3512 11:45:30.433107 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3513 11:45:30.436802 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3514 11:45:30.439882 [Gating] SW calibration Done
3515 11:45:30.440297 ==
3516 11:45:30.443184 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 11:45:30.446108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 11:45:30.449872 ==
3519 11:45:30.450294 RX Vref Scan: 0
3520 11:45:30.450624
3521 11:45:30.453196 RX Vref 0 -> 0, step: 1
3522 11:45:30.453611
3523 11:45:30.456203 RX Delay -40 -> 252, step: 8
3524 11:45:30.459850 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3525 11:45:30.463059 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3526 11:45:30.466087 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3527 11:45:30.469630 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3528 11:45:30.475797 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3529 11:45:30.479419 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3530 11:45:30.482548 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3531 11:45:30.485684 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3532 11:45:30.489416 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3533 11:45:30.495674 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3534 11:45:30.498600 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3535 11:45:30.502177 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3536 11:45:30.505329 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3537 11:45:30.508366 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3538 11:45:30.515148 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3539 11:45:30.518196 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3540 11:45:30.518333 ==
3541 11:45:30.521996 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 11:45:30.525026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 11:45:30.525132 ==
3544 11:45:30.527976 DQS Delay:
3545 11:45:30.528078 DQS0 = 0, DQS1 = 0
3546 11:45:30.531826 DQM Delay:
3547 11:45:30.531917 DQM0 = 110, DQM1 = 106
3548 11:45:30.532010 DQ Delay:
3549 11:45:30.534750 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3550 11:45:30.541313 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3551 11:45:30.544426 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3552 11:45:30.547972 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =115
3553 11:45:30.548056
3554 11:45:30.548121
3555 11:45:30.548179 ==
3556 11:45:30.550805 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 11:45:30.554281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 11:45:30.554363 ==
3559 11:45:30.554427
3560 11:45:30.554484
3561 11:45:30.557722 TX Vref Scan disable
3562 11:45:30.561197 == TX Byte 0 ==
3563 11:45:30.564129 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3564 11:45:30.567597 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3565 11:45:30.571162 == TX Byte 1 ==
3566 11:45:30.574211 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3567 11:45:30.577488 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3568 11:45:30.577562 ==
3569 11:45:30.580535 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 11:45:30.587174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 11:45:30.587255 ==
3572 11:45:30.597685 TX Vref=22, minBit 0, minWin=25, winSum=421
3573 11:45:30.600748 TX Vref=24, minBit 11, minWin=25, winSum=423
3574 11:45:30.604311 TX Vref=26, minBit 1, minWin=26, winSum=431
3575 11:45:30.607545 TX Vref=28, minBit 9, minWin=26, winSum=434
3576 11:45:30.610758 TX Vref=30, minBit 1, minWin=26, winSum=432
3577 11:45:30.617290 TX Vref=32, minBit 9, minWin=26, winSum=431
3578 11:45:30.620523 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3579 11:45:30.620628
3580 11:45:30.623610 Final TX Range 1 Vref 28
3581 11:45:30.623691
3582 11:45:30.623751 ==
3583 11:45:30.627332 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 11:45:30.630208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 11:45:30.633856 ==
3586 11:45:30.633952
3587 11:45:30.634045
3588 11:45:30.634131 TX Vref Scan disable
3589 11:45:30.637061 == TX Byte 0 ==
3590 11:45:30.640781 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3591 11:45:30.647365 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3592 11:45:30.647444 == TX Byte 1 ==
3593 11:45:30.650371 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3594 11:45:30.657313 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3595 11:45:30.657388
3596 11:45:30.657449 [DATLAT]
3597 11:45:30.657521 Freq=1200, CH1 RK1
3598 11:45:30.657580
3599 11:45:30.660863 DATLAT Default: 0xd
3600 11:45:30.660941 0, 0xFFFF, sum = 0
3601 11:45:30.663639 1, 0xFFFF, sum = 0
3602 11:45:30.667022 2, 0xFFFF, sum = 0
3603 11:45:30.667094 3, 0xFFFF, sum = 0
3604 11:45:30.670705 4, 0xFFFF, sum = 0
3605 11:45:30.670780 5, 0xFFFF, sum = 0
3606 11:45:30.674023 6, 0xFFFF, sum = 0
3607 11:45:30.674128 7, 0xFFFF, sum = 0
3608 11:45:30.677015 8, 0xFFFF, sum = 0
3609 11:45:30.677088 9, 0xFFFF, sum = 0
3610 11:45:30.680592 10, 0xFFFF, sum = 0
3611 11:45:30.680660 11, 0xFFFF, sum = 0
3612 11:45:30.683719 12, 0x0, sum = 1
3613 11:45:30.683800 13, 0x0, sum = 2
3614 11:45:30.686779 14, 0x0, sum = 3
3615 11:45:30.686896 15, 0x0, sum = 4
3616 11:45:30.690664 best_step = 13
3617 11:45:30.690763
3618 11:45:30.690839 ==
3619 11:45:30.693721 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 11:45:30.696729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 11:45:30.696828 ==
3622 11:45:30.696916 RX Vref Scan: 0
3623 11:45:30.699906
3624 11:45:30.700004 RX Vref 0 -> 0, step: 1
3625 11:45:30.700089
3626 11:45:30.703611 RX Delay -21 -> 252, step: 4
3627 11:45:30.709880 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3628 11:45:30.713850 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3629 11:45:30.716789 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3630 11:45:30.719755 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3631 11:45:30.723745 iDelay=195, Bit 4, Center 108 (35 ~ 182) 148
3632 11:45:30.729812 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3633 11:45:30.733470 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3634 11:45:30.736431 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3635 11:45:30.739593 iDelay=195, Bit 8, Center 96 (35 ~ 158) 124
3636 11:45:30.742718 iDelay=195, Bit 9, Center 102 (35 ~ 170) 136
3637 11:45:30.749866 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3638 11:45:30.752773 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3639 11:45:30.756382 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3640 11:45:30.759423 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3641 11:45:30.762571 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3642 11:45:30.769424 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3643 11:45:30.769523 ==
3644 11:45:30.772478 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 11:45:30.776190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 11:45:30.776288 ==
3647 11:45:30.776380 DQS Delay:
3648 11:45:30.779010 DQS0 = 0, DQS1 = 0
3649 11:45:30.779080 DQM Delay:
3650 11:45:30.782228 DQM0 = 111, DQM1 = 109
3651 11:45:30.782292 DQ Delay:
3652 11:45:30.785789 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3653 11:45:30.789245 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =108
3654 11:45:30.792333 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =102
3655 11:45:30.799094 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3656 11:45:30.799176
3657 11:45:30.799238
3658 11:45:30.805335 [DQSOSCAuto] RK1, (LSB)MR18= 0xf807, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3659 11:45:30.809058 CH1 RK1: MR19=304, MR18=F807
3660 11:45:30.815206 CH1_RK1: MR19=0x304, MR18=0xF807, DQSOSC=407, MR23=63, INC=39, DEC=26
3661 11:45:30.818859 [RxdqsGatingPostProcess] freq 1200
3662 11:45:30.822020 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3663 11:45:30.825051 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 11:45:30.828742 best DQS1 dly(2T, 0.5T) = (0, 11)
3665 11:45:30.831820 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 11:45:30.834928 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3667 11:45:30.838461 best DQS0 dly(2T, 0.5T) = (0, 11)
3668 11:45:30.842121 best DQS1 dly(2T, 0.5T) = (0, 11)
3669 11:45:30.845247 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3670 11:45:30.848559 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3671 11:45:30.851701 Pre-setting of DQS Precalculation
3672 11:45:30.854908 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3673 11:45:30.864499 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3674 11:45:30.871062 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3675 11:45:30.871142
3676 11:45:30.871204
3677 11:45:30.874579 [Calibration Summary] 2400 Mbps
3678 11:45:30.874674 CH 0, Rank 0
3679 11:45:30.877924 SW Impedance : PASS
3680 11:45:30.881045 DUTY Scan : NO K
3681 11:45:30.881124 ZQ Calibration : PASS
3682 11:45:30.884648 Jitter Meter : NO K
3683 11:45:30.887495 CBT Training : PASS
3684 11:45:30.887574 Write leveling : PASS
3685 11:45:30.891019 RX DQS gating : PASS
3686 11:45:30.891100 RX DQ/DQS(RDDQC) : PASS
3687 11:45:30.894392 TX DQ/DQS : PASS
3688 11:45:30.897483 RX DATLAT : PASS
3689 11:45:30.897562 RX DQ/DQS(Engine): PASS
3690 11:45:30.901093 TX OE : NO K
3691 11:45:30.901173 All Pass.
3692 11:45:30.901235
3693 11:45:30.904125 CH 0, Rank 1
3694 11:45:30.904210 SW Impedance : PASS
3695 11:45:30.907252 DUTY Scan : NO K
3696 11:45:30.911017 ZQ Calibration : PASS
3697 11:45:30.911096 Jitter Meter : NO K
3698 11:45:30.914083 CBT Training : PASS
3699 11:45:30.917159 Write leveling : PASS
3700 11:45:30.917238 RX DQS gating : PASS
3701 11:45:30.920943 RX DQ/DQS(RDDQC) : PASS
3702 11:45:30.924155 TX DQ/DQS : PASS
3703 11:45:30.924235 RX DATLAT : PASS
3704 11:45:30.927166 RX DQ/DQS(Engine): PASS
3705 11:45:30.930902 TX OE : NO K
3706 11:45:30.930982 All Pass.
3707 11:45:30.931044
3708 11:45:30.931102 CH 1, Rank 0
3709 11:45:30.934032 SW Impedance : PASS
3710 11:45:30.937172 DUTY Scan : NO K
3711 11:45:30.937251 ZQ Calibration : PASS
3712 11:45:30.940331 Jitter Meter : NO K
3713 11:45:30.944042 CBT Training : PASS
3714 11:45:30.944120 Write leveling : PASS
3715 11:45:30.947156 RX DQS gating : PASS
3716 11:45:30.950206 RX DQ/DQS(RDDQC) : PASS
3717 11:45:30.950288 TX DQ/DQS : PASS
3718 11:45:30.953522 RX DATLAT : PASS
3719 11:45:30.956653 RX DQ/DQS(Engine): PASS
3720 11:45:30.956761 TX OE : NO K
3721 11:45:30.960467 All Pass.
3722 11:45:30.960565
3723 11:45:30.960659 CH 1, Rank 1
3724 11:45:30.963396 SW Impedance : PASS
3725 11:45:30.963465 DUTY Scan : NO K
3726 11:45:30.966442 ZQ Calibration : PASS
3727 11:45:30.970117 Jitter Meter : NO K
3728 11:45:30.970191 CBT Training : PASS
3729 11:45:30.973167 Write leveling : PASS
3730 11:45:30.976849 RX DQS gating : PASS
3731 11:45:30.976948 RX DQ/DQS(RDDQC) : PASS
3732 11:45:30.979800 TX DQ/DQS : PASS
3733 11:45:30.979884 RX DATLAT : PASS
3734 11:45:30.983342 RX DQ/DQS(Engine): PASS
3735 11:45:30.986335 TX OE : NO K
3736 11:45:30.986405 All Pass.
3737 11:45:30.986465
3738 11:45:30.989920 DramC Write-DBI off
3739 11:45:30.992975 PER_BANK_REFRESH: Hybrid Mode
3740 11:45:30.993046 TX_TRACKING: ON
3741 11:45:31.002727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3742 11:45:31.006363 [FAST_K] Save calibration result to emmc
3743 11:45:31.009882 dramc_set_vcore_voltage set vcore to 650000
3744 11:45:31.013043 Read voltage for 600, 5
3745 11:45:31.013138 Vio18 = 0
3746 11:45:31.013229 Vcore = 650000
3747 11:45:31.016197 Vdram = 0
3748 11:45:31.016291 Vddq = 0
3749 11:45:31.016381 Vmddr = 0
3750 11:45:31.022954 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3751 11:45:31.026026 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3752 11:45:31.029465 MEM_TYPE=3, freq_sel=19
3753 11:45:31.032953 sv_algorithm_assistance_LP4_1600
3754 11:45:31.036152 ============ PULL DRAM RESETB DOWN ============
3755 11:45:31.039141 ========== PULL DRAM RESETB DOWN end =========
3756 11:45:31.045947 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3757 11:45:31.049412 ===================================
3758 11:45:31.049508 LPDDR4 DRAM CONFIGURATION
3759 11:45:31.052509 ===================================
3760 11:45:31.055766 EX_ROW_EN[0] = 0x0
3761 11:45:31.059245 EX_ROW_EN[1] = 0x0
3762 11:45:31.059314 LP4Y_EN = 0x0
3763 11:45:31.062315 WORK_FSP = 0x0
3764 11:45:31.062379 WL = 0x2
3765 11:45:31.065437 RL = 0x2
3766 11:45:31.065530 BL = 0x2
3767 11:45:31.069119 RPST = 0x0
3768 11:45:31.069210 RD_PRE = 0x0
3769 11:45:31.072220 WR_PRE = 0x1
3770 11:45:31.072290 WR_PST = 0x0
3771 11:45:31.075178 DBI_WR = 0x0
3772 11:45:31.075249 DBI_RD = 0x0
3773 11:45:31.078738 OTF = 0x1
3774 11:45:31.081948 ===================================
3775 11:45:31.085368 ===================================
3776 11:45:31.085469 ANA top config
3777 11:45:31.088515 ===================================
3778 11:45:31.092237 DLL_ASYNC_EN = 0
3779 11:45:31.095291 ALL_SLAVE_EN = 1
3780 11:45:31.098942 NEW_RANK_MODE = 1
3781 11:45:31.099042 DLL_IDLE_MODE = 1
3782 11:45:31.101804 LP45_APHY_COMB_EN = 1
3783 11:45:31.105242 TX_ODT_DIS = 1
3784 11:45:31.108673 NEW_8X_MODE = 1
3785 11:45:31.111585 ===================================
3786 11:45:31.115133 ===================================
3787 11:45:31.118220 data_rate = 1200
3788 11:45:31.121368 CKR = 1
3789 11:45:31.121464 DQ_P2S_RATIO = 8
3790 11:45:31.124867 ===================================
3791 11:45:31.128464 CA_P2S_RATIO = 8
3792 11:45:31.131589 DQ_CA_OPEN = 0
3793 11:45:31.134696 DQ_SEMI_OPEN = 0
3794 11:45:31.137792 CA_SEMI_OPEN = 0
3795 11:45:31.141461 CA_FULL_RATE = 0
3796 11:45:31.141554 DQ_CKDIV4_EN = 1
3797 11:45:31.144698 CA_CKDIV4_EN = 1
3798 11:45:31.147688 CA_PREDIV_EN = 0
3799 11:45:31.151461 PH8_DLY = 0
3800 11:45:31.154327 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3801 11:45:31.157542 DQ_AAMCK_DIV = 4
3802 11:45:31.157635 CA_AAMCK_DIV = 4
3803 11:45:31.161191 CA_ADMCK_DIV = 4
3804 11:45:31.164286 DQ_TRACK_CA_EN = 0
3805 11:45:31.167647 CA_PICK = 600
3806 11:45:31.171173 CA_MCKIO = 600
3807 11:45:31.174189 MCKIO_SEMI = 0
3808 11:45:31.177747 PLL_FREQ = 2288
3809 11:45:31.180846 DQ_UI_PI_RATIO = 32
3810 11:45:31.180918 CA_UI_PI_RATIO = 0
3811 11:45:31.183988 ===================================
3812 11:45:31.187612 ===================================
3813 11:45:31.190629 memory_type:LPDDR4
3814 11:45:31.194239 GP_NUM : 10
3815 11:45:31.194341 SRAM_EN : 1
3816 11:45:31.197484 MD32_EN : 0
3817 11:45:31.200676 ===================================
3818 11:45:31.203669 [ANA_INIT] >>>>>>>>>>>>>>
3819 11:45:31.207180 <<<<<< [CONFIGURE PHASE]: ANA_TX
3820 11:45:31.210753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3821 11:45:31.213779 ===================================
3822 11:45:31.213878 data_rate = 1200,PCW = 0X5800
3823 11:45:31.217152 ===================================
3824 11:45:31.220575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3825 11:45:31.227202 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 11:45:31.233537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 11:45:31.237215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3828 11:45:31.240267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3829 11:45:31.243326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3830 11:45:31.246975 [ANA_INIT] flow start
3831 11:45:31.250082 [ANA_INIT] PLL >>>>>>>>
3832 11:45:31.250178 [ANA_INIT] PLL <<<<<<<<
3833 11:45:31.253727 [ANA_INIT] MIDPI >>>>>>>>
3834 11:45:31.256700 [ANA_INIT] MIDPI <<<<<<<<
3835 11:45:31.256796 [ANA_INIT] DLL >>>>>>>>
3836 11:45:31.259744 [ANA_INIT] flow end
3837 11:45:31.263428 ============ LP4 DIFF to SE enter ============
3838 11:45:31.266635 ============ LP4 DIFF to SE exit ============
3839 11:45:31.269704 [ANA_INIT] <<<<<<<<<<<<<
3840 11:45:31.273585 [Flow] Enable top DCM control >>>>>
3841 11:45:31.276518 [Flow] Enable top DCM control <<<<<
3842 11:45:31.279605 Enable DLL master slave shuffle
3843 11:45:31.286525 ==============================================================
3844 11:45:31.286627 Gating Mode config
3845 11:45:31.293206 ==============================================================
3846 11:45:31.296101 Config description:
3847 11:45:31.303078 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3848 11:45:31.309310 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3849 11:45:31.315831 SELPH_MODE 0: By rank 1: By Phase
3850 11:45:31.322500 ==============================================================
3851 11:45:31.325882 GAT_TRACK_EN = 1
3852 11:45:31.325984 RX_GATING_MODE = 2
3853 11:45:31.329269 RX_GATING_TRACK_MODE = 2
3854 11:45:31.332377 SELPH_MODE = 1
3855 11:45:31.335458 PICG_EARLY_EN = 1
3856 11:45:31.338836 VALID_LAT_VALUE = 1
3857 11:45:31.345734 ==============================================================
3858 11:45:31.348711 Enter into Gating configuration >>>>
3859 11:45:31.352484 Exit from Gating configuration <<<<
3860 11:45:31.355863 Enter into DVFS_PRE_config >>>>>
3861 11:45:31.365263 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3862 11:45:31.368407 Exit from DVFS_PRE_config <<<<<
3863 11:45:31.372110 Enter into PICG configuration >>>>
3864 11:45:31.375143 Exit from PICG configuration <<<<
3865 11:45:31.378928 [RX_INPUT] configuration >>>>>
3866 11:45:31.382320 [RX_INPUT] configuration <<<<<
3867 11:45:31.385173 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3868 11:45:31.391492 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3869 11:45:31.398311 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 11:45:31.404716 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 11:45:31.408464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3872 11:45:31.414857 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3873 11:45:31.421099 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3874 11:45:31.424429 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3875 11:45:31.427584 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3876 11:45:31.431081 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3877 11:45:31.438062 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3878 11:45:31.441147 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 11:45:31.444153 ===================================
3880 11:45:31.447847 LPDDR4 DRAM CONFIGURATION
3881 11:45:31.450574 ===================================
3882 11:45:31.450679 EX_ROW_EN[0] = 0x0
3883 11:45:31.454363 EX_ROW_EN[1] = 0x0
3884 11:45:31.454465 LP4Y_EN = 0x0
3885 11:45:31.457429 WORK_FSP = 0x0
3886 11:45:31.457537 WL = 0x2
3887 11:45:31.460662 RL = 0x2
3888 11:45:31.460767 BL = 0x2
3889 11:45:31.463883 RPST = 0x0
3890 11:45:31.467464 RD_PRE = 0x0
3891 11:45:31.467568 WR_PRE = 0x1
3892 11:45:31.470621 WR_PST = 0x0
3893 11:45:31.470717 DBI_WR = 0x0
3894 11:45:31.473774 DBI_RD = 0x0
3895 11:45:31.473874 OTF = 0x1
3896 11:45:31.476982 ===================================
3897 11:45:31.480196 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3898 11:45:31.487189 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3899 11:45:31.490498 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3900 11:45:31.493596 ===================================
3901 11:45:31.496931 LPDDR4 DRAM CONFIGURATION
3902 11:45:31.500103 ===================================
3903 11:45:31.500206 EX_ROW_EN[0] = 0x10
3904 11:45:31.503234 EX_ROW_EN[1] = 0x0
3905 11:45:31.503330 LP4Y_EN = 0x0
3906 11:45:31.506940 WORK_FSP = 0x0
3907 11:45:31.509829 WL = 0x2
3908 11:45:31.509927 RL = 0x2
3909 11:45:31.513657 BL = 0x2
3910 11:45:31.513752 RPST = 0x0
3911 11:45:31.516498 RD_PRE = 0x0
3912 11:45:31.516593 WR_PRE = 0x1
3913 11:45:31.520158 WR_PST = 0x0
3914 11:45:31.520262 DBI_WR = 0x0
3915 11:45:31.523178 DBI_RD = 0x0
3916 11:45:31.523274 OTF = 0x1
3917 11:45:31.526778 ===================================
3918 11:45:31.533122 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3919 11:45:31.537212 nWR fixed to 30
3920 11:45:31.540686 [ModeRegInit_LP4] CH0 RK0
3921 11:45:31.540766 [ModeRegInit_LP4] CH0 RK1
3922 11:45:31.543834 [ModeRegInit_LP4] CH1 RK0
3923 11:45:31.546813 [ModeRegInit_LP4] CH1 RK1
3924 11:45:31.546966 match AC timing 17
3925 11:45:31.553521 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3926 11:45:31.556944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3927 11:45:31.560096 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3928 11:45:31.566375 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3929 11:45:31.570143 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3930 11:45:31.570223 ==
3931 11:45:31.573262 Dram Type= 6, Freq= 0, CH_0, rank 0
3932 11:45:31.576447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 11:45:31.579602 ==
3934 11:45:31.582857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 11:45:31.589729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3936 11:45:31.592983 [CA 0] Center 37 (7~67) winsize 61
3937 11:45:31.596024 [CA 1] Center 37 (7~67) winsize 61
3938 11:45:31.599902 [CA 2] Center 35 (5~65) winsize 61
3939 11:45:31.603320 [CA 3] Center 35 (5~65) winsize 61
3940 11:45:31.606041 [CA 4] Center 34 (4~65) winsize 62
3941 11:45:31.609150 [CA 5] Center 33 (3~64) winsize 62
3942 11:45:31.609230
3943 11:45:31.612892 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3944 11:45:31.612971
3945 11:45:31.615923 [CATrainingPosCal] consider 1 rank data
3946 11:45:31.619089 u2DelayCellTimex100 = 270/100 ps
3947 11:45:31.622709 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3948 11:45:31.625919 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3949 11:45:31.632628 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3950 11:45:31.635786 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3951 11:45:31.638806 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 11:45:31.642412 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 11:45:31.642517
3954 11:45:31.645771 CA PerBit enable=1, Macro0, CA PI delay=33
3955 11:45:31.645850
3956 11:45:31.648645 [CBTSetCACLKResult] CA Dly = 33
3957 11:45:31.652115 CS Dly: 4 (0~35)
3958 11:45:31.652195 ==
3959 11:45:31.655120 Dram Type= 6, Freq= 0, CH_0, rank 1
3960 11:45:31.658772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 11:45:31.658879 ==
3962 11:45:31.664977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 11:45:31.668277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 11:45:31.672523 [CA 0] Center 37 (7~67) winsize 61
3965 11:45:31.676157 [CA 1] Center 37 (7~67) winsize 61
3966 11:45:31.679266 [CA 2] Center 35 (5~65) winsize 61
3967 11:45:31.682441 [CA 3] Center 34 (4~65) winsize 62
3968 11:45:31.685535 [CA 4] Center 34 (4~65) winsize 62
3969 11:45:31.689446 [CA 5] Center 33 (3~64) winsize 62
3970 11:45:31.689547
3971 11:45:31.692653 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 11:45:31.692735
3973 11:45:31.695728 [CATrainingPosCal] consider 2 rank data
3974 11:45:31.699061 u2DelayCellTimex100 = 270/100 ps
3975 11:45:31.702507 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3976 11:45:31.708811 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3977 11:45:31.712164 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3978 11:45:31.715361 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3979 11:45:31.718982 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3980 11:45:31.722096 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 11:45:31.722228
3982 11:45:31.725409 CA PerBit enable=1, Macro0, CA PI delay=33
3983 11:45:31.725514
3984 11:45:31.728358 [CBTSetCACLKResult] CA Dly = 33
3985 11:45:31.732041 CS Dly: 5 (0~38)
3986 11:45:31.732113
3987 11:45:31.735373 ----->DramcWriteLeveling(PI) begin...
3988 11:45:31.735454 ==
3989 11:45:31.738494 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 11:45:31.741587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 11:45:31.741687 ==
3992 11:45:31.744805 Write leveling (Byte 0): 32 => 32
3993 11:45:31.748571 Write leveling (Byte 1): 32 => 32
3994 11:45:31.751613 DramcWriteLeveling(PI) end<-----
3995 11:45:31.751698
3996 11:45:31.751764 ==
3997 11:45:31.754591 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 11:45:31.758167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 11:45:31.758289 ==
4000 11:45:31.761168 [Gating] SW mode calibration
4001 11:45:31.767731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4002 11:45:31.774590 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4003 11:45:31.777647 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 11:45:31.784518 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 11:45:31.787736 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 11:45:31.790982 0 9 12 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 1)
4007 11:45:31.797925 0 9 16 | B1->B0 | 3232 2c2c | 0 1 | (0 0) (1 0)
4008 11:45:31.801127 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 11:45:31.804514 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 11:45:31.810790 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 11:45:31.813980 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 11:45:31.817119 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 11:45:31.823996 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 11:45:31.827105 0 10 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
4015 11:45:31.830338 0 10 16 | B1->B0 | 3333 3a3a | 1 0 | (0 0) (0 0)
4016 11:45:31.837252 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4017 11:45:31.840495 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 11:45:31.843728 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 11:45:31.849984 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 11:45:31.853118 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 11:45:31.856713 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 11:45:31.863560 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4023 11:45:31.866978 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 11:45:31.869896 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 11:45:31.876631 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 11:45:31.879943 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 11:45:31.883155 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 11:45:31.889372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 11:45:31.892586 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 11:45:31.895870 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 11:45:31.902915 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 11:45:31.905888 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 11:45:31.909046 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 11:45:31.915568 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 11:45:31.918862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 11:45:31.922705 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 11:45:31.928973 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 11:45:31.932083 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4039 11:45:31.935861 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4040 11:45:31.942126 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 11:45:31.945726 Total UI for P1: 0, mck2ui 16
4042 11:45:31.948725 best dqsien dly found for B0: ( 0, 13, 14)
4043 11:45:31.952357 Total UI for P1: 0, mck2ui 16
4044 11:45:31.955296 best dqsien dly found for B1: ( 0, 13, 18)
4045 11:45:31.958921 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4046 11:45:31.961964 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4047 11:45:31.962070
4048 11:45:31.965599 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4049 11:45:31.968586 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4050 11:45:31.971658 [Gating] SW calibration Done
4051 11:45:31.971756 ==
4052 11:45:31.975246 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 11:45:31.978803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 11:45:31.978918 ==
4055 11:45:31.982157 RX Vref Scan: 0
4056 11:45:31.982229
4057 11:45:31.985153 RX Vref 0 -> 0, step: 1
4058 11:45:31.985255
4059 11:45:31.985343 RX Delay -230 -> 252, step: 16
4060 11:45:31.991998 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4061 11:45:31.995090 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4062 11:45:31.998715 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4063 11:45:32.001910 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4064 11:45:32.008118 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4065 11:45:32.011343 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4066 11:45:32.015081 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4067 11:45:32.018088 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4068 11:45:32.024604 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4069 11:45:32.027766 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4070 11:45:32.030972 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4071 11:45:32.034609 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4072 11:45:32.040914 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4073 11:45:32.044762 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4074 11:45:32.047956 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4075 11:45:32.051077 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4076 11:45:32.051158 ==
4077 11:45:32.054078 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 11:45:32.061269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 11:45:32.061377 ==
4080 11:45:32.061473 DQS Delay:
4081 11:45:32.064231 DQS0 = 0, DQS1 = 0
4082 11:45:32.064334 DQM Delay:
4083 11:45:32.064432 DQM0 = 38, DQM1 = 30
4084 11:45:32.067223 DQ Delay:
4085 11:45:32.070694 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4086 11:45:32.074242 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4087 11:45:32.077307 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4088 11:45:32.080368 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4089 11:45:32.080448
4090 11:45:32.080511
4091 11:45:32.080586 ==
4092 11:45:32.083880 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 11:45:32.086978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 11:45:32.087083 ==
4095 11:45:32.087183
4096 11:45:32.087269
4097 11:45:32.090603 TX Vref Scan disable
4098 11:45:32.093726 == TX Byte 0 ==
4099 11:45:32.096968 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4100 11:45:32.100217 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4101 11:45:32.103503 == TX Byte 1 ==
4102 11:45:32.106984 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4103 11:45:32.110148 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4104 11:45:32.110255 ==
4105 11:45:32.113743 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 11:45:32.120195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 11:45:32.120279 ==
4108 11:45:32.120342
4109 11:45:32.120401
4110 11:45:32.120474 TX Vref Scan disable
4111 11:45:32.124133 == TX Byte 0 ==
4112 11:45:32.127239 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4113 11:45:32.134194 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4114 11:45:32.134295 == TX Byte 1 ==
4115 11:45:32.137188 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4116 11:45:32.144154 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4117 11:45:32.144268
4118 11:45:32.144365 [DATLAT]
4119 11:45:32.144461 Freq=600, CH0 RK0
4120 11:45:32.144526
4121 11:45:32.147518 DATLAT Default: 0x9
4122 11:45:32.150726 0, 0xFFFF, sum = 0
4123 11:45:32.150808 1, 0xFFFF, sum = 0
4124 11:45:32.153892 2, 0xFFFF, sum = 0
4125 11:45:32.153972 3, 0xFFFF, sum = 0
4126 11:45:32.157458 4, 0xFFFF, sum = 0
4127 11:45:32.157563 5, 0xFFFF, sum = 0
4128 11:45:32.160534 6, 0xFFFF, sum = 0
4129 11:45:32.160665 7, 0xFFFF, sum = 0
4130 11:45:32.163556 8, 0x0, sum = 1
4131 11:45:32.163665 9, 0x0, sum = 2
4132 11:45:32.167255 10, 0x0, sum = 3
4133 11:45:32.167361 11, 0x0, sum = 4
4134 11:45:32.167454 best_step = 9
4135 11:45:32.167540
4136 11:45:32.170601 ==
4137 11:45:32.173617 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 11:45:32.176759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 11:45:32.176881 ==
4140 11:45:32.176971 RX Vref Scan: 1
4141 11:45:32.177074
4142 11:45:32.180229 RX Vref 0 -> 0, step: 1
4143 11:45:32.180321
4144 11:45:32.183429 RX Delay -195 -> 252, step: 8
4145 11:45:32.183535
4146 11:45:32.187052 Set Vref, RX VrefLevel [Byte0]: 60
4147 11:45:32.190071 [Byte1]: 47
4148 11:45:32.190186
4149 11:45:32.193170 Final RX Vref Byte 0 = 60 to rank0
4150 11:45:32.196791 Final RX Vref Byte 1 = 47 to rank0
4151 11:45:32.199975 Final RX Vref Byte 0 = 60 to rank1
4152 11:45:32.203060 Final RX Vref Byte 1 = 47 to rank1==
4153 11:45:32.206635 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 11:45:32.210144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 11:45:32.213418 ==
4156 11:45:32.213524 DQS Delay:
4157 11:45:32.213618 DQS0 = 0, DQS1 = 0
4158 11:45:32.216579 DQM Delay:
4159 11:45:32.216681 DQM0 = 34, DQM1 = 28
4160 11:45:32.219769 DQ Delay:
4161 11:45:32.222959 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4162 11:45:32.223058 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4163 11:45:32.226145 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4164 11:45:32.233078 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4165 11:45:32.233178
4166 11:45:32.233273
4167 11:45:32.239367 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4168 11:45:32.242593 CH0 RK0: MR19=808, MR18=3838
4169 11:45:32.249467 CH0_RK0: MR19=0x808, MR18=0x3838, DQSOSC=399, MR23=63, INC=164, DEC=109
4170 11:45:32.249573
4171 11:45:32.252805 ----->DramcWriteLeveling(PI) begin...
4172 11:45:32.252913 ==
4173 11:45:32.256082 Dram Type= 6, Freq= 0, CH_0, rank 1
4174 11:45:32.259177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 11:45:32.259258 ==
4176 11:45:32.262524 Write leveling (Byte 0): 32 => 32
4177 11:45:32.266058 Write leveling (Byte 1): 31 => 31
4178 11:45:32.269220 DramcWriteLeveling(PI) end<-----
4179 11:45:32.269323
4180 11:45:32.269413 ==
4181 11:45:32.272250 Dram Type= 6, Freq= 0, CH_0, rank 1
4182 11:45:32.276065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 11:45:32.276168 ==
4184 11:45:32.279141 [Gating] SW mode calibration
4185 11:45:32.285827 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4186 11:45:32.292143 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4187 11:45:32.295726 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 11:45:32.302203 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 11:45:32.305523 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4190 11:45:32.308647 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4191 11:45:32.315173 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4192 11:45:32.318383 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 11:45:32.322369 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 11:45:32.328382 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 11:45:32.332132 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 11:45:32.335605 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 11:45:32.341547 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 11:45:32.345157 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
4199 11:45:32.348223 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4200 11:45:32.354795 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 11:45:32.357869 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 11:45:32.361162 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 11:45:32.368290 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 11:45:32.371427 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 11:45:32.374429 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 11:45:32.381148 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4207 11:45:32.384228 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 11:45:32.388017 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 11:45:32.394369 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 11:45:32.397436 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 11:45:32.401094 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 11:45:32.407177 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 11:45:32.410834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 11:45:32.413912 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 11:45:32.420541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 11:45:32.423917 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 11:45:32.427099 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 11:45:32.433602 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 11:45:32.437013 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 11:45:32.440208 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 11:45:32.446742 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 11:45:32.450425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 11:45:32.453518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4224 11:45:32.456797 Total UI for P1: 0, mck2ui 16
4225 11:45:32.459925 best dqsien dly found for B1: ( 0, 13, 14)
4226 11:45:32.466443 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 11:45:32.466517 Total UI for P1: 0, mck2ui 16
4228 11:45:32.473547 best dqsien dly found for B0: ( 0, 13, 16)
4229 11:45:32.476677 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4230 11:45:32.479943 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4231 11:45:32.480018
4232 11:45:32.483443 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4233 11:45:32.486710 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4234 11:45:32.489586 [Gating] SW calibration Done
4235 11:45:32.489697 ==
4236 11:45:32.492751 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 11:45:32.496472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 11:45:32.496579 ==
4239 11:45:32.499478 RX Vref Scan: 0
4240 11:45:32.499582
4241 11:45:32.502964 RX Vref 0 -> 0, step: 1
4242 11:45:32.503068
4243 11:45:32.503168 RX Delay -230 -> 252, step: 16
4244 11:45:32.509447 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4245 11:45:32.512612 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4246 11:45:32.516630 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4247 11:45:32.519419 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4248 11:45:32.525968 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4249 11:45:32.529178 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4250 11:45:32.532259 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4251 11:45:32.535988 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4252 11:45:32.542406 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4253 11:45:32.545495 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4254 11:45:32.548744 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4255 11:45:32.552137 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4256 11:45:32.559003 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4257 11:45:32.562124 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4258 11:45:32.565222 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4259 11:45:32.568531 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4260 11:45:32.568610 ==
4261 11:45:32.571968 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 11:45:32.578864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 11:45:32.578964 ==
4264 11:45:32.579029 DQS Delay:
4265 11:45:32.582289 DQS0 = 0, DQS1 = 0
4266 11:45:32.582388 DQM Delay:
4267 11:45:32.582481 DQM0 = 35, DQM1 = 29
4268 11:45:32.585462 DQ Delay:
4269 11:45:32.588609 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4270 11:45:32.591803 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4271 11:45:32.594879 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =25
4272 11:45:32.598488 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =33
4273 11:45:32.598595
4274 11:45:32.598687
4275 11:45:32.598774 ==
4276 11:45:32.601476 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 11:45:32.605049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 11:45:32.605149 ==
4279 11:45:32.605244
4280 11:45:32.605331
4281 11:45:32.608081 TX Vref Scan disable
4282 11:45:32.611575 == TX Byte 0 ==
4283 11:45:32.614479 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4284 11:45:32.618258 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4285 11:45:32.621219 == TX Byte 1 ==
4286 11:45:32.624822 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 11:45:32.628097 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 11:45:32.628182 ==
4289 11:45:32.631197 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 11:45:32.637611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 11:45:32.637694 ==
4292 11:45:32.637759
4293 11:45:32.637818
4294 11:45:32.637873 TX Vref Scan disable
4295 11:45:32.642067 == TX Byte 0 ==
4296 11:45:32.645112 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4297 11:45:32.651756 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4298 11:45:32.651838 == TX Byte 1 ==
4299 11:45:32.655683 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4300 11:45:32.661819 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4301 11:45:32.661903
4302 11:45:32.661967 [DATLAT]
4303 11:45:32.662026 Freq=600, CH0 RK1
4304 11:45:32.662084
4305 11:45:32.665024 DATLAT Default: 0x9
4306 11:45:32.665104 0, 0xFFFF, sum = 0
4307 11:45:32.668317 1, 0xFFFF, sum = 0
4308 11:45:32.668397 2, 0xFFFF, sum = 0
4309 11:45:32.671462 3, 0xFFFF, sum = 0
4310 11:45:32.674904 4, 0xFFFF, sum = 0
4311 11:45:32.674980 5, 0xFFFF, sum = 0
4312 11:45:32.678662 6, 0xFFFF, sum = 0
4313 11:45:32.678762 7, 0xFFFF, sum = 0
4314 11:45:32.681889 8, 0x0, sum = 1
4315 11:45:32.681997 9, 0x0, sum = 2
4316 11:45:32.682090 10, 0x0, sum = 3
4317 11:45:32.685152 11, 0x0, sum = 4
4318 11:45:32.685234 best_step = 9
4319 11:45:32.685296
4320 11:45:32.685353 ==
4321 11:45:32.688300 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 11:45:32.695185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 11:45:32.695266 ==
4324 11:45:32.695329 RX Vref Scan: 0
4325 11:45:32.695387
4326 11:45:32.698402 RX Vref 0 -> 0, step: 1
4327 11:45:32.698471
4328 11:45:32.701540 RX Delay -195 -> 252, step: 8
4329 11:45:32.704617 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4330 11:45:32.711106 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4331 11:45:32.714706 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4332 11:45:32.717937 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4333 11:45:32.721484 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4334 11:45:32.728213 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4335 11:45:32.731214 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4336 11:45:32.734190 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4337 11:45:32.737602 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4338 11:45:32.744603 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4339 11:45:32.747646 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4340 11:45:32.750841 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4341 11:45:32.754337 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4342 11:45:32.760716 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4343 11:45:32.764005 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4344 11:45:32.767161 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4345 11:45:32.767241 ==
4346 11:45:32.770352 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 11:45:32.774115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 11:45:32.777385 ==
4349 11:45:32.777460 DQS Delay:
4350 11:45:32.777521 DQS0 = 0, DQS1 = 0
4351 11:45:32.780658 DQM Delay:
4352 11:45:32.780737 DQM0 = 33, DQM1 = 28
4353 11:45:32.783810 DQ Delay:
4354 11:45:32.787166 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4355 11:45:32.787243 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =40
4356 11:45:32.790259 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4357 11:45:32.796551 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4358 11:45:32.796663
4359 11:45:32.796765
4360 11:45:32.803143 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4361 11:45:32.806359 CH0 RK1: MR19=808, MR18=6B3A
4362 11:45:32.813191 CH0_RK1: MR19=0x808, MR18=0x6B3A, DQSOSC=389, MR23=63, INC=173, DEC=115
4363 11:45:32.816853 [RxdqsGatingPostProcess] freq 600
4364 11:45:32.819785 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4365 11:45:32.823488 Pre-setting of DQS Precalculation
4366 11:45:32.830091 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4367 11:45:32.830175 ==
4368 11:45:32.832988 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 11:45:32.836064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 11:45:32.836148 ==
4371 11:45:32.842807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 11:45:32.849530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 11:45:32.852709 [CA 0] Center 36 (6~66) winsize 61
4374 11:45:32.855915 [CA 1] Center 36 (6~66) winsize 61
4375 11:45:32.859257 [CA 2] Center 34 (4~65) winsize 62
4376 11:45:32.862610 [CA 3] Center 34 (4~65) winsize 62
4377 11:45:32.865693 [CA 4] Center 34 (4~65) winsize 62
4378 11:45:32.869325 [CA 5] Center 33 (3~64) winsize 62
4379 11:45:32.869422
4380 11:45:32.872586 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 11:45:32.872667
4382 11:45:32.875779 [CATrainingPosCal] consider 1 rank data
4383 11:45:32.879094 u2DelayCellTimex100 = 270/100 ps
4384 11:45:32.882367 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4385 11:45:32.885625 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4386 11:45:32.888922 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 11:45:32.892126 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 11:45:32.895561 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 11:45:32.898733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 11:45:32.901861
4391 11:45:32.905585 CA PerBit enable=1, Macro0, CA PI delay=33
4392 11:45:32.905690
4393 11:45:32.908781 [CBTSetCACLKResult] CA Dly = 33
4394 11:45:32.908912 CS Dly: 4 (0~35)
4395 11:45:32.909006 ==
4396 11:45:32.912038 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 11:45:32.915164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 11:45:32.915264 ==
4399 11:45:32.921608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 11:45:32.928265 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4401 11:45:32.931764 [CA 0] Center 35 (5~66) winsize 62
4402 11:45:32.935456 [CA 1] Center 36 (5~67) winsize 63
4403 11:45:32.938210 [CA 2] Center 34 (4~65) winsize 62
4404 11:45:32.941619 [CA 3] Center 34 (3~65) winsize 63
4405 11:45:32.945150 [CA 4] Center 34 (4~65) winsize 62
4406 11:45:32.948092 [CA 5] Center 33 (3~64) winsize 62
4407 11:45:32.948163
4408 11:45:32.951744 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4409 11:45:32.951824
4410 11:45:32.954806 [CATrainingPosCal] consider 2 rank data
4411 11:45:32.958356 u2DelayCellTimex100 = 270/100 ps
4412 11:45:32.961255 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4413 11:45:32.964511 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4414 11:45:32.968196 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 11:45:32.974895 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 11:45:32.978158 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4417 11:45:32.981317 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 11:45:32.981419
4419 11:45:32.984450 CA PerBit enable=1, Macro0, CA PI delay=33
4420 11:45:32.984550
4421 11:45:32.987561 [CBTSetCACLKResult] CA Dly = 33
4422 11:45:32.987661 CS Dly: 4 (0~36)
4423 11:45:32.987756
4424 11:45:32.991201 ----->DramcWriteLeveling(PI) begin...
4425 11:45:32.994251 ==
4426 11:45:32.997382 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 11:45:33.000501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 11:45:33.000599 ==
4429 11:45:33.004238 Write leveling (Byte 0): 27 => 27
4430 11:45:33.007296 Write leveling (Byte 1): 31 => 31
4431 11:45:33.011040 DramcWriteLeveling(PI) end<-----
4432 11:45:33.011137
4433 11:45:33.011227 ==
4434 11:45:33.014105 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 11:45:33.017285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 11:45:33.017381 ==
4437 11:45:33.020490 [Gating] SW mode calibration
4438 11:45:33.027197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4439 11:45:33.033638 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4440 11:45:33.037257 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 11:45:33.040518 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 11:45:33.047295 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 11:45:33.050031 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (0 1) (1 0)
4444 11:45:33.053413 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (1 1)
4445 11:45:33.059802 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 11:45:33.063519 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 11:45:33.066513 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 11:45:33.073286 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 11:45:33.076458 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 11:45:33.080047 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 11:45:33.086305 0 10 12 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
4452 11:45:33.089429 0 10 16 | B1->B0 | 4545 4141 | 0 0 | (0 0) (0 0)
4453 11:45:33.093228 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 11:45:33.099430 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 11:45:33.103157 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 11:45:33.106198 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 11:45:33.112496 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 11:45:33.116255 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 11:45:33.119566 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4460 11:45:33.125819 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4461 11:45:33.129019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 11:45:33.132818 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 11:45:33.138959 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 11:45:33.142438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 11:45:33.145811 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 11:45:33.152125 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 11:45:33.155799 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 11:45:33.158796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 11:45:33.165114 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 11:45:33.168578 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 11:45:33.172104 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 11:45:33.178667 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 11:45:33.181583 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 11:45:33.185125 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 11:45:33.191734 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 11:45:33.195145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4477 11:45:33.198467 Total UI for P1: 0, mck2ui 16
4478 11:45:33.201522 best dqsien dly found for B0: ( 0, 13, 14)
4479 11:45:33.204733 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 11:45:33.208021 Total UI for P1: 0, mck2ui 16
4481 11:45:33.211241 best dqsien dly found for B1: ( 0, 13, 16)
4482 11:45:33.214428 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4483 11:45:33.221413 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4484 11:45:33.221522
4485 11:45:33.224694 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4486 11:45:33.227821 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4487 11:45:33.231143 [Gating] SW calibration Done
4488 11:45:33.231214 ==
4489 11:45:33.234646 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 11:45:33.237544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 11:45:33.237648 ==
4492 11:45:33.240911 RX Vref Scan: 0
4493 11:45:33.241016
4494 11:45:33.241105 RX Vref 0 -> 0, step: 1
4495 11:45:33.241198
4496 11:45:33.244002 RX Delay -230 -> 252, step: 16
4497 11:45:33.247680 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4498 11:45:33.254291 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4499 11:45:33.257388 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4500 11:45:33.260518 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4501 11:45:33.264140 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4502 11:45:33.270260 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4503 11:45:33.273900 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4504 11:45:33.276865 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4505 11:45:33.280337 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4506 11:45:33.283990 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4507 11:45:33.290640 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4508 11:45:33.293569 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4509 11:45:33.296934 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4510 11:45:33.300224 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4511 11:45:33.306685 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4512 11:45:33.309970 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4513 11:45:33.310045 ==
4514 11:45:33.313238 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 11:45:33.316609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 11:45:33.316692 ==
4517 11:45:33.320244 DQS Delay:
4518 11:45:33.320354 DQS0 = 0, DQS1 = 0
4519 11:45:33.323453 DQM Delay:
4520 11:45:33.323554 DQM0 = 38, DQM1 = 29
4521 11:45:33.323644 DQ Delay:
4522 11:45:33.326602 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4523 11:45:33.329795 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4524 11:45:33.333129 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4525 11:45:33.336503 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4526 11:45:33.336604
4527 11:45:33.336695
4528 11:45:33.339668 ==
4529 11:45:33.343019 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 11:45:33.346087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 11:45:33.346171 ==
4532 11:45:33.346236
4533 11:45:33.346297
4534 11:45:33.349558 TX Vref Scan disable
4535 11:45:33.349640 == TX Byte 0 ==
4536 11:45:33.356551 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4537 11:45:33.359539 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4538 11:45:33.359623 == TX Byte 1 ==
4539 11:45:33.365938 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4540 11:45:33.369516 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4541 11:45:33.369599 ==
4542 11:45:33.372533 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 11:45:33.375659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 11:45:33.375743 ==
4545 11:45:33.375807
4546 11:45:33.375867
4547 11:45:33.379411 TX Vref Scan disable
4548 11:45:33.382619 == TX Byte 0 ==
4549 11:45:33.385730 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4550 11:45:33.392606 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4551 11:45:33.392717 == TX Byte 1 ==
4552 11:45:33.395808 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4553 11:45:33.402037 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4554 11:45:33.402150
4555 11:45:33.402251 [DATLAT]
4556 11:45:33.402341 Freq=600, CH1 RK0
4557 11:45:33.402440
4558 11:45:33.405134 DATLAT Default: 0x9
4559 11:45:33.409109 0, 0xFFFF, sum = 0
4560 11:45:33.409215 1, 0xFFFF, sum = 0
4561 11:45:33.412260 2, 0xFFFF, sum = 0
4562 11:45:33.412372 3, 0xFFFF, sum = 0
4563 11:45:33.415488 4, 0xFFFF, sum = 0
4564 11:45:33.415585 5, 0xFFFF, sum = 0
4565 11:45:33.418637 6, 0xFFFF, sum = 0
4566 11:45:33.418738 7, 0xFFFF, sum = 0
4567 11:45:33.421900 8, 0x0, sum = 1
4568 11:45:33.422001 9, 0x0, sum = 2
4569 11:45:33.425142 10, 0x0, sum = 3
4570 11:45:33.425250 11, 0x0, sum = 4
4571 11:45:33.425342 best_step = 9
4572 11:45:33.425428
4573 11:45:33.428259 ==
4574 11:45:33.431543 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 11:45:33.435392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 11:45:33.435479 ==
4577 11:45:33.435573 RX Vref Scan: 1
4578 11:45:33.435665
4579 11:45:33.438584 RX Vref 0 -> 0, step: 1
4580 11:45:33.438691
4581 11:45:33.441807 RX Delay -195 -> 252, step: 8
4582 11:45:33.441912
4583 11:45:33.445021 Set Vref, RX VrefLevel [Byte0]: 54
4584 11:45:33.448107 [Byte1]: 48
4585 11:45:33.448183
4586 11:45:33.451477 Final RX Vref Byte 0 = 54 to rank0
4587 11:45:33.454587 Final RX Vref Byte 1 = 48 to rank0
4588 11:45:33.457961 Final RX Vref Byte 0 = 54 to rank1
4589 11:45:33.461156 Final RX Vref Byte 1 = 48 to rank1==
4590 11:45:33.464385 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 11:45:33.470920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 11:45:33.471022 ==
4593 11:45:33.471102 DQS Delay:
4594 11:45:33.471161 DQS0 = 0, DQS1 = 0
4595 11:45:33.474474 DQM Delay:
4596 11:45:33.474592 DQM0 = 39, DQM1 = 28
4597 11:45:33.478065 DQ Delay:
4598 11:45:33.480835 DQ0 =48, DQ1 =32, DQ2 =28, DQ3 =36
4599 11:45:33.484350 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4600 11:45:33.487890 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4601 11:45:33.490814 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4602 11:45:33.490918
4603 11:45:33.490981
4604 11:45:33.497622 [DQSOSCAuto] RK0, (LSB)MR18= 0x2330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4605 11:45:33.500842 CH1 RK0: MR19=808, MR18=2330
4606 11:45:33.507419 CH1_RK0: MR19=0x808, MR18=0x2330, DQSOSC=400, MR23=63, INC=163, DEC=109
4607 11:45:33.507502
4608 11:45:33.511121 ----->DramcWriteLeveling(PI) begin...
4609 11:45:33.511204 ==
4610 11:45:33.514182 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 11:45:33.517403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 11:45:33.517484 ==
4613 11:45:33.520667 Write leveling (Byte 0): 31 => 31
4614 11:45:33.523928 Write leveling (Byte 1): 31 => 31
4615 11:45:33.527146 DramcWriteLeveling(PI) end<-----
4616 11:45:33.527227
4617 11:45:33.527289 ==
4618 11:45:33.530423 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 11:45:33.534194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 11:45:33.537529 ==
4621 11:45:33.537600 [Gating] SW mode calibration
4622 11:45:33.547162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4623 11:45:33.550466 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4624 11:45:33.553660 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 11:45:33.560191 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 11:45:33.563292 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4627 11:45:33.566650 0 9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (0 0)
4628 11:45:33.573547 0 9 16 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
4629 11:45:33.576658 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 11:45:33.579812 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 11:45:33.586469 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 11:45:33.590105 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 11:45:33.592984 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4634 11:45:33.599616 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4635 11:45:33.603193 0 10 12 | B1->B0 | 3333 4242 | 0 0 | (0 0) (0 0)
4636 11:45:33.606183 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4637 11:45:33.612756 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 11:45:33.615901 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 11:45:33.619522 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 11:45:33.626222 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 11:45:33.629484 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 11:45:33.632578 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 11:45:33.638902 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 11:45:33.642181 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4645 11:45:33.645998 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 11:45:33.652585 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 11:45:33.655856 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 11:45:33.659088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 11:45:33.665826 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 11:45:33.669103 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 11:45:33.672329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 11:45:33.678749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 11:45:33.681836 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 11:45:33.684957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 11:45:33.691558 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 11:45:33.695107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 11:45:33.698028 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 11:45:33.704953 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4659 11:45:33.708494 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4660 11:45:33.711622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 11:45:33.715125 Total UI for P1: 0, mck2ui 16
4662 11:45:33.718218 best dqsien dly found for B0: ( 0, 13, 10)
4663 11:45:33.721354 Total UI for P1: 0, mck2ui 16
4664 11:45:33.725039 best dqsien dly found for B1: ( 0, 13, 12)
4665 11:45:33.728288 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4666 11:45:33.734506 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4667 11:45:33.734588
4668 11:45:33.737812 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4669 11:45:33.741400 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4670 11:45:33.744696 [Gating] SW calibration Done
4671 11:45:33.744804 ==
4672 11:45:33.748034 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 11:45:33.751188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 11:45:33.751298 ==
4675 11:45:33.754395 RX Vref Scan: 0
4676 11:45:33.754499
4677 11:45:33.754589 RX Vref 0 -> 0, step: 1
4678 11:45:33.754675
4679 11:45:33.758417 RX Delay -230 -> 252, step: 16
4680 11:45:33.761320 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4681 11:45:33.767868 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4682 11:45:33.771083 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4683 11:45:33.774362 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4684 11:45:33.777670 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4685 11:45:33.784229 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4686 11:45:33.787443 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4687 11:45:33.791142 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4688 11:45:33.794304 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4689 11:45:33.797277 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4690 11:45:33.803933 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4691 11:45:33.807676 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4692 11:45:33.810551 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4693 11:45:33.814139 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4694 11:45:33.820366 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4695 11:45:33.823943 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4696 11:45:33.824024 ==
4697 11:45:33.826945 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 11:45:33.830036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 11:45:33.830111 ==
4700 11:45:33.833623 DQS Delay:
4701 11:45:33.833707 DQS0 = 0, DQS1 = 0
4702 11:45:33.836995 DQM Delay:
4703 11:45:33.837074 DQM0 = 35, DQM1 = 29
4704 11:45:33.837138 DQ Delay:
4705 11:45:33.839963 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4706 11:45:33.843769 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4707 11:45:33.847063 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4708 11:45:33.850200 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4709 11:45:33.850269
4710 11:45:33.853415
4711 11:45:33.853499 ==
4712 11:45:33.856696 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 11:45:33.860009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 11:45:33.860078 ==
4715 11:45:33.860136
4716 11:45:33.860190
4717 11:45:33.863089 TX Vref Scan disable
4718 11:45:33.863155 == TX Byte 0 ==
4719 11:45:33.869616 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4720 11:45:33.872790 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4721 11:45:33.872870 == TX Byte 1 ==
4722 11:45:33.879267 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4723 11:45:33.882493 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4724 11:45:33.882568 ==
4725 11:45:33.885774 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 11:45:33.889140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 11:45:33.889250 ==
4728 11:45:33.889345
4729 11:45:33.892519
4730 11:45:33.892648 TX Vref Scan disable
4731 11:45:33.895787 == TX Byte 0 ==
4732 11:45:33.899037 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4733 11:45:33.905771 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4734 11:45:33.905883 == TX Byte 1 ==
4735 11:45:33.909369 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4736 11:45:33.915624 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4737 11:45:33.915709
4738 11:45:33.915772 [DATLAT]
4739 11:45:33.915830 Freq=600, CH1 RK1
4740 11:45:33.915897
4741 11:45:33.919010 DATLAT Default: 0x9
4742 11:45:33.921956 0, 0xFFFF, sum = 0
4743 11:45:33.922060 1, 0xFFFF, sum = 0
4744 11:45:33.925674 2, 0xFFFF, sum = 0
4745 11:45:33.925815 3, 0xFFFF, sum = 0
4746 11:45:33.928779 4, 0xFFFF, sum = 0
4747 11:45:33.928878 5, 0xFFFF, sum = 0
4748 11:45:33.932191 6, 0xFFFF, sum = 0
4749 11:45:33.932307 7, 0xFFFF, sum = 0
4750 11:45:33.935185 8, 0x0, sum = 1
4751 11:45:33.935304 9, 0x0, sum = 2
4752 11:45:33.938786 10, 0x0, sum = 3
4753 11:45:33.938924 11, 0x0, sum = 4
4754 11:45:33.938994 best_step = 9
4755 11:45:33.939055
4756 11:45:33.941817 ==
4757 11:45:33.945083 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 11:45:33.948173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 11:45:33.948249 ==
4760 11:45:33.948311 RX Vref Scan: 0
4761 11:45:33.948373
4762 11:45:33.951472 RX Vref 0 -> 0, step: 1
4763 11:45:33.951567
4764 11:45:33.955323 RX Delay -195 -> 252, step: 8
4765 11:45:33.961729 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4766 11:45:33.965035 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4767 11:45:33.968149 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4768 11:45:33.971167 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4769 11:45:33.978221 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4770 11:45:33.981428 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4771 11:45:33.984625 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4772 11:45:33.987847 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4773 11:45:33.991016 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4774 11:45:33.998108 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4775 11:45:34.001433 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4776 11:45:34.004760 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4777 11:45:34.008079 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4778 11:45:34.014198 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4779 11:45:34.017895 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4780 11:45:34.020909 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4781 11:45:34.021019 ==
4782 11:45:34.024042 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 11:45:34.030921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 11:45:34.031028 ==
4785 11:45:34.031130 DQS Delay:
4786 11:45:34.031220 DQS0 = 0, DQS1 = 0
4787 11:45:34.033964 DQM Delay:
4788 11:45:34.034066 DQM0 = 36, DQM1 = 30
4789 11:45:34.037635 DQ Delay:
4790 11:45:34.040642 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4791 11:45:34.044323 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4792 11:45:34.047222 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4793 11:45:34.050866 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4794 11:45:34.050957
4795 11:45:34.051018
4796 11:45:34.057050 [DQSOSCAuto] RK1, (LSB)MR18= 0x3453, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4797 11:45:34.060938 CH1 RK1: MR19=808, MR18=3453
4798 11:45:34.067388 CH1_RK1: MR19=0x808, MR18=0x3453, DQSOSC=394, MR23=63, INC=168, DEC=112
4799 11:45:34.070576 [RxdqsGatingPostProcess] freq 600
4800 11:45:34.073784 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4801 11:45:34.077276 Pre-setting of DQS Precalculation
4802 11:45:34.083498 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4803 11:45:34.089899 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4804 11:45:34.096446 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4805 11:45:34.096551
4806 11:45:34.096643
4807 11:45:34.099761 [Calibration Summary] 1200 Mbps
4808 11:45:34.099867 CH 0, Rank 0
4809 11:45:34.103016 SW Impedance : PASS
4810 11:45:34.106421 DUTY Scan : NO K
4811 11:45:34.106521 ZQ Calibration : PASS
4812 11:45:34.109658 Jitter Meter : NO K
4813 11:45:34.113432 CBT Training : PASS
4814 11:45:34.113541 Write leveling : PASS
4815 11:45:34.116475 RX DQS gating : PASS
4816 11:45:34.119622 RX DQ/DQS(RDDQC) : PASS
4817 11:45:34.119729 TX DQ/DQS : PASS
4818 11:45:34.123055 RX DATLAT : PASS
4819 11:45:34.126011 RX DQ/DQS(Engine): PASS
4820 11:45:34.126091 TX OE : NO K
4821 11:45:34.129854 All Pass.
4822 11:45:34.129935
4823 11:45:34.129999 CH 0, Rank 1
4824 11:45:34.132840 SW Impedance : PASS
4825 11:45:34.132921 DUTY Scan : NO K
4826 11:45:34.135854 ZQ Calibration : PASS
4827 11:45:34.139512 Jitter Meter : NO K
4828 11:45:34.139594 CBT Training : PASS
4829 11:45:34.142564 Write leveling : PASS
4830 11:45:34.146093 RX DQS gating : PASS
4831 11:45:34.146174 RX DQ/DQS(RDDQC) : PASS
4832 11:45:34.149065 TX DQ/DQS : PASS
4833 11:45:34.152697 RX DATLAT : PASS
4834 11:45:34.152778 RX DQ/DQS(Engine): PASS
4835 11:45:34.156231 TX OE : NO K
4836 11:45:34.156313 All Pass.
4837 11:45:34.156376
4838 11:45:34.159410 CH 1, Rank 0
4839 11:45:34.159492 SW Impedance : PASS
4840 11:45:34.162413 DUTY Scan : NO K
4841 11:45:34.165682 ZQ Calibration : PASS
4842 11:45:34.165763 Jitter Meter : NO K
4843 11:45:34.168919 CBT Training : PASS
4844 11:45:34.172132 Write leveling : PASS
4845 11:45:34.172213 RX DQS gating : PASS
4846 11:45:34.175983 RX DQ/DQS(RDDQC) : PASS
4847 11:45:34.179071 TX DQ/DQS : PASS
4848 11:45:34.179152 RX DATLAT : PASS
4849 11:45:34.182143 RX DQ/DQS(Engine): PASS
4850 11:45:34.182225 TX OE : NO K
4851 11:45:34.185479 All Pass.
4852 11:45:34.185602
4853 11:45:34.185707 CH 1, Rank 1
4854 11:45:34.188686 SW Impedance : PASS
4855 11:45:34.188776 DUTY Scan : NO K
4856 11:45:34.191906 ZQ Calibration : PASS
4857 11:45:34.195317 Jitter Meter : NO K
4858 11:45:34.195419 CBT Training : PASS
4859 11:45:34.198401 Write leveling : PASS
4860 11:45:34.202372 RX DQS gating : PASS
4861 11:45:34.202456 RX DQ/DQS(RDDQC) : PASS
4862 11:45:34.205624 TX DQ/DQS : PASS
4863 11:45:34.208735 RX DATLAT : PASS
4864 11:45:34.208818 RX DQ/DQS(Engine): PASS
4865 11:45:34.212054 TX OE : NO K
4866 11:45:34.212163 All Pass.
4867 11:45:34.212256
4868 11:45:34.215403 DramC Write-DBI off
4869 11:45:34.218666 PER_BANK_REFRESH: Hybrid Mode
4870 11:45:34.218754 TX_TRACKING: ON
4871 11:45:34.228128 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4872 11:45:34.231396 [FAST_K] Save calibration result to emmc
4873 11:45:34.235149 dramc_set_vcore_voltage set vcore to 662500
4874 11:45:34.238126 Read voltage for 933, 3
4875 11:45:34.238235 Vio18 = 0
4876 11:45:34.238329 Vcore = 662500
4877 11:45:34.241433 Vdram = 0
4878 11:45:34.241508 Vddq = 0
4879 11:45:34.241571 Vmddr = 0
4880 11:45:34.248096 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4881 11:45:34.255041 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4882 11:45:34.255146 MEM_TYPE=3, freq_sel=17
4883 11:45:34.257877 sv_algorithm_assistance_LP4_1600
4884 11:45:34.261073 ============ PULL DRAM RESETB DOWN ============
4885 11:45:34.267923 ========== PULL DRAM RESETB DOWN end =========
4886 11:45:34.271136 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4887 11:45:34.274525 ===================================
4888 11:45:34.277516 LPDDR4 DRAM CONFIGURATION
4889 11:45:34.280548 ===================================
4890 11:45:34.280657 EX_ROW_EN[0] = 0x0
4891 11:45:34.284290 EX_ROW_EN[1] = 0x0
4892 11:45:34.284392 LP4Y_EN = 0x0
4893 11:45:34.287411 WORK_FSP = 0x0
4894 11:45:34.290707 WL = 0x3
4895 11:45:34.290810 RL = 0x3
4896 11:45:34.293844 BL = 0x2
4897 11:45:34.293948 RPST = 0x0
4898 11:45:34.297194 RD_PRE = 0x0
4899 11:45:34.297273 WR_PRE = 0x1
4900 11:45:34.300589 WR_PST = 0x0
4901 11:45:34.300690 DBI_WR = 0x0
4902 11:45:34.303564 DBI_RD = 0x0
4903 11:45:34.303664 OTF = 0x1
4904 11:45:34.307245 ===================================
4905 11:45:34.310468 ===================================
4906 11:45:34.313560 ANA top config
4907 11:45:34.316743 ===================================
4908 11:45:34.316839 DLL_ASYNC_EN = 0
4909 11:45:34.320461 ALL_SLAVE_EN = 1
4910 11:45:34.323425 NEW_RANK_MODE = 1
4911 11:45:34.326637 DLL_IDLE_MODE = 1
4912 11:45:34.330479 LP45_APHY_COMB_EN = 1
4913 11:45:34.330576 TX_ODT_DIS = 1
4914 11:45:34.333633 NEW_8X_MODE = 1
4915 11:45:34.336922 ===================================
4916 11:45:34.339929 ===================================
4917 11:45:34.343632 data_rate = 1866
4918 11:45:34.346577 CKR = 1
4919 11:45:34.350177 DQ_P2S_RATIO = 8
4920 11:45:34.353345 ===================================
4921 11:45:34.356399 CA_P2S_RATIO = 8
4922 11:45:34.356507 DQ_CA_OPEN = 0
4923 11:45:34.360146 DQ_SEMI_OPEN = 0
4924 11:45:34.363338 CA_SEMI_OPEN = 0
4925 11:45:34.366367 CA_FULL_RATE = 0
4926 11:45:34.369569 DQ_CKDIV4_EN = 1
4927 11:45:34.373070 CA_CKDIV4_EN = 1
4928 11:45:34.373155 CA_PREDIV_EN = 0
4929 11:45:34.376658 PH8_DLY = 0
4930 11:45:34.379870 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4931 11:45:34.383130 DQ_AAMCK_DIV = 4
4932 11:45:34.386172 CA_AAMCK_DIV = 4
4933 11:45:34.389937 CA_ADMCK_DIV = 4
4934 11:45:34.390019 DQ_TRACK_CA_EN = 0
4935 11:45:34.393313 CA_PICK = 933
4936 11:45:34.396561 CA_MCKIO = 933
4937 11:45:34.399727 MCKIO_SEMI = 0
4938 11:45:34.402977 PLL_FREQ = 3732
4939 11:45:34.406171 DQ_UI_PI_RATIO = 32
4940 11:45:34.409463 CA_UI_PI_RATIO = 0
4941 11:45:34.412772 ===================================
4942 11:45:34.416073 ===================================
4943 11:45:34.416159 memory_type:LPDDR4
4944 11:45:34.419277 GP_NUM : 10
4945 11:45:34.422563 SRAM_EN : 1
4946 11:45:34.422692 MD32_EN : 0
4947 11:45:34.425651 ===================================
4948 11:45:34.429391 [ANA_INIT] >>>>>>>>>>>>>>
4949 11:45:34.432645 <<<<<< [CONFIGURE PHASE]: ANA_TX
4950 11:45:34.435956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4951 11:45:34.439254 ===================================
4952 11:45:34.442541 data_rate = 1866,PCW = 0X8f00
4953 11:45:34.445606 ===================================
4954 11:45:34.448906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4955 11:45:34.452492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 11:45:34.458782 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 11:45:34.462660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4958 11:45:34.465584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4959 11:45:34.468663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4960 11:45:34.472205 [ANA_INIT] flow start
4961 11:45:34.475413 [ANA_INIT] PLL >>>>>>>>
4962 11:45:34.475488 [ANA_INIT] PLL <<<<<<<<
4963 11:45:34.478400 [ANA_INIT] MIDPI >>>>>>>>
4964 11:45:34.481670 [ANA_INIT] MIDPI <<<<<<<<
4965 11:45:34.485184 [ANA_INIT] DLL >>>>>>>>
4966 11:45:34.485268 [ANA_INIT] flow end
4967 11:45:34.488187 ============ LP4 DIFF to SE enter ============
4968 11:45:34.494950 ============ LP4 DIFF to SE exit ============
4969 11:45:34.495047 [ANA_INIT] <<<<<<<<<<<<<
4970 11:45:34.498119 [Flow] Enable top DCM control >>>>>
4971 11:45:34.501346 [Flow] Enable top DCM control <<<<<
4972 11:45:34.504775 Enable DLL master slave shuffle
4973 11:45:34.511882 ==============================================================
4974 11:45:34.514990 Gating Mode config
4975 11:45:34.518329 ==============================================================
4976 11:45:34.521558 Config description:
4977 11:45:34.531144 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4978 11:45:34.537533 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4979 11:45:34.541440 SELPH_MODE 0: By rank 1: By Phase
4980 11:45:34.547884 ==============================================================
4981 11:45:34.551058 GAT_TRACK_EN = 1
4982 11:45:34.554138 RX_GATING_MODE = 2
4983 11:45:34.557765 RX_GATING_TRACK_MODE = 2
4984 11:45:34.560933 SELPH_MODE = 1
4985 11:45:34.561021 PICG_EARLY_EN = 1
4986 11:45:34.564034 VALID_LAT_VALUE = 1
4987 11:45:34.570800 ==============================================================
4988 11:45:34.573787 Enter into Gating configuration >>>>
4989 11:45:34.577473 Exit from Gating configuration <<<<
4990 11:45:34.580439 Enter into DVFS_PRE_config >>>>>
4991 11:45:34.590165 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4992 11:45:34.593926 Exit from DVFS_PRE_config <<<<<
4993 11:45:34.597081 Enter into PICG configuration >>>>
4994 11:45:34.600493 Exit from PICG configuration <<<<
4995 11:45:34.603623 [RX_INPUT] configuration >>>>>
4996 11:45:34.606571 [RX_INPUT] configuration <<<<<
4997 11:45:34.613078 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4998 11:45:34.616441 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4999 11:45:34.623553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 11:45:34.629871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 11:45:34.636364 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 11:45:34.643482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 11:45:34.646557 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5004 11:45:34.649730 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5005 11:45:34.652862 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5006 11:45:34.659651 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5007 11:45:34.662765 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5008 11:45:34.665945 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5009 11:45:34.669286 ===================================
5010 11:45:34.672450 LPDDR4 DRAM CONFIGURATION
5011 11:45:34.675769 ===================================
5012 11:45:34.679424 EX_ROW_EN[0] = 0x0
5013 11:45:34.679518 EX_ROW_EN[1] = 0x0
5014 11:45:34.682572 LP4Y_EN = 0x0
5015 11:45:34.682652 WORK_FSP = 0x0
5016 11:45:34.685990 WL = 0x3
5017 11:45:34.686070 RL = 0x3
5018 11:45:34.689027 BL = 0x2
5019 11:45:34.689107 RPST = 0x0
5020 11:45:34.692177 RD_PRE = 0x0
5021 11:45:34.692256 WR_PRE = 0x1
5022 11:45:34.695808 WR_PST = 0x0
5023 11:45:34.695929 DBI_WR = 0x0
5024 11:45:34.698811 DBI_RD = 0x0
5025 11:45:34.702567 OTF = 0x1
5026 11:45:34.705756 ===================================
5027 11:45:34.709043 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5028 11:45:34.711900 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5029 11:45:34.715056 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5030 11:45:34.718848 ===================================
5031 11:45:34.722026 LPDDR4 DRAM CONFIGURATION
5032 11:45:34.725279 ===================================
5033 11:45:34.728520 EX_ROW_EN[0] = 0x10
5034 11:45:34.728627 EX_ROW_EN[1] = 0x0
5035 11:45:34.731866 LP4Y_EN = 0x0
5036 11:45:34.731949 WORK_FSP = 0x0
5037 11:45:34.735100 WL = 0x3
5038 11:45:34.735178 RL = 0x3
5039 11:45:34.738373 BL = 0x2
5040 11:45:34.738474 RPST = 0x0
5041 11:45:34.741500 RD_PRE = 0x0
5042 11:45:34.741598 WR_PRE = 0x1
5043 11:45:34.744579 WR_PST = 0x0
5044 11:45:34.748446 DBI_WR = 0x0
5045 11:45:34.748519 DBI_RD = 0x0
5046 11:45:34.751671 OTF = 0x1
5047 11:45:34.754785 ===================================
5048 11:45:34.758149 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5049 11:45:34.763134 nWR fixed to 30
5050 11:45:34.766288 [ModeRegInit_LP4] CH0 RK0
5051 11:45:34.766394 [ModeRegInit_LP4] CH0 RK1
5052 11:45:34.770196 [ModeRegInit_LP4] CH1 RK0
5053 11:45:34.773403 [ModeRegInit_LP4] CH1 RK1
5054 11:45:34.773502 match AC timing 9
5055 11:45:34.779744 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5056 11:45:34.783441 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5057 11:45:34.786355 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5058 11:45:34.792872 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5059 11:45:34.796441 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5060 11:45:34.796545 ==
5061 11:45:34.799549 Dram Type= 6, Freq= 0, CH_0, rank 0
5062 11:45:34.803247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 11:45:34.803331 ==
5064 11:45:34.809604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 11:45:34.816373 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5066 11:45:34.819492 [CA 0] Center 38 (8~69) winsize 62
5067 11:45:34.822575 [CA 1] Center 38 (8~69) winsize 62
5068 11:45:34.826267 [CA 2] Center 35 (5~66) winsize 62
5069 11:45:34.829488 [CA 3] Center 35 (5~65) winsize 61
5070 11:45:34.832698 [CA 4] Center 34 (4~65) winsize 62
5071 11:45:34.835868 [CA 5] Center 33 (3~64) winsize 62
5072 11:45:34.835967
5073 11:45:34.839113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5074 11:45:34.839210
5075 11:45:34.842913 [CATrainingPosCal] consider 1 rank data
5076 11:45:34.845908 u2DelayCellTimex100 = 270/100 ps
5077 11:45:34.849200 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5078 11:45:34.852491 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5079 11:45:34.855708 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5080 11:45:34.862594 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5081 11:45:34.865949 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5082 11:45:34.869183 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5083 11:45:34.869286
5084 11:45:34.872598 CA PerBit enable=1, Macro0, CA PI delay=33
5085 11:45:34.872696
5086 11:45:34.875834 [CBTSetCACLKResult] CA Dly = 33
5087 11:45:34.875909 CS Dly: 7 (0~38)
5088 11:45:34.875971 ==
5089 11:45:34.879004 Dram Type= 6, Freq= 0, CH_0, rank 1
5090 11:45:34.885634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 11:45:34.885728 ==
5092 11:45:34.888948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 11:45:34.895380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5094 11:45:34.898360 [CA 0] Center 38 (8~69) winsize 62
5095 11:45:34.901825 [CA 1] Center 38 (8~69) winsize 62
5096 11:45:34.905453 [CA 2] Center 35 (5~65) winsize 61
5097 11:45:34.908889 [CA 3] Center 35 (5~65) winsize 61
5098 11:45:34.911769 [CA 4] Center 34 (4~64) winsize 61
5099 11:45:34.914780 [CA 5] Center 34 (4~64) winsize 61
5100 11:45:34.914885
5101 11:45:34.918494 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5102 11:45:34.918595
5103 11:45:34.921541 [CATrainingPosCal] consider 2 rank data
5104 11:45:34.925222 u2DelayCellTimex100 = 270/100 ps
5105 11:45:34.928511 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5106 11:45:34.934935 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5107 11:45:34.938381 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5108 11:45:34.941743 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5109 11:45:34.945002 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5110 11:45:34.948257 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5111 11:45:34.948358
5112 11:45:34.951262 CA PerBit enable=1, Macro0, CA PI delay=34
5113 11:45:34.951339
5114 11:45:34.954477 [CBTSetCACLKResult] CA Dly = 34
5115 11:45:34.958403 CS Dly: 7 (0~39)
5116 11:45:34.958509
5117 11:45:34.961610 ----->DramcWriteLeveling(PI) begin...
5118 11:45:34.961727 ==
5119 11:45:34.964945 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 11:45:34.968151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 11:45:34.968259 ==
5122 11:45:34.971273 Write leveling (Byte 0): 30 => 30
5123 11:45:34.974304 Write leveling (Byte 1): 29 => 29
5124 11:45:34.978166 DramcWriteLeveling(PI) end<-----
5125 11:45:34.978248
5126 11:45:34.978312 ==
5127 11:45:34.981339 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 11:45:34.984509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 11:45:34.984592 ==
5130 11:45:34.987896 [Gating] SW mode calibration
5131 11:45:34.994208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5132 11:45:35.000680 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5133 11:45:35.004462 0 14 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
5134 11:45:35.007504 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5135 11:45:35.013767 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 11:45:35.017389 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 11:45:35.020876 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 11:45:35.026853 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 11:45:35.030598 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 11:45:35.033688 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5141 11:45:35.040177 0 15 0 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 0)
5142 11:45:35.043459 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5143 11:45:35.046568 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 11:45:35.053526 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 11:45:35.056552 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 11:45:35.059826 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 11:45:35.066887 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 11:45:35.070055 0 15 28 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5149 11:45:35.073247 1 0 0 | B1->B0 | 2d2d 3838 | 0 0 | (0 0) (0 0)
5150 11:45:35.080279 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5151 11:45:35.083622 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 11:45:35.086935 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 11:45:35.092799 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 11:45:35.096574 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 11:45:35.099692 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 11:45:35.106265 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5157 11:45:35.109856 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5158 11:45:35.112800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5159 11:45:35.119310 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 11:45:35.122801 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 11:45:35.125830 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 11:45:35.132613 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 11:45:35.136175 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 11:45:35.139246 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 11:45:35.145806 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 11:45:35.148952 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 11:45:35.152034 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 11:45:35.158724 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 11:45:35.162531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 11:45:35.165702 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 11:45:35.172054 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 11:45:35.175316 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5173 11:45:35.178414 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 11:45:35.181932 Total UI for P1: 0, mck2ui 16
5175 11:45:35.185221 best dqsien dly found for B0: ( 1, 2, 28)
5176 11:45:35.191588 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5177 11:45:35.194779 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 11:45:35.198134 Total UI for P1: 0, mck2ui 16
5179 11:45:35.201514 best dqsien dly found for B1: ( 1, 3, 2)
5180 11:45:35.204747 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5181 11:45:35.207986 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5182 11:45:35.208093
5183 11:45:35.212030 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5184 11:45:35.218438 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5185 11:45:35.218547 [Gating] SW calibration Done
5186 11:45:35.218640 ==
5187 11:45:35.221516 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 11:45:35.227915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 11:45:35.228033 ==
5190 11:45:35.228127 RX Vref Scan: 0
5191 11:45:35.228218
5192 11:45:35.231109 RX Vref 0 -> 0, step: 1
5193 11:45:35.231209
5194 11:45:35.234667 RX Delay -80 -> 252, step: 8
5195 11:45:35.237570 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5196 11:45:35.241378 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5197 11:45:35.244529 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5198 11:45:35.247466 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5199 11:45:35.254222 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5200 11:45:35.257409 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5201 11:45:35.260637 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5202 11:45:35.264328 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5203 11:45:35.267471 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5204 11:45:35.273913 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5205 11:45:35.277185 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5206 11:45:35.280429 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5207 11:45:35.284321 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5208 11:45:35.287466 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5209 11:45:35.293692 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5210 11:45:35.297037 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5211 11:45:35.297113 ==
5212 11:45:35.300183 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 11:45:35.303920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 11:45:35.304003 ==
5215 11:45:35.307118 DQS Delay:
5216 11:45:35.307225 DQS0 = 0, DQS1 = 0
5217 11:45:35.307318 DQM Delay:
5218 11:45:35.310298 DQM0 = 95, DQM1 = 83
5219 11:45:35.310380 DQ Delay:
5220 11:45:35.313694 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5221 11:45:35.316907 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5222 11:45:35.320144 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5223 11:45:35.323449 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5224 11:45:35.323531
5225 11:45:35.323596
5226 11:45:35.323655 ==
5227 11:45:35.326593 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 11:45:35.333385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 11:45:35.333468 ==
5230 11:45:35.333532
5231 11:45:35.333591
5232 11:45:35.336428 TX Vref Scan disable
5233 11:45:35.336510 == TX Byte 0 ==
5234 11:45:35.339665 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5235 11:45:35.346227 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5236 11:45:35.346343 == TX Byte 1 ==
5237 11:45:35.349737 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5238 11:45:35.356348 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5239 11:45:35.356459 ==
5240 11:45:35.359363 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 11:45:35.362551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 11:45:35.362659 ==
5243 11:45:35.362752
5244 11:45:35.362846
5245 11:45:35.366381 TX Vref Scan disable
5246 11:45:35.369448 == TX Byte 0 ==
5247 11:45:35.372682 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5248 11:45:35.375825 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5249 11:45:35.379710 == TX Byte 1 ==
5250 11:45:35.383020 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5251 11:45:35.386260 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5252 11:45:35.386338
5253 11:45:35.389499 [DATLAT]
5254 11:45:35.389573 Freq=933, CH0 RK0
5255 11:45:35.389636
5256 11:45:35.392609 DATLAT Default: 0xd
5257 11:45:35.392710 0, 0xFFFF, sum = 0
5258 11:45:35.395868 1, 0xFFFF, sum = 0
5259 11:45:35.395953 2, 0xFFFF, sum = 0
5260 11:45:35.399055 3, 0xFFFF, sum = 0
5261 11:45:35.399135 4, 0xFFFF, sum = 0
5262 11:45:35.402380 5, 0xFFFF, sum = 0
5263 11:45:35.402460 6, 0xFFFF, sum = 0
5264 11:45:35.406395 7, 0xFFFF, sum = 0
5265 11:45:35.406502 8, 0xFFFF, sum = 0
5266 11:45:35.409335 9, 0xFFFF, sum = 0
5267 11:45:35.409419 10, 0x0, sum = 1
5268 11:45:35.412642 11, 0x0, sum = 2
5269 11:45:35.412718 12, 0x0, sum = 3
5270 11:45:35.415745 13, 0x0, sum = 4
5271 11:45:35.415854 best_step = 11
5272 11:45:35.415949
5273 11:45:35.416038 ==
5274 11:45:35.419112 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 11:45:35.425989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 11:45:35.426074 ==
5277 11:45:35.426142 RX Vref Scan: 1
5278 11:45:35.426230
5279 11:45:35.429379 RX Vref 0 -> 0, step: 1
5280 11:45:35.429478
5281 11:45:35.432555 RX Delay -69 -> 252, step: 4
5282 11:45:35.432626
5283 11:45:35.435717 Set Vref, RX VrefLevel [Byte0]: 60
5284 11:45:35.438683 [Byte1]: 47
5285 11:45:35.438791
5286 11:45:35.442649 Final RX Vref Byte 0 = 60 to rank0
5287 11:45:35.445498 Final RX Vref Byte 1 = 47 to rank0
5288 11:45:35.448658 Final RX Vref Byte 0 = 60 to rank1
5289 11:45:35.452316 Final RX Vref Byte 1 = 47 to rank1==
5290 11:45:35.455487 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 11:45:35.458536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 11:45:35.458639 ==
5293 11:45:35.462054 DQS Delay:
5294 11:45:35.462155 DQS0 = 0, DQS1 = 0
5295 11:45:35.465190 DQM Delay:
5296 11:45:35.465291 DQM0 = 95, DQM1 = 83
5297 11:45:35.465399 DQ Delay:
5298 11:45:35.468922 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =92
5299 11:45:35.471810 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5300 11:45:35.484234 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5301 11:45:35.484355 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5302 11:45:35.484420
5303 11:45:35.484479
5304 11:45:35.488177 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5305 11:45:35.491630 CH0 RK0: MR19=505, MR18=1010
5306 11:45:35.498615 CH0_RK0: MR19=0x505, MR18=0x1010, DQSOSC=416, MR23=63, INC=62, DEC=41
5307 11:45:35.498736
5308 11:45:35.501817 ----->DramcWriteLeveling(PI) begin...
5309 11:45:35.501942 ==
5310 11:45:35.504921 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 11:45:35.508395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 11:45:35.508476 ==
5313 11:45:35.511433 Write leveling (Byte 0): 30 => 30
5314 11:45:35.514637 Write leveling (Byte 1): 29 => 29
5315 11:45:35.517946 DramcWriteLeveling(PI) end<-----
5316 11:45:35.518050
5317 11:45:35.518141 ==
5318 11:45:35.521197 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 11:45:35.524959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 11:45:35.525072 ==
5321 11:45:35.527692 [Gating] SW mode calibration
5322 11:45:35.534748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5323 11:45:35.541196 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5324 11:45:35.544550 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5325 11:45:35.547834 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 11:45:35.554151 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 11:45:35.557386 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 11:45:35.560930 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 11:45:35.567796 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 11:45:35.570737 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5331 11:45:35.574013 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (1 1)
5332 11:45:35.581041 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5333 11:45:35.584038 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 11:45:35.587060 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 11:45:35.593462 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 11:45:35.596722 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 11:45:35.603540 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 11:45:35.606762 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 11:45:35.610016 0 15 28 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5340 11:45:35.616367 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5341 11:45:35.619688 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 11:45:35.622952 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 11:45:35.629904 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 11:45:35.633023 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 11:45:35.636344 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 11:45:35.642637 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 11:45:35.645842 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5348 11:45:35.649167 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5349 11:45:35.656167 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 11:45:35.659051 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 11:45:35.662718 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 11:45:35.669563 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 11:45:35.672693 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 11:45:35.675663 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 11:45:35.682443 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:45:35.685647 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 11:45:35.688767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 11:45:35.695550 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 11:45:35.698898 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 11:45:35.702032 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 11:45:35.708938 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 11:45:35.712155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 11:45:35.715505 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 11:45:35.722440 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 11:45:35.722526 Total UI for P1: 0, mck2ui 16
5366 11:45:35.728381 best dqsien dly found for B0: ( 1, 2, 30)
5367 11:45:35.728469 Total UI for P1: 0, mck2ui 16
5368 11:45:35.735265 best dqsien dly found for B1: ( 1, 2, 30)
5369 11:45:35.738546 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5370 11:45:35.741745 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5371 11:45:35.741833
5372 11:45:35.745077 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5373 11:45:35.748287 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5374 11:45:35.751403 [Gating] SW calibration Done
5375 11:45:35.751488 ==
5376 11:45:35.754696 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 11:45:35.757839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 11:45:35.757951 ==
5379 11:45:35.761202 RX Vref Scan: 0
5380 11:45:35.761305
5381 11:45:35.761406 RX Vref 0 -> 0, step: 1
5382 11:45:35.761504
5383 11:45:35.764598 RX Delay -80 -> 252, step: 8
5384 11:45:35.771201 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5385 11:45:35.774271 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5386 11:45:35.777989 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5387 11:45:35.781086 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5388 11:45:35.784130 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5389 11:45:35.787667 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5390 11:45:35.794499 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5391 11:45:35.797272 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5392 11:45:35.800885 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5393 11:45:35.804118 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5394 11:45:35.807371 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5395 11:45:35.813876 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5396 11:45:35.817083 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5397 11:45:35.820431 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5398 11:45:35.823460 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5399 11:45:35.827228 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5400 11:45:35.830444 ==
5401 11:45:35.833595 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 11:45:35.837055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 11:45:35.837161 ==
5404 11:45:35.837246 DQS Delay:
5405 11:45:35.840175 DQS0 = 0, DQS1 = 0
5406 11:45:35.840287 DQM Delay:
5407 11:45:35.843633 DQM0 = 93, DQM1 = 82
5408 11:45:35.843727 DQ Delay:
5409 11:45:35.846784 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5410 11:45:35.849999 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5411 11:45:35.853681 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =75
5412 11:45:35.856905 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5413 11:45:35.857031
5414 11:45:35.857132
5415 11:45:35.857221 ==
5416 11:45:35.859976 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 11:45:35.863391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 11:45:35.863472 ==
5419 11:45:35.863535
5420 11:45:35.866711
5421 11:45:35.866846 TX Vref Scan disable
5422 11:45:35.869937 == TX Byte 0 ==
5423 11:45:35.873451 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5424 11:45:35.876541 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5425 11:45:35.879651 == TX Byte 1 ==
5426 11:45:35.882685 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5427 11:45:35.886201 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5428 11:45:35.889971 ==
5429 11:45:35.890077 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 11:45:35.896508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 11:45:35.896592 ==
5432 11:45:35.896655
5433 11:45:35.896714
5434 11:45:35.899603 TX Vref Scan disable
5435 11:45:35.899684 == TX Byte 0 ==
5436 11:45:35.905780 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5437 11:45:35.909433 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5438 11:45:35.909515 == TX Byte 1 ==
5439 11:45:35.916053 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5440 11:45:35.919452 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5441 11:45:35.919537
5442 11:45:35.919602 [DATLAT]
5443 11:45:35.922694 Freq=933, CH0 RK1
5444 11:45:35.922802
5445 11:45:35.922885 DATLAT Default: 0xb
5446 11:45:35.925899 0, 0xFFFF, sum = 0
5447 11:45:35.925982 1, 0xFFFF, sum = 0
5448 11:45:35.929206 2, 0xFFFF, sum = 0
5449 11:45:35.929312 3, 0xFFFF, sum = 0
5450 11:45:35.932245 4, 0xFFFF, sum = 0
5451 11:45:35.932357 5, 0xFFFF, sum = 0
5452 11:45:35.935564 6, 0xFFFF, sum = 0
5453 11:45:35.938735 7, 0xFFFF, sum = 0
5454 11:45:35.938856 8, 0xFFFF, sum = 0
5455 11:45:35.941993 9, 0xFFFF, sum = 0
5456 11:45:35.942113 10, 0x0, sum = 1
5457 11:45:35.945243 11, 0x0, sum = 2
5458 11:45:35.945349 12, 0x0, sum = 3
5459 11:45:35.945451 13, 0x0, sum = 4
5460 11:45:35.948478 best_step = 11
5461 11:45:35.948564
5462 11:45:35.948626 ==
5463 11:45:35.952238 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 11:45:35.955553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 11:45:35.955643 ==
5466 11:45:35.958543 RX Vref Scan: 0
5467 11:45:35.958620
5468 11:45:35.961657 RX Vref 0 -> 0, step: 1
5469 11:45:35.961739
5470 11:45:35.961807 RX Delay -77 -> 252, step: 4
5471 11:45:35.969578 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5472 11:45:35.972911 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5473 11:45:35.976178 iDelay=199, Bit 2, Center 86 (-9 ~ 182) 192
5474 11:45:35.979493 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5475 11:45:35.982466 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5476 11:45:35.989728 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5477 11:45:35.992542 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5478 11:45:35.995526 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5479 11:45:35.999481 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5480 11:45:36.002731 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5481 11:45:36.009062 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5482 11:45:36.012272 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5483 11:45:36.015858 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5484 11:45:36.018845 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5485 11:45:36.022026 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5486 11:45:36.028628 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5487 11:45:36.028707 ==
5488 11:45:36.032136 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 11:45:36.035553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 11:45:36.035629 ==
5491 11:45:36.035691 DQS Delay:
5492 11:45:36.038750 DQS0 = 0, DQS1 = 0
5493 11:45:36.038854 DQM Delay:
5494 11:45:36.042096 DQM0 = 91, DQM1 = 84
5495 11:45:36.042194 DQ Delay:
5496 11:45:36.045361 DQ0 =90, DQ1 =94, DQ2 =86, DQ3 =86
5497 11:45:36.048779 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =102
5498 11:45:36.052146 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =78
5499 11:45:36.055298 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5500 11:45:36.055372
5501 11:45:36.055434
5502 11:45:36.064934 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5503 11:45:36.065014 CH0 RK1: MR19=505, MR18=2E0F
5504 11:45:36.072066 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5505 11:45:36.075305 [RxdqsGatingPostProcess] freq 933
5506 11:45:36.081923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5507 11:45:36.084550 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 11:45:36.088102 best DQS1 dly(2T, 0.5T) = (0, 11)
5509 11:45:36.091772 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 11:45:36.094697 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5511 11:45:36.098371 best DQS0 dly(2T, 0.5T) = (0, 10)
5512 11:45:36.098448 best DQS1 dly(2T, 0.5T) = (0, 10)
5513 11:45:36.101426 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5514 11:45:36.104435 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5515 11:45:36.108012 Pre-setting of DQS Precalculation
5516 11:45:36.114392 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5517 11:45:36.114497 ==
5518 11:45:36.118036 Dram Type= 6, Freq= 0, CH_1, rank 0
5519 11:45:36.121224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 11:45:36.121333 ==
5521 11:45:36.127677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5522 11:45:36.134606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5523 11:45:36.137713 [CA 0] Center 37 (7~67) winsize 61
5524 11:45:36.141317 [CA 1] Center 37 (7~67) winsize 61
5525 11:45:36.144192 [CA 2] Center 34 (5~64) winsize 60
5526 11:45:36.147640 [CA 3] Center 34 (5~64) winsize 60
5527 11:45:36.150928 [CA 4] Center 35 (5~65) winsize 61
5528 11:45:36.154056 [CA 5] Center 34 (4~64) winsize 61
5529 11:45:36.154129
5530 11:45:36.157416 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5531 11:45:36.157518
5532 11:45:36.160658 [CATrainingPosCal] consider 1 rank data
5533 11:45:36.163925 u2DelayCellTimex100 = 270/100 ps
5534 11:45:36.166993 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5535 11:45:36.170890 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5536 11:45:36.174083 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5537 11:45:36.177509 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5538 11:45:36.180618 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5539 11:45:36.183986 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5540 11:45:36.187461
5541 11:45:36.190722 CA PerBit enable=1, Macro0, CA PI delay=34
5542 11:45:36.190843
5543 11:45:36.194111 [CBTSetCACLKResult] CA Dly = 34
5544 11:45:36.194222 CS Dly: 6 (0~37)
5545 11:45:36.194285 ==
5546 11:45:36.197047 Dram Type= 6, Freq= 0, CH_1, rank 1
5547 11:45:36.200228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 11:45:36.200311 ==
5549 11:45:36.207073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5550 11:45:36.213798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5551 11:45:36.216761 [CA 0] Center 37 (8~67) winsize 60
5552 11:45:36.219883 [CA 1] Center 37 (7~68) winsize 62
5553 11:45:36.223703 [CA 2] Center 35 (5~65) winsize 61
5554 11:45:36.226781 [CA 3] Center 34 (4~64) winsize 61
5555 11:45:36.229873 [CA 4] Center 34 (4~65) winsize 62
5556 11:45:36.233464 [CA 5] Center 34 (4~64) winsize 61
5557 11:45:36.233586
5558 11:45:36.236587 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5559 11:45:36.236674
5560 11:45:36.239712 [CATrainingPosCal] consider 2 rank data
5561 11:45:36.243525 u2DelayCellTimex100 = 270/100 ps
5562 11:45:36.246801 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5563 11:45:36.249922 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5564 11:45:36.253083 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5565 11:45:36.256288 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5566 11:45:36.263180 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5567 11:45:36.266512 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5568 11:45:36.266614
5569 11:45:36.269731 CA PerBit enable=1, Macro0, CA PI delay=34
5570 11:45:36.269841
5571 11:45:36.272724 [CBTSetCACLKResult] CA Dly = 34
5572 11:45:36.272828 CS Dly: 7 (0~39)
5573 11:45:36.272927
5574 11:45:36.275956 ----->DramcWriteLeveling(PI) begin...
5575 11:45:36.276061 ==
5576 11:45:36.279796 Dram Type= 6, Freq= 0, CH_1, rank 0
5577 11:45:36.286189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 11:45:36.286299 ==
5579 11:45:36.289436 Write leveling (Byte 0): 26 => 26
5580 11:45:36.293173 Write leveling (Byte 1): 28 => 28
5581 11:45:36.295738 DramcWriteLeveling(PI) end<-----
5582 11:45:36.295845
5583 11:45:36.295941 ==
5584 11:45:36.298924 Dram Type= 6, Freq= 0, CH_1, rank 0
5585 11:45:36.302696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 11:45:36.302807 ==
5587 11:45:36.305716 [Gating] SW mode calibration
5588 11:45:36.312648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5589 11:45:36.319017 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5590 11:45:36.322550 0 14 0 | B1->B0 | 3131 3232 | 0 1 | (0 0) (1 1)
5591 11:45:36.325768 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 11:45:36.332131 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 11:45:36.335809 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 11:45:36.338834 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 11:45:36.345369 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 11:45:36.348505 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 11:45:36.352348 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (0 1)
5598 11:45:36.355636 0 15 0 | B1->B0 | 2525 2727 | 0 0 | (1 0) (1 0)
5599 11:45:36.362191 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 11:45:36.365469 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 11:45:36.368718 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 11:45:36.375061 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 11:45:36.378186 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 11:45:36.385239 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 11:45:36.388641 0 15 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5606 11:45:36.391736 1 0 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (1 1)
5607 11:45:36.398212 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 11:45:36.401555 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 11:45:36.404816 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 11:45:36.411341 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 11:45:36.414461 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 11:45:36.417761 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 11:45:36.424149 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5614 11:45:36.427909 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 11:45:36.431016 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 11:45:36.437274 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 11:45:36.440965 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 11:45:36.444115 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 11:45:36.451014 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 11:45:36.453771 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 11:45:36.457494 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:45:36.463806 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:45:36.467034 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 11:45:36.470295 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 11:45:36.477170 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 11:45:36.480396 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 11:45:36.483694 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 11:45:36.490209 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 11:45:36.493653 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5630 11:45:36.496772 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 11:45:36.503283 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 11:45:36.503365 Total UI for P1: 0, mck2ui 16
5633 11:45:36.509622 best dqsien dly found for B0: ( 1, 2, 30)
5634 11:45:36.509730 Total UI for P1: 0, mck2ui 16
5635 11:45:36.516531 best dqsien dly found for B1: ( 1, 2, 30)
5636 11:45:36.519754 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5637 11:45:36.523062 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5638 11:45:36.523142
5639 11:45:36.526056 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5640 11:45:36.529946 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5641 11:45:36.533056 [Gating] SW calibration Done
5642 11:45:36.533136 ==
5643 11:45:36.536094 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 11:45:36.539356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 11:45:36.539437 ==
5646 11:45:36.543101 RX Vref Scan: 0
5647 11:45:36.543181
5648 11:45:36.543244 RX Vref 0 -> 0, step: 1
5649 11:45:36.543302
5650 11:45:36.546358 RX Delay -80 -> 252, step: 8
5651 11:45:36.549457 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5652 11:45:36.556166 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5653 11:45:36.559218 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5654 11:45:36.562698 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5655 11:45:36.565748 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5656 11:45:36.569636 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5657 11:45:36.576188 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5658 11:45:36.579524 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5659 11:45:36.582627 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5660 11:45:36.585736 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5661 11:45:36.589000 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5662 11:45:36.595612 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5663 11:45:36.598922 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5664 11:45:36.602050 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5665 11:45:36.605797 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5666 11:45:36.609037 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5667 11:45:36.609140 ==
5668 11:45:36.612323 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 11:45:36.618435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 11:45:36.618542 ==
5671 11:45:36.618637 DQS Delay:
5672 11:45:36.622312 DQS0 = 0, DQS1 = 0
5673 11:45:36.622422 DQM Delay:
5674 11:45:36.625507 DQM0 = 94, DQM1 = 85
5675 11:45:36.625611 DQ Delay:
5676 11:45:36.628682 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5677 11:45:36.632216 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5678 11:45:36.635133 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =83
5679 11:45:36.638709 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5680 11:45:36.638836
5681 11:45:36.638937
5682 11:45:36.639037 ==
5683 11:45:36.641859 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 11:45:36.645157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 11:45:36.645267 ==
5686 11:45:36.645375
5687 11:45:36.645479
5688 11:45:36.648369 TX Vref Scan disable
5689 11:45:36.651623 == TX Byte 0 ==
5690 11:45:36.654856 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5691 11:45:36.658186 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5692 11:45:36.661222 == TX Byte 1 ==
5693 11:45:36.665020 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5694 11:45:36.668426 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5695 11:45:36.668551 ==
5696 11:45:36.671451 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:45:36.678252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:45:36.678460 ==
5699 11:45:36.678646
5700 11:45:36.678871
5701 11:45:36.679072 TX Vref Scan disable
5702 11:45:36.682198 == TX Byte 0 ==
5703 11:45:36.685471 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5704 11:45:36.692318 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5705 11:45:36.692674 == TX Byte 1 ==
5706 11:45:36.695583 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5707 11:45:36.702242 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5708 11:45:36.702884
5709 11:45:36.703432 [DATLAT]
5710 11:45:36.703954 Freq=933, CH1 RK0
5711 11:45:36.704450
5712 11:45:36.705468 DATLAT Default: 0xd
5713 11:45:36.705888 0, 0xFFFF, sum = 0
5714 11:45:36.708619 1, 0xFFFF, sum = 0
5715 11:45:36.711883 2, 0xFFFF, sum = 0
5716 11:45:36.712310 3, 0xFFFF, sum = 0
5717 11:45:36.715009 4, 0xFFFF, sum = 0
5718 11:45:36.715524 5, 0xFFFF, sum = 0
5719 11:45:36.718883 6, 0xFFFF, sum = 0
5720 11:45:36.719376 7, 0xFFFF, sum = 0
5721 11:45:36.721824 8, 0xFFFF, sum = 0
5722 11:45:36.722375 9, 0xFFFF, sum = 0
5723 11:45:36.725229 10, 0x0, sum = 1
5724 11:45:36.725853 11, 0x0, sum = 2
5725 11:45:36.728431 12, 0x0, sum = 3
5726 11:45:36.728962 13, 0x0, sum = 4
5727 11:45:36.729503 best_step = 11
5728 11:45:36.731837
5729 11:45:36.732314 ==
5730 11:45:36.735378 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 11:45:36.738645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 11:45:36.739244 ==
5733 11:45:36.739833 RX Vref Scan: 1
5734 11:45:36.740331
5735 11:45:36.741581 RX Vref 0 -> 0, step: 1
5736 11:45:36.742039
5737 11:45:36.745121 RX Delay -69 -> 252, step: 4
5738 11:45:36.745591
5739 11:45:36.748330 Set Vref, RX VrefLevel [Byte0]: 54
5740 11:45:36.751219 [Byte1]: 48
5741 11:45:36.755160
5742 11:45:36.755582 Final RX Vref Byte 0 = 54 to rank0
5743 11:45:36.758302 Final RX Vref Byte 1 = 48 to rank0
5744 11:45:36.761481 Final RX Vref Byte 0 = 54 to rank1
5745 11:45:36.764605 Final RX Vref Byte 1 = 48 to rank1==
5746 11:45:36.768229 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 11:45:36.774896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 11:45:36.775322 ==
5749 11:45:36.775655 DQS Delay:
5750 11:45:36.778130 DQS0 = 0, DQS1 = 0
5751 11:45:36.778547 DQM Delay:
5752 11:45:36.779110 DQM0 = 95, DQM1 = 88
5753 11:45:36.781205 DQ Delay:
5754 11:45:36.784133 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =94
5755 11:45:36.787391 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5756 11:45:36.791121 DQ8 =76, DQ9 =80, DQ10 =86, DQ11 =82
5757 11:45:36.794337 DQ12 =100, DQ13 =92, DQ14 =96, DQ15 =94
5758 11:45:36.794913
5759 11:45:36.795468
5760 11:45:36.800928 [DQSOSCAuto] RK0, (LSB)MR18= 0x9, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5761 11:45:36.804049 CH1 RK0: MR19=505, MR18=9
5762 11:45:36.810785 CH1_RK0: MR19=0x505, MR18=0x9, DQSOSC=419, MR23=63, INC=61, DEC=41
5763 11:45:36.811243
5764 11:45:36.813826 ----->DramcWriteLeveling(PI) begin...
5765 11:45:36.814347 ==
5766 11:45:36.817005 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 11:45:36.820894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 11:45:36.821510 ==
5769 11:45:36.823944 Write leveling (Byte 0): 26 => 26
5770 11:45:36.826956 Write leveling (Byte 1): 30 => 30
5771 11:45:36.830779 DramcWriteLeveling(PI) end<-----
5772 11:45:36.831430
5773 11:45:36.832003 ==
5774 11:45:36.833954 Dram Type= 6, Freq= 0, CH_1, rank 1
5775 11:45:36.837232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 11:45:36.837891 ==
5777 11:45:36.840294 [Gating] SW mode calibration
5778 11:45:36.846743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5779 11:45:36.853625 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5780 11:45:36.856683 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5781 11:45:36.863367 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 11:45:36.866576 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 11:45:36.869694 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 11:45:36.876664 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 11:45:36.879588 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5786 11:45:36.882982 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5787 11:45:36.889777 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (1 1)
5788 11:45:36.892933 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 11:45:36.896171 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 11:45:36.902462 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 11:45:36.905676 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 11:45:36.909470 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 11:45:36.915957 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 11:45:36.919407 0 15 24 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 0)
5795 11:45:36.922437 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5796 11:45:36.929411 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5797 11:45:36.932672 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 11:45:36.935866 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 11:45:36.942205 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 11:45:36.945601 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 11:45:36.948618 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 11:45:36.955673 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5803 11:45:36.958740 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5804 11:45:36.961894 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 11:45:36.968896 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 11:45:36.971868 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 11:45:36.975095 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 11:45:36.981757 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 11:45:36.984937 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 11:45:36.988618 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 11:45:36.994685 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 11:45:36.998559 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 11:45:37.001843 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 11:45:37.008237 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 11:45:37.011682 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 11:45:37.014814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 11:45:37.021318 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 11:45:37.024643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5819 11:45:37.027930 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5820 11:45:37.031195 Total UI for P1: 0, mck2ui 16
5821 11:45:37.034821 best dqsien dly found for B0: ( 1, 2, 24)
5822 11:45:37.041322 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 11:45:37.041740 Total UI for P1: 0, mck2ui 16
5824 11:45:37.047567 best dqsien dly found for B1: ( 1, 2, 26)
5825 11:45:37.050895 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5826 11:45:37.054747 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5827 11:45:37.055401
5828 11:45:37.057936 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5829 11:45:37.061494 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5830 11:45:37.064664 [Gating] SW calibration Done
5831 11:45:37.065188 ==
5832 11:45:37.067467 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 11:45:37.071092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 11:45:37.071505 ==
5835 11:45:37.074269 RX Vref Scan: 0
5836 11:45:37.074721
5837 11:45:37.075201 RX Vref 0 -> 0, step: 1
5838 11:45:37.077206
5839 11:45:37.077571 RX Delay -80 -> 252, step: 8
5840 11:45:37.084003 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5841 11:45:37.087724 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5842 11:45:37.090789 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5843 11:45:37.093825 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5844 11:45:37.097521 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5845 11:45:37.100705 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5846 11:45:37.107125 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5847 11:45:37.110109 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5848 11:45:37.113351 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5849 11:45:37.116718 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5850 11:45:37.120422 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5851 11:45:37.127051 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5852 11:45:37.130199 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5853 11:45:37.133514 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5854 11:45:37.136466 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5855 11:45:37.140172 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5856 11:45:37.143464 ==
5857 11:45:37.146581 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 11:45:37.149862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 11:45:37.149966 ==
5860 11:45:37.150067 DQS Delay:
5861 11:45:37.152674 DQS0 = 0, DQS1 = 0
5862 11:45:37.152779 DQM Delay:
5863 11:45:37.156066 DQM0 = 92, DQM1 = 87
5864 11:45:37.156149 DQ Delay:
5865 11:45:37.159389 DQ0 =95, DQ1 =91, DQ2 =79, DQ3 =91
5866 11:45:37.163150 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =91
5867 11:45:37.166235 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5868 11:45:37.169437 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5869 11:45:37.169546
5870 11:45:37.169639
5871 11:45:37.169728 ==
5872 11:45:37.172545 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 11:45:37.175982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 11:45:37.176066 ==
5875 11:45:37.176131
5876 11:45:37.176191
5877 11:45:37.179416 TX Vref Scan disable
5878 11:45:37.182545 == TX Byte 0 ==
5879 11:45:37.185668 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5880 11:45:37.188899 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5881 11:45:37.192132 == TX Byte 1 ==
5882 11:45:37.195900 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5883 11:45:37.199012 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5884 11:45:37.199117 ==
5885 11:45:37.202005 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 11:45:37.208753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 11:45:37.208860 ==
5888 11:45:37.208953
5889 11:45:37.209050
5890 11:45:37.209137 TX Vref Scan disable
5891 11:45:37.212996 == TX Byte 0 ==
5892 11:45:37.216644 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5893 11:45:37.223003 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5894 11:45:37.223089 == TX Byte 1 ==
5895 11:45:37.226017 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5896 11:45:37.232543 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5897 11:45:37.232627
5898 11:45:37.232691 [DATLAT]
5899 11:45:37.232752 Freq=933, CH1 RK1
5900 11:45:37.232810
5901 11:45:37.236385 DATLAT Default: 0xb
5902 11:45:37.239529 0, 0xFFFF, sum = 0
5903 11:45:37.239613 1, 0xFFFF, sum = 0
5904 11:45:37.242769 2, 0xFFFF, sum = 0
5905 11:45:37.242861 3, 0xFFFF, sum = 0
5906 11:45:37.245998 4, 0xFFFF, sum = 0
5907 11:45:37.246081 5, 0xFFFF, sum = 0
5908 11:45:37.249239 6, 0xFFFF, sum = 0
5909 11:45:37.249322 7, 0xFFFF, sum = 0
5910 11:45:37.252546 8, 0xFFFF, sum = 0
5911 11:45:37.252648 9, 0xFFFF, sum = 0
5912 11:45:37.255853 10, 0x0, sum = 1
5913 11:45:37.255926 11, 0x0, sum = 2
5914 11:45:37.259034 12, 0x0, sum = 3
5915 11:45:37.259135 13, 0x0, sum = 4
5916 11:45:37.262224 best_step = 11
5917 11:45:37.262299
5918 11:45:37.262360 ==
5919 11:45:37.265354 Dram Type= 6, Freq= 0, CH_1, rank 1
5920 11:45:37.269202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5921 11:45:37.269314 ==
5922 11:45:37.269409 RX Vref Scan: 0
5923 11:45:37.272507
5924 11:45:37.272588 RX Vref 0 -> 0, step: 1
5925 11:45:37.272654
5926 11:45:37.275797 RX Delay -69 -> 252, step: 4
5927 11:45:37.282515 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5928 11:45:37.285769 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5929 11:45:37.288916 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5930 11:45:37.291904 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5931 11:45:37.295820 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5932 11:45:37.302013 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5933 11:45:37.305103 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5934 11:45:37.308356 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5935 11:45:37.312293 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5936 11:45:37.315206 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5937 11:45:37.321974 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5938 11:45:37.325030 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5939 11:45:37.328120 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5940 11:45:37.331872 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5941 11:45:37.335090 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5942 11:45:37.341613 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5943 11:45:37.341716 ==
5944 11:45:37.344926 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 11:45:37.348029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 11:45:37.348141 ==
5947 11:45:37.348235 DQS Delay:
5948 11:45:37.351120 DQS0 = 0, DQS1 = 0
5949 11:45:37.351194 DQM Delay:
5950 11:45:37.354409 DQM0 = 91, DQM1 = 91
5951 11:45:37.354482 DQ Delay:
5952 11:45:37.357734 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5953 11:45:37.361521 DQ4 =90, DQ5 =100, DQ6 =102, DQ7 =88
5954 11:45:37.364743 DQ8 =78, DQ9 =82, DQ10 =92, DQ11 =82
5955 11:45:37.368121 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =96
5956 11:45:37.368196
5957 11:45:37.368259
5958 11:45:37.377879 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5959 11:45:37.377963 CH1 RK1: MR19=505, MR18=B1E
5960 11:45:37.384108 CH1_RK1: MR19=0x505, MR18=0xB1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5961 11:45:37.387347 [RxdqsGatingPostProcess] freq 933
5962 11:45:37.393820 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5963 11:45:37.397509 best DQS0 dly(2T, 0.5T) = (0, 10)
5964 11:45:37.400584 best DQS1 dly(2T, 0.5T) = (0, 10)
5965 11:45:37.404339 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5966 11:45:37.407473 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5967 11:45:37.410888 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 11:45:37.413915 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 11:45:37.417289 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 11:45:37.420384 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 11:45:37.420466 Pre-setting of DQS Precalculation
5972 11:45:37.427183 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5973 11:45:37.433511 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5974 11:45:37.440067 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5975 11:45:37.440162
5976 11:45:37.440227
5977 11:45:37.443250 [Calibration Summary] 1866 Mbps
5978 11:45:37.446510 CH 0, Rank 0
5979 11:45:37.446606 SW Impedance : PASS
5980 11:45:37.450254 DUTY Scan : NO K
5981 11:45:37.453346 ZQ Calibration : PASS
5982 11:45:37.453440 Jitter Meter : NO K
5983 11:45:37.456589 CBT Training : PASS
5984 11:45:37.459752 Write leveling : PASS
5985 11:45:37.459858 RX DQS gating : PASS
5986 11:45:37.463035 RX DQ/DQS(RDDQC) : PASS
5987 11:45:37.466744 TX DQ/DQS : PASS
5988 11:45:37.466889 RX DATLAT : PASS
5989 11:45:37.470002 RX DQ/DQS(Engine): PASS
5990 11:45:37.473272 TX OE : NO K
5991 11:45:37.473353 All Pass.
5992 11:45:37.473415
5993 11:45:37.473473 CH 0, Rank 1
5994 11:45:37.476494 SW Impedance : PASS
5995 11:45:37.479773 DUTY Scan : NO K
5996 11:45:37.479853 ZQ Calibration : PASS
5997 11:45:37.482740 Jitter Meter : NO K
5998 11:45:37.486053 CBT Training : PASS
5999 11:45:37.486134 Write leveling : PASS
6000 11:45:37.489519 RX DQS gating : PASS
6001 11:45:37.492613 RX DQ/DQS(RDDQC) : PASS
6002 11:45:37.492693 TX DQ/DQS : PASS
6003 11:45:37.495959 RX DATLAT : PASS
6004 11:45:37.496039 RX DQ/DQS(Engine): PASS
6005 11:45:37.499625 TX OE : NO K
6006 11:45:37.499708 All Pass.
6007 11:45:37.499771
6008 11:45:37.502700 CH 1, Rank 0
6009 11:45:37.502782 SW Impedance : PASS
6010 11:45:37.505999 DUTY Scan : NO K
6011 11:45:37.508938 ZQ Calibration : PASS
6012 11:45:37.509018 Jitter Meter : NO K
6013 11:45:37.512812 CBT Training : PASS
6014 11:45:37.515765 Write leveling : PASS
6015 11:45:37.515845 RX DQS gating : PASS
6016 11:45:37.519316 RX DQ/DQS(RDDQC) : PASS
6017 11:45:37.522139 TX DQ/DQS : PASS
6018 11:45:37.522249 RX DATLAT : PASS
6019 11:45:37.525419 RX DQ/DQS(Engine): PASS
6020 11:45:37.529075 TX OE : NO K
6021 11:45:37.529171 All Pass.
6022 11:45:37.529235
6023 11:45:37.529294 CH 1, Rank 1
6024 11:45:37.532179 SW Impedance : PASS
6025 11:45:37.535367 DUTY Scan : NO K
6026 11:45:37.535470 ZQ Calibration : PASS
6027 11:45:37.539011 Jitter Meter : NO K
6028 11:45:37.541980 CBT Training : PASS
6029 11:45:37.542086 Write leveling : PASS
6030 11:45:37.545545 RX DQS gating : PASS
6031 11:45:37.548889 RX DQ/DQS(RDDQC) : PASS
6032 11:45:37.548970 TX DQ/DQS : PASS
6033 11:45:37.551513 RX DATLAT : PASS
6034 11:45:37.555288 RX DQ/DQS(Engine): PASS
6035 11:45:37.555385 TX OE : NO K
6036 11:45:37.558291 All Pass.
6037 11:45:37.558395
6038 11:45:37.558496 DramC Write-DBI off
6039 11:45:37.561607 PER_BANK_REFRESH: Hybrid Mode
6040 11:45:37.561721 TX_TRACKING: ON
6041 11:45:37.571522 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6042 11:45:37.574714 [FAST_K] Save calibration result to emmc
6043 11:45:37.577919 dramc_set_vcore_voltage set vcore to 650000
6044 11:45:37.581196 Read voltage for 400, 6
6045 11:45:37.581270 Vio18 = 0
6046 11:45:37.584490 Vcore = 650000
6047 11:45:37.584594 Vdram = 0
6048 11:45:37.584684 Vddq = 0
6049 11:45:37.587628 Vmddr = 0
6050 11:45:37.591531 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6051 11:45:37.597804 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6052 11:45:37.597910 MEM_TYPE=3, freq_sel=20
6053 11:45:37.600942 sv_algorithm_assistance_LP4_800
6054 11:45:37.607324 ============ PULL DRAM RESETB DOWN ============
6055 11:45:37.610618 ========== PULL DRAM RESETB DOWN end =========
6056 11:45:37.614565 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6057 11:45:37.617616 ===================================
6058 11:45:37.620362 LPDDR4 DRAM CONFIGURATION
6059 11:45:37.624091 ===================================
6060 11:45:37.627022 EX_ROW_EN[0] = 0x0
6061 11:45:37.627129 EX_ROW_EN[1] = 0x0
6062 11:45:37.630740 LP4Y_EN = 0x0
6063 11:45:37.630855 WORK_FSP = 0x0
6064 11:45:37.633972 WL = 0x2
6065 11:45:37.634078 RL = 0x2
6066 11:45:37.637187 BL = 0x2
6067 11:45:37.637268 RPST = 0x0
6068 11:45:37.640221 RD_PRE = 0x0
6069 11:45:37.640304 WR_PRE = 0x1
6070 11:45:37.643410 WR_PST = 0x0
6071 11:45:37.647047 DBI_WR = 0x0
6072 11:45:37.647154 DBI_RD = 0x0
6073 11:45:37.650316 OTF = 0x1
6074 11:45:37.653515 ===================================
6075 11:45:37.656638 ===================================
6076 11:45:37.656719 ANA top config
6077 11:45:37.660082 ===================================
6078 11:45:37.663377 DLL_ASYNC_EN = 0
6079 11:45:37.666571 ALL_SLAVE_EN = 1
6080 11:45:37.666708 NEW_RANK_MODE = 1
6081 11:45:37.669914 DLL_IDLE_MODE = 1
6082 11:45:37.673188 LP45_APHY_COMB_EN = 1
6083 11:45:37.676260 TX_ODT_DIS = 1
6084 11:45:37.679552 NEW_8X_MODE = 1
6085 11:45:37.683286 ===================================
6086 11:45:37.686495 ===================================
6087 11:45:37.686577 data_rate = 800
6088 11:45:37.689683 CKR = 1
6089 11:45:37.693019 DQ_P2S_RATIO = 4
6090 11:45:37.696041 ===================================
6091 11:45:37.699747 CA_P2S_RATIO = 4
6092 11:45:37.702798 DQ_CA_OPEN = 0
6093 11:45:37.706017 DQ_SEMI_OPEN = 1
6094 11:45:37.706124 CA_SEMI_OPEN = 1
6095 11:45:37.709245 CA_FULL_RATE = 0
6096 11:45:37.712394 DQ_CKDIV4_EN = 0
6097 11:45:37.716172 CA_CKDIV4_EN = 1
6098 11:45:37.719275 CA_PREDIV_EN = 0
6099 11:45:37.722412 PH8_DLY = 0
6100 11:45:37.722517 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6101 11:45:37.725628 DQ_AAMCK_DIV = 0
6102 11:45:37.729483 CA_AAMCK_DIV = 0
6103 11:45:37.732570 CA_ADMCK_DIV = 4
6104 11:45:37.735655 DQ_TRACK_CA_EN = 0
6105 11:45:37.739237 CA_PICK = 800
6106 11:45:37.742326 CA_MCKIO = 400
6107 11:45:37.742419 MCKIO_SEMI = 400
6108 11:45:37.745583 PLL_FREQ = 3016
6109 11:45:37.749332 DQ_UI_PI_RATIO = 32
6110 11:45:37.752648 CA_UI_PI_RATIO = 32
6111 11:45:37.755612 ===================================
6112 11:45:37.758651 ===================================
6113 11:45:37.762519 memory_type:LPDDR4
6114 11:45:37.762593 GP_NUM : 10
6115 11:45:37.765602 SRAM_EN : 1
6116 11:45:37.768587 MD32_EN : 0
6117 11:45:37.772485 ===================================
6118 11:45:37.772566 [ANA_INIT] >>>>>>>>>>>>>>
6119 11:45:37.775643 <<<<<< [CONFIGURE PHASE]: ANA_TX
6120 11:45:37.778703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6121 11:45:37.781931 ===================================
6122 11:45:37.785059 data_rate = 800,PCW = 0X7400
6123 11:45:37.788950 ===================================
6124 11:45:37.792158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6125 11:45:37.798539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6126 11:45:37.808685 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 11:45:37.815106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6128 11:45:37.818201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6129 11:45:37.821457 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6130 11:45:37.821541 [ANA_INIT] flow start
6131 11:45:37.825235 [ANA_INIT] PLL >>>>>>>>
6132 11:45:37.828516 [ANA_INIT] PLL <<<<<<<<
6133 11:45:37.828598 [ANA_INIT] MIDPI >>>>>>>>
6134 11:45:37.831679 [ANA_INIT] MIDPI <<<<<<<<
6135 11:45:37.834751 [ANA_INIT] DLL >>>>>>>>
6136 11:45:37.834861 [ANA_INIT] flow end
6137 11:45:37.841527 ============ LP4 DIFF to SE enter ============
6138 11:45:37.845080 ============ LP4 DIFF to SE exit ============
6139 11:45:37.848106 [ANA_INIT] <<<<<<<<<<<<<
6140 11:45:37.851169 [Flow] Enable top DCM control >>>>>
6141 11:45:37.854823 [Flow] Enable top DCM control <<<<<
6142 11:45:37.854914 Enable DLL master slave shuffle
6143 11:45:37.861312 ==============================================================
6144 11:45:37.864270 Gating Mode config
6145 11:45:37.867872 ==============================================================
6146 11:45:37.870881 Config description:
6147 11:45:37.881292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6148 11:45:37.887742 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6149 11:45:37.891007 SELPH_MODE 0: By rank 1: By Phase
6150 11:45:37.897426 ==============================================================
6151 11:45:37.900662 GAT_TRACK_EN = 0
6152 11:45:37.904269 RX_GATING_MODE = 2
6153 11:45:37.907525 RX_GATING_TRACK_MODE = 2
6154 11:45:37.910778 SELPH_MODE = 1
6155 11:45:37.914176 PICG_EARLY_EN = 1
6156 11:45:37.917401 VALID_LAT_VALUE = 1
6157 11:45:37.920542 ==============================================================
6158 11:45:37.923684 Enter into Gating configuration >>>>
6159 11:45:37.926878 Exit from Gating configuration <<<<
6160 11:45:37.930107 Enter into DVFS_PRE_config >>>>>
6161 11:45:37.943264 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6162 11:45:37.943351 Exit from DVFS_PRE_config <<<<<
6163 11:45:37.946630 Enter into PICG configuration >>>>
6164 11:45:37.949985 Exit from PICG configuration <<<<
6165 11:45:37.953092 [RX_INPUT] configuration >>>>>
6166 11:45:37.956220 [RX_INPUT] configuration <<<<<
6167 11:45:37.963180 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6168 11:45:37.966522 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6169 11:45:37.972994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 11:45:37.979650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 11:45:37.986058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6172 11:45:37.992924 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6173 11:45:37.996386 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6174 11:45:37.999440 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6175 11:45:38.005835 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6176 11:45:38.008911 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6177 11:45:38.012610 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6178 11:45:38.015855 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6179 11:45:38.019180 ===================================
6180 11:45:38.022544 LPDDR4 DRAM CONFIGURATION
6181 11:45:38.025607 ===================================
6182 11:45:38.028959 EX_ROW_EN[0] = 0x0
6183 11:45:38.029071 EX_ROW_EN[1] = 0x0
6184 11:45:38.032152 LP4Y_EN = 0x0
6185 11:45:38.032235 WORK_FSP = 0x0
6186 11:45:38.035263 WL = 0x2
6187 11:45:38.035345 RL = 0x2
6188 11:45:38.038672 BL = 0x2
6189 11:45:38.042377 RPST = 0x0
6190 11:45:38.042459 RD_PRE = 0x0
6191 11:45:38.045304 WR_PRE = 0x1
6192 11:45:38.045385 WR_PST = 0x0
6193 11:45:38.048697 DBI_WR = 0x0
6194 11:45:38.048780 DBI_RD = 0x0
6195 11:45:38.051924 OTF = 0x1
6196 11:45:38.055013 ===================================
6197 11:45:38.058921 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6198 11:45:38.061896 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6199 11:45:38.065098 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 11:45:38.068386 ===================================
6201 11:45:38.071591 LPDDR4 DRAM CONFIGURATION
6202 11:45:38.075177 ===================================
6203 11:45:38.078343 EX_ROW_EN[0] = 0x10
6204 11:45:38.078422 EX_ROW_EN[1] = 0x0
6205 11:45:38.081364 LP4Y_EN = 0x0
6206 11:45:38.081453 WORK_FSP = 0x0
6207 11:45:38.084936 WL = 0x2
6208 11:45:38.085047 RL = 0x2
6209 11:45:38.088171 BL = 0x2
6210 11:45:38.091522 RPST = 0x0
6211 11:45:38.091604 RD_PRE = 0x0
6212 11:45:38.094699 WR_PRE = 0x1
6213 11:45:38.094803 WR_PST = 0x0
6214 11:45:38.097909 DBI_WR = 0x0
6215 11:45:38.098007 DBI_RD = 0x0
6216 11:45:38.101160 OTF = 0x1
6217 11:45:38.104441 ===================================
6218 11:45:38.110812 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6219 11:45:38.114488 nWR fixed to 30
6220 11:45:38.114587 [ModeRegInit_LP4] CH0 RK0
6221 11:45:38.117838 [ModeRegInit_LP4] CH0 RK1
6222 11:45:38.121142 [ModeRegInit_LP4] CH1 RK0
6223 11:45:38.121223 [ModeRegInit_LP4] CH1 RK1
6224 11:45:38.124156 match AC timing 19
6225 11:45:38.127468 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6226 11:45:38.133965 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6227 11:45:38.137265 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6228 11:45:38.141157 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6229 11:45:38.147558 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6230 11:45:38.147693 ==
6231 11:45:38.150751 Dram Type= 6, Freq= 0, CH_0, rank 0
6232 11:45:38.153887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 11:45:38.153969 ==
6234 11:45:38.160459 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 11:45:38.167182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 11:45:38.170961 [CA 0] Center 36 (8~64) winsize 57
6237 11:45:38.171043 [CA 1] Center 36 (8~64) winsize 57
6238 11:45:38.173515 [CA 2] Center 36 (8~64) winsize 57
6239 11:45:38.177328 [CA 3] Center 36 (8~64) winsize 57
6240 11:45:38.180543 [CA 4] Center 36 (8~64) winsize 57
6241 11:45:38.183621 [CA 5] Center 36 (8~64) winsize 57
6242 11:45:38.183726
6243 11:45:38.186599 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 11:45:38.190344
6245 11:45:38.193260 [CATrainingPosCal] consider 1 rank data
6246 11:45:38.193370 u2DelayCellTimex100 = 270/100 ps
6247 11:45:38.200153 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:45:38.203416 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:45:38.206847 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:45:38.210006 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:45:38.213191 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:45:38.216488 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:45:38.216596
6254 11:45:38.219530 CA PerBit enable=1, Macro0, CA PI delay=36
6255 11:45:38.219637
6256 11:45:38.223526 [CBTSetCACLKResult] CA Dly = 36
6257 11:45:38.226764 CS Dly: 1 (0~32)
6258 11:45:38.226896 ==
6259 11:45:38.229438 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 11:45:38.232800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 11:45:38.232900 ==
6262 11:45:38.239956 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6263 11:45:38.245979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6264 11:45:38.246089 [CA 0] Center 36 (8~64) winsize 57
6265 11:45:38.249335 [CA 1] Center 36 (8~64) winsize 57
6266 11:45:38.252990 [CA 2] Center 36 (8~64) winsize 57
6267 11:45:38.256168 [CA 3] Center 36 (8~64) winsize 57
6268 11:45:38.259396 [CA 4] Center 36 (8~64) winsize 57
6269 11:45:38.262701 [CA 5] Center 36 (8~64) winsize 57
6270 11:45:38.262808
6271 11:45:38.265885 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6272 11:45:38.265984
6273 11:45:38.269554 [CATrainingPosCal] consider 2 rank data
6274 11:45:38.272671 u2DelayCellTimex100 = 270/100 ps
6275 11:45:38.275719 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 11:45:38.282944 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:45:38.285785 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 11:45:38.289219 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 11:45:38.292522 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:45:38.295435 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 11:45:38.295515
6282 11:45:38.298993 CA PerBit enable=1, Macro0, CA PI delay=36
6283 11:45:38.299074
6284 11:45:38.302055 [CBTSetCACLKResult] CA Dly = 36
6285 11:45:38.305764 CS Dly: 1 (0~32)
6286 11:45:38.305845
6287 11:45:38.308626 ----->DramcWriteLeveling(PI) begin...
6288 11:45:38.308702 ==
6289 11:45:38.311851 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 11:45:38.315647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 11:45:38.315730 ==
6292 11:45:38.318941 Write leveling (Byte 0): 40 => 8
6293 11:45:38.322034 Write leveling (Byte 1): 40 => 8
6294 11:45:38.325240 DramcWriteLeveling(PI) end<-----
6295 11:45:38.325330
6296 11:45:38.325393 ==
6297 11:45:38.328662 Dram Type= 6, Freq= 0, CH_0, rank 0
6298 11:45:38.331868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 11:45:38.331949 ==
6300 11:45:38.335027 [Gating] SW mode calibration
6301 11:45:38.341975 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6302 11:45:38.348175 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6303 11:45:38.351658 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6304 11:45:38.354699 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 11:45:38.361200 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 11:45:38.364945 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 11:45:38.368201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 11:45:38.374467 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 11:45:38.378318 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 11:45:38.381508 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 11:45:38.387867 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 11:45:38.391156 Total UI for P1: 0, mck2ui 16
6313 11:45:38.394181 best dqsien dly found for B0: ( 0, 14, 24)
6314 11:45:38.397961 Total UI for P1: 0, mck2ui 16
6315 11:45:38.401044 best dqsien dly found for B1: ( 0, 14, 24)
6316 11:45:38.404133 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6317 11:45:38.407828 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6318 11:45:38.407902
6319 11:45:38.410740 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6320 11:45:38.414428 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 11:45:38.417452 [Gating] SW calibration Done
6322 11:45:38.417533 ==
6323 11:45:38.420717 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 11:45:38.423917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 11:45:38.423997 ==
6326 11:45:38.428005 RX Vref Scan: 0
6327 11:45:38.428092
6328 11:45:38.430569 RX Vref 0 -> 0, step: 1
6329 11:45:38.430681
6330 11:45:38.430783 RX Delay -410 -> 252, step: 16
6331 11:45:38.437488 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6332 11:45:38.440681 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6333 11:45:38.443845 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6334 11:45:38.450356 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6335 11:45:38.453733 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6336 11:45:38.457060 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6337 11:45:38.460158 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6338 11:45:38.466909 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6339 11:45:38.470219 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6340 11:45:38.473193 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6341 11:45:38.476593 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6342 11:45:38.483448 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6343 11:45:38.486618 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6344 11:45:38.490223 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6345 11:45:38.493448 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6346 11:45:38.499844 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6347 11:45:38.499926 ==
6348 11:45:38.503089 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 11:45:38.506184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 11:45:38.506265 ==
6351 11:45:38.509824 DQS Delay:
6352 11:45:38.509932 DQS0 = 59, DQS1 = 59
6353 11:45:38.510024 DQM Delay:
6354 11:45:38.512710 DQM0 = 18, DQM1 = 10
6355 11:45:38.512801 DQ Delay:
6356 11:45:38.516467 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6357 11:45:38.519737 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6358 11:45:38.522705 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6359 11:45:38.525898 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6360 11:45:38.525980
6361 11:45:38.526046
6362 11:45:38.526105 ==
6363 11:45:38.529708 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 11:45:38.535847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 11:45:38.535927 ==
6366 11:45:38.535998
6367 11:45:38.536061
6368 11:45:38.536117 TX Vref Scan disable
6369 11:45:38.539043 == TX Byte 0 ==
6370 11:45:38.542361 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 11:45:38.546140 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 11:45:38.549276 == TX Byte 1 ==
6373 11:45:38.552508 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6374 11:45:38.555672 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6375 11:45:38.555747 ==
6376 11:45:38.558972 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 11:45:38.565323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 11:45:38.565412 ==
6379 11:45:38.565477
6380 11:45:38.565537
6381 11:45:38.569046 TX Vref Scan disable
6382 11:45:38.569157 == TX Byte 0 ==
6383 11:45:38.572121 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 11:45:38.578466 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 11:45:38.578576 == TX Byte 1 ==
6386 11:45:38.581616 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 11:45:38.588034 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 11:45:38.588140
6389 11:45:38.588233 [DATLAT]
6390 11:45:38.588323 Freq=400, CH0 RK0
6391 11:45:38.588410
6392 11:45:38.591855 DATLAT Default: 0xf
6393 11:45:38.595087 0, 0xFFFF, sum = 0
6394 11:45:38.595167 1, 0xFFFF, sum = 0
6395 11:45:38.598090 2, 0xFFFF, sum = 0
6396 11:45:38.598163 3, 0xFFFF, sum = 0
6397 11:45:38.601188 4, 0xFFFF, sum = 0
6398 11:45:38.601271 5, 0xFFFF, sum = 0
6399 11:45:38.604488 6, 0xFFFF, sum = 0
6400 11:45:38.604573 7, 0xFFFF, sum = 0
6401 11:45:38.607640 8, 0xFFFF, sum = 0
6402 11:45:38.607730 9, 0xFFFF, sum = 0
6403 11:45:38.610845 10, 0xFFFF, sum = 0
6404 11:45:38.610957 11, 0xFFFF, sum = 0
6405 11:45:38.614585 12, 0xFFFF, sum = 0
6406 11:45:38.614698 13, 0x0, sum = 1
6407 11:45:38.617922 14, 0x0, sum = 2
6408 11:45:38.618033 15, 0x0, sum = 3
6409 11:45:38.621010 16, 0x0, sum = 4
6410 11:45:38.621123 best_step = 14
6411 11:45:38.621217
6412 11:45:38.621305 ==
6413 11:45:38.623998 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 11:45:38.630976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 11:45:38.631083 ==
6416 11:45:38.631176 RX Vref Scan: 1
6417 11:45:38.631264
6418 11:45:38.634576 RX Vref 0 -> 0, step: 1
6419 11:45:38.634663
6420 11:45:38.637618 RX Delay -359 -> 252, step: 8
6421 11:45:38.637725
6422 11:45:38.640610 Set Vref, RX VrefLevel [Byte0]: 60
6423 11:45:38.644426 [Byte1]: 47
6424 11:45:38.647709
6425 11:45:38.647826 Final RX Vref Byte 0 = 60 to rank0
6426 11:45:38.651119 Final RX Vref Byte 1 = 47 to rank0
6427 11:45:38.654244 Final RX Vref Byte 0 = 60 to rank1
6428 11:45:38.657378 Final RX Vref Byte 1 = 47 to rank1==
6429 11:45:38.660624 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 11:45:38.667051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 11:45:38.667139 ==
6432 11:45:38.667204 DQS Delay:
6433 11:45:38.670338 DQS0 = 60, DQS1 = 64
6434 11:45:38.670420 DQM Delay:
6435 11:45:38.670484 DQM0 = 16, DQM1 = 11
6436 11:45:38.673579 DQ Delay:
6437 11:45:38.677137 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =16
6438 11:45:38.680466 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =28
6439 11:45:38.683551 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6440 11:45:38.686714 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6441 11:45:38.686822
6442 11:45:38.686897
6443 11:45:38.693865 [DQSOSCAuto] RK0, (LSB)MR18= 0x7e7c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6444 11:45:38.696865 CH0 RK0: MR19=C0C, MR18=7E7C
6445 11:45:38.703652 CH0_RK0: MR19=0xC0C, MR18=0x7E7C, DQSOSC=393, MR23=63, INC=382, DEC=254
6446 11:45:38.703760 ==
6447 11:45:38.706817 Dram Type= 6, Freq= 0, CH_0, rank 1
6448 11:45:38.709996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 11:45:38.710107 ==
6450 11:45:38.713209 [Gating] SW mode calibration
6451 11:45:38.720270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6452 11:45:38.726651 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6453 11:45:38.729743 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6454 11:45:38.733504 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 11:45:38.739756 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 11:45:38.742785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 11:45:38.746508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 11:45:38.752830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 11:45:38.756116 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 11:45:38.759561 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 11:45:38.766544 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 11:45:38.769838 Total UI for P1: 0, mck2ui 16
6463 11:45:38.772999 best dqsien dly found for B0: ( 0, 14, 24)
6464 11:45:38.773103 Total UI for P1: 0, mck2ui 16
6465 11:45:38.779657 best dqsien dly found for B1: ( 0, 14, 24)
6466 11:45:38.782823 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6467 11:45:38.786335 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6468 11:45:38.786416
6469 11:45:38.789593 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6470 11:45:38.792331 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 11:45:38.795566 [Gating] SW calibration Done
6472 11:45:38.795649 ==
6473 11:45:38.798781 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 11:45:38.802590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 11:45:38.802695 ==
6476 11:45:38.805787 RX Vref Scan: 0
6477 11:45:38.805865
6478 11:45:38.808892 RX Vref 0 -> 0, step: 1
6479 11:45:38.808996
6480 11:45:38.809089 RX Delay -410 -> 252, step: 16
6481 11:45:38.815491 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6482 11:45:38.818701 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6483 11:45:38.822090 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6484 11:45:38.829252 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6485 11:45:38.832552 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6486 11:45:38.835856 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6487 11:45:38.839118 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6488 11:45:38.845332 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6489 11:45:38.848528 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6490 11:45:38.851729 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6491 11:45:38.855597 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6492 11:45:38.862220 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6493 11:45:38.865468 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6494 11:45:38.868691 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6495 11:45:38.871908 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6496 11:45:38.878446 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6497 11:45:38.878551 ==
6498 11:45:38.881704 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 11:45:38.885346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 11:45:38.885461 ==
6501 11:45:38.885557 DQS Delay:
6502 11:45:38.888525 DQS0 = 59, DQS1 = 59
6503 11:45:38.888626 DQM Delay:
6504 11:45:38.891845 DQM0 = 16, DQM1 = 10
6505 11:45:38.891946 DQ Delay:
6506 11:45:38.895007 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6507 11:45:38.898242 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6508 11:45:38.901466 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6509 11:45:38.904522 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6510 11:45:38.904629
6511 11:45:38.904720
6512 11:45:38.904808 ==
6513 11:45:38.908252 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 11:45:38.911375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 11:45:38.914953 ==
6516 11:45:38.915060
6517 11:45:38.915162
6518 11:45:38.915260 TX Vref Scan disable
6519 11:45:38.917840 == TX Byte 0 ==
6520 11:45:38.921510 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6521 11:45:38.924749 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6522 11:45:38.927840 == TX Byte 1 ==
6523 11:45:38.930889 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6524 11:45:38.934870 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6525 11:45:38.935236 ==
6526 11:45:38.938419 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 11:45:38.944810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 11:45:38.945288 ==
6529 11:45:38.945725
6530 11:45:38.946060
6531 11:45:38.946377 TX Vref Scan disable
6532 11:45:38.947756 == TX Byte 0 ==
6533 11:45:38.951120 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6534 11:45:38.954164 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6535 11:45:38.957376 == TX Byte 1 ==
6536 11:45:38.961001 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6537 11:45:38.964248 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6538 11:45:38.964707
6539 11:45:38.967820 [DATLAT]
6540 11:45:38.968274 Freq=400, CH0 RK1
6541 11:45:38.968632
6542 11:45:38.970759 DATLAT Default: 0xe
6543 11:45:38.971253 0, 0xFFFF, sum = 0
6544 11:45:38.973915 1, 0xFFFF, sum = 0
6545 11:45:38.974381 2, 0xFFFF, sum = 0
6546 11:45:38.977589 3, 0xFFFF, sum = 0
6547 11:45:38.978048 4, 0xFFFF, sum = 0
6548 11:45:38.980824 5, 0xFFFF, sum = 0
6549 11:45:38.981287 6, 0xFFFF, sum = 0
6550 11:45:38.983908 7, 0xFFFF, sum = 0
6551 11:45:38.987499 8, 0xFFFF, sum = 0
6552 11:45:38.987939 9, 0xFFFF, sum = 0
6553 11:45:38.990442 10, 0xFFFF, sum = 0
6554 11:45:38.990878 11, 0xFFFF, sum = 0
6555 11:45:38.994220 12, 0xFFFF, sum = 0
6556 11:45:38.994637 13, 0x0, sum = 1
6557 11:45:38.997411 14, 0x0, sum = 2
6558 11:45:38.997827 15, 0x0, sum = 3
6559 11:45:39.000546 16, 0x0, sum = 4
6560 11:45:39.001000 best_step = 14
6561 11:45:39.001321
6562 11:45:39.001617 ==
6563 11:45:39.004009 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 11:45:39.007332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 11:45:39.007882 ==
6566 11:45:39.010507 RX Vref Scan: 0
6567 11:45:39.011017
6568 11:45:39.013587 RX Vref 0 -> 0, step: 1
6569 11:45:39.014127
6570 11:45:39.014594 RX Delay -359 -> 252, step: 8
6571 11:45:39.022657 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6572 11:45:39.025756 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6573 11:45:39.029424 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6574 11:45:39.035862 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6575 11:45:39.038799 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6576 11:45:39.042030 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6577 11:45:39.045517 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6578 11:45:39.052093 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6579 11:45:39.055697 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6580 11:45:39.058668 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6581 11:45:39.062101 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6582 11:45:39.068711 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6583 11:45:39.071700 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6584 11:45:39.074754 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6585 11:45:39.077979 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6586 11:45:39.085174 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6587 11:45:39.085391 ==
6588 11:45:39.088252 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 11:45:39.091428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 11:45:39.091627 ==
6591 11:45:39.094434 DQS Delay:
6592 11:45:39.094633 DQS0 = 60, DQS1 = 72
6593 11:45:39.094818 DQM Delay:
6594 11:45:39.097686 DQM0 = 11, DQM1 = 17
6595 11:45:39.097879 DQ Delay:
6596 11:45:39.101584 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6597 11:45:39.104733 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6598 11:45:39.107989 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6599 11:45:39.111299 DQ12 =24, DQ13 =28, DQ14 =24, DQ15 =24
6600 11:45:39.111502
6601 11:45:39.111704
6602 11:45:39.120961 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe75, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6603 11:45:39.121139 CH0 RK1: MR19=C0C, MR18=BE75
6604 11:45:39.127865 CH0_RK1: MR19=0xC0C, MR18=0xBE75, DQSOSC=386, MR23=63, INC=396, DEC=264
6605 11:45:39.130867 [RxdqsGatingPostProcess] freq 400
6606 11:45:39.137405 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6607 11:45:39.140854 best DQS0 dly(2T, 0.5T) = (0, 10)
6608 11:45:39.144113 best DQS1 dly(2T, 0.5T) = (0, 10)
6609 11:45:39.147818 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6610 11:45:39.151261 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6611 11:45:39.154370 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 11:45:39.154964 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 11:45:39.157536 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 11:45:39.160932 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 11:45:39.164377 Pre-setting of DQS Precalculation
6616 11:45:39.170943 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6617 11:45:39.171524 ==
6618 11:45:39.173710 Dram Type= 6, Freq= 0, CH_1, rank 0
6619 11:45:39.177249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 11:45:39.177814 ==
6621 11:45:39.183764 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 11:45:39.190391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6623 11:45:39.193995 [CA 0] Center 36 (8~64) winsize 57
6624 11:45:39.197176 [CA 1] Center 36 (8~64) winsize 57
6625 11:45:39.200201 [CA 2] Center 36 (8~64) winsize 57
6626 11:45:39.204091 [CA 3] Center 36 (8~64) winsize 57
6627 11:45:39.204559 [CA 4] Center 36 (8~64) winsize 57
6628 11:45:39.207081 [CA 5] Center 36 (8~64) winsize 57
6629 11:45:39.207642
6630 11:45:39.213335 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6631 11:45:39.213896
6632 11:45:39.216624 [CATrainingPosCal] consider 1 rank data
6633 11:45:39.220347 u2DelayCellTimex100 = 270/100 ps
6634 11:45:39.223553 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:45:39.226653 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:45:39.229828 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:45:39.233533 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:45:39.236577 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:45:39.240115 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:45:39.240571
6641 11:45:39.243571 CA PerBit enable=1, Macro0, CA PI delay=36
6642 11:45:39.243979
6643 11:45:39.246415 [CBTSetCACLKResult] CA Dly = 36
6644 11:45:39.249774 CS Dly: 1 (0~32)
6645 11:45:39.250295 ==
6646 11:45:39.253368 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 11:45:39.256472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 11:45:39.256972 ==
6649 11:45:39.262749 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6650 11:45:39.269486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6651 11:45:39.272614 [CA 0] Center 36 (8~64) winsize 57
6652 11:45:39.276276 [CA 1] Center 36 (8~64) winsize 57
6653 11:45:39.279371 [CA 2] Center 36 (8~64) winsize 57
6654 11:45:39.279942 [CA 3] Center 36 (8~64) winsize 57
6655 11:45:39.282944 [CA 4] Center 36 (8~64) winsize 57
6656 11:45:39.285890 [CA 5] Center 36 (8~64) winsize 57
6657 11:45:39.286389
6658 11:45:39.292682 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6659 11:45:39.293346
6660 11:45:39.295608 [CATrainingPosCal] consider 2 rank data
6661 11:45:39.299268 u2DelayCellTimex100 = 270/100 ps
6662 11:45:39.302398 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 11:45:39.305370 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:45:39.308372 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 11:45:39.312121 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 11:45:39.315266 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:45:39.318345 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 11:45:39.318864
6669 11:45:39.322141 CA PerBit enable=1, Macro0, CA PI delay=36
6670 11:45:39.322632
6671 11:45:39.325387 [CBTSetCACLKResult] CA Dly = 36
6672 11:45:39.328425 CS Dly: 1 (0~32)
6673 11:45:39.328834
6674 11:45:39.331446 ----->DramcWriteLeveling(PI) begin...
6675 11:45:39.331967 ==
6676 11:45:39.335088 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 11:45:39.338036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 11:45:39.338551 ==
6679 11:45:39.341766 Write leveling (Byte 0): 40 => 8
6680 11:45:39.344776 Write leveling (Byte 1): 40 => 8
6681 11:45:39.348345 DramcWriteLeveling(PI) end<-----
6682 11:45:39.348921
6683 11:45:39.349394 ==
6684 11:45:39.351549 Dram Type= 6, Freq= 0, CH_1, rank 0
6685 11:45:39.354502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 11:45:39.355084 ==
6687 11:45:39.358266 [Gating] SW mode calibration
6688 11:45:39.364661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6689 11:45:39.371352 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6690 11:45:39.374394 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6691 11:45:39.380889 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6692 11:45:39.384479 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 11:45:39.387528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 11:45:39.394232 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 11:45:39.397817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 11:45:39.400813 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 11:45:39.407339 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 11:45:39.410451 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 11:45:39.414004 Total UI for P1: 0, mck2ui 16
6700 11:45:39.417317 best dqsien dly found for B0: ( 0, 14, 24)
6701 11:45:39.420447 Total UI for P1: 0, mck2ui 16
6702 11:45:39.424220 best dqsien dly found for B1: ( 0, 14, 24)
6703 11:45:39.427284 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6704 11:45:39.430484 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6705 11:45:39.431004
6706 11:45:39.433653 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6707 11:45:39.440526 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 11:45:39.440978 [Gating] SW calibration Done
6709 11:45:39.441332 ==
6710 11:45:39.443526 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 11:45:39.450223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 11:45:39.450678 ==
6713 11:45:39.451190 RX Vref Scan: 0
6714 11:45:39.451631
6715 11:45:39.453872 RX Vref 0 -> 0, step: 1
6716 11:45:39.454275
6717 11:45:39.456724 RX Delay -410 -> 252, step: 16
6718 11:45:39.460213 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6719 11:45:39.463510 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6720 11:45:39.469999 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6721 11:45:39.473041 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6722 11:45:39.476854 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6723 11:45:39.479794 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6724 11:45:39.486030 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6725 11:45:39.489269 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6726 11:45:39.493227 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6727 11:45:39.496389 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6728 11:45:39.502811 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6729 11:45:39.505717 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6730 11:45:39.509388 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6731 11:45:39.515811 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6732 11:45:39.518883 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6733 11:45:39.522559 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6734 11:45:39.522911 ==
6735 11:45:39.525550 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 11:45:39.528705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 11:45:39.532243 ==
6738 11:45:39.532433 DQS Delay:
6739 11:45:39.532625 DQS0 = 51, DQS1 = 67
6740 11:45:39.535227 DQM Delay:
6741 11:45:39.535388 DQM0 = 13, DQM1 = 19
6742 11:45:39.539036 DQ Delay:
6743 11:45:39.542076 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6744 11:45:39.542209 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6745 11:45:39.545142 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6746 11:45:39.548885 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6747 11:45:39.548989
6748 11:45:39.552244
6749 11:45:39.552426 ==
6750 11:45:39.555356 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 11:45:39.558800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 11:45:39.558995 ==
6753 11:45:39.559093
6754 11:45:39.559171
6755 11:45:39.561692 TX Vref Scan disable
6756 11:45:39.561829 == TX Byte 0 ==
6757 11:45:39.565448 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 11:45:39.571844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 11:45:39.572004 == TX Byte 1 ==
6760 11:45:39.574700 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6761 11:45:39.581657 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6762 11:45:39.581751 ==
6763 11:45:39.584645 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 11:45:39.588459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 11:45:39.588627 ==
6766 11:45:39.588735
6767 11:45:39.588824
6768 11:45:39.591611 TX Vref Scan disable
6769 11:45:39.591729 == TX Byte 0 ==
6770 11:45:39.597778 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 11:45:39.601334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 11:45:39.601469 == TX Byte 1 ==
6773 11:45:39.608044 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 11:45:39.611322 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 11:45:39.611496
6776 11:45:39.611709 [DATLAT]
6777 11:45:39.614744 Freq=400, CH1 RK0
6778 11:45:39.614996
6779 11:45:39.615236 DATLAT Default: 0xf
6780 11:45:39.617479 0, 0xFFFF, sum = 0
6781 11:45:39.617680 1, 0xFFFF, sum = 0
6782 11:45:39.621188 2, 0xFFFF, sum = 0
6783 11:45:39.621430 3, 0xFFFF, sum = 0
6784 11:45:39.624362 4, 0xFFFF, sum = 0
6785 11:45:39.624789 5, 0xFFFF, sum = 0
6786 11:45:39.627921 6, 0xFFFF, sum = 0
6787 11:45:39.628301 7, 0xFFFF, sum = 0
6788 11:45:39.631042 8, 0xFFFF, sum = 0
6789 11:45:39.631535 9, 0xFFFF, sum = 0
6790 11:45:39.634290 10, 0xFFFF, sum = 0
6791 11:45:39.637894 11, 0xFFFF, sum = 0
6792 11:45:39.638506 12, 0xFFFF, sum = 0
6793 11:45:39.640977 13, 0x0, sum = 1
6794 11:45:39.641631 14, 0x0, sum = 2
6795 11:45:39.642165 15, 0x0, sum = 3
6796 11:45:39.644051 16, 0x0, sum = 4
6797 11:45:39.644610 best_step = 14
6798 11:45:39.645171
6799 11:45:39.647776 ==
6800 11:45:39.648368 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 11:45:39.654069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 11:45:39.654650 ==
6803 11:45:39.655242 RX Vref Scan: 1
6804 11:45:39.655610
6805 11:45:39.657347 RX Vref 0 -> 0, step: 1
6806 11:45:39.657802
6807 11:45:39.661294 RX Delay -375 -> 252, step: 8
6808 11:45:39.661898
6809 11:45:39.664160 Set Vref, RX VrefLevel [Byte0]: 54
6810 11:45:39.667589 [Byte1]: 48
6811 11:45:39.671113
6812 11:45:39.671676 Final RX Vref Byte 0 = 54 to rank0
6813 11:45:39.674279 Final RX Vref Byte 1 = 48 to rank0
6814 11:45:39.677849 Final RX Vref Byte 0 = 54 to rank1
6815 11:45:39.681266 Final RX Vref Byte 1 = 48 to rank1==
6816 11:45:39.684759 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 11:45:39.691148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 11:45:39.691627 ==
6819 11:45:39.691991 DQS Delay:
6820 11:45:39.694612 DQS0 = 52, DQS1 = 68
6821 11:45:39.695220 DQM Delay:
6822 11:45:39.695585 DQM0 = 9, DQM1 = 14
6823 11:45:39.698008 DQ Delay:
6824 11:45:39.700575 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6825 11:45:39.704458 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6826 11:45:39.704915 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6827 11:45:39.707441 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6828 11:45:39.710444
6829 11:45:39.710944
6830 11:45:39.717222 [DQSOSCAuto] RK0, (LSB)MR18= 0x5569, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6831 11:45:39.720248 CH1 RK0: MR19=C0C, MR18=5569
6832 11:45:39.727165 CH1_RK0: MR19=0xC0C, MR18=0x5569, DQSOSC=396, MR23=63, INC=376, DEC=251
6833 11:45:39.727643 ==
6834 11:45:39.730275 Dram Type= 6, Freq= 0, CH_1, rank 1
6835 11:45:39.733942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 11:45:39.734517 ==
6837 11:45:39.737418 [Gating] SW mode calibration
6838 11:45:39.743387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6839 11:45:39.750273 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6840 11:45:39.753413 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6841 11:45:39.757096 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6842 11:45:39.763334 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 11:45:39.766495 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 11:45:39.770087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 11:45:39.776842 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 11:45:39.779941 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 11:45:39.783051 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 11:45:39.789497 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 11:45:39.793198 Total UI for P1: 0, mck2ui 16
6850 11:45:39.796070 best dqsien dly found for B0: ( 0, 14, 24)
6851 11:45:39.796525 Total UI for P1: 0, mck2ui 16
6852 11:45:39.802986 best dqsien dly found for B1: ( 0, 14, 24)
6853 11:45:39.806146 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6854 11:45:39.809294 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6855 11:45:39.809752
6856 11:45:39.812907 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6857 11:45:39.816346 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 11:45:39.819974 [Gating] SW calibration Done
6859 11:45:39.820570 ==
6860 11:45:39.822746 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 11:45:39.826007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 11:45:39.826559 ==
6863 11:45:39.829634 RX Vref Scan: 0
6864 11:45:39.830217
6865 11:45:39.832353 RX Vref 0 -> 0, step: 1
6866 11:45:39.832907
6867 11:45:39.833405 RX Delay -410 -> 252, step: 16
6868 11:45:39.838923 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6869 11:45:39.842670 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6870 11:45:39.845513 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6871 11:45:39.852354 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6872 11:45:39.855428 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6873 11:45:39.859208 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6874 11:45:39.862244 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6875 11:45:39.868722 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6876 11:45:39.872780 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6877 11:45:39.875422 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6878 11:45:39.878716 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6879 11:45:39.885249 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6880 11:45:39.888428 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6881 11:45:39.891882 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6882 11:45:39.895251 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6883 11:45:39.901983 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6884 11:45:39.902537 ==
6885 11:45:39.905047 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 11:45:39.908202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 11:45:39.908848 ==
6888 11:45:39.911422 DQS Delay:
6889 11:45:39.911890 DQS0 = 59, DQS1 = 59
6890 11:45:39.912412 DQM Delay:
6891 11:45:39.914553 DQM0 = 19, DQM1 = 12
6892 11:45:39.915141 DQ Delay:
6893 11:45:39.918329 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6894 11:45:39.921588 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6895 11:45:39.924596 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6896 11:45:39.928371 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6897 11:45:39.928827
6898 11:45:39.929188
6899 11:45:39.929523 ==
6900 11:45:39.931541 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 11:45:39.937870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 11:45:39.938442 ==
6903 11:45:39.938812
6904 11:45:39.939186
6905 11:45:39.939508 TX Vref Scan disable
6906 11:45:39.941221 == TX Byte 0 ==
6907 11:45:39.944749 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6908 11:45:39.947702 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6909 11:45:39.951012 == TX Byte 1 ==
6910 11:45:39.954048 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6911 11:45:39.957611 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6912 11:45:39.958095 ==
6913 11:45:39.961415 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 11:45:39.967507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 11:45:39.967969 ==
6916 11:45:39.968328
6917 11:45:39.968662
6918 11:45:39.968984 TX Vref Scan disable
6919 11:45:39.970628 == TX Byte 0 ==
6920 11:45:39.973826 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6921 11:45:39.977747 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6922 11:45:39.980911 == TX Byte 1 ==
6923 11:45:39.983979 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6924 11:45:39.987318 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6925 11:45:39.987784
6926 11:45:39.990522 [DATLAT]
6927 11:45:39.991160 Freq=400, CH1 RK1
6928 11:45:39.991693
6929 11:45:39.994143 DATLAT Default: 0xe
6930 11:45:39.994601 0, 0xFFFF, sum = 0
6931 11:45:39.997062 1, 0xFFFF, sum = 0
6932 11:45:39.997528 2, 0xFFFF, sum = 0
6933 11:45:40.000509 3, 0xFFFF, sum = 0
6934 11:45:40.000980 4, 0xFFFF, sum = 0
6935 11:45:40.003979 5, 0xFFFF, sum = 0
6936 11:45:40.006758 6, 0xFFFF, sum = 0
6937 11:45:40.007308 7, 0xFFFF, sum = 0
6938 11:45:40.010302 8, 0xFFFF, sum = 0
6939 11:45:40.010958 9, 0xFFFF, sum = 0
6940 11:45:40.013526 10, 0xFFFF, sum = 0
6941 11:45:40.013991 11, 0xFFFF, sum = 0
6942 11:45:40.016662 12, 0xFFFF, sum = 0
6943 11:45:40.017130 13, 0x0, sum = 1
6944 11:45:40.020745 14, 0x0, sum = 2
6945 11:45:40.021211 15, 0x0, sum = 3
6946 11:45:40.023626 16, 0x0, sum = 4
6947 11:45:40.024093 best_step = 14
6948 11:45:40.024456
6949 11:45:40.024791 ==
6950 11:45:40.026688 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 11:45:40.030152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 11:45:40.033137 ==
6953 11:45:40.033602 RX Vref Scan: 0
6954 11:45:40.034189
6955 11:45:40.036162 RX Vref 0 -> 0, step: 1
6956 11:45:40.036621
6957 11:45:40.040008 RX Delay -359 -> 252, step: 8
6958 11:45:40.046443 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6959 11:45:40.049647 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6960 11:45:40.052616 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6961 11:45:40.056186 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6962 11:45:40.062746 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6963 11:45:40.066313 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6964 11:45:40.069589 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6965 11:45:40.072360 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6966 11:45:40.079530 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6967 11:45:40.082211 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6968 11:45:40.085919 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6969 11:45:40.089239 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6970 11:45:40.096022 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6971 11:45:40.098957 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6972 11:45:40.101887 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6973 11:45:40.109015 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6974 11:45:40.109490 ==
6975 11:45:40.111966 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 11:45:40.115265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 11:45:40.115820 ==
6978 11:45:40.116344 DQS Delay:
6979 11:45:40.118313 DQS0 = 60, DQS1 = 64
6980 11:45:40.118767 DQM Delay:
6981 11:45:40.122019 DQM0 = 13, DQM1 = 10
6982 11:45:40.122471 DQ Delay:
6983 11:45:40.125090 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6984 11:45:40.128150 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6985 11:45:40.132167 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6986 11:45:40.135199 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6987 11:45:40.135661
6988 11:45:40.136050
6989 11:45:40.142257 [DQSOSCAuto] RK1, (LSB)MR18= 0x7baa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6990 11:45:40.145095 CH1 RK1: MR19=C0C, MR18=7BAA
6991 11:45:40.151684 CH1_RK1: MR19=0xC0C, MR18=0x7BAA, DQSOSC=388, MR23=63, INC=392, DEC=261
6992 11:45:40.154643 [RxdqsGatingPostProcess] freq 400
6993 11:45:40.161354 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6994 11:45:40.164417 best DQS0 dly(2T, 0.5T) = (0, 10)
6995 11:45:40.168223 best DQS1 dly(2T, 0.5T) = (0, 10)
6996 11:45:40.171381 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6997 11:45:40.174858 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6998 11:45:40.175325 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 11:45:40.177827 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 11:45:40.181351 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 11:45:40.184569 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 11:45:40.187582 Pre-setting of DQS Precalculation
7003 11:45:40.194232 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7004 11:45:40.200628 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7005 11:45:40.207495 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7006 11:45:40.208100
7007 11:45:40.208615
7008 11:45:40.210472 [Calibration Summary] 800 Mbps
7009 11:45:40.210973 CH 0, Rank 0
7010 11:45:40.214320 SW Impedance : PASS
7011 11:45:40.216987 DUTY Scan : NO K
7012 11:45:40.217585 ZQ Calibration : PASS
7013 11:45:40.220722 Jitter Meter : NO K
7014 11:45:40.223969 CBT Training : PASS
7015 11:45:40.224427 Write leveling : PASS
7016 11:45:40.226677 RX DQS gating : PASS
7017 11:45:40.230400 RX DQ/DQS(RDDQC) : PASS
7018 11:45:40.230982 TX DQ/DQS : PASS
7019 11:45:40.233686 RX DATLAT : PASS
7020 11:45:40.236860 RX DQ/DQS(Engine): PASS
7021 11:45:40.237316 TX OE : NO K
7022 11:45:40.240592 All Pass.
7023 11:45:40.241047
7024 11:45:40.241407 CH 0, Rank 1
7025 11:45:40.243773 SW Impedance : PASS
7026 11:45:40.244227 DUTY Scan : NO K
7027 11:45:40.246790 ZQ Calibration : PASS
7028 11:45:40.250073 Jitter Meter : NO K
7029 11:45:40.250526 CBT Training : PASS
7030 11:45:40.253451 Write leveling : NO K
7031 11:45:40.256494 RX DQS gating : PASS
7032 11:45:40.256909 RX DQ/DQS(RDDQC) : PASS
7033 11:45:40.260110 TX DQ/DQS : PASS
7034 11:45:40.263163 RX DATLAT : PASS
7035 11:45:40.263575 RX DQ/DQS(Engine): PASS
7036 11:45:40.266229 TX OE : NO K
7037 11:45:40.266769 All Pass.
7038 11:45:40.267145
7039 11:45:40.269409 CH 1, Rank 0
7040 11:45:40.269821 SW Impedance : PASS
7041 11:45:40.273068 DUTY Scan : NO K
7042 11:45:40.276435 ZQ Calibration : PASS
7043 11:45:40.276848 Jitter Meter : NO K
7044 11:45:40.279481 CBT Training : PASS
7045 11:45:40.283034 Write leveling : PASS
7046 11:45:40.283445 RX DQS gating : PASS
7047 11:45:40.285869 RX DQ/DQS(RDDQC) : PASS
7048 11:45:40.289341 TX DQ/DQS : PASS
7049 11:45:40.289754 RX DATLAT : PASS
7050 11:45:40.293133 RX DQ/DQS(Engine): PASS
7051 11:45:40.293542 TX OE : NO K
7052 11:45:40.296327 All Pass.
7053 11:45:40.296737
7054 11:45:40.297063 CH 1, Rank 1
7055 11:45:40.299484 SW Impedance : PASS
7056 11:45:40.302376 DUTY Scan : NO K
7057 11:45:40.302748 ZQ Calibration : PASS
7058 11:45:40.306221 Jitter Meter : NO K
7059 11:45:40.306633 CBT Training : PASS
7060 11:45:40.309056 Write leveling : NO K
7061 11:45:40.312423 RX DQS gating : PASS
7062 11:45:40.312963 RX DQ/DQS(RDDQC) : PASS
7063 11:45:40.315549 TX DQ/DQS : PASS
7064 11:45:40.319149 RX DATLAT : PASS
7065 11:45:40.319555 RX DQ/DQS(Engine): PASS
7066 11:45:40.322316 TX OE : NO K
7067 11:45:40.322772 All Pass.
7068 11:45:40.323296
7069 11:45:40.325690 DramC Write-DBI off
7070 11:45:40.329069 PER_BANK_REFRESH: Hybrid Mode
7071 11:45:40.329661 TX_TRACKING: ON
7072 11:45:40.338419 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7073 11:45:40.342282 [FAST_K] Save calibration result to emmc
7074 11:45:40.345442 dramc_set_vcore_voltage set vcore to 725000
7075 11:45:40.348749 Read voltage for 1600, 0
7076 11:45:40.349380 Vio18 = 0
7077 11:45:40.351588 Vcore = 725000
7078 11:45:40.351996 Vdram = 0
7079 11:45:40.352321 Vddq = 0
7080 11:45:40.352622 Vmddr = 0
7081 11:45:40.358350 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7082 11:45:40.365062 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7083 11:45:40.365607 MEM_TYPE=3, freq_sel=13
7084 11:45:40.368448 sv_algorithm_assistance_LP4_3733
7085 11:45:40.375103 ============ PULL DRAM RESETB DOWN ============
7086 11:45:40.378195 ========== PULL DRAM RESETB DOWN end =========
7087 11:45:40.381730 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7088 11:45:40.384655 ===================================
7089 11:45:40.388136 LPDDR4 DRAM CONFIGURATION
7090 11:45:40.391069 ===================================
7091 11:45:40.391556 EX_ROW_EN[0] = 0x0
7092 11:45:40.394583 EX_ROW_EN[1] = 0x0
7093 11:45:40.397445 LP4Y_EN = 0x0
7094 11:45:40.398116 WORK_FSP = 0x1
7095 11:45:40.401251 WL = 0x5
7096 11:45:40.401769 RL = 0x5
7097 11:45:40.404496 BL = 0x2
7098 11:45:40.404916 RPST = 0x0
7099 11:45:40.407885 RD_PRE = 0x0
7100 11:45:40.408343 WR_PRE = 0x1
7101 11:45:40.410535 WR_PST = 0x1
7102 11:45:40.411215 DBI_WR = 0x0
7103 11:45:40.414062 DBI_RD = 0x0
7104 11:45:40.414598 OTF = 0x1
7105 11:45:40.417187 ===================================
7106 11:45:40.421080 ===================================
7107 11:45:40.424308 ANA top config
7108 11:45:40.427309 ===================================
7109 11:45:40.430416 DLL_ASYNC_EN = 0
7110 11:45:40.430983 ALL_SLAVE_EN = 0
7111 11:45:40.433900 NEW_RANK_MODE = 1
7112 11:45:40.437222 DLL_IDLE_MODE = 1
7113 11:45:40.440322 LP45_APHY_COMB_EN = 1
7114 11:45:40.444284 TX_ODT_DIS = 0
7115 11:45:40.444884 NEW_8X_MODE = 1
7116 11:45:40.446900 ===================================
7117 11:45:40.450613 ===================================
7118 11:45:40.453750 data_rate = 3200
7119 11:45:40.457080 CKR = 1
7120 11:45:40.460518 DQ_P2S_RATIO = 8
7121 11:45:40.463471 ===================================
7122 11:45:40.467116 CA_P2S_RATIO = 8
7123 11:45:40.470255 DQ_CA_OPEN = 0
7124 11:45:40.470714 DQ_SEMI_OPEN = 0
7125 11:45:40.473473 CA_SEMI_OPEN = 0
7126 11:45:40.476693 CA_FULL_RATE = 0
7127 11:45:40.480291 DQ_CKDIV4_EN = 0
7128 11:45:40.483452 CA_CKDIV4_EN = 0
7129 11:45:40.486523 CA_PREDIV_EN = 0
7130 11:45:40.486965 PH8_DLY = 12
7131 11:45:40.490080 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7132 11:45:40.493049 DQ_AAMCK_DIV = 4
7133 11:45:40.496614 CA_AAMCK_DIV = 4
7134 11:45:40.499587 CA_ADMCK_DIV = 4
7135 11:45:40.503140 DQ_TRACK_CA_EN = 0
7136 11:45:40.506095 CA_PICK = 1600
7137 11:45:40.506505 CA_MCKIO = 1600
7138 11:45:40.509634 MCKIO_SEMI = 0
7139 11:45:40.512972 PLL_FREQ = 3068
7140 11:45:40.516231 DQ_UI_PI_RATIO = 32
7141 11:45:40.519667 CA_UI_PI_RATIO = 0
7142 11:45:40.522569 ===================================
7143 11:45:40.526403 ===================================
7144 11:45:40.529531 memory_type:LPDDR4
7145 11:45:40.529977 GP_NUM : 10
7146 11:45:40.532686 SRAM_EN : 1
7147 11:45:40.533090 MD32_EN : 0
7148 11:45:40.535770 ===================================
7149 11:45:40.539409 [ANA_INIT] >>>>>>>>>>>>>>
7150 11:45:40.542695 <<<<<< [CONFIGURE PHASE]: ANA_TX
7151 11:45:40.545794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7152 11:45:40.549176 ===================================
7153 11:45:40.552422 data_rate = 3200,PCW = 0X7600
7154 11:45:40.555799 ===================================
7155 11:45:40.558792 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7156 11:45:40.565515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7157 11:45:40.569060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 11:45:40.575280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7159 11:45:40.578928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7160 11:45:40.582058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7161 11:45:40.582472 [ANA_INIT] flow start
7162 11:45:40.585728 [ANA_INIT] PLL >>>>>>>>
7163 11:45:40.588838 [ANA_INIT] PLL <<<<<<<<
7164 11:45:40.591922 [ANA_INIT] MIDPI >>>>>>>>
7165 11:45:40.592331 [ANA_INIT] MIDPI <<<<<<<<
7166 11:45:40.595698 [ANA_INIT] DLL >>>>>>>>
7167 11:45:40.598553 [ANA_INIT] DLL <<<<<<<<
7168 11:45:40.599017 [ANA_INIT] flow end
7169 11:45:40.602163 ============ LP4 DIFF to SE enter ============
7170 11:45:40.608235 ============ LP4 DIFF to SE exit ============
7171 11:45:40.608668 [ANA_INIT] <<<<<<<<<<<<<
7172 11:45:40.611684 [Flow] Enable top DCM control >>>>>
7173 11:45:40.615098 [Flow] Enable top DCM control <<<<<
7174 11:45:40.618050 Enable DLL master slave shuffle
7175 11:45:40.624869 ==============================================================
7176 11:45:40.628088 Gating Mode config
7177 11:45:40.631833 ==============================================================
7178 11:45:40.634975 Config description:
7179 11:45:40.644844 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7180 11:45:40.651233 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7181 11:45:40.654777 SELPH_MODE 0: By rank 1: By Phase
7182 11:45:40.661278 ==============================================================
7183 11:45:40.664385 GAT_TRACK_EN = 1
7184 11:45:40.667558 RX_GATING_MODE = 2
7185 11:45:40.671052 RX_GATING_TRACK_MODE = 2
7186 11:45:40.674254 SELPH_MODE = 1
7187 11:45:40.674724 PICG_EARLY_EN = 1
7188 11:45:40.677780 VALID_LAT_VALUE = 1
7189 11:45:40.683967 ==============================================================
7190 11:45:40.687675 Enter into Gating configuration >>>>
7191 11:45:40.690801 Exit from Gating configuration <<<<
7192 11:45:40.694357 Enter into DVFS_PRE_config >>>>>
7193 11:45:40.703674 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7194 11:45:40.707270 Exit from DVFS_PRE_config <<<<<
7195 11:45:40.710305 Enter into PICG configuration >>>>
7196 11:45:40.714003 Exit from PICG configuration <<<<
7197 11:45:40.716847 [RX_INPUT] configuration >>>>>
7198 11:45:40.720213 [RX_INPUT] configuration <<<<<
7199 11:45:40.726606 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7200 11:45:40.730230 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7201 11:45:40.736604 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 11:45:40.743500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 11:45:40.749576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7204 11:45:40.756658 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7205 11:45:40.759673 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7206 11:45:40.762735 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7207 11:45:40.766127 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7208 11:45:40.772999 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7209 11:45:40.776265 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7210 11:45:40.779268 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7211 11:45:40.782938 ===================================
7212 11:45:40.786433 LPDDR4 DRAM CONFIGURATION
7213 11:45:40.789516 ===================================
7214 11:45:40.792762 EX_ROW_EN[0] = 0x0
7215 11:45:40.793334 EX_ROW_EN[1] = 0x0
7216 11:45:40.796153 LP4Y_EN = 0x0
7217 11:45:40.796563 WORK_FSP = 0x1
7218 11:45:40.799263 WL = 0x5
7219 11:45:40.799671 RL = 0x5
7220 11:45:40.802349 BL = 0x2
7221 11:45:40.802758 RPST = 0x0
7222 11:45:40.805481 RD_PRE = 0x0
7223 11:45:40.805834 WR_PRE = 0x1
7224 11:45:40.808790 WR_PST = 0x1
7225 11:45:40.809138 DBI_WR = 0x0
7226 11:45:40.812009 DBI_RD = 0x0
7227 11:45:40.812377 OTF = 0x1
7228 11:45:40.815736 ===================================
7229 11:45:40.822020 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7230 11:45:40.825137 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7231 11:45:40.828596 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 11:45:40.831710 ===================================
7233 11:45:40.835319 LPDDR4 DRAM CONFIGURATION
7234 11:45:40.838905 ===================================
7235 11:45:40.842096 EX_ROW_EN[0] = 0x10
7236 11:45:40.842498 EX_ROW_EN[1] = 0x0
7237 11:45:40.845309 LP4Y_EN = 0x0
7238 11:45:40.845829 WORK_FSP = 0x1
7239 11:45:40.848493 WL = 0x5
7240 11:45:40.848841 RL = 0x5
7241 11:45:40.851546 BL = 0x2
7242 11:45:40.851959 RPST = 0x0
7243 11:45:40.855478 RD_PRE = 0x0
7244 11:45:40.855899 WR_PRE = 0x1
7245 11:45:40.858814 WR_PST = 0x1
7246 11:45:40.859272 DBI_WR = 0x0
7247 11:45:40.861913 DBI_RD = 0x0
7248 11:45:40.862399 OTF = 0x1
7249 11:45:40.865009 ===================================
7250 11:45:40.871485 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7251 11:45:40.872029 ==
7252 11:45:40.875091 Dram Type= 6, Freq= 0, CH_0, rank 0
7253 11:45:40.881648 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7254 11:45:40.882096 ==
7255 11:45:40.882488 [Duty_Offset_Calibration]
7256 11:45:40.884628 B0:2 B1:0 CA:3
7257 11:45:40.885167
7258 11:45:40.888339 [DutyScan_Calibration_Flow] k_type=0
7259 11:45:40.897583
7260 11:45:40.898140 ==CLK 0==
7261 11:45:40.900689 Final CLK duty delay cell = 0
7262 11:45:40.904526 [0] MAX Duty = 5031%(X100), DQS PI = 12
7263 11:45:40.907825 [0] MIN Duty = 4907%(X100), DQS PI = 6
7264 11:45:40.908402 [0] AVG Duty = 4969%(X100)
7265 11:45:40.911149
7266 11:45:40.914433 CH0 CLK Duty spec in!! Max-Min= 124%
7267 11:45:40.917443 [DutyScan_Calibration_Flow] ====Done====
7268 11:45:40.918013
7269 11:45:40.920720 [DutyScan_Calibration_Flow] k_type=1
7270 11:45:40.937620
7271 11:45:40.938102 ==DQS 0 ==
7272 11:45:40.940552 Final DQS duty delay cell = 0
7273 11:45:40.943810 [0] MAX Duty = 5125%(X100), DQS PI = 30
7274 11:45:40.947191 [0] MIN Duty = 4875%(X100), DQS PI = 48
7275 11:45:40.950662 [0] AVG Duty = 5000%(X100)
7276 11:45:40.951133
7277 11:45:40.951485 ==DQS 1 ==
7278 11:45:40.953713 Final DQS duty delay cell = 0
7279 11:45:40.956881 [0] MAX Duty = 5156%(X100), DQS PI = 30
7280 11:45:40.960519 [0] MIN Duty = 5062%(X100), DQS PI = 0
7281 11:45:40.963250 [0] AVG Duty = 5109%(X100)
7282 11:45:40.963670
7283 11:45:40.967089 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7284 11:45:40.967516
7285 11:45:40.970288 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7286 11:45:40.973494 [DutyScan_Calibration_Flow] ====Done====
7287 11:45:40.973911
7288 11:45:40.976553 [DutyScan_Calibration_Flow] k_type=3
7289 11:45:40.994895
7290 11:45:40.995311 ==DQM 0 ==
7291 11:45:40.998118 Final DQM duty delay cell = 0
7292 11:45:41.001362 [0] MAX Duty = 5187%(X100), DQS PI = 32
7293 11:45:41.004693 [0] MIN Duty = 4875%(X100), DQS PI = 0
7294 11:45:41.008126 [0] AVG Duty = 5031%(X100)
7295 11:45:41.008682
7296 11:45:41.009180 ==DQM 1 ==
7297 11:45:41.011285 Final DQM duty delay cell = 4
7298 11:45:41.014539 [4] MAX Duty = 5187%(X100), DQS PI = 60
7299 11:45:41.017806 [4] MIN Duty = 5031%(X100), DQS PI = 12
7300 11:45:41.020866 [4] AVG Duty = 5109%(X100)
7301 11:45:41.021081
7302 11:45:41.024710 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7303 11:45:41.024896
7304 11:45:41.027886 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7305 11:45:41.030980 [DutyScan_Calibration_Flow] ====Done====
7306 11:45:41.031126
7307 11:45:41.034194 [DutyScan_Calibration_Flow] k_type=2
7308 11:45:41.050837
7309 11:45:41.050985 ==DQ 0 ==
7310 11:45:41.053956 Final DQ duty delay cell = -4
7311 11:45:41.057658 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7312 11:45:41.060588 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7313 11:45:41.064317 [-4] AVG Duty = 4938%(X100)
7314 11:45:41.064509
7315 11:45:41.064693 ==DQ 1 ==
7316 11:45:41.067694 Final DQ duty delay cell = 0
7317 11:45:41.070929 [0] MAX Duty = 5156%(X100), DQS PI = 60
7318 11:45:41.074365 [0] MIN Duty = 5000%(X100), DQS PI = 16
7319 11:45:41.077343 [0] AVG Duty = 5078%(X100)
7320 11:45:41.077744
7321 11:45:41.081066 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7322 11:45:41.081468
7323 11:45:41.083815 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7324 11:45:41.087474 [DutyScan_Calibration_Flow] ====Done====
7325 11:45:41.088010 ==
7326 11:45:41.091005 Dram Type= 6, Freq= 0, CH_1, rank 0
7327 11:45:41.094106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7328 11:45:41.094576 ==
7329 11:45:41.097349 [Duty_Offset_Calibration]
7330 11:45:41.097792 B0:1 B1:-2 CA:1
7331 11:45:41.098138
7332 11:45:41.100677 [DutyScan_Calibration_Flow] k_type=0
7333 11:45:41.112275
7334 11:45:41.112809 ==CLK 0==
7335 11:45:41.114861 Final CLK duty delay cell = 0
7336 11:45:41.118068 [0] MAX Duty = 5062%(X100), DQS PI = 20
7337 11:45:41.121435 [0] MIN Duty = 4844%(X100), DQS PI = 0
7338 11:45:41.124643 [0] AVG Duty = 4953%(X100)
7339 11:45:41.125210
7340 11:45:41.128503 CH1 CLK Duty spec in!! Max-Min= 218%
7341 11:45:41.131672 [DutyScan_Calibration_Flow] ====Done====
7342 11:45:41.132343
7343 11:45:41.134882 [DutyScan_Calibration_Flow] k_type=1
7344 11:45:41.151562
7345 11:45:41.152173 ==DQS 0 ==
7346 11:45:41.154602 Final DQS duty delay cell = 0
7347 11:45:41.157609 [0] MAX Duty = 5187%(X100), DQS PI = 24
7348 11:45:41.161074 [0] MIN Duty = 5062%(X100), DQS PI = 46
7349 11:45:41.164145 [0] AVG Duty = 5124%(X100)
7350 11:45:41.164689
7351 11:45:41.165203 ==DQS 1 ==
7352 11:45:41.167510 Final DQS duty delay cell = 0
7353 11:45:41.171234 [0] MAX Duty = 5093%(X100), DQS PI = 0
7354 11:45:41.174336 [0] MIN Duty = 4844%(X100), DQS PI = 24
7355 11:45:41.177682 [0] AVG Duty = 4968%(X100)
7356 11:45:41.178156
7357 11:45:41.180909 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7358 11:45:41.181380
7359 11:45:41.184065 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7360 11:45:41.187234 [DutyScan_Calibration_Flow] ====Done====
7361 11:45:41.187836
7362 11:45:41.190681 [DutyScan_Calibration_Flow] k_type=3
7363 11:45:41.208154
7364 11:45:41.208555 ==DQM 0 ==
7365 11:45:41.211279 Final DQM duty delay cell = 0
7366 11:45:41.214524 [0] MAX Duty = 5031%(X100), DQS PI = 24
7367 11:45:41.217715 [0] MIN Duty = 4813%(X100), DQS PI = 54
7368 11:45:41.221431 [0] AVG Duty = 4922%(X100)
7369 11:45:41.221834
7370 11:45:41.222147 ==DQM 1 ==
7371 11:45:41.224720 Final DQM duty delay cell = 0
7372 11:45:41.228105 [0] MAX Duty = 5094%(X100), DQS PI = 36
7373 11:45:41.231406 [0] MIN Duty = 4875%(X100), DQS PI = 24
7374 11:45:41.234340 [0] AVG Duty = 4984%(X100)
7375 11:45:41.234995
7376 11:45:41.237440 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7377 11:45:41.238017
7378 11:45:41.241188 CH1 DQM 1 Duty spec in!! Max-Min= 219%
7379 11:45:41.244354 [DutyScan_Calibration_Flow] ====Done====
7380 11:45:41.244894
7381 11:45:41.247614 [DutyScan_Calibration_Flow] k_type=2
7382 11:45:41.264615
7383 11:45:41.265035 ==DQ 0 ==
7384 11:45:41.267918 Final DQ duty delay cell = 0
7385 11:45:41.271567 [0] MAX Duty = 5093%(X100), DQS PI = 20
7386 11:45:41.274748 [0] MIN Duty = 4907%(X100), DQS PI = 62
7387 11:45:41.277885 [0] AVG Duty = 5000%(X100)
7388 11:45:41.278363
7389 11:45:41.278684 ==DQ 1 ==
7390 11:45:41.281014 Final DQ duty delay cell = 0
7391 11:45:41.284358 [0] MAX Duty = 5156%(X100), DQS PI = 36
7392 11:45:41.288082 [0] MIN Duty = 4969%(X100), DQS PI = 24
7393 11:45:41.288611 [0] AVG Duty = 5062%(X100)
7394 11:45:41.291269
7395 11:45:41.294400 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7396 11:45:41.294944
7397 11:45:41.297972 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7398 11:45:41.300762 [DutyScan_Calibration_Flow] ====Done====
7399 11:45:41.304393 nWR fixed to 30
7400 11:45:41.307663 [ModeRegInit_LP4] CH0 RK0
7401 11:45:41.308082 [ModeRegInit_LP4] CH0 RK1
7402 11:45:41.310537 [ModeRegInit_LP4] CH1 RK0
7403 11:45:41.314064 [ModeRegInit_LP4] CH1 RK1
7404 11:45:41.314441 match AC timing 5
7405 11:45:41.320603 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7406 11:45:41.323717 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7407 11:45:41.327594 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7408 11:45:41.333480 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7409 11:45:41.337156 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7410 11:45:41.337531 [MiockJmeterHQA]
7411 11:45:41.337913
7412 11:45:41.340385 [DramcMiockJmeter] u1RxGatingPI = 0
7413 11:45:41.423775 0 : 4260, 4032
7414 11:45:41.423943 4 : 4254, 4029
7415 11:45:41.424035 8 : 4253, 4027
7416 11:45:41.424118 12 : 4366, 4139
7417 11:45:41.424198 16 : 4257, 4030
7418 11:45:41.424276 20 : 4368, 4139
7419 11:45:41.424353 24 : 4366, 4140
7420 11:45:41.424460 28 : 4255, 4026
7421 11:45:41.424540 32 : 4255, 4029
7422 11:45:41.424616 36 : 4255, 4029
7423 11:45:41.424692 40 : 4370, 4142
7424 11:45:41.424766 44 : 4255, 4029
7425 11:45:41.424841 48 : 4257, 4032
7426 11:45:41.424914 52 : 4365, 4140
7427 11:45:41.424987 56 : 4255, 4030
7428 11:45:41.425060 60 : 4363, 4140
7429 11:45:41.425134 64 : 4252, 4029
7430 11:45:41.425207 68 : 4255, 4029
7431 11:45:41.425280 72 : 4254, 4030
7432 11:45:41.425354 76 : 4252, 4029
7433 11:45:41.425427 80 : 4257, 4031
7434 11:45:41.425499 84 : 4255, 4029
7435 11:45:41.425572 88 : 4253, 4029
7436 11:45:41.425651 92 : 4254, 4030
7437 11:45:41.425724 96 : 4252, 4029
7438 11:45:41.425797 100 : 4252, 4030
7439 11:45:41.425870 104 : 4257, 3535
7440 11:45:41.425944 108 : 4366, 2
7441 11:45:41.426056 112 : 4250, 0
7442 11:45:41.426133 116 : 4252, 0
7443 11:45:41.426207 120 : 4361, 0
7444 11:45:41.426281 124 : 4365, 0
7445 11:45:41.426355 128 : 4252, 0
7446 11:45:41.426427 132 : 4253, 0
7447 11:45:41.426500 136 : 4252, 0
7448 11:45:41.426573 140 : 4255, 0
7449 11:45:41.426645 144 : 4363, 0
7450 11:45:41.426718 148 : 4255, 0
7451 11:45:41.426791 152 : 4365, 0
7452 11:45:41.426879 156 : 4253, 0
7453 11:45:41.426954 160 : 4255, 0
7454 11:45:41.427028 164 : 4255, 0
7455 11:45:41.427101 168 : 4360, 0
7456 11:45:41.427175 172 : 4252, 0
7457 11:45:41.427246 176 : 4250, 0
7458 11:45:41.427319 180 : 4257, 0
7459 11:45:41.427392 184 : 4252, 0
7460 11:45:41.427465 188 : 4252, 0
7461 11:45:41.427537 192 : 4257, 0
7462 11:45:41.427609 196 : 4255, 0
7463 11:45:41.427683 200 : 4252, 0
7464 11:45:41.427755 204 : 4368, 0
7465 11:45:41.427828 208 : 4363, 0
7466 11:45:41.427902 212 : 4363, 0
7467 11:45:41.427974 216 : 4368, 0
7468 11:45:41.428046 220 : 4360, 0
7469 11:45:41.428119 224 : 4365, 0
7470 11:45:41.428191 228 : 4368, 0
7471 11:45:41.428264 232 : 4255, 0
7472 11:45:41.428336 236 : 4253, 1368
7473 11:45:41.428611 240 : 4363, 4140
7474 11:45:41.428708 244 : 4254, 4029
7475 11:45:41.429327 248 : 4253, 4029
7476 11:45:41.429450 252 : 4252, 4029
7477 11:45:41.432503 256 : 4361, 4137
7478 11:45:41.432627 260 : 4252, 4026
7479 11:45:41.435816 264 : 4255, 4029
7480 11:45:41.435953 268 : 4255, 4029
7481 11:45:41.438930 272 : 4250, 4026
7482 11:45:41.439086 276 : 4250, 4027
7483 11:45:41.442694 280 : 4368, 4142
7484 11:45:41.442865 284 : 4255, 4029
7485 11:45:41.445850 288 : 4252, 4030
7486 11:45:41.446006 292 : 4253, 4029
7487 11:45:41.449075 296 : 4257, 4032
7488 11:45:41.449231 300 : 4255, 4029
7489 11:45:41.449354 304 : 4252, 4030
7490 11:45:41.452343 308 : 4253, 4029
7491 11:45:41.452499 312 : 4252, 4030
7492 11:45:41.455382 316 : 4368, 4142
7493 11:45:41.455538 320 : 4255, 4029
7494 11:45:41.458617 324 : 4365, 4140
7495 11:45:41.458772 328 : 4252, 4030
7496 11:45:41.461855 332 : 4255, 4029
7497 11:45:41.462019 336 : 4365, 4140
7498 11:45:41.465518 340 : 4252, 4029
7499 11:45:41.465677 344 : 4253, 4029
7500 11:45:41.468757 348 : 4257, 4032
7501 11:45:41.468961 352 : 4255, 4011
7502 11:45:41.472294 356 : 4365, 2928
7503 11:45:41.472453 360 : 4252, 0
7504 11:45:41.472578
7505 11:45:41.475445 MIOCK jitter meter ch=0
7506 11:45:41.475591
7507 11:45:41.478727 1T = (360-108) = 252 dly cells
7508 11:45:41.481726 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7509 11:45:41.481884 ==
7510 11:45:41.484868 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 11:45:41.491737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7512 11:45:41.491896 ==
7513 11:45:41.494898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7514 11:45:41.501849 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7515 11:45:41.504850 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7516 11:45:41.511690 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7517 11:45:41.519681 [CA 0] Center 44 (14~74) winsize 61
7518 11:45:41.522869 [CA 1] Center 43 (13~74) winsize 62
7519 11:45:41.525905 [CA 2] Center 39 (10~68) winsize 59
7520 11:45:41.529700 [CA 3] Center 38 (9~68) winsize 60
7521 11:45:41.533103 [CA 4] Center 36 (7~66) winsize 60
7522 11:45:41.536296 [CA 5] Center 36 (7~66) winsize 60
7523 11:45:41.536456
7524 11:45:41.539688 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7525 11:45:41.539900
7526 11:45:41.542873 [CATrainingPosCal] consider 1 rank data
7527 11:45:41.546356 u2DelayCellTimex100 = 258/100 ps
7528 11:45:41.552657 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7529 11:45:41.555993 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7530 11:45:41.559129 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7531 11:45:41.562400 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7532 11:45:41.565556 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7533 11:45:41.569317 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7534 11:45:41.569475
7535 11:45:41.572390 CA PerBit enable=1, Macro0, CA PI delay=36
7536 11:45:41.572602
7537 11:45:41.575506 [CBTSetCACLKResult] CA Dly = 36
7538 11:45:41.578807 CS Dly: 11 (0~42)
7539 11:45:41.582122 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7540 11:45:41.585421 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7541 11:45:41.585622 ==
7542 11:45:41.588547 Dram Type= 6, Freq= 0, CH_0, rank 1
7543 11:45:41.595551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 11:45:41.595709 ==
7545 11:45:41.598582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 11:45:41.604932 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 11:45:41.608610 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 11:45:41.614797 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 11:45:41.623362 [CA 0] Center 44 (14~75) winsize 62
7550 11:45:41.626465 [CA 1] Center 43 (13~74) winsize 62
7551 11:45:41.630077 [CA 2] Center 39 (10~69) winsize 60
7552 11:45:41.633076 [CA 3] Center 39 (10~69) winsize 60
7553 11:45:41.636211 [CA 4] Center 37 (8~67) winsize 60
7554 11:45:41.640197 [CA 5] Center 37 (7~67) winsize 61
7555 11:45:41.640609
7556 11:45:41.643133 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 11:45:41.643633
7558 11:45:41.649551 [CATrainingPosCal] consider 2 rank data
7559 11:45:41.650162 u2DelayCellTimex100 = 258/100 ps
7560 11:45:41.656647 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7561 11:45:41.659643 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7562 11:45:41.663149 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7563 11:45:41.666367 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7564 11:45:41.669602 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7565 11:45:41.672680 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7566 11:45:41.673192
7567 11:45:41.675978 CA PerBit enable=1, Macro0, CA PI delay=36
7568 11:45:41.679073
7569 11:45:41.679519 [CBTSetCACLKResult] CA Dly = 36
7570 11:45:41.682348 CS Dly: 11 (0~43)
7571 11:45:41.686238 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 11:45:41.689370 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 11:45:41.692510
7574 11:45:41.695490 ----->DramcWriteLeveling(PI) begin...
7575 11:45:41.695985 ==
7576 11:45:41.699313 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 11:45:41.702526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 11:45:41.703088 ==
7579 11:45:41.705651 Write leveling (Byte 0): 36 => 36
7580 11:45:41.708835 Write leveling (Byte 1): 31 => 31
7581 11:45:41.711901 DramcWriteLeveling(PI) end<-----
7582 11:45:41.712410
7583 11:45:41.712945 ==
7584 11:45:41.715079 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 11:45:41.718808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 11:45:41.719264 ==
7587 11:45:41.721658 [Gating] SW mode calibration
7588 11:45:41.728362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7589 11:45:41.734721 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7590 11:45:41.738505 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 11:45:41.741558 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 11:45:41.748002 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 11:45:41.751694 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 11:45:41.754802 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7595 11:45:41.761729 1 4 20 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
7596 11:45:41.764244 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7597 11:45:41.768119 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 11:45:41.774245 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7599 11:45:41.777980 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7600 11:45:41.780957 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7601 11:45:41.787710 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7602 11:45:41.790952 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7603 11:45:41.794180 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7604 11:45:41.800516 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7605 11:45:41.804217 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7606 11:45:41.807439 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 11:45:41.813703 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 11:45:41.817039 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 11:45:41.820238 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7610 11:45:41.827006 1 6 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7611 11:45:41.830203 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7612 11:45:41.833316 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7613 11:45:41.839917 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 11:45:41.843143 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 11:45:41.849848 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7616 11:45:41.852999 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7617 11:45:41.856573 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7618 11:45:41.863458 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7619 11:45:41.866684 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7620 11:45:41.869988 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7621 11:45:41.876293 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7622 11:45:41.880262 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 11:45:41.883233 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 11:45:41.889456 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 11:45:41.892847 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 11:45:41.896063 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 11:45:41.902404 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 11:45:41.906135 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 11:45:41.909349 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 11:45:41.915994 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 11:45:41.919234 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 11:45:41.922390 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 11:45:41.929000 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 11:45:41.932821 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7635 11:45:41.935749 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 11:45:41.938718 Total UI for P1: 0, mck2ui 16
7637 11:45:41.942276 best dqsien dly found for B0: ( 1, 9, 16)
7638 11:45:41.945420 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7639 11:45:41.952099 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 11:45:41.955777 Total UI for P1: 0, mck2ui 16
7641 11:45:41.958489 best dqsien dly found for B1: ( 1, 9, 22)
7642 11:45:41.961849 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7643 11:45:41.965511 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7644 11:45:41.965799
7645 11:45:41.968614 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7646 11:45:41.972184 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7647 11:45:41.975379 [Gating] SW calibration Done
7648 11:45:41.975600 ==
7649 11:45:41.978350 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 11:45:41.982326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 11:45:41.982686 ==
7652 11:45:41.985428 RX Vref Scan: 0
7653 11:45:41.985735
7654 11:45:41.988605 RX Vref 0 -> 0, step: 1
7655 11:45:41.988924
7656 11:45:41.989180 RX Delay 0 -> 252, step: 8
7657 11:45:41.995080 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7658 11:45:41.998352 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7659 11:45:42.001550 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7660 11:45:42.004801 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7661 11:45:42.011771 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7662 11:45:42.014860 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7663 11:45:42.017982 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7664 11:45:42.021150 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7665 11:45:42.024599 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7666 11:45:42.031530 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7667 11:45:42.034670 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7668 11:45:42.038012 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7669 11:45:42.041242 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7670 11:45:42.044188 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7671 11:45:42.051069 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7672 11:45:42.054217 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7673 11:45:42.054445 ==
7674 11:45:42.057794 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 11:45:42.060972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 11:45:42.061397 ==
7677 11:45:42.064700 DQS Delay:
7678 11:45:42.065122 DQS0 = 0, DQS1 = 0
7679 11:45:42.067702 DQM Delay:
7680 11:45:42.068124 DQM0 = 127, DQM1 = 123
7681 11:45:42.068548 DQ Delay:
7682 11:45:42.070772 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7683 11:45:42.077513 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7684 11:45:42.081263 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7685 11:45:42.084311 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7686 11:45:42.084734
7687 11:45:42.085240
7688 11:45:42.085733 ==
7689 11:45:42.087471 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 11:45:42.090667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 11:45:42.091137 ==
7692 11:45:42.091562
7693 11:45:42.091964
7694 11:45:42.094236 TX Vref Scan disable
7695 11:45:42.097404 == TX Byte 0 ==
7696 11:45:42.100693 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7697 11:45:42.103920 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7698 11:45:42.107679 == TX Byte 1 ==
7699 11:45:42.110787 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7700 11:45:42.113843 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7701 11:45:42.114385 ==
7702 11:45:42.116929 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 11:45:42.120775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 11:45:42.123871 ==
7705 11:45:42.135424
7706 11:45:42.138583 TX Vref early break, caculate TX vref
7707 11:45:42.142377 TX Vref=16, minBit 8, minWin=22, winSum=374
7708 11:45:42.145564 TX Vref=18, minBit 0, minWin=23, winSum=384
7709 11:45:42.148562 TX Vref=20, minBit 0, minWin=24, winSum=395
7710 11:45:42.152056 TX Vref=22, minBit 4, minWin=24, winSum=406
7711 11:45:42.155070 TX Vref=24, minBit 4, minWin=24, winSum=410
7712 11:45:42.162080 TX Vref=26, minBit 0, minWin=25, winSum=421
7713 11:45:42.165145 TX Vref=28, minBit 8, minWin=25, winSum=424
7714 11:45:42.168659 TX Vref=30, minBit 4, minWin=25, winSum=417
7715 11:45:42.171926 TX Vref=32, minBit 9, minWin=24, winSum=411
7716 11:45:42.174867 TX Vref=34, minBit 8, minWin=23, winSum=397
7717 11:45:42.181723 [TxChooseVref] Worse bit 8, Min win 25, Win sum 424, Final Vref 28
7718 11:45:42.182253
7719 11:45:42.184830 Final TX Range 0 Vref 28
7720 11:45:42.185409
7721 11:45:42.185887 ==
7722 11:45:42.187853 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 11:45:42.191565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 11:45:42.192104 ==
7725 11:45:42.192571
7726 11:45:42.192908
7727 11:45:42.194582 TX Vref Scan disable
7728 11:45:42.201285 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7729 11:45:42.201696 == TX Byte 0 ==
7730 11:45:42.204241 u2DelayCellOfst[0]=15 cells (4 PI)
7731 11:45:42.208097 u2DelayCellOfst[1]=18 cells (5 PI)
7732 11:45:42.211330 u2DelayCellOfst[2]=11 cells (3 PI)
7733 11:45:42.214659 u2DelayCellOfst[3]=15 cells (4 PI)
7734 11:45:42.217911 u2DelayCellOfst[4]=11 cells (3 PI)
7735 11:45:42.221136 u2DelayCellOfst[5]=0 cells (0 PI)
7736 11:45:42.224274 u2DelayCellOfst[6]=18 cells (5 PI)
7737 11:45:42.227406 u2DelayCellOfst[7]=18 cells (5 PI)
7738 11:45:42.231116 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7739 11:45:42.234078 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7740 11:45:42.237270 == TX Byte 1 ==
7741 11:45:42.240359 u2DelayCellOfst[8]=0 cells (0 PI)
7742 11:45:42.244181 u2DelayCellOfst[9]=0 cells (0 PI)
7743 11:45:42.247453 u2DelayCellOfst[10]=7 cells (2 PI)
7744 11:45:42.250745 u2DelayCellOfst[11]=3 cells (1 PI)
7745 11:45:42.253981 u2DelayCellOfst[12]=15 cells (4 PI)
7746 11:45:42.256981 u2DelayCellOfst[13]=11 cells (3 PI)
7747 11:45:42.257388 u2DelayCellOfst[14]=18 cells (5 PI)
7748 11:45:42.260406 u2DelayCellOfst[15]=11 cells (3 PI)
7749 11:45:42.267118 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7750 11:45:42.270198 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7751 11:45:42.273450 DramC Write-DBI on
7752 11:45:42.273862 ==
7753 11:45:42.277286 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 11:45:42.280428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 11:45:42.280847 ==
7756 11:45:42.281173
7757 11:45:42.281469
7758 11:45:42.283696 TX Vref Scan disable
7759 11:45:42.284113 == TX Byte 0 ==
7760 11:45:42.290032 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7761 11:45:42.290479 == TX Byte 1 ==
7762 11:45:42.293055 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7763 11:45:42.296789 DramC Write-DBI off
7764 11:45:42.297216
7765 11:45:42.297732 [DATLAT]
7766 11:45:42.299969 Freq=1600, CH0 RK0
7767 11:45:42.300379
7768 11:45:42.300701 DATLAT Default: 0xf
7769 11:45:42.302895 0, 0xFFFF, sum = 0
7770 11:45:42.305933 1, 0xFFFF, sum = 0
7771 11:45:42.306318 2, 0xFFFF, sum = 0
7772 11:45:42.309831 3, 0xFFFF, sum = 0
7773 11:45:42.310250 4, 0xFFFF, sum = 0
7774 11:45:42.312946 5, 0xFFFF, sum = 0
7775 11:45:42.313363 6, 0xFFFF, sum = 0
7776 11:45:42.316114 7, 0xFFFF, sum = 0
7777 11:45:42.316661 8, 0xFFFF, sum = 0
7778 11:45:42.319378 9, 0xFFFF, sum = 0
7779 11:45:42.319809 10, 0xFFFF, sum = 0
7780 11:45:42.322511 11, 0xFFFF, sum = 0
7781 11:45:42.322977 12, 0xFFFF, sum = 0
7782 11:45:42.326057 13, 0xFFFF, sum = 0
7783 11:45:42.326648 14, 0x0, sum = 1
7784 11:45:42.329610 15, 0x0, sum = 2
7785 11:45:42.330084 16, 0x0, sum = 3
7786 11:45:42.332906 17, 0x0, sum = 4
7787 11:45:42.333335 best_step = 15
7788 11:45:42.333653
7789 11:45:42.333950 ==
7790 11:45:42.336062 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 11:45:42.342725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 11:45:42.343180 ==
7793 11:45:42.343507 RX Vref Scan: 1
7794 11:45:42.343806
7795 11:45:42.345684 Set Vref Range= 24 -> 127
7796 11:45:42.346091
7797 11:45:42.348761 RX Vref 24 -> 127, step: 1
7798 11:45:42.349168
7799 11:45:42.352737 RX Delay 11 -> 252, step: 4
7800 11:45:42.353143
7801 11:45:42.355409 Set Vref, RX VrefLevel [Byte0]: 24
7802 11:45:42.358662 [Byte1]: 24
7803 11:45:42.359119
7804 11:45:42.362440 Set Vref, RX VrefLevel [Byte0]: 25
7805 11:45:42.365062 [Byte1]: 25
7806 11:45:42.365469
7807 11:45:42.368727 Set Vref, RX VrefLevel [Byte0]: 26
7808 11:45:42.372118 [Byte1]: 26
7809 11:45:42.375626
7810 11:45:42.376027 Set Vref, RX VrefLevel [Byte0]: 27
7811 11:45:42.378638 [Byte1]: 27
7812 11:45:42.382898
7813 11:45:42.383304 Set Vref, RX VrefLevel [Byte0]: 28
7814 11:45:42.386410 [Byte1]: 28
7815 11:45:42.390984
7816 11:45:42.391489 Set Vref, RX VrefLevel [Byte0]: 29
7817 11:45:42.393816 [Byte1]: 29
7818 11:45:42.398625
7819 11:45:42.399185 Set Vref, RX VrefLevel [Byte0]: 30
7820 11:45:42.401901 [Byte1]: 30
7821 11:45:42.406042
7822 11:45:42.406451 Set Vref, RX VrefLevel [Byte0]: 31
7823 11:45:42.408973 [Byte1]: 31
7824 11:45:42.413659
7825 11:45:42.414170 Set Vref, RX VrefLevel [Byte0]: 32
7826 11:45:42.416595 [Byte1]: 32
7827 11:45:42.421512
7828 11:45:42.421960 Set Vref, RX VrefLevel [Byte0]: 33
7829 11:45:42.424811 [Byte1]: 33
7830 11:45:42.429079
7831 11:45:42.429529 Set Vref, RX VrefLevel [Byte0]: 34
7832 11:45:42.432175 [Byte1]: 34
7833 11:45:42.436705
7834 11:45:42.437295 Set Vref, RX VrefLevel [Byte0]: 35
7835 11:45:42.439520 [Byte1]: 35
7836 11:45:42.443775
7837 11:45:42.444233 Set Vref, RX VrefLevel [Byte0]: 36
7838 11:45:42.447326 [Byte1]: 36
7839 11:45:42.451932
7840 11:45:42.452512 Set Vref, RX VrefLevel [Byte0]: 37
7841 11:45:42.454716 [Byte1]: 37
7842 11:45:42.459586
7843 11:45:42.460042 Set Vref, RX VrefLevel [Byte0]: 38
7844 11:45:42.462555 [Byte1]: 38
7845 11:45:42.467154
7846 11:45:42.467710 Set Vref, RX VrefLevel [Byte0]: 39
7847 11:45:42.470117 [Byte1]: 39
7848 11:45:42.474821
7849 11:45:42.475306 Set Vref, RX VrefLevel [Byte0]: 40
7850 11:45:42.477616 [Byte1]: 40
7851 11:45:42.482693
7852 11:45:42.483302 Set Vref, RX VrefLevel [Byte0]: 41
7853 11:45:42.485211 [Byte1]: 41
7854 11:45:42.490141
7855 11:45:42.490704 Set Vref, RX VrefLevel [Byte0]: 42
7856 11:45:42.492930 [Byte1]: 42
7857 11:45:42.497239
7858 11:45:42.497697 Set Vref, RX VrefLevel [Byte0]: 43
7859 11:45:42.500944 [Byte1]: 43
7860 11:45:42.504918
7861 11:45:42.505377 Set Vref, RX VrefLevel [Byte0]: 44
7862 11:45:42.507886 [Byte1]: 44
7863 11:45:42.512444
7864 11:45:42.512900 Set Vref, RX VrefLevel [Byte0]: 45
7865 11:45:42.515769 [Byte1]: 45
7866 11:45:42.520039
7867 11:45:42.520494 Set Vref, RX VrefLevel [Byte0]: 46
7868 11:45:42.523235 [Byte1]: 46
7869 11:45:42.527651
7870 11:45:42.528108 Set Vref, RX VrefLevel [Byte0]: 47
7871 11:45:42.530923 [Byte1]: 47
7872 11:45:42.535170
7873 11:45:42.535628 Set Vref, RX VrefLevel [Byte0]: 48
7874 11:45:42.538950 [Byte1]: 48
7875 11:45:42.543173
7876 11:45:42.543623 Set Vref, RX VrefLevel [Byte0]: 49
7877 11:45:42.546138 [Byte1]: 49
7878 11:45:42.550680
7879 11:45:42.551188 Set Vref, RX VrefLevel [Byte0]: 50
7880 11:45:42.553682 [Byte1]: 50
7881 11:45:42.557896
7882 11:45:42.558353 Set Vref, RX VrefLevel [Byte0]: 51
7883 11:45:42.561648 [Byte1]: 51
7884 11:45:42.566010
7885 11:45:42.566465 Set Vref, RX VrefLevel [Byte0]: 52
7886 11:45:42.569232 [Byte1]: 52
7887 11:45:42.573125
7888 11:45:42.573540 Set Vref, RX VrefLevel [Byte0]: 53
7889 11:45:42.576895 [Byte1]: 53
7890 11:45:42.581073
7891 11:45:42.581557 Set Vref, RX VrefLevel [Byte0]: 54
7892 11:45:42.583925 [Byte1]: 54
7893 11:45:42.588333
7894 11:45:42.588752 Set Vref, RX VrefLevel [Byte0]: 55
7895 11:45:42.592286 [Byte1]: 55
7896 11:45:42.596274
7897 11:45:42.596688 Set Vref, RX VrefLevel [Byte0]: 56
7898 11:45:42.599200 [Byte1]: 56
7899 11:45:42.603650
7900 11:45:42.606714 Set Vref, RX VrefLevel [Byte0]: 57
7901 11:45:42.610436 [Byte1]: 57
7902 11:45:42.611084
7903 11:45:42.613659 Set Vref, RX VrefLevel [Byte0]: 58
7904 11:45:42.616857 [Byte1]: 58
7905 11:45:42.617285
7906 11:45:42.619900 Set Vref, RX VrefLevel [Byte0]: 59
7907 11:45:42.623079 [Byte1]: 59
7908 11:45:42.626436
7909 11:45:42.627046 Set Vref, RX VrefLevel [Byte0]: 60
7910 11:45:42.629693 [Byte1]: 60
7911 11:45:42.634235
7912 11:45:42.634794 Set Vref, RX VrefLevel [Byte0]: 61
7913 11:45:42.637675 [Byte1]: 61
7914 11:45:42.641491
7915 11:45:42.642127 Set Vref, RX VrefLevel [Byte0]: 62
7916 11:45:42.644854 [Byte1]: 62
7917 11:45:42.649443
7918 11:45:42.649939 Set Vref, RX VrefLevel [Byte0]: 63
7919 11:45:42.652771 [Byte1]: 63
7920 11:45:42.657112
7921 11:45:42.657527 Set Vref, RX VrefLevel [Byte0]: 64
7922 11:45:42.660191 [Byte1]: 64
7923 11:45:42.664573
7924 11:45:42.665119 Set Vref, RX VrefLevel [Byte0]: 65
7925 11:45:42.668132 [Byte1]: 65
7926 11:45:42.672025
7927 11:45:42.672482 Set Vref, RX VrefLevel [Byte0]: 66
7928 11:45:42.675656 [Byte1]: 66
7929 11:45:42.680085
7930 11:45:42.680495 Set Vref, RX VrefLevel [Byte0]: 67
7931 11:45:42.683275 [Byte1]: 67
7932 11:45:42.687479
7933 11:45:42.687997 Set Vref, RX VrefLevel [Byte0]: 68
7934 11:45:42.690928 [Byte1]: 68
7935 11:45:42.695330
7936 11:45:42.695770 Set Vref, RX VrefLevel [Byte0]: 69
7937 11:45:42.698116 [Byte1]: 69
7938 11:45:42.702578
7939 11:45:42.703027 Set Vref, RX VrefLevel [Byte0]: 70
7940 11:45:42.706051 [Byte1]: 70
7941 11:45:42.710278
7942 11:45:42.710689 Set Vref, RX VrefLevel [Byte0]: 71
7943 11:45:42.713376 [Byte1]: 71
7944 11:45:42.718260
7945 11:45:42.718864 Set Vref, RX VrefLevel [Byte0]: 72
7946 11:45:42.721254 [Byte1]: 72
7947 11:45:42.725466
7948 11:45:42.725851 Set Vref, RX VrefLevel [Byte0]: 73
7949 11:45:42.728770 [Byte1]: 73
7950 11:45:42.732936
7951 11:45:42.733451 Set Vref, RX VrefLevel [Byte0]: 74
7952 11:45:42.736642 [Byte1]: 74
7953 11:45:42.741069
7954 11:45:42.741480 Set Vref, RX VrefLevel [Byte0]: 75
7955 11:45:42.744191 [Byte1]: 75
7956 11:45:42.748279
7957 11:45:42.748663 Final RX Vref Byte 0 = 63 to rank0
7958 11:45:42.752362 Final RX Vref Byte 1 = 61 to rank0
7959 11:45:42.755517 Final RX Vref Byte 0 = 63 to rank1
7960 11:45:42.758459 Final RX Vref Byte 1 = 61 to rank1==
7961 11:45:42.761636 Dram Type= 6, Freq= 0, CH_0, rank 0
7962 11:45:42.768362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7963 11:45:42.768874 ==
7964 11:45:42.769311 DQS Delay:
7965 11:45:42.771415 DQS0 = 0, DQS1 = 0
7966 11:45:42.771827 DQM Delay:
7967 11:45:42.772149 DQM0 = 126, DQM1 = 119
7968 11:45:42.774993 DQ Delay:
7969 11:45:42.777887 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7970 11:45:42.781528 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7971 11:45:42.784927 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7972 11:45:42.787952 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =126
7973 11:45:42.788360
7974 11:45:42.788681
7975 11:45:42.789024
7976 11:45:42.791478 [DramC_TX_OE_Calibration] TA2
7977 11:45:42.794450 Original DQ_B0 (3 6) =30, OEN = 27
7978 11:45:42.798200 Original DQ_B1 (3 6) =30, OEN = 27
7979 11:45:42.801075 24, 0x0, End_B0=24 End_B1=24
7980 11:45:42.804222 25, 0x0, End_B0=25 End_B1=25
7981 11:45:42.804680 26, 0x0, End_B0=26 End_B1=26
7982 11:45:42.807894 27, 0x0, End_B0=27 End_B1=27
7983 11:45:42.811040 28, 0x0, End_B0=28 End_B1=28
7984 11:45:42.814097 29, 0x0, End_B0=29 End_B1=29
7985 11:45:42.814559 30, 0x0, End_B0=30 End_B1=30
7986 11:45:42.817833 31, 0x4141, End_B0=30 End_B1=30
7987 11:45:42.821031 Byte0 end_step=30 best_step=27
7988 11:45:42.824231 Byte1 end_step=30 best_step=27
7989 11:45:42.827316 Byte0 TX OE(2T, 0.5T) = (3, 3)
7990 11:45:42.831000 Byte1 TX OE(2T, 0.5T) = (3, 3)
7991 11:45:42.831421
7992 11:45:42.831835
7993 11:45:42.837719 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
7994 11:45:42.840938 CH0 RK0: MR19=303, MR18=1212
7995 11:45:42.847269 CH0_RK0: MR19=0x303, MR18=0x1212, DQSOSC=400, MR23=63, INC=23, DEC=15
7996 11:45:42.847699
7997 11:45:42.850690 ----->DramcWriteLeveling(PI) begin...
7998 11:45:42.851113 ==
7999 11:45:42.853882 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 11:45:42.857108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 11:45:42.857416 ==
8002 11:45:42.860275 Write leveling (Byte 0): 34 => 34
8003 11:45:42.863597 Write leveling (Byte 1): 30 => 30
8004 11:45:42.866869 DramcWriteLeveling(PI) end<-----
8005 11:45:42.867175
8006 11:45:42.867480 ==
8007 11:45:42.870221 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 11:45:42.877016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 11:45:42.877326 ==
8010 11:45:42.877631 [Gating] SW mode calibration
8011 11:45:42.886957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8012 11:45:42.889800 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8013 11:45:42.893606 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 11:45:42.899894 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8015 11:45:42.903249 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 11:45:42.906358 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8017 11:45:42.913117 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8018 11:45:42.916101 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8019 11:45:42.919776 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 11:45:42.926441 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 11:45:42.929614 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 11:45:42.932667 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 11:45:42.939150 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8024 11:45:42.942911 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8025 11:45:42.946263 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8026 11:45:42.952629 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8027 11:45:42.955753 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 11:45:42.959020 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 11:45:42.965919 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 11:45:42.969213 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 11:45:42.972486 1 6 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
8032 11:45:42.978855 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8033 11:45:42.982615 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8034 11:45:42.985630 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 11:45:42.992048 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 11:45:42.995806 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 11:45:42.998899 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 11:45:43.005657 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 11:45:43.008753 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 11:45:43.012367 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8041 11:45:43.019102 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 11:45:43.022048 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8043 11:45:43.025630 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 11:45:43.032081 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 11:45:43.035012 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 11:45:43.038686 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 11:45:43.044860 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:45:43.048758 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 11:45:43.051454 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:45:43.058233 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 11:45:43.061341 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 11:45:43.064715 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 11:45:43.071531 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 11:45:43.074927 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 11:45:43.077914 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8056 11:45:43.084602 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8057 11:45:43.087593 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 11:45:43.090909 Total UI for P1: 0, mck2ui 16
8059 11:45:43.094407 best dqsien dly found for B0: ( 1, 9, 10)
8060 11:45:43.097347 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 11:45:43.101314 Total UI for P1: 0, mck2ui 16
8062 11:45:43.104326 best dqsien dly found for B1: ( 1, 9, 16)
8063 11:45:43.107325 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8064 11:45:43.114163 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8065 11:45:43.114707
8066 11:45:43.117205 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8067 11:45:43.120778 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8068 11:45:43.123886 [Gating] SW calibration Done
8069 11:45:43.124528 ==
8070 11:45:43.126972 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 11:45:43.130700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 11:45:43.131244 ==
8073 11:45:43.133787 RX Vref Scan: 0
8074 11:45:43.134365
8075 11:45:43.134892 RX Vref 0 -> 0, step: 1
8076 11:45:43.135390
8077 11:45:43.136783 RX Delay 0 -> 252, step: 8
8078 11:45:43.140533 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8079 11:45:43.146692 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8080 11:45:43.150662 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8081 11:45:43.153831 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8082 11:45:43.156923 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8083 11:45:43.160082 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8084 11:45:43.166825 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8085 11:45:43.170142 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8086 11:45:43.173812 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8087 11:45:43.176419 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8088 11:45:43.180086 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8089 11:45:43.186358 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8090 11:45:43.190069 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8091 11:45:43.193127 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8092 11:45:43.197003 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8093 11:45:43.203455 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8094 11:45:43.203878 ==
8095 11:45:43.206514 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 11:45:43.209598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 11:45:43.209914 ==
8098 11:45:43.210154 DQS Delay:
8099 11:45:43.212849 DQS0 = 0, DQS1 = 0
8100 11:45:43.213143 DQM Delay:
8101 11:45:43.216276 DQM0 = 128, DQM1 = 122
8102 11:45:43.216499 DQ Delay:
8103 11:45:43.219205 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8104 11:45:43.222655 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8105 11:45:43.226028 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8106 11:45:43.229407 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8107 11:45:43.229536
8108 11:45:43.229637
8109 11:45:43.232513 ==
8110 11:45:43.235544 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 11:45:43.239136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 11:45:43.239237 ==
8113 11:45:43.239317
8114 11:45:43.239390
8115 11:45:43.242106 TX Vref Scan disable
8116 11:45:43.242207 == TX Byte 0 ==
8117 11:45:43.248617 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8118 11:45:43.252318 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8119 11:45:43.252410 == TX Byte 1 ==
8120 11:45:43.259012 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8121 11:45:43.262071 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8122 11:45:43.262190 ==
8123 11:45:43.265384 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 11:45:43.268401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 11:45:43.268541 ==
8126 11:45:43.283972
8127 11:45:43.286973 TX Vref early break, caculate TX vref
8128 11:45:43.290949 TX Vref=16, minBit 0, minWin=23, winSum=373
8129 11:45:43.293943 TX Vref=18, minBit 0, minWin=22, winSum=376
8130 11:45:43.297016 TX Vref=20, minBit 1, minWin=23, winSum=390
8131 11:45:43.300546 TX Vref=22, minBit 0, minWin=24, winSum=403
8132 11:45:43.303725 TX Vref=24, minBit 0, minWin=24, winSum=403
8133 11:45:43.310255 TX Vref=26, minBit 2, minWin=25, winSum=416
8134 11:45:43.313682 TX Vref=28, minBit 2, minWin=25, winSum=415
8135 11:45:43.317163 TX Vref=30, minBit 0, minWin=25, winSum=414
8136 11:45:43.320198 TX Vref=32, minBit 8, minWin=24, winSum=406
8137 11:45:43.323330 TX Vref=34, minBit 4, minWin=24, winSum=398
8138 11:45:43.329706 TX Vref=36, minBit 7, minWin=23, winSum=388
8139 11:45:43.333475 [TxChooseVref] Worse bit 2, Min win 25, Win sum 416, Final Vref 26
8140 11:45:43.334022
8141 11:45:43.336257 Final TX Range 0 Vref 26
8142 11:45:43.336777
8143 11:45:43.337309 ==
8144 11:45:43.339750 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 11:45:43.343338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 11:45:43.346399 ==
8147 11:45:43.347035
8148 11:45:43.347635
8149 11:45:43.348000 TX Vref Scan disable
8150 11:45:43.353230 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8151 11:45:43.353791 == TX Byte 0 ==
8152 11:45:43.356716 u2DelayCellOfst[0]=15 cells (4 PI)
8153 11:45:43.359665 u2DelayCellOfst[1]=22 cells (6 PI)
8154 11:45:43.362634 u2DelayCellOfst[2]=15 cells (4 PI)
8155 11:45:43.366628 u2DelayCellOfst[3]=15 cells (4 PI)
8156 11:45:43.369738 u2DelayCellOfst[4]=11 cells (3 PI)
8157 11:45:43.372903 u2DelayCellOfst[5]=0 cells (0 PI)
8158 11:45:43.376155 u2DelayCellOfst[6]=22 cells (6 PI)
8159 11:45:43.379775 u2DelayCellOfst[7]=22 cells (6 PI)
8160 11:45:43.383092 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8161 11:45:43.389259 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8162 11:45:43.389797 == TX Byte 1 ==
8163 11:45:43.392538 u2DelayCellOfst[8]=0 cells (0 PI)
8164 11:45:43.395620 u2DelayCellOfst[9]=0 cells (0 PI)
8165 11:45:43.398898 u2DelayCellOfst[10]=3 cells (1 PI)
8166 11:45:43.402940 u2DelayCellOfst[11]=3 cells (1 PI)
8167 11:45:43.405592 u2DelayCellOfst[12]=11 cells (3 PI)
8168 11:45:43.409143 u2DelayCellOfst[13]=11 cells (3 PI)
8169 11:45:43.412567 u2DelayCellOfst[14]=15 cells (4 PI)
8170 11:45:43.415267 u2DelayCellOfst[15]=11 cells (3 PI)
8171 11:45:43.419116 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8172 11:45:43.422119 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8173 11:45:43.425259 DramC Write-DBI on
8174 11:45:43.425712 ==
8175 11:45:43.428355 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 11:45:43.431886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 11:45:43.432541 ==
8178 11:45:43.433140
8179 11:45:43.433724
8180 11:45:43.434773 TX Vref Scan disable
8181 11:45:43.438491 == TX Byte 0 ==
8182 11:45:43.441575 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8183 11:45:43.442027 == TX Byte 1 ==
8184 11:45:43.448058 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8185 11:45:43.448508 DramC Write-DBI off
8186 11:45:43.448864
8187 11:45:43.451871 [DATLAT]
8188 11:45:43.452340 Freq=1600, CH0 RK1
8189 11:45:43.452702
8190 11:45:43.455166 DATLAT Default: 0xf
8191 11:45:43.455629 0, 0xFFFF, sum = 0
8192 11:45:43.458091 1, 0xFFFF, sum = 0
8193 11:45:43.458516 2, 0xFFFF, sum = 0
8194 11:45:43.461526 3, 0xFFFF, sum = 0
8195 11:45:43.461959 4, 0xFFFF, sum = 0
8196 11:45:43.464422 5, 0xFFFF, sum = 0
8197 11:45:43.464744 6, 0xFFFF, sum = 0
8198 11:45:43.467909 7, 0xFFFF, sum = 0
8199 11:45:43.468321 8, 0xFFFF, sum = 0
8200 11:45:43.471200 9, 0xFFFF, sum = 0
8201 11:45:43.471519 10, 0xFFFF, sum = 0
8202 11:45:43.474716 11, 0xFFFF, sum = 0
8203 11:45:43.477869 12, 0xFFFF, sum = 0
8204 11:45:43.478189 13, 0xCFFF, sum = 0
8205 11:45:43.481171 14, 0x0, sum = 1
8206 11:45:43.481490 15, 0x0, sum = 2
8207 11:45:43.481741 16, 0x0, sum = 3
8208 11:45:43.484310 17, 0x0, sum = 4
8209 11:45:43.484628 best_step = 15
8210 11:45:43.484874
8211 11:45:43.488089 ==
8212 11:45:43.488403 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 11:45:43.494519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 11:45:43.494856 ==
8215 11:45:43.495109 RX Vref Scan: 0
8216 11:45:43.495338
8217 11:45:43.497634 RX Vref 0 -> 0, step: 1
8218 11:45:43.498067
8219 11:45:43.500850 RX Delay 3 -> 252, step: 4
8220 11:45:43.504484 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8221 11:45:43.507653 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8222 11:45:43.513876 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8223 11:45:43.517173 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8224 11:45:43.520818 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8225 11:45:43.523770 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8226 11:45:43.526724 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8227 11:45:43.533429 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8228 11:45:43.536590 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8229 11:45:43.540079 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8230 11:45:43.543589 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8231 11:45:43.550292 iDelay=191, Bit 11, Center 110 (55 ~ 166) 112
8232 11:45:43.553420 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8233 11:45:43.556497 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8234 11:45:43.559836 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8235 11:45:43.563266 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8236 11:45:43.566231 ==
8237 11:45:43.569768 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 11:45:43.573125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 11:45:43.573271 ==
8240 11:45:43.573408 DQS Delay:
8241 11:45:43.576208 DQS0 = 0, DQS1 = 0
8242 11:45:43.576329 DQM Delay:
8243 11:45:43.579457 DQM0 = 124, DQM1 = 117
8244 11:45:43.579587 DQ Delay:
8245 11:45:43.582604 DQ0 =124, DQ1 =124, DQ2 =120, DQ3 =122
8246 11:45:43.586440 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8247 11:45:43.589698 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =110
8248 11:45:43.592994 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8249 11:45:43.593208
8250 11:45:43.593430
8251 11:45:43.596317
8252 11:45:43.596546 [DramC_TX_OE_Calibration] TA2
8253 11:45:43.599577 Original DQ_B0 (3 6) =30, OEN = 27
8254 11:45:43.602665 Original DQ_B1 (3 6) =30, OEN = 27
8255 11:45:43.605953 24, 0x0, End_B0=24 End_B1=24
8256 11:45:43.609194 25, 0x0, End_B0=25 End_B1=25
8257 11:45:43.613052 26, 0x0, End_B0=26 End_B1=26
8258 11:45:43.613336 27, 0x0, End_B0=27 End_B1=27
8259 11:45:43.615659 28, 0x0, End_B0=28 End_B1=28
8260 11:45:43.619382 29, 0x0, End_B0=29 End_B1=29
8261 11:45:43.622711 30, 0x0, End_B0=30 End_B1=30
8262 11:45:43.625836 31, 0x5151, End_B0=30 End_B1=30
8263 11:45:43.626230 Byte0 end_step=30 best_step=27
8264 11:45:43.628816 Byte1 end_step=30 best_step=27
8265 11:45:43.632589 Byte0 TX OE(2T, 0.5T) = (3, 3)
8266 11:45:43.636098 Byte1 TX OE(2T, 0.5T) = (3, 3)
8267 11:45:43.636481
8268 11:45:43.636818
8269 11:45:43.645110 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8270 11:45:43.645218 CH0 RK1: MR19=303, MR18=210E
8271 11:45:43.651797 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8272 11:45:43.654949 [RxdqsGatingPostProcess] freq 1600
8273 11:45:43.661609 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8274 11:45:43.665341 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 11:45:43.668615 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 11:45:43.671657 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 11:45:43.674812 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 11:45:43.674903 best DQS0 dly(2T, 0.5T) = (1, 1)
8279 11:45:43.678159 best DQS1 dly(2T, 0.5T) = (1, 1)
8280 11:45:43.681373 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8281 11:45:43.685038 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8282 11:45:43.688238 Pre-setting of DQS Precalculation
8283 11:45:43.694663 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8284 11:45:43.694772 ==
8285 11:45:43.697981 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 11:45:43.701169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 11:45:43.701252 ==
8288 11:45:43.708256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 11:45:43.711498 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 11:45:43.714764 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 11:45:43.721162 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 11:45:43.729872 [CA 0] Center 42 (13~71) winsize 59
8293 11:45:43.733573 [CA 1] Center 42 (13~72) winsize 60
8294 11:45:43.736683 [CA 2] Center 37 (9~66) winsize 58
8295 11:45:43.739813 [CA 3] Center 37 (8~66) winsize 59
8296 11:45:43.742895 [CA 4] Center 37 (8~66) winsize 59
8297 11:45:43.746776 [CA 5] Center 37 (8~66) winsize 59
8298 11:45:43.746879
8299 11:45:43.749981 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8300 11:45:43.750101
8301 11:45:43.753163 [CATrainingPosCal] consider 1 rank data
8302 11:45:43.756074 u2DelayCellTimex100 = 258/100 ps
8303 11:45:43.762772 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8304 11:45:43.766371 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8305 11:45:43.769374 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8306 11:45:43.772500 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8307 11:45:43.776255 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
8308 11:45:43.779171 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8309 11:45:43.779270
8310 11:45:43.782645 CA PerBit enable=1, Macro0, CA PI delay=37
8311 11:45:43.782751
8312 11:45:43.785790 [CBTSetCACLKResult] CA Dly = 37
8313 11:45:43.789315 CS Dly: 9 (0~40)
8314 11:45:43.792330 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 11:45:43.795768 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 11:45:43.795867 ==
8317 11:45:43.799087 Dram Type= 6, Freq= 0, CH_1, rank 1
8318 11:45:43.805443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 11:45:43.805542 ==
8320 11:45:43.809173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8321 11:45:43.815537 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8322 11:45:43.818736 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8323 11:45:43.825165 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8324 11:45:43.833129 [CA 0] Center 42 (13~72) winsize 60
8325 11:45:43.836180 [CA 1] Center 42 (12~72) winsize 61
8326 11:45:43.839724 [CA 2] Center 38 (9~67) winsize 59
8327 11:45:43.842808 [CA 3] Center 36 (7~66) winsize 60
8328 11:45:43.846473 [CA 4] Center 38 (8~68) winsize 61
8329 11:45:43.849527 [CA 5] Center 37 (7~67) winsize 61
8330 11:45:43.849632
8331 11:45:43.852655 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8332 11:45:43.852752
8333 11:45:43.856486 [CATrainingPosCal] consider 2 rank data
8334 11:45:43.859500 u2DelayCellTimex100 = 258/100 ps
8335 11:45:43.865834 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8336 11:45:43.869509 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8337 11:45:43.872441 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8338 11:45:43.875935 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8339 11:45:43.879601 CA4 delay=37 (8~66),Diff = 0 PI (0 cell)
8340 11:45:43.882450 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8341 11:45:43.882545
8342 11:45:43.886004 CA PerBit enable=1, Macro0, CA PI delay=37
8343 11:45:43.886108
8344 11:45:43.889307 [CBTSetCACLKResult] CA Dly = 37
8345 11:45:43.892273 CS Dly: 11 (0~44)
8346 11:45:43.895842 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8347 11:45:43.899625 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8348 11:45:43.899730
8349 11:45:43.902606 ----->DramcWriteLeveling(PI) begin...
8350 11:45:43.902704 ==
8351 11:45:43.905586 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 11:45:43.912088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 11:45:43.912176 ==
8354 11:45:43.915737 Write leveling (Byte 0): 26 => 26
8355 11:45:43.918900 Write leveling (Byte 1): 28 => 28
8356 11:45:43.918972 DramcWriteLeveling(PI) end<-----
8357 11:45:43.922135
8358 11:45:43.922203 ==
8359 11:45:43.925237 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 11:45:43.928491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 11:45:43.928562 ==
8362 11:45:43.931646 [Gating] SW mode calibration
8363 11:45:43.938507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8364 11:45:43.941517 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8365 11:45:43.948450 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 11:45:43.951616 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 11:45:43.954740 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 11:45:43.961494 1 4 12 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)
8369 11:45:43.964775 1 4 16 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
8370 11:45:43.968598 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 11:45:43.974684 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 11:45:43.978225 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 11:45:43.981369 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 11:45:43.988073 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 11:45:43.991103 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 11:45:43.997721 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 11:45:44.000825 1 5 16 | B1->B0 | 2c2c 2d2d | 0 0 | (0 0) (0 1)
8378 11:45:44.004353 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 11:45:44.011182 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 11:45:44.014273 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 11:45:44.017681 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 11:45:44.024352 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 11:45:44.027627 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 11:45:44.030801 1 6 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8385 11:45:44.037469 1 6 16 | B1->B0 | 4444 4242 | 0 0 | (0 0) (0 0)
8386 11:45:44.040717 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 11:45:44.043957 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 11:45:44.050581 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 11:45:44.053670 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 11:45:44.057330 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 11:45:44.063581 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 11:45:44.066817 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 11:45:44.069927 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8394 11:45:44.076783 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8395 11:45:44.080005 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:45:44.083565 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:45:44.090118 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:45:44.093178 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:45:44.096828 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:45:44.103333 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:45:44.106613 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:45:44.109782 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:45:44.116285 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:45:44.119407 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 11:45:44.123146 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 11:45:44.129372 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 11:45:44.133113 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 11:45:44.136245 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 11:45:44.142554 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8410 11:45:44.145951 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 11:45:44.149052 Total UI for P1: 0, mck2ui 16
8412 11:45:44.152658 best dqsien dly found for B0: ( 1, 9, 16)
8413 11:45:44.155825 Total UI for P1: 0, mck2ui 16
8414 11:45:44.158821 best dqsien dly found for B1: ( 1, 9, 16)
8415 11:45:44.162345 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8416 11:45:44.165835 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8417 11:45:44.165917
8418 11:45:44.168957 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8419 11:45:44.172028 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8420 11:45:44.175155 [Gating] SW calibration Done
8421 11:45:44.175237 ==
8422 11:45:44.178692 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 11:45:44.184988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 11:45:44.185072 ==
8425 11:45:44.185137 RX Vref Scan: 0
8426 11:45:44.185198
8427 11:45:44.188864 RX Vref 0 -> 0, step: 1
8428 11:45:44.188947
8429 11:45:44.191810 RX Delay 0 -> 252, step: 8
8430 11:45:44.195037 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8431 11:45:44.198484 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8432 11:45:44.201337 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8433 11:45:44.204797 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8434 11:45:44.211248 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8435 11:45:44.214841 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8436 11:45:44.218464 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8437 11:45:44.221289 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8438 11:45:44.224904 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8439 11:45:44.231210 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8440 11:45:44.234301 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8441 11:45:44.238117 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8442 11:45:44.241072 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8443 11:45:44.247533 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8444 11:45:44.251143 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8445 11:45:44.254302 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8446 11:45:44.254398 ==
8447 11:45:44.257465 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 11:45:44.260637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 11:45:44.264246 ==
8450 11:45:44.264321 DQS Delay:
8451 11:45:44.264382 DQS0 = 0, DQS1 = 0
8452 11:45:44.267419 DQM Delay:
8453 11:45:44.267487 DQM0 = 131, DQM1 = 125
8454 11:45:44.270456 DQ Delay:
8455 11:45:44.274040 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8456 11:45:44.277119 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =127
8457 11:45:44.280313 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8458 11:45:44.284002 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8459 11:45:44.284072
8460 11:45:44.284136
8461 11:45:44.284194 ==
8462 11:45:44.287081 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 11:45:44.290352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 11:45:44.293411 ==
8465 11:45:44.293506
8466 11:45:44.293604
8467 11:45:44.293690 TX Vref Scan disable
8468 11:45:44.297082 == TX Byte 0 ==
8469 11:45:44.300250 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8470 11:45:44.303299 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8471 11:45:44.306567 == TX Byte 1 ==
8472 11:45:44.309857 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8473 11:45:44.313224 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8474 11:45:44.316691 ==
8475 11:45:44.319552 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 11:45:44.322963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 11:45:44.323040 ==
8478 11:45:44.336069
8479 11:45:44.339740 TX Vref early break, caculate TX vref
8480 11:45:44.342916 TX Vref=16, minBit 9, minWin=21, winSum=364
8481 11:45:44.346052 TX Vref=18, minBit 9, minWin=22, winSum=371
8482 11:45:44.349289 TX Vref=20, minBit 5, minWin=23, winSum=382
8483 11:45:44.353092 TX Vref=22, minBit 8, minWin=23, winSum=393
8484 11:45:44.356146 TX Vref=24, minBit 10, minWin=24, winSum=404
8485 11:45:44.362590 TX Vref=26, minBit 11, minWin=24, winSum=411
8486 11:45:44.365715 TX Vref=28, minBit 1, minWin=25, winSum=421
8487 11:45:44.369339 TX Vref=30, minBit 1, minWin=25, winSum=412
8488 11:45:44.372500 TX Vref=32, minBit 1, minWin=25, winSum=409
8489 11:45:44.375542 TX Vref=34, minBit 0, minWin=24, winSum=399
8490 11:45:44.382454 TX Vref=36, minBit 1, minWin=23, winSum=384
8491 11:45:44.385932 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8492 11:45:44.386012
8493 11:45:44.389148 Final TX Range 0 Vref 28
8494 11:45:44.389228
8495 11:45:44.389290 ==
8496 11:45:44.392051 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 11:45:44.395750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 11:45:44.398846 ==
8499 11:45:44.398925
8500 11:45:44.398988
8501 11:45:44.399044 TX Vref Scan disable
8502 11:45:44.405897 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8503 11:45:44.405995 == TX Byte 0 ==
8504 11:45:44.409080 u2DelayCellOfst[0]=18 cells (5 PI)
8505 11:45:44.412013 u2DelayCellOfst[1]=15 cells (4 PI)
8506 11:45:44.415688 u2DelayCellOfst[2]=0 cells (0 PI)
8507 11:45:44.418988 u2DelayCellOfst[3]=7 cells (2 PI)
8508 11:45:44.421971 u2DelayCellOfst[4]=7 cells (2 PI)
8509 11:45:44.425396 u2DelayCellOfst[5]=22 cells (6 PI)
8510 11:45:44.428491 u2DelayCellOfst[6]=22 cells (6 PI)
8511 11:45:44.432030 u2DelayCellOfst[7]=7 cells (2 PI)
8512 11:45:44.435668 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8513 11:45:44.438500 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8514 11:45:44.442278 == TX Byte 1 ==
8515 11:45:44.445508 u2DelayCellOfst[8]=0 cells (0 PI)
8516 11:45:44.448684 u2DelayCellOfst[9]=3 cells (1 PI)
8517 11:45:44.452078 u2DelayCellOfst[10]=11 cells (3 PI)
8518 11:45:44.455385 u2DelayCellOfst[11]=7 cells (2 PI)
8519 11:45:44.458592 u2DelayCellOfst[12]=15 cells (4 PI)
8520 11:45:44.461806 u2DelayCellOfst[13]=18 cells (5 PI)
8521 11:45:44.461915 u2DelayCellOfst[14]=18 cells (5 PI)
8522 11:45:44.464842 u2DelayCellOfst[15]=18 cells (5 PI)
8523 11:45:44.471624 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8524 11:45:44.474676 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8525 11:45:44.478475 DramC Write-DBI on
8526 11:45:44.478554 ==
8527 11:45:44.481590 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 11:45:44.484765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 11:45:44.484859 ==
8530 11:45:44.484921
8531 11:45:44.484978
8532 11:45:44.487770 TX Vref Scan disable
8533 11:45:44.487849 == TX Byte 0 ==
8534 11:45:44.494376 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8535 11:45:44.494456 == TX Byte 1 ==
8536 11:45:44.498027 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8537 11:45:44.501118 DramC Write-DBI off
8538 11:45:44.501197
8539 11:45:44.501259 [DATLAT]
8540 11:45:44.504151 Freq=1600, CH1 RK0
8541 11:45:44.504231
8542 11:45:44.504293 DATLAT Default: 0xf
8543 11:45:44.507845 0, 0xFFFF, sum = 0
8544 11:45:44.510902 1, 0xFFFF, sum = 0
8545 11:45:44.510983 2, 0xFFFF, sum = 0
8546 11:45:44.514583 3, 0xFFFF, sum = 0
8547 11:45:44.514664 4, 0xFFFF, sum = 0
8548 11:45:44.517715 5, 0xFFFF, sum = 0
8549 11:45:44.517796 6, 0xFFFF, sum = 0
8550 11:45:44.520771 7, 0xFFFF, sum = 0
8551 11:45:44.520852 8, 0xFFFF, sum = 0
8552 11:45:44.524373 9, 0xFFFF, sum = 0
8553 11:45:44.524454 10, 0xFFFF, sum = 0
8554 11:45:44.527404 11, 0xFFFF, sum = 0
8555 11:45:44.527485 12, 0xFFFF, sum = 0
8556 11:45:44.530919 13, 0x8FFF, sum = 0
8557 11:45:44.530999 14, 0x0, sum = 1
8558 11:45:44.534017 15, 0x0, sum = 2
8559 11:45:44.534125 16, 0x0, sum = 3
8560 11:45:44.537443 17, 0x0, sum = 4
8561 11:45:44.537551 best_step = 15
8562 11:45:44.537640
8563 11:45:44.537727 ==
8564 11:45:44.541023 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 11:45:44.547203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 11:45:44.547283 ==
8567 11:45:44.547346 RX Vref Scan: 1
8568 11:45:44.547405
8569 11:45:44.550649 Set Vref Range= 24 -> 127
8570 11:45:44.550753
8571 11:45:44.553841 RX Vref 24 -> 127, step: 1
8572 11:45:44.553921
8573 11:45:44.553983 RX Delay 11 -> 252, step: 4
8574 11:45:44.557573
8575 11:45:44.557652 Set Vref, RX VrefLevel [Byte0]: 24
8576 11:45:44.560693 [Byte1]: 24
8577 11:45:44.565004
8578 11:45:44.565084 Set Vref, RX VrefLevel [Byte0]: 25
8579 11:45:44.568221 [Byte1]: 25
8580 11:45:44.572678
8581 11:45:44.572758 Set Vref, RX VrefLevel [Byte0]: 26
8582 11:45:44.575673 [Byte1]: 26
8583 11:45:44.579914
8584 11:45:44.579993 Set Vref, RX VrefLevel [Byte0]: 27
8585 11:45:44.583007 [Byte1]: 27
8586 11:45:44.587984
8587 11:45:44.588063 Set Vref, RX VrefLevel [Byte0]: 28
8588 11:45:44.591076 [Byte1]: 28
8589 11:45:44.595306
8590 11:45:44.595384 Set Vref, RX VrefLevel [Byte0]: 29
8591 11:45:44.598378 [Byte1]: 29
8592 11:45:44.602997
8593 11:45:44.603076 Set Vref, RX VrefLevel [Byte0]: 30
8594 11:45:44.605892 [Byte1]: 30
8595 11:45:44.610569
8596 11:45:44.610648 Set Vref, RX VrefLevel [Byte0]: 31
8597 11:45:44.613500 [Byte1]: 31
8598 11:45:44.618199
8599 11:45:44.618278 Set Vref, RX VrefLevel [Byte0]: 32
8600 11:45:44.621631 [Byte1]: 32
8601 11:45:44.625441
8602 11:45:44.625520 Set Vref, RX VrefLevel [Byte0]: 33
8603 11:45:44.629084 [Byte1]: 33
8604 11:45:44.633512
8605 11:45:44.633591 Set Vref, RX VrefLevel [Byte0]: 34
8606 11:45:44.636226 [Byte1]: 34
8607 11:45:44.641035
8608 11:45:44.641127 Set Vref, RX VrefLevel [Byte0]: 35
8609 11:45:44.643921 [Byte1]: 35
8610 11:45:44.648506
8611 11:45:44.648586 Set Vref, RX VrefLevel [Byte0]: 36
8612 11:45:44.652065 [Byte1]: 36
8613 11:45:44.656087
8614 11:45:44.656166 Set Vref, RX VrefLevel [Byte0]: 37
8615 11:45:44.659544 [Byte1]: 37
8616 11:45:44.663898
8617 11:45:44.663976 Set Vref, RX VrefLevel [Byte0]: 38
8618 11:45:44.666984 [Byte1]: 38
8619 11:45:44.671407
8620 11:45:44.671486 Set Vref, RX VrefLevel [Byte0]: 39
8621 11:45:44.674472 [Byte1]: 39
8622 11:45:44.679295
8623 11:45:44.679375 Set Vref, RX VrefLevel [Byte0]: 40
8624 11:45:44.682336 [Byte1]: 40
8625 11:45:44.686611
8626 11:45:44.686690 Set Vref, RX VrefLevel [Byte0]: 41
8627 11:45:44.689719 [Byte1]: 41
8628 11:45:44.694082
8629 11:45:44.694161 Set Vref, RX VrefLevel [Byte0]: 42
8630 11:45:44.697206 [Byte1]: 42
8631 11:45:44.701523
8632 11:45:44.701603 Set Vref, RX VrefLevel [Byte0]: 43
8633 11:45:44.705149 [Byte1]: 43
8634 11:45:44.709515
8635 11:45:44.709620 Set Vref, RX VrefLevel [Byte0]: 44
8636 11:45:44.713085 [Byte1]: 44
8637 11:45:44.717129
8638 11:45:44.717209 Set Vref, RX VrefLevel [Byte0]: 45
8639 11:45:44.720028 [Byte1]: 45
8640 11:45:44.724329
8641 11:45:44.724440 Set Vref, RX VrefLevel [Byte0]: 46
8642 11:45:44.728099 [Byte1]: 46
8643 11:45:44.732542
8644 11:45:44.732621 Set Vref, RX VrefLevel [Byte0]: 47
8645 11:45:44.735565 [Byte1]: 47
8646 11:45:44.739824
8647 11:45:44.739903 Set Vref, RX VrefLevel [Byte0]: 48
8648 11:45:44.743336 [Byte1]: 48
8649 11:45:44.747427
8650 11:45:44.747506 Set Vref, RX VrefLevel [Byte0]: 49
8651 11:45:44.751056 [Byte1]: 49
8652 11:45:44.755010
8653 11:45:44.755130 Set Vref, RX VrefLevel [Byte0]: 50
8654 11:45:44.758549 [Byte1]: 50
8655 11:45:44.762476
8656 11:45:44.762581 Set Vref, RX VrefLevel [Byte0]: 51
8657 11:45:44.766040 [Byte1]: 51
8658 11:45:44.770071
8659 11:45:44.770151 Set Vref, RX VrefLevel [Byte0]: 52
8660 11:45:44.773803 [Byte1]: 52
8661 11:45:44.778125
8662 11:45:44.778204 Set Vref, RX VrefLevel [Byte0]: 53
8663 11:45:44.781200 [Byte1]: 53
8664 11:45:44.785609
8665 11:45:44.785688 Set Vref, RX VrefLevel [Byte0]: 54
8666 11:45:44.788548 [Byte1]: 54
8667 11:45:44.793011
8668 11:45:44.793119 Set Vref, RX VrefLevel [Byte0]: 55
8669 11:45:44.796698 [Byte1]: 55
8670 11:45:44.801093
8671 11:45:44.801172 Set Vref, RX VrefLevel [Byte0]: 56
8672 11:45:44.804175 [Byte1]: 56
8673 11:45:44.808512
8674 11:45:44.808608 Set Vref, RX VrefLevel [Byte0]: 57
8675 11:45:44.811605 [Byte1]: 57
8676 11:45:44.815900
8677 11:45:44.815980 Set Vref, RX VrefLevel [Byte0]: 58
8678 11:45:44.819009 [Byte1]: 58
8679 11:45:44.823535
8680 11:45:44.823630 Set Vref, RX VrefLevel [Byte0]: 59
8681 11:45:44.827097 [Byte1]: 59
8682 11:45:44.830939
8683 11:45:44.831044 Set Vref, RX VrefLevel [Byte0]: 60
8684 11:45:44.834654 [Byte1]: 60
8685 11:45:44.838945
8686 11:45:44.839024 Set Vref, RX VrefLevel [Byte0]: 61
8687 11:45:44.842042 [Byte1]: 61
8688 11:45:44.846324
8689 11:45:44.846403 Set Vref, RX VrefLevel [Byte0]: 62
8690 11:45:44.849467 [Byte1]: 62
8691 11:45:44.854201
8692 11:45:44.854280 Set Vref, RX VrefLevel [Byte0]: 63
8693 11:45:44.857157 [Byte1]: 63
8694 11:45:44.861354
8695 11:45:44.861433 Set Vref, RX VrefLevel [Byte0]: 64
8696 11:45:44.864818 [Byte1]: 64
8697 11:45:44.869202
8698 11:45:44.869305 Set Vref, RX VrefLevel [Byte0]: 65
8699 11:45:44.872297 [Byte1]: 65
8700 11:45:44.876856
8701 11:45:44.876935 Set Vref, RX VrefLevel [Byte0]: 66
8702 11:45:44.879904 [Byte1]: 66
8703 11:45:44.884279
8704 11:45:44.884358 Set Vref, RX VrefLevel [Byte0]: 67
8705 11:45:44.887916 [Byte1]: 67
8706 11:45:44.892304
8707 11:45:44.892383 Set Vref, RX VrefLevel [Byte0]: 68
8708 11:45:44.895292 [Byte1]: 68
8709 11:45:44.899616
8710 11:45:44.899695 Set Vref, RX VrefLevel [Byte0]: 69
8711 11:45:44.902654 [Byte1]: 69
8712 11:45:44.907100
8713 11:45:44.907206 Set Vref, RX VrefLevel [Byte0]: 70
8714 11:45:44.910881 [Byte1]: 70
8715 11:45:44.914882
8716 11:45:44.914960 Set Vref, RX VrefLevel [Byte0]: 71
8717 11:45:44.917957 [Byte1]: 71
8718 11:45:44.922477
8719 11:45:44.922556 Final RX Vref Byte 0 = 63 to rank0
8720 11:45:44.925572 Final RX Vref Byte 1 = 53 to rank0
8721 11:45:44.929155 Final RX Vref Byte 0 = 63 to rank1
8722 11:45:44.932519 Final RX Vref Byte 1 = 53 to rank1==
8723 11:45:44.935548 Dram Type= 6, Freq= 0, CH_1, rank 0
8724 11:45:44.942496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 11:45:44.942576 ==
8726 11:45:44.942638 DQS Delay:
8727 11:45:44.945575 DQS0 = 0, DQS1 = 0
8728 11:45:44.945654 DQM Delay:
8729 11:45:44.945717 DQM0 = 131, DQM1 = 123
8730 11:45:44.948695 DQ Delay:
8731 11:45:44.951815 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8732 11:45:44.955636 DQ4 =128, DQ5 =144, DQ6 =144, DQ7 =126
8733 11:45:44.958625 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8734 11:45:44.962274 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8735 11:45:44.962382
8736 11:45:44.962473
8737 11:45:44.962561
8738 11:45:44.965130 [DramC_TX_OE_Calibration] TA2
8739 11:45:44.968763 Original DQ_B0 (3 6) =30, OEN = 27
8740 11:45:44.971779 Original DQ_B1 (3 6) =30, OEN = 27
8741 11:45:44.975191 24, 0x0, End_B0=24 End_B1=24
8742 11:45:44.978259 25, 0x0, End_B0=25 End_B1=25
8743 11:45:44.978340 26, 0x0, End_B0=26 End_B1=26
8744 11:45:44.981879 27, 0x0, End_B0=27 End_B1=27
8745 11:45:44.985374 28, 0x0, End_B0=28 End_B1=28
8746 11:45:44.988586 29, 0x0, End_B0=29 End_B1=29
8747 11:45:44.988668 30, 0x0, End_B0=30 End_B1=30
8748 11:45:44.991553 31, 0x4141, End_B0=30 End_B1=30
8749 11:45:44.994678 Byte0 end_step=30 best_step=27
8750 11:45:44.998507 Byte1 end_step=30 best_step=27
8751 11:45:45.001691 Byte0 TX OE(2T, 0.5T) = (3, 3)
8752 11:45:45.004745 Byte1 TX OE(2T, 0.5T) = (3, 3)
8753 11:45:45.004826
8754 11:45:45.004889
8755 11:45:45.011440 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8756 11:45:45.014493 CH1 RK0: MR19=303, MR18=90E
8757 11:45:45.021215 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8758 11:45:45.021297
8759 11:45:45.024720 ----->DramcWriteLeveling(PI) begin...
8760 11:45:45.024802 ==
8761 11:45:45.027911 Dram Type= 6, Freq= 0, CH_1, rank 1
8762 11:45:45.030993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 11:45:45.031075 ==
8764 11:45:45.034703 Write leveling (Byte 0): 26 => 26
8765 11:45:45.037561 Write leveling (Byte 1): 27 => 27
8766 11:45:45.041143 DramcWriteLeveling(PI) end<-----
8767 11:45:45.041223
8768 11:45:45.041286 ==
8769 11:45:45.044353 Dram Type= 6, Freq= 0, CH_1, rank 1
8770 11:45:45.047489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 11:45:45.050600 ==
8772 11:45:45.050706 [Gating] SW mode calibration
8773 11:45:45.060679 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8774 11:45:45.064283 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8775 11:45:45.067386 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 11:45:45.074183 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 11:45:45.077134 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8778 11:45:45.080667 1 4 12 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
8779 11:45:45.087196 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 11:45:45.090198 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 11:45:45.094022 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 11:45:45.100550 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 11:45:45.103719 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 11:45:45.106918 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 11:45:45.113685 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
8786 11:45:45.116687 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8787 11:45:45.119795 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 11:45:45.126774 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 11:45:45.130072 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 11:45:45.133159 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 11:45:45.139919 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 11:45:45.143563 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8793 11:45:45.146573 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8794 11:45:45.152851 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 11:45:45.156575 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 11:45:45.159717 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 11:45:45.166608 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 11:45:45.169767 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 11:45:45.172957 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 11:45:45.179583 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 11:45:45.183077 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8802 11:45:45.186058 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8803 11:45:45.193076 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 11:45:45.195994 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:45:45.199603 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:45:45.205996 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:45:45.209494 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 11:45:45.212721 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 11:45:45.218750 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 11:45:45.222588 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 11:45:45.225714 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 11:45:45.232543 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 11:45:45.235612 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 11:45:45.238732 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 11:45:45.245423 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 11:45:45.248627 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:45:45.251759 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 11:45:45.258767 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8819 11:45:45.262095 Total UI for P1: 0, mck2ui 16
8820 11:45:45.265168 best dqsien dly found for B0: ( 1, 9, 8)
8821 11:45:45.268525 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 11:45:45.271843 Total UI for P1: 0, mck2ui 16
8823 11:45:45.275107 best dqsien dly found for B1: ( 1, 9, 12)
8824 11:45:45.278388 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8825 11:45:45.281366 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8826 11:45:45.281463
8827 11:45:45.284731 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8828 11:45:45.291576 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8829 11:45:45.291655 [Gating] SW calibration Done
8830 11:45:45.291717 ==
8831 11:45:45.294546 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 11:45:45.301550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 11:45:45.301627 ==
8834 11:45:45.301692 RX Vref Scan: 0
8835 11:45:45.301750
8836 11:45:45.304593 RX Vref 0 -> 0, step: 1
8837 11:45:45.304691
8838 11:45:45.308117 RX Delay 0 -> 252, step: 8
8839 11:45:45.310971 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8840 11:45:45.314527 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8841 11:45:45.317763 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8842 11:45:45.324404 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8843 11:45:45.327557 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8844 11:45:45.331043 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8845 11:45:45.334140 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8846 11:45:45.337958 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8847 11:45:45.344163 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8848 11:45:45.347903 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8849 11:45:45.350797 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8850 11:45:45.353926 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8851 11:45:45.357698 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8852 11:45:45.364404 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8853 11:45:45.367493 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8854 11:45:45.370638 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8855 11:45:45.370739 ==
8856 11:45:45.373813 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 11:45:45.377535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 11:45:45.380616 ==
8859 11:45:45.380712 DQS Delay:
8860 11:45:45.380799 DQS0 = 0, DQS1 = 0
8861 11:45:45.383707 DQM Delay:
8862 11:45:45.383777 DQM0 = 131, DQM1 = 128
8863 11:45:45.387241 DQ Delay:
8864 11:45:45.390371 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =127
8865 11:45:45.393974 DQ4 =123, DQ5 =143, DQ6 =139, DQ7 =131
8866 11:45:45.397232 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8867 11:45:45.400259 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =139
8868 11:45:45.400362
8869 11:45:45.400440
8870 11:45:45.400498 ==
8871 11:45:45.403860 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 11:45:45.407222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 11:45:45.407336 ==
8874 11:45:45.407423
8875 11:45:45.410323
8876 11:45:45.410418 TX Vref Scan disable
8877 11:45:45.413291 == TX Byte 0 ==
8878 11:45:45.416958 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8879 11:45:45.419996 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8880 11:45:45.423657 == TX Byte 1 ==
8881 11:45:45.426672 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8882 11:45:45.430242 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8883 11:45:45.430344 ==
8884 11:45:45.433254 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 11:45:45.439880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 11:45:45.439961 ==
8887 11:45:45.451711
8888 11:45:45.455096 TX Vref early break, caculate TX vref
8889 11:45:45.458129 TX Vref=16, minBit 0, minWin=23, winSum=385
8890 11:45:45.461846 TX Vref=18, minBit 6, minWin=23, winSum=394
8891 11:45:45.465050 TX Vref=20, minBit 0, minWin=24, winSum=404
8892 11:45:45.468118 TX Vref=22, minBit 0, minWin=24, winSum=410
8893 11:45:45.471253 TX Vref=24, minBit 0, minWin=25, winSum=421
8894 11:45:45.477981 TX Vref=26, minBit 0, minWin=25, winSum=427
8895 11:45:45.481766 TX Vref=28, minBit 1, minWin=25, winSum=427
8896 11:45:45.484929 TX Vref=30, minBit 1, minWin=25, winSum=425
8897 11:45:45.487963 TX Vref=32, minBit 5, minWin=24, winSum=415
8898 11:45:45.491153 TX Vref=34, minBit 5, minWin=23, winSum=404
8899 11:45:45.497770 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8900 11:45:45.497843
8901 11:45:45.501577 Final TX Range 0 Vref 26
8902 11:45:45.501675
8903 11:45:45.501761 ==
8904 11:45:45.504680 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 11:45:45.507827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 11:45:45.507949 ==
8907 11:45:45.508036
8908 11:45:45.508120
8909 11:45:45.511259 TX Vref Scan disable
8910 11:45:45.517659 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8911 11:45:45.517761 == TX Byte 0 ==
8912 11:45:45.521314 u2DelayCellOfst[0]=18 cells (5 PI)
8913 11:45:45.524081 u2DelayCellOfst[1]=11 cells (3 PI)
8914 11:45:45.527536 u2DelayCellOfst[2]=0 cells (0 PI)
8915 11:45:45.530565 u2DelayCellOfst[3]=7 cells (2 PI)
8916 11:45:45.534146 u2DelayCellOfst[4]=11 cells (3 PI)
8917 11:45:45.537635 u2DelayCellOfst[5]=18 cells (5 PI)
8918 11:45:45.540765 u2DelayCellOfst[6]=18 cells (5 PI)
8919 11:45:45.544504 u2DelayCellOfst[7]=7 cells (2 PI)
8920 11:45:45.547605 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8921 11:45:45.550471 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8922 11:45:45.553618 == TX Byte 1 ==
8923 11:45:45.557277 u2DelayCellOfst[8]=0 cells (0 PI)
8924 11:45:45.560331 u2DelayCellOfst[9]=7 cells (2 PI)
8925 11:45:45.560402 u2DelayCellOfst[10]=15 cells (4 PI)
8926 11:45:45.563416 u2DelayCellOfst[11]=7 cells (2 PI)
8927 11:45:45.567231 u2DelayCellOfst[12]=15 cells (4 PI)
8928 11:45:45.570436 u2DelayCellOfst[13]=18 cells (5 PI)
8929 11:45:45.573479 u2DelayCellOfst[14]=22 cells (6 PI)
8930 11:45:45.577077 u2DelayCellOfst[15]=22 cells (6 PI)
8931 11:45:45.583220 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8932 11:45:45.586452 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8933 11:45:45.586532 DramC Write-DBI on
8934 11:45:45.590256 ==
8935 11:45:45.590335 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 11:45:45.596590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 11:45:45.596694 ==
8938 11:45:45.596788
8939 11:45:45.596874
8940 11:45:45.599518 TX Vref Scan disable
8941 11:45:45.599614 == TX Byte 0 ==
8942 11:45:45.606231 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8943 11:45:45.606336 == TX Byte 1 ==
8944 11:45:45.610017 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8945 11:45:45.613173 DramC Write-DBI off
8946 11:45:45.613252
8947 11:45:45.613313 [DATLAT]
8948 11:45:45.616103 Freq=1600, CH1 RK1
8949 11:45:45.616208
8950 11:45:45.616298 DATLAT Default: 0xf
8951 11:45:45.619543 0, 0xFFFF, sum = 0
8952 11:45:45.619651 1, 0xFFFF, sum = 0
8953 11:45:45.622549 2, 0xFFFF, sum = 0
8954 11:45:45.622646 3, 0xFFFF, sum = 0
8955 11:45:45.626070 4, 0xFFFF, sum = 0
8956 11:45:45.626150 5, 0xFFFF, sum = 0
8957 11:45:45.629735 6, 0xFFFF, sum = 0
8958 11:45:45.632759 7, 0xFFFF, sum = 0
8959 11:45:45.632859 8, 0xFFFF, sum = 0
8960 11:45:45.635745 9, 0xFFFF, sum = 0
8961 11:45:45.635852 10, 0xFFFF, sum = 0
8962 11:45:45.639426 11, 0xFFFF, sum = 0
8963 11:45:45.639534 12, 0xFFFF, sum = 0
8964 11:45:45.642298 13, 0x8FFF, sum = 0
8965 11:45:45.642398 14, 0x0, sum = 1
8966 11:45:45.645879 15, 0x0, sum = 2
8967 11:45:45.645959 16, 0x0, sum = 3
8968 11:45:45.649440 17, 0x0, sum = 4
8969 11:45:45.649521 best_step = 15
8970 11:45:45.649583
8971 11:45:45.649641 ==
8972 11:45:45.652335 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 11:45:45.655798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 11:45:45.659189 ==
8975 11:45:45.659268 RX Vref Scan: 0
8976 11:45:45.659330
8977 11:45:45.662291 RX Vref 0 -> 0, step: 1
8978 11:45:45.662404
8979 11:45:45.665314 RX Delay 11 -> 252, step: 4
8980 11:45:45.668491 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8981 11:45:45.672171 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8982 11:45:45.675311 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8983 11:45:45.682155 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8984 11:45:45.685405 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
8985 11:45:45.688474 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8986 11:45:45.692094 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8987 11:45:45.695167 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
8988 11:45:45.701970 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8989 11:45:45.705084 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8990 11:45:45.708683 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8991 11:45:45.743989 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8992 11:45:45.744278 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8993 11:45:45.744349 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8994 11:45:45.744410 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8995 11:45:45.744468 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8996 11:45:45.744522 ==
8997 11:45:45.744577 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 11:45:45.744630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 11:45:45.744685 ==
9000 11:45:45.744739 DQS Delay:
9001 11:45:45.744792 DQS0 = 0, DQS1 = 0
9002 11:45:45.744845 DQM Delay:
9003 11:45:45.744897 DQM0 = 130, DQM1 = 125
9004 11:45:45.744961 DQ Delay:
9005 11:45:45.747777 DQ0 =134, DQ1 =130, DQ2 =118, DQ3 =126
9006 11:45:45.751364 DQ4 =124, DQ5 =142, DQ6 =142, DQ7 =126
9007 11:45:45.754355 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9008 11:45:45.757924 DQ12 =132, DQ13 =136, DQ14 =130, DQ15 =136
9009 11:45:45.758012
9010 11:45:45.758076
9011 11:45:45.758135
9012 11:45:45.761010 [DramC_TX_OE_Calibration] TA2
9013 11:45:45.764708 Original DQ_B0 (3 6) =30, OEN = 27
9014 11:45:45.767697 Original DQ_B1 (3 6) =30, OEN = 27
9015 11:45:45.770969 24, 0x0, End_B0=24 End_B1=24
9016 11:45:45.771050 25, 0x0, End_B0=25 End_B1=25
9017 11:45:45.774684 26, 0x0, End_B0=26 End_B1=26
9018 11:45:45.777800 27, 0x0, End_B0=27 End_B1=27
9019 11:45:45.780988 28, 0x0, End_B0=28 End_B1=28
9020 11:45:45.784028 29, 0x0, End_B0=29 End_B1=29
9021 11:45:45.784136 30, 0x0, End_B0=30 End_B1=30
9022 11:45:45.788122 31, 0x4141, End_B0=30 End_B1=30
9023 11:45:45.790858 Byte0 end_step=30 best_step=27
9024 11:45:45.793860 Byte1 end_step=30 best_step=27
9025 11:45:45.797589 Byte0 TX OE(2T, 0.5T) = (3, 3)
9026 11:45:45.800588 Byte1 TX OE(2T, 0.5T) = (3, 3)
9027 11:45:45.800668
9028 11:45:45.800730
9029 11:45:45.807284 [DQSOSCAuto] RK1, (LSB)MR18= 0x121d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
9030 11:45:45.810944 CH1 RK1: MR19=303, MR18=121D
9031 11:45:45.817284 CH1_RK1: MR19=0x303, MR18=0x121D, DQSOSC=395, MR23=63, INC=23, DEC=15
9032 11:45:45.820281 [RxdqsGatingPostProcess] freq 1600
9033 11:45:45.824013 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9034 11:45:45.827094 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 11:45:45.830566 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 11:45:45.833613 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 11:45:45.837161 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 11:45:45.840174 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 11:45:45.843916 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 11:45:45.846795 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 11:45:45.850454 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 11:45:45.853692 Pre-setting of DQS Precalculation
9043 11:45:45.856708 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9044 11:45:45.863420 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9045 11:45:45.873003 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9046 11:45:45.873084
9047 11:45:45.873146
9048 11:45:45.876768 [Calibration Summary] 3200 Mbps
9049 11:45:45.876848 CH 0, Rank 0
9050 11:45:45.879854 SW Impedance : PASS
9051 11:45:45.879933 DUTY Scan : NO K
9052 11:45:45.882984 ZQ Calibration : PASS
9053 11:45:45.886088 Jitter Meter : NO K
9054 11:45:45.886168 CBT Training : PASS
9055 11:45:45.889772 Write leveling : PASS
9056 11:45:45.892854 RX DQS gating : PASS
9057 11:45:45.892934 RX DQ/DQS(RDDQC) : PASS
9058 11:45:45.896584 TX DQ/DQS : PASS
9059 11:45:45.899585 RX DATLAT : PASS
9060 11:45:45.899664 RX DQ/DQS(Engine): PASS
9061 11:45:45.902739 TX OE : PASS
9062 11:45:45.902819 All Pass.
9063 11:45:45.902923
9064 11:45:45.906491 CH 0, Rank 1
9065 11:45:45.906571 SW Impedance : PASS
9066 11:45:45.909589 DUTY Scan : NO K
9067 11:45:45.909668 ZQ Calibration : PASS
9068 11:45:45.912521 Jitter Meter : NO K
9069 11:45:45.916319 CBT Training : PASS
9070 11:45:45.916400 Write leveling : PASS
9071 11:45:45.919524 RX DQS gating : PASS
9072 11:45:45.922600 RX DQ/DQS(RDDQC) : PASS
9073 11:45:45.922705 TX DQ/DQS : PASS
9074 11:45:45.926055 RX DATLAT : PASS
9075 11:45:45.929437 RX DQ/DQS(Engine): PASS
9076 11:45:45.929516 TX OE : PASS
9077 11:45:45.932259 All Pass.
9078 11:45:45.932332
9079 11:45:45.932400 CH 1, Rank 0
9080 11:45:45.935850 SW Impedance : PASS
9081 11:45:45.935923 DUTY Scan : NO K
9082 11:45:45.938940 ZQ Calibration : PASS
9083 11:45:45.942434 Jitter Meter : NO K
9084 11:45:45.942530 CBT Training : PASS
9085 11:45:45.945430 Write leveling : PASS
9086 11:45:45.948897 RX DQS gating : PASS
9087 11:45:45.948992 RX DQ/DQS(RDDQC) : PASS
9088 11:45:45.952497 TX DQ/DQS : PASS
9089 11:45:45.955478 RX DATLAT : PASS
9090 11:45:45.955550 RX DQ/DQS(Engine): PASS
9091 11:45:45.958802 TX OE : PASS
9092 11:45:45.958915 All Pass.
9093 11:45:45.958976
9094 11:45:45.962233 CH 1, Rank 1
9095 11:45:45.962402 SW Impedance : PASS
9096 11:45:45.965324 DUTY Scan : NO K
9097 11:45:45.968576 ZQ Calibration : PASS
9098 11:45:45.968655 Jitter Meter : NO K
9099 11:45:45.972212 CBT Training : PASS
9100 11:45:45.975152 Write leveling : PASS
9101 11:45:45.975230 RX DQS gating : PASS
9102 11:45:45.978197 RX DQ/DQS(RDDQC) : PASS
9103 11:45:45.982039 TX DQ/DQS : PASS
9104 11:45:45.982118 RX DATLAT : PASS
9105 11:45:45.985098 RX DQ/DQS(Engine): PASS
9106 11:45:45.988252 TX OE : PASS
9107 11:45:45.988330 All Pass.
9108 11:45:45.988393
9109 11:45:45.988450 DramC Write-DBI on
9110 11:45:45.992054 PER_BANK_REFRESH: Hybrid Mode
9111 11:45:45.995017 TX_TRACKING: ON
9112 11:45:46.001797 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9113 11:45:46.011735 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9114 11:45:46.018196 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 11:45:46.021386 [FAST_K] Save calibration result to emmc
9116 11:45:46.024446 sync common calibartion params.
9117 11:45:46.027590 sync cbt_mode0:1, 1:1
9118 11:45:46.027671 dram_init: ddr_geometry: 2
9119 11:45:46.031275 dram_init: ddr_geometry: 2
9120 11:45:46.034341 dram_init: ddr_geometry: 2
9121 11:45:46.034446 0:dram_rank_size:100000000
9122 11:45:46.038077 1:dram_rank_size:100000000
9123 11:45:46.044694 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9124 11:45:46.047727 DFS_SHUFFLE_HW_MODE: ON
9125 11:45:46.050722 dramc_set_vcore_voltage set vcore to 725000
9126 11:45:46.050851 Read voltage for 1600, 0
9127 11:45:46.054191 Vio18 = 0
9128 11:45:46.054272 Vcore = 725000
9129 11:45:46.054335 Vdram = 0
9130 11:45:46.057819 Vddq = 0
9131 11:45:46.057899 Vmddr = 0
9132 11:45:46.060849 switch to 3200 Mbps bootup
9133 11:45:46.060929 [DramcRunTimeConfig]
9134 11:45:46.060991 PHYPLL
9135 11:45:46.064363 DPM_CONTROL_AFTERK: ON
9136 11:45:46.067874 PER_BANK_REFRESH: ON
9137 11:45:46.070658 REFRESH_OVERHEAD_REDUCTION: ON
9138 11:45:46.070764 CMD_PICG_NEW_MODE: OFF
9139 11:45:46.074187 XRTWTW_NEW_MODE: ON
9140 11:45:46.074293 XRTRTR_NEW_MODE: ON
9141 11:45:46.077197 TX_TRACKING: ON
9142 11:45:46.077278 RDSEL_TRACKING: OFF
9143 11:45:46.080845 DQS Precalculation for DVFS: ON
9144 11:45:46.084050 RX_TRACKING: OFF
9145 11:45:46.084130 HW_GATING DBG: ON
9146 11:45:46.087106 ZQCS_ENABLE_LP4: ON
9147 11:45:46.087186 RX_PICG_NEW_MODE: ON
9148 11:45:46.090820 TX_PICG_NEW_MODE: ON
9149 11:45:46.090921 ENABLE_RX_DCM_DPHY: ON
9150 11:45:46.093856 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9151 11:45:46.097060 DUMMY_READ_FOR_TRACKING: OFF
9152 11:45:46.100853 !!! SPM_CONTROL_AFTERK: OFF
9153 11:45:46.104075 !!! SPM could not control APHY
9154 11:45:46.104156 IMPEDANCE_TRACKING: ON
9155 11:45:46.107201 TEMP_SENSOR: ON
9156 11:45:46.107281 HW_SAVE_FOR_SR: OFF
9157 11:45:46.110312 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9158 11:45:46.113468 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9159 11:45:46.117192 Read ODT Tracking: ON
9160 11:45:46.120216 Refresh Rate DeBounce: ON
9161 11:45:46.120323 DFS_NO_QUEUE_FLUSH: ON
9162 11:45:46.123268 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9163 11:45:46.127092 ENABLE_DFS_RUNTIME_MRW: OFF
9164 11:45:46.129952 DDR_RESERVE_NEW_MODE: ON
9165 11:45:46.130032 MR_CBT_SWITCH_FREQ: ON
9166 11:45:46.133144 =========================
9167 11:45:46.152060 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9168 11:45:46.155546 dram_init: ddr_geometry: 2
9169 11:45:46.173804 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9170 11:45:46.177406 dram_init: dram init end (result: 0)
9171 11:45:46.183855 DRAM-K: Full calibration passed in 24596 msecs
9172 11:45:46.186810 MRC: failed to locate region type 0.
9173 11:45:46.186963 DRAM rank0 size:0x100000000,
9174 11:45:46.190622 DRAM rank1 size=0x100000000
9175 11:45:46.199999 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9176 11:45:46.206616 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9177 11:45:46.213617 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9178 11:45:46.223512 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9179 11:45:46.223593 DRAM rank0 size:0x100000000,
9180 11:45:46.226461 DRAM rank1 size=0x100000000
9181 11:45:46.226581 CBMEM:
9182 11:45:46.230230 IMD: root @ 0xfffff000 254 entries.
9183 11:45:46.233372 IMD: root @ 0xffffec00 62 entries.
9184 11:45:46.236446 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9185 11:45:46.243372 WARNING: RO_VPD is uninitialized or empty.
9186 11:45:46.246428 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9187 11:45:46.253711 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9188 11:45:46.266759 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9189 11:45:46.277902 BS: romstage times (exec / console): total (unknown) / 24059 ms
9190 11:45:46.278024
9191 11:45:46.278114
9192 11:45:46.288078 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9193 11:45:46.291169 ARM64: Exception handlers installed.
9194 11:45:46.294997 ARM64: Testing exception
9195 11:45:46.298053 ARM64: Done test exception
9196 11:45:46.298133 Enumerating buses...
9197 11:45:46.301228 Show all devs... Before device enumeration.
9198 11:45:46.304307 Root Device: enabled 1
9199 11:45:46.308059 CPU_CLUSTER: 0: enabled 1
9200 11:45:46.308131 CPU: 00: enabled 1
9201 11:45:46.311228 Compare with tree...
9202 11:45:46.311297 Root Device: enabled 1
9203 11:45:46.314476 CPU_CLUSTER: 0: enabled 1
9204 11:45:46.317460 CPU: 00: enabled 1
9205 11:45:46.317529 Root Device scanning...
9206 11:45:46.321194 scan_static_bus for Root Device
9207 11:45:46.324338 CPU_CLUSTER: 0 enabled
9208 11:45:46.327406 scan_static_bus for Root Device done
9209 11:45:46.331017 scan_bus: bus Root Device finished in 8 msecs
9210 11:45:46.331087 done
9211 11:45:46.337404 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9212 11:45:46.340489 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9213 11:45:46.347468 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9214 11:45:46.353706 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9215 11:45:46.353778 Allocating resources...
9216 11:45:46.356897 Reading resources...
9217 11:45:46.360643 Root Device read_resources bus 0 link: 0
9218 11:45:46.363682 DRAM rank0 size:0x100000000,
9219 11:45:46.363750 DRAM rank1 size=0x100000000
9220 11:45:46.370204 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9221 11:45:46.370280 CPU: 00 missing read_resources
9222 11:45:46.376428 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9223 11:45:46.379972 Root Device read_resources bus 0 link: 0 done
9224 11:45:46.383473 Done reading resources.
9225 11:45:46.386294 Show resources in subtree (Root Device)...After reading.
9226 11:45:46.389821 Root Device child on link 0 CPU_CLUSTER: 0
9227 11:45:46.393459 CPU_CLUSTER: 0 child on link 0 CPU: 00
9228 11:45:46.402935 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9229 11:45:46.403016 CPU: 00
9230 11:45:46.409696 Root Device assign_resources, bus 0 link: 0
9231 11:45:46.412923 CPU_CLUSTER: 0 missing set_resources
9232 11:45:46.416044 Root Device assign_resources, bus 0 link: 0 done
9233 11:45:46.419707 Done setting resources.
9234 11:45:46.422800 Show resources in subtree (Root Device)...After assigning values.
9235 11:45:46.425873 Root Device child on link 0 CPU_CLUSTER: 0
9236 11:45:46.432901 CPU_CLUSTER: 0 child on link 0 CPU: 00
9237 11:45:46.439304 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9238 11:45:46.442586 CPU: 00
9239 11:45:46.442691 Done allocating resources.
9240 11:45:46.449279 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9241 11:45:46.449359 Enabling resources...
9242 11:45:46.452368 done.
9243 11:45:46.455566 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9244 11:45:46.458748 Initializing devices...
9245 11:45:46.458894 Root Device init
9246 11:45:46.462475 init hardware done!
9247 11:45:46.462579 0x00000018: ctrlr->caps
9248 11:45:46.465766 52.000 MHz: ctrlr->f_max
9249 11:45:46.468918 0.400 MHz: ctrlr->f_min
9250 11:45:46.471803 0x40ff8080: ctrlr->voltages
9251 11:45:46.471886 sclk: 390625
9252 11:45:46.471956 Bus Width = 1
9253 11:45:46.475207 sclk: 390625
9254 11:45:46.475286 Bus Width = 1
9255 11:45:46.478775 Early init status = 3
9256 11:45:46.481719 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9257 11:45:46.485934 in-header: 03 fc 00 00 01 00 00 00
9258 11:45:46.488852 in-data: 00
9259 11:45:46.492244 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9260 11:45:46.496857 in-header: 03 fd 00 00 00 00 00 00
9261 11:45:46.499919 in-data:
9262 11:45:46.503294 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9263 11:45:46.506744 in-header: 03 fc 00 00 01 00 00 00
9264 11:45:46.510451 in-data: 00
9265 11:45:46.513007 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9266 11:45:46.517872 in-header: 03 fd 00 00 00 00 00 00
9267 11:45:46.521550 in-data:
9268 11:45:46.524750 [SSUSB] Setting up USB HOST controller...
9269 11:45:46.527837 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9270 11:45:46.531039 [SSUSB] phy power-on done.
9271 11:45:46.534697 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9272 11:45:46.541477 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9273 11:45:46.544486 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9274 11:45:46.550734 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9275 11:45:46.557488 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9276 11:45:46.564444 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9277 11:45:46.570662 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9278 11:45:46.577618 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9279 11:45:46.580648 SPM: binary array size = 0x9dc
9280 11:45:46.583656 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9281 11:45:46.590257 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9282 11:45:46.597171 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9283 11:45:46.603708 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9284 11:45:46.606611 configure_display: Starting display init
9285 11:45:46.641528 anx7625_power_on_init: Init interface.
9286 11:45:46.644586 anx7625_disable_pd_protocol: Disabled PD feature.
9287 11:45:46.647659 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9288 11:45:46.675584 anx7625_start_dp_work: Secure OCM version=00
9289 11:45:46.678668 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9290 11:45:46.693820 sp_tx_get_edid_block: EDID Block = 1
9291 11:45:46.796539 Extracted contents:
9292 11:45:46.799369 header: 00 ff ff ff ff ff ff 00
9293 11:45:46.802898 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9294 11:45:46.806490 version: 01 04
9295 11:45:46.809384 basic params: 95 1f 11 78 0a
9296 11:45:46.812966 chroma info: 76 90 94 55 54 90 27 21 50 54
9297 11:45:46.815830 established: 00 00 00
9298 11:45:46.822914 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9299 11:45:46.829289 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9300 11:45:46.832478 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9301 11:45:46.839096 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9302 11:45:46.845845 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9303 11:45:46.848951 extensions: 00
9304 11:45:46.849031 checksum: fb
9305 11:45:46.849094
9306 11:45:46.856066 Manufacturer: IVO Model 57d Serial Number 0
9307 11:45:46.856144 Made week 0 of 2020
9308 11:45:46.858996 EDID version: 1.4
9309 11:45:46.859074 Digital display
9310 11:45:46.862152 6 bits per primary color channel
9311 11:45:46.865130 DisplayPort interface
9312 11:45:46.865208 Maximum image size: 31 cm x 17 cm
9313 11:45:46.868892 Gamma: 220%
9314 11:45:46.868995 Check DPMS levels
9315 11:45:46.875247 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9316 11:45:46.878515 First detailed timing is preferred timing
9317 11:45:46.881617 Established timings supported:
9318 11:45:46.881695 Standard timings supported:
9319 11:45:46.884735 Detailed timings
9320 11:45:46.888829 Hex of detail: 383680a07038204018303c0035ae10000019
9321 11:45:46.894988 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9322 11:45:46.897914 0780 0798 07c8 0820 hborder 0
9323 11:45:46.901677 0438 043b 0447 0458 vborder 0
9324 11:45:46.904774 -hsync -vsync
9325 11:45:46.904872 Did detailed timing
9326 11:45:46.911450 Hex of detail: 000000000000000000000000000000000000
9327 11:45:46.914505 Manufacturer-specified data, tag 0
9328 11:45:46.918077 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9329 11:45:46.921109 ASCII string: InfoVision
9330 11:45:46.924746 Hex of detail: 000000fe00523134304e574635205248200a
9331 11:45:46.927621 ASCII string: R140NWF5 RH
9332 11:45:46.927748 Checksum
9333 11:45:46.931128 Checksum: 0xfb (valid)
9334 11:45:46.934671 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9335 11:45:46.937450 DSI data_rate: 832800000 bps
9336 11:45:46.944249 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9337 11:45:46.947327 anx7625_parse_edid: pixelclock(138800).
9338 11:45:46.950895 hactive(1920), hsync(48), hfp(24), hbp(88)
9339 11:45:46.953898 vactive(1080), vsync(12), vfp(3), vbp(17)
9340 11:45:46.957397 anx7625_dsi_config: config dsi.
9341 11:45:46.964489 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9342 11:45:46.978131 anx7625_dsi_config: success to config DSI
9343 11:45:46.981946 anx7625_dp_start: MIPI phy setup OK.
9344 11:45:46.985092 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9345 11:45:46.988301 mtk_ddp_mode_set invalid vrefresh 60
9346 11:45:46.991971 main_disp_path_setup
9347 11:45:46.992079 ovl_layer_smi_id_en
9348 11:45:46.994984 ovl_layer_smi_id_en
9349 11:45:46.995065 ccorr_config
9350 11:45:46.995129 aal_config
9351 11:45:46.998004 gamma_config
9352 11:45:46.998101 postmask_config
9353 11:45:47.001683 dither_config
9354 11:45:47.004708 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9355 11:45:47.011321 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9356 11:45:47.014884 Root Device init finished in 551 msecs
9357 11:45:47.017731 CPU_CLUSTER: 0 init
9358 11:45:47.024810 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9359 11:45:47.031256 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9360 11:45:47.031337 APU_MBOX 0x190000b0 = 0x10001
9361 11:45:47.034222 APU_MBOX 0x190001b0 = 0x10001
9362 11:45:47.037743 APU_MBOX 0x190005b0 = 0x10001
9363 11:45:47.040835 APU_MBOX 0x190006b0 = 0x10001
9364 11:45:47.047574 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9365 11:45:47.057388 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9366 11:45:47.069826 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9367 11:45:47.076002 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9368 11:45:47.087990 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9369 11:45:47.097191 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9370 11:45:47.100414 CPU_CLUSTER: 0 init finished in 81 msecs
9371 11:45:47.103423 Devices initialized
9372 11:45:47.107180 Show all devs... After init.
9373 11:45:47.107260 Root Device: enabled 1
9374 11:45:47.110108 CPU_CLUSTER: 0: enabled 1
9375 11:45:47.113851 CPU: 00: enabled 1
9376 11:45:47.116871 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9377 11:45:47.120398 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9378 11:45:47.123239 ELOG: NV offset 0x57f000 size 0x1000
9379 11:45:47.130409 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9380 11:45:47.136858 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9381 11:45:47.140384 ELOG: Event(17) added with size 13 at 2023-06-15 11:45:47 UTC
9382 11:45:47.146802 out: cmd=0x121: 03 db 21 01 00 00 00 00
9383 11:45:47.149707 in-header: 03 3f 00 00 2c 00 00 00
9384 11:45:47.159773 in-data: 1f 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9385 11:45:47.166255 ELOG: Event(A1) added with size 10 at 2023-06-15 11:45:47 UTC
9386 11:45:47.173227 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9387 11:45:47.179433 ELOG: Event(A0) added with size 9 at 2023-06-15 11:45:47 UTC
9388 11:45:47.183149 elog_add_boot_reason: Logged dev mode boot
9389 11:45:47.189473 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9390 11:45:47.189544 Finalize devices...
9391 11:45:47.192446 Devices finalized
9392 11:45:47.195807 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9393 11:45:47.199402 Writing coreboot table at 0xffe64000
9394 11:45:47.202429 0. 000000000010a000-0000000000113fff: RAMSTAGE
9395 11:45:47.209206 1. 0000000040000000-00000000400fffff: RAM
9396 11:45:47.212768 2. 0000000040100000-000000004032afff: RAMSTAGE
9397 11:45:47.216424 3. 000000004032b000-00000000545fffff: RAM
9398 11:45:47.219638 4. 0000000054600000-000000005465ffff: BL31
9399 11:45:47.222573 5. 0000000054660000-00000000ffe63fff: RAM
9400 11:45:47.229073 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9401 11:45:47.232806 7. 0000000100000000-000000023fffffff: RAM
9402 11:45:47.235719 Passing 5 GPIOs to payload:
9403 11:45:47.239142 NAME | PORT | POLARITY | VALUE
9404 11:45:47.245546 EC in RW | 0x000000aa | low | undefined
9405 11:45:47.249240 EC interrupt | 0x00000005 | low | undefined
9406 11:45:47.252234 TPM interrupt | 0x000000ab | high | undefined
9407 11:45:47.259074 SD card detect | 0x00000011 | high | undefined
9408 11:45:47.262330 speaker enable | 0x00000093 | high | undefined
9409 11:45:47.265331 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9410 11:45:47.268391 in-header: 03 f9 00 00 02 00 00 00
9411 11:45:47.272198 in-data: 02 00
9412 11:45:47.275377 ADC[4]: Raw value=894081 ID=7
9413 11:45:47.278778 ADC[3]: Raw value=213810 ID=1
9414 11:45:47.278887 RAM Code: 0x71
9415 11:45:47.281674 ADC[6]: Raw value=74722 ID=0
9416 11:45:47.285435 ADC[5]: Raw value=212330 ID=1
9417 11:45:47.285518 SKU Code: 0x1
9418 11:45:47.291533 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9419 11:45:47.291612 coreboot table: 964 bytes.
9420 11:45:47.295307 IMD ROOT 0. 0xfffff000 0x00001000
9421 11:45:47.298432 IMD SMALL 1. 0xffffe000 0x00001000
9422 11:45:47.301623 RO MCACHE 2. 0xffffc000 0x00001104
9423 11:45:47.304866 CONSOLE 3. 0xfff7c000 0x00080000
9424 11:45:47.308046 FMAP 4. 0xfff7b000 0x00000452
9425 11:45:47.311700 TIME STAMP 5. 0xfff7a000 0x00000910
9426 11:45:47.314732 VBOOT WORK 6. 0xfff66000 0x00014000
9427 11:45:47.317969 RAMOOPS 7. 0xffe66000 0x00100000
9428 11:45:47.320943 COREBOOT 8. 0xffe64000 0x00002000
9429 11:45:47.324690 IMD small region:
9430 11:45:47.327702 IMD ROOT 0. 0xffffec00 0x00000400
9431 11:45:47.331285 VPD 1. 0xffffeba0 0x0000004c
9432 11:45:47.334117 MMC STATUS 2. 0xffffeb80 0x00000004
9433 11:45:47.341253 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9434 11:45:47.341359 Probing TPM: done!
9435 11:45:47.347717 Connected to device vid:did:rid of 1ae0:0028:00
9436 11:45:47.354162 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9437 11:45:47.357737 Initialized TPM device CR50 revision 0
9438 11:45:47.361135 Checking cr50 for pending updates
9439 11:45:47.366727 Reading cr50 TPM mode
9440 11:45:47.375533 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9441 11:45:47.381866 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9442 11:45:47.422122 read SPI 0x3990ec 0x4f1b0: 34861 us, 9294 KB/s, 74.352 Mbps
9443 11:45:47.425359 Checking segment from ROM address 0x40100000
9444 11:45:47.428348 Checking segment from ROM address 0x4010001c
9445 11:45:47.435203 Loading segment from ROM address 0x40100000
9446 11:45:47.435305 code (compression=0)
9447 11:45:47.445629 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9448 11:45:47.451786 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9449 11:45:47.451870 it's not compressed!
9450 11:45:47.458572 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9451 11:45:47.465143 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9452 11:45:47.482601 Loading segment from ROM address 0x4010001c
9453 11:45:47.482685 Entry Point 0x80000000
9454 11:45:47.485544 Loaded segments
9455 11:45:47.489208 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9456 11:45:47.495344 Jumping to boot code at 0x80000000(0xffe64000)
9457 11:45:47.502070 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9458 11:45:47.509044 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9459 11:45:47.516979 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9460 11:45:47.520025 Checking segment from ROM address 0x40100000
9461 11:45:47.523712 Checking segment from ROM address 0x4010001c
9462 11:45:47.529963 Loading segment from ROM address 0x40100000
9463 11:45:47.530045 code (compression=1)
9464 11:45:47.536856 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9465 11:45:47.546347 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9466 11:45:47.546446 using LZMA
9467 11:45:47.555276 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9468 11:45:47.561760 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9469 11:45:47.564713 Loading segment from ROM address 0x4010001c
9470 11:45:47.568236 Entry Point 0x54601000
9471 11:45:47.568312 Loaded segments
9472 11:45:47.571782 NOTICE: MT8192 bl31_setup
9473 11:45:47.579120 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9474 11:45:47.582277 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9475 11:45:47.585436 WARNING: region 0:
9476 11:45:47.589153 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 11:45:47.589240 WARNING: region 1:
9478 11:45:47.595874 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9479 11:45:47.599057 WARNING: region 2:
9480 11:45:47.602027 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9481 11:45:47.605249 WARNING: region 3:
9482 11:45:47.608972 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 11:45:47.612099 WARNING: region 4:
9484 11:45:47.618736 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 11:45:47.618818 WARNING: region 5:
9486 11:45:47.621823 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 11:45:47.625703 WARNING: region 6:
9488 11:45:47.628820 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 11:45:47.631964 WARNING: region 7:
9490 11:45:47.635019 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 11:45:47.641904 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9492 11:45:47.644922 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9493 11:45:47.648565 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9494 11:45:47.655167 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9495 11:45:47.658667 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9496 11:45:47.665244 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9497 11:45:47.668389 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9498 11:45:47.671892 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9499 11:45:47.678510 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9500 11:45:47.681570 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9501 11:45:47.684719 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9502 11:45:47.691705 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9503 11:45:47.694653 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9504 11:45:47.701307 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9505 11:45:47.705016 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9506 11:45:47.708163 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9507 11:45:47.714957 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9508 11:45:47.718097 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9509 11:45:47.721236 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9510 11:45:47.728103 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9511 11:45:47.731312 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9512 11:45:47.738080 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9513 11:45:47.741223 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9514 11:45:47.745165 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9515 11:45:47.751180 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9516 11:45:47.754593 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9517 11:45:47.761094 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9518 11:45:47.764614 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9519 11:45:47.770957 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9520 11:45:47.774482 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9521 11:45:47.777924 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9522 11:45:47.784505 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9523 11:45:47.787410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9524 11:45:47.790965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9525 11:45:47.794188 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9526 11:45:47.800840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9527 11:45:47.804397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9528 11:45:47.807572 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9529 11:45:47.810691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9530 11:45:47.817263 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9531 11:45:47.820997 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9532 11:45:47.824142 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9533 11:45:47.827219 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9534 11:45:47.834019 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9535 11:45:47.837598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9536 11:45:47.840706 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9537 11:45:47.847546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9538 11:45:47.850617 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9539 11:45:47.853790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9540 11:45:47.860481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9541 11:45:47.863970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9542 11:45:47.870336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9543 11:45:47.873547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9544 11:45:47.877133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9545 11:45:47.883907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9546 11:45:47.887070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9547 11:45:47.893492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9548 11:45:47.896992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9549 11:45:47.903680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9550 11:45:47.906607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9551 11:45:47.913569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9552 11:45:47.916701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9553 11:45:47.920135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9554 11:45:47.927019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9555 11:45:47.930035 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9556 11:45:47.936411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9557 11:45:47.940037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9558 11:45:47.946285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9559 11:45:47.950038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9560 11:45:47.953161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9561 11:45:47.959484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9562 11:45:47.963191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9563 11:45:47.969475 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9564 11:45:47.973080 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9565 11:45:47.980085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9566 11:45:47.983148 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9567 11:45:47.989626 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9568 11:45:47.993251 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9569 11:45:47.996132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9570 11:45:48.002885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9571 11:45:48.006428 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9572 11:45:48.012947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9573 11:45:48.016138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9574 11:45:48.023068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9575 11:45:48.026217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9576 11:45:48.029168 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9577 11:45:48.036034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9578 11:45:48.039268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9579 11:45:48.045959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9580 11:45:48.049129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9581 11:45:48.055951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9582 11:45:48.059202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9583 11:45:48.066103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9584 11:45:48.069237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9585 11:45:48.072918 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9586 11:45:48.079063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9587 11:45:48.082557 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9588 11:45:48.086215 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9589 11:45:48.092632 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9590 11:45:48.095785 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9591 11:45:48.099355 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9592 11:45:48.105904 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9593 11:45:48.109381 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9594 11:45:48.112324 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9595 11:45:48.118987 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9596 11:45:48.122039 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9597 11:45:48.128901 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9598 11:45:48.132670 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9599 11:45:48.135635 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9600 11:45:48.142413 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9601 11:45:48.145440 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9602 11:45:48.152421 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9603 11:45:48.155497 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9604 11:45:48.158725 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9605 11:45:48.165501 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9606 11:45:48.168707 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9607 11:45:48.172312 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9608 11:45:48.178671 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9609 11:45:48.182125 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9610 11:45:48.185175 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9611 11:45:48.192239 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9612 11:45:48.195287 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9613 11:45:48.198710 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9614 11:45:48.202171 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9615 11:45:48.208677 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9616 11:45:48.211641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9617 11:45:48.218406 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9618 11:45:48.222042 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9619 11:45:48.225008 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9620 11:45:48.231732 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9621 11:45:48.234934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9622 11:45:48.241597 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9623 11:45:48.244736 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9624 11:45:48.248360 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9625 11:45:48.255226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9626 11:45:48.258373 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9627 11:45:48.264707 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9628 11:45:48.268056 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9629 11:45:48.271684 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9630 11:45:48.277932 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9631 11:45:48.281664 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9632 11:45:48.284662 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9633 11:45:48.291235 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9634 11:45:48.294785 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9635 11:45:48.301316 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9636 11:45:48.304938 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9637 11:45:48.307936 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9638 11:45:48.314777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9639 11:45:48.317964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9640 11:45:48.324516 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9641 11:45:48.328085 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9642 11:45:48.331569 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9643 11:45:48.337806 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9644 11:45:48.341401 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9645 11:45:48.348115 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9646 11:45:48.351109 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9647 11:45:48.354169 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9648 11:45:48.361113 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9649 11:45:48.364161 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9650 11:45:48.370932 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9651 11:45:48.374645 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9652 11:45:48.377864 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9653 11:45:48.384097 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9654 11:45:48.387852 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9655 11:45:48.394010 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9656 11:45:48.397655 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9657 11:45:48.400622 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9658 11:45:48.407258 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9659 11:45:48.410670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9660 11:45:48.417163 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9661 11:45:48.420747 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9662 11:45:48.423811 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9663 11:45:48.430235 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9664 11:45:48.433372 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9665 11:45:48.440429 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9666 11:45:48.443461 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9667 11:45:48.446448 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9668 11:45:48.453218 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9669 11:45:48.456378 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9670 11:45:48.463310 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9671 11:45:48.466514 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9672 11:45:48.469666 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9673 11:45:48.476661 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9674 11:45:48.479766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9675 11:45:48.486483 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9676 11:45:48.489527 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9677 11:45:48.492667 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9678 11:45:48.499564 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9679 11:45:48.502688 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9680 11:45:48.509192 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9681 11:45:48.512706 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9682 11:45:48.519356 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9683 11:45:48.522361 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9684 11:45:48.525940 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9685 11:45:48.532530 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9686 11:45:48.535394 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9687 11:45:48.542050 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9688 11:45:48.545564 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9689 11:45:48.551837 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9690 11:45:48.555423 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9691 11:45:48.558488 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9692 11:45:48.565141 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9693 11:45:48.568195 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9694 11:45:48.575115 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9695 11:45:48.578236 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9696 11:45:48.584565 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9697 11:45:48.588443 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9698 11:45:48.591629 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9699 11:45:48.597963 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9700 11:45:48.601118 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9701 11:45:48.607967 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9702 11:45:48.610921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9703 11:45:48.617970 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9704 11:45:48.621054 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9705 11:45:48.624325 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9706 11:45:48.631266 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9707 11:45:48.634223 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9708 11:45:48.640860 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9709 11:45:48.643845 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9710 11:45:48.650484 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9711 11:45:48.653946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9712 11:45:48.656983 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9713 11:45:48.663667 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9714 11:45:48.667182 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9715 11:45:48.673973 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9716 11:45:48.677087 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9717 11:45:48.683885 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9718 11:45:48.687012 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9719 11:45:48.690098 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9720 11:45:48.696837 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9721 11:45:48.699915 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9722 11:45:48.703718 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9723 11:45:48.706842 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9724 11:45:48.713101 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9725 11:45:48.716692 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9726 11:45:48.719795 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9727 11:45:48.726178 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9728 11:45:48.729828 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9729 11:45:48.733339 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9730 11:45:48.739706 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9731 11:45:48.742804 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9732 11:45:48.749437 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9733 11:45:48.752487 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9734 11:45:48.756233 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9735 11:45:48.762597 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9736 11:45:48.765699 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9737 11:45:48.772391 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9738 11:45:48.776044 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9739 11:45:48.778977 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9740 11:45:48.785863 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9741 11:45:48.789144 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9742 11:45:48.792298 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9743 11:45:48.799159 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9744 11:45:48.802224 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9745 11:45:48.805335 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9746 11:45:48.812115 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9747 11:45:48.815351 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9748 11:45:48.822054 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9749 11:45:48.825127 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9750 11:45:48.828098 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9751 11:45:48.835287 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9752 11:45:48.838225 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9753 11:45:48.844678 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9754 11:45:48.847982 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9755 11:45:48.851625 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9756 11:45:48.857888 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9757 11:45:48.861072 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9758 11:45:48.867630 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9759 11:45:48.871072 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9760 11:45:48.874641 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9761 11:45:48.877905 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9762 11:45:48.880835 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9763 11:45:48.887448 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9764 11:45:48.890718 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9765 11:45:48.894470 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9766 11:45:48.897611 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9767 11:45:48.903851 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9768 11:45:48.907574 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9769 11:45:48.910704 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9770 11:45:48.913923 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9771 11:45:48.920795 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9772 11:45:48.924014 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9773 11:45:48.930575 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9774 11:45:48.933567 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9775 11:45:48.937127 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9776 11:45:48.943857 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9777 11:45:48.946942 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9778 11:45:48.953328 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9779 11:45:48.956981 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9780 11:45:48.960063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9781 11:45:48.966403 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9782 11:45:48.970147 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9783 11:45:48.976659 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9784 11:45:48.979671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9785 11:45:48.986566 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9786 11:45:48.989619 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9787 11:45:48.996459 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9788 11:45:48.999566 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9789 11:45:49.002691 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9790 11:45:49.009590 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9791 11:45:49.012834 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9792 11:45:49.019044 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9793 11:45:49.022799 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9794 11:45:49.025976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9795 11:45:49.032088 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9796 11:45:49.036081 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9797 11:45:49.042275 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9798 11:45:49.045260 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9799 11:45:49.051879 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9800 11:45:49.055526 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9801 11:45:49.058430 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9802 11:45:49.064955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9803 11:45:49.068754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9804 11:45:49.074993 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9805 11:45:49.078069 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9806 11:45:49.084612 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9807 11:45:49.088286 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9808 11:45:49.091305 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9809 11:45:49.097810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9810 11:45:49.100998 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9811 11:45:49.107675 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9812 11:45:49.111474 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9813 11:45:49.114713 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9814 11:45:49.121042 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9815 11:45:49.124717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9816 11:45:49.130911 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9817 11:45:49.134640 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9818 11:45:49.140822 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9819 11:45:49.144555 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9820 11:45:49.147825 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9821 11:45:49.154190 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9822 11:45:49.157089 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9823 11:45:49.163787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9824 11:45:49.167104 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9825 11:45:49.173900 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9826 11:45:49.176994 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9827 11:45:49.180632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9828 11:45:49.186747 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9829 11:45:49.190154 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9830 11:45:49.197029 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9831 11:45:49.199901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9832 11:45:49.203705 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9833 11:45:49.209810 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9834 11:45:49.213009 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9835 11:45:49.219671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9836 11:45:49.222845 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9837 11:45:49.229895 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9838 11:45:49.232952 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9839 11:45:49.236077 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9840 11:45:49.243084 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9841 11:45:49.246225 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9842 11:45:49.252811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9843 11:45:49.256229 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9844 11:45:49.259179 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9845 11:45:49.266149 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9846 11:45:49.269145 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9847 11:45:49.275600 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9848 11:45:49.279051 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9849 11:45:49.285797 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9850 11:45:49.289063 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9851 11:45:49.295835 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9852 11:45:49.298649 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9853 11:45:49.302331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9854 11:45:49.308493 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9855 11:45:49.312060 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9856 11:45:49.318727 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9857 11:45:49.321858 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9858 11:45:49.328197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9859 11:45:49.331921 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9860 11:45:49.338251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9861 11:45:49.341849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9862 11:45:49.345150 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9863 11:45:49.351451 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9864 11:45:49.354549 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9865 11:45:49.361629 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9866 11:45:49.364436 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9867 11:45:49.371049 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9868 11:45:49.374709 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9869 11:45:49.381223 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9870 11:45:49.384200 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9871 11:45:49.390948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9872 11:45:49.394076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9873 11:45:49.397608 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9874 11:45:49.404485 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9875 11:45:49.407647 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9876 11:45:49.414314 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9877 11:45:49.417405 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9878 11:45:49.424236 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9879 11:45:49.427333 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9880 11:45:49.434121 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9881 11:45:49.437309 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9882 11:45:49.440546 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9883 11:45:49.447342 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9884 11:45:49.450426 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9885 11:45:49.457193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9886 11:45:49.460272 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9887 11:45:49.466947 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9888 11:45:49.470362 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9889 11:45:49.476401 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9890 11:45:49.479874 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9891 11:45:49.483545 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9892 11:45:49.490101 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9893 11:45:49.493416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9894 11:45:49.500063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9895 11:45:49.502949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9896 11:45:49.509999 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9897 11:45:49.512815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9898 11:45:49.519366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9899 11:45:49.523282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9900 11:45:49.526150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9901 11:45:49.532555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9902 11:45:49.536376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9903 11:45:49.542559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9904 11:45:49.545724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9905 11:45:49.552506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9906 11:45:49.555588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9907 11:45:49.562470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9908 11:45:49.565636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9909 11:45:49.572368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9910 11:45:49.575400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9911 11:45:49.582009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9912 11:45:49.584995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9913 11:45:49.592044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9914 11:45:49.598511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9915 11:45:49.601600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9916 11:45:49.608187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9917 11:45:49.611388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9918 11:45:49.618092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9919 11:45:49.621203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9920 11:45:49.628088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9921 11:45:49.631153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9922 11:45:49.638011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9923 11:45:49.641164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9924 11:45:49.648050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9925 11:45:49.651225 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9926 11:45:49.654238 INFO: [APUAPC] vio 0
9927 11:45:49.658086 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9928 11:45:49.664564 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9929 11:45:49.667797 INFO: [APUAPC] D0_APC_0: 0x400510
9930 11:45:49.668251 INFO: [APUAPC] D0_APC_1: 0x0
9931 11:45:49.671242 INFO: [APUAPC] D0_APC_2: 0x1540
9932 11:45:49.674710 INFO: [APUAPC] D0_APC_3: 0x0
9933 11:45:49.677631 INFO: [APUAPC] D1_APC_0: 0xffffffff
9934 11:45:49.681377 INFO: [APUAPC] D1_APC_1: 0xffffffff
9935 11:45:49.684468 INFO: [APUAPC] D1_APC_2: 0x3fffff
9936 11:45:49.687327 INFO: [APUAPC] D1_APC_3: 0x0
9937 11:45:49.690929 INFO: [APUAPC] D2_APC_0: 0xffffffff
9938 11:45:49.694546 INFO: [APUAPC] D2_APC_1: 0xffffffff
9939 11:45:49.697479 INFO: [APUAPC] D2_APC_2: 0x3fffff
9940 11:45:49.700922 INFO: [APUAPC] D2_APC_3: 0x0
9941 11:45:49.704088 INFO: [APUAPC] D3_APC_0: 0xffffffff
9942 11:45:49.707462 INFO: [APUAPC] D3_APC_1: 0xffffffff
9943 11:45:49.710369 INFO: [APUAPC] D3_APC_2: 0x3fffff
9944 11:45:49.713665 INFO: [APUAPC] D3_APC_3: 0x0
9945 11:45:49.717511 INFO: [APUAPC] D4_APC_0: 0xffffffff
9946 11:45:49.720637 INFO: [APUAPC] D4_APC_1: 0xffffffff
9947 11:45:49.724117 INFO: [APUAPC] D4_APC_2: 0x3fffff
9948 11:45:49.727143 INFO: [APUAPC] D4_APC_3: 0x0
9949 11:45:49.730870 INFO: [APUAPC] D5_APC_0: 0xffffffff
9950 11:45:49.733899 INFO: [APUAPC] D5_APC_1: 0xffffffff
9951 11:45:49.737090 INFO: [APUAPC] D5_APC_2: 0x3fffff
9952 11:45:49.740153 INFO: [APUAPC] D5_APC_3: 0x0
9953 11:45:49.743886 INFO: [APUAPC] D6_APC_0: 0xffffffff
9954 11:45:49.746952 INFO: [APUAPC] D6_APC_1: 0xffffffff
9955 11:45:49.750056 INFO: [APUAPC] D6_APC_2: 0x3fffff
9956 11:45:49.753799 INFO: [APUAPC] D6_APC_3: 0x0
9957 11:45:49.756752 INFO: [APUAPC] D7_APC_0: 0xffffffff
9958 11:45:49.759875 INFO: [APUAPC] D7_APC_1: 0xffffffff
9959 11:45:49.763631 INFO: [APUAPC] D7_APC_2: 0x3fffff
9960 11:45:49.766784 INFO: [APUAPC] D7_APC_3: 0x0
9961 11:45:49.769922 INFO: [APUAPC] D8_APC_0: 0xffffffff
9962 11:45:49.773070 INFO: [APUAPC] D8_APC_1: 0xffffffff
9963 11:45:49.776253 INFO: [APUAPC] D8_APC_2: 0x3fffff
9964 11:45:49.779956 INFO: [APUAPC] D8_APC_3: 0x0
9965 11:45:49.782803 INFO: [APUAPC] D9_APC_0: 0xffffffff
9966 11:45:49.786527 INFO: [APUAPC] D9_APC_1: 0xffffffff
9967 11:45:49.789718 INFO: [APUAPC] D9_APC_2: 0x3fffff
9968 11:45:49.792887 INFO: [APUAPC] D9_APC_3: 0x0
9969 11:45:49.796342 INFO: [APUAPC] D10_APC_0: 0xffffffff
9970 11:45:49.799295 INFO: [APUAPC] D10_APC_1: 0xffffffff
9971 11:45:49.802944 INFO: [APUAPC] D10_APC_2: 0x3fffff
9972 11:45:49.805958 INFO: [APUAPC] D10_APC_3: 0x0
9973 11:45:49.809372 INFO: [APUAPC] D11_APC_0: 0xffffffff
9974 11:45:49.812486 INFO: [APUAPC] D11_APC_1: 0xffffffff
9975 11:45:49.816271 INFO: [APUAPC] D11_APC_2: 0x3fffff
9976 11:45:49.819202 INFO: [APUAPC] D11_APC_3: 0x0
9977 11:45:49.822816 INFO: [APUAPC] D12_APC_0: 0xffffffff
9978 11:45:49.825774 INFO: [APUAPC] D12_APC_1: 0xffffffff
9979 11:45:49.829316 INFO: [APUAPC] D12_APC_2: 0x3fffff
9980 11:45:49.832435 INFO: [APUAPC] D12_APC_3: 0x0
9981 11:45:49.835391 INFO: [APUAPC] D13_APC_0: 0xffffffff
9982 11:45:49.839068 INFO: [APUAPC] D13_APC_1: 0xffffffff
9983 11:45:49.842123 INFO: [APUAPC] D13_APC_2: 0x3fffff
9984 11:45:49.845310 INFO: [APUAPC] D13_APC_3: 0x0
9985 11:45:49.849111 INFO: [APUAPC] D14_APC_0: 0xffffffff
9986 11:45:49.852124 INFO: [APUAPC] D14_APC_1: 0xffffffff
9987 11:45:49.855153 INFO: [APUAPC] D14_APC_2: 0x3fffff
9988 11:45:49.858911 INFO: [APUAPC] D14_APC_3: 0x0
9989 11:45:49.862109 INFO: [APUAPC] D15_APC_0: 0xffffffff
9990 11:45:49.865197 INFO: [APUAPC] D15_APC_1: 0xffffffff
9991 11:45:49.868875 INFO: [APUAPC] D15_APC_2: 0x3fffff
9992 11:45:49.871941 INFO: [APUAPC] D15_APC_3: 0x0
9993 11:45:49.874934 INFO: [APUAPC] APC_CON: 0x4
9994 11:45:49.878890 INFO: [NOCDAPC] D0_APC_0: 0x0
9995 11:45:49.882123 INFO: [NOCDAPC] D0_APC_1: 0x0
9996 11:45:49.885325 INFO: [NOCDAPC] D1_APC_0: 0x0
9997 11:45:49.888081 INFO: [NOCDAPC] D1_APC_1: 0xfff
9998 11:45:49.892199 INFO: [NOCDAPC] D2_APC_0: 0x0
9999 11:45:49.892758 INFO: [NOCDAPC] D2_APC_1: 0xfff
10000 11:45:49.895054 INFO: [NOCDAPC] D3_APC_0: 0x0
10001 11:45:49.898165 INFO: [NOCDAPC] D3_APC_1: 0xfff
10002 11:45:49.901369 INFO: [NOCDAPC] D4_APC_0: 0x0
10003 11:45:49.905039 INFO: [NOCDAPC] D4_APC_1: 0xfff
10004 11:45:49.907760 INFO: [NOCDAPC] D5_APC_0: 0x0
10005 11:45:49.911325 INFO: [NOCDAPC] D5_APC_1: 0xfff
10006 11:45:49.914551 INFO: [NOCDAPC] D6_APC_0: 0x0
10007 11:45:49.918191 INFO: [NOCDAPC] D6_APC_1: 0xfff
10008 11:45:49.920955 INFO: [NOCDAPC] D7_APC_0: 0x0
10009 11:45:49.924556 INFO: [NOCDAPC] D7_APC_1: 0xfff
10010 11:45:49.925017 INFO: [NOCDAPC] D8_APC_0: 0x0
10011 11:45:49.928151 INFO: [NOCDAPC] D8_APC_1: 0xfff
10012 11:45:49.930965 INFO: [NOCDAPC] D9_APC_0: 0x0
10013 11:45:49.934389 INFO: [NOCDAPC] D9_APC_1: 0xfff
10014 11:45:49.938081 INFO: [NOCDAPC] D10_APC_0: 0x0
10015 11:45:49.941075 INFO: [NOCDAPC] D10_APC_1: 0xfff
10016 11:45:49.944125 INFO: [NOCDAPC] D11_APC_0: 0x0
10017 11:45:49.948210 INFO: [NOCDAPC] D11_APC_1: 0xfff
10018 11:45:49.951009 INFO: [NOCDAPC] D12_APC_0: 0x0
10019 11:45:49.954022 INFO: [NOCDAPC] D12_APC_1: 0xfff
10020 11:45:49.957629 INFO: [NOCDAPC] D13_APC_0: 0x0
10021 11:45:49.960804 INFO: [NOCDAPC] D13_APC_1: 0xfff
10022 11:45:49.963814 INFO: [NOCDAPC] D14_APC_0: 0x0
10023 11:45:49.967473 INFO: [NOCDAPC] D14_APC_1: 0xfff
10024 11:45:49.970622 INFO: [NOCDAPC] D15_APC_0: 0x0
10025 11:45:49.973802 INFO: [NOCDAPC] D15_APC_1: 0xfff
10026 11:45:49.976936 INFO: [NOCDAPC] APC_CON: 0x4
10027 11:45:49.980118 INFO: [APUAPC] set_apusys_apc done
10028 11:45:49.980531 INFO: [DEVAPC] devapc_init done
10029 11:45:49.987095 INFO: GICv3 without legacy support detected.
10030 11:45:49.990057 INFO: ARM GICv3 driver initialized in EL3
10031 11:45:49.993225 INFO: Maximum SPI INTID supported: 639
10032 11:45:49.997012 INFO: BL31: Initializing runtime services
10033 11:45:50.003343 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10034 11:45:50.006886 INFO: SPM: enable CPC mode
10035 11:45:50.009945 INFO: mcdi ready for mcusys-off-idle and system suspend
10036 11:45:50.016421 INFO: BL31: Preparing for EL3 exit to normal world
10037 11:45:50.019850 INFO: Entry point address = 0x80000000
10038 11:45:50.023177 INFO: SPSR = 0x8
10039 11:45:50.027333
10040 11:45:50.027929
10041 11:45:50.028441
10042 11:45:50.030671 Starting depthcharge on Spherion...
10043 11:45:50.031233
10044 11:45:50.031599 Wipe memory regions:
10045 11:45:50.031935
10046 11:45:50.034413 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10047 11:45:50.034994 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 11:45:50.035454 Setting prompt string to ['asurada:']
10049 11:45:50.035856 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 11:45:50.036603 [0x00000040000000, 0x00000054600000)
10051 11:45:50.156320
10052 11:45:50.156780 [0x00000054660000, 0x00000080000000)
10053 11:45:50.416875
10054 11:45:50.417430 [0x000000821a7280, 0x000000ffe64000)
10055 11:45:51.161711
10056 11:45:51.162244 [0x00000100000000, 0x00000240000000)
10057 11:45:53.051449
10058 11:45:53.054114 Initializing XHCI USB controller at 0x11200000.
10059 11:45:54.092162
10060 11:45:54.095310 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10061 11:45:54.095932
10062 11:45:54.096463
10063 11:45:54.096970
10064 11:45:54.097952 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 11:45:54.199495 asurada: tftpboot 192.168.201.1 10742256/tftp-deploy-35vbjk6z/kernel/image.itb 10742256/tftp-deploy-35vbjk6z/kernel/cmdline
10067 11:45:54.200175 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 11:45:54.200775 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 11:45:54.204951 tftpboot 192.168.201.1 10742256/tftp-deploy-35vbjk6z/kernel/image.itp-deploy-35vbjk6z/kernel/cmdline
10070 11:45:54.205345
10071 11:45:54.205791 Waiting for link
10072 11:45:54.364923
10073 11:45:54.365525 R8152: Initializing
10074 11:45:54.366013
10075 11:45:54.368382 Version 6 (ocp_data = 5c30)
10076 11:45:54.368916
10077 11:45:54.372076 R8152: Done initializing
10078 11:45:54.372621
10079 11:45:54.373124 Adding net device
10080 11:45:56.271743
10081 11:45:56.272332 done.
10082 11:45:56.272704
10083 11:45:56.273034 MAC: 00:24:32:30:78:ff
10084 11:45:56.273358
10085 11:45:56.274584 Sending DHCP discover... done.
10086 11:45:56.275006
10087 11:45:56.277817 Waiting for reply... done.
10088 11:45:56.278266
10089 11:45:56.281491 Sending DHCP request... done.
10090 11:45:56.281902
10091 11:46:01.520955 Waiting for reply... done.
10092 11:46:01.521168
10093 11:46:01.521242 My ip is 192.168.201.21
10094 11:46:01.521303
10095 11:46:01.523687 The DHCP server ip is 192.168.201.1
10096 11:46:01.523769
10097 11:46:01.530346 TFTP server IP predefined by user: 192.168.201.1
10098 11:46:01.530459
10099 11:46:01.536843 Bootfile predefined by user: 10742256/tftp-deploy-35vbjk6z/kernel/image.itb
10100 11:46:01.536931
10101 11:46:01.540466 Sending tftp read request... done.
10102 11:46:01.540554
10103 11:46:01.544436 Waiting for the transfer...
10104 11:46:01.544517
10105 11:46:02.089281 00000000 ################################################################
10106 11:46:02.089461
10107 11:46:02.627341 00080000 ################################################################
10108 11:46:02.627501
10109 11:46:03.156310 00100000 ################################################################
10110 11:46:03.156448
10111 11:46:03.687530 00180000 ################################################################
10112 11:46:03.687664
10113 11:46:04.222509 00200000 ################################################################
10114 11:46:04.222648
10115 11:46:04.765155 00280000 ################################################################
10116 11:46:04.765292
10117 11:46:05.299482 00300000 ################################################################
10118 11:46:05.299648
10119 11:46:06.908037 00380000 ################################################################
10120 11:46:06.908585
10121 11:46:06.908919 00400000 ################################################################
10122 11:46:06.909231
10123 11:46:07.095178 00480000 ################################################################
10124 11:46:07.095328
10125 11:46:07.749664 00500000 ################################################################
10126 11:46:07.750166
10127 11:46:08.321446 00580000 ################################################################
10128 11:46:08.321606
10129 11:46:08.886799 00600000 ################################################################
10130 11:46:08.886982
10131 11:46:09.486335 00680000 ################################################################
10132 11:46:09.486505
10133 11:46:10.074239 00700000 ################################################################
10134 11:46:10.074899
10135 11:46:10.636034 00780000 ################################################################
10136 11:46:10.636181
10137 11:46:11.257712 00800000 ################################################################
10138 11:46:11.258332
10139 11:46:11.847262 00880000 ################################################################
10140 11:46:11.847798
10141 11:46:12.405695 00900000 ################################################################
10142 11:46:12.405888
10143 11:46:13.006946 00980000 ################################################################
10144 11:46:13.007140
10145 11:46:13.660859 00a00000 ################################################################
10146 11:46:13.661040
10147 11:46:14.279076 00a80000 ################################################################
10148 11:46:14.279217
10149 11:46:14.820391 00b00000 ################################################################
10150 11:46:14.820537
10151 11:46:15.384807 00b80000 ################################################################
10152 11:46:15.384975
10153 11:46:15.989109 00c00000 ################################################################
10154 11:46:15.989643
10155 11:46:16.592001 00c80000 ################################################################
10156 11:46:16.592628
10157 11:46:17.188443 00d00000 ################################################################
10158 11:46:17.188608
10159 11:46:17.794850 00d80000 ################################################################
10160 11:46:17.794995
10161 11:46:18.429351 00e00000 ################################################################
10162 11:46:18.429857
10163 11:46:19.068670 00e80000 ################################################################
10164 11:46:19.069316
10165 11:46:19.697417 00f00000 ################################################################
10166 11:46:19.698125
10167 11:46:20.666667 00f80000 ################################################################
10168 11:46:20.667422
10169 11:46:21.022819 01000000 ################################################################
10170 11:46:21.023491
10171 11:46:21.659256 01080000 ################################################################
10172 11:46:21.659887
10173 11:46:22.303053 01100000 ################################################################
10174 11:46:22.303616
10175 11:46:22.945209 01180000 ################################################################
10176 11:46:22.945439
10177 11:46:23.512318 01200000 ################################################################
10178 11:46:23.512880
10179 11:46:25.622624 01280000 ################################################################
10180 11:46:25.623282
10181 11:46:25.623660 01300000 ################################################################
10182 11:46:25.624027
10183 11:46:25.624604 01380000 ################################################################
10184 11:46:25.625005
10185 11:46:25.968496 01400000 ################################################################
10186 11:46:25.968637
10187 11:46:26.543763 01480000 ################################################################
10188 11:46:26.543920
10189 11:46:27.136491 01500000 ################################################################
10190 11:46:27.136633
10191 11:46:27.715503 01580000 ################################################################
10192 11:46:27.715651
10193 11:46:28.274942 01600000 ################################################################
10194 11:46:28.275110
10195 11:46:28.818113 01680000 ################################################################
10196 11:46:28.818308
10197 11:46:29.370282 01700000 ################################################################
10198 11:46:29.370443
10199 11:46:30.036474 01780000 ################################################################
10200 11:46:30.036627
10201 11:46:30.733202 01800000 ################################################################
10202 11:46:30.733348
10203 11:46:31.987061 01880000 ################################################################
10204 11:46:31.987588
10205 11:46:32.125003 01900000 ################################################################
10206 11:46:32.125197
10207 11:46:32.831555 01980000 ################################################################
10208 11:46:32.831702
10209 11:46:33.454017 01a00000 ################################################################
10210 11:46:33.454166
10211 11:46:34.024667 01a80000 ################################################################
10212 11:46:34.024812
10213 11:46:34.653163 01b00000 ################################################################
10214 11:46:34.653342
10215 11:46:35.216977 01b80000 ################################################################
10216 11:46:35.217118
10217 11:46:35.792632 01c00000 ################################################################
10218 11:46:35.792783
10219 11:46:36.420650 01c80000 ################################################################
10220 11:46:36.421129
10221 11:46:39.601173 01d00000 ################################################################
10222 11:46:39.601716
10223 11:46:39.602237 01d80000 ################################################################
10224 11:46:39.602757
10225 11:46:39.603297 01e00000 ################################################################
10226 11:46:39.603781
10227 11:46:39.604271 01e80000 ################################################################
10228 11:46:39.604781
10229 11:46:39.605287 01f00000 ################################################################
10230 11:46:39.605797
10231 11:46:40.161960 01f80000 ################################################################
10232 11:46:40.162115
10233 11:46:40.843864 02000000 ################################################################
10234 11:46:40.844146
10235 11:46:41.505276 02080000 ################################################################
10236 11:46:41.505455
10237 11:46:42.203384 02100000 ################################################################
10238 11:46:42.203558
10239 11:46:42.913873 02180000 ################################################################
10240 11:46:42.914520
10241 11:46:43.558796 02200000 ################################################################
10242 11:46:43.559411
10243 11:46:44.200973 02280000 ################################################################
10244 11:46:44.201479
10245 11:46:44.937089 02300000 ################################################################
10246 11:46:44.937243
10247 11:46:46.302528 02380000 ################################################################
10248 11:46:46.303291
10249 11:46:46.303958 02400000 ################################################################
10250 11:46:46.304635
10251 11:46:46.857708 02480000 ################################################################
10252 11:46:46.858482
10253 11:46:47.637355 02500000 ################################################################
10254 11:46:47.638007
10255 11:46:48.411611 02580000 ################################################################
10256 11:46:48.412290
10257 11:46:49.166637 02600000 ################################################################
10258 11:46:49.166798
10259 11:46:49.875238 02680000 ################################################################
10260 11:46:49.875378
10261 11:46:50.533916 02700000 ################################################################
10262 11:46:50.534453
10263 11:46:51.173754 02780000 ################################################################
10264 11:46:51.174240
10265 11:46:51.816150 02800000 ################################################################
10266 11:46:51.816652
10267 11:46:52.464746 02880000 ################################################################
10268 11:46:52.465496
10269 11:46:53.121676 02900000 ################################################################
10270 11:46:53.122391
10271 11:46:53.785320 02980000 ################################################################
10272 11:46:53.785893
10273 11:46:54.420927 02a00000 ################################################################
10274 11:46:54.421483
10275 11:46:55.082623 02a80000 ################################################################
10276 11:46:55.083206
10277 11:46:55.776012 02b00000 ################################################################
10278 11:46:55.776157
10279 11:46:56.415507 02b80000 ################################################################
10280 11:46:56.415656
10281 11:46:57.047459 02c00000 ################################################################
10282 11:46:57.047665
10283 11:46:57.701565 02c80000 ################################################################
10284 11:46:57.701702
10285 11:46:58.339208 02d00000 ################################################################
10286 11:46:58.339385
10287 11:46:58.927466 02d80000 ################################################################
10288 11:46:58.927612
10289 11:46:59.463837 02e00000 ################################################################
10290 11:46:59.463984
10291 11:47:00.000651 02e80000 ################################################################
10292 11:47:00.000793
10293 11:47:00.545724 02f00000 ################################################################
10294 11:47:00.545861
10295 11:47:01.113294 02f80000 ################################################################
10296 11:47:01.113435
10297 11:47:01.709238 03000000 ################################################################
10298 11:47:01.709380
10299 11:47:02.267959 03080000 ################################################################
10300 11:47:02.268109
10301 11:47:02.889781 03100000 ################################################################
10302 11:47:02.889955
10303 11:47:03.521689 03180000 ################################################################
10304 11:47:03.521836
10305 11:47:04.148412 03200000 ################################################################
10306 11:47:04.148552
10307 11:47:04.770717 03280000 ################################################################
10308 11:47:04.770858
10309 11:47:05.325803 03300000 ################################################################
10310 11:47:05.326326
10311 11:47:05.917231 03380000 ################################################################
10312 11:47:05.917870
10313 11:47:06.500197 03400000 ################################################################
10314 11:47:06.500710
10315 11:47:07.097134 03480000 ################################################################
10316 11:47:07.097743
10317 11:47:07.676722 03500000 ################################################################
10318 11:47:07.676872
10319 11:47:08.241238 03580000 ################################################################
10320 11:47:08.241416
10321 11:47:08.953090 03600000 ################################################################
10322 11:47:08.953664
10323 11:47:09.728872 03680000 ################################################################
10324 11:47:09.729209
10325 11:47:10.462482 03700000 ################################################################
10326 11:47:10.462616
10327 11:47:11.050434 03780000 ################################################################
10328 11:47:11.050932
10329 11:47:11.604380 03800000 ################################################################
10330 11:47:11.604845
10331 11:47:12.194274 03880000 ################################################################
10332 11:47:12.194944
10333 11:47:12.810145 03900000 ################################################################
10334 11:47:12.810784
10335 11:47:13.482471 03980000 ################################################################
10336 11:47:13.482609
10337 11:47:14.172172 03a00000 ################################################################
10338 11:47:14.172337
10339 11:47:14.839557 03a80000 ################################################################
10340 11:47:14.839948
10341 11:47:15.520075 03b00000 ################################################################
10342 11:47:15.520221
10343 11:47:16.182568 03b80000 ################################################################
10344 11:47:16.183450
10345 11:47:16.895152 03c00000 ################################################################
10346 11:47:16.895353
10347 11:47:17.589492 03c80000 ################################################################
10348 11:47:17.589667
10349 11:47:18.300274 03d00000 ################################################################
10350 11:47:18.300426
10351 11:47:19.007711 03d80000 ################################################################
10352 11:47:19.007863
10353 11:47:19.669707 03e00000 ################################################################
10354 11:47:19.669842
10355 11:47:20.347372 03e80000 ################################################################
10356 11:47:20.347507
10357 11:47:21.046516 03f00000 ################################################################
10358 11:47:21.046663
10359 11:47:21.405627 03f80000 ################################## done.
10360 11:47:21.405777
10361 11:47:21.409370 The bootfile was 66856958 bytes long.
10362 11:47:21.409450
10363 11:47:21.412531 Sending tftp read request... done.
10364 11:47:21.412635
10365 11:47:21.415715 Waiting for the transfer...
10366 11:47:21.415796
10367 11:47:21.415879 00000000 # done.
10368 11:47:21.419518
10369 11:47:21.425821 Command line loaded dynamically from TFTP file: 10742256/tftp-deploy-35vbjk6z/kernel/cmdline
10370 11:47:21.425906
10371 11:47:21.435817 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10372 11:47:21.435902
10373 11:47:21.438970 Loading FIT.
10374 11:47:21.439044
10375 11:47:21.442494 Image ramdisk-1 has 56364637 bytes.
10376 11:47:21.442569
10377 11:47:21.442631 Image fdt-1 has 46924 bytes.
10378 11:47:21.442689
10379 11:47:21.445313 Image kernel-1 has 10443363 bytes.
10380 11:47:21.445390
10381 11:47:21.455533 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10382 11:47:21.455613
10383 11:47:21.472018 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10384 11:47:21.472108
10385 11:47:21.478563 Choosing best match conf-1 for compat google,spherion-rev2.
10386 11:47:21.482539
10387 11:47:21.486786 Connected to device vid:did:rid of 1ae0:0028:00
10388 11:47:21.494316
10389 11:47:21.497531 tpm_get_response: command 0x17b, return code 0x0
10390 11:47:21.497606
10391 11:47:21.500733 ec_init: CrosEC protocol v3 supported (256, 248)
10392 11:47:21.505737
10393 11:47:21.508846 tpm_cleanup: add release locality here.
10394 11:47:21.508948
10395 11:47:21.509035 Shutting down all USB controllers.
10396 11:47:21.512642
10397 11:47:21.512717 Removing current net device
10398 11:47:21.512778
10399 11:47:21.518825 Exiting depthcharge with code 4 at timestamp: 120824228
10400 11:47:21.518936
10401 11:47:21.522043 LZMA decompressing kernel-1 to 0x821a6718
10402 11:47:21.522116
10403 11:47:21.525734 LZMA decompressing kernel-1 to 0x40000000
10404 11:47:22.836595
10405 11:47:22.836732 jumping to kernel
10406 11:47:22.837480 end: 2.2.4 bootloader-commands (duration 00:01:33) [common]
10407 11:47:22.837612 start: 2.2.5 auto-login-action (timeout 00:02:52) [common]
10408 11:47:22.837718 Setting prompt string to ['Linux version [0-9]']
10409 11:47:22.837813 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10410 11:47:22.837911 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10411 11:47:22.919020
10412 11:47:22.922168 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10413 11:47:22.925670 start: 2.2.5.1 login-action (timeout 00:02:52) [common]
10414 11:47:22.925789 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10415 11:47:22.925911 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10416 11:47:22.926021 Using line separator: #'\n'#
10417 11:47:22.926109 No login prompt set.
10418 11:47:22.926213 Parsing kernel messages
10419 11:47:22.926299 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10420 11:47:22.926483 [login-action] Waiting for messages, (timeout 00:02:52)
10421 11:47:22.945510 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10422 11:47:22.948991 [ 0.000000] random: crng init done
10423 11:47:22.952022 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10424 11:47:22.955285 [ 0.000000] efi: UEFI not found.
10425 11:47:22.965259 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10426 11:47:22.971884 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10427 11:47:22.981641 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10428 11:47:22.991557 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10429 11:47:22.997796 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10430 11:47:23.004666 [ 0.000000] printk: bootconsole [mtk8250] enabled
10431 11:47:23.011010 [ 0.000000] NUMA: No NUMA configuration found
10432 11:47:23.018022 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10433 11:47:23.021142 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10434 11:47:23.024304 [ 0.000000] Zone ranges:
10435 11:47:23.030745 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10436 11:47:23.033995 [ 0.000000] DMA32 empty
10437 11:47:23.040879 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10438 11:47:23.044130 [ 0.000000] Movable zone start for each node
10439 11:47:23.047095 [ 0.000000] Early memory node ranges
10440 11:47:23.054162 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10441 11:47:23.060664 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10442 11:47:23.067007 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10443 11:47:23.073783 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10444 11:47:23.080104 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10445 11:47:23.086578 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10446 11:47:23.143122 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10447 11:47:23.149367 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10448 11:47:23.155978 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10449 11:47:23.159524 [ 0.000000] psci: probing for conduit method from DT.
10450 11:47:23.166321 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10451 11:47:23.169227 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10452 11:47:23.175825 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10453 11:47:23.179391 [ 0.000000] psci: SMC Calling Convention v1.2
10454 11:47:23.185711 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10455 11:47:23.189147 [ 0.000000] Detected VIPT I-cache on CPU0
10456 11:47:23.195714 [ 0.000000] CPU features: detected: GIC system register CPU interface
10457 11:47:23.202430 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10458 11:47:23.208708 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10459 11:47:23.215639 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10460 11:47:23.225195 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10461 11:47:23.231513 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10462 11:47:23.235252 [ 0.000000] alternatives: applying boot alternatives
10463 11:47:23.241706 [ 0.000000] Fallback order for Node 0: 0
10464 11:47:23.248648 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10465 11:47:23.251812 [ 0.000000] Policy zone: Normal
10466 11:47:23.264840 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10467 11:47:23.274862 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10468 11:47:23.284296 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10469 11:47:23.294241 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10470 11:47:23.300798 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10471 11:47:23.304514 <6>[ 0.000000] software IO TLB: area num 8.
10472 11:47:23.360147 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10473 11:47:23.509474 <6>[ 0.000000] Memory: 7916112K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 436656K reserved, 32768K cma-reserved)
10474 11:47:23.516130 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10475 11:47:23.522196 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10476 11:47:23.525826 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10477 11:47:23.532110 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10478 11:47:23.538764 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10479 11:47:23.542509 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10480 11:47:23.551980 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10481 11:47:23.558933 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10482 11:47:23.565465 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10483 11:47:23.571726 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10484 11:47:23.575484 <6>[ 0.000000] GICv3: 608 SPIs implemented
10485 11:47:23.578235 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10486 11:47:23.584735 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10487 11:47:23.588303 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10488 11:47:23.595003 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10489 11:47:23.607957 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10490 11:47:23.621257 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10491 11:47:23.627527 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10492 11:47:23.635666 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10493 11:47:23.649430 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10494 11:47:23.655696 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10495 11:47:23.662710 <6>[ 0.009225] Console: colour dummy device 80x25
10496 11:47:23.672389 <6>[ 0.013951] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10497 11:47:23.678720 <6>[ 0.024458] pid_max: default: 32768 minimum: 301
10498 11:47:23.682377 <6>[ 0.029333] LSM: Security Framework initializing
10499 11:47:23.688833 <6>[ 0.034272] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10500 11:47:23.698389 <6>[ 0.042133] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10501 11:47:23.708808 <6>[ 0.051559] cblist_init_generic: Setting adjustable number of callback queues.
10502 11:47:23.715050 <6>[ 0.059011] cblist_init_generic: Setting shift to 3 and lim to 1.
10503 11:47:23.718042 <6>[ 0.065350] cblist_init_generic: Setting shift to 3 and lim to 1.
10504 11:47:23.724839 <6>[ 0.071759] rcu: Hierarchical SRCU implementation.
10505 11:47:23.731825 <6>[ 0.076771] rcu: Max phase no-delay instances is 1000.
10506 11:47:23.738024 <6>[ 0.083796] EFI services will not be available.
10507 11:47:23.741579 <6>[ 0.088766] smp: Bringing up secondary CPUs ...
10508 11:47:23.749612 <6>[ 0.093845] Detected VIPT I-cache on CPU1
10509 11:47:23.755812 <6>[ 0.093919] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10510 11:47:23.762442 <6>[ 0.093950] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10511 11:47:23.765577 <6>[ 0.094290] Detected VIPT I-cache on CPU2
10512 11:47:23.775897 <6>[ 0.094345] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10513 11:47:23.782229 <6>[ 0.094362] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10514 11:47:23.785375 <6>[ 0.094619] Detected VIPT I-cache on CPU3
10515 11:47:23.791551 <6>[ 0.094661] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10516 11:47:23.798503 <6>[ 0.094675] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10517 11:47:23.805206 <6>[ 0.094964] CPU features: detected: Spectre-v4
10518 11:47:23.808202 <6>[ 0.094969] CPU features: detected: Spectre-BHB
10519 11:47:23.811874 <6>[ 0.094974] Detected PIPT I-cache on CPU4
10520 11:47:23.821563 <6>[ 0.095025] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10521 11:47:23.828452 <6>[ 0.095040] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10522 11:47:23.831733 <6>[ 0.095329] Detected PIPT I-cache on CPU5
10523 11:47:23.837826 <6>[ 0.095392] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10524 11:47:23.844564 <6>[ 0.095409] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10525 11:47:23.848120 <6>[ 0.095691] Detected PIPT I-cache on CPU6
10526 11:47:23.857692 <6>[ 0.095756] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10527 11:47:23.864704 <6>[ 0.095772] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10528 11:47:23.867977 <6>[ 0.096070] Detected PIPT I-cache on CPU7
10529 11:47:23.874282 <6>[ 0.096135] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10530 11:47:23.880621 <6>[ 0.096151] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10531 11:47:23.887088 <6>[ 0.096199] smp: Brought up 1 node, 8 CPUs
10532 11:47:23.890946 <6>[ 0.237665] SMP: Total of 8 processors activated.
10533 11:47:23.897009 <6>[ 0.242586] CPU features: detected: 32-bit EL0 Support
10534 11:47:23.904027 <6>[ 0.247949] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10535 11:47:23.910596 <6>[ 0.256804] CPU features: detected: Common not Private translations
10536 11:47:23.917346 <6>[ 0.263279] CPU features: detected: CRC32 instructions
10537 11:47:23.923787 <6>[ 0.268664] CPU features: detected: RCpc load-acquire (LDAPR)
10538 11:47:23.929986 <6>[ 0.274623] CPU features: detected: LSE atomic instructions
10539 11:47:23.933601 <6>[ 0.280405] CPU features: detected: Privileged Access Never
10540 11:47:23.940023 <6>[ 0.286220] CPU features: detected: RAS Extension Support
10541 11:47:23.946952 <6>[ 0.291828] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10542 11:47:23.953581 <6>[ 0.299050] CPU: All CPU(s) started at EL2
10543 11:47:23.956078 <6>[ 0.303367] alternatives: applying system-wide alternatives
10544 11:47:23.967366 <6>[ 0.314072] devtmpfs: initialized
10545 11:47:23.979415 <6>[ 0.322878] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10546 11:47:23.989401 <6>[ 0.332838] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10547 11:47:23.995577 <6>[ 0.341018] pinctrl core: initialized pinctrl subsystem
10548 11:47:23.999417 <6>[ 0.347688] DMI not present or invalid.
10549 11:47:24.005551 <6>[ 0.352092] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10550 11:47:24.015795 <6>[ 0.358964] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10551 11:47:24.021833 <6>[ 0.366542] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10552 11:47:24.032019 <6>[ 0.374765] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10553 11:47:24.034990 <6>[ 0.383002] audit: initializing netlink subsys (disabled)
10554 11:47:24.045213 <5>[ 0.388693] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10555 11:47:24.051547 <6>[ 0.389398] thermal_sys: Registered thermal governor 'step_wise'
10556 11:47:24.058186 <6>[ 0.396657] thermal_sys: Registered thermal governor 'power_allocator'
10557 11:47:24.061713 <6>[ 0.402913] cpuidle: using governor menu
10558 11:47:24.068701 <6>[ 0.413869] NET: Registered PF_QIPCRTR protocol family
10559 11:47:24.075010 <6>[ 0.419350] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10560 11:47:24.081388 <6>[ 0.426451] ASID allocator initialised with 32768 entries
10561 11:47:24.084512 <6>[ 0.433010] Serial: AMBA PL011 UART driver
10562 11:47:24.094660 <4>[ 0.441696] Trying to register duplicate clock ID: 134
10563 11:47:24.149063 <6>[ 0.498919] KASLR enabled
10564 11:47:24.163276 <6>[ 0.506624] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10565 11:47:24.169592 <6>[ 0.513636] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10566 11:47:24.176028 <6>[ 0.520122] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10567 11:47:24.183005 <6>[ 0.527127] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10568 11:47:24.189378 <6>[ 0.533614] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10569 11:47:24.195904 <6>[ 0.540620] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10570 11:47:24.202272 <6>[ 0.547108] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10571 11:47:24.209259 <6>[ 0.554112] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10572 11:47:24.212468 <6>[ 0.561579] ACPI: Interpreter disabled.
10573 11:47:24.221229 <6>[ 0.567982] iommu: Default domain type: Translated
10574 11:47:24.227731 <6>[ 0.573097] iommu: DMA domain TLB invalidation policy: strict mode
10575 11:47:24.230771 <5>[ 0.579755] SCSI subsystem initialized
10576 11:47:24.237420 <6>[ 0.583992] usbcore: registered new interface driver usbfs
10577 11:47:24.244042 <6>[ 0.589723] usbcore: registered new interface driver hub
10578 11:47:24.247780 <6>[ 0.595278] usbcore: registered new device driver usb
10579 11:47:24.254578 <6>[ 0.601374] pps_core: LinuxPPS API ver. 1 registered
10580 11:47:24.264459 <6>[ 0.606568] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10581 11:47:24.267511 <6>[ 0.615910] PTP clock support registered
10582 11:47:24.270736 <6>[ 0.620152] EDAC MC: Ver: 3.0.0
10583 11:47:24.278633 <6>[ 0.625324] FPGA manager framework
10584 11:47:24.281763 <6>[ 0.628999] Advanced Linux Sound Architecture Driver Initialized.
10585 11:47:24.285637 <6>[ 0.635762] vgaarb: loaded
10586 11:47:24.292054 <6>[ 0.638925] clocksource: Switched to clocksource arch_sys_counter
10587 11:47:24.298997 <5>[ 0.645374] VFS: Disk quotas dquot_6.6.0
10588 11:47:24.305373 <6>[ 0.649563] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10589 11:47:24.308659 <6>[ 0.656754] pnp: PnP ACPI: disabled
10590 11:47:24.316837 <6>[ 0.663469] NET: Registered PF_INET protocol family
10591 11:47:24.326279 <6>[ 0.669069] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10592 11:47:24.337820 <6>[ 0.681277] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10593 11:47:24.347958 <6>[ 0.690104] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10594 11:47:24.354281 <6>[ 0.698067] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10595 11:47:24.363982 <6>[ 0.706764] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10596 11:47:24.370793 <6>[ 0.716471] TCP: Hash tables configured (established 65536 bind 65536)
10597 11:47:24.377040 <6>[ 0.723326] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10598 11:47:24.387133 <6>[ 0.730525] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10599 11:47:24.393731 <6>[ 0.738225] NET: Registered PF_UNIX/PF_LOCAL protocol family
10600 11:47:24.400342 <6>[ 0.744386] RPC: Registered named UNIX socket transport module.
10601 11:47:24.403344 <6>[ 0.750540] RPC: Registered udp transport module.
10602 11:47:24.410274 <6>[ 0.755473] RPC: Registered tcp transport module.
10603 11:47:24.416607 <6>[ 0.760404] RPC: Registered tcp NFSv4.1 backchannel transport module.
10604 11:47:24.420338 <6>[ 0.767070] PCI: CLS 0 bytes, default 64
10605 11:47:24.423529 <6>[ 0.771452] Unpacking initramfs...
10606 11:47:24.447213 <6>[ 0.791062] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10607 11:47:24.457515 <6>[ 0.799775] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10608 11:47:24.460465 <6>[ 0.808611] kvm [1]: IPA Size Limit: 40 bits
10609 11:47:24.467035 <6>[ 0.813149] kvm [1]: GICv3: no GICV resource entry
10610 11:47:24.470674 <6>[ 0.818174] kvm [1]: disabling GICv2 emulation
10611 11:47:24.477402 <6>[ 0.822859] kvm [1]: GIC system register CPU interface enabled
10612 11:47:24.480485 <6>[ 0.829016] kvm [1]: vgic interrupt IRQ18
10613 11:47:24.486739 <6>[ 0.833373] kvm [1]: VHE mode initialized successfully
10614 11:47:24.494023 <5>[ 0.839775] Initialise system trusted keyrings
10615 11:47:24.500384 <6>[ 0.844580] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10616 11:47:24.507698 <6>[ 0.854720] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10617 11:47:24.514199 <5>[ 0.861113] NFS: Registering the id_resolver key type
10618 11:47:24.517426 <5>[ 0.866418] Key type id_resolver registered
10619 11:47:24.524435 <5>[ 0.870834] Key type id_legacy registered
10620 11:47:24.530545 <6>[ 0.875113] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10621 11:47:24.537450 <6>[ 0.882036] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10622 11:47:24.543720 <6>[ 0.889768] 9p: Installing v9fs 9p2000 file system support
10623 11:47:24.581311 <5>[ 0.927947] Key type asymmetric registered
10624 11:47:24.584110 <5>[ 0.932280] Asymmetric key parser 'x509' registered
10625 11:47:24.594049 <6>[ 0.937426] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10626 11:47:24.597548 <6>[ 0.945053] io scheduler mq-deadline registered
10627 11:47:24.600701 <6>[ 0.949816] io scheduler kyber registered
10628 11:47:24.619478 <6>[ 0.966503] EINJ: ACPI disabled.
10629 11:47:24.651705 <4>[ 0.992160] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 11:47:24.661415 <4>[ 1.002780] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 11:47:24.676717 <6>[ 1.023479] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10632 11:47:24.684417 <6>[ 1.031521] printk: console [ttyS0] disabled
10633 11:47:24.712400 <6>[ 1.056166] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10634 11:47:24.718930 <6>[ 1.065647] printk: console [ttyS0] enabled
10635 11:47:24.722030 <6>[ 1.065647] printk: console [ttyS0] enabled
10636 11:47:24.728905 <6>[ 1.074540] printk: bootconsole [mtk8250] disabled
10637 11:47:24.732017 <6>[ 1.074540] printk: bootconsole [mtk8250] disabled
10638 11:47:24.738788 <6>[ 1.085879] SuperH (H)SCI(F) driver initialized
10639 11:47:24.741960 <6>[ 1.091171] msm_serial: driver initialized
10640 11:47:24.756357 <6>[ 1.100095] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10641 11:47:24.766116 <6>[ 1.108640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10642 11:47:24.772934 <6>[ 1.117182] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10643 11:47:24.782988 <6>[ 1.125810] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10644 11:47:24.792550 <6>[ 1.134517] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10645 11:47:24.799453 <6>[ 1.143237] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10646 11:47:24.809312 <6>[ 1.151780] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10647 11:47:24.815613 <6>[ 1.160601] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10648 11:47:24.825780 <6>[ 1.169144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10649 11:47:24.837646 <6>[ 1.184797] loop: module loaded
10650 11:47:24.844383 <6>[ 1.190791] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10651 11:47:24.867076 <4>[ 1.214300] mtk-pmic-keys: Failed to locate of_node [id: -1]
10652 11:47:24.874409 <6>[ 1.221222] megasas: 07.719.03.00-rc1
10653 11:47:24.884175 <6>[ 1.231090] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10654 11:47:24.891800 <6>[ 1.238311] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10655 11:47:24.908030 <6>[ 1.254936] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10656 11:47:24.968610 <6>[ 1.308795] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10657 11:47:26.850670 <6>[ 3.197728] Freeing initrd memory: 55040K
10658 11:47:26.861207 <6>[ 3.208233] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10659 11:47:26.872230 <6>[ 3.219303] tun: Universal TUN/TAP device driver, 1.6
10660 11:47:26.875298 <6>[ 3.225356] thunder_xcv, ver 1.0
10661 11:47:26.878444 <6>[ 3.228861] thunder_bgx, ver 1.0
10662 11:47:26.881709 <6>[ 3.232357] nicpf, ver 1.0
10663 11:47:26.892368 <6>[ 3.236359] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10664 11:47:26.895514 <6>[ 3.243834] hns3: Copyright (c) 2017 Huawei Corporation.
10665 11:47:26.902626 <6>[ 3.249421] hclge is initializing
10666 11:47:26.905591 <6>[ 3.253001] e1000: Intel(R) PRO/1000 Network Driver
10667 11:47:26.912423 <6>[ 3.258130] e1000: Copyright (c) 1999-2006 Intel Corporation.
10668 11:47:26.915534 <6>[ 3.264165] e1000e: Intel(R) PRO/1000 Network Driver
10669 11:47:26.922371 <6>[ 3.269381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10670 11:47:26.929086 <6>[ 3.275569] igb: Intel(R) Gigabit Ethernet Network Driver
10671 11:47:26.935574 <6>[ 3.281219] igb: Copyright (c) 2007-2014 Intel Corporation.
10672 11:47:26.942454 <6>[ 3.287055] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10673 11:47:26.948715 <6>[ 3.293574] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10674 11:47:26.952179 <6>[ 3.300036] sky2: driver version 1.30
10675 11:47:26.958272 <6>[ 3.305015] VFIO - User Level meta-driver version: 0.3
10676 11:47:26.966135 <6>[ 3.313208] usbcore: registered new interface driver usb-storage
10677 11:47:26.972732 <6>[ 3.319650] usbcore: registered new device driver onboard-usb-hub
10678 11:47:26.981557 <6>[ 3.328764] mt6397-rtc mt6359-rtc: registered as rtc0
10679 11:47:26.991771 <6>[ 3.334252] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:47:27 UTC (1686829647)
10680 11:47:26.995003 <6>[ 3.343881] i2c_dev: i2c /dev entries driver
10681 11:47:27.011351 <6>[ 3.355575] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10682 11:47:27.018404 <6>[ 3.365752] sdhci: Secure Digital Host Controller Interface driver
10683 11:47:27.025322 <6>[ 3.372189] sdhci: Copyright(c) Pierre Ossman
10684 11:47:27.031722 <6>[ 3.377585] Synopsys Designware Multimedia Card Interface Driver
10685 11:47:27.035402 <6>[ 3.384208] mmc0: CQHCI version 5.10
10686 11:47:27.041416 <6>[ 3.384725] sdhci-pltfm: SDHCI platform and OF driver helper
10687 11:47:27.049317 <6>[ 3.396306] ledtrig-cpu: registered to indicate activity on CPUs
10688 11:47:27.059589 <6>[ 3.403716] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10689 11:47:27.066284 <6>[ 3.411124] usbcore: registered new interface driver usbhid
10690 11:47:27.069921 <6>[ 3.416951] usbhid: USB HID core driver
10691 11:47:27.076027 <6>[ 3.421203] spi_master spi0: will run message pump with realtime priority
10692 11:47:27.120765 <6>[ 3.461498] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10693 11:47:27.139817 <6>[ 3.476531] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10694 11:47:27.143026 <6>[ 3.490117] mmc0: Command Queue Engine enabled
10695 11:47:27.149713 <6>[ 3.492138] cros-ec-spi spi0.0: Chrome EC device registered
10696 11:47:27.156371 <6>[ 3.494848] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10697 11:47:27.159307 <6>[ 3.507947] mmcblk0: mmc0:0001 DA4128 116 GiB
10698 11:47:27.174102 <6>[ 3.518059] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10699 11:47:27.180961 <6>[ 3.521196] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10700 11:47:27.187583 <6>[ 3.529436] NET: Registered PF_PACKET protocol family
10701 11:47:27.190734 <6>[ 3.534633] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10702 11:47:27.197426 <6>[ 3.538705] 9pnet: Installing 9P2000 support
10703 11:47:27.200611 <6>[ 3.544530] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10704 11:47:27.207447 <5>[ 3.548394] Key type dns_resolver registered
10705 11:47:27.213892 <6>[ 3.554227] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10706 11:47:27.217140 <6>[ 3.558592] registered taskstats version 1
10707 11:47:27.220224 <5>[ 3.568996] Loading compiled-in X.509 certificates
10708 11:47:27.254974 <4>[ 3.595537] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10709 11:47:27.265101 <4>[ 3.606257] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10710 11:47:27.275483 <3>[ 3.619340] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10711 11:47:27.288332 <6>[ 3.635445] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10712 11:47:27.294994 <6>[ 3.642176] xhci-mtk 11200000.usb: xHCI Host Controller
10713 11:47:27.301624 <6>[ 3.647672] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10714 11:47:27.311445 <6>[ 3.655521] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10715 11:47:27.318459 <6>[ 3.664948] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10716 11:47:27.324519 <6>[ 3.671123] xhci-mtk 11200000.usb: xHCI Host Controller
10717 11:47:27.331531 <6>[ 3.676625] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10718 11:47:27.337963 <6>[ 3.684288] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10719 11:47:27.344768 <6>[ 3.692171] hub 1-0:1.0: USB hub found
10720 11:47:27.348387 <6>[ 3.696219] hub 1-0:1.0: 1 port detected
10721 11:47:27.357979 <6>[ 3.700579] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10722 11:47:27.361660 <6>[ 3.709400] hub 2-0:1.0: USB hub found
10723 11:47:27.364944 <6>[ 3.713451] hub 2-0:1.0: 1 port detected
10724 11:47:27.373307 <6>[ 3.720687] mtk-msdc 11f70000.mmc: Got CD GPIO
10725 11:47:27.390652 <6>[ 3.734324] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10726 11:47:27.397400 <6>[ 3.742379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10727 11:47:27.407034 <4>[ 3.750364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10728 11:47:27.416981 <6>[ 3.760029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10729 11:47:27.423231 <6>[ 3.768116] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10730 11:47:27.433140 <6>[ 3.776139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10731 11:47:27.440066 <6>[ 3.784064] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10732 11:47:27.446479 <6>[ 3.791886] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10733 11:47:27.456586 <6>[ 3.799708] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10734 11:47:27.466310 <6>[ 3.810319] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10735 11:47:27.476199 <6>[ 3.818724] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10736 11:47:27.482773 <6>[ 3.827081] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10737 11:47:27.492947 <6>[ 3.835425] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10738 11:47:27.499387 <6>[ 3.843769] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10739 11:47:27.509150 <6>[ 3.852113] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10740 11:47:27.515931 <6>[ 3.860457] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10741 11:47:27.525619 <6>[ 3.868801] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10742 11:47:27.532550 <6>[ 3.877144] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10743 11:47:27.542104 <6>[ 3.885488] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10744 11:47:27.549158 <6>[ 3.893831] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10745 11:47:27.559090 <6>[ 3.902175] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10746 11:47:27.565411 <6>[ 3.910519] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10747 11:47:27.575688 <6>[ 3.918863] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10748 11:47:27.582091 <6>[ 3.927210] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10749 11:47:27.588706 <6>[ 3.936186] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10750 11:47:27.596553 <6>[ 3.943760] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10751 11:47:27.603858 <6>[ 3.950865] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10752 11:47:27.614247 <6>[ 3.958015] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10753 11:47:27.620419 <6>[ 3.965340] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10754 11:47:27.630809 <6>[ 3.972267] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10755 11:47:27.636975 <6>[ 3.981408] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10756 11:47:27.647136 <6>[ 3.990550] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10757 11:47:27.656623 <6>[ 3.999856] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10758 11:47:27.666575 <6>[ 4.009333] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10759 11:47:27.676400 <6>[ 4.018812] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10760 11:47:27.686400 <6>[ 4.027939] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10761 11:47:27.693321 <6>[ 4.037413] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10762 11:47:27.702812 <6>[ 4.046539] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10763 11:47:27.713118 <6>[ 4.055841] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10764 11:47:27.722873 <6>[ 4.066006] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10765 11:47:27.733980 <6>[ 4.077879] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10766 11:47:27.755011 <6>[ 4.099226] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10767 11:47:27.782359 <6>[ 4.129654] hub 2-1:1.0: USB hub found
10768 11:47:27.785528 <6>[ 4.134062] hub 2-1:1.0: 3 ports detected
10769 11:47:27.907205 <6>[ 4.251091] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10770 11:47:28.061461 <6>[ 4.408785] hub 1-1:1.0: USB hub found
10771 11:47:28.064433 <6>[ 4.413186] hub 1-1:1.0: 4 ports detected
10772 11:47:28.139065 <6>[ 4.483318] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10773 11:47:28.386969 <6>[ 4.731209] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10774 11:47:28.519909 <6>[ 4.867513] hub 1-1.4:1.0: USB hub found
10775 11:47:28.523136 <6>[ 4.872196] hub 1-1.4:1.0: 2 ports detected
10776 11:47:28.823126 <6>[ 5.167198] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10777 11:47:29.015162 <6>[ 5.359198] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10778 11:47:40.011688 <6>[ 16.363748] ALSA device list:
10779 11:47:40.018487 <6>[ 16.367005] No soundcards found.
10780 11:47:40.030646 <6>[ 16.379459] Freeing unused kernel memory: 8384K
10781 11:47:40.033738 <6>[ 16.384379] Run /init as init process
10782 11:47:40.064668 <6>[ 16.413216] NET: Registered PF_INET6 protocol family
10783 11:47:40.070915 <6>[ 16.419765] Segment Routing with IPv6
10784 11:47:40.074525 <6>[ 16.423759] In-situ OAM (IOAM) with IPv6
10785 11:47:40.109496 <30>[ 16.438324] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10786 11:47:40.112616 <30>[ 16.462290] systemd[1]: Detected architecture arm64.
10787 11:47:40.115968
10788 11:47:40.119141 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10789 11:47:40.119219
10790 11:47:40.134388 <30>[ 16.483320] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10791 11:47:40.260525 <30>[ 16.606285] systemd[1]: Queued start job for default target Graphical Interface.
10792 11:47:40.295681 <30>[ 16.644569] systemd[1]: Created slice system-getty.slice.
10793 11:47:40.302469 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10794 11:47:40.319470 <30>[ 16.667819] systemd[1]: Created slice system-modprobe.slice.
10795 11:47:40.325850 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10796 11:47:40.343409 <30>[ 16.692319] systemd[1]: Created slice system-serial\x2dgetty.slice.
10797 11:47:40.354017 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10798 11:47:40.367160 <30>[ 16.715714] systemd[1]: Created slice User and Session Slice.
10799 11:47:40.373481 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10800 11:47:40.394621 <30>[ 16.739757] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10801 11:47:40.403880 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10802 11:47:40.422334 <30>[ 16.767708] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10803 11:47:40.428840 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10804 11:47:40.448883 <30>[ 16.791321] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10805 11:47:40.455968 <30>[ 16.803356] systemd[1]: Reached target Local Encrypted Volumes.
10806 11:47:40.462089 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10807 11:47:40.479185 <30>[ 16.827554] systemd[1]: Reached target Paths.
10808 11:47:40.482030 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10809 11:47:40.498483 <30>[ 16.847256] systemd[1]: Reached target Remote File Systems.
10810 11:47:40.505247 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10811 11:47:40.522745 <30>[ 16.871467] systemd[1]: Reached target Slices.
10812 11:47:40.529597 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10813 11:47:40.542761 <30>[ 16.891266] systemd[1]: Reached target Swap.
10814 11:47:40.545997 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10815 11:47:40.566105 <30>[ 16.911479] systemd[1]: Listening on initctl Compatibility Named Pipe.
10816 11:47:40.572450 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10817 11:47:40.579424 <30>[ 16.926291] systemd[1]: Listening on Journal Audit Socket.
10818 11:47:40.585560 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10819 11:47:40.598618 <30>[ 16.947513] systemd[1]: Listening on Journal Socket (/dev/log).
10820 11:47:40.605118 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10821 11:47:40.623475 <30>[ 16.971988] systemd[1]: Listening on Journal Socket.
10822 11:47:40.630000 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10823 11:47:40.642587 <30>[ 16.991566] systemd[1]: Listening on udev Control Socket.
10824 11:47:40.649381 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10825 11:47:40.666613 <30>[ 17.015871] systemd[1]: Listening on udev Kernel Socket.
10826 11:47:40.673579 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10827 11:47:40.710901 <30>[ 17.059637] systemd[1]: Mounting Huge Pages File System...
10828 11:47:40.717432 Mounting [0;1;39mHuge Pages File System[0m...
10829 11:47:40.735714 <30>[ 17.081325] systemd[1]: Mounting POSIX Message Queue File System...
10830 11:47:40.738638 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10831 11:47:40.756593 <30>[ 17.105201] systemd[1]: Mounting Kernel Debug File System...
10832 11:47:40.763070 Mounting [0;1;39mKernel Debug File System[0m...
10833 11:47:40.781891 <30>[ 17.127560] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10834 11:47:40.806327 <30>[ 17.151709] systemd[1]: Starting Create list of static device nodes for the current kernel...
10835 11:47:40.812779 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10836 11:47:40.833035 <30>[ 17.181520] systemd[1]: Starting Load Kernel Module configfs...
10837 11:47:40.839537 Starting [0;1;39mLoad Kernel Module configfs[0m...
10838 11:47:40.856736 <30>[ 17.205521] systemd[1]: Starting Load Kernel Module drm...
10839 11:47:40.863055 Starting [0;1;39mLoad Kernel Module drm[0m...
10840 11:47:40.881686 <30>[ 17.227487] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10841 11:47:40.891959 <30>[ 17.240968] systemd[1]: Starting Journal Service...
10842 11:47:40.895871 Starting [0;1;39mJournal Service[0m...
10843 11:47:40.912983 <30>[ 17.261858] systemd[1]: Starting Load Kernel Modules...
10844 11:47:40.919571 Starting [0;1;39mLoad Kernel Modules[0m...
10845 11:47:40.940921 <30>[ 17.286109] systemd[1]: Starting Remount Root and Kernel File Systems...
10846 11:47:40.947446 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10847 11:47:40.965145 <30>[ 17.313910] systemd[1]: Starting Coldplug All udev Devices...
10848 11:47:40.972050 Starting [0;1;39mColdplug All udev Devices[0m...
10849 11:47:40.989057 <30>[ 17.337905] systemd[1]: Mounted Huge Pages File System.
10850 11:47:40.995412 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10851 11:47:41.010908 <30>[ 17.359702] systemd[1]: Started Journal Service.
10852 11:47:41.017520 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10853 11:47:41.032390 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10854 11:47:41.047366 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10855 11:47:41.067136 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10856 11:47:41.084261 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10857 11:47:41.100168 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10858 11:47:41.119877 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10859 11:47:41.139185 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10860 11:47:41.154354 See 'systemctl status systemd-remount-fs.service' for details.
10861 11:47:41.207671 Mounting [0;1;39mKernel Configuration File System[0m...
10862 11:47:41.229474 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10863 11:47:41.246353 <46>[ 17.592164] systemd-journald[176]: Received client request to flush runtime journal.
10864 11:47:41.257583 Starting [0;1;39mLoad/Save Random Seed[0m...
10865 11:47:41.273393 Starting [0;1;39mApply Kernel Variables[0m...
10866 11:47:41.290081 Starting [0;1;39mCreate System Users[0m...
10867 11:47:41.314058 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10868 11:47:41.331037 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10869 11:47:41.343681 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10870 11:47:41.359634 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10871 11:47:41.375870 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10872 11:47:41.391464 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10873 11:47:41.443083 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10874 11:47:41.465478 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10875 11:47:41.478916 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10876 11:47:41.494629 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10877 11:47:41.539358 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10878 11:47:41.562329 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10879 11:47:41.583280 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10880 11:47:41.603461 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10881 11:47:41.651179 Starting [0;1;39mNetwork Time Synchronization[0m...
10882 11:47:41.672496 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10883 11:47:41.706460 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10884 11:47:41.745175 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10885 11:47:41.765268 <6>[ 18.110580] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10886 11:47:41.795972 <6>[ 18.144445] remoteproc remoteproc0: scp is available
10887 11:47:41.805281 <4>[ 18.150363] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10888 11:47:41.813723 Startin<6>[ 18.162590] remoteproc remoteproc0: powering up scp
10889 11:47:41.826639 g [0;1;39mLoad/<4>[ 18.169153] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10890 11:47:41.833689 Save Screen …o<3>[ 18.180310] remoteproc remoteproc0: request_firmware failed: -2
10891 11:47:41.843316 f leds:white:kbd_backlight[0m..<3>[ 18.190324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 11:47:41.853135 <4>[ 18.198456] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10893 11:47:41.853259 .
10894 11:47:41.859523 <3>[ 18.198957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 11:47:41.869515 <3>[ 18.214469] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10896 11:47:41.876209 <4>[ 18.217951] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10897 11:47:41.883017 <6>[ 18.224564] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10898 11:47:41.892911 <6>[ 18.237666] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10899 11:47:41.899572 <3>[ 18.238658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 11:47:41.909127 <6>[ 18.246389] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10901 11:47:41.916220 <6>[ 18.249550] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10902 11:47:41.925924 <3>[ 18.254534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10903 11:47:41.936175 [[0;32m OK [<3>[ 18.278973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10904 11:47:41.942530 0m] Started [0;<3>[ 18.288709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10905 11:47:41.948855 1;39mNetwork Tim<6>[ 18.290971] mc: Linux media interface: v0.10
10906 11:47:41.955634 e Synchronizatio<6>[ 18.290993] usbcore: registered new interface driver r8152
10907 11:47:41.965690 <3>[ 18.298098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 11:47:41.965840 n[0m.
10909 11:47:41.975388 <6>[ 18.319517] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10910 11:47:41.985558 <3>[ 18.322564] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 11:47:41.991818 <6>[ 18.330321] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10912 11:47:42.001762 <4>[ 18.338083] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10913 11:47:42.008185 <4>[ 18.338083] Fallback method does not support PEC.
10914 11:47:42.014846 <3>[ 18.338209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 11:47:42.025324 <6>[ 18.356367] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10916 11:47:42.031540 <3>[ 18.360857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 11:47:42.038167 <6>[ 18.377598] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10918 11:47:42.048166 <3>[ 18.378346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 11:47:42.054475 <6>[ 18.388585] pci_bus 0000:00: root bus resource [bus 00-ff]
10920 11:47:42.061244 <3>[ 18.396596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 11:47:42.067957 <6>[ 18.397910] videodev: Linux video capture interface: v2.00
10922 11:47:42.074283 <6>[ 18.402734] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10923 11:47:42.080609 <6>[ 18.403197] usbcore: registered new interface driver cdc_ether
10924 11:47:42.087382 <3>[ 18.407244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10925 11:47:42.097569 <6>[ 18.415266] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10926 11:47:42.104058 <6>[ 18.415327] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10927 11:47:42.110527 <6>[ 18.416191] usbcore: registered new interface driver r8153_ecm
10928 11:47:42.120446 <3>[ 18.421188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10929 11:47:42.126963 <6>[ 18.428594] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10930 11:47:42.133725 <6>[ 18.428827] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10931 11:47:42.143223 <3>[ 18.434619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 11:47:42.146780 <6>[ 18.436285] Bluetooth: Core ver 2.22
10933 11:47:42.150382 <6>[ 18.439905] NET: Registered PF_BLUETOOTH protocol family
10934 11:47:42.157315 <6>[ 18.439911] Bluetooth: HCI device and connection manager initialized
10935 11:47:42.164153 <6>[ 18.439933] Bluetooth: HCI socket layer initialized
10936 11:47:42.167213 <6>[ 18.439940] Bluetooth: L2CAP socket layer initialized
10937 11:47:42.174140 <6>[ 18.439961] Bluetooth: SCO socket layer initialized
10938 11:47:42.177322 <6>[ 18.442699] pci 0000:00:00.0: supports D1 D2
10939 11:47:42.184538 <6>[ 18.444182] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10940 11:47:42.198656 <6>[ 18.445404] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10941 11:47:42.204862 <6>[ 18.445559] usbcore: registered new interface driver uvcvideo
10942 11:47:42.211416 <3>[ 18.452822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10943 11:47:42.217983 <6>[ 18.458824] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10944 11:47:42.228102 <6>[ 18.461087] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10945 11:47:42.235250 <4>[ 18.461707] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10946 11:47:42.245308 <4>[ 18.461721] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10947 11:47:42.252232 <3>[ 18.465342] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 11:47:42.259040 <6>[ 18.473260] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10949 11:47:42.265602 <6>[ 18.475451] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10950 11:47:42.275629 <4>[ 18.490336] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10951 11:47:42.282117 <6>[ 18.492739] usbcore: registered new interface driver btusb
10952 11:47:42.289067 <6>[ 18.495820] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10953 11:47:42.295788 <6>[ 18.495847] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10954 11:47:42.302109 <6>[ 18.497079] remoteproc remoteproc0: powering up scp
10955 11:47:42.312767 <4>[ 18.497161] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10956 11:47:42.316448 <3>[ 18.497173] remoteproc remoteproc0: request_firmware failed: -2
10957 11:47:42.322918 <3>[ 18.497176] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10958 11:47:42.329762 <3>[ 18.499678] Bluetooth: hci0: Failed to load firmware file (-2)
10959 11:47:42.339995 <6>[ 18.505246] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10960 11:47:42.343452 <3>[ 18.511843] Bluetooth: hci0: Failed to set up firmware (-2)
10961 11:47:42.352982 <3>[ 18.513663] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:47:42.362976 <3>[ 18.514256] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
10963 11:47:42.366235 <6>[ 18.515106] r8152 2-1.3:1.0 eth0: v1.12.13
10964 11:47:42.369358 <6>[ 18.517088] pci 0000:01:00.0: supports D1 D2
10965 11:47:42.379984 <4>[ 18.522288] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10966 11:47:42.386412 <6>[ 18.527031] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10967 11:47:42.393497 <6>[ 18.527401] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10968 11:47:42.403355 <3>[ 18.549160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 11:47:42.410282 <3>[ 18.549892] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10970 11:47:42.417773 <6>[ 18.567140] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10971 11:47:42.427194 <3>[ 18.590311] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:47:42.434422 <6>[ 18.597770] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10973 11:47:42.444559 <3>[ 18.607542] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 11:47:42.451186 <6>[ 18.612103] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10975 11:47:42.457991 <6>[ 18.612117] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10976 11:47:42.467878 <3>[ 18.639830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 11:47:42.475320 <6>[ 18.642355] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10978 11:47:42.485620 <3>[ 18.669548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 11:47:42.491875 <6>[ 18.670947] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10980 11:47:42.498707 <6>[ 18.670963] pci 0000:00:00.0: PCI bridge to [bus 01]
10981 11:47:42.505126 <3>[ 18.699148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 11:47:42.515190 <6>[ 18.706660] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10983 11:47:42.521503 <6>[ 18.706876] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10984 11:47:42.528066 <3>[ 18.737068] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 11:47:42.534755 <6>[ 18.741750] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10986 11:47:42.544707 [[0;32m OK [<6>[ 18.890291] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10987 11:47:42.551366 0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10988 11:47:42.564331 <5>[ 18.909810] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10989 11:47:42.582355 [[0;32m OK [0m] Found device<5>[ 18.930341] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10990 11:47:42.595785 [0;1;39m/dev/t<4>[ 18.937794] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10991 11:47:42.599015 <6>[ 18.947975] cfg80211: failed to load regulatory.db
10992 11:47:42.599145 tyS0[0m.
10993 11:47:42.645455 <6>[ 18.991212] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10994 11:47:42.652054 <6>[ 18.998732] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10995 11:47:42.676553 <6>[ 19.025541] mt7921e 0000:01:00.0: ASIC revision: 79610010
10996 11:47:42.784669 <4>[ 19.127009] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 11:47:42.791359 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10998 11:47:42.806556 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10999 11:47:42.825430 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11000 11:47:42.838223 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11001 11:47:42.854102 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11002 11:47:42.873834 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11003 11:47:42.887213 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11004 11:47:42.903884 <4>[ 19.246008] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11005 11:47:42.913992 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11006 11:47:42.926458 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11007 11:47:42.942502 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11008 11:47:42.961671 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11009 11:47:43.008559 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11010 11:47:43.024859 <4>[ 19.367032] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11011 11:47:43.047306 Starting [0;1;39mUser Login Management[0m...
11012 11:47:43.068739 Starting [0;1;39mPermit User Sessions[0m...
11013 11:47:43.087933 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11014 11:47:43.105236 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11015 11:47:43.122149 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11016 11:47:43.131349 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11017 11:47:43.147082 <4>[ 19.489730] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11018 11:47:43.162986 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11019 11:47:43.183537 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11020 11:47:43.203375 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11021 11:47:43.219158 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11022 11:47:43.234338 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11023 11:47:43.271846 <4>[ 19.614040] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11024 11:47:43.293214 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11025 11:47:43.318310 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11026 11:47:43.332182
11027 11:47:43.332393
11028 11:47:43.335900 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11029 11:47:43.336037
11030 11:47:43.339090 debian-bullseye-arm64 login: root (automatic login)
11031 11:47:43.339196
11032 11:47:43.339303
11033 11:47:43.355924 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
11034 11:47:43.356105
11035 11:47:43.362625 The programs included with the Debian GNU/Linux system are free software;
11036 11:47:43.369040 the exact distribution terms for each program are described in the
11037 11:47:43.372339 individual files in /usr/share/doc/*/copyright.
11038 11:47:43.372420
11039 11:47:43.379356 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11040 11:47:43.391772 permitted by appl<4>[ 19.733419] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11041 11:47:43.391863 icable law.
11042 11:47:43.392204 Matched prompt #10: / #
11044 11:47:43.392419 Setting prompt string to ['/ #']
11045 11:47:43.392513 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11047 11:47:43.392716 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11048 11:47:43.392811 start: 2.2.6 expect-shell-connection (timeout 00:02:32) [common]
11049 11:47:43.392881 Setting prompt string to ['/ #']
11050 11:47:43.392953 Forcing a shell prompt, looking for ['/ #']
11052 11:47:43.443157 / #
11053 11:47:43.443345 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11054 11:47:43.443453 Waiting using forced prompt support (timeout 00:02:30)
11055 11:47:43.448644
11056 11:47:43.448940 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11057 11:47:43.449038 start: 2.2.7 export-device-env (timeout 00:02:32) [common]
11058 11:47:43.449146 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11059 11:47:43.449235 end: 2.2 depthcharge-retry (duration 00:02:28) [common]
11060 11:47:43.449341 end: 2 depthcharge-action (duration 00:02:28) [common]
11061 11:47:43.449435 start: 3 lava-test-retry (timeout 00:06:34) [common]
11062 11:47:43.449522 start: 3.1 lava-test-shell (timeout 00:06:34) [common]
11063 11:47:43.449606 Using namespace: common
11065 11:47:43.549901 / # #
11066 11:47:43.550082 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11067 11:47:43.550225 <4>[ 19.853308] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11068 11:47:43.555204 #
11069 11:47:43.555484 Using /lava-10742256
11071 11:47:43.655794 / # export SHELL=/bin/sh
11072 11:47:43.656010 export SHELL=/bin/sh<4>[ 19.973132] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11073 11:47:43.660991
11075 11:47:43.761487 / # . /lava-10742256/environment
11076 11:47:43.761708 . /lava-10742256/environment<4>[ 20.093485] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11077 11:47:43.766750
11079 11:47:43.867348 / # /lava-10742256/bin/lava-test-runner /lava-10742256/0
11080 11:47:43.867556 Test shell timeout: 10s (minimum of the action and connection timeout)
11081 11:47:43.910983 /lava-10742256/bin/lava-test-runner /lava-10742256/0<4>[ 20.213523] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11082 11:47:43.911131
11083 11:47:43.911397 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.257969] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 10742256_1.5.2.3.1>
11084 11:47:43.911650 Received signal: <STARTRUN> 0_igt-kms-mediatek 10742256_1.5.2.3.1
11085 11:47:43.911740 Starting test lava.0_igt-kms-mediatek (10742256_1.5.2.3.1)
11086 11:47:43.911825 Skipping test definition patterns.
11087 11:47:43.914010 diatek
11088 11:47:43.916964 + cd /lava-10742256/0/tests/0_igt-kms-mediatek
11089 11:47:43.917076 + cat uuid
11090 11:47:43.920506 + UUID=10742256_1.5.2.3.1
11091 11:47:43.920619 + set +x
11092 11:47:43.940093 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic km<8>[ 20.289612] <LAVA_SIGNAL_TESTSET START core_auth>
11093 11:47:43.940389 Received signal: <TESTSET> START core_auth
11094 11:47:43.940494 Starting test_set core_auth
11095 11:47:43.946525 s_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11096 11:47:43.964297 <14>[ 20.313177] [IGT] core_auth: executing
11097 11:47:43.970443 IGT-Version: 1.2<14>[ 20.317568] [IGT] core_auth: starting subtest getclient-simple
11098 11:47:43.977071 7.1-g2dd77d6 (aarch64) (Linux: 6<14>[ 20.326563] [IGT] core_auth: exiting, ret=0
11099 11:47:43.983987 <3>[ 20.331796] mt7921e 0000:01:00.0: hardware init failed
11100 11:47:43.984065 .1.31 aarch64)
11101 11:47:43.987166 Starting subtest: getclient-simple
11102 11:47:43.997287 Opened device: /dev/dri/card<8>[ 20.344254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11103 11:47:43.997406 0
11104 11:47:43.997679 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11106 11:47:44.003569 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11107 11:47:44.021490 <14>[ 20.370415] [IGT] core_auth: executing
11108 11:47:44.028039 IGT-Version: 1.2<14>[ 20.375139] [IGT] core_auth: starting subtest getclient-master-drop
11109 11:47:44.034723 7.1-g2dd77d6 (aa<14>[ 20.383231] [IGT] core_auth: exiting, ret=0
11110 11:47:44.037749 rch64) (Linux: 6.1.31 aarch64)
11111 11:47:44.041242 Starting subtest: getclient-master-drop
11112 11:47:44.047918 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11114 11:47:44.050732 Opened <8>[ 20.394491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11115 11:47:44.050819 device: /dev/dri/card0
11116 11:47:44.057490 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11117 11:47:44.072107 <14>[ 20.420852] [IGT] core_auth: executing
11118 11:47:44.078405 IGT-Version: 1.2<14>[ 20.425306] [IGT] core_auth: starting subtest basic-auth
11119 11:47:44.084788 7.1-g2dd77d6 (aa<14>[ 20.432332] [IGT] core_auth: exiting, ret=0
11120 11:47:44.088002 rch64) (Linux: 6.1.31 aarch64)
11121 11:47:44.088115 Opened device: /dev/dri/card0
11122 11:47:44.098174 Starting subtest:<8>[ 20.444121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11123 11:47:44.098279 basic-auth
11124 11:47:44.098550 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11126 11:47:44.101433 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11127 11:47:44.120144 <14>[ 20.469167] [IGT] core_auth: executing
11128 11:47:44.126369 IGT-Version: 1.2<14>[ 20.473648] [IGT] core_auth: starting subtest many-magics
11129 11:47:44.130074 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11130 11:47:44.133487 Opened device: /dev/dri/card0
11131 11:47:44.136333 Starting subtest: many-magics
11132 11:47:44.139558 Reopening device failed after 1020 opens
11133 11:47:44.143227 <14>[ 20.493699] [IGT] core_auth: exiting, ret=0
11134 11:47:44.149708 [1mSubtest many-magics: SUCCESS (0.013s)[0m
11135 11:47:44.156180 <8>[ 20.504350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11136 11:47:44.156467 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11138 11:47:44.163526 <8>[ 20.512808] <LAVA_SIGNAL_TESTSET STOP>
11139 11:47:44.163816 Received signal: <TESTSET> STOP
11140 11:47:44.163928 Closing test_set core_auth
11141 11:47:44.204950 <14>[ 20.553877] [IGT] core_getclient: executing
11142 11:47:44.211597 IGT-Version: 1.2<14>[ 20.558936] [IGT] core_getclient: exiting, ret=0
11143 11:47:44.214745 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11144 11:47:44.217945 Opened device: /dev/dri/card0
11145 11:47:44.225010 S<8>[ 20.571124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11146 11:47:44.225292 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11148 11:47:44.227577 UCCESS (0.006s)
11149 11:47:44.266019 <14>[ 20.614949] [IGT] core_getstats: executing
11150 11:47:44.272139 IGT-Version: 1.2<14>[ 20.619809] [IGT] core_getstats: exiting, ret=0
11151 11:47:44.275566 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11152 11:47:44.279409 Opened device: /dev/dri/card0
11153 11:47:44.285889 S<8>[ 20.631994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11154 11:47:44.286011 UCCESS (0.006s)
11155 11:47:44.286281 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11157 11:47:44.326369 <14>[ 20.675709] [IGT] core_getversion: executing
11158 11:47:44.332917 IGT-Version: 1.2<14>[ 20.680697] [IGT] core_getversion: exiting, ret=0
11159 11:47:44.336665 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11160 11:47:44.339657 Opened device: /dev/dri/card0
11161 11:47:44.346417 S<8>[ 20.693000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11162 11:47:44.346715 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11164 11:47:44.349297 UCCESS (0.006s)
11165 11:47:44.388003 <14>[ 20.737367] [IGT] core_setmaster_vs_auth: executing
11166 11:47:44.395096 IGT-Version: 1.2<14>[ 20.743358] [IGT] core_setmaster_vs_auth: exiting, ret=0
11167 11:47:44.401295 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11168 11:47:44.401391 Opened device: /dev/dri/card0
11169 11:47:44.411103 S<8>[ 20.756571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11170 11:47:44.411204 UCCESS (0.007s)
11171 11:47:44.411446 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11173 11:47:44.437075 <8>[ 20.786237] <LAVA_SIGNAL_TESTSET START drm_read>
11174 11:47:44.437361 Received signal: <TESTSET> START drm_read
11175 11:47:44.437435 Starting test_set drm_read
11176 11:47:44.459863 <14>[ 20.809094] [IGT] drm_read: executing
11177 11:47:44.466613 IGT-Version: 1.2<14>[ 20.813696] [IGT] drm_read: exiting, ret=77
11178 11:47:44.469625 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11179 11:47:44.473165 Opened device: /dev/dri/card0
11180 11:47:44.479920 N<8>[ 20.825752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11181 11:47:44.480214 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11183 11:47:44.483009 o KMS driver or no outputs, pipes: 8, outputs: 0
11184 11:47:44.486069 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11185 11:47:44.502435 <14>[ 20.851414] [IGT] drm_read: executing
11186 11:47:44.508942 IGT-Version: 1.2<14>[ 20.856162] [IGT] drm_read: exiting, ret=77
11187 11:47:44.512136 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11188 11:47:44.515277 Opened device: /dev/dri/card0
11189 11:47:44.522172 N<8>[ 20.867489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11190 11:47:44.522446 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11192 11:47:44.525474 o KMS driver or no outputs, pipes: 8, outputs: 0
11193 11:47:44.528664 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11194 11:47:44.544532 <14>[ 20.893454] [IGT] drm_read: executing
11195 11:47:44.550583 IGT-Version: 1.2<14>[ 20.898038] [IGT] drm_read: exiting, ret=77
11196 11:47:44.554071 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11197 11:47:44.557537 Opened device: /dev/dri/card0
11198 11:47:44.563985 N<8>[ 20.910000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11199 11:47:44.564248 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11201 11:47:44.567207 o KMS driver or no outputs, pipes: 8, outputs: 0
11202 11:47:44.570820 [1mSubtest empty-block: SKIP (0.000s)[0m
11203 11:47:44.586372 <14>[ 20.935742] [IGT] drm_read: executing
11204 11:47:44.593199 IGT-Version: 1.2<14>[ 20.940424] [IGT] drm_read: exiting, ret=77
11205 11:47:44.596309 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11206 11:47:44.599919 Opened device: /dev/dri/card0
11207 11:47:44.606532 N<8>[ 20.952393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11208 11:47:44.606791 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11210 11:47:44.609633 o KMS driver or no outputs, pipes: 8, outputs: 0
11211 11:47:44.612884 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11212 11:47:44.629117 <14>[ 20.978011] [IGT] drm_read: executing
11213 11:47:44.635341 IGT-Version: 1.2<14>[ 20.982562] [IGT] drm_read: exiting, ret=77
11214 11:47:44.638523 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11215 11:47:44.641810 Opened device: /dev/dri/card0
11216 11:47:44.648366 N<8>[ 20.994399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11217 11:47:44.648622 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11219 11:47:44.652180 o KMS driver or no outputs, pipes: 8, outputs: 0
11220 11:47:44.658117 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11221 11:47:44.670704 <14>[ 21.019912] [IGT] drm_read: executing
11222 11:47:44.677559 IGT-Version: 1.2<14>[ 21.024480] [IGT] drm_read: exiting, ret=77
11223 11:47:44.680426 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11224 11:47:44.684020 Opened device: /dev/dri/card0
11225 11:47:44.690643 N<8>[ 21.035976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11226 11:47:44.690944 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11228 11:47:44.693920 o KMS driver or no outputs, pipes: 8, outputs: 0
11229 11:47:44.700167 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11230 11:47:44.713074 <14>[ 21.062187] [IGT] drm_read: executing
11231 11:47:44.719954 IGT-Version: 1.2<14>[ 21.066768] [IGT] drm_read: exiting, ret=77
11232 11:47:44.723133 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11233 11:47:44.726280 Opened device: /dev/dri/card0
11234 11:47:44.732492 N<8>[ 21.077824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11235 11:47:44.732753 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11237 11:47:44.739580 o KMS driver or no outputs, pipe<8>[ 21.088443] <LAVA_SIGNAL_TESTSET STOP>
11238 11:47:44.739832 Received signal: <TESTSET> STOP
11239 11:47:44.739905 Closing test_set drm_read
11240 11:47:44.742639 s: 8, outputs: 0
11241 11:47:44.745895 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11242 11:47:44.765610 <8>[ 21.115068] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11243 11:47:44.765968 Received signal: <TESTSET> START kms_addfb_basic
11244 11:47:44.766094 Starting test_set kms_addfb_basic
11245 11:47:44.789012 <14>[ 21.138265] [IGT] kms_addfb_basic: executing
11246 11:47:44.795679 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11247 11:47:44.801969 <14>[ 21.148116] [IGT] kms_addfb_basic: starting subtest unused-handle
11248 11:47:44.805588 Opened device: /dev/dri/card0
11249 11:47:44.805670 Starting subtest: unused-handle
11250 11:47:44.811948 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11251 11:47:44.818692 Test requiremen<14>[ 21.165458] [IGT] kms_addfb_basic: exiting, ret=0
11252 11:47:44.821876 t not met in function igt_require_i915, file ../lib/drmtest.c:721:
11253 11:47:44.832091 Test require<8>[ 21.178163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11254 11:47:44.832388 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11256 11:47:44.835157 ment: is_i915_device(fd)
11257 11:47:44.841444 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11258 11:47:44.845241 Test requirement: is_i915_device(fd)
11259 11:47:44.848578 No KMS driver or no outputs, pipes: 8, outputs: 0
11260 11:47:44.855031 <14>[ 21.203308] [IGT] kms_addfb_basic: executing
11261 11:47:44.858174 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11262 11:47:44.864470 <14>[ 21.212650] [IGT] kms_addfb_basic: starting subtest unused-pitches
11263 11:47:44.868203 Opened device: /dev/dri/card0
11264 11:47:44.871279 Starting subtest: unused-pitches
11265 11:47:44.874817 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11266 11:47:44.881159 Test requirem<14>[ 21.230216] [IGT] kms_addfb_basic: exiting, ret=0
11267 11:47:44.887694 ent not met in function igt_require_i915, file ../lib/drmtest.c:721:
11268 11:47:44.897891 Test requi<8>[ 21.242736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11269 11:47:44.897989 rement: is_i915_device(fd)
11270 11:47:44.898230 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11272 11:47:44.907498 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11273 11:47:44.910549 Test requirement: is_i915_device(fd)
11274 11:47:44.914328 No KMS driver or no outputs, pipes: 8, outputs: 0
11275 11:47:44.920547 <14>[ 21.268562] [IGT] kms_addfb_basic: executing
11276 11:47:44.923700 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11277 11:47:44.930681 <14>[ 21.278055] [IGT] kms_addfb_basic: starting subtest unused-offsets
11278 11:47:44.933943 Opened device: /dev/dri/card0
11279 11:47:44.937130 Starting subtest: unused-offsets
11280 11:47:44.940220 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11281 11:47:44.946589 Test requirem<14>[ 21.295592] [IGT] kms_addfb_basic: exiting, ret=0
11282 11:47:44.953144 ent not met in function igt_require_i915, file ../lib/drmtest.c:721:
11283 11:47:44.960120 Test requi<8>[ 21.308300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11284 11:47:44.960410 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11286 11:47:44.963285 rement: is_i915_device(fd)
11287 11:47:44.970090 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11288 11:47:44.973308 Test requirement: is_i915_device(fd)
11289 11:47:44.980043 No KMS driver or no outputs, pipes: 8, outputs: 0
11290 11:47:44.982997 <14>[ 21.334111] [IGT] kms_addfb_basic: executing
11291 11:47:44.990016 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11292 11:47:44.996602 <14>[ 21.343798] [IGT] kms_addfb_basic: starting subtest unused-modifier
11293 11:47:44.999510 Opened device: /dev/dri/card0
11294 11:47:45.003095 Starting subtest: unused-modifier
11295 11:47:45.006599 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11296 11:47:45.012777 Test requir<14>[ 21.361291] [IGT] kms_addfb_basic: exiting, ret=0
11297 11:47:45.019403 ement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11298 11:47:45.026176 Test req<8>[ 21.374093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11299 11:47:45.026524 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11301 11:47:45.029803 uirement: is_i915_device(fd)
11302 11:47:45.036142 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11303 11:47:45.039420 Test requirement: is_i915_device(fd)
11304 11:47:45.045641 No KMS driver or no outputs, pipes: 8, outputs: 0
11305 11:47:45.049489 <14>[ 21.399655] [IGT] kms_addfb_basic: executing
11306 11:47:45.055884 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11307 11:47:45.062573 <14>[ 21.409263] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11308 11:47:45.065862 Opened device: /dev/dri/card0
11309 11:47:45.069043 Starting subtest: clobberred-modifier
11310 11:47:45.078537 Test requirement not met in function igt_require_i915, fil<14>[ 21.427231] [IGT] kms_addfb_basic: exiting, ret=77
11311 11:47:45.082207 e ../lib/drmtest.c:721:
11312 11:47:45.085518 Test requirement: is_i915_device(fd)
11313 11:47:45.092235 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11315 11:47:45.095037 [1mSubtest clobb<8>[ 21.440018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11316 11:47:45.095164 erred-modifier: SKIP (0.000s)[0m
11317 11:47:45.105087 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11318 11:47:45.108113 Test requirement: is_i915_device(fd)
11319 11:47:45.118315 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 21.466035] [IGT] kms_addfb_basic: executing
11320 11:47:45.118441 rmtest.c:721:
11321 11:47:45.121326 Test requirement: is_i915_device(fd)
11322 11:47:45.131189 No KMS driv<14>[ 21.476904] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11323 11:47:45.135033 er or no outputs, pipes: 8, outputs: 0
11324 11:47:45.141496 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11325 11:47:45.147939 Opened device: /dev/dri/<14>[ 21.495342] [IGT] kms_addfb_basic: exiting, ret=77
11326 11:47:45.148027 card0
11327 11:47:45.151014 Starting subtest: invalid-smem-bo-on-discrete
11328 11:47:45.161159 Test requirement not met i<8>[ 21.508282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11329 11:47:45.161418 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11331 11:47:45.167380 n function igt_require_intel, file ../lib/drmtest.c:716:
11332 11:47:45.171197 Test requirement: is_intel_device(fd)
11333 11:47:45.177625 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11334 11:47:45.187564 Test requirement not met in function igt_require_i915, file ../lib/<14>[ 21.534854] [IGT] kms_addfb_basic: executing
11335 11:47:45.187649 drmtest.c:721:
11336 11:47:45.190538 Test requirement: is_i915_device(fd)
11337 11:47:45.197114 Test requi<14>[ 21.545739] [IGT] kms_addfb_basic: starting subtest legacy-format
11338 11:47:45.203782 rement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11339 11:47:45.206993 Test requirement: is_i915_device(fd)
11340 11:47:45.214026 No KMS driver or no outputs, pipes: 8, outputs: 0
11341 11:47:45.217003 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11342 11:47:45.220024 Opened device: /dev/dri/card0
11343 11:47:45.226698 Starting subtes<14>[ 21.575380] [IGT] kms_addfb_basic: exiting, ret=0
11344 11:47:45.230271 t: legacy-format
11345 11:47:45.233331 Successfully fuzzed 10000 {bpp, depth} variations
11346 11:47:45.239875 [1mSubtest<8>[ 21.588252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11347 11:47:45.240155 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11349 11:47:45.243020 legacy-format: SUCCESS (0.013s)[0m
11350 11:47:45.252941 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11351 11:47:45.256640 Test requirement: is_i915_device(fd)
11352 11:47:45.266250 Test requirement not met in function igt_require_i915, file ../li<14>[ 21.614183] [IGT] kms_addfb_basic: executing
11353 11:47:45.266338 b/drmtest.c:721:
11354 11:47:45.269538 Test requirement: is_i915_device(fd)
11355 11:47:45.279646 No KMS driver or no outputs, pipes: 8, o<14>[ 21.626699] [IGT] kms_addfb_basic: starting subtest no-handle
11356 11:47:45.279729 utputs: 0
11357 11:47:45.286123 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11358 11:47:45.293056 Opened device: /dev/d<14>[ 21.641621] [IGT] kms_addfb_basic: exiting, ret=0
11359 11:47:45.293140 ri/card0
11360 11:47:45.296129 Starting subtest: no-handle
11361 11:47:45.305860 [1mSubtest no-handle: SUCCESS (0.000s)[<8>[ 21.653651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11362 11:47:45.306022 0m
11363 11:47:45.306263 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11365 11:47:45.316117 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11366 11:47:45.318959 Test requirement: is_i915_device(fd)
11367 11:47:45.325640 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11368 11:47:45.332383 Test requirement<14>[ 21.679150] [IGT] kms_addfb_basic: executing
11369 11:47:45.332465 : is_i915_device(fd)
11370 11:47:45.338658 No KMS driver or no outputs, pipes: 8, outputs: 0
11371 11:47:45.345508 IGT-Version: 1.27.1-g2d<14>[ 21.692799] [IGT] kms_addfb_basic: starting subtest basic
11372 11:47:45.348795 d77d6 (aarch64) (Linux: 6.1.31 aarch64)
11373 11:47:45.352052 Opened device: /dev/dri/card0
11374 11:47:45.352132 Starting subtest: basic
11375 11:47:45.358411 <14>[ 21.706588] [IGT] kms_addfb_basic: exiting, ret=0
11376 11:47:45.358494
11377 11:47:45.362115 [1mSubtest basic: SUCCESS (0.000s)[0m
11378 11:47:45.371506 Test requirement not met in function i<8>[ 21.718636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11379 11:47:45.371766 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11381 11:47:45.375417 gt_require_i915, file ../lib/drmtest.c:721:
11382 11:47:45.378600 Test requirement: is_i915_device(fd)
11383 11:47:45.385006 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11384 11:47:45.388196 Test requirement: is_i915_device(fd)
11385 11:47:45.394624 No KMS driver or no <14>[ 21.744134] [IGT] kms_addfb_basic: executing
11386 11:47:45.397912 outputs, pipes: 8, outputs: 0
11387 11:47:45.404457 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11388 11:47:45.411371 O<14>[ 21.757657] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11389 11:47:45.414332 pened device: /dev/dri/card0
11390 11:47:45.414441 Starting subtest: bad-pitch-0
11391 11:47:45.424565 [1mSubtest bad-pitch-0: SUCCESS (0<14>[ 21.771935] [IGT] kms_addfb_basic: exiting, ret=0
11392 11:47:45.424678 .000s)[0m
11393 11:47:45.437482 Test requirement not met in function igt_require_i915, file ../lib/d<8>[ 21.784369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11394 11:47:45.437611 rmtest.c:721:
11395 11:47:45.437895 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11397 11:47:45.440999 Test requirement: is_i915_device(fd)
11398 11:47:45.450751 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11399 11:47:45.453912 Test requirement: is_i915_device(fd)
11400 11:47:45.457013 No KMS driver or no outputs, pipes: 8, outputs: 0
11401 11:47:45.460635 <14>[ 21.809986] [IGT] kms_addfb_basic: executing
11402 11:47:45.460718
11403 11:47:45.467548 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11404 11:47:45.470665 Opened device: /dev/dri/card0
11405 11:47:45.476931 <14>[ 21.823572] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11406 11:47:45.480138 Starting subtest: bad-pitch-32
11407 11:47:45.484067 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11408 11:47:45.490308 Test requirement<14>[ 21.838273] [IGT] kms_addfb_basic: exiting, ret=0
11409 11:47:45.496941 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11410 11:47:45.503292 Test requirem<8>[ 21.850396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11411 11:47:45.503546 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11413 11:47:45.506634 ent: is_i915_device(fd)
11414 11:47:45.513341 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11415 11:47:45.516615 Test requirement: is_i915_device(fd)
11416 11:47:45.520048 No KMS driver or no outputs, pipes: 8, outputs: 0
11417 11:47:45.527039 <14>[ 21.876108] [IGT] kms_addfb_basic: executing
11418 11:47:45.533503 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11419 11:47:45.533590 Opened device: /dev/dri/card0
11420 11:47:45.540114 <14>[ 21.888376] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11421 11:47:45.543503 Starting subtest: bad-pitch-63
11422 11:47:45.549890 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11423 11:47:45.553452 Test requirement<14>[ 21.903001] [IGT] kms_addfb_basic: exiting, ret=0
11424 11:47:45.559621 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11425 11:47:45.569765 Test requirem<8>[ 21.915420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11426 11:47:45.569874 ent: is_i915_device(fd)
11427 11:47:45.570113 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11429 11:47:45.579869 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11430 11:47:45.582959 Test requirement: is_i915_device(fd)
11431 11:47:45.586195 No KMS driver or no outputs, pipes: 8, outputs: 0
11432 11:47:45.593140 <14>[ 21.941476] [IGT] kms_addfb_basic: executing
11433 11:47:45.596283 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11434 11:47:45.599447 Opened device: /dev/dri/card0
11435 11:47:45.605770 <14>[ 21.953862] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11436 11:47:45.609644 Starting subtest: bad-pitch-128
11437 11:47:45.612746 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11438 11:47:45.618971 Test requireme<14>[ 21.968513] [IGT] kms_addfb_basic: exiting, ret=0
11439 11:47:45.625900 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11440 11:47:45.635927 Test requir<8>[ 21.981137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11441 11:47:45.636035 ement: is_i915_device(fd)
11442 11:47:45.636277 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11444 11:47:45.645278 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11445 11:47:45.648791 Test requirement: is_i915_device(fd)
11446 11:47:45.651914 No KMS driver or no outputs, pipes: 8, outputs: 0
11447 11:47:45.655493 <14>[ 22.006190] [IGT] kms_addfb_basic: executing
11448 11:47:45.661948 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11449 11:47:45.665527 Opened device: /dev/dri/card0
11450 11:47:45.671686 <14>[ 22.018298] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11451 11:47:45.675315 Starting subtest: bad-pitch-256
11452 11:47:45.678405 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11453 11:47:45.684961 Test requireme<14>[ 22.033255] [IGT] kms_addfb_basic: exiting, ret=0
11454 11:47:45.691405 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11455 11:47:45.698376 Test requir<8>[ 22.045523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11456 11:47:45.698632 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11458 11:47:45.701683 ement: is_i915_device(fd)
11459 11:47:45.707900 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11460 11:47:45.711660 Test requirement: is_i915_device(fd)
11461 11:47:45.714854 No KMS driver or no outputs, pipes: 8, outputs: 0
11462 11:47:45.721716 <14>[ 22.070774] [IGT] kms_addfb_basic: executing
11463 11:47:45.727884 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11464 11:47:45.727973 Opened device: /dev/dri/card0
11465 11:47:45.734988 <14>[ 22.082820] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11466 11:47:45.737716 Starting subtest: bad-pitch-1024
11467 11:47:45.744513 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11468 11:47:45.751173 Test require<14>[ 22.097802] [IGT] kms_addfb_basic: exiting, ret=0
11469 11:47:45.754745 ment not met in function igt_require_i915, file ../lib/drmtest.c:721:
11470 11:47:45.764162 Test requ<8>[ 22.109859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11471 11:47:45.764420 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11473 11:47:45.767685 irement: is_i915_device(fd)
11474 11:47:45.774183 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11475 11:47:45.777746 Test requirement: is_i915_device(fd)
11476 11:47:45.780659 No KMS driver or no outputs, pipes: 8, outputs: 0
11477 11:47:45.787251 <14>[ 22.135967] [IGT] kms_addfb_basic: executing
11478 11:47:45.790449 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11479 11:47:45.794291 Opened device: /dev/dri/card0
11480 11:47:45.800745 <14>[ 22.148257] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11481 11:47:45.803968 Starting subtest: bad-pitch-999
11482 11:47:45.807227 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11483 11:47:45.813542 Test requireme<14>[ 22.163015] [IGT] kms_addfb_basic: exiting, ret=0
11484 11:47:45.820462 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11485 11:47:45.830483 Test requir<8>[ 22.175980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11486 11:47:45.830579 ement: is_i915_device(fd)
11487 11:47:45.830819 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11489 11:47:45.840049 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11490 11:47:45.843487 Test requirement: is_i915_device(fd)
11491 11:47:45.846793 No KMS driver or no outputs, pipes: 8, outputs: 0
11492 11:47:45.853206 <14>[ 22.201688] [IGT] kms_addfb_basic: executing
11493 11:47:45.856903 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11494 11:47:45.859698 Opened device: /dev/dri/card0
11495 11:47:45.866603 <14>[ 22.214028] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11496 11:47:45.869411 Starting subtest: bad-pitch-65536
11497 11:47:45.876123 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11498 11:47:45.879738 Test requi<14>[ 22.228768] [IGT] kms_addfb_basic: exiting, ret=0
11499 11:47:45.886162 rement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11500 11:47:45.896281 Test re<8>[ 22.241625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11501 11:47:45.896400 quirement: is_i915_device(fd)
11502 11:47:45.896669 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11504 11:47:45.905849 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11505 11:47:45.909050 Test requirement: is_i915_device(fd)
11506 11:47:45.912275 No KMS driver or no outputs, pipes: 8, outputs: 0
11507 11:47:45.919231 <14>[ 22.267462] [IGT] kms_addfb_basic: executing
11508 11:47:45.922367 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11509 11:47:45.925548 Opened device: /dev/dri/card0
11510 11:47:45.936282 <14>[ 22.282007] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11511 11:47:45.939356 Starting subtest: invalid-get-prop-any
11512 11:47:45.945693 [1mSubtest invalid-get-<14>[ 22.294130] [IGT] kms_addfb_basic: exiting, ret=0
11513 11:47:45.949184 prop-any: SUCCESS (0.000s)[0m
11514 11:47:45.959414 Test requirement not met in function igt_require<8>[ 22.306515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11515 11:47:45.959706 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11517 11:47:45.962428 _i915, file ../lib/drmtest.c:721:
11518 11:47:45.966046 Test requirement: is_i915_device(fd)
11519 11:47:45.972415 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11520 11:47:45.975436 Test requirement: is_i915_device(fd)
11521 11:47:45.985661 No KMS driver or no outputs, p<14>[ 22.332773] [IGT] kms_addfb_basic: executing
11522 11:47:45.985751 ipes: 8, outputs: 0
11523 11:47:45.991959 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11524 11:47:45.995606 Opened device: /dev/dri/card0
11525 11:47:46.001957 <14>[ 22.348475] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11526 11:47:46.005055 Starting subtest: invalid-get-prop
11527 11:47:46.011491 [1mSubtest invalid-get-prop<14>[ 22.360485] [IGT] kms_addfb_basic: exiting, ret=0
11528 11:47:46.015286 : SUCCESS (0.000s)[0m
11529 11:47:46.024708 Test requirement not met in function igt_require_i915, f<8>[ 22.372601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11530 11:47:46.024969 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11532 11:47:46.028012 ile ../lib/drmtest.c:721:
11533 11:47:46.031876 Test requirement: is_i915_device(fd)
11534 11:47:46.038084 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11535 11:47:46.041324 Test requirement: is_i915_device(fd)
11536 11:47:46.048159 No KMS driver or no ou<14>[ 22.397813] [IGT] kms_addfb_basic: executing
11537 11:47:46.051330 tputs, pipes: 8, outputs: 0
11538 11:47:46.058018 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11539 11:47:46.058103 Opened device: /dev/dri/card0
11540 11:47:46.067966 <14>[ 22.412739] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11541 11:47:46.070956 Starting subtest: invalid-set-prop-any
11542 11:47:46.077902 [1mSubtest invalid-set-<14>[ 22.425988] [IGT] kms_addfb_basic: exiting, ret=0
11543 11:47:46.080924 prop-any: SUCCESS (0.000s)[0m
11544 11:47:46.090544 Test requirement not met in function igt_require<8>[ 22.438219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11545 11:47:46.090866 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11547 11:47:46.094140 _i915, file ../lib/drmtest.c:721:
11548 11:47:46.097695 Test requirement: is_i915_device(fd)
11549 11:47:46.104276 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11550 11:47:46.107373 Test requirement: is_i915_device(fd)
11551 11:47:46.113853 No KMS driver <14>[ 22.463493] [IGT] kms_addfb_basic: executing
11552 11:47:46.117007 or no outputs, pipes: 8, outputs: 0
11553 11:47:46.123483 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11554 11:47:46.130372 Opened devi<14>[ 22.478598] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11555 11:47:46.133721 ce: /dev/dri/card0
11556 11:47:46.136982 Starting subtest: invalid-set-prop
11557 11:47:46.140060 [1mSubt<14>[ 22.490461] [IGT] kms_addfb_basic: exiting, ret=0
11558 11:47:46.146988 est invalid-set-prop: SUCCESS (0.000s)[0m
11559 11:47:46.156478 Test requirement not met in function<8>[ 22.502433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11560 11:47:46.156734 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11562 11:47:46.159621 igt_require_i915, file ../lib/drmtest.c:721:
11563 11:47:46.163558 Test requirement: is_i915_device(fd)
11564 11:47:46.169802 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11565 11:47:46.173545 Test requirement: is_i915_device(fd)
11566 11:47:46.179500 No KMS driver or n<14>[ 22.528694] [IGT] kms_addfb_basic: executing
11567 11:47:46.183192 o outputs, pipes: 8, outputs: 0
11568 11:47:46.189675 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11569 11:47:46.189763 Opened device: /dev/dri/card0
11570 11:47:46.197015 <14>[ 22.546596] [IGT] kms_addfb_basic: starting subtest master-rmfb
11571 11:47:46.200418 Starting subtest: master-rmfb
11572 11:47:46.207117 [1mSubtest maste<14>[ 22.555807] [IGT] kms_addfb_basic: exiting, ret=0
11573 11:47:46.210169 r-rmfb: SUCCESS (0.000s)[0m
11574 11:47:46.219987 Test requirement not met in function igt_require_i<8>[ 22.568574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11575 11:47:46.220246 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11577 11:47:46.223790 915, file ../lib/drmtest.c:721:
11578 11:47:46.227119 Test requirement: is_i915_device(fd)
11579 11:47:46.236296 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11580 11:47:46.240102 Test requirement: is_i915_device(fd)
11581 11:47:46.243243 No KMS driver or<14>[ 22.593373] [IGT] kms_addfb_basic: executing
11582 11:47:46.246428 no outputs, pipes: 8, outputs: 0
11583 11:47:46.252855 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11584 11:47:46.255895 Opened device: /dev/dri/card0
11585 11:47:46.267103 <14>[ 22.613150] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11586 11:47:46.273651 Starting subtest<14>[ 22.621112] [IGT] kms_addfb_basic: exiting, ret=0
11587 11:47:46.273733 : addfb25-modifier-no-flag
11588 11:47:46.287088 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000<8>[ 22.633686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11589 11:47:46.287178 s)[0m
11590 11:47:46.287420 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11592 11:47:46.296624 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11593 11:47:46.300373 Test requirement: is_i915_device(fd)
11594 11:47:46.306607 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11595 11:47:46.313137 Test require<14>[ 22.660208] [IGT] kms_addfb_basic: executing
11596 11:47:46.313222 ment: is_i915_device(fd)
11597 11:47:46.319846 No KMS driver or no outputs, pipes: 8, outputs: 0
11598 11:47:46.323572 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11599 11:47:46.326766 Opened device: /dev/dri/card0
11600 11:47:46.333146 <14>[ 22.680582] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11601 11:47:46.336321 Starting subtest: addfb25-bad-modifier
11602 11:47:46.349619 (kms_addfb_basic:427) CRITICAL: Test assertion failure function addfb25_<14>[ 22.697750] [IGT] kms_addfb_basic: exiting, ret=98
11603 11:47:46.352860 tests, file ../tests/kms_addfb_basic.c:662:
11604 11:47:46.362509 (kms_addfb_basic:427) CRITICAL: Fai<8>[ 22.709799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11605 11:47:46.362799 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11607 11:47:46.378935 led assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11608 11:47:46.385515 (kms_addfb_basic:427) CRITICAL: error<14>[ 22.735684] [IGT] kms_addfb_basic: executing
11609 11:47:46.385611 : 0 != -1
11610 11:47:46.389130 Stack trace:
11611 11:47:46.392450 #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11612 11:47:46.395679 #1 [<unknown>+0xb90647e0]
11613 11:47:46.398956 #2 [<unknown>+0xb9066278]
11614 11:47:46.399040 #3 [<unknown>+0xb906167c]
11615 11:47:46.405275 #4 [__libc_st<14>[ 22.755336] [IGT] kms_addfb_basic: exiting, ret=77
11616 11:47:46.408948 art_main+0xe8]
11617 11:47:46.411968 #5 [<unknown>+0xb90616b4]
11618 11:47:46.412050 #6 [<unknown>+0xb90616b4]
11619 11:47:46.422174 Subtes<8>[ 22.767412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11620 11:47:46.422480 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11622 11:47:46.425304 t addfb25-bad-modifier failed.
11623 11:47:46.425385 **** DEBUG ****
11624 11:47:46.435321 (kms_addfb_basic:427) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11625 11:47:46.444946 (kms_addfb_basic:427) CRITICAL: Test assertion failure function <14>[ 22.794412] [IGT] kms_addfb_basic: executing
11626 11:47:46.448199 addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11627 11:47:46.464533 (kms_addfb_basic:427) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0<14>[ 22.813830] [IGT] kms_addfb_basic: exiting, ret=77
11628 11:47:46.481342 xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -<8>[ 22.826009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11629 11:47:46.481447 1
11630 11:47:46.481690 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11632 11:47:46.484600 (kms_addfb_basic:427) CRITICAL: error: 0 != -1
11633 11:47:46.487671 (kms_addfb_basic:427) igt_core-INFO: Stack trace:
11634 11:47:46.497646 (kms_addfb_basic:427) igt_core-INFO: #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11635 11:47:46.504275 (kms_addfb_basic:427<14>[ 22.852111] [IGT] kms_addfb_basic: executing
11636 11:47:46.507245 ) igt_core-INFO: #1 [<unknown>+0xb90647e0]
11637 11:47:46.514248 (kms_addfb_basic:427) igt_core-INFO: #2 [<unknown>+0xb9066278]
11638 11:47:46.523974 (kms_addfb_basic:427) igt_core-INFO: #3 [<unknown>+0xb906167c]<14>[ 22.871779] [IGT] kms_addfb_basic: exiting, ret=77
11639 11:47:46.524061
11640 11:47:46.530442 (kms_addfb_basic:427) igt_core-INFO: #4 [__libc_start_main+0xe8]
11641 11:47:46.540165 (kms_addfb<8>[ 22.883900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11642 11:47:46.540428 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11644 11:47:46.543340 _basic:427) igt_core-INFO: #5 [<unknown>+0xb90616b4]
11645 11:47:46.550256 (kms_addfb_basic:427) igt_core-INFO: #6 [<unknown>+0xb90616b4]
11646 11:47:46.550337 **** END ****
11647 11:47:46.556475 [1mSubtest addfb25-bad-modifier: FAIL (0.009s)[0m
11648 11:47:46.563370 Test requirement not met in func<14>[ 22.911312] [IGT] kms_addfb_basic: executing
11649 11:47:46.566570 tion igt_require_i915, file ../lib/drmtest.c:721:
11650 11:47:46.569696 Test requirement: is_i915_device(fd)
11651 11:47:46.576647 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11652 11:47:46.583079 Test<14>[ 22.932221] [IGT] kms_addfb_basic: exiting, ret=77
11653 11:47:46.586214 requirement: is_i915_device(fd)
11654 11:47:46.596100 No KMS driver or no outputs, pipes: 8, outputs<8>[ 22.944264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11655 11:47:46.596368 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11657 11:47:46.599916 : 0
11658 11:47:46.602945 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11659 11:47:46.606418 Opened device: /dev/dri/card0
11660 11:47:46.612920 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11661 11:47:46.616519 Test requirement: is_i915_device(fd)
11662 11:47:46.623073 [1<14>[ 22.970472] [IGT] kms_addfb_basic: executing
11663 11:47:46.626131 mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11664 11:47:46.635893 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11665 11:47:46.642353 Test requirement: is_i915_device<14>[ 22.991526] [IGT] kms_addfb_basic: exiting, ret=77
11666 11:47:46.642444 (fd)
11667 11:47:46.646054 No KMS driver or no outputs, pipes: 8, outputs: 0
11668 11:47:46.656100 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11670 11:47:46.658986 IGT-Version: 1.27.1-g2d<8>[ 23.003382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11671 11:47:46.662094 d77d6 (aarch64) (Linux: 6.1.31 aarch64)
11672 11:47:46.662173 Opened device: /dev/dri/card0
11673 11:47:46.672170 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11674 11:47:46.675904 Test requirement: is_i915_device(fd)
11675 11:47:46.682170 [1mSubtest addfb25-x-tiled-leg<14>[ 23.030206] [IGT] kms_addfb_basic: executing
11676 11:47:46.682249 acy: SKIP (0.000s)[0m
11677 11:47:46.691874 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11678 11:47:46.695618 Test requirement: is_i915_device(fd)
11679 11:47:46.702029 No KMS driver or no outputs, pi<14>[ 23.050880] [IGT] kms_addfb_basic: exiting, ret=77
11680 11:47:46.705299 pes: 8, outputs: 0
11681 11:47:46.715537 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch6<8>[ 23.062509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11682 11:47:46.715789 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11684 11:47:46.718341 4)
11685 11:47:46.718412 Opened device: /dev/dri/card0
11686 11:47:46.728485 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11687 11:47:46.731551 Test requirement: is_i915_device(fd)
11688 11:47:46.735131 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11689 11:47:46.741963 Te<14>[ 23.089320] [IGT] kms_addfb_basic: executing
11690 11:47:46.747907 st requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11691 11:47:46.751463 Test requirement: is_i915_device(fd)
11692 11:47:46.755128 No KMS driver or no outputs, pipes: 8, outputs: 0
11693 11:47:46.761358 IGT-Ve<14>[ 23.109823] [IGT] kms_addfb_basic: exiting, ret=77
11694 11:47:46.764500 rsion: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11695 11:47:46.774446 Opened device: /dev/dr<8>[ 23.121727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11696 11:47:46.774752 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11698 11:47:46.778209 i/card0
11699 11:47:46.784639 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11700 11:47:46.787861 Test requirement: is_i915_device(fd)
11701 11:47:46.794111 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11702 11:47:46.800913 Test requir<14>[ 23.148417] [IGT] kms_addfb_basic: executing
11703 11:47:46.801000 ement: is_i915_device(fd)
11704 11:47:46.807360 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11705 11:47:46.811154 No KMS driver or no outputs, pipes: 8, outputs: 0
11706 11:47:46.821026 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux<14>[ 23.169081] [IGT] kms_addfb_basic: exiting, ret=77
11707 11:47:46.821167 : 6.1.31 aarch64)
11708 11:47:46.824094 Opened device: /dev/dri/card0
11709 11:47:46.834280 Test requirement not met in fu<8>[ 23.180791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11710 11:47:46.834596 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11712 11:47:46.837263 nction igt_require_i915, file ../lib/drmtest.c:721:
11713 11:47:46.840791 Test requirement: is_i915_device(fd)
11714 11:47:46.847334 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11715 11:47:46.850251 Test requirement: is_i915_device(fd)
11716 11:47:46.857089 [1mSubtest <14>[ 23.206415] [IGT] kms_addfb_basic: executing
11717 11:47:46.860694 framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11718 11:47:46.867156 No KMS driver or no outputs, pipes: 8, outputs: 0
11719 11:47:46.870017 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11720 11:47:46.877016 Opened device: <14>[ 23.227157] [IGT] kms_addfb_basic: exiting, ret=77
11721 11:47:46.880265 /dev/dri/card0
11722 11:47:46.890205 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11724 11:47:46.893189 Test requirement not met in function igt_require_i915, file ../l<8>[ 23.238578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11725 11:47:46.893265 ib/drmtest.c:721:
11726 11:47:46.897037 Test requirement: is_i915_device(fd)
11727 11:47:46.903422 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11728 11:47:46.906448 Test requirement: is_i915_device(fd)
11729 11:47:46.913467 [1mSubtest tile-pitch-mismatc<14>[ 23.263395] [IGT] kms_addfb_basic: executing
11730 11:47:46.916523 h: SKIP (0.000s)[0m
11731 11:47:46.920216 No KMS driver or no outputs, pipes: 8, outputs: 0
11732 11:47:46.926454 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11733 11:47:46.929503 Opened device: /dev/dri/card0
11734 11:47:46.936098 Test req<14>[ 23.283678] [IGT] kms_addfb_basic: exiting, ret=77
11735 11:47:46.942978 uirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11736 11:47:46.949028 Test <8>[ 23.295734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11737 11:47:46.949337 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11739 11:47:46.952689 requirement: is_i915_device(fd)
11740 11:47:46.959189 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11741 11:47:46.962890 Test requirement: is_i915_device(fd)
11742 11:47:46.965929 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11743 11:47:46.972094 No KMS driver or <14>[ 23.321159] [IGT] kms_addfb_basic: executing
11744 11:47:46.975568 no outputs, pipes: 8, outputs: 0
11745 11:47:46.982177 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11746 11:47:46.982260 Opened device: /dev/dri/card0
11747 11:47:46.992385 Test requirement not met in function igt_requir<14>[ 23.342021] [IGT] kms_addfb_basic: exiting, ret=77
11748 11:47:46.995601 e_i915, file ../lib/drmtest.c:721:
11749 11:47:46.998743 Test requirement: is_i915_device(fd)
11750 11:47:47.005275 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11752 11:47:47.008670 Test r<8>[ 23.354237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11753 11:47:47.014960 equirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11754 11:47:47.018623 Test requirement: is_i915_device(fd)
11755 11:47:47.021712 No KMS driver or no outputs, pipes: 8, outputs: 0
11756 11:47:47.024916 [1mSubtest size-max: SKIP (0.000s)[0m
11757 11:47:47.031780 IGT-Version: 1.27<14>[ 23.380256] [IGT] kms_addfb_basic: executing
11758 11:47:47.034981 .1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11759 11:47:47.038011 Opened device: /dev/dri/card0
11760 11:47:47.045015 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11761 11:47:47.051670 Test requiremen<14>[ 23.400561] [IGT] kms_addfb_basic: exiting, ret=77
11762 11:47:47.054689 t: is_i915_device(fd)
11763 11:47:47.064375 Test requirement not met in function igt_require_i915, fi<8>[ 23.412411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11764 11:47:47.064684 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11766 11:47:47.067946 le ../lib/drmtest.c:721:
11767 11:47:47.071204 Test requirement: is_i915_device(fd)
11768 11:47:47.074368 No KMS driver or no outputs, pipes: 8, outputs: 0
11769 11:47:47.077528 [1mSubtest too-wide: SKIP (0.000s)[0m
11770 11:47:47.084110 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11771 11:47:47.087675 Open<14>[ 23.437814] [IGT] kms_addfb_basic: executing
11772 11:47:47.090691 ed device: /dev/dri/card0
11773 11:47:47.097704 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11774 11:47:47.100974 Test requirement: is_i915_device(fd)
11775 11:47:47.110605 Test requirement not met in <14>[ 23.458725] [IGT] kms_addfb_basic: exiting, ret=77
11776 11:47:47.114511 function igt_require_i915, file ../lib/drmtest.c:721:
11777 11:47:47.123955 Test requirement: is_i915<8>[ 23.470215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11778 11:47:47.124239 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11780 11:47:47.127112 _device(fd)
11781 11:47:47.130361 No KMS driver or no outputs, pipes: 8, outputs: 0
11782 11:47:47.134023 [1mSubtest too-high: SKIP (0.000s)[0m
11783 11:47:47.140237 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11784 11:47:47.143447 Opened device: /dev/dri/card0
11785 11:47:47.150324 Test requirement not met<14>[ 23.497707] [IGT] kms_addfb_basic: executing
11786 11:47:47.153433 in function igt_require_i915, file ../lib/drmtest.c:721:
11787 11:47:47.156527 Test requirement: is_i915_device(fd)
11788 11:47:47.169793 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 23.518220] [IGT] kms_addfb_basic: exiting, ret=77
11789 11:47:47.169917 1:
11790 11:47:47.173465 Test requirement: is_i915_device(fd)
11791 11:47:47.183407 No KMS driver or no outputs, pipes: 8,<8>[ 23.530031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11792 11:47:47.183710 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11794 11:47:47.186518 outputs: 0
11795 11:47:47.189574 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11796 11:47:47.193255 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11797 11:47:47.196239 Opened device: /dev/dri/card0
11798 11:47:47.209555 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 23.556787] [IGT] kms_addfb_basic: executing
11799 11:47:47.209668 est.c:721:
11800 11:47:47.212696 Test requirement: is_i915_device(fd)
11801 11:47:47.219286 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11802 11:47:47.222512 Test requirement: is_i915_device(fd)
11803 11:47:47.229515 No KM<14>[ 23.577516] [IGT] kms_addfb_basic: exiting, ret=77
11804 11:47:47.232721 S driver or no outputs, pipes: 8, outputs: 0
11805 11:47:47.242496 [1mSubtest small-bo: SKIP (0.000s<8>[ 23.589425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11806 11:47:47.242604 )[0m
11807 11:47:47.242869 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11809 11:47:47.249050 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11810 11:47:47.252646 Opened device: /dev/dri/card0
11811 11:47:47.259130 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11812 11:47:47.266064 Test requirement: is_i9<14>[ 23.615787] [IGT] kms_addfb_basic: executing
11813 11:47:47.266159 15_device(fd)
11814 11:47:47.275716 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11815 11:47:47.278960 Test requirement: is_i915_device(fd)
11816 11:47:47.285912 No KMS driver or no outputs, pipes: 8, o<14>[ 23.635503] [IGT] kms_addfb_basic: exiting, ret=77
11817 11:47:47.288995 utputs: 0
11818 11:47:47.292060 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11819 11:47:47.302428 IGT-Versio<8>[ 23.647408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11820 11:47:47.302739 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11822 11:47:47.305635 n: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11823 11:47:47.308830 Opened device: /dev/dri/card0
11824 11:47:47.315259 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11825 11:47:47.318534 Test requirement: is_i915_device(fd)
11826 11:47:47.325261 Test requirement n<14>[ 23.674481] [IGT] kms_addfb_basic: executing
11827 11:47:47.332162 ot met in function igt_require_i915, file ../lib/drmtest.c:721:
11828 11:47:47.335344 Test requirement: is_i915_device(fd)
11829 11:47:47.338424 No KMS driver or no outputs, pipes: 8, outputs: 0
11830 11:47:47.345087 [1mSubtest addfb25-y-<14>[ 23.695306] [IGT] kms_addfb_basic: exiting, ret=77
11831 11:47:47.348215 tiled-legacy: SKIP (0.000s)[0m
11832 11:47:47.361865 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: <8>[ 23.707200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11833 11:47:47.361979 6.1.31 aarch64)
11834 11:47:47.362259 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11836 11:47:47.368272 Opened device: <8>[ 23.716617] <LAVA_SIGNAL_TESTSET STOP>
11837 11:47:47.368355 /dev/dri/card0
11838 11:47:47.368609 Received signal: <TESTSET> STOP
11839 11:47:47.368711 Closing test_set kms_addfb_basic
11840 11:47:47.374751 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11841 11:47:47.378317 Test requirement: is_i915_device(fd)
11842 11:47:47.387895 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11843 11:47:47.394750 Test requirement: is_i915_device(fd)<8>[ 23.743322] <LAVA_SIGNAL_TESTSET START kms_atomic>
11844 11:47:47.394910
11845 11:47:47.395205 Received signal: <TESTSET> START kms_atomic
11846 11:47:47.395315 Starting test_set kms_atomic
11847 11:47:47.397907 No KMS driver or no outputs, pipes: 8, outputs: 0
11848 11:47:47.404646 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11849 11:47:47.411286 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11850 11:47:47.411412 Opened device: /dev/dri/card0
11851 11:47:47.417610 Test requirement not<14>[ 23.767254] [IGT] kms_atomic: executing
11852 11:47:47.424374 met in function<14>[ 23.773564] [IGT] kms_atomic: exiting, ret=77
11853 11:47:47.427505 igt_require_i915, file ../lib/drmtest.c:721:
11854 11:47:47.437447 Test requirement: is_i915_device(<8>[ 23.784733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11855 11:47:47.437791 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11857 11:47:47.440786 fd)
11858 11:47:47.447414 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11859 11:47:47.450541 Test requirement: is_i915_device(fd)
11860 11:47:47.453711 No KMS driver or no outputs, pipes: 8, outputs: 0
11861 11:47:47.463718 [1mSubtest addfb25-y-tiled-small-legacy: SKIP <14>[ 23.811731] [IGT] kms_atomic: executing
11862 11:47:47.463833 (0.000s)[0m
11863 11:47:47.467299 IG<14>[ 23.817870] [IGT] kms_atomic: exiting, ret=77
11864 11:47:47.473922 T-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11865 11:47:47.483436 Opened device: /de<8>[ 23.829182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11866 11:47:47.483566 v/dri/card0
11867 11:47:47.483864 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11869 11:47:47.489966 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11870 11:47:47.493539 Test requirement: is_i915_device(fd)
11871 11:47:47.506768 Test requirement not met in function igt_require_i915, file ../lib/drmtest<14>[ 23.855863] [IGT] kms_atomic: executing
11872 11:47:47.506918 .c:721:
11873 11:47:47.513542 Test re<14>[ 23.860602] [IGT] kms_atomic: exiting, ret=77
11874 11:47:47.513699 quirement: is_i915_device(fd)
11875 11:47:47.526850 No KMS driver or no outputs, pipes: 8, outputs: 0<8>[ 23.872301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11876 11:47:47.526985
11877 11:47:47.527249 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11879 11:47:47.533135 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11880 11:47:47.536246 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11881 11:47:47.539552 Opened device: /dev/dri/card0
11882 11:47:47.543262 No KMS driver or no outputs, pipes: 8, outputs: 0
11883 11:47:47.549852 [1mSubtest plane-overlay-le<14>[ 23.900201] [IGT] kms_atomic: executing
11884 11:47:47.555987 gacy: SKIP (0.00<14>[ 23.906356] [IGT] kms_atomic: exiting, ret=77
11885 11:47:47.559858 0s)[0m
11886 11:47:47.563053 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11887 11:47:47.572342 Opened <8>[ 23.917728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11888 11:47:47.572441 device: /dev/dri/card0
11889 11:47:47.572683 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11891 11:47:47.579360 No KMS driver or no outputs, pipes: 8, outputs: 0
11892 11:47:47.582251 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11893 11:47:47.588905 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11894 11:47:47.595840 Opened device: /<14>[ 23.943784] [IGT] kms_atomic: executing
11895 11:47:47.595982 dev/dri/card0
11896 11:47:47.598899 N<14>[ 23.949265] [IGT] kms_atomic: exiting, ret=77
11897 11:47:47.605652 o KMS driver or no outputs, pipes: 8, outputs: 0
11898 11:47:47.612085 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11900 11:47:47.615431 [1mSubtest plane-primary-over<8>[ 23.960806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11901 11:47:47.618520 lay-mutable-zpos: SKIP (0.000s)[0m
11902 11:47:47.621901 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11903 11:47:47.625531 Opened device: /dev/dri/card0
11904 11:47:47.628858 No KMS driver or no outputs, pipes: 8, outputs: 0
11905 11:47:47.635208 [1mSubtest plane-immutab<14>[ 23.986392] [IGT] kms_atomic: executing
11906 11:47:47.641524 le-zpos: SKIP (0<14>[ 23.991643] [IGT] kms_atomic: exiting, ret=77
11907 11:47:47.641636 .000s)[0m
11908 11:47:47.648375 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11909 11:47:47.658352 Open<8>[ 24.002790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11910 11:47:47.658469 ed device: /dev/dri/card0
11911 11:47:47.658740 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11913 11:47:47.664654 No KMS driver or no outputs, pipes: 8, outputs: 0
11914 11:47:47.667854 [1mSubtest test-only: SKIP (0.000s)[0m
11915 11:47:47.671802 IGT-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11916 11:47:47.674965 Opened device: /dev/dri/card0
11917 11:47:47.681142 No KMS dr<14>[ 24.029578] [IGT] kms_atomic: executing
11918 11:47:47.687882 iver or no outpu<14>[ 24.035761] [IGT] kms_atomic: exiting, ret=77
11919 11:47:47.688002 ts, pipes: 8, outputs: 0
11920 11:47:47.694315 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11921 11:47:47.700755 IG<8>[ 24.046741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11922 11:47:47.701048 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11924 11:47:47.707355 T-Version: 1.27.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11925 11:47:47.711018 Opened device: /dev/dri/card0
11926 11:47:47.714080 No KMS driver or no outputs, pipes: 8, outputs: 0
11927 11:47:47.717634 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11928 11:47:47.723921 <14>[ 24.073631] [IGT] kms_atomic: executing
11929 11:47:47.731032 IGT-Version: 1.2<14>[ 24.078445] [IGT] kms_atomic: exiting, ret=77
11930 11:47:47.734120 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11931 11:47:47.737298 Opened device: /dev/dri/card0
11932 11:47:47.744006 N<8>[ 24.090501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11933 11:47:47.744302 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11935 11:47:47.750352 o KMS driver or no outputs, pipes: 8, outputs: 0
11936 11:47:47.754004 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11937 11:47:47.768328 <14>[ 24.117705] [IGT] kms_atomic: executing
11938 11:47:47.774617 IGT-Version: 1.2<14>[ 24.122601] [IGT] kms_atomic: exiting, ret=77
11939 11:47:47.778288 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11940 11:47:47.781353 Opened device: /dev/dri/card0
11941 11:47:47.787592 N<8>[ 24.134377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11942 11:47:47.787928 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11944 11:47:47.790781 o KMS driver or no outputs, pipes: 8, outputs: 0
11945 11:47:47.797409 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11946 11:47:47.811893 <14>[ 24.161171] [IGT] kms_atomic: executing
11947 11:47:47.818110 IGT-Version: 1.2<14>[ 24.165864] [IGT] kms_atomic: exiting, ret=77
11948 11:47:47.821186 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11949 11:47:47.824818 Opened device: /dev/dri/card0
11950 11:47:47.831442 N<8>[ 24.178346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11951 11:47:47.831747 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11953 11:47:47.838141 o KMS driver or no outputs, pipes: 8, outputs: 0
11954 11:47:47.841081 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11955 11:47:47.855339 <14>[ 24.205060] [IGT] kms_atomic: executing
11956 11:47:47.862268 IGT-Version: 1.2<14>[ 24.209803] [IGT] kms_atomic: exiting, ret=77
11957 11:47:47.865206 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11958 11:47:47.868476 Opened device: /dev/dri/card0
11959 11:47:47.875509 N<8>[ 24.221486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11960 11:47:47.875808 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11962 11:47:47.878694 o KMS driver or no outputs, pipes: 8, outputs: 0
11963 11:47:47.884913 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11964 11:47:47.898703 <14>[ 24.248112] [IGT] kms_atomic: executing
11965 11:47:47.905005 IGT-Version: 1.2<14>[ 24.252982] [IGT] kms_atomic: exiting, ret=77
11966 11:47:47.908458 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11967 11:47:47.911900 Opened device: /dev/dri/card0
11968 11:47:47.918580 N<8>[ 24.264825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11969 11:47:47.918848 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11971 11:47:47.925106 o KMS driver or no outputs, pipe<8>[ 24.274706] <LAVA_SIGNAL_TESTSET STOP>
11972 11:47:47.925361 Received signal: <TESTSET> STOP
11973 11:47:47.925429 Closing test_set kms_atomic
11974 11:47:47.928174 s: 8, outputs: 0
11975 11:47:47.931244 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11976 11:47:47.952250 <8>[ 24.301575] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11977 11:47:47.952570 Received signal: <TESTSET> START kms_flip_event_leak
11978 11:47:47.952674 Starting test_set kms_flip_event_leak
11979 11:47:47.975894 <14>[ 24.325528] [IGT] kms_flip_event_leak: executing
11980 11:47:47.983067 IGT-Version: 1.2<14>[ 24.331327] [IGT] kms_flip_event_leak: exiting, ret=77
11981 11:47:47.986081 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
11982 11:47:47.989272 Opened device: /dev/dri/card0
11983 11:47:47.996143 N<8>[ 24.343425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11984 11:47:47.996408 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11986 11:47:48.002436 o KMS driver or no outputs, pipe<8>[ 24.352471] <LAVA_SIGNAL_TESTSET STOP>
11987 11:47:48.002685 Received signal: <TESTSET> STOP
11988 11:47:48.002752 Closing test_set kms_flip_event_leak
11989 11:47:48.005671 s: 8, outputs: 0
11990 11:47:48.008847 [1mSubtest basic: SKIP (0.000s)[0m
11991 11:47:48.028926 <8>[ 24.378774] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11992 11:47:48.029217 Received signal: <TESTSET> START kms_prop_blob
11993 11:47:48.029288 Starting test_set kms_prop_blob
11994 11:47:48.052974 <14>[ 24.402471] [IGT] kms_prop_blob: executing
11995 11:47:48.059536 IGT-Version: 1.2<14>[ 24.407584] [IGT] kms_prop_blob: starting subtest basic
11996 11:47:48.066180 7.1-g2dd77d6 (aa<14>[ 24.414409] [IGT] kms_prop_blob: exiting, ret=0
11997 11:47:48.069277 rch64) (Linux: 6.1.31 aarch64)
11998 11:47:48.072960 Opened device: /dev/dri/card0
11999 11:47:48.079386 Starting subtest:<8>[ 24.426303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12000 11:47:48.079473 basic
12001 11:47:48.079711 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12003 11:47:48.082558 [1mSubtest basic: SUCCESS (0.000s)[0m
12004 11:47:48.102142 <14>[ 24.451913] [IGT] kms_prop_blob: executing
12005 11:47:48.109330 IGT-Version: 1.2<14>[ 24.456903] [IGT] kms_prop_blob: starting subtest blob-prop-core
12006 11:47:48.115543 7.1-g2dd77d6 (aa<14>[ 24.464534] [IGT] kms_prop_blob: exiting, ret=0
12007 11:47:48.119220 rch64) (Linux: 6.1.31 aarch64)
12008 11:47:48.122344 Opened device: /dev/dri/card0
12009 11:47:48.128864 Starting subtest:<8>[ 24.476672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12010 11:47:48.129129 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12012 11:47:48.131898 blob-prop-core
12013 11:47:48.135696 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12014 11:47:48.153418 <14>[ 24.502735] [IGT] kms_prop_blob: executing
12015 11:47:48.159541 IGT-Version: 1.2<14>[ 24.507840] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12016 11:47:48.166479 7.1-g2dd77d6 (aa<14>[ 24.515905] [IGT] kms_prop_blob: exiting, ret=0
12017 11:47:48.169582 rch64) (Linux: 6.1.31 aarch64)
12018 11:47:48.172549 Opened device: /dev/dri/card0
12019 11:47:48.182531 Starting subtest:<8>[ 24.528223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12020 11:47:48.182631 blob-prop-validate
12021 11:47:48.182902 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12023 11:47:48.189406 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12024 11:47:48.206382 <14>[ 24.555997] [IGT] kms_prop_blob: executing
12025 11:47:48.212776 IGT-Version: 1.2<14>[ 24.560954] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12026 11:47:48.219669 7.1-g2dd77d6 (aa<14>[ 24.569346] [IGT] kms_prop_blob: exiting, ret=0
12027 11:47:48.222812 rch64) (Linux: 6.1.31 aarch64)
12028 11:47:48.226449 Opened device: /dev/dri/card0
12029 11:47:48.235916 Starting subtest:<8>[ 24.581393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12030 11:47:48.236040 blob-prop-lifetime
12031 11:47:48.236293 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12033 11:47:48.242680 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12034 11:47:48.257195 <14>[ 24.606947] [IGT] kms_prop_blob: executing
12035 11:47:48.264128 IGT-Version: 1.2<14>[ 24.611760] [IGT] kms_prop_blob: starting subtest blob-multiple
12036 11:47:48.270638 7.1-g2dd77d6 (aa<14>[ 24.619668] [IGT] kms_prop_blob: exiting, ret=0
12037 11:47:48.273687 rch64) (Linux: 6.1.31 aarch64)
12038 11:47:48.276821 Opened device: /dev/dri/card0
12039 11:47:48.283437 Starting subtest:<8>[ 24.631731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12040 11:47:48.283699 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12042 11:47:48.287234 blob-multiple
12043 11:47:48.290376 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12044 11:47:48.308297 <14>[ 24.657903] [IGT] kms_prop_blob: executing
12045 11:47:48.314724 IGT-Version: 1.2<14>[ 24.662951] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12046 11:47:48.321681 7.1-g2dd77d6 (aa<14>[ 24.671089] [IGT] kms_prop_blob: exiting, ret=0
12047 11:47:48.324770 rch64) (Linux: 6.1.31 aarch64)
12048 11:47:48.327928 Opened device: /dev/dri/card0
12049 11:47:48.338197 Starting subtest:<8>[ 24.683507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12050 11:47:48.338307 invalid-get-prop-any
12051 11:47:48.338576 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12053 11:47:48.344681 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12054 11:47:48.360235 <14>[ 24.710074] [IGT] kms_prop_blob: executing
12055 11:47:48.366993 IGT-Version: 1.2<14>[ 24.714994] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12056 11:47:48.373988 7.1-g2dd77d6 (aa<14>[ 24.722851] [IGT] kms_prop_blob: exiting, ret=0
12057 11:47:48.376901 rch64) (Linux: 6.1.31 aarch64)
12058 11:47:48.380491 Opened device: /dev/dri/card0
12059 11:47:48.387110 Starting subtest:<8>[ 24.734542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12060 11:47:48.387386 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12062 11:47:48.390316 invalid-get-prop
12063 11:47:48.393593 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12064 11:47:48.411679 <14>[ 24.761042] [IGT] kms_prop_blob: executing
12065 11:47:48.417991 IGT-Version: 1.2<14>[ 24.765877] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12066 11:47:48.424960 7.1-g2dd77d6 (aa<14>[ 24.774401] [IGT] kms_prop_blob: exiting, ret=0
12067 11:47:48.428180 rch64) (Linux: 6.1.31 aarch64)
12068 11:47:48.431385 Opened device: /dev/dri/card0
12069 11:47:48.441260 Starting subtest:<8>[ 24.786141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12070 11:47:48.441364 invalid-set-prop-any
12071 11:47:48.441603 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12073 11:47:48.447755 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12074 11:47:48.462233 <14>[ 24.812082] [IGT] kms_prop_blob: executing
12075 11:47:48.468920 IGT-Version: 1.2<14>[ 24.817063] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12076 11:47:48.475578 7.1-g2dd77d6 (aa<14>[ 24.824887] [IGT] kms_prop_blob: exiting, ret=0
12077 11:47:48.479311 rch64) (Linux: 6.1.31 aarch64)
12078 11:47:48.482069 Opened device: /dev/dri/card0
12079 11:47:48.491937 Starting subtest:<8>[ 24.837129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12080 11:47:48.492019 invalid-set-prop
12081 11:47:48.492278 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12083 11:47:48.499000 [1mSubtest i<8>[ 24.847287] <LAVA_SIGNAL_TESTSET STOP>
12084 11:47:48.499300 Received signal: <TESTSET> STOP
12085 11:47:48.499395 Closing test_set kms_prop_blob
12086 11:47:48.502031 nvalid-set-prop: SUCCESS (0.000s)[0m
12087 11:47:48.524594 <8>[ 24.874165] <LAVA_SIGNAL_TESTSET START kms_setmode>
12088 11:47:48.524886 Received signal: <TESTSET> START kms_setmode
12089 11:47:48.524958 Starting test_set kms_setmode
12090 11:47:48.548186 <14>[ 24.897679] [IGT] kms_setmode: executing
12091 11:47:48.554457 IGT-Version: 1.2<14>[ 24.902583] [IGT] kms_setmode: starting subtest basic
12092 11:47:48.561007 7.1-g2dd77d6 (aa<14>[ 24.909133] [IGT] kms_setmode: exiting, ret=77
12093 11:47:48.564673 rch64) (Linux: 6.1.31 aarch64)
12094 11:47:48.564780 Opened device: /dev/dri/card0
12095 11:47:48.574172 Starting subtest:<8>[ 24.921469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12096 11:47:48.574264 basic
12097 11:47:48.574500 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12099 11:47:48.577953 No dynamic tests executed.
12100 11:47:48.581024 [1mSubtest basic: SKIP (0.000s)[0m
12101 11:47:48.597283 <14>[ 24.946872] [IGT] kms_setmode: executing
12102 11:47:48.603809 IGT-Version: 1.2<14>[ 24.951632] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12103 11:47:48.610478 7.1-g2dd77d6 (aa<14>[ 24.960203] [IGT] kms_setmode: exiting, ret=77
12104 11:47:48.613554 rch64) (Linux: 6.1.31 aarch64)
12105 11:47:48.617178 Opened device: /dev/dri/card0
12106 11:47:48.627120 Starting subtest:<8>[ 24.972039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12107 11:47:48.627208 basic-clone-single-crtc
12108 11:47:48.627446 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12110 11:47:48.630274 No dynamic tests executed.
12111 11:47:48.636663 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12112 11:47:48.649310 <14>[ 24.999022] [IGT] kms_setmode: executing
12113 11:47:48.655963 IGT-Version: 1.2<14>[ 25.003772] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12114 11:47:48.662374 7.1-g2dd77d6 (aa<14>[ 25.012311] [IGT] kms_setmode: exiting, ret=77
12115 11:47:48.665933 rch64) (Linux: 6.1.31 aarch64)
12116 11:47:48.668875 Opened device: /dev/dri/card0
12117 11:47:48.678864 Starting subtest:<8>[ 25.024295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12118 11:47:48.679182 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12120 11:47:48.682365 invalid-clone-single-crtc
12121 11:47:48.682467 No dynamic tests executed.
12122 11:47:48.688562 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12123 11:47:48.701912 <14>[ 25.051595] [IGT] kms_setmode: executing
12124 11:47:48.712160 IGT-Version: 1.2<14>[ 25.056502] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12125 11:47:48.715415 7.1-g2dd77d6 (aa<14>[ 25.065079] [IGT] kms_setmode: exiting, ret=77
12126 11:47:48.718435 rch64) (Linux: 6.1.31 aarch64)
12127 11:47:48.721506 Opened device: /dev/dri/card0
12128 11:47:48.731500 Starting subtest:<8>[ 25.077043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12129 11:47:48.731764 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12131 11:47:48.734692 invalid-clone-exclusive-crtc
12132 11:47:48.737864 No dynamic tests executed.
12133 11:47:48.741079 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12134 11:47:48.754900 <14>[ 25.104561] [IGT] kms_setmode: executing
12135 11:47:48.761635 IGT-Version: 1.2<14>[ 25.109387] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12136 11:47:48.768223 7.1-g2dd77d6 (aa<14>[ 25.117500] [IGT] kms_setmode: exiting, ret=77
12137 11:47:48.771142 rch64) (Linux: 6.1.31 aarch64)
12138 11:47:48.774654 Opened device: /dev/dri/card0
12139 11:47:48.784549 Starting subtest:<8>[ 25.129352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12140 11:47:48.784637 clone-exclusive-crtc
12141 11:47:48.784877 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12143 11:47:48.788116 No dynamic tests executed.
12144 11:47:48.791082 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12145 11:47:48.805227 <14>[ 25.155088] [IGT] kms_setmode: executing
12146 11:47:48.815615 IGT-Version: 1.2<14>[ 25.159808] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12147 11:47:48.821857 7.1-g2dd77d6 (aa<14>[ 25.168929] [IGT] kms_setmode: exiting, ret=77
12148 11:47:48.821945 rch64) (Linux: 6.1.31 aarch64)
12149 11:47:48.825262 Opened device: /dev/dri/card0
12150 11:47:48.835317 Starting subtest:<8>[ 25.180775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12151 11:47:48.835606 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12153 11:47:48.841607 invalid-clone-single-crtc-steal<8>[ 25.192398] <LAVA_SIGNAL_TESTSET STOP>
12154 11:47:48.841889 Received signal: <TESTSET> STOP
12155 11:47:48.841986 Closing test_set kms_setmode
12156 11:47:48.844682 ing
12157 11:47:48.844781 No dynamic tests executed.
12158 11:47:48.851225 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12159 11:47:48.869784 <8>[ 25.219327] <LAVA_SIGNAL_TESTSET START kms_vblank>
12160 11:47:48.870067 Received signal: <TESTSET> START kms_vblank
12161 11:47:48.870138 Starting test_set kms_vblank
12162 11:47:48.892863 <14>[ 25.242391] [IGT] kms_vblank: executing
12163 11:47:48.899424 IGT-Version: 1.2<14>[ 25.247632] [IGT] kms_vblank: exiting, ret=77
12164 11:47:48.902886 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12165 11:47:48.905949 Opened device: /dev/dri/card0
12166 11:47:48.912452 N<8>[ 25.258725] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12167 11:47:48.912717 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12169 11:47:48.915621 o KMS driver or no outputs, pipes: 8, outputs: 0
12170 11:47:48.919032 [1mSubtest invalid: SKIP (0.000s)[0m
12171 11:47:48.934335 <14>[ 25.284313] [IGT] kms_vblank: executing
12172 11:47:48.941306 IGT-Version: 1.2<14>[ 25.289326] [IGT] kms_vblank: exiting, ret=77
12173 11:47:48.944535 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12174 11:47:48.947783 Opened device: /dev/dri/card0
12175 11:47:48.954234 N<8>[ 25.300953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12176 11:47:48.954491 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12178 11:47:48.957451 o KMS driver or no outputs, pipes: 8, outputs: 0
12179 11:47:48.961302 [1mSubtest crtc-id: SKIP (0.000s)[0m
12180 11:47:48.977268 <14>[ 25.326736] [IGT] kms_vblank: executing
12181 11:47:48.983408 IGT-Version: 1.2<14>[ 25.331809] [IGT] kms_vblank: exiting, ret=77
12182 11:47:48.987067 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12183 11:47:48.990336 Opened device: /dev/dri/card0
12184 11:47:48.996465 N<8>[ 25.343411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12185 11:47:48.996779 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12187 11:47:49.000023 o KMS driver or no outputs, pipes: 8, outputs: 0
12188 11:47:49.006717 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12189 11:47:49.020691 <14>[ 25.370057] [IGT] kms_vblank: executing
12190 11:47:49.026973 IGT-Version: 1.2<14>[ 25.375227] [IGT] kms_vblank: exiting, ret=77
12191 11:47:49.030066 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12192 11:47:49.033628 Opened device: /dev/dri/card0
12193 11:47:49.039981 N<8>[ 25.386080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12194 11:47:49.040261 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12196 11:47:49.043251 o KMS driver or no outputs, pipes: 8, outputs: 0
12197 11:47:49.049809 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12198 11:47:49.063622 <14>[ 25.413200] [IGT] kms_vblank: executing
12199 11:47:49.069938 IGT-Version: 1.2<14>[ 25.418488] [IGT] kms_vblank: exiting, ret=77
12200 11:47:49.073625 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12201 11:47:49.076875 Opened device: /dev/dri/card0
12202 11:47:49.083189 N<8>[ 25.429721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12203 11:47:49.083448 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12205 11:47:49.090065 o KMS driver or no outputs, pipes: 8, outputs: 0
12206 11:47:49.093150 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12207 11:47:49.106899 <14>[ 25.456811] [IGT] kms_vblank: executing
12208 11:47:49.113830 IGT-Version: 1.2<14>[ 25.462047] [IGT] kms_vblank: exiting, ret=77
12209 11:47:49.116728 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12210 11:47:49.120330 Opened device: /dev/dri/card0
12211 11:47:49.126732 N<8>[ 25.473396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12212 11:47:49.127048 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12214 11:47:49.130262 o KMS driver or no outputs, pipes: 8, outputs: 0
12215 11:47:49.136564 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12216 11:47:49.150455 <14>[ 25.500011] [IGT] kms_vblank: executing
12217 11:47:49.156840 IGT-Version: 1.27.1-g2dd77d6 (aa<14>[ 25.506627] [IGT] kms_vblank: exiting, ret=77
12218 11:47:49.160089 rch64) (Linux: 6.1.31 aarch64)
12219 11:47:49.163203 Opened device: /dev/dri/card0
12220 11:47:49.173347 No KMS driver or no outputs, pipe<8>[ 25.520315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12221 11:47:49.173670 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12223 11:47:49.176457 s: 8, outputs: 0
12224 11:47:49.179653 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12225 11:47:49.196563 <14>[ 25.545974] [IGT] kms_vblank: executing
12226 11:47:49.202629 IGT-Version: 1.2<14>[ 25.550962] [IGT] kms_vblank: exiting, ret=77
12227 11:47:49.206185 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12228 11:47:49.209189 Opened device: /dev/dri/card0
12229 11:47:49.216043 N<8>[ 25.562260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12230 11:47:49.216350 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12232 11:47:49.219152 o KMS driver or no outputs, pipes: 8, outputs: 0
12233 11:47:49.225917 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12234 11:47:49.238130 <14>[ 25.588053] [IGT] kms_vblank: executing
12235 11:47:49.244804 IGT-Version: 1.2<14>[ 25.593080] [IGT] kms_vblank: exiting, ret=77
12236 11:47:49.248502 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12237 11:47:49.251648 Opened device: /dev/dri/card0
12238 11:47:49.258119 N<8>[ 25.604496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12239 11:47:49.258431 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12241 11:47:49.261350 o KMS driver or no outputs, pipes: 8, outputs: 0
12242 11:47:49.267653 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12243 11:47:49.281053 <14>[ 25.630635] [IGT] kms_vblank: executing
12244 11:47:49.287369 IGT-Version: 1.2<14>[ 25.635873] [IGT] kms_vblank: exiting, ret=77
12245 11:47:49.290443 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12246 11:47:49.294165 Opened device: /dev/dri/card0
12247 11:47:49.300441 N<8>[ 25.647350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12248 11:47:49.300732 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12250 11:47:49.307297 o KMS driver or no outputs, pipes: 8, outputs: 0
12251 11:47:49.310433 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12252 11:47:49.323739 <14>[ 25.673306] [IGT] kms_vblank: executing
12253 11:47:49.330473 IGT-Version: 1.2<14>[ 25.678555] [IGT] kms_vblank: exiting, ret=77
12254 11:47:49.333429 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12255 11:47:49.336966 Opened device: /dev/dri/card0
12256 11:47:49.343404 N<8>[ 25.690007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12257 11:47:49.343707 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12259 11:47:49.349956 o KMS driver or no outputs, pipes: 8, outputs: 0
12260 11:47:49.353631 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12261 11:47:49.366860 <14>[ 25.716616] [IGT] kms_vblank: executing
12262 11:47:49.373890 IGT-Version: 1.2<14>[ 25.721602] [IGT] kms_vblank: exiting, ret=77
12263 11:47:49.377079 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12264 11:47:49.380281 Opened device: /dev/dri/card0
12265 11:47:49.386555 N<8>[ 25.732879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12266 11:47:49.386852 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12268 11:47:49.390257 o KMS driver or no outputs, pipes: 8, outputs: 0
12269 11:47:49.396430 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12270 11:47:49.408656 <14>[ 25.758600] [IGT] kms_vblank: executing
12271 11:47:49.415503 IGT-Version: 1.2<14>[ 25.763818] [IGT] kms_vblank: exiting, ret=77
12272 11:47:49.418515 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12273 11:47:49.422190 Opened device: /dev/dri/card0
12274 11:47:49.428978 N<8>[ 25.774895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12275 11:47:49.429274 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12277 11:47:49.432138 o KMS driver or no outputs, pipes: 8, outputs: 0
12278 11:47:49.438150 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12279 11:47:49.450976 <14>[ 25.800867] [IGT] kms_vblank: executing
12280 11:47:49.457462 IGT-Version: 1.2<14>[ 25.805879] [IGT] kms_vblank: exiting, ret=77
12281 11:47:49.461259 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12282 11:47:49.464456 Opened device: /dev/dri/card0
12283 11:47:49.470937 N<8>[ 25.817131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12284 11:47:49.471196 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12286 11:47:49.474036 o KMS driver or no outputs, pipes: 8, outputs: 0
12287 11:47:49.481043 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12288 11:47:49.493175 <14>[ 25.842832] [IGT] kms_vblank: executing
12289 11:47:49.499500 IGT-Version: 1.2<14>[ 25.847920] [IGT] kms_vblank: exiting, ret=77
12290 11:47:49.502592 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12291 11:47:49.506380 Opened device: /dev/dri/card0
12292 11:47:49.512862 N<8>[ 25.858946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12293 11:47:49.513157 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12295 11:47:49.519195 o KMS driver or no outputs, pipes: 8, outputs: 0
12296 11:47:49.522444 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12297 11:47:49.536388 <14>[ 25.885999] [IGT] kms_vblank: executing
12298 11:47:49.542996 IGT-Version: 1.2<14>[ 25.890984] [IGT] kms_vblank: exiting, ret=77
12299 11:47:49.546138 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12300 11:47:49.549673 Opened device: /dev/dri/card0
12301 11:47:49.556141 N<8>[ 25.902377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12302 11:47:49.556432 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12304 11:47:49.559486 o KMS driver or no outputs, pipes: 8, outputs: 0
12305 11:47:49.565995 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12306 11:47:49.578352 <14>[ 25.927956] [IGT] kms_vblank: executing
12307 11:47:49.584713 IGT-Version: 1.2<14>[ 25.932944] [IGT] kms_vblank: exiting, ret=77
12308 11:47:49.587874 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12309 11:47:49.591557 Opened device: /dev/dri/card0
12310 11:47:49.597987 N<8>[ 25.944125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12311 11:47:49.598256 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12313 11:47:49.601109 o KMS driver or no outputs, pipes: 8, outputs: 0
12314 11:47:49.607922 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12315 11:47:49.620403 <14>[ 25.970145] [IGT] kms_vblank: executing
12316 11:47:49.626807 IGT-Version: 1.2<14>[ 25.975159] [IGT] kms_vblank: exiting, ret=77
12317 11:47:49.630438 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12318 11:47:49.640197 Opened device: /<8>[ 25.986019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12319 11:47:49.640318 dev/dri/card0
12320 11:47:49.640593 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12322 11:47:49.643318 No KMS driver or no outputs, pipes: 8, outputs: 0
12323 11:47:49.649854 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12324 11:47:49.661293 <14>[ 26.011345] [IGT] kms_vblank: executing
12325 11:47:49.667860 IGT-Version: 1.2<14>[ 26.016387] [IGT] kms_vblank: exiting, ret=77
12326 11:47:49.671288 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12327 11:47:49.675058 Opened device: /dev/dri/card0
12328 11:47:49.681349 N<8>[ 26.027428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12329 11:47:49.681614 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12331 11:47:49.687878 o KMS driver or no outputs, pipes: 8, outputs: 0
12332 11:47:49.691069 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12333 11:47:49.705009 <14>[ 26.054830] [IGT] kms_vblank: executing
12334 11:47:49.711899 IGT-Version: 1.2<14>[ 26.059923] [IGT] kms_vblank: exiting, ret=77
12335 11:47:49.715276 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12336 11:47:49.718364 Opened device: /dev/dri/card0
12337 11:47:49.725156 N<8>[ 26.071230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12338 11:47:49.725413 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12340 11:47:49.731304 o KMS driver or no outputs, pipes: 8, outputs: 0
12341 11:47:49.734447 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12342 11:47:49.747875 <14>[ 26.097754] [IGT] kms_vblank: executing
12343 11:47:49.754485 IGT-Version: 1.2<14>[ 26.102806] [IGT] kms_vblank: exiting, ret=77
12344 11:47:49.758103 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12345 11:47:49.767649 Opened device: /<8>[ 26.113698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12346 11:47:49.767748 dev/dri/card0
12347 11:47:49.767984 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12349 11:47:49.774276 No KMS driver or no outputs, pipes: 8, outputs: 0
12350 11:47:49.777247 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12351 11:47:49.790497 <14>[ 26.140266] [IGT] kms_vblank: executing
12352 11:47:49.797350 IGT-Version: 1.2<14>[ 26.145495] [IGT] kms_vblank: exiting, ret=77
12353 11:47:49.800462 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12354 11:47:49.803538 Opened device: /dev/dri/card0
12355 11:47:49.810622 N<8>[ 26.156464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12356 11:47:49.810854 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12358 11:47:49.816872 o KMS driver or no outputs, pipes: 8, outputs: 0
12359 11:47:49.819981 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12360 11:47:49.833569 <14>[ 26.183614] [IGT] kms_vblank: executing
12361 11:47:49.840940 IGT-Version: 1.2<14>[ 26.188620] [IGT] kms_vblank: exiting, ret=77
12362 11:47:49.843871 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12363 11:47:49.847000 Opened device: /dev/dri/card0
12364 11:47:49.853618 N<8>[ 26.199638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12365 11:47:49.853885 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12367 11:47:49.860182 o KMS driver or no outputs, pipes: 8, outputs: 0
12368 11:47:49.866805 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12369 11:47:49.877693 <14>[ 26.227341] [IGT] kms_vblank: executing
12370 11:47:49.884326 IGT-Version: 1.2<14>[ 26.232327] [IGT] kms_vblank: exiting, ret=77
12371 11:47:49.887424 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12372 11:47:49.890551 Opened device: /dev/dri/card0
12373 11:47:49.897549 N<8>[ 26.243301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12374 11:47:49.897865 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12376 11:47:49.903878 o KMS driver or no outputs, pipes: 8, outputs: 0
12377 11:47:49.906795 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12378 11:47:49.920560 <14>[ 26.270236] [IGT] kms_vblank: executing
12379 11:47:49.926847 IGT-Version: 1.2<14>[ 26.275298] [IGT] kms_vblank: exiting, ret=77
12380 11:47:49.930322 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12381 11:47:49.940073 Opened device: /<8>[ 26.286199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12382 11:47:49.940170 dev/dri/card0
12383 11:47:49.940425 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12385 11:47:49.947033 No KMS driver or no outputs, pipes: 8, outputs: 0
12386 11:47:49.950060 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12387 11:47:49.962909 <14>[ 26.312813] [IGT] kms_vblank: executing
12388 11:47:49.969448 IGT-Version: 1.2<14>[ 26.317809] [IGT] kms_vblank: exiting, ret=77
12389 11:47:49.973047 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12390 11:47:49.976013 Opened device: /dev/dri/card0
12391 11:47:49.982618 N<8>[ 26.328911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12392 11:47:49.982857 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12394 11:47:49.989184 o KMS driver or no outputs, pipes: 8, outputs: 0
12395 11:47:49.996079 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12396 11:47:50.006369 <14>[ 26.356317] [IGT] kms_vblank: executing
12397 11:47:50.013279 IGT-Version: 1.2<14>[ 26.361421] [IGT] kms_vblank: exiting, ret=77
12398 11:47:50.016432 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12399 11:47:50.019669 Opened device: /dev/dri/card0
12400 11:47:50.026517 N<8>[ 26.372375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12401 11:47:50.026775 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12403 11:47:50.032716 o KMS driver or no outputs, pipes: 8, outputs: 0
12404 11:47:50.039520 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12405 11:47:50.051021 <14>[ 26.400488] [IGT] kms_vblank: executing
12406 11:47:50.057597 IGT-Version: 1.2<14>[ 26.405573] [IGT] kms_vblank: exiting, ret=77
12407 11:47:50.060794 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12408 11:47:50.063948 Opened device: /dev/dri/card0
12409 11:47:50.070485 N<8>[ 26.416910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12410 11:47:50.070750 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12412 11:47:50.073595 o KMS driver or no outputs, pipes: 8, outputs: 0
12413 11:47:50.080148 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12414 11:47:50.094040 <14>[ 26.443795] [IGT] kms_vblank: executing
12415 11:47:50.100879 IGT-Version: 1.2<14>[ 26.448995] [IGT] kms_vblank: exiting, ret=77
12416 11:47:50.104055 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12417 11:47:50.107259 Opened device: /dev/dri/card0
12418 11:47:50.113735 N<8>[ 26.460219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12419 11:47:50.113996 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12421 11:47:50.116763 o KMS driver or no outputs, pipes: 8, outputs: 0
12422 11:47:50.123663 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12423 11:47:50.136119 <14>[ 26.485731] [IGT] kms_vblank: executing
12424 11:47:50.142235 IGT-Version: 1.2<14>[ 26.490821] [IGT] kms_vblank: exiting, ret=77
12425 11:47:50.146062 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12426 11:47:50.149208 Opened device: /dev/dri/card0
12427 11:47:50.155557 N<8>[ 26.501896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12428 11:47:50.155847 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12430 11:47:50.162275 o KMS driver or no outputs, pipes: 8, outputs: 0
12431 11:47:50.165158 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12432 11:47:50.179431 <14>[ 26.528984] [IGT] kms_vblank: executing
12433 11:47:50.186042 IGT-Version: 1.2<14>[ 26.534254] [IGT] kms_vblank: exiting, ret=77
12434 11:47:50.188915 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12435 11:47:50.192596 Opened device: /dev/dri/card0
12436 11:47:50.199049 N<8>[ 26.545287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12437 11:47:50.199312 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12439 11:47:50.202095 o KMS driver or no outputs, pipes: 8, outputs: 0
12440 11:47:50.208449 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12441 11:47:50.221770 <14>[ 26.571361] [IGT] kms_vblank: executing
12442 11:47:50.228066 IGT-Version: 1.2<14>[ 26.576387] [IGT] kms_vblank: exiting, ret=77
12443 11:47:50.231090 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12444 11:47:50.234812 Opened device: /dev/dri/card0
12445 11:47:50.241071 N<8>[ 26.587373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12446 11:47:50.241348 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12448 11:47:50.248015 o KMS driver or no outputs, pipes: 8, outputs: 0
12449 11:47:50.251318 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12450 11:47:50.264083 <14>[ 26.613912] [IGT] kms_vblank: executing
12451 11:47:50.270678 IGT-Version: 1.2<14>[ 26.618873] [IGT] kms_vblank: exiting, ret=77
12452 11:47:50.273815 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12453 11:47:50.277401 Opened device: /dev/dri/card0
12454 11:47:50.284089 N<8>[ 26.629883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12455 11:47:50.284373 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12457 11:47:50.287167 o KMS driver or no outputs, pipes: 8, outputs: 0
12458 11:47:50.293596 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12459 11:47:50.305832 <14>[ 26.655810] [IGT] kms_vblank: executing
12460 11:47:50.312724 IGT-Version: 1.2<14>[ 26.660871] [IGT] kms_vblank: exiting, ret=77
12461 11:47:50.316059 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12462 11:47:50.319142 Opened device: /dev/dri/card0
12463 11:47:50.325963 N<8>[ 26.672074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12464 11:47:50.326217 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12466 11:47:50.329117 o KMS driver or no outputs, pipes: 8, outputs: 0
12467 11:47:50.335854 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12468 11:47:50.348315 <14>[ 26.698041] [IGT] kms_vblank: executing
12469 11:47:50.354764 IGT-Version: 1.2<14>[ 26.703050] [IGT] kms_vblank: exiting, ret=77
12470 11:47:50.357902 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12471 11:47:50.361635 Opened device: /dev/dri/card0
12472 11:47:50.367941 N<8>[ 26.714305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12473 11:47:50.368224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12475 11:47:50.374707 o KMS driver or no outputs, pipes: 8, outputs: 0
12476 11:47:50.377857 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12477 11:47:50.390547 <14>[ 26.740458] [IGT] kms_vblank: executing
12478 11:47:50.397254 IGT-Version: 1.2<14>[ 26.745550] [IGT] kms_vblank: exiting, ret=77
12479 11:47:50.400688 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12480 11:47:50.410146 Opened device: /<8>[ 26.756495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12481 11:47:50.410243 dev/dri/card0
12482 11:47:50.410503 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12484 11:47:50.416678 No KMS driver or no outputs, pipes: 8, outputs: 0
12485 11:47:50.419914 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12486 11:47:50.433086 <14>[ 26.782721] [IGT] kms_vblank: executing
12487 11:47:50.439233 IGT-Version: 1.2<14>[ 26.787858] [IGT] kms_vblank: exiting, ret=77
12488 11:47:50.442893 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12489 11:47:50.445996 Opened device: /dev/dri/card0
12490 11:47:50.452849 N<8>[ 26.799478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12491 11:47:50.453158 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12493 11:47:50.455949 o KMS driver or no outputs, pipes: 8, outputs: 0
12494 11:47:50.462360 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12495 11:47:50.474655 <14>[ 26.824508] [IGT] kms_vblank: executing
12496 11:47:50.481513 IGT-Version: 1.2<14>[ 26.829542] [IGT] kms_vblank: exiting, ret=77
12497 11:47:50.484504 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12498 11:47:50.487657 Opened device: /dev/dri/card0
12499 11:47:50.494460 N<8>[ 26.840566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12500 11:47:50.494746 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12502 11:47:50.498083 o KMS driver or no outputs, pipes: 8, outputs: 0
12503 11:47:50.504149 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12504 11:47:50.517632 <14>[ 26.867782] [IGT] kms_vblank: executing
12505 11:47:50.524586 IGT-Version: 1.2<14>[ 26.872730] [IGT] kms_vblank: exiting, ret=77
12506 11:47:50.527819 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12507 11:47:50.530928 Opened device: /dev/dri/card0
12508 11:47:50.538004 N<8>[ 26.884192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12509 11:47:50.538283 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12511 11:47:50.541289 o KMS driver or no outputs, pipes: 8, outputs: 0
12512 11:47:50.547522 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12513 11:47:50.559983 <14>[ 26.909611] [IGT] kms_vblank: executing
12514 11:47:50.566360 IGT-Version: 1.2<14>[ 26.914639] [IGT] kms_vblank: exiting, ret=77
12515 11:47:50.569545 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12516 11:47:50.572732 Opened device: /dev/dri/card0
12517 11:47:50.579831 N<8>[ 26.925921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12518 11:47:50.580098 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12520 11:47:50.582986 o KMS driver or no outputs, pipes: 8, outputs: 0
12521 11:47:50.589761 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12522 11:47:50.602599 <14>[ 26.952268] [IGT] kms_vblank: executing
12523 11:47:50.609034 IGT-Version: 1.2<14>[ 26.957267] [IGT] kms_vblank: exiting, ret=77
12524 11:47:50.612038 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12525 11:47:50.615524 Opened device: /dev/dri/card0
12526 11:47:50.622154 N<8>[ 26.968377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12527 11:47:50.622420 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12529 11:47:50.625146 o KMS driver or no outputs, pipes: 8, outputs: 0
12530 11:47:50.631929 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12531 11:47:50.644069 <14>[ 26.994151] [IGT] kms_vblank: executing
12532 11:47:50.650877 IGT-Version: 1.2<14>[ 26.999198] [IGT] kms_vblank: exiting, ret=77
12533 11:47:50.654089 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12534 11:47:50.663960 Opened device: /<8>[ 27.009869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12535 11:47:50.664080 dev/dri/card0
12536 11:47:50.664353 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12538 11:47:50.667139 No KMS driver or no outputs, pipes: 8, outputs: 0
12539 11:47:50.674005 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12540 11:47:50.686098 <14>[ 27.035872] [IGT] kms_vblank: executing
12541 11:47:50.692388 IGT-Version: 1.2<14>[ 27.040859] [IGT] kms_vblank: exiting, ret=77
12542 11:47:50.696076 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12543 11:47:50.699059 Opened device: /dev/dri/card0
12544 11:47:50.705907 N<8>[ 27.052290] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12545 11:47:50.706178 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12547 11:47:50.712555 o KMS driver or no outputs, pipes: 8, outputs: 0
12548 11:47:50.715627 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12549 11:47:50.728724 <14>[ 27.078341] [IGT] kms_vblank: executing
12550 11:47:50.735014 IGT-Version: 1.2<14>[ 27.083522] [IGT] kms_vblank: exiting, ret=77
12551 11:47:50.738409 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12552 11:47:50.748295 Opened device: /<8>[ 27.094126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12553 11:47:50.748393 dev/dri/card0
12554 11:47:50.748653 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12556 11:47:50.755093 No KMS driver or no outputs, pipes: 8, outputs: 0
12557 11:47:50.758333 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12558 11:47:50.770913 <14>[ 27.120467] [IGT] kms_vblank: executing
12559 11:47:50.777202 IGT-Version: 1.2<14>[ 27.125538] [IGT] kms_vblank: exiting, ret=77
12560 11:47:50.780514 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12561 11:47:50.783816 Opened device: /dev/dri/card0
12562 11:47:50.790085 N<8>[ 27.136958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12563 11:47:50.790352 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12565 11:47:50.797036 o KMS driver or no outputs, pipes: 8, outputs: 0
12566 11:47:50.800015 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12567 11:47:50.814865 <14>[ 27.164516] [IGT] kms_vblank: executing
12568 11:47:50.821277 IGT-Version: 1.2<14>[ 27.169727] [IGT] kms_vblank: exiting, ret=77
12569 11:47:50.824344 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12570 11:47:50.827954 Opened device: /dev/dri/card0
12571 11:47:50.834644 N<8>[ 27.180925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12572 11:47:50.834953 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12574 11:47:50.840932 o KMS driver or no outputs, pipes: 8, outputs: 0
12575 11:47:50.844448 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12576 11:47:50.858192 <14>[ 27.207926] [IGT] kms_vblank: executing
12577 11:47:50.864496 IGT-Version: 1.2<14>[ 27.213027] [IGT] kms_vblank: exiting, ret=77
12578 11:47:50.868014 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12579 11:47:50.871315 Opened device: /dev/dri/card0
12580 11:47:50.877731 N<8>[ 27.224000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12581 11:47:50.877993 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12583 11:47:50.884327 o KMS driver or no outputs, pipes: 8, outputs: 0
12584 11:47:50.887375 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12585 11:47:50.901513 <14>[ 27.251118] [IGT] kms_vblank: executing
12586 11:47:50.908163 IGT-Version: 1.2<14>[ 27.256249] [IGT] kms_vblank: exiting, ret=77
12587 11:47:50.911102 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12588 11:47:50.921102 Opened device: /<8>[ 27.267115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12589 11:47:50.921393 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12591 11:47:50.924154 dev/dri/card0
12592 11:47:50.927753 No KMS driver or no outputs, pipes: 8, outputs: 0
12593 11:47:50.933883 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12594 11:47:50.943781 <14>[ 27.293905] [IGT] kms_vblank: executing
12595 11:47:50.950654 IGT-Version: 1.2<14>[ 27.298904] [IGT] kms_vblank: exiting, ret=77
12596 11:47:50.953557 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12597 11:47:50.957464 Opened device: /dev/dri/card0
12598 11:47:50.963824 N<8>[ 27.310636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12599 11:47:50.964090 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12601 11:47:50.970605 o KMS driver or no outputs, pipes: 8, outputs: 0
12602 11:47:50.973723 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12603 11:47:50.986807 <14>[ 27.336746] [IGT] kms_vblank: executing
12604 11:47:50.993237 IGT-Version: 1.2<14>[ 27.341832] [IGT] kms_vblank: exiting, ret=77
12605 11:47:50.997050 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12606 11:47:51.006605 Opened device: /<8>[ 27.352795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12607 11:47:51.006707 dev/dri/card0
12608 11:47:51.006948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12610 11:47:51.013292 No KMS driver or no outputs, pipes: 8, outputs: 0
12611 11:47:51.016277 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12612 11:47:51.029291 <14>[ 27.379312] [IGT] kms_vblank: executing
12613 11:47:51.035998 IGT-Version: 1.2<14>[ 27.384565] [IGT] kms_vblank: exiting, ret=77
12614 11:47:51.039427 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12615 11:47:51.042518 Opened device: /dev/dri/card0
12616 11:47:51.049505 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12618 11:47:51.052388 N<8>[ 27.395549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12619 11:47:51.056004 o KMS driver or no outputs, pipes: 8, outputs: 0
12620 11:47:51.062495 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12621 11:47:51.073157 <14>[ 27.423078] [IGT] kms_vblank: executing
12622 11:47:51.079691 IGT-Version: 1.2<14>[ 27.428094] [IGT] kms_vblank: exiting, ret=77
12623 11:47:51.082893 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12624 11:47:51.092971 Opened device: /<8>[ 27.439002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12625 11:47:51.093093 dev/dri/card0
12626 11:47:51.093385 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12628 11:47:51.099296 No KMS driver or no outputs, pipes: 8, outputs: 0
12629 11:47:51.106233 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12630 11:47:51.115950 <14>[ 27.465637] [IGT] kms_vblank: executing
12631 11:47:51.122151 IGT-Version: 1.2<14>[ 27.471221] [IGT] kms_vblank: exiting, ret=77
12632 11:47:51.125752 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12633 11:47:51.128687 Opened device: /dev/dri/card0
12634 11:47:51.135603 N<8>[ 27.482265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12635 11:47:51.135855 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12637 11:47:51.142223 o KMS driver or no outputs, pipes: 8, outputs: 0
12638 11:47:51.145237 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12639 11:47:51.158189 <14>[ 27.508104] [IGT] kms_vblank: executing
12640 11:47:51.164489 IGT-Version: 1.2<14>[ 27.513179] [IGT] kms_vblank: exiting, ret=77
12641 11:47:51.168040 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12642 11:47:51.171056 Opened device: /dev/dri/card0
12643 11:47:51.177683 N<8>[ 27.524216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12644 11:47:51.177958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12646 11:47:51.181395 o KMS driver or no outputs, pipes: 8, outputs: 0
12647 11:47:51.187841 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12648 11:47:51.200065 <14>[ 27.550081] [IGT] kms_vblank: executing
12649 11:47:51.206942 IGT-Version: 1.2<14>[ 27.555113] [IGT] kms_vblank: exiting, ret=77
12650 11:47:51.209996 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12651 11:47:51.220097 Opened device: /<8>[ 27.565876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12652 11:47:51.220178 dev/dri/card0
12653 11:47:51.220415 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12655 11:47:51.223363 No KMS driver or no outputs, pipes: 8, outputs: 0
12656 11:47:51.229453 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12657 11:47:51.241962 <14>[ 27.591794] [IGT] kms_vblank: executing
12658 11:47:51.248615 IGT-Version: 1.2<14>[ 27.596784] [IGT] kms_vblank: exiting, ret=77
12659 11:47:51.251732 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12660 11:47:51.255189 Opened device: /dev/dri/card0
12661 11:47:51.261536 N<8>[ 27.608222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12662 11:47:51.261808 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12664 11:47:51.265136 o KMS driver or no outputs, pipes: 8, outputs: 0
12665 11:47:51.271756 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12666 11:47:51.284258 <14>[ 27.633801] [IGT] kms_vblank: executing
12667 11:47:51.290367 IGT-Version: 1.2<14>[ 27.638811] [IGT] kms_vblank: exiting, ret=77
12668 11:47:51.293567 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12669 11:47:51.303731 Opened device: /<8>[ 27.649698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12670 11:47:51.303827 dev/dri/card0
12671 11:47:51.304067 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12673 11:47:51.310067 No KMS driver or no outputs, pipes: 8, outputs: 0
12674 11:47:51.313328 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12675 11:47:51.324881 <14>[ 27.674905] [IGT] kms_vblank: executing
12676 11:47:51.331876 IGT-Version: 1.2<14>[ 27.679901] [IGT] kms_vblank: exiting, ret=77
12677 11:47:51.335065 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12678 11:47:51.344810 Opened device: /<8>[ 27.690695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12679 11:47:51.344937 dev/dri/card0
12680 11:47:51.345227 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12682 11:47:51.347834 No KMS driver or no outputs, pipes: 8, outputs: 0
12683 11:47:51.354412 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12684 11:47:51.365262 <14>[ 27.715485] [IGT] kms_vblank: executing
12685 11:47:51.372462 IGT-Version: 1.2<14>[ 27.720473] [IGT] kms_vblank: exiting, ret=77
12686 11:47:51.375418 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12687 11:47:51.378487 Opened device: /dev/dri/card0
12688 11:47:51.385503 N<8>[ 27.731791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12689 11:47:51.385808 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12691 11:47:51.388513 o KMS driver or no outputs, pipes: 8, outputs: 0
12692 11:47:51.395046 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12693 11:47:51.408281 <14>[ 27.757983] [IGT] kms_vblank: executing
12694 11:47:51.414628 IGT-Version: 1.2<14>[ 27.763122] [IGT] kms_vblank: exiting, ret=77
12695 11:47:51.417865 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12696 11:47:51.427918 Opened device: /<8>[ 27.773728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12697 11:47:51.428005 dev/dri/card0
12698 11:47:51.428251 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12700 11:47:51.434312 No KMS driver or no outputs, pipes: 8, outputs: 0
12701 11:47:51.437394 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12702 11:47:51.449152 <14>[ 27.799148] [IGT] kms_vblank: executing
12703 11:47:51.455877 IGT-Version: 1.2<14>[ 27.804126] [IGT] kms_vblank: exiting, ret=77
12704 11:47:51.458924 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12705 11:47:51.462290 Opened device: /dev/dri/card0
12706 11:47:51.468712 N<8>[ 27.815132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12707 11:47:51.469023 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12709 11:47:51.475096 o KMS driver or no outputs, pipes: 8, outputs: 0
12710 11:47:51.478668 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12711 11:47:51.492750 <14>[ 27.842792] [IGT] kms_vblank: executing
12712 11:47:51.499449 IGT-Version: 1.2<14>[ 27.847918] [IGT] kms_vblank: exiting, ret=77
12713 11:47:51.502548 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12714 11:47:51.506186 Opened device: /dev/dri/card0
12715 11:47:51.512606 N<8>[ 27.859167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12716 11:47:51.512864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12718 11:47:51.515789 o KMS driver or no outputs, pipes: 8, outputs: 0
12719 11:47:51.522132 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12720 11:47:51.534835 <14>[ 27.884728] [IGT] kms_vblank: executing
12721 11:47:51.541208 IGT-Version: 1.2<14>[ 27.889832] [IGT] kms_vblank: exiting, ret=77
12722 11:47:51.544897 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12723 11:47:51.547965 Opened device: /dev/dri/card0
12724 11:47:51.554374 N<8>[ 27.900970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12725 11:47:51.554634 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12727 11:47:51.558148 o KMS driver or no outputs, pipes: 8, outputs: 0
12728 11:47:51.564287 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12729 11:47:51.577758 <14>[ 27.927816] [IGT] kms_vblank: executing
12730 11:47:51.584560 IGT-Version: 1.2<14>[ 27.933060] [IGT] kms_vblank: exiting, ret=77
12731 11:47:51.587493 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12732 11:47:51.591033 Opened device: /dev/dri/card0
12733 11:47:51.597805 N<8>[ 27.944129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12734 11:47:51.598080 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12736 11:47:51.600756 o KMS driver or no outputs, pipes: 8, outputs: 0
12737 11:47:51.607519 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12738 11:47:51.619907 <14>[ 27.969946] [IGT] kms_vblank: executing
12739 11:47:51.626794 IGT-Version: 1.2<14>[ 27.974883] [IGT] kms_vblank: exiting, ret=77
12740 11:47:51.630004 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12741 11:47:51.633263 Opened device: /dev/dri/card0
12742 11:47:51.639566 N<8>[ 27.986076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12743 11:47:51.639842 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12745 11:47:51.645975 o KMS driver or no outputs, pipes: 8, outputs: 0
12746 11:47:51.649691 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12747 11:47:51.662248 <14>[ 28.012126] [IGT] kms_vblank: executing
12748 11:47:51.668915 IGT-Version: 1.2<14>[ 28.017182] [IGT] kms_vblank: exiting, ret=77
12749 11:47:51.671908 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12750 11:47:51.675451 Opened device: /dev/dri/card0
12751 11:47:51.682372 N<8>[ 28.028339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12752 11:47:51.682638 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12754 11:47:51.685312 o KMS driver or no outputs, pipes: 8, outputs: 0
12755 11:47:51.691759 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12756 11:47:51.704189 <14>[ 28.054182] [IGT] kms_vblank: executing
12757 11:47:51.710730 IGT-Version: 1.2<14>[ 28.059267] [IGT] kms_vblank: exiting, ret=77
12758 11:47:51.714280 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12759 11:47:51.717258 Opened device: /dev/dri/card0
12760 11:47:51.724173 N<8>[ 28.070418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12761 11:47:51.724432 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12763 11:47:51.727222 o KMS driver or no outputs, pipes: 8, outputs: 0
12764 11:47:51.733618 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12765 11:47:51.746009 <14>[ 28.096265] [IGT] kms_vblank: executing
12766 11:47:51.753068 IGT-Version: 1.2<14>[ 28.101230] [IGT] kms_vblank: exiting, ret=77
12767 11:47:51.756193 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12768 11:47:51.759366 Opened device: /dev/dri/card0
12769 11:47:51.766322 N<8>[ 28.112429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12770 11:47:51.766582 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12772 11:47:51.769535 o KMS driver or no outputs, pipes: 8, outputs: 0
12773 11:47:51.775885 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12774 11:47:51.789039 <14>[ 28.138602] [IGT] kms_vblank: executing
12775 11:47:51.795002 IGT-Version: 1.2<14>[ 28.143817] [IGT] kms_vblank: exiting, ret=77
12776 11:47:51.798498 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12777 11:47:51.801922 Opened device: /dev/dri/card0
12778 11:47:51.808704 N<8>[ 28.154753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12779 11:47:51.808962 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12781 11:47:51.815115 o KMS driver or no outputs, pipes: 8, outputs: 0
12782 11:47:51.818167 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12783 11:47:51.831526 <14>[ 28.181609] [IGT] kms_vblank: executing
12784 11:47:51.837995 IGT-Version: 1.2<14>[ 28.186652] [IGT] kms_vblank: exiting, ret=77
12785 11:47:51.841821 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12786 11:47:51.844988 Opened device: /dev/dri/card0
12787 11:47:51.851212 N<8>[ 28.197759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12788 11:47:51.851468 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12790 11:47:51.858398 o KMS driver or no outputs, pipes: 8, outputs: 0
12791 11:47:51.861598 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12792 11:47:51.874441 <14>[ 28.224356] [IGT] kms_vblank: executing
12793 11:47:51.881284 IGT-Version: 1.2<14>[ 28.229346] [IGT] kms_vblank: exiting, ret=77
12794 11:47:51.884402 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12795 11:47:51.887432 Opened device: /dev/dri/card0
12796 11:47:51.894350 N<8>[ 28.240657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12797 11:47:51.894610 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12799 11:47:51.900886 o KMS driver or no outputs, pipes: 8, outputs: 0
12800 11:47:51.903745 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12801 11:47:51.917423 <14>[ 28.267556] [IGT] kms_vblank: executing
12802 11:47:51.924355 IGT-Version: 1.2<14>[ 28.272629] [IGT] kms_vblank: exiting, ret=77
12803 11:47:51.927439 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12804 11:47:51.930519 Opened device: /dev/dri/card0
12805 11:47:51.937219 N<8>[ 28.283799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12806 11:47:51.937478 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12808 11:47:51.943771 o KMS driver or no outputs, pipes: 8, outputs: 0
12809 11:47:51.946976 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12810 11:47:51.961521 <14>[ 28.311801] [IGT] kms_vblank: executing
12811 11:47:51.968364 IGT-Version: 1.2<14>[ 28.316800] [IGT] kms_vblank: exiting, ret=77
12812 11:47:51.971581 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12813 11:47:51.974776 Opened device: /dev/dri/card0
12814 11:47:51.981671 N<8>[ 28.328090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12815 11:47:51.981935 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12817 11:47:51.988015 o KMS driver or no outputs, pipes: 8, outputs: 0
12818 11:47:51.995055 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12819 11:47:52.004931 <14>[ 28.355088] [IGT] kms_vblank: executing
12820 11:47:52.011554 IGT-Version: 1.2<14>[ 28.360096] [IGT] kms_vblank: exiting, ret=77
12821 11:47:52.015095 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12822 11:47:52.018582 Opened device: /dev/dri/card0
12823 11:47:52.025045 N<8>[ 28.371212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12824 11:47:52.025326 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12826 11:47:52.031368 o KMS driver or no outputs, pipes: 8, outputs: 0
12827 11:47:52.034472 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12828 11:47:52.048873 <14>[ 28.398953] [IGT] kms_vblank: executing
12829 11:47:52.055891 IGT-Version: 1.2<14>[ 28.404267] [IGT] kms_vblank: exiting, ret=77
12830 11:47:52.059022 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12831 11:47:52.062129 Opened device: /dev/dri/card0
12832 11:47:52.068434 N<8>[ 28.415595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12833 11:47:52.068731 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12835 11:47:52.075537 o KMS driver or no outputs, pipes: 8, outputs: 0
12836 11:47:52.078691 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12837 11:47:52.093098 <14>[ 28.443284] [IGT] kms_vblank: executing
12838 11:47:52.099540 IGT-Version: 1.2<14>[ 28.448482] [IGT] kms_vblank: exiting, ret=77
12839 11:47:52.103320 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12840 11:47:52.106487 Opened device: /dev/dri/card0
12841 11:47:52.116390 N<8>[ 28.459716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12842 11:47:52.116673 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12844 11:47:52.119259 o KMS driver or no outputs, pipes: 8, outputs: 0
12845 11:47:52.126055 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12846 11:47:52.136653 <14>[ 28.486657] [IGT] kms_vblank: executing
12847 11:47:52.142862 IGT-Version: 1.2<14>[ 28.491826] [IGT] kms_vblank: exiting, ret=77
12848 11:47:52.146434 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12849 11:47:52.149918 Opened device: /dev/dri/card0
12850 11:47:52.156136 N<8>[ 28.503001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12851 11:47:52.156423 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12853 11:47:52.163217 o KMS driver or no outputs, pipes: 8, outputs: 0
12854 11:47:52.169691 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12855 11:47:52.179948 <14>[ 28.530123] [IGT] kms_vblank: executing
12856 11:47:52.186877 IGT-Version: 1.2<14>[ 28.535196] [IGT] kms_vblank: exiting, ret=77
12857 11:47:52.189953 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12858 11:47:52.193014 Opened device: /dev/dri/card0
12859 11:47:52.200185 N<8>[ 28.546132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12860 11:47:52.200469 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12862 11:47:52.203315 o KMS driver or no outputs, pipes: 8, outputs: 0
12863 11:47:52.209514 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12864 11:47:52.223229 <14>[ 28.573200] [IGT] kms_vblank: executing
12865 11:47:52.229536 IGT-Version: 1.2<14>[ 28.578185] [IGT] kms_vblank: exiting, ret=77
12866 11:47:52.233172 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12867 11:47:52.236129 Opened device: /dev/dri/card0
12868 11:47:52.242694 N<8>[ 28.589719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12869 11:47:52.242985 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12871 11:47:52.246084 o KMS driver or no outputs, pipes: 8, outputs: 0
12872 11:47:52.252917 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12873 11:47:52.265243 <14>[ 28.614863] [IGT] kms_vblank: executing
12874 11:47:52.271560 IGT-Version: 1.2<14>[ 28.619858] [IGT] kms_vblank: exiting, ret=77
12875 11:47:52.274710 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12876 11:47:52.278426 Opened device: /dev/dri/card0
12877 11:47:52.284623 N<8>[ 28.631051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12878 11:47:52.284912 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12880 11:47:52.287752 o KMS driver or no outputs, pipes: 8, outputs: 0
12881 11:47:52.294633 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12882 11:47:52.308018 <14>[ 28.657974] [IGT] kms_vblank: executing
12883 11:47:52.314251 IGT-Version: 1.2<14>[ 28.663259] [IGT] kms_vblank: exiting, ret=77
12884 11:47:52.318083 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12885 11:47:52.327953 Opened device: /<8>[ 28.673922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12886 11:47:52.328060 dev/dri/card0
12887 11:47:52.328334 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12889 11:47:52.331063 No KMS driver or no outputs, pipes: 8, outputs: 0
12890 11:47:52.337570 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12891 11:47:52.348461 <14>[ 28.698653] [IGT] kms_vblank: executing
12892 11:47:52.354999 IGT-Version: 1.2<14>[ 28.703863] [IGT] kms_vblank: exiting, ret=77
12893 11:47:52.358596 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12894 11:47:52.361647 Opened device: /dev/dri/card0
12895 11:47:52.368142 N<8>[ 28.714659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12896 11:47:52.368434 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12898 11:47:52.375105 o KMS driver or no outputs, pipes: 8, outputs: 0
12899 11:47:52.378393 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12900 11:47:52.391312 <14>[ 28.741206] [IGT] kms_vblank: executing
12901 11:47:52.397605 IGT-Version: 1.2<14>[ 28.746279] [IGT] kms_vblank: exiting, ret=77
12902 11:47:52.400918 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12903 11:47:52.411035 Opened device: /<8>[ 28.757332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12904 11:47:52.411124 dev/dri/card0
12905 11:47:52.411381 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12907 11:47:52.414268 No KMS driver or no outputs, pipes: 8, outputs: 0
12908 11:47:52.420719 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12909 11:47:52.431591 <14>[ 28.781780] [IGT] kms_vblank: executing
12910 11:47:52.438580 IGT-Version: 1.2<14>[ 28.786828] [IGT] kms_vblank: exiting, ret=77
12911 11:47:52.441538 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12912 11:47:52.444907 Opened device: /dev/dri/card0
12913 11:47:52.451669 N<8>[ 28.798090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12914 11:47:52.451930 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12916 11:47:52.455025 o KMS driver or no outputs, pipes: 8, outputs: 0
12917 11:47:52.461129 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12918 11:47:52.475342 <14>[ 28.825016] [IGT] kms_vblank: executing
12919 11:47:52.481732 IGT-Version: 1.2<14>[ 28.830016] [IGT] kms_vblank: exiting, ret=77
12920 11:47:52.485007 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12921 11:47:52.488022 Opened device: /dev/dri/card0
12922 11:47:52.494944 N<8>[ 28.841237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12923 11:47:52.495202 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12925 11:47:52.501766 o KMS driver or no outputs, pipes: 8, outputs: 0
12926 11:47:52.505026 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12927 11:47:52.517638 <14>[ 28.867280] [IGT] kms_vblank: executing
12928 11:47:52.524007 IGT-Version: 1.2<14>[ 28.872371] [IGT] kms_vblank: exiting, ret=77
12929 11:47:52.527343 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12930 11:47:52.537006 Opened device: /<8>[ 28.883299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12931 11:47:52.537134 dev/dri/card0
12932 11:47:52.537440 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12934 11:47:52.543466 No KMS driver or no outputs, pipes: 8, outputs: 0
12935 11:47:52.546922 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12936 11:47:52.559416 <14>[ 28.909477] [IGT] kms_vblank: executing
12937 11:47:52.565842 IGT-Version: 1.2<14>[ 28.914498] [IGT] kms_vblank: exiting, ret=77
12938 11:47:52.569466 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12939 11:47:52.578883 Opened device: /<8>[ 28.925423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12940 11:47:52.578985 dev/dri/card0
12941 11:47:52.579224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12943 11:47:52.582474 No KMS driver or no outputs, pipes: 8, outputs: 0
12944 11:47:52.588985 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12945 11:47:52.599765 <14>[ 28.949825] [IGT] kms_vblank: executing
12946 11:47:52.606628 IGT-Version: 1.2<14>[ 28.954834] [IGT] kms_vblank: exiting, ret=77
12947 11:47:52.609717 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12948 11:47:52.612997 Opened device: /dev/dri/card0
12949 11:47:52.619383 N<8>[ 28.965870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12950 11:47:52.619641 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12952 11:47:52.622592 o KMS driver or no outputs, pipes: 8, outputs: 0
12953 11:47:52.629121 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12954 11:47:52.642413 <14>[ 28.992667] [IGT] kms_vblank: executing
12955 11:47:52.649379 IGT-Version: 1.2<14>[ 28.997911] [IGT] kms_vblank: exiting, ret=77
12956 11:47:52.652453 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12957 11:47:52.655988 Opened device: /dev/dri/card0
12958 11:47:52.662333 N<8>[ 29.009328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12959 11:47:52.662594 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12961 11:47:52.666017 o KMS driver or no outputs, pipes: 8, outputs: 0
12962 11:47:52.672416 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12963 11:47:52.685145 <14>[ 29.035163] [IGT] kms_vblank: executing
12964 11:47:52.691538 IGT-Version: 1.2<14>[ 29.040181] [IGT] kms_vblank: exiting, ret=77
12965 11:47:52.694726 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12966 11:47:52.698426 Opened device: /dev/dri/card0
12967 11:47:52.704798 N<8>[ 29.051368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12968 11:47:52.705055 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12970 11:47:52.707940 o KMS driver or no outputs, pipes: 8, outputs: 0
12971 11:47:52.715008 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12972 11:47:52.727082 <14>[ 29.077294] [IGT] kms_vblank: executing
12973 11:47:52.734126 IGT-Version: 1.2<14>[ 29.082233] [IGT] kms_vblank: exiting, ret=77
12974 11:47:52.737381 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12975 11:47:52.740507 Opened device: /dev/dri/card0
12976 11:47:52.746784 N<8>[ 29.093547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12977 11:47:52.747088 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12979 11:47:52.750020 o KMS driver or no outputs, pipes: 8, outputs: 0
12980 11:47:52.757065 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12981 11:47:52.769439 <14>[ 29.119193] [IGT] kms_vblank: executing
12982 11:47:52.775962 IGT-Version: 1.2<14>[ 29.124280] [IGT] kms_vblank: exiting, ret=77
12983 11:47:52.778789 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12984 11:47:52.782528 Opened device: /dev/dri/card0
12985 11:47:52.788988 N<8>[ 29.135430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12986 11:47:52.789244 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12988 11:47:52.792562 o KMS driver or no outputs, pipes: 8, outputs: 0
12989 11:47:52.799024 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12990 11:47:52.811234 <14>[ 29.161311] [IGT] kms_vblank: executing
12991 11:47:52.817613 IGT-Version: 1.2<14>[ 29.166305] [IGT] kms_vblank: exiting, ret=77
12992 11:47:52.821354 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
12993 11:47:52.824552 Opened device: /dev/dri/card0
12994 11:47:52.830957 N<8>[ 29.177406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12995 11:47:52.831219 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12997 11:47:52.837850 o KMS driver or no outputs, pipes: 8, outputs: 0
12998 11:47:52.841051 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12999 11:47:52.853582 <14>[ 29.203827] [IGT] kms_vblank: executing
13000 11:47:52.860429 IGT-Version: 1.2<14>[ 29.208765] [IGT] kms_vblank: exiting, ret=77
13001 11:47:52.863563 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13002 11:47:52.866683 Opened device: /dev/dri/card0
13003 11:47:52.873407 N<8>[ 29.219924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13004 11:47:52.873662 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13006 11:47:52.880036 o KMS driver or no outputs, pipes: 8, outputs: 0
13007 11:47:52.883053 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13008 11:47:52.897376 <14>[ 29.247374] [IGT] kms_vblank: executing
13009 11:47:52.904053 IGT-Version: 1.2<14>[ 29.252446] [IGT] kms_vblank: exiting, ret=77
13010 11:47:52.907375 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13011 11:47:52.910471 Opened device: /dev/dri/card0
13012 11:47:52.917344 N<8>[ 29.263779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13013 11:47:52.917603 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13015 11:47:52.923652 o KMS driver or no outputs, pipes: 8, outputs: 0
13016 11:47:52.926783 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13017 11:47:52.940188 <14>[ 29.290084] [IGT] kms_vblank: executing
13018 11:47:52.946552 IGT-Version: 1.2<14>[ 29.295110] [IGT] kms_vblank: exiting, ret=77
13019 11:47:52.949584 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13020 11:47:52.953286 Opened device: /dev/dri/card0
13021 11:47:52.959788 N<8>[ 29.306084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13022 11:47:52.960044 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13024 11:47:52.966531 o KMS driver or no outputs, pipes: 8, outputs: 0
13025 11:47:52.969716 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13026 11:47:52.983134 <14>[ 29.333057] [IGT] kms_vblank: executing
13027 11:47:52.989594 IGT-Version: 1.2<14>[ 29.338149] [IGT] kms_vblank: exiting, ret=77
13028 11:47:52.993356 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13029 11:47:52.996291 Opened device: /dev/dri/card0
13030 11:47:53.002719 N<8>[ 29.349258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13031 11:47:53.003007 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13033 11:47:53.009371 o KMS driver or no outputs, pipes: 8, outputs: 0
13034 11:47:53.012983 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13035 11:47:53.025940 <14>[ 29.376343] [IGT] kms_vblank: executing
13036 11:47:53.032925 IGT-Version: 1.2<14>[ 29.381359] [IGT] kms_vblank: exiting, ret=77
13037 11:47:53.036171 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13038 11:47:53.039321 Opened device: /dev/dri/card0
13039 11:47:53.045832 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13041 11:47:53.048975 N<8>[ 29.392342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13042 11:47:53.052578 o KMS driver or no outputs, pipes: 8, outputs: 0
13043 11:47:53.058709 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13044 11:47:53.070234 <14>[ 29.420555] [IGT] kms_vblank: executing
13045 11:47:53.077108 IGT-Version: 1.2<14>[ 29.425536] [IGT] kms_vblank: exiting, ret=77
13046 11:47:53.080231 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13047 11:47:53.083805 Opened device: /dev/dri/card0
13048 11:47:53.090051 N<8>[ 29.436818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13049 11:47:53.090342 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13051 11:47:53.096584 o KMS driver or no outputs, pipes: 8, outputs: 0
13052 11:47:53.100299 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13053 11:47:53.114104 <14>[ 29.464126] [IGT] kms_vblank: executing
13054 11:47:53.120781 IGT-Version: 1.2<14>[ 29.469233] [IGT] kms_vblank: exiting, ret=77
13055 11:47:53.123847 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13056 11:47:53.126966 Opened device: /dev/dri/card0
13057 11:47:53.133933 N<8>[ 29.480521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13058 11:47:53.134191 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13060 11:47:53.140225 o KMS driver or no outputs, pipes: 8, outputs: 0
13061 11:47:53.143494 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13062 11:47:53.156907 <14>[ 29.507290] [IGT] kms_vblank: executing
13063 11:47:53.163880 IGT-Version: 1.2<14>[ 29.512351] [IGT] kms_vblank: exiting, ret=77
13064 11:47:53.167407 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13065 11:47:53.170383 Opened device: /dev/dri/card0
13066 11:47:53.176625 N<8>[ 29.523296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13067 11:47:53.176902 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13069 11:47:53.183531 o KMS driver or no outputs, pipes: 8, outputs: 0
13070 11:47:53.189657 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13071 11:47:53.200305 <14>[ 29.550671] [IGT] kms_vblank: executing
13072 11:47:53.207050 IGT-Version: 1.2<14>[ 29.555823] [IGT] kms_vblank: exiting, ret=77
13073 11:47:53.210537 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13074 11:47:53.220375 Opened device: /<8>[ 29.566613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13075 11:47:53.220694 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13077 11:47:53.223394 dev/dri/card0
13078 11:47:53.227133 No KMS driver or no outputs, pipes: 8, outputs: 0
13079 11:47:53.233353 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13080 11:47:53.243489 <14>[ 29.593530] [IGT] kms_vblank: executing
13081 11:47:53.249987 IGT-Version: 1.2<14>[ 29.598502] [IGT] kms_vblank: exiting, ret=77
13082 11:47:53.253084 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13083 11:47:53.256785 Opened device: /dev/dri/card0
13084 11:47:53.262984 N<8>[ 29.609711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13085 11:47:53.263265 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13087 11:47:53.266197 o KMS driver or no outputs, pipes: 8, outputs: 0
13088 11:47:53.273117 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13089 11:47:53.285628 <14>[ 29.635751] [IGT] kms_vblank: executing
13090 11:47:53.291884 IGT-Version: 1.2<14>[ 29.640739] [IGT] kms_vblank: exiting, ret=77
13091 11:47:53.295695 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13092 11:47:53.298874 Opened device: /dev/dri/card0
13093 11:47:53.305341 N<8>[ 29.651768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13094 11:47:53.305616 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13096 11:47:53.308816 o KMS driver or no outputs, pipes: 8, outputs: 0
13097 11:47:53.315262 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13098 11:47:53.328456 <14>[ 29.678437] [IGT] kms_vblank: executing
13099 11:47:53.334783 IGT-Version: 1.2<14>[ 29.683713] [IGT] kms_vblank: exiting, ret=77
13100 11:47:53.338304 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13101 11:47:53.348308 Opened device: /<8>[ 29.694506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13102 11:47:53.348416 dev/dri/card0
13103 11:47:53.348682 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13105 11:47:53.351365 No KMS driver or no outputs, pipes: 8, outputs: 0
13106 11:47:53.357707 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13107 11:47:53.370141 <14>[ 29.720546] [IGT] kms_vblank: executing
13108 11:47:53.377086 IGT-Version: 1.2<14>[ 29.725819] [IGT] kms_vblank: exiting, ret=77
13109 11:47:53.380323 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13110 11:47:53.383341 Opened device: /dev/dri/card0
13111 11:47:53.390234 N<8>[ 29.736716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13112 11:47:53.390522 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13114 11:47:53.393338 o KMS driver or no outputs, pipes: 8, outputs: 0
13115 11:47:53.399581 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13116 11:47:53.412588 <14>[ 29.762882] [IGT] kms_vblank: executing
13117 11:47:53.419261 IGT-Version: 1.2<14>[ 29.767930] [IGT] kms_vblank: exiting, ret=77
13118 11:47:53.422740 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13119 11:47:53.425648 Opened device: /dev/dri/card0
13120 11:47:53.432113 N<8>[ 29.778910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13121 11:47:53.432380 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13123 11:47:53.438878 o KMS driver or no outputs, pipes: 8, outputs: 0
13124 11:47:53.442302 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13125 11:47:53.455757 <14>[ 29.805982] [IGT] kms_vblank: executing
13126 11:47:53.462242 IGT-Version: 1.2<14>[ 29.811779] [IGT] kms_vblank: exiting, ret=77
13127 11:47:53.465987 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13128 11:47:53.469079 Opened device: /dev/dri/card0
13129 11:47:53.475291 N<8>[ 29.822623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13130 11:47:53.475595 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13132 11:47:53.482140 o KMS driver or no outputs, pipes: 8, outputs: 0
13133 11:47:53.485211 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13134 11:47:53.499534 <14>[ 29.849554] [IGT] kms_vblank: executing
13135 11:47:53.505905 IGT-Version: 1.2<14>[ 29.854826] [IGT] kms_vblank: exiting, ret=77
13136 11:47:53.509035 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13137 11:47:53.512231 Opened device: /dev/dri/card0
13138 11:47:53.519248 N<8>[ 29.865695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13139 11:47:53.519513 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13141 11:47:53.525657 o KMS driver or no outputs, pipes: 8, outputs: 0
13142 11:47:53.528676 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13143 11:47:53.542957 <14>[ 29.892895] [IGT] kms_vblank: executing
13144 11:47:53.549519 IGT-Version: 1.2<14>[ 29.898229] [IGT] kms_vblank: exiting, ret=77
13145 11:47:53.552417 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13146 11:47:53.555994 Opened device: /dev/dri/card0
13147 11:47:53.562760 N<8>[ 29.909482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13148 11:47:53.563058 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13150 11:47:53.569207 o KMS driver or no outputs, pipes: 8, outputs: 0
13151 11:47:53.572261 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13152 11:47:53.585545 <14>[ 29.935806] [IGT] kms_vblank: executing
13153 11:47:53.592526 IGT-Version: 1.2<14>[ 29.940820] [IGT] kms_vblank: exiting, ret=77
13154 11:47:53.595685 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13155 11:47:53.598713 Opened device: /dev/dri/card0
13156 11:47:53.605696 N<8>[ 29.952416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13157 11:47:53.605965 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13159 11:47:53.612090 o KMS driver or no outputs, pipes: 8, outputs: 0
13160 11:47:53.615108 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13161 11:47:53.628677 <14>[ 29.978948] [IGT] kms_vblank: executing
13162 11:47:53.635000 IGT-Version: 1.2<14>[ 29.984126] [IGT] kms_vblank: exiting, ret=77
13163 11:47:53.638705 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13164 11:47:53.641725 Opened device: /dev/dri/card0
13165 11:47:53.648118 N<8>[ 29.995195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13166 11:47:53.648414 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13168 11:47:53.651555 o KMS driver or no outputs, pipes: 8, outputs: 0
13169 11:47:53.658052 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13170 11:47:53.671156 <14>[ 30.021588] [IGT] kms_vblank: executing
13171 11:47:53.678038 IGT-Version: 1.2<14>[ 30.026520] [IGT] kms_vblank: exiting, ret=77
13172 11:47:53.681223 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13173 11:47:53.684202 Opened device: /dev/dri/card0
13174 11:47:53.691345 N<8>[ 30.037535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13175 11:47:53.691604 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13177 11:47:53.694341 o KMS driver or no outputs, pipes: 8, outputs: 0
13178 11:47:53.700898 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13179 11:47:53.713481 <14>[ 30.063754] [IGT] kms_vblank: executing
13180 11:47:53.720327 IGT-Version: 1.2<14>[ 30.068875] [IGT] kms_vblank: exiting, ret=77
13181 11:47:53.723476 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13182 11:47:53.726615 Opened device: /dev/dri/card0
13183 11:47:53.733052 N<8>[ 30.080039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13184 11:47:53.733310 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13186 11:47:53.736650 o KMS driver or no outputs, pipes: 8, outputs: 0
13187 11:47:53.743295 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13188 11:47:53.756306 <14>[ 30.106464] [IGT] kms_vblank: executing
13189 11:47:53.762973 IGT-Version: 1.2<14>[ 30.111888] [IGT] kms_vblank: exiting, ret=77
13190 11:47:53.766266 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13191 11:47:53.776080 Opened device: /<8>[ 30.122548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13192 11:47:53.776172 dev/dri/card0
13193 11:47:53.776430 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13195 11:47:53.782353 No KMS driver or no outputs, pipes: 8, outputs: 0
13196 11:47:53.785711 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13197 11:47:53.797689 <14>[ 30.147575] [IGT] kms_vblank: executing
13198 11:47:53.804008 IGT-Version: 1.2<14>[ 30.152539] [IGT] kms_vblank: exiting, ret=77
13199 11:47:53.807128 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13200 11:47:53.810855 Opened device: /dev/dri/card0
13201 11:47:53.817239 N<8>[ 30.163867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13202 11:47:53.817522 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13204 11:47:53.820487 o KMS driver or no outputs, pipes: 8, outputs: 0
13205 11:47:53.826859 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13206 11:47:53.839887 <14>[ 30.190151] [IGT] kms_vblank: executing
13207 11:47:53.846163 IGT-Version: 1.2<14>[ 30.195431] [IGT] kms_vblank: exiting, ret=77
13208 11:47:53.849731 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13209 11:47:53.859392 Opened device: /<8>[ 30.206058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13210 11:47:53.859506 dev/dri/card0
13211 11:47:53.859749 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13213 11:47:53.862953 No KMS driver or no outputs, pipes: 8, outputs: 0
13214 11:47:53.869806 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13215 11:47:53.881467 <14>[ 30.232023] [IGT] kms_vblank: executing
13216 11:47:53.888337 IGT-Version: 1.2<14>[ 30.237224] [IGT] kms_vblank: exiting, ret=77
13217 11:47:53.891915 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13218 11:47:53.895022 Opened device: /dev/dri/card0
13219 11:47:53.901413 N<8>[ 30.248204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13220 11:47:53.901681 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13222 11:47:53.908307 o KMS driver or no outputs, pipes: 8, outputs: 0
13223 11:47:53.911344 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13224 11:47:53.923877 <14>[ 30.274587] [IGT] kms_vblank: executing
13225 11:47:53.931046 IGT-Version: 1.2<14>[ 30.279699] [IGT] kms_vblank: exiting, ret=77
13226 11:47:53.934108 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13227 11:47:53.937330 Opened device: /dev/dri/card0
13228 11:47:53.944188 N<8>[ 30.290580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13229 11:47:53.944462 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13231 11:47:53.950478 o KMS driver or no outputs, pipes: 8, outputs: 0
13232 11:47:53.953417 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13233 11:47:53.967030 <14>[ 30.317402] [IGT] kms_vblank: executing
13234 11:47:53.973659 IGT-Version: 1.2<14>[ 30.322383] [IGT] kms_vblank: exiting, ret=77
13235 11:47:53.976803 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13236 11:47:53.980339 Opened device: /dev/dri/card0
13237 11:47:53.987003 N<8>[ 30.333406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13238 11:47:53.987315 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13240 11:47:53.993047 o KMS driver or no outputs, pipes: 8, outputs: 0
13241 11:47:53.996589 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13242 11:47:54.009922 <14>[ 30.360172] [IGT] kms_vblank: executing
13243 11:47:54.016359 IGT-Version: 1.2<14>[ 30.365253] [IGT] kms_vblank: exiting, ret=77
13244 11:47:54.019977 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13245 11:47:54.023276 Opened device: /dev/dri/card0
13246 11:47:54.029672 N<8>[ 30.376404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13247 11:47:54.029931 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13249 11:47:54.036154 o KMS driver or no outputs, pipes: 8, outputs: 0
13250 11:47:54.042543 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13251 11:47:54.054382 <14>[ 30.404303] [IGT] kms_vblank: executing
13252 11:47:54.060909 IGT-Version: 1.2<14>[ 30.409290] [IGT] kms_vblank: exiting, ret=77
13253 11:47:54.063919 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13254 11:47:54.067042 Opened device: /dev/dri/card0
13255 11:47:54.073806 N<8>[ 30.420564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13256 11:47:54.074100 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13258 11:47:54.080419 o KMS driver or no outputs, pipes: 8, outputs: 0
13259 11:47:54.084121 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13260 11:47:54.097332 <14>[ 30.447377] [IGT] kms_vblank: executing
13261 11:47:54.103867 IGT-Version: 1.2<14>[ 30.452380] [IGT] kms_vblank: exiting, ret=77
13262 11:47:54.106944 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13263 11:47:54.110001 Opened device: /dev/dri/card0
13264 11:47:54.117084 N<8>[ 30.463416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13265 11:47:54.117366 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13267 11:47:54.123777 o KMS driver or no outputs, pipes: 8, outputs: 0
13268 11:47:54.130207 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13269 11:47:54.141617 <14>[ 30.491878] [IGT] kms_vblank: executing
13270 11:47:54.148458 IGT-Version: 1.2<14>[ 30.497076] [IGT] kms_vblank: exiting, ret=77
13271 11:47:54.151532 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13272 11:47:54.154583 Opened device: /dev/dri/card0
13273 11:47:54.161459 N<8>[ 30.508228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13274 11:47:54.161746 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13276 11:47:54.167736 o KMS driver or no outputs, pipes: 8, outputs: 0
13277 11:47:54.171218 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13278 11:47:54.185119 <14>[ 30.534828] [IGT] kms_vblank: executing
13279 11:47:54.190835 IGT-Version: 1.2<14>[ 30.539808] [IGT] kms_vblank: exiting, ret=77
13280 11:47:54.194446 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13281 11:47:54.197486 Opened device: /dev/dri/card0
13282 11:47:54.204058 N<8>[ 30.550979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13283 11:47:54.204379 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13285 11:47:54.210743 o KMS driver or no outputs, pipes: 8, outputs: 0
13286 11:47:54.213936 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13287 11:47:54.228400 <14>[ 30.578733] [IGT] kms_vblank: executing
13288 11:47:54.234855 IGT-Version: 1.2<14>[ 30.584295] [IGT] kms_vblank: exiting, ret=77
13289 11:47:54.238079 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13290 11:47:54.241932 Opened device: /dev/dri/card0
13291 11:47:54.251531 N<8>[ 30.595597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13292 11:47:54.251812 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13294 11:47:54.254670 o KMS driver or no outputs, pipes: 8, outputs: 0
13295 11:47:54.261509 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13296 11:47:54.272311 <14>[ 30.622751] [IGT] kms_vblank: executing
13297 11:47:54.278937 IGT-Version: 1.2<14>[ 30.627925] [IGT] kms_vblank: exiting, ret=77
13298 11:47:54.282467 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13299 11:47:54.285644 Opened device: /dev/dri/card0
13300 11:47:54.292099 N<8>[ 30.639037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13301 11:47:54.292379 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13303 11:47:54.298726 o KMS driver or no outputs, pipes: 8, outputs: 0
13304 11:47:54.305187 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13305 11:47:54.315727 <14>[ 30.666113] [IGT] kms_vblank: executing
13306 11:47:54.322245 IGT-Version: 1.2<14>[ 30.671114] [IGT] kms_vblank: exiting, ret=77
13307 11:47:54.326028 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13308 11:47:54.328983 Opened device: /dev/dri/card0
13309 11:47:54.335986 N<8>[ 30.682097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13310 11:47:54.336253 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13312 11:47:54.339247 o KMS driver or no outputs, pipes: 8, outputs: 0
13313 11:47:54.345338 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13314 11:47:54.358604 <14>[ 30.709044] [IGT] kms_vblank: executing
13315 11:47:54.365251 IGT-Version: 1.2<14>[ 30.714097] [IGT] kms_vblank: exiting, ret=77
13316 11:47:54.368285 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13317 11:47:54.372169 Opened device: /dev/dri/card0
13318 11:47:54.378494 N<8>[ 30.725347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13319 11:47:54.378761 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13321 11:47:54.381848 o KMS driver or no outputs, pipes: 8, outputs: 0
13322 11:47:54.388017 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13323 11:47:54.400894 <14>[ 30.751129] [IGT] kms_vblank: executing
13324 11:47:54.407710 IGT-Version: 1.2<14>[ 30.756146] [IGT] kms_vblank: exiting, ret=77
13325 11:47:54.410751 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13326 11:47:54.414341 Opened device: /dev/dri/card0
13327 11:47:54.420441 N<8>[ 30.767333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13328 11:47:54.420707 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13330 11:47:54.424161 o KMS driver or no outputs, pipes: 8, outputs: 0
13331 11:47:54.430169 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13332 11:47:54.443405 <14>[ 30.793380] [IGT] kms_vblank: executing
13333 11:47:54.449499 IGT-Version: 1.2<14>[ 30.798368] [IGT] kms_vblank: exiting, ret=77
13334 11:47:54.452833 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13335 11:47:54.456099 Opened device: /dev/dri/card0
13336 11:47:54.462576 N<8>[ 30.809614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13337 11:47:54.462847 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13339 11:47:54.466217 o KMS driver or no outputs, pipes: 8, outputs: 0
13340 11:47:54.472540 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13341 11:47:54.486094 <14>[ 30.836353] [IGT] kms_vblank: executing
13342 11:47:54.492913 IGT-Version: 1.2<14>[ 30.841531] [IGT] kms_vblank: exiting, ret=77
13343 11:47:54.496244 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13344 11:47:54.499237 Opened device: /dev/dri/card0
13345 11:47:54.505834 N<8>[ 30.852543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13346 11:47:54.506097 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13348 11:47:54.512403 o KMS driver or no outputs, pipes: 8, outputs: 0
13349 11:47:54.515892 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13350 11:47:54.529211 <14>[ 30.879708] [IGT] kms_vblank: executing
13351 11:47:54.536264 IGT-Version: 1.2<14>[ 30.884961] [IGT] kms_vblank: exiting, ret=77
13352 11:47:54.539262 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13353 11:47:54.542365 Opened device: /dev/dri/card0
13354 11:47:54.549090 N<8>[ 30.896066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13355 11:47:54.549358 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13357 11:47:54.552260 o KMS driver or no outputs, pipes: 8, outputs: 0
13358 11:47:54.559277 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13359 11:47:54.571902 <14>[ 30.921852] [IGT] kms_vblank: executing
13360 11:47:54.577938 IGT-Version: 1.2<14>[ 30.926850] [IGT] kms_vblank: exiting, ret=77
13361 11:47:54.581119 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13362 11:47:54.591263 Opened device: /<8>[ 30.937786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13363 11:47:54.591348 dev/dri/card0
13364 11:47:54.591586 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13366 11:47:54.594460 No KMS driver or no outputs, pipes: 8, outputs: 0
13367 11:47:54.601201 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13368 11:47:54.612116 <14>[ 30.962696] [IGT] kms_vblank: executing
13369 11:47:54.618787 IGT-Version: 1.2<14>[ 30.967861] [IGT] kms_vblank: exiting, ret=77
13370 11:47:54.622021 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13371 11:47:54.632308 Opened device: /<8>[ 30.978644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13372 11:47:54.632449 dev/dri/card0
13373 11:47:54.632706 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13375 11:47:54.638806 No KMS driver or no outputs, pipes: 8, outputs: 0
13376 11:47:54.641792 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13377 11:47:54.654193 <14>[ 31.004562] [IGT] kms_vblank: executing
13378 11:47:54.660679 IGT-Version: 1.2<14>[ 31.010227] [IGT] kms_vblank: exiting, ret=77
13379 11:47:54.664487 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13380 11:47:54.667690 Opened device: /dev/dri/card0
13381 11:47:54.674134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13383 11:47:54.677608 N<8>[ 31.021525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13384 11:47:54.680783 o KMS driver or no outputs, pipes: 8, outputs: 0
13385 11:47:54.683990 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13386 11:47:54.698704 <14>[ 31.049128] [IGT] kms_vblank: executing
13387 11:47:54.705601 IGT-Version: 1.2<14>[ 31.054255] [IGT] kms_vblank: exiting, ret=77
13388 11:47:54.708739 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13389 11:47:54.711707 Opened device: /dev/dri/card0
13390 11:47:54.718802 N<8>[ 31.065557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13391 11:47:54.719107 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13393 11:47:54.721766 o KMS driver or no outputs, pipes: 8, outputs: 0
13394 11:47:54.728482 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13395 11:47:54.740897 <14>[ 31.091054] [IGT] kms_vblank: executing
13396 11:47:54.747464 IGT-Version: 1.2<14>[ 31.096057] [IGT] kms_vblank: exiting, ret=77
13397 11:47:54.750557 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13398 11:47:54.760273 Opened device: /<8>[ 31.106881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13399 11:47:54.760387 dev/dri/card0
13400 11:47:54.760660 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13402 11:47:54.763465 No KMS driver or no outputs, pipes: 8, outputs: 0
13403 11:47:54.770384 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13404 11:47:54.782155 <14>[ 31.132475] [IGT] kms_vblank: executing
13405 11:47:54.788511 IGT-Version: 1.2<14>[ 31.137544] [IGT] kms_vblank: exiting, ret=77
13406 11:47:54.791900 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13407 11:47:54.795453 Opened device: /dev/dri/card0
13408 11:47:54.801932 N<8>[ 31.148940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13409 11:47:54.802216 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13411 11:47:54.805005 o KMS driver or no outputs, pipes: 8, outputs: 0
13412 11:47:54.811912 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13413 11:47:54.823942 <14>[ 31.174451] [IGT] kms_vblank: executing
13414 11:47:54.830346 IGT-Version: 1.2<14>[ 31.179544] [IGT] kms_vblank: exiting, ret=77
13415 11:47:54.834088 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13416 11:47:54.843746 Opened device: /<8>[ 31.190220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13417 11:47:54.843836 dev/dri/card0
13418 11:47:54.844075 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13420 11:47:54.847439 No KMS driver or no outputs, pipes: 8, outputs: 0
13421 11:47:54.853507 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13422 11:47:54.865694 <14>[ 31.216002] [IGT] kms_vblank: executing
13423 11:47:54.871975 IGT-Version: 1.2<14>[ 31.221055] [IGT] kms_vblank: exiting, ret=77
13424 11:47:54.875880 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13425 11:47:54.879004 Opened device: /dev/dri/card0
13426 11:47:54.885705 N<8>[ 31.232318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13427 11:47:54.885977 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13429 11:47:54.889037 o KMS driver or no outputs, pipes: 8, outputs: 0
13430 11:47:54.895524 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13431 11:47:54.908157 <14>[ 31.258703] [IGT] kms_vblank: executing
13432 11:47:54.914869 IGT-Version: 1.2<14>[ 31.264071] [IGT] kms_vblank: exiting, ret=77
13433 11:47:54.918030 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13434 11:47:54.921136 Opened device: /dev/dri/card0
13435 11:47:54.927871 N<8>[ 31.275011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13436 11:47:54.928128 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13438 11:47:54.934835 o KMS driver or no outputs, pipes: 8, outputs: 0
13439 11:47:54.938179 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13440 11:47:54.951220 <14>[ 31.301250] [IGT] kms_vblank: executing
13441 11:47:54.957657 IGT-Version: 1.2<14>[ 31.306372] [IGT] kms_vblank: exiting, ret=77
13442 11:47:54.960623 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13443 11:47:54.970425 Opened device: /<8>[ 31.317237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13444 11:47:54.970530 dev/dri/card0
13445 11:47:54.970767 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13447 11:47:54.977613 No KMS driver or no outputs, pipes: 8, outputs: 0
13448 11:47:54.980779 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13449 11:47:54.992588 <14>[ 31.343048] [IGT] kms_vblank: executing
13450 11:47:54.999553 IGT-Version: 1.2<14>[ 31.348619] [IGT] kms_vblank: exiting, ret=77
13451 11:47:55.002769 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13452 11:47:55.005857 Opened device: /dev/dri/card0
13453 11:47:55.012245 N<8>[ 31.359630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13454 11:47:55.012501 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13456 11:47:55.019119 o KMS driver or no outputs, pipes: 8, outputs: 0
13457 11:47:55.022426 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13458 11:47:55.037178 <14>[ 31.387314] [IGT] kms_vblank: executing
13459 11:47:55.043803 IGT-Version: 1.2<14>[ 31.392564] [IGT] kms_vblank: exiting, ret=77
13460 11:47:55.047197 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13461 11:47:55.050114 Opened device: /dev/dri/card0
13462 11:47:55.056489 N<8>[ 31.404200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13463 11:47:55.056753 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13465 11:47:55.063380 o KMS driver or no outputs, pipes: 8, outputs: 0
13466 11:47:55.066449 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13467 11:47:55.081244 <14>[ 31.431495] [IGT] kms_vblank: executing
13468 11:47:55.087892 IGT-Version: 1.2<14>[ 31.436513] [IGT] kms_vblank: exiting, ret=77
13469 11:47:55.090967 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13470 11:47:55.094079 Opened device: /dev/dri/card0
13471 11:47:55.101022 N<8>[ 31.447654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13472 11:47:55.101278 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13474 11:47:55.107282 o KMS driver or no outputs, pipes: 8, outputs: 0
13475 11:47:55.111078 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13476 11:47:55.124339 <14>[ 31.474452] [IGT] kms_vblank: executing
13477 11:47:55.130614 IGT-Version: 1.2<14>[ 31.479638] [IGT] kms_vblank: exiting, ret=77
13478 11:47:55.133846 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13479 11:47:55.143531 Opened device: /<8>[ 31.490394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13480 11:47:55.143654 dev/dri/card0
13481 11:47:55.143950 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13483 11:47:55.150617 No KMS driver or no outputs, pipes: 8, outputs: 0
13484 11:47:55.153543 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13485 11:47:55.166181 <14>[ 31.516859] [IGT] kms_vblank: executing
13486 11:47:55.172922 IGT-Version: 1.2<14>[ 31.522174] [IGT] kms_vblank: exiting, ret=77
13487 11:47:55.176208 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13488 11:47:55.179379 Opened device: /dev/dri/card0
13489 11:47:55.189624 N<8>[ 31.533207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13490 11:47:55.189890 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13492 11:47:55.192700 o KMS driver or no outputs, pipes: 8, outputs: 0
13493 11:47:55.199173 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13494 11:47:55.211275 <14>[ 31.561486] [IGT] kms_vblank: executing
13495 11:47:55.217687 IGT-Version: 1.2<14>[ 31.566800] [IGT] kms_vblank: exiting, ret=77
13496 11:47:55.220867 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13497 11:47:55.224628 Opened device: /dev/dri/card0
13498 11:47:55.230698 N<8>[ 31.577797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13499 11:47:55.230984 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13501 11:47:55.237596 o KMS driver or no outputs, pipes: 8, outputs: 0
13502 11:47:55.241002 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13503 11:47:55.255040 <14>[ 31.605612] [IGT] kms_vblank: executing
13504 11:47:55.262099 IGT-Version: 1.2<14>[ 31.611228] [IGT] kms_vblank: exiting, ret=77
13505 11:47:55.265030 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13506 11:47:55.268328 Opened device: /dev/dri/card0
13507 11:47:55.275017 N<8>[ 31.622127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13508 11:47:55.275281 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13510 11:47:55.281935 o KMS driver or no outputs, pipes: 8, outputs: 0
13511 11:47:55.285192 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13512 11:47:55.299585 <14>[ 31.649913] [IGT] kms_vblank: executing
13513 11:47:55.305987 IGT-Version: 1.2<14>[ 31.655209] [IGT] kms_vblank: exiting, ret=77
13514 11:47:55.309777 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13515 11:47:55.312832 Opened device: /dev/dri/card0
13516 11:47:55.319250 N<8>[ 31.666211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13517 11:47:55.319503 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13519 11:47:55.325699 o KMS driver or no outputs, pipes: 8, outputs: 0
13520 11:47:55.332435 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13521 11:47:55.343251 <14>[ 31.693471] [IGT] kms_vblank: executing
13522 11:47:55.349617 IGT-Version: 1.2<14>[ 31.698613] [IGT] kms_vblank: exiting, ret=77
13523 11:47:55.352840 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13524 11:47:55.355972 Opened device: /dev/dri/card0
13525 11:47:55.363117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13527 11:47:55.365855 N<8>[ 31.709545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13528 11:47:55.369467 o KMS driver or no outputs, pipes: 8, outputs: 0
13529 11:47:55.376017 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13530 11:47:55.387456 <14>[ 31.737568] [IGT] kms_vblank: executing
13531 11:47:55.393774 IGT-Version: 1.2<14>[ 31.742719] [IGT] kms_vblank: exiting, ret=77
13532 11:47:55.396815 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13533 11:47:55.400449 Opened device: /dev/dri/card0
13534 11:47:55.406651 N<8>[ 31.753898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13535 11:47:55.406927 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13537 11:47:55.410172 o KMS driver or no outputs, pipes: 8, outputs: 0
13538 11:47:55.416400 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13539 11:47:55.429561 <14>[ 31.779866] [IGT] kms_vblank: executing
13540 11:47:55.436327 IGT-Version: 1.2<14>[ 31.784850] [IGT] kms_vblank: exiting, ret=77
13541 11:47:55.439502 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13542 11:47:55.442696 Opened device: /dev/dri/card0
13543 11:47:55.449046 N<8>[ 31.795981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13544 11:47:55.449334 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13546 11:47:55.452231 o KMS driver or no outputs, pipes: 8, outputs: 0
13547 11:47:55.459239 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13548 11:47:55.471363 <14>[ 31.821930] [IGT] kms_vblank: executing
13549 11:47:55.477856 IGT-Version: 1.2<14>[ 31.826967] [IGT] kms_vblank: exiting, ret=77
13550 11:47:55.481263 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13551 11:47:55.491213 Opened device: /<8>[ 31.837836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13552 11:47:55.491306 dev/dri/card0
13553 11:47:55.491547 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13555 11:47:55.494352 No KMS driver or no outputs, pipes: 8, outputs: 0
13556 11:47:55.501336 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13557 11:47:55.512276 <14>[ 31.862804] [IGT] kms_vblank: executing
13558 11:47:55.519019 IGT-Version: 1.2<14>[ 31.867809] [IGT] kms_vblank: exiting, ret=77
13559 11:47:55.522056 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13560 11:47:55.525933 Opened device: /dev/dri/card0
13561 11:47:55.532301 N<8>[ 31.878973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13562 11:47:55.532556 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13564 11:47:55.535577 o KMS driver or no outputs, pipes: 8, outputs: 0
13565 11:47:55.541829 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13566 11:47:55.555504 <14>[ 31.905840] [IGT] kms_vblank: executing
13567 11:47:55.562182 IGT-Version: 1.2<14>[ 31.911172] [IGT] kms_vblank: exiting, ret=77
13568 11:47:55.565257 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13569 11:47:55.575158 Opened device: /<8>[ 31.921844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13570 11:47:55.575285 dev/dri/card0
13571 11:47:55.575535 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13573 11:47:55.582112 No KMS driver or no outputs, pipes: 8, outputs: 0
13574 11:47:55.584925 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13575 11:47:55.597762 <14>[ 31.947906] [IGT] kms_vblank: executing
13576 11:47:55.604331 IGT-Version: 1.2<14>[ 31.953131] [IGT] kms_vblank: exiting, ret=77
13577 11:47:55.607429 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13578 11:47:55.617360 Opened device: /<8>[ 31.963946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13579 11:47:55.617468 dev/dri/card0
13580 11:47:55.617716 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13582 11:47:55.620498 No KMS driver or no outputs, pipes: 8, outputs: 0
13583 11:47:55.626995 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13584 11:47:55.638488 <14>[ 31.988618] [IGT] kms_vblank: executing
13585 11:47:55.644706 IGT-Version: 1.2<14>[ 31.993616] [IGT] kms_vblank: exiting, ret=77
13586 11:47:55.647882 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13587 11:47:55.658084 Opened device: /<8>[ 32.004443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13588 11:47:55.658172 dev/dri/card0
13589 11:47:55.658412 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13591 11:47:55.661241 No KMS driver or no outputs, pipes: 8, outputs: 0
13592 11:47:55.667590 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13593 11:47:55.678836 <14>[ 32.029384] [IGT] kms_vblank: executing
13594 11:47:55.685600 IGT-Version: 1.2<14>[ 32.034363] [IGT] kms_vblank: exiting, ret=77
13595 11:47:55.688607 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13596 11:47:55.692376 Opened device: /dev/dri/card0
13597 11:47:55.698981 N<8>[ 32.045495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13598 11:47:55.699260 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13600 11:47:55.705000 o KMS driver or no outputs, pipes: 8, outputs: 0
13601 11:47:55.708629 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13602 11:47:55.721424 <14>[ 32.071848] [IGT] kms_vblank: executing
13603 11:47:55.727980 IGT-Version: 1.2<14>[ 32.076841] [IGT] kms_vblank: exiting, ret=77
13604 11:47:55.731526 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13605 11:47:55.734586 Opened device: /dev/dri/card0
13606 11:47:55.741539 N<8>[ 32.087982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13607 11:47:55.741828 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13609 11:47:55.747614 o KMS driver or no outputs, pipes: 8, outputs: 0
13610 11:47:55.751450 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13611 11:47:55.764300 <14>[ 32.114867] [IGT] kms_vblank: executing
13612 11:47:55.771402 IGT-Version: 1.2<14>[ 32.119898] [IGT] kms_vblank: exiting, ret=77
13613 11:47:55.774519 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13614 11:47:55.783886 Opened device: /<8>[ 32.130682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13615 11:47:55.784018 dev/dri/card0
13616 11:47:55.784264 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13618 11:47:55.787203 No KMS driver or no outputs, pipes: 8, outputs: 0
13619 11:47:55.793772 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13620 11:47:55.805624 <14>[ 32.156164] [IGT] kms_vblank: executing
13621 11:47:55.812683 IGT-Version: 1.2<14>[ 32.161223] [IGT] kms_vblank: exiting, ret=77
13622 11:47:55.815733 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13623 11:47:55.818705 Opened device: /dev/dri/card0
13624 11:47:55.825485 N<8>[ 32.172405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13625 11:47:55.825795 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13627 11:47:55.828648 o KMS driver or no outputs, pipes: 8, outputs: 0
13628 11:47:55.835274 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13629 11:47:55.847934 <14>[ 32.198083] [IGT] kms_vblank: executing
13630 11:47:55.854137 IGT-Version: 1.2<14>[ 32.203218] [IGT] kms_vblank: exiting, ret=77
13631 11:47:55.857362 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13632 11:47:55.867704 Opened device: /<8>[ 32.214150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13633 11:47:55.867849 dev/dri/card0
13634 11:47:55.868101 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13636 11:47:55.870739 No KMS driver or no outputs, pipes: 8, outputs: 0
13637 11:47:55.877017 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13638 11:47:55.888234 <14>[ 32.238719] [IGT] kms_vblank: executing
13639 11:47:55.894635 IGT-Version: 1.2<14>[ 32.243837] [IGT] kms_vblank: exiting, ret=77
13640 11:47:55.898281 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13641 11:47:55.907854 Opened device: /<8>[ 32.254722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13642 11:47:55.907945 dev/dri/card0
13643 11:47:55.908185 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13645 11:47:55.914585 No KMS driver or no outputs, pipes: 8, outputs: 0
13646 11:47:55.917828 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13647 11:47:55.930018 <14>[ 32.280713] [IGT] kms_vblank: executing
13648 11:47:55.936954 IGT-Version: 1.2<14>[ 32.286055] [IGT] kms_vblank: exiting, ret=77
13649 11:47:55.940128 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13650 11:47:55.943683 Opened device: /dev/dri/card0
13651 11:47:55.950330 N<8>[ 32.297451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13652 11:47:55.950600 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13654 11:47:55.953326 o KMS driver or no outputs, pipes: 8, outputs: 0
13655 11:47:55.959983 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13656 11:47:55.972192 <14>[ 32.322802] [IGT] kms_vblank: executing
13657 11:47:55.979163 IGT-Version: 1.2<14>[ 32.327930] [IGT] kms_vblank: exiting, ret=77
13658 11:47:55.982423 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13659 11:47:55.985699 Opened device: /dev/dri/card0
13660 11:47:55.992153 N<8>[ 32.339950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13661 11:47:55.992413 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13663 11:47:55.995440 o KMS driver or no outputs, pipes: 8, outputs: 0
13664 11:47:56.001746 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13665 11:47:56.014972 <14>[ 32.365531] [IGT] kms_vblank: executing
13666 11:47:56.021432 IGT-Version: 1.2<14>[ 32.370645] [IGT] kms_vblank: exiting, ret=77
13667 11:47:56.025143 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13668 11:47:56.028109 Opened device: /dev/dri/card0
13669 11:47:56.034812 N<8>[ 32.382031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13670 11:47:56.035146 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13672 11:47:56.041647 o KMS driver or no outputs, pipes: 8, outputs: 0
13673 11:47:56.044923 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13674 11:47:56.058583 <14>[ 32.409169] [IGT] kms_vblank: executing
13675 11:47:56.065578 IGT-Version: 1.2<14>[ 32.414338] [IGT] kms_vblank: exiting, ret=77
13676 11:47:56.068777 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13677 11:47:56.071906 Opened device: /dev/dri/card0
13678 11:47:56.078353 N<8>[ 32.425802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13679 11:47:56.078618 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13681 11:47:56.085363 o KMS driver or no outputs, pipes: 8, outputs: 0
13682 11:47:56.088504 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13683 11:47:56.102144 <14>[ 32.452516] [IGT] kms_vblank: executing
13684 11:47:56.108551 IGT-Version: 1.2<14>[ 32.457481] [IGT] kms_vblank: exiting, ret=77
13685 11:47:56.112150 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13686 11:47:56.115169 Opened device: /dev/dri/card0
13687 11:47:56.121682 N<8>[ 32.468802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13688 11:47:56.121959 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13690 11:47:56.128309 o KMS driver or no outputs, pipes: 8, outputs: 0
13691 11:47:56.131384 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13692 11:47:56.145322 <14>[ 32.496053] [IGT] kms_vblank: executing
13693 11:47:56.152109 IGT-Version: 1.2<14>[ 32.501012] [IGT] kms_vblank: exiting, ret=77
13694 11:47:56.155321 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13695 11:47:56.158884 Opened device: /dev/dri/card0
13696 11:47:56.165463 N<8>[ 32.512638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13697 11:47:56.165767 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13699 11:47:56.171791 o KMS driver or no outputs, pipes: 8, outputs: 0
13700 11:47:56.175469 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13701 11:47:56.189504 <14>[ 32.539822] [IGT] kms_vblank: executing
13702 11:47:56.195777 IGT-Version: 1.2<14>[ 32.544752] [IGT] kms_vblank: exiting, ret=77
13703 11:47:56.198915 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13704 11:47:56.202848 Opened device: /dev/dri/card0
13705 11:47:56.209206 N<8>[ 32.556241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13706 11:47:56.209454 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13708 11:47:56.215663 o KMS driver or no outputs, pipes: 8, outputs: 0
13709 11:47:56.218685 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13710 11:47:56.232933 <14>[ 32.583383] [IGT] kms_vblank: executing
13711 11:47:56.239476 IGT-Version: 1.2<14>[ 32.588437] [IGT] kms_vblank: exiting, ret=77
13712 11:47:56.242449 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13713 11:47:56.246180 Opened device: /dev/dri/card0
13714 11:47:56.252572 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13716 11:47:56.256074 N<8>[ 32.600095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13717 11:47:56.259042 o KMS driver or no outputs, pipes: 8, outputs: 0
13718 11:47:56.265451 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13719 11:47:56.277157 <14>[ 32.627470] [IGT] kms_vblank: executing
13720 11:47:56.283506 IGT-Version: 1.2<14>[ 32.632536] [IGT] kms_vblank: exiting, ret=77
13721 11:47:56.286737 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13722 11:47:56.289955 Opened device: /dev/dri/card0
13723 11:47:56.296855 N<8>[ 32.644016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13724 11:47:56.297114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13726 11:47:56.303609 o KMS driver or no outputs, pipes: 8, outputs: 0
13727 11:47:56.306842 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13728 11:47:56.321318 <14>[ 32.671574] [IGT] kms_vblank: executing
13729 11:47:56.327833 IGT-Version: 1.2<14>[ 32.676571] [IGT] kms_vblank: exiting, ret=77
13730 11:47:56.331178 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13731 11:47:56.334074 Opened device: /dev/dri/card0
13732 11:47:56.340647 N<8>[ 32.688281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13733 11:47:56.340943 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13735 11:47:56.347622 o KMS driver or no outputs, pipes: 8, outputs: 0
13736 11:47:56.350791 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13737 11:47:56.364897 <14>[ 32.715600] [IGT] kms_vblank: executing
13738 11:47:56.371449 IGT-Version: 1.2<14>[ 32.720797] [IGT] kms_vblank: exiting, ret=77
13739 11:47:56.375056 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13740 11:47:56.378023 Opened device: /dev/dri/card0
13741 11:47:56.385346 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13743 11:47:56.388275 N<8>[ 32.732081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13744 11:47:56.391507 o KMS driver or no outputs, pipes: 8, outputs: 0
13745 11:47:56.397956 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13746 11:47:56.409264 <14>[ 32.759580] [IGT] kms_vblank: executing
13747 11:47:56.415709 IGT-Version: 1.2<14>[ 32.764613] [IGT] kms_vblank: exiting, ret=77
13748 11:47:56.418972 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13749 11:47:56.422098 Opened device: /dev/dri/card0
13750 11:47:56.429025 N<8>[ 32.776147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13751 11:47:56.429324 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13753 11:47:56.435578 o KMS driver or no outputs, pipes: 8, outputs: 0
13754 11:47:56.442156 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13755 11:47:56.453335 <14>[ 32.803748] [IGT] kms_vblank: executing
13756 11:47:56.459834 IGT-Version: 1.2<14>[ 32.808845] [IGT] kms_vblank: exiting, ret=77
13757 11:47:56.462918 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13758 11:47:56.466319 Opened device: /dev/dri/card0
13759 11:47:56.473097 N<8>[ 32.820508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13760 11:47:56.473424 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13762 11:47:56.476681 o KMS driver or no outputs, pipes: 8, outputs: 0
13763 11:47:56.483012 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13764 11:47:56.497059 <14>[ 32.847594] [IGT] kms_vblank: executing
13765 11:47:56.503349 IGT-Version: 1.2<14>[ 32.852827] [IGT] kms_vblank: exiting, ret=77
13766 11:47:56.507026 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13767 11:47:56.510025 Opened device: /dev/dri/card0
13768 11:47:56.516443 N<8>[ 32.864163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13769 11:47:56.516700 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13771 11:47:56.520371 o KMS driver or no outputs, pipes: 8, outputs: 0
13772 11:47:56.526785 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13773 11:47:56.539617 <14>[ 32.889749] [IGT] kms_vblank: executing
13774 11:47:56.545586 IGT-Version: 1.2<14>[ 32.894798] [IGT] kms_vblank: exiting, ret=77
13775 11:47:56.548959 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13776 11:47:56.552588 Opened device: /dev/dri/card0
13777 11:47:56.559235 N<8>[ 32.906191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13778 11:47:56.559512 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13780 11:47:56.565652 o KMS driver or no outputs, pipes: 8, outputs: 0
13781 11:47:56.568577 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13782 11:47:56.582458 <14>[ 32.932958] [IGT] kms_vblank: executing
13783 11:47:56.588935 IGT-Version: 1.2<14>[ 32.938128] [IGT] kms_vblank: exiting, ret=77
13784 11:47:56.592435 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13785 11:47:56.595487 Opened device: /dev/dri/card0
13786 11:47:56.602149 N<8>[ 32.949398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13787 11:47:56.602445 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13789 11:47:56.605281 o KMS driver or no outputs, pipes: 8, outputs: 0
13790 11:47:56.612265 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13791 11:47:56.624291 <14>[ 32.975145] [IGT] kms_vblank: executing
13792 11:47:56.630942 IGT-Version: 1.2<14>[ 32.980238] [IGT] kms_vblank: exiting, ret=77
13793 11:47:56.634746 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13794 11:47:56.637940 Opened device: /dev/dri/card0
13795 11:47:56.644234 N<8>[ 32.991756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13796 11:47:56.644523 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13798 11:47:56.650809 o KMS driver or no outputs, pipes: 8, outputs: 0
13799 11:47:56.654358 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13800 11:47:56.667952 <14>[ 33.018421] [IGT] kms_vblank: executing
13801 11:47:56.674247 IGT-Version: 1.2<14>[ 33.023731] [IGT] kms_vblank: exiting, ret=77
13802 11:47:56.677555 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13803 11:47:56.681123 Opened device: /dev/dri/card0
13804 11:47:56.687924 N<8>[ 33.034474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13805 11:47:56.688219 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13807 11:47:56.690988 o KMS driver or no outputs, pipes: 8, outputs: 0
13808 11:47:56.697453 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13809 11:47:56.710521 <14>[ 33.061188] [IGT] kms_vblank: executing
13810 11:47:56.717392 IGT-Version: 1.2<14>[ 33.066715] [IGT] kms_vblank: exiting, ret=77
13811 11:47:56.720520 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13812 11:47:56.723819 Opened device: /dev/dri/card0
13813 11:47:56.730743 N<8>[ 33.077783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13814 11:47:56.731010 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13816 11:47:56.737184 o KMS driver or no outputs, pipes: 8, outputs: 0
13817 11:47:56.740442 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13818 11:47:56.753784 <14>[ 33.104061] [IGT] kms_vblank: executing
13819 11:47:56.759812 IGT-Version: 1.2<14>[ 33.109158] [IGT] kms_vblank: exiting, ret=77
13820 11:47:56.763550 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13821 11:47:56.766627 Opened device: /dev/dri/card0
13822 11:47:56.773410 N<8>[ 33.120384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13823 11:47:56.773685 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13825 11:47:56.779586 o KMS driver or no outputs, pipes: 8, outputs: 0
13826 11:47:56.783229 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13827 11:47:56.796215 <14>[ 33.146602] [IGT] kms_vblank: executing
13828 11:47:56.802682 IGT-Version: 1.2<14>[ 33.151716] [IGT] kms_vblank: exiting, ret=77
13829 11:47:56.805590 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13830 11:47:56.809409 Opened device: /dev/dri/card0
13831 11:47:56.815743 N<8>[ 33.162598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13832 11:47:56.816005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13834 11:47:56.822523 o KMS driver or no outputs, pipes: 8, outputs: 0
13835 11:47:56.825758 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13836 11:47:56.839526 <14>[ 33.190166] [IGT] kms_vblank: executing
13837 11:47:56.845818 IGT-Version: 1.2<14>[ 33.195206] [IGT] kms_vblank: exiting, ret=77
13838 11:47:56.849603 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13839 11:47:56.859025 Opened device: /<8>[ 33.206097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13840 11:47:56.859162 dev/dri/card0
13841 11:47:56.859443 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13843 11:47:56.862625 No KMS driver or no outputs, pipes: 8, outputs: 0
13844 11:47:56.869074 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13845 11:47:56.880067 <14>[ 33.230421] [IGT] kms_vblank: executing
13846 11:47:56.886593 IGT-Version: 1.2<14>[ 33.235490] [IGT] kms_vblank: exiting, ret=77
13847 11:47:56.889804 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13848 11:47:56.899754 Opened device: /<8>[ 33.246283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13849 11:47:56.899867 dev/dri/card0
13850 11:47:56.900138 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13852 11:47:56.903218 No KMS driver or no outputs, pipes: 8, outputs: 0
13853 11:47:56.909450 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13854 11:47:56.921426 <14>[ 33.271862] [IGT] kms_vblank: executing
13855 11:47:56.927582 IGT-Version: 1.2<14>[ 33.276867] [IGT] kms_vblank: exiting, ret=77
13856 11:47:56.930938 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13857 11:47:56.934839 Opened device: /dev/dri/card0
13858 11:47:56.940908 N<8>[ 33.288426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13859 11:47:56.941160 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13861 11:47:56.944101 o KMS driver or no outputs, pipes: 8, outputs: 0
13862 11:47:56.950587 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13863 11:47:56.963798 <14>[ 33.314079] [IGT] kms_vblank: executing
13864 11:47:56.970048 IGT-Version: 1.2<14>[ 33.319146] [IGT] kms_vblank: exiting, ret=77
13865 11:47:56.973533 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13866 11:47:56.983216 Opened device: /<8>[ 33.329965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13867 11:47:56.983310 dev/dri/card0
13868 11:47:56.983558 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13870 11:47:56.986930 No KMS driver or no outputs, pipes: 8, outputs: 0
13871 11:47:56.993210 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13872 11:47:57.004998 <14>[ 33.355702] [IGT] kms_vblank: executing
13873 11:47:57.011473 IGT-Version: 1.2<14>[ 33.360732] [IGT] kms_vblank: exiting, ret=77
13874 11:47:57.015092 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13875 11:47:57.018511 Opened device: /dev/dri/card0
13876 11:47:57.025087 N<8>[ 33.372139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13877 11:47:57.025347 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13879 11:47:57.028102 o KMS driver or no outputs, pipes: 8, outputs: 0
13880 11:47:57.034375 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13881 11:47:57.047107 <14>[ 33.397586] [IGT] kms_vblank: executing
13882 11:47:57.053352 IGT-Version: 1.2<14>[ 33.402624] [IGT] kms_vblank: exiting, ret=77
13883 11:47:57.056514 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13884 11:47:57.060358 Opened device: /dev/dri/card0
13885 11:47:57.066717 N<8>[ 33.413631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13886 11:47:57.067019 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13888 11:47:57.073563 o KMS driver or no outputs, pipes: 8, outputs: 0
13889 11:47:57.076486 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13890 11:47:57.089416 <14>[ 33.440129] [IGT] kms_vblank: executing
13891 11:47:57.096341 IGT-Version: 1.2<14>[ 33.445173] [IGT] kms_vblank: exiting, ret=77
13892 11:47:57.099467 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13893 11:47:57.102597 Opened device: /dev/dri/card0
13894 11:47:57.109260 N<8>[ 33.456227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13895 11:47:57.109517 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13897 11:47:57.115991 o KMS driver or no outputs, pipes: 8, outputs: 0
13898 11:47:57.119076 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13899 11:47:57.132932 <14>[ 33.483372] [IGT] kms_vblank: executing
13900 11:47:57.139337 IGT-Version: 1.2<14>[ 33.488744] [IGT] kms_vblank: exiting, ret=77
13901 11:47:57.142398 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13902 11:47:57.146107 Opened device: /dev/dri/card0
13903 11:47:57.152425 N<8>[ 33.499810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13904 11:47:57.152689 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13906 11:47:57.159001 o KMS driver or no outputs, pipes: 8, outputs: 0
13907 11:47:57.162246 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13908 11:47:57.175997 <14>[ 33.526525] [IGT] kms_vblank: executing
13909 11:47:57.182663 IGT-Version: 1.2<14>[ 33.531772] [IGT] kms_vblank: exiting, ret=77
13910 11:47:57.185658 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13911 11:47:57.195774 Opened device: /<8>[ 33.542451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13912 11:47:57.195946 dev/dri/card0
13913 11:47:57.196235 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13915 11:47:57.202271 No KMS driver or no outputs, pipes: 8, outputs: 0
13916 11:47:57.205642 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13917 11:47:57.217271 <14>[ 33.568045] [IGT] kms_vblank: executing
13918 11:47:57.223960 IGT-Version: 1.2<14>[ 33.573158] [IGT] kms_vblank: exiting, ret=77
13919 11:47:57.227492 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13920 11:47:57.230515 Opened device: /dev/dri/card0
13921 11:47:57.237221 N<8>[ 33.584231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13922 11:47:57.237524 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13924 11:47:57.243549 o KMS driver or no outputs, pipes: 8, outputs: 0
13925 11:47:57.246913 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13926 11:47:57.261658 <14>[ 33.612060] [IGT] kms_vblank: executing
13927 11:47:57.268079 IGT-Version: 1.2<14>[ 33.617344] [IGT] kms_vblank: exiting, ret=77
13928 11:47:57.271244 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13929 11:47:57.274389 Opened device: /dev/dri/card0
13930 11:47:57.281299 N<8>[ 33.628454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13931 11:47:57.281585 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13933 11:47:57.287522 o KMS driver or no outputs, pipes: 8, outputs: 0
13934 11:47:57.291265 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13935 11:47:57.304608 <14>[ 33.655485] [IGT] kms_vblank: executing
13936 11:47:57.311485 IGT-Version: 1.2<14>[ 33.660553] [IGT] kms_vblank: exiting, ret=77
13937 11:47:57.314379 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13938 11:47:57.318057 Opened device: /dev/dri/card0
13939 11:47:57.324751 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13941 11:47:57.327471 N<8>[ 33.671661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13942 11:47:57.331056 o KMS driver or no outputs, pipes: 8, outputs: 0
13943 11:47:57.337593 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13944 11:47:57.348803 <14>[ 33.699122] [IGT] kms_vblank: executing
13945 11:47:57.355025 IGT-Version: 1.2<14>[ 33.704169] [IGT] kms_vblank: exiting, ret=77
13946 11:47:57.358190 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13947 11:47:57.361851 Opened device: /dev/dri/card0
13948 11:47:57.368227 N<8>[ 33.715179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13949 11:47:57.368563 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13951 11:47:57.375244 o KMS driver or no outputs, pipes: 8, outputs: 0
13952 11:47:57.378438 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13953 11:47:57.392240 <14>[ 33.742807] [IGT] kms_vblank: executing
13954 11:47:57.398446 IGT-Version: 1.2<14>[ 33.748147] [IGT] kms_vblank: exiting, ret=77
13955 11:47:57.402259 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13956 11:47:57.405350 Opened device: /dev/dri/card0
13957 11:47:57.411627 N<8>[ 33.759363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13958 11:47:57.411943 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13960 11:47:57.418732 o KMS driver or no outputs, pipes: 8, outputs: 0
13961 11:47:57.421642 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13962 11:47:57.436052 <14>[ 33.787027] [IGT] kms_vblank: executing
13963 11:47:57.443052 IGT-Version: 1.2<14>[ 33.792617] [IGT] kms_vblank: exiting, ret=77
13964 11:47:57.445939 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13965 11:47:57.449641 Opened device: /dev/dri/card0
13966 11:47:57.459152 N<8>[ 33.803970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13967 11:47:57.459484 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13969 11:47:57.463049 o KMS driver or no outputs, pipes: 8, outputs: 0
13970 11:47:57.469243 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13971 11:47:57.480248 <14>[ 33.831219] [IGT] kms_vblank: executing
13972 11:47:57.487260 IGT-Version: 1.2<14>[ 33.836363] [IGT] kms_vblank: exiting, ret=77
13973 11:47:57.490473 7.1-g2dd77d6 (aarch64) (Linux: 6.1.31 aarch64)
13974 11:47:57.493611 Opened device: /dev/dri/card0
13975 11:47:57.500442 N<8>[ 33.847396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13976 11:47:57.500743 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13978 11:47:57.506981 Received signal: <TESTSET> STOP
13979 11:47:57.507083 Closing test_set kms_vblank
13980 11:47:57.510495 o KMS driver or no outputs, pipe<8>[ 33.859148] <LAVA_SIGNAL_TESTSET STOP>
13981 11:47:57.516499 s: 8, outputs: 0<8>[ 33.865307] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 10742256_1.5.2.3.1>
13982 11:47:57.516624
13983 11:47:57.516896 Received signal: <ENDRUN> 0_igt-kms-mediatek 10742256_1.5.2.3.1
13984 11:47:57.517014 Ending use of test pattern.
13985 11:47:57.517109 Ending test lava.0_igt-kms-mediatek (10742256_1.5.2.3.1), duration 13.61
13987 11:47:57.523444 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13988 11:47:57.523548 + set +x
13989 11:47:57.526338 <LAVA_TEST_RUNNER EXIT>
13990 11:47:57.526626 ok: lava_test_shell seems to have completed
13991 11:47:57.532633 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13992 11:47:57.532905 end: 3.1 lava-test-shell (duration 00:00:14) [common]
13993 11:47:57.533000 end: 3 lava-test-retry (duration 00:00:14) [common]
13994 11:47:57.533108 start: 4 finalize (timeout 00:06:20) [common]
13995 11:47:57.533204 start: 4.1 power-off (timeout 00:00:30) [common]
13996 11:47:57.533369 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
13997 11:47:57.609489 >> Command sent successfully.
13998 11:47:57.611907 Returned 0 in 0 seconds
13999 11:47:57.712312 end: 4.1 power-off (duration 00:00:00) [common]
14001 11:47:57.712666 start: 4.2 read-feedback (timeout 00:06:20) [common]
14002 11:47:57.712951 Listened to connection for namespace 'common' for up to 1s
14003 11:47:58.713873 Finalising connection for namespace 'common'
14004 11:47:58.714083 Disconnecting from shell: Finalise
14005 11:47:58.714166 / #
14006 11:47:58.814493 end: 4.2 read-feedback (duration 00:00:01) [common]
14007 11:47:58.814672 end: 4 finalize (duration 00:00:01) [common]
14008 11:47:58.814790 Cleaning after the job
14009 11:47:58.814938 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/ramdisk
14010 11:47:58.821598 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/kernel
14011 11:47:58.828101 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/dtb
14012 11:47:58.828289 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742256/tftp-deploy-35vbjk6z/modules
14013 11:47:58.834083 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742256
14014 11:47:58.936457 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742256
14015 11:47:58.936673 Job finished correctly