Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 34
- Errors: 0
1 11:39:49.263300 lava-dispatcher, installed at version: 2023.05.1
2 11:39:49.263516 start: 0 validate
3 11:39:49.263651 Start time: 2023-06-15 11:39:49.263644+00:00 (UTC)
4 11:39:49.263788 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:39:49.263918 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 11:39:49.524425 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:39:49.524613 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:40:21.674740 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:40:21.675478 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:40:21.939454 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:40:21.940162 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:40:22.454063 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:40:22.454753 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:40:24.971284 validate duration: 35.71
16 11:40:24.971562 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:40:24.971657 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:40:24.971744 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:40:24.971867 Not decompressing ramdisk as can be used compressed.
20 11:40:24.971953 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230609.0/arm64/initrd.cpio.gz
21 11:40:24.972016 saving as /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/ramdisk/initrd.cpio.gz
22 11:40:24.972078 total size: 5625704 (5MB)
23 11:40:25.238848 progress 0% (0MB)
24 11:40:25.241475 progress 5% (0MB)
25 11:40:25.244123 progress 10% (0MB)
26 11:40:25.246434 progress 15% (0MB)
27 11:40:25.249006 progress 20% (1MB)
28 11:40:25.251269 progress 25% (1MB)
29 11:40:25.253816 progress 30% (1MB)
30 11:40:25.256322 progress 35% (1MB)
31 11:40:25.258564 progress 40% (2MB)
32 11:40:25.261056 progress 45% (2MB)
33 11:40:25.263284 progress 50% (2MB)
34 11:40:25.265775 progress 55% (2MB)
35 11:40:25.268269 progress 60% (3MB)
36 11:40:25.270504 progress 65% (3MB)
37 11:40:25.273019 progress 70% (3MB)
38 11:40:25.275223 progress 75% (4MB)
39 11:40:25.277718 progress 80% (4MB)
40 11:40:25.279943 progress 85% (4MB)
41 11:40:25.282427 progress 90% (4MB)
42 11:40:25.284870 progress 95% (5MB)
43 11:40:25.286265 progress 100% (5MB)
44 11:40:25.286463 5MB downloaded in 0.31s (17.07MB/s)
45 11:40:25.286617 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:40:25.286852 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:40:25.286937 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:40:25.287019 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:40:25.287155 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:40:25.287225 saving as /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/kernel/Image
52 11:40:25.287285 total size: 47581696 (45MB)
53 11:40:25.287344 No compression specified
54 11:40:25.288474 progress 0% (0MB)
55 11:40:25.300608 progress 5% (2MB)
56 11:40:25.312449 progress 10% (4MB)
57 11:40:25.324352 progress 15% (6MB)
58 11:40:25.336490 progress 20% (9MB)
59 11:40:25.348774 progress 25% (11MB)
60 11:40:25.360677 progress 30% (13MB)
61 11:40:25.372617 progress 35% (15MB)
62 11:40:25.384260 progress 40% (18MB)
63 11:40:25.396118 progress 45% (20MB)
64 11:40:25.408102 progress 50% (22MB)
65 11:40:25.419786 progress 55% (24MB)
66 11:40:25.431912 progress 60% (27MB)
67 11:40:25.443723 progress 65% (29MB)
68 11:40:25.455671 progress 70% (31MB)
69 11:40:25.467556 progress 75% (34MB)
70 11:40:25.479178 progress 80% (36MB)
71 11:40:25.491027 progress 85% (38MB)
72 11:40:25.502826 progress 90% (40MB)
73 11:40:25.514517 progress 95% (43MB)
74 11:40:25.526231 progress 100% (45MB)
75 11:40:25.526359 45MB downloaded in 0.24s (189.81MB/s)
76 11:40:25.526504 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:40:25.526740 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:40:25.526831 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:40:25.526950 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:40:25.527090 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:40:25.527159 saving as /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/dtb/mt8192-asurada-spherion-r0.dtb
83 11:40:25.527221 total size: 46924 (0MB)
84 11:40:25.527280 No compression specified
85 11:40:25.528373 progress 69% (0MB)
86 11:40:25.528683 progress 100% (0MB)
87 11:40:25.528839 0MB downloaded in 0.00s (27.69MB/s)
88 11:40:25.528975 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:40:25.529198 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:40:25.529280 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:40:25.529360 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:40:25.529467 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230609.0/arm64/full.rootfs.tar.xz
94 11:40:25.529534 saving as /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/nfsrootfs/full.rootfs.tar
95 11:40:25.529594 total size: 195135828 (186MB)
96 11:40:25.529652 Using unxz to decompress xz
97 11:40:25.533234 progress 0% (0MB)
98 11:40:26.076395 progress 5% (9MB)
99 11:40:26.567008 progress 10% (18MB)
100 11:40:27.149928 progress 15% (27MB)
101 11:40:27.434436 progress 20% (37MB)
102 11:40:27.904741 progress 25% (46MB)
103 11:40:28.473070 progress 30% (55MB)
104 11:40:29.038530 progress 35% (65MB)
105 11:40:29.615446 progress 40% (74MB)
106 11:40:30.191178 progress 45% (83MB)
107 11:40:30.828883 progress 50% (93MB)
108 11:40:31.446392 progress 55% (102MB)
109 11:40:32.408335 progress 60% (111MB)
110 11:40:32.792884 progress 65% (120MB)
111 11:40:32.875631 progress 70% (130MB)
112 11:40:33.032148 progress 75% (139MB)
113 11:40:33.110966 progress 80% (148MB)
114 11:40:33.157476 progress 85% (158MB)
115 11:40:33.249763 progress 90% (167MB)
116 11:40:33.619989 progress 95% (176MB)
117 11:40:34.225719 progress 100% (186MB)
118 11:40:34.230912 186MB downloaded in 8.70s (21.39MB/s)
119 11:40:34.231514 end: 1.4.1 http-download (duration 00:00:09) [common]
121 11:40:34.232030 end: 1.4 download-retry (duration 00:00:09) [common]
122 11:40:34.232192 start: 1.5 download-retry (timeout 00:09:51) [common]
123 11:40:34.232350 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 11:40:34.232584 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:40:34.232716 saving as /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/modules/modules.tar
126 11:40:34.232837 total size: 8555256 (8MB)
127 11:40:34.232962 Using unxz to decompress xz
128 11:40:34.494000 progress 0% (0MB)
129 11:40:34.516611 progress 5% (0MB)
130 11:40:34.541630 progress 10% (0MB)
131 11:40:34.566457 progress 15% (1MB)
132 11:40:34.591733 progress 20% (1MB)
133 11:40:34.618401 progress 25% (2MB)
134 11:40:34.641816 progress 30% (2MB)
135 11:40:34.669855 progress 35% (2MB)
136 11:40:34.694744 progress 40% (3MB)
137 11:40:34.718676 progress 45% (3MB)
138 11:40:34.745864 progress 50% (4MB)
139 11:40:34.772592 progress 55% (4MB)
140 11:40:34.798073 progress 60% (4MB)
141 11:40:34.823595 progress 65% (5MB)
142 11:40:34.848750 progress 70% (5MB)
143 11:40:34.873235 progress 75% (6MB)
144 11:40:34.896815 progress 80% (6MB)
145 11:40:34.921059 progress 85% (6MB)
146 11:40:34.950169 progress 90% (7MB)
147 11:40:34.977660 progress 95% (7MB)
148 11:40:35.002735 progress 100% (8MB)
149 11:40:35.007017 8MB downloaded in 0.77s (10.54MB/s)
150 11:40:35.007285 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:40:35.007569 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:40:35.007663 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:40:35.007756 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:40:38.330560 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10742214/extract-nfsrootfs-9pw3phm6
156 11:40:38.330776 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:40:38.330873 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 11:40:38.331044 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8
159 11:40:38.331175 makedir: /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin
160 11:40:38.331274 makedir: /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/tests
161 11:40:38.331369 makedir: /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/results
162 11:40:38.331469 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-add-keys
163 11:40:38.331611 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-add-sources
164 11:40:38.331733 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-background-process-start
165 11:40:38.331852 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-background-process-stop
166 11:40:38.331970 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-common-functions
167 11:40:38.332085 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-echo-ipv4
168 11:40:38.332201 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-install-packages
169 11:40:38.332314 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-installed-packages
170 11:40:38.332431 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-os-build
171 11:40:38.332552 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-probe-channel
172 11:40:38.332667 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-probe-ip
173 11:40:38.332783 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-target-ip
174 11:40:38.332897 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-target-mac
175 11:40:38.333011 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-target-storage
176 11:40:38.333126 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-test-case
177 11:40:38.333243 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-test-event
178 11:40:38.333357 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-test-feedback
179 11:40:38.333472 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-test-raise
180 11:40:38.333586 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-test-reference
181 11:40:38.333705 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-test-runner
182 11:40:38.333819 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-test-set
183 11:40:38.333932 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-test-shell
184 11:40:38.334048 Updating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-add-keys (debian)
185 11:40:38.334196 Updating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-add-sources (debian)
186 11:40:38.334338 Updating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-install-packages (debian)
187 11:40:38.334471 Updating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-installed-packages (debian)
188 11:40:38.334603 Updating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/bin/lava-os-build (debian)
189 11:40:38.334719 Creating /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/environment
190 11:40:38.334816 LAVA metadata
191 11:40:38.334884 - LAVA_JOB_ID=10742214
192 11:40:38.334945 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:40:38.335042 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 11:40:38.335106 skipped lava-vland-overlay
195 11:40:38.335179 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:40:38.335256 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 11:40:38.335314 skipped lava-multinode-overlay
198 11:40:38.335382 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:40:38.335457 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 11:40:38.335526 Loading test definitions
201 11:40:38.335614 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 11:40:38.335682 Using /lava-10742214 at stage 0
203 11:40:38.335950 uuid=10742214_1.6.2.3.1 testdef=None
204 11:40:38.336035 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:40:38.336116 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 11:40:38.336799 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:40:38.337024 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 11:40:38.337564 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:40:38.337789 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 11:40:38.338304 runner path: /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/0/tests/0_timesync-off test_uuid 10742214_1.6.2.3.1
213 11:40:38.338451 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:40:38.338671 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 11:40:38.338741 Using /lava-10742214 at stage 0
217 11:40:38.338834 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:40:38.338911 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/0/tests/1_kselftest-alsa'
219 11:40:43.582764 Running '/usr/bin/git checkout kernelci.org
220 11:40:43.727299 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:40:43.728031 uuid=10742214_1.6.2.3.5 testdef=None
222 11:40:43.728193 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 11:40:43.728439 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 11:40:43.729215 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:40:43.729447 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 11:40:43.730454 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:40:43.730690 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 11:40:43.731602 runner path: /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/0/tests/1_kselftest-alsa test_uuid 10742214_1.6.2.3.5
232 11:40:43.731694 BOARD='mt8192-asurada-spherion-r0'
233 11:40:43.731759 BRANCH='cip'
234 11:40:43.731818 SKIPFILE='/dev/null'
235 11:40:43.731876 SKIP_INSTALL='True'
236 11:40:43.731931 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:40:43.731988 TST_CASENAME=''
238 11:40:43.732041 TST_CMDFILES='alsa'
239 11:40:43.732181 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:40:43.732385 Creating lava-test-runner.conf files
242 11:40:43.732449 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742214/lava-overlay-npyw53m8/lava-10742214/0 for stage 0
243 11:40:43.732594 - 0_timesync-off
244 11:40:43.732678 - 1_kselftest-alsa
245 11:40:43.732771 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 11:40:43.732857 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 11:40:51.502877 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:40:51.503033 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 11:40:51.503162 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:40:51.503266 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 11:40:51.503364 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 11:40:51.667514 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:40:51.667882 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 11:40:51.667998 extracting modules file /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742214/extract-nfsrootfs-9pw3phm6
255 11:40:51.873941 extracting modules file /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742214/extract-overlay-ramdisk-k8780vhq/ramdisk
256 11:40:52.084705 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:40:52.084876 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 11:40:52.084972 [common] Applying overlay to NFS
259 11:40:52.085040 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742214/compress-overlay-vv_0oeqy/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742214/extract-nfsrootfs-9pw3phm6
260 11:40:52.983519 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:40:52.983686 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 11:40:52.983785 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:40:52.983879 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 11:40:52.983961 Building ramdisk /var/lib/lava/dispatcher/tmp/10742214/extract-overlay-ramdisk-k8780vhq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742214/extract-overlay-ramdisk-k8780vhq/ramdisk
265 11:40:53.277329 >> 128929 blocks
266 11:40:55.264061 rename /var/lib/lava/dispatcher/tmp/10742214/extract-overlay-ramdisk-k8780vhq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/ramdisk/ramdisk.cpio.gz
267 11:40:55.264547 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:40:55.264707 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 11:40:55.264819 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 11:40:55.264944 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/kernel/Image'
271 11:41:07.783614 Returned 0 in 12 seconds
272 11:41:07.884220 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/kernel/image.itb
273 11:41:08.218226 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:41:08.218640 output: Created: Thu Jun 15 12:41:08 2023
275 11:41:08.218766 output: Image 0 (kernel-1)
276 11:41:08.218865 output: Description:
277 11:41:08.218958 output: Created: Thu Jun 15 12:41:08 2023
278 11:41:08.219076 output: Type: Kernel Image
279 11:41:08.219171 output: Compression: lzma compressed
280 11:41:08.219280 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
281 11:41:08.219376 output: Architecture: AArch64
282 11:41:08.219474 output: OS: Linux
283 11:41:08.219562 output: Load Address: 0x00000000
284 11:41:08.219666 output: Entry Point: 0x00000000
285 11:41:08.219745 output: Hash algo: crc32
286 11:41:08.219803 output: Hash value: cd22d0e5
287 11:41:08.219869 output: Image 1 (fdt-1)
288 11:41:08.219929 output: Description: mt8192-asurada-spherion-r0
289 11:41:08.220013 output: Created: Thu Jun 15 12:41:08 2023
290 11:41:08.220113 output: Type: Flat Device Tree
291 11:41:08.220196 output: Compression: uncompressed
292 11:41:08.220290 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 11:41:08.220373 output: Architecture: AArch64
294 11:41:08.220479 output: Hash algo: crc32
295 11:41:08.220588 output: Hash value: 1df858fa
296 11:41:08.220643 output: Image 2 (ramdisk-1)
297 11:41:08.220724 output: Description: unavailable
298 11:41:08.220801 output: Created: Thu Jun 15 12:41:08 2023
299 11:41:08.220885 output: Type: RAMDisk Image
300 11:41:08.220983 output: Compression: Unknown Compression
301 11:41:08.221043 output: Data Size: 18608583 Bytes = 18172.44 KiB = 17.75 MiB
302 11:41:08.221134 output: Architecture: AArch64
303 11:41:08.221238 output: OS: Linux
304 11:41:08.221328 output: Load Address: unavailable
305 11:41:08.221413 output: Entry Point: unavailable
306 11:41:08.221502 output: Hash algo: crc32
307 11:41:08.221607 output: Hash value: 2798172f
308 11:41:08.221691 output: Default Configuration: 'conf-1'
309 11:41:08.221773 output: Configuration 0 (conf-1)
310 11:41:08.221883 output: Description: mt8192-asurada-spherion-r0
311 11:41:08.221966 output: Kernel: kernel-1
312 11:41:08.222057 output: Init Ramdisk: ramdisk-1
313 11:41:08.222163 output: FDT: fdt-1
314 11:41:08.222247 output: Loadables: kernel-1
315 11:41:08.222337 output:
316 11:41:08.222585 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:41:08.222717 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:41:08.222855 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 11:41:08.223004 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 11:41:08.223110 No LXC device requested
321 11:41:08.223230 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:41:08.223368 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 11:41:08.223484 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:41:08.223581 Checking files for TFTP limit of 4294967296 bytes.
325 11:41:08.224317 end: 1 tftp-deploy (duration 00:00:43) [common]
326 11:41:08.224461 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:41:08.224618 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:41:08.224767 substitutions:
329 11:41:08.224836 - {DTB}: 10742214/tftp-deploy-1tj29zfq/dtb/mt8192-asurada-spherion-r0.dtb
330 11:41:08.224914 - {INITRD}: 10742214/tftp-deploy-1tj29zfq/ramdisk/ramdisk.cpio.gz
331 11:41:08.224983 - {KERNEL}: 10742214/tftp-deploy-1tj29zfq/kernel/Image
332 11:41:08.225062 - {LAVA_MAC}: None
333 11:41:08.225135 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10742214/extract-nfsrootfs-9pw3phm6
334 11:41:08.225209 - {NFS_SERVER_IP}: 192.168.201.1
335 11:41:08.225269 - {PRESEED_CONFIG}: None
336 11:41:08.225325 - {PRESEED_LOCAL}: None
337 11:41:08.225379 - {RAMDISK}: 10742214/tftp-deploy-1tj29zfq/ramdisk/ramdisk.cpio.gz
338 11:41:08.225459 - {ROOT_PART}: None
339 11:41:08.225549 - {ROOT}: None
340 11:41:08.225640 - {SERVER_IP}: 192.168.201.1
341 11:41:08.225724 - {TEE}: None
342 11:41:08.225918 Parsed boot commands:
343 11:41:08.226020 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:41:08.226254 Parsed boot commands: tftpboot 192.168.201.1 10742214/tftp-deploy-1tj29zfq/kernel/image.itb 10742214/tftp-deploy-1tj29zfq/kernel/cmdline
345 11:41:08.226401 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:41:08.226525 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:41:08.226653 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:41:08.226795 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:41:08.226899 Not connected, no need to disconnect.
350 11:41:08.227066 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:41:08.227181 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:41:08.227288 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 11:41:08.230822 Setting prompt string to ['lava-test: # ']
354 11:41:08.231211 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:41:08.231372 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:41:08.231511 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:41:08.231626 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:41:08.231829 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 11:41:13.363499 >> Command sent successfully.
360 11:41:13.365786 Returned 0 in 5 seconds
361 11:41:13.466179 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:41:13.466735 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:41:13.466855 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:41:13.466963 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:41:13.467038 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:41:13.467118 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:41:13.467407 [Enter `^Ec?' for help]
369 11:41:13.640676
370 11:41:13.640845
371 11:41:13.640933 F0: 102B 0000
372 11:41:13.641002
373 11:41:13.641064 F3: 1001 0000 [0200]
374 11:41:13.641155
375 11:41:13.644575 F3: 1001 0000
376 11:41:13.644666
377 11:41:13.644734 F7: 102D 0000
378 11:41:13.644798
379 11:41:13.644858 F1: 0000 0000
380 11:41:13.644918
381 11:41:13.648498 V0: 0000 0000 [0001]
382 11:41:13.648595
383 11:41:13.648693 00: 0007 8000
384 11:41:13.648765
385 11:41:13.651846 01: 0000 0000
386 11:41:13.651948
387 11:41:13.652040 BP: 0C00 0209 [0000]
388 11:41:13.652130
389 11:41:13.655536 G0: 1182 0000
390 11:41:13.655624
391 11:41:13.655693 EC: 0000 0021 [4000]
392 11:41:13.655758
393 11:41:13.659467 S7: 0000 0000 [0000]
394 11:41:13.659545
395 11:41:13.659610 CC: 0000 0000 [0001]
396 11:41:13.659674
397 11:41:13.662305 T0: 0000 0040 [010F]
398 11:41:13.662388
399 11:41:13.662474 Jump to BL
400 11:41:13.662570
401 11:41:13.687357
402 11:41:13.687462
403 11:41:13.687534
404 11:41:13.694335 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:41:13.697578 ARM64: Exception handlers installed.
406 11:41:13.701419 ARM64: Testing exception
407 11:41:13.704974 ARM64: Done test exception
408 11:41:13.712640 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:41:13.723154 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:41:13.730038 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:41:13.741101 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:41:13.744554 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:41:13.755310 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:41:13.765314 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:41:13.772011 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:41:13.790327 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:41:13.793757 WDT: Last reset was cold boot
418 11:41:13.797228 SPI1(PAD0) initialized at 2873684 Hz
419 11:41:13.800564 SPI5(PAD0) initialized at 992727 Hz
420 11:41:13.804016 VBOOT: Loading verstage.
421 11:41:13.810125 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:41:13.813841 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:41:13.817022 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:41:13.820293 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:41:13.827595 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:41:13.834000 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:41:13.845305 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 11:41:13.845395
429 11:41:13.845463
430 11:41:13.855322 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:41:13.858686 ARM64: Exception handlers installed.
432 11:41:13.861865 ARM64: Testing exception
433 11:41:13.861950 ARM64: Done test exception
434 11:41:13.868309 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:41:13.871960 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:41:13.886014 Probing TPM: . done!
437 11:41:13.886103 TPM ready after 0 ms
438 11:41:13.893440 Connected to device vid:did:rid of 1ae0:0028:00
439 11:41:13.903371 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 11:41:13.941961 Initialized TPM device CR50 revision 0
441 11:41:13.953310 tlcl_send_startup: Startup return code is 0
442 11:41:13.953426 TPM: setup succeeded
443 11:41:13.965436 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:41:13.974102 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:41:13.984870 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:41:13.994194 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:41:13.997743 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:41:14.000933 in-header: 03 07 00 00 08 00 00 00
449 11:41:14.004307 in-data: aa e4 47 04 13 02 00 00
450 11:41:14.007699 Chrome EC: UHEPI supported
451 11:41:14.014575 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:41:14.018127 in-header: 03 ad 00 00 08 00 00 00
453 11:41:14.021528 in-data: 00 20 20 08 00 00 00 00
454 11:41:14.021634 Phase 1
455 11:41:14.024400 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:41:14.031567 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:41:14.037591 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:41:14.041029 Recovery requested (1009000e)
459 11:41:14.044724 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:41:14.053042 tlcl_extend: response is 0
461 11:41:14.061335 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:41:14.066570 tlcl_extend: response is 0
463 11:41:14.072998 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:41:14.094282 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:41:14.101016 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:41:14.101120
467 11:41:14.101205
468 11:41:14.111186 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:41:14.114436 ARM64: Exception handlers installed.
470 11:41:14.114546 ARM64: Testing exception
471 11:41:14.117724 ARM64: Done test exception
472 11:41:14.139670 pmic_efuse_setting: Set efuses in 11 msecs
473 11:41:14.142952 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:41:14.149606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:41:14.153576 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:41:14.156848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:41:14.162991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:41:14.166647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:41:14.173404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:41:14.176816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:41:14.183468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:41:14.186617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:41:14.189898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:41:14.196353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:41:14.200267 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:41:14.206440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:41:14.212857 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:41:14.217000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:41:14.223190 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:41:14.229747 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:41:14.233095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:41:14.239507 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:41:14.246375 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:41:14.249668 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:41:14.256630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:41:14.264018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:41:14.268047 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:41:14.274414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:41:14.277316 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:41:14.284555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:41:14.287772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:41:14.295030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:41:14.298261 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:41:14.301816 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:41:14.308049 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:41:14.311542 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:41:14.318224 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:41:14.321459 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:41:14.328308 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:41:14.334861 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:41:14.338500 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:41:14.341932 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:41:14.348724 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:41:14.352832 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:41:14.356199 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:41:14.359205 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:41:14.365532 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:41:14.368875 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:41:14.372183 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:41:14.379005 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:41:14.382281 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:41:14.385736 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:41:14.388520 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:41:14.395564 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:41:14.402081 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:41:14.411708 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:41:14.415284 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:41:14.421963 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:41:14.432022 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:41:14.435410 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:41:14.441880 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:41:14.444953 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:41:14.452031 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x23
534 11:41:14.458418 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:41:14.461801 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 11:41:14.468051 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:41:14.476869 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 11:41:14.485942 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 11:41:14.495491 [RTC]rtc_get_frequency_meter,154: input=11, output=771
540 11:41:14.504619 [RTC]rtc_get_frequency_meter,154: input=13, output=802
541 11:41:14.514297 [RTC]rtc_get_frequency_meter,154: input=12, output=786
542 11:41:14.523918 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 11:41:14.533431 [RTC]rtc_get_frequency_meter,154: input=13, output=802
544 11:41:14.536556 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 11:41:14.543963 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 11:41:14.547142 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:41:14.550325 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:41:14.557066 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:41:14.560311 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:41:14.563990 ADC[4]: Raw value=906357 ID=7
551 11:41:14.564076 ADC[3]: Raw value=213282 ID=1
552 11:41:14.567379 RAM Code: 0x71
553 11:41:14.570659 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:41:14.577391 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:41:14.583637 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:41:14.590464 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:41:14.593526 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:41:14.596847 in-header: 03 07 00 00 08 00 00 00
559 11:41:14.600228 in-data: aa e4 47 04 13 02 00 00
560 11:41:14.603456 Chrome EC: UHEPI supported
561 11:41:14.610051 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:41:14.613628 in-header: 03 dd 00 00 08 00 00 00
563 11:41:14.616634 in-data: 90 20 60 08 00 00 00 00
564 11:41:14.620189 MRC: failed to locate region type 0.
565 11:41:14.626719 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:41:14.630570 DRAM-K: Running full calibration
567 11:41:14.636756 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:41:14.636845 header.status = 0x0
569 11:41:14.639883 header.version = 0x6 (expected: 0x6)
570 11:41:14.643155 header.size = 0xd00 (expected: 0xd00)
571 11:41:14.646755 header.flags = 0x0
572 11:41:14.653538 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:41:14.670190 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 11:41:14.676498 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:41:14.679972 dram_init: ddr_geometry: 2
576 11:41:14.683581 [EMI] MDL number = 2
577 11:41:14.683675 [EMI] Get MDL freq = 0
578 11:41:14.686652 dram_init: ddr_type: 0
579 11:41:14.686734 is_discrete_lpddr4: 1
580 11:41:14.690101 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:41:14.690210
582 11:41:14.690317
583 11:41:14.693292 [Bian_co] ETT version 0.0.0.1
584 11:41:14.699826 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:41:14.699912
586 11:41:14.703184 dramc_set_vcore_voltage set vcore to 650000
587 11:41:14.706311 Read voltage for 800, 4
588 11:41:14.706395 Vio18 = 0
589 11:41:14.706503 Vcore = 650000
590 11:41:14.709665 Vdram = 0
591 11:41:14.709772 Vddq = 0
592 11:41:14.709876 Vmddr = 0
593 11:41:14.712932 dram_init: config_dvfs: 1
594 11:41:14.716384 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:41:14.723285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:41:14.726536 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 11:41:14.729775 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 11:41:14.733034 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 11:41:14.739608 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 11:41:14.739690 MEM_TYPE=3, freq_sel=18
601 11:41:14.743161 sv_algorithm_assistance_LP4_1600
602 11:41:14.746320 ============ PULL DRAM RESETB DOWN ============
603 11:41:14.753035 ========== PULL DRAM RESETB DOWN end =========
604 11:41:14.755780 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:41:14.759422 ===================================
606 11:41:14.762784 LPDDR4 DRAM CONFIGURATION
607 11:41:14.765830 ===================================
608 11:41:14.765939 EX_ROW_EN[0] = 0x0
609 11:41:14.769211 EX_ROW_EN[1] = 0x0
610 11:41:14.769297 LP4Y_EN = 0x0
611 11:41:14.772428 WORK_FSP = 0x0
612 11:41:14.775623 WL = 0x2
613 11:41:14.775707 RL = 0x2
614 11:41:14.779049 BL = 0x2
615 11:41:14.779155 RPST = 0x0
616 11:41:14.782453 RD_PRE = 0x0
617 11:41:14.782588 WR_PRE = 0x1
618 11:41:14.785868 WR_PST = 0x0
619 11:41:14.785973 DBI_WR = 0x0
620 11:41:14.788854 DBI_RD = 0x0
621 11:41:14.788964 OTF = 0x1
622 11:41:14.792174 ===================================
623 11:41:14.795504 ===================================
624 11:41:14.798799 ANA top config
625 11:41:14.802155 ===================================
626 11:41:14.802261 DLL_ASYNC_EN = 0
627 11:41:14.805507 ALL_SLAVE_EN = 1
628 11:41:14.808993 NEW_RANK_MODE = 1
629 11:41:14.812026 DLL_IDLE_MODE = 1
630 11:41:14.812134 LP45_APHY_COMB_EN = 1
631 11:41:14.815165 TX_ODT_DIS = 1
632 11:41:14.818804 NEW_8X_MODE = 1
633 11:41:14.822024 ===================================
634 11:41:14.825280 ===================================
635 11:41:14.828560 data_rate = 1600
636 11:41:14.831798 CKR = 1
637 11:41:14.835320 DQ_P2S_RATIO = 8
638 11:41:14.838788 ===================================
639 11:41:14.838892 CA_P2S_RATIO = 8
640 11:41:14.841549 DQ_CA_OPEN = 0
641 11:41:14.845025 DQ_SEMI_OPEN = 0
642 11:41:14.848172 CA_SEMI_OPEN = 0
643 11:41:14.851575 CA_FULL_RATE = 0
644 11:41:14.854746 DQ_CKDIV4_EN = 1
645 11:41:14.854851 CA_CKDIV4_EN = 1
646 11:41:14.858517 CA_PREDIV_EN = 0
647 11:41:14.861871 PH8_DLY = 0
648 11:41:14.865242 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:41:14.868290 DQ_AAMCK_DIV = 4
650 11:41:14.871910 CA_AAMCK_DIV = 4
651 11:41:14.871994 CA_ADMCK_DIV = 4
652 11:41:14.875108 DQ_TRACK_CA_EN = 0
653 11:41:14.878426 CA_PICK = 800
654 11:41:14.881642 CA_MCKIO = 800
655 11:41:14.884926 MCKIO_SEMI = 0
656 11:41:14.887870 PLL_FREQ = 3068
657 11:41:14.891646 DQ_UI_PI_RATIO = 32
658 11:41:14.894885 CA_UI_PI_RATIO = 0
659 11:41:14.898281 ===================================
660 11:41:14.898364 ===================================
661 11:41:14.901427 memory_type:LPDDR4
662 11:41:14.904623 GP_NUM : 10
663 11:41:14.907588 SRAM_EN : 1
664 11:41:14.907673 MD32_EN : 0
665 11:41:14.911473 ===================================
666 11:41:14.914541 [ANA_INIT] >>>>>>>>>>>>>>
667 11:41:14.917791 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:41:14.921209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:41:14.924744 ===================================
670 11:41:14.927679 data_rate = 1600,PCW = 0X7600
671 11:41:14.931193 ===================================
672 11:41:14.934235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:41:14.937596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:41:14.944183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:41:14.947624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:41:14.951021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:41:14.954222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:41:14.957711 [ANA_INIT] flow start
679 11:41:14.961013 [ANA_INIT] PLL >>>>>>>>
680 11:41:14.961115 [ANA_INIT] PLL <<<<<<<<
681 11:41:14.964107 [ANA_INIT] MIDPI >>>>>>>>
682 11:41:14.966910 [ANA_INIT] MIDPI <<<<<<<<
683 11:41:14.970837 [ANA_INIT] DLL >>>>>>>>
684 11:41:14.970951 [ANA_INIT] flow end
685 11:41:14.973678 ============ LP4 DIFF to SE enter ============
686 11:41:14.981259 ============ LP4 DIFF to SE exit ============
687 11:41:14.981347 [ANA_INIT] <<<<<<<<<<<<<
688 11:41:14.984046 [Flow] Enable top DCM control >>>>>
689 11:41:14.987187 [Flow] Enable top DCM control <<<<<
690 11:41:14.990285 Enable DLL master slave shuffle
691 11:41:14.997186 ==============================================================
692 11:41:14.997269 Gating Mode config
693 11:41:15.003384 ==============================================================
694 11:41:15.006753 Config description:
695 11:41:15.016843 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:41:15.023139 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:41:15.026811 SELPH_MODE 0: By rank 1: By Phase
698 11:41:15.033260 ==============================================================
699 11:41:15.036410 GAT_TRACK_EN = 1
700 11:41:15.039760 RX_GATING_MODE = 2
701 11:41:15.039837 RX_GATING_TRACK_MODE = 2
702 11:41:15.043135 SELPH_MODE = 1
703 11:41:15.046560 PICG_EARLY_EN = 1
704 11:41:15.050047 VALID_LAT_VALUE = 1
705 11:41:15.056704 ==============================================================
706 11:41:15.059441 Enter into Gating configuration >>>>
707 11:41:15.062926 Exit from Gating configuration <<<<
708 11:41:15.066411 Enter into DVFS_PRE_config >>>>>
709 11:41:15.076218 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:41:15.079587 Exit from DVFS_PRE_config <<<<<
711 11:41:15.083107 Enter into PICG configuration >>>>
712 11:41:15.086571 Exit from PICG configuration <<<<
713 11:41:15.089721 [RX_INPUT] configuration >>>>>
714 11:41:15.092863 [RX_INPUT] configuration <<<<<
715 11:41:15.096303 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:41:15.103153 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:41:15.106927 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:41:15.114294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:41:15.121444 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:41:15.128510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:41:15.132634 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:41:15.136332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:41:15.139446 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:41:15.143719 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:41:15.146988 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:41:15.150709 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:41:15.154169 ===================================
728 11:41:15.157957 LPDDR4 DRAM CONFIGURATION
729 11:41:15.161322 ===================================
730 11:41:15.161402 EX_ROW_EN[0] = 0x0
731 11:41:15.165058 EX_ROW_EN[1] = 0x0
732 11:41:15.165172 LP4Y_EN = 0x0
733 11:41:15.168547 WORK_FSP = 0x0
734 11:41:15.172007 WL = 0x2
735 11:41:15.172086 RL = 0x2
736 11:41:15.172152 BL = 0x2
737 11:41:15.175361 RPST = 0x0
738 11:41:15.175440 RD_PRE = 0x0
739 11:41:15.179199 WR_PRE = 0x1
740 11:41:15.179278 WR_PST = 0x0
741 11:41:15.182924 DBI_WR = 0x0
742 11:41:15.183036 DBI_RD = 0x0
743 11:41:15.186633 OTF = 0x1
744 11:41:15.190333 ===================================
745 11:41:15.193963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:41:15.197457 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:41:15.200685 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:41:15.204158 ===================================
749 11:41:15.208169 LPDDR4 DRAM CONFIGURATION
750 11:41:15.211361 ===================================
751 11:41:15.211444 EX_ROW_EN[0] = 0x10
752 11:41:15.215202 EX_ROW_EN[1] = 0x0
753 11:41:15.215282 LP4Y_EN = 0x0
754 11:41:15.218979 WORK_FSP = 0x0
755 11:41:15.219059 WL = 0x2
756 11:41:15.222779 RL = 0x2
757 11:41:15.222861 BL = 0x2
758 11:41:15.226166 RPST = 0x0
759 11:41:15.226256 RD_PRE = 0x0
760 11:41:15.230175 WR_PRE = 0x1
761 11:41:15.230253 WR_PST = 0x0
762 11:41:15.233591 DBI_WR = 0x0
763 11:41:15.233669 DBI_RD = 0x0
764 11:41:15.233736 OTF = 0x1
765 11:41:15.236953 ===================================
766 11:41:15.243873 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:41:15.249004 nWR fixed to 40
768 11:41:15.252362 [ModeRegInit_LP4] CH0 RK0
769 11:41:15.252470 [ModeRegInit_LP4] CH0 RK1
770 11:41:15.256427 [ModeRegInit_LP4] CH1 RK0
771 11:41:15.256510 [ModeRegInit_LP4] CH1 RK1
772 11:41:15.259873 match AC timing 13
773 11:41:15.263053 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:41:15.266250 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:41:15.273430 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:41:15.276706 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:41:15.280290 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:41:15.283699 [EMI DOE] emi_dcm 0
779 11:41:15.286735 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:41:15.286809 ==
781 11:41:15.290016 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:41:15.296932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:41:15.297052 ==
784 11:41:15.299939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:41:15.306634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:41:15.315723 [CA 0] Center 37 (7~68) winsize 62
787 11:41:15.319389 [CA 1] Center 37 (6~68) winsize 63
788 11:41:15.322583 [CA 2] Center 34 (4~65) winsize 62
789 11:41:15.325984 [CA 3] Center 34 (4~65) winsize 62
790 11:41:15.329167 [CA 4] Center 33 (3~64) winsize 62
791 11:41:15.332632 [CA 5] Center 33 (3~64) winsize 62
792 11:41:15.332738
793 11:41:15.336212 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:41:15.336318
795 11:41:15.339670 [CATrainingPosCal] consider 1 rank data
796 11:41:15.342791 u2DelayCellTimex100 = 270/100 ps
797 11:41:15.346240 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 11:41:15.349650 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 11:41:15.352965 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:41:15.359689 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:41:15.362564 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:41:15.365694 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:41:15.365807
804 11:41:15.369352 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:41:15.369432
806 11:41:15.372691 [CBTSetCACLKResult] CA Dly = 33
807 11:41:15.372761 CS Dly: 6 (0~37)
808 11:41:15.372823 ==
809 11:41:15.375864 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:41:15.382454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:41:15.382534 ==
812 11:41:15.385662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:41:15.392441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:41:15.402101 [CA 0] Center 37 (6~68) winsize 63
815 11:41:15.405495 [CA 1] Center 37 (7~68) winsize 62
816 11:41:15.408866 [CA 2] Center 34 (4~65) winsize 62
817 11:41:15.412002 [CA 3] Center 34 (4~65) winsize 62
818 11:41:15.415313 [CA 4] Center 33 (3~64) winsize 62
819 11:41:15.418398 [CA 5] Center 33 (2~64) winsize 63
820 11:41:15.418482
821 11:41:15.421976 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:41:15.422101
823 11:41:15.425126 [CATrainingPosCal] consider 2 rank data
824 11:41:15.428705 u2DelayCellTimex100 = 270/100 ps
825 11:41:15.431939 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:41:15.435175 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:41:15.442125 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:41:15.445414 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:41:15.448990 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:41:15.452758 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:41:15.452837
832 11:41:15.456735 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:41:15.456888
834 11:41:15.460036 [CBTSetCACLKResult] CA Dly = 33
835 11:41:15.460116 CS Dly: 6 (0~38)
836 11:41:15.460190
837 11:41:15.463791 ----->DramcWriteLeveling(PI) begin...
838 11:41:15.463951 ==
839 11:41:15.467745 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:41:15.470723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:41:15.470885 ==
842 11:41:15.474238 Write leveling (Byte 0): 31 => 31
843 11:41:15.477576 Write leveling (Byte 1): 31 => 31
844 11:41:15.480857 DramcWriteLeveling(PI) end<-----
845 11:41:15.480941
846 11:41:15.481009 ==
847 11:41:15.484213 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:41:15.487352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:41:15.487436 ==
850 11:41:15.490766 [Gating] SW mode calibration
851 11:41:15.497626 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:41:15.503957 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:41:15.507377 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:41:15.511198 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:41:15.517706 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 11:41:15.520723 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:41:15.524337 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:41:15.530675 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:41:15.533920 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:41:15.537246 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:41:15.543961 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:41:15.547113 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:41:15.550694 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:41:15.557173 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:41:15.560462 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:41:15.564054 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:41:15.570487 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:41:15.574043 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:41:15.577350 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:41:15.584184 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:41:15.587523 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
872 11:41:15.590978 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
873 11:41:15.594281 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:41:15.600762 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:41:15.604124 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:41:15.607297 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:41:15.613873 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:41:15.617063 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:41:15.620752 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
880 11:41:15.627042 0 9 12 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
881 11:41:15.630750 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:41:15.633693 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:41:15.640768 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:41:15.643615 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:41:15.647345 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:41:15.653908 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 11:41:15.657101 0 10 8 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (1 0)
888 11:41:15.660566 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
889 11:41:15.666751 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:41:15.669984 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:41:15.673543 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:41:15.680296 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:41:15.683349 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:41:15.686657 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
895 11:41:15.693320 0 11 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
896 11:41:15.696406 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
897 11:41:15.699732 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:41:15.706726 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:41:15.709763 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:41:15.713135 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:41:15.719511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:41:15.723110 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:41:15.726778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 11:41:15.733005 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 11:41:15.736394 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:41:15.739574 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:41:15.746260 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:41:15.749243 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:41:15.752676 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:41:15.759086 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:41:15.762682 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:41:15.765682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:41:15.772315 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:41:15.775905 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:41:15.779111 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:41:15.785327 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:41:15.788810 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:41:15.792138 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 11:41:15.798768 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 11:41:15.802054 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 11:41:15.805367 Total UI for P1: 0, mck2ui 16
922 11:41:15.808675 best dqsien dly found for B0: ( 0, 14, 6)
923 11:41:15.811933 Total UI for P1: 0, mck2ui 16
924 11:41:15.815286 best dqsien dly found for B1: ( 0, 14, 10)
925 11:41:15.818609 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 11:41:15.822452 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 11:41:15.822575
928 11:41:15.826150 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 11:41:15.829176 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 11:41:15.833113 [Gating] SW calibration Done
931 11:41:15.833193 ==
932 11:41:15.836607 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:41:15.840219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:41:15.840301 ==
935 11:41:15.843647 RX Vref Scan: 0
936 11:41:15.843726
937 11:41:15.843791 RX Vref 0 -> 0, step: 1
938 11:41:15.843854
939 11:41:15.847751 RX Delay -130 -> 252, step: 16
940 11:41:15.850942 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 11:41:15.855074 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 11:41:15.858567 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 11:41:15.861931 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 11:41:15.865827 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 11:41:15.873018 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 11:41:15.877281 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 11:41:15.880649 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 11:41:15.883956 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 11:41:15.887600 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 11:41:15.891378 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 11:41:15.894638 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 11:41:15.898577 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 11:41:15.902169 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 11:41:15.908557 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:41:15.911863 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 11:41:15.911939 ==
957 11:41:15.915341 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:41:15.918533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:41:15.918629 ==
960 11:41:15.921576 DQS Delay:
961 11:41:15.921714 DQS0 = 0, DQS1 = 0
962 11:41:15.921806 DQM Delay:
963 11:41:15.925060 DQM0 = 85, DQM1 = 74
964 11:41:15.925166 DQ Delay:
965 11:41:15.928254 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 11:41:15.931614 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
967 11:41:15.934875 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 11:41:15.938952 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
969 11:41:15.939053
970 11:41:15.939145
971 11:41:15.939235 ==
972 11:41:15.942262 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:41:15.946291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:41:15.946391 ==
975 11:41:15.946493
976 11:41:15.946589
977 11:41:15.949974 TX Vref Scan disable
978 11:41:15.953769 == TX Byte 0 ==
979 11:41:15.957023 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 11:41:15.960681 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 11:41:15.960773 == TX Byte 1 ==
982 11:41:15.964947 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 11:41:15.971327 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 11:41:15.971407 ==
985 11:41:15.974683 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:41:15.977489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:41:15.977587 ==
988 11:41:15.990516 TX Vref=22, minBit 4, minWin=27, winSum=441
989 11:41:15.993690 TX Vref=24, minBit 5, minWin=27, winSum=445
990 11:41:15.996866 TX Vref=26, minBit 5, minWin=27, winSum=448
991 11:41:16.000241 TX Vref=28, minBit 10, minWin=27, winSum=448
992 11:41:16.003881 TX Vref=30, minBit 10, minWin=27, winSum=449
993 11:41:16.010440 TX Vref=32, minBit 4, minWin=27, winSum=443
994 11:41:16.013701 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 30
995 11:41:16.013774
996 11:41:16.017091 Final TX Range 1 Vref 30
997 11:41:16.017166
998 11:41:16.017230 ==
999 11:41:16.020313 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:41:16.023376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:41:16.027322 ==
1002 11:41:16.027424
1003 11:41:16.027516
1004 11:41:16.027606 TX Vref Scan disable
1005 11:41:16.030553 == TX Byte 0 ==
1006 11:41:16.034377 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 11:41:16.040640 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 11:41:16.040741 == TX Byte 1 ==
1009 11:41:16.043947 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 11:41:16.050671 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 11:41:16.050777
1012 11:41:16.050872 [DATLAT]
1013 11:41:16.050962 Freq=800, CH0 RK0
1014 11:41:16.051050
1015 11:41:16.053966 DATLAT Default: 0xa
1016 11:41:16.054035 0, 0xFFFF, sum = 0
1017 11:41:16.057255 1, 0xFFFF, sum = 0
1018 11:41:16.057370 2, 0xFFFF, sum = 0
1019 11:41:16.060747 3, 0xFFFF, sum = 0
1020 11:41:16.063930 4, 0xFFFF, sum = 0
1021 11:41:16.064028 5, 0xFFFF, sum = 0
1022 11:41:16.067146 6, 0xFFFF, sum = 0
1023 11:41:16.067248 7, 0xFFFF, sum = 0
1024 11:41:16.070515 8, 0xFFFF, sum = 0
1025 11:41:16.070629 9, 0x0, sum = 1
1026 11:41:16.073553 10, 0x0, sum = 2
1027 11:41:16.073631 11, 0x0, sum = 3
1028 11:41:16.073695 12, 0x0, sum = 4
1029 11:41:16.076874 best_step = 10
1030 11:41:16.076941
1031 11:41:16.077001 ==
1032 11:41:16.080218 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:41:16.083812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:41:16.083925 ==
1035 11:41:16.086907 RX Vref Scan: 1
1036 11:41:16.087015
1037 11:41:16.090702 Set Vref Range= 32 -> 127
1038 11:41:16.090795
1039 11:41:16.090882 RX Vref 32 -> 127, step: 1
1040 11:41:16.090967
1041 11:41:16.093984 RX Delay -111 -> 252, step: 8
1042 11:41:16.094081
1043 11:41:16.097243 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:41:16.100723 [Byte1]: 32
1045 11:41:16.100809
1046 11:41:16.103783 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:41:16.107373 [Byte1]: 33
1048 11:41:16.111120
1049 11:41:16.111204 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:41:16.114263 [Byte1]: 34
1051 11:41:16.118498
1052 11:41:16.118592 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:41:16.121887 [Byte1]: 35
1054 11:41:16.126844
1055 11:41:16.126987 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:41:16.130172 [Byte1]: 36
1057 11:41:16.133940
1058 11:41:16.134010 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:41:16.137464 [Byte1]: 37
1060 11:41:16.142283
1061 11:41:16.142413 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:41:16.145685 [Byte1]: 38
1063 11:41:16.149093
1064 11:41:16.149167 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:41:16.152368 [Byte1]: 39
1066 11:41:16.157288
1067 11:41:16.157386 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:41:16.160030 [Byte1]: 40
1069 11:41:16.164766
1070 11:41:16.164839 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:41:16.168069 [Byte1]: 41
1072 11:41:16.172653
1073 11:41:16.172733 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:41:16.175312 [Byte1]: 42
1075 11:41:16.180125
1076 11:41:16.180225 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:41:16.183421 [Byte1]: 43
1078 11:41:16.187880
1079 11:41:16.187982 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:41:16.191396 [Byte1]: 44
1081 11:41:16.195262
1082 11:41:16.195336 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:41:16.198384 [Byte1]: 45
1084 11:41:16.202853
1085 11:41:16.202955 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:41:16.205899 [Byte1]: 46
1087 11:41:16.210357
1088 11:41:16.210459 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:41:16.213864 [Byte1]: 47
1090 11:41:16.218007
1091 11:41:16.218113 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:41:16.221400 [Byte1]: 48
1093 11:41:16.226003
1094 11:41:16.226108 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:41:16.229176 [Byte1]: 49
1096 11:41:16.233438
1097 11:41:16.233512 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:41:16.236951 [Byte1]: 50
1099 11:41:16.240920
1100 11:41:16.240993 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:41:16.244296 [Byte1]: 51
1102 11:41:16.248784
1103 11:41:16.248887 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:41:16.252124 [Byte1]: 52
1105 11:41:16.256767
1106 11:41:16.256845 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:41:16.260186 [Byte1]: 53
1108 11:41:16.264356
1109 11:41:16.264469 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:41:16.268207 [Byte1]: 54
1111 11:41:16.271970
1112 11:41:16.272069 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:41:16.275182 [Byte1]: 55
1114 11:41:16.279513
1115 11:41:16.279613 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:41:16.283336 [Byte1]: 56
1117 11:41:16.287473
1118 11:41:16.287614 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:41:16.290657 [Byte1]: 57
1120 11:41:16.294999
1121 11:41:16.295099 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:41:16.298653 [Byte1]: 58
1123 11:41:16.302607
1124 11:41:16.302720 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:41:16.305814 [Byte1]: 59
1126 11:41:16.309861
1127 11:41:16.313070 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:41:16.313184 [Byte1]: 60
1129 11:41:16.317513
1130 11:41:16.320863 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:41:16.320965 [Byte1]: 61
1132 11:41:16.325358
1133 11:41:16.325464 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:41:16.329464 [Byte1]: 62
1135 11:41:16.333089
1136 11:41:16.333162 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:41:16.336554 [Byte1]: 63
1138 11:41:16.341054
1139 11:41:16.341155 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:41:16.344296 [Byte1]: 64
1141 11:41:16.348619
1142 11:41:16.348700 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:41:16.352359 [Byte1]: 65
1144 11:41:16.355627
1145 11:41:16.355728 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:41:16.359043 [Byte1]: 66
1147 11:41:16.363447
1148 11:41:16.363550 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:41:16.366932 [Byte1]: 67
1150 11:41:16.371231
1151 11:41:16.371312 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:41:16.374825 [Byte1]: 68
1153 11:41:16.379152
1154 11:41:16.379227 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:41:16.381928 [Byte1]: 69
1156 11:41:16.386819
1157 11:41:16.386896 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:41:16.390132 [Byte1]: 70
1159 11:41:16.394090
1160 11:41:16.394170 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:41:16.397564 [Byte1]: 71
1162 11:41:16.402242
1163 11:41:16.402320 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:41:16.405473 [Byte1]: 72
1165 11:41:16.409967
1166 11:41:16.410042 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:41:16.413036 [Byte1]: 73
1168 11:41:16.417059
1169 11:41:16.417143 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:41:16.420938 [Byte1]: 74
1171 11:41:16.424744
1172 11:41:16.428121 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:41:16.430999 [Byte1]: 75
1174 11:41:16.431113
1175 11:41:16.434608 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:41:16.438450 [Byte1]: 76
1177 11:41:16.438553
1178 11:41:16.442219 Set Vref, RX VrefLevel [Byte0]: 77
1179 11:41:16.445091 [Byte1]: 77
1180 11:41:16.445178
1181 11:41:16.448690 Set Vref, RX VrefLevel [Byte0]: 78
1182 11:41:16.452598 [Byte1]: 78
1183 11:41:16.452682
1184 11:41:16.456087 Set Vref, RX VrefLevel [Byte0]: 79
1185 11:41:16.459578 [Byte1]: 79
1186 11:41:16.459706
1187 11:41:16.463257 Set Vref, RX VrefLevel [Byte0]: 80
1188 11:41:16.467126 [Byte1]: 80
1189 11:41:16.470855
1190 11:41:16.470969 Final RX Vref Byte 0 = 68 to rank0
1191 11:41:16.474251 Final RX Vref Byte 1 = 53 to rank0
1192 11:41:16.477545 Final RX Vref Byte 0 = 68 to rank1
1193 11:41:16.481337 Final RX Vref Byte 1 = 53 to rank1==
1194 11:41:16.485166 Dram Type= 6, Freq= 0, CH_0, rank 0
1195 11:41:16.488922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 11:41:16.489005 ==
1197 11:41:16.489069 DQS Delay:
1198 11:41:16.492676 DQS0 = 0, DQS1 = 0
1199 11:41:16.492786 DQM Delay:
1200 11:41:16.496469 DQM0 = 88, DQM1 = 75
1201 11:41:16.496570 DQ Delay:
1202 11:41:16.500609 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1203 11:41:16.504122 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1204 11:41:16.504204 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1205 11:41:16.507971 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1206 11:41:16.508084
1207 11:41:16.508148
1208 11:41:16.518545 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f22, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1209 11:41:16.518629 CH0 RK0: MR19=606, MR18=3F22
1210 11:41:16.526163 CH0_RK0: MR19=0x606, MR18=0x3F22, DQSOSC=393, MR23=63, INC=95, DEC=63
1211 11:41:16.526249
1212 11:41:16.529884 ----->DramcWriteLeveling(PI) begin...
1213 11:41:16.529989 ==
1214 11:41:16.533627 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 11:41:16.537380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 11:41:16.537478 ==
1217 11:41:16.540687 Write leveling (Byte 0): 31 => 31
1218 11:41:16.544141 Write leveling (Byte 1): 30 => 30
1219 11:41:16.548002 DramcWriteLeveling(PI) end<-----
1220 11:41:16.548083
1221 11:41:16.548148 ==
1222 11:41:16.551462 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 11:41:16.555264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 11:41:16.555348 ==
1225 11:41:16.558496 [Gating] SW mode calibration
1226 11:41:16.606146 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1227 11:41:16.606432 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1228 11:41:16.606504 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 11:41:16.607134 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 11:41:16.607396 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1231 11:41:16.607647 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:41:16.607717 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:41:16.608250 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:41:16.608553 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:41:16.608641 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:41:16.650545 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:41:16.650646 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:41:16.651066 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:41:16.651653 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:41:16.652355 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:41:16.652617 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:41:16.652689 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:41:16.652753 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:41:16.653519 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:41:16.653781 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1246 11:41:16.694462 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1247 11:41:16.694564 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1248 11:41:16.695159 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:41:16.695422 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:41:16.695491 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:41:16.695564 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:41:16.695627 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:41:16.696277 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:41:16.696575 0 9 8 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 1)
1255 11:41:16.696645 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1256 11:41:16.738308 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 11:41:16.738480 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 11:41:16.738853 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 11:41:16.739307 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 11:41:16.739699 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 11:41:16.740172 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 11:41:16.740257 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0)
1263 11:41:16.740867 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1264 11:41:16.741132 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 11:41:16.741382 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 11:41:16.778418 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 11:41:16.778569 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 11:41:16.779176 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 11:41:16.779460 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1270 11:41:16.780179 0 11 8 | B1->B0 | 2626 3737 | 0 1 | (0 0) (0 0)
1271 11:41:16.780446 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1272 11:41:16.780540 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 11:41:16.780620 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 11:41:16.781018 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 11:41:16.783810 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 11:41:16.787469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 11:41:16.790692 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1278 11:41:16.793753 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1279 11:41:16.797181 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:41:16.803787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:41:16.807220 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:41:16.810771 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:41:16.817308 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:41:16.820304 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:41:16.824013 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:41:16.830541 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:41:16.833403 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:41:16.836966 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 11:41:16.840369 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 11:41:16.847053 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 11:41:16.850544 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 11:41:16.853658 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 11:41:16.860248 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 11:41:16.863528 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1295 11:41:16.866560 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1296 11:41:16.870141 Total UI for P1: 0, mck2ui 16
1297 11:41:16.873305 best dqsien dly found for B0: ( 0, 14, 8)
1298 11:41:16.876765 Total UI for P1: 0, mck2ui 16
1299 11:41:16.880082 best dqsien dly found for B1: ( 0, 14, 8)
1300 11:41:16.883469 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1301 11:41:16.886434 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1302 11:41:16.889979
1303 11:41:16.893334 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1304 11:41:16.896336 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 11:41:16.900097 [Gating] SW calibration Done
1306 11:41:16.900195 ==
1307 11:41:16.903070 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 11:41:16.906666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 11:41:16.906766 ==
1310 11:41:16.906856 RX Vref Scan: 0
1311 11:41:16.906945
1312 11:41:16.909808 RX Vref 0 -> 0, step: 1
1313 11:41:16.909905
1314 11:41:16.912975 RX Delay -130 -> 252, step: 16
1315 11:41:16.916592 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1316 11:41:16.919935 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1317 11:41:16.926441 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1318 11:41:16.929795 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1319 11:41:16.932759 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1320 11:41:16.936371 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1321 11:41:16.940027 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1322 11:41:16.946354 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1323 11:41:16.949403 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1324 11:41:16.952616 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1325 11:41:16.956131 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1326 11:41:16.959923 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1327 11:41:16.966189 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1328 11:41:16.969611 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1329 11:41:16.972941 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1330 11:41:16.976301 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1331 11:41:16.976400 ==
1332 11:41:16.979464 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 11:41:16.986045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 11:41:16.986145 ==
1335 11:41:16.986236 DQS Delay:
1336 11:41:16.989397 DQS0 = 0, DQS1 = 0
1337 11:41:16.989504 DQM Delay:
1338 11:41:16.989596 DQM0 = 83, DQM1 = 76
1339 11:41:16.992595 DQ Delay:
1340 11:41:16.995983 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1341 11:41:16.999710 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1342 11:41:17.002866 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1343 11:41:17.005954 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1344 11:41:17.006056
1345 11:41:17.006146
1346 11:41:17.006233 ==
1347 11:41:17.009197 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 11:41:17.012876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 11:41:17.012959 ==
1350 11:41:17.013024
1351 11:41:17.013084
1352 11:41:17.015928 TX Vref Scan disable
1353 11:41:17.019447 == TX Byte 0 ==
1354 11:41:17.022229 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1355 11:41:17.025649 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1356 11:41:17.029304 == TX Byte 1 ==
1357 11:41:17.032376 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1358 11:41:17.035830 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1359 11:41:17.035914 ==
1360 11:41:17.038916 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 11:41:17.042329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 11:41:17.042411 ==
1363 11:41:17.056440 TX Vref=22, minBit 3, minWin=27, winSum=442
1364 11:41:17.060209 TX Vref=24, minBit 8, minWin=27, winSum=448
1365 11:41:17.063152 TX Vref=26, minBit 9, minWin=27, winSum=447
1366 11:41:17.066815 TX Vref=28, minBit 9, minWin=27, winSum=447
1367 11:41:17.070064 TX Vref=30, minBit 8, minWin=27, winSum=447
1368 11:41:17.076553 TX Vref=32, minBit 9, minWin=27, winSum=443
1369 11:41:17.079688 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 24
1370 11:41:17.079793
1371 11:41:17.083146 Final TX Range 1 Vref 24
1372 11:41:17.083241
1373 11:41:17.083333 ==
1374 11:41:17.086448 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 11:41:17.089721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 11:41:17.089791 ==
1377 11:41:17.092979
1378 11:41:17.093048
1379 11:41:17.093110 TX Vref Scan disable
1380 11:41:17.096443 == TX Byte 0 ==
1381 11:41:17.099784 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1382 11:41:17.106889 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1383 11:41:17.106963 == TX Byte 1 ==
1384 11:41:17.109995 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1385 11:41:17.116719 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1386 11:41:17.116790
1387 11:41:17.116851 [DATLAT]
1388 11:41:17.116909 Freq=800, CH0 RK1
1389 11:41:17.116970
1390 11:41:17.119717 DATLAT Default: 0xa
1391 11:41:17.119786 0, 0xFFFF, sum = 0
1392 11:41:17.122833 1, 0xFFFF, sum = 0
1393 11:41:17.122908 2, 0xFFFF, sum = 0
1394 11:41:17.126284 3, 0xFFFF, sum = 0
1395 11:41:17.129758 4, 0xFFFF, sum = 0
1396 11:41:17.129827 5, 0xFFFF, sum = 0
1397 11:41:17.133140 6, 0xFFFF, sum = 0
1398 11:41:17.133212 7, 0xFFFF, sum = 0
1399 11:41:17.136328 8, 0xFFFF, sum = 0
1400 11:41:17.136424 9, 0x0, sum = 1
1401 11:41:17.136518 10, 0x0, sum = 2
1402 11:41:17.139731 11, 0x0, sum = 3
1403 11:41:17.139801 12, 0x0, sum = 4
1404 11:41:17.143022 best_step = 10
1405 11:41:17.143089
1406 11:41:17.143147 ==
1407 11:41:17.146320 Dram Type= 6, Freq= 0, CH_0, rank 1
1408 11:41:17.149630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 11:41:17.149726 ==
1410 11:41:17.153323 RX Vref Scan: 0
1411 11:41:17.153393
1412 11:41:17.153451 RX Vref 0 -> 0, step: 1
1413 11:41:17.153507
1414 11:41:17.156140 RX Delay -111 -> 252, step: 8
1415 11:41:17.163369 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1416 11:41:17.166726 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1417 11:41:17.170039 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1418 11:41:17.173727 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1419 11:41:17.176768 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1420 11:41:17.183451 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1421 11:41:17.186731 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1422 11:41:17.189610 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1423 11:41:17.193001 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1424 11:41:17.199667 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1425 11:41:17.203060 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1426 11:41:17.206491 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1427 11:41:17.209801 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1428 11:41:17.212711 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1429 11:41:17.219709 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1430 11:41:17.222929 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1431 11:41:17.223005 ==
1432 11:41:17.226082 Dram Type= 6, Freq= 0, CH_0, rank 1
1433 11:41:17.229317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 11:41:17.229392 ==
1435 11:41:17.232817 DQS Delay:
1436 11:41:17.232913 DQS0 = 0, DQS1 = 0
1437 11:41:17.232998 DQM Delay:
1438 11:41:17.236022 DQM0 = 86, DQM1 = 77
1439 11:41:17.236096 DQ Delay:
1440 11:41:17.239430 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =84
1441 11:41:17.242633 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1442 11:41:17.245954 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1443 11:41:17.249013 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1444 11:41:17.249087
1445 11:41:17.249152
1446 11:41:17.259218 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1447 11:41:17.262480 CH0 RK1: MR19=606, MR18=3C02
1448 11:41:17.265549 CH0_RK1: MR19=0x606, MR18=0x3C02, DQSOSC=394, MR23=63, INC=95, DEC=63
1449 11:41:17.268991 [RxdqsGatingPostProcess] freq 800
1450 11:41:17.275968 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1451 11:41:17.279117 Pre-setting of DQS Precalculation
1452 11:41:17.282330 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1453 11:41:17.282404 ==
1454 11:41:17.285693 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 11:41:17.292138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 11:41:17.292215 ==
1457 11:41:17.296219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1458 11:41:17.301954 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1459 11:41:17.311859 [CA 0] Center 36 (6~67) winsize 62
1460 11:41:17.314938 [CA 1] Center 36 (6~67) winsize 62
1461 11:41:17.318406 [CA 2] Center 34 (4~65) winsize 62
1462 11:41:17.321806 [CA 3] Center 34 (3~65) winsize 63
1463 11:41:17.324947 [CA 4] Center 34 (4~65) winsize 62
1464 11:41:17.328127 [CA 5] Center 34 (3~65) winsize 63
1465 11:41:17.328229
1466 11:41:17.331941 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1467 11:41:17.332023
1468 11:41:17.335236 [CATrainingPosCal] consider 1 rank data
1469 11:41:17.338592 u2DelayCellTimex100 = 270/100 ps
1470 11:41:17.341408 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1471 11:41:17.348041 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 11:41:17.351563 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1473 11:41:17.354799 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1474 11:41:17.358183 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 11:41:17.361362 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1476 11:41:17.361460
1477 11:41:17.364693 CA PerBit enable=1, Macro0, CA PI delay=34
1478 11:41:17.364776
1479 11:41:17.367900 [CBTSetCACLKResult] CA Dly = 34
1480 11:41:17.367983 CS Dly: 5 (0~36)
1481 11:41:17.371206 ==
1482 11:41:17.374492 Dram Type= 6, Freq= 0, CH_1, rank 1
1483 11:41:17.378187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1484 11:41:17.378263 ==
1485 11:41:17.384382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1486 11:41:17.388131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1487 11:41:17.397819 [CA 0] Center 36 (6~67) winsize 62
1488 11:41:17.401584 [CA 1] Center 36 (6~67) winsize 62
1489 11:41:17.404695 [CA 2] Center 34 (4~65) winsize 62
1490 11:41:17.408044 [CA 3] Center 34 (3~65) winsize 63
1491 11:41:17.411280 [CA 4] Center 34 (4~65) winsize 62
1492 11:41:17.414294 [CA 5] Center 33 (3~64) winsize 62
1493 11:41:17.414365
1494 11:41:17.417975 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1495 11:41:17.418059
1496 11:41:17.421074 [CATrainingPosCal] consider 2 rank data
1497 11:41:17.424577 u2DelayCellTimex100 = 270/100 ps
1498 11:41:17.427861 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1499 11:41:17.434283 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1500 11:41:17.437374 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1501 11:41:17.440677 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1502 11:41:17.443973 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1503 11:41:17.447353 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1504 11:41:17.447442
1505 11:41:17.450935 CA PerBit enable=1, Macro0, CA PI delay=33
1506 11:41:17.451036
1507 11:41:17.454019 [CBTSetCACLKResult] CA Dly = 33
1508 11:41:17.454166 CS Dly: 6 (0~38)
1509 11:41:17.457836
1510 11:41:17.460744 ----->DramcWriteLeveling(PI) begin...
1511 11:41:17.460819 ==
1512 11:41:17.464037 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 11:41:17.467851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 11:41:17.467927 ==
1515 11:41:17.470678 Write leveling (Byte 0): 28 => 28
1516 11:41:17.474378 Write leveling (Byte 1): 28 => 28
1517 11:41:17.477881 DramcWriteLeveling(PI) end<-----
1518 11:41:17.477952
1519 11:41:17.478013 ==
1520 11:41:17.480627 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 11:41:17.484546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 11:41:17.484633 ==
1523 11:41:17.487812 [Gating] SW mode calibration
1524 11:41:17.494093 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1525 11:41:17.501005 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1526 11:41:17.504107 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1527 11:41:17.507622 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1528 11:41:17.513733 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1529 11:41:17.517431 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:41:17.520426 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:41:17.526995 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:41:17.530727 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:41:17.533753 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:41:17.540299 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:41:17.543557 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:41:17.547043 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:41:17.550623 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:41:17.556941 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:41:17.560170 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:41:17.564046 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:41:17.570282 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:41:17.574004 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:41:17.577001 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1544 11:41:17.583691 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1545 11:41:17.587052 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:41:17.590317 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:41:17.596739 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:41:17.600209 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:41:17.603637 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:41:17.610202 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:41:17.613453 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:41:17.616925 0 9 8 | B1->B0 | 3030 3231 | 0 1 | (0 0) (0 0)
1553 11:41:17.623704 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 11:41:17.626361 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 11:41:17.630212 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 11:41:17.636687 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 11:41:17.639951 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 11:41:17.643231 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 11:41:17.649863 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
1560 11:41:17.653016 0 10 8 | B1->B0 | 2c2c 2727 | 0 1 | (1 0) (1 0)
1561 11:41:17.656261 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 11:41:17.663242 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 11:41:17.666199 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 11:41:17.669943 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 11:41:17.676739 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 11:41:17.679641 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 11:41:17.683151 0 11 4 | B1->B0 | 2525 2727 | 0 1 | (0 0) (0 0)
1568 11:41:17.689565 0 11 8 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (0 0)
1569 11:41:17.693038 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 11:41:17.696420 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 11:41:17.702865 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 11:41:17.705940 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 11:41:17.709639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 11:41:17.716131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 11:41:17.719741 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1576 11:41:17.722883 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1577 11:41:17.726141 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:41:17.732764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:41:17.735997 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:41:17.742665 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:41:17.745948 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:41:17.749331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 11:41:17.752694 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 11:41:17.759086 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 11:41:17.762453 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 11:41:17.765854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 11:41:17.772777 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 11:41:17.775958 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 11:41:17.779505 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 11:41:17.785985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 11:41:17.788901 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1592 11:41:17.792180 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1593 11:41:17.795357 Total UI for P1: 0, mck2ui 16
1594 11:41:17.799186 best dqsien dly found for B0: ( 0, 14, 4)
1595 11:41:17.802620 Total UI for P1: 0, mck2ui 16
1596 11:41:17.805325 best dqsien dly found for B1: ( 0, 14, 4)
1597 11:41:17.809087 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1598 11:41:17.812026 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1599 11:41:17.812115
1600 11:41:17.819054 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1601 11:41:17.822711 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1602 11:41:17.822816 [Gating] SW calibration Done
1603 11:41:17.825733 ==
1604 11:41:17.828935 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 11:41:17.832395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 11:41:17.832505 ==
1607 11:41:17.832583 RX Vref Scan: 0
1608 11:41:17.832645
1609 11:41:17.835395 RX Vref 0 -> 0, step: 1
1610 11:41:17.835468
1611 11:41:17.838807 RX Delay -130 -> 252, step: 16
1612 11:41:17.842026 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1613 11:41:17.845481 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1614 11:41:17.852062 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1615 11:41:17.855573 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1616 11:41:17.858380 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1617 11:41:17.861657 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1618 11:41:17.865572 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1619 11:41:17.871929 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1620 11:41:17.875316 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1621 11:41:17.878164 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1622 11:41:17.881755 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1623 11:41:17.885068 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1624 11:41:17.891426 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1625 11:41:17.895214 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1626 11:41:17.898238 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1627 11:41:17.901743 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1628 11:41:17.904572 ==
1629 11:41:17.904652 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 11:41:17.911327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 11:41:17.911409 ==
1632 11:41:17.911474 DQS Delay:
1633 11:41:17.914639 DQS0 = 0, DQS1 = 0
1634 11:41:17.914721 DQM Delay:
1635 11:41:17.918324 DQM0 = 88, DQM1 = 78
1636 11:41:17.918405 DQ Delay:
1637 11:41:17.921513 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1638 11:41:17.925021 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1639 11:41:17.928274 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1640 11:41:17.931394 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1641 11:41:17.931475
1642 11:41:17.931538
1643 11:41:17.931597 ==
1644 11:41:17.934796 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 11:41:17.938149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 11:41:17.938231 ==
1647 11:41:17.938295
1648 11:41:17.938354
1649 11:41:17.941474 TX Vref Scan disable
1650 11:41:17.944748 == TX Byte 0 ==
1651 11:41:17.947575 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1652 11:41:17.951338 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1653 11:41:17.954495 == TX Byte 1 ==
1654 11:41:17.957843 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1655 11:41:17.961109 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1656 11:41:17.961190 ==
1657 11:41:17.964425 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 11:41:17.970952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 11:41:17.971033 ==
1660 11:41:17.982770 TX Vref=22, minBit 8, minWin=26, winSum=442
1661 11:41:17.985948 TX Vref=24, minBit 0, minWin=27, winSum=446
1662 11:41:17.989013 TX Vref=26, minBit 9, minWin=27, winSum=450
1663 11:41:17.992385 TX Vref=28, minBit 10, minWin=27, winSum=449
1664 11:41:17.995779 TX Vref=30, minBit 8, minWin=27, winSum=448
1665 11:41:18.002579 TX Vref=32, minBit 8, minWin=27, winSum=448
1666 11:41:18.005707 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 26
1667 11:41:18.005789
1668 11:41:18.008896 Final TX Range 1 Vref 26
1669 11:41:18.008977
1670 11:41:18.009042 ==
1671 11:41:18.012407 Dram Type= 6, Freq= 0, CH_1, rank 0
1672 11:41:18.015389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1673 11:41:18.018685 ==
1674 11:41:18.018766
1675 11:41:18.018830
1676 11:41:18.018890 TX Vref Scan disable
1677 11:41:18.022446 == TX Byte 0 ==
1678 11:41:18.025852 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1679 11:41:18.028965 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1680 11:41:18.032385 == TX Byte 1 ==
1681 11:41:18.036100 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1682 11:41:18.042186 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1683 11:41:18.042266
1684 11:41:18.042330 [DATLAT]
1685 11:41:18.042388 Freq=800, CH1 RK0
1686 11:41:18.042446
1687 11:41:18.045523 DATLAT Default: 0xa
1688 11:41:18.045603 0, 0xFFFF, sum = 0
1689 11:41:18.049071 1, 0xFFFF, sum = 0
1690 11:41:18.049153 2, 0xFFFF, sum = 0
1691 11:41:18.052337 3, 0xFFFF, sum = 0
1692 11:41:18.055361 4, 0xFFFF, sum = 0
1693 11:41:18.055442 5, 0xFFFF, sum = 0
1694 11:41:18.058665 6, 0xFFFF, sum = 0
1695 11:41:18.058747 7, 0xFFFF, sum = 0
1696 11:41:18.062399 8, 0xFFFF, sum = 0
1697 11:41:18.062481 9, 0x0, sum = 1
1698 11:41:18.065781 10, 0x0, sum = 2
1699 11:41:18.065863 11, 0x0, sum = 3
1700 11:41:18.065929 12, 0x0, sum = 4
1701 11:41:18.068640 best_step = 10
1702 11:41:18.068720
1703 11:41:18.068784 ==
1704 11:41:18.071778 Dram Type= 6, Freq= 0, CH_1, rank 0
1705 11:41:18.075255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1706 11:41:18.075337 ==
1707 11:41:18.078636 RX Vref Scan: 1
1708 11:41:18.078717
1709 11:41:18.081959 Set Vref Range= 32 -> 127
1710 11:41:18.082040
1711 11:41:18.082103 RX Vref 32 -> 127, step: 1
1712 11:41:18.082163
1713 11:41:18.085371 RX Delay -95 -> 252, step: 8
1714 11:41:18.085451
1715 11:41:18.088741 Set Vref, RX VrefLevel [Byte0]: 32
1716 11:41:18.091469 [Byte1]: 32
1717 11:41:18.095470
1718 11:41:18.095550 Set Vref, RX VrefLevel [Byte0]: 33
1719 11:41:18.098367 [Byte1]: 33
1720 11:41:18.102993
1721 11:41:18.103073 Set Vref, RX VrefLevel [Byte0]: 34
1722 11:41:18.106066 [Byte1]: 34
1723 11:41:18.110845
1724 11:41:18.110951 Set Vref, RX VrefLevel [Byte0]: 35
1725 11:41:18.113505 [Byte1]: 35
1726 11:41:18.117817
1727 11:41:18.117897 Set Vref, RX VrefLevel [Byte0]: 36
1728 11:41:18.121641 [Byte1]: 36
1729 11:41:18.125312
1730 11:41:18.125393 Set Vref, RX VrefLevel [Byte0]: 37
1731 11:41:18.128665 [Byte1]: 37
1732 11:41:18.133339
1733 11:41:18.136321 Set Vref, RX VrefLevel [Byte0]: 38
1734 11:41:18.136427 [Byte1]: 38
1735 11:41:18.140716
1736 11:41:18.140796 Set Vref, RX VrefLevel [Byte0]: 39
1737 11:41:18.144136 [Byte1]: 39
1738 11:41:18.148755
1739 11:41:18.148839 Set Vref, RX VrefLevel [Byte0]: 40
1740 11:41:18.151727 [Byte1]: 40
1741 11:41:18.155974
1742 11:41:18.156054 Set Vref, RX VrefLevel [Byte0]: 41
1743 11:41:18.159355 [Byte1]: 41
1744 11:41:18.163495
1745 11:41:18.163576 Set Vref, RX VrefLevel [Byte0]: 42
1746 11:41:18.166719 [Byte1]: 42
1747 11:41:18.171022
1748 11:41:18.171103 Set Vref, RX VrefLevel [Byte0]: 43
1749 11:41:18.174447 [Byte1]: 43
1750 11:41:18.178791
1751 11:41:18.178872 Set Vref, RX VrefLevel [Byte0]: 44
1752 11:41:18.182311 [Byte1]: 44
1753 11:41:18.186233
1754 11:41:18.186313 Set Vref, RX VrefLevel [Byte0]: 45
1755 11:41:18.189489 [Byte1]: 45
1756 11:41:18.194143
1757 11:41:18.194224 Set Vref, RX VrefLevel [Byte0]: 46
1758 11:41:18.197399 [Byte1]: 46
1759 11:41:18.201468
1760 11:41:18.201548 Set Vref, RX VrefLevel [Byte0]: 47
1761 11:41:18.205036 [Byte1]: 47
1762 11:41:18.209015
1763 11:41:18.209095 Set Vref, RX VrefLevel [Byte0]: 48
1764 11:41:18.212701 [Byte1]: 48
1765 11:41:18.216748
1766 11:41:18.216854 Set Vref, RX VrefLevel [Byte0]: 49
1767 11:41:18.219869 [Byte1]: 49
1768 11:41:18.224652
1769 11:41:18.224734 Set Vref, RX VrefLevel [Byte0]: 50
1770 11:41:18.227665 [Byte1]: 50
1771 11:41:18.231875
1772 11:41:18.231956 Set Vref, RX VrefLevel [Byte0]: 51
1773 11:41:18.235421 [Byte1]: 51
1774 11:41:18.239423
1775 11:41:18.239523 Set Vref, RX VrefLevel [Byte0]: 52
1776 11:41:18.243022 [Byte1]: 52
1777 11:41:18.247219
1778 11:41:18.247301 Set Vref, RX VrefLevel [Byte0]: 53
1779 11:41:18.250472 [Byte1]: 53
1780 11:41:18.254537
1781 11:41:18.254619 Set Vref, RX VrefLevel [Byte0]: 54
1782 11:41:18.258173 [Byte1]: 54
1783 11:41:18.262500
1784 11:41:18.262582 Set Vref, RX VrefLevel [Byte0]: 55
1785 11:41:18.268828 [Byte1]: 55
1786 11:41:18.268909
1787 11:41:18.271802 Set Vref, RX VrefLevel [Byte0]: 56
1788 11:41:18.275156 [Byte1]: 56
1789 11:41:18.275238
1790 11:41:18.278915 Set Vref, RX VrefLevel [Byte0]: 57
1791 11:41:18.282153 [Byte1]: 57
1792 11:41:18.282235
1793 11:41:18.285225 Set Vref, RX VrefLevel [Byte0]: 58
1794 11:41:18.288530 [Byte1]: 58
1795 11:41:18.292842
1796 11:41:18.292923 Set Vref, RX VrefLevel [Byte0]: 59
1797 11:41:18.296318 [Byte1]: 59
1798 11:41:18.300434
1799 11:41:18.300522 Set Vref, RX VrefLevel [Byte0]: 60
1800 11:41:18.304146 [Byte1]: 60
1801 11:41:18.308146
1802 11:41:18.308224 Set Vref, RX VrefLevel [Byte0]: 61
1803 11:41:18.311253 [Byte1]: 61
1804 11:41:18.315349
1805 11:41:18.315435 Set Vref, RX VrefLevel [Byte0]: 62
1806 11:41:18.318702 [Byte1]: 62
1807 11:41:18.323246
1808 11:41:18.323327 Set Vref, RX VrefLevel [Byte0]: 63
1809 11:41:18.326965 [Byte1]: 63
1810 11:41:18.330562
1811 11:41:18.330647 Set Vref, RX VrefLevel [Byte0]: 64
1812 11:41:18.334479 [Byte1]: 64
1813 11:41:18.338191
1814 11:41:18.338300 Set Vref, RX VrefLevel [Byte0]: 65
1815 11:41:18.341838 [Byte1]: 65
1816 11:41:18.346252
1817 11:41:18.346337 Set Vref, RX VrefLevel [Byte0]: 66
1818 11:41:18.349342 [Byte1]: 66
1819 11:41:18.353605
1820 11:41:18.353690 Set Vref, RX VrefLevel [Byte0]: 67
1821 11:41:18.356717 [Byte1]: 67
1822 11:41:18.361428
1823 11:41:18.361512 Set Vref, RX VrefLevel [Byte0]: 68
1824 11:41:18.364731 [Byte1]: 68
1825 11:41:18.368777
1826 11:41:18.368862 Set Vref, RX VrefLevel [Byte0]: 69
1827 11:41:18.371989 [Byte1]: 69
1828 11:41:18.376265
1829 11:41:18.376350 Set Vref, RX VrefLevel [Byte0]: 70
1830 11:41:18.379777 [Byte1]: 70
1831 11:41:18.384239
1832 11:41:18.384324 Set Vref, RX VrefLevel [Byte0]: 71
1833 11:41:18.387449 [Byte1]: 71
1834 11:41:18.391546
1835 11:41:18.391631 Set Vref, RX VrefLevel [Byte0]: 72
1836 11:41:18.394702 [Byte1]: 72
1837 11:41:18.398871
1838 11:41:18.398956 Set Vref, RX VrefLevel [Byte0]: 73
1839 11:41:18.402300 [Byte1]: 73
1840 11:41:18.406528
1841 11:41:18.406644 Set Vref, RX VrefLevel [Byte0]: 74
1842 11:41:18.410188 [Byte1]: 74
1843 11:41:18.414468
1844 11:41:18.414552 Final RX Vref Byte 0 = 53 to rank0
1845 11:41:18.417447 Final RX Vref Byte 1 = 65 to rank0
1846 11:41:18.421101 Final RX Vref Byte 0 = 53 to rank1
1847 11:41:18.424607 Final RX Vref Byte 1 = 65 to rank1==
1848 11:41:18.427935 Dram Type= 6, Freq= 0, CH_1, rank 0
1849 11:41:18.434413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 11:41:18.434499 ==
1851 11:41:18.434584 DQS Delay:
1852 11:41:18.434663 DQS0 = 0, DQS1 = 0
1853 11:41:18.437507 DQM Delay:
1854 11:41:18.437592 DQM0 = 86, DQM1 = 79
1855 11:41:18.440922 DQ Delay:
1856 11:41:18.444155 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
1857 11:41:18.444240 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1858 11:41:18.447746 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1859 11:41:18.454413 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1860 11:41:18.454499
1861 11:41:18.454583
1862 11:41:18.460733 [DQSOSCAuto] RK0, (LSB)MR18= 0x2916, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
1863 11:41:18.464216 CH1 RK0: MR19=606, MR18=2916
1864 11:41:18.471123 CH1_RK0: MR19=0x606, MR18=0x2916, DQSOSC=399, MR23=63, INC=92, DEC=61
1865 11:41:18.471210
1866 11:41:18.474496 ----->DramcWriteLeveling(PI) begin...
1867 11:41:18.474583 ==
1868 11:41:18.477557 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 11:41:18.480725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 11:41:18.480811 ==
1871 11:41:18.484195 Write leveling (Byte 0): 28 => 28
1872 11:41:18.487324 Write leveling (Byte 1): 27 => 27
1873 11:41:18.490780 DramcWriteLeveling(PI) end<-----
1874 11:41:18.490866
1875 11:41:18.490952 ==
1876 11:41:18.493909 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 11:41:18.497283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 11:41:18.497368 ==
1879 11:41:18.500955 [Gating] SW mode calibration
1880 11:41:18.507424 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1881 11:41:18.513864 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1882 11:41:18.517666 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1883 11:41:18.520988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1884 11:41:18.527304 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:41:18.530761 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:41:18.533902 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:41:18.540830 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:41:18.544092 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:41:18.547375 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:41:18.553767 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:41:18.557787 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:41:18.560337 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:41:18.566852 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:41:18.570801 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:41:18.573654 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:41:18.580552 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:41:18.583548 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:41:18.586865 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1899 11:41:18.593857 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1900 11:41:18.597107 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1901 11:41:18.599908 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:41:18.606734 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:41:18.610316 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:41:18.613451 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:41:18.620105 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:41:18.623492 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:41:18.626703 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:41:18.633480 0 9 8 | B1->B0 | 2e2e 2626 | 1 1 | (1 1) (0 0)
1909 11:41:18.636449 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 11:41:18.639667 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 11:41:18.646484 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 11:41:18.649750 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 11:41:18.653154 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 11:41:18.659896 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:41:18.663436 0 10 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1916 11:41:18.666140 0 10 8 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
1917 11:41:18.672728 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 11:41:18.676424 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 11:41:18.679712 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:41:18.686105 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:41:18.689255 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:41:18.692777 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:41:18.699324 0 11 4 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
1924 11:41:18.702717 0 11 8 | B1->B0 | 4040 3939 | 1 0 | (0 0) (0 0)
1925 11:41:18.705855 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 11:41:18.712503 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 11:41:18.715954 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 11:41:18.719273 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 11:41:18.725865 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 11:41:18.729083 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:41:18.732162 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1932 11:41:18.735722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:41:18.742754 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:41:18.745843 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:41:18.749388 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:41:18.755366 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:41:18.758657 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:41:18.762045 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:41:18.768866 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:41:18.772393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:41:18.775648 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:41:18.782092 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:41:18.785123 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:41:18.788570 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:41:18.795334 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:41:18.798880 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:41:18.802185 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1948 11:41:18.808209 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 11:41:18.811792 Total UI for P1: 0, mck2ui 16
1950 11:41:18.814806 best dqsien dly found for B0: ( 0, 14, 4)
1951 11:41:18.818074 Total UI for P1: 0, mck2ui 16
1952 11:41:18.822190 best dqsien dly found for B1: ( 0, 14, 4)
1953 11:41:18.825260 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1954 11:41:18.828537 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1955 11:41:18.828634
1956 11:41:18.831855 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1957 11:41:18.834646 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1958 11:41:18.838158 [Gating] SW calibration Done
1959 11:41:18.838258 ==
1960 11:41:18.841573 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 11:41:18.844977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 11:41:18.845060 ==
1963 11:41:18.847950 RX Vref Scan: 0
1964 11:41:18.848059
1965 11:41:18.848156 RX Vref 0 -> 0, step: 1
1966 11:41:18.851206
1967 11:41:18.851304 RX Delay -130 -> 252, step: 16
1968 11:41:18.857906 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1969 11:41:18.861677 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1970 11:41:18.864721 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1971 11:41:18.868078 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1972 11:41:18.871060 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1973 11:41:18.878043 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1974 11:41:18.881227 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1975 11:41:18.884621 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1976 11:41:18.887850 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1977 11:41:18.891620 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1978 11:41:18.898535 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1979 11:41:18.902134 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1980 11:41:18.904975 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1981 11:41:18.907909 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1982 11:41:18.911725 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1983 11:41:18.918329 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1984 11:41:18.918861 ==
1985 11:41:18.921963 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 11:41:18.924889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 11:41:18.925349 ==
1988 11:41:18.925697 DQS Delay:
1989 11:41:18.928259 DQS0 = 0, DQS1 = 0
1990 11:41:18.928853 DQM Delay:
1991 11:41:18.931382 DQM0 = 86, DQM1 = 80
1992 11:41:18.931897 DQ Delay:
1993 11:41:18.934602 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =77
1994 11:41:18.938218 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1995 11:41:18.941245 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1996 11:41:18.944483 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1997 11:41:18.944945
1998 11:41:18.945299
1999 11:41:18.945644 ==
2000 11:41:18.947763 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 11:41:18.951170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 11:41:18.954598 ==
2003 11:41:18.955059
2004 11:41:18.955401
2005 11:41:18.955727 TX Vref Scan disable
2006 11:41:18.958206 == TX Byte 0 ==
2007 11:41:18.961410 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2008 11:41:18.965215 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2009 11:41:18.968386 == TX Byte 1 ==
2010 11:41:18.971687 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2011 11:41:18.975216 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2012 11:41:18.975652 ==
2013 11:41:18.978203 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 11:41:18.984700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 11:41:18.985123 ==
2016 11:41:18.997069 TX Vref=22, minBit 8, minWin=27, winSum=444
2017 11:41:19.000274 TX Vref=24, minBit 8, minWin=27, winSum=445
2018 11:41:19.004133 TX Vref=26, minBit 13, minWin=27, winSum=451
2019 11:41:19.007316 TX Vref=28, minBit 13, minWin=27, winSum=450
2020 11:41:19.010533 TX Vref=30, minBit 8, minWin=27, winSum=449
2021 11:41:19.016973 TX Vref=32, minBit 0, minWin=28, winSum=449
2022 11:41:19.020700 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 32
2023 11:41:19.021264
2024 11:41:19.023280 Final TX Range 1 Vref 32
2025 11:41:19.023763
2026 11:41:19.024092 ==
2027 11:41:19.026791 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 11:41:19.030174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 11:41:19.030845 ==
2030 11:41:19.033657
2031 11:41:19.034085
2032 11:41:19.034578 TX Vref Scan disable
2033 11:41:19.037029 == TX Byte 0 ==
2034 11:41:19.040557 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2035 11:41:19.046874 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2036 11:41:19.047429 == TX Byte 1 ==
2037 11:41:19.050212 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2038 11:41:19.056799 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2039 11:41:19.057349
2040 11:41:19.057829 [DATLAT]
2041 11:41:19.058352 Freq=800, CH1 RK1
2042 11:41:19.058879
2043 11:41:19.060103 DATLAT Default: 0xa
2044 11:41:19.060700 0, 0xFFFF, sum = 0
2045 11:41:19.063991 1, 0xFFFF, sum = 0
2046 11:41:19.066601 2, 0xFFFF, sum = 0
2047 11:41:19.067270 3, 0xFFFF, sum = 0
2048 11:41:19.070251 4, 0xFFFF, sum = 0
2049 11:41:19.070729 5, 0xFFFF, sum = 0
2050 11:41:19.073298 6, 0xFFFF, sum = 0
2051 11:41:19.073878 7, 0xFFFF, sum = 0
2052 11:41:19.076743 8, 0xFFFF, sum = 0
2053 11:41:19.077388 9, 0x0, sum = 1
2054 11:41:19.080290 10, 0x0, sum = 2
2055 11:41:19.080787 11, 0x0, sum = 3
2056 11:41:19.081135 12, 0x0, sum = 4
2057 11:41:19.083503 best_step = 10
2058 11:41:19.083998
2059 11:41:19.084459 ==
2060 11:41:19.086955 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 11:41:19.090209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 11:41:19.090748 ==
2063 11:41:19.093382 RX Vref Scan: 0
2064 11:41:19.093818
2065 11:41:19.094164 RX Vref 0 -> 0, step: 1
2066 11:41:19.096606
2067 11:41:19.097107 RX Delay -95 -> 252, step: 8
2068 11:41:19.103867 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2069 11:41:19.107220 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2070 11:41:19.110441 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2071 11:41:19.113623 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2072 11:41:19.116960 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2073 11:41:19.123636 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2074 11:41:19.127109 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2075 11:41:19.130313 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2076 11:41:19.133696 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2077 11:41:19.136880 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2078 11:41:19.143564 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2079 11:41:19.146793 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2080 11:41:19.150019 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2081 11:41:19.153152 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2082 11:41:19.160232 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2083 11:41:19.163316 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2084 11:41:19.163842 ==
2085 11:41:19.166747 Dram Type= 6, Freq= 0, CH_1, rank 1
2086 11:41:19.169911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2087 11:41:19.170612 ==
2088 11:41:19.173234 DQS Delay:
2089 11:41:19.173746 DQS0 = 0, DQS1 = 0
2090 11:41:19.174200 DQM Delay:
2091 11:41:19.176575 DQM0 = 87, DQM1 = 78
2092 11:41:19.177015 DQ Delay:
2093 11:41:19.180437 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2094 11:41:19.183279 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2095 11:41:19.186694 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2096 11:41:19.190161 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2097 11:41:19.190598
2098 11:41:19.191033
2099 11:41:19.199949 [DQSOSCAuto] RK1, (LSB)MR18= 0x1911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2100 11:41:19.200395 CH1 RK1: MR19=606, MR18=1911
2101 11:41:19.206445 CH1_RK1: MR19=0x606, MR18=0x1911, DQSOSC=403, MR23=63, INC=90, DEC=60
2102 11:41:19.209675 [RxdqsGatingPostProcess] freq 800
2103 11:41:19.216259 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2104 11:41:19.219454 Pre-setting of DQS Precalculation
2105 11:41:19.223079 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2106 11:41:19.233292 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2107 11:41:19.239464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2108 11:41:19.239893
2109 11:41:19.240247
2110 11:41:19.243259 [Calibration Summary] 1600 Mbps
2111 11:41:19.243696 CH 0, Rank 0
2112 11:41:19.246207 SW Impedance : PASS
2113 11:41:19.246657 DUTY Scan : NO K
2114 11:41:19.249651 ZQ Calibration : PASS
2115 11:41:19.252868 Jitter Meter : NO K
2116 11:41:19.253311 CBT Training : PASS
2117 11:41:19.256192 Write leveling : PASS
2118 11:41:19.259531 RX DQS gating : PASS
2119 11:41:19.259951 RX DQ/DQS(RDDQC) : PASS
2120 11:41:19.263295 TX DQ/DQS : PASS
2121 11:41:19.263792 RX DATLAT : PASS
2122 11:41:19.266101 RX DQ/DQS(Engine): PASS
2123 11:41:19.269732 TX OE : NO K
2124 11:41:19.270268 All Pass.
2125 11:41:19.270685
2126 11:41:19.271009 CH 0, Rank 1
2127 11:41:19.273015 SW Impedance : PASS
2128 11:41:19.276268 DUTY Scan : NO K
2129 11:41:19.276832 ZQ Calibration : PASS
2130 11:41:19.279494 Jitter Meter : NO K
2131 11:41:19.282853 CBT Training : PASS
2132 11:41:19.283279 Write leveling : PASS
2133 11:41:19.286165 RX DQS gating : PASS
2134 11:41:19.289762 RX DQ/DQS(RDDQC) : PASS
2135 11:41:19.290298 TX DQ/DQS : PASS
2136 11:41:19.292908 RX DATLAT : PASS
2137 11:41:19.295914 RX DQ/DQS(Engine): PASS
2138 11:41:19.296422 TX OE : NO K
2139 11:41:19.299271 All Pass.
2140 11:41:19.299716
2141 11:41:19.300184 CH 1, Rank 0
2142 11:41:19.302917 SW Impedance : PASS
2143 11:41:19.303362 DUTY Scan : NO K
2144 11:41:19.306058 ZQ Calibration : PASS
2145 11:41:19.309251 Jitter Meter : NO K
2146 11:41:19.309748 CBT Training : PASS
2147 11:41:19.312606 Write leveling : PASS
2148 11:41:19.315907 RX DQS gating : PASS
2149 11:41:19.316423 RX DQ/DQS(RDDQC) : PASS
2150 11:41:19.319005 TX DQ/DQS : PASS
2151 11:41:19.319553 RX DATLAT : PASS
2152 11:41:19.322760 RX DQ/DQS(Engine): PASS
2153 11:41:19.325812 TX OE : NO K
2154 11:41:19.326330 All Pass.
2155 11:41:19.326708
2156 11:41:19.327096 CH 1, Rank 1
2157 11:41:19.329241 SW Impedance : PASS
2158 11:41:19.332827 DUTY Scan : NO K
2159 11:41:19.333370 ZQ Calibration : PASS
2160 11:41:19.335789 Jitter Meter : NO K
2161 11:41:19.339103 CBT Training : PASS
2162 11:41:19.339523 Write leveling : PASS
2163 11:41:19.342747 RX DQS gating : PASS
2164 11:41:19.345841 RX DQ/DQS(RDDQC) : PASS
2165 11:41:19.346258 TX DQ/DQS : PASS
2166 11:41:19.349520 RX DATLAT : PASS
2167 11:41:19.352368 RX DQ/DQS(Engine): PASS
2168 11:41:19.352973 TX OE : NO K
2169 11:41:19.355386 All Pass.
2170 11:41:19.355798
2171 11:41:19.356126 DramC Write-DBI off
2172 11:41:19.358762 PER_BANK_REFRESH: Hybrid Mode
2173 11:41:19.359179 TX_TRACKING: ON
2174 11:41:19.362218 [GetDramInforAfterCalByMRR] Vendor 6.
2175 11:41:19.368807 [GetDramInforAfterCalByMRR] Revision 606.
2176 11:41:19.372593 [GetDramInforAfterCalByMRR] Revision 2 0.
2177 11:41:19.373012 MR0 0x3b3b
2178 11:41:19.373344 MR8 0x5151
2179 11:41:19.375577 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 11:41:19.376115
2181 11:41:19.378841 MR0 0x3b3b
2182 11:41:19.379408 MR8 0x5151
2183 11:41:19.382201 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 11:41:19.382707
2185 11:41:19.392089 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2186 11:41:19.395465 [FAST_K] Save calibration result to emmc
2187 11:41:19.398719 [FAST_K] Save calibration result to emmc
2188 11:41:19.402075 dram_init: config_dvfs: 1
2189 11:41:19.405555 dramc_set_vcore_voltage set vcore to 662500
2190 11:41:19.408598 Read voltage for 1200, 2
2191 11:41:19.409012 Vio18 = 0
2192 11:41:19.409349 Vcore = 662500
2193 11:41:19.411849 Vdram = 0
2194 11:41:19.412264 Vddq = 0
2195 11:41:19.412641 Vmddr = 0
2196 11:41:19.418340 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2197 11:41:19.422070 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2198 11:41:19.425451 MEM_TYPE=3, freq_sel=15
2199 11:41:19.428776 sv_algorithm_assistance_LP4_1600
2200 11:41:19.432042 ============ PULL DRAM RESETB DOWN ============
2201 11:41:19.434769 ========== PULL DRAM RESETB DOWN end =========
2202 11:41:19.441348 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2203 11:41:19.445077 ===================================
2204 11:41:19.448302 LPDDR4 DRAM CONFIGURATION
2205 11:41:19.451456 ===================================
2206 11:41:19.451878 EX_ROW_EN[0] = 0x0
2207 11:41:19.454961 EX_ROW_EN[1] = 0x0
2208 11:41:19.455514 LP4Y_EN = 0x0
2209 11:41:19.458159 WORK_FSP = 0x0
2210 11:41:19.458818 WL = 0x4
2211 11:41:19.461518 RL = 0x4
2212 11:41:19.461942 BL = 0x2
2213 11:41:19.465201 RPST = 0x0
2214 11:41:19.465621 RD_PRE = 0x0
2215 11:41:19.468454 WR_PRE = 0x1
2216 11:41:19.468911 WR_PST = 0x0
2217 11:41:19.471928 DBI_WR = 0x0
2218 11:41:19.472480 DBI_RD = 0x0
2219 11:41:19.475006 OTF = 0x1
2220 11:41:19.478143 ===================================
2221 11:41:19.481891 ===================================
2222 11:41:19.482554 ANA top config
2223 11:41:19.484997 ===================================
2224 11:41:19.488192 DLL_ASYNC_EN = 0
2225 11:41:19.491602 ALL_SLAVE_EN = 0
2226 11:41:19.494777 NEW_RANK_MODE = 1
2227 11:41:19.495202 DLL_IDLE_MODE = 1
2228 11:41:19.497905 LP45_APHY_COMB_EN = 1
2229 11:41:19.501229 TX_ODT_DIS = 1
2230 11:41:19.504486 NEW_8X_MODE = 1
2231 11:41:19.508282 ===================================
2232 11:41:19.511021 ===================================
2233 11:41:19.514685 data_rate = 2400
2234 11:41:19.517725 CKR = 1
2235 11:41:19.518197 DQ_P2S_RATIO = 8
2236 11:41:19.521151 ===================================
2237 11:41:19.524362 CA_P2S_RATIO = 8
2238 11:41:19.527918 DQ_CA_OPEN = 0
2239 11:41:19.531243 DQ_SEMI_OPEN = 0
2240 11:41:19.534874 CA_SEMI_OPEN = 0
2241 11:41:19.535297 CA_FULL_RATE = 0
2242 11:41:19.537732 DQ_CKDIV4_EN = 0
2243 11:41:19.540866 CA_CKDIV4_EN = 0
2244 11:41:19.544281 CA_PREDIV_EN = 0
2245 11:41:19.547615 PH8_DLY = 17
2246 11:41:19.550945 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2247 11:41:19.551371 DQ_AAMCK_DIV = 4
2248 11:41:19.554506 CA_AAMCK_DIV = 4
2249 11:41:19.557898 CA_ADMCK_DIV = 4
2250 11:41:19.561040 DQ_TRACK_CA_EN = 0
2251 11:41:19.564245 CA_PICK = 1200
2252 11:41:19.567408 CA_MCKIO = 1200
2253 11:41:19.570924 MCKIO_SEMI = 0
2254 11:41:19.574246 PLL_FREQ = 2366
2255 11:41:19.574740 DQ_UI_PI_RATIO = 32
2256 11:41:19.577592 CA_UI_PI_RATIO = 0
2257 11:41:19.581067 ===================================
2258 11:41:19.584179 ===================================
2259 11:41:19.587315 memory_type:LPDDR4
2260 11:41:19.590514 GP_NUM : 10
2261 11:41:19.590942 SRAM_EN : 1
2262 11:41:19.594027 MD32_EN : 0
2263 11:41:19.597066 ===================================
2264 11:41:19.601009 [ANA_INIT] >>>>>>>>>>>>>>
2265 11:41:19.601447 <<<<<< [CONFIGURE PHASE]: ANA_TX
2266 11:41:19.607377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2267 11:41:19.607832 ===================================
2268 11:41:19.610675 data_rate = 2400,PCW = 0X5b00
2269 11:41:19.614196 ===================================
2270 11:41:19.617729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2271 11:41:19.623989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 11:41:19.630574 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2273 11:41:19.633649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2274 11:41:19.637369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2275 11:41:19.640273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2276 11:41:19.644152 [ANA_INIT] flow start
2277 11:41:19.644783 [ANA_INIT] PLL >>>>>>>>
2278 11:41:19.647385 [ANA_INIT] PLL <<<<<<<<
2279 11:41:19.650218 [ANA_INIT] MIDPI >>>>>>>>
2280 11:41:19.653686 [ANA_INIT] MIDPI <<<<<<<<
2281 11:41:19.654128 [ANA_INIT] DLL >>>>>>>>
2282 11:41:19.656845 [ANA_INIT] DLL <<<<<<<<
2283 11:41:19.657281 [ANA_INIT] flow end
2284 11:41:19.663593 ============ LP4 DIFF to SE enter ============
2285 11:41:19.666874 ============ LP4 DIFF to SE exit ============
2286 11:41:19.670102 [ANA_INIT] <<<<<<<<<<<<<
2287 11:41:19.674046 [Flow] Enable top DCM control >>>>>
2288 11:41:19.677071 [Flow] Enable top DCM control <<<<<
2289 11:41:19.677685 Enable DLL master slave shuffle
2290 11:41:19.683763 ==============================================================
2291 11:41:19.686722 Gating Mode config
2292 11:41:19.690046 ==============================================================
2293 11:41:19.693912 Config description:
2294 11:41:19.703391 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2295 11:41:19.710274 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2296 11:41:19.713849 SELPH_MODE 0: By rank 1: By Phase
2297 11:41:19.720088 ==============================================================
2298 11:41:19.723312 GAT_TRACK_EN = 1
2299 11:41:19.726516 RX_GATING_MODE = 2
2300 11:41:19.730096 RX_GATING_TRACK_MODE = 2
2301 11:41:19.733323 SELPH_MODE = 1
2302 11:41:19.736323 PICG_EARLY_EN = 1
2303 11:41:19.736887 VALID_LAT_VALUE = 1
2304 11:41:19.743162 ==============================================================
2305 11:41:19.746058 Enter into Gating configuration >>>>
2306 11:41:19.749238 Exit from Gating configuration <<<<
2307 11:41:19.752647 Enter into DVFS_PRE_config >>>>>
2308 11:41:19.762563 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2309 11:41:19.765873 Exit from DVFS_PRE_config <<<<<
2310 11:41:19.769319 Enter into PICG configuration >>>>
2311 11:41:19.772447 Exit from PICG configuration <<<<
2312 11:41:19.776099 [RX_INPUT] configuration >>>>>
2313 11:41:19.778988 [RX_INPUT] configuration <<<<<
2314 11:41:19.785939 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2315 11:41:19.789062 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2316 11:41:19.795602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 11:41:19.802297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 11:41:19.808908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 11:41:19.815522 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 11:41:19.818844 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2321 11:41:19.822464 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2322 11:41:19.825398 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2323 11:41:19.831914 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2324 11:41:19.835729 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2325 11:41:19.838862 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 11:41:19.842316 ===================================
2327 11:41:19.845460 LPDDR4 DRAM CONFIGURATION
2328 11:41:19.848950 ===================================
2329 11:41:19.849032 EX_ROW_EN[0] = 0x0
2330 11:41:19.851786 EX_ROW_EN[1] = 0x0
2331 11:41:19.855386 LP4Y_EN = 0x0
2332 11:41:19.855496 WORK_FSP = 0x0
2333 11:41:19.858770 WL = 0x4
2334 11:41:19.858867 RL = 0x4
2335 11:41:19.861845 BL = 0x2
2336 11:41:19.861941 RPST = 0x0
2337 11:41:19.865175 RD_PRE = 0x0
2338 11:41:19.865274 WR_PRE = 0x1
2339 11:41:19.868302 WR_PST = 0x0
2340 11:41:19.868402 DBI_WR = 0x0
2341 11:41:19.871638 DBI_RD = 0x0
2342 11:41:19.871720 OTF = 0x1
2343 11:41:19.875199 ===================================
2344 11:41:19.878909 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2345 11:41:19.885092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2346 11:41:19.888794 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2347 11:41:19.891779 ===================================
2348 11:41:19.895068 LPDDR4 DRAM CONFIGURATION
2349 11:41:19.898414 ===================================
2350 11:41:19.898525 EX_ROW_EN[0] = 0x10
2351 11:41:19.901624 EX_ROW_EN[1] = 0x0
2352 11:41:19.904830 LP4Y_EN = 0x0
2353 11:41:19.904912 WORK_FSP = 0x0
2354 11:41:19.908173 WL = 0x4
2355 11:41:19.908243 RL = 0x4
2356 11:41:19.911365 BL = 0x2
2357 11:41:19.911467 RPST = 0x0
2358 11:41:19.914737 RD_PRE = 0x0
2359 11:41:19.914849 WR_PRE = 0x1
2360 11:41:19.918202 WR_PST = 0x0
2361 11:41:19.918291 DBI_WR = 0x0
2362 11:41:19.921633 DBI_RD = 0x0
2363 11:41:19.921756 OTF = 0x1
2364 11:41:19.924513 ===================================
2365 11:41:19.931439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2366 11:41:19.931556 ==
2367 11:41:19.934509 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 11:41:19.937798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 11:41:19.937881 ==
2370 11:41:19.941068 [Duty_Offset_Calibration]
2371 11:41:19.944957 B0:1 B1:-1 CA:0
2372 11:41:19.945052
2373 11:41:19.947787 [DutyScan_Calibration_Flow] k_type=0
2374 11:41:19.956223
2375 11:41:19.956300 ==CLK 0==
2376 11:41:19.959867 Final CLK duty delay cell = 0
2377 11:41:19.962658 [0] MAX Duty = 5094%(X100), DQS PI = 16
2378 11:41:19.966334 [0] MIN Duty = 4875%(X100), DQS PI = 10
2379 11:41:19.969531 [0] AVG Duty = 4984%(X100)
2380 11:41:19.969605
2381 11:41:19.972790 CH0 CLK Duty spec in!! Max-Min= 219%
2382 11:41:19.976448 [DutyScan_Calibration_Flow] ====Done====
2383 11:41:19.976563
2384 11:41:19.979345 [DutyScan_Calibration_Flow] k_type=1
2385 11:41:19.994333
2386 11:41:19.994414 ==DQS 0 ==
2387 11:41:19.997600 Final DQS duty delay cell = -4
2388 11:41:20.000941 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2389 11:41:20.004015 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2390 11:41:20.007209 [-4] AVG Duty = 4968%(X100)
2391 11:41:20.007282
2392 11:41:20.007344 ==DQS 1 ==
2393 11:41:20.010452 Final DQS duty delay cell = -4
2394 11:41:20.014020 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2395 11:41:20.017322 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2396 11:41:20.020348 [-4] AVG Duty = 4938%(X100)
2397 11:41:20.020417
2398 11:41:20.023883 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2399 11:41:20.023955
2400 11:41:20.027323 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2401 11:41:20.030204 [DutyScan_Calibration_Flow] ====Done====
2402 11:41:20.030277
2403 11:41:20.033444 [DutyScan_Calibration_Flow] k_type=3
2404 11:41:20.051966
2405 11:41:20.052041 ==DQM 0 ==
2406 11:41:20.055111 Final DQM duty delay cell = 0
2407 11:41:20.058445 [0] MAX Duty = 5062%(X100), DQS PI = 18
2408 11:41:20.061981 [0] MIN Duty = 4875%(X100), DQS PI = 6
2409 11:41:20.065318 [0] AVG Duty = 4968%(X100)
2410 11:41:20.065387
2411 11:41:20.065446 ==DQM 1 ==
2412 11:41:20.068694 Final DQM duty delay cell = 4
2413 11:41:20.071946 [4] MAX Duty = 5187%(X100), DQS PI = 16
2414 11:41:20.075596 [4] MIN Duty = 5000%(X100), DQS PI = 24
2415 11:41:20.078480 [4] AVG Duty = 5093%(X100)
2416 11:41:20.078556
2417 11:41:20.082153 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2418 11:41:20.082236
2419 11:41:20.085340 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2420 11:41:20.088768 [DutyScan_Calibration_Flow] ====Done====
2421 11:41:20.088843
2422 11:41:20.091639 [DutyScan_Calibration_Flow] k_type=2
2423 11:41:20.107498
2424 11:41:20.107576 ==DQ 0 ==
2425 11:41:20.111456 Final DQ duty delay cell = -4
2426 11:41:20.114510 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2427 11:41:20.118041 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2428 11:41:20.121147 [-4] AVG Duty = 4969%(X100)
2429 11:41:20.121220
2430 11:41:20.121281 ==DQ 1 ==
2431 11:41:20.124386 Final DQ duty delay cell = 0
2432 11:41:20.127664 [0] MAX Duty = 5093%(X100), DQS PI = 2
2433 11:41:20.130779 [0] MIN Duty = 4969%(X100), DQS PI = 40
2434 11:41:20.134257 [0] AVG Duty = 5031%(X100)
2435 11:41:20.134336
2436 11:41:20.137479 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2437 11:41:20.137640
2438 11:41:20.140828 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2439 11:41:20.144413 [DutyScan_Calibration_Flow] ====Done====
2440 11:41:20.144484 ==
2441 11:41:20.147710 Dram Type= 6, Freq= 0, CH_1, rank 0
2442 11:41:20.150801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 11:41:20.150905 ==
2444 11:41:20.154452 [Duty_Offset_Calibration]
2445 11:41:20.154530 B0:-1 B1:1 CA:1
2446 11:41:20.154593
2447 11:41:20.157527 [DutyScan_Calibration_Flow] k_type=0
2448 11:41:20.167838
2449 11:41:20.167918 ==CLK 0==
2450 11:41:20.171844 Final CLK duty delay cell = 0
2451 11:41:20.175004 [0] MAX Duty = 5156%(X100), DQS PI = 20
2452 11:41:20.177872 [0] MIN Duty = 4969%(X100), DQS PI = 60
2453 11:41:20.177947 [0] AVG Duty = 5062%(X100)
2454 11:41:20.181303
2455 11:41:20.184375 CH1 CLK Duty spec in!! Max-Min= 187%
2456 11:41:20.187828 [DutyScan_Calibration_Flow] ====Done====
2457 11:41:20.187904
2458 11:41:20.191192 [DutyScan_Calibration_Flow] k_type=1
2459 11:41:20.207166
2460 11:41:20.207246 ==DQS 0 ==
2461 11:41:20.210552 Final DQS duty delay cell = 0
2462 11:41:20.214084 [0] MAX Duty = 5125%(X100), DQS PI = 18
2463 11:41:20.217322 [0] MIN Duty = 4907%(X100), DQS PI = 6
2464 11:41:20.220602 [0] AVG Duty = 5016%(X100)
2465 11:41:20.220698
2466 11:41:20.220792 ==DQS 1 ==
2467 11:41:20.224018 Final DQS duty delay cell = 0
2468 11:41:20.226996 [0] MAX Duty = 5062%(X100), DQS PI = 10
2469 11:41:20.230307 [0] MIN Duty = 4969%(X100), DQS PI = 56
2470 11:41:20.233664 [0] AVG Duty = 5015%(X100)
2471 11:41:20.233770
2472 11:41:20.236822 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2473 11:41:20.236930
2474 11:41:20.240197 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2475 11:41:20.243931 [DutyScan_Calibration_Flow] ====Done====
2476 11:41:20.244050
2477 11:41:20.247092 [DutyScan_Calibration_Flow] k_type=3
2478 11:41:20.262968
2479 11:41:20.263073 ==DQM 0 ==
2480 11:41:20.266085 Final DQM duty delay cell = -4
2481 11:41:20.269869 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2482 11:41:20.272919 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2483 11:41:20.276395 [-4] AVG Duty = 4969%(X100)
2484 11:41:20.276495
2485 11:41:20.276586 ==DQM 1 ==
2486 11:41:20.279323 Final DQM duty delay cell = 0
2487 11:41:20.283132 [0] MAX Duty = 5156%(X100), DQS PI = 2
2488 11:41:20.286226 [0] MIN Duty = 5000%(X100), DQS PI = 28
2489 11:41:20.289389 [0] AVG Duty = 5078%(X100)
2490 11:41:20.289468
2491 11:41:20.292478 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2492 11:41:20.292596
2493 11:41:20.296020 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2494 11:41:20.299340 [DutyScan_Calibration_Flow] ====Done====
2495 11:41:20.299496
2496 11:41:20.302836 [DutyScan_Calibration_Flow] k_type=2
2497 11:41:20.319581
2498 11:41:20.319664 ==DQ 0 ==
2499 11:41:20.323072 Final DQ duty delay cell = 0
2500 11:41:20.326320 [0] MAX Duty = 5156%(X100), DQS PI = 28
2501 11:41:20.329688 [0] MIN Duty = 4876%(X100), DQS PI = 8
2502 11:41:20.329771 [0] AVG Duty = 5016%(X100)
2503 11:41:20.333013
2504 11:41:20.333097 ==DQ 1 ==
2505 11:41:20.336447 Final DQ duty delay cell = 0
2506 11:41:20.339871 [0] MAX Duty = 5124%(X100), DQS PI = 10
2507 11:41:20.342853 [0] MIN Duty = 4969%(X100), DQS PI = 60
2508 11:41:20.342937 [0] AVG Duty = 5046%(X100)
2509 11:41:20.343003
2510 11:41:20.345992 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2511 11:41:20.349471
2512 11:41:20.352894 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2513 11:41:20.355915 [DutyScan_Calibration_Flow] ====Done====
2514 11:41:20.359414 nWR fixed to 30
2515 11:41:20.359499 [ModeRegInit_LP4] CH0 RK0
2516 11:41:20.362524 [ModeRegInit_LP4] CH0 RK1
2517 11:41:20.366033 [ModeRegInit_LP4] CH1 RK0
2518 11:41:20.369472 [ModeRegInit_LP4] CH1 RK1
2519 11:41:20.369556 match AC timing 7
2520 11:41:20.373001 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2521 11:41:20.379174 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2522 11:41:20.382634 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2523 11:41:20.389263 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2524 11:41:20.392832 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2525 11:41:20.392942 ==
2526 11:41:20.396121 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 11:41:20.399253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 11:41:20.399362 ==
2529 11:41:20.405826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2530 11:41:20.412645 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2531 11:41:20.419730 [CA 0] Center 39 (9~70) winsize 62
2532 11:41:20.422976 [CA 1] Center 39 (9~69) winsize 61
2533 11:41:20.426250 [CA 2] Center 35 (5~66) winsize 62
2534 11:41:20.429672 [CA 3] Center 35 (5~66) winsize 62
2535 11:41:20.433204 [CA 4] Center 33 (4~63) winsize 60
2536 11:41:20.436023 [CA 5] Center 33 (3~63) winsize 61
2537 11:41:20.436136
2538 11:41:20.439699 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2539 11:41:20.439781
2540 11:41:20.442840 [CATrainingPosCal] consider 1 rank data
2541 11:41:20.446316 u2DelayCellTimex100 = 270/100 ps
2542 11:41:20.449144 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2543 11:41:20.456223 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2544 11:41:20.459666 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2545 11:41:20.462857 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2546 11:41:20.466012 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2547 11:41:20.469260 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2548 11:41:20.469345
2549 11:41:20.472635 CA PerBit enable=1, Macro0, CA PI delay=33
2550 11:41:20.472728
2551 11:41:20.475866 [CBTSetCACLKResult] CA Dly = 33
2552 11:41:20.475950 CS Dly: 8 (0~39)
2553 11:41:20.479501 ==
2554 11:41:20.482301 Dram Type= 6, Freq= 0, CH_0, rank 1
2555 11:41:20.485788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 11:41:20.485873 ==
2557 11:41:20.489114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2558 11:41:20.495478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2559 11:41:20.505276 [CA 0] Center 39 (9~70) winsize 62
2560 11:41:20.508589 [CA 1] Center 39 (9~70) winsize 62
2561 11:41:20.511756 [CA 2] Center 35 (5~66) winsize 62
2562 11:41:20.515706 [CA 3] Center 34 (4~65) winsize 62
2563 11:41:20.518962 [CA 4] Center 33 (3~64) winsize 62
2564 11:41:20.521709 [CA 5] Center 33 (3~63) winsize 61
2565 11:41:20.521792
2566 11:41:20.525660 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2567 11:41:20.525746
2568 11:41:20.528801 [CATrainingPosCal] consider 2 rank data
2569 11:41:20.532115 u2DelayCellTimex100 = 270/100 ps
2570 11:41:20.535165 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2571 11:41:20.538757 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2572 11:41:20.545508 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2573 11:41:20.548573 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2574 11:41:20.551905 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2575 11:41:20.555105 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2576 11:41:20.555188
2577 11:41:20.558660 CA PerBit enable=1, Macro0, CA PI delay=33
2578 11:41:20.558744
2579 11:41:20.561701 [CBTSetCACLKResult] CA Dly = 33
2580 11:41:20.561784 CS Dly: 9 (0~41)
2581 11:41:20.565215
2582 11:41:20.568363 ----->DramcWriteLeveling(PI) begin...
2583 11:41:20.568446 ==
2584 11:41:20.571618 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 11:41:20.575304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 11:41:20.575412 ==
2587 11:41:20.578215 Write leveling (Byte 0): 34 => 34
2588 11:41:20.581482 Write leveling (Byte 1): 28 => 28
2589 11:41:20.584940 DramcWriteLeveling(PI) end<-----
2590 11:41:20.585022
2591 11:41:20.585087 ==
2592 11:41:20.588340 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 11:41:20.591509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 11:41:20.591592 ==
2595 11:41:20.595068 [Gating] SW mode calibration
2596 11:41:20.601281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2597 11:41:20.607896 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2598 11:41:20.611049 0 15 0 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
2599 11:41:20.614756 0 15 4 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2600 11:41:20.621347 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2601 11:41:20.624833 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 11:41:20.627606 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 11:41:20.634405 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 11:41:20.637995 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 11:41:20.641242 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
2606 11:41:20.648071 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
2607 11:41:20.650928 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2608 11:41:20.654484 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 11:41:20.660722 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 11:41:20.664191 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 11:41:20.667747 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 11:41:20.674235 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 11:41:20.677319 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2614 11:41:20.680624 1 1 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2615 11:41:20.687628 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2616 11:41:20.690821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 11:41:20.694522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 11:41:20.701129 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 11:41:20.704084 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 11:41:20.707325 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 11:41:20.714258 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2622 11:41:20.717368 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2623 11:41:20.720884 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2624 11:41:20.724058 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:41:20.730303 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:41:20.734115 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:41:20.737157 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:41:20.743507 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:41:20.746835 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:41:20.750299 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:41:20.757203 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:41:20.760697 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:41:20.763940 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:41:20.770672 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:41:20.773725 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:41:20.777096 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 11:41:20.783759 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2638 11:41:20.787177 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2639 11:41:20.790042 Total UI for P1: 0, mck2ui 16
2640 11:41:20.793688 best dqsien dly found for B0: ( 1, 3, 26)
2641 11:41:20.796640 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2642 11:41:20.799941 Total UI for P1: 0, mck2ui 16
2643 11:41:20.803071 best dqsien dly found for B1: ( 1, 4, 0)
2644 11:41:20.807054 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2645 11:41:20.810083 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2646 11:41:20.810167
2647 11:41:20.816680 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2648 11:41:20.820036 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2649 11:41:20.820119 [Gating] SW calibration Done
2650 11:41:20.823118 ==
2651 11:41:20.826620 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 11:41:20.829886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 11:41:20.829997 ==
2654 11:41:20.830091 RX Vref Scan: 0
2655 11:41:20.830179
2656 11:41:20.833011 RX Vref 0 -> 0, step: 1
2657 11:41:20.833096
2658 11:41:20.836250 RX Delay -40 -> 252, step: 8
2659 11:41:20.840075 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2660 11:41:20.842918 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2661 11:41:20.849822 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2662 11:41:20.853204 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2663 11:41:20.856703 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2664 11:41:20.860082 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2665 11:41:20.862998 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2666 11:41:20.866808 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2667 11:41:20.873187 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2668 11:41:20.876614 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2669 11:41:20.879406 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2670 11:41:20.882677 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2671 11:41:20.889376 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2672 11:41:20.892738 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2673 11:41:20.896668 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2674 11:41:20.899482 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2675 11:41:20.899561 ==
2676 11:41:20.902883 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 11:41:20.906099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 11:41:20.909730 ==
2679 11:41:20.909812 DQS Delay:
2680 11:41:20.909877 DQS0 = 0, DQS1 = 0
2681 11:41:20.912944 DQM Delay:
2682 11:41:20.913026 DQM0 = 119, DQM1 = 105
2683 11:41:20.916146 DQ Delay:
2684 11:41:20.919541 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2685 11:41:20.922982 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2686 11:41:20.926280 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2687 11:41:20.929245 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2688 11:41:20.929327
2689 11:41:20.929427
2690 11:41:20.929491 ==
2691 11:41:20.932665 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 11:41:20.936042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 11:41:20.936155 ==
2694 11:41:20.936248
2695 11:41:20.939204
2696 11:41:20.939314 TX Vref Scan disable
2697 11:41:20.942278 == TX Byte 0 ==
2698 11:41:20.946206 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2699 11:41:20.949066 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2700 11:41:20.953001 == TX Byte 1 ==
2701 11:41:20.955893 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2702 11:41:20.959595 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2703 11:41:20.959677 ==
2704 11:41:20.962449 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 11:41:20.969208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 11:41:20.969298 ==
2707 11:41:20.979823 TX Vref=22, minBit 1, minWin=25, winSum=415
2708 11:41:20.983134 TX Vref=24, minBit 1, minWin=26, winSum=425
2709 11:41:20.986401 TX Vref=26, minBit 4, minWin=26, winSum=430
2710 11:41:20.990051 TX Vref=28, minBit 12, minWin=25, winSum=427
2711 11:41:20.993495 TX Vref=30, minBit 13, minWin=25, winSum=432
2712 11:41:20.999697 TX Vref=32, minBit 14, minWin=25, winSum=426
2713 11:41:21.003631 [TxChooseVref] Worse bit 4, Min win 26, Win sum 430, Final Vref 26
2714 11:41:21.003743
2715 11:41:21.006991 Final TX Range 1 Vref 26
2716 11:41:21.007095
2717 11:41:21.007223 ==
2718 11:41:21.009785 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 11:41:21.013782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 11:41:21.016563 ==
2721 11:41:21.016645
2722 11:41:21.016709
2723 11:41:21.016768 TX Vref Scan disable
2724 11:41:21.020071 == TX Byte 0 ==
2725 11:41:21.023380 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2726 11:41:21.029986 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2727 11:41:21.030080 == TX Byte 1 ==
2728 11:41:21.033275 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2729 11:41:21.039812 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2730 11:41:21.039965
2731 11:41:21.040098 [DATLAT]
2732 11:41:21.040230 Freq=1200, CH0 RK0
2733 11:41:21.040376
2734 11:41:21.043197 DATLAT Default: 0xd
2735 11:41:21.046828 0, 0xFFFF, sum = 0
2736 11:41:21.046992 1, 0xFFFF, sum = 0
2737 11:41:21.049946 2, 0xFFFF, sum = 0
2738 11:41:21.050085 3, 0xFFFF, sum = 0
2739 11:41:21.053112 4, 0xFFFF, sum = 0
2740 11:41:21.053301 5, 0xFFFF, sum = 0
2741 11:41:21.056755 6, 0xFFFF, sum = 0
2742 11:41:21.056869 7, 0xFFFF, sum = 0
2743 11:41:21.059708 8, 0xFFFF, sum = 0
2744 11:41:21.059819 9, 0xFFFF, sum = 0
2745 11:41:21.062797 10, 0xFFFF, sum = 0
2746 11:41:21.062910 11, 0xFFFF, sum = 0
2747 11:41:21.066624 12, 0x0, sum = 1
2748 11:41:21.066707 13, 0x0, sum = 2
2749 11:41:21.070020 14, 0x0, sum = 3
2750 11:41:21.070126 15, 0x0, sum = 4
2751 11:41:21.073039 best_step = 13
2752 11:41:21.073116
2753 11:41:21.073178 ==
2754 11:41:21.076507 Dram Type= 6, Freq= 0, CH_0, rank 0
2755 11:41:21.079405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2756 11:41:21.079498 ==
2757 11:41:21.079582 RX Vref Scan: 1
2758 11:41:21.082705
2759 11:41:21.082819 Set Vref Range= 32 -> 127
2760 11:41:21.082911
2761 11:41:21.085975 RX Vref 32 -> 127, step: 1
2762 11:41:21.086046
2763 11:41:21.089680 RX Delay -21 -> 252, step: 4
2764 11:41:21.089762
2765 11:41:21.092891 Set Vref, RX VrefLevel [Byte0]: 32
2766 11:41:21.095900 [Byte1]: 32
2767 11:41:21.095977
2768 11:41:21.099250 Set Vref, RX VrefLevel [Byte0]: 33
2769 11:41:21.102579 [Byte1]: 33
2770 11:41:21.106448
2771 11:41:21.106528 Set Vref, RX VrefLevel [Byte0]: 34
2772 11:41:21.109723 [Byte1]: 34
2773 11:41:21.114283
2774 11:41:21.114368 Set Vref, RX VrefLevel [Byte0]: 35
2775 11:41:21.117632 [Byte1]: 35
2776 11:41:21.122348
2777 11:41:21.122460 Set Vref, RX VrefLevel [Byte0]: 36
2778 11:41:21.125615 [Byte1]: 36
2779 11:41:21.130477
2780 11:41:21.130583 Set Vref, RX VrefLevel [Byte0]: 37
2781 11:41:21.133529 [Byte1]: 37
2782 11:41:21.138116
2783 11:41:21.138239 Set Vref, RX VrefLevel [Byte0]: 38
2784 11:41:21.141215 [Byte1]: 38
2785 11:41:21.146060
2786 11:41:21.146143 Set Vref, RX VrefLevel [Byte0]: 39
2787 11:41:21.149221 [Byte1]: 39
2788 11:41:21.154117
2789 11:41:21.154192 Set Vref, RX VrefLevel [Byte0]: 40
2790 11:41:21.157240 [Byte1]: 40
2791 11:41:21.162218
2792 11:41:21.162292 Set Vref, RX VrefLevel [Byte0]: 41
2793 11:41:21.165408 [Byte1]: 41
2794 11:41:21.170257
2795 11:41:21.170348 Set Vref, RX VrefLevel [Byte0]: 42
2796 11:41:21.173011 [Byte1]: 42
2797 11:41:21.177938
2798 11:41:21.178034 Set Vref, RX VrefLevel [Byte0]: 43
2799 11:41:21.181308 [Byte1]: 43
2800 11:41:21.185933
2801 11:41:21.186039 Set Vref, RX VrefLevel [Byte0]: 44
2802 11:41:21.189372 [Byte1]: 44
2803 11:41:21.193802
2804 11:41:21.193903 Set Vref, RX VrefLevel [Byte0]: 45
2805 11:41:21.196950 [Byte1]: 45
2806 11:41:21.201588
2807 11:41:21.201669 Set Vref, RX VrefLevel [Byte0]: 46
2808 11:41:21.204796 [Byte1]: 46
2809 11:41:21.209455
2810 11:41:21.209526 Set Vref, RX VrefLevel [Byte0]: 47
2811 11:41:21.212971 [Byte1]: 47
2812 11:41:21.217574
2813 11:41:21.217657 Set Vref, RX VrefLevel [Byte0]: 48
2814 11:41:21.220773 [Byte1]: 48
2815 11:41:21.225239
2816 11:41:21.225316 Set Vref, RX VrefLevel [Byte0]: 49
2817 11:41:21.228905 [Byte1]: 49
2818 11:41:21.233262
2819 11:41:21.233347 Set Vref, RX VrefLevel [Byte0]: 50
2820 11:41:21.236460 [Byte1]: 50
2821 11:41:21.241269
2822 11:41:21.241448 Set Vref, RX VrefLevel [Byte0]: 51
2823 11:41:21.244659 [Byte1]: 51
2824 11:41:21.249521
2825 11:41:21.249597 Set Vref, RX VrefLevel [Byte0]: 52
2826 11:41:21.252314 [Byte1]: 52
2827 11:41:21.257037
2828 11:41:21.257139 Set Vref, RX VrefLevel [Byte0]: 53
2829 11:41:21.260930 [Byte1]: 53
2830 11:41:21.265335
2831 11:41:21.265438 Set Vref, RX VrefLevel [Byte0]: 54
2832 11:41:21.268567 [Byte1]: 54
2833 11:41:21.273013
2834 11:41:21.273110 Set Vref, RX VrefLevel [Byte0]: 55
2835 11:41:21.276087 [Byte1]: 55
2836 11:41:21.281168
2837 11:41:21.281254 Set Vref, RX VrefLevel [Byte0]: 56
2838 11:41:21.284133 [Byte1]: 56
2839 11:41:21.288966
2840 11:41:21.289068 Set Vref, RX VrefLevel [Byte0]: 57
2841 11:41:21.292001 [Byte1]: 57
2842 11:41:21.296813
2843 11:41:21.296898 Set Vref, RX VrefLevel [Byte0]: 58
2844 11:41:21.299951 [Byte1]: 58
2845 11:41:21.305035
2846 11:41:21.305120 Set Vref, RX VrefLevel [Byte0]: 59
2847 11:41:21.308208 [Byte1]: 59
2848 11:41:21.312476
2849 11:41:21.312599 Set Vref, RX VrefLevel [Byte0]: 60
2850 11:41:21.315661 [Byte1]: 60
2851 11:41:21.320984
2852 11:41:21.321067 Set Vref, RX VrefLevel [Byte0]: 61
2853 11:41:21.323727 [Byte1]: 61
2854 11:41:21.328891
2855 11:41:21.328974 Set Vref, RX VrefLevel [Byte0]: 62
2856 11:41:21.331965 [Byte1]: 62
2857 11:41:21.336262
2858 11:41:21.336340 Set Vref, RX VrefLevel [Byte0]: 63
2859 11:41:21.342886 [Byte1]: 63
2860 11:41:21.342985
2861 11:41:21.346232 Set Vref, RX VrefLevel [Byte0]: 64
2862 11:41:21.349673 [Byte1]: 64
2863 11:41:21.349772
2864 11:41:21.353023 Set Vref, RX VrefLevel [Byte0]: 65
2865 11:41:21.355899 [Byte1]: 65
2866 11:41:21.360269
2867 11:41:21.360366 Set Vref, RX VrefLevel [Byte0]: 66
2868 11:41:21.363378 [Byte1]: 66
2869 11:41:21.368195
2870 11:41:21.368296 Set Vref, RX VrefLevel [Byte0]: 67
2871 11:41:21.371485 [Byte1]: 67
2872 11:41:21.375968
2873 11:41:21.376063 Set Vref, RX VrefLevel [Byte0]: 68
2874 11:41:21.379271 [Byte1]: 68
2875 11:41:21.384044
2876 11:41:21.384119 Set Vref, RX VrefLevel [Byte0]: 69
2877 11:41:21.387697 [Byte1]: 69
2878 11:41:21.391752
2879 11:41:21.391822 Set Vref, RX VrefLevel [Byte0]: 70
2880 11:41:21.395738 [Byte1]: 70
2881 11:41:21.399816
2882 11:41:21.399886 Set Vref, RX VrefLevel [Byte0]: 71
2883 11:41:21.403007 [Byte1]: 71
2884 11:41:21.407908
2885 11:41:21.408007 Set Vref, RX VrefLevel [Byte0]: 72
2886 11:41:21.411121 [Byte1]: 72
2887 11:41:21.415525
2888 11:41:21.415623 Set Vref, RX VrefLevel [Byte0]: 73
2889 11:41:21.418944 [Byte1]: 73
2890 11:41:21.423388
2891 11:41:21.423482 Set Vref, RX VrefLevel [Byte0]: 74
2892 11:41:21.426878 [Byte1]: 74
2893 11:41:21.431281
2894 11:41:21.431352 Set Vref, RX VrefLevel [Byte0]: 75
2895 11:41:21.434636 [Byte1]: 75
2896 11:41:21.439410
2897 11:41:21.439510 Set Vref, RX VrefLevel [Byte0]: 76
2898 11:41:21.442873 [Byte1]: 76
2899 11:41:21.447171
2900 11:41:21.447273 Set Vref, RX VrefLevel [Byte0]: 77
2901 11:41:21.451167 [Byte1]: 77
2902 11:41:21.455411
2903 11:41:21.455509 Final RX Vref Byte 0 = 59 to rank0
2904 11:41:21.458530 Final RX Vref Byte 1 = 56 to rank0
2905 11:41:21.462024 Final RX Vref Byte 0 = 59 to rank1
2906 11:41:21.465171 Final RX Vref Byte 1 = 56 to rank1==
2907 11:41:21.468213 Dram Type= 6, Freq= 0, CH_0, rank 0
2908 11:41:21.475060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 11:41:21.475143 ==
2910 11:41:21.475208 DQS Delay:
2911 11:41:21.475268 DQS0 = 0, DQS1 = 0
2912 11:41:21.478508 DQM Delay:
2913 11:41:21.478590 DQM0 = 118, DQM1 = 108
2914 11:41:21.482114 DQ Delay:
2915 11:41:21.485108 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =114
2916 11:41:21.488213 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =124
2917 11:41:21.491862 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =100
2918 11:41:21.495219 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
2919 11:41:21.495327
2920 11:41:21.495419
2921 11:41:21.501613 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2922 11:41:21.504983 CH0 RK0: MR19=403, MR18=10FC
2923 11:41:21.511873 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2924 11:41:21.511977
2925 11:41:21.515350 ----->DramcWriteLeveling(PI) begin...
2926 11:41:21.515484 ==
2927 11:41:21.518615 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 11:41:21.524882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 11:41:21.524964 ==
2930 11:41:21.528168 Write leveling (Byte 0): 32 => 32
2931 11:41:21.528273 Write leveling (Byte 1): 30 => 30
2932 11:41:21.531273 DramcWriteLeveling(PI) end<-----
2933 11:41:21.531354
2934 11:41:21.531420 ==
2935 11:41:21.535265 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 11:41:21.541208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 11:41:21.541291 ==
2938 11:41:21.544570 [Gating] SW mode calibration
2939 11:41:21.551929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2940 11:41:21.554674 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2941 11:41:21.561777 0 15 0 | B1->B0 | 2424 3131 | 0 1 | (0 0) (1 1)
2942 11:41:21.564658 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2943 11:41:21.567989 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2944 11:41:21.574576 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2945 11:41:21.577666 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 11:41:21.580928 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 11:41:21.588472 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 11:41:21.591114 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2949 11:41:21.594182 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2950 11:41:21.600894 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2951 11:41:21.604751 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2952 11:41:21.608002 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 11:41:21.614611 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 11:41:21.617637 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 11:41:21.620739 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 11:41:21.627845 1 0 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2957 11:41:21.631059 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2958 11:41:21.634541 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 11:41:21.640797 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 11:41:21.644463 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 11:41:21.647214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 11:41:21.654100 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 11:41:21.657562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 11:41:21.660389 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2965 11:41:21.667189 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2966 11:41:21.670770 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 11:41:21.674010 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 11:41:21.677197 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 11:41:21.683726 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 11:41:21.687524 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 11:41:21.690591 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 11:41:21.697077 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 11:41:21.700419 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 11:41:21.703968 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 11:41:21.710422 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 11:41:21.713925 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:41:21.717138 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:41:21.723794 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:41:21.727296 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:41:21.730529 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2981 11:41:21.737429 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2982 11:41:21.740436 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 11:41:21.744223 Total UI for P1: 0, mck2ui 16
2984 11:41:21.747511 best dqsien dly found for B0: ( 1, 3, 30)
2985 11:41:21.750285 Total UI for P1: 0, mck2ui 16
2986 11:41:21.753658 best dqsien dly found for B1: ( 1, 4, 0)
2987 11:41:21.757019 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2988 11:41:21.760259 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2989 11:41:21.760342
2990 11:41:21.763468 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2991 11:41:21.766943 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2992 11:41:21.770062 [Gating] SW calibration Done
2993 11:41:21.770145 ==
2994 11:41:21.773387 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 11:41:21.776505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 11:41:21.779848 ==
2997 11:41:21.779931 RX Vref Scan: 0
2998 11:41:21.779997
2999 11:41:21.783531 RX Vref 0 -> 0, step: 1
3000 11:41:21.783614
3001 11:41:21.783680 RX Delay -40 -> 252, step: 8
3002 11:41:21.790295 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3003 11:41:21.793578 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3004 11:41:21.796642 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3005 11:41:21.800149 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3006 11:41:21.803291 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3007 11:41:21.810213 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3008 11:41:21.813560 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3009 11:41:21.816802 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3010 11:41:21.820054 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3011 11:41:21.823780 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3012 11:41:21.830399 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3013 11:41:21.833141 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3014 11:41:21.836463 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3015 11:41:21.840048 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3016 11:41:21.846792 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3017 11:41:21.849686 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3018 11:41:21.849761 ==
3019 11:41:21.853261 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 11:41:21.856732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 11:41:21.856806 ==
3022 11:41:21.856869 DQS Delay:
3023 11:41:21.860015 DQS0 = 0, DQS1 = 0
3024 11:41:21.860085 DQM Delay:
3025 11:41:21.863126 DQM0 = 116, DQM1 = 108
3026 11:41:21.863197 DQ Delay:
3027 11:41:21.866181 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3028 11:41:21.869542 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3029 11:41:21.873408 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3030 11:41:21.876045 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3031 11:41:21.879381
3032 11:41:21.879513
3033 11:41:21.879643 ==
3034 11:41:21.883097 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 11:41:21.886663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 11:41:21.886746 ==
3037 11:41:21.886809
3038 11:41:21.886955
3039 11:41:21.889506 TX Vref Scan disable
3040 11:41:21.889578 == TX Byte 0 ==
3041 11:41:21.896612 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3042 11:41:21.900046 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3043 11:41:21.900147 == TX Byte 1 ==
3044 11:41:21.906231 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3045 11:41:21.909255 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3046 11:41:21.909331 ==
3047 11:41:21.913464 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 11:41:21.916330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 11:41:21.916443 ==
3050 11:41:21.928590 TX Vref=22, minBit 10, minWin=25, winSum=419
3051 11:41:21.932419 TX Vref=24, minBit 2, minWin=26, winSum=426
3052 11:41:21.935296 TX Vref=26, minBit 1, minWin=26, winSum=426
3053 11:41:21.938882 TX Vref=28, minBit 8, minWin=26, winSum=428
3054 11:41:21.942174 TX Vref=30, minBit 13, minWin=25, winSum=427
3055 11:41:21.948846 TX Vref=32, minBit 12, minWin=25, winSum=428
3056 11:41:21.952306 [TxChooseVref] Worse bit 8, Min win 26, Win sum 428, Final Vref 28
3057 11:41:21.952388
3058 11:41:21.955808 Final TX Range 1 Vref 28
3059 11:41:21.955889
3060 11:41:21.955954 ==
3061 11:41:21.959003 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 11:41:21.962271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 11:41:21.965482 ==
3064 11:41:21.965578
3065 11:41:21.965644
3066 11:41:21.965705 TX Vref Scan disable
3067 11:41:21.968586 == TX Byte 0 ==
3068 11:41:21.971973 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3069 11:41:21.978296 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3070 11:41:21.978441 == TX Byte 1 ==
3071 11:41:21.981962 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3072 11:41:21.988305 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3073 11:41:21.988387
3074 11:41:21.988452 [DATLAT]
3075 11:41:21.988513 Freq=1200, CH0 RK1
3076 11:41:21.988581
3077 11:41:21.991858 DATLAT Default: 0xd
3078 11:41:21.994811 0, 0xFFFF, sum = 0
3079 11:41:21.994894 1, 0xFFFF, sum = 0
3080 11:41:21.998061 2, 0xFFFF, sum = 0
3081 11:41:21.998145 3, 0xFFFF, sum = 0
3082 11:41:22.001563 4, 0xFFFF, sum = 0
3083 11:41:22.001648 5, 0xFFFF, sum = 0
3084 11:41:22.005234 6, 0xFFFF, sum = 0
3085 11:41:22.005344 7, 0xFFFF, sum = 0
3086 11:41:22.008185 8, 0xFFFF, sum = 0
3087 11:41:22.008284 9, 0xFFFF, sum = 0
3088 11:41:22.011700 10, 0xFFFF, sum = 0
3089 11:41:22.011799 11, 0xFFFF, sum = 0
3090 11:41:22.014750 12, 0x0, sum = 1
3091 11:41:22.014834 13, 0x0, sum = 2
3092 11:41:22.018310 14, 0x0, sum = 3
3093 11:41:22.018395 15, 0x0, sum = 4
3094 11:41:22.021637 best_step = 13
3095 11:41:22.021720
3096 11:41:22.021785 ==
3097 11:41:22.024849 Dram Type= 6, Freq= 0, CH_0, rank 1
3098 11:41:22.028579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 11:41:22.028662 ==
3100 11:41:22.028728 RX Vref Scan: 0
3101 11:41:22.031249
3102 11:41:22.031331 RX Vref 0 -> 0, step: 1
3103 11:41:22.031397
3104 11:41:22.034685 RX Delay -21 -> 252, step: 4
3105 11:41:22.041323 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3106 11:41:22.044722 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3107 11:41:22.048438 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3108 11:41:22.051290 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3109 11:41:22.054762 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3110 11:41:22.061661 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3111 11:41:22.065151 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3112 11:41:22.068237 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3113 11:41:22.071357 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3114 11:41:22.074727 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3115 11:41:22.078075 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3116 11:41:22.084740 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3117 11:41:22.088171 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3118 11:41:22.091431 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3119 11:41:22.094513 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3120 11:41:22.101219 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3121 11:41:22.101302 ==
3122 11:41:22.104703 Dram Type= 6, Freq= 0, CH_0, rank 1
3123 11:41:22.107871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 11:41:22.107954 ==
3125 11:41:22.108020 DQS Delay:
3126 11:41:22.111017 DQS0 = 0, DQS1 = 0
3127 11:41:22.111099 DQM Delay:
3128 11:41:22.114536 DQM0 = 116, DQM1 = 108
3129 11:41:22.114618 DQ Delay:
3130 11:41:22.117600 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3131 11:41:22.121301 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3132 11:41:22.124109 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =102
3133 11:41:22.128023 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3134 11:41:22.128105
3135 11:41:22.128170
3136 11:41:22.137822 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3137 11:41:22.141225 CH0 RK1: MR19=403, MR18=8E4
3138 11:41:22.144545 CH0_RK1: MR19=0x403, MR18=0x8E4, DQSOSC=406, MR23=63, INC=39, DEC=26
3139 11:41:22.148238 [RxdqsGatingPostProcess] freq 1200
3140 11:41:22.154422 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3141 11:41:22.157757 best DQS0 dly(2T, 0.5T) = (0, 11)
3142 11:41:22.160934 best DQS1 dly(2T, 0.5T) = (0, 12)
3143 11:41:22.164209 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3144 11:41:22.167588 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3145 11:41:22.170959 best DQS0 dly(2T, 0.5T) = (0, 11)
3146 11:41:22.174180 best DQS1 dly(2T, 0.5T) = (0, 12)
3147 11:41:22.177634 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3148 11:41:22.180839 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3149 11:41:22.180922 Pre-setting of DQS Precalculation
3150 11:41:22.187166 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3151 11:41:22.187250 ==
3152 11:41:22.190577 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 11:41:22.193825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 11:41:22.193908 ==
3155 11:41:22.200663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3156 11:41:22.207124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3157 11:41:22.215073 [CA 0] Center 37 (7~67) winsize 61
3158 11:41:22.217830 [CA 1] Center 37 (7~68) winsize 62
3159 11:41:22.221318 [CA 2] Center 34 (4~64) winsize 61
3160 11:41:22.225030 [CA 3] Center 33 (3~64) winsize 62
3161 11:41:22.228221 [CA 4] Center 34 (4~64) winsize 61
3162 11:41:22.231481 [CA 5] Center 33 (3~64) winsize 62
3163 11:41:22.231565
3164 11:41:22.234149 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3165 11:41:22.234232
3166 11:41:22.237965 [CATrainingPosCal] consider 1 rank data
3167 11:41:22.240796 u2DelayCellTimex100 = 270/100 ps
3168 11:41:22.244059 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3169 11:41:22.250627 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3170 11:41:22.254350 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3171 11:41:22.257749 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3172 11:41:22.261229 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 11:41:22.264420 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 11:41:22.264535
3175 11:41:22.267776 CA PerBit enable=1, Macro0, CA PI delay=33
3176 11:41:22.267859
3177 11:41:22.271171 [CBTSetCACLKResult] CA Dly = 33
3178 11:41:22.273912 CS Dly: 6 (0~37)
3179 11:41:22.273995 ==
3180 11:41:22.277305 Dram Type= 6, Freq= 0, CH_1, rank 1
3181 11:41:22.280681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 11:41:22.280765 ==
3183 11:41:22.287481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3184 11:41:22.290824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3185 11:41:22.300241 [CA 0] Center 37 (7~68) winsize 62
3186 11:41:22.303475 [CA 1] Center 38 (8~68) winsize 61
3187 11:41:22.307034 [CA 2] Center 34 (4~65) winsize 62
3188 11:41:22.310497 [CA 3] Center 33 (3~64) winsize 62
3189 11:41:22.313568 [CA 4] Center 34 (3~65) winsize 63
3190 11:41:22.316805 [CA 5] Center 33 (3~64) winsize 62
3191 11:41:22.316888
3192 11:41:22.320240 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3193 11:41:22.320348
3194 11:41:22.323476 [CATrainingPosCal] consider 2 rank data
3195 11:41:22.326874 u2DelayCellTimex100 = 270/100 ps
3196 11:41:22.329939 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3197 11:41:22.337066 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3198 11:41:22.340386 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3199 11:41:22.343665 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3200 11:41:22.347065 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3201 11:41:22.350006 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 11:41:22.350088
3203 11:41:22.353807 CA PerBit enable=1, Macro0, CA PI delay=33
3204 11:41:22.353891
3205 11:41:22.357049 [CBTSetCACLKResult] CA Dly = 33
3206 11:41:22.357132 CS Dly: 7 (0~40)
3207 11:41:22.357198
3208 11:41:22.363519 ----->DramcWriteLeveling(PI) begin...
3209 11:41:22.363603 ==
3210 11:41:22.366822 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 11:41:22.370115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 11:41:22.370199 ==
3213 11:41:22.373723 Write leveling (Byte 0): 25 => 25
3214 11:41:22.376881 Write leveling (Byte 1): 27 => 27
3215 11:41:22.379685 DramcWriteLeveling(PI) end<-----
3216 11:41:22.379767
3217 11:41:22.379833 ==
3218 11:41:22.383068 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 11:41:22.386582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 11:41:22.386665 ==
3221 11:41:22.389806 [Gating] SW mode calibration
3222 11:41:22.396454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3223 11:41:22.403077 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3224 11:41:22.406623 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3225 11:41:22.409662 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3226 11:41:22.416683 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3227 11:41:22.420124 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 11:41:22.423280 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 11:41:22.430052 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 11:41:22.433551 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3231 11:41:22.436225 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
3232 11:41:22.440119 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3233 11:41:22.446425 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3234 11:41:22.449509 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 11:41:22.452989 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 11:41:22.459988 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 11:41:22.463490 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 11:41:22.466691 1 0 24 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
3239 11:41:22.472700 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3240 11:41:22.476373 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 11:41:22.479928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 11:41:22.486380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 11:41:22.489864 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 11:41:22.492808 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 11:41:22.499574 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 11:41:22.502701 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3247 11:41:22.506057 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3248 11:41:22.512512 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 11:41:22.516051 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 11:41:22.519457 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 11:41:22.525780 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 11:41:22.529200 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 11:41:22.532803 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 11:41:22.539095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 11:41:22.542663 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 11:41:22.546086 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 11:41:22.552447 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 11:41:22.556685 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 11:41:22.559429 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 11:41:22.565705 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 11:41:22.569657 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 11:41:22.572410 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3263 11:41:22.579031 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 11:41:22.579201 Total UI for P1: 0, mck2ui 16
3265 11:41:22.582414 best dqsien dly found for B0: ( 1, 3, 24)
3266 11:41:22.585759 Total UI for P1: 0, mck2ui 16
3267 11:41:22.589137 best dqsien dly found for B1: ( 1, 3, 24)
3268 11:41:22.595474 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3269 11:41:22.598823 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3270 11:41:22.598934
3271 11:41:22.602455 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3272 11:41:22.605736 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3273 11:41:22.609291 [Gating] SW calibration Done
3274 11:41:22.609373 ==
3275 11:41:22.612393 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 11:41:22.615514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 11:41:22.615605 ==
3278 11:41:22.619321 RX Vref Scan: 0
3279 11:41:22.619403
3280 11:41:22.619537 RX Vref 0 -> 0, step: 1
3281 11:41:22.619676
3282 11:41:22.622101 RX Delay -40 -> 252, step: 8
3283 11:41:22.625788 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3284 11:41:22.632670 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3285 11:41:22.635457 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3286 11:41:22.638622 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3287 11:41:22.641982 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3288 11:41:22.645684 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3289 11:41:22.648697 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3290 11:41:22.655618 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3291 11:41:22.659058 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3292 11:41:22.662362 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3293 11:41:22.665205 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3294 11:41:22.668547 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3295 11:41:22.675732 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3296 11:41:22.678682 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3297 11:41:22.681952 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3298 11:41:22.685311 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3299 11:41:22.685395 ==
3300 11:41:22.688570 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 11:41:22.695366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 11:41:22.695482 ==
3303 11:41:22.695578 DQS Delay:
3304 11:41:22.698642 DQS0 = 0, DQS1 = 0
3305 11:41:22.698760 DQM Delay:
3306 11:41:22.698854 DQM0 = 118, DQM1 = 109
3307 11:41:22.702050 DQ Delay:
3308 11:41:22.705321 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3309 11:41:22.708371 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3310 11:41:22.711775 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3311 11:41:22.714887 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3312 11:41:22.714991
3313 11:41:22.715091
3314 11:41:22.715190 ==
3315 11:41:22.718283 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 11:41:22.721439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 11:41:22.725272 ==
3318 11:41:22.725358
3319 11:41:22.725422
3320 11:41:22.725484 TX Vref Scan disable
3321 11:41:22.728582 == TX Byte 0 ==
3322 11:41:22.731557 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3323 11:41:22.735493 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3324 11:41:22.738451 == TX Byte 1 ==
3325 11:41:22.741869 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3326 11:41:22.745066 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3327 11:41:22.748293 ==
3328 11:41:22.748404 Dram Type= 6, Freq= 0, CH_1, rank 0
3329 11:41:22.755112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3330 11:41:22.755215 ==
3331 11:41:22.765614 TX Vref=22, minBit 11, minWin=24, winSum=415
3332 11:41:22.769124 TX Vref=24, minBit 8, minWin=25, winSum=422
3333 11:41:22.772275 TX Vref=26, minBit 9, minWin=25, winSum=428
3334 11:41:22.775981 TX Vref=28, minBit 9, minWin=25, winSum=429
3335 11:41:22.779208 TX Vref=30, minBit 9, minWin=25, winSum=430
3336 11:41:22.782614 TX Vref=32, minBit 9, minWin=25, winSum=424
3337 11:41:22.789299 [TxChooseVref] Worse bit 9, Min win 25, Win sum 430, Final Vref 30
3338 11:41:22.789376
3339 11:41:22.792446 Final TX Range 1 Vref 30
3340 11:41:22.792594
3341 11:41:22.792686 ==
3342 11:41:22.795780 Dram Type= 6, Freq= 0, CH_1, rank 0
3343 11:41:22.799228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3344 11:41:22.799309 ==
3345 11:41:22.802213
3346 11:41:22.802284
3347 11:41:22.802353 TX Vref Scan disable
3348 11:41:22.805700 == TX Byte 0 ==
3349 11:41:22.808858 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3350 11:41:22.815505 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3351 11:41:22.815613 == TX Byte 1 ==
3352 11:41:22.818485 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3353 11:41:22.824980 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3354 11:41:22.825056
3355 11:41:22.825118 [DATLAT]
3356 11:41:22.825177 Freq=1200, CH1 RK0
3357 11:41:22.825243
3358 11:41:22.828196 DATLAT Default: 0xd
3359 11:41:22.832154 0, 0xFFFF, sum = 0
3360 11:41:22.832259 1, 0xFFFF, sum = 0
3361 11:41:22.835322 2, 0xFFFF, sum = 0
3362 11:41:22.835429 3, 0xFFFF, sum = 0
3363 11:41:22.839092 4, 0xFFFF, sum = 0
3364 11:41:22.839197 5, 0xFFFF, sum = 0
3365 11:41:22.841860 6, 0xFFFF, sum = 0
3366 11:41:22.841948 7, 0xFFFF, sum = 0
3367 11:41:22.845542 8, 0xFFFF, sum = 0
3368 11:41:22.845623 9, 0xFFFF, sum = 0
3369 11:41:22.848277 10, 0xFFFF, sum = 0
3370 11:41:22.848359 11, 0xFFFF, sum = 0
3371 11:41:22.851699 12, 0x0, sum = 1
3372 11:41:22.851780 13, 0x0, sum = 2
3373 11:41:22.855499 14, 0x0, sum = 3
3374 11:41:22.855581 15, 0x0, sum = 4
3375 11:41:22.858159 best_step = 13
3376 11:41:22.858238
3377 11:41:22.858301 ==
3378 11:41:22.861660 Dram Type= 6, Freq= 0, CH_1, rank 0
3379 11:41:22.865401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3380 11:41:22.865482 ==
3381 11:41:22.865545 RX Vref Scan: 1
3382 11:41:22.868313
3383 11:41:22.868392 Set Vref Range= 32 -> 127
3384 11:41:22.868455
3385 11:41:22.871802 RX Vref 32 -> 127, step: 1
3386 11:41:22.871881
3387 11:41:22.874973 RX Delay -21 -> 252, step: 4
3388 11:41:22.875054
3389 11:41:22.878511 Set Vref, RX VrefLevel [Byte0]: 32
3390 11:41:22.881844 [Byte1]: 32
3391 11:41:22.881924
3392 11:41:22.885202 Set Vref, RX VrefLevel [Byte0]: 33
3393 11:41:22.888511 [Byte1]: 33
3394 11:41:22.891825
3395 11:41:22.891904 Set Vref, RX VrefLevel [Byte0]: 34
3396 11:41:22.895103 [Byte1]: 34
3397 11:41:22.899783
3398 11:41:22.899863 Set Vref, RX VrefLevel [Byte0]: 35
3399 11:41:22.903043 [Byte1]: 35
3400 11:41:22.907925
3401 11:41:22.908005 Set Vref, RX VrefLevel [Byte0]: 36
3402 11:41:22.911015 [Byte1]: 36
3403 11:41:22.915897
3404 11:41:22.915978 Set Vref, RX VrefLevel [Byte0]: 37
3405 11:41:22.918874 [Byte1]: 37
3406 11:41:22.923464
3407 11:41:22.923544 Set Vref, RX VrefLevel [Byte0]: 38
3408 11:41:22.927065 [Byte1]: 38
3409 11:41:22.931288
3410 11:41:22.931367 Set Vref, RX VrefLevel [Byte0]: 39
3411 11:41:22.934770 [Byte1]: 39
3412 11:41:22.939995
3413 11:41:22.940075 Set Vref, RX VrefLevel [Byte0]: 40
3414 11:41:22.942733 [Byte1]: 40
3415 11:41:22.947246
3416 11:41:22.947326 Set Vref, RX VrefLevel [Byte0]: 41
3417 11:41:22.950730 [Byte1]: 41
3418 11:41:22.955070
3419 11:41:22.955149 Set Vref, RX VrefLevel [Byte0]: 42
3420 11:41:22.959040 [Byte1]: 42
3421 11:41:22.963105
3422 11:41:22.963184 Set Vref, RX VrefLevel [Byte0]: 43
3423 11:41:22.966382 [Byte1]: 43
3424 11:41:22.971024
3425 11:41:22.971148 Set Vref, RX VrefLevel [Byte0]: 44
3426 11:41:22.974213 [Byte1]: 44
3427 11:41:22.978942
3428 11:41:22.979021 Set Vref, RX VrefLevel [Byte0]: 45
3429 11:41:22.982170 [Byte1]: 45
3430 11:41:22.986971
3431 11:41:22.987052 Set Vref, RX VrefLevel [Byte0]: 46
3432 11:41:22.993544 [Byte1]: 46
3433 11:41:22.993625
3434 11:41:22.996790 Set Vref, RX VrefLevel [Byte0]: 47
3435 11:41:23.000219 [Byte1]: 47
3436 11:41:23.000316
3437 11:41:23.003656 Set Vref, RX VrefLevel [Byte0]: 48
3438 11:41:23.006402 [Byte1]: 48
3439 11:41:23.010810
3440 11:41:23.010915 Set Vref, RX VrefLevel [Byte0]: 49
3441 11:41:23.014039 [Byte1]: 49
3442 11:41:23.018754
3443 11:41:23.018833 Set Vref, RX VrefLevel [Byte0]: 50
3444 11:41:23.022316 [Byte1]: 50
3445 11:41:23.026724
3446 11:41:23.026844 Set Vref, RX VrefLevel [Byte0]: 51
3447 11:41:23.029843 [Byte1]: 51
3448 11:41:23.034662
3449 11:41:23.034744 Set Vref, RX VrefLevel [Byte0]: 52
3450 11:41:23.037466 [Byte1]: 52
3451 11:41:23.042265
3452 11:41:23.042347 Set Vref, RX VrefLevel [Byte0]: 53
3453 11:41:23.045793 [Byte1]: 53
3454 11:41:23.050514
3455 11:41:23.050596 Set Vref, RX VrefLevel [Byte0]: 54
3456 11:41:23.053751 [Byte1]: 54
3457 11:41:23.058002
3458 11:41:23.058134 Set Vref, RX VrefLevel [Byte0]: 55
3459 11:41:23.061738 [Byte1]: 55
3460 11:41:23.065999
3461 11:41:23.066080 Set Vref, RX VrefLevel [Byte0]: 56
3462 11:41:23.069202 [Byte1]: 56
3463 11:41:23.073898
3464 11:41:23.073988 Set Vref, RX VrefLevel [Byte0]: 57
3465 11:41:23.077338 [Byte1]: 57
3466 11:41:23.081728
3467 11:41:23.081810 Set Vref, RX VrefLevel [Byte0]: 58
3468 11:41:23.085283 [Byte1]: 58
3469 11:41:23.090089
3470 11:41:23.090173 Set Vref, RX VrefLevel [Byte0]: 59
3471 11:41:23.093461 [Byte1]: 59
3472 11:41:23.097768
3473 11:41:23.097850 Set Vref, RX VrefLevel [Byte0]: 60
3474 11:41:23.101315 [Byte1]: 60
3475 11:41:23.105699
3476 11:41:23.105780 Set Vref, RX VrefLevel [Byte0]: 61
3477 11:41:23.108932 [Byte1]: 61
3478 11:41:23.113916
3479 11:41:23.113998 Set Vref, RX VrefLevel [Byte0]: 62
3480 11:41:23.116993 [Byte1]: 62
3481 11:41:23.121657
3482 11:41:23.121746 Set Vref, RX VrefLevel [Byte0]: 63
3483 11:41:23.124907 [Byte1]: 63
3484 11:41:23.129617
3485 11:41:23.129700 Set Vref, RX VrefLevel [Byte0]: 64
3486 11:41:23.133101 [Byte1]: 64
3487 11:41:23.137437
3488 11:41:23.137553 Set Vref, RX VrefLevel [Byte0]: 65
3489 11:41:23.140749 [Byte1]: 65
3490 11:41:23.145626
3491 11:41:23.145708 Set Vref, RX VrefLevel [Byte0]: 66
3492 11:41:23.148401 [Byte1]: 66
3493 11:41:23.153492
3494 11:41:23.153573 Set Vref, RX VrefLevel [Byte0]: 67
3495 11:41:23.157447 [Byte1]: 67
3496 11:41:23.161208
3497 11:41:23.161316 Set Vref, RX VrefLevel [Byte0]: 68
3498 11:41:23.164336 [Byte1]: 68
3499 11:41:23.169556
3500 11:41:23.169638 Final RX Vref Byte 0 = 48 to rank0
3501 11:41:23.172732 Final RX Vref Byte 1 = 54 to rank0
3502 11:41:23.175820 Final RX Vref Byte 0 = 48 to rank1
3503 11:41:23.179084 Final RX Vref Byte 1 = 54 to rank1==
3504 11:41:23.182164 Dram Type= 6, Freq= 0, CH_1, rank 0
3505 11:41:23.189232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 11:41:23.189315 ==
3507 11:41:23.189381 DQS Delay:
3508 11:41:23.192713 DQS0 = 0, DQS1 = 0
3509 11:41:23.192795 DQM Delay:
3510 11:41:23.192860 DQM0 = 116, DQM1 = 110
3511 11:41:23.196090 DQ Delay:
3512 11:41:23.198597 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3513 11:41:23.202291 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3514 11:41:23.205778 DQ8 =96, DQ9 =104, DQ10 =112, DQ11 =100
3515 11:41:23.208713 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3516 11:41:23.208795
3517 11:41:23.208860
3518 11:41:23.218884 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3519 11:41:23.218967 CH1 RK0: MR19=403, MR18=F4
3520 11:41:23.225152 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3521 11:41:23.225234
3522 11:41:23.228618 ----->DramcWriteLeveling(PI) begin...
3523 11:41:23.228701 ==
3524 11:41:23.231691 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 11:41:23.235635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 11:41:23.238877 ==
3527 11:41:23.238964 Write leveling (Byte 0): 25 => 25
3528 11:41:23.242105 Write leveling (Byte 1): 27 => 27
3529 11:41:23.245429 DramcWriteLeveling(PI) end<-----
3530 11:41:23.245511
3531 11:41:23.245577 ==
3532 11:41:23.248658 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 11:41:23.254986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 11:41:23.255069 ==
3535 11:41:23.258309 [Gating] SW mode calibration
3536 11:41:23.264844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3537 11:41:23.268081 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3538 11:41:23.274973 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3539 11:41:23.278326 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 11:41:23.281441 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 11:41:23.288216 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 11:41:23.291730 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 11:41:23.295086 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 11:41:23.301278 0 15 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (0 0)
3545 11:41:23.304667 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3546 11:41:23.308193 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 11:41:23.314562 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 11:41:23.318742 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 11:41:23.321404 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 11:41:23.327891 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 11:41:23.331474 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 11:41:23.334626 1 0 24 | B1->B0 | 3434 2525 | 1 0 | (0 0) (0 0)
3553 11:41:23.341128 1 0 28 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
3554 11:41:23.344381 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 11:41:23.347417 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 11:41:23.354522 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 11:41:23.357454 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 11:41:23.361291 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 11:41:23.364799 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 11:41:23.370891 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 11:41:23.374020 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3562 11:41:23.380674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 11:41:23.384008 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 11:41:23.387152 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 11:41:23.393931 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 11:41:23.397184 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 11:41:23.400087 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 11:41:23.406694 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 11:41:23.410216 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 11:41:23.413567 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 11:41:23.420194 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 11:41:23.423445 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 11:41:23.426552 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 11:41:23.433341 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 11:41:23.436777 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 11:41:23.439535 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3577 11:41:23.446575 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3578 11:41:23.450008 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 11:41:23.453316 Total UI for P1: 0, mck2ui 16
3580 11:41:23.456437 best dqsien dly found for B0: ( 1, 3, 26)
3581 11:41:23.459738 Total UI for P1: 0, mck2ui 16
3582 11:41:23.462918 best dqsien dly found for B1: ( 1, 3, 26)
3583 11:41:23.465941 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3584 11:41:23.469294 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3585 11:41:23.469377
3586 11:41:23.472735 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3587 11:41:23.476094 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3588 11:41:23.479910 [Gating] SW calibration Done
3589 11:41:23.479994 ==
3590 11:41:23.482904 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 11:41:23.485763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 11:41:23.488989 ==
3593 11:41:23.489072 RX Vref Scan: 0
3594 11:41:23.489139
3595 11:41:23.492327 RX Vref 0 -> 0, step: 1
3596 11:41:23.492409
3597 11:41:23.495914 RX Delay -40 -> 252, step: 8
3598 11:41:23.499043 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3599 11:41:23.502565 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3600 11:41:23.505968 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3601 11:41:23.508719 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3602 11:41:23.516077 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3603 11:41:23.518649 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3604 11:41:23.521996 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3605 11:41:23.525640 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3606 11:41:23.528757 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3607 11:41:23.535173 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3608 11:41:23.538792 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3609 11:41:23.541977 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3610 11:41:23.544966 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3611 11:41:23.548328 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3612 11:41:23.555035 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3613 11:41:23.558703 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3614 11:41:23.558787 ==
3615 11:41:23.562026 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 11:41:23.564942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 11:41:23.565026 ==
3618 11:41:23.568139 DQS Delay:
3619 11:41:23.568221 DQS0 = 0, DQS1 = 0
3620 11:41:23.571480 DQM Delay:
3621 11:41:23.571562 DQM0 = 116, DQM1 = 110
3622 11:41:23.571628 DQ Delay:
3623 11:41:23.575361 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3624 11:41:23.581454 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3625 11:41:23.584985 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3626 11:41:23.587835 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3627 11:41:23.587918
3628 11:41:23.587983
3629 11:41:23.588045 ==
3630 11:41:23.591389 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 11:41:23.594765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 11:41:23.594848 ==
3633 11:41:23.594914
3634 11:41:23.594975
3635 11:41:23.597821 TX Vref Scan disable
3636 11:41:23.601412 == TX Byte 0 ==
3637 11:41:23.604649 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3638 11:41:23.607910 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3639 11:41:23.611045 == TX Byte 1 ==
3640 11:41:23.614384 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3641 11:41:23.617832 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3642 11:41:23.617915 ==
3643 11:41:23.621092 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 11:41:23.627674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 11:41:23.627757 ==
3646 11:41:23.637807 TX Vref=22, minBit 8, minWin=25, winSum=421
3647 11:41:23.641054 TX Vref=24, minBit 3, minWin=26, winSum=428
3648 11:41:23.644362 TX Vref=26, minBit 8, minWin=26, winSum=431
3649 11:41:23.647818 TX Vref=28, minBit 9, minWin=26, winSum=434
3650 11:41:23.650829 TX Vref=30, minBit 9, minWin=26, winSum=434
3651 11:41:23.657440 TX Vref=32, minBit 8, minWin=26, winSum=429
3652 11:41:23.660712 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3653 11:41:23.660796
3654 11:41:23.663925 Final TX Range 1 Vref 28
3655 11:41:23.664008
3656 11:41:23.664073 ==
3657 11:41:23.667268 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 11:41:23.674077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 11:41:23.674160 ==
3660 11:41:23.674226
3661 11:41:23.674287
3662 11:41:23.674345 TX Vref Scan disable
3663 11:41:23.677427 == TX Byte 0 ==
3664 11:41:23.680738 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3665 11:41:23.687086 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3666 11:41:23.687171 == TX Byte 1 ==
3667 11:41:23.690610 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3668 11:41:23.697650 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3669 11:41:23.697734
3670 11:41:23.697802 [DATLAT]
3671 11:41:23.697877 Freq=1200, CH1 RK1
3672 11:41:23.697952
3673 11:41:23.700840 DATLAT Default: 0xd
3674 11:41:23.704338 0, 0xFFFF, sum = 0
3675 11:41:23.704415 1, 0xFFFF, sum = 0
3676 11:41:23.707759 2, 0xFFFF, sum = 0
3677 11:41:23.707832 3, 0xFFFF, sum = 0
3678 11:41:23.710627 4, 0xFFFF, sum = 0
3679 11:41:23.710711 5, 0xFFFF, sum = 0
3680 11:41:23.714048 6, 0xFFFF, sum = 0
3681 11:41:23.714148 7, 0xFFFF, sum = 0
3682 11:41:23.717094 8, 0xFFFF, sum = 0
3683 11:41:23.717166 9, 0xFFFF, sum = 0
3684 11:41:23.720116 10, 0xFFFF, sum = 0
3685 11:41:23.720215 11, 0xFFFF, sum = 0
3686 11:41:23.723467 12, 0x0, sum = 1
3687 11:41:23.723577 13, 0x0, sum = 2
3688 11:41:23.726757 14, 0x0, sum = 3
3689 11:41:23.726856 15, 0x0, sum = 4
3690 11:41:23.730192 best_step = 13
3691 11:41:23.730288
3692 11:41:23.730376 ==
3693 11:41:23.733736 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 11:41:23.736951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 11:41:23.737032 ==
3696 11:41:23.739972 RX Vref Scan: 0
3697 11:41:23.740069
3698 11:41:23.740158 RX Vref 0 -> 0, step: 1
3699 11:41:23.740244
3700 11:41:23.743218 RX Delay -21 -> 252, step: 4
3701 11:41:23.750136 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3702 11:41:23.753177 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3703 11:41:23.756681 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3704 11:41:23.759599 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3705 11:41:23.762948 iDelay=199, Bit 4, Center 112 (43 ~ 182) 140
3706 11:41:23.769836 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3707 11:41:23.773235 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3708 11:41:23.776228 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3709 11:41:23.779583 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3710 11:41:23.783132 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3711 11:41:23.789361 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3712 11:41:23.792482 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3713 11:41:23.796327 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3714 11:41:23.799665 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3715 11:41:23.806173 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3716 11:41:23.809676 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3717 11:41:23.809775 ==
3718 11:41:23.812458 Dram Type= 6, Freq= 0, CH_1, rank 1
3719 11:41:23.815750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3720 11:41:23.815826 ==
3721 11:41:23.818974 DQS Delay:
3722 11:41:23.819045 DQS0 = 0, DQS1 = 0
3723 11:41:23.819107 DQM Delay:
3724 11:41:23.822324 DQM0 = 116, DQM1 = 110
3725 11:41:23.822420 DQ Delay:
3726 11:41:23.825490 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =112
3727 11:41:23.828735 DQ4 =112, DQ5 =128, DQ6 =130, DQ7 =114
3728 11:41:23.832433 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3729 11:41:23.839107 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3730 11:41:23.839218
3731 11:41:23.839313
3732 11:41:23.845768 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0eb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
3733 11:41:23.848328 CH1 RK1: MR19=303, MR18=F0EB
3734 11:41:23.855668 CH1_RK1: MR19=0x303, MR18=0xF0EB, DQSOSC=416, MR23=63, INC=37, DEC=25
3735 11:41:23.858437 [RxdqsGatingPostProcess] freq 1200
3736 11:41:23.865184 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3737 11:41:23.865288 best DQS0 dly(2T, 0.5T) = (0, 11)
3738 11:41:23.868432 best DQS1 dly(2T, 0.5T) = (0, 11)
3739 11:41:23.871601 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3740 11:41:23.875480 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3741 11:41:23.878814 best DQS0 dly(2T, 0.5T) = (0, 11)
3742 11:41:23.881917 best DQS1 dly(2T, 0.5T) = (0, 11)
3743 11:41:23.885436 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3744 11:41:23.888181 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3745 11:41:23.891615 Pre-setting of DQS Precalculation
3746 11:41:23.898273 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3747 11:41:23.904698 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3748 11:41:23.911137 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3749 11:41:23.911240
3750 11:41:23.911334
3751 11:41:23.914630 [Calibration Summary] 2400 Mbps
3752 11:41:23.914703 CH 0, Rank 0
3753 11:41:23.917893 SW Impedance : PASS
3754 11:41:23.921556 DUTY Scan : NO K
3755 11:41:23.921627 ZQ Calibration : PASS
3756 11:41:23.924312 Jitter Meter : NO K
3757 11:41:23.927701 CBT Training : PASS
3758 11:41:23.927773 Write leveling : PASS
3759 11:41:23.931008 RX DQS gating : PASS
3760 11:41:23.931080 RX DQ/DQS(RDDQC) : PASS
3761 11:41:23.934538 TX DQ/DQS : PASS
3762 11:41:23.937960 RX DATLAT : PASS
3763 11:41:23.938037 RX DQ/DQS(Engine): PASS
3764 11:41:23.941392 TX OE : NO K
3765 11:41:23.941466 All Pass.
3766 11:41:23.941528
3767 11:41:23.944324 CH 0, Rank 1
3768 11:41:23.944421 SW Impedance : PASS
3769 11:41:23.947278 DUTY Scan : NO K
3770 11:41:23.950654 ZQ Calibration : PASS
3771 11:41:23.950726 Jitter Meter : NO K
3772 11:41:23.954106 CBT Training : PASS
3773 11:41:23.957412 Write leveling : PASS
3774 11:41:23.957510 RX DQS gating : PASS
3775 11:41:23.960795 RX DQ/DQS(RDDQC) : PASS
3776 11:41:23.964301 TX DQ/DQS : PASS
3777 11:41:23.964402 RX DATLAT : PASS
3778 11:41:23.967258 RX DQ/DQS(Engine): PASS
3779 11:41:23.970710 TX OE : NO K
3780 11:41:23.970783 All Pass.
3781 11:41:23.970844
3782 11:41:23.970903 CH 1, Rank 0
3783 11:41:23.973733 SW Impedance : PASS
3784 11:41:23.977543 DUTY Scan : NO K
3785 11:41:23.977643 ZQ Calibration : PASS
3786 11:41:23.980927 Jitter Meter : NO K
3787 11:41:23.983985 CBT Training : PASS
3788 11:41:23.984058 Write leveling : PASS
3789 11:41:23.987264 RX DQS gating : PASS
3790 11:41:23.990275 RX DQ/DQS(RDDQC) : PASS
3791 11:41:23.990347 TX DQ/DQS : PASS
3792 11:41:23.993994 RX DATLAT : PASS
3793 11:41:23.996991 RX DQ/DQS(Engine): PASS
3794 11:41:23.997062 TX OE : NO K
3795 11:41:24.000740 All Pass.
3796 11:41:24.000813
3797 11:41:24.000875 CH 1, Rank 1
3798 11:41:24.003609 SW Impedance : PASS
3799 11:41:24.003679 DUTY Scan : NO K
3800 11:41:24.007063 ZQ Calibration : PASS
3801 11:41:24.010071 Jitter Meter : NO K
3802 11:41:24.010170 CBT Training : PASS
3803 11:41:24.013601 Write leveling : PASS
3804 11:41:24.013674 RX DQS gating : PASS
3805 11:41:24.016788 RX DQ/DQS(RDDQC) : PASS
3806 11:41:24.020126 TX DQ/DQS : PASS
3807 11:41:24.020224 RX DATLAT : PASS
3808 11:41:24.023561 RX DQ/DQS(Engine): PASS
3809 11:41:24.026465 TX OE : NO K
3810 11:41:24.026536 All Pass.
3811 11:41:24.026596
3812 11:41:24.030478 DramC Write-DBI off
3813 11:41:24.030546 PER_BANK_REFRESH: Hybrid Mode
3814 11:41:24.033287 TX_TRACKING: ON
3815 11:41:24.043091 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3816 11:41:24.046165 [FAST_K] Save calibration result to emmc
3817 11:41:24.049719 dramc_set_vcore_voltage set vcore to 650000
3818 11:41:24.052698 Read voltage for 600, 5
3819 11:41:24.052769 Vio18 = 0
3820 11:41:24.052831 Vcore = 650000
3821 11:41:24.055989 Vdram = 0
3822 11:41:24.056059 Vddq = 0
3823 11:41:24.056120 Vmddr = 0
3824 11:41:24.062581 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3825 11:41:24.065982 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3826 11:41:24.069633 MEM_TYPE=3, freq_sel=19
3827 11:41:24.072962 sv_algorithm_assistance_LP4_1600
3828 11:41:24.075790 ============ PULL DRAM RESETB DOWN ============
3829 11:41:24.079469 ========== PULL DRAM RESETB DOWN end =========
3830 11:41:24.085726 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 11:41:24.089456 ===================================
3832 11:41:24.092358 LPDDR4 DRAM CONFIGURATION
3833 11:41:24.095587 ===================================
3834 11:41:24.095672 EX_ROW_EN[0] = 0x0
3835 11:41:24.099064 EX_ROW_EN[1] = 0x0
3836 11:41:24.099165 LP4Y_EN = 0x0
3837 11:41:24.102308 WORK_FSP = 0x0
3838 11:41:24.102405 WL = 0x2
3839 11:41:24.105545 RL = 0x2
3840 11:41:24.105641 BL = 0x2
3841 11:41:24.108779 RPST = 0x0
3842 11:41:24.108853 RD_PRE = 0x0
3843 11:41:24.112189 WR_PRE = 0x1
3844 11:41:24.112284 WR_PST = 0x0
3845 11:41:24.115384 DBI_WR = 0x0
3846 11:41:24.115482 DBI_RD = 0x0
3847 11:41:24.118987 OTF = 0x1
3848 11:41:24.122366 ===================================
3849 11:41:24.125456 ===================================
3850 11:41:24.125554 ANA top config
3851 11:41:24.128484 ===================================
3852 11:41:24.132017 DLL_ASYNC_EN = 0
3853 11:41:24.135447 ALL_SLAVE_EN = 1
3854 11:41:24.138613 NEW_RANK_MODE = 1
3855 11:41:24.138719 DLL_IDLE_MODE = 1
3856 11:41:24.141771 LP45_APHY_COMB_EN = 1
3857 11:41:24.145246 TX_ODT_DIS = 1
3858 11:41:24.148288 NEW_8X_MODE = 1
3859 11:41:24.151720 ===================================
3860 11:41:24.154913 ===================================
3861 11:41:24.158341 data_rate = 1200
3862 11:41:24.161739 CKR = 1
3863 11:41:24.161852 DQ_P2S_RATIO = 8
3864 11:41:24.164950 ===================================
3865 11:41:24.168171 CA_P2S_RATIO = 8
3866 11:41:24.171391 DQ_CA_OPEN = 0
3867 11:41:24.174809 DQ_SEMI_OPEN = 0
3868 11:41:24.178702 CA_SEMI_OPEN = 0
3869 11:41:24.181546 CA_FULL_RATE = 0
3870 11:41:24.181628 DQ_CKDIV4_EN = 1
3871 11:41:24.184750 CA_CKDIV4_EN = 1
3872 11:41:24.188425 CA_PREDIV_EN = 0
3873 11:41:24.191310 PH8_DLY = 0
3874 11:41:24.194502 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3875 11:41:24.198344 DQ_AAMCK_DIV = 4
3876 11:41:24.198447 CA_AAMCK_DIV = 4
3877 11:41:24.201053 CA_ADMCK_DIV = 4
3878 11:41:24.204885 DQ_TRACK_CA_EN = 0
3879 11:41:24.207635 CA_PICK = 600
3880 11:41:24.211321 CA_MCKIO = 600
3881 11:41:24.214639 MCKIO_SEMI = 0
3882 11:41:24.217754 PLL_FREQ = 2288
3883 11:41:24.217840 DQ_UI_PI_RATIO = 32
3884 11:41:24.221347 CA_UI_PI_RATIO = 0
3885 11:41:24.224304 ===================================
3886 11:41:24.227737 ===================================
3887 11:41:24.231095 memory_type:LPDDR4
3888 11:41:24.234336 GP_NUM : 10
3889 11:41:24.234418 SRAM_EN : 1
3890 11:41:24.237911 MD32_EN : 0
3891 11:41:24.241038 ===================================
3892 11:41:24.244360 [ANA_INIT] >>>>>>>>>>>>>>
3893 11:41:24.244441 <<<<<< [CONFIGURE PHASE]: ANA_TX
3894 11:41:24.250905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3895 11:41:24.254236 ===================================
3896 11:41:24.254343 data_rate = 1200,PCW = 0X5800
3897 11:41:24.257470 ===================================
3898 11:41:24.260903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3899 11:41:24.267288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3900 11:41:24.274129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 11:41:24.277557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3902 11:41:24.280623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3903 11:41:24.283809 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3904 11:41:24.286933 [ANA_INIT] flow start
3905 11:41:24.290667 [ANA_INIT] PLL >>>>>>>>
3906 11:41:24.290749 [ANA_INIT] PLL <<<<<<<<
3907 11:41:24.293856 [ANA_INIT] MIDPI >>>>>>>>
3908 11:41:24.297136 [ANA_INIT] MIDPI <<<<<<<<
3909 11:41:24.297226 [ANA_INIT] DLL >>>>>>>>
3910 11:41:24.300190 [ANA_INIT] flow end
3911 11:41:24.303751 ============ LP4 DIFF to SE enter ============
3912 11:41:24.306663 ============ LP4 DIFF to SE exit ============
3913 11:41:24.310139 [ANA_INIT] <<<<<<<<<<<<<
3914 11:41:24.313586 [Flow] Enable top DCM control >>>>>
3915 11:41:24.316846 [Flow] Enable top DCM control <<<<<
3916 11:41:24.319991 Enable DLL master slave shuffle
3917 11:41:24.327064 ==============================================================
3918 11:41:24.327165 Gating Mode config
3919 11:41:24.333091 ==============================================================
3920 11:41:24.336479 Config description:
3921 11:41:24.342944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3922 11:41:24.349568 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3923 11:41:24.356237 SELPH_MODE 0: By rank 1: By Phase
3924 11:41:24.362843 ==============================================================
3925 11:41:24.362926 GAT_TRACK_EN = 1
3926 11:41:24.366044 RX_GATING_MODE = 2
3927 11:41:24.369356 RX_GATING_TRACK_MODE = 2
3928 11:41:24.372443 SELPH_MODE = 1
3929 11:41:24.376057 PICG_EARLY_EN = 1
3930 11:41:24.379589 VALID_LAT_VALUE = 1
3931 11:41:24.385739 ==============================================================
3932 11:41:24.389418 Enter into Gating configuration >>>>
3933 11:41:24.392374 Exit from Gating configuration <<<<
3934 11:41:24.396108 Enter into DVFS_PRE_config >>>>>
3935 11:41:24.405661 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3936 11:41:24.409300 Exit from DVFS_PRE_config <<<<<
3937 11:41:24.412709 Enter into PICG configuration >>>>
3938 11:41:24.415941 Exit from PICG configuration <<<<
3939 11:41:24.419033 [RX_INPUT] configuration >>>>>
3940 11:41:24.422409 [RX_INPUT] configuration <<<<<
3941 11:41:24.426001 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3942 11:41:24.432258 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3943 11:41:24.438997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3944 11:41:24.445683 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3945 11:41:24.448661 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3946 11:41:24.455421 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3947 11:41:24.458598 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3948 11:41:24.465288 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3949 11:41:24.468510 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3950 11:41:24.471719 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3951 11:41:24.474886 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3952 11:41:24.481782 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 11:41:24.484960 ===================================
3954 11:41:24.487931 LPDDR4 DRAM CONFIGURATION
3955 11:41:24.491374 ===================================
3956 11:41:24.491456 EX_ROW_EN[0] = 0x0
3957 11:41:24.494555 EX_ROW_EN[1] = 0x0
3958 11:41:24.494665 LP4Y_EN = 0x0
3959 11:41:24.498479 WORK_FSP = 0x0
3960 11:41:24.498560 WL = 0x2
3961 11:41:24.501619 RL = 0x2
3962 11:41:24.501718 BL = 0x2
3963 11:41:24.504889 RPST = 0x0
3964 11:41:24.504997 RD_PRE = 0x0
3965 11:41:24.507950 WR_PRE = 0x1
3966 11:41:24.508059 WR_PST = 0x0
3967 11:41:24.511176 DBI_WR = 0x0
3968 11:41:24.511250 DBI_RD = 0x0
3969 11:41:24.514403 OTF = 0x1
3970 11:41:24.518006 ===================================
3971 11:41:24.521127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3972 11:41:24.524490 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3973 11:41:24.531078 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3974 11:41:24.534590 ===================================
3975 11:41:24.537580 LPDDR4 DRAM CONFIGURATION
3976 11:41:24.540800 ===================================
3977 11:41:24.540893 EX_ROW_EN[0] = 0x10
3978 11:41:24.544080 EX_ROW_EN[1] = 0x0
3979 11:41:24.544186 LP4Y_EN = 0x0
3980 11:41:24.547462 WORK_FSP = 0x0
3981 11:41:24.547549 WL = 0x2
3982 11:41:24.550747 RL = 0x2
3983 11:41:24.550829 BL = 0x2
3984 11:41:24.554439 RPST = 0x0
3985 11:41:24.554521 RD_PRE = 0x0
3986 11:41:24.557480 WR_PRE = 0x1
3987 11:41:24.557561 WR_PST = 0x0
3988 11:41:24.561020 DBI_WR = 0x0
3989 11:41:24.561102 DBI_RD = 0x0
3990 11:41:24.563855 OTF = 0x1
3991 11:41:24.567401 ===================================
3992 11:41:24.573876 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3993 11:41:24.577414 nWR fixed to 30
3994 11:41:24.580646 [ModeRegInit_LP4] CH0 RK0
3995 11:41:24.580728 [ModeRegInit_LP4] CH0 RK1
3996 11:41:24.583790 [ModeRegInit_LP4] CH1 RK0
3997 11:41:24.587018 [ModeRegInit_LP4] CH1 RK1
3998 11:41:24.587100 match AC timing 17
3999 11:41:24.594053 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4000 11:41:24.597317 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4001 11:41:24.600402 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4002 11:41:24.607062 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4003 11:41:24.610251 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4004 11:41:24.610354 ==
4005 11:41:24.613553 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 11:41:24.616768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 11:41:24.616850 ==
4008 11:41:24.623399 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 11:41:24.630345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4010 11:41:24.633480 [CA 0] Center 36 (6~66) winsize 61
4011 11:41:24.636727 [CA 1] Center 36 (6~66) winsize 61
4012 11:41:24.639992 [CA 2] Center 34 (4~65) winsize 62
4013 11:41:24.643264 [CA 3] Center 34 (4~65) winsize 62
4014 11:41:24.646705 [CA 4] Center 34 (4~64) winsize 61
4015 11:41:24.649777 [CA 5] Center 33 (3~64) winsize 62
4016 11:41:24.649859
4017 11:41:24.653328 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4018 11:41:24.653409
4019 11:41:24.656350 [CATrainingPosCal] consider 1 rank data
4020 11:41:24.660326 u2DelayCellTimex100 = 270/100 ps
4021 11:41:24.663177 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 11:41:24.666375 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 11:41:24.669890 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4024 11:41:24.673045 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4025 11:41:24.679720 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4026 11:41:24.683271 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 11:41:24.683353
4028 11:41:24.686616 CA PerBit enable=1, Macro0, CA PI delay=33
4029 11:41:24.686699
4030 11:41:24.689618 [CBTSetCACLKResult] CA Dly = 33
4031 11:41:24.689701 CS Dly: 5 (0~36)
4032 11:41:24.689768 ==
4033 11:41:24.692714 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 11:41:24.699344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 11:41:24.699427 ==
4036 11:41:24.702596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4037 11:41:24.709231 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4038 11:41:24.712919 [CA 0] Center 36 (6~66) winsize 61
4039 11:41:24.716025 [CA 1] Center 36 (6~66) winsize 61
4040 11:41:24.719374 [CA 2] Center 33 (3~64) winsize 62
4041 11:41:24.722877 [CA 3] Center 33 (3~64) winsize 62
4042 11:41:24.725851 [CA 4] Center 33 (3~64) winsize 62
4043 11:41:24.729289 [CA 5] Center 33 (2~64) winsize 63
4044 11:41:24.729372
4045 11:41:24.732510 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4046 11:41:24.732632
4047 11:41:24.736058 [CATrainingPosCal] consider 2 rank data
4048 11:41:24.739148 u2DelayCellTimex100 = 270/100 ps
4049 11:41:24.742176 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4050 11:41:24.749427 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4051 11:41:24.752028 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4052 11:41:24.755359 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4053 11:41:24.758736 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4054 11:41:24.762530 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4055 11:41:24.762613
4056 11:41:24.765524 CA PerBit enable=1, Macro0, CA PI delay=33
4057 11:41:24.765607
4058 11:41:24.768784 [CBTSetCACLKResult] CA Dly = 33
4059 11:41:24.772134 CS Dly: 5 (0~37)
4060 11:41:24.772216
4061 11:41:24.775240 ----->DramcWriteLeveling(PI) begin...
4062 11:41:24.775325 ==
4063 11:41:24.778741 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 11:41:24.782386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 11:41:24.782469 ==
4066 11:41:24.785493 Write leveling (Byte 0): 36 => 36
4067 11:41:24.788583 Write leveling (Byte 1): 30 => 30
4068 11:41:24.792116 DramcWriteLeveling(PI) end<-----
4069 11:41:24.792198
4070 11:41:24.792264 ==
4071 11:41:24.795531 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 11:41:24.798471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 11:41:24.798582 ==
4074 11:41:24.801844 [Gating] SW mode calibration
4075 11:41:24.808238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4076 11:41:24.815220 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4077 11:41:24.818130 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4078 11:41:24.821395 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 11:41:24.828181 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 11:41:24.831433 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4081 11:41:24.834697 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4082 11:41:24.841563 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 11:41:24.844647 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 11:41:24.848033 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 11:41:24.854719 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 11:41:24.857981 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 11:41:24.861364 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 11:41:24.867562 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4089 11:41:24.870818 0 10 16 | B1->B0 | 3130 4646 | 1 0 | (0 0) (0 0)
4090 11:41:24.874126 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 11:41:24.880838 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 11:41:24.883972 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 11:41:24.887670 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 11:41:24.894143 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 11:41:24.897540 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 11:41:24.901084 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4097 11:41:24.906974 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 11:41:24.910520 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 11:41:24.913725 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 11:41:24.920651 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 11:41:24.923762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 11:41:24.927368 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 11:41:24.933411 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 11:41:24.937135 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 11:41:24.940348 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 11:41:24.946635 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 11:41:24.949847 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 11:41:24.953657 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 11:41:24.960700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 11:41:24.963425 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 11:41:24.966686 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 11:41:24.973096 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 11:41:24.976476 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4114 11:41:24.979743 Total UI for P1: 0, mck2ui 16
4115 11:41:24.983148 best dqsien dly found for B0: ( 0, 13, 14)
4116 11:41:24.986309 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4117 11:41:24.990064 Total UI for P1: 0, mck2ui 16
4118 11:41:24.992899 best dqsien dly found for B1: ( 0, 13, 16)
4119 11:41:24.996568 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4120 11:41:24.999491 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4121 11:41:25.002849
4122 11:41:25.006586 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4123 11:41:25.009559 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4124 11:41:25.012941 [Gating] SW calibration Done
4125 11:41:25.013043 ==
4126 11:41:25.016007 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 11:41:25.019803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 11:41:25.019875 ==
4129 11:41:25.019936 RX Vref Scan: 0
4130 11:41:25.022862
4131 11:41:25.022931 RX Vref 0 -> 0, step: 1
4132 11:41:25.022991
4133 11:41:25.026138 RX Delay -230 -> 252, step: 16
4134 11:41:25.029359 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4135 11:41:25.036070 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4136 11:41:25.039486 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4137 11:41:25.042480 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4138 11:41:25.045680 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4139 11:41:25.049583 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4140 11:41:25.055966 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4141 11:41:25.059313 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4142 11:41:25.062878 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4143 11:41:25.066031 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4144 11:41:25.072293 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4145 11:41:25.076178 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4146 11:41:25.078959 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4147 11:41:25.082092 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4148 11:41:25.089249 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4149 11:41:25.091953 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4150 11:41:25.092035 ==
4151 11:41:25.095559 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 11:41:25.098642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 11:41:25.098724 ==
4154 11:41:25.102101 DQS Delay:
4155 11:41:25.102183 DQS0 = 0, DQS1 = 0
4156 11:41:25.102248 DQM Delay:
4157 11:41:25.105307 DQM0 = 41, DQM1 = 30
4158 11:41:25.105389 DQ Delay:
4159 11:41:25.108667 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4160 11:41:25.112073 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4161 11:41:25.115149 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4162 11:41:25.118738 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4163 11:41:25.118820
4164 11:41:25.118885
4165 11:41:25.118945 ==
4166 11:41:25.121778 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 11:41:25.128375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 11:41:25.128459 ==
4169 11:41:25.128531
4170 11:41:25.128650
4171 11:41:25.131532 TX Vref Scan disable
4172 11:41:25.131613 == TX Byte 0 ==
4173 11:41:25.138034 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4174 11:41:25.141433 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4175 11:41:25.141513 == TX Byte 1 ==
4176 11:41:25.148267 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4177 11:41:25.151265 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4178 11:41:25.151366 ==
4179 11:41:25.154573 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 11:41:25.157697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 11:41:25.157797 ==
4182 11:41:25.157888
4183 11:41:25.157976
4184 11:41:25.161542 TX Vref Scan disable
4185 11:41:25.164335 == TX Byte 0 ==
4186 11:41:25.167743 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4187 11:41:25.171082 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4188 11:41:25.174253 == TX Byte 1 ==
4189 11:41:25.177976 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4190 11:41:25.180969 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4191 11:41:25.184319
4192 11:41:25.184424 [DATLAT]
4193 11:41:25.184569 Freq=600, CH0 RK0
4194 11:41:25.184672
4195 11:41:25.187643 DATLAT Default: 0x9
4196 11:41:25.187738 0, 0xFFFF, sum = 0
4197 11:41:25.190893 1, 0xFFFF, sum = 0
4198 11:41:25.190989 2, 0xFFFF, sum = 0
4199 11:41:25.194333 3, 0xFFFF, sum = 0
4200 11:41:25.194430 4, 0xFFFF, sum = 0
4201 11:41:25.197520 5, 0xFFFF, sum = 0
4202 11:41:25.197624 6, 0xFFFF, sum = 0
4203 11:41:25.200924 7, 0xFFFF, sum = 0
4204 11:41:25.201022 8, 0x0, sum = 1
4205 11:41:25.204184 9, 0x0, sum = 2
4206 11:41:25.204255 10, 0x0, sum = 3
4207 11:41:25.207429 11, 0x0, sum = 4
4208 11:41:25.207540 best_step = 9
4209 11:41:25.207645
4210 11:41:25.207738 ==
4211 11:41:25.210999 Dram Type= 6, Freq= 0, CH_0, rank 0
4212 11:41:25.217540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 11:41:25.217640 ==
4214 11:41:25.217709 RX Vref Scan: 1
4215 11:41:25.217768
4216 11:41:25.220610 RX Vref 0 -> 0, step: 1
4217 11:41:25.220694
4218 11:41:25.223898 RX Delay -195 -> 252, step: 8
4219 11:41:25.223968
4220 11:41:25.227161 Set Vref, RX VrefLevel [Byte0]: 59
4221 11:41:25.230438 [Byte1]: 56
4222 11:41:25.230544
4223 11:41:25.234060 Final RX Vref Byte 0 = 59 to rank0
4224 11:41:25.237098 Final RX Vref Byte 1 = 56 to rank0
4225 11:41:25.240804 Final RX Vref Byte 0 = 59 to rank1
4226 11:41:25.243822 Final RX Vref Byte 1 = 56 to rank1==
4227 11:41:25.246920 Dram Type= 6, Freq= 0, CH_0, rank 0
4228 11:41:25.250505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 11:41:25.250608 ==
4230 11:41:25.253561 DQS Delay:
4231 11:41:25.253672 DQS0 = 0, DQS1 = 0
4232 11:41:25.256763 DQM Delay:
4233 11:41:25.256880 DQM0 = 43, DQM1 = 33
4234 11:41:25.256974 DQ Delay:
4235 11:41:25.260127 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4236 11:41:25.263911 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4237 11:41:25.266929 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4238 11:41:25.269906 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4239 11:41:25.270022
4240 11:41:25.270120
4241 11:41:25.280126 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c34, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
4242 11:41:25.283194 CH0 RK0: MR19=808, MR18=5C34
4243 11:41:25.290000 CH0_RK0: MR19=0x808, MR18=0x5C34, DQSOSC=392, MR23=63, INC=170, DEC=113
4244 11:41:25.290117
4245 11:41:25.292837 ----->DramcWriteLeveling(PI) begin...
4246 11:41:25.292940 ==
4247 11:41:25.296204 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 11:41:25.299566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 11:41:25.299673 ==
4250 11:41:25.302972 Write leveling (Byte 0): 33 => 33
4251 11:41:25.307094 Write leveling (Byte 1): 30 => 30
4252 11:41:25.309720 DramcWriteLeveling(PI) end<-----
4253 11:41:25.309829
4254 11:41:25.309948 ==
4255 11:41:25.312875 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 11:41:25.316057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 11:41:25.316169 ==
4258 11:41:25.319325 [Gating] SW mode calibration
4259 11:41:25.326389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4260 11:41:25.332892 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4261 11:41:25.336139 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 11:41:25.342537 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 11:41:25.346488 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4264 11:41:25.349354 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4265 11:41:25.355724 0 9 16 | B1->B0 | 3030 2c2c | 1 0 | (0 0) (0 0)
4266 11:41:25.358898 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 11:41:25.362120 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 11:41:25.368670 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 11:41:25.372101 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 11:41:25.375227 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 11:41:25.382239 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 11:41:25.385426 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4273 11:41:25.388631 0 10 16 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
4274 11:41:25.395019 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 11:41:25.398535 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 11:41:25.401819 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 11:41:25.408111 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 11:41:25.411755 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 11:41:25.414909 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 11:41:25.421453 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4281 11:41:25.424605 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4282 11:41:25.427949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 11:41:25.434740 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 11:41:25.437889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 11:41:25.441186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 11:41:25.447924 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 11:41:25.451339 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 11:41:25.454830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 11:41:25.460999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 11:41:25.464573 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 11:41:25.467547 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 11:41:25.474458 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 11:41:25.477724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 11:41:25.480941 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 11:41:25.484366 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 11:41:25.491337 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4297 11:41:25.494032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 11:41:25.497695 Total UI for P1: 0, mck2ui 16
4299 11:41:25.500916 best dqsien dly found for B0: ( 0, 13, 12)
4300 11:41:25.503814 Total UI for P1: 0, mck2ui 16
4301 11:41:25.507292 best dqsien dly found for B1: ( 0, 13, 12)
4302 11:41:25.510453 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4303 11:41:25.513983 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4304 11:41:25.514060
4305 11:41:25.517123 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4306 11:41:25.523767 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4307 11:41:25.523848 [Gating] SW calibration Done
4308 11:41:25.527658 ==
4309 11:41:25.527741 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 11:41:25.534090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 11:41:25.534173 ==
4312 11:41:25.534238 RX Vref Scan: 0
4313 11:41:25.534300
4314 11:41:25.536907 RX Vref 0 -> 0, step: 1
4315 11:41:25.536989
4316 11:41:25.540799 RX Delay -230 -> 252, step: 16
4317 11:41:25.543771 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4318 11:41:25.547014 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4319 11:41:25.553793 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4320 11:41:25.557048 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4321 11:41:25.560054 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4322 11:41:25.563721 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4323 11:41:25.570086 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4324 11:41:25.573344 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4325 11:41:25.576487 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4326 11:41:25.580303 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4327 11:41:25.583250 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4328 11:41:25.590040 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4329 11:41:25.593069 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4330 11:41:25.596375 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4331 11:41:25.599980 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4332 11:41:25.606516 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4333 11:41:25.606598 ==
4334 11:41:25.610004 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 11:41:25.613026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 11:41:25.613109 ==
4337 11:41:25.613175 DQS Delay:
4338 11:41:25.616174 DQS0 = 0, DQS1 = 0
4339 11:41:25.616255 DQM Delay:
4340 11:41:25.620132 DQM0 = 44, DQM1 = 37
4341 11:41:25.620259 DQ Delay:
4342 11:41:25.623246 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4343 11:41:25.626511 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4344 11:41:25.629723 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =41
4345 11:41:25.632902 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4346 11:41:25.632985
4347 11:41:25.633051
4348 11:41:25.633144 ==
4349 11:41:25.636425 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 11:41:25.639534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 11:41:25.642793 ==
4352 11:41:25.642892
4353 11:41:25.643020
4354 11:41:25.643113 TX Vref Scan disable
4355 11:41:25.646064 == TX Byte 0 ==
4356 11:41:25.649530 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4357 11:41:25.656320 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4358 11:41:25.656420 == TX Byte 1 ==
4359 11:41:25.659115 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4360 11:41:25.665888 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4361 11:41:25.665970 ==
4362 11:41:25.669106 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 11:41:25.672808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 11:41:25.672890 ==
4365 11:41:25.672955
4366 11:41:25.673014
4367 11:41:25.675845 TX Vref Scan disable
4368 11:41:25.679178 == TX Byte 0 ==
4369 11:41:25.682076 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4370 11:41:25.685428 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4371 11:41:25.688743 == TX Byte 1 ==
4372 11:41:25.692083 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4373 11:41:25.695311 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4374 11:41:25.695392
4375 11:41:25.698659 [DATLAT]
4376 11:41:25.698740 Freq=600, CH0 RK1
4377 11:41:25.698811
4378 11:41:25.702154 DATLAT Default: 0x9
4379 11:41:25.702235 0, 0xFFFF, sum = 0
4380 11:41:25.705596 1, 0xFFFF, sum = 0
4381 11:41:25.705678 2, 0xFFFF, sum = 0
4382 11:41:25.708483 3, 0xFFFF, sum = 0
4383 11:41:25.708614 4, 0xFFFF, sum = 0
4384 11:41:25.711903 5, 0xFFFF, sum = 0
4385 11:41:25.711985 6, 0xFFFF, sum = 0
4386 11:41:25.715668 7, 0xFFFF, sum = 0
4387 11:41:25.715749 8, 0x0, sum = 1
4388 11:41:25.719022 9, 0x0, sum = 2
4389 11:41:25.719103 10, 0x0, sum = 3
4390 11:41:25.722280 11, 0x0, sum = 4
4391 11:41:25.722362 best_step = 9
4392 11:41:25.722426
4393 11:41:25.722486 ==
4394 11:41:25.724972 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 11:41:25.728306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 11:41:25.728403 ==
4397 11:41:25.732324 RX Vref Scan: 0
4398 11:41:25.732403
4399 11:41:25.734858 RX Vref 0 -> 0, step: 1
4400 11:41:25.734938
4401 11:41:25.738427 RX Delay -195 -> 252, step: 8
4402 11:41:25.741519 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4403 11:41:25.744754 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4404 11:41:25.751311 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4405 11:41:25.755034 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4406 11:41:25.758259 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4407 11:41:25.761381 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4408 11:41:25.767980 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4409 11:41:25.771360 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4410 11:41:25.774643 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4411 11:41:25.777667 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4412 11:41:25.781512 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4413 11:41:25.787679 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4414 11:41:25.791348 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4415 11:41:25.794346 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4416 11:41:25.800775 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4417 11:41:25.804316 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4418 11:41:25.804466 ==
4419 11:41:25.807548 Dram Type= 6, Freq= 0, CH_0, rank 1
4420 11:41:25.810959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 11:41:25.811040 ==
4422 11:41:25.814245 DQS Delay:
4423 11:41:25.814324 DQS0 = 0, DQS1 = 0
4424 11:41:25.814387 DQM Delay:
4425 11:41:25.817694 DQM0 = 41, DQM1 = 36
4426 11:41:25.817773 DQ Delay:
4427 11:41:25.820499 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =40
4428 11:41:25.824133 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4429 11:41:25.827129 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4430 11:41:25.830311 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4431 11:41:25.830385
4432 11:41:25.830447
4433 11:41:25.840115 [DQSOSCAuto] RK1, (LSB)MR18= 0x570b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
4434 11:41:25.843718 CH0 RK1: MR19=808, MR18=570B
4435 11:41:25.847007 CH0_RK1: MR19=0x808, MR18=0x570B, DQSOSC=393, MR23=63, INC=169, DEC=113
4436 11:41:25.850432 [RxdqsGatingPostProcess] freq 600
4437 11:41:25.856709 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4438 11:41:25.860090 Pre-setting of DQS Precalculation
4439 11:41:25.863471 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4440 11:41:25.863575 ==
4441 11:41:25.867101 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 11:41:25.873130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 11:41:25.873235 ==
4444 11:41:25.876522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 11:41:25.883279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4446 11:41:25.886708 [CA 0] Center 35 (5~66) winsize 62
4447 11:41:25.890310 [CA 1] Center 35 (5~66) winsize 62
4448 11:41:25.893144 [CA 2] Center 34 (4~65) winsize 62
4449 11:41:25.896789 [CA 3] Center 33 (3~64) winsize 62
4450 11:41:25.900047 [CA 4] Center 34 (4~65) winsize 62
4451 11:41:25.903266 [CA 5] Center 33 (3~64) winsize 62
4452 11:41:25.903368
4453 11:41:25.906704 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4454 11:41:25.906780
4455 11:41:25.910063 [CATrainingPosCal] consider 1 rank data
4456 11:41:25.913163 u2DelayCellTimex100 = 270/100 ps
4457 11:41:25.916326 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 11:41:25.923389 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4459 11:41:25.926922 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 11:41:25.929608 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 11:41:25.932804 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 11:41:25.936268 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 11:41:25.936371
4464 11:41:25.940095 CA PerBit enable=1, Macro0, CA PI delay=33
4465 11:41:25.940198
4466 11:41:25.942916 [CBTSetCACLKResult] CA Dly = 33
4467 11:41:25.946528 CS Dly: 5 (0~36)
4468 11:41:25.946639 ==
4469 11:41:25.949876 Dram Type= 6, Freq= 0, CH_1, rank 1
4470 11:41:25.952630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 11:41:25.952708 ==
4472 11:41:25.959608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4473 11:41:25.962431 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4474 11:41:25.967086 [CA 0] Center 35 (5~66) winsize 62
4475 11:41:25.970157 [CA 1] Center 36 (6~66) winsize 61
4476 11:41:25.973490 [CA 2] Center 34 (4~65) winsize 62
4477 11:41:25.976937 [CA 3] Center 34 (3~65) winsize 63
4478 11:41:25.979800 [CA 4] Center 34 (4~65) winsize 62
4479 11:41:25.983407 [CA 5] Center 34 (3~65) winsize 63
4480 11:41:25.983509
4481 11:41:25.986656 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4482 11:41:25.986758
4483 11:41:25.990321 [CATrainingPosCal] consider 2 rank data
4484 11:41:25.993388 u2DelayCellTimex100 = 270/100 ps
4485 11:41:25.996653 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4486 11:41:26.003449 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4487 11:41:26.006752 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4488 11:41:26.009953 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4489 11:41:26.013278 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4490 11:41:26.016126 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4491 11:41:26.016222
4492 11:41:26.019991 CA PerBit enable=1, Macro0, CA PI delay=33
4493 11:41:26.020087
4494 11:41:26.023321 [CBTSetCACLKResult] CA Dly = 33
4495 11:41:26.025989 CS Dly: 5 (0~37)
4496 11:41:26.026074
4497 11:41:26.029954 ----->DramcWriteLeveling(PI) begin...
4498 11:41:26.030029 ==
4499 11:41:26.032814 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 11:41:26.035950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 11:41:26.036048 ==
4502 11:41:26.039309 Write leveling (Byte 0): 31 => 31
4503 11:41:26.042556 Write leveling (Byte 1): 30 => 30
4504 11:41:26.045704 DramcWriteLeveling(PI) end<-----
4505 11:41:26.045779
4506 11:41:26.045845 ==
4507 11:41:26.049456 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 11:41:26.052399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 11:41:26.052522 ==
4510 11:41:26.056238 [Gating] SW mode calibration
4511 11:41:26.062630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4512 11:41:26.068842 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4513 11:41:26.072061 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 11:41:26.076001 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 11:41:26.082213 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4516 11:41:26.085806 0 9 12 | B1->B0 | 3434 2b2b | 0 0 | (0 1) (0 1)
4517 11:41:26.089128 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4518 11:41:26.095329 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 11:41:26.098483 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 11:41:26.102582 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 11:41:26.108806 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 11:41:26.111895 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 11:41:26.115197 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 11:41:26.121943 0 10 12 | B1->B0 | 3232 3737 | 0 0 | (0 0) (1 1)
4525 11:41:26.125394 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4526 11:41:26.128440 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 11:41:26.134953 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 11:41:26.138153 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 11:41:26.141703 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 11:41:26.148499 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 11:41:26.151596 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 11:41:26.154618 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4533 11:41:26.161088 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4534 11:41:26.164265 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 11:41:26.167573 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 11:41:26.174749 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 11:41:26.177646 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 11:41:26.180798 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 11:41:26.187341 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 11:41:26.191062 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 11:41:26.193789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 11:41:26.200733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 11:41:26.203917 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 11:41:26.210467 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 11:41:26.213473 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 11:41:26.217020 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 11:41:26.223297 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 11:41:26.226538 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4549 11:41:26.229918 Total UI for P1: 0, mck2ui 16
4550 11:41:26.233517 best dqsien dly found for B0: ( 0, 13, 10)
4551 11:41:26.236956 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4552 11:41:26.240268 Total UI for P1: 0, mck2ui 16
4553 11:41:26.243415 best dqsien dly found for B1: ( 0, 13, 12)
4554 11:41:26.246538 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4555 11:41:26.249963 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4556 11:41:26.250046
4557 11:41:26.256450 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4558 11:41:26.260014 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4559 11:41:26.260123 [Gating] SW calibration Done
4560 11:41:26.263069 ==
4561 11:41:26.263177 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 11:41:26.269700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 11:41:26.269815 ==
4564 11:41:26.269909 RX Vref Scan: 0
4565 11:41:26.270010
4566 11:41:26.273093 RX Vref 0 -> 0, step: 1
4567 11:41:26.273172
4568 11:41:26.276147 RX Delay -230 -> 252, step: 16
4569 11:41:26.279682 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4570 11:41:26.283246 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4571 11:41:26.289683 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4572 11:41:26.292697 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4573 11:41:26.295865 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4574 11:41:26.299279 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4575 11:41:26.305966 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4576 11:41:26.309122 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4577 11:41:26.312599 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4578 11:41:26.316044 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4579 11:41:26.322564 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4580 11:41:26.326095 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4581 11:41:26.328903 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4582 11:41:26.332177 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4583 11:41:26.339063 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4584 11:41:26.342604 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4585 11:41:26.342716 ==
4586 11:41:26.345371 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 11:41:26.348629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 11:41:26.348711 ==
4589 11:41:26.352071 DQS Delay:
4590 11:41:26.352153 DQS0 = 0, DQS1 = 0
4591 11:41:26.352218 DQM Delay:
4592 11:41:26.355360 DQM0 = 48, DQM1 = 37
4593 11:41:26.355443 DQ Delay:
4594 11:41:26.358800 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =41
4595 11:41:26.361817 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =49
4596 11:41:26.365481 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4597 11:41:26.368684 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4598 11:41:26.368806
4599 11:41:26.368909
4600 11:41:26.368984 ==
4601 11:41:26.372108 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 11:41:26.378576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 11:41:26.378683 ==
4604 11:41:26.378752
4605 11:41:26.378813
4606 11:41:26.378871 TX Vref Scan disable
4607 11:41:26.382404 == TX Byte 0 ==
4608 11:41:26.385456 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4609 11:41:26.391976 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4610 11:41:26.392061 == TX Byte 1 ==
4611 11:41:26.395622 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4612 11:41:26.402021 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4613 11:41:26.402108 ==
4614 11:41:26.405284 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 11:41:26.408540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 11:41:26.408637 ==
4617 11:41:26.408703
4618 11:41:26.408764
4619 11:41:26.411669 TX Vref Scan disable
4620 11:41:26.415422 == TX Byte 0 ==
4621 11:41:26.418329 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4622 11:41:26.422099 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4623 11:41:26.425340 == TX Byte 1 ==
4624 11:41:26.428470 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4625 11:41:26.431890 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4626 11:41:26.432002
4627 11:41:26.432090 [DATLAT]
4628 11:41:26.435282 Freq=600, CH1 RK0
4629 11:41:26.435407
4630 11:41:26.438169 DATLAT Default: 0x9
4631 11:41:26.438291 0, 0xFFFF, sum = 0
4632 11:41:26.441915 1, 0xFFFF, sum = 0
4633 11:41:26.442053 2, 0xFFFF, sum = 0
4634 11:41:26.444850 3, 0xFFFF, sum = 0
4635 11:41:26.445004 4, 0xFFFF, sum = 0
4636 11:41:26.448018 5, 0xFFFF, sum = 0
4637 11:41:26.448173 6, 0xFFFF, sum = 0
4638 11:41:26.451279 7, 0xFFFF, sum = 0
4639 11:41:26.451517 8, 0x0, sum = 1
4640 11:41:26.454991 9, 0x0, sum = 2
4641 11:41:26.455196 10, 0x0, sum = 3
4642 11:41:26.458201 11, 0x0, sum = 4
4643 11:41:26.458408 best_step = 9
4644 11:41:26.458590
4645 11:41:26.458769 ==
4646 11:41:26.461675 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 11:41:26.464865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 11:41:26.465179 ==
4649 11:41:26.468128 RX Vref Scan: 1
4650 11:41:26.468498
4651 11:41:26.471790 RX Vref 0 -> 0, step: 1
4652 11:41:26.472390
4653 11:41:26.472970 RX Delay -179 -> 252, step: 8
4654 11:41:26.475055
4655 11:41:26.475587 Set Vref, RX VrefLevel [Byte0]: 48
4656 11:41:26.478335 [Byte1]: 54
4657 11:41:26.483099
4658 11:41:26.483727 Final RX Vref Byte 0 = 48 to rank0
4659 11:41:26.486362 Final RX Vref Byte 1 = 54 to rank0
4660 11:41:26.489424 Final RX Vref Byte 0 = 48 to rank1
4661 11:41:26.492645 Final RX Vref Byte 1 = 54 to rank1==
4662 11:41:26.496221 Dram Type= 6, Freq= 0, CH_1, rank 0
4663 11:41:26.502495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 11:41:26.502919 ==
4665 11:41:26.503257 DQS Delay:
4666 11:41:26.506021 DQS0 = 0, DQS1 = 0
4667 11:41:26.506444 DQM Delay:
4668 11:41:26.506779 DQM0 = 47, DQM1 = 38
4669 11:41:26.509384 DQ Delay:
4670 11:41:26.512310 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4671 11:41:26.515762 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4672 11:41:26.518995 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4673 11:41:26.522494 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4674 11:41:26.523017
4675 11:41:26.523486
4676 11:41:26.528781 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4677 11:41:26.531985 CH1 RK0: MR19=808, MR18=4B30
4678 11:41:26.538431 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4679 11:41:26.538513
4680 11:41:26.541708 ----->DramcWriteLeveling(PI) begin...
4681 11:41:26.541792 ==
4682 11:41:26.545195 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 11:41:26.548359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 11:41:26.548443 ==
4685 11:41:26.551715 Write leveling (Byte 0): 29 => 29
4686 11:41:26.555016 Write leveling (Byte 1): 29 => 29
4687 11:41:26.558297 DramcWriteLeveling(PI) end<-----
4688 11:41:26.558379
4689 11:41:26.558444 ==
4690 11:41:26.561411 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 11:41:26.568676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 11:41:26.568759 ==
4693 11:41:26.568825 [Gating] SW mode calibration
4694 11:41:26.577922 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4695 11:41:26.580955 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4696 11:41:26.587732 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 11:41:26.591270 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 11:41:26.594323 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4699 11:41:26.601131 0 9 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4700 11:41:26.604167 0 9 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4701 11:41:26.607521 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 11:41:26.614208 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 11:41:26.617812 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 11:41:26.620415 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 11:41:26.627271 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 11:41:26.630596 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 11:41:26.633530 0 10 12 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
4708 11:41:26.640151 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
4709 11:41:26.643608 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 11:41:26.646856 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 11:41:26.653620 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 11:41:26.656211 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 11:41:26.659593 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 11:41:26.666676 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 11:41:26.670030 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 11:41:26.673437 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 11:41:26.679576 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 11:41:26.683185 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 11:41:26.686667 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 11:41:26.692811 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 11:41:26.696332 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 11:41:26.699635 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 11:41:26.706308 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 11:41:26.709506 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 11:41:26.712776 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 11:41:26.719553 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 11:41:26.722896 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 11:41:26.725635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 11:41:26.732426 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 11:41:26.735769 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4731 11:41:26.739333 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4732 11:41:26.746035 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 11:41:26.746118 Total UI for P1: 0, mck2ui 16
4734 11:41:26.752389 best dqsien dly found for B0: ( 0, 13, 12)
4735 11:41:26.752503 Total UI for P1: 0, mck2ui 16
4736 11:41:26.758929 best dqsien dly found for B1: ( 0, 13, 10)
4737 11:41:26.762018 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4738 11:41:26.765408 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4739 11:41:26.765492
4740 11:41:26.769259 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4741 11:41:26.771847 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4742 11:41:26.775318 [Gating] SW calibration Done
4743 11:41:26.775426 ==
4744 11:41:26.778571 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 11:41:26.782304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 11:41:26.782412 ==
4747 11:41:26.785359 RX Vref Scan: 0
4748 11:41:26.785433
4749 11:41:26.785496 RX Vref 0 -> 0, step: 1
4750 11:41:26.785555
4751 11:41:26.788723 RX Delay -230 -> 252, step: 16
4752 11:41:26.795436 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4753 11:41:26.798685 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4754 11:41:26.802003 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4755 11:41:26.805260 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4756 11:41:26.808473 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4757 11:41:26.814948 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4758 11:41:26.818373 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4759 11:41:26.821869 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4760 11:41:26.824797 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4761 11:41:26.831343 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4762 11:41:26.835000 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4763 11:41:26.838149 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4764 11:41:26.841366 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4765 11:41:26.847779 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4766 11:41:26.851590 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4767 11:41:26.854948 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4768 11:41:26.855029 ==
4769 11:41:26.857579 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 11:41:26.860924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 11:41:26.864217 ==
4772 11:41:26.864298 DQS Delay:
4773 11:41:26.864362 DQS0 = 0, DQS1 = 0
4774 11:41:26.867760 DQM Delay:
4775 11:41:26.867841 DQM0 = 45, DQM1 = 36
4776 11:41:26.870802 DQ Delay:
4777 11:41:26.874456 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4778 11:41:26.874538 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4779 11:41:26.877733 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4780 11:41:26.883947 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =49
4781 11:41:26.884051
4782 11:41:26.884162
4783 11:41:26.884280 ==
4784 11:41:26.887495 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 11:41:26.891019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 11:41:26.891106 ==
4787 11:41:26.891172
4788 11:41:26.891231
4789 11:41:26.894051 TX Vref Scan disable
4790 11:41:26.894135 == TX Byte 0 ==
4791 11:41:26.900714 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4792 11:41:26.904026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4793 11:41:26.904108 == TX Byte 1 ==
4794 11:41:26.911570 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4795 11:41:26.914305 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4796 11:41:26.914387 ==
4797 11:41:26.917008 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 11:41:26.920263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 11:41:26.920347 ==
4800 11:41:26.920413
4801 11:41:26.924079
4802 11:41:26.924161 TX Vref Scan disable
4803 11:41:26.927280 == TX Byte 0 ==
4804 11:41:26.930480 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4805 11:41:26.937277 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4806 11:41:26.937359 == TX Byte 1 ==
4807 11:41:26.940388 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4808 11:41:26.946897 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4809 11:41:26.946981
4810 11:41:26.947046 [DATLAT]
4811 11:41:26.947106 Freq=600, CH1 RK1
4812 11:41:26.947165
4813 11:41:26.950568 DATLAT Default: 0x9
4814 11:41:26.950650 0, 0xFFFF, sum = 0
4815 11:41:26.954102 1, 0xFFFF, sum = 0
4816 11:41:26.956913 2, 0xFFFF, sum = 0
4817 11:41:26.956997 3, 0xFFFF, sum = 0
4818 11:41:26.960043 4, 0xFFFF, sum = 0
4819 11:41:26.960127 5, 0xFFFF, sum = 0
4820 11:41:26.963601 6, 0xFFFF, sum = 0
4821 11:41:26.963684 7, 0xFFFF, sum = 0
4822 11:41:26.966706 8, 0x0, sum = 1
4823 11:41:26.966790 9, 0x0, sum = 2
4824 11:41:26.969884 10, 0x0, sum = 3
4825 11:41:26.969967 11, 0x0, sum = 4
4826 11:41:26.970034 best_step = 9
4827 11:41:26.970095
4828 11:41:26.973569 ==
4829 11:41:26.973652 Dram Type= 6, Freq= 0, CH_1, rank 1
4830 11:41:26.980155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4831 11:41:26.980238 ==
4832 11:41:26.980303 RX Vref Scan: 0
4833 11:41:26.980364
4834 11:41:26.983354 RX Vref 0 -> 0, step: 1
4835 11:41:26.983436
4836 11:41:26.986303 RX Delay -195 -> 252, step: 8
4837 11:41:26.993267 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4838 11:41:26.996381 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4839 11:41:26.999787 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4840 11:41:27.003365 iDelay=213, Bit 3, Center 44 (-99 ~ 188) 288
4841 11:41:27.006998 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4842 11:41:27.012866 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4843 11:41:27.016662 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4844 11:41:27.019379 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4845 11:41:27.022982 iDelay=213, Bit 8, Center 28 (-123 ~ 180) 304
4846 11:41:27.026237 iDelay=213, Bit 9, Center 28 (-123 ~ 180) 304
4847 11:41:27.033106 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4848 11:41:27.036310 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4849 11:41:27.039825 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4850 11:41:27.042572 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4851 11:41:27.049504 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4852 11:41:27.052463 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4853 11:41:27.052600 ==
4854 11:41:27.056021 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 11:41:27.059419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 11:41:27.059506 ==
4857 11:41:27.062444 DQS Delay:
4858 11:41:27.062552 DQS0 = 0, DQS1 = 0
4859 11:41:27.065995 DQM Delay:
4860 11:41:27.066077 DQM0 = 46, DQM1 = 38
4861 11:41:27.066142 DQ Delay:
4862 11:41:27.068972 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4863 11:41:27.072349 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4864 11:41:27.076022 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =28
4865 11:41:27.078866 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4866 11:41:27.078948
4867 11:41:27.079014
4868 11:41:27.088932 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a1f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
4869 11:41:27.092435 CH1 RK1: MR19=808, MR18=2A1F
4870 11:41:27.098891 CH1_RK1: MR19=0x808, MR18=0x2A1F, DQSOSC=401, MR23=63, INC=163, DEC=108
4871 11:41:27.102101 [RxdqsGatingPostProcess] freq 600
4872 11:41:27.105378 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4873 11:41:27.108634 Pre-setting of DQS Precalculation
4874 11:41:27.115048 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4875 11:41:27.121874 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4876 11:41:27.128326 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4877 11:41:27.128409
4878 11:41:27.128474
4879 11:41:27.131575 [Calibration Summary] 1200 Mbps
4880 11:41:27.131658 CH 0, Rank 0
4881 11:41:27.135130 SW Impedance : PASS
4882 11:41:27.138509 DUTY Scan : NO K
4883 11:41:27.138591 ZQ Calibration : PASS
4884 11:41:27.141847 Jitter Meter : NO K
4885 11:41:27.144648 CBT Training : PASS
4886 11:41:27.144730 Write leveling : PASS
4887 11:41:27.148144 RX DQS gating : PASS
4888 11:41:27.148232 RX DQ/DQS(RDDQC) : PASS
4889 11:41:27.151221 TX DQ/DQS : PASS
4890 11:41:27.154563 RX DATLAT : PASS
4891 11:41:27.154645 RX DQ/DQS(Engine): PASS
4892 11:41:27.157986 TX OE : NO K
4893 11:41:27.158069 All Pass.
4894 11:41:27.158134
4895 11:41:27.161089 CH 0, Rank 1
4896 11:41:27.161197 SW Impedance : PASS
4897 11:41:27.164386 DUTY Scan : NO K
4898 11:41:27.167909 ZQ Calibration : PASS
4899 11:41:27.167983 Jitter Meter : NO K
4900 11:41:27.171244 CBT Training : PASS
4901 11:41:27.174529 Write leveling : PASS
4902 11:41:27.174628 RX DQS gating : PASS
4903 11:41:27.177842 RX DQ/DQS(RDDQC) : PASS
4904 11:41:27.181268 TX DQ/DQS : PASS
4905 11:41:27.181340 RX DATLAT : PASS
4906 11:41:27.184251 RX DQ/DQS(Engine): PASS
4907 11:41:27.187705 TX OE : NO K
4908 11:41:27.187805 All Pass.
4909 11:41:27.187895
4910 11:41:27.187984 CH 1, Rank 0
4911 11:41:27.190865 SW Impedance : PASS
4912 11:41:27.194395 DUTY Scan : NO K
4913 11:41:27.194494 ZQ Calibration : PASS
4914 11:41:27.197481 Jitter Meter : NO K
4915 11:41:27.200707 CBT Training : PASS
4916 11:41:27.200783 Write leveling : PASS
4917 11:41:27.203913 RX DQS gating : PASS
4918 11:41:27.207276 RX DQ/DQS(RDDQC) : PASS
4919 11:41:27.207349 TX DQ/DQS : PASS
4920 11:41:27.210880 RX DATLAT : PASS
4921 11:41:27.214271 RX DQ/DQS(Engine): PASS
4922 11:41:27.214347 TX OE : NO K
4923 11:41:27.214410 All Pass.
4924 11:41:27.217282
4925 11:41:27.217364 CH 1, Rank 1
4926 11:41:27.220698 SW Impedance : PASS
4927 11:41:27.220772 DUTY Scan : NO K
4928 11:41:27.223889 ZQ Calibration : PASS
4929 11:41:27.226898 Jitter Meter : NO K
4930 11:41:27.226970 CBT Training : PASS
4931 11:41:27.230392 Write leveling : PASS
4932 11:41:27.233522 RX DQS gating : PASS
4933 11:41:27.233598 RX DQ/DQS(RDDQC) : PASS
4934 11:41:27.236750 TX DQ/DQS : PASS
4935 11:41:27.236823 RX DATLAT : PASS
4936 11:41:27.240399 RX DQ/DQS(Engine): PASS
4937 11:41:27.243612 TX OE : NO K
4938 11:41:27.243716 All Pass.
4939 11:41:27.243807
4940 11:41:27.247006 DramC Write-DBI off
4941 11:41:27.247108 PER_BANK_REFRESH: Hybrid Mode
4942 11:41:27.250316 TX_TRACKING: ON
4943 11:41:27.260064 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4944 11:41:27.263373 [FAST_K] Save calibration result to emmc
4945 11:41:27.266827 dramc_set_vcore_voltage set vcore to 662500
4946 11:41:27.266912 Read voltage for 933, 3
4947 11:41:27.270173 Vio18 = 0
4948 11:41:27.270256 Vcore = 662500
4949 11:41:27.270339 Vdram = 0
4950 11:41:27.273625 Vddq = 0
4951 11:41:27.273708 Vmddr = 0
4952 11:41:27.279865 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4953 11:41:27.283365 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4954 11:41:27.286634 MEM_TYPE=3, freq_sel=17
4955 11:41:27.289793 sv_algorithm_assistance_LP4_1600
4956 11:41:27.293594 ============ PULL DRAM RESETB DOWN ============
4957 11:41:27.296764 ========== PULL DRAM RESETB DOWN end =========
4958 11:41:27.303599 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4959 11:41:27.306191 ===================================
4960 11:41:27.306272 LPDDR4 DRAM CONFIGURATION
4961 11:41:27.309517 ===================================
4962 11:41:27.313043 EX_ROW_EN[0] = 0x0
4963 11:41:27.316315 EX_ROW_EN[1] = 0x0
4964 11:41:27.316396 LP4Y_EN = 0x0
4965 11:41:27.319460 WORK_FSP = 0x0
4966 11:41:27.319542 WL = 0x3
4967 11:41:27.322771 RL = 0x3
4968 11:41:27.322853 BL = 0x2
4969 11:41:27.326222 RPST = 0x0
4970 11:41:27.326304 RD_PRE = 0x0
4971 11:41:27.329618 WR_PRE = 0x1
4972 11:41:27.329699 WR_PST = 0x0
4973 11:41:27.332958 DBI_WR = 0x0
4974 11:41:27.333065 DBI_RD = 0x0
4975 11:41:27.336112 OTF = 0x1
4976 11:41:27.339569 ===================================
4977 11:41:27.342780 ===================================
4978 11:41:27.342862 ANA top config
4979 11:41:27.345986 ===================================
4980 11:41:27.349383 DLL_ASYNC_EN = 0
4981 11:41:27.352730 ALL_SLAVE_EN = 1
4982 11:41:27.355883 NEW_RANK_MODE = 1
4983 11:41:27.355965 DLL_IDLE_MODE = 1
4984 11:41:27.359375 LP45_APHY_COMB_EN = 1
4985 11:41:27.362545 TX_ODT_DIS = 1
4986 11:41:27.365935 NEW_8X_MODE = 1
4987 11:41:27.369082 ===================================
4988 11:41:27.372520 ===================================
4989 11:41:27.375465 data_rate = 1866
4990 11:41:27.375546 CKR = 1
4991 11:41:27.379210 DQ_P2S_RATIO = 8
4992 11:41:27.382372 ===================================
4993 11:41:27.385844 CA_P2S_RATIO = 8
4994 11:41:27.388711 DQ_CA_OPEN = 0
4995 11:41:27.392689 DQ_SEMI_OPEN = 0
4996 11:41:27.395769 CA_SEMI_OPEN = 0
4997 11:41:27.395869 CA_FULL_RATE = 0
4998 11:41:27.399091 DQ_CKDIV4_EN = 1
4999 11:41:27.401864 CA_CKDIV4_EN = 1
5000 11:41:27.405342 CA_PREDIV_EN = 0
5001 11:41:27.408380 PH8_DLY = 0
5002 11:41:27.412522 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5003 11:41:27.412617 DQ_AAMCK_DIV = 4
5004 11:41:27.415295 CA_AAMCK_DIV = 4
5005 11:41:27.418696 CA_ADMCK_DIV = 4
5006 11:41:27.421973 DQ_TRACK_CA_EN = 0
5007 11:41:27.425428 CA_PICK = 933
5008 11:41:27.428177 CA_MCKIO = 933
5009 11:41:27.431758 MCKIO_SEMI = 0
5010 11:41:27.435088 PLL_FREQ = 3732
5011 11:41:27.435170 DQ_UI_PI_RATIO = 32
5012 11:41:27.438374 CA_UI_PI_RATIO = 0
5013 11:41:27.441696 ===================================
5014 11:41:27.445081 ===================================
5015 11:41:27.448007 memory_type:LPDDR4
5016 11:41:27.451477 GP_NUM : 10
5017 11:41:27.451560 SRAM_EN : 1
5018 11:41:27.454455 MD32_EN : 0
5019 11:41:27.457862 ===================================
5020 11:41:27.461096 [ANA_INIT] >>>>>>>>>>>>>>
5021 11:41:27.461178 <<<<<< [CONFIGURE PHASE]: ANA_TX
5022 11:41:27.464966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5023 11:41:27.468041 ===================================
5024 11:41:27.471389 data_rate = 1866,PCW = 0X8f00
5025 11:41:27.474228 ===================================
5026 11:41:27.478226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5027 11:41:27.484574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5028 11:41:27.491218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 11:41:27.494641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5030 11:41:27.497355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5031 11:41:27.500719 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5032 11:41:27.504286 [ANA_INIT] flow start
5033 11:41:27.504358 [ANA_INIT] PLL >>>>>>>>
5034 11:41:27.508156 [ANA_INIT] PLL <<<<<<<<
5035 11:41:27.510974 [ANA_INIT] MIDPI >>>>>>>>
5036 11:41:27.514154 [ANA_INIT] MIDPI <<<<<<<<
5037 11:41:27.514226 [ANA_INIT] DLL >>>>>>>>
5038 11:41:27.517052 [ANA_INIT] flow end
5039 11:41:27.520530 ============ LP4 DIFF to SE enter ============
5040 11:41:27.523779 ============ LP4 DIFF to SE exit ============
5041 11:41:27.527180 [ANA_INIT] <<<<<<<<<<<<<
5042 11:41:27.530583 [Flow] Enable top DCM control >>>>>
5043 11:41:27.533579 [Flow] Enable top DCM control <<<<<
5044 11:41:27.537415 Enable DLL master slave shuffle
5045 11:41:27.543948 ==============================================================
5046 11:41:27.544031 Gating Mode config
5047 11:41:27.550503 ==============================================================
5048 11:41:27.550614 Config description:
5049 11:41:27.560365 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5050 11:41:27.567176 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5051 11:41:27.573349 SELPH_MODE 0: By rank 1: By Phase
5052 11:41:27.577463 ==============================================================
5053 11:41:27.580027 GAT_TRACK_EN = 1
5054 11:41:27.583233 RX_GATING_MODE = 2
5055 11:41:27.586615 RX_GATING_TRACK_MODE = 2
5056 11:41:27.589965 SELPH_MODE = 1
5057 11:41:27.593366 PICG_EARLY_EN = 1
5058 11:41:27.596681 VALID_LAT_VALUE = 1
5059 11:41:27.603331 ==============================================================
5060 11:41:27.606515 Enter into Gating configuration >>>>
5061 11:41:27.609638 Exit from Gating configuration <<<<
5062 11:41:27.613275 Enter into DVFS_PRE_config >>>>>
5063 11:41:27.622853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5064 11:41:27.626356 Exit from DVFS_PRE_config <<<<<
5065 11:41:27.629339 Enter into PICG configuration >>>>
5066 11:41:27.632724 Exit from PICG configuration <<<<
5067 11:41:27.635958 [RX_INPUT] configuration >>>>>
5068 11:41:27.636062 [RX_INPUT] configuration <<<<<
5069 11:41:27.642883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5070 11:41:27.649084 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5071 11:41:27.655808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 11:41:27.659037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 11:41:27.665750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 11:41:27.672814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 11:41:27.675724 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5076 11:41:27.679172 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5077 11:41:27.685966 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5078 11:41:27.689113 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5079 11:41:27.691906 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5080 11:41:27.699361 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 11:41:27.702006 ===================================
5082 11:41:27.702160 LPDDR4 DRAM CONFIGURATION
5083 11:41:27.705771 ===================================
5084 11:41:27.708909 EX_ROW_EN[0] = 0x0
5085 11:41:27.711992 EX_ROW_EN[1] = 0x0
5086 11:41:27.712187 LP4Y_EN = 0x0
5087 11:41:27.715463 WORK_FSP = 0x0
5088 11:41:27.715746 WL = 0x3
5089 11:41:27.718621 RL = 0x3
5090 11:41:27.718998 BL = 0x2
5091 11:41:27.721949 RPST = 0x0
5092 11:41:27.722235 RD_PRE = 0x0
5093 11:41:27.725415 WR_PRE = 0x1
5094 11:41:27.725830 WR_PST = 0x0
5095 11:41:27.728600 DBI_WR = 0x0
5096 11:41:27.729100 DBI_RD = 0x0
5097 11:41:27.732492 OTF = 0x1
5098 11:41:27.735437 ===================================
5099 11:41:27.738727 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5100 11:41:27.741878 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5101 11:41:27.748261 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 11:41:27.751445 ===================================
5103 11:41:27.751889 LPDDR4 DRAM CONFIGURATION
5104 11:41:27.754814 ===================================
5105 11:41:27.758777 EX_ROW_EN[0] = 0x10
5106 11:41:27.761844 EX_ROW_EN[1] = 0x0
5107 11:41:27.762287 LP4Y_EN = 0x0
5108 11:41:27.765049 WORK_FSP = 0x0
5109 11:41:27.765522 WL = 0x3
5110 11:41:27.768299 RL = 0x3
5111 11:41:27.768857 BL = 0x2
5112 11:41:27.771507 RPST = 0x0
5113 11:41:27.771949 RD_PRE = 0x0
5114 11:41:27.774709 WR_PRE = 0x1
5115 11:41:27.775151 WR_PST = 0x0
5116 11:41:27.778185 DBI_WR = 0x0
5117 11:41:27.778671 DBI_RD = 0x0
5118 11:41:27.781318 OTF = 0x1
5119 11:41:27.784621 ===================================
5120 11:41:27.791336 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5121 11:41:27.794454 nWR fixed to 30
5122 11:41:27.797688 [ModeRegInit_LP4] CH0 RK0
5123 11:41:27.797759 [ModeRegInit_LP4] CH0 RK1
5124 11:41:27.801148 [ModeRegInit_LP4] CH1 RK0
5125 11:41:27.804043 [ModeRegInit_LP4] CH1 RK1
5126 11:41:27.804124 match AC timing 9
5127 11:41:27.810543 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5128 11:41:27.813819 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5129 11:41:27.817113 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5130 11:41:27.824028 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5131 11:41:27.827187 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5132 11:41:27.827292 ==
5133 11:41:27.830423 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 11:41:27.833778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 11:41:27.833904 ==
5136 11:41:27.840211 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 11:41:27.847289 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5138 11:41:27.850527 [CA 0] Center 37 (7~68) winsize 62
5139 11:41:27.853619 [CA 1] Center 37 (7~68) winsize 62
5140 11:41:27.857135 [CA 2] Center 34 (4~65) winsize 62
5141 11:41:27.860288 [CA 3] Center 34 (4~65) winsize 62
5142 11:41:27.863311 [CA 4] Center 33 (3~64) winsize 62
5143 11:41:27.867125 [CA 5] Center 33 (3~63) winsize 61
5144 11:41:27.867428
5145 11:41:27.870529 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5146 11:41:27.870923
5147 11:41:27.873779 [CATrainingPosCal] consider 1 rank data
5148 11:41:27.876986 u2DelayCellTimex100 = 270/100 ps
5149 11:41:27.880575 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5150 11:41:27.883335 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5151 11:41:27.886844 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5152 11:41:27.893284 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5153 11:41:27.896429 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5154 11:41:27.899636 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5155 11:41:27.900200
5156 11:41:27.903210 CA PerBit enable=1, Macro0, CA PI delay=33
5157 11:41:27.903710
5158 11:41:27.906721 [CBTSetCACLKResult] CA Dly = 33
5159 11:41:27.907232 CS Dly: 7 (0~38)
5160 11:41:27.907707 ==
5161 11:41:27.909881 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 11:41:27.916267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 11:41:27.916830 ==
5164 11:41:27.919915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5165 11:41:27.926131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5166 11:41:27.929425 [CA 0] Center 37 (7~68) winsize 62
5167 11:41:27.932852 [CA 1] Center 37 (7~68) winsize 62
5168 11:41:27.936209 [CA 2] Center 34 (4~65) winsize 62
5169 11:41:27.939385 [CA 3] Center 35 (5~65) winsize 61
5170 11:41:27.943154 [CA 4] Center 33 (3~64) winsize 62
5171 11:41:27.945961 [CA 5] Center 33 (2~64) winsize 63
5172 11:41:27.946435
5173 11:41:27.949471 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5174 11:41:27.949981
5175 11:41:27.952716 [CATrainingPosCal] consider 2 rank data
5176 11:41:27.956232 u2DelayCellTimex100 = 270/100 ps
5177 11:41:27.959676 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5178 11:41:27.965832 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 11:41:27.969070 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5180 11:41:27.972618 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5181 11:41:27.975825 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5182 11:41:27.979242 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5183 11:41:27.979700
5184 11:41:27.982343 CA PerBit enable=1, Macro0, CA PI delay=33
5185 11:41:27.982771
5186 11:41:27.986170 [CBTSetCACLKResult] CA Dly = 33
5187 11:41:27.989395 CS Dly: 7 (0~39)
5188 11:41:27.989813
5189 11:41:27.992365 ----->DramcWriteLeveling(PI) begin...
5190 11:41:27.992835 ==
5191 11:41:27.995427 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 11:41:27.998763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 11:41:27.999283 ==
5194 11:41:28.002326 Write leveling (Byte 0): 34 => 34
5195 11:41:28.005506 Write leveling (Byte 1): 27 => 27
5196 11:41:28.008774 DramcWriteLeveling(PI) end<-----
5197 11:41:28.009242
5198 11:41:28.009766 ==
5199 11:41:28.012193 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 11:41:28.015562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 11:41:28.016016 ==
5202 11:41:28.018844 [Gating] SW mode calibration
5203 11:41:28.025291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5204 11:41:28.032301 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5205 11:41:28.035381 0 14 0 | B1->B0 | 2322 3131 | 1 1 | (1 0) (1 1)
5206 11:41:28.038444 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5207 11:41:28.044886 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 11:41:28.048970 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 11:41:28.051497 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 11:41:28.058527 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 11:41:28.061891 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 11:41:28.064986 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5213 11:41:28.071656 0 15 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (1 0)
5214 11:41:28.074731 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 11:41:28.078376 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 11:41:28.084730 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 11:41:28.088271 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 11:41:28.091342 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 11:41:28.098000 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 11:41:28.101477 0 15 28 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5221 11:41:28.104878 1 0 0 | B1->B0 | 2f2e 4646 | 1 0 | (0 0) (0 0)
5222 11:41:28.111148 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 11:41:28.114342 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 11:41:28.117631 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 11:41:28.124592 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 11:41:28.127374 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 11:41:28.130834 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 11:41:28.137762 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5229 11:41:28.140837 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5230 11:41:28.143985 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 11:41:28.150965 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 11:41:28.153935 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 11:41:28.157555 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 11:41:28.163901 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 11:41:28.166938 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 11:41:28.170281 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 11:41:28.176960 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 11:41:28.180069 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 11:41:28.183975 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 11:41:28.190378 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 11:41:28.193869 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 11:41:28.196687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 11:41:28.203721 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 11:41:28.206736 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5245 11:41:28.210367 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5246 11:41:28.213033 Total UI for P1: 0, mck2ui 16
5247 11:41:28.216419 best dqsien dly found for B0: ( 1, 2, 28)
5248 11:41:28.223873 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 11:41:28.224419 Total UI for P1: 0, mck2ui 16
5250 11:41:28.230039 best dqsien dly found for B1: ( 1, 3, 0)
5251 11:41:28.233077 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5252 11:41:28.236342 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5253 11:41:28.236874
5254 11:41:28.239938 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5255 11:41:28.243118 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5256 11:41:28.246255 [Gating] SW calibration Done
5257 11:41:28.246672 ==
5258 11:41:28.249745 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 11:41:28.253018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 11:41:28.253436 ==
5261 11:41:28.256308 RX Vref Scan: 0
5262 11:41:28.256923
5263 11:41:28.257400 RX Vref 0 -> 0, step: 1
5264 11:41:28.259476
5265 11:41:28.259959 RX Delay -80 -> 252, step: 8
5266 11:41:28.266079 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5267 11:41:28.269228 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5268 11:41:28.272363 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5269 11:41:28.275907 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5270 11:41:28.279505 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5271 11:41:28.282505 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5272 11:41:28.289211 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5273 11:41:28.292232 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5274 11:41:28.295843 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5275 11:41:28.298662 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5276 11:41:28.302120 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5277 11:41:28.308617 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5278 11:41:28.311977 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5279 11:41:28.315404 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5280 11:41:28.318524 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5281 11:41:28.322007 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5282 11:41:28.325349 ==
5283 11:41:28.325764 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 11:41:28.332087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:41:28.332656 ==
5286 11:41:28.333004 DQS Delay:
5287 11:41:28.335358 DQS0 = 0, DQS1 = 0
5288 11:41:28.335777 DQM Delay:
5289 11:41:28.338408 DQM0 = 97, DQM1 = 85
5290 11:41:28.338821 DQ Delay:
5291 11:41:28.341555 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5292 11:41:28.345020 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5293 11:41:28.348665 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5294 11:41:28.351420 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5295 11:41:28.351836
5296 11:41:28.352167
5297 11:41:28.352474 ==
5298 11:41:28.354799 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 11:41:28.358087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 11:41:28.358508 ==
5301 11:41:28.358843
5302 11:41:28.359148
5303 11:41:28.361524 TX Vref Scan disable
5304 11:41:28.364880 == TX Byte 0 ==
5305 11:41:28.368025 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5306 11:41:28.371533 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5307 11:41:28.374899 == TX Byte 1 ==
5308 11:41:28.378327 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5309 11:41:28.381195 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5310 11:41:28.381615 ==
5311 11:41:28.384898 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 11:41:28.391195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 11:41:28.391755 ==
5314 11:41:28.392135
5315 11:41:28.392628
5316 11:41:28.393078 TX Vref Scan disable
5317 11:41:28.395140 == TX Byte 0 ==
5318 11:41:28.398768 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5319 11:41:28.404845 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5320 11:41:28.405553 == TX Byte 1 ==
5321 11:41:28.408277 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5322 11:41:28.415324 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5323 11:41:28.415953
5324 11:41:28.416579 [DATLAT]
5325 11:41:28.417148 Freq=933, CH0 RK0
5326 11:41:28.417727
5327 11:41:28.418565 DATLAT Default: 0xd
5328 11:41:28.421837 0, 0xFFFF, sum = 0
5329 11:41:28.422429 1, 0xFFFF, sum = 0
5330 11:41:28.424772 2, 0xFFFF, sum = 0
5331 11:41:28.425222 3, 0xFFFF, sum = 0
5332 11:41:28.428381 4, 0xFFFF, sum = 0
5333 11:41:28.428966 5, 0xFFFF, sum = 0
5334 11:41:28.431840 6, 0xFFFF, sum = 0
5335 11:41:28.432380 7, 0xFFFF, sum = 0
5336 11:41:28.434570 8, 0xFFFF, sum = 0
5337 11:41:28.435208 9, 0xFFFF, sum = 0
5338 11:41:28.438432 10, 0x0, sum = 1
5339 11:41:28.439082 11, 0x0, sum = 2
5340 11:41:28.441229 12, 0x0, sum = 3
5341 11:41:28.441788 13, 0x0, sum = 4
5342 11:41:28.444991 best_step = 11
5343 11:41:28.445460
5344 11:41:28.446036 ==
5345 11:41:28.448129 Dram Type= 6, Freq= 0, CH_0, rank 0
5346 11:41:28.451306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 11:41:28.451869 ==
5348 11:41:28.452457 RX Vref Scan: 1
5349 11:41:28.454515
5350 11:41:28.454988 RX Vref 0 -> 0, step: 1
5351 11:41:28.455468
5352 11:41:28.457944 RX Delay -61 -> 252, step: 4
5353 11:41:28.458373
5354 11:41:28.461055 Set Vref, RX VrefLevel [Byte0]: 59
5355 11:41:28.464410 [Byte1]: 56
5356 11:41:28.467733
5357 11:41:28.468147 Final RX Vref Byte 0 = 59 to rank0
5358 11:41:28.471528 Final RX Vref Byte 1 = 56 to rank0
5359 11:41:28.474524 Final RX Vref Byte 0 = 59 to rank1
5360 11:41:28.478245 Final RX Vref Byte 1 = 56 to rank1==
5361 11:41:28.480771 Dram Type= 6, Freq= 0, CH_0, rank 0
5362 11:41:28.487575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 11:41:28.487869 ==
5364 11:41:28.488102 DQS Delay:
5365 11:41:28.490568 DQS0 = 0, DQS1 = 0
5366 11:41:28.490789 DQM Delay:
5367 11:41:28.490963 DQM0 = 97, DQM1 = 87
5368 11:41:28.493873 DQ Delay:
5369 11:41:28.497338 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5370 11:41:28.500799 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5371 11:41:28.503850 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5372 11:41:28.507197 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =92
5373 11:41:28.507373
5374 11:41:28.507512
5375 11:41:28.513708 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5376 11:41:28.517152 CH0 RK0: MR19=505, MR18=2A11
5377 11:41:28.524060 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5378 11:41:28.524239
5379 11:41:28.526804 ----->DramcWriteLeveling(PI) begin...
5380 11:41:28.526983 ==
5381 11:41:28.530667 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 11:41:28.533844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 11:41:28.534094 ==
5384 11:41:28.537207 Write leveling (Byte 0): 34 => 34
5385 11:41:28.540290 Write leveling (Byte 1): 31 => 31
5386 11:41:28.543864 DramcWriteLeveling(PI) end<-----
5387 11:41:28.544271
5388 11:41:28.544630 ==
5389 11:41:28.546986 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 11:41:28.550085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 11:41:28.553291 ==
5392 11:41:28.553698 [Gating] SW mode calibration
5393 11:41:28.563410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5394 11:41:28.566487 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5395 11:41:28.569914 0 14 0 | B1->B0 | 2525 3131 | 0 0 | (0 0) (1 1)
5396 11:41:28.576609 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 11:41:28.579664 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 11:41:28.583460 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 11:41:28.590254 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 11:41:28.593076 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 11:41:28.599331 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 11:41:28.603252 0 14 28 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)
5403 11:41:28.606021 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5404 11:41:28.612902 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5405 11:41:28.616185 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 11:41:28.619250 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 11:41:28.622447 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 11:41:28.629574 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 11:41:28.632380 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5410 11:41:28.638945 0 15 28 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
5411 11:41:28.642218 1 0 0 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
5412 11:41:28.646017 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 11:41:28.648847 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 11:41:28.655545 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 11:41:28.658903 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 11:41:28.662232 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 11:41:28.669379 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 11:41:28.672010 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5419 11:41:28.675724 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5420 11:41:28.682264 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 11:41:28.685507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 11:41:28.689382 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 11:41:28.695820 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 11:41:28.698684 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 11:41:28.702334 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 11:41:28.708724 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 11:41:28.712588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 11:41:28.715296 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 11:41:28.721916 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 11:41:28.725452 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 11:41:28.729188 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 11:41:28.735227 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 11:41:28.738303 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 11:41:28.742170 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5435 11:41:28.748252 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5436 11:41:28.751463 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 11:41:28.754770 Total UI for P1: 0, mck2ui 16
5438 11:41:28.758166 best dqsien dly found for B0: ( 1, 2, 30)
5439 11:41:28.761523 Total UI for P1: 0, mck2ui 16
5440 11:41:28.764716 best dqsien dly found for B1: ( 1, 3, 0)
5441 11:41:28.768449 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5442 11:41:28.771535 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5443 11:41:28.772036
5444 11:41:28.775100 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5445 11:41:28.778358 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5446 11:41:28.781440 [Gating] SW calibration Done
5447 11:41:28.781982 ==
5448 11:41:28.784568 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 11:41:28.787789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 11:41:28.791431 ==
5451 11:41:28.791921 RX Vref Scan: 0
5452 11:41:28.792306
5453 11:41:28.794110 RX Vref 0 -> 0, step: 1
5454 11:41:28.794494
5455 11:41:28.798070 RX Delay -80 -> 252, step: 8
5456 11:41:28.801462 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5457 11:41:28.804473 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5458 11:41:28.807698 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5459 11:41:28.811217 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5460 11:41:28.814336 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5461 11:41:28.821098 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5462 11:41:28.824734 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5463 11:41:28.827654 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5464 11:41:28.831160 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5465 11:41:28.834459 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5466 11:41:28.837671 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5467 11:41:28.844499 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5468 11:41:28.847599 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5469 11:41:28.850670 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5470 11:41:28.853848 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5471 11:41:28.857824 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5472 11:41:28.861051 ==
5473 11:41:28.861630 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 11:41:28.867452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 11:41:28.867878 ==
5476 11:41:28.868236 DQS Delay:
5477 11:41:28.870605 DQS0 = 0, DQS1 = 0
5478 11:41:28.871087 DQM Delay:
5479 11:41:28.873895 DQM0 = 96, DQM1 = 90
5480 11:41:28.874322 DQ Delay:
5481 11:41:28.877235 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5482 11:41:28.880896 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5483 11:41:28.884239 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5484 11:41:28.887516 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5485 11:41:28.887941
5486 11:41:28.888370
5487 11:41:28.888825 ==
5488 11:41:28.890860 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 11:41:28.894013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 11:41:28.894455 ==
5491 11:41:28.894978
5492 11:41:28.895320
5493 11:41:28.897448 TX Vref Scan disable
5494 11:41:28.900409 == TX Byte 0 ==
5495 11:41:28.903714 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5496 11:41:28.907145 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5497 11:41:28.910620 == TX Byte 1 ==
5498 11:41:28.913952 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5499 11:41:28.917099 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5500 11:41:28.917524 ==
5501 11:41:28.920355 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 11:41:28.927107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 11:41:28.927534 ==
5504 11:41:28.927878
5505 11:41:28.928192
5506 11:41:28.928496 TX Vref Scan disable
5507 11:41:28.930789 == TX Byte 0 ==
5508 11:41:28.934136 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5509 11:41:28.940692 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5510 11:41:28.941122 == TX Byte 1 ==
5511 11:41:28.943917 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5512 11:41:28.950254 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5513 11:41:28.950902
5514 11:41:28.951454 [DATLAT]
5515 11:41:28.951812 Freq=933, CH0 RK1
5516 11:41:28.952234
5517 11:41:28.953705 DATLAT Default: 0xb
5518 11:41:28.957311 0, 0xFFFF, sum = 0
5519 11:41:28.957779 1, 0xFFFF, sum = 0
5520 11:41:28.960568 2, 0xFFFF, sum = 0
5521 11:41:28.960954 3, 0xFFFF, sum = 0
5522 11:41:28.963777 4, 0xFFFF, sum = 0
5523 11:41:28.964244 5, 0xFFFF, sum = 0
5524 11:41:28.966819 6, 0xFFFF, sum = 0
5525 11:41:28.967267 7, 0xFFFF, sum = 0
5526 11:41:28.970041 8, 0xFFFF, sum = 0
5527 11:41:28.970532 9, 0xFFFF, sum = 0
5528 11:41:28.973347 10, 0x0, sum = 1
5529 11:41:28.973770 11, 0x0, sum = 2
5530 11:41:28.976384 12, 0x0, sum = 3
5531 11:41:28.977048 13, 0x0, sum = 4
5532 11:41:28.979785 best_step = 11
5533 11:41:28.980226
5534 11:41:28.980746 ==
5535 11:41:28.983016 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 11:41:28.986563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 11:41:28.987031 ==
5538 11:41:28.989598 RX Vref Scan: 0
5539 11:41:28.990022
5540 11:41:28.990365 RX Vref 0 -> 0, step: 1
5541 11:41:28.990686
5542 11:41:28.992995 RX Delay -61 -> 252, step: 4
5543 11:41:28.999780 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5544 11:41:29.003470 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5545 11:41:29.006690 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5546 11:41:29.009821 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5547 11:41:29.012960 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5548 11:41:29.016794 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5549 11:41:29.023178 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5550 11:41:29.026663 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5551 11:41:29.029356 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5552 11:41:29.032743 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5553 11:41:29.035828 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5554 11:41:29.042851 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5555 11:41:29.046152 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5556 11:41:29.049056 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5557 11:41:29.052181 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5558 11:41:29.059053 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5559 11:41:29.059623 ==
5560 11:41:29.062139 Dram Type= 6, Freq= 0, CH_0, rank 1
5561 11:41:29.065766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 11:41:29.066205 ==
5563 11:41:29.066548 DQS Delay:
5564 11:41:29.068874 DQS0 = 0, DQS1 = 0
5565 11:41:29.069417 DQM Delay:
5566 11:41:29.072345 DQM0 = 95, DQM1 = 87
5567 11:41:29.072924 DQ Delay:
5568 11:41:29.075606 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =94
5569 11:41:29.078724 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5570 11:41:29.082173 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =80
5571 11:41:29.085473 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5572 11:41:29.085935
5573 11:41:29.086305
5574 11:41:29.091894 [DQSOSCAuto] RK1, (LSB)MR18= 0x23f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 410 ps
5575 11:41:29.094937 CH0 RK1: MR19=504, MR18=23F4
5576 11:41:29.101670 CH0_RK1: MR19=0x504, MR18=0x23F4, DQSOSC=410, MR23=63, INC=64, DEC=42
5577 11:41:29.104954 [RxdqsGatingPostProcess] freq 933
5578 11:41:29.111300 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5579 11:41:29.114556 best DQS0 dly(2T, 0.5T) = (0, 10)
5580 11:41:29.117946 best DQS1 dly(2T, 0.5T) = (0, 11)
5581 11:41:29.121463 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5582 11:41:29.125116 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5583 11:41:29.128030 best DQS0 dly(2T, 0.5T) = (0, 10)
5584 11:41:29.128462 best DQS1 dly(2T, 0.5T) = (0, 11)
5585 11:41:29.131313 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5586 11:41:29.134740 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5587 11:41:29.137986 Pre-setting of DQS Precalculation
5588 11:41:29.144996 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5589 11:41:29.145419 ==
5590 11:41:29.148336 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 11:41:29.151625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 11:41:29.152087 ==
5593 11:41:29.158067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 11:41:29.164593 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5595 11:41:29.167761 [CA 0] Center 37 (7~67) winsize 61
5596 11:41:29.170954 [CA 1] Center 37 (6~68) winsize 63
5597 11:41:29.174105 [CA 2] Center 34 (4~65) winsize 62
5598 11:41:29.177647 [CA 3] Center 33 (3~64) winsize 62
5599 11:41:29.181177 [CA 4] Center 34 (4~64) winsize 61
5600 11:41:29.184426 [CA 5] Center 33 (3~64) winsize 62
5601 11:41:29.184928
5602 11:41:29.187496 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5603 11:41:29.187920
5604 11:41:29.190963 [CATrainingPosCal] consider 1 rank data
5605 11:41:29.194193 u2DelayCellTimex100 = 270/100 ps
5606 11:41:29.197467 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5607 11:41:29.200458 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5608 11:41:29.203929 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5609 11:41:29.207579 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 11:41:29.210670 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 11:41:29.214031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5612 11:41:29.214452
5613 11:41:29.220383 CA PerBit enable=1, Macro0, CA PI delay=33
5614 11:41:29.220873
5615 11:41:29.223609 [CBTSetCACLKResult] CA Dly = 33
5616 11:41:29.224032 CS Dly: 6 (0~37)
5617 11:41:29.224370 ==
5618 11:41:29.227445 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 11:41:29.230283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 11:41:29.230710 ==
5621 11:41:29.237193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5622 11:41:29.243359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5623 11:41:29.246988 [CA 0] Center 36 (6~67) winsize 62
5624 11:41:29.250319 [CA 1] Center 37 (7~68) winsize 62
5625 11:41:29.253638 [CA 2] Center 34 (4~65) winsize 62
5626 11:41:29.256647 [CA 3] Center 34 (3~65) winsize 63
5627 11:41:29.260733 [CA 4] Center 34 (4~65) winsize 62
5628 11:41:29.263276 [CA 5] Center 33 (3~64) winsize 62
5629 11:41:29.263855
5630 11:41:29.266581 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5631 11:41:29.267021
5632 11:41:29.270521 [CATrainingPosCal] consider 2 rank data
5633 11:41:29.273225 u2DelayCellTimex100 = 270/100 ps
5634 11:41:29.277007 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5635 11:41:29.280220 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5636 11:41:29.283376 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5637 11:41:29.286660 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5638 11:41:29.293016 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5639 11:41:29.296504 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5640 11:41:29.297198
5641 11:41:29.300024 CA PerBit enable=1, Macro0, CA PI delay=33
5642 11:41:29.300416
5643 11:41:29.303359 [CBTSetCACLKResult] CA Dly = 33
5644 11:41:29.303786 CS Dly: 7 (0~39)
5645 11:41:29.304120
5646 11:41:29.306708 ----->DramcWriteLeveling(PI) begin...
5647 11:41:29.307133 ==
5648 11:41:29.310137 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 11:41:29.316467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 11:41:29.316957 ==
5651 11:41:29.319985 Write leveling (Byte 0): 27 => 27
5652 11:41:29.322355 Write leveling (Byte 1): 27 => 27
5653 11:41:29.322461 DramcWriteLeveling(PI) end<-----
5654 11:41:29.325927
5655 11:41:29.326026 ==
5656 11:41:29.329046 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 11:41:29.332631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 11:41:29.332717 ==
5659 11:41:29.335691 [Gating] SW mode calibration
5660 11:41:29.342325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5661 11:41:29.346117 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5662 11:41:29.352089 0 14 0 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
5663 11:41:29.355971 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 11:41:29.358986 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 11:41:29.365697 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 11:41:29.369043 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 11:41:29.372510 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 11:41:29.378946 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
5669 11:41:29.382362 0 14 28 | B1->B0 | 2e2e 2f2f | 0 0 | (1 1) (1 1)
5670 11:41:29.385327 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5671 11:41:29.392057 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 11:41:29.395404 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 11:41:29.398645 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 11:41:29.405615 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 11:41:29.408903 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 11:41:29.412005 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5677 11:41:29.418709 0 15 28 | B1->B0 | 3737 4141 | 1 0 | (1 1) (0 0)
5678 11:41:29.421712 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 11:41:29.425081 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 11:41:29.431695 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 11:41:29.435391 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 11:41:29.438333 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 11:41:29.445092 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5684 11:41:29.448451 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5685 11:41:29.451654 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5686 11:41:29.458079 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 11:41:29.461672 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 11:41:29.464612 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 11:41:29.471280 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 11:41:29.474786 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 11:41:29.478152 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 11:41:29.484364 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 11:41:29.487602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 11:41:29.491387 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 11:41:29.497809 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 11:41:29.501191 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 11:41:29.504756 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 11:41:29.511796 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 11:41:29.514948 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 11:41:29.517567 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5701 11:41:29.524388 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5702 11:41:29.524491 Total UI for P1: 0, mck2ui 16
5703 11:41:29.530621 best dqsien dly found for B0: ( 1, 2, 24)
5704 11:41:29.534018 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5705 11:41:29.537564 Total UI for P1: 0, mck2ui 16
5706 11:41:29.540891 best dqsien dly found for B1: ( 1, 2, 26)
5707 11:41:29.544209 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5708 11:41:29.547771 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5709 11:41:29.547852
5710 11:41:29.550823 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5711 11:41:29.554292 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5712 11:41:29.557386 [Gating] SW calibration Done
5713 11:41:29.557487 ==
5714 11:41:29.560721 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 11:41:29.563788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 11:41:29.567075 ==
5717 11:41:29.567160 RX Vref Scan: 0
5718 11:41:29.567226
5719 11:41:29.570695 RX Vref 0 -> 0, step: 1
5720 11:41:29.570777
5721 11:41:29.574112 RX Delay -80 -> 252, step: 8
5722 11:41:29.577119 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5723 11:41:29.580753 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5724 11:41:29.583997 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5725 11:41:29.587220 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5726 11:41:29.590693 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5727 11:41:29.597214 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5728 11:41:29.600392 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5729 11:41:29.603565 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5730 11:41:29.606880 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5731 11:41:29.610054 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5732 11:41:29.617060 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5733 11:41:29.620419 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5734 11:41:29.623178 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5735 11:41:29.626951 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5736 11:41:29.629848 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5737 11:41:29.636715 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5738 11:41:29.636797 ==
5739 11:41:29.640009 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 11:41:29.643392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:41:29.643478 ==
5742 11:41:29.643549 DQS Delay:
5743 11:41:29.646411 DQS0 = 0, DQS1 = 0
5744 11:41:29.646518 DQM Delay:
5745 11:41:29.649883 DQM0 = 102, DQM1 = 91
5746 11:41:29.649982 DQ Delay:
5747 11:41:29.652977 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =103
5748 11:41:29.656479 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5749 11:41:29.659877 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5750 11:41:29.663323 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5751 11:41:29.663405
5752 11:41:29.663470
5753 11:41:29.663531 ==
5754 11:41:29.666519 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 11:41:29.669522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 11:41:29.673190 ==
5757 11:41:29.673271
5758 11:41:29.673336
5759 11:41:29.673396 TX Vref Scan disable
5760 11:41:29.676386 == TX Byte 0 ==
5761 11:41:29.679524 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5762 11:41:29.682896 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5763 11:41:29.686181 == TX Byte 1 ==
5764 11:41:29.689715 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5765 11:41:29.693196 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5766 11:41:29.696391 ==
5767 11:41:29.696473 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 11:41:29.702767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 11:41:29.702873 ==
5770 11:41:29.702966
5771 11:41:29.703056
5772 11:41:29.706134 TX Vref Scan disable
5773 11:41:29.706215 == TX Byte 0 ==
5774 11:41:29.712711 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5775 11:41:29.715448 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5776 11:41:29.715549 == TX Byte 1 ==
5777 11:41:29.722494 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5778 11:41:29.725600 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5779 11:41:29.725710
5780 11:41:29.725806 [DATLAT]
5781 11:41:29.728867 Freq=933, CH1 RK0
5782 11:41:29.728964
5783 11:41:29.729053 DATLAT Default: 0xd
5784 11:41:29.732094 0, 0xFFFF, sum = 0
5785 11:41:29.732191 1, 0xFFFF, sum = 0
5786 11:41:29.735497 2, 0xFFFF, sum = 0
5787 11:41:29.735586 3, 0xFFFF, sum = 0
5788 11:41:29.738712 4, 0xFFFF, sum = 0
5789 11:41:29.742049 5, 0xFFFF, sum = 0
5790 11:41:29.742149 6, 0xFFFF, sum = 0
5791 11:41:29.745137 7, 0xFFFF, sum = 0
5792 11:41:29.745235 8, 0xFFFF, sum = 0
5793 11:41:29.748690 9, 0xFFFF, sum = 0
5794 11:41:29.748789 10, 0x0, sum = 1
5795 11:41:29.752126 11, 0x0, sum = 2
5796 11:41:29.752208 12, 0x0, sum = 3
5797 11:41:29.752275 13, 0x0, sum = 4
5798 11:41:29.755549 best_step = 11
5799 11:41:29.755630
5800 11:41:29.755695 ==
5801 11:41:29.758459 Dram Type= 6, Freq= 0, CH_1, rank 0
5802 11:41:29.761729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 11:41:29.761811 ==
5804 11:41:29.765210 RX Vref Scan: 1
5805 11:41:29.765291
5806 11:41:29.768457 RX Vref 0 -> 0, step: 1
5807 11:41:29.768577
5808 11:41:29.768643 RX Delay -61 -> 252, step: 4
5809 11:41:29.768704
5810 11:41:29.772273 Set Vref, RX VrefLevel [Byte0]: 48
5811 11:41:29.774969 [Byte1]: 54
5812 11:41:29.780004
5813 11:41:29.780085 Final RX Vref Byte 0 = 48 to rank0
5814 11:41:29.782778 Final RX Vref Byte 1 = 54 to rank0
5815 11:41:29.786254 Final RX Vref Byte 0 = 48 to rank1
5816 11:41:29.790008 Final RX Vref Byte 1 = 54 to rank1==
5817 11:41:29.793122 Dram Type= 6, Freq= 0, CH_1, rank 0
5818 11:41:29.799935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 11:41:29.800017 ==
5820 11:41:29.800083 DQS Delay:
5821 11:41:29.803072 DQS0 = 0, DQS1 = 0
5822 11:41:29.803153 DQM Delay:
5823 11:41:29.803218 DQM0 = 101, DQM1 = 94
5824 11:41:29.806072 DQ Delay:
5825 11:41:29.809608 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =100
5826 11:41:29.813254 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5827 11:41:29.815946 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5828 11:41:29.819221 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5829 11:41:29.819302
5830 11:41:29.819367
5831 11:41:29.826101 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5832 11:41:29.828926 CH1 RK0: MR19=505, MR18=1A0A
5833 11:41:29.835604 CH1_RK0: MR19=0x505, MR18=0x1A0A, DQSOSC=413, MR23=63, INC=63, DEC=42
5834 11:41:29.835704
5835 11:41:29.839029 ----->DramcWriteLeveling(PI) begin...
5836 11:41:29.839138 ==
5837 11:41:29.842034 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 11:41:29.845776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 11:41:29.849116 ==
5840 11:41:29.852170 Write leveling (Byte 0): 25 => 25
5841 11:41:29.852276 Write leveling (Byte 1): 32 => 32
5842 11:41:29.855352 DramcWriteLeveling(PI) end<-----
5843 11:41:29.855434
5844 11:41:29.858969 ==
5845 11:41:29.859051 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 11:41:29.865132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 11:41:29.865239 ==
5848 11:41:29.868641 [Gating] SW mode calibration
5849 11:41:29.875539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5850 11:41:29.878198 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5851 11:41:29.885378 0 14 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5852 11:41:29.888574 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 11:41:29.891419 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 11:41:29.897987 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 11:41:29.901313 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 11:41:29.905106 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 11:41:29.911461 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
5858 11:41:29.914544 0 14 28 | B1->B0 | 2a2a 3030 | 0 0 | (1 1) (0 1)
5859 11:41:29.917790 0 15 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 0)
5860 11:41:29.924553 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 11:41:29.927857 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 11:41:29.931026 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 11:41:29.937655 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 11:41:29.941060 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 11:41:29.944105 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5866 11:41:29.950995 0 15 28 | B1->B0 | 3d3d 2e2e | 0 0 | (0 0) (0 0)
5867 11:41:29.954078 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5868 11:41:29.957101 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 11:41:29.963918 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 11:41:29.967006 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 11:41:29.970879 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 11:41:29.977457 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 11:41:29.980193 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5874 11:41:29.984167 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5875 11:41:29.990174 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 11:41:29.993749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 11:41:29.996893 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 11:41:30.003989 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 11:41:30.006827 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 11:41:30.009969 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 11:41:30.016685 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 11:41:30.019824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 11:41:30.023292 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 11:41:30.029759 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 11:41:30.033368 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 11:41:30.036337 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 11:41:30.043102 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 11:41:30.046128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 11:41:30.049282 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 11:41:30.056367 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5891 11:41:30.059281 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5892 11:41:30.062432 Total UI for P1: 0, mck2ui 16
5893 11:41:30.066104 best dqsien dly found for B0: ( 1, 2, 30)
5894 11:41:30.069652 Total UI for P1: 0, mck2ui 16
5895 11:41:30.072820 best dqsien dly found for B1: ( 1, 2, 28)
5896 11:41:30.075641 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5897 11:41:30.079035 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5898 11:41:30.079121
5899 11:41:30.082208 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5900 11:41:30.089000 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5901 11:41:30.089083 [Gating] SW calibration Done
5902 11:41:30.089149 ==
5903 11:41:30.092297 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 11:41:30.098772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 11:41:30.098876 ==
5906 11:41:30.098968 RX Vref Scan: 0
5907 11:41:30.099056
5908 11:41:30.101792 RX Vref 0 -> 0, step: 1
5909 11:41:30.101876
5910 11:41:30.105190 RX Delay -80 -> 252, step: 8
5911 11:41:30.108437 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5912 11:41:30.111821 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5913 11:41:30.115123 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5914 11:41:30.121958 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5915 11:41:30.125037 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5916 11:41:30.128234 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5917 11:41:30.131577 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5918 11:41:30.135407 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5919 11:41:30.138079 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5920 11:41:30.144594 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5921 11:41:30.148019 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5922 11:41:30.151192 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5923 11:41:30.154445 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5924 11:41:30.157587 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5925 11:41:30.164831 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5926 11:41:30.167797 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5927 11:41:30.167885 ==
5928 11:41:30.171181 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 11:41:30.174669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 11:41:30.174772 ==
5931 11:41:30.177397 DQS Delay:
5932 11:41:30.177499 DQS0 = 0, DQS1 = 0
5933 11:41:30.177580 DQM Delay:
5934 11:41:30.180774 DQM0 = 99, DQM1 = 91
5935 11:41:30.180885 DQ Delay:
5936 11:41:30.184112 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =95
5937 11:41:30.187963 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5938 11:41:30.191134 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5939 11:41:30.194067 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5940 11:41:30.194220
5941 11:41:30.194342
5942 11:41:30.194455 ==
5943 11:41:30.197247 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 11:41:30.203996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 11:41:30.204200 ==
5946 11:41:30.204361
5947 11:41:30.204509
5948 11:41:30.204675 TX Vref Scan disable
5949 11:41:30.207778 == TX Byte 0 ==
5950 11:41:30.211468 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5951 11:41:30.217787 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5952 11:41:30.218088 == TX Byte 1 ==
5953 11:41:30.221104 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5954 11:41:30.228285 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5955 11:41:30.228743 ==
5956 11:41:30.230855 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 11:41:30.234463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 11:41:30.234887 ==
5959 11:41:30.235219
5960 11:41:30.235550
5961 11:41:30.237891 TX Vref Scan disable
5962 11:41:30.241107 == TX Byte 0 ==
5963 11:41:30.244357 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5964 11:41:30.247850 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5965 11:41:30.251012 == TX Byte 1 ==
5966 11:41:30.254083 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5967 11:41:30.257239 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5968 11:41:30.257663
5969 11:41:30.257999 [DATLAT]
5970 11:41:30.260463 Freq=933, CH1 RK1
5971 11:41:30.260940
5972 11:41:30.264320 DATLAT Default: 0xb
5973 11:41:30.264808 0, 0xFFFF, sum = 0
5974 11:41:30.267395 1, 0xFFFF, sum = 0
5975 11:41:30.267822 2, 0xFFFF, sum = 0
5976 11:41:30.270711 3, 0xFFFF, sum = 0
5977 11:41:30.271138 4, 0xFFFF, sum = 0
5978 11:41:30.273915 5, 0xFFFF, sum = 0
5979 11:41:30.274344 6, 0xFFFF, sum = 0
5980 11:41:30.277320 7, 0xFFFF, sum = 0
5981 11:41:30.277856 8, 0xFFFF, sum = 0
5982 11:41:30.280642 9, 0xFFFF, sum = 0
5983 11:41:30.281068 10, 0x0, sum = 1
5984 11:41:30.283995 11, 0x0, sum = 2
5985 11:41:30.284422 12, 0x0, sum = 3
5986 11:41:30.287474 13, 0x0, sum = 4
5987 11:41:30.287904 best_step = 11
5988 11:41:30.288238
5989 11:41:30.288601 ==
5990 11:41:30.290520 Dram Type= 6, Freq= 0, CH_1, rank 1
5991 11:41:30.294034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5992 11:41:30.297407 ==
5993 11:41:30.297828 RX Vref Scan: 0
5994 11:41:30.298163
5995 11:41:30.300775 RX Vref 0 -> 0, step: 1
5996 11:41:30.301347
5997 11:41:30.303762 RX Delay -61 -> 252, step: 4
5998 11:41:30.307058 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5999 11:41:30.309985 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
6000 11:41:30.316770 iDelay=207, Bit 2, Center 92 (7 ~ 178) 172
6001 11:41:30.320143 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6002 11:41:30.323120 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6003 11:41:30.326445 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6004 11:41:30.330085 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6005 11:41:30.336411 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6006 11:41:30.339793 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6007 11:41:30.342943 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6008 11:41:30.346450 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6009 11:41:30.349298 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6010 11:41:30.353149 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6011 11:41:30.359572 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6012 11:41:30.362971 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6013 11:41:30.366371 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6014 11:41:30.366797 ==
6015 11:41:30.369347 Dram Type= 6, Freq= 0, CH_1, rank 1
6016 11:41:30.372370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6017 11:41:30.375609 ==
6018 11:41:30.376086 DQS Delay:
6019 11:41:30.376622 DQS0 = 0, DQS1 = 0
6020 11:41:30.379016 DQM Delay:
6021 11:41:30.379531 DQM0 = 101, DQM1 = 93
6022 11:41:30.382424 DQ Delay:
6023 11:41:30.385891 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
6024 11:41:30.389179 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
6025 11:41:30.392238 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
6026 11:41:30.395981 DQ12 =102, DQ13 =102, DQ14 =98, DQ15 =102
6027 11:41:30.396451
6028 11:41:30.397012
6029 11:41:30.402062 [DQSOSCAuto] RK1, (LSB)MR18= 0x4fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 420 ps
6030 11:41:30.405305 CH1 RK1: MR19=504, MR18=4FD
6031 11:41:30.412492 CH1_RK1: MR19=0x504, MR18=0x4FD, DQSOSC=420, MR23=63, INC=61, DEC=40
6032 11:41:30.415688 [RxdqsGatingPostProcess] freq 933
6033 11:41:30.418482 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6034 11:41:30.422349 best DQS0 dly(2T, 0.5T) = (0, 10)
6035 11:41:30.425171 best DQS1 dly(2T, 0.5T) = (0, 10)
6036 11:41:30.428702 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6037 11:41:30.432017 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6038 11:41:30.435046 best DQS0 dly(2T, 0.5T) = (0, 10)
6039 11:41:30.438349 best DQS1 dly(2T, 0.5T) = (0, 10)
6040 11:41:30.442041 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6041 11:41:30.445435 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6042 11:41:30.448303 Pre-setting of DQS Precalculation
6043 11:41:30.455209 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6044 11:41:30.461750 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6045 11:41:30.468216 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6046 11:41:30.468720
6047 11:41:30.469064
6048 11:41:30.471760 [Calibration Summary] 1866 Mbps
6049 11:41:30.472236 CH 0, Rank 0
6050 11:41:30.475070 SW Impedance : PASS
6051 11:41:30.478216 DUTY Scan : NO K
6052 11:41:30.478642 ZQ Calibration : PASS
6053 11:41:30.481475 Jitter Meter : NO K
6054 11:41:30.481905 CBT Training : PASS
6055 11:41:30.484678 Write leveling : PASS
6056 11:41:30.487896 RX DQS gating : PASS
6057 11:41:30.488277 RX DQ/DQS(RDDQC) : PASS
6058 11:41:30.491376 TX DQ/DQS : PASS
6059 11:41:30.494997 RX DATLAT : PASS
6060 11:41:30.495435 RX DQ/DQS(Engine): PASS
6061 11:41:30.498020 TX OE : NO K
6062 11:41:30.498435 All Pass.
6063 11:41:30.498782
6064 11:41:30.501307 CH 0, Rank 1
6065 11:41:30.501734 SW Impedance : PASS
6066 11:41:30.504673 DUTY Scan : NO K
6067 11:41:30.508017 ZQ Calibration : PASS
6068 11:41:30.508441 Jitter Meter : NO K
6069 11:41:30.511084 CBT Training : PASS
6070 11:41:30.514391 Write leveling : PASS
6071 11:41:30.514850 RX DQS gating : PASS
6072 11:41:30.518123 RX DQ/DQS(RDDQC) : PASS
6073 11:41:30.520968 TX DQ/DQS : PASS
6074 11:41:30.521399 RX DATLAT : PASS
6075 11:41:30.524393 RX DQ/DQS(Engine): PASS
6076 11:41:30.527839 TX OE : NO K
6077 11:41:30.528265 All Pass.
6078 11:41:30.528661
6079 11:41:30.528997 CH 1, Rank 0
6080 11:41:30.530695 SW Impedance : PASS
6081 11:41:30.534145 DUTY Scan : NO K
6082 11:41:30.534606 ZQ Calibration : PASS
6083 11:41:30.537436 Jitter Meter : NO K
6084 11:41:30.540659 CBT Training : PASS
6085 11:41:30.541160 Write leveling : PASS
6086 11:41:30.544346 RX DQS gating : PASS
6087 11:41:30.544813 RX DQ/DQS(RDDQC) : PASS
6088 11:41:30.547293 TX DQ/DQS : PASS
6089 11:41:30.550646 RX DATLAT : PASS
6090 11:41:30.551061 RX DQ/DQS(Engine): PASS
6091 11:41:30.553894 TX OE : NO K
6092 11:41:30.554313 All Pass.
6093 11:41:30.554643
6094 11:41:30.557155 CH 1, Rank 1
6095 11:41:30.557573 SW Impedance : PASS
6096 11:41:30.560961 DUTY Scan : NO K
6097 11:41:30.564066 ZQ Calibration : PASS
6098 11:41:30.564483 Jitter Meter : NO K
6099 11:41:30.567565 CBT Training : PASS
6100 11:41:30.570316 Write leveling : PASS
6101 11:41:30.570884 RX DQS gating : PASS
6102 11:41:30.573835 RX DQ/DQS(RDDQC) : PASS
6103 11:41:30.577258 TX DQ/DQS : PASS
6104 11:41:30.577678 RX DATLAT : PASS
6105 11:41:30.580178 RX DQ/DQS(Engine): PASS
6106 11:41:30.583554 TX OE : NO K
6107 11:41:30.583972 All Pass.
6108 11:41:30.584305
6109 11:41:30.587108 DramC Write-DBI off
6110 11:41:30.587756 PER_BANK_REFRESH: Hybrid Mode
6111 11:41:30.590602 TX_TRACKING: ON
6112 11:41:30.597386 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6113 11:41:30.603469 [FAST_K] Save calibration result to emmc
6114 11:41:30.607392 dramc_set_vcore_voltage set vcore to 650000
6115 11:41:30.607910 Read voltage for 400, 6
6116 11:41:30.610009 Vio18 = 0
6117 11:41:30.610585 Vcore = 650000
6118 11:41:30.611074 Vdram = 0
6119 11:41:30.613233 Vddq = 0
6120 11:41:30.613688 Vmddr = 0
6121 11:41:30.616611 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6122 11:41:30.623265 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6123 11:41:30.626667 MEM_TYPE=3, freq_sel=20
6124 11:41:30.629967 sv_algorithm_assistance_LP4_800
6125 11:41:30.633126 ============ PULL DRAM RESETB DOWN ============
6126 11:41:30.636418 ========== PULL DRAM RESETB DOWN end =========
6127 11:41:30.643575 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6128 11:41:30.646900 ===================================
6129 11:41:30.647465 LPDDR4 DRAM CONFIGURATION
6130 11:41:30.649918 ===================================
6131 11:41:30.653106 EX_ROW_EN[0] = 0x0
6132 11:41:30.653674 EX_ROW_EN[1] = 0x0
6133 11:41:30.656154 LP4Y_EN = 0x0
6134 11:41:30.656646 WORK_FSP = 0x0
6135 11:41:30.659491 WL = 0x2
6136 11:41:30.662932 RL = 0x2
6137 11:41:30.663386 BL = 0x2
6138 11:41:30.666367 RPST = 0x0
6139 11:41:30.666829 RD_PRE = 0x0
6140 11:41:30.669611 WR_PRE = 0x1
6141 11:41:30.670031 WR_PST = 0x0
6142 11:41:30.673051 DBI_WR = 0x0
6143 11:41:30.673471 DBI_RD = 0x0
6144 11:41:30.676332 OTF = 0x1
6145 11:41:30.679501 ===================================
6146 11:41:30.683221 ===================================
6147 11:41:30.683645 ANA top config
6148 11:41:30.686012 ===================================
6149 11:41:30.689566 DLL_ASYNC_EN = 0
6150 11:41:30.692812 ALL_SLAVE_EN = 1
6151 11:41:30.693231 NEW_RANK_MODE = 1
6152 11:41:30.695671 DLL_IDLE_MODE = 1
6153 11:41:30.699007 LP45_APHY_COMB_EN = 1
6154 11:41:30.702242 TX_ODT_DIS = 1
6155 11:41:30.705614 NEW_8X_MODE = 1
6156 11:41:30.709380 ===================================
6157 11:41:30.712276 ===================================
6158 11:41:30.715576 data_rate = 800
6159 11:41:30.715997 CKR = 1
6160 11:41:30.718904 DQ_P2S_RATIO = 4
6161 11:41:30.722404 ===================================
6162 11:41:30.725798 CA_P2S_RATIO = 4
6163 11:41:30.729107 DQ_CA_OPEN = 0
6164 11:41:30.732093 DQ_SEMI_OPEN = 1
6165 11:41:30.735249 CA_SEMI_OPEN = 1
6166 11:41:30.735669 CA_FULL_RATE = 0
6167 11:41:30.739194 DQ_CKDIV4_EN = 0
6168 11:41:30.742137 CA_CKDIV4_EN = 1
6169 11:41:30.745642 CA_PREDIV_EN = 0
6170 11:41:30.748710 PH8_DLY = 0
6171 11:41:30.752012 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6172 11:41:30.752433 DQ_AAMCK_DIV = 0
6173 11:41:30.755415 CA_AAMCK_DIV = 0
6174 11:41:30.758632 CA_ADMCK_DIV = 4
6175 11:41:30.762210 DQ_TRACK_CA_EN = 0
6176 11:41:30.765108 CA_PICK = 800
6177 11:41:30.768704 CA_MCKIO = 400
6178 11:41:30.771920 MCKIO_SEMI = 400
6179 11:41:30.772342 PLL_FREQ = 3016
6180 11:41:30.775024 DQ_UI_PI_RATIO = 32
6181 11:41:30.778425 CA_UI_PI_RATIO = 32
6182 11:41:30.782075 ===================================
6183 11:41:30.784887 ===================================
6184 11:41:30.788234 memory_type:LPDDR4
6185 11:41:30.791366 GP_NUM : 10
6186 11:41:30.791865 SRAM_EN : 1
6187 11:41:30.794960 MD32_EN : 0
6188 11:41:30.798677 ===================================
6189 11:41:30.799098 [ANA_INIT] >>>>>>>>>>>>>>
6190 11:41:30.801452 <<<<<< [CONFIGURE PHASE]: ANA_TX
6191 11:41:30.804822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6192 11:41:30.808617 ===================================
6193 11:41:30.811800 data_rate = 800,PCW = 0X7400
6194 11:41:30.814772 ===================================
6195 11:41:30.818082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6196 11:41:30.824386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6197 11:41:30.834788 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6198 11:41:30.841401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6199 11:41:30.844583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6200 11:41:30.847508 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6201 11:41:30.847930 [ANA_INIT] flow start
6202 11:41:30.851125 [ANA_INIT] PLL >>>>>>>>
6203 11:41:30.854191 [ANA_INIT] PLL <<<<<<<<
6204 11:41:30.857766 [ANA_INIT] MIDPI >>>>>>>>
6205 11:41:30.858187 [ANA_INIT] MIDPI <<<<<<<<
6206 11:41:30.861269 [ANA_INIT] DLL >>>>>>>>
6207 11:41:30.863912 [ANA_INIT] flow end
6208 11:41:30.867416 ============ LP4 DIFF to SE enter ============
6209 11:41:30.870684 ============ LP4 DIFF to SE exit ============
6210 11:41:30.873826 [ANA_INIT] <<<<<<<<<<<<<
6211 11:41:30.877435 [Flow] Enable top DCM control >>>>>
6212 11:41:30.880616 [Flow] Enable top DCM control <<<<<
6213 11:41:30.883831 Enable DLL master slave shuffle
6214 11:41:30.887561 ==============================================================
6215 11:41:30.890822 Gating Mode config
6216 11:41:30.897284 ==============================================================
6217 11:41:30.897708 Config description:
6218 11:41:30.907271 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6219 11:41:30.913820 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6220 11:41:30.920192 SELPH_MODE 0: By rank 1: By Phase
6221 11:41:30.923346 ==============================================================
6222 11:41:30.926798 GAT_TRACK_EN = 0
6223 11:41:30.930149 RX_GATING_MODE = 2
6224 11:41:30.933024 RX_GATING_TRACK_MODE = 2
6225 11:41:30.936550 SELPH_MODE = 1
6226 11:41:30.939818 PICG_EARLY_EN = 1
6227 11:41:30.943308 VALID_LAT_VALUE = 1
6228 11:41:30.946160 ==============================================================
6229 11:41:30.949650 Enter into Gating configuration >>>>
6230 11:41:30.952790 Exit from Gating configuration <<<<
6231 11:41:30.956279 Enter into DVFS_PRE_config >>>>>
6232 11:41:30.969517 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6233 11:41:30.972886 Exit from DVFS_PRE_config <<<<<
6234 11:41:30.976081 Enter into PICG configuration >>>>
6235 11:41:30.979360 Exit from PICG configuration <<<<
6236 11:41:30.979776 [RX_INPUT] configuration >>>>>
6237 11:41:30.982598 [RX_INPUT] configuration <<<<<
6238 11:41:30.989140 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6239 11:41:30.992655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6240 11:41:30.999008 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6241 11:41:31.005455 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6242 11:41:31.012227 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6243 11:41:31.018850 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6244 11:41:31.022121 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6245 11:41:31.025410 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6246 11:41:31.032094 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6247 11:41:31.035439 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6248 11:41:31.038843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6249 11:41:31.045588 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6250 11:41:31.048817 ===================================
6251 11:41:31.049243 LPDDR4 DRAM CONFIGURATION
6252 11:41:31.051892 ===================================
6253 11:41:31.055003 EX_ROW_EN[0] = 0x0
6254 11:41:31.055436 EX_ROW_EN[1] = 0x0
6255 11:41:31.058573 LP4Y_EN = 0x0
6256 11:41:31.059000 WORK_FSP = 0x0
6257 11:41:31.061679 WL = 0x2
6258 11:41:31.065369 RL = 0x2
6259 11:41:31.065793 BL = 0x2
6260 11:41:31.067965 RPST = 0x0
6261 11:41:31.068799 RD_PRE = 0x0
6262 11:41:31.071360 WR_PRE = 0x1
6263 11:41:31.071925 WR_PST = 0x0
6264 11:41:31.074828 DBI_WR = 0x0
6265 11:41:31.075297 DBI_RD = 0x0
6266 11:41:31.078094 OTF = 0x1
6267 11:41:31.081788 ===================================
6268 11:41:31.084682 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6269 11:41:31.087935 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6270 11:41:31.094796 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6271 11:41:31.098372 ===================================
6272 11:41:31.098795 LPDDR4 DRAM CONFIGURATION
6273 11:41:31.101713 ===================================
6274 11:41:31.104838 EX_ROW_EN[0] = 0x10
6275 11:41:31.105316 EX_ROW_EN[1] = 0x0
6276 11:41:31.107820 LP4Y_EN = 0x0
6277 11:41:31.108241 WORK_FSP = 0x0
6278 11:41:31.111106 WL = 0x2
6279 11:41:31.114450 RL = 0x2
6280 11:41:31.114868 BL = 0x2
6281 11:41:31.117974 RPST = 0x0
6282 11:41:31.118394 RD_PRE = 0x0
6283 11:41:31.121163 WR_PRE = 0x1
6284 11:41:31.121601 WR_PST = 0x0
6285 11:41:31.125070 DBI_WR = 0x0
6286 11:41:31.125492 DBI_RD = 0x0
6287 11:41:31.128270 OTF = 0x1
6288 11:41:31.131140 ===================================
6289 11:41:31.137488 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6290 11:41:31.140849 nWR fixed to 30
6291 11:41:31.141277 [ModeRegInit_LP4] CH0 RK0
6292 11:41:31.144187 [ModeRegInit_LP4] CH0 RK1
6293 11:41:31.147758 [ModeRegInit_LP4] CH1 RK0
6294 11:41:31.150735 [ModeRegInit_LP4] CH1 RK1
6295 11:41:31.151157 match AC timing 19
6296 11:41:31.154184 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6297 11:41:31.160702 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6298 11:41:31.163891 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6299 11:41:31.167893 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6300 11:41:31.173722 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6301 11:41:31.174277 ==
6302 11:41:31.177227 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 11:41:31.180578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 11:41:31.181007 ==
6305 11:41:31.187289 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6306 11:41:31.193968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6307 11:41:31.196768 [CA 0] Center 36 (8~64) winsize 57
6308 11:41:31.197197 [CA 1] Center 36 (8~64) winsize 57
6309 11:41:31.200435 [CA 2] Center 36 (8~64) winsize 57
6310 11:41:31.203609 [CA 3] Center 36 (8~64) winsize 57
6311 11:41:31.206753 [CA 4] Center 36 (8~64) winsize 57
6312 11:41:31.210455 [CA 5] Center 36 (8~64) winsize 57
6313 11:41:31.210974
6314 11:41:31.213844 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6315 11:41:31.214359
6316 11:41:31.220582 [CATrainingPosCal] consider 1 rank data
6317 11:41:31.221010 u2DelayCellTimex100 = 270/100 ps
6318 11:41:31.223377 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 11:41:31.230352 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 11:41:31.233242 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 11:41:31.236510 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 11:41:31.240045 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 11:41:31.243215 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 11:41:31.243641
6325 11:41:31.246700 CA PerBit enable=1, Macro0, CA PI delay=36
6326 11:41:31.247128
6327 11:41:31.249827 [CBTSetCACLKResult] CA Dly = 36
6328 11:41:31.252817 CS Dly: 1 (0~32)
6329 11:41:31.253241 ==
6330 11:41:31.256475 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 11:41:31.259870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 11:41:31.260301 ==
6333 11:41:31.266134 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6334 11:41:31.269862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6335 11:41:31.273070 [CA 0] Center 36 (8~64) winsize 57
6336 11:41:31.275973 [CA 1] Center 36 (8~64) winsize 57
6337 11:41:31.279270 [CA 2] Center 36 (8~64) winsize 57
6338 11:41:31.283219 [CA 3] Center 36 (8~64) winsize 57
6339 11:41:31.286544 [CA 4] Center 36 (8~64) winsize 57
6340 11:41:31.289198 [CA 5] Center 36 (8~64) winsize 57
6341 11:41:31.289710
6342 11:41:31.292466 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6343 11:41:31.293005
6344 11:41:31.295670 [CATrainingPosCal] consider 2 rank data
6345 11:41:31.299377 u2DelayCellTimex100 = 270/100 ps
6346 11:41:31.303076 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 11:41:31.309335 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 11:41:31.312296 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 11:41:31.315443 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 11:41:31.318856 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 11:41:31.321970 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6352 11:41:31.322513
6353 11:41:31.325351 CA PerBit enable=1, Macro0, CA PI delay=36
6354 11:41:31.325847
6355 11:41:31.329019 [CBTSetCACLKResult] CA Dly = 36
6356 11:41:31.332007 CS Dly: 1 (0~32)
6357 11:41:31.332584
6358 11:41:31.335464 ----->DramcWriteLeveling(PI) begin...
6359 11:41:31.335968 ==
6360 11:41:31.338659 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 11:41:31.341936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 11:41:31.342484 ==
6363 11:41:31.345208 Write leveling (Byte 0): 40 => 8
6364 11:41:31.348878 Write leveling (Byte 1): 32 => 0
6365 11:41:31.352153 DramcWriteLeveling(PI) end<-----
6366 11:41:31.352595
6367 11:41:31.352925 ==
6368 11:41:31.355273 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 11:41:31.358928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 11:41:31.359382 ==
6371 11:41:31.362003 [Gating] SW mode calibration
6372 11:41:31.368633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6373 11:41:31.375151 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6374 11:41:31.378583 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6375 11:41:31.381457 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6376 11:41:31.388281 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 11:41:31.391517 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6378 11:41:31.394830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 11:41:31.401217 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 11:41:31.404985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6381 11:41:31.407830 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6382 11:41:31.415378 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6383 11:41:31.415788 Total UI for P1: 0, mck2ui 16
6384 11:41:31.421027 best dqsien dly found for B0: ( 0, 14, 24)
6385 11:41:31.421433 Total UI for P1: 0, mck2ui 16
6386 11:41:31.427521 best dqsien dly found for B1: ( 0, 14, 24)
6387 11:41:31.431003 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6388 11:41:31.434501 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6389 11:41:31.434907
6390 11:41:31.437476 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6391 11:41:31.441062 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6392 11:41:31.444477 [Gating] SW calibration Done
6393 11:41:31.444926 ==
6394 11:41:31.447804 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 11:41:31.451166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 11:41:31.451577 ==
6397 11:41:31.454425 RX Vref Scan: 0
6398 11:41:31.454839
6399 11:41:31.457339 RX Vref 0 -> 0, step: 1
6400 11:41:31.457750
6401 11:41:31.458137 RX Delay -410 -> 252, step: 16
6402 11:41:31.463718 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6403 11:41:31.467209 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6404 11:41:31.470391 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6405 11:41:31.477311 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6406 11:41:31.480156 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6407 11:41:31.484038 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6408 11:41:31.487027 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6409 11:41:31.493553 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6410 11:41:31.496897 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6411 11:41:31.500237 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6412 11:41:31.503523 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6413 11:41:31.509906 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6414 11:41:31.513538 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6415 11:41:31.516711 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6416 11:41:31.519965 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6417 11:41:31.526501 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6418 11:41:31.526926 ==
6419 11:41:31.530123 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 11:41:31.533072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:41:31.533501 ==
6422 11:41:31.533844 DQS Delay:
6423 11:41:31.536455 DQS0 = 43, DQS1 = 59
6424 11:41:31.536927 DQM Delay:
6425 11:41:31.539810 DQM0 = 9, DQM1 = 11
6426 11:41:31.540235 DQ Delay:
6427 11:41:31.542756 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6428 11:41:31.545930 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6429 11:41:31.549355 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6430 11:41:31.552986 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6431 11:41:31.553413
6432 11:41:31.553755
6433 11:41:31.554070 ==
6434 11:41:31.556140 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 11:41:31.559552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 11:41:31.562927 ==
6437 11:41:31.563351
6438 11:41:31.563692
6439 11:41:31.564006 TX Vref Scan disable
6440 11:41:31.565999 == TX Byte 0 ==
6441 11:41:31.569555 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6442 11:41:31.572764 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6443 11:41:31.575730 == TX Byte 1 ==
6444 11:41:31.579084 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6445 11:41:31.582549 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6446 11:41:31.582980 ==
6447 11:41:31.585571 Dram Type= 6, Freq= 0, CH_0, rank 0
6448 11:41:31.592608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6449 11:41:31.593067 ==
6450 11:41:31.593442
6451 11:41:31.593760
6452 11:41:31.594073 TX Vref Scan disable
6453 11:41:31.596064 == TX Byte 0 ==
6454 11:41:31.599047 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6455 11:41:31.602027 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6456 11:41:31.605312 == TX Byte 1 ==
6457 11:41:31.609000 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6458 11:41:31.612060 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6459 11:41:31.612486
6460 11:41:31.615402 [DATLAT]
6461 11:41:31.615848 Freq=400, CH0 RK0
6462 11:41:31.616210
6463 11:41:31.618517 DATLAT Default: 0xf
6464 11:41:31.618997 0, 0xFFFF, sum = 0
6465 11:41:31.621727 1, 0xFFFF, sum = 0
6466 11:41:31.622270 2, 0xFFFF, sum = 0
6467 11:41:31.625077 3, 0xFFFF, sum = 0
6468 11:41:31.625594 4, 0xFFFF, sum = 0
6469 11:41:31.628571 5, 0xFFFF, sum = 0
6470 11:41:31.628979 6, 0xFFFF, sum = 0
6471 11:41:31.632224 7, 0xFFFF, sum = 0
6472 11:41:31.635353 8, 0xFFFF, sum = 0
6473 11:41:31.635928 9, 0xFFFF, sum = 0
6474 11:41:31.638796 10, 0xFFFF, sum = 0
6475 11:41:31.639259 11, 0xFFFF, sum = 0
6476 11:41:31.641749 12, 0xFFFF, sum = 0
6477 11:41:31.642180 13, 0x0, sum = 1
6478 11:41:31.645210 14, 0x0, sum = 2
6479 11:41:31.645926 15, 0x0, sum = 3
6480 11:41:31.648390 16, 0x0, sum = 4
6481 11:41:31.648954 best_step = 14
6482 11:41:31.649455
6483 11:41:31.649934 ==
6484 11:41:31.651573 Dram Type= 6, Freq= 0, CH_0, rank 0
6485 11:41:31.654796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 11:41:31.655227 ==
6487 11:41:31.658107 RX Vref Scan: 1
6488 11:41:31.658660
6489 11:41:31.661745 RX Vref 0 -> 0, step: 1
6490 11:41:31.662202
6491 11:41:31.665271 RX Delay -359 -> 252, step: 8
6492 11:41:31.665688
6493 11:41:31.667839 Set Vref, RX VrefLevel [Byte0]: 59
6494 11:41:31.671003 [Byte1]: 56
6495 11:41:31.671418
6496 11:41:31.674802 Final RX Vref Byte 0 = 59 to rank0
6497 11:41:31.678322 Final RX Vref Byte 1 = 56 to rank0
6498 11:41:31.680916 Final RX Vref Byte 0 = 59 to rank1
6499 11:41:31.684073 Final RX Vref Byte 1 = 56 to rank1==
6500 11:41:31.687754 Dram Type= 6, Freq= 0, CH_0, rank 0
6501 11:41:31.690842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 11:41:31.694402 ==
6503 11:41:31.694884 DQS Delay:
6504 11:41:31.695438 DQS0 = 48, DQS1 = 60
6505 11:41:31.697441 DQM Delay:
6506 11:41:31.697898 DQM0 = 12, DQM1 = 11
6507 11:41:31.700759 DQ Delay:
6508 11:41:31.701184 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6509 11:41:31.703731 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6510 11:41:31.707666 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6511 11:41:31.710413 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6512 11:41:31.710857
6513 11:41:31.714123
6514 11:41:31.720434 [DQSOSCAuto] RK0, (LSB)MR18= 0xb77c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6515 11:41:31.723955 CH0 RK0: MR19=C0C, MR18=B77C
6516 11:41:31.730264 CH0_RK0: MR19=0xC0C, MR18=0xB77C, DQSOSC=387, MR23=63, INC=394, DEC=262
6517 11:41:31.730842 ==
6518 11:41:31.733592 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 11:41:31.736783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 11:41:31.737446 ==
6521 11:41:31.740033 [Gating] SW mode calibration
6522 11:41:31.746695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6523 11:41:31.753220 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6524 11:41:31.756302 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6525 11:41:31.760091 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6526 11:41:31.766534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 11:41:31.769963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6528 11:41:31.772886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 11:41:31.779425 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 11:41:31.782696 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 11:41:31.786188 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6532 11:41:31.792880 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6533 11:41:31.796124 Total UI for P1: 0, mck2ui 16
6534 11:41:31.799619 best dqsien dly found for B0: ( 0, 14, 24)
6535 11:41:31.800045 Total UI for P1: 0, mck2ui 16
6536 11:41:31.806335 best dqsien dly found for B1: ( 0, 14, 24)
6537 11:41:31.809460 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6538 11:41:31.812322 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6539 11:41:31.812800
6540 11:41:31.815870 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6541 11:41:31.819076 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6542 11:41:31.822348 [Gating] SW calibration Done
6543 11:41:31.822773 ==
6544 11:41:31.825593 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 11:41:31.829155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 11:41:31.829621 ==
6547 11:41:31.832509 RX Vref Scan: 0
6548 11:41:31.832942
6549 11:41:31.835625 RX Vref 0 -> 0, step: 1
6550 11:41:31.836051
6551 11:41:31.836392 RX Delay -410 -> 252, step: 16
6552 11:41:31.842760 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6553 11:41:31.845527 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6554 11:41:31.848626 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6555 11:41:31.851992 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6556 11:41:31.858376 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6557 11:41:31.861988 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6558 11:41:31.865391 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6559 11:41:31.868821 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6560 11:41:31.875312 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6561 11:41:31.878636 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6562 11:41:31.882212 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6563 11:41:31.888623 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6564 11:41:31.891805 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6565 11:41:31.894989 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6566 11:41:31.898553 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6567 11:41:31.905261 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6568 11:41:31.905689 ==
6569 11:41:31.907989 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 11:41:31.911418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 11:41:31.911969 ==
6572 11:41:31.912458 DQS Delay:
6573 11:41:31.914921 DQS0 = 43, DQS1 = 59
6574 11:41:31.915437 DQM Delay:
6575 11:41:31.918151 DQM0 = 10, DQM1 = 15
6576 11:41:31.918518 DQ Delay:
6577 11:41:31.921405 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6578 11:41:31.925321 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6579 11:41:31.928048 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6580 11:41:31.931438 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6581 11:41:31.931998
6582 11:41:31.932367
6583 11:41:31.932821 ==
6584 11:41:31.934647 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 11:41:31.938127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 11:41:31.938585 ==
6587 11:41:31.938931
6588 11:41:31.941384
6589 11:41:31.941812 TX Vref Scan disable
6590 11:41:31.944456 == TX Byte 0 ==
6591 11:41:31.947656 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6592 11:41:31.951049 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6593 11:41:31.954474 == TX Byte 1 ==
6594 11:41:31.957553 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6595 11:41:31.960727 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6596 11:41:31.961212 ==
6597 11:41:31.964080 Dram Type= 6, Freq= 0, CH_0, rank 1
6598 11:41:31.967242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 11:41:31.970662 ==
6600 11:41:31.971073
6601 11:41:31.971472
6602 11:41:31.971809 TX Vref Scan disable
6603 11:41:31.974088 == TX Byte 0 ==
6604 11:41:31.977449 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6605 11:41:31.980822 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6606 11:41:31.984358 == TX Byte 1 ==
6607 11:41:31.987638 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6608 11:41:31.990432 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6609 11:41:31.990892
6610 11:41:31.994158 [DATLAT]
6611 11:41:31.994777 Freq=400, CH0 RK1
6612 11:41:31.995341
6613 11:41:31.997041 DATLAT Default: 0xe
6614 11:41:31.997459 0, 0xFFFF, sum = 0
6615 11:41:32.000146 1, 0xFFFF, sum = 0
6616 11:41:32.000787 2, 0xFFFF, sum = 0
6617 11:41:32.004022 3, 0xFFFF, sum = 0
6618 11:41:32.004450 4, 0xFFFF, sum = 0
6619 11:41:32.007429 5, 0xFFFF, sum = 0
6620 11:41:32.007859 6, 0xFFFF, sum = 0
6621 11:41:32.010114 7, 0xFFFF, sum = 0
6622 11:41:32.010707 8, 0xFFFF, sum = 0
6623 11:41:32.013272 9, 0xFFFF, sum = 0
6624 11:41:32.013356 10, 0xFFFF, sum = 0
6625 11:41:32.016552 11, 0xFFFF, sum = 0
6626 11:41:32.019814 12, 0xFFFF, sum = 0
6627 11:41:32.019897 13, 0x0, sum = 1
6628 11:41:32.019962 14, 0x0, sum = 2
6629 11:41:32.023000 15, 0x0, sum = 3
6630 11:41:32.023083 16, 0x0, sum = 4
6631 11:41:32.026209 best_step = 14
6632 11:41:32.026296
6633 11:41:32.026365 ==
6634 11:41:32.029605 Dram Type= 6, Freq= 0, CH_0, rank 1
6635 11:41:32.033124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 11:41:32.033219 ==
6637 11:41:32.036128 RX Vref Scan: 0
6638 11:41:32.036230
6639 11:41:32.036311 RX Vref 0 -> 0, step: 1
6640 11:41:32.036387
6641 11:41:32.039401 RX Delay -359 -> 252, step: 8
6642 11:41:32.047865 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6643 11:41:32.051612 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6644 11:41:32.054795 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6645 11:41:32.061111 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6646 11:41:32.064792 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6647 11:41:32.067576 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6648 11:41:32.071152 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6649 11:41:32.078036 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6650 11:41:32.081019 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6651 11:41:32.084684 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6652 11:41:32.088233 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6653 11:41:32.094570 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6654 11:41:32.098071 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6655 11:41:32.101131 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6656 11:41:32.104018 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6657 11:41:32.110912 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6658 11:41:32.111334 ==
6659 11:41:32.113957 Dram Type= 6, Freq= 0, CH_0, rank 1
6660 11:41:32.117304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 11:41:32.117726 ==
6662 11:41:32.118066 DQS Delay:
6663 11:41:32.120476 DQS0 = 44, DQS1 = 56
6664 11:41:32.120934 DQM Delay:
6665 11:41:32.124106 DQM0 = 7, DQM1 = 11
6666 11:41:32.124580 DQ Delay:
6667 11:41:32.127220 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6668 11:41:32.130447 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6669 11:41:32.134021 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6670 11:41:32.137365 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6671 11:41:32.137788
6672 11:41:32.138191
6673 11:41:32.143804 [DQSOSCAuto] RK1, (LSB)MR18= 0xb13d, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6674 11:41:32.147714 CH0 RK1: MR19=C0C, MR18=B13D
6675 11:41:32.153931 CH0_RK1: MR19=0xC0C, MR18=0xB13D, DQSOSC=387, MR23=63, INC=394, DEC=262
6676 11:41:32.157326 [RxdqsGatingPostProcess] freq 400
6677 11:41:32.163722 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6678 11:41:32.166909 best DQS0 dly(2T, 0.5T) = (0, 10)
6679 11:41:32.170546 best DQS1 dly(2T, 0.5T) = (0, 10)
6680 11:41:32.173486 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6681 11:41:32.177009 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6682 11:41:32.177435 best DQS0 dly(2T, 0.5T) = (0, 10)
6683 11:41:32.180639 best DQS1 dly(2T, 0.5T) = (0, 10)
6684 11:41:32.183383 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6685 11:41:32.186857 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6686 11:41:32.190286 Pre-setting of DQS Precalculation
6687 11:41:32.196617 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6688 11:41:32.197048 ==
6689 11:41:32.200090 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 11:41:32.203293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 11:41:32.203718 ==
6692 11:41:32.209853 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6693 11:41:32.216740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6694 11:41:32.219609 [CA 0] Center 36 (8~64) winsize 57
6695 11:41:32.223006 [CA 1] Center 36 (8~64) winsize 57
6696 11:41:32.223522 [CA 2] Center 36 (8~64) winsize 57
6697 11:41:32.226491 [CA 3] Center 36 (8~64) winsize 57
6698 11:41:32.229721 [CA 4] Center 36 (8~64) winsize 57
6699 11:41:32.232972 [CA 5] Center 36 (8~64) winsize 57
6700 11:41:32.233396
6701 11:41:32.236080 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6702 11:41:32.240087
6703 11:41:32.242657 [CATrainingPosCal] consider 1 rank data
6704 11:41:32.243086 u2DelayCellTimex100 = 270/100 ps
6705 11:41:32.249351 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 11:41:32.252567 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 11:41:32.256387 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 11:41:32.259608 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 11:41:32.262583 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 11:41:32.266348 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 11:41:32.266926
6712 11:41:32.269166 CA PerBit enable=1, Macro0, CA PI delay=36
6713 11:41:32.269671
6714 11:41:32.272627 [CBTSetCACLKResult] CA Dly = 36
6715 11:41:32.275878 CS Dly: 1 (0~32)
6716 11:41:32.276360 ==
6717 11:41:32.279115 Dram Type= 6, Freq= 0, CH_1, rank 1
6718 11:41:32.282420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 11:41:32.282843 ==
6720 11:41:32.289181 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6721 11:41:32.292383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6722 11:41:32.296020 [CA 0] Center 36 (8~64) winsize 57
6723 11:41:32.299316 [CA 1] Center 36 (8~64) winsize 57
6724 11:41:32.302230 [CA 2] Center 36 (8~64) winsize 57
6725 11:41:32.305621 [CA 3] Center 36 (8~64) winsize 57
6726 11:41:32.309038 [CA 4] Center 36 (8~64) winsize 57
6727 11:41:32.312382 [CA 5] Center 36 (8~64) winsize 57
6728 11:41:32.312871
6729 11:41:32.315245 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6730 11:41:32.315670
6731 11:41:32.318889 [CATrainingPosCal] consider 2 rank data
6732 11:41:32.322177 u2DelayCellTimex100 = 270/100 ps
6733 11:41:32.325532 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 11:41:32.328928 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 11:41:32.335173 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 11:41:32.338334 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 11:41:32.341897 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 11:41:32.344654 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6739 11:41:32.344736
6740 11:41:32.348099 CA PerBit enable=1, Macro0, CA PI delay=36
6741 11:41:32.348182
6742 11:41:32.351441 [CBTSetCACLKResult] CA Dly = 36
6743 11:41:32.351523 CS Dly: 1 (0~32)
6744 11:41:32.354901
6745 11:41:32.358149 ----->DramcWriteLeveling(PI) begin...
6746 11:41:32.358233 ==
6747 11:41:32.361299 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 11:41:32.364979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 11:41:32.365064 ==
6750 11:41:32.367853 Write leveling (Byte 0): 40 => 8
6751 11:41:32.371120 Write leveling (Byte 1): 40 => 8
6752 11:41:32.374912 DramcWriteLeveling(PI) end<-----
6753 11:41:32.374994
6754 11:41:32.375058 ==
6755 11:41:32.377521 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 11:41:32.381028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 11:41:32.381111 ==
6758 11:41:32.384341 [Gating] SW mode calibration
6759 11:41:32.390689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6760 11:41:32.397464 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6761 11:41:32.400777 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6762 11:41:32.404154 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6763 11:41:32.410672 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 11:41:32.413951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6765 11:41:32.417883 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 11:41:32.424430 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 11:41:32.427635 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6768 11:41:32.430613 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6769 11:41:32.437047 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6770 11:41:32.437133 Total UI for P1: 0, mck2ui 16
6771 11:41:32.444022 best dqsien dly found for B0: ( 0, 14, 24)
6772 11:41:32.444105 Total UI for P1: 0, mck2ui 16
6773 11:41:32.450663 best dqsien dly found for B1: ( 0, 14, 24)
6774 11:41:32.453810 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6775 11:41:32.457259 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6776 11:41:32.457341
6777 11:41:32.460118 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6778 11:41:32.463617 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6779 11:41:32.467078 [Gating] SW calibration Done
6780 11:41:32.467160 ==
6781 11:41:32.470421 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 11:41:32.473291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 11:41:32.473374 ==
6784 11:41:32.476684 RX Vref Scan: 0
6785 11:41:32.476766
6786 11:41:32.476832 RX Vref 0 -> 0, step: 1
6787 11:41:32.480385
6788 11:41:32.480467 RX Delay -410 -> 252, step: 16
6789 11:41:32.486755 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6790 11:41:32.489814 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6791 11:41:32.493108 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6792 11:41:32.496488 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6793 11:41:32.502936 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6794 11:41:32.506230 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6795 11:41:32.509828 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6796 11:41:32.513067 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6797 11:41:32.519638 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6798 11:41:32.522931 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6799 11:41:32.526176 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6800 11:41:32.532927 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6801 11:41:32.536195 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6802 11:41:32.539112 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6803 11:41:32.542930 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6804 11:41:32.549744 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6805 11:41:32.549826 ==
6806 11:41:32.552644 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 11:41:32.555638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:41:32.555720 ==
6809 11:41:32.555785 DQS Delay:
6810 11:41:32.559502 DQS0 = 43, DQS1 = 51
6811 11:41:32.559583 DQM Delay:
6812 11:41:32.562023 DQM0 = 12, DQM1 = 14
6813 11:41:32.562129 DQ Delay:
6814 11:41:32.565562 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6815 11:41:32.568691 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6816 11:41:32.572221 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6817 11:41:32.575353 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6818 11:41:32.575436
6819 11:41:32.575500
6820 11:41:32.575560 ==
6821 11:41:32.578688 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 11:41:32.581895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 11:41:32.581977 ==
6824 11:41:32.582043
6825 11:41:32.585604
6826 11:41:32.585689 TX Vref Scan disable
6827 11:41:32.588557 == TX Byte 0 ==
6828 11:41:32.591890 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6829 11:41:32.595074 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6830 11:41:32.598473 == TX Byte 1 ==
6831 11:41:32.602085 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6832 11:41:32.604824 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6833 11:41:32.604906 ==
6834 11:41:32.608463 Dram Type= 6, Freq= 0, CH_1, rank 0
6835 11:41:32.611411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6836 11:41:32.614803 ==
6837 11:41:32.614884
6838 11:41:32.614950
6839 11:41:32.615010 TX Vref Scan disable
6840 11:41:32.618425 == TX Byte 0 ==
6841 11:41:32.621345 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6842 11:41:32.624648 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6843 11:41:32.627898 == TX Byte 1 ==
6844 11:41:32.631111 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6845 11:41:32.634980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6846 11:41:32.635063
6847 11:41:32.637883 [DATLAT]
6848 11:41:32.637964 Freq=400, CH1 RK0
6849 11:41:32.638030
6850 11:41:32.641249 DATLAT Default: 0xf
6851 11:41:32.641331 0, 0xFFFF, sum = 0
6852 11:41:32.644317 1, 0xFFFF, sum = 0
6853 11:41:32.644419 2, 0xFFFF, sum = 0
6854 11:41:32.647611 3, 0xFFFF, sum = 0
6855 11:41:32.647695 4, 0xFFFF, sum = 0
6856 11:41:32.650986 5, 0xFFFF, sum = 0
6857 11:41:32.651070 6, 0xFFFF, sum = 0
6858 11:41:32.654555 7, 0xFFFF, sum = 0
6859 11:41:32.654638 8, 0xFFFF, sum = 0
6860 11:41:32.657798 9, 0xFFFF, sum = 0
6861 11:41:32.661314 10, 0xFFFF, sum = 0
6862 11:41:32.661397 11, 0xFFFF, sum = 0
6863 11:41:32.664400 12, 0xFFFF, sum = 0
6864 11:41:32.664484 13, 0x0, sum = 1
6865 11:41:32.667584 14, 0x0, sum = 2
6866 11:41:32.667667 15, 0x0, sum = 3
6867 11:41:32.670435 16, 0x0, sum = 4
6868 11:41:32.670520 best_step = 14
6869 11:41:32.670585
6870 11:41:32.670646 ==
6871 11:41:32.674485 Dram Type= 6, Freq= 0, CH_1, rank 0
6872 11:41:32.677625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 11:41:32.677708 ==
6874 11:41:32.680426 RX Vref Scan: 1
6875 11:41:32.680508
6876 11:41:32.684155 RX Vref 0 -> 0, step: 1
6877 11:41:32.684237
6878 11:41:32.684302 RX Delay -343 -> 252, step: 8
6879 11:41:32.684363
6880 11:41:32.687224 Set Vref, RX VrefLevel [Byte0]: 48
6881 11:41:32.690583 [Byte1]: 54
6882 11:41:32.696379
6883 11:41:32.696466 Final RX Vref Byte 0 = 48 to rank0
6884 11:41:32.699568 Final RX Vref Byte 1 = 54 to rank0
6885 11:41:32.703126 Final RX Vref Byte 0 = 48 to rank1
6886 11:41:32.706254 Final RX Vref Byte 1 = 54 to rank1==
6887 11:41:32.709469 Dram Type= 6, Freq= 0, CH_1, rank 0
6888 11:41:32.716225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 11:41:32.716697 ==
6890 11:41:32.717042 DQS Delay:
6891 11:41:32.719591 DQS0 = 44, DQS1 = 56
6892 11:41:32.720012 DQM Delay:
6893 11:41:32.720350 DQM0 = 9, DQM1 = 13
6894 11:41:32.723062 DQ Delay:
6895 11:41:32.726149 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6896 11:41:32.726575 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6897 11:41:32.729487 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6898 11:41:32.732703 DQ12 =24, DQ13 =16, DQ14 =20, DQ15 =24
6899 11:41:32.733131
6900 11:41:32.733472
6901 11:41:32.742804 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e64, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6902 11:41:32.745982 CH1 RK0: MR19=C0C, MR18=8E64
6903 11:41:32.752456 CH1_RK0: MR19=0xC0C, MR18=0x8E64, DQSOSC=392, MR23=63, INC=384, DEC=256
6904 11:41:32.752591 ==
6905 11:41:32.755527 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 11:41:32.759283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 11:41:32.759761 ==
6908 11:41:32.763355 [Gating] SW mode calibration
6909 11:41:32.768904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6910 11:41:32.775696 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6911 11:41:32.779393 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6912 11:41:32.782720 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6913 11:41:32.788648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 11:41:32.792013 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6915 11:41:32.795480 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 11:41:32.802027 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 11:41:32.805411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6918 11:41:32.808326 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6919 11:41:32.815125 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6920 11:41:32.816390 Total UI for P1: 0, mck2ui 16
6921 11:41:32.821856 best dqsien dly found for B0: ( 0, 14, 24)
6922 11:41:32.822375 Total UI for P1: 0, mck2ui 16
6923 11:41:32.828306 best dqsien dly found for B1: ( 0, 14, 24)
6924 11:41:32.831605 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6925 11:41:32.834714 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6926 11:41:32.835185
6927 11:41:32.838482 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6928 11:41:32.841183 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6929 11:41:32.844486 [Gating] SW calibration Done
6930 11:41:32.844953 ==
6931 11:41:32.848426 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 11:41:32.851348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 11:41:32.851766 ==
6934 11:41:32.854963 RX Vref Scan: 0
6935 11:41:32.855382
6936 11:41:32.855716 RX Vref 0 -> 0, step: 1
6937 11:41:32.856027
6938 11:41:32.857725 RX Delay -410 -> 252, step: 16
6939 11:41:32.864903 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6940 11:41:32.867998 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6941 11:41:32.871021 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6942 11:41:32.874673 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6943 11:41:32.880913 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6944 11:41:32.884388 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6945 11:41:32.887619 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6946 11:41:32.891061 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6947 11:41:32.897424 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6948 11:41:32.901037 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6949 11:41:32.904563 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6950 11:41:32.911143 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6951 11:41:32.914519 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6952 11:41:32.917554 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6953 11:41:32.920569 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6954 11:41:32.927366 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6955 11:41:32.927888 ==
6956 11:41:32.930419 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 11:41:32.933683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 11:41:32.934099 ==
6959 11:41:32.934434 DQS Delay:
6960 11:41:32.937067 DQS0 = 51, DQS1 = 51
6961 11:41:32.937484 DQM Delay:
6962 11:41:32.940301 DQM0 = 19, DQM1 = 14
6963 11:41:32.940924 DQ Delay:
6964 11:41:32.943590 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6965 11:41:32.946780 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6966 11:41:32.950796 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6967 11:41:32.954096 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6968 11:41:32.954518
6969 11:41:32.954848
6970 11:41:32.955196 ==
6971 11:41:32.957038 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 11:41:32.960553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 11:41:32.961039 ==
6974 11:41:32.961525
6975 11:41:32.963747
6976 11:41:32.964289 TX Vref Scan disable
6977 11:41:32.966587 == TX Byte 0 ==
6978 11:41:32.970272 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6979 11:41:32.973780 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6980 11:41:32.977101 == TX Byte 1 ==
6981 11:41:32.979945 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6982 11:41:32.983562 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6983 11:41:32.983983 ==
6984 11:41:32.987073 Dram Type= 6, Freq= 0, CH_1, rank 1
6985 11:41:32.990189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6986 11:41:32.993005 ==
6987 11:41:32.993426
6988 11:41:32.993756
6989 11:41:32.994066 TX Vref Scan disable
6990 11:41:32.996446 == TX Byte 0 ==
6991 11:41:32.999726 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6992 11:41:33.002914 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6993 11:41:33.006297 == TX Byte 1 ==
6994 11:41:33.009751 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6995 11:41:33.012902 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6996 11:41:33.013421
6997 11:41:33.016300 [DATLAT]
6998 11:41:33.016760 Freq=400, CH1 RK1
6999 11:41:33.017082
7000 11:41:33.019548 DATLAT Default: 0xe
7001 11:41:33.019968 0, 0xFFFF, sum = 0
7002 11:41:33.022765 1, 0xFFFF, sum = 0
7003 11:41:33.023252 2, 0xFFFF, sum = 0
7004 11:41:33.026193 3, 0xFFFF, sum = 0
7005 11:41:33.026620 4, 0xFFFF, sum = 0
7006 11:41:33.029411 5, 0xFFFF, sum = 0
7007 11:41:33.029842 6, 0xFFFF, sum = 0
7008 11:41:33.032662 7, 0xFFFF, sum = 0
7009 11:41:33.033089 8, 0xFFFF, sum = 0
7010 11:41:33.035685 9, 0xFFFF, sum = 0
7011 11:41:33.036270 10, 0xFFFF, sum = 0
7012 11:41:33.039205 11, 0xFFFF, sum = 0
7013 11:41:33.042481 12, 0xFFFF, sum = 0
7014 11:41:33.042991 13, 0x0, sum = 1
7015 11:41:33.043460 14, 0x0, sum = 2
7016 11:41:33.045552 15, 0x0, sum = 3
7017 11:41:33.046014 16, 0x0, sum = 4
7018 11:41:33.049253 best_step = 14
7019 11:41:33.049679
7020 11:41:33.050013 ==
7021 11:41:33.052267 Dram Type= 6, Freq= 0, CH_1, rank 1
7022 11:41:33.056272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7023 11:41:33.056733 ==
7024 11:41:33.059041 RX Vref Scan: 0
7025 11:41:33.059461
7026 11:41:33.059800 RX Vref 0 -> 0, step: 1
7027 11:41:33.062065
7028 11:41:33.062525 RX Delay -343 -> 252, step: 8
7029 11:41:33.070810 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7030 11:41:33.074125 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7031 11:41:33.077510 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7032 11:41:33.084255 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7033 11:41:33.087058 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7034 11:41:33.090692 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7035 11:41:33.093854 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7036 11:41:33.097418 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7037 11:41:33.103940 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7038 11:41:33.107035 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7039 11:41:33.110588 iDelay=225, Bit 10, Center -40 (-287 ~ 208) 496
7040 11:41:33.117042 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7041 11:41:33.120761 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7042 11:41:33.123830 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7043 11:41:33.126817 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7044 11:41:33.133201 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7045 11:41:33.133622 ==
7046 11:41:33.136979 Dram Type= 6, Freq= 0, CH_1, rank 1
7047 11:41:33.140107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7048 11:41:33.140566 ==
7049 11:41:33.140915 DQS Delay:
7050 11:41:33.143241 DQS0 = 48, DQS1 = 56
7051 11:41:33.143661 DQM Delay:
7052 11:41:33.146497 DQM0 = 13, DQM1 = 11
7053 11:41:33.146917 DQ Delay:
7054 11:41:33.149631 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7055 11:41:33.153118 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =8
7056 11:41:33.156674 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7057 11:41:33.159334 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7058 11:41:33.159833
7059 11:41:33.160177
7060 11:41:33.169302 [DQSOSCAuto] RK1, (LSB)MR18= 0x6452, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7061 11:41:33.169732 CH1 RK1: MR19=C0C, MR18=6452
7062 11:41:33.175884 CH1_RK1: MR19=0xC0C, MR18=0x6452, DQSOSC=397, MR23=63, INC=374, DEC=249
7063 11:41:33.179723 [RxdqsGatingPostProcess] freq 400
7064 11:41:33.185745 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7065 11:41:33.189804 best DQS0 dly(2T, 0.5T) = (0, 10)
7066 11:41:33.193071 best DQS1 dly(2T, 0.5T) = (0, 10)
7067 11:41:33.196330 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7068 11:41:33.199627 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7069 11:41:33.202258 best DQS0 dly(2T, 0.5T) = (0, 10)
7070 11:41:33.205607 best DQS1 dly(2T, 0.5T) = (0, 10)
7071 11:41:33.209061 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7072 11:41:33.209484 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7073 11:41:33.212425 Pre-setting of DQS Precalculation
7074 11:41:33.218713 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7075 11:41:33.225440 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7076 11:41:33.232123 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7077 11:41:33.232588
7078 11:41:33.232957
7079 11:41:33.235427 [Calibration Summary] 800 Mbps
7080 11:41:33.238861 CH 0, Rank 0
7081 11:41:33.239283 SW Impedance : PASS
7082 11:41:33.241744 DUTY Scan : NO K
7083 11:41:33.245020 ZQ Calibration : PASS
7084 11:41:33.245442 Jitter Meter : NO K
7085 11:41:33.248828 CBT Training : PASS
7086 11:41:33.251762 Write leveling : PASS
7087 11:41:33.252181 RX DQS gating : PASS
7088 11:41:33.254891 RX DQ/DQS(RDDQC) : PASS
7089 11:41:33.255313 TX DQ/DQS : PASS
7090 11:41:33.258489 RX DATLAT : PASS
7091 11:41:33.261704 RX DQ/DQS(Engine): PASS
7092 11:41:33.262126 TX OE : NO K
7093 11:41:33.264997 All Pass.
7094 11:41:33.265426
7095 11:41:33.265767 CH 0, Rank 1
7096 11:41:33.268297 SW Impedance : PASS
7097 11:41:33.268776 DUTY Scan : NO K
7098 11:41:33.271627 ZQ Calibration : PASS
7099 11:41:33.274902 Jitter Meter : NO K
7100 11:41:33.275325 CBT Training : PASS
7101 11:41:33.278228 Write leveling : NO K
7102 11:41:33.281803 RX DQS gating : PASS
7103 11:41:33.282226 RX DQ/DQS(RDDQC) : PASS
7104 11:41:33.284918 TX DQ/DQS : PASS
7105 11:41:33.287858 RX DATLAT : PASS
7106 11:41:33.288424 RX DQ/DQS(Engine): PASS
7107 11:41:33.291644 TX OE : NO K
7108 11:41:33.292067 All Pass.
7109 11:41:33.292407
7110 11:41:33.295106 CH 1, Rank 0
7111 11:41:33.295526 SW Impedance : PASS
7112 11:41:33.298334 DUTY Scan : NO K
7113 11:41:33.301609 ZQ Calibration : PASS
7114 11:41:33.302028 Jitter Meter : NO K
7115 11:41:33.304900 CBT Training : PASS
7116 11:41:33.307615 Write leveling : PASS
7117 11:41:33.308035 RX DQS gating : PASS
7118 11:41:33.310960 RX DQ/DQS(RDDQC) : PASS
7119 11:41:33.314222 TX DQ/DQS : PASS
7120 11:41:33.314637 RX DATLAT : PASS
7121 11:41:33.317588 RX DQ/DQS(Engine): PASS
7122 11:41:33.321036 TX OE : NO K
7123 11:41:33.321117 All Pass.
7124 11:41:33.321182
7125 11:41:33.321243 CH 1, Rank 1
7126 11:41:33.323796 SW Impedance : PASS
7127 11:41:33.327522 DUTY Scan : NO K
7128 11:41:33.327603 ZQ Calibration : PASS
7129 11:41:33.330952 Jitter Meter : NO K
7130 11:41:33.334016 CBT Training : PASS
7131 11:41:33.334098 Write leveling : NO K
7132 11:41:33.337163 RX DQS gating : PASS
7133 11:41:33.337246 RX DQ/DQS(RDDQC) : PASS
7134 11:41:33.340366 TX DQ/DQS : PASS
7135 11:41:33.343713 RX DATLAT : PASS
7136 11:41:33.343795 RX DQ/DQS(Engine): PASS
7137 11:41:33.347182 TX OE : NO K
7138 11:41:33.347265 All Pass.
7139 11:41:33.347331
7140 11:41:33.350543 DramC Write-DBI off
7141 11:41:33.353726 PER_BANK_REFRESH: Hybrid Mode
7142 11:41:33.353809 TX_TRACKING: ON
7143 11:41:33.363509 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7144 11:41:33.366852 [FAST_K] Save calibration result to emmc
7145 11:41:33.370160 dramc_set_vcore_voltage set vcore to 725000
7146 11:41:33.373268 Read voltage for 1600, 0
7147 11:41:33.373346 Vio18 = 0
7148 11:41:33.376617 Vcore = 725000
7149 11:41:33.376693 Vdram = 0
7150 11:41:33.376775 Vddq = 0
7151 11:41:33.376873 Vmddr = 0
7152 11:41:33.383042 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7153 11:41:33.389656 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7154 11:41:33.389736 MEM_TYPE=3, freq_sel=13
7155 11:41:33.392903 sv_algorithm_assistance_LP4_3733
7156 11:41:33.396603 ============ PULL DRAM RESETB DOWN ============
7157 11:41:33.403077 ========== PULL DRAM RESETB DOWN end =========
7158 11:41:33.406268 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7159 11:41:33.409573 ===================================
7160 11:41:33.413297 LPDDR4 DRAM CONFIGURATION
7161 11:41:33.416020 ===================================
7162 11:41:33.416101 EX_ROW_EN[0] = 0x0
7163 11:41:33.419737 EX_ROW_EN[1] = 0x0
7164 11:41:33.422580 LP4Y_EN = 0x0
7165 11:41:33.422661 WORK_FSP = 0x1
7166 11:41:33.426021 WL = 0x5
7167 11:41:33.426103 RL = 0x5
7168 11:41:33.429865 BL = 0x2
7169 11:41:33.429947 RPST = 0x0
7170 11:41:33.432801 RD_PRE = 0x0
7171 11:41:33.432883 WR_PRE = 0x1
7172 11:41:33.436039 WR_PST = 0x1
7173 11:41:33.436121 DBI_WR = 0x0
7174 11:41:33.439219 DBI_RD = 0x0
7175 11:41:33.439301 OTF = 0x1
7176 11:41:33.442452 ===================================
7177 11:41:33.445811 ===================================
7178 11:41:33.449208 ANA top config
7179 11:41:33.452201 ===================================
7180 11:41:33.452283 DLL_ASYNC_EN = 0
7181 11:41:33.455987 ALL_SLAVE_EN = 0
7182 11:41:33.459176 NEW_RANK_MODE = 1
7183 11:41:33.462194 DLL_IDLE_MODE = 1
7184 11:41:33.465496 LP45_APHY_COMB_EN = 1
7185 11:41:33.465609 TX_ODT_DIS = 0
7186 11:41:33.468641 NEW_8X_MODE = 1
7187 11:41:33.472135 ===================================
7188 11:41:33.475587 ===================================
7189 11:41:33.479063 data_rate = 3200
7190 11:41:33.482304 CKR = 1
7191 11:41:33.485426 DQ_P2S_RATIO = 8
7192 11:41:33.488679 ===================================
7193 11:41:33.491935 CA_P2S_RATIO = 8
7194 11:41:33.492017 DQ_CA_OPEN = 0
7195 11:41:33.495315 DQ_SEMI_OPEN = 0
7196 11:41:33.498484 CA_SEMI_OPEN = 0
7197 11:41:33.501817 CA_FULL_RATE = 0
7198 11:41:33.505354 DQ_CKDIV4_EN = 0
7199 11:41:33.508402 CA_CKDIV4_EN = 0
7200 11:41:33.508552 CA_PREDIV_EN = 0
7201 11:41:33.511826 PH8_DLY = 12
7202 11:41:33.515319 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7203 11:41:33.518538 DQ_AAMCK_DIV = 4
7204 11:41:33.521573 CA_AAMCK_DIV = 4
7205 11:41:33.525211 CA_ADMCK_DIV = 4
7206 11:41:33.525293 DQ_TRACK_CA_EN = 0
7207 11:41:33.528427 CA_PICK = 1600
7208 11:41:33.531820 CA_MCKIO = 1600
7209 11:41:33.534922 MCKIO_SEMI = 0
7210 11:41:33.538330 PLL_FREQ = 3068
7211 11:41:33.541317 DQ_UI_PI_RATIO = 32
7212 11:41:33.545472 CA_UI_PI_RATIO = 0
7213 11:41:33.548032 ===================================
7214 11:41:33.551293 ===================================
7215 11:41:33.554526 memory_type:LPDDR4
7216 11:41:33.554607 GP_NUM : 10
7217 11:41:33.557747 SRAM_EN : 1
7218 11:41:33.557829 MD32_EN : 0
7219 11:41:33.561010 ===================================
7220 11:41:33.564506 [ANA_INIT] >>>>>>>>>>>>>>
7221 11:41:33.568043 <<<<<< [CONFIGURE PHASE]: ANA_TX
7222 11:41:33.571173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7223 11:41:33.574455 ===================================
7224 11:41:33.577656 data_rate = 3200,PCW = 0X7600
7225 11:41:33.581032 ===================================
7226 11:41:33.584351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7227 11:41:33.590805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7228 11:41:33.594337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7229 11:41:33.600717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7230 11:41:33.604424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7231 11:41:33.607629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7232 11:41:33.607711 [ANA_INIT] flow start
7233 11:41:33.610557 [ANA_INIT] PLL >>>>>>>>
7234 11:41:33.614346 [ANA_INIT] PLL <<<<<<<<
7235 11:41:33.614428 [ANA_INIT] MIDPI >>>>>>>>
7236 11:41:33.617551 [ANA_INIT] MIDPI <<<<<<<<
7237 11:41:33.620787 [ANA_INIT] DLL >>>>>>>>
7238 11:41:33.620869 [ANA_INIT] DLL <<<<<<<<
7239 11:41:33.624319 [ANA_INIT] flow end
7240 11:41:33.627415 ============ LP4 DIFF to SE enter ============
7241 11:41:33.633590 ============ LP4 DIFF to SE exit ============
7242 11:41:33.633673 [ANA_INIT] <<<<<<<<<<<<<
7243 11:41:33.637269 [Flow] Enable top DCM control >>>>>
7244 11:41:33.640640 [Flow] Enable top DCM control <<<<<
7245 11:41:33.643504 Enable DLL master slave shuffle
7246 11:41:33.650088 ==============================================================
7247 11:41:33.650170 Gating Mode config
7248 11:41:33.656631 ==============================================================
7249 11:41:33.659765 Config description:
7250 11:41:33.669848 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7251 11:41:33.676306 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7252 11:41:33.679931 SELPH_MODE 0: By rank 1: By Phase
7253 11:41:33.686419 ==============================================================
7254 11:41:33.689549 GAT_TRACK_EN = 1
7255 11:41:33.692927 RX_GATING_MODE = 2
7256 11:41:33.693009 RX_GATING_TRACK_MODE = 2
7257 11:41:33.696348 SELPH_MODE = 1
7258 11:41:33.699492 PICG_EARLY_EN = 1
7259 11:41:33.702912 VALID_LAT_VALUE = 1
7260 11:41:33.709357 ==============================================================
7261 11:41:33.712712 Enter into Gating configuration >>>>
7262 11:41:33.715786 Exit from Gating configuration <<<<
7263 11:41:33.719081 Enter into DVFS_PRE_config >>>>>
7264 11:41:33.729564 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7265 11:41:33.732322 Exit from DVFS_PRE_config <<<<<
7266 11:41:33.735637 Enter into PICG configuration >>>>
7267 11:41:33.739022 Exit from PICG configuration <<<<
7268 11:41:33.742165 [RX_INPUT] configuration >>>>>
7269 11:41:33.745946 [RX_INPUT] configuration <<<<<
7270 11:41:33.749249 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7271 11:41:33.755392 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7272 11:41:33.762256 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7273 11:41:33.768508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7274 11:41:33.775349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7275 11:41:33.778686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7276 11:41:33.785592 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7277 11:41:33.788315 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7278 11:41:33.792172 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7279 11:41:33.795410 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7280 11:41:33.801803 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7281 11:41:33.804916 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7282 11:41:33.808222 ===================================
7283 11:41:33.811486 LPDDR4 DRAM CONFIGURATION
7284 11:41:33.814902 ===================================
7285 11:41:33.814984 EX_ROW_EN[0] = 0x0
7286 11:41:33.818222 EX_ROW_EN[1] = 0x0
7287 11:41:33.818329 LP4Y_EN = 0x0
7288 11:41:33.821503 WORK_FSP = 0x1
7289 11:41:33.821601 WL = 0x5
7290 11:41:33.824741 RL = 0x5
7291 11:41:33.828163 BL = 0x2
7292 11:41:33.828257 RPST = 0x0
7293 11:41:33.831391 RD_PRE = 0x0
7294 11:41:33.831472 WR_PRE = 0x1
7295 11:41:33.834736 WR_PST = 0x1
7296 11:41:33.834817 DBI_WR = 0x0
7297 11:41:33.837846 DBI_RD = 0x0
7298 11:41:33.837927 OTF = 0x1
7299 11:41:33.841356 ===================================
7300 11:41:33.844479 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7301 11:41:33.851286 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7302 11:41:33.854310 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7303 11:41:33.857704 ===================================
7304 11:41:33.860994 LPDDR4 DRAM CONFIGURATION
7305 11:41:33.864442 ===================================
7306 11:41:33.864532 EX_ROW_EN[0] = 0x10
7307 11:41:33.867752 EX_ROW_EN[1] = 0x0
7308 11:41:33.867835 LP4Y_EN = 0x0
7309 11:41:33.870953 WORK_FSP = 0x1
7310 11:41:33.874166 WL = 0x5
7311 11:41:33.874275 RL = 0x5
7312 11:41:33.877623 BL = 0x2
7313 11:41:33.877785 RPST = 0x0
7314 11:41:33.881024 RD_PRE = 0x0
7315 11:41:33.881125 WR_PRE = 0x1
7316 11:41:33.884301 WR_PST = 0x1
7317 11:41:33.884401 DBI_WR = 0x0
7318 11:41:33.887153 DBI_RD = 0x0
7319 11:41:33.887268 OTF = 0x1
7320 11:41:33.890523 ===================================
7321 11:41:33.897483 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7322 11:41:33.897604 ==
7323 11:41:33.900943 Dram Type= 6, Freq= 0, CH_0, rank 0
7324 11:41:33.903884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7325 11:41:33.906826 ==
7326 11:41:33.906930 [Duty_Offset_Calibration]
7327 11:41:33.910895 B0:1 B1:-1 CA:0
7328 11:41:33.910974
7329 11:41:33.913605 [DutyScan_Calibration_Flow] k_type=0
7330 11:41:33.922932
7331 11:41:33.923038 ==CLK 0==
7332 11:41:33.926285 Final CLK duty delay cell = 0
7333 11:41:33.928949 [0] MAX Duty = 5125%(X100), DQS PI = 20
7334 11:41:33.932394 [0] MIN Duty = 4907%(X100), DQS PI = 10
7335 11:41:33.935794 [0] AVG Duty = 5016%(X100)
7336 11:41:33.935897
7337 11:41:33.939183 CH0 CLK Duty spec in!! Max-Min= 218%
7338 11:41:33.942584 [DutyScan_Calibration_Flow] ====Done====
7339 11:41:33.942687
7340 11:41:33.945980 [DutyScan_Calibration_Flow] k_type=1
7341 11:41:33.962021
7342 11:41:33.962109 ==DQS 0 ==
7343 11:41:33.964969 Final DQS duty delay cell = -4
7344 11:41:33.968301 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7345 11:41:33.971426 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7346 11:41:33.975076 [-4] AVG Duty = 4922%(X100)
7347 11:41:33.975176
7348 11:41:33.975271 ==DQS 1 ==
7349 11:41:33.978674 Final DQS duty delay cell = 0
7350 11:41:33.981859 [0] MAX Duty = 5187%(X100), DQS PI = 4
7351 11:41:33.984707 [0] MIN Duty = 5031%(X100), DQS PI = 18
7352 11:41:33.988036 [0] AVG Duty = 5109%(X100)
7353 11:41:33.988135
7354 11:41:33.991406 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7355 11:41:33.991508
7356 11:41:33.995320 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7357 11:41:33.998393 [DutyScan_Calibration_Flow] ====Done====
7358 11:41:33.998498
7359 11:41:34.001444 [DutyScan_Calibration_Flow] k_type=3
7360 11:41:34.019100
7361 11:41:34.019214 ==DQM 0 ==
7362 11:41:34.022448 Final DQM duty delay cell = 0
7363 11:41:34.026011 [0] MAX Duty = 5124%(X100), DQS PI = 20
7364 11:41:34.029126 [0] MIN Duty = 4907%(X100), DQS PI = 8
7365 11:41:34.032576 [0] AVG Duty = 5015%(X100)
7366 11:41:34.032665
7367 11:41:34.032753 ==DQM 1 ==
7368 11:41:34.035980 Final DQM duty delay cell = 0
7369 11:41:34.039061 [0] MAX Duty = 5031%(X100), DQS PI = 52
7370 11:41:34.042544 [0] MIN Duty = 4813%(X100), DQS PI = 20
7371 11:41:34.045927 [0] AVG Duty = 4922%(X100)
7372 11:41:34.046030
7373 11:41:34.049338 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7374 11:41:34.049440
7375 11:41:34.052172 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7376 11:41:34.055546 [DutyScan_Calibration_Flow] ====Done====
7377 11:41:34.055625
7378 11:41:34.059035 [DutyScan_Calibration_Flow] k_type=2
7379 11:41:34.075524
7380 11:41:34.075641 ==DQ 0 ==
7381 11:41:34.078765 Final DQ duty delay cell = -4
7382 11:41:34.082068 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7383 11:41:34.085780 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7384 11:41:34.089118 [-4] AVG Duty = 4953%(X100)
7385 11:41:34.089219
7386 11:41:34.089316 ==DQ 1 ==
7387 11:41:34.092606 Final DQ duty delay cell = 0
7388 11:41:34.095328 [0] MAX Duty = 5125%(X100), DQS PI = 2
7389 11:41:34.099018 [0] MIN Duty = 4969%(X100), DQS PI = 38
7390 11:41:34.102275 [0] AVG Duty = 5047%(X100)
7391 11:41:34.102385
7392 11:41:34.105477 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7393 11:41:34.105581
7394 11:41:34.108475 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7395 11:41:34.111858 [DutyScan_Calibration_Flow] ====Done====
7396 11:41:34.111959 ==
7397 11:41:34.115408 Dram Type= 6, Freq= 0, CH_1, rank 0
7398 11:41:34.118643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7399 11:41:34.118759 ==
7400 11:41:34.121797 [Duty_Offset_Calibration]
7401 11:41:34.121898 B0:-1 B1:1 CA:2
7402 11:41:34.122004
7403 11:41:34.125049 [DutyScan_Calibration_Flow] k_type=0
7404 11:41:34.136216
7405 11:41:34.136326 ==CLK 0==
7406 11:41:34.139515 Final CLK duty delay cell = 0
7407 11:41:34.142933 [0] MAX Duty = 5187%(X100), DQS PI = 22
7408 11:41:34.145928 [0] MIN Duty = 5062%(X100), DQS PI = 0
7409 11:41:34.149083 [0] AVG Duty = 5124%(X100)
7410 11:41:34.149197
7411 11:41:34.152746 CH1 CLK Duty spec in!! Max-Min= 125%
7412 11:41:34.155792 [DutyScan_Calibration_Flow] ====Done====
7413 11:41:34.155911
7414 11:41:34.158982 [DutyScan_Calibration_Flow] k_type=1
7415 11:41:34.175898
7416 11:41:34.175997 ==DQS 0 ==
7417 11:41:34.178998 Final DQS duty delay cell = 0
7418 11:41:34.182702 [0] MAX Duty = 5156%(X100), DQS PI = 20
7419 11:41:34.185706 [0] MIN Duty = 4907%(X100), DQS PI = 42
7420 11:41:34.188857 [0] AVG Duty = 5031%(X100)
7421 11:41:34.188930
7422 11:41:34.188994 ==DQS 1 ==
7423 11:41:34.192099 Final DQS duty delay cell = 0
7424 11:41:34.196001 [0] MAX Duty = 5093%(X100), DQS PI = 42
7425 11:41:34.198706 [0] MIN Duty = 5000%(X100), DQS PI = 22
7426 11:41:34.202496 [0] AVG Duty = 5046%(X100)
7427 11:41:34.202570
7428 11:41:34.205231 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7429 11:41:34.205327
7430 11:41:34.208630 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7431 11:41:34.212051 [DutyScan_Calibration_Flow] ====Done====
7432 11:41:34.212142
7433 11:41:34.215667 [DutyScan_Calibration_Flow] k_type=3
7434 11:41:34.231811
7435 11:41:34.231888 ==DQM 0 ==
7436 11:41:34.235097 Final DQM duty delay cell = -4
7437 11:41:34.238611 [-4] MAX Duty = 5062%(X100), DQS PI = 6
7438 11:41:34.242001 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7439 11:41:34.245366 [-4] AVG Duty = 4937%(X100)
7440 11:41:34.245437
7441 11:41:34.245497 ==DQM 1 ==
7442 11:41:34.248704 Final DQM duty delay cell = 0
7443 11:41:34.251392 [0] MAX Duty = 5187%(X100), DQS PI = 34
7444 11:41:34.254878 [0] MIN Duty = 4969%(X100), DQS PI = 2
7445 11:41:34.258156 [0] AVG Duty = 5078%(X100)
7446 11:41:34.258266
7447 11:41:34.261598 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7448 11:41:34.261701
7449 11:41:34.264751 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7450 11:41:34.268043 [DutyScan_Calibration_Flow] ====Done====
7451 11:41:34.268151
7452 11:41:34.271719 [DutyScan_Calibration_Flow] k_type=2
7453 11:41:34.289341
7454 11:41:34.289425 ==DQ 0 ==
7455 11:41:34.292452 Final DQ duty delay cell = 0
7456 11:41:34.295726 [0] MAX Duty = 5156%(X100), DQS PI = 0
7457 11:41:34.299148 [0] MIN Duty = 4906%(X100), DQS PI = 42
7458 11:41:34.299232 [0] AVG Duty = 5031%(X100)
7459 11:41:34.302241
7460 11:41:34.302323 ==DQ 1 ==
7461 11:41:34.305413 Final DQ duty delay cell = 0
7462 11:41:34.308711 [0] MAX Duty = 5156%(X100), DQS PI = 42
7463 11:41:34.312199 [0] MIN Duty = 4969%(X100), DQS PI = 26
7464 11:41:34.312309 [0] AVG Duty = 5062%(X100)
7465 11:41:34.312378
7466 11:41:34.318524 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7467 11:41:34.318606
7468 11:41:34.322362 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7469 11:41:34.325589 [DutyScan_Calibration_Flow] ====Done====
7470 11:41:34.328564 nWR fixed to 30
7471 11:41:34.328647 [ModeRegInit_LP4] CH0 RK0
7472 11:41:34.331825 [ModeRegInit_LP4] CH0 RK1
7473 11:41:34.335273 [ModeRegInit_LP4] CH1 RK0
7474 11:41:34.338562 [ModeRegInit_LP4] CH1 RK1
7475 11:41:34.338644 match AC timing 5
7476 11:41:34.345608 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7477 11:41:34.348678 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7478 11:41:34.351816 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7479 11:41:34.358539 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7480 11:41:34.362040 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7481 11:41:34.362148 [MiockJmeterHQA]
7482 11:41:34.362256
7483 11:41:34.364822 [DramcMiockJmeter] u1RxGatingPI = 0
7484 11:41:34.368820 0 : 4363, 4138
7485 11:41:34.368930 4 : 4253, 4027
7486 11:41:34.371754 8 : 4252, 4027
7487 11:41:34.371832 12 : 4252, 4027
7488 11:41:34.371898 16 : 4253, 4026
7489 11:41:34.375222 20 : 4363, 4138
7490 11:41:34.375314 24 : 4253, 4027
7491 11:41:34.378237 28 : 4252, 4027
7492 11:41:34.378320 32 : 4252, 4027
7493 11:41:34.381482 36 : 4255, 4029
7494 11:41:34.381565 40 : 4252, 4027
7495 11:41:34.385262 44 : 4363, 4137
7496 11:41:34.385346 48 : 4363, 4138
7497 11:41:34.385412 52 : 4255, 4030
7498 11:41:34.388206 56 : 4252, 4027
7499 11:41:34.388289 60 : 4253, 4027
7500 11:41:34.391459 64 : 4249, 4027
7501 11:41:34.391542 68 : 4255, 4029
7502 11:41:34.394855 72 : 4363, 4140
7503 11:41:34.394938 76 : 4252, 4029
7504 11:41:34.398181 80 : 4249, 4027
7505 11:41:34.398264 84 : 4249, 4027
7506 11:41:34.398340 88 : 4253, 4029
7507 11:41:34.401200 92 : 4249, 757
7508 11:41:34.401284 96 : 4250, 0
7509 11:41:34.404466 100 : 4361, 0
7510 11:41:34.404604 104 : 4252, 0
7511 11:41:34.404700 108 : 4360, 0
7512 11:41:34.407883 112 : 4250, 0
7513 11:41:34.407985 116 : 4250, 0
7514 11:41:34.411134 120 : 4250, 0
7515 11:41:34.411235 124 : 4250, 0
7516 11:41:34.411331 128 : 4250, 0
7517 11:41:34.414442 132 : 4250, 0
7518 11:41:34.414548 136 : 4250, 0
7519 11:41:34.417651 140 : 4250, 0
7520 11:41:34.417751 144 : 4250, 0
7521 11:41:34.417844 148 : 4252, 0
7522 11:41:34.420955 152 : 4250, 0
7523 11:41:34.421053 156 : 4361, 0
7524 11:41:34.424189 160 : 4360, 0
7525 11:41:34.424301 164 : 4361, 0
7526 11:41:34.424403 168 : 4360, 0
7527 11:41:34.427314 172 : 4250, 0
7528 11:41:34.427446 176 : 4250, 0
7529 11:41:34.431025 180 : 4250, 0
7530 11:41:34.431126 184 : 4249, 0
7531 11:41:34.431219 188 : 4250, 0
7532 11:41:34.434216 192 : 4250, 0
7533 11:41:34.434316 196 : 4250, 0
7534 11:41:34.434409 200 : 4252, 0
7535 11:41:34.437409 204 : 4250, 0
7536 11:41:34.437514 208 : 4360, 0
7537 11:41:34.441240 212 : 4361, 0
7538 11:41:34.441340 216 : 4361, 0
7539 11:41:34.441434 220 : 4360, 0
7540 11:41:34.443983 224 : 4250, 357
7541 11:41:34.444084 228 : 4250, 3574
7542 11:41:34.447525 232 : 4250, 4027
7543 11:41:34.447632 236 : 4250, 4026
7544 11:41:34.450662 240 : 4250, 4027
7545 11:41:34.450760 244 : 4250, 4027
7546 11:41:34.453822 248 : 4360, 4137
7547 11:41:34.453923 252 : 4250, 4026
7548 11:41:34.457330 256 : 4250, 4027
7549 11:41:34.457428 260 : 4361, 4138
7550 11:41:34.460572 264 : 4251, 4027
7551 11:41:34.460687 268 : 4250, 4026
7552 11:41:34.463834 272 : 4363, 4140
7553 11:41:34.463950 276 : 4250, 4027
7554 11:41:34.464048 280 : 4250, 4027
7555 11:41:34.467226 284 : 4250, 4026
7556 11:41:34.467311 288 : 4253, 4029
7557 11:41:34.470309 292 : 4250, 4027
7558 11:41:34.470393 296 : 4250, 4027
7559 11:41:34.473767 300 : 4360, 4137
7560 11:41:34.473851 304 : 4250, 4026
7561 11:41:34.476976 308 : 4250, 4027
7562 11:41:34.477060 312 : 4361, 4138
7563 11:41:34.480465 316 : 4250, 4027
7564 11:41:34.480602 320 : 4250, 4026
7565 11:41:34.483635 324 : 4363, 4140
7566 11:41:34.483719 328 : 4250, 4027
7567 11:41:34.486802 332 : 4250, 4027
7568 11:41:34.486886 336 : 4252, 3804
7569 11:41:34.489843 340 : 4253, 1960
7570 11:41:34.489926
7571 11:41:34.489991 MIOCK jitter meter ch=0
7572 11:41:34.490052
7573 11:41:34.493311 1T = (340-92) = 248 dly cells
7574 11:41:34.499717 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7575 11:41:34.499799 ==
7576 11:41:34.503627 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 11:41:34.506847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 11:41:34.506930 ==
7579 11:41:34.513144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7580 11:41:34.516447 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7581 11:41:34.523009 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7582 11:41:34.525925 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7583 11:41:34.536016 [CA 0] Center 43 (13~74) winsize 62
7584 11:41:34.539780 [CA 1] Center 42 (12~73) winsize 62
7585 11:41:34.542936 [CA 2] Center 38 (9~68) winsize 60
7586 11:41:34.545845 [CA 3] Center 38 (8~68) winsize 61
7587 11:41:34.549284 [CA 4] Center 36 (7~66) winsize 60
7588 11:41:34.552341 [CA 5] Center 35 (6~65) winsize 60
7589 11:41:34.552423
7590 11:41:34.555758 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7591 11:41:34.555839
7592 11:41:34.562928 [CATrainingPosCal] consider 1 rank data
7593 11:41:34.563011 u2DelayCellTimex100 = 262/100 ps
7594 11:41:34.568957 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7595 11:41:34.572076 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7596 11:41:34.575521 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7597 11:41:34.579032 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7598 11:41:34.581652 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7599 11:41:34.585238 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7600 11:41:34.585320
7601 11:41:34.588605 CA PerBit enable=1, Macro0, CA PI delay=35
7602 11:41:34.591849
7603 11:41:34.591930 [CBTSetCACLKResult] CA Dly = 35
7604 11:41:34.594873 CS Dly: 12 (0~43)
7605 11:41:34.598091 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7606 11:41:34.601668 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7607 11:41:34.605179 ==
7608 11:41:34.608313 Dram Type= 6, Freq= 0, CH_0, rank 1
7609 11:41:34.611351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 11:41:34.611434 ==
7611 11:41:34.614834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7612 11:41:34.621556 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7613 11:41:34.625125 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7614 11:41:34.631116 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7615 11:41:34.639527 [CA 0] Center 42 (12~73) winsize 62
7616 11:41:34.643314 [CA 1] Center 43 (13~73) winsize 61
7617 11:41:34.646434 [CA 2] Center 37 (8~67) winsize 60
7618 11:41:34.649764 [CA 3] Center 37 (7~67) winsize 61
7619 11:41:34.653070 [CA 4] Center 35 (6~65) winsize 60
7620 11:41:34.656223 [CA 5] Center 35 (5~65) winsize 61
7621 11:41:34.656333
7622 11:41:34.659493 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7623 11:41:34.659566
7624 11:41:34.662929 [CATrainingPosCal] consider 2 rank data
7625 11:41:34.666259 u2DelayCellTimex100 = 262/100 ps
7626 11:41:34.672407 CA0 delay=43 (13~73),Diff = 8 PI (29 cell)
7627 11:41:34.676462 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7628 11:41:34.679177 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7629 11:41:34.682298 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7630 11:41:34.685945 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7631 11:41:34.689210 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7632 11:41:34.689292
7633 11:41:34.692185 CA PerBit enable=1, Macro0, CA PI delay=35
7634 11:41:34.692266
7635 11:41:34.695931 [CBTSetCACLKResult] CA Dly = 35
7636 11:41:34.699055 CS Dly: 12 (0~44)
7637 11:41:34.702507 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7638 11:41:34.705517 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7639 11:41:34.705598
7640 11:41:34.709087 ----->DramcWriteLeveling(PI) begin...
7641 11:41:34.709170 ==
7642 11:41:34.712254 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 11:41:34.718710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 11:41:34.718796 ==
7645 11:41:34.721656 Write leveling (Byte 0): 34 => 34
7646 11:41:34.725352 Write leveling (Byte 1): 29 => 29
7647 11:41:34.728626 DramcWriteLeveling(PI) end<-----
7648 11:41:34.728708
7649 11:41:34.728772 ==
7650 11:41:34.732010 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 11:41:34.735024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 11:41:34.735107 ==
7653 11:41:34.738315 [Gating] SW mode calibration
7654 11:41:34.744995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7655 11:41:34.751495 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7656 11:41:34.754938 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 11:41:34.758140 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 11:41:34.764593 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 11:41:34.767862 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
7660 11:41:34.771151 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7661 11:41:34.777822 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7662 11:41:34.780979 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7663 11:41:34.784621 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 11:41:34.791517 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 11:41:34.794441 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7666 11:41:34.797727 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7667 11:41:34.804537 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
7668 11:41:34.807954 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7669 11:41:34.811144 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7670 11:41:34.817143 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7671 11:41:34.821040 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 11:41:34.824358 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 11:41:34.830756 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 11:41:34.834068 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 11:41:34.837293 1 6 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7676 11:41:34.843826 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7677 11:41:34.847306 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7678 11:41:34.850294 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7679 11:41:34.856828 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 11:41:34.860303 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 11:41:34.863799 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 11:41:34.869881 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 11:41:34.873275 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7684 11:41:34.876670 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7685 11:41:34.883181 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7686 11:41:34.886448 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7687 11:41:34.890160 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 11:41:34.896832 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 11:41:34.899773 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 11:41:34.903032 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 11:41:34.909547 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 11:41:34.912699 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 11:41:34.915895 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 11:41:34.922699 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 11:41:34.926418 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 11:41:34.929377 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 11:41:34.935929 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 11:41:34.939347 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 11:41:34.942777 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7700 11:41:34.946140 Total UI for P1: 0, mck2ui 16
7701 11:41:34.949072 best dqsien dly found for B0: ( 1, 9, 10)
7702 11:41:34.955617 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7703 11:41:34.958819 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7704 11:41:34.962391 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 11:41:34.965673 Total UI for P1: 0, mck2ui 16
7706 11:41:34.969135 best dqsien dly found for B1: ( 1, 9, 18)
7707 11:41:34.972700 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7708 11:41:34.975978 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7709 11:41:34.976060
7710 11:41:34.978884 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7711 11:41:34.985394 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7712 11:41:34.985477 [Gating] SW calibration Done
7713 11:41:34.988943 ==
7714 11:41:34.991930 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 11:41:34.995319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 11:41:34.995401 ==
7717 11:41:34.995466 RX Vref Scan: 0
7718 11:41:34.995528
7719 11:41:34.998645 RX Vref 0 -> 0, step: 1
7720 11:41:34.998727
7721 11:41:35.002076 RX Delay 0 -> 252, step: 8
7722 11:41:35.005682 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7723 11:41:35.008528 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7724 11:41:35.012132 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7725 11:41:35.019049 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7726 11:41:35.021785 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7727 11:41:35.024828 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7728 11:41:35.028748 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7729 11:41:35.032103 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7730 11:41:35.038341 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7731 11:41:35.041373 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7732 11:41:35.044520 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7733 11:41:35.048010 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7734 11:41:35.054547 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7735 11:41:35.057966 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7736 11:41:35.061330 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7737 11:41:35.064640 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7738 11:41:35.064715 ==
7739 11:41:35.068032 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 11:41:35.074318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 11:41:35.074399 ==
7742 11:41:35.074472 DQS Delay:
7743 11:41:35.077652 DQS0 = 0, DQS1 = 0
7744 11:41:35.077757 DQM Delay:
7745 11:41:35.077848 DQM0 = 134, DQM1 = 126
7746 11:41:35.080775 DQ Delay:
7747 11:41:35.084505 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7748 11:41:35.087495 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7749 11:41:35.090716 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7750 11:41:35.094112 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7751 11:41:35.094184
7752 11:41:35.094255
7753 11:41:35.094317 ==
7754 11:41:35.097841 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 11:41:35.103733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 11:41:35.103811 ==
7757 11:41:35.103876
7758 11:41:35.103943
7759 11:41:35.104002 TX Vref Scan disable
7760 11:41:35.107643 == TX Byte 0 ==
7761 11:41:35.110688 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7762 11:41:35.117357 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7763 11:41:35.117435 == TX Byte 1 ==
7764 11:41:35.120575 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7765 11:41:35.127329 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7766 11:41:35.127406 ==
7767 11:41:35.130310 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 11:41:35.133590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 11:41:35.133673 ==
7770 11:41:35.146542
7771 11:41:35.149839 TX Vref early break, caculate TX vref
7772 11:41:35.153166 TX Vref=16, minBit 0, minWin=23, winSum=375
7773 11:41:35.156229 TX Vref=18, minBit 1, minWin=23, winSum=383
7774 11:41:35.159625 TX Vref=20, minBit 6, minWin=23, winSum=390
7775 11:41:35.162990 TX Vref=22, minBit 1, minWin=24, winSum=402
7776 11:41:35.166354 TX Vref=24, minBit 1, minWin=24, winSum=410
7777 11:41:35.172883 TX Vref=26, minBit 0, minWin=25, winSum=419
7778 11:41:35.176048 TX Vref=28, minBit 3, minWin=25, winSum=423
7779 11:41:35.179430 TX Vref=30, minBit 5, minWin=24, winSum=416
7780 11:41:35.182735 TX Vref=32, minBit 4, minWin=24, winSum=403
7781 11:41:35.186178 TX Vref=34, minBit 0, minWin=23, winSum=397
7782 11:41:35.192752 [TxChooseVref] Worse bit 3, Min win 25, Win sum 423, Final Vref 28
7783 11:41:35.192830
7784 11:41:35.196144 Final TX Range 0 Vref 28
7785 11:41:35.196224
7786 11:41:35.196287 ==
7787 11:41:35.199596 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 11:41:35.202655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 11:41:35.202739 ==
7790 11:41:35.202806
7791 11:41:35.202867
7792 11:41:35.205897 TX Vref Scan disable
7793 11:41:35.212777 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7794 11:41:35.212860 == TX Byte 0 ==
7795 11:41:35.215952 u2DelayCellOfst[0]=11 cells (3 PI)
7796 11:41:35.219053 u2DelayCellOfst[1]=14 cells (4 PI)
7797 11:41:35.222319 u2DelayCellOfst[2]=11 cells (3 PI)
7798 11:41:35.225671 u2DelayCellOfst[3]=11 cells (3 PI)
7799 11:41:35.229008 u2DelayCellOfst[4]=7 cells (2 PI)
7800 11:41:35.232403 u2DelayCellOfst[5]=0 cells (0 PI)
7801 11:41:35.235527 u2DelayCellOfst[6]=18 cells (5 PI)
7802 11:41:35.238792 u2DelayCellOfst[7]=18 cells (5 PI)
7803 11:41:35.242057 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7804 11:41:35.245063 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7805 11:41:35.248491 == TX Byte 1 ==
7806 11:41:35.252121 u2DelayCellOfst[8]=0 cells (0 PI)
7807 11:41:35.255354 u2DelayCellOfst[9]=3 cells (1 PI)
7808 11:41:35.255433 u2DelayCellOfst[10]=7 cells (2 PI)
7809 11:41:35.258394 u2DelayCellOfst[11]=3 cells (1 PI)
7810 11:41:35.261939 u2DelayCellOfst[12]=11 cells (3 PI)
7811 11:41:35.265568 u2DelayCellOfst[13]=11 cells (3 PI)
7812 11:41:35.269020 u2DelayCellOfst[14]=14 cells (4 PI)
7813 11:41:35.272085 u2DelayCellOfst[15]=11 cells (3 PI)
7814 11:41:35.278722 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7815 11:41:35.282273 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7816 11:41:35.282868 DramC Write-DBI on
7817 11:41:35.283427 ==
7818 11:41:35.285708 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 11:41:35.292298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 11:41:35.292891 ==
7821 11:41:35.293389
7822 11:41:35.293868
7823 11:41:35.294393 TX Vref Scan disable
7824 11:41:35.296218 == TX Byte 0 ==
7825 11:41:35.299409 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7826 11:41:35.302515 == TX Byte 1 ==
7827 11:41:35.305983 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7828 11:41:35.309192 DramC Write-DBI off
7829 11:41:35.309818
7830 11:41:35.310317 [DATLAT]
7831 11:41:35.310792 Freq=1600, CH0 RK0
7832 11:41:35.311276
7833 11:41:35.312361 DATLAT Default: 0xf
7834 11:41:35.315869 0, 0xFFFF, sum = 0
7835 11:41:35.316440 1, 0xFFFF, sum = 0
7836 11:41:35.319328 2, 0xFFFF, sum = 0
7837 11:41:35.319761 3, 0xFFFF, sum = 0
7838 11:41:35.322527 4, 0xFFFF, sum = 0
7839 11:41:35.322959 5, 0xFFFF, sum = 0
7840 11:41:35.325664 6, 0xFFFF, sum = 0
7841 11:41:35.326088 7, 0xFFFF, sum = 0
7842 11:41:35.329383 8, 0xFFFF, sum = 0
7843 11:41:35.329807 9, 0xFFFF, sum = 0
7844 11:41:35.332073 10, 0xFFFF, sum = 0
7845 11:41:35.332499 11, 0xFFFF, sum = 0
7846 11:41:35.335198 12, 0xFFFF, sum = 0
7847 11:41:35.339045 13, 0xFFFF, sum = 0
7848 11:41:35.339471 14, 0x0, sum = 1
7849 11:41:35.339816 15, 0x0, sum = 2
7850 11:41:35.342262 16, 0x0, sum = 3
7851 11:41:35.342688 17, 0x0, sum = 4
7852 11:41:35.345394 best_step = 15
7853 11:41:35.345832
7854 11:41:35.346171 ==
7855 11:41:35.348586 Dram Type= 6, Freq= 0, CH_0, rank 0
7856 11:41:35.351922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7857 11:41:35.352379 ==
7858 11:41:35.355002 RX Vref Scan: 1
7859 11:41:35.355553
7860 11:41:35.356122 Set Vref Range= 24 -> 127
7861 11:41:35.358220
7862 11:41:35.358643 RX Vref 24 -> 127, step: 1
7863 11:41:35.358979
7864 11:41:35.361670 RX Delay 11 -> 252, step: 4
7865 11:41:35.362094
7866 11:41:35.365076 Set Vref, RX VrefLevel [Byte0]: 24
7867 11:41:35.368337 [Byte1]: 24
7868 11:41:35.368871
7869 11:41:35.371812 Set Vref, RX VrefLevel [Byte0]: 25
7870 11:41:35.374602 [Byte1]: 25
7871 11:41:35.379046
7872 11:41:35.379470 Set Vref, RX VrefLevel [Byte0]: 26
7873 11:41:35.382076 [Byte1]: 26
7874 11:41:35.386465
7875 11:41:35.386993 Set Vref, RX VrefLevel [Byte0]: 27
7876 11:41:35.390272 [Byte1]: 27
7877 11:41:35.393984
7878 11:41:35.394504 Set Vref, RX VrefLevel [Byte0]: 28
7879 11:41:35.397411 [Byte1]: 28
7880 11:41:35.401713
7881 11:41:35.402135 Set Vref, RX VrefLevel [Byte0]: 29
7882 11:41:35.405547 [Byte1]: 29
7883 11:41:35.409505
7884 11:41:35.409958 Set Vref, RX VrefLevel [Byte0]: 30
7885 11:41:35.412951 [Byte1]: 30
7886 11:41:35.417060
7887 11:41:35.417619 Set Vref, RX VrefLevel [Byte0]: 31
7888 11:41:35.420310 [Byte1]: 31
7889 11:41:35.424878
7890 11:41:35.425394 Set Vref, RX VrefLevel [Byte0]: 32
7891 11:41:35.427892 [Byte1]: 32
7892 11:41:35.431617
7893 11:41:35.431729 Set Vref, RX VrefLevel [Byte0]: 33
7894 11:41:35.435161 [Byte1]: 33
7895 11:41:35.439522
7896 11:41:35.439598 Set Vref, RX VrefLevel [Byte0]: 34
7897 11:41:35.443052 [Byte1]: 34
7898 11:41:35.447197
7899 11:41:35.447300 Set Vref, RX VrefLevel [Byte0]: 35
7900 11:41:35.450458 [Byte1]: 35
7901 11:41:35.454611
7902 11:41:35.454720 Set Vref, RX VrefLevel [Byte0]: 36
7903 11:41:35.458329 [Byte1]: 36
7904 11:41:35.462362
7905 11:41:35.462464 Set Vref, RX VrefLevel [Byte0]: 37
7906 11:41:35.465524 [Byte1]: 37
7907 11:41:35.470170
7908 11:41:35.470276 Set Vref, RX VrefLevel [Byte0]: 38
7909 11:41:35.473202 [Byte1]: 38
7910 11:41:35.477485
7911 11:41:35.477585 Set Vref, RX VrefLevel [Byte0]: 39
7912 11:41:35.480988 [Byte1]: 39
7913 11:41:35.485246
7914 11:41:35.485322 Set Vref, RX VrefLevel [Byte0]: 40
7915 11:41:35.488288 [Byte1]: 40
7916 11:41:35.492637
7917 11:41:35.492716 Set Vref, RX VrefLevel [Byte0]: 41
7918 11:41:35.496247 [Byte1]: 41
7919 11:41:35.500104
7920 11:41:35.503359 Set Vref, RX VrefLevel [Byte0]: 42
7921 11:41:35.506638 [Byte1]: 42
7922 11:41:35.506742
7923 11:41:35.509856 Set Vref, RX VrefLevel [Byte0]: 43
7924 11:41:35.513290 [Byte1]: 43
7925 11:41:35.513401
7926 11:41:35.516599 Set Vref, RX VrefLevel [Byte0]: 44
7927 11:41:35.520206 [Byte1]: 44
7928 11:41:35.523275
7929 11:41:35.523391 Set Vref, RX VrefLevel [Byte0]: 45
7930 11:41:35.526650 [Byte1]: 45
7931 11:41:35.530681
7932 11:41:35.530799 Set Vref, RX VrefLevel [Byte0]: 46
7933 11:41:35.533983 [Byte1]: 46
7934 11:41:35.538397
7935 11:41:35.538504 Set Vref, RX VrefLevel [Byte0]: 47
7936 11:41:35.541800 [Byte1]: 47
7937 11:41:35.546058
7938 11:41:35.546163 Set Vref, RX VrefLevel [Byte0]: 48
7939 11:41:35.549513 [Byte1]: 48
7940 11:41:35.553644
7941 11:41:35.553747 Set Vref, RX VrefLevel [Byte0]: 49
7942 11:41:35.556949 [Byte1]: 49
7943 11:41:35.561203
7944 11:41:35.561307 Set Vref, RX VrefLevel [Byte0]: 50
7945 11:41:35.564339 [Byte1]: 50
7946 11:41:35.568671
7947 11:41:35.568799 Set Vref, RX VrefLevel [Byte0]: 51
7948 11:41:35.572501 [Byte1]: 51
7949 11:41:35.576685
7950 11:41:35.576792 Set Vref, RX VrefLevel [Byte0]: 52
7951 11:41:35.580006 [Byte1]: 52
7952 11:41:35.583826
7953 11:41:35.583931 Set Vref, RX VrefLevel [Byte0]: 53
7954 11:41:35.587664 [Byte1]: 53
7955 11:41:35.591419
7956 11:41:35.591520 Set Vref, RX VrefLevel [Byte0]: 54
7957 11:41:35.595186 [Byte1]: 54
7958 11:41:35.599087
7959 11:41:35.599194 Set Vref, RX VrefLevel [Byte0]: 55
7960 11:41:35.602533 [Byte1]: 55
7961 11:41:35.607081
7962 11:41:35.607185 Set Vref, RX VrefLevel [Byte0]: 56
7963 11:41:35.610478 [Byte1]: 56
7964 11:41:35.614270
7965 11:41:35.614373 Set Vref, RX VrefLevel [Byte0]: 57
7966 11:41:35.617779 [Byte1]: 57
7967 11:41:35.622693
7968 11:41:35.622801 Set Vref, RX VrefLevel [Byte0]: 58
7969 11:41:35.625162 [Byte1]: 58
7970 11:41:35.629964
7971 11:41:35.630066 Set Vref, RX VrefLevel [Byte0]: 59
7972 11:41:35.633138 [Byte1]: 59
7973 11:41:35.637213
7974 11:41:35.637317 Set Vref, RX VrefLevel [Byte0]: 60
7975 11:41:35.641110 [Byte1]: 60
7976 11:41:35.645194
7977 11:41:35.645301 Set Vref, RX VrefLevel [Byte0]: 61
7978 11:41:35.648572 [Byte1]: 61
7979 11:41:35.652757
7980 11:41:35.652865 Set Vref, RX VrefLevel [Byte0]: 62
7981 11:41:35.655756 [Byte1]: 62
7982 11:41:35.660136
7983 11:41:35.660243 Set Vref, RX VrefLevel [Byte0]: 63
7984 11:41:35.663239 [Byte1]: 63
7985 11:41:35.667751
7986 11:41:35.667858 Set Vref, RX VrefLevel [Byte0]: 64
7987 11:41:35.671326 [Byte1]: 64
7988 11:41:35.675147
7989 11:41:35.675264 Set Vref, RX VrefLevel [Byte0]: 65
7990 11:41:35.678464 [Byte1]: 65
7991 11:41:35.683047
7992 11:41:35.683152 Set Vref, RX VrefLevel [Byte0]: 66
7993 11:41:35.686103 [Byte1]: 66
7994 11:41:35.690543
7995 11:41:35.690620 Set Vref, RX VrefLevel [Byte0]: 67
7996 11:41:35.694039 [Byte1]: 67
7997 11:41:35.698282
7998 11:41:35.701594 Set Vref, RX VrefLevel [Byte0]: 68
7999 11:41:35.704984 [Byte1]: 68
8000 11:41:35.705067
8001 11:41:35.708156 Set Vref, RX VrefLevel [Byte0]: 69
8002 11:41:35.711473 [Byte1]: 69
8003 11:41:35.711556
8004 11:41:35.714970 Set Vref, RX VrefLevel [Byte0]: 70
8005 11:41:35.717561 [Byte1]: 70
8006 11:41:35.721241
8007 11:41:35.721324 Set Vref, RX VrefLevel [Byte0]: 71
8008 11:41:35.724282 [Byte1]: 71
8009 11:41:35.728921
8010 11:41:35.729003 Set Vref, RX VrefLevel [Byte0]: 72
8011 11:41:35.732311 [Byte1]: 72
8012 11:41:35.736262
8013 11:41:35.736369 Set Vref, RX VrefLevel [Byte0]: 73
8014 11:41:35.739795 [Byte1]: 73
8015 11:41:35.744018
8016 11:41:35.744100 Set Vref, RX VrefLevel [Byte0]: 74
8017 11:41:35.747327 [Byte1]: 74
8018 11:41:35.751607
8019 11:41:35.751715 Set Vref, RX VrefLevel [Byte0]: 75
8020 11:41:35.754990 [Byte1]: 75
8021 11:41:35.759247
8022 11:41:35.759364 Set Vref, RX VrefLevel [Byte0]: 76
8023 11:41:35.762818 [Byte1]: 76
8024 11:41:35.766569
8025 11:41:35.766651 Set Vref, RX VrefLevel [Byte0]: 77
8026 11:41:35.770088 [Byte1]: 77
8027 11:41:35.774325
8028 11:41:35.774409 Set Vref, RX VrefLevel [Byte0]: 78
8029 11:41:35.777936 [Byte1]: 78
8030 11:41:35.782232
8031 11:41:35.782314 Set Vref, RX VrefLevel [Byte0]: 79
8032 11:41:35.785404 [Byte1]: 79
8033 11:41:35.790012
8034 11:41:35.790095 Set Vref, RX VrefLevel [Byte0]: 80
8035 11:41:35.793437 [Byte1]: 80
8036 11:41:35.797362
8037 11:41:35.800417 Final RX Vref Byte 0 = 68 to rank0
8038 11:41:35.800557 Final RX Vref Byte 1 = 60 to rank0
8039 11:41:35.803637 Final RX Vref Byte 0 = 68 to rank1
8040 11:41:35.807063 Final RX Vref Byte 1 = 60 to rank1==
8041 11:41:35.810290 Dram Type= 6, Freq= 0, CH_0, rank 0
8042 11:41:35.816998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8043 11:41:35.817106 ==
8044 11:41:35.817200 DQS Delay:
8045 11:41:35.820526 DQS0 = 0, DQS1 = 0
8046 11:41:35.820599 DQM Delay:
8047 11:41:35.823902 DQM0 = 133, DQM1 = 123
8048 11:41:35.823984 DQ Delay:
8049 11:41:35.827083 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8050 11:41:35.830608 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8051 11:41:35.833103 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8052 11:41:35.837023 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8053 11:41:35.837106
8054 11:41:35.837171
8055 11:41:35.837232
8056 11:41:35.839970 [DramC_TX_OE_Calibration] TA2
8057 11:41:35.843586 Original DQ_B0 (3 6) =30, OEN = 27
8058 11:41:35.846845 Original DQ_B1 (3 6) =30, OEN = 27
8059 11:41:35.849740 24, 0x0, End_B0=24 End_B1=24
8060 11:41:35.852986 25, 0x0, End_B0=25 End_B1=25
8061 11:41:35.853090 26, 0x0, End_B0=26 End_B1=26
8062 11:41:35.856453 27, 0x0, End_B0=27 End_B1=27
8063 11:41:35.859723 28, 0x0, End_B0=28 End_B1=28
8064 11:41:35.863139 29, 0x0, End_B0=29 End_B1=29
8065 11:41:35.866396 30, 0x0, End_B0=30 End_B1=30
8066 11:41:35.866481 31, 0x4141, End_B0=30 End_B1=30
8067 11:41:35.869655 Byte0 end_step=30 best_step=27
8068 11:41:35.872715 Byte1 end_step=30 best_step=27
8069 11:41:35.876003 Byte0 TX OE(2T, 0.5T) = (3, 3)
8070 11:41:35.879369 Byte1 TX OE(2T, 0.5T) = (3, 3)
8071 11:41:35.879452
8072 11:41:35.879517
8073 11:41:35.886089 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8074 11:41:35.889257 CH0 RK0: MR19=303, MR18=2112
8075 11:41:35.895743 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8076 11:41:35.895826
8077 11:41:35.899422 ----->DramcWriteLeveling(PI) begin...
8078 11:41:35.899507 ==
8079 11:41:35.902395 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 11:41:35.906260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 11:41:35.906344 ==
8082 11:41:35.908957 Write leveling (Byte 0): 34 => 34
8083 11:41:35.912277 Write leveling (Byte 1): 27 => 27
8084 11:41:35.916071 DramcWriteLeveling(PI) end<-----
8085 11:41:35.916191
8086 11:41:35.916296 ==
8087 11:41:35.919046 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 11:41:35.925876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 11:41:35.925959 ==
8090 11:41:35.926025 [Gating] SW mode calibration
8091 11:41:35.935741 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8092 11:41:35.939017 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8093 11:41:35.945503 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 11:41:35.948777 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 11:41:35.951908 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 11:41:35.955639 1 4 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8097 11:41:35.961659 1 4 16 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
8098 11:41:35.965003 1 4 20 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
8099 11:41:35.971862 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 11:41:35.974888 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 11:41:35.978688 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8102 11:41:35.984904 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 11:41:35.988415 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 11:41:35.991936 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
8105 11:41:35.994739 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8106 11:41:36.001402 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8107 11:41:36.004583 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8108 11:41:36.007763 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 11:41:36.014599 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 11:41:36.017757 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 11:41:36.021104 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 11:41:36.027833 1 6 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8113 11:41:36.031323 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8114 11:41:36.034655 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8115 11:41:36.040746 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 11:41:36.044161 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 11:41:36.047697 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 11:41:36.053920 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 11:41:36.057138 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 11:41:36.060600 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8121 11:41:36.067290 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8122 11:41:36.070979 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 11:41:36.074202 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 11:41:36.080759 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 11:41:36.084011 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 11:41:36.086990 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 11:41:36.093647 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 11:41:36.097353 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 11:41:36.100152 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 11:41:36.107347 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 11:41:36.110511 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 11:41:36.114004 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 11:41:36.120556 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 11:41:36.123919 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 11:41:36.126964 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 11:41:36.133951 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8137 11:41:36.136682 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8138 11:41:36.139833 Total UI for P1: 0, mck2ui 16
8139 11:41:36.143083 best dqsien dly found for B0: ( 1, 9, 12)
8140 11:41:36.146389 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8141 11:41:36.153056 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8142 11:41:36.156384 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 11:41:36.159989 Total UI for P1: 0, mck2ui 16
8144 11:41:36.163223 best dqsien dly found for B1: ( 1, 9, 20)
8145 11:41:36.166458 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8146 11:41:36.169453 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8147 11:41:36.169535
8148 11:41:36.173272 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8149 11:41:36.179715 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8150 11:41:36.179800 [Gating] SW calibration Done
8151 11:41:36.179866 ==
8152 11:41:36.182878 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 11:41:36.189381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 11:41:36.189464 ==
8155 11:41:36.189530 RX Vref Scan: 0
8156 11:41:36.189591
8157 11:41:36.192954 RX Vref 0 -> 0, step: 1
8158 11:41:36.193036
8159 11:41:36.195867 RX Delay 0 -> 252, step: 8
8160 11:41:36.199086 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8161 11:41:36.202794 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8162 11:41:36.205841 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8163 11:41:36.212939 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8164 11:41:36.215878 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8165 11:41:36.219349 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8166 11:41:36.222762 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8167 11:41:36.225775 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8168 11:41:36.232102 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8169 11:41:36.235832 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8170 11:41:36.239196 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8171 11:41:36.242384 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8172 11:41:36.248861 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8173 11:41:36.251953 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8174 11:41:36.255909 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8175 11:41:36.258653 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8176 11:41:36.258736 ==
8177 11:41:36.262058 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 11:41:36.268555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 11:41:36.268638 ==
8180 11:41:36.268704 DQS Delay:
8181 11:41:36.268766 DQS0 = 0, DQS1 = 0
8182 11:41:36.272064 DQM Delay:
8183 11:41:36.272147 DQM0 = 133, DQM1 = 128
8184 11:41:36.275398 DQ Delay:
8185 11:41:36.278279 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8186 11:41:36.281395 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8187 11:41:36.285220 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8188 11:41:36.288334 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8189 11:41:36.288456
8190 11:41:36.288581
8191 11:41:36.288645 ==
8192 11:41:36.291445 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 11:41:36.297973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 11:41:36.298059 ==
8195 11:41:36.298125
8196 11:41:36.298191
8197 11:41:36.298251 TX Vref Scan disable
8198 11:41:36.301142 == TX Byte 0 ==
8199 11:41:36.304653 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8200 11:41:36.311191 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8201 11:41:36.311279 == TX Byte 1 ==
8202 11:41:36.314409 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8203 11:41:36.320803 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8204 11:41:36.320912 ==
8205 11:41:36.324367 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 11:41:36.327463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 11:41:36.327547 ==
8208 11:41:36.340833
8209 11:41:36.344086 TX Vref early break, caculate TX vref
8210 11:41:36.347270 TX Vref=16, minBit 0, minWin=23, winSum=378
8211 11:41:36.351091 TX Vref=18, minBit 1, minWin=23, winSum=388
8212 11:41:36.354178 TX Vref=20, minBit 1, minWin=23, winSum=393
8213 11:41:36.357282 TX Vref=22, minBit 5, minWin=23, winSum=400
8214 11:41:36.360385 TX Vref=24, minBit 1, minWin=24, winSum=410
8215 11:41:36.367109 TX Vref=26, minBit 1, minWin=24, winSum=413
8216 11:41:36.370612 TX Vref=28, minBit 1, minWin=24, winSum=408
8217 11:41:36.374018 TX Vref=30, minBit 5, minWin=24, winSum=403
8218 11:41:36.377491 TX Vref=32, minBit 0, minWin=24, winSum=392
8219 11:41:36.380872 TX Vref=34, minBit 5, minWin=23, winSum=386
8220 11:41:36.387067 [TxChooseVref] Worse bit 1, Min win 24, Win sum 413, Final Vref 26
8221 11:41:36.387179
8222 11:41:36.390380 Final TX Range 0 Vref 26
8223 11:41:36.390503
8224 11:41:36.390600 ==
8225 11:41:36.393549 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 11:41:36.397355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 11:41:36.397491 ==
8228 11:41:36.397599
8229 11:41:36.397699
8230 11:41:36.400554 TX Vref Scan disable
8231 11:41:36.406816 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8232 11:41:36.406992 == TX Byte 0 ==
8233 11:41:36.410585 u2DelayCellOfst[0]=11 cells (3 PI)
8234 11:41:36.413584 u2DelayCellOfst[1]=18 cells (5 PI)
8235 11:41:36.416846 u2DelayCellOfst[2]=11 cells (3 PI)
8236 11:41:36.420634 u2DelayCellOfst[3]=14 cells (4 PI)
8237 11:41:36.423772 u2DelayCellOfst[4]=7 cells (2 PI)
8238 11:41:36.427175 u2DelayCellOfst[5]=0 cells (0 PI)
8239 11:41:36.430653 u2DelayCellOfst[6]=18 cells (5 PI)
8240 11:41:36.434096 u2DelayCellOfst[7]=18 cells (5 PI)
8241 11:41:36.436880 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8242 11:41:36.440160 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8243 11:41:36.443879 == TX Byte 1 ==
8244 11:41:36.447490 u2DelayCellOfst[8]=0 cells (0 PI)
8245 11:41:36.450309 u2DelayCellOfst[9]=3 cells (1 PI)
8246 11:41:36.450934 u2DelayCellOfst[10]=7 cells (2 PI)
8247 11:41:36.453891 u2DelayCellOfst[11]=0 cells (0 PI)
8248 11:41:36.456585 u2DelayCellOfst[12]=11 cells (3 PI)
8249 11:41:36.459805 u2DelayCellOfst[13]=11 cells (3 PI)
8250 11:41:36.463006 u2DelayCellOfst[14]=18 cells (5 PI)
8251 11:41:36.466529 u2DelayCellOfst[15]=11 cells (3 PI)
8252 11:41:36.473373 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8253 11:41:36.476094 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8254 11:41:36.476553 DramC Write-DBI on
8255 11:41:36.479373 ==
8256 11:41:36.479805 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 11:41:36.486478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 11:41:36.486908 ==
8259 11:41:36.487250
8260 11:41:36.487567
8261 11:41:36.489324 TX Vref Scan disable
8262 11:41:36.489880 == TX Byte 0 ==
8263 11:41:36.496165 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8264 11:41:36.496690 == TX Byte 1 ==
8265 11:41:36.499429 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8266 11:41:36.502540 DramC Write-DBI off
8267 11:41:36.502623
8268 11:41:36.502687 [DATLAT]
8269 11:41:36.505215 Freq=1600, CH0 RK1
8270 11:41:36.505289
8271 11:41:36.505350 DATLAT Default: 0xf
8272 11:41:36.508546 0, 0xFFFF, sum = 0
8273 11:41:36.508633 1, 0xFFFF, sum = 0
8274 11:41:36.511873 2, 0xFFFF, sum = 0
8275 11:41:36.511982 3, 0xFFFF, sum = 0
8276 11:41:36.515326 4, 0xFFFF, sum = 0
8277 11:41:36.515427 5, 0xFFFF, sum = 0
8278 11:41:36.518475 6, 0xFFFF, sum = 0
8279 11:41:36.521986 7, 0xFFFF, sum = 0
8280 11:41:36.522060 8, 0xFFFF, sum = 0
8281 11:41:36.525063 9, 0xFFFF, sum = 0
8282 11:41:36.525135 10, 0xFFFF, sum = 0
8283 11:41:36.528443 11, 0xFFFF, sum = 0
8284 11:41:36.528522 12, 0xFFFF, sum = 0
8285 11:41:36.531892 13, 0xFFFF, sum = 0
8286 11:41:36.531988 14, 0x0, sum = 1
8287 11:41:36.535161 15, 0x0, sum = 2
8288 11:41:36.535257 16, 0x0, sum = 3
8289 11:41:36.539257 17, 0x0, sum = 4
8290 11:41:36.539352 best_step = 15
8291 11:41:36.539427
8292 11:41:36.539540 ==
8293 11:41:36.542149 Dram Type= 6, Freq= 0, CH_0, rank 1
8294 11:41:36.545738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 11:41:36.548864 ==
8296 11:41:36.549063 RX Vref Scan: 0
8297 11:41:36.549203
8298 11:41:36.551950 RX Vref 0 -> 0, step: 1
8299 11:41:36.552093
8300 11:41:36.555022 RX Delay 11 -> 252, step: 4
8301 11:41:36.558365 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8302 11:41:36.562118 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8303 11:41:36.565255 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8304 11:41:36.571644 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8305 11:41:36.575077 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8306 11:41:36.578268 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8307 11:41:36.581702 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8308 11:41:36.584889 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8309 11:41:36.591505 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8310 11:41:36.595044 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8311 11:41:36.598116 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8312 11:41:36.601400 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8313 11:41:36.604630 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8314 11:41:36.611060 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8315 11:41:36.614405 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8316 11:41:36.617660 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8317 11:41:36.618087 ==
8318 11:41:36.621692 Dram Type= 6, Freq= 0, CH_0, rank 1
8319 11:41:36.624267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 11:41:36.628229 ==
8321 11:41:36.628900 DQS Delay:
8322 11:41:36.629273 DQS0 = 0, DQS1 = 0
8323 11:41:36.631497 DQM Delay:
8324 11:41:36.631926 DQM0 = 129, DQM1 = 125
8325 11:41:36.634164 DQ Delay:
8326 11:41:36.638120 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =126
8327 11:41:36.641433 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140
8328 11:41:36.644642 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8329 11:41:36.647977 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8330 11:41:36.648454
8331 11:41:36.648872
8332 11:41:36.649190
8333 11:41:36.650996 [DramC_TX_OE_Calibration] TA2
8334 11:41:36.654041 Original DQ_B0 (3 6) =30, OEN = 27
8335 11:41:36.657967 Original DQ_B1 (3 6) =30, OEN = 27
8336 11:41:36.660702 24, 0x0, End_B0=24 End_B1=24
8337 11:41:36.661130 25, 0x0, End_B0=25 End_B1=25
8338 11:41:36.664391 26, 0x0, End_B0=26 End_B1=26
8339 11:41:36.667311 27, 0x0, End_B0=27 End_B1=27
8340 11:41:36.670809 28, 0x0, End_B0=28 End_B1=28
8341 11:41:36.674291 29, 0x0, End_B0=29 End_B1=29
8342 11:41:36.674769 30, 0x0, End_B0=30 End_B1=30
8343 11:41:36.677117 31, 0x4141, End_B0=30 End_B1=30
8344 11:41:36.680509 Byte0 end_step=30 best_step=27
8345 11:41:36.683628 Byte1 end_step=30 best_step=27
8346 11:41:36.687067 Byte0 TX OE(2T, 0.5T) = (3, 3)
8347 11:41:36.690423 Byte1 TX OE(2T, 0.5T) = (3, 3)
8348 11:41:36.690877
8349 11:41:36.691302
8350 11:41:36.697060 [DQSOSCAuto] RK1, (LSB)MR18= 0x1bff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 396 ps
8351 11:41:36.700621 CH0 RK1: MR19=302, MR18=1BFF
8352 11:41:36.706980 CH0_RK1: MR19=0x302, MR18=0x1BFF, DQSOSC=396, MR23=63, INC=23, DEC=15
8353 11:41:36.710090 [RxdqsGatingPostProcess] freq 1600
8354 11:41:36.713949 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8355 11:41:36.716932 best DQS0 dly(2T, 0.5T) = (1, 1)
8356 11:41:36.720901 best DQS1 dly(2T, 0.5T) = (1, 1)
8357 11:41:36.723926 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8358 11:41:36.727073 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8359 11:41:36.730102 best DQS0 dly(2T, 0.5T) = (1, 1)
8360 11:41:36.733346 best DQS1 dly(2T, 0.5T) = (1, 1)
8361 11:41:36.737255 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8362 11:41:36.739907 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8363 11:41:36.743220 Pre-setting of DQS Precalculation
8364 11:41:36.746855 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8365 11:41:36.747268 ==
8366 11:41:36.749849 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 11:41:36.756599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 11:41:36.756992 ==
8369 11:41:36.759731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 11:41:36.763197 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 11:41:36.769661 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 11:41:36.776591 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 11:41:36.783649 [CA 0] Center 41 (12~71) winsize 60
8374 11:41:36.787106 [CA 1] Center 41 (12~71) winsize 60
8375 11:41:36.790471 [CA 2] Center 37 (8~66) winsize 59
8376 11:41:36.793634 [CA 3] Center 36 (7~65) winsize 59
8377 11:41:36.797111 [CA 4] Center 36 (7~66) winsize 60
8378 11:41:36.800320 [CA 5] Center 36 (7~66) winsize 60
8379 11:41:36.800815
8380 11:41:36.803675 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8381 11:41:36.804259
8382 11:41:36.806665 [CATrainingPosCal] consider 1 rank data
8383 11:41:36.810699 u2DelayCellTimex100 = 262/100 ps
8384 11:41:36.817151 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8385 11:41:36.820240 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8386 11:41:36.823182 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8387 11:41:36.826711 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8388 11:41:36.830105 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8389 11:41:36.833513 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 11:41:36.833973
8391 11:41:36.836668 CA PerBit enable=1, Macro0, CA PI delay=36
8392 11:41:36.837148
8393 11:41:36.839624 [CBTSetCACLKResult] CA Dly = 36
8394 11:41:36.843140 CS Dly: 8 (0~39)
8395 11:41:36.846469 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 11:41:36.849885 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 11:41:36.850299 ==
8398 11:41:36.853014 Dram Type= 6, Freq= 0, CH_1, rank 1
8399 11:41:36.860039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 11:41:36.860461 ==
8401 11:41:36.863105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8402 11:41:36.866206 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8403 11:41:36.872311 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8404 11:41:36.878895 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8405 11:41:36.886618 [CA 0] Center 42 (12~72) winsize 61
8406 11:41:36.890112 [CA 1] Center 42 (13~72) winsize 60
8407 11:41:36.893229 [CA 2] Center 37 (8~67) winsize 60
8408 11:41:36.896817 [CA 3] Center 37 (8~67) winsize 60
8409 11:41:36.899432 [CA 4] Center 37 (8~67) winsize 60
8410 11:41:36.902753 [CA 5] Center 37 (8~66) winsize 59
8411 11:41:36.902837
8412 11:41:36.906020 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8413 11:41:36.906122
8414 11:41:36.913012 [CATrainingPosCal] consider 2 rank data
8415 11:41:36.913095 u2DelayCellTimex100 = 262/100 ps
8416 11:41:36.919526 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8417 11:41:36.922675 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8418 11:41:36.926046 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8419 11:41:36.929356 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8420 11:41:36.932738 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8421 11:41:36.935762 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8422 11:41:36.935845
8423 11:41:36.938790 CA PerBit enable=1, Macro0, CA PI delay=36
8424 11:41:36.938873
8425 11:41:36.942568 [CBTSetCACLKResult] CA Dly = 36
8426 11:41:36.945779 CS Dly: 10 (0~43)
8427 11:41:36.948795 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8428 11:41:36.951958 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8429 11:41:36.952040
8430 11:41:36.955174 ----->DramcWriteLeveling(PI) begin...
8431 11:41:36.958745 ==
8432 11:41:36.962123 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 11:41:36.965225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 11:41:36.965375 ==
8435 11:41:36.969010 Write leveling (Byte 0): 24 => 24
8436 11:41:36.971872 Write leveling (Byte 1): 26 => 26
8437 11:41:36.975204 DramcWriteLeveling(PI) end<-----
8438 11:41:36.975287
8439 11:41:36.975351 ==
8440 11:41:36.978227 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 11:41:36.982089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 11:41:36.982172 ==
8443 11:41:36.985329 [Gating] SW mode calibration
8444 11:41:36.991401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8445 11:41:36.998285 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8446 11:41:37.001741 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 11:41:37.005131 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 11:41:37.011488 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 11:41:37.014749 1 4 12 | B1->B0 | 2929 3333 | 0 1 | (0 0) (1 1)
8450 11:41:37.017918 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8451 11:41:37.024684 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 11:41:37.027927 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 11:41:37.030980 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 11:41:37.037954 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 11:41:37.041064 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 11:41:37.044712 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8457 11:41:37.051092 1 5 12 | B1->B0 | 3030 2525 | 0 0 | (0 1) (1 0)
8458 11:41:37.054640 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 11:41:37.058013 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 11:41:37.064695 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 11:41:37.067623 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 11:41:37.070893 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 11:41:37.077451 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 11:41:37.080896 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8465 11:41:37.084411 1 6 12 | B1->B0 | 3434 4040 | 0 0 | (1 1) (0 0)
8466 11:41:37.090903 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 11:41:37.094132 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 11:41:37.097522 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 11:41:37.104283 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 11:41:37.106995 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 11:41:37.110560 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 11:41:37.117136 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8473 11:41:37.120388 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8474 11:41:37.123543 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8475 11:41:37.130061 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 11:41:37.133410 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 11:41:37.136945 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 11:41:37.143432 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 11:41:37.147232 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 11:41:37.150149 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 11:41:37.156586 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 11:41:37.159931 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 11:41:37.163182 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 11:41:37.169755 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 11:41:37.173001 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 11:41:37.176054 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 11:41:37.182798 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 11:41:37.186641 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8489 11:41:37.189397 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8490 11:41:37.196671 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8491 11:41:37.197055 Total UI for P1: 0, mck2ui 16
8492 11:41:37.203403 best dqsien dly found for B0: ( 1, 9, 10)
8493 11:41:37.206829 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 11:41:37.209643 Total UI for P1: 0, mck2ui 16
8495 11:41:37.212659 best dqsien dly found for B1: ( 1, 9, 12)
8496 11:41:37.216404 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8497 11:41:37.219701 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8498 11:41:37.220223
8499 11:41:37.222891 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8500 11:41:37.225949 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8501 11:41:37.229044 [Gating] SW calibration Done
8502 11:41:37.229127 ==
8503 11:41:37.232160 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 11:41:37.235572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 11:41:37.239092 ==
8506 11:41:37.239174 RX Vref Scan: 0
8507 11:41:37.239252
8508 11:41:37.242235 RX Vref 0 -> 0, step: 1
8509 11:41:37.242317
8510 11:41:37.245616 RX Delay 0 -> 252, step: 8
8511 11:41:37.248898 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8512 11:41:37.252362 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8513 11:41:37.255438 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8514 11:41:37.259008 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8515 11:41:37.265176 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8516 11:41:37.268289 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8517 11:41:37.272240 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8518 11:41:37.275776 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8519 11:41:37.278637 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8520 11:41:37.285206 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8521 11:41:37.288259 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8522 11:41:37.292011 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8523 11:41:37.294962 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8524 11:41:37.298629 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8525 11:41:37.305397 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8526 11:41:37.308761 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8527 11:41:37.309018 ==
8528 11:41:37.312121 Dram Type= 6, Freq= 0, CH_1, rank 0
8529 11:41:37.315523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8530 11:41:37.315976 ==
8531 11:41:37.318870 DQS Delay:
8532 11:41:37.319601 DQS0 = 0, DQS1 = 0
8533 11:41:37.320142 DQM Delay:
8534 11:41:37.322056 DQM0 = 137, DQM1 = 129
8535 11:41:37.322502 DQ Delay:
8536 11:41:37.325341 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8537 11:41:37.328359 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8538 11:41:37.335342 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8539 11:41:37.338130 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8540 11:41:37.338756
8541 11:41:37.339304
8542 11:41:37.339855 ==
8543 11:41:37.341656 Dram Type= 6, Freq= 0, CH_1, rank 0
8544 11:41:37.344888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8545 11:41:37.345339 ==
8546 11:41:37.345738
8547 11:41:37.346106
8548 11:41:37.348021 TX Vref Scan disable
8549 11:41:37.351536 == TX Byte 0 ==
8550 11:41:37.355208 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8551 11:41:37.358338 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8552 11:41:37.361495 == TX Byte 1 ==
8553 11:41:37.364870 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8554 11:41:37.368249 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8555 11:41:37.368848 ==
8556 11:41:37.371166 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 11:41:37.374390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 11:41:37.378099 ==
8559 11:41:37.388874
8560 11:41:37.392201 TX Vref early break, caculate TX vref
8561 11:41:37.395465 TX Vref=16, minBit 0, minWin=22, winSum=379
8562 11:41:37.398598 TX Vref=18, minBit 0, minWin=22, winSum=386
8563 11:41:37.402134 TX Vref=20, minBit 1, minWin=23, winSum=394
8564 11:41:37.405493 TX Vref=22, minBit 0, minWin=23, winSum=406
8565 11:41:37.408681 TX Vref=24, minBit 5, minWin=23, winSum=414
8566 11:41:37.414850 TX Vref=26, minBit 0, minWin=25, winSum=420
8567 11:41:37.418359 TX Vref=28, minBit 0, minWin=25, winSum=421
8568 11:41:37.422116 TX Vref=30, minBit 5, minWin=24, winSum=412
8569 11:41:37.424973 TX Vref=32, minBit 1, minWin=23, winSum=403
8570 11:41:37.428259 TX Vref=34, minBit 1, minWin=23, winSum=395
8571 11:41:37.435189 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8572 11:41:37.435753
8573 11:41:37.438396 Final TX Range 0 Vref 28
8574 11:41:37.438981
8575 11:41:37.439355 ==
8576 11:41:37.441483 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 11:41:37.444628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 11:41:37.445132 ==
8579 11:41:37.445515
8580 11:41:37.447929
8581 11:41:37.448352 TX Vref Scan disable
8582 11:41:37.455227 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8583 11:41:37.455687 == TX Byte 0 ==
8584 11:41:37.457790 u2DelayCellOfst[0]=18 cells (5 PI)
8585 11:41:37.461417 u2DelayCellOfst[1]=11 cells (3 PI)
8586 11:41:37.464934 u2DelayCellOfst[2]=0 cells (0 PI)
8587 11:41:37.467949 u2DelayCellOfst[3]=3 cells (1 PI)
8588 11:41:37.471619 u2DelayCellOfst[4]=7 cells (2 PI)
8589 11:41:37.474186 u2DelayCellOfst[5]=18 cells (5 PI)
8590 11:41:37.477425 u2DelayCellOfst[6]=18 cells (5 PI)
8591 11:41:37.480641 u2DelayCellOfst[7]=7 cells (2 PI)
8592 11:41:37.484167 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8593 11:41:37.487453 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8594 11:41:37.491193 == TX Byte 1 ==
8595 11:41:37.493908 u2DelayCellOfst[8]=0 cells (0 PI)
8596 11:41:37.497048 u2DelayCellOfst[9]=3 cells (1 PI)
8597 11:41:37.500829 u2DelayCellOfst[10]=11 cells (3 PI)
8598 11:41:37.503874 u2DelayCellOfst[11]=7 cells (2 PI)
8599 11:41:37.506972 u2DelayCellOfst[12]=18 cells (5 PI)
8600 11:41:37.510181 u2DelayCellOfst[13]=18 cells (5 PI)
8601 11:41:37.510799 u2DelayCellOfst[14]=18 cells (5 PI)
8602 11:41:37.513983 u2DelayCellOfst[15]=18 cells (5 PI)
8603 11:41:37.520496 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8604 11:41:37.523622 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8605 11:41:37.527060 DramC Write-DBI on
8606 11:41:37.527625 ==
8607 11:41:37.530173 Dram Type= 6, Freq= 0, CH_1, rank 0
8608 11:41:37.534024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8609 11:41:37.534641 ==
8610 11:41:37.535181
8611 11:41:37.535575
8612 11:41:37.536837 TX Vref Scan disable
8613 11:41:37.537301 == TX Byte 0 ==
8614 11:41:37.543527 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8615 11:41:37.544100 == TX Byte 1 ==
8616 11:41:37.546752 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8617 11:41:37.550263 DramC Write-DBI off
8618 11:41:37.550733
8619 11:41:37.551107 [DATLAT]
8620 11:41:37.553114 Freq=1600, CH1 RK0
8621 11:41:37.553586
8622 11:41:37.553959 DATLAT Default: 0xf
8623 11:41:37.556704 0, 0xFFFF, sum = 0
8624 11:41:37.557210 1, 0xFFFF, sum = 0
8625 11:41:37.559524 2, 0xFFFF, sum = 0
8626 11:41:37.560028 3, 0xFFFF, sum = 0
8627 11:41:37.562937 4, 0xFFFF, sum = 0
8628 11:41:37.566283 5, 0xFFFF, sum = 0
8629 11:41:37.566757 6, 0xFFFF, sum = 0
8630 11:41:37.569571 7, 0xFFFF, sum = 0
8631 11:41:37.570047 8, 0xFFFF, sum = 0
8632 11:41:37.573617 9, 0xFFFF, sum = 0
8633 11:41:37.574048 10, 0xFFFF, sum = 0
8634 11:41:37.576628 11, 0xFFFF, sum = 0
8635 11:41:37.577222 12, 0xFFFF, sum = 0
8636 11:41:37.579901 13, 0xFFFF, sum = 0
8637 11:41:37.580325 14, 0x0, sum = 1
8638 11:41:37.582656 15, 0x0, sum = 2
8639 11:41:37.583084 16, 0x0, sum = 3
8640 11:41:37.586365 17, 0x0, sum = 4
8641 11:41:37.586789 best_step = 15
8642 11:41:37.587123
8643 11:41:37.587437 ==
8644 11:41:37.589838 Dram Type= 6, Freq= 0, CH_1, rank 0
8645 11:41:37.592791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8646 11:41:37.596409 ==
8647 11:41:37.596869 RX Vref Scan: 1
8648 11:41:37.597209
8649 11:41:37.599587 Set Vref Range= 24 -> 127
8650 11:41:37.600001
8651 11:41:37.602500 RX Vref 24 -> 127, step: 1
8652 11:41:37.602917
8653 11:41:37.603254 RX Delay 11 -> 252, step: 4
8654 11:41:37.603591
8655 11:41:37.606121 Set Vref, RX VrefLevel [Byte0]: 24
8656 11:41:37.609132 [Byte1]: 24
8657 11:41:37.613361
8658 11:41:37.613781 Set Vref, RX VrefLevel [Byte0]: 25
8659 11:41:37.616474 [Byte1]: 25
8660 11:41:37.620787
8661 11:41:37.621200 Set Vref, RX VrefLevel [Byte0]: 26
8662 11:41:37.624220 [Byte1]: 26
8663 11:41:37.628503
8664 11:41:37.628949 Set Vref, RX VrefLevel [Byte0]: 27
8665 11:41:37.631916 [Byte1]: 27
8666 11:41:37.636604
8667 11:41:37.637019 Set Vref, RX VrefLevel [Byte0]: 28
8668 11:41:37.639469 [Byte1]: 28
8669 11:41:37.643787
8670 11:41:37.644202 Set Vref, RX VrefLevel [Byte0]: 29
8671 11:41:37.646822 [Byte1]: 29
8672 11:41:37.651362
8673 11:41:37.651776 Set Vref, RX VrefLevel [Byte0]: 30
8674 11:41:37.654621 [Byte1]: 30
8675 11:41:37.658601
8676 11:41:37.659019 Set Vref, RX VrefLevel [Byte0]: 31
8677 11:41:37.662379 [Byte1]: 31
8678 11:41:37.666751
8679 11:41:37.667171 Set Vref, RX VrefLevel [Byte0]: 32
8680 11:41:37.669969 [Byte1]: 32
8681 11:41:37.674409
8682 11:41:37.674846 Set Vref, RX VrefLevel [Byte0]: 33
8683 11:41:37.677361 [Byte1]: 33
8684 11:41:37.681876
8685 11:41:37.682434 Set Vref, RX VrefLevel [Byte0]: 34
8686 11:41:37.685278 [Byte1]: 34
8687 11:41:37.689147
8688 11:41:37.689570 Set Vref, RX VrefLevel [Byte0]: 35
8689 11:41:37.692660 [Byte1]: 35
8690 11:41:37.696944
8691 11:41:37.697370 Set Vref, RX VrefLevel [Byte0]: 36
8692 11:41:37.700587 [Byte1]: 36
8693 11:41:37.705004
8694 11:41:37.705539 Set Vref, RX VrefLevel [Byte0]: 37
8695 11:41:37.707768 [Byte1]: 37
8696 11:41:37.712403
8697 11:41:37.712874 Set Vref, RX VrefLevel [Byte0]: 38
8698 11:41:37.715618 [Byte1]: 38
8699 11:41:37.719573
8700 11:41:37.720181 Set Vref, RX VrefLevel [Byte0]: 39
8701 11:41:37.723295 [Byte1]: 39
8702 11:41:37.727696
8703 11:41:37.728260 Set Vref, RX VrefLevel [Byte0]: 40
8704 11:41:37.730559 [Byte1]: 40
8705 11:41:37.735088
8706 11:41:37.735529 Set Vref, RX VrefLevel [Byte0]: 41
8707 11:41:37.738287 [Byte1]: 41
8708 11:41:37.742471
8709 11:41:37.742903 Set Vref, RX VrefLevel [Byte0]: 42
8710 11:41:37.746207 [Byte1]: 42
8711 11:41:37.750426
8712 11:41:37.750860 Set Vref, RX VrefLevel [Byte0]: 43
8713 11:41:37.753610 [Byte1]: 43
8714 11:41:37.758122
8715 11:41:37.758558 Set Vref, RX VrefLevel [Byte0]: 44
8716 11:41:37.761175 [Byte1]: 44
8717 11:41:37.765493
8718 11:41:37.765928 Set Vref, RX VrefLevel [Byte0]: 45
8719 11:41:37.768989 [Byte1]: 45
8720 11:41:37.772950
8721 11:41:37.773385 Set Vref, RX VrefLevel [Byte0]: 46
8722 11:41:37.776345 [Byte1]: 46
8723 11:41:37.780545
8724 11:41:37.780976 Set Vref, RX VrefLevel [Byte0]: 47
8725 11:41:37.784105 [Byte1]: 47
8726 11:41:37.788373
8727 11:41:37.788834 Set Vref, RX VrefLevel [Byte0]: 48
8728 11:41:37.791964 [Byte1]: 48
8729 11:41:37.796370
8730 11:41:37.796945 Set Vref, RX VrefLevel [Byte0]: 49
8731 11:41:37.799491 [Byte1]: 49
8732 11:41:37.803566
8733 11:41:37.804354 Set Vref, RX VrefLevel [Byte0]: 50
8734 11:41:37.806704 [Byte1]: 50
8735 11:41:37.811249
8736 11:41:37.811672 Set Vref, RX VrefLevel [Byte0]: 51
8737 11:41:37.814845 [Byte1]: 51
8738 11:41:37.818733
8739 11:41:37.819155 Set Vref, RX VrefLevel [Byte0]: 52
8740 11:41:37.822046 [Byte1]: 52
8741 11:41:37.826501
8742 11:41:37.826929 Set Vref, RX VrefLevel [Byte0]: 53
8743 11:41:37.829751 [Byte1]: 53
8744 11:41:37.833695
8745 11:41:37.833778 Set Vref, RX VrefLevel [Byte0]: 54
8746 11:41:37.836834 [Byte1]: 54
8747 11:41:37.841370
8748 11:41:37.841453 Set Vref, RX VrefLevel [Byte0]: 55
8749 11:41:37.844727 [Byte1]: 55
8750 11:41:37.849004
8751 11:41:37.849087 Set Vref, RX VrefLevel [Byte0]: 56
8752 11:41:37.852106 [Byte1]: 56
8753 11:41:37.856584
8754 11:41:37.856667 Set Vref, RX VrefLevel [Byte0]: 57
8755 11:41:37.859653 [Byte1]: 57
8756 11:41:37.863962
8757 11:41:37.864045 Set Vref, RX VrefLevel [Byte0]: 58
8758 11:41:37.867560 [Byte1]: 58
8759 11:41:37.872031
8760 11:41:37.872113 Set Vref, RX VrefLevel [Byte0]: 59
8761 11:41:37.875222 [Byte1]: 59
8762 11:41:37.879325
8763 11:41:37.879412 Set Vref, RX VrefLevel [Byte0]: 60
8764 11:41:37.883234 [Byte1]: 60
8765 11:41:37.887364
8766 11:41:37.887790 Set Vref, RX VrefLevel [Byte0]: 61
8767 11:41:37.891052 [Byte1]: 61
8768 11:41:37.895435
8769 11:41:37.896032 Set Vref, RX VrefLevel [Byte0]: 62
8770 11:41:37.898418 [Byte1]: 62
8771 11:41:37.902859
8772 11:41:37.903438 Set Vref, RX VrefLevel [Byte0]: 63
8773 11:41:37.905913 [Byte1]: 63
8774 11:41:37.910567
8775 11:41:37.911131 Set Vref, RX VrefLevel [Byte0]: 64
8776 11:41:37.913364 [Byte1]: 64
8777 11:41:37.917937
8778 11:41:37.918514 Set Vref, RX VrefLevel [Byte0]: 65
8779 11:41:37.921505 [Byte1]: 65
8780 11:41:37.925286
8781 11:41:37.925755 Set Vref, RX VrefLevel [Byte0]: 66
8782 11:41:37.929201 [Byte1]: 66
8783 11:41:37.933483
8784 11:41:37.934059 Set Vref, RX VrefLevel [Byte0]: 67
8785 11:41:37.936725 [Byte1]: 67
8786 11:41:37.941040
8787 11:41:37.941510 Set Vref, RX VrefLevel [Byte0]: 68
8788 11:41:37.943844 [Byte1]: 68
8789 11:41:37.948658
8790 11:41:37.949232 Set Vref, RX VrefLevel [Byte0]: 69
8791 11:41:37.951517 [Byte1]: 69
8792 11:41:37.955744
8793 11:41:37.956210 Set Vref, RX VrefLevel [Byte0]: 70
8794 11:41:37.959570 [Byte1]: 70
8795 11:41:37.963204
8796 11:41:37.963627 Set Vref, RX VrefLevel [Byte0]: 71
8797 11:41:37.966491 [Byte1]: 71
8798 11:41:37.971149
8799 11:41:37.971683 Set Vref, RX VrefLevel [Byte0]: 72
8800 11:41:37.974339 [Byte1]: 72
8801 11:41:37.978214
8802 11:41:37.978299 Final RX Vref Byte 0 = 54 to rank0
8803 11:41:37.981481 Final RX Vref Byte 1 = 60 to rank0
8804 11:41:37.984889 Final RX Vref Byte 0 = 54 to rank1
8805 11:41:37.988167 Final RX Vref Byte 1 = 60 to rank1==
8806 11:41:37.991765 Dram Type= 6, Freq= 0, CH_1, rank 0
8807 11:41:37.998295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 11:41:37.998483 ==
8809 11:41:37.998577 DQS Delay:
8810 11:41:38.001277 DQS0 = 0, DQS1 = 0
8811 11:41:38.001438 DQM Delay:
8812 11:41:38.001542 DQM0 = 133, DQM1 = 128
8813 11:41:38.004911 DQ Delay:
8814 11:41:38.008063 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8815 11:41:38.011484 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8816 11:41:38.014951 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8817 11:41:38.018152 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8818 11:41:38.018393
8819 11:41:38.018529
8820 11:41:38.018655
8821 11:41:38.021765 [DramC_TX_OE_Calibration] TA2
8822 11:41:38.024422 Original DQ_B0 (3 6) =30, OEN = 27
8823 11:41:38.028158 Original DQ_B1 (3 6) =30, OEN = 27
8824 11:41:38.031579 24, 0x0, End_B0=24 End_B1=24
8825 11:41:38.034578 25, 0x0, End_B0=25 End_B1=25
8826 11:41:38.034887 26, 0x0, End_B0=26 End_B1=26
8827 11:41:38.038105 27, 0x0, End_B0=27 End_B1=27
8828 11:41:38.041701 28, 0x0, End_B0=28 End_B1=28
8829 11:41:38.045042 29, 0x0, End_B0=29 End_B1=29
8830 11:41:38.045627 30, 0x0, End_B0=30 End_B1=30
8831 11:41:38.048368 31, 0x4141, End_B0=30 End_B1=30
8832 11:41:38.051024 Byte0 end_step=30 best_step=27
8833 11:41:38.053986 Byte1 end_step=30 best_step=27
8834 11:41:38.057398 Byte0 TX OE(2T, 0.5T) = (3, 3)
8835 11:41:38.061018 Byte1 TX OE(2T, 0.5T) = (3, 3)
8836 11:41:38.061489
8837 11:41:38.061863
8838 11:41:38.067423 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8839 11:41:38.071281 CH1 RK0: MR19=303, MR18=170D
8840 11:41:38.077423 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8841 11:41:38.078319
8842 11:41:38.081351 ----->DramcWriteLeveling(PI) begin...
8843 11:41:38.081937 ==
8844 11:41:38.083912 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 11:41:38.087602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 11:41:38.088034 ==
8847 11:41:38.090665 Write leveling (Byte 0): 22 => 22
8848 11:41:38.094007 Write leveling (Byte 1): 28 => 28
8849 11:41:38.097639 DramcWriteLeveling(PI) end<-----
8850 11:41:38.098250
8851 11:41:38.098734 ==
8852 11:41:38.100376 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 11:41:38.107289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 11:41:38.107923 ==
8855 11:41:38.108483 [Gating] SW mode calibration
8856 11:41:38.116805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8857 11:41:38.120346 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8858 11:41:38.126971 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 11:41:38.129907 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 11:41:38.133084 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8861 11:41:38.136170 1 4 12 | B1->B0 | 3333 2423 | 1 1 | (0 0) (0 0)
8862 11:41:38.143061 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8863 11:41:38.146333 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8864 11:41:38.153140 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8865 11:41:38.155973 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8866 11:41:38.159498 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8867 11:41:38.166189 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 11:41:38.169370 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8869 11:41:38.172579 1 5 12 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8870 11:41:38.179105 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
8871 11:41:38.182357 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8872 11:41:38.185604 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 11:41:38.188988 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 11:41:38.195725 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 11:41:38.199136 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 11:41:38.205882 1 6 8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8877 11:41:38.209158 1 6 12 | B1->B0 | 4545 2727 | 0 1 | (0 0) (0 0)
8878 11:41:38.212433 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 11:41:38.218880 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 11:41:38.221995 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 11:41:38.225804 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 11:41:38.232139 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 11:41:38.235376 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 11:41:38.238655 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 11:41:38.245752 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8886 11:41:38.249212 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8887 11:41:38.252487 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8888 11:41:38.259155 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 11:41:38.262136 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 11:41:38.265030 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 11:41:38.271836 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 11:41:38.274800 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 11:41:38.278484 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 11:41:38.284673 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 11:41:38.288218 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 11:41:38.291530 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 11:41:38.298276 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 11:41:38.301269 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 11:41:38.305107 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 11:41:38.311828 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8901 11:41:38.314710 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8902 11:41:38.318044 Total UI for P1: 0, mck2ui 16
8903 11:41:38.321956 best dqsien dly found for B1: ( 1, 9, 8)
8904 11:41:38.324762 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8905 11:41:38.327607 Total UI for P1: 0, mck2ui 16
8906 11:41:38.331007 best dqsien dly found for B0: ( 1, 9, 12)
8907 11:41:38.334538 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8908 11:41:38.337885 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8909 11:41:38.338351
8910 11:41:38.341224 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8911 11:41:38.348116 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8912 11:41:38.348726 [Gating] SW calibration Done
8913 11:41:38.351097 ==
8914 11:41:38.351587 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 11:41:38.357921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 11:41:38.358504 ==
8917 11:41:38.358878 RX Vref Scan: 0
8918 11:41:38.359229
8919 11:41:38.360596 RX Vref 0 -> 0, step: 1
8920 11:41:38.361058
8921 11:41:38.364070 RX Delay 0 -> 252, step: 8
8922 11:41:38.367309 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8923 11:41:38.370685 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8924 11:41:38.373671 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8925 11:41:38.380607 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8926 11:41:38.383525 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8927 11:41:38.387175 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8928 11:41:38.390283 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8929 11:41:38.393399 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8930 11:41:38.400199 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8931 11:41:38.403528 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8932 11:41:38.406907 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8933 11:41:38.410211 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8934 11:41:38.416650 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8935 11:41:38.419921 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8936 11:41:38.423289 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8937 11:41:38.426511 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8938 11:41:38.427076 ==
8939 11:41:38.430176 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 11:41:38.436450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 11:41:38.437058 ==
8942 11:41:38.437434 DQS Delay:
8943 11:41:38.439828 DQS0 = 0, DQS1 = 0
8944 11:41:38.440391 DQM Delay:
8945 11:41:38.442980 DQM0 = 136, DQM1 = 129
8946 11:41:38.443442 DQ Delay:
8947 11:41:38.446413 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8948 11:41:38.449811 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8949 11:41:38.452619 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8950 11:41:38.456181 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8951 11:41:38.456788
8952 11:41:38.457163
8953 11:41:38.457590 ==
8954 11:41:38.459588 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 11:41:38.466317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 11:41:38.466887 ==
8957 11:41:38.467260
8958 11:41:38.467604
8959 11:41:38.467930 TX Vref Scan disable
8960 11:41:38.469326 == TX Byte 0 ==
8961 11:41:38.473199 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8962 11:41:38.479335 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8963 11:41:38.479840 == TX Byte 1 ==
8964 11:41:38.482444 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8965 11:41:38.489027 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8966 11:41:38.489493 ==
8967 11:41:38.492351 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 11:41:38.495419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 11:41:38.495885 ==
8970 11:41:38.509755
8971 11:41:38.512849 TX Vref early break, caculate TX vref
8972 11:41:38.516558 TX Vref=16, minBit 5, minWin=21, winSum=375
8973 11:41:38.519706 TX Vref=18, minBit 5, minWin=21, winSum=382
8974 11:41:38.523152 TX Vref=20, minBit 1, minWin=23, winSum=392
8975 11:41:38.525991 TX Vref=22, minBit 0, minWin=24, winSum=401
8976 11:41:38.529905 TX Vref=24, minBit 0, minWin=23, winSum=406
8977 11:41:38.536171 TX Vref=26, minBit 0, minWin=25, winSum=416
8978 11:41:38.539746 TX Vref=28, minBit 0, minWin=23, winSum=414
8979 11:41:38.543133 TX Vref=30, minBit 0, minWin=23, winSum=411
8980 11:41:38.546385 TX Vref=32, minBit 0, minWin=23, winSum=402
8981 11:41:38.549433 TX Vref=34, minBit 0, minWin=23, winSum=395
8982 11:41:38.552586 TX Vref=36, minBit 0, minWin=21, winSum=379
8983 11:41:38.559321 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8984 11:41:38.559889
8985 11:41:38.563143 Final TX Range 0 Vref 26
8986 11:41:38.563709
8987 11:41:38.564088 ==
8988 11:41:38.566371 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 11:41:38.568884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 11:41:38.572626 ==
8991 11:41:38.573194
8992 11:41:38.573565
8993 11:41:38.573912 TX Vref Scan disable
8994 11:41:38.579040 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8995 11:41:38.579604 == TX Byte 0 ==
8996 11:41:38.582117 u2DelayCellOfst[0]=18 cells (5 PI)
8997 11:41:38.585199 u2DelayCellOfst[1]=11 cells (3 PI)
8998 11:41:38.588690 u2DelayCellOfst[2]=0 cells (0 PI)
8999 11:41:38.591973 u2DelayCellOfst[3]=3 cells (1 PI)
9000 11:41:38.595222 u2DelayCellOfst[4]=7 cells (2 PI)
9001 11:41:38.598775 u2DelayCellOfst[5]=18 cells (5 PI)
9002 11:41:38.601532 u2DelayCellOfst[6]=18 cells (5 PI)
9003 11:41:38.604987 u2DelayCellOfst[7]=3 cells (1 PI)
9004 11:41:38.608354 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
9005 11:41:38.611736 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
9006 11:41:38.614948 == TX Byte 1 ==
9007 11:41:38.618206 u2DelayCellOfst[8]=0 cells (0 PI)
9008 11:41:38.622089 u2DelayCellOfst[9]=7 cells (2 PI)
9009 11:41:38.624687 u2DelayCellOfst[10]=14 cells (4 PI)
9010 11:41:38.628370 u2DelayCellOfst[11]=3 cells (1 PI)
9011 11:41:38.631587 u2DelayCellOfst[12]=14 cells (4 PI)
9012 11:41:38.634541 u2DelayCellOfst[13]=18 cells (5 PI)
9013 11:41:38.637662 u2DelayCellOfst[14]=18 cells (5 PI)
9014 11:41:38.641464 u2DelayCellOfst[15]=18 cells (5 PI)
9015 11:41:38.644673 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9016 11:41:38.648331 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9017 11:41:38.651463 DramC Write-DBI on
9018 11:41:38.652028 ==
9019 11:41:38.654789 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 11:41:38.657847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 11:41:38.658421 ==
9022 11:41:38.658800
9023 11:41:38.659149
9024 11:41:38.661021 TX Vref Scan disable
9025 11:41:38.664284 == TX Byte 0 ==
9026 11:41:38.667733 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
9027 11:41:38.668208 == TX Byte 1 ==
9028 11:41:38.674848 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9029 11:41:38.675425 DramC Write-DBI off
9030 11:41:38.675804
9031 11:41:38.676152 [DATLAT]
9032 11:41:38.677467 Freq=1600, CH1 RK1
9033 11:41:38.677937
9034 11:41:38.680665 DATLAT Default: 0xf
9035 11:41:38.681203 0, 0xFFFF, sum = 0
9036 11:41:38.683717 1, 0xFFFF, sum = 0
9037 11:41:38.684195 2, 0xFFFF, sum = 0
9038 11:41:38.687358 3, 0xFFFF, sum = 0
9039 11:41:38.687983 4, 0xFFFF, sum = 0
9040 11:41:38.690493 5, 0xFFFF, sum = 0
9041 11:41:38.690973 6, 0xFFFF, sum = 0
9042 11:41:38.694194 7, 0xFFFF, sum = 0
9043 11:41:38.694669 8, 0xFFFF, sum = 0
9044 11:41:38.697425 9, 0xFFFF, sum = 0
9045 11:41:38.697902 10, 0xFFFF, sum = 0
9046 11:41:38.700698 11, 0xFFFF, sum = 0
9047 11:41:38.701176 12, 0xFFFF, sum = 0
9048 11:41:38.704092 13, 0xFFFF, sum = 0
9049 11:41:38.704728 14, 0x0, sum = 1
9050 11:41:38.707005 15, 0x0, sum = 2
9051 11:41:38.707482 16, 0x0, sum = 3
9052 11:41:38.710614 17, 0x0, sum = 4
9053 11:41:38.711187 best_step = 15
9054 11:41:38.711566
9055 11:41:38.711915 ==
9056 11:41:38.714220 Dram Type= 6, Freq= 0, CH_1, rank 1
9057 11:41:38.720299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9058 11:41:38.721118 ==
9059 11:41:38.721513 RX Vref Scan: 0
9060 11:41:38.721870
9061 11:41:38.723858 RX Vref 0 -> 0, step: 1
9062 11:41:38.724329
9063 11:41:38.726991 RX Delay 11 -> 252, step: 4
9064 11:41:38.730149 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9065 11:41:38.733624 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9066 11:41:38.740513 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9067 11:41:38.743427 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9068 11:41:38.747213 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9069 11:41:38.750557 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9070 11:41:38.752966 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9071 11:41:38.760285 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9072 11:41:38.763277 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9073 11:41:38.766462 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9074 11:41:38.770274 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9075 11:41:38.772964 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9076 11:41:38.779433 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9077 11:41:38.783279 iDelay=203, Bit 13, Center 134 (83 ~ 186) 104
9078 11:41:38.785916 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9079 11:41:38.789667 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9080 11:41:38.790137 ==
9081 11:41:38.793101 Dram Type= 6, Freq= 0, CH_1, rank 1
9082 11:41:38.799734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9083 11:41:38.800204 ==
9084 11:41:38.800624 DQS Delay:
9085 11:41:38.802704 DQS0 = 0, DQS1 = 0
9086 11:41:38.803170 DQM Delay:
9087 11:41:38.805940 DQM0 = 134, DQM1 = 127
9088 11:41:38.806483 DQ Delay:
9089 11:41:38.809135 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9090 11:41:38.812904 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9091 11:41:38.816283 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9092 11:41:38.819346 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9093 11:41:38.819815
9094 11:41:38.820184
9095 11:41:38.820628
9096 11:41:38.822713 [DramC_TX_OE_Calibration] TA2
9097 11:41:38.825776 Original DQ_B0 (3 6) =30, OEN = 27
9098 11:41:38.829630 Original DQ_B1 (3 6) =30, OEN = 27
9099 11:41:38.832486 24, 0x0, End_B0=24 End_B1=24
9100 11:41:38.835981 25, 0x0, End_B0=25 End_B1=25
9101 11:41:38.836581 26, 0x0, End_B0=26 End_B1=26
9102 11:41:38.839235 27, 0x0, End_B0=27 End_B1=27
9103 11:41:38.842138 28, 0x0, End_B0=28 End_B1=28
9104 11:41:38.846110 29, 0x0, End_B0=29 End_B1=29
9105 11:41:38.849154 30, 0x0, End_B0=30 End_B1=30
9106 11:41:38.849722 31, 0x4141, End_B0=30 End_B1=30
9107 11:41:38.852181 Byte0 end_step=30 best_step=27
9108 11:41:38.855958 Byte1 end_step=30 best_step=27
9109 11:41:38.859405 Byte0 TX OE(2T, 0.5T) = (3, 3)
9110 11:41:38.862739 Byte1 TX OE(2T, 0.5T) = (3, 3)
9111 11:41:38.863300
9112 11:41:38.863672
9113 11:41:38.868848 [DQSOSCAuto] RK1, (LSB)MR18= 0x906, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
9114 11:41:38.871952 CH1 RK1: MR19=303, MR18=906
9115 11:41:38.878603 CH1_RK1: MR19=0x303, MR18=0x906, DQSOSC=405, MR23=63, INC=22, DEC=15
9116 11:41:38.881998 [RxdqsGatingPostProcess] freq 1600
9117 11:41:38.888360 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9118 11:41:38.888919 best DQS0 dly(2T, 0.5T) = (1, 1)
9119 11:41:38.892006 best DQS1 dly(2T, 0.5T) = (1, 1)
9120 11:41:38.895576 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9121 11:41:38.898317 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9122 11:41:38.901407 best DQS0 dly(2T, 0.5T) = (1, 1)
9123 11:41:38.905062 best DQS1 dly(2T, 0.5T) = (1, 1)
9124 11:41:38.908081 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9125 11:41:38.911680 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9126 11:41:38.914592 Pre-setting of DQS Precalculation
9127 11:41:38.918654 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9128 11:41:38.928120 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9129 11:41:38.934742 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 11:41:38.935314
9131 11:41:38.935689
9132 11:41:38.938094 [Calibration Summary] 3200 Mbps
9133 11:41:38.938560 CH 0, Rank 0
9134 11:41:38.941510 SW Impedance : PASS
9135 11:41:38.942094 DUTY Scan : NO K
9136 11:41:38.944607 ZQ Calibration : PASS
9137 11:41:38.948108 Jitter Meter : NO K
9138 11:41:38.948712 CBT Training : PASS
9139 11:41:38.951033 Write leveling : PASS
9140 11:41:38.954469 RX DQS gating : PASS
9141 11:41:38.955040 RX DQ/DQS(RDDQC) : PASS
9142 11:41:38.957803 TX DQ/DQS : PASS
9143 11:41:38.960665 RX DATLAT : PASS
9144 11:41:38.961138 RX DQ/DQS(Engine): PASS
9145 11:41:38.964180 TX OE : PASS
9146 11:41:38.964683 All Pass.
9147 11:41:38.965065
9148 11:41:38.967441 CH 0, Rank 1
9149 11:41:38.968013 SW Impedance : PASS
9150 11:41:38.971300 DUTY Scan : NO K
9151 11:41:38.974452 ZQ Calibration : PASS
9152 11:41:38.974923 Jitter Meter : NO K
9153 11:41:38.976971 CBT Training : PASS
9154 11:41:38.980482 Write leveling : PASS
9155 11:41:38.980994 RX DQS gating : PASS
9156 11:41:38.983864 RX DQ/DQS(RDDQC) : PASS
9157 11:41:38.987651 TX DQ/DQS : PASS
9158 11:41:38.988148 RX DATLAT : PASS
9159 11:41:38.990990 RX DQ/DQS(Engine): PASS
9160 11:41:38.994075 TX OE : PASS
9161 11:41:38.994596 All Pass.
9162 11:41:38.994980
9163 11:41:38.995328 CH 1, Rank 0
9164 11:41:38.997810 SW Impedance : PASS
9165 11:41:39.000695 DUTY Scan : NO K
9166 11:41:39.001167 ZQ Calibration : PASS
9167 11:41:39.004130 Jitter Meter : NO K
9168 11:41:39.007342 CBT Training : PASS
9169 11:41:39.007812 Write leveling : PASS
9170 11:41:39.010312 RX DQS gating : PASS
9171 11:41:39.010783 RX DQ/DQS(RDDQC) : PASS
9172 11:41:39.013986 TX DQ/DQS : PASS
9173 11:41:39.017009 RX DATLAT : PASS
9174 11:41:39.017486 RX DQ/DQS(Engine): PASS
9175 11:41:39.020382 TX OE : PASS
9176 11:41:39.020902 All Pass.
9177 11:41:39.021278
9178 11:41:39.023733 CH 1, Rank 1
9179 11:41:39.024298 SW Impedance : PASS
9180 11:41:39.026956 DUTY Scan : NO K
9181 11:41:39.030151 ZQ Calibration : PASS
9182 11:41:39.030720 Jitter Meter : NO K
9183 11:41:39.033420 CBT Training : PASS
9184 11:41:39.036767 Write leveling : PASS
9185 11:41:39.037242 RX DQS gating : PASS
9186 11:41:39.040432 RX DQ/DQS(RDDQC) : PASS
9187 11:41:39.043162 TX DQ/DQS : PASS
9188 11:41:39.043640 RX DATLAT : PASS
9189 11:41:39.047441 RX DQ/DQS(Engine): PASS
9190 11:41:39.050497 TX OE : PASS
9191 11:41:39.051068 All Pass.
9192 11:41:39.051443
9193 11:41:39.053817 DramC Write-DBI on
9194 11:41:39.054381 PER_BANK_REFRESH: Hybrid Mode
9195 11:41:39.057361 TX_TRACKING: ON
9196 11:41:39.063126 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9197 11:41:39.073299 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9198 11:41:39.079577 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9199 11:41:39.083076 [FAST_K] Save calibration result to emmc
9200 11:41:39.086548 sync common calibartion params.
9201 11:41:39.089631 sync cbt_mode0:1, 1:1
9202 11:41:39.090209 dram_init: ddr_geometry: 2
9203 11:41:39.093072 dram_init: ddr_geometry: 2
9204 11:41:39.096695 dram_init: ddr_geometry: 2
9205 11:41:39.099706 0:dram_rank_size:100000000
9206 11:41:39.100190 1:dram_rank_size:100000000
9207 11:41:39.106413 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9208 11:41:39.109240 DFS_SHUFFLE_HW_MODE: ON
9209 11:41:39.112895 dramc_set_vcore_voltage set vcore to 725000
9210 11:41:39.113431 Read voltage for 1600, 0
9211 11:41:39.115726 Vio18 = 0
9212 11:41:39.116201 Vcore = 725000
9213 11:41:39.116760 Vdram = 0
9214 11:41:39.119385 Vddq = 0
9215 11:41:39.119858 Vmddr = 0
9216 11:41:39.122846 switch to 3200 Mbps bootup
9217 11:41:39.123419 [DramcRunTimeConfig]
9218 11:41:39.125875 PHYPLL
9219 11:41:39.126361 DPM_CONTROL_AFTERK: ON
9220 11:41:39.129154 PER_BANK_REFRESH: ON
9221 11:41:39.132624 REFRESH_OVERHEAD_REDUCTION: ON
9222 11:41:39.133205 CMD_PICG_NEW_MODE: OFF
9223 11:41:39.135878 XRTWTW_NEW_MODE: ON
9224 11:41:39.136448 XRTRTR_NEW_MODE: ON
9225 11:41:39.139484 TX_TRACKING: ON
9226 11:41:39.140092 RDSEL_TRACKING: OFF
9227 11:41:39.142280 DQS Precalculation for DVFS: ON
9228 11:41:39.145388 RX_TRACKING: OFF
9229 11:41:39.146023 HW_GATING DBG: ON
9230 11:41:39.149318 ZQCS_ENABLE_LP4: ON
9231 11:41:39.149827 RX_PICG_NEW_MODE: ON
9232 11:41:39.151946 TX_PICG_NEW_MODE: ON
9233 11:41:39.152424 ENABLE_RX_DCM_DPHY: ON
9234 11:41:39.155900 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9235 11:41:39.159200 DUMMY_READ_FOR_TRACKING: OFF
9236 11:41:39.162838 !!! SPM_CONTROL_AFTERK: OFF
9237 11:41:39.165246 !!! SPM could not control APHY
9238 11:41:39.165727 IMPEDANCE_TRACKING: ON
9239 11:41:39.168649 TEMP_SENSOR: ON
9240 11:41:39.169124 HW_SAVE_FOR_SR: OFF
9241 11:41:39.172434 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9242 11:41:39.175400 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9243 11:41:39.179019 Read ODT Tracking: ON
9244 11:41:39.182271 Refresh Rate DeBounce: ON
9245 11:41:39.182936 DFS_NO_QUEUE_FLUSH: ON
9246 11:41:39.184953 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9247 11:41:39.188269 ENABLE_DFS_RUNTIME_MRW: OFF
9248 11:41:39.191529 DDR_RESERVE_NEW_MODE: ON
9249 11:41:39.192080 MR_CBT_SWITCH_FREQ: ON
9250 11:41:39.194879 =========================
9251 11:41:39.213947 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9252 11:41:39.217493 dram_init: ddr_geometry: 2
9253 11:41:39.235655 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9254 11:41:39.238706 dram_init: dram init end (result: 0)
9255 11:41:39.245265 DRAM-K: Full calibration passed in 24603 msecs
9256 11:41:39.248506 MRC: failed to locate region type 0.
9257 11:41:39.248650 DRAM rank0 size:0x100000000,
9258 11:41:39.251636 DRAM rank1 size=0x100000000
9259 11:41:39.261921 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9260 11:41:39.268301 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9261 11:41:39.277943 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9262 11:41:39.284958 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9263 11:41:39.285261 DRAM rank0 size:0x100000000,
9264 11:41:39.287947 DRAM rank1 size=0x100000000
9265 11:41:39.288189 CBMEM:
9266 11:41:39.291551 IMD: root @ 0xfffff000 254 entries.
9267 11:41:39.294986 IMD: root @ 0xffffec00 62 entries.
9268 11:41:39.301457 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9269 11:41:39.304712 WARNING: RO_VPD is uninitialized or empty.
9270 11:41:39.308634 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9271 11:41:39.315834 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9272 11:41:39.328401 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9273 11:41:39.339946 BS: romstage times (exec / console): total (unknown) / 24097 ms
9274 11:41:39.340585
9275 11:41:39.341118
9276 11:41:39.349864 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9277 11:41:39.353272 ARM64: Exception handlers installed.
9278 11:41:39.356644 ARM64: Testing exception
9279 11:41:39.359876 ARM64: Done test exception
9280 11:41:39.360446 Enumerating buses...
9281 11:41:39.363025 Show all devs... Before device enumeration.
9282 11:41:39.365955 Root Device: enabled 1
9283 11:41:39.369853 CPU_CLUSTER: 0: enabled 1
9284 11:41:39.370423 CPU: 00: enabled 1
9285 11:41:39.373081 Compare with tree...
9286 11:41:39.373647 Root Device: enabled 1
9287 11:41:39.376703 CPU_CLUSTER: 0: enabled 1
9288 11:41:39.379464 CPU: 00: enabled 1
9289 11:41:39.379941 Root Device scanning...
9290 11:41:39.383044 scan_static_bus for Root Device
9291 11:41:39.385793 CPU_CLUSTER: 0 enabled
9292 11:41:39.389713 scan_static_bus for Root Device done
9293 11:41:39.393021 scan_bus: bus Root Device finished in 8 msecs
9294 11:41:39.393497 done
9295 11:41:39.399430 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9296 11:41:39.402991 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9297 11:41:39.408953 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9298 11:41:39.412373 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9299 11:41:39.415842 Allocating resources...
9300 11:41:39.419410 Reading resources...
9301 11:41:39.422382 Root Device read_resources bus 0 link: 0
9302 11:41:39.425805 DRAM rank0 size:0x100000000,
9303 11:41:39.426375 DRAM rank1 size=0x100000000
9304 11:41:39.433361 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9305 11:41:39.433929 CPU: 00 missing read_resources
9306 11:41:39.439486 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9307 11:41:39.442765 Root Device read_resources bus 0 link: 0 done
9308 11:41:39.445736 Done reading resources.
9309 11:41:39.448796 Show resources in subtree (Root Device)...After reading.
9310 11:41:39.452059 Root Device child on link 0 CPU_CLUSTER: 0
9311 11:41:39.455653 CPU_CLUSTER: 0 child on link 0 CPU: 00
9312 11:41:39.465000 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9313 11:41:39.465467 CPU: 00
9314 11:41:39.468836 Root Device assign_resources, bus 0 link: 0
9315 11:41:39.471738 CPU_CLUSTER: 0 missing set_resources
9316 11:41:39.478535 Root Device assign_resources, bus 0 link: 0 done
9317 11:41:39.479001 Done setting resources.
9318 11:41:39.484812 Show resources in subtree (Root Device)...After assigning values.
9319 11:41:39.488078 Root Device child on link 0 CPU_CLUSTER: 0
9320 11:41:39.491825 CPU_CLUSTER: 0 child on link 0 CPU: 00
9321 11:41:39.501198 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9322 11:41:39.501620 CPU: 00
9323 11:41:39.505030 Done allocating resources.
9324 11:41:39.511161 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9325 11:41:39.511592 Enabling resources...
9326 11:41:39.514505 done.
9327 11:41:39.517911 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9328 11:41:39.521467 Initializing devices...
9329 11:41:39.521884 Root Device init
9330 11:41:39.524831 init hardware done!
9331 11:41:39.525250 0x00000018: ctrlr->caps
9332 11:41:39.528132 52.000 MHz: ctrlr->f_max
9333 11:41:39.531251 0.400 MHz: ctrlr->f_min
9334 11:41:39.531681 0x40ff8080: ctrlr->voltages
9335 11:41:39.534240 sclk: 390625
9336 11:41:39.534655 Bus Width = 1
9337 11:41:39.537604 sclk: 390625
9338 11:41:39.538023 Bus Width = 1
9339 11:41:39.541695 Early init status = 3
9340 11:41:39.544330 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9341 11:41:39.549390 in-header: 03 fb 00 00 01 00 00 00
9342 11:41:39.552924 in-data: 01
9343 11:41:39.556202 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9344 11:41:39.560465 in-header: 03 fb 00 00 01 00 00 00
9345 11:41:39.563590 in-data: 01
9346 11:41:39.567333 [SSUSB] Setting up USB HOST controller...
9347 11:41:39.570458 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9348 11:41:39.573696 [SSUSB] phy power-on done.
9349 11:41:39.577176 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9350 11:41:39.583611 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9351 11:41:39.587437 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9352 11:41:39.593578 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9353 11:41:39.600380 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9354 11:41:39.606840 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9355 11:41:39.613697 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9356 11:41:39.620405 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9357 11:41:39.623381 SPM: binary array size = 0x9dc
9358 11:41:39.626869 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9359 11:41:39.633232 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9360 11:41:39.639715 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9361 11:41:39.646180 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9362 11:41:39.649731 configure_display: Starting display init
9363 11:41:39.683883 anx7625_power_on_init: Init interface.
9364 11:41:39.687032 anx7625_disable_pd_protocol: Disabled PD feature.
9365 11:41:39.690210 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9366 11:41:39.718674 anx7625_start_dp_work: Secure OCM version=00
9367 11:41:39.721783 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9368 11:41:39.736370 sp_tx_get_edid_block: EDID Block = 1
9369 11:41:39.838372 Extracted contents:
9370 11:41:39.841879 header: 00 ff ff ff ff ff ff 00
9371 11:41:39.845052 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9372 11:41:39.848793 version: 01 04
9373 11:41:39.851630 basic params: 95 1f 11 78 0a
9374 11:41:39.855137 chroma info: 76 90 94 55 54 90 27 21 50 54
9375 11:41:39.858782 established: 00 00 00
9376 11:41:39.864772 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9377 11:41:39.868446 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9378 11:41:39.875161 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 11:41:39.881338 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9380 11:41:39.887883 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9381 11:41:39.891300 extensions: 00
9382 11:41:39.891382 checksum: fb
9383 11:41:39.891448
9384 11:41:39.897762 Manufacturer: IVO Model 57d Serial Number 0
9385 11:41:39.897844 Made week 0 of 2020
9386 11:41:39.900993 EDID version: 1.4
9387 11:41:39.901074 Digital display
9388 11:41:39.904366 6 bits per primary color channel
9389 11:41:39.904449 DisplayPort interface
9390 11:41:39.908194 Maximum image size: 31 cm x 17 cm
9391 11:41:39.910990 Gamma: 220%
9392 11:41:39.911071 Check DPMS levels
9393 11:41:39.914272 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9394 11:41:39.921063 First detailed timing is preferred timing
9395 11:41:39.921146 Established timings supported:
9396 11:41:39.924443 Standard timings supported:
9397 11:41:39.927617 Detailed timings
9398 11:41:39.930827 Hex of detail: 383680a07038204018303c0035ae10000019
9399 11:41:39.937580 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9400 11:41:39.940844 0780 0798 07c8 0820 hborder 0
9401 11:41:39.944370 0438 043b 0447 0458 vborder 0
9402 11:41:39.947675 -hsync -vsync
9403 11:41:39.947756 Did detailed timing
9404 11:41:39.954100 Hex of detail: 000000000000000000000000000000000000
9405 11:41:39.957675 Manufacturer-specified data, tag 0
9406 11:41:39.960422 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9407 11:41:39.964380 ASCII string: InfoVision
9408 11:41:39.967685 Hex of detail: 000000fe00523134304e574635205248200a
9409 11:41:39.970239 ASCII string: R140NWF5 RH
9410 11:41:39.970320 Checksum
9411 11:41:39.973787 Checksum: 0xfb (valid)
9412 11:41:39.976818 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9413 11:41:39.980827 DSI data_rate: 832800000 bps
9414 11:41:39.986985 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9415 11:41:39.990239 anx7625_parse_edid: pixelclock(138800).
9416 11:41:39.993891 hactive(1920), hsync(48), hfp(24), hbp(88)
9417 11:41:39.996913 vactive(1080), vsync(12), vfp(3), vbp(17)
9418 11:41:40.000049 anx7625_dsi_config: config dsi.
9419 11:41:40.007054 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9420 11:41:40.020871 anx7625_dsi_config: success to config DSI
9421 11:41:40.024211 anx7625_dp_start: MIPI phy setup OK.
9422 11:41:40.027092 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9423 11:41:40.030784 mtk_ddp_mode_set invalid vrefresh 60
9424 11:41:40.034273 main_disp_path_setup
9425 11:41:40.034366 ovl_layer_smi_id_en
9426 11:41:40.037091 ovl_layer_smi_id_en
9427 11:41:40.037192 ccorr_config
9428 11:41:40.037272 aal_config
9429 11:41:40.040389 gamma_config
9430 11:41:40.040497 postmask_config
9431 11:41:40.043562 dither_config
9432 11:41:40.047046 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9433 11:41:40.053728 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9434 11:41:40.056664 Root Device init finished in 532 msecs
9435 11:41:40.060408 CPU_CLUSTER: 0 init
9436 11:41:40.066810 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9437 11:41:40.073716 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9438 11:41:40.073811 APU_MBOX 0x190000b0 = 0x10001
9439 11:41:40.076830 APU_MBOX 0x190001b0 = 0x10001
9440 11:41:40.080064 APU_MBOX 0x190005b0 = 0x10001
9441 11:41:40.083513 APU_MBOX 0x190006b0 = 0x10001
9442 11:41:40.090058 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9443 11:41:40.099851 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9444 11:41:40.111967 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9445 11:41:40.118608 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9446 11:41:40.130359 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9447 11:41:40.139434 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9448 11:41:40.142410 CPU_CLUSTER: 0 init finished in 81 msecs
9449 11:41:40.146338 Devices initialized
9450 11:41:40.149796 Show all devs... After init.
9451 11:41:40.149878 Root Device: enabled 1
9452 11:41:40.152810 CPU_CLUSTER: 0: enabled 1
9453 11:41:40.155701 CPU: 00: enabled 1
9454 11:41:40.158946 BS: BS_DEV_INIT run times (exec / console): 209 / 428 ms
9455 11:41:40.163137 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9456 11:41:40.166039 ELOG: NV offset 0x57f000 size 0x1000
9457 11:41:40.172716 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9458 11:41:40.179696 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9459 11:41:40.182513 ELOG: Event(17) added with size 13 at 2023-06-15 11:41:40 UTC
9460 11:41:40.189065 out: cmd=0x121: 03 db 21 01 00 00 00 00
9461 11:41:40.192042 in-header: 03 e5 00 00 2c 00 00 00
9462 11:41:40.201793 in-data: 7a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9463 11:41:40.208562 ELOG: Event(A1) added with size 10 at 2023-06-15 11:41:40 UTC
9464 11:41:40.215025 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9465 11:41:40.221677 ELOG: Event(A0) added with size 9 at 2023-06-15 11:41:40 UTC
9466 11:41:40.224827 elog_add_boot_reason: Logged dev mode boot
9467 11:41:40.232136 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9468 11:41:40.232218 Finalize devices...
9469 11:41:40.235031 Devices finalized
9470 11:41:40.238123 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9471 11:41:40.241577 Writing coreboot table at 0xffe64000
9472 11:41:40.244941 0. 000000000010a000-0000000000113fff: RAMSTAGE
9473 11:41:40.251433 1. 0000000040000000-00000000400fffff: RAM
9474 11:41:40.254866 2. 0000000040100000-000000004032afff: RAMSTAGE
9475 11:41:40.257945 3. 000000004032b000-00000000545fffff: RAM
9476 11:41:40.261800 4. 0000000054600000-000000005465ffff: BL31
9477 11:41:40.264772 5. 0000000054660000-00000000ffe63fff: RAM
9478 11:41:40.271348 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9479 11:41:40.275321 7. 0000000100000000-000000023fffffff: RAM
9480 11:41:40.277864 Passing 5 GPIOs to payload:
9481 11:41:40.281506 NAME | PORT | POLARITY | VALUE
9482 11:41:40.287774 EC in RW | 0x000000aa | low | undefined
9483 11:41:40.291137 EC interrupt | 0x00000005 | low | undefined
9484 11:41:40.294588 TPM interrupt | 0x000000ab | high | undefined
9485 11:41:40.301104 SD card detect | 0x00000011 | high | undefined
9486 11:41:40.304050 speaker enable | 0x00000093 | high | undefined
9487 11:41:40.307877 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9488 11:41:40.310872 in-header: 03 f9 00 00 02 00 00 00
9489 11:41:40.313949 in-data: 02 00
9490 11:41:40.317231 ADC[4]: Raw value=903031 ID=7
9491 11:41:40.320890 ADC[3]: Raw value=213282 ID=1
9492 11:41:40.321025 RAM Code: 0x71
9493 11:41:40.324165 ADC[6]: Raw value=75036 ID=0
9494 11:41:40.327498 ADC[5]: Raw value=213652 ID=1
9495 11:41:40.327598 SKU Code: 0x1
9496 11:41:40.333783 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169
9497 11:41:40.333865 coreboot table: 964 bytes.
9498 11:41:40.337320 IMD ROOT 0. 0xfffff000 0x00001000
9499 11:41:40.340452 IMD SMALL 1. 0xffffe000 0x00001000
9500 11:41:40.343714 RO MCACHE 2. 0xffffc000 0x00001104
9501 11:41:40.347276 CONSOLE 3. 0xfff7c000 0x00080000
9502 11:41:40.350680 FMAP 4. 0xfff7b000 0x00000452
9503 11:41:40.354004 TIME STAMP 5. 0xfff7a000 0x00000910
9504 11:41:40.357178 VBOOT WORK 6. 0xfff66000 0x00014000
9505 11:41:40.360789 RAMOOPS 7. 0xffe66000 0x00100000
9506 11:41:40.364160 COREBOOT 8. 0xffe64000 0x00002000
9507 11:41:40.367326 IMD small region:
9508 11:41:40.370155 IMD ROOT 0. 0xffffec00 0x00000400
9509 11:41:40.373514 VPD 1. 0xffffeba0 0x0000004c
9510 11:41:40.377032 MMC STATUS 2. 0xffffeb80 0x00000004
9511 11:41:40.383856 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9512 11:41:40.383939 Probing TPM: done!
9513 11:41:40.390301 Connected to device vid:did:rid of 1ae0:0028:00
9514 11:41:40.397203 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9515 11:41:40.400208 Initialized TPM device CR50 revision 0
9516 11:41:40.403750 Checking cr50 for pending updates
9517 11:41:40.408964 Reading cr50 TPM mode
9518 11:41:40.417716 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9519 11:41:40.424015 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9520 11:41:40.464426 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9521 11:41:40.467912 Checking segment from ROM address 0x40100000
9522 11:41:40.471320 Checking segment from ROM address 0x4010001c
9523 11:41:40.477898 Loading segment from ROM address 0x40100000
9524 11:41:40.478201 code (compression=0)
9525 11:41:40.487781 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9526 11:41:40.494465 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9527 11:41:40.494896 it's not compressed!
9528 11:41:40.501102 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9529 11:41:40.507888 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9530 11:41:40.524966 Loading segment from ROM address 0x4010001c
9531 11:41:40.525391 Entry Point 0x80000000
9532 11:41:40.528557 Loaded segments
9533 11:41:40.531552 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9534 11:41:40.538096 Jumping to boot code at 0x80000000(0xffe64000)
9535 11:41:40.544798 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9536 11:41:40.551598 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9537 11:41:40.559676 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9538 11:41:40.562708 Checking segment from ROM address 0x40100000
9539 11:41:40.566518 Checking segment from ROM address 0x4010001c
9540 11:41:40.572675 Loading segment from ROM address 0x40100000
9541 11:41:40.573204 code (compression=1)
9542 11:41:40.579686 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9543 11:41:40.588986 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9544 11:41:40.589528 using LZMA
9545 11:41:40.597737 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9546 11:41:40.604480 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9547 11:41:40.607691 Loading segment from ROM address 0x4010001c
9548 11:41:40.608122 Entry Point 0x54601000
9549 11:41:40.611345 Loaded segments
9550 11:41:40.614380 NOTICE: MT8192 bl31_setup
9551 11:41:40.621878 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9552 11:41:40.624589 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9553 11:41:40.628281 WARNING: region 0:
9554 11:41:40.631330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 11:41:40.631753 WARNING: region 1:
9556 11:41:40.638294 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9557 11:41:40.641430 WARNING: region 2:
9558 11:41:40.645127 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9559 11:41:40.648288 WARNING: region 3:
9560 11:41:40.651454 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9561 11:41:40.654145 WARNING: region 4:
9562 11:41:40.660804 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9563 11:41:40.660894 WARNING: region 5:
9564 11:41:40.664199 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9565 11:41:40.667643 WARNING: region 6:
9566 11:41:40.671138 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9567 11:41:40.674208 WARNING: region 7:
9568 11:41:40.677793 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9569 11:41:40.684366 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9570 11:41:40.687588 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9571 11:41:40.690964 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9572 11:41:40.697939 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9573 11:41:40.700500 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9574 11:41:40.704116 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9575 11:41:40.710782 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9576 11:41:40.714006 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9577 11:41:40.720773 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9578 11:41:40.724697 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9579 11:41:40.727902 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9580 11:41:40.733932 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9581 11:41:40.737748 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9582 11:41:40.740870 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9583 11:41:40.747591 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9584 11:41:40.750893 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9585 11:41:40.757328 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9586 11:41:40.760919 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9587 11:41:40.764394 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9588 11:41:40.771235 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9589 11:41:40.774284 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9590 11:41:40.780770 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9591 11:41:40.784150 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9592 11:41:40.787299 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9593 11:41:40.794145 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9594 11:41:40.797254 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9595 11:41:40.804029 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9596 11:41:40.806964 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9597 11:41:40.810669 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9598 11:41:40.816987 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9599 11:41:40.820418 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9600 11:41:40.827610 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9601 11:41:40.830323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9602 11:41:40.833497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9603 11:41:40.836991 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9604 11:41:40.843923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9605 11:41:40.846694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9606 11:41:40.849985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9607 11:41:40.853679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9608 11:41:40.859967 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9609 11:41:40.863685 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9610 11:41:40.866990 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9611 11:41:40.870250 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9612 11:41:40.876775 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9613 11:41:40.880169 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9614 11:41:40.883466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9615 11:41:40.886725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9616 11:41:40.893601 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9617 11:41:40.896968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9618 11:41:40.903520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9619 11:41:40.906340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9620 11:41:40.910123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9621 11:41:40.916677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9622 11:41:40.920057 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9623 11:41:40.926426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9624 11:41:40.929925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9625 11:41:40.936853 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9626 11:41:40.939726 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9627 11:41:40.943068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9628 11:41:40.949562 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9629 11:41:40.953108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9630 11:41:40.959474 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9631 11:41:40.963188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9632 11:41:40.969433 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9633 11:41:40.972933 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9634 11:41:40.979588 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9635 11:41:40.982950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9636 11:41:40.986101 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9637 11:41:40.992858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9638 11:41:40.996480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9639 11:41:41.002781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9640 11:41:41.006141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9641 11:41:41.012925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9642 11:41:41.015842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9643 11:41:41.022458 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9644 11:41:41.026329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9645 11:41:41.029455 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9646 11:41:41.036254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9647 11:41:41.039072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9648 11:41:41.045474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9649 11:41:41.048810 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9650 11:41:41.055754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9651 11:41:41.058924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9652 11:41:41.065592 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9653 11:41:41.068964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9654 11:41:41.072227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9655 11:41:41.078944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9656 11:41:41.081964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9657 11:41:41.088476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9658 11:41:41.092428 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9659 11:41:41.098655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9660 11:41:41.102168 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9661 11:41:41.108450 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9662 11:41:41.111957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9663 11:41:41.115765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9664 11:41:41.121904 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9665 11:41:41.124980 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9666 11:41:41.128615 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9667 11:41:41.134956 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9668 11:41:41.138817 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9669 11:41:41.141837 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9670 11:41:41.148364 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9671 11:41:41.151723 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9672 11:41:41.155007 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9673 11:41:41.162243 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9674 11:41:41.165052 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9675 11:41:41.171912 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9676 11:41:41.175302 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9677 11:41:41.178775 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9678 11:41:41.185159 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9679 11:41:41.188292 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9680 11:41:41.194984 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9681 11:41:41.198330 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9682 11:41:41.201615 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9683 11:41:41.208444 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9684 11:41:41.211877 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9685 11:41:41.214682 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9686 11:41:41.221793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9687 11:41:41.225089 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9688 11:41:41.228374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9689 11:41:41.231809 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9690 11:41:41.238367 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9691 11:41:41.241788 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9692 11:41:41.245116 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9693 11:41:41.252018 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9694 11:41:41.255543 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9695 11:41:41.258229 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9696 11:41:41.264870 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9697 11:41:41.268500 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9698 11:41:41.274940 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9699 11:41:41.278015 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9700 11:41:41.281379 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9701 11:41:41.287910 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9702 11:41:41.291232 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9703 11:41:41.297723 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9704 11:41:41.301348 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9705 11:41:41.304546 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9706 11:41:41.310690 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9707 11:41:41.314527 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9708 11:41:41.320930 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9709 11:41:41.324291 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9710 11:41:41.327888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9711 11:41:41.333860 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9712 11:41:41.337009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9713 11:41:41.343661 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9714 11:41:41.347435 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9715 11:41:41.350465 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9716 11:41:41.357147 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9717 11:41:41.360355 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9718 11:41:41.367111 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9719 11:41:41.370589 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9720 11:41:41.373507 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9721 11:41:41.379953 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9722 11:41:41.383341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9723 11:41:41.390018 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9724 11:41:41.393113 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9725 11:41:41.396560 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9726 11:41:41.403147 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9727 11:41:41.406988 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9728 11:41:41.413181 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9729 11:41:41.416502 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9730 11:41:41.419556 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9731 11:41:41.426264 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9732 11:41:41.429780 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9733 11:41:41.436157 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9734 11:41:41.439533 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9735 11:41:41.442777 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9736 11:41:41.449190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9737 11:41:41.453008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9738 11:41:41.459321 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9739 11:41:41.462847 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9740 11:41:41.466260 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9741 11:41:41.472324 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9742 11:41:41.475514 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9743 11:41:41.482710 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9744 11:41:41.486381 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9745 11:41:41.488764 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9746 11:41:41.495527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9747 11:41:41.499212 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9748 11:41:41.505862 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9749 11:41:41.508891 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9750 11:41:41.512175 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9751 11:41:41.518644 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9752 11:41:41.522261 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9753 11:41:41.528626 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9754 11:41:41.531973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9755 11:41:41.535080 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9756 11:41:41.541740 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9757 11:41:41.545138 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9758 11:41:41.551880 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9759 11:41:41.554795 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9760 11:41:41.561760 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9761 11:41:41.564493 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9762 11:41:41.567968 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9763 11:41:41.575101 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9764 11:41:41.577797 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9765 11:41:41.584359 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9766 11:41:41.587840 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9767 11:41:41.594743 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9768 11:41:41.598179 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9769 11:41:41.601039 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9770 11:41:41.607895 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9771 11:41:41.611195 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9772 11:41:41.617869 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9773 11:41:41.621367 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9774 11:41:41.627296 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9775 11:41:41.631081 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9776 11:41:41.634136 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9777 11:41:41.641249 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9778 11:41:41.644014 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9779 11:41:41.650628 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9780 11:41:41.654104 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9781 11:41:41.657169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9782 11:41:41.663922 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9783 11:41:41.667147 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9784 11:41:41.674025 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9785 11:41:41.677211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9786 11:41:41.683306 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9787 11:41:41.686623 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9788 11:41:41.690225 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9789 11:41:41.697145 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9790 11:41:41.699932 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9791 11:41:41.706897 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9792 11:41:41.710141 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9793 11:41:41.716438 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9794 11:41:41.720127 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9795 11:41:41.723430 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9796 11:41:41.730389 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9797 11:41:41.733106 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9798 11:41:41.736993 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9799 11:41:41.743385 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9800 11:41:41.746482 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9801 11:41:41.749761 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9802 11:41:41.752858 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9803 11:41:41.759697 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9804 11:41:41.762836 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9805 11:41:41.769486 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9806 11:41:41.772648 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9807 11:41:41.775988 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9808 11:41:41.783061 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9809 11:41:41.785741 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9810 11:41:41.789159 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9811 11:41:41.795959 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9812 11:41:41.799188 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9813 11:41:41.805905 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9814 11:41:41.809206 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9815 11:41:41.812405 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9816 11:41:41.819043 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9817 11:41:41.822202 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9818 11:41:41.825894 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9819 11:41:41.832388 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9820 11:41:41.835431 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9821 11:41:41.842007 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9822 11:41:41.845841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9823 11:41:41.848917 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9824 11:41:41.854959 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9825 11:41:41.858439 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9826 11:41:41.861938 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9827 11:41:41.868509 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9828 11:41:41.872181 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9829 11:41:41.878526 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9830 11:41:41.881915 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9831 11:41:41.885317 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9832 11:41:41.891762 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9833 11:41:41.895043 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9834 11:41:41.898404 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9835 11:41:41.905019 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9836 11:41:41.908267 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9837 11:41:41.911159 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9838 11:41:41.918345 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9839 11:41:41.921308 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9840 11:41:41.924436 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9841 11:41:41.928223 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9842 11:41:41.931091 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9843 11:41:41.938014 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9844 11:41:41.941141 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9845 11:41:41.944474 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9846 11:41:41.951501 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9847 11:41:41.954911 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9848 11:41:41.957506 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9849 11:41:41.960717 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9850 11:41:41.967778 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9851 11:41:41.971310 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9852 11:41:41.977535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9853 11:41:41.980623 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9854 11:41:41.984227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9855 11:41:41.990913 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9856 11:41:41.993636 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9857 11:41:42.000798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9858 11:41:42.003772 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9859 11:41:42.010387 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9860 11:41:42.013673 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9861 11:41:42.016834 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9862 11:41:42.023831 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9863 11:41:42.026597 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9864 11:41:42.033543 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9865 11:41:42.037014 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9866 11:41:42.040153 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9867 11:41:42.047123 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9868 11:41:42.050210 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9869 11:41:42.056577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9870 11:41:42.060010 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9871 11:41:42.066908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9872 11:41:42.070186 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9873 11:41:42.073365 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9874 11:41:42.079766 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9875 11:41:42.083497 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9876 11:41:42.089389 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9877 11:41:42.092672 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9878 11:41:42.096248 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9879 11:41:42.102830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9880 11:41:42.106138 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9881 11:41:42.112673 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9882 11:41:42.115967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9883 11:41:42.119204 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9884 11:41:42.125910 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9885 11:41:42.129164 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9886 11:41:42.135826 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9887 11:41:42.139222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9888 11:41:42.145627 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9889 11:41:42.149382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9890 11:41:42.153225 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9891 11:41:42.158799 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9892 11:41:42.162662 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9893 11:41:42.168576 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9894 11:41:42.172011 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9895 11:41:42.178865 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9896 11:41:42.182274 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9897 11:41:42.185549 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9898 11:41:42.191694 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9899 11:41:42.195222 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9900 11:41:42.201998 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9901 11:41:42.205080 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9902 11:41:42.211842 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9903 11:41:42.215000 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9904 11:41:42.218318 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9905 11:41:42.224618 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9906 11:41:42.228005 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9907 11:41:42.234726 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9908 11:41:42.237856 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9909 11:41:42.240997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9910 11:41:42.248133 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9911 11:41:42.251096 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9912 11:41:42.257623 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9913 11:41:42.261373 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9914 11:41:42.263963 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9915 11:41:42.271512 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9916 11:41:42.274120 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9917 11:41:42.281185 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9918 11:41:42.283915 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9919 11:41:42.290811 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9920 11:41:42.294038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9921 11:41:42.297652 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9922 11:41:42.303881 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9923 11:41:42.307162 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9924 11:41:42.313851 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9925 11:41:42.317034 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9926 11:41:42.323579 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9927 11:41:42.326721 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9928 11:41:42.333999 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9929 11:41:42.337017 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9930 11:41:42.340349 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9931 11:41:42.347111 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9932 11:41:42.350324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9933 11:41:42.356300 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9934 11:41:42.360496 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9935 11:41:42.366849 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9936 11:41:42.370379 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9937 11:41:42.376761 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9938 11:41:42.379637 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9939 11:41:42.382914 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9940 11:41:42.390206 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9941 11:41:42.393090 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9942 11:41:42.399769 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9943 11:41:42.403075 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9944 11:41:42.409130 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9945 11:41:42.412504 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9946 11:41:42.415751 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9947 11:41:42.422285 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9948 11:41:42.425582 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9949 11:41:42.432812 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9950 11:41:42.436062 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9951 11:41:42.442542 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9952 11:41:42.445374 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9953 11:41:42.452832 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9954 11:41:42.456299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9955 11:41:42.458869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9956 11:41:42.465478 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9957 11:41:42.469025 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9958 11:41:42.475602 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9959 11:41:42.478696 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9960 11:41:42.485090 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9961 11:41:42.488434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9962 11:41:42.495443 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9963 11:41:42.498367 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9964 11:41:42.501902 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9965 11:41:42.508765 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9966 11:41:42.512164 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9967 11:41:42.518767 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9968 11:41:42.521370 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9969 11:41:42.528297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9970 11:41:42.531413 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9971 11:41:42.534853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9972 11:41:42.541628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9973 11:41:42.544773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9974 11:41:42.551054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9975 11:41:42.554601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9976 11:41:42.560958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9977 11:41:42.564274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9978 11:41:42.571086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9979 11:41:42.574491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9980 11:41:42.581183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9981 11:41:42.584278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9982 11:41:42.591164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9983 11:41:42.594381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9984 11:41:42.600616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9985 11:41:42.604005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9986 11:41:42.610842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9987 11:41:42.614320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9988 11:41:42.620539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9989 11:41:42.624789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9990 11:41:42.630677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9991 11:41:42.634176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9992 11:41:42.640180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9993 11:41:42.643680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9994 11:41:42.650475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9995 11:41:42.653706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9996 11:41:42.660156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9997 11:41:42.663959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9998 11:41:42.669852 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9999 11:41:42.673260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10000 11:41:42.680023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10001 11:41:42.682924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10002 11:41:42.689728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10003 11:41:42.693240 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10004 11:41:42.696426 INFO: [APUAPC] vio 0
10005 11:41:42.699455 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10006 11:41:42.706545 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10007 11:41:42.710054 INFO: [APUAPC] D0_APC_0: 0x400510
10008 11:41:42.710478 INFO: [APUAPC] D0_APC_1: 0x0
10009 11:41:42.712804 INFO: [APUAPC] D0_APC_2: 0x1540
10010 11:41:42.715858 INFO: [APUAPC] D0_APC_3: 0x0
10011 11:41:42.719314 INFO: [APUAPC] D1_APC_0: 0xffffffff
10012 11:41:42.722854 INFO: [APUAPC] D1_APC_1: 0xffffffff
10013 11:41:42.725850 INFO: [APUAPC] D1_APC_2: 0x3fffff
10014 11:41:42.729660 INFO: [APUAPC] D1_APC_3: 0x0
10015 11:41:42.732914 INFO: [APUAPC] D2_APC_0: 0xffffffff
10016 11:41:42.735982 INFO: [APUAPC] D2_APC_1: 0xffffffff
10017 11:41:42.739238 INFO: [APUAPC] D2_APC_2: 0x3fffff
10018 11:41:42.742319 INFO: [APUAPC] D2_APC_3: 0x0
10019 11:41:42.745764 INFO: [APUAPC] D3_APC_0: 0xffffffff
10020 11:41:42.748873 INFO: [APUAPC] D3_APC_1: 0xffffffff
10021 11:41:42.752169 INFO: [APUAPC] D3_APC_2: 0x3fffff
10022 11:41:42.755747 INFO: [APUAPC] D3_APC_3: 0x0
10023 11:41:42.758590 INFO: [APUAPC] D4_APC_0: 0xffffffff
10024 11:41:42.761844 INFO: [APUAPC] D4_APC_1: 0xffffffff
10025 11:41:42.765224 INFO: [APUAPC] D4_APC_2: 0x3fffff
10026 11:41:42.768508 INFO: [APUAPC] D4_APC_3: 0x0
10027 11:41:42.771733 INFO: [APUAPC] D5_APC_0: 0xffffffff
10028 11:41:42.775345 INFO: [APUAPC] D5_APC_1: 0xffffffff
10029 11:41:42.778756 INFO: [APUAPC] D5_APC_2: 0x3fffff
10030 11:41:42.781704 INFO: [APUAPC] D5_APC_3: 0x0
10031 11:41:42.785101 INFO: [APUAPC] D6_APC_0: 0xffffffff
10032 11:41:42.788492 INFO: [APUAPC] D6_APC_1: 0xffffffff
10033 11:41:42.792618 INFO: [APUAPC] D6_APC_2: 0x3fffff
10034 11:41:42.795225 INFO: [APUAPC] D6_APC_3: 0x0
10035 11:41:42.798315 INFO: [APUAPC] D7_APC_0: 0xffffffff
10036 11:41:42.801551 INFO: [APUAPC] D7_APC_1: 0xffffffff
10037 11:41:42.804998 INFO: [APUAPC] D7_APC_2: 0x3fffff
10038 11:41:42.808128 INFO: [APUAPC] D7_APC_3: 0x0
10039 11:41:42.811610 INFO: [APUAPC] D8_APC_0: 0xffffffff
10040 11:41:42.814733 INFO: [APUAPC] D8_APC_1: 0xffffffff
10041 11:41:42.818181 INFO: [APUAPC] D8_APC_2: 0x3fffff
10042 11:41:42.821495 INFO: [APUAPC] D8_APC_3: 0x0
10043 11:41:42.824654 INFO: [APUAPC] D9_APC_0: 0xffffffff
10044 11:41:42.827979 INFO: [APUAPC] D9_APC_1: 0xffffffff
10045 11:41:42.831482 INFO: [APUAPC] D9_APC_2: 0x3fffff
10046 11:41:42.834557 INFO: [APUAPC] D9_APC_3: 0x0
10047 11:41:42.837592 INFO: [APUAPC] D10_APC_0: 0xffffffff
10048 11:41:42.841112 INFO: [APUAPC] D10_APC_1: 0xffffffff
10049 11:41:42.844180 INFO: [APUAPC] D10_APC_2: 0x3fffff
10050 11:41:42.847451 INFO: [APUAPC] D10_APC_3: 0x0
10051 11:41:42.850791 INFO: [APUAPC] D11_APC_0: 0xffffffff
10052 11:41:42.854267 INFO: [APUAPC] D11_APC_1: 0xffffffff
10053 11:41:42.857599 INFO: [APUAPC] D11_APC_2: 0x3fffff
10054 11:41:42.860872 INFO: [APUAPC] D11_APC_3: 0x0
10055 11:41:42.864210 INFO: [APUAPC] D12_APC_0: 0xffffffff
10056 11:41:42.867244 INFO: [APUAPC] D12_APC_1: 0xffffffff
10057 11:41:42.870530 INFO: [APUAPC] D12_APC_2: 0x3fffff
10058 11:41:42.873781 INFO: [APUAPC] D12_APC_3: 0x0
10059 11:41:42.877990 INFO: [APUAPC] D13_APC_0: 0xffffffff
10060 11:41:42.880701 INFO: [APUAPC] D13_APC_1: 0xffffffff
10061 11:41:42.883692 INFO: [APUAPC] D13_APC_2: 0x3fffff
10062 11:41:42.886987 INFO: [APUAPC] D13_APC_3: 0x0
10063 11:41:42.890369 INFO: [APUAPC] D14_APC_0: 0xffffffff
10064 11:41:42.893722 INFO: [APUAPC] D14_APC_1: 0xffffffff
10065 11:41:42.897550 INFO: [APUAPC] D14_APC_2: 0x3fffff
10066 11:41:42.900407 INFO: [APUAPC] D14_APC_3: 0x0
10067 11:41:42.903742 INFO: [APUAPC] D15_APC_0: 0xffffffff
10068 11:41:42.906722 INFO: [APUAPC] D15_APC_1: 0xffffffff
10069 11:41:42.910209 INFO: [APUAPC] D15_APC_2: 0x3fffff
10070 11:41:42.913465 INFO: [APUAPC] D15_APC_3: 0x0
10071 11:41:42.916898 INFO: [APUAPC] APC_CON: 0x4
10072 11:41:42.920188 INFO: [NOCDAPC] D0_APC_0: 0x0
10073 11:41:42.922984 INFO: [NOCDAPC] D0_APC_1: 0x0
10074 11:41:42.926941 INFO: [NOCDAPC] D1_APC_0: 0x0
10075 11:41:42.930060 INFO: [NOCDAPC] D1_APC_1: 0xfff
10076 11:41:42.930151 INFO: [NOCDAPC] D2_APC_0: 0x0
10077 11:41:42.933161 INFO: [NOCDAPC] D2_APC_1: 0xfff
10078 11:41:42.936363 INFO: [NOCDAPC] D3_APC_0: 0x0
10079 11:41:42.939590 INFO: [NOCDAPC] D3_APC_1: 0xfff
10080 11:41:42.943088 INFO: [NOCDAPC] D4_APC_0: 0x0
10081 11:41:42.946284 INFO: [NOCDAPC] D4_APC_1: 0xfff
10082 11:41:42.949614 INFO: [NOCDAPC] D5_APC_0: 0x0
10083 11:41:42.953218 INFO: [NOCDAPC] D5_APC_1: 0xfff
10084 11:41:42.956384 INFO: [NOCDAPC] D6_APC_0: 0x0
10085 11:41:42.959844 INFO: [NOCDAPC] D6_APC_1: 0xfff
10086 11:41:42.962545 INFO: [NOCDAPC] D7_APC_0: 0x0
10087 11:41:42.965944 INFO: [NOCDAPC] D7_APC_1: 0xfff
10088 11:41:42.969276 INFO: [NOCDAPC] D8_APC_0: 0x0
10089 11:41:42.969352 INFO: [NOCDAPC] D8_APC_1: 0xfff
10090 11:41:42.972384 INFO: [NOCDAPC] D9_APC_0: 0x0
10091 11:41:42.976243 INFO: [NOCDAPC] D9_APC_1: 0xfff
10092 11:41:42.979355 INFO: [NOCDAPC] D10_APC_0: 0x0
10093 11:41:42.982795 INFO: [NOCDAPC] D10_APC_1: 0xfff
10094 11:41:42.985902 INFO: [NOCDAPC] D11_APC_0: 0x0
10095 11:41:42.989603 INFO: [NOCDAPC] D11_APC_1: 0xfff
10096 11:41:42.992435 INFO: [NOCDAPC] D12_APC_0: 0x0
10097 11:41:42.995786 INFO: [NOCDAPC] D12_APC_1: 0xfff
10098 11:41:42.998969 INFO: [NOCDAPC] D13_APC_0: 0x0
10099 11:41:43.002236 INFO: [NOCDAPC] D13_APC_1: 0xfff
10100 11:41:43.005746 INFO: [NOCDAPC] D14_APC_0: 0x0
10101 11:41:43.008816 INFO: [NOCDAPC] D14_APC_1: 0xfff
10102 11:41:43.012322 INFO: [NOCDAPC] D15_APC_0: 0x0
10103 11:41:43.015299 INFO: [NOCDAPC] D15_APC_1: 0xfff
10104 11:41:43.015394 INFO: [NOCDAPC] APC_CON: 0x4
10105 11:41:43.018933 INFO: [APUAPC] set_apusys_apc done
10106 11:41:43.022545 INFO: [DEVAPC] devapc_init done
10107 11:41:43.028784 INFO: GICv3 without legacy support detected.
10108 11:41:43.032182 INFO: ARM GICv3 driver initialized in EL3
10109 11:41:43.035278 INFO: Maximum SPI INTID supported: 639
10110 11:41:43.039150 INFO: BL31: Initializing runtime services
10111 11:41:43.045334 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10112 11:41:43.048537 INFO: SPM: enable CPC mode
10113 11:41:43.052315 INFO: mcdi ready for mcusys-off-idle and system suspend
10114 11:41:43.058465 INFO: BL31: Preparing for EL3 exit to normal world
10115 11:41:43.062087 INFO: Entry point address = 0x80000000
10116 11:41:43.062386 INFO: SPSR = 0x8
10117 11:41:43.069368
10118 11:41:43.069830
10119 11:41:43.070165
10120 11:41:43.072574 Starting depthcharge on Spherion...
10121 11:41:43.073148
10122 11:41:43.073506 Wipe memory regions:
10123 11:41:43.073819
10124 11:41:43.076036 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10125 11:41:43.076565 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10126 11:41:43.077000 Setting prompt string to ['asurada:']
10127 11:41:43.077398 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10128 11:41:43.078043 [0x00000040000000, 0x00000054600000)
10129 11:41:43.197995
10130 11:41:43.198603 [0x00000054660000, 0x00000080000000)
10131 11:41:43.458444
10132 11:41:43.458582 [0x000000821a7280, 0x000000ffe64000)
10133 11:41:44.203913
10134 11:41:44.204090 [0x00000100000000, 0x00000240000000)
10135 11:41:46.094412
10136 11:41:46.097071 Initializing XHCI USB controller at 0x11200000.
10137 11:41:47.079625
10138 11:41:47.079757 R8152: Initializing
10139 11:41:47.079826
10140 11:41:47.082844 Version 9 (ocp_data = 6010)
10141 11:41:47.082925
10142 11:41:47.086025 R8152: Done initializing
10143 11:41:47.086127
10144 11:41:47.086217 Adding net device
10145 11:41:47.608693
10146 11:41:47.611552 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10147 11:41:47.611745
10148 11:41:47.611846
10149 11:41:47.611932
10150 11:41:47.612259 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10152 11:41:47.712588 asurada: tftpboot 192.168.201.1 10742214/tftp-deploy-1tj29zfq/kernel/image.itb 10742214/tftp-deploy-1tj29zfq/kernel/cmdline
10153 11:41:47.712755 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10154 11:41:47.712861 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10155 11:41:47.717324 tftpboot 192.168.201.1 10742214/tftp-deploy-1tj29zfq/kernel/image.itp-deploy-1tj29zfq/kernel/cmdline
10156 11:41:47.717452
10157 11:41:47.717548 Waiting for link
10158 11:41:47.919815
10159 11:41:47.920302 done.
10160 11:41:47.920717
10161 11:41:47.921143 MAC: f4:f5:e8:50:de:0a
10162 11:41:47.921460
10163 11:41:47.923013 Sending DHCP discover... done.
10164 11:41:47.923515
10165 11:41:47.927381 Waiting for reply... done.
10166 11:41:47.927800
10167 11:41:47.930104 Sending DHCP request... done.
10168 11:41:47.930550
10169 11:41:47.934097 Waiting for reply... done.
10170 11:41:47.934562
10171 11:41:47.935047 My ip is 192.168.201.14
10172 11:41:47.935386
10173 11:41:47.937376 The DHCP server ip is 192.168.201.1
10174 11:41:47.937792
10175 11:41:47.944249 TFTP server IP predefined by user: 192.168.201.1
10176 11:41:47.944890
10177 11:41:47.951061 Bootfile predefined by user: 10742214/tftp-deploy-1tj29zfq/kernel/image.itb
10178 11:41:47.951488
10179 11:41:47.954423 Sending tftp read request... done.
10180 11:41:47.954610
10181 11:41:47.958939 Waiting for the transfer...
10182 11:41:47.959022
10183 11:41:48.204050 00000000 ################################################################
10184 11:41:48.204189
10185 11:41:48.444113 00080000 ################################################################
10186 11:41:48.444275
10187 11:41:48.668595 00100000 ################################################################
10188 11:41:48.668736
10189 11:41:48.897511 00180000 ################################################################
10190 11:41:48.897654
10191 11:41:49.127484 00200000 ################################################################
10192 11:41:49.127652
10193 11:41:49.352927 00280000 ################################################################
10194 11:41:49.353125
10195 11:41:49.580368 00300000 ################################################################
10196 11:41:49.580567
10197 11:41:49.811615 00380000 ################################################################
10198 11:41:49.811830
10199 11:41:50.044537 00400000 ################################################################
10200 11:41:50.044708
10201 11:41:50.278684 00480000 ################################################################
10202 11:41:50.278891
10203 11:41:50.510329 00500000 ################################################################
10204 11:41:50.510487
10205 11:41:50.742344 00580000 ################################################################
10206 11:41:50.742522
10207 11:41:50.981490 00600000 ################################################################
10208 11:41:50.981689
10209 11:41:51.220082 00680000 ################################################################
10210 11:41:51.220238
10211 11:41:51.460253 00700000 ################################################################
10212 11:41:51.460414
10213 11:41:51.711495 00780000 ################################################################
10214 11:41:51.711685
10215 11:41:51.955471 00800000 ################################################################
10216 11:41:51.955633
10217 11:41:52.191974 00880000 ################################################################
10218 11:41:52.192163
10219 11:41:52.418315 00900000 ################################################################
10220 11:41:52.418491
10221 11:41:52.643196 00980000 ################################################################
10222 11:41:52.643442
10223 11:41:52.876895 00a00000 ################################################################
10224 11:41:52.877072
10225 11:41:53.105960 00a80000 ################################################################
10226 11:41:53.106181
10227 11:41:53.343015 00b00000 ################################################################
10228 11:41:53.343201
10229 11:41:53.572124 00b80000 ################################################################
10230 11:41:53.572333
10231 11:41:53.792782 00c00000 ################################################################
10232 11:41:53.792960
10233 11:41:54.013888 00c80000 ################################################################
10234 11:41:54.014043
10235 11:41:54.242113 00d00000 ################################################################
10236 11:41:54.242307
10237 11:41:54.486052 00d80000 ################################################################
10238 11:41:54.486212
10239 11:41:54.737480 00e00000 ################################################################
10240 11:41:54.737687
10241 11:41:54.985207 00e80000 ################################################################
10242 11:41:54.985358
10243 11:41:55.220926 00f00000 ################################################################
10244 11:41:55.221076
10245 11:41:55.452941 00f80000 ################################################################
10246 11:41:55.453105
10247 11:41:55.669121 01000000 ################################################################
10248 11:41:55.669274
10249 11:41:55.902090 01080000 ################################################################
10250 11:41:55.902270
10251 11:41:56.126555 01100000 ################################################################
10252 11:41:56.126733
10253 11:41:56.343578 01180000 ################################################################
10254 11:41:56.343729
10255 11:41:56.581942 01200000 ################################################################
10256 11:41:56.582101
10257 11:41:56.830944 01280000 ################################################################
10258 11:41:56.831149
10259 11:41:57.057304 01300000 ################################################################
10260 11:41:57.057505
10261 11:41:57.297302 01380000 ################################################################
10262 11:41:57.297507
10263 11:41:57.537341 01400000 ################################################################
10264 11:41:57.537547
10265 11:41:57.767542 01480000 ################################################################
10266 11:41:57.767751
10267 11:41:58.028675 01500000 ################################################################
10268 11:41:58.028881
10269 11:41:58.298825 01580000 ################################################################
10270 11:41:58.298986
10271 11:41:58.532093 01600000 ################################################################
10272 11:41:58.532258
10273 11:41:58.775048 01680000 ################################################################
10274 11:41:58.775222
10275 11:41:58.997464 01700000 ################################################################
10276 11:41:58.997620
10277 11:41:59.216616 01780000 ################################################################
10278 11:41:59.216764
10279 11:41:59.444687 01800000 ################################################################
10280 11:41:59.444841
10281 11:41:59.670975 01880000 ################################################################
10282 11:41:59.671143
10283 11:41:59.915192 01900000 ################################################################
10284 11:41:59.915365
10285 11:42:00.143133 01980000 ################################################################
10286 11:42:00.143308
10287 11:42:00.363699 01a00000 ################################################################
10288 11:42:00.363877
10289 11:42:00.577117 01a80000 ################################################################
10290 11:42:00.577284
10291 11:42:00.793382 01b00000 ################################################################
10292 11:42:00.793545
10293 11:42:00.899387 01b80000 ################################# done.
10294 11:42:00.899563
10295 11:42:00.902458 The bootfile was 29100902 bytes long.
10296 11:42:00.902552
10297 11:42:00.905784 Sending tftp read request... done.
10298 11:42:00.905934
10299 11:42:00.909317 Waiting for the transfer...
10300 11:42:00.909484
10301 11:42:00.909586 00000000 # done.
10302 11:42:00.909688
10303 11:42:00.919017 Command line loaded dynamically from TFTP file: 10742214/tftp-deploy-1tj29zfq/kernel/cmdline
10304 11:42:00.919184
10305 11:42:00.938750 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742214/extract-nfsrootfs-9pw3phm6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10306 11:42:00.938935
10307 11:42:00.939036 Loading FIT.
10308 11:42:00.939134
10309 11:42:00.942278 Image ramdisk-1 has 18608583 bytes.
10310 11:42:00.942418
10311 11:42:00.945424 Image fdt-1 has 46924 bytes.
10312 11:42:00.945550
10313 11:42:00.949034 Image kernel-1 has 10443363 bytes.
10314 11:42:00.949140
10315 11:42:00.955697 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10316 11:42:00.955868
10317 11:42:00.975607 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10318 11:42:00.975765
10319 11:42:00.978396 Choosing best match conf-1 for compat google,spherion-rev2.
10320 11:42:00.983704
10321 11:42:00.988248 Connected to device vid:did:rid of 1ae0:0028:00
10322 11:42:00.995341
10323 11:42:00.998648 tpm_get_response: command 0x17b, return code 0x0
10324 11:42:01.002320
10325 11:42:01.005593 ec_init: CrosEC protocol v3 supported (256, 248)
10326 11:42:01.005714
10327 11:42:01.009121 tpm_cleanup: add release locality here.
10328 11:42:01.009265
10329 11:42:01.012816 Shutting down all USB controllers.
10330 11:42:01.012987
10331 11:42:01.015808 Removing current net device
10332 11:42:01.015910
10333 11:42:01.022447 Exiting depthcharge with code 4 at timestamp: 47330650
10334 11:42:01.022591
10335 11:42:01.026073 LZMA decompressing kernel-1 to 0x821a6718
10336 11:42:01.026192
10337 11:42:01.029067 LZMA decompressing kernel-1 to 0x40000000
10338 11:42:02.340253
10339 11:42:02.340699 jumping to kernel
10340 11:42:02.341766 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10341 11:42:02.342144 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10342 11:42:02.342442 Setting prompt string to ['Linux version [0-9]']
10343 11:42:02.342712 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10344 11:42:02.343342 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10345 11:42:02.421577
10346 11:42:02.424873 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10347 11:42:02.428889 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10348 11:42:02.429008 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10349 11:42:02.429131 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10350 11:42:02.429209 Using line separator: #'\n'#
10351 11:42:02.429270 No login prompt set.
10352 11:42:02.429335 Parsing kernel messages
10353 11:42:02.429392 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10354 11:42:02.429495 [login-action] Waiting for messages, (timeout 00:04:06)
10355 11:42:02.447905 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10356 11:42:02.451072 [ 0.000000] random: crng init done
10357 11:42:02.454788 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10358 11:42:02.457887 [ 0.000000] efi: UEFI not found.
10359 11:42:02.467838 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10360 11:42:02.474593 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10361 11:42:02.484295 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10362 11:42:02.494142 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10363 11:42:02.500679 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10364 11:42:02.507361 [ 0.000000] printk: bootconsole [mtk8250] enabled
10365 11:42:02.513646 [ 0.000000] NUMA: No NUMA configuration found
10366 11:42:02.520446 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10367 11:42:02.523461 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10368 11:42:02.527035 [ 0.000000] Zone ranges:
10369 11:42:02.533601 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10370 11:42:02.537088 [ 0.000000] DMA32 empty
10371 11:42:02.544028 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10372 11:42:02.546665 [ 0.000000] Movable zone start for each node
10373 11:42:02.549745 [ 0.000000] Early memory node ranges
10374 11:42:02.556375 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10375 11:42:02.563756 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10376 11:42:02.569951 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10377 11:42:02.576403 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10378 11:42:02.582995 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10379 11:42:02.589994 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10380 11:42:02.645618 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10381 11:42:02.652406 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10382 11:42:02.658761 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10383 11:42:02.661637 [ 0.000000] psci: probing for conduit method from DT.
10384 11:42:02.668344 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10385 11:42:02.672051 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10386 11:42:02.678426 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10387 11:42:02.681981 [ 0.000000] psci: SMC Calling Convention v1.2
10388 11:42:02.688182 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10389 11:42:02.692056 [ 0.000000] Detected VIPT I-cache on CPU0
10390 11:42:02.698763 [ 0.000000] CPU features: detected: GIC system register CPU interface
10391 11:42:02.704859 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10392 11:42:02.711286 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10393 11:42:02.718550 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10394 11:42:02.727910 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10395 11:42:02.734345 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10396 11:42:02.737688 [ 0.000000] alternatives: applying boot alternatives
10397 11:42:02.744153 [ 0.000000] Fallback order for Node 0: 0
10398 11:42:02.750844 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10399 11:42:02.754228 [ 0.000000] Policy zone: Normal
10400 11:42:02.773820 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742214/extract-nfsrootfs-9pw3phm6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10401 11:42:02.783464 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10402 11:42:02.795565 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10403 11:42:02.805757 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10404 11:42:02.811947 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10405 11:42:02.815379 <6>[ 0.000000] software IO TLB: area num 8.
10406 11:42:02.872014 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10407 11:42:03.021194 <6>[ 0.000000] Memory: 7952988K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 399780K reserved, 32768K cma-reserved)
10408 11:42:03.028031 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10409 11:42:03.034162 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10410 11:42:03.037869 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10411 11:42:03.044402 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10412 11:42:03.050908 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10413 11:42:03.054283 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10414 11:42:03.064348 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10415 11:42:03.070556 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10416 11:42:03.077560 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10417 11:42:03.083943 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10418 11:42:03.087323 <6>[ 0.000000] GICv3: 608 SPIs implemented
10419 11:42:03.090582 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10420 11:42:03.097413 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10421 11:42:03.100568 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10422 11:42:03.107245 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10423 11:42:03.120344 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10424 11:42:03.133322 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10425 11:42:03.139988 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10426 11:42:03.147615 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10427 11:42:03.161101 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10428 11:42:03.167703 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10429 11:42:03.174245 <6>[ 0.009227] Console: colour dummy device 80x25
10430 11:42:03.184170 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10431 11:42:03.190489 <6>[ 0.024396] pid_max: default: 32768 minimum: 301
10432 11:42:03.194060 <6>[ 0.029263] LSM: Security Framework initializing
10433 11:42:03.200811 <6>[ 0.034204] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 11:42:03.210492 <6>[ 0.042019] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 11:42:03.220491 <6>[ 0.051507] cblist_init_generic: Setting adjustable number of callback queues.
10436 11:42:03.227026 <6>[ 0.058959] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 11:42:03.230267 <6>[ 0.065298] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 11:42:03.236493 <6>[ 0.071709] rcu: Hierarchical SRCU implementation.
10439 11:42:03.243194 <6>[ 0.076722] rcu: Max phase no-delay instances is 1000.
10440 11:42:03.249643 <6>[ 0.083769] EFI services will not be available.
10441 11:42:03.253351 <6>[ 0.088740] smp: Bringing up secondary CPUs ...
10442 11:42:03.261343 <6>[ 0.093790] Detected VIPT I-cache on CPU1
10443 11:42:03.267717 <6>[ 0.093864] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10444 11:42:03.274279 <6>[ 0.093893] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10445 11:42:03.277510 <6>[ 0.094228] Detected VIPT I-cache on CPU2
10446 11:42:03.284370 <6>[ 0.094282] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10447 11:42:03.294189 <6>[ 0.094300] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10448 11:42:03.297431 <6>[ 0.094558] Detected VIPT I-cache on CPU3
10449 11:42:03.304730 <6>[ 0.094605] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10450 11:42:03.310707 <6>[ 0.094620] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10451 11:42:03.314586 <6>[ 0.094923] CPU features: detected: Spectre-v4
10452 11:42:03.320438 <6>[ 0.094931] CPU features: detected: Spectre-BHB
10453 11:42:03.323972 <6>[ 0.094937] Detected PIPT I-cache on CPU4
10454 11:42:03.331024 <6>[ 0.094995] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10455 11:42:03.337130 <6>[ 0.095011] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10456 11:42:03.343840 <6>[ 0.095304] Detected PIPT I-cache on CPU5
10457 11:42:03.350137 <6>[ 0.095366] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10458 11:42:03.357067 <6>[ 0.095383] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10459 11:42:03.360407 <6>[ 0.095665] Detected PIPT I-cache on CPU6
10460 11:42:03.366671 <6>[ 0.095730] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10461 11:42:03.373389 <6>[ 0.095746] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10462 11:42:03.380188 <6>[ 0.096047] Detected PIPT I-cache on CPU7
10463 11:42:03.386527 <6>[ 0.096112] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10464 11:42:03.393546 <6>[ 0.096129] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10465 11:42:03.396694 <6>[ 0.096176] smp: Brought up 1 node, 8 CPUs
10466 11:42:03.403013 <6>[ 0.237554] SMP: Total of 8 processors activated.
10467 11:42:03.406740 <6>[ 0.242506] CPU features: detected: 32-bit EL0 Support
10468 11:42:03.416328 <6>[ 0.247868] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10469 11:42:03.422988 <6>[ 0.256669] CPU features: detected: Common not Private translations
10470 11:42:03.429141 <6>[ 0.263184] CPU features: detected: CRC32 instructions
10471 11:42:03.435849 <6>[ 0.268535] CPU features: detected: RCpc load-acquire (LDAPR)
10472 11:42:03.439697 <6>[ 0.274532] CPU features: detected: LSE atomic instructions
10473 11:42:03.445895 <6>[ 0.280313] CPU features: detected: Privileged Access Never
10474 11:42:03.452798 <6>[ 0.286092] CPU features: detected: RAS Extension Support
10475 11:42:03.459227 <6>[ 0.291701] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10476 11:42:03.462524 <6>[ 0.298921] CPU: All CPU(s) started at EL2
10477 11:42:03.469311 <6>[ 0.303238] alternatives: applying system-wide alternatives
10478 11:42:03.478840 <6>[ 0.313983] devtmpfs: initialized
10479 11:42:03.491542 <6>[ 0.322814] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10480 11:42:03.501383 <6>[ 0.332772] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10481 11:42:03.507564 <6>[ 0.340899] pinctrl core: initialized pinctrl subsystem
10482 11:42:03.511161 <6>[ 0.347571] DMI not present or invalid.
10483 11:42:03.517984 <6>[ 0.351978] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10484 11:42:03.527939 <6>[ 0.358857] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10485 11:42:03.534716 <6>[ 0.366436] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10486 11:42:03.544012 <6>[ 0.374659] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10487 11:42:03.547085 <6>[ 0.382904] audit: initializing netlink subsys (disabled)
10488 11:42:03.557235 <5>[ 0.388594] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10489 11:42:03.564102 <6>[ 0.389304] thermal_sys: Registered thermal governor 'step_wise'
10490 11:42:03.570844 <6>[ 0.396563] thermal_sys: Registered thermal governor 'power_allocator'
10491 11:42:03.574106 <6>[ 0.402817] cpuidle: using governor menu
10492 11:42:03.580989 <6>[ 0.413775] NET: Registered PF_QIPCRTR protocol family
10493 11:42:03.587192 <6>[ 0.419266] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10494 11:42:03.593805 <6>[ 0.426371] ASID allocator initialised with 32768 entries
10495 11:42:03.597207 <6>[ 0.432931] Serial: AMBA PL011 UART driver
10496 11:42:03.607410 <4>[ 0.441634] Trying to register duplicate clock ID: 134
10497 11:42:03.660901 <6>[ 0.498788] KASLR enabled
10498 11:42:03.675354 <6>[ 0.506487] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10499 11:42:03.681427 <6>[ 0.513502] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10500 11:42:03.688410 <6>[ 0.519987] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10501 11:42:03.695076 <6>[ 0.526994] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10502 11:42:03.702038 <6>[ 0.533482] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10503 11:42:03.707904 <6>[ 0.540487] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10504 11:42:03.714584 <6>[ 0.546971] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10505 11:42:03.721099 <6>[ 0.553974] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10506 11:42:03.724711 <6>[ 0.561443] ACPI: Interpreter disabled.
10507 11:42:03.733554 <6>[ 0.567844] iommu: Default domain type: Translated
10508 11:42:03.739489 <6>[ 0.572956] iommu: DMA domain TLB invalidation policy: strict mode
10509 11:42:03.743264 <5>[ 0.579621] SCSI subsystem initialized
10510 11:42:03.750360 <6>[ 0.583857] usbcore: registered new interface driver usbfs
10511 11:42:03.756184 <6>[ 0.589586] usbcore: registered new interface driver hub
10512 11:42:03.759500 <6>[ 0.595140] usbcore: registered new device driver usb
10513 11:42:03.766513 <6>[ 0.601241] pps_core: LinuxPPS API ver. 1 registered
10514 11:42:03.776486 <6>[ 0.606435] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10515 11:42:03.779802 <6>[ 0.615777] PTP clock support registered
10516 11:42:03.783022 <6>[ 0.620019] EDAC MC: Ver: 3.0.0
10517 11:42:03.791001 <6>[ 0.625205] FPGA manager framework
10518 11:42:03.796938 <6>[ 0.628884] Advanced Linux Sound Architecture Driver Initialized.
10519 11:42:03.800309 <6>[ 0.635646] vgaarb: loaded
10520 11:42:03.806799 <6>[ 0.638813] clocksource: Switched to clocksource arch_sys_counter
10521 11:42:03.810090 <5>[ 0.645258] VFS: Disk quotas dquot_6.6.0
10522 11:42:03.816741 <6>[ 0.649442] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10523 11:42:03.820112 <6>[ 0.656634] pnp: PnP ACPI: disabled
10524 11:42:03.828459 <6>[ 0.663330] NET: Registered PF_INET protocol family
10525 11:42:03.838102 <6>[ 0.668929] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10526 11:42:03.849722 <6>[ 0.681216] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10527 11:42:03.859506 <6>[ 0.690032] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10528 11:42:03.866448 <6>[ 0.698002] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10529 11:42:03.876292 <6>[ 0.706698] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10530 11:42:03.883091 <6>[ 0.716432] TCP: Hash tables configured (established 65536 bind 65536)
10531 11:42:03.922509 <6>[ 0.723288] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10532 11:42:03.923046 <6>[ 0.730486] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 11:42:03.923395 <6>[ 0.738188] NET: Registered PF_UNIX/PF_LOCAL protocol family
10534 11:42:03.923773 <6>[ 0.744284] RPC: Registered named UNIX socket transport module.
10535 11:42:03.924110 <6>[ 0.750429] RPC: Registered udp transport module.
10536 11:42:03.924415 <6>[ 0.755362] RPC: Registered tcp transport module.
10537 11:42:03.928884 <6>[ 0.760291] RPC: Registered tcp NFSv4.1 backchannel transport module.
10538 11:42:03.932638 <6>[ 0.766958] PCI: CLS 0 bytes, default 64
10539 11:42:03.934917 <6>[ 0.771357] Unpacking initramfs...
10540 11:42:03.959067 <6>[ 0.790936] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10541 11:42:03.969023 <6>[ 0.799607] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10542 11:42:03.972405 <6>[ 0.808461] kvm [1]: IPA Size Limit: 40 bits
10543 11:42:03.979008 <6>[ 0.812990] kvm [1]: GICv3: no GICV resource entry
10544 11:42:03.982292 <6>[ 0.818007] kvm [1]: disabling GICv2 emulation
10545 11:42:03.988512 <6>[ 0.822693] kvm [1]: GIC system register CPU interface enabled
10546 11:42:03.992124 <6>[ 0.828856] kvm [1]: vgic interrupt IRQ18
10547 11:42:03.998927 <6>[ 0.833217] kvm [1]: VHE mode initialized successfully
10548 11:42:04.005148 <5>[ 0.839744] Initialise system trusted keyrings
10549 11:42:04.011969 <6>[ 0.844537] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10550 11:42:04.019473 <6>[ 0.854530] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10551 11:42:04.026003 <5>[ 0.860913] NFS: Registering the id_resolver key type
10552 11:42:04.029292 <5>[ 0.866227] Key type id_resolver registered
10553 11:42:04.035780 <5>[ 0.870640] Key type id_legacy registered
10554 11:42:04.042603 <6>[ 0.874918] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10555 11:42:04.049180 <6>[ 0.881841] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10556 11:42:04.055814 <6>[ 0.889554] 9p: Installing v9fs 9p2000 file system support
10557 11:42:04.092825 <5>[ 0.927858] Key type asymmetric registered
10558 11:42:04.096258 <5>[ 0.932193] Asymmetric key parser 'x509' registered
10559 11:42:04.106136 <6>[ 0.937336] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10560 11:42:04.109222 <6>[ 0.944952] io scheduler mq-deadline registered
10561 11:42:04.112667 <6>[ 0.949711] io scheduler kyber registered
10562 11:42:04.131535 <6>[ 0.966606] EINJ: ACPI disabled.
10563 11:42:04.163101 <4>[ 0.991791] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10564 11:42:04.172956 <4>[ 1.002400] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 11:42:04.187729 <6>[ 1.022747] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10566 11:42:04.195422 <6>[ 1.030588] printk: console [ttyS0] disabled
10567 11:42:04.223869 <6>[ 1.055240] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10568 11:42:04.229964 <6>[ 1.064714] printk: console [ttyS0] enabled
10569 11:42:04.233437 <6>[ 1.064714] printk: console [ttyS0] enabled
10570 11:42:04.240070 <6>[ 1.073608] printk: bootconsole [mtk8250] disabled
10571 11:42:04.243360 <6>[ 1.073608] printk: bootconsole [mtk8250] disabled
10572 11:42:04.249934 <6>[ 1.084618] SuperH (H)SCI(F) driver initialized
10573 11:42:04.253025 <6>[ 1.089870] msm_serial: driver initialized
10574 11:42:04.267333 <6>[ 1.098702] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10575 11:42:04.276702 <6>[ 1.107249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10576 11:42:04.284013 <6>[ 1.115791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10577 11:42:04.293573 <6>[ 1.124417] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10578 11:42:04.303165 <6>[ 1.133122] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10579 11:42:04.310034 <6>[ 1.141836] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10580 11:42:04.320019 <6>[ 1.150375] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10581 11:42:04.326694 <6>[ 1.159168] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10582 11:42:04.336374 <6>[ 1.167710] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10583 11:42:04.347687 <6>[ 1.183009] loop: module loaded
10584 11:42:04.354641 <6>[ 1.189019] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10585 11:42:04.377376 <4>[ 1.212227] mtk-pmic-keys: Failed to locate of_node [id: -1]
10586 11:42:04.383844 <6>[ 1.218918] megasas: 07.719.03.00-rc1
10587 11:42:04.393984 <6>[ 1.228561] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10588 11:42:04.403636 <6>[ 1.238172] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10589 11:42:04.419762 <6>[ 1.254472] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10590 11:42:04.478982 <6>[ 1.307517] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10591 11:42:04.724644 <6>[ 1.559861] Freeing initrd memory: 18168K
10592 11:42:04.736196 <6>[ 1.571187] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10593 11:42:04.747038 <6>[ 1.582169] tun: Universal TUN/TAP device driver, 1.6
10594 11:42:04.750492 <6>[ 1.588217] thunder_xcv, ver 1.0
10595 11:42:04.753982 <6>[ 1.591724] thunder_bgx, ver 1.0
10596 11:42:04.757308 <6>[ 1.595220] nicpf, ver 1.0
10597 11:42:04.767155 <6>[ 1.599229] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10598 11:42:04.770521 <6>[ 1.606704] hns3: Copyright (c) 2017 Huawei Corporation.
10599 11:42:04.774391 <6>[ 1.612292] hclge is initializing
10600 11:42:04.780774 <6>[ 1.615868] e1000: Intel(R) PRO/1000 Network Driver
10601 11:42:04.787530 <6>[ 1.620997] e1000: Copyright (c) 1999-2006 Intel Corporation.
10602 11:42:04.790605 <6>[ 1.627011] e1000e: Intel(R) PRO/1000 Network Driver
10603 11:42:04.797096 <6>[ 1.632228] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10604 11:42:04.804124 <6>[ 1.638412] igb: Intel(R) Gigabit Ethernet Network Driver
10605 11:42:04.810341 <6>[ 1.644063] igb: Copyright (c) 2007-2014 Intel Corporation.
10606 11:42:04.817098 <6>[ 1.649902] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10607 11:42:04.823819 <6>[ 1.656420] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10608 11:42:04.826983 <6>[ 1.662883] sky2: driver version 1.30
10609 11:42:04.833583 <6>[ 1.667868] VFIO - User Level meta-driver version: 0.3
10610 11:42:04.840826 <6>[ 1.676048] usbcore: registered new interface driver usb-storage
10611 11:42:04.847989 <6>[ 1.682493] usbcore: registered new device driver onboard-usb-hub
10612 11:42:04.856675 <6>[ 1.691632] mt6397-rtc mt6359-rtc: registered as rtc0
10613 11:42:04.867006 <6>[ 1.697100] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:42:05 UTC (1686829325)
10614 11:42:04.869658 <6>[ 1.706664] i2c_dev: i2c /dev entries driver
10615 11:42:04.886745 <6>[ 1.718324] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10616 11:42:04.893278 <6>[ 1.728585] sdhci: Secure Digital Host Controller Interface driver
10617 11:42:04.900191 <6>[ 1.735022] sdhci: Copyright(c) Pierre Ossman
10618 11:42:04.906689 <6>[ 1.740414] Synopsys Designware Multimedia Card Interface Driver
10619 11:42:04.910128 <6>[ 1.747036] mmc0: CQHCI version 5.10
10620 11:42:04.916930 <6>[ 1.747569] sdhci-pltfm: SDHCI platform and OF driver helper
10621 11:42:04.924667 <6>[ 1.759275] ledtrig-cpu: registered to indicate activity on CPUs
10622 11:42:04.934761 <6>[ 1.766782] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10623 11:42:04.941758 <6>[ 1.774188] usbcore: registered new interface driver usbhid
10624 11:42:04.944871 <6>[ 1.780020] usbhid: USB HID core driver
10625 11:42:04.951280 <6>[ 1.784264] spi_master spi0: will run message pump with realtime priority
10626 11:42:04.996041 <6>[ 1.824799] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10627 11:42:05.003139 <6>[ 1.838112] mmc0: Command Queue Engine enabled
10628 11:42:05.009493 <6>[ 1.842853] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10629 11:42:05.016328 <6>[ 1.850258] mmcblk0: mmc0:0001 DA4128 116 GiB
10630 11:42:05.029346 <6>[ 1.855607] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10631 11:42:05.036123 <6>[ 1.858452] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10632 11:42:05.042983 <6>[ 1.875850] cros-ec-spi spi0.0: Chrome EC device registered
10633 11:42:05.046779 <6>[ 1.876375] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10634 11:42:05.052875 <6>[ 1.887561] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10635 11:42:05.059567 <6>[ 1.893533] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10636 11:42:05.081330 <6>[ 1.912815] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10637 11:42:05.089256 <6>[ 1.924196] NET: Registered PF_PACKET protocol family
10638 11:42:05.096072 <6>[ 1.929618] 9pnet: Installing 9P2000 support
10639 11:42:05.098737 <5>[ 1.934195] Key type dns_resolver registered
10640 11:42:05.102449 <6>[ 1.939246] registered taskstats version 1
10641 11:42:05.108872 <5>[ 1.943651] Loading compiled-in X.509 certificates
10642 11:42:05.143763 <4>[ 1.971861] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 11:42:05.152941 <4>[ 1.982572] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10644 11:42:05.163566 <3>[ 1.995586] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10645 11:42:05.176193 <6>[ 2.011256] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10646 11:42:05.183104 <6>[ 2.018026] xhci-mtk 11200000.usb: xHCI Host Controller
10647 11:42:05.192823 <6>[ 2.023522] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10648 11:42:05.199549 <6>[ 2.031368] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10649 11:42:05.206070 <6>[ 2.040801] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10650 11:42:05.212372 <6>[ 2.046917] xhci-mtk 11200000.usb: xHCI Host Controller
10651 11:42:05.218874 <6>[ 2.052517] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10652 11:42:05.228755 <6>[ 2.060197] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10653 11:42:05.232485 <6>[ 2.068066] hub 1-0:1.0: USB hub found
10654 11:42:05.235548 <6>[ 2.072101] hub 1-0:1.0: 1 port detected
10655 11:42:05.245646 <6>[ 2.076471] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10656 11:42:05.248708 <6>[ 2.085266] hub 2-0:1.0: USB hub found
10657 11:42:05.252050 <6>[ 2.089304] hub 2-0:1.0: 1 port detected
10658 11:42:05.261230 <6>[ 2.096399] mtk-msdc 11f70000.mmc: Got CD GPIO
10659 11:42:05.278463 <6>[ 2.110294] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10660 11:42:05.285163 <6>[ 2.118335] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10661 11:42:05.295097 <4>[ 2.126335] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10662 11:42:05.305233 <6>[ 2.135995] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10663 11:42:05.311284 <6>[ 2.144078] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10664 11:42:05.321288 <6>[ 2.152113] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10665 11:42:05.328044 <6>[ 2.160028] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10666 11:42:05.334441 <6>[ 2.167848] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10667 11:42:05.344770 <6>[ 2.175668] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10668 11:42:05.355052 <6>[ 2.186413] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10669 11:42:05.364405 <6>[ 2.194782] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10670 11:42:05.370832 <6>[ 2.203137] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10671 11:42:05.380776 <6>[ 2.211480] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10672 11:42:05.387190 <6>[ 2.219822] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10673 11:42:05.397299 <6>[ 2.228165] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10674 11:42:05.403910 <6>[ 2.236507] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10675 11:42:05.413871 <6>[ 2.244849] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10676 11:42:05.420144 <6>[ 2.253197] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10677 11:42:05.430858 <6>[ 2.261539] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10678 11:42:05.437130 <6>[ 2.269881] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10679 11:42:05.447185 <6>[ 2.278224] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10680 11:42:05.453331 <6>[ 2.286567] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10681 11:42:05.463711 <6>[ 2.294912] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10682 11:42:05.469969 <6>[ 2.303262] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10683 11:42:05.477388 <6>[ 2.312176] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10684 11:42:05.484509 <6>[ 2.319609] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10685 11:42:05.491394 <6>[ 2.326652] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10686 11:42:05.501876 <6>[ 2.333765] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10687 11:42:05.508725 <6>[ 2.341050] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10688 11:42:05.518450 <6>[ 2.348047] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10689 11:42:05.524948 <6>[ 2.357209] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10690 11:42:05.534887 <6>[ 2.366336] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10691 11:42:05.544611 <6>[ 2.375636] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10692 11:42:05.554893 <6>[ 2.385115] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10693 11:42:05.564577 <6>[ 2.394590] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10694 11:42:05.574687 <6>[ 2.403716] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10695 11:42:05.581417 <6>[ 2.413192] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10696 11:42:05.590840 <6>[ 2.422319] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10697 11:42:05.600710 <6>[ 2.431621] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10698 11:42:05.611145 <6>[ 2.441787] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10699 11:42:05.621622 <6>[ 2.453324] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10700 11:42:05.628348 <6>[ 2.463340] Trying to probe devices needed for running init ...
10701 11:42:05.647179 <6>[ 2.479255] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10702 11:42:05.675908 <6>[ 2.511095] hub 2-1:1.0: USB hub found
10703 11:42:05.679165 <6>[ 2.515624] hub 2-1:1.0: 3 ports detected
10704 11:42:05.798890 <6>[ 2.630994] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10705 11:42:05.953229 <6>[ 2.788667] hub 1-1:1.0: USB hub found
10706 11:42:05.956745 <6>[ 2.793094] hub 1-1:1.0: 4 ports detected
10707 11:42:06.279336 <6>[ 3.111088] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10708 11:42:06.410339 <6>[ 3.244976] hub 1-1.1:1.0: USB hub found
10709 11:42:06.413335 <6>[ 3.249257] hub 1-1.1:1.0: 4 ports detected
10710 11:42:06.527291 <6>[ 3.358866] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10711 11:42:06.660207 <6>[ 3.495335] hub 1-1.4:1.0: USB hub found
10712 11:42:06.663595 <6>[ 3.499985] hub 1-1.4:1.0: 2 ports detected
10713 11:42:06.739185 <6>[ 3.571091] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10714 11:42:06.927032 <6>[ 3.759085] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10715 11:42:07.011789 <3>[ 3.847294] usb 1-1.1.4: device descriptor read/64, error -32
10716 11:42:07.203760 <3>[ 4.039298] usb 1-1.1.4: device descriptor read/64, error -32
10717 11:42:07.398956 <6>[ 4.231085] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10718 11:42:07.586825 <6>[ 4.419090] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10719 11:42:07.672270 <3>[ 4.507296] usb 1-1.1.4: device descriptor read/64, error -32
10720 11:42:07.864329 <3>[ 4.699300] usb 1-1.1.4: device descriptor read/64, error -32
10721 11:42:07.976875 <6>[ 4.811662] usb 1-1.1-port4: attempt power cycle
10722 11:42:08.063127 <6>[ 4.895113] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10723 11:42:08.587073 <6>[ 5.419085] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10724 11:42:08.593957 <4>[ 5.426538] usb 1-1.1.4: Device not responding to setup address.
10725 11:42:08.856615 <4>[ 5.639361] usb 1-1.1.4: Device not responding to setup address.
10726 11:42:09.015956 <3>[ 5.851079] usb 1-1.1.4: device not accepting address 10, error -71
10727 11:42:09.103141 <6>[ 5.935085] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10728 11:42:09.109524 <4>[ 5.942532] usb 1-1.1.4: Device not responding to setup address.
10729 11:42:09.319934 <4>[ 6.155360] usb 1-1.1.4: Device not responding to setup address.
10730 11:42:09.531853 <3>[ 6.367079] usb 1-1.1.4: device not accepting address 11, error -71
10731 11:42:09.538824 <3>[ 6.374030] usb 1-1.1-port4: unable to enumerate USB device
10732 11:42:17.923578 <6>[ 14.763699] ALSA device list:
10733 11:42:17.929934 <6>[ 14.766958] No soundcards found.
10734 11:42:17.942517 <6>[ 14.779347] Freeing unused kernel memory: 8384K
10735 11:42:17.946047 <6>[ 14.784267] Run /init as init process
10736 11:42:17.956480 Loading, please wait...
10737 11:42:17.983677 Starting systemd-udevd version 252.6-1
10738 11:42:18.385460 <6>[ 15.218992] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10739 11:42:18.397154 <6>[ 15.230712] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10740 11:42:18.406992 <6>[ 15.238956] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10741 11:42:18.410467 <6>[ 15.241081] remoteproc remoteproc0: scp is available
10742 11:42:18.420121 <6>[ 15.247745] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10743 11:42:18.430497 <4>[ 15.262034] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10744 11:42:18.437015 <6>[ 15.272025] remoteproc remoteproc0: powering up scp
10745 11:42:18.446978 <4>[ 15.277278] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10746 11:42:18.450230 <3>[ 15.287173] remoteproc remoteproc0: request_firmware failed: -2
10747 11:42:18.456619 <6>[ 15.287972] mc: Linux media interface: v0.10
10748 11:42:18.463660 <3>[ 15.294939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 11:42:18.470118 <6>[ 15.299781] usbcore: registered new interface driver r8152
10750 11:42:18.476704 <4>[ 15.300360] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10751 11:42:18.482913 <4>[ 15.300489] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10752 11:42:18.493360 <3>[ 15.306045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 11:42:18.499561 <6>[ 15.312842] videodev: Linux video capture interface: v2.00
10754 11:42:18.506583 <3>[ 15.319118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 11:42:18.516403 <3>[ 15.319333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 11:42:18.522706 <6>[ 15.319947] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10757 11:42:18.529649 <4>[ 15.345121] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10758 11:42:18.536178 <4>[ 15.345121] Fallback method does not support PEC.
10759 11:42:18.543016 <3>[ 15.348433] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 11:42:18.552663 <3>[ 15.348464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 11:42:18.560119 <6>[ 15.372418] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10762 11:42:18.569540 <3>[ 15.375905] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10763 11:42:18.576290 <3>[ 15.378200] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 11:42:18.582998 <6>[ 15.386275] pci_bus 0000:00: root bus resource [bus 00-ff]
10765 11:42:18.589436 <3>[ 15.394264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 11:42:18.599830 <3>[ 15.397597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10767 11:42:18.605899 <6>[ 15.401324] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10768 11:42:18.612844 <6>[ 15.401975] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10769 11:42:18.622765 <6>[ 15.401985] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10770 11:42:18.629556 <6>[ 15.402024] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10771 11:42:18.635751 <6>[ 15.402043] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10772 11:42:18.642264 <6>[ 15.402121] pci 0000:00:00.0: supports D1 D2
10773 11:42:18.649117 <6>[ 15.402124] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10774 11:42:18.656046 <6>[ 15.403942] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10775 11:42:18.662082 <6>[ 15.404056] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10776 11:42:18.668993 <6>[ 15.404085] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10777 11:42:18.679006 <6>[ 15.404103] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10778 11:42:18.685325 <6>[ 15.404121] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10779 11:42:18.688661 <6>[ 15.404233] pci 0000:01:00.0: supports D1 D2
10780 11:42:18.695516 <6>[ 15.404236] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10781 11:42:18.705482 <6>[ 15.406149] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10782 11:42:18.715500 <3>[ 15.410249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 11:42:18.725122 <6>[ 15.416089] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10784 11:42:18.734836 <6>[ 15.416383] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10785 11:42:18.741749 <6>[ 15.419838] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10786 11:42:18.748487 <3>[ 15.423934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 11:42:18.754837 <6>[ 15.432120] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10788 11:42:18.761395 <6>[ 15.432499] usbcore: registered new interface driver cdc_ether
10789 11:42:18.771402 <3>[ 15.440747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 11:42:18.777784 <3>[ 15.440756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 11:42:18.787766 <3>[ 15.440870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 11:42:18.794463 <6>[ 15.441585] usbcore: registered new interface driver r8153_ecm
10793 11:42:18.797750 <6>[ 15.441634] Bluetooth: Core ver 2.22
10794 11:42:18.801130 <6>[ 15.441722] NET: Registered PF_BLUETOOTH protocol family
10795 11:42:18.807499 <6>[ 15.441727] Bluetooth: HCI device and connection manager initialized
10796 11:42:18.814304 <6>[ 15.441756] Bluetooth: HCI socket layer initialized
10797 11:42:18.820735 <6>[ 15.441763] Bluetooth: L2CAP socket layer initialized
10798 11:42:18.824405 <6>[ 15.441778] Bluetooth: SCO socket layer initialized
10799 11:42:18.830630 <6>[ 15.448206] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10800 11:42:18.840761 <3>[ 15.455249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 11:42:18.847109 <6>[ 15.465190] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10802 11:42:18.857193 <3>[ 15.471424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 11:42:18.863640 <6>[ 15.478932] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10804 11:42:18.870684 <6>[ 15.480262] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10805 11:42:18.876796 <6>[ 15.480415] usbcore: registered new interface driver btusb
10806 11:42:18.886916 <4>[ 15.480931] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10807 11:42:18.893224 <3>[ 15.480940] Bluetooth: hci0: Failed to load firmware file (-2)
10808 11:42:18.900069 <3>[ 15.480943] Bluetooth: hci0: Failed to set up firmware (-2)
10809 11:42:18.909636 <4>[ 15.480947] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10810 11:42:18.923069 <6>[ 15.481851] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10811 11:42:18.929901 <6>[ 15.481981] usbcore: registered new interface driver uvcvideo
10812 11:42:18.936386 <3>[ 15.483438] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 11:42:18.943117 <6>[ 15.490317] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10814 11:42:18.952704 <3>[ 15.498568] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 11:42:18.959470 <6>[ 15.504837] pci 0000:00:00.0: PCI bridge to [bus 01]
10816 11:42:18.966404 <3>[ 15.512341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10817 11:42:18.972768 <6>[ 15.512966] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10818 11:42:18.979063 <6>[ 15.519782] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10819 11:42:18.986359 <6>[ 15.822554] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10820 11:42:18.993346 <6>[ 15.829832] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10821 11:42:18.999508 <6>[ 15.836466] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10822 11:42:19.014616 <4>[ 15.847732] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10823 11:42:19.024266 <4>[ 15.857030] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10824 11:42:19.034725 <5>[ 15.868331] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10825 11:42:19.038241 <6>[ 15.874885] r8152 1-1.1.1:1.0 eth0: v1.12.13
10826 11:42:19.057594 <5>[ 15.890748] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10827 11:42:19.060942 <6>[ 15.892211] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10828 11:42:19.098019 <4>[ 15.931316] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10829 11:42:19.104564 <6>[ 15.940277] cfg80211: failed to load regulatory.db
10830 11:42:19.142708 <6>[ 15.975823] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10831 11:42:19.149502 <6>[ 15.983406] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10832 11:42:19.174240 <6>[ 16.010112] mt7921e 0000:01:00.0: ASIC revision: 79610010
10833 11:42:19.281787 <4>[ 16.111564] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10834 11:42:19.285083 Begin: Loading essential drivers ... done.
10835 11:42:19.291755 Begin: Running /scripts/init-premount ... done.
10836 11:42:19.298704 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10837 11:42:19.305042 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10838 11:42:19.311386 Device /sys/class/net/enxf4f5e850de0a found
10839 11:42:19.311866 done.
10840 11:42:19.323375 Begin: Waiting up to 180 secs for any network device to become available ... done.
10841 11:42:19.357736 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10842 11:42:19.403967 <4>[ 16.233542] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 11:42:19.522952 <4>[ 16.352797] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10844 11:42:19.638844 <4>[ 16.468588] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 11:42:19.754469 <4>[ 16.584543] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10846 11:42:19.870436 <4>[ 16.700447] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10847 11:42:20.018881 <4>[ 16.816371] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10848 11:42:20.101907 <4>[ 16.932294] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10849 11:42:20.217916 <4>[ 17.048243] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10850 11:42:20.334481 <4>[ 17.164250] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10851 11:42:20.360824 IP-Config: no response after 2 secs - giving up
10852 11:42:20.401373 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10853 11:42:20.442597 <3>[ 17.278920] mt7921e 0000:01:00.0: hardware init failed
10854 11:42:21.012348 <6>[ 17.849182] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10855 11:42:21.862643 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10856 11:42:21.869339 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10857 11:42:21.875377 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10858 11:42:21.882176 host : mt8192-asurada-spherion-r0-cbg-9
10859 11:42:21.889108 domain : lava-rack
10860 11:42:21.895436 rootserver: 192.168.201.1 rootpath:
10861 11:42:21.895571 filename :
10862 11:42:21.911634 done.
10863 11:42:21.915408 Begin: Running /scripts/nfs-bottom ... done.
10864 11:42:21.938288 Begin: Running /scripts/init-bottom ... done.
10865 11:42:23.157410 <6>[ 19.994433] NET: Registered PF_INET6 protocol family
10866 11:42:23.164276 <6>[ 20.001474] Segment Routing with IPv6
10867 11:42:23.167740 <6>[ 20.005444] In-situ OAM (IOAM) with IPv6
10868 11:42:23.326865 <30>[ 20.137898] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10869 11:42:23.333560 <30>[ 20.170177] systemd[1]: Detected architecture arm64.
10870 11:42:23.337918
10871 11:42:23.341173 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10872 11:42:23.341270
10873 11:42:23.370398 <30>[ 20.207215] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10874 11:42:23.925056 <30>[ 20.758824] systemd[1]: Queued start job for default target graphical.target.
10875 11:42:23.967177 <30>[ 20.801131] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10876 11:42:23.973703 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10877 11:42:23.993581 <30>[ 20.827861] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10878 11:42:24.000370 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10879 11:42:24.022412 <30>[ 20.856470] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10880 11:42:24.032274 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10881 11:42:24.050038 <30>[ 20.883654] systemd[1]: Created slice user.slice - User and Session Slice.
10882 11:42:24.056178 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10883 11:42:24.076872 <30>[ 20.907313] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10884 11:42:24.082883 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10885 11:42:24.104609 <30>[ 20.935273] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10886 11:42:24.110843 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10887 11:42:24.139553 <30>[ 20.963545] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10888 11:42:24.149290 <30>[ 20.983373] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10889 11:42:24.156023 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10890 11:42:24.173323 <30>[ 21.007094] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10891 11:42:24.182980 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10892 11:42:24.197550 <30>[ 21.035184] systemd[1]: Reached target paths.target - Path Units.
10893 11:42:24.204350 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10894 11:42:24.225427 <30>[ 21.059155] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10895 11:42:24.231601 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10896 11:42:24.245975 <30>[ 21.083117] systemd[1]: Reached target slices.target - Slice Units.
10897 11:42:24.255684 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10898 11:42:24.269783 <30>[ 21.107435] systemd[1]: Reached target swap.target - Swaps.
10899 11:42:24.276840 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10900 11:42:24.297267 <30>[ 21.131158] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10901 11:42:24.306981 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10902 11:42:24.325248 <30>[ 21.159372] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10903 11:42:24.334913 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10904 11:42:24.354446 <30>[ 21.188794] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10905 11:42:24.364464 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10906 11:42:24.382132 <30>[ 21.216052] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10907 11:42:24.391991 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10908 11:42:24.409394 <30>[ 21.243399] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10909 11:42:24.416026 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10910 11:42:24.433759 <30>[ 21.268051] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10911 11:42:24.443930 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10912 11:42:24.463639 <30>[ 21.297803] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10913 11:42:24.473324 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10914 11:42:24.489520 <30>[ 21.323848] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10915 11:42:24.499355 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10916 11:42:24.553274 <30>[ 21.387328] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10917 11:42:24.559782 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10918 11:42:24.579113 <30>[ 21.413352] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10919 11:42:24.585988 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10920 11:42:24.641301 <30>[ 21.475400] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10921 11:42:24.647709 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10922 11:42:24.675708 <30>[ 21.503426] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10923 11:42:24.688256 <30>[ 21.522159] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10924 11:42:24.698093 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10925 11:42:24.715895 <30>[ 21.549866] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10926 11:42:24.722116 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10927 11:42:24.765261 <30>[ 21.599563] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10928 11:42:24.771648 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10929 11:42:24.795981 <30>[ 21.630035] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10930 11:42:24.805732 Starting [0;1;39mmodpr<6>[ 21.639530] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10931 11:42:24.812164 obe@drm.service[0m - Load Kernel Module drm...
10932 11:42:24.831888 <30>[ 21.665848] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10933 11:42:24.838226 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10934 11:42:24.859959 <30>[ 21.693907] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10935 11:42:24.866617 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10936 11:42:24.887843 <30>[ 21.721868] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10937 11:42:24.893963 Startin<6>[ 21.730791] fuse: init (API version 7.37)
10938 11:42:24.900834 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10939 11:42:24.921651 <30>[ 21.756070] systemd[1]: Starting systemd-journald.service - Journal Service...
10940 11:42:24.928402 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10941 11:42:24.951204 <30>[ 21.785287] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10942 11:42:24.957935 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10943 11:42:25.024775 <30>[ 21.855749] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10944 11:42:25.031443 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10945 11:42:25.052057 <30>[ 21.886620] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10946 11:42:25.062470 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10947 11:42:25.084838 <30>[ 21.918511] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10948 11:42:25.094902 <3>[ 21.925914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 11:42:25.101635 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10950 11:42:25.124526 <30>[ 21.958758] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10951 11:42:25.130902 <3>[ 21.960271] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:42:25.140971 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10953 11:42:25.157700 <30>[ 21.991597] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10954 11:42:25.164334 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10955 11:42:25.179726 <3>[ 22.014189] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 11:42:25.189787 <30>[ 22.023621] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10957 11:42:25.196478 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10958 11:42:25.209080 <3>[ 22.043038] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:42:25.218835 <30>[ 22.052692] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10960 11:42:25.228570 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10961 11:42:25.241480 <3>[ 22.075567] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:42:25.251699 <30>[ 22.085967] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10963 11:42:25.258424 <30>[ 22.093806] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10964 11:42:25.275256 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Modu<3>[ 22.108631] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:42:25.278274 le configfs.
10966 11:42:25.293918 <30>[ 22.128216] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10967 11:42:25.300872 <30>[ 22.135891] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10968 11:42:25.311490 <3>[ 22.142985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 11:42:25.317783 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10970 11:42:25.338265 <30>[ 22.172491] systemd[1]: modprobe@drm.service: Deactivated successfully.
10971 11:42:25.345058 <3>[ 22.177409] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:42:25.354786 <30>[ 22.179892] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10973 11:42:25.361403 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10974 11:42:25.379169 <3>[ 22.213467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 11:42:25.389119 <30>[ 22.223441] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10976 11:42:25.399740 <30>[ 22.231588] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10977 11:42:25.409887 [[0;32m OK [0m] Finished [0<3>[ 22.243061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 11:42:25.416144 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10979 11:42:25.434129 <30>[ 22.268190] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10980 11:42:25.440547 <30>[ 22.275711] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10981 11:42:25.450717 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10982 11:42:25.465717 <30>[ 22.299773] systemd[1]: Started systemd-journald.service - Journal Service.
10983 11:42:25.472104 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10984 11:42:25.491531 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10985 11:42:25.510241 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10986 11:42:25.529987 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10987 11:42:25.554063 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10988 11:42:25.578271 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10989 11:42:25.625531 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10990 11:42:25.647931 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10991 11:42:25.668391 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10992 11:42:25.685492 <4>[ 22.512573] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10993 11:42:25.691591 <3>[ 22.528294] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10994 11:42:25.702092 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10995 11:42:25.727966 <46>[ 22.562469] systemd-journald[299]: Received client request to flush runtime journal.
10996 11:42:25.734817 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10997 11:42:25.757316 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10998 11:42:25.784437 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10999 11:42:25.805538 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11000 11:42:25.825429 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11001 11:42:25.845210 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11002 11:42:25.861288 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11003 11:42:25.909402 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11004 11:42:25.973381 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11005 11:42:25.989309 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11006 11:42:26.008711 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11007 11:42:26.049435 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11008 11:42:26.068443 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11009 11:42:26.086350 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11010 11:42:26.105658 See 'systemctl status systemd-binfmt.service' for details.
11011 11:42:26.130541 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11012 11:42:26.947398 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11013 11:42:27.007090 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11014 11:42:27.071717 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11015 11:42:27.737713 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11016 11:42:27.744587 <6>[ 24.581338] remoteproc remoteproc0: powering up scp
11017 11:42:27.754359 <4>[ 24.587121] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11018 11:42:27.761017 <3>[ 24.597043] remoteproc remoteproc0: request_firmware failed: -2
11019 11:42:27.767551 <3>[ 24.603227] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11020 11:42:27.777609 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11021 11:42:27.829326 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11022 11:42:27.845108 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11023 11:42:27.868313 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11024 11:42:27.888040 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11025 11:42:27.908772 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11026 11:42:27.948691 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11027 11:42:28.627578 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11028 11:42:29.493035 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11029 11:42:29.557149 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11030 11:42:30.797307 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11031 11:42:30.857344 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11032 11:42:30.879413 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11033 11:42:31.002478 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11034 11:42:31.015370 <46>[ 27.853408] systemd-journald[299]: Time jumped backwards, rotating.
11035 11:42:31.028029 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11036 11:42:31.880096 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11037 11:42:31.897028 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11038 11:42:32.614884 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11039 11:42:32.634750 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11040 11:42:32.652268 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11041 11:42:32.671571 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11042 11:42:32.691788 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11043 11:42:32.708598 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11044 11:42:32.724617 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11045 11:42:32.742714 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11046 11:42:32.760422 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11047 11:42:32.776334 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11048 11:42:32.821734 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11049 11:42:32.859169 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11050 11:42:32.901105 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11051 11:42:32.923959 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11052 11:42:33.394175 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11053 11:42:33.441186 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11054 11:42:33.466099 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11055 11:42:33.488955 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11056 11:42:33.509511 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11057 11:42:33.536284 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11058 11:42:33.554747 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11059 11:42:33.861592 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11060 11:42:33.880747 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11061 11:42:33.938413 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11062 11:42:33.964231 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11063 11:42:34.409364 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11064 11:42:35.114028 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11065 11:42:35.199601
11066 11:42:35.200287
11067 11:42:35.202587 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11068 11:42:35.203185
11069 11:42:35.206171 debian-bookworm-arm64 login: root (automatic login)
11070 11:42:35.206821
11071 11:42:35.207413
11072 11:42:35.441556 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
11073 11:42:35.441716
11074 11:42:35.447836 The programs included with the Debian GNU/Linux system are free software;
11075 11:42:35.454530 the exact distribution terms for each program are described in the
11076 11:42:35.458049 individual files in /usr/share/doc/*/copyright.
11077 11:42:35.458188
11078 11:42:35.464433 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11079 11:42:35.467909 permitted by applicable law.
11080 11:42:37.863386 Matched prompt #10: / #
11082 11:42:37.863981 Setting prompt string to ['/ #']
11083 11:42:37.864182 end: 2.2.5.1 login-action (duration 00:00:35) [common]
11085 11:42:37.864663 end: 2.2.5 auto-login-action (duration 00:00:36) [common]
11086 11:42:37.864853 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
11087 11:42:37.865007 Setting prompt string to ['/ #']
11088 11:42:37.865145 Forcing a shell prompt, looking for ['/ #']
11090 11:42:37.915571 / #
11091 11:42:37.915810 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11092 11:42:37.915997 Waiting using forced prompt support (timeout 00:02:30)
11093 11:42:37.920448
11094 11:42:37.920855 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11095 11:42:37.921028 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
11097 11:42:38.021698 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742214/extract-nfsrootfs-9pw3phm6'
11098 11:42:38.028321 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742214/extract-nfsrootfs-9pw3phm6'
11100 11:42:38.130108 / # export NFS_SERVER_IP='192.168.201.1'
11101 11:42:38.136471 export NFS_SERVER_IP='192.168.201.1'
11102 11:42:38.137292 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11103 11:42:38.137793 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
11104 11:42:38.138255 end: 2 depthcharge-action (duration 00:01:30) [common]
11105 11:42:38.138716 start: 3 lava-test-retry (timeout 00:07:47) [common]
11106 11:42:38.139156 start: 3.1 lava-test-shell (timeout 00:07:47) [common]
11107 11:42:38.139537 Using namespace: common
11109 11:42:38.240585 / # #
11110 11:42:38.241166 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11111 11:42:38.246172 #
11112 11:42:38.246892 Using /lava-10742214
11114 11:42:38.347936 / # export SHELL=/bin/bash
11115 11:42:38.353753 export SHELL=/bin/bash
11117 11:42:38.455176 / # . /lava-10742214/environment
11118 11:42:38.460975 . /lava-10742214/environment
11120 11:42:38.567500 / # /lava-10742214/bin/lava-test-runner /lava-10742214/0
11121 11:42:38.568130 Test shell timeout: 10s (minimum of the action and connection timeout)
11122 11:42:38.574131 /lava-10742214/bin/lava-test-runner /lava-10742214/0
11123 11:42:38.791575 + export TESTRUN_ID=0_timesync-off
11124 11:42:38.794719 + TESTRUN_ID=0_timesync-off
11125 11:42:38.797736 + cd /lava-10742214/0/tests/0_timesync-off
11126 11:42:38.801300 ++ cat uuid
11127 11:42:38.804538 + UUID=10742214_1.6.2.3.1
11128 11:42:38.804633 + set +x
11129 11:42:38.807856 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10742214_1.6.2.3.1>
11130 11:42:38.808139 Received signal: <STARTRUN> 0_timesync-off 10742214_1.6.2.3.1
11131 11:42:38.808242 Starting test lava.0_timesync-off (10742214_1.6.2.3.1)
11132 11:42:38.808362 Skipping test definition patterns.
11133 11:42:38.810930 + systemctl stop systemd-timesyncd
11134 11:42:38.850032 + set +x
11135 11:42:38.853482 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10742214_1.6.2.3.1>
11136 11:42:38.853769 Received signal: <ENDRUN> 0_timesync-off 10742214_1.6.2.3.1
11137 11:42:38.853883 Ending use of test pattern.
11138 11:42:38.853975 Ending test lava.0_timesync-off (10742214_1.6.2.3.1), duration 0.05
11140 11:42:38.906014 + export TESTRUN_ID=1_kselftest-alsa
11141 11:42:38.909489 + TESTRUN_ID=1_kselftest-alsa
11142 11:42:38.915990 + cd /lava-10742214/0/tests/1_kselftest-alsa
11143 11:42:38.916102 ++ cat uuid
11144 11:42:38.918954 + UUID=10742214_1.6.2.3.5
11145 11:42:38.919059 + set +x
11146 11:42:38.922536 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10742214_1.6.2.3.5>
11147 11:42:38.922810 Received signal: <STARTRUN> 1_kselftest-alsa 10742214_1.6.2.3.5
11148 11:42:38.922907 Starting test lava.1_kselftest-alsa (10742214_1.6.2.3.5)
11149 11:42:38.923023 Skipping test definition patterns.
11150 11:42:38.925671 + cd ./automated/linux/kselftest/
11151 11:42:38.952541 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11152 11:42:38.984468 INFO: install_deps skipped
11153 11:42:39.452437 --2023-06-15 11:42:39-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11154 11:42:39.455497 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11155 11:42:39.578821 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11156 11:42:39.708132 HTTP request sent, awaiting response... 200 OK
11157 11:42:39.711686 Length: 2884276 (2.8M) [application/octet-stream]
11158 11:42:39.715030 Saving to: 'kselftest.tar.xz'
11159 11:42:39.715459
11160 11:42:39.715802
11161 11:42:39.966842 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11162 11:42:40.227741 kselftest.tar.xz 1%[ ] 49.22K 192KB/s
11163 11:42:40.662991 kselftest.tar.xz 7%[> ] 217.50K 420KB/s
11164 11:42:40.874302 kselftest.tar.xz 26%[====> ] 735.04K 771KB/s
11165 11:42:41.021232 kselftest.tar.xz 83%[===============> ] 2.31M 1.98MB/s
11166 11:42:41.027768 kselftest.tar.xz 100%[===================>] 2.75M 2.10MB/s in 1.3s
11167 11:42:41.028209
11168 11:42:41.277059 2023-06-15 11:42:41 (2.10 MB/s) - 'kselftest.tar.xz' saved [2884276/2884276]
11169 11:42:41.277282
11170 11:42:46.554510 skiplist:
11171 11:42:46.558005 ========================================
11172 11:42:46.560745 ========================================
11173 11:42:46.604315 alsa:mixer-test
11174 11:42:46.623168 ============== Tests to run ===============
11175 11:42:46.623666 alsa:mixer-test
11176 11:42:46.626423 ===========End Tests to run ===============
11177 11:42:46.717000 <12>[ 43.556682] kselftest: Running tests in alsa
11178 11:42:46.725751 TAP version 13
11179 11:42:46.738816 1..1
11180 11:42:46.752035 # selftests: alsa: mixer-test
11181 11:42:47.162755 # TAP version 13
11182 11:42:47.162917 # 1..0
11183 11:42:47.169053 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11184 11:42:47.172483 ok 1 selftests: alsa: mixer-test
11185 11:42:47.795608 alsa_mixer-test pass
11186 11:42:47.827397 + ../../utils/send-to-lava.sh ./output/result.txt
11187 11:42:47.886019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11188 11:42:47.886482 + set +x
11189 11:42:47.887095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11191 11:42:47.892246 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10742214_1.6.2.3.5>
11192 11:42:47.893034 Received signal: <ENDRUN> 1_kselftest-alsa 10742214_1.6.2.3.5
11193 11:42:47.893427 Ending use of test pattern.
11194 11:42:47.893744 Ending test lava.1_kselftest-alsa (10742214_1.6.2.3.5), duration 8.97
11196 11:42:47.895593 <LAVA_TEST_RUNNER EXIT>
11197 11:42:47.896255 ok: lava_test_shell seems to have completed
11198 11:42:47.896781 alsa_mixer-test: pass
11199 11:42:47.897191 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11200 11:42:47.897619 end: 3 lava-test-retry (duration 00:00:10) [common]
11201 11:42:47.898060 start: 4 finalize (timeout 00:07:37) [common]
11202 11:42:47.898496 start: 4.1 power-off (timeout 00:00:30) [common]
11203 11:42:47.899230 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11204 11:42:48.019490 >> Command sent successfully.
11205 11:42:48.031289 Returned 0 in 0 seconds
11206 11:42:48.132693 end: 4.1 power-off (duration 00:00:00) [common]
11208 11:42:48.134073 start: 4.2 read-feedback (timeout 00:07:37) [common]
11209 11:42:48.135269 Listened to connection for namespace 'common' for up to 1s
11210 11:42:49.135812 Finalising connection for namespace 'common'
11211 11:42:49.135988 Disconnecting from shell: Finalise
11212 11:42:49.136088 / #
11213 11:42:49.236412 end: 4.2 read-feedback (duration 00:00:01) [common]
11214 11:42:49.236675 end: 4 finalize (duration 00:00:01) [common]
11215 11:42:49.236844 Cleaning after the job
11216 11:42:49.236981 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/ramdisk
11217 11:42:49.240138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/kernel
11218 11:42:49.252465 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/dtb
11219 11:42:49.252769 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/nfsrootfs
11220 11:42:49.332066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742214/tftp-deploy-1tj29zfq/modules
11221 11:42:49.338161 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742214
11222 11:42:50.084291 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742214
11223 11:42:50.084995 Job finished correctly