Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
- Errors: 0
1 11:43:29.081233 lava-dispatcher, installed at version: 2023.05.1
2 11:43:29.081471 start: 0 validate
3 11:43:29.081611 Start time: 2023-06-15 11:43:29.081603+00:00 (UTC)
4 11:43:29.081746 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:43:29.081882 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 11:43:29.352002 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:43:29.352202 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:43:29.609731 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:43:29.609980 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:43:30.102762 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:43:30.103051 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:43:30.380793 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:43:30.381030 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:43:30.384531 validate duration: 1.30
16 11:43:30.384902 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:43:30.385049 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:43:30.385184 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:43:30.385362 Not decompressing ramdisk as can be used compressed.
20 11:43:30.385493 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/initrd.cpio.gz
21 11:43:30.385603 saving as /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/ramdisk/initrd.cpio.gz
22 11:43:30.385703 total size: 4665397 (4MB)
23 11:43:30.387266 progress 0% (0MB)
24 11:43:30.389437 progress 5% (0MB)
25 11:43:30.390882 progress 10% (0MB)
26 11:43:30.392305 progress 15% (0MB)
27 11:43:30.393716 progress 20% (0MB)
28 11:43:30.395117 progress 25% (1MB)
29 11:43:30.396494 progress 30% (1MB)
30 11:43:30.397902 progress 35% (1MB)
31 11:43:30.399285 progress 40% (1MB)
32 11:43:30.400849 progress 45% (2MB)
33 11:43:30.402226 progress 50% (2MB)
34 11:43:30.403584 progress 55% (2MB)
35 11:43:30.425484 progress 60% (2MB)
36 11:43:30.426878 progress 65% (2MB)
37 11:43:30.428251 progress 70% (3MB)
38 11:43:30.429636 progress 75% (3MB)
39 11:43:30.430975 progress 80% (3MB)
40 11:43:30.432461 progress 85% (3MB)
41 11:43:30.433788 progress 90% (4MB)
42 11:43:30.435096 progress 95% (4MB)
43 11:43:30.436435 progress 100% (4MB)
44 11:43:30.436660 4MB downloaded in 0.05s (87.33MB/s)
45 11:43:30.436876 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:43:30.437277 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:43:30.437401 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:43:30.437531 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:43:30.437696 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:43:30.437804 saving as /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/kernel/Image
52 11:43:30.437896 total size: 47581696 (45MB)
53 11:43:30.437994 No compression specified
54 11:43:30.439537 progress 0% (0MB)
55 11:43:30.478299 progress 5% (2MB)
56 11:43:30.493188 progress 10% (4MB)
57 11:43:30.530633 progress 15% (6MB)
58 11:43:30.572137 progress 20% (9MB)
59 11:43:30.587515 progress 25% (11MB)
60 11:43:30.625918 progress 30% (13MB)
61 11:43:30.668689 progress 35% (15MB)
62 11:43:30.683333 progress 40% (18MB)
63 11:43:30.723413 progress 45% (20MB)
64 11:43:30.763344 progress 50% (22MB)
65 11:43:30.776814 progress 55% (24MB)
66 11:43:30.816399 progress 60% (27MB)
67 11:43:30.857936 progress 65% (29MB)
68 11:43:30.872113 progress 70% (31MB)
69 11:43:30.916205 progress 75% (34MB)
70 11:43:30.930361 progress 80% (36MB)
71 11:43:30.968831 progress 85% (38MB)
72 11:43:31.013211 progress 90% (40MB)
73 11:43:31.027332 progress 95% (43MB)
74 11:43:31.064110 progress 100% (45MB)
75 11:43:31.064327 45MB downloaded in 0.63s (72.44MB/s)
76 11:43:31.064550 end: 1.2.1 http-download (duration 00:00:01) [common]
78 11:43:31.064795 end: 1.2 download-retry (duration 00:00:01) [common]
79 11:43:31.064887 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:43:31.064978 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:43:31.065106 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:43:31.065177 saving as /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/dtb/mt8192-asurada-spherion-r0.dtb
83 11:43:31.065239 total size: 46924 (0MB)
84 11:43:31.065300 No compression specified
85 11:43:31.066389 progress 69% (0MB)
86 11:43:31.066669 progress 100% (0MB)
87 11:43:31.066825 0MB downloaded in 0.00s (28.26MB/s)
88 11:43:31.066947 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:43:31.067176 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:43:31.067262 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:43:31.067345 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:43:31.067457 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/full.rootfs.tar.xz
94 11:43:31.067526 saving as /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/nfsrootfs/full.rootfs.tar
95 11:43:31.067586 total size: 200816996 (191MB)
96 11:43:31.067647 Using unxz to decompress xz
97 11:43:31.071315 progress 0% (0MB)
98 11:43:31.905841 progress 5% (9MB)
99 11:43:32.428143 progress 10% (19MB)
100 11:43:33.529441 progress 15% (28MB)
101 11:43:34.250147 progress 20% (38MB)
102 11:43:34.792212 progress 25% (47MB)
103 11:43:36.306126 progress 30% (57MB)
104 11:43:37.344235 progress 35% (67MB)
105 11:43:38.459963 progress 40% (76MB)
106 11:43:39.280921 progress 45% (86MB)
107 11:43:40.576190 progress 50% (95MB)
108 11:43:41.270037 progress 55% (105MB)
109 11:43:42.023940 progress 60% (114MB)
110 11:43:42.155416 progress 65% (124MB)
111 11:43:42.316332 progress 70% (134MB)
112 11:43:42.408867 progress 75% (143MB)
113 11:43:42.486142 progress 80% (153MB)
114 11:43:42.566161 progress 85% (162MB)
115 11:43:42.697823 progress 90% (172MB)
116 11:43:43.015940 progress 95% (181MB)
117 11:43:43.651005 progress 100% (191MB)
118 11:43:43.657113 191MB downloaded in 12.59s (15.21MB/s)
119 11:43:43.657432 end: 1.4.1 http-download (duration 00:00:13) [common]
121 11:43:43.657851 end: 1.4 download-retry (duration 00:00:13) [common]
122 11:43:43.657976 start: 1.5 download-retry (timeout 00:09:47) [common]
123 11:43:43.658096 start: 1.5.1 http-download (timeout 00:09:47) [common]
124 11:43:43.658282 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:43:43.658384 saving as /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/modules/modules.tar
126 11:43:43.658476 total size: 8555256 (8MB)
127 11:43:43.658569 Using unxz to decompress xz
128 11:43:43.941462 progress 0% (0MB)
129 11:43:43.965826 progress 5% (0MB)
130 11:43:43.992234 progress 10% (0MB)
131 11:43:44.018421 progress 15% (1MB)
132 11:43:44.045943 progress 20% (1MB)
133 11:43:44.072317 progress 25% (2MB)
134 11:43:44.096958 progress 30% (2MB)
135 11:43:44.125784 progress 35% (2MB)
136 11:43:44.152348 progress 40% (3MB)
137 11:43:44.177489 progress 45% (3MB)
138 11:43:44.206257 progress 50% (4MB)
139 11:43:44.232827 progress 55% (4MB)
140 11:43:44.259837 progress 60% (4MB)
141 11:43:44.287336 progress 65% (5MB)
142 11:43:44.313621 progress 70% (5MB)
143 11:43:44.338414 progress 75% (6MB)
144 11:43:44.362297 progress 80% (6MB)
145 11:43:44.386788 progress 85% (6MB)
146 11:43:44.416470 progress 90% (7MB)
147 11:43:44.444783 progress 95% (7MB)
148 11:43:44.470527 progress 100% (8MB)
149 11:43:44.474938 8MB downloaded in 0.82s (9.99MB/s)
150 11:43:44.475207 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:43:44.475473 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:43:44.475566 start: 1.6 prepare-tftp-overlay (timeout 00:09:46) [common]
154 11:43:44.475661 start: 1.6.1 extract-nfsrootfs (timeout 00:09:46) [common]
155 11:44:11.698071 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10742248/extract-nfsrootfs-g598sjkx
156 11:44:11.698282 end: 1.6.1 extract-nfsrootfs (duration 00:00:27) [common]
157 11:44:11.698382 start: 1.6.2 lava-overlay (timeout 00:09:19) [common]
158 11:44:11.698547 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov
159 11:44:11.698675 makedir: /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin
160 11:44:11.698775 makedir: /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/tests
161 11:44:11.698872 makedir: /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/results
162 11:44:11.698973 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-add-keys
163 11:44:11.699115 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-add-sources
164 11:44:11.699243 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-background-process-start
165 11:44:11.699370 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-background-process-stop
166 11:44:11.699495 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-common-functions
167 11:44:11.699619 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-echo-ipv4
168 11:44:11.699743 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-install-packages
169 11:44:11.699865 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-installed-packages
170 11:44:11.699987 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-os-build
171 11:44:11.700109 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-probe-channel
172 11:44:11.700231 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-probe-ip
173 11:44:11.700379 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-target-ip
174 11:44:11.700504 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-target-mac
175 11:44:11.700847 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-target-storage
176 11:44:11.700975 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-test-case
177 11:44:11.701106 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-test-event
178 11:44:11.701228 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-test-feedback
179 11:44:11.701350 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-test-raise
180 11:44:11.701472 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-test-reference
181 11:44:11.701595 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-test-runner
182 11:44:11.701717 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-test-set
183 11:44:11.701846 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-test-shell
184 11:44:11.701971 Updating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-add-keys (debian)
185 11:44:11.865531 Updating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-add-sources (debian)
186 11:44:11.865818 Updating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-install-packages (debian)
187 11:44:11.866015 Updating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-installed-packages (debian)
188 11:44:11.866203 Updating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/bin/lava-os-build (debian)
189 11:44:11.866374 Creating /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/environment
190 11:44:11.866626 LAVA metadata
191 11:44:11.866758 - LAVA_JOB_ID=10742248
192 11:44:11.866860 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:44:11.867016 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:19) [common]
194 11:44:11.867116 skipped lava-vland-overlay
195 11:44:11.867230 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:44:11.867347 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:19) [common]
197 11:44:11.867438 skipped lava-multinode-overlay
198 11:44:11.867546 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:44:11.867634 start: 1.6.2.3 test-definition (timeout 00:09:19) [common]
200 11:44:11.867716 Loading test definitions
201 11:44:11.867819 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:19) [common]
202 11:44:11.867924 Using /lava-10742248 at stage 0
203 11:44:11.868312 uuid=10742248_1.6.2.3.1 testdef=None
204 11:44:11.868434 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:44:11.868559 start: 1.6.2.3.2 test-overlay (timeout 00:09:19) [common]
206 11:44:11.869145 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:44:11.869432 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:19) [common]
209 11:44:11.870014 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:44:11.870313 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:19) [common]
212 11:44:12.791785 runner path: /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/0/tests/0_timesync-off test_uuid 10742248_1.6.2.3.1
213 11:44:12.792047 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:01) [common]
215 11:44:12.792446 start: 1.6.2.3.5 git-repo-action (timeout 00:09:18) [common]
216 11:44:12.792574 Using /lava-10742248 at stage 0
217 11:44:12.792683 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:44:12.792791 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/0/tests/1_kselftest-rtc'
219 11:44:36.751228 Running '/usr/bin/git checkout kernelci.org
220 11:44:36.795247 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 11:44:36.795983 uuid=10742248_1.6.2.3.5 testdef=None
222 11:44:36.796145 end: 1.6.2.3.5 git-repo-action (duration 00:00:24) [common]
224 11:44:36.796397 start: 1.6.2.3.6 test-overlay (timeout 00:08:54) [common]
225 11:44:36.797167 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:44:36.797401 start: 1.6.2.3.7 test-install-overlay (timeout 00:08:54) [common]
228 11:44:36.803631 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:44:36.803872 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:08:54) [common]
231 11:44:36.816018 runner path: /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/0/tests/1_kselftest-rtc test_uuid 10742248_1.6.2.3.5
232 11:44:36.816140 BOARD='mt8192-asurada-spherion-r0'
233 11:44:36.816211 BRANCH='cip'
234 11:44:36.816273 SKIPFILE='/dev/null'
235 11:44:36.816334 SKIP_INSTALL='True'
236 11:44:36.816391 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:44:36.816451 TST_CASENAME=''
238 11:44:36.816508 TST_CMDFILES='rtc'
239 11:44:36.816680 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:44:36.816897 Creating lava-test-runner.conf files
242 11:44:36.816964 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742248/lava-overlay-3hujjkov/lava-10742248/0 for stage 0
243 11:44:36.817060 - 0_timesync-off
244 11:44:36.817135 - 1_kselftest-rtc
245 11:44:36.817236 end: 1.6.2.3 test-definition (duration 00:00:25) [common]
246 11:44:36.817331 start: 1.6.2.4 compress-overlay (timeout 00:08:54) [common]
247 11:44:45.522681 end: 1.6.2.4 compress-overlay (duration 00:00:09) [common]
248 11:44:45.522882 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:08:45) [common]
249 11:44:45.523006 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:44:45.523135 end: 1.6.2 lava-overlay (duration 00:00:34) [common]
251 11:44:45.523257 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:45) [common]
252 11:44:46.349254 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
253 11:44:46.349652 start: 1.6.4 extract-modules (timeout 00:08:44) [common]
254 11:44:46.349804 extracting modules file /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742248/extract-nfsrootfs-g598sjkx
255 11:44:52.185351 extracting modules file /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742248/extract-overlay-ramdisk-8lpq2xw0/ramdisk
256 11:44:55.100794 end: 1.6.4 extract-modules (duration 00:00:09) [common]
257 11:44:55.101074 start: 1.6.5 apply-overlay-tftp (timeout 00:08:35) [common]
258 11:44:55.101244 [common] Applying overlay to NFS
259 11:44:55.101372 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742248/compress-overlay-18df4py4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742248/extract-nfsrootfs-g598sjkx
260 11:45:02.202872 end: 1.6.5 apply-overlay-tftp (duration 00:00:07) [common]
261 11:45:02.203126 start: 1.6.6 configure-preseed-file (timeout 00:08:28) [common]
262 11:45:02.203268 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:45:02.203405 start: 1.6.7 compress-ramdisk (timeout 00:08:28) [common]
264 11:45:02.203518 Building ramdisk /var/lib/lava/dispatcher/tmp/10742248/extract-overlay-ramdisk-8lpq2xw0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742248/extract-overlay-ramdisk-8lpq2xw0/ramdisk
265 11:45:05.858436 >> 117806 blocks
266 11:45:08.156665 rename /var/lib/lava/dispatcher/tmp/10742248/extract-overlay-ramdisk-8lpq2xw0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/ramdisk/ramdisk.cpio.gz
267 11:45:08.157976 end: 1.6.7 compress-ramdisk (duration 00:00:06) [common]
268 11:45:08.158412 start: 1.6.8 prepare-kernel (timeout 00:08:22) [common]
269 11:45:08.158793 start: 1.6.8.1 prepare-fit (timeout 00:08:22) [common]
270 11:45:08.159179 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/kernel/Image'
271 11:45:22.361713 Returned 0 in 14 seconds
272 11:45:22.462531 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/kernel/image.itb
273 11:45:26.945772 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:45:26.946160 output: Created: Thu Jun 15 12:45:26 2023
275 11:45:26.946272 output: Image 0 (kernel-1)
276 11:45:26.946367 output: Description:
277 11:45:26.946468 output: Created: Thu Jun 15 12:45:26 2023
278 11:45:26.946559 output: Type: Kernel Image
279 11:45:26.946657 output: Compression: lzma compressed
280 11:45:26.946724 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
281 11:45:26.946784 output: Architecture: AArch64
282 11:45:26.946844 output: OS: Linux
283 11:45:26.946923 output: Load Address: 0x00000000
284 11:45:26.946984 output: Entry Point: 0x00000000
285 11:45:26.947064 output: Hash algo: crc32
286 11:45:26.947160 output: Hash value: cd22d0e5
287 11:45:26.947264 output: Image 1 (fdt-1)
288 11:45:26.947347 output: Description: mt8192-asurada-spherion-r0
289 11:45:26.947440 output: Created: Thu Jun 15 12:45:26 2023
290 11:45:26.947523 output: Type: Flat Device Tree
291 11:45:26.947606 output: Compression: uncompressed
292 11:45:26.947699 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 11:45:26.947782 output: Architecture: AArch64
294 11:45:26.947864 output: Hash algo: crc32
295 11:45:26.947962 output: Hash value: 1df858fa
296 11:45:26.948045 output: Image 2 (ramdisk-1)
297 11:45:26.948132 output: Description: unavailable
298 11:45:26.948221 output: Created: Thu Jun 15 12:45:26 2023
299 11:45:26.948303 output: Type: RAMDisk Image
300 11:45:26.948393 output: Compression: Unknown Compression
301 11:45:26.948479 output: Data Size: 17645382 Bytes = 17231.82 KiB = 16.83 MiB
302 11:45:26.948585 output: Architecture: AArch64
303 11:45:26.948660 output: OS: Linux
304 11:45:26.948716 output: Load Address: unavailable
305 11:45:26.948770 output: Entry Point: unavailable
306 11:45:26.948824 output: Hash algo: crc32
307 11:45:26.948888 output: Hash value: c510b8bf
308 11:45:26.948948 output: Default Configuration: 'conf-1'
309 11:45:26.949002 output: Configuration 0 (conf-1)
310 11:45:26.949055 output: Description: mt8192-asurada-spherion-r0
311 11:45:26.949110 output: Kernel: kernel-1
312 11:45:26.949177 output: Init Ramdisk: ramdisk-1
313 11:45:26.949230 output: FDT: fdt-1
314 11:45:26.949283 output: Loadables: kernel-1
315 11:45:26.949337 output:
316 11:45:26.949552 end: 1.6.8.1 prepare-fit (duration 00:00:19) [common]
317 11:45:26.949669 end: 1.6.8 prepare-kernel (duration 00:00:19) [common]
318 11:45:26.949777 end: 1.6 prepare-tftp-overlay (duration 00:01:42) [common]
319 11:45:26.949884 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:03) [common]
320 11:45:26.949969 No LXC device requested
321 11:45:26.950051 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:45:26.950150 start: 1.8 deploy-device-env (timeout 00:08:03) [common]
323 11:45:26.950235 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:45:26.950302 Checking files for TFTP limit of 4294967296 bytes.
325 11:45:26.950966 end: 1 tftp-deploy (duration 00:01:57) [common]
326 11:45:26.951103 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:45:26.951242 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:45:26.951423 substitutions:
329 11:45:26.951522 - {DTB}: 10742248/tftp-deploy-n56okomi/dtb/mt8192-asurada-spherion-r0.dtb
330 11:45:26.951622 - {INITRD}: 10742248/tftp-deploy-n56okomi/ramdisk/ramdisk.cpio.gz
331 11:45:26.951717 - {KERNEL}: 10742248/tftp-deploy-n56okomi/kernel/Image
332 11:45:26.951804 - {LAVA_MAC}: None
333 11:45:26.951901 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10742248/extract-nfsrootfs-g598sjkx
334 11:45:26.951988 - {NFS_SERVER_IP}: 192.168.201.1
335 11:45:26.952073 - {PRESEED_CONFIG}: None
336 11:45:26.952168 - {PRESEED_LOCAL}: None
337 11:45:26.952253 - {RAMDISK}: 10742248/tftp-deploy-n56okomi/ramdisk/ramdisk.cpio.gz
338 11:45:26.952338 - {ROOT_PART}: None
339 11:45:26.952434 - {ROOT}: None
340 11:45:26.952540 - {SERVER_IP}: 192.168.201.1
341 11:45:26.952646 - {TEE}: None
342 11:45:26.952710 Parsed boot commands:
343 11:45:26.952768 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:45:26.952957 Parsed boot commands: tftpboot 192.168.201.1 10742248/tftp-deploy-n56okomi/kernel/image.itb 10742248/tftp-deploy-n56okomi/kernel/cmdline
345 11:45:26.953053 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:45:26.953144 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:45:26.953245 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:45:26.953339 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:45:26.953428 Not connected, no need to disconnect.
350 11:45:26.953506 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:45:26.953588 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:45:26.953676 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 11:45:26.957204 Setting prompt string to ['lava-test: # ']
354 11:45:26.957556 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:45:26.957699 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:45:26.957842 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:45:26.957964 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:45:26.958304 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 11:45:32.106264 >> Command sent successfully.
360 11:45:32.117097 Returned 0 in 5 seconds
361 11:45:32.218339 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:45:32.220296 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:45:32.220998 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:45:32.221594 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:45:32.222077 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:45:32.222571 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:45:32.224250 [Enter `^Ec?' for help]
369 11:45:32.382296
370 11:45:32.382931
371 11:45:32.383297 F0: 102B 0000
372 11:45:32.383636
373 11:45:32.383954 F3: 1001 0000 [0200]
374 11:45:32.384271
375 11:45:32.385455 F3: 1001 0000
376 11:45:32.385942
377 11:45:32.386311 F7: 102D 0000
378 11:45:32.386643
379 11:45:32.388596 F1: 0000 0000
380 11:45:32.389035
381 11:45:32.389378 V0: 0000 0000 [0001]
382 11:45:32.389701
383 11:45:32.391990 00: 0007 8000
384 11:45:32.392556
385 11:45:32.393026 01: 0000 0000
386 11:45:32.393283
387 11:45:32.395270 BP: 0C00 0209 [0000]
388 11:45:32.395579
389 11:45:32.395827 G0: 1182 0000
390 11:45:32.396062
391 11:45:32.398822 EC: 0000 0021 [4000]
392 11:45:32.399132
393 11:45:32.399479 S7: 0000 0000 [0000]
394 11:45:32.399741
395 11:45:32.402066 CC: 0000 0000 [0001]
396 11:45:32.402467
397 11:45:32.402805 T0: 0000 0040 [010F]
398 11:45:32.403050
399 11:45:32.403369 Jump to BL
400 11:45:32.405580
401 11:45:32.428810
402 11:45:32.429153
403 11:45:32.429407
404 11:45:32.436258 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:45:32.440174 ARM64: Exception handlers installed.
406 11:45:32.443680 ARM64: Testing exception
407 11:45:32.447154 ARM64: Done test exception
408 11:45:32.454966 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:45:32.464922 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:45:32.471486 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:45:32.481163 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:45:32.487736 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:45:32.494417 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:45:32.505225 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:45:32.511850 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:45:32.532024 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:45:32.535066 WDT: Last reset was cold boot
418 11:45:32.538629 SPI1(PAD0) initialized at 2873684 Hz
419 11:45:32.541798 SPI5(PAD0) initialized at 992727 Hz
420 11:45:32.545000 VBOOT: Loading verstage.
421 11:45:32.551396 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:45:32.555278 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:45:32.558236 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:45:32.561454 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:45:32.569297 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:45:32.575715 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:45:32.586708 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:45:32.587281
429 11:45:32.587680
430 11:45:32.596553 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:45:32.599736 ARM64: Exception handlers installed.
432 11:45:32.603432 ARM64: Testing exception
433 11:45:32.604132 ARM64: Done test exception
434 11:45:32.610294 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:45:32.613256 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:45:32.627517 Probing TPM: . done!
437 11:45:32.628099 TPM ready after 0 ms
438 11:45:32.634797 Connected to device vid:did:rid of 1ae0:0028:00
439 11:45:32.644358 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 11:45:32.683630 Initialized TPM device CR50 revision 0
441 11:45:32.694539 tlcl_send_startup: Startup return code is 0
442 11:45:32.694780 TPM: setup succeeded
443 11:45:32.707208 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:45:32.715836 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:45:32.726557 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:45:32.734790 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:45:32.738178 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:45:32.741750 in-header: 03 07 00 00 08 00 00 00
449 11:45:32.744689 in-data: aa e4 47 04 13 02 00 00
450 11:45:32.748244 Chrome EC: UHEPI supported
451 11:45:32.755106 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:45:32.758014 in-header: 03 ad 00 00 08 00 00 00
453 11:45:32.762045 in-data: 00 20 20 08 00 00 00 00
454 11:45:32.762480 Phase 1
455 11:45:32.764957 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:45:32.771763 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:45:32.778390 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:45:32.781851 Recovery requested (1009000e)
459 11:45:32.785951 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:45:32.793866 tlcl_extend: response is 0
461 11:45:32.802115 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:45:32.807102 tlcl_extend: response is 0
463 11:45:32.813644 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:45:32.834220 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:45:32.841411 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:45:32.842006
467 11:45:32.842509
468 11:45:32.851552 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:45:32.854588 ARM64: Exception handlers installed.
470 11:45:32.858194 ARM64: Testing exception
471 11:45:32.858994 ARM64: Done test exception
472 11:45:32.880333 pmic_efuse_setting: Set efuses in 11 msecs
473 11:45:32.883608 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:45:32.890901 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:45:32.894001 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:45:32.896954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:45:32.903863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:45:32.907199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:45:32.913880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:45:32.917528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:45:32.923701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:45:32.927113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:45:32.930820 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:45:32.937380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:45:32.940458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:45:32.943924 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:45:32.951236 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:45:32.957935 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:45:32.964221 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:45:32.967762 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:45:32.974222 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:45:32.980853 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:45:32.984386 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:45:32.990860 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:45:32.997679 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:45:33.001814 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:45:33.009108 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:45:33.012235 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:45:33.018868 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:45:33.025822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:45:33.029151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:45:33.032431 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:45:33.039662 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:45:33.043086 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:45:33.049704 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:45:33.053238 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:45:33.059652 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:45:33.063177 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:45:33.070331 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:45:33.073766 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:45:33.077434 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:45:33.083917 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:45:33.087524 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:45:33.090926 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:45:33.097612 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:45:33.101101 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:45:33.103891 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:45:33.110779 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:45:33.114108 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:45:33.117362 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:45:33.120646 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:45:33.127477 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:45:33.130834 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:45:33.134215 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:45:33.144191 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:45:33.150629 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:45:33.157519 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:45:33.164049 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:45:33.173924 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:45:33.177459 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:45:33.180724 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:45:33.187134 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:45:33.193950 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x23
534 11:45:33.196840 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:45:33.204321 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 11:45:33.207686 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:45:33.216865 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 11:45:33.226652 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 11:45:33.235938 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 11:45:33.245671 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 11:45:33.254916 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 11:45:33.264456 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 11:45:33.273911 [RTC]rtc_get_frequency_meter,154: input=13, output=804
544 11:45:33.277348 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 11:45:33.284946 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 11:45:33.287998 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:45:33.290932 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:45:33.297899 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:45:33.301155 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:45:33.304495 ADC[4]: Raw value=905988 ID=7
551 11:45:33.304993 ADC[3]: Raw value=213282 ID=1
552 11:45:33.307871 RAM Code: 0x71
553 11:45:33.310878 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:45:33.317527 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:45:33.324410 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:45:33.330959 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:45:33.334611 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:45:33.337981 in-header: 03 07 00 00 08 00 00 00
559 11:45:33.340810 in-data: aa e4 47 04 13 02 00 00
560 11:45:33.344311 Chrome EC: UHEPI supported
561 11:45:33.350864 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:45:33.354305 in-header: 03 dd 00 00 08 00 00 00
563 11:45:33.357964 in-data: 90 20 60 08 00 00 00 00
564 11:45:33.361302 MRC: failed to locate region type 0.
565 11:45:33.367512 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:45:33.371107 DRAM-K: Running full calibration
567 11:45:33.377637 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:45:33.378082 header.status = 0x0
569 11:45:33.380950 header.version = 0x6 (expected: 0x6)
570 11:45:33.384260 header.size = 0xd00 (expected: 0xd00)
571 11:45:33.387643 header.flags = 0x0
572 11:45:33.394587 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:45:33.410524 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 11:45:33.417331 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:45:33.420456 dram_init: ddr_geometry: 2
576 11:45:33.423748 [EMI] MDL number = 2
577 11:45:33.424269 [EMI] Get MDL freq = 0
578 11:45:33.427096 dram_init: ddr_type: 0
579 11:45:33.427595 is_discrete_lpddr4: 1
580 11:45:33.430476 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:45:33.430988
582 11:45:33.433786
583 11:45:33.434283 [Bian_co] ETT version 0.0.0.1
584 11:45:33.440625 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:45:33.441180
586 11:45:33.443908 dramc_set_vcore_voltage set vcore to 650000
587 11:45:33.446816 Read voltage for 800, 4
588 11:45:33.447331 Vio18 = 0
589 11:45:33.447803 Vcore = 650000
590 11:45:33.450240 Vdram = 0
591 11:45:33.450729 Vddq = 0
592 11:45:33.451180 Vmddr = 0
593 11:45:33.453786 dram_init: config_dvfs: 1
594 11:45:33.457164 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:45:33.463991 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:45:33.467023 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 11:45:33.470439 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 11:45:33.473586 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 11:45:33.477010 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 11:45:33.480608 MEM_TYPE=3, freq_sel=18
601 11:45:33.483924 sv_algorithm_assistance_LP4_1600
602 11:45:33.486789 ============ PULL DRAM RESETB DOWN ============
603 11:45:33.493615 ========== PULL DRAM RESETB DOWN end =========
604 11:45:33.496800 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:45:33.500042 ===================================
606 11:45:33.503701 LPDDR4 DRAM CONFIGURATION
607 11:45:33.506663 ===================================
608 11:45:33.507241 EX_ROW_EN[0] = 0x0
609 11:45:33.510110 EX_ROW_EN[1] = 0x0
610 11:45:33.510535 LP4Y_EN = 0x0
611 11:45:33.513463 WORK_FSP = 0x0
612 11:45:33.513888 WL = 0x2
613 11:45:33.516977 RL = 0x2
614 11:45:33.517532 BL = 0x2
615 11:45:33.520356 RPST = 0x0
616 11:45:33.520916 RD_PRE = 0x0
617 11:45:33.523209 WR_PRE = 0x1
618 11:45:33.526720 WR_PST = 0x0
619 11:45:33.527225 DBI_WR = 0x0
620 11:45:33.530144 DBI_RD = 0x0
621 11:45:33.530570 OTF = 0x1
622 11:45:33.533416 ===================================
623 11:45:33.536771 ===================================
624 11:45:33.537294 ANA top config
625 11:45:33.540198 ===================================
626 11:45:33.543276 DLL_ASYNC_EN = 0
627 11:45:33.546641 ALL_SLAVE_EN = 1
628 11:45:33.549918 NEW_RANK_MODE = 1
629 11:45:33.553267 DLL_IDLE_MODE = 1
630 11:45:33.553709 LP45_APHY_COMB_EN = 1
631 11:45:33.556738 TX_ODT_DIS = 1
632 11:45:33.559757 NEW_8X_MODE = 1
633 11:45:33.563170 ===================================
634 11:45:33.566697 ===================================
635 11:45:33.569503 data_rate = 1600
636 11:45:33.573106 CKR = 1
637 11:45:33.573529 DQ_P2S_RATIO = 8
638 11:45:33.576692 ===================================
639 11:45:33.579564 CA_P2S_RATIO = 8
640 11:45:33.582990 DQ_CA_OPEN = 0
641 11:45:33.586045 DQ_SEMI_OPEN = 0
642 11:45:33.589299 CA_SEMI_OPEN = 0
643 11:45:33.592841 CA_FULL_RATE = 0
644 11:45:33.593291 DQ_CKDIV4_EN = 1
645 11:45:33.596156 CA_CKDIV4_EN = 1
646 11:45:33.599586 CA_PREDIV_EN = 0
647 11:45:33.603142 PH8_DLY = 0
648 11:45:33.605970 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:45:33.609691 DQ_AAMCK_DIV = 4
650 11:45:33.609999 CA_AAMCK_DIV = 4
651 11:45:33.612826 CA_ADMCK_DIV = 4
652 11:45:33.616289 DQ_TRACK_CA_EN = 0
653 11:45:33.619445 CA_PICK = 800
654 11:45:33.622946 CA_MCKIO = 800
655 11:45:33.626343 MCKIO_SEMI = 0
656 11:45:33.629448 PLL_FREQ = 3068
657 11:45:33.630043 DQ_UI_PI_RATIO = 32
658 11:45:33.633415 CA_UI_PI_RATIO = 0
659 11:45:33.636032 ===================================
660 11:45:33.639554 ===================================
661 11:45:33.643225 memory_type:LPDDR4
662 11:45:33.646138 GP_NUM : 10
663 11:45:33.646728 SRAM_EN : 1
664 11:45:33.649518 MD32_EN : 0
665 11:45:33.652889 ===================================
666 11:45:33.653436 [ANA_INIT] >>>>>>>>>>>>>>
667 11:45:33.656134 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:45:33.659942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:45:33.662916 ===================================
670 11:45:33.666547 data_rate = 1600,PCW = 0X7600
671 11:45:33.669972 ===================================
672 11:45:33.672848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:45:33.679283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:45:33.686525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:45:33.689983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:45:33.693393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:45:33.696237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:45:33.699724 [ANA_INIT] flow start
679 11:45:33.700162 [ANA_INIT] PLL >>>>>>>>
680 11:45:33.703256 [ANA_INIT] PLL <<<<<<<<
681 11:45:33.706669 [ANA_INIT] MIDPI >>>>>>>>
682 11:45:33.707103 [ANA_INIT] MIDPI <<<<<<<<
683 11:45:33.709599 [ANA_INIT] DLL >>>>>>>>
684 11:45:33.713235 [ANA_INIT] flow end
685 11:45:33.716636 ============ LP4 DIFF to SE enter ============
686 11:45:33.719357 ============ LP4 DIFF to SE exit ============
687 11:45:33.722837 [ANA_INIT] <<<<<<<<<<<<<
688 11:45:33.726038 [Flow] Enable top DCM control >>>>>
689 11:45:33.729808 [Flow] Enable top DCM control <<<<<
690 11:45:33.733060 Enable DLL master slave shuffle
691 11:45:33.736356 ==============================================================
692 11:45:33.739199 Gating Mode config
693 11:45:33.745823 ==============================================================
694 11:45:33.746267 Config description:
695 11:45:33.755701 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:45:33.762490 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:45:33.766213 SELPH_MODE 0: By rank 1: By Phase
698 11:45:33.772831 ==============================================================
699 11:45:33.775787 GAT_TRACK_EN = 1
700 11:45:33.779225 RX_GATING_MODE = 2
701 11:45:33.782699 RX_GATING_TRACK_MODE = 2
702 11:45:33.785823 SELPH_MODE = 1
703 11:45:33.789283 PICG_EARLY_EN = 1
704 11:45:33.792215 VALID_LAT_VALUE = 1
705 11:45:33.795685 ==============================================================
706 11:45:33.799217 Enter into Gating configuration >>>>
707 11:45:33.802146 Exit from Gating configuration <<<<
708 11:45:33.805480 Enter into DVFS_PRE_config >>>>>
709 11:45:33.818786 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:45:33.822150 Exit from DVFS_PRE_config <<<<<
711 11:45:33.822589 Enter into PICG configuration >>>>
712 11:45:33.825519 Exit from PICG configuration <<<<
713 11:45:33.829072 [RX_INPUT] configuration >>>>>
714 11:45:33.831957 [RX_INPUT] configuration <<<<<
715 11:45:33.838584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:45:33.842581 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:45:33.849784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:45:33.857009 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:45:33.860172 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:45:33.867416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:45:33.871010 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:45:33.874956 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:45:33.878550 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:45:33.885765 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:45:33.889309 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:45:33.892961 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:45:33.896438 ===================================
728 11:45:33.899971 LPDDR4 DRAM CONFIGURATION
729 11:45:33.900406 ===================================
730 11:45:33.903402 EX_ROW_EN[0] = 0x0
731 11:45:33.907557 EX_ROW_EN[1] = 0x0
732 11:45:33.907995 LP4Y_EN = 0x0
733 11:45:33.910952 WORK_FSP = 0x0
734 11:45:33.911388 WL = 0x2
735 11:45:33.911736 RL = 0x2
736 11:45:33.914867 BL = 0x2
737 11:45:33.915394 RPST = 0x0
738 11:45:33.918235 RD_PRE = 0x0
739 11:45:33.918993 WR_PRE = 0x1
740 11:45:33.921886 WR_PST = 0x0
741 11:45:33.922409 DBI_WR = 0x0
742 11:45:33.925926 DBI_RD = 0x0
743 11:45:33.926491 OTF = 0x1
744 11:45:33.929700 ===================================
745 11:45:33.933372 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:45:33.936757 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:45:33.943451 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:45:33.947375 ===================================
749 11:45:33.947935 LPDDR4 DRAM CONFIGURATION
750 11:45:33.950853 ===================================
751 11:45:33.954751 EX_ROW_EN[0] = 0x10
752 11:45:33.955202 EX_ROW_EN[1] = 0x0
753 11:45:33.958318 LP4Y_EN = 0x0
754 11:45:33.958877 WORK_FSP = 0x0
755 11:45:33.961828 WL = 0x2
756 11:45:33.962398 RL = 0x2
757 11:45:33.965582 BL = 0x2
758 11:45:33.966308 RPST = 0x0
759 11:45:33.967006 RD_PRE = 0x0
760 11:45:33.969480 WR_PRE = 0x1
761 11:45:33.969928 WR_PST = 0x0
762 11:45:33.973515 DBI_WR = 0x0
763 11:45:33.973942 DBI_RD = 0x0
764 11:45:33.976706 OTF = 0x1
765 11:45:33.979885 ===================================
766 11:45:33.983728 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:45:33.989238 nWR fixed to 40
768 11:45:33.992605 [ModeRegInit_LP4] CH0 RK0
769 11:45:33.993011 [ModeRegInit_LP4] CH0 RK1
770 11:45:33.996375 [ModeRegInit_LP4] CH1 RK0
771 11:45:33.999939 [ModeRegInit_LP4] CH1 RK1
772 11:45:34.000605 match AC timing 13
773 11:45:34.003443 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:45:34.006681 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:45:34.013605 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:45:34.017593 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:45:34.020404 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:45:34.023756 [EMI DOE] emi_dcm 0
779 11:45:34.027198 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:45:34.027501 ==
781 11:45:34.030766 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:45:34.038098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:45:34.038344 ==
784 11:45:34.040959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:45:34.047477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:45:34.056101 [CA 0] Center 37 (6~68) winsize 63
787 11:45:34.059509 [CA 1] Center 37 (7~67) winsize 61
788 11:45:34.062826 [CA 2] Center 34 (4~65) winsize 62
789 11:45:34.066557 [CA 3] Center 34 (4~65) winsize 62
790 11:45:34.069717 [CA 4] Center 33 (3~64) winsize 62
791 11:45:34.073715 [CA 5] Center 33 (3~64) winsize 62
792 11:45:34.073805
793 11:45:34.076797 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 11:45:34.076875
795 11:45:34.080248 [CATrainingPosCal] consider 1 rank data
796 11:45:34.083066 u2DelayCellTimex100 = 270/100 ps
797 11:45:34.086664 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 11:45:34.089715 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
799 11:45:34.093205 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:45:34.099568 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:45:34.103133 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:45:34.106542 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:45:34.106620
804 11:45:34.109628 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:45:34.109711
806 11:45:34.113126 [CBTSetCACLKResult] CA Dly = 33
807 11:45:34.113209 CS Dly: 7 (0~38)
808 11:45:34.113281 ==
809 11:45:34.116491 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:45:34.122961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:45:34.123043 ==
812 11:45:34.126453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:45:34.133328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:45:34.142341 [CA 0] Center 37 (6~68) winsize 63
815 11:45:34.145667 [CA 1] Center 37 (7~68) winsize 62
816 11:45:34.149020 [CA 2] Center 34 (4~65) winsize 62
817 11:45:34.151960 [CA 3] Center 34 (4~65) winsize 62
818 11:45:34.155592 [CA 4] Center 33 (3~64) winsize 62
819 11:45:34.158824 [CA 5] Center 33 (3~64) winsize 62
820 11:45:34.158942
821 11:45:34.162186 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:45:34.162300
823 11:45:34.165782 [CATrainingPosCal] consider 2 rank data
824 11:45:34.169056 u2DelayCellTimex100 = 270/100 ps
825 11:45:34.172058 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 11:45:34.179004 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 11:45:34.182503 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:45:34.186095 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:45:34.189685 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:45:34.193307 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:45:34.193413
832 11:45:34.196885 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:45:34.196991
834 11:45:34.200548 [CBTSetCACLKResult] CA Dly = 33
835 11:45:34.200664 CS Dly: 7 (0~38)
836 11:45:34.200757
837 11:45:34.204679 ----->DramcWriteLeveling(PI) begin...
838 11:45:34.204810 ==
839 11:45:34.208376 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:45:34.211984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:45:34.212628 ==
842 11:45:34.215347 Write leveling (Byte 0): 33 => 33
843 11:45:34.218987 Write leveling (Byte 1): 29 => 29
844 11:45:34.221907 DramcWriteLeveling(PI) end<-----
845 11:45:34.222339
846 11:45:34.222687 ==
847 11:45:34.225382 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:45:34.228760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:45:34.229208 ==
850 11:45:34.232304 [Gating] SW mode calibration
851 11:45:34.238641 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:45:34.245367 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:45:34.248601 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:45:34.251998 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 11:45:34.258407 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 11:45:34.261826 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:45:34.265134 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:45:34.272332 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:45:34.274922 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:45:34.278384 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:45:34.285403 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:45:34.288265 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:45:34.291886 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:45:34.298288 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:45:34.301777 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:45:34.305311 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:45:34.308867 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:45:34.315365 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:45:34.318593 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:45:34.321879 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:45:34.328375 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 11:45:34.332090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:45:34.335429 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:45:34.341530 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:45:34.344981 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:45:34.348283 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:45:34.355133 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:45:34.358414 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:45:34.361938 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
880 11:45:34.368315 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
881 11:45:34.371534 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:45:34.374909 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:45:34.381605 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:45:34.385008 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:45:34.388234 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:45:34.394773 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 11:45:34.398343 0 10 8 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)
888 11:45:34.401988 0 10 12 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
889 11:45:34.408497 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:45:34.411423 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:45:34.414992 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:45:34.421325 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:45:34.424629 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:45:34.427640 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 11:45:34.431107 0 11 8 | B1->B0 | 2424 3b3b | 1 1 | (0 0) (0 0)
896 11:45:34.437981 0 11 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
897 11:45:34.441226 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:45:34.444506 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:45:34.450937 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:45:34.454943 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:45:34.457784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:45:34.464398 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:45:34.467801 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 11:45:34.471244 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:45:34.478235 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:45:34.481201 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:45:34.484353 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:45:34.491415 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:45:34.494704 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:45:34.497704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:45:34.504756 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:45:34.508425 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:45:34.511819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:45:34.515412 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:45:34.522084 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:45:34.526248 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:45:34.530168 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:45:34.533925 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:45:34.537658 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 11:45:34.541179 Total UI for P1: 0, mck2ui 16
921 11:45:34.544581 best dqsien dly found for B0: ( 0, 14, 6)
922 11:45:34.547952 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 11:45:34.552121 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 11:45:34.556096 Total UI for P1: 0, mck2ui 16
925 11:45:34.559510 best dqsien dly found for B1: ( 0, 14, 10)
926 11:45:34.562926 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 11:45:34.566470 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 11:45:34.567050
929 11:45:34.570232 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 11:45:34.573256 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 11:45:34.577283 [Gating] SW calibration Done
932 11:45:34.577749 ==
933 11:45:34.580367 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:45:34.583971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:45:34.587119 ==
936 11:45:34.587556 RX Vref Scan: 0
937 11:45:34.587971
938 11:45:34.590315 RX Vref 0 -> 0, step: 1
939 11:45:34.590749
940 11:45:34.593739 RX Delay -130 -> 252, step: 16
941 11:45:34.597100 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 11:45:34.600677 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 11:45:34.603647 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 11:45:34.607320 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 11:45:34.614303 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 11:45:34.617783 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 11:45:34.620758 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
948 11:45:34.624742 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
949 11:45:34.628738 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 11:45:34.632355 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 11:45:34.635774 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 11:45:34.639252 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 11:45:34.645969 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
954 11:45:34.648920 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
955 11:45:34.652351 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 11:45:34.655975 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
957 11:45:34.656409 ==
958 11:45:34.658797 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:45:34.665505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:45:34.665943 ==
961 11:45:34.666290 DQS Delay:
962 11:45:34.666613 DQS0 = 0, DQS1 = 0
963 11:45:34.668914 DQM Delay:
964 11:45:34.669346 DQM0 = 85, DQM1 = 73
965 11:45:34.672336 DQ Delay:
966 11:45:34.675191 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 11:45:34.678682 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
968 11:45:34.681934 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
969 11:45:34.685883 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
970 11:45:34.686313
971 11:45:34.686650
972 11:45:34.686967 ==
973 11:45:34.688971 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:45:34.692251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:45:34.692738 ==
976 11:45:34.693089
977 11:45:34.693407
978 11:45:34.695707 TX Vref Scan disable
979 11:45:34.696285 == TX Byte 0 ==
980 11:45:34.702021 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 11:45:34.705608 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 11:45:34.706146 == TX Byte 1 ==
983 11:45:34.712056 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 11:45:34.715173 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 11:45:34.715676 ==
986 11:45:34.718743 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:45:34.721631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:45:34.722122 ==
989 11:45:34.736498 TX Vref=22, minBit 3, minWin=27, winSum=439
990 11:45:34.739720 TX Vref=24, minBit 8, minWin=27, winSum=444
991 11:45:34.743256 TX Vref=26, minBit 8, minWin=27, winSum=449
992 11:45:34.746076 TX Vref=28, minBit 8, minWin=27, winSum=449
993 11:45:34.749409 TX Vref=30, minBit 7, minWin=27, winSum=444
994 11:45:34.756321 TX Vref=32, minBit 4, minWin=27, winSum=443
995 11:45:34.759210 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 26
996 11:45:34.759659
997 11:45:34.762496 Final TX Range 1 Vref 26
998 11:45:34.762897
999 11:45:34.763414 ==
1000 11:45:34.765993 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:45:34.769559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:45:34.769956 ==
1003 11:45:34.772358
1004 11:45:34.772838
1005 11:45:34.773253 TX Vref Scan disable
1006 11:45:34.775932 == TX Byte 0 ==
1007 11:45:34.779204 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1008 11:45:34.786282 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1009 11:45:34.786727 == TX Byte 1 ==
1010 11:45:34.789453 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1011 11:45:34.795992 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1012 11:45:34.796636
1013 11:45:34.797389 [DATLAT]
1014 11:45:34.798111 Freq=800, CH0 RK0
1015 11:45:34.798784
1016 11:45:34.799810 DATLAT Default: 0xa
1017 11:45:34.800313 0, 0xFFFF, sum = 0
1018 11:45:34.802673 1, 0xFFFF, sum = 0
1019 11:45:34.803118 2, 0xFFFF, sum = 0
1020 11:45:34.806236 3, 0xFFFF, sum = 0
1021 11:45:34.809559 4, 0xFFFF, sum = 0
1022 11:45:34.809995 5, 0xFFFF, sum = 0
1023 11:45:34.812456 6, 0xFFFF, sum = 0
1024 11:45:34.813060 7, 0xFFFF, sum = 0
1025 11:45:34.815944 8, 0xFFFF, sum = 0
1026 11:45:34.816371 9, 0x0, sum = 1
1027 11:45:34.818994 10, 0x0, sum = 2
1028 11:45:34.819423 11, 0x0, sum = 3
1029 11:45:34.822604 12, 0x0, sum = 4
1030 11:45:34.823034 best_step = 10
1031 11:45:34.823373
1032 11:45:34.823686 ==
1033 11:45:34.825533 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:45:34.829058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:45:34.829487 ==
1036 11:45:34.832075 RX Vref Scan: 1
1037 11:45:34.832495
1038 11:45:34.835640 Set Vref Range= 32 -> 127
1039 11:45:34.836059
1040 11:45:34.836396 RX Vref 32 -> 127, step: 1
1041 11:45:34.836766
1042 11:45:34.839197 RX Delay -95 -> 252, step: 8
1043 11:45:34.839621
1044 11:45:34.842522 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:45:34.845360 [Byte1]: 32
1046 11:45:34.848807
1047 11:45:34.849579 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:45:34.852106 [Byte1]: 33
1049 11:45:34.856464
1050 11:45:34.856925 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:45:34.859937 [Byte1]: 34
1052 11:45:34.864048
1053 11:45:34.864423 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:45:34.867628 [Byte1]: 35
1055 11:45:34.872252
1056 11:45:34.872671 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:45:34.875398 [Byte1]: 36
1058 11:45:34.878951
1059 11:45:34.879368 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:45:34.882354 [Byte1]: 37
1061 11:45:34.886928
1062 11:45:34.887346 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:45:34.890175 [Byte1]: 38
1064 11:45:34.894501
1065 11:45:34.894894 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:45:34.897987 [Byte1]: 39
1067 11:45:34.901843
1068 11:45:34.902261 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:45:34.905412 [Byte1]: 40
1070 11:45:34.909810
1071 11:45:34.910228 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:45:34.913019 [Byte1]: 41
1073 11:45:34.917347
1074 11:45:34.917765 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:45:34.920828 [Byte1]: 42
1076 11:45:34.925029
1077 11:45:34.925449 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:45:34.927892 [Byte1]: 43
1079 11:45:34.932642
1080 11:45:34.933062 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:45:34.935634 [Byte1]: 44
1082 11:45:34.940414
1083 11:45:34.940888 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:45:34.943257 [Byte1]: 45
1085 11:45:34.947209
1086 11:45:34.947595 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:45:34.950660 [Byte1]: 46
1088 11:45:34.955264
1089 11:45:34.955639 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:45:34.958680 [Byte1]: 47
1091 11:45:34.962730
1092 11:45:34.963310 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:45:34.966033 [Byte1]: 48
1094 11:45:34.970092
1095 11:45:34.970504 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:45:34.973560 [Byte1]: 49
1097 11:45:34.978130
1098 11:45:34.978528 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:45:34.980956 [Byte1]: 50
1100 11:45:34.985648
1101 11:45:34.986107 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:45:34.988897 [Byte1]: 51
1103 11:45:34.993476
1104 11:45:34.993903 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:45:34.996225 [Byte1]: 52
1106 11:45:35.000742
1107 11:45:35.001174 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:45:35.004010 [Byte1]: 53
1109 11:45:35.008199
1110 11:45:35.008733 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:45:35.011889 [Byte1]: 54
1112 11:45:35.015850
1113 11:45:35.016279 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:45:35.019369 [Byte1]: 55
1115 11:45:35.023583
1116 11:45:35.024121 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:45:35.026956 [Byte1]: 56
1118 11:45:35.031182
1119 11:45:35.031626 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:45:35.034784 [Byte1]: 57
1121 11:45:35.038668
1122 11:45:35.039091 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:45:35.042386 [Byte1]: 58
1124 11:45:35.046443
1125 11:45:35.046877 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:45:35.049937 [Byte1]: 59
1127 11:45:35.053914
1128 11:45:35.057515 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:45:35.057945 [Byte1]: 60
1130 11:45:35.062214
1131 11:45:35.062642 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:45:35.064958 [Byte1]: 61
1133 11:45:35.069054
1134 11:45:35.069526 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:45:35.072503 [Byte1]: 62
1136 11:45:35.077173
1137 11:45:35.077602 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:45:35.080327 [Byte1]: 63
1139 11:45:35.084485
1140 11:45:35.084944 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:45:35.087855 [Byte1]: 64
1142 11:45:35.092423
1143 11:45:35.092932 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:45:35.095949 [Byte1]: 65
1145 11:45:35.099811
1146 11:45:35.100279 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:45:35.102980 [Byte1]: 66
1148 11:45:35.107198
1149 11:45:35.107767 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:45:35.110849 [Byte1]: 67
1151 11:45:35.114808
1152 11:45:35.115390 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:45:35.118410 [Byte1]: 68
1154 11:45:35.122107
1155 11:45:35.122510 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:45:35.125774 [Byte1]: 69
1157 11:45:35.129953
1158 11:45:35.130376 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:45:35.133594 [Byte1]: 70
1160 11:45:35.137704
1161 11:45:35.138135 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:45:35.141258 [Byte1]: 71
1163 11:45:35.145215
1164 11:45:35.145677 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:45:35.148691 [Byte1]: 72
1166 11:45:35.152748
1167 11:45:35.153157 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:45:35.156235 [Byte1]: 73
1169 11:45:35.160382
1170 11:45:35.160841 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:45:35.163892 [Byte1]: 74
1172 11:45:35.168332
1173 11:45:35.168853 Set Vref, RX VrefLevel [Byte0]: 75
1174 11:45:35.171206 [Byte1]: 75
1175 11:45:35.175798
1176 11:45:35.176336 Set Vref, RX VrefLevel [Byte0]: 76
1177 11:45:35.178666 [Byte1]: 76
1178 11:45:35.183545
1179 11:45:35.183974 Set Vref, RX VrefLevel [Byte0]: 77
1180 11:45:35.186896 [Byte1]: 77
1181 11:45:35.190504
1182 11:45:35.193832 Set Vref, RX VrefLevel [Byte0]: 78
1183 11:45:35.194226 [Byte1]: 78
1184 11:45:35.198204
1185 11:45:35.198622 Set Vref, RX VrefLevel [Byte0]: 79
1186 11:45:35.205067 [Byte1]: 79
1187 11:45:35.205695
1188 11:45:35.208234 Set Vref, RX VrefLevel [Byte0]: 80
1189 11:45:35.211956 [Byte1]: 80
1190 11:45:35.212582
1191 11:45:35.215300 Final RX Vref Byte 0 = 68 to rank0
1192 11:45:35.219440 Final RX Vref Byte 1 = 50 to rank0
1193 11:45:35.222875 Final RX Vref Byte 0 = 68 to rank1
1194 11:45:35.226760 Final RX Vref Byte 1 = 50 to rank1==
1195 11:45:35.227193 Dram Type= 6, Freq= 0, CH_0, rank 0
1196 11:45:35.233615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 11:45:35.234059 ==
1198 11:45:35.234447 DQS Delay:
1199 11:45:35.234768 DQS0 = 0, DQS1 = 0
1200 11:45:35.237365 DQM Delay:
1201 11:45:35.237794 DQM0 = 88, DQM1 = 76
1202 11:45:35.238161 DQ Delay:
1203 11:45:35.241400 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1204 11:45:35.244801 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1205 11:45:35.248197 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1206 11:45:35.251729 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1207 11:45:35.252315
1208 11:45:35.252913
1209 11:45:35.259329 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f21, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1210 11:45:35.262660 CH0 RK0: MR19=606, MR18=3F21
1211 11:45:35.270192 CH0_RK0: MR19=0x606, MR18=0x3F21, DQSOSC=393, MR23=63, INC=95, DEC=63
1212 11:45:35.270783
1213 11:45:35.274141 ----->DramcWriteLeveling(PI) begin...
1214 11:45:35.274647 ==
1215 11:45:35.277517 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 11:45:35.281111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 11:45:35.281672 ==
1218 11:45:35.284971 Write leveling (Byte 0): 35 => 35
1219 11:45:35.285575 Write leveling (Byte 1): 30 => 30
1220 11:45:35.288192 DramcWriteLeveling(PI) end<-----
1221 11:45:35.288753
1222 11:45:35.289297 ==
1223 11:45:35.291881 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 11:45:35.296080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 11:45:35.299234 ==
1226 11:45:35.299662 [Gating] SW mode calibration
1227 11:45:35.347124 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1228 11:45:35.347676 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1229 11:45:35.348453 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 11:45:35.348883 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1231 11:45:35.349231 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1232 11:45:35.349602 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:45:35.349945 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:45:35.350274 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:45:35.350862 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:45:35.351470 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:45:35.391195 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:45:35.392083 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:45:35.392466 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:45:35.392896 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:45:35.393226 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:45:35.393597 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:45:35.393915 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:45:35.394216 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:45:35.394514 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:45:35.394868 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:45:35.435225 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1248 11:45:35.435767 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1249 11:45:35.436455 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:45:35.436863 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:45:35.437225 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:45:35.437596 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:45:35.437918 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:45:35.438295 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:45:35.438623 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1256 11:45:35.438920 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1257 11:45:35.479418 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 11:45:35.480382 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 11:45:35.480944 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 11:45:35.481464 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 11:45:35.481970 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 11:45:35.482482 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1263 11:45:35.482892 0 10 8 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
1264 11:45:35.483295 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1265 11:45:35.483691 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 11:45:35.484161 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 11:45:35.523159 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 11:45:35.523658 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 11:45:35.524456 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 11:45:35.525053 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1271 11:45:35.525589 0 11 8 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
1272 11:45:35.526043 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1273 11:45:35.526369 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 11:45:35.526744 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 11:45:35.527059 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 11:45:35.527357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 11:45:35.527975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 11:45:35.531592 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 11:45:35.537815 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1280 11:45:35.541199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:45:35.544811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:45:35.551122 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:45:35.554519 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:45:35.557632 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:45:35.561124 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:45:35.567532 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:45:35.571067 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:45:35.577775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 11:45:35.580698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 11:45:35.584162 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 11:45:35.587546 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 11:45:35.594305 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 11:45:35.597826 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 11:45:35.600662 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 11:45:35.607572 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1296 11:45:35.610969 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1297 11:45:35.614271 Total UI for P1: 0, mck2ui 16
1298 11:45:35.617667 best dqsien dly found for B0: ( 0, 14, 8)
1299 11:45:35.621018 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1300 11:45:35.623822 Total UI for P1: 0, mck2ui 16
1301 11:45:35.627220 best dqsien dly found for B1: ( 0, 14, 12)
1302 11:45:35.630542 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1303 11:45:35.637646 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1304 11:45:35.638100
1305 11:45:35.640574 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1306 11:45:35.644006 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1307 11:45:35.646831 [Gating] SW calibration Done
1308 11:45:35.647255 ==
1309 11:45:35.650307 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 11:45:35.653760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 11:45:35.654167 ==
1312 11:45:35.654500 RX Vref Scan: 0
1313 11:45:35.657378
1314 11:45:35.657792 RX Vref 0 -> 0, step: 1
1315 11:45:35.658129
1316 11:45:35.660356 RX Delay -130 -> 252, step: 16
1317 11:45:35.663828 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1318 11:45:35.670445 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1319 11:45:35.673931 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1320 11:45:35.677031 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1321 11:45:35.680264 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1322 11:45:35.683873 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1323 11:45:35.690336 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1324 11:45:35.693569 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1325 11:45:35.696910 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1326 11:45:35.699788 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1327 11:45:35.703317 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1328 11:45:35.710016 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1329 11:45:35.713547 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1330 11:45:35.716484 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1331 11:45:35.719810 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1332 11:45:35.723252 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1333 11:45:35.726683 ==
1334 11:45:35.730114 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 11:45:35.733271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 11:45:35.733698 ==
1337 11:45:35.734035 DQS Delay:
1338 11:45:35.737051 DQS0 = 0, DQS1 = 0
1339 11:45:35.737818 DQM Delay:
1340 11:45:35.739767 DQM0 = 84, DQM1 = 79
1341 11:45:35.740219 DQ Delay:
1342 11:45:35.742955 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1343 11:45:35.746295 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1344 11:45:35.749514 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1345 11:45:35.752679 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1346 11:45:35.753108
1347 11:45:35.753473
1348 11:45:35.753800 ==
1349 11:45:35.756252 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 11:45:35.759928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 11:45:35.760357 ==
1352 11:45:35.760789
1353 11:45:35.761118
1354 11:45:35.762813 TX Vref Scan disable
1355 11:45:35.766443 == TX Byte 0 ==
1356 11:45:35.769549 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1357 11:45:35.772973 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1358 11:45:35.776329 == TX Byte 1 ==
1359 11:45:35.779871 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1360 11:45:35.782820 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1361 11:45:35.783235 ==
1362 11:45:35.786167 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 11:45:35.792457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 11:45:35.792928 ==
1365 11:45:35.805022 TX Vref=22, minBit 2, minWin=27, winSum=443
1366 11:45:35.808010 TX Vref=24, minBit 3, minWin=27, winSum=445
1367 11:45:35.811205 TX Vref=26, minBit 4, minWin=27, winSum=448
1368 11:45:35.814798 TX Vref=28, minBit 9, minWin=27, winSum=448
1369 11:45:35.817518 TX Vref=30, minBit 9, minWin=27, winSum=446
1370 11:45:35.824356 TX Vref=32, minBit 9, minWin=27, winSum=447
1371 11:45:35.827961 [TxChooseVref] Worse bit 4, Min win 27, Win sum 448, Final Vref 26
1372 11:45:35.828188
1373 11:45:35.831456 Final TX Range 1 Vref 26
1374 11:45:35.831761
1375 11:45:35.832015 ==
1376 11:45:35.834863 Dram Type= 6, Freq= 0, CH_0, rank 1
1377 11:45:35.838078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 11:45:35.838357 ==
1379 11:45:35.841090
1380 11:45:35.841361
1381 11:45:35.841578 TX Vref Scan disable
1382 11:45:35.844883 == TX Byte 0 ==
1383 11:45:35.848272 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1384 11:45:35.854569 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1385 11:45:35.855145 == TX Byte 1 ==
1386 11:45:35.857969 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1387 11:45:35.864406 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1388 11:45:35.864887
1389 11:45:35.865244 [DATLAT]
1390 11:45:35.865563 Freq=800, CH0 RK1
1391 11:45:35.865869
1392 11:45:35.867999 DATLAT Default: 0xa
1393 11:45:35.868411 0, 0xFFFF, sum = 0
1394 11:45:35.871463 1, 0xFFFF, sum = 0
1395 11:45:35.874380 2, 0xFFFF, sum = 0
1396 11:45:35.874803 3, 0xFFFF, sum = 0
1397 11:45:35.878139 4, 0xFFFF, sum = 0
1398 11:45:35.878695 5, 0xFFFF, sum = 0
1399 11:45:35.880964 6, 0xFFFF, sum = 0
1400 11:45:35.881389 7, 0xFFFF, sum = 0
1401 11:45:35.884591 8, 0xFFFF, sum = 0
1402 11:45:35.885025 9, 0x0, sum = 1
1403 11:45:35.888061 10, 0x0, sum = 2
1404 11:45:35.888482 11, 0x0, sum = 3
1405 11:45:35.888864 12, 0x0, sum = 4
1406 11:45:35.891444 best_step = 10
1407 11:45:35.891857
1408 11:45:35.892186 ==
1409 11:45:35.894372 Dram Type= 6, Freq= 0, CH_0, rank 1
1410 11:45:35.897862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 11:45:35.898342 ==
1412 11:45:35.901140 RX Vref Scan: 0
1413 11:45:35.901669
1414 11:45:35.904174 RX Vref 0 -> 0, step: 1
1415 11:45:35.904636
1416 11:45:35.904999 RX Delay -95 -> 252, step: 8
1417 11:45:35.911622 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1418 11:45:35.914686 iDelay=217, Bit 1, Center 84 (-31 ~ 200) 232
1419 11:45:35.917905 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1420 11:45:35.921534 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1421 11:45:35.924944 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1422 11:45:35.931629 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1423 11:45:35.934765 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1424 11:45:35.938254 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1425 11:45:35.940988 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1426 11:45:35.944306 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1427 11:45:35.950877 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1428 11:45:35.954466 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1429 11:45:35.957717 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1430 11:45:35.961349 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1431 11:45:35.967697 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1432 11:45:35.971288 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1433 11:45:35.971831 ==
1434 11:45:35.974321 Dram Type= 6, Freq= 0, CH_0, rank 1
1435 11:45:35.977831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 11:45:35.978437 ==
1437 11:45:35.981303 DQS Delay:
1438 11:45:35.981737 DQS0 = 0, DQS1 = 0
1439 11:45:35.982261 DQM Delay:
1440 11:45:35.984328 DQM0 = 84, DQM1 = 77
1441 11:45:35.984838 DQ Delay:
1442 11:45:35.987780 DQ0 =84, DQ1 =84, DQ2 =76, DQ3 =84
1443 11:45:35.991312 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1444 11:45:35.994270 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1445 11:45:35.997712 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1446 11:45:35.998297
1447 11:45:35.998654
1448 11:45:36.007693 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1449 11:45:36.008141 CH0 RK1: MR19=606, MR18=3C03
1450 11:45:36.014107 CH0_RK1: MR19=0x606, MR18=0x3C03, DQSOSC=394, MR23=63, INC=95, DEC=63
1451 11:45:36.017457 [RxdqsGatingPostProcess] freq 800
1452 11:45:36.024288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1453 11:45:36.027251 Pre-setting of DQS Precalculation
1454 11:45:36.030810 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1455 11:45:36.031242 ==
1456 11:45:36.033984 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 11:45:36.040821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 11:45:36.041221 ==
1459 11:45:36.044402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1460 11:45:36.050410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1461 11:45:36.059961 [CA 0] Center 36 (6~67) winsize 62
1462 11:45:36.063296 [CA 1] Center 36 (6~67) winsize 62
1463 11:45:36.066557 [CA 2] Center 34 (4~65) winsize 62
1464 11:45:36.069527 [CA 3] Center 34 (3~65) winsize 63
1465 11:45:36.073034 [CA 4] Center 34 (4~65) winsize 62
1466 11:45:36.076799 [CA 5] Center 33 (3~64) winsize 62
1467 11:45:36.077222
1468 11:45:36.079576 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1469 11:45:36.079997
1470 11:45:36.083301 [CATrainingPosCal] consider 1 rank data
1471 11:45:36.086704 u2DelayCellTimex100 = 270/100 ps
1472 11:45:36.089652 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1473 11:45:36.096556 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1474 11:45:36.099304 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1475 11:45:36.102771 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1476 11:45:36.106299 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1477 11:45:36.109093 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1478 11:45:36.109558
1479 11:45:36.112638 CA PerBit enable=1, Macro0, CA PI delay=33
1480 11:45:36.113062
1481 11:45:36.116034 [CBTSetCACLKResult] CA Dly = 33
1482 11:45:36.119664 CS Dly: 4 (0~35)
1483 11:45:36.120213 ==
1484 11:45:36.122317 Dram Type= 6, Freq= 0, CH_1, rank 1
1485 11:45:36.125900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1486 11:45:36.126331 ==
1487 11:45:36.132956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1488 11:45:36.135794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1489 11:45:36.146019 [CA 0] Center 36 (6~67) winsize 62
1490 11:45:36.149515 [CA 1] Center 37 (6~68) winsize 63
1491 11:45:36.152551 [CA 2] Center 34 (4~65) winsize 62
1492 11:45:36.155650 [CA 3] Center 34 (4~65) winsize 62
1493 11:45:36.159465 [CA 4] Center 34 (4~65) winsize 62
1494 11:45:36.162312 [CA 5] Center 33 (3~64) winsize 62
1495 11:45:36.162736
1496 11:45:36.165729 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1497 11:45:36.166158
1498 11:45:36.169132 [CATrainingPosCal] consider 2 rank data
1499 11:45:36.172234 u2DelayCellTimex100 = 270/100 ps
1500 11:45:36.176023 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1501 11:45:36.182437 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1502 11:45:36.185837 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1503 11:45:36.188631 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1504 11:45:36.192178 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1505 11:45:36.195728 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1506 11:45:36.196281
1507 11:45:36.198613 CA PerBit enable=1, Macro0, CA PI delay=33
1508 11:45:36.199037
1509 11:45:36.202287 [CBTSetCACLKResult] CA Dly = 33
1510 11:45:36.202710 CS Dly: 5 (0~38)
1511 11:45:36.205650
1512 11:45:36.209232 ----->DramcWriteLeveling(PI) begin...
1513 11:45:36.209664 ==
1514 11:45:36.212143 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 11:45:36.215411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 11:45:36.215835 ==
1517 11:45:36.219025 Write leveling (Byte 0): 25 => 25
1518 11:45:36.222529 Write leveling (Byte 1): 29 => 29
1519 11:45:36.225419 DramcWriteLeveling(PI) end<-----
1520 11:45:36.225841
1521 11:45:36.226178 ==
1522 11:45:36.228875 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 11:45:36.232358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 11:45:36.232830 ==
1525 11:45:36.235401 [Gating] SW mode calibration
1526 11:45:36.241951 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1527 11:45:36.248170 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1528 11:45:36.252031 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1529 11:45:36.255473 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1530 11:45:36.261593 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:45:36.265038 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:45:36.268131 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:45:36.275144 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:45:36.278295 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:45:36.281686 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:45:36.288216 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:45:36.291622 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:45:36.294639 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:45:36.301554 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:45:36.304507 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:45:36.307881 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:45:36.314881 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:45:36.318293 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:45:36.321153 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:45:36.328054 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1546 11:45:36.331110 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:45:36.334315 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:45:36.341043 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:45:36.344405 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:45:36.347738 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:45:36.351236 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:45:36.358121 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:45:36.361372 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:45:36.364775 0 9 8 | B1->B0 | 2e2e 3131 | 1 1 | (1 1) (1 1)
1555 11:45:36.371302 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 11:45:36.374454 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 11:45:36.377624 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 11:45:36.384642 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 11:45:36.387760 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 11:45:36.391246 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 11:45:36.397739 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1562 11:45:36.401178 0 10 8 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
1563 11:45:36.404069 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 11:45:36.410611 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 11:45:36.414150 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 11:45:36.417660 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 11:45:36.423863 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 11:45:36.427437 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 11:45:36.430887 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1570 11:45:36.437829 0 11 8 | B1->B0 | 3c3c 3e3e | 0 0 | (0 0) (0 0)
1571 11:45:36.440594 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 11:45:36.444007 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 11:45:36.450801 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 11:45:36.453959 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 11:45:36.457464 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 11:45:36.463806 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 11:45:36.466978 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1578 11:45:36.470384 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:45:36.477010 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:45:36.480436 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:45:36.483457 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:45:36.490554 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 11:45:36.493555 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 11:45:36.497036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 11:45:36.503485 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 11:45:36.506912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 11:45:36.509945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 11:45:36.516934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 11:45:36.520243 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 11:45:36.523339 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 11:45:36.530047 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 11:45:36.533495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 11:45:36.537061 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1594 11:45:36.539912 Total UI for P1: 0, mck2ui 16
1595 11:45:36.543151 best dqsien dly found for B0: ( 0, 14, 2)
1596 11:45:36.546894 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1597 11:45:36.549777 Total UI for P1: 0, mck2ui 16
1598 11:45:36.552989 best dqsien dly found for B1: ( 0, 14, 4)
1599 11:45:36.559830 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1600 11:45:36.563402 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1601 11:45:36.563931
1602 11:45:36.566286 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1603 11:45:36.569553 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1604 11:45:36.572952 [Gating] SW calibration Done
1605 11:45:36.573382 ==
1606 11:45:36.576082 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 11:45:36.580205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 11:45:36.580727 ==
1609 11:45:36.581422 RX Vref Scan: 0
1610 11:45:36.582974
1611 11:45:36.583721 RX Vref 0 -> 0, step: 1
1612 11:45:36.584323
1613 11:45:36.586252 RX Delay -130 -> 252, step: 16
1614 11:45:36.589478 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1615 11:45:36.596498 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1616 11:45:36.599820 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1617 11:45:36.602824 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1618 11:45:36.606356 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1619 11:45:36.609800 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1620 11:45:36.616209 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1621 11:45:36.619243 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1622 11:45:36.622685 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1623 11:45:36.626165 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1624 11:45:36.629887 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1625 11:45:36.635884 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1626 11:45:36.639445 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1627 11:45:36.642859 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1628 11:45:36.646211 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1629 11:45:36.649600 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1630 11:45:36.652478 ==
1631 11:45:36.655856 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 11:45:36.659434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 11:45:36.659839 ==
1634 11:45:36.660175 DQS Delay:
1635 11:45:36.662727 DQS0 = 0, DQS1 = 0
1636 11:45:36.663156 DQM Delay:
1637 11:45:36.666165 DQM0 = 89, DQM1 = 78
1638 11:45:36.666593 DQ Delay:
1639 11:45:36.669442 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1640 11:45:36.672757 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1641 11:45:36.676202 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1642 11:45:36.679518 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1643 11:45:36.679944
1644 11:45:36.680306
1645 11:45:36.680654 ==
1646 11:45:36.682846 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 11:45:36.686183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 11:45:36.686613 ==
1649 11:45:36.686953
1650 11:45:36.687273
1651 11:45:36.689007 TX Vref Scan disable
1652 11:45:36.692802 == TX Byte 0 ==
1653 11:45:36.695741 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1654 11:45:36.699278 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1655 11:45:36.702659 == TX Byte 1 ==
1656 11:45:36.705566 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1657 11:45:36.709367 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1658 11:45:36.709839 ==
1659 11:45:36.713004 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 11:45:36.718889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 11:45:36.719480 ==
1662 11:45:36.730844 TX Vref=22, minBit 3, minWin=26, winSum=434
1663 11:45:36.733899 TX Vref=24, minBit 9, minWin=27, winSum=445
1664 11:45:36.737518 TX Vref=26, minBit 8, minWin=27, winSum=447
1665 11:45:36.740732 TX Vref=28, minBit 9, minWin=27, winSum=445
1666 11:45:36.744136 TX Vref=30, minBit 0, minWin=27, winSum=446
1667 11:45:36.750283 TX Vref=32, minBit 0, minWin=27, winSum=443
1668 11:45:36.753649 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 26
1669 11:45:36.754098
1670 11:45:36.757131 Final TX Range 1 Vref 26
1671 11:45:36.757773
1672 11:45:36.758138 ==
1673 11:45:36.760565 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 11:45:36.764031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1675 11:45:36.764582 ==
1676 11:45:36.766799
1677 11:45:36.767272
1678 11:45:36.767707 TX Vref Scan disable
1679 11:45:36.770313 == TX Byte 0 ==
1680 11:45:36.773772 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1681 11:45:36.780647 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1682 11:45:36.781075 == TX Byte 1 ==
1683 11:45:36.783787 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1684 11:45:36.790640 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1685 11:45:36.791168
1686 11:45:36.791512 [DATLAT]
1687 11:45:36.791827 Freq=800, CH1 RK0
1688 11:45:36.792134
1689 11:45:36.794109 DATLAT Default: 0xa
1690 11:45:36.794537 0, 0xFFFF, sum = 0
1691 11:45:36.797300 1, 0xFFFF, sum = 0
1692 11:45:36.797731 2, 0xFFFF, sum = 0
1693 11:45:36.800350 3, 0xFFFF, sum = 0
1694 11:45:36.803644 4, 0xFFFF, sum = 0
1695 11:45:36.804181 5, 0xFFFF, sum = 0
1696 11:45:36.807326 6, 0xFFFF, sum = 0
1697 11:45:36.807889 7, 0xFFFF, sum = 0
1698 11:45:36.810634 8, 0xFFFF, sum = 0
1699 11:45:36.811337 9, 0x0, sum = 1
1700 11:45:36.811921 10, 0x0, sum = 2
1701 11:45:36.813709 11, 0x0, sum = 3
1702 11:45:36.814284 12, 0x0, sum = 4
1703 11:45:36.817118 best_step = 10
1704 11:45:36.817548
1705 11:45:36.817889 ==
1706 11:45:36.820703 Dram Type= 6, Freq= 0, CH_1, rank 0
1707 11:45:36.823727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1708 11:45:36.824158 ==
1709 11:45:36.827352 RX Vref Scan: 1
1710 11:45:36.827807
1711 11:45:36.830635 Set Vref Range= 32 -> 127
1712 11:45:36.831066
1713 11:45:36.831432 RX Vref 32 -> 127, step: 1
1714 11:45:36.831755
1715 11:45:36.833774 RX Delay -95 -> 252, step: 8
1716 11:45:36.834267
1717 11:45:36.836708 Set Vref, RX VrefLevel [Byte0]: 32
1718 11:45:36.840149 [Byte1]: 32
1719 11:45:36.840639
1720 11:45:36.843395 Set Vref, RX VrefLevel [Byte0]: 33
1721 11:45:36.847089 [Byte1]: 33
1722 11:45:36.851296
1723 11:45:36.851721 Set Vref, RX VrefLevel [Byte0]: 34
1724 11:45:36.854203 [Byte1]: 34
1725 11:45:36.858687
1726 11:45:36.859177 Set Vref, RX VrefLevel [Byte0]: 35
1727 11:45:36.862176 [Byte1]: 35
1728 11:45:36.866477
1729 11:45:36.867081 Set Vref, RX VrefLevel [Byte0]: 36
1730 11:45:36.870021 [Byte1]: 36
1731 11:45:36.873942
1732 11:45:36.874370 Set Vref, RX VrefLevel [Byte0]: 37
1733 11:45:36.876779 [Byte1]: 37
1734 11:45:36.881406
1735 11:45:36.884773 Set Vref, RX VrefLevel [Byte0]: 38
1736 11:45:36.885274 [Byte1]: 38
1737 11:45:36.889289
1738 11:45:36.889824 Set Vref, RX VrefLevel [Byte0]: 39
1739 11:45:36.892486 [Byte1]: 39
1740 11:45:36.896611
1741 11:45:36.897173 Set Vref, RX VrefLevel [Byte0]: 40
1742 11:45:36.899774 [Byte1]: 40
1743 11:45:36.904042
1744 11:45:36.904663 Set Vref, RX VrefLevel [Byte0]: 41
1745 11:45:36.907436 [Byte1]: 41
1746 11:45:36.911814
1747 11:45:36.912342 Set Vref, RX VrefLevel [Byte0]: 42
1748 11:45:36.915310 [Byte1]: 42
1749 11:45:36.919483
1750 11:45:36.919906 Set Vref, RX VrefLevel [Byte0]: 43
1751 11:45:36.922993 [Byte1]: 43
1752 11:45:36.927039
1753 11:45:36.927459 Set Vref, RX VrefLevel [Byte0]: 44
1754 11:45:36.930642 [Byte1]: 44
1755 11:45:36.934575
1756 11:45:36.935148 Set Vref, RX VrefLevel [Byte0]: 45
1757 11:45:36.938372 [Byte1]: 45
1758 11:45:36.942390
1759 11:45:36.942847 Set Vref, RX VrefLevel [Byte0]: 46
1760 11:45:36.945247 [Byte1]: 46
1761 11:45:36.949653
1762 11:45:36.950225 Set Vref, RX VrefLevel [Byte0]: 47
1763 11:45:36.953029 [Byte1]: 47
1764 11:45:36.957119
1765 11:45:36.957548 Set Vref, RX VrefLevel [Byte0]: 48
1766 11:45:36.960925 [Byte1]: 48
1767 11:45:36.965198
1768 11:45:36.965649 Set Vref, RX VrefLevel [Byte0]: 49
1769 11:45:36.968286 [Byte1]: 49
1770 11:45:36.972483
1771 11:45:36.972947 Set Vref, RX VrefLevel [Byte0]: 50
1772 11:45:36.975930 [Byte1]: 50
1773 11:45:36.980273
1774 11:45:36.980812 Set Vref, RX VrefLevel [Byte0]: 51
1775 11:45:36.983361 [Byte1]: 51
1776 11:45:36.987784
1777 11:45:36.988293 Set Vref, RX VrefLevel [Byte0]: 52
1778 11:45:36.990997 [Byte1]: 52
1779 11:45:36.995370
1780 11:45:36.995790 Set Vref, RX VrefLevel [Byte0]: 53
1781 11:45:36.998759 [Byte1]: 53
1782 11:45:37.002820
1783 11:45:37.003241 Set Vref, RX VrefLevel [Byte0]: 54
1784 11:45:37.006082 [Byte1]: 54
1785 11:45:37.010482
1786 11:45:37.010904 Set Vref, RX VrefLevel [Byte0]: 55
1787 11:45:37.016956 [Byte1]: 55
1788 11:45:37.017380
1789 11:45:37.020544 Set Vref, RX VrefLevel [Byte0]: 56
1790 11:45:37.023534 [Byte1]: 56
1791 11:45:37.023996
1792 11:45:37.027053 Set Vref, RX VrefLevel [Byte0]: 57
1793 11:45:37.030145 [Byte1]: 57
1794 11:45:37.030570
1795 11:45:37.033543 Set Vref, RX VrefLevel [Byte0]: 58
1796 11:45:37.036989 [Byte1]: 58
1797 11:45:37.040855
1798 11:45:37.041332 Set Vref, RX VrefLevel [Byte0]: 59
1799 11:45:37.044408 [Byte1]: 59
1800 11:45:37.048466
1801 11:45:37.048936 Set Vref, RX VrefLevel [Byte0]: 60
1802 11:45:37.051752 [Byte1]: 60
1803 11:45:37.055837
1804 11:45:37.056553 Set Vref, RX VrefLevel [Byte0]: 61
1805 11:45:37.059439 [Byte1]: 61
1806 11:45:37.063905
1807 11:45:37.064334 Set Vref, RX VrefLevel [Byte0]: 62
1808 11:45:37.066844 [Byte1]: 62
1809 11:45:37.071587
1810 11:45:37.072023 Set Vref, RX VrefLevel [Byte0]: 63
1811 11:45:37.075001 [Byte1]: 63
1812 11:45:37.078998
1813 11:45:37.079425 Set Vref, RX VrefLevel [Byte0]: 64
1814 11:45:37.082531 [Byte1]: 64
1815 11:45:37.086350
1816 11:45:37.086774 Set Vref, RX VrefLevel [Byte0]: 65
1817 11:45:37.089792 [Byte1]: 65
1818 11:45:37.094201
1819 11:45:37.094767 Set Vref, RX VrefLevel [Byte0]: 66
1820 11:45:37.097141 [Byte1]: 66
1821 11:45:37.101544
1822 11:45:37.101976 Set Vref, RX VrefLevel [Byte0]: 67
1823 11:45:37.105040 [Byte1]: 67
1824 11:45:37.108963
1825 11:45:37.109385 Set Vref, RX VrefLevel [Byte0]: 68
1826 11:45:37.112879 [Byte1]: 68
1827 11:45:37.117056
1828 11:45:37.117481 Set Vref, RX VrefLevel [Byte0]: 69
1829 11:45:37.120464 [Byte1]: 69
1830 11:45:37.124618
1831 11:45:37.125046 Set Vref, RX VrefLevel [Byte0]: 70
1832 11:45:37.127998 [Byte1]: 70
1833 11:45:37.132069
1834 11:45:37.132494 Set Vref, RX VrefLevel [Byte0]: 71
1835 11:45:37.135786 [Byte1]: 71
1836 11:45:37.140016
1837 11:45:37.140564 Set Vref, RX VrefLevel [Byte0]: 72
1838 11:45:37.142900 [Byte1]: 72
1839 11:45:37.147472
1840 11:45:37.147899 Set Vref, RX VrefLevel [Byte0]: 73
1841 11:45:37.150377 [Byte1]: 73
1842 11:45:37.154883
1843 11:45:37.155348 Set Vref, RX VrefLevel [Byte0]: 74
1844 11:45:37.158279 [Byte1]: 74
1845 11:45:37.162478
1846 11:45:37.162907 Set Vref, RX VrefLevel [Byte0]: 75
1847 11:45:37.166067 [Byte1]: 75
1848 11:45:37.169932
1849 11:45:37.170373 Final RX Vref Byte 0 = 54 to rank0
1850 11:45:37.173403 Final RX Vref Byte 1 = 64 to rank0
1851 11:45:37.176913 Final RX Vref Byte 0 = 54 to rank1
1852 11:45:37.180134 Final RX Vref Byte 1 = 64 to rank1==
1853 11:45:37.183441 Dram Type= 6, Freq= 0, CH_1, rank 0
1854 11:45:37.189656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 11:45:37.190094 ==
1856 11:45:37.190437 DQS Delay:
1857 11:45:37.190808 DQS0 = 0, DQS1 = 0
1858 11:45:37.193461 DQM Delay:
1859 11:45:37.193884 DQM0 = 87, DQM1 = 79
1860 11:45:37.197056 DQ Delay:
1861 11:45:37.199947 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
1862 11:45:37.203150 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1863 11:45:37.206265 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1864 11:45:37.209881 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1865 11:45:37.210300
1866 11:45:37.210629
1867 11:45:37.216190 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1868 11:45:37.219667 CH1 RK0: MR19=606, MR18=2C18
1869 11:45:37.226442 CH1_RK0: MR19=0x606, MR18=0x2C18, DQSOSC=398, MR23=63, INC=93, DEC=62
1870 11:45:37.226551
1871 11:45:37.229454 ----->DramcWriteLeveling(PI) begin...
1872 11:45:37.229599 ==
1873 11:45:37.232869 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 11:45:37.235698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 11:45:37.235815 ==
1876 11:45:37.239199 Write leveling (Byte 0): 26 => 26
1877 11:45:37.242798 Write leveling (Byte 1): 31 => 31
1878 11:45:37.245740 DramcWriteLeveling(PI) end<-----
1879 11:45:37.245821
1880 11:45:37.245913 ==
1881 11:45:37.249136 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 11:45:37.252644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1883 11:45:37.252731 ==
1884 11:45:37.256164 [Gating] SW mode calibration
1885 11:45:37.262339 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1886 11:45:37.269423 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1887 11:45:37.272947 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1888 11:45:37.278785 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1889 11:45:37.282200 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:45:37.285644 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:45:37.289058 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:45:37.296061 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:45:37.298821 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:45:37.302207 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:45:37.308835 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:45:37.312229 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:45:37.315609 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:45:37.322625 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:45:37.325776 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:45:37.328758 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:45:37.335261 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:45:37.338678 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:45:37.342211 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1904 11:45:37.348766 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:45:37.352171 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1906 11:45:37.355684 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:45:37.362006 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:45:37.365370 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:45:37.368387 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:45:37.375197 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:45:37.378509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:45:37.381765 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:45:37.388691 0 9 8 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (0 0)
1914 11:45:37.391587 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:45:37.395138 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 11:45:37.401435 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 11:45:37.405000 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 11:45:37.408207 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 11:45:37.415252 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 11:45:37.418451 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1921 11:45:37.421854 0 10 8 | B1->B0 | 2626 2b2b | 1 1 | (1 0) (1 0)
1922 11:45:37.428587 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:45:37.431560 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:45:37.435097 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:45:37.441535 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:45:37.444996 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 11:45:37.448653 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 11:45:37.454889 0 11 4 | B1->B0 | 2a2a 2828 | 0 0 | (0 0) (0 0)
1929 11:45:37.458416 0 11 8 | B1->B0 | 4444 3a3a | 0 0 | (1 1) (0 0)
1930 11:45:37.461894 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:45:37.468189 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:45:37.471711 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:45:37.475153 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 11:45:37.481393 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 11:45:37.484829 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 11:45:37.488176 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1937 11:45:37.494448 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1938 11:45:37.497966 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:45:37.501165 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:45:37.507633 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:45:37.511094 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:45:37.514410 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:45:37.521150 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:45:37.524218 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:45:37.527468 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:45:37.530907 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:45:37.537516 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:45:37.541124 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:45:37.544143 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:45:37.550337 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:45:37.554081 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 11:45:37.557541 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1953 11:45:37.563700 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1954 11:45:37.567473 Total UI for P1: 0, mck2ui 16
1955 11:45:37.570882 best dqsien dly found for B1: ( 0, 14, 4)
1956 11:45:37.574161 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1957 11:45:37.577250 Total UI for P1: 0, mck2ui 16
1958 11:45:37.580667 best dqsien dly found for B0: ( 0, 14, 6)
1959 11:45:37.584081 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1960 11:45:37.587168 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1961 11:45:37.587473
1962 11:45:37.590917 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1963 11:45:37.594622 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1964 11:45:37.597223 [Gating] SW calibration Done
1965 11:45:37.597461 ==
1966 11:45:37.600786 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 11:45:37.604186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 11:45:37.607753 ==
1969 11:45:37.608035 RX Vref Scan: 0
1970 11:45:37.608368
1971 11:45:37.610691 RX Vref 0 -> 0, step: 1
1972 11:45:37.610995
1973 11:45:37.613978 RX Delay -130 -> 252, step: 16
1974 11:45:37.617215 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1975 11:45:37.620689 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1976 11:45:37.624492 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1977 11:45:37.627165 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1978 11:45:37.634031 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1979 11:45:37.637541 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1980 11:45:37.640367 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1981 11:45:37.643894 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1982 11:45:37.646954 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1983 11:45:37.654011 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1984 11:45:37.657189 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1985 11:45:37.660566 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1986 11:45:37.663963 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1987 11:45:37.670371 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1988 11:45:37.673899 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1989 11:45:37.677172 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1990 11:45:37.677578 ==
1991 11:45:37.680245 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 11:45:37.683636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 11:45:37.684056 ==
1994 11:45:37.687355 DQS Delay:
1995 11:45:37.687842 DQS0 = 0, DQS1 = 0
1996 11:45:37.688147 DQM Delay:
1997 11:45:37.690587 DQM0 = 87, DQM1 = 78
1998 11:45:37.690941 DQ Delay:
1999 11:45:37.693816 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
2000 11:45:37.696721 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2001 11:45:37.700185 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2002 11:45:37.703422 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2003 11:45:37.703925
2004 11:45:37.704342
2005 11:45:37.704790 ==
2006 11:45:37.707014 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 11:45:37.713407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 11:45:37.713889 ==
2009 11:45:37.714302
2010 11:45:37.714695
2011 11:45:37.716579 TX Vref Scan disable
2012 11:45:37.717010 == TX Byte 0 ==
2013 11:45:37.719883 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2014 11:45:37.726852 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2015 11:45:37.727481 == TX Byte 1 ==
2016 11:45:37.730140 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2017 11:45:37.736769 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2018 11:45:37.737136 ==
2019 11:45:37.740259 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 11:45:37.743050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 11:45:37.743409 ==
2022 11:45:37.756888 TX Vref=22, minBit 8, minWin=26, winSum=441
2023 11:45:37.759983 TX Vref=24, minBit 8, minWin=27, winSum=446
2024 11:45:37.763347 TX Vref=26, minBit 8, minWin=27, winSum=448
2025 11:45:37.766814 TX Vref=28, minBit 13, minWin=27, winSum=450
2026 11:45:37.770280 TX Vref=30, minBit 8, minWin=27, winSum=449
2027 11:45:37.777189 TX Vref=32, minBit 9, minWin=27, winSum=448
2028 11:45:37.779979 [TxChooseVref] Worse bit 13, Min win 27, Win sum 450, Final Vref 28
2029 11:45:37.780554
2030 11:45:37.783414 Final TX Range 1 Vref 28
2031 11:45:37.783770
2032 11:45:37.784049 ==
2033 11:45:37.786923 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 11:45:37.790450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 11:45:37.793407 ==
2036 11:45:37.793767
2037 11:45:37.794051
2038 11:45:37.794319 TX Vref Scan disable
2039 11:45:37.797308 == TX Byte 0 ==
2040 11:45:37.800638 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2041 11:45:37.806845 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2042 11:45:37.807287 == TX Byte 1 ==
2043 11:45:37.810369 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2044 11:45:37.817240 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2045 11:45:37.817602
2046 11:45:37.817882 [DATLAT]
2047 11:45:37.818147 Freq=800, CH1 RK1
2048 11:45:37.818406
2049 11:45:37.819993 DATLAT Default: 0xa
2050 11:45:37.820437 0, 0xFFFF, sum = 0
2051 11:45:37.823759 1, 0xFFFF, sum = 0
2052 11:45:37.826807 2, 0xFFFF, sum = 0
2053 11:45:37.827170 3, 0xFFFF, sum = 0
2054 11:45:37.829687 4, 0xFFFF, sum = 0
2055 11:45:37.830065 5, 0xFFFF, sum = 0
2056 11:45:37.833492 6, 0xFFFF, sum = 0
2057 11:45:37.833860 7, 0xFFFF, sum = 0
2058 11:45:37.836864 8, 0xFFFF, sum = 0
2059 11:45:37.837235 9, 0x0, sum = 1
2060 11:45:37.839656 10, 0x0, sum = 2
2061 11:45:37.840152 11, 0x0, sum = 3
2062 11:45:37.843440 12, 0x0, sum = 4
2063 11:45:37.843922 best_step = 10
2064 11:45:37.844366
2065 11:45:37.844841 ==
2066 11:45:37.846358 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 11:45:37.849853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 11:45:37.850222 ==
2069 11:45:37.853347 RX Vref Scan: 0
2070 11:45:37.853714
2071 11:45:37.856288 RX Vref 0 -> 0, step: 1
2072 11:45:37.856678
2073 11:45:37.856972 RX Delay -95 -> 252, step: 8
2074 11:45:37.863926 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2075 11:45:37.866884 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2076 11:45:37.870520 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2077 11:45:37.873277 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2078 11:45:37.876684 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2079 11:45:37.883274 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2080 11:45:37.887183 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2081 11:45:37.890206 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2082 11:45:37.893358 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2083 11:45:37.896812 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2084 11:45:37.903576 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2085 11:45:37.906951 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2086 11:45:37.910572 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2087 11:45:37.913918 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2088 11:45:37.920134 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2089 11:45:37.923632 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2090 11:45:37.924135 ==
2091 11:45:37.927012 Dram Type= 6, Freq= 0, CH_1, rank 1
2092 11:45:37.930275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2093 11:45:37.930698 ==
2094 11:45:37.931033 DQS Delay:
2095 11:45:37.933535 DQS0 = 0, DQS1 = 0
2096 11:45:37.933955 DQM Delay:
2097 11:45:37.936932 DQM0 = 87, DQM1 = 79
2098 11:45:37.937398 DQ Delay:
2099 11:45:37.940010 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2100 11:45:37.943406 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2101 11:45:37.946843 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =72
2102 11:45:37.950027 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2103 11:45:37.950449
2104 11:45:37.950783
2105 11:45:37.960137 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2106 11:45:37.960702 CH1 RK1: MR19=606, MR18=1A13
2107 11:45:37.966931 CH1_RK1: MR19=0x606, MR18=0x1A13, DQSOSC=403, MR23=63, INC=90, DEC=60
2108 11:45:37.970106 [RxdqsGatingPostProcess] freq 800
2109 11:45:37.976373 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2110 11:45:37.979854 Pre-setting of DQS Precalculation
2111 11:45:37.983454 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2112 11:45:37.989869 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2113 11:45:38.000069 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2114 11:45:38.000747
2115 11:45:38.001206
2116 11:45:38.003413 [Calibration Summary] 1600 Mbps
2117 11:45:38.003842 CH 0, Rank 0
2118 11:45:38.006208 SW Impedance : PASS
2119 11:45:38.006637 DUTY Scan : NO K
2120 11:45:38.009525 ZQ Calibration : PASS
2121 11:45:38.012655 Jitter Meter : NO K
2122 11:45:38.013277 CBT Training : PASS
2123 11:45:38.016061 Write leveling : PASS
2124 11:45:38.019597 RX DQS gating : PASS
2125 11:45:38.020030 RX DQ/DQS(RDDQC) : PASS
2126 11:45:38.022895 TX DQ/DQS : PASS
2127 11:45:38.023324 RX DATLAT : PASS
2128 11:45:38.026457 RX DQ/DQS(Engine): PASS
2129 11:45:38.029350 TX OE : NO K
2130 11:45:38.029781 All Pass.
2131 11:45:38.030124
2132 11:45:38.030442 CH 0, Rank 1
2133 11:45:38.032730 SW Impedance : PASS
2134 11:45:38.035975 DUTY Scan : NO K
2135 11:45:38.036399 ZQ Calibration : PASS
2136 11:45:38.039335 Jitter Meter : NO K
2137 11:45:38.042653 CBT Training : PASS
2138 11:45:38.043079 Write leveling : PASS
2139 11:45:38.046075 RX DQS gating : PASS
2140 11:45:38.049380 RX DQ/DQS(RDDQC) : PASS
2141 11:45:38.049806 TX DQ/DQS : PASS
2142 11:45:38.052690 RX DATLAT : PASS
2143 11:45:38.056206 RX DQ/DQS(Engine): PASS
2144 11:45:38.056670 TX OE : NO K
2145 11:45:38.059634 All Pass.
2146 11:45:38.060059
2147 11:45:38.060396 CH 1, Rank 0
2148 11:45:38.062499 SW Impedance : PASS
2149 11:45:38.062933 DUTY Scan : NO K
2150 11:45:38.066094 ZQ Calibration : PASS
2151 11:45:38.068961 Jitter Meter : NO K
2152 11:45:38.069718 CBT Training : PASS
2153 11:45:38.072487 Write leveling : PASS
2154 11:45:38.075549 RX DQS gating : PASS
2155 11:45:38.076067 RX DQ/DQS(RDDQC) : PASS
2156 11:45:38.079165 TX DQ/DQS : PASS
2157 11:45:38.079595 RX DATLAT : PASS
2158 11:45:38.082492 RX DQ/DQS(Engine): PASS
2159 11:45:38.085847 TX OE : NO K
2160 11:45:38.086313 All Pass.
2161 11:45:38.086655
2162 11:45:38.086973 CH 1, Rank 1
2163 11:45:38.089631 SW Impedance : PASS
2164 11:45:38.092508 DUTY Scan : NO K
2165 11:45:38.092958 ZQ Calibration : PASS
2166 11:45:38.095732 Jitter Meter : NO K
2167 11:45:38.099346 CBT Training : PASS
2168 11:45:38.099781 Write leveling : PASS
2169 11:45:38.102772 RX DQS gating : PASS
2170 11:45:38.105745 RX DQ/DQS(RDDQC) : PASS
2171 11:45:38.106203 TX DQ/DQS : PASS
2172 11:45:38.109415 RX DATLAT : PASS
2173 11:45:38.112876 RX DQ/DQS(Engine): PASS
2174 11:45:38.113312 TX OE : NO K
2175 11:45:38.115519 All Pass.
2176 11:45:38.115941
2177 11:45:38.116276 DramC Write-DBI off
2178 11:45:38.119273 PER_BANK_REFRESH: Hybrid Mode
2179 11:45:38.119696 TX_TRACKING: ON
2180 11:45:38.122559 [GetDramInforAfterCalByMRR] Vendor 6.
2181 11:45:38.129374 [GetDramInforAfterCalByMRR] Revision 606.
2182 11:45:38.132195 [GetDramInforAfterCalByMRR] Revision 2 0.
2183 11:45:38.132670 MR0 0x3b3b
2184 11:45:38.133106 MR8 0x5151
2185 11:45:38.135778 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 11:45:38.136211
2187 11:45:38.138940 MR0 0x3b3b
2188 11:45:38.139375 MR8 0x5151
2189 11:45:38.142360 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2190 11:45:38.142797
2191 11:45:38.152448 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2192 11:45:38.155603 [FAST_K] Save calibration result to emmc
2193 11:45:38.158873 [FAST_K] Save calibration result to emmc
2194 11:45:38.162410 dram_init: config_dvfs: 1
2195 11:45:38.165937 dramc_set_vcore_voltage set vcore to 662500
2196 11:45:38.168861 Read voltage for 1200, 2
2197 11:45:38.169296 Vio18 = 0
2198 11:45:38.169631 Vcore = 662500
2199 11:45:38.172353 Vdram = 0
2200 11:45:38.172813 Vddq = 0
2201 11:45:38.173148 Vmddr = 0
2202 11:45:38.179055 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2203 11:45:38.182083 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2204 11:45:38.185591 MEM_TYPE=3, freq_sel=15
2205 11:45:38.188944 sv_algorithm_assistance_LP4_1600
2206 11:45:38.192053 ============ PULL DRAM RESETB DOWN ============
2207 11:45:38.195648 ========== PULL DRAM RESETB DOWN end =========
2208 11:45:38.202522 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2209 11:45:38.205379 ===================================
2210 11:45:38.205882 LPDDR4 DRAM CONFIGURATION
2211 11:45:38.208842 ===================================
2212 11:45:38.212232 EX_ROW_EN[0] = 0x0
2213 11:45:38.215477 EX_ROW_EN[1] = 0x0
2214 11:45:38.215897 LP4Y_EN = 0x0
2215 11:45:38.218739 WORK_FSP = 0x0
2216 11:45:38.219157 WL = 0x4
2217 11:45:38.221832 RL = 0x4
2218 11:45:38.222217 BL = 0x2
2219 11:45:38.225183 RPST = 0x0
2220 11:45:38.225616 RD_PRE = 0x0
2221 11:45:38.228513 WR_PRE = 0x1
2222 11:45:38.229263 WR_PST = 0x0
2223 11:45:38.232023 DBI_WR = 0x0
2224 11:45:38.232587 DBI_RD = 0x0
2225 11:45:38.235504 OTF = 0x1
2226 11:45:38.239054 ===================================
2227 11:45:38.242202 ===================================
2228 11:45:38.242754 ANA top config
2229 11:45:38.245652 ===================================
2230 11:45:38.248754 DLL_ASYNC_EN = 0
2231 11:45:38.252133 ALL_SLAVE_EN = 0
2232 11:45:38.255374 NEW_RANK_MODE = 1
2233 11:45:38.255803 DLL_IDLE_MODE = 1
2234 11:45:38.258404 LP45_APHY_COMB_EN = 1
2235 11:45:38.261679 TX_ODT_DIS = 1
2236 11:45:38.264982 NEW_8X_MODE = 1
2237 11:45:38.268392 ===================================
2238 11:45:38.271971 ===================================
2239 11:45:38.275028 data_rate = 2400
2240 11:45:38.275457 CKR = 1
2241 11:45:38.278540 DQ_P2S_RATIO = 8
2242 11:45:38.282259 ===================================
2243 11:45:38.285054 CA_P2S_RATIO = 8
2244 11:45:38.288757 DQ_CA_OPEN = 0
2245 11:45:38.292083 DQ_SEMI_OPEN = 0
2246 11:45:38.292548 CA_SEMI_OPEN = 0
2247 11:45:38.295400 CA_FULL_RATE = 0
2248 11:45:38.298431 DQ_CKDIV4_EN = 0
2249 11:45:38.301891 CA_CKDIV4_EN = 0
2250 11:45:38.304728 CA_PREDIV_EN = 0
2251 11:45:38.308281 PH8_DLY = 17
2252 11:45:38.311753 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2253 11:45:38.312358 DQ_AAMCK_DIV = 4
2254 11:45:38.315270 CA_AAMCK_DIV = 4
2255 11:45:38.318002 CA_ADMCK_DIV = 4
2256 11:45:38.321433 DQ_TRACK_CA_EN = 0
2257 11:45:38.325034 CA_PICK = 1200
2258 11:45:38.328512 CA_MCKIO = 1200
2259 11:45:38.328992 MCKIO_SEMI = 0
2260 11:45:38.331336 PLL_FREQ = 2366
2261 11:45:38.334831 DQ_UI_PI_RATIO = 32
2262 11:45:38.338420 CA_UI_PI_RATIO = 0
2263 11:45:38.341371 ===================================
2264 11:45:38.345166 ===================================
2265 11:45:38.347826 memory_type:LPDDR4
2266 11:45:38.348251 GP_NUM : 10
2267 11:45:38.351619 SRAM_EN : 1
2268 11:45:38.354856 MD32_EN : 0
2269 11:45:38.358086 ===================================
2270 11:45:38.358517 [ANA_INIT] >>>>>>>>>>>>>>
2271 11:45:38.361772 <<<<<< [CONFIGURE PHASE]: ANA_TX
2272 11:45:38.364419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2273 11:45:38.367760 ===================================
2274 11:45:38.371347 data_rate = 2400,PCW = 0X5b00
2275 11:45:38.374773 ===================================
2276 11:45:38.377824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2277 11:45:38.384505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2278 11:45:38.388079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 11:45:38.394490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2280 11:45:38.397892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2281 11:45:38.401342 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2282 11:45:38.401785 [ANA_INIT] flow start
2283 11:45:38.404785 [ANA_INIT] PLL >>>>>>>>
2284 11:45:38.408165 [ANA_INIT] PLL <<<<<<<<
2285 11:45:38.411443 [ANA_INIT] MIDPI >>>>>>>>
2286 11:45:38.411871 [ANA_INIT] MIDPI <<<<<<<<
2287 11:45:38.415016 [ANA_INIT] DLL >>>>>>>>
2288 11:45:38.417691 [ANA_INIT] DLL <<<<<<<<
2289 11:45:38.418126 [ANA_INIT] flow end
2290 11:45:38.421248 ============ LP4 DIFF to SE enter ============
2291 11:45:38.427825 ============ LP4 DIFF to SE exit ============
2292 11:45:38.428259 [ANA_INIT] <<<<<<<<<<<<<
2293 11:45:38.431504 [Flow] Enable top DCM control >>>>>
2294 11:45:38.434293 [Flow] Enable top DCM control <<<<<
2295 11:45:38.438332 Enable DLL master slave shuffle
2296 11:45:38.444875 ==============================================================
2297 11:45:38.445305 Gating Mode config
2298 11:45:38.451202 ==============================================================
2299 11:45:38.454577 Config description:
2300 11:45:38.464627 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2301 11:45:38.470596 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2302 11:45:38.474018 SELPH_MODE 0: By rank 1: By Phase
2303 11:45:38.480489 ==============================================================
2304 11:45:38.484090 GAT_TRACK_EN = 1
2305 11:45:38.486933 RX_GATING_MODE = 2
2306 11:45:38.490411 RX_GATING_TRACK_MODE = 2
2307 11:45:38.490856 SELPH_MODE = 1
2308 11:45:38.494094 PICG_EARLY_EN = 1
2309 11:45:38.497018 VALID_LAT_VALUE = 1
2310 11:45:38.503393 ==============================================================
2311 11:45:38.506986 Enter into Gating configuration >>>>
2312 11:45:38.510341 Exit from Gating configuration <<<<
2313 11:45:38.513385 Enter into DVFS_PRE_config >>>>>
2314 11:45:38.523542 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2315 11:45:38.526971 Exit from DVFS_PRE_config <<<<<
2316 11:45:38.530385 Enter into PICG configuration >>>>
2317 11:45:38.533733 Exit from PICG configuration <<<<
2318 11:45:38.536511 [RX_INPUT] configuration >>>>>
2319 11:45:38.540000 [RX_INPUT] configuration <<<<<
2320 11:45:38.543408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2321 11:45:38.550087 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2322 11:45:38.556938 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 11:45:38.563460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 11:45:38.569918 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2325 11:45:38.572983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2326 11:45:38.579793 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2327 11:45:38.583393 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2328 11:45:38.586616 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2329 11:45:38.589987 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2330 11:45:38.596638 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2331 11:45:38.600048 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2332 11:45:38.603002 ===================================
2333 11:45:38.606247 LPDDR4 DRAM CONFIGURATION
2334 11:45:38.609707 ===================================
2335 11:45:38.610527 EX_ROW_EN[0] = 0x0
2336 11:45:38.613212 EX_ROW_EN[1] = 0x0
2337 11:45:38.613722 LP4Y_EN = 0x0
2338 11:45:38.616093 WORK_FSP = 0x0
2339 11:45:38.616591 WL = 0x4
2340 11:45:38.619512 RL = 0x4
2341 11:45:38.619969 BL = 0x2
2342 11:45:38.623151 RPST = 0x0
2343 11:45:38.623570 RD_PRE = 0x0
2344 11:45:38.626223 WR_PRE = 0x1
2345 11:45:38.629778 WR_PST = 0x0
2346 11:45:38.630276 DBI_WR = 0x0
2347 11:45:38.633070 DBI_RD = 0x0
2348 11:45:38.633502 OTF = 0x1
2349 11:45:38.635897 ===================================
2350 11:45:38.639428 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2351 11:45:38.643088 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2352 11:45:38.649244 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2353 11:45:38.652807 ===================================
2354 11:45:38.656347 LPDDR4 DRAM CONFIGURATION
2355 11:45:38.659233 ===================================
2356 11:45:38.659786 EX_ROW_EN[0] = 0x10
2357 11:45:38.662763 EX_ROW_EN[1] = 0x0
2358 11:45:38.663310 LP4Y_EN = 0x0
2359 11:45:38.665730 WORK_FSP = 0x0
2360 11:45:38.666281 WL = 0x4
2361 11:45:38.669127 RL = 0x4
2362 11:45:38.669535 BL = 0x2
2363 11:45:38.672430 RPST = 0x0
2364 11:45:38.672879 RD_PRE = 0x0
2365 11:45:38.676079 WR_PRE = 0x1
2366 11:45:38.676637 WR_PST = 0x0
2367 11:45:38.678810 DBI_WR = 0x0
2368 11:45:38.682840 DBI_RD = 0x0
2369 11:45:38.683256 OTF = 0x1
2370 11:45:38.685672 ===================================
2371 11:45:38.692091 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2372 11:45:38.692693 ==
2373 11:45:38.695608 Dram Type= 6, Freq= 0, CH_0, rank 0
2374 11:45:38.699122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 11:45:38.699649 ==
2376 11:45:38.701948 [Duty_Offset_Calibration]
2377 11:45:38.702462 B0:1 B1:-1 CA:0
2378 11:45:38.705607
2379 11:45:38.708596 [DutyScan_Calibration_Flow] k_type=0
2380 11:45:38.716876
2381 11:45:38.717176 ==CLK 0==
2382 11:45:38.720222 Final CLK duty delay cell = 0
2383 11:45:38.723125 [0] MAX Duty = 5125%(X100), DQS PI = 22
2384 11:45:38.726470 [0] MIN Duty = 4875%(X100), DQS PI = 8
2385 11:45:38.726780 [0] AVG Duty = 5000%(X100)
2386 11:45:38.729926
2387 11:45:38.733248 CH0 CLK Duty spec in!! Max-Min= 250%
2388 11:45:38.736361 [DutyScan_Calibration_Flow] ====Done====
2389 11:45:38.736731
2390 11:45:38.739696 [DutyScan_Calibration_Flow] k_type=1
2391 11:45:38.754117
2392 11:45:38.754409 ==DQS 0 ==
2393 11:45:38.757534 Final DQS duty delay cell = -4
2394 11:45:38.761083 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2395 11:45:38.763891 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2396 11:45:38.767458 [-4] AVG Duty = 4968%(X100)
2397 11:45:38.767613
2398 11:45:38.767734 ==DQS 1 ==
2399 11:45:38.770745 Final DQS duty delay cell = -4
2400 11:45:38.773991 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2401 11:45:38.777379 [-4] MIN Duty = 4876%(X100), DQS PI = 22
2402 11:45:38.780324 [-4] AVG Duty = 4938%(X100)
2403 11:45:38.780427
2404 11:45:38.783650 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2405 11:45:38.783776
2406 11:45:38.787481 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2407 11:45:38.790489 [DutyScan_Calibration_Flow] ====Done====
2408 11:45:38.790600
2409 11:45:38.794156 [DutyScan_Calibration_Flow] k_type=3
2410 11:45:38.812215
2411 11:45:38.812333 ==DQM 0 ==
2412 11:45:38.815101 Final DQM duty delay cell = 0
2413 11:45:38.818625 [0] MAX Duty = 5031%(X100), DQS PI = 16
2414 11:45:38.821932 [0] MIN Duty = 4875%(X100), DQS PI = 6
2415 11:45:38.825303 [0] AVG Duty = 4953%(X100)
2416 11:45:38.825398
2417 11:45:38.825466 ==DQM 1 ==
2418 11:45:38.828330 Final DQM duty delay cell = 4
2419 11:45:38.831722 [4] MAX Duty = 5187%(X100), DQS PI = 14
2420 11:45:38.835320 [4] MIN Duty = 5000%(X100), DQS PI = 24
2421 11:45:38.838619 [4] AVG Duty = 5093%(X100)
2422 11:45:38.838752
2423 11:45:38.842232 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2424 11:45:38.842308
2425 11:45:38.845061 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2426 11:45:38.848460 [DutyScan_Calibration_Flow] ====Done====
2427 11:45:38.848560
2428 11:45:38.852004 [DutyScan_Calibration_Flow] k_type=2
2429 11:45:38.866709
2430 11:45:38.866900 ==DQ 0 ==
2431 11:45:38.870234 Final DQ duty delay cell = -4
2432 11:45:38.873572 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2433 11:45:38.876943 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2434 11:45:38.880090 [-4] AVG Duty = 4953%(X100)
2435 11:45:38.880241
2436 11:45:38.880388 ==DQ 1 ==
2437 11:45:38.883597 Final DQ duty delay cell = -4
2438 11:45:38.887061 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2439 11:45:38.890427 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2440 11:45:38.894046 [-4] AVG Duty = 4938%(X100)
2441 11:45:38.894197
2442 11:45:38.896934 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2443 11:45:38.897178
2444 11:45:38.900396 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2445 11:45:38.903303 [DutyScan_Calibration_Flow] ====Done====
2446 11:45:38.903554 ==
2447 11:45:38.907027 Dram Type= 6, Freq= 0, CH_1, rank 0
2448 11:45:38.910561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 11:45:38.910710 ==
2450 11:45:38.913360 [Duty_Offset_Calibration]
2451 11:45:38.913508 B0:-1 B1:1 CA:1
2452 11:45:38.913626
2453 11:45:38.916668 [DutyScan_Calibration_Flow] k_type=0
2454 11:45:38.928104
2455 11:45:38.928258 ==CLK 0==
2456 11:45:38.931008 Final CLK duty delay cell = 0
2457 11:45:38.934470 [0] MAX Duty = 5156%(X100), DQS PI = 2
2458 11:45:38.938033 [0] MIN Duty = 5000%(X100), DQS PI = 28
2459 11:45:38.940893 [0] AVG Duty = 5078%(X100)
2460 11:45:38.941049
2461 11:45:38.944323 CH1 CLK Duty spec in!! Max-Min= 156%
2462 11:45:38.947210 [DutyScan_Calibration_Flow] ====Done====
2463 11:45:38.947362
2464 11:45:38.950634 [DutyScan_Calibration_Flow] k_type=1
2465 11:45:38.967280
2466 11:45:38.967477 ==DQS 0 ==
2467 11:45:38.970256 Final DQS duty delay cell = 0
2468 11:45:38.973729 [0] MAX Duty = 5125%(X100), DQS PI = 16
2469 11:45:38.977109 [0] MIN Duty = 4907%(X100), DQS PI = 38
2470 11:45:38.980351 [0] AVG Duty = 5016%(X100)
2471 11:45:38.980761
2472 11:45:38.981136 ==DQS 1 ==
2473 11:45:38.983678 Final DQS duty delay cell = 0
2474 11:45:38.986627 [0] MAX Duty = 5062%(X100), DQS PI = 0
2475 11:45:38.989916 [0] MIN Duty = 4969%(X100), DQS PI = 26
2476 11:45:38.993840 [0] AVG Duty = 5015%(X100)
2477 11:45:38.994236
2478 11:45:38.996827 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2479 11:45:38.997216
2480 11:45:39.000266 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2481 11:45:39.003264 [DutyScan_Calibration_Flow] ====Done====
2482 11:45:39.003514
2483 11:45:39.006899 [DutyScan_Calibration_Flow] k_type=3
2484 11:45:39.022586
2485 11:45:39.022717 ==DQM 0 ==
2486 11:45:39.025875 Final DQM duty delay cell = -4
2487 11:45:39.029458 [-4] MAX Duty = 5062%(X100), DQS PI = 0
2488 11:45:39.033007 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2489 11:45:39.035961 [-4] AVG Duty = 4969%(X100)
2490 11:45:39.036399
2491 11:45:39.036884 ==DQM 1 ==
2492 11:45:39.039307 Final DQM duty delay cell = 0
2493 11:45:39.042705 [0] MAX Duty = 5187%(X100), DQS PI = 34
2494 11:45:39.045811 [0] MIN Duty = 4969%(X100), DQS PI = 0
2495 11:45:39.049121 [0] AVG Duty = 5078%(X100)
2496 11:45:39.049789
2497 11:45:39.052562 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2498 11:45:39.053268
2499 11:45:39.056092 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2500 11:45:39.059597 [DutyScan_Calibration_Flow] ====Done====
2501 11:45:39.060081
2502 11:45:39.062833 [DutyScan_Calibration_Flow] k_type=2
2503 11:45:39.079199
2504 11:45:39.079447 ==DQ 0 ==
2505 11:45:39.082600 Final DQ duty delay cell = 0
2506 11:45:39.085858 [0] MAX Duty = 5156%(X100), DQS PI = 62
2507 11:45:39.089710 [0] MIN Duty = 4907%(X100), DQS PI = 38
2508 11:45:39.089813 [0] AVG Duty = 5031%(X100)
2509 11:45:39.089895
2510 11:45:39.092634 ==DQ 1 ==
2511 11:45:39.095912 Final DQ duty delay cell = 0
2512 11:45:39.099453 [0] MAX Duty = 5124%(X100), DQS PI = 42
2513 11:45:39.102213 [0] MIN Duty = 4969%(X100), DQS PI = 2
2514 11:45:39.102310 [0] AVG Duty = 5046%(X100)
2515 11:45:39.105898
2516 11:45:39.109059 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2517 11:45:39.109511
2518 11:45:39.112774 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2519 11:45:39.115627 [DutyScan_Calibration_Flow] ====Done====
2520 11:45:39.119042 nWR fixed to 30
2521 11:45:39.119787 [ModeRegInit_LP4] CH0 RK0
2522 11:45:39.122710 [ModeRegInit_LP4] CH0 RK1
2523 11:45:39.125775 [ModeRegInit_LP4] CH1 RK0
2524 11:45:39.128923 [ModeRegInit_LP4] CH1 RK1
2525 11:45:39.129320 match AC timing 7
2526 11:45:39.135063 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2527 11:45:39.138439 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2528 11:45:39.142103 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2529 11:45:39.148950 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2530 11:45:39.151958 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2531 11:45:39.152379 ==
2532 11:45:39.155411 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 11:45:39.158682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 11:45:39.159107 ==
2535 11:45:39.165183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 11:45:39.172512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2537 11:45:39.179485 [CA 0] Center 39 (9~70) winsize 62
2538 11:45:39.182809 [CA 1] Center 39 (9~69) winsize 61
2539 11:45:39.186165 [CA 2] Center 35 (5~66) winsize 62
2540 11:45:39.189565 [CA 3] Center 35 (5~66) winsize 62
2541 11:45:39.192694 [CA 4] Center 33 (4~63) winsize 60
2542 11:45:39.196154 [CA 5] Center 33 (3~63) winsize 61
2543 11:45:39.196605
2544 11:45:39.199396 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2545 11:45:39.199815
2546 11:45:39.202155 [CATrainingPosCal] consider 1 rank data
2547 11:45:39.205698 u2DelayCellTimex100 = 270/100 ps
2548 11:45:39.208908 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2549 11:45:39.215866 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2550 11:45:39.218889 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2551 11:45:39.222379 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2552 11:45:39.225914 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2553 11:45:39.228698 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2554 11:45:39.229118
2555 11:45:39.232271 CA PerBit enable=1, Macro0, CA PI delay=33
2556 11:45:39.232836
2557 11:45:39.235615 [CBTSetCACLKResult] CA Dly = 33
2558 11:45:39.236032 CS Dly: 8 (0~39)
2559 11:45:39.238956 ==
2560 11:45:39.242315 Dram Type= 6, Freq= 0, CH_0, rank 1
2561 11:45:39.245434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 11:45:39.245854 ==
2563 11:45:39.248759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2564 11:45:39.255590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2565 11:45:39.265311 [CA 0] Center 39 (9~70) winsize 62
2566 11:45:39.268279 [CA 1] Center 39 (9~70) winsize 62
2567 11:45:39.271678 [CA 2] Center 35 (5~66) winsize 62
2568 11:45:39.275160 [CA 3] Center 34 (4~65) winsize 62
2569 11:45:39.278562 [CA 4] Center 33 (3~64) winsize 62
2570 11:45:39.282171 [CA 5] Center 33 (3~63) winsize 61
2571 11:45:39.282601
2572 11:45:39.284761 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2573 11:45:39.285188
2574 11:45:39.288118 [CATrainingPosCal] consider 2 rank data
2575 11:45:39.291543 u2DelayCellTimex100 = 270/100 ps
2576 11:45:39.295011 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2577 11:45:39.301572 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2578 11:45:39.304981 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2579 11:45:39.308229 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2580 11:45:39.311265 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2581 11:45:39.314902 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2582 11:45:39.315334
2583 11:45:39.318492 CA PerBit enable=1, Macro0, CA PI delay=33
2584 11:45:39.318917
2585 11:45:39.321514 [CBTSetCACLKResult] CA Dly = 33
2586 11:45:39.321940 CS Dly: 9 (0~41)
2587 11:45:39.325242
2588 11:45:39.328008 ----->DramcWriteLeveling(PI) begin...
2589 11:45:39.328442 ==
2590 11:45:39.331328 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 11:45:39.334849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 11:45:39.335372 ==
2593 11:45:39.338173 Write leveling (Byte 0): 33 => 33
2594 11:45:39.341620 Write leveling (Byte 1): 29 => 29
2595 11:45:39.345082 DramcWriteLeveling(PI) end<-----
2596 11:45:39.345509
2597 11:45:39.345846 ==
2598 11:45:39.347907 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 11:45:39.351472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 11:45:39.351902 ==
2601 11:45:39.354799 [Gating] SW mode calibration
2602 11:45:39.361639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2603 11:45:39.367934 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2604 11:45:39.371318 0 15 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2605 11:45:39.374879 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
2606 11:45:39.381054 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 11:45:39.384325 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:45:39.387864 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 11:45:39.394767 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 11:45:39.397914 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 11:45:39.401044 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
2612 11:45:39.407712 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2613 11:45:39.411178 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 11:45:39.414171 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 11:45:39.417654 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:45:39.424227 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 11:45:39.427826 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 11:45:39.430749 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 11:45:39.437831 1 0 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
2620 11:45:39.440763 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2621 11:45:39.444261 1 1 4 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
2622 11:45:39.450603 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 11:45:39.454139 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:45:39.457394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 11:45:39.464367 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 11:45:39.467199 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:45:39.470466 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2628 11:45:39.477421 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2629 11:45:39.480220 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2630 11:45:39.483875 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:45:39.490692 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:45:39.493652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:45:39.496993 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:45:39.503541 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:45:39.506843 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:45:39.510290 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:45:39.517107 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:45:39.520458 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:45:39.523487 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:45:39.529758 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:45:39.533316 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 11:45:39.536938 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 11:45:39.543063 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2644 11:45:39.546640 Total UI for P1: 0, mck2ui 16
2645 11:45:39.550199 best dqsien dly found for B0: ( 1, 3, 26)
2646 11:45:39.553465 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2647 11:45:39.556381 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2648 11:45:39.559994 Total UI for P1: 0, mck2ui 16
2649 11:45:39.563394 best dqsien dly found for B1: ( 1, 3, 30)
2650 11:45:39.566305 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2651 11:45:39.569988 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2652 11:45:39.570449
2653 11:45:39.576630 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2654 11:45:39.580140 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2655 11:45:39.580605 [Gating] SW calibration Done
2656 11:45:39.583087 ==
2657 11:45:39.586525 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 11:45:39.589991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 11:45:39.590414 ==
2660 11:45:39.590746 RX Vref Scan: 0
2661 11:45:39.591055
2662 11:45:39.593191 RX Vref 0 -> 0, step: 1
2663 11:45:39.593683
2664 11:45:39.596071 RX Delay -40 -> 252, step: 8
2665 11:45:39.599410 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2666 11:45:39.602763 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2667 11:45:39.609192 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2668 11:45:39.612482 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2669 11:45:39.616033 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2670 11:45:39.619369 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2671 11:45:39.623438 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2672 11:45:39.629367 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2673 11:45:39.633012 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2674 11:45:39.635978 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2675 11:45:39.639502 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2676 11:45:39.642915 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2677 11:45:39.649488 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2678 11:45:39.652931 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2679 11:45:39.655763 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2680 11:45:39.659249 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2681 11:45:39.659673 ==
2682 11:45:39.662825 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 11:45:39.669246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 11:45:39.669702 ==
2685 11:45:39.670220 DQS Delay:
2686 11:45:39.670700 DQS0 = 0, DQS1 = 0
2687 11:45:39.672092 DQM Delay:
2688 11:45:39.672456 DQM0 = 119, DQM1 = 106
2689 11:45:39.676099 DQ Delay:
2690 11:45:39.679330 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2691 11:45:39.682161 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2692 11:45:39.685870 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2693 11:45:39.689151 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2694 11:45:39.689589
2695 11:45:39.689920
2696 11:45:39.690242 ==
2697 11:45:39.692438 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 11:45:39.695891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 11:45:39.696327 ==
2700 11:45:39.699196
2701 11:45:39.699574
2702 11:45:39.699887 TX Vref Scan disable
2703 11:45:39.702130 == TX Byte 0 ==
2704 11:45:39.705493 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2705 11:45:39.708905 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2706 11:45:39.712172 == TX Byte 1 ==
2707 11:45:39.715416 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2708 11:45:39.718815 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2709 11:45:39.719235 ==
2710 11:45:39.722140 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 11:45:39.728926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 11:45:39.729381 ==
2713 11:45:39.739564 TX Vref=22, minBit 7, minWin=25, winSum=415
2714 11:45:39.743094 TX Vref=24, minBit 13, minWin=25, winSum=423
2715 11:45:39.746576 TX Vref=26, minBit 13, minWin=25, winSum=428
2716 11:45:39.749515 TX Vref=28, minBit 10, minWin=26, winSum=436
2717 11:45:39.753013 TX Vref=30, minBit 5, minWin=26, winSum=435
2718 11:45:39.759501 TX Vref=32, minBit 5, minWin=26, winSum=432
2719 11:45:39.762832 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 28
2720 11:45:39.763262
2721 11:45:39.766378 Final TX Range 1 Vref 28
2722 11:45:39.766814
2723 11:45:39.767148 ==
2724 11:45:39.769806 Dram Type= 6, Freq= 0, CH_0, rank 0
2725 11:45:39.776090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2726 11:45:39.776539 ==
2727 11:45:39.776885
2728 11:45:39.777248
2729 11:45:39.777556 TX Vref Scan disable
2730 11:45:39.779607 == TX Byte 0 ==
2731 11:45:39.783050 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2732 11:45:39.789952 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2733 11:45:39.790374 == TX Byte 1 ==
2734 11:45:39.792952 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2735 11:45:39.799530 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2736 11:45:39.800074
2737 11:45:39.800600 [DATLAT]
2738 11:45:39.801122 Freq=1200, CH0 RK0
2739 11:45:39.801636
2740 11:45:39.802968 DATLAT Default: 0xd
2741 11:45:39.806429 0, 0xFFFF, sum = 0
2742 11:45:39.806967 1, 0xFFFF, sum = 0
2743 11:45:39.809311 2, 0xFFFF, sum = 0
2744 11:45:39.809837 3, 0xFFFF, sum = 0
2745 11:45:39.812811 4, 0xFFFF, sum = 0
2746 11:45:39.813272 5, 0xFFFF, sum = 0
2747 11:45:39.815908 6, 0xFFFF, sum = 0
2748 11:45:39.816335 7, 0xFFFF, sum = 0
2749 11:45:39.819872 8, 0xFFFF, sum = 0
2750 11:45:39.820323 9, 0xFFFF, sum = 0
2751 11:45:39.822689 10, 0xFFFF, sum = 0
2752 11:45:39.823067 11, 0xFFFF, sum = 0
2753 11:45:39.826109 12, 0x0, sum = 1
2754 11:45:39.826545 13, 0x0, sum = 2
2755 11:45:39.829030 14, 0x0, sum = 3
2756 11:45:39.829457 15, 0x0, sum = 4
2757 11:45:39.832898 best_step = 13
2758 11:45:39.833366
2759 11:45:39.833697 ==
2760 11:45:39.835926 Dram Type= 6, Freq= 0, CH_0, rank 0
2761 11:45:39.839341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2762 11:45:39.839767 ==
2763 11:45:39.842396 RX Vref Scan: 1
2764 11:45:39.842816
2765 11:45:39.843149 Set Vref Range= 32 -> 127
2766 11:45:39.843462
2767 11:45:39.845914 RX Vref 32 -> 127, step: 1
2768 11:45:39.846333
2769 11:45:39.849396 RX Delay -21 -> 252, step: 4
2770 11:45:39.849820
2771 11:45:39.852376 Set Vref, RX VrefLevel [Byte0]: 32
2772 11:45:39.855814 [Byte1]: 32
2773 11:45:39.856235
2774 11:45:39.858866 Set Vref, RX VrefLevel [Byte0]: 33
2775 11:45:39.862416 [Byte1]: 33
2776 11:45:39.866510
2777 11:45:39.866931 Set Vref, RX VrefLevel [Byte0]: 34
2778 11:45:39.869830 [Byte1]: 34
2779 11:45:39.874520
2780 11:45:39.875043 Set Vref, RX VrefLevel [Byte0]: 35
2781 11:45:39.877465 [Byte1]: 35
2782 11:45:39.882259
2783 11:45:39.882682 Set Vref, RX VrefLevel [Byte0]: 36
2784 11:45:39.885679 [Byte1]: 36
2785 11:45:39.890231
2786 11:45:39.890788 Set Vref, RX VrefLevel [Byte0]: 37
2787 11:45:39.893517 [Byte1]: 37
2788 11:45:39.898233
2789 11:45:39.898656 Set Vref, RX VrefLevel [Byte0]: 38
2790 11:45:39.901714 [Byte1]: 38
2791 11:45:39.906149
2792 11:45:39.906734 Set Vref, RX VrefLevel [Byte0]: 39
2793 11:45:39.909448 [Byte1]: 39
2794 11:45:39.914161
2795 11:45:39.914586 Set Vref, RX VrefLevel [Byte0]: 40
2796 11:45:39.917189 [Byte1]: 40
2797 11:45:39.921416
2798 11:45:39.925048 Set Vref, RX VrefLevel [Byte0]: 41
2799 11:45:39.928484 [Byte1]: 41
2800 11:45:39.928827
2801 11:45:39.931790 Set Vref, RX VrefLevel [Byte0]: 42
2802 11:45:39.935004 [Byte1]: 42
2803 11:45:39.935313
2804 11:45:39.937876 Set Vref, RX VrefLevel [Byte0]: 43
2805 11:45:39.941545 [Byte1]: 43
2806 11:45:39.945847
2807 11:45:39.946271 Set Vref, RX VrefLevel [Byte0]: 44
2808 11:45:39.948924 [Byte1]: 44
2809 11:45:39.953575
2810 11:45:39.953997 Set Vref, RX VrefLevel [Byte0]: 45
2811 11:45:39.957078 [Byte1]: 45
2812 11:45:39.961803
2813 11:45:39.962530 Set Vref, RX VrefLevel [Byte0]: 46
2814 11:45:39.964733 [Byte1]: 46
2815 11:45:39.969195
2816 11:45:39.969610 Set Vref, RX VrefLevel [Byte0]: 47
2817 11:45:39.972572 [Byte1]: 47
2818 11:45:39.977581
2819 11:45:39.978027 Set Vref, RX VrefLevel [Byte0]: 48
2820 11:45:39.980503 [Byte1]: 48
2821 11:45:39.985239
2822 11:45:39.985657 Set Vref, RX VrefLevel [Byte0]: 49
2823 11:45:39.988802 [Byte1]: 49
2824 11:45:39.993404
2825 11:45:39.993820 Set Vref, RX VrefLevel [Byte0]: 50
2826 11:45:39.996596 [Byte1]: 50
2827 11:45:40.001416
2828 11:45:40.002166 Set Vref, RX VrefLevel [Byte0]: 51
2829 11:45:40.004104 [Byte1]: 51
2830 11:45:40.008803
2831 11:45:40.009195 Set Vref, RX VrefLevel [Byte0]: 52
2832 11:45:40.012220 [Byte1]: 52
2833 11:45:40.016952
2834 11:45:40.017367 Set Vref, RX VrefLevel [Byte0]: 53
2835 11:45:40.020397 [Byte1]: 53
2836 11:45:40.024830
2837 11:45:40.025559 Set Vref, RX VrefLevel [Byte0]: 54
2838 11:45:40.028482 [Byte1]: 54
2839 11:45:40.032578
2840 11:45:40.033001 Set Vref, RX VrefLevel [Byte0]: 55
2841 11:45:40.036176 [Byte1]: 55
2842 11:45:40.040497
2843 11:45:40.040962 Set Vref, RX VrefLevel [Byte0]: 56
2844 11:45:40.044259 [Byte1]: 56
2845 11:45:40.048912
2846 11:45:40.049666 Set Vref, RX VrefLevel [Byte0]: 57
2847 11:45:40.051746 [Byte1]: 57
2848 11:45:40.056393
2849 11:45:40.056836 Set Vref, RX VrefLevel [Byte0]: 58
2850 11:45:40.059960 [Byte1]: 58
2851 11:45:40.064747
2852 11:45:40.065162 Set Vref, RX VrefLevel [Byte0]: 59
2853 11:45:40.067575 [Byte1]: 59
2854 11:45:40.072256
2855 11:45:40.072850 Set Vref, RX VrefLevel [Byte0]: 60
2856 11:45:40.075817 [Byte1]: 60
2857 11:45:40.080003
2858 11:45:40.080463 Set Vref, RX VrefLevel [Byte0]: 61
2859 11:45:40.083760 [Byte1]: 61
2860 11:45:40.088218
2861 11:45:40.088770 Set Vref, RX VrefLevel [Byte0]: 62
2862 11:45:40.091740 [Byte1]: 62
2863 11:45:40.096372
2864 11:45:40.096848 Set Vref, RX VrefLevel [Byte0]: 63
2865 11:45:40.099178 [Byte1]: 63
2866 11:45:40.104217
2867 11:45:40.104450 Set Vref, RX VrefLevel [Byte0]: 64
2868 11:45:40.107175 [Byte1]: 64
2869 11:45:40.111769
2870 11:45:40.111965 Set Vref, RX VrefLevel [Byte0]: 65
2871 11:45:40.114961 [Byte1]: 65
2872 11:45:40.119819
2873 11:45:40.123174 Set Vref, RX VrefLevel [Byte0]: 66
2874 11:45:40.123310 [Byte1]: 66
2875 11:45:40.127600
2876 11:45:40.127716 Set Vref, RX VrefLevel [Byte0]: 67
2877 11:45:40.131004 [Byte1]: 67
2878 11:45:40.135313
2879 11:45:40.135434 Set Vref, RX VrefLevel [Byte0]: 68
2880 11:45:40.138819 [Byte1]: 68
2881 11:45:40.143311
2882 11:45:40.143432 Set Vref, RX VrefLevel [Byte0]: 69
2883 11:45:40.146650 [Byte1]: 69
2884 11:45:40.151386
2885 11:45:40.151508 Set Vref, RX VrefLevel [Byte0]: 70
2886 11:45:40.155216 [Byte1]: 70
2887 11:45:40.160029
2888 11:45:40.160618 Set Vref, RX VrefLevel [Byte0]: 71
2889 11:45:40.162970 [Byte1]: 71
2890 11:45:40.167762
2891 11:45:40.168312 Set Vref, RX VrefLevel [Byte0]: 72
2892 11:45:40.171136 [Byte1]: 72
2893 11:45:40.175105
2894 11:45:40.175529 Set Vref, RX VrefLevel [Byte0]: 73
2895 11:45:40.178722 [Byte1]: 73
2896 11:45:40.183236
2897 11:45:40.183625 Set Vref, RX VrefLevel [Byte0]: 74
2898 11:45:40.186892 [Byte1]: 74
2899 11:45:40.191304
2900 11:45:40.191731 Set Vref, RX VrefLevel [Byte0]: 75
2901 11:45:40.194779 [Byte1]: 75
2902 11:45:40.199344
2903 11:45:40.200089 Set Vref, RX VrefLevel [Byte0]: 76
2904 11:45:40.202833 [Byte1]: 76
2905 11:45:40.207345
2906 11:45:40.207772 Final RX Vref Byte 0 = 61 to rank0
2907 11:45:40.210229 Final RX Vref Byte 1 = 49 to rank0
2908 11:45:40.213684 Final RX Vref Byte 0 = 61 to rank1
2909 11:45:40.217064 Final RX Vref Byte 1 = 49 to rank1==
2910 11:45:40.220362 Dram Type= 6, Freq= 0, CH_0, rank 0
2911 11:45:40.226859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 11:45:40.227452 ==
2913 11:45:40.227935 DQS Delay:
2914 11:45:40.228393 DQS0 = 0, DQS1 = 0
2915 11:45:40.230589 DQM Delay:
2916 11:45:40.231040 DQM0 = 119, DQM1 = 107
2917 11:45:40.233985 DQ Delay:
2918 11:45:40.237255 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2919 11:45:40.240350 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =126
2920 11:45:40.243616 DQ8 =98, DQ9 =92, DQ10 =110, DQ11 =100
2921 11:45:40.246849 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2922 11:45:40.247277
2923 11:45:40.247612
2924 11:45:40.253771 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2925 11:45:40.256717 CH0 RK0: MR19=403, MR18=EFA
2926 11:45:40.263813 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2927 11:45:40.264241
2928 11:45:40.266884 ----->DramcWriteLeveling(PI) begin...
2929 11:45:40.267311 ==
2930 11:45:40.270346 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 11:45:40.273965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 11:45:40.274362 ==
2933 11:45:40.277299 Write leveling (Byte 0): 32 => 32
2934 11:45:40.280243 Write leveling (Byte 1): 32 => 32
2935 11:45:40.283726 DramcWriteLeveling(PI) end<-----
2936 11:45:40.284157
2937 11:45:40.284589 ==
2938 11:45:40.286742 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 11:45:40.293751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 11:45:40.294174 ==
2941 11:45:40.294508 [Gating] SW mode calibration
2942 11:45:40.303539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2943 11:45:40.307020 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2944 11:45:40.310221 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2945 11:45:40.316730 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 11:45:40.320048 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 11:45:40.323764 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 11:45:40.329773 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 11:45:40.333332 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 11:45:40.336616 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2951 11:45:40.343244 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2952 11:45:40.346745 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2953 11:45:40.350101 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 11:45:40.356720 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 11:45:40.359622 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 11:45:40.363341 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 11:45:40.369904 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 11:45:40.372832 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 11:45:40.375950 1 0 28 | B1->B0 | 2525 3130 | 0 1 | (0 0) (0 0)
2960 11:45:40.383069 1 1 0 | B1->B0 | 3737 4545 | 0 1 | (0 0) (0 0)
2961 11:45:40.386011 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 11:45:40.389383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 11:45:40.396300 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 11:45:40.399351 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 11:45:40.403146 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 11:45:40.409288 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 11:45:40.412870 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2968 11:45:40.416103 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2969 11:45:40.422553 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 11:45:40.425930 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 11:45:40.429508 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 11:45:40.436189 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 11:45:40.439586 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 11:45:40.442901 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 11:45:40.449661 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 11:45:40.452372 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:45:40.455682 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:45:40.462585 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:45:40.466147 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:45:40.469234 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:45:40.475675 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:45:40.479262 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:45:40.482771 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2984 11:45:40.486051 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2985 11:45:40.489625 Total UI for P1: 0, mck2ui 16
2986 11:45:40.492888 best dqsien dly found for B0: ( 1, 3, 28)
2987 11:45:40.499204 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 11:45:40.502230 Total UI for P1: 0, mck2ui 16
2989 11:45:40.506022 best dqsien dly found for B1: ( 1, 4, 0)
2990 11:45:40.508967 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2991 11:45:40.512017 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2992 11:45:40.512588
2993 11:45:40.515555 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2994 11:45:40.519513 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2995 11:45:40.522265 [Gating] SW calibration Done
2996 11:45:40.522815 ==
2997 11:45:40.526105 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 11:45:40.529208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 11:45:40.529676 ==
3000 11:45:40.532843 RX Vref Scan: 0
3001 11:45:40.533263
3002 11:45:40.533598 RX Vref 0 -> 0, step: 1
3003 11:45:40.533963
3004 11:45:40.535503 RX Delay -40 -> 252, step: 8
3005 11:45:40.542481 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3006 11:45:40.545953 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3007 11:45:40.549243 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3008 11:45:40.552611 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3009 11:45:40.555410 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3010 11:45:40.562206 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3011 11:45:40.565269 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3012 11:45:40.568987 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3013 11:45:40.571936 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3014 11:45:40.575456 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3015 11:45:40.578519 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3016 11:45:40.585497 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3017 11:45:40.589071 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3018 11:45:40.592114 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3019 11:45:40.595386 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3020 11:45:40.601652 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3021 11:45:40.602074 ==
3022 11:45:40.605117 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 11:45:40.608665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 11:45:40.609143 ==
3025 11:45:40.609485 DQS Delay:
3026 11:45:40.611968 DQS0 = 0, DQS1 = 0
3027 11:45:40.612583 DQM Delay:
3028 11:45:40.615462 DQM0 = 117, DQM1 = 108
3029 11:45:40.616007 DQ Delay:
3030 11:45:40.618369 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3031 11:45:40.621749 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3032 11:45:40.625063 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3033 11:45:40.628791 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3034 11:45:40.629346
3035 11:45:40.629825
3036 11:45:40.630280 ==
3037 11:45:40.631626 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 11:45:40.638637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 11:45:40.639420 ==
3040 11:45:40.640103
3041 11:45:40.640617
3042 11:45:40.642213 TX Vref Scan disable
3043 11:45:40.642640 == TX Byte 0 ==
3044 11:45:40.644939 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3045 11:45:40.651488 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3046 11:45:40.651921 == TX Byte 1 ==
3047 11:45:40.654724 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3048 11:45:40.661449 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3049 11:45:40.662226 ==
3050 11:45:40.664832 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 11:45:40.667829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 11:45:40.668262 ==
3053 11:45:40.680174 TX Vref=22, minBit 5, minWin=25, winSum=418
3054 11:45:40.683637 TX Vref=24, minBit 5, minWin=25, winSum=426
3055 11:45:40.686463 TX Vref=26, minBit 13, minWin=25, winSum=427
3056 11:45:40.690061 TX Vref=28, minBit 10, minWin=26, winSum=431
3057 11:45:40.693565 TX Vref=30, minBit 13, minWin=26, winSum=433
3058 11:45:40.700044 TX Vref=32, minBit 8, minWin=26, winSum=427
3059 11:45:40.702990 [TxChooseVref] Worse bit 13, Min win 26, Win sum 433, Final Vref 30
3060 11:45:40.703420
3061 11:45:40.706223 Final TX Range 1 Vref 30
3062 11:45:40.706653
3063 11:45:40.706992 ==
3064 11:45:40.709759 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 11:45:40.716126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 11:45:40.716597 ==
3067 11:45:40.716951
3068 11:45:40.717268
3069 11:45:40.717572 TX Vref Scan disable
3070 11:45:40.720095 == TX Byte 0 ==
3071 11:45:40.723533 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3072 11:45:40.730211 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3073 11:45:40.730643 == TX Byte 1 ==
3074 11:45:40.733089 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3075 11:45:40.740104 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3076 11:45:40.740562
3077 11:45:40.740904 [DATLAT]
3078 11:45:40.741223 Freq=1200, CH0 RK1
3079 11:45:40.741532
3080 11:45:40.743413 DATLAT Default: 0xd
3081 11:45:40.743838 0, 0xFFFF, sum = 0
3082 11:45:40.746473 1, 0xFFFF, sum = 0
3083 11:45:40.749855 2, 0xFFFF, sum = 0
3084 11:45:40.750286 3, 0xFFFF, sum = 0
3085 11:45:40.753434 4, 0xFFFF, sum = 0
3086 11:45:40.753866 5, 0xFFFF, sum = 0
3087 11:45:40.756405 6, 0xFFFF, sum = 0
3088 11:45:40.756877 7, 0xFFFF, sum = 0
3089 11:45:40.759896 8, 0xFFFF, sum = 0
3090 11:45:40.760330 9, 0xFFFF, sum = 0
3091 11:45:40.763031 10, 0xFFFF, sum = 0
3092 11:45:40.763465 11, 0xFFFF, sum = 0
3093 11:45:40.766591 12, 0x0, sum = 1
3094 11:45:40.767022 13, 0x0, sum = 2
3095 11:45:40.769508 14, 0x0, sum = 3
3096 11:45:40.769942 15, 0x0, sum = 4
3097 11:45:40.773629 best_step = 13
3098 11:45:40.774054
3099 11:45:40.774392 ==
3100 11:45:40.776213 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 11:45:40.779782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 11:45:40.780218 ==
3103 11:45:40.780618 RX Vref Scan: 0
3104 11:45:40.780949
3105 11:45:40.783217 RX Vref 0 -> 0, step: 1
3106 11:45:40.783644
3107 11:45:40.786449 RX Delay -21 -> 252, step: 4
3108 11:45:40.789917 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3109 11:45:40.796439 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3110 11:45:40.799527 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3111 11:45:40.802911 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3112 11:45:40.806378 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3113 11:45:40.809796 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3114 11:45:40.816184 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3115 11:45:40.819346 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3116 11:45:40.822810 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3117 11:45:40.826346 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3118 11:45:40.829895 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3119 11:45:40.836053 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3120 11:45:40.839624 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3121 11:45:40.842276 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3122 11:45:40.845828 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3123 11:45:40.852802 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3124 11:45:40.853475 ==
3125 11:45:40.856216 Dram Type= 6, Freq= 0, CH_0, rank 1
3126 11:45:40.859413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 11:45:40.859978 ==
3128 11:45:40.860455 DQS Delay:
3129 11:45:40.862337 DQS0 = 0, DQS1 = 0
3130 11:45:40.862753 DQM Delay:
3131 11:45:40.866023 DQM0 = 116, DQM1 = 107
3132 11:45:40.866620 DQ Delay:
3133 11:45:40.869303 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3134 11:45:40.872253 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3135 11:45:40.875605 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3136 11:45:40.878982 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3137 11:45:40.879542
3138 11:45:40.880021
3139 11:45:40.888826 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3140 11:45:40.892337 CH0 RK1: MR19=403, MR18=DE8
3141 11:45:40.895311 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3142 11:45:40.898910 [RxdqsGatingPostProcess] freq 1200
3143 11:45:40.905261 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3144 11:45:40.908539 best DQS0 dly(2T, 0.5T) = (0, 11)
3145 11:45:40.912108 best DQS1 dly(2T, 0.5T) = (0, 11)
3146 11:45:40.915441 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3147 11:45:40.918674 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3148 11:45:40.922101 best DQS0 dly(2T, 0.5T) = (0, 11)
3149 11:45:40.924982 best DQS1 dly(2T, 0.5T) = (0, 12)
3150 11:45:40.928764 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3151 11:45:40.932256 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3152 11:45:40.935219 Pre-setting of DQS Precalculation
3153 11:45:40.938469 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3154 11:45:40.939017 ==
3155 11:45:40.941878 Dram Type= 6, Freq= 0, CH_1, rank 0
3156 11:45:40.945030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 11:45:40.945579 ==
3158 11:45:40.951849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3159 11:45:40.958766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3160 11:45:40.965989 [CA 0] Center 37 (8~67) winsize 60
3161 11:45:40.969804 [CA 1] Center 37 (7~68) winsize 62
3162 11:45:40.972555 [CA 2] Center 34 (4~64) winsize 61
3163 11:45:40.975791 [CA 3] Center 33 (3~64) winsize 62
3164 11:45:40.979165 [CA 4] Center 34 (4~64) winsize 61
3165 11:45:40.982241 [CA 5] Center 33 (3~64) winsize 62
3166 11:45:40.982538
3167 11:45:40.985772 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3168 11:45:40.986008
3169 11:45:40.988810 [CATrainingPosCal] consider 1 rank data
3170 11:45:40.992294 u2DelayCellTimex100 = 270/100 ps
3171 11:45:40.995915 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3172 11:45:41.002400 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3173 11:45:41.005774 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3174 11:45:41.008743 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3175 11:45:41.012264 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3176 11:45:41.015646 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3177 11:45:41.015730
3178 11:45:41.018808 CA PerBit enable=1, Macro0, CA PI delay=33
3179 11:45:41.018893
3180 11:45:41.022400 [CBTSetCACLKResult] CA Dly = 33
3181 11:45:41.025116 CS Dly: 5 (0~36)
3182 11:45:41.025258 ==
3183 11:45:41.028424 Dram Type= 6, Freq= 0, CH_1, rank 1
3184 11:45:41.032094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 11:45:41.032178 ==
3186 11:45:41.038960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3187 11:45:41.041717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3188 11:45:41.051887 [CA 0] Center 37 (7~67) winsize 61
3189 11:45:41.055115 [CA 1] Center 38 (8~68) winsize 61
3190 11:45:41.058531 [CA 2] Center 34 (3~65) winsize 63
3191 11:45:41.061240 [CA 3] Center 34 (4~64) winsize 61
3192 11:45:41.064709 [CA 4] Center 34 (3~65) winsize 63
3193 11:45:41.068504 [CA 5] Center 33 (3~64) winsize 62
3194 11:45:41.068981
3195 11:45:41.071882 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3196 11:45:41.072313
3197 11:45:41.075265 [CATrainingPosCal] consider 2 rank data
3198 11:45:41.078463 u2DelayCellTimex100 = 270/100 ps
3199 11:45:41.081484 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3200 11:45:41.088183 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3201 11:45:41.091768 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3202 11:45:41.095250 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3203 11:45:41.098346 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3204 11:45:41.101850 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3205 11:45:41.102276
3206 11:45:41.104709 CA PerBit enable=1, Macro0, CA PI delay=33
3207 11:45:41.105086
3208 11:45:41.108146 [CBTSetCACLKResult] CA Dly = 33
3209 11:45:41.108717 CS Dly: 7 (0~40)
3210 11:45:41.111121
3211 11:45:41.114644 ----->DramcWriteLeveling(PI) begin...
3212 11:45:41.115082 ==
3213 11:45:41.118210 Dram Type= 6, Freq= 0, CH_1, rank 0
3214 11:45:41.121466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3215 11:45:41.121773 ==
3216 11:45:41.124912 Write leveling (Byte 0): 24 => 24
3217 11:45:41.127967 Write leveling (Byte 1): 29 => 29
3218 11:45:41.131389 DramcWriteLeveling(PI) end<-----
3219 11:45:41.131573
3220 11:45:41.131720 ==
3221 11:45:41.134930 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 11:45:41.137740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 11:45:41.138010 ==
3224 11:45:41.141155 [Gating] SW mode calibration
3225 11:45:41.147720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3226 11:45:41.154557 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3227 11:45:41.158121 0 15 0 | B1->B0 | 2f2e 3434 | 1 1 | (0 0) (1 1)
3228 11:45:41.161299 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 11:45:41.167540 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 11:45:41.171000 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 11:45:41.174440 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 11:45:41.181200 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3233 11:45:41.184409 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3234 11:45:41.187628 0 15 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
3235 11:45:41.194282 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 11:45:41.197146 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 11:45:41.200814 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 11:45:41.207062 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 11:45:41.210655 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 11:45:41.213749 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3241 11:45:41.220691 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
3242 11:45:41.223940 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3243 11:45:41.227451 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 11:45:41.233954 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 11:45:41.237349 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 11:45:41.240219 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 11:45:41.243852 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 11:45:41.250572 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 11:45:41.253670 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3250 11:45:41.257129 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3251 11:45:41.263818 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 11:45:41.266654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 11:45:41.270174 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 11:45:41.276719 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 11:45:41.280010 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 11:45:41.283443 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 11:45:41.290378 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 11:45:41.293675 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 11:45:41.296335 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 11:45:41.303250 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 11:45:41.306794 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 11:45:41.309840 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 11:45:41.316847 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 11:45:41.319747 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 11:45:41.323222 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3266 11:45:41.329644 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3267 11:45:41.329828 Total UI for P1: 0, mck2ui 16
3268 11:45:41.336807 best dqsien dly found for B0: ( 1, 3, 24)
3269 11:45:41.339497 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3270 11:45:41.343080 Total UI for P1: 0, mck2ui 16
3271 11:45:41.346719 best dqsien dly found for B1: ( 1, 3, 26)
3272 11:45:41.349653 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3273 11:45:41.352899 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3274 11:45:41.353070
3275 11:45:41.356409 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3276 11:45:41.359906 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3277 11:45:41.362856 [Gating] SW calibration Done
3278 11:45:41.363009 ==
3279 11:45:41.366338 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 11:45:41.369754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 11:45:41.373475 ==
3282 11:45:41.373637 RX Vref Scan: 0
3283 11:45:41.373705
3284 11:45:41.376084 RX Vref 0 -> 0, step: 1
3285 11:45:41.376204
3286 11:45:41.379560 RX Delay -40 -> 252, step: 8
3287 11:45:41.382963 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3288 11:45:41.386156 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3289 11:45:41.389570 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3290 11:45:41.392783 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
3291 11:45:41.399655 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3292 11:45:41.402446 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3293 11:45:41.406074 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3294 11:45:41.409563 iDelay=208, Bit 7, Center 119 (56 ~ 183) 128
3295 11:45:41.412502 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3296 11:45:41.419499 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3297 11:45:41.422547 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3298 11:45:41.425915 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3299 11:45:41.428860 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3300 11:45:41.432328 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3301 11:45:41.439472 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3302 11:45:41.442218 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3303 11:45:41.442380 ==
3304 11:45:41.445676 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 11:45:41.448827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 11:45:41.448997 ==
3307 11:45:41.452201 DQS Delay:
3308 11:45:41.452364 DQS0 = 0, DQS1 = 0
3309 11:45:41.452463 DQM Delay:
3310 11:45:41.455522 DQM0 = 120, DQM1 = 111
3311 11:45:41.455683 DQ Delay:
3312 11:45:41.458910 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3313 11:45:41.462375 DQ4 =115, DQ5 =131, DQ6 =127, DQ7 =119
3314 11:45:41.465332 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =99
3315 11:45:41.472201 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3316 11:45:41.472382
3317 11:45:41.472476
3318 11:45:41.472613 ==
3319 11:45:41.475518 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 11:45:41.478918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 11:45:41.479094 ==
3322 11:45:41.479192
3323 11:45:41.479282
3324 11:45:41.481878 TX Vref Scan disable
3325 11:45:41.485390 == TX Byte 0 ==
3326 11:45:41.488618 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3327 11:45:41.491969 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3328 11:45:41.495228 == TX Byte 1 ==
3329 11:45:41.498728 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3330 11:45:41.502010 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3331 11:45:41.502169 ==
3332 11:45:41.505496 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 11:45:41.508527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 11:45:41.508772 ==
3335 11:45:41.522049 TX Vref=22, minBit 10, minWin=24, winSum=418
3336 11:45:41.525001 TX Vref=24, minBit 9, minWin=25, winSum=419
3337 11:45:41.528566 TX Vref=26, minBit 10, minWin=25, winSum=425
3338 11:45:41.531520 TX Vref=28, minBit 3, minWin=26, winSum=427
3339 11:45:41.535060 TX Vref=30, minBit 0, minWin=26, winSum=425
3340 11:45:41.541383 TX Vref=32, minBit 9, minWin=25, winSum=419
3341 11:45:41.544865 [TxChooseVref] Worse bit 3, Min win 26, Win sum 427, Final Vref 28
3342 11:45:41.545021
3343 11:45:41.548140 Final TX Range 1 Vref 28
3344 11:45:41.548285
3345 11:45:41.548355 ==
3346 11:45:41.551712 Dram Type= 6, Freq= 0, CH_1, rank 0
3347 11:45:41.555144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3348 11:45:41.558037 ==
3349 11:45:41.558190
3350 11:45:41.558261
3351 11:45:41.558322 TX Vref Scan disable
3352 11:45:41.561948 == TX Byte 0 ==
3353 11:45:41.564939 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3354 11:45:41.571437 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3355 11:45:41.571635 == TX Byte 1 ==
3356 11:45:41.574860 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3357 11:45:41.581706 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3358 11:45:41.581920
3359 11:45:41.582035 [DATLAT]
3360 11:45:41.582134 Freq=1200, CH1 RK0
3361 11:45:41.582224
3362 11:45:41.584722 DATLAT Default: 0xd
3363 11:45:41.584967 0, 0xFFFF, sum = 0
3364 11:45:41.588047 1, 0xFFFF, sum = 0
3365 11:45:41.591360 2, 0xFFFF, sum = 0
3366 11:45:41.591510 3, 0xFFFF, sum = 0
3367 11:45:41.594825 4, 0xFFFF, sum = 0
3368 11:45:41.594962 5, 0xFFFF, sum = 0
3369 11:45:41.597899 6, 0xFFFF, sum = 0
3370 11:45:41.598040 7, 0xFFFF, sum = 0
3371 11:45:41.601273 8, 0xFFFF, sum = 0
3372 11:45:41.601414 9, 0xFFFF, sum = 0
3373 11:45:41.604937 10, 0xFFFF, sum = 0
3374 11:45:41.605110 11, 0xFFFF, sum = 0
3375 11:45:41.608178 12, 0x0, sum = 1
3376 11:45:41.608340 13, 0x0, sum = 2
3377 11:45:41.611686 14, 0x0, sum = 3
3378 11:45:41.611852 15, 0x0, sum = 4
3379 11:45:41.614789 best_step = 13
3380 11:45:41.614986
3381 11:45:41.615079 ==
3382 11:45:41.618195 Dram Type= 6, Freq= 0, CH_1, rank 0
3383 11:45:41.621674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3384 11:45:41.621860 ==
3385 11:45:41.621954 RX Vref Scan: 1
3386 11:45:41.624505
3387 11:45:41.624684 Set Vref Range= 32 -> 127
3388 11:45:41.624751
3389 11:45:41.628118 RX Vref 32 -> 127, step: 1
3390 11:45:41.628245
3391 11:45:41.631188 RX Delay -13 -> 252, step: 4
3392 11:45:41.631357
3393 11:45:41.634192 Set Vref, RX VrefLevel [Byte0]: 32
3394 11:45:41.637609 [Byte1]: 32
3395 11:45:41.637749
3396 11:45:41.641058 Set Vref, RX VrefLevel [Byte0]: 33
3397 11:45:41.644582 [Byte1]: 33
3398 11:45:41.648228
3399 11:45:41.648377 Set Vref, RX VrefLevel [Byte0]: 34
3400 11:45:41.651529 [Byte1]: 34
3401 11:45:41.656209
3402 11:45:41.656370 Set Vref, RX VrefLevel [Byte0]: 35
3403 11:45:41.659256 [Byte1]: 35
3404 11:45:41.663777
3405 11:45:41.663926 Set Vref, RX VrefLevel [Byte0]: 36
3406 11:45:41.666961 [Byte1]: 36
3407 11:45:41.671789
3408 11:45:41.671968 Set Vref, RX VrefLevel [Byte0]: 37
3409 11:45:41.675309 [Byte1]: 37
3410 11:45:41.679782
3411 11:45:41.679964 Set Vref, RX VrefLevel [Byte0]: 38
3412 11:45:41.683018 [Byte1]: 38
3413 11:45:41.687938
3414 11:45:41.688194 Set Vref, RX VrefLevel [Byte0]: 39
3415 11:45:41.690784 [Byte1]: 39
3416 11:45:41.695780
3417 11:45:41.696025 Set Vref, RX VrefLevel [Byte0]: 40
3418 11:45:41.699137 [Byte1]: 40
3419 11:45:41.703472
3420 11:45:41.703699 Set Vref, RX VrefLevel [Byte0]: 41
3421 11:45:41.706851 [Byte1]: 41
3422 11:45:41.711287
3423 11:45:41.711532 Set Vref, RX VrefLevel [Byte0]: 42
3424 11:45:41.714677 [Byte1]: 42
3425 11:45:41.718806
3426 11:45:41.719041 Set Vref, RX VrefLevel [Byte0]: 43
3427 11:45:41.722442 [Byte1]: 43
3428 11:45:41.726899
3429 11:45:41.727128 Set Vref, RX VrefLevel [Byte0]: 44
3430 11:45:41.730119 [Byte1]: 44
3431 11:45:41.734648
3432 11:45:41.734884 Set Vref, RX VrefLevel [Byte0]: 45
3433 11:45:41.738246 [Byte1]: 45
3434 11:45:41.742487
3435 11:45:41.742718 Set Vref, RX VrefLevel [Byte0]: 46
3436 11:45:41.745751 [Byte1]: 46
3437 11:45:41.750496
3438 11:45:41.750732 Set Vref, RX VrefLevel [Byte0]: 47
3439 11:45:41.753935 [Byte1]: 47
3440 11:45:41.758456
3441 11:45:41.758689 Set Vref, RX VrefLevel [Byte0]: 48
3442 11:45:41.761514 [Byte1]: 48
3443 11:45:41.766048
3444 11:45:41.766288 Set Vref, RX VrefLevel [Byte0]: 49
3445 11:45:41.769454 [Byte1]: 49
3446 11:45:41.774060
3447 11:45:41.774305 Set Vref, RX VrefLevel [Byte0]: 50
3448 11:45:41.777469 [Byte1]: 50
3449 11:45:41.782123
3450 11:45:41.782356 Set Vref, RX VrefLevel [Byte0]: 51
3451 11:45:41.785450 [Byte1]: 51
3452 11:45:41.790073
3453 11:45:41.790311 Set Vref, RX VrefLevel [Byte0]: 52
3454 11:45:41.793503 [Byte1]: 52
3455 11:45:41.798039
3456 11:45:41.798269 Set Vref, RX VrefLevel [Byte0]: 53
3457 11:45:41.801163 [Byte1]: 53
3458 11:45:41.805685
3459 11:45:41.805934 Set Vref, RX VrefLevel [Byte0]: 54
3460 11:45:41.809117 [Byte1]: 54
3461 11:45:41.813852
3462 11:45:41.814092 Set Vref, RX VrefLevel [Byte0]: 55
3463 11:45:41.817128 [Byte1]: 55
3464 11:45:41.821780
3465 11:45:41.822016 Set Vref, RX VrefLevel [Byte0]: 56
3466 11:45:41.824645 [Byte1]: 56
3467 11:45:41.829415
3468 11:45:41.829658 Set Vref, RX VrefLevel [Byte0]: 57
3469 11:45:41.832346 [Byte1]: 57
3470 11:45:41.837108
3471 11:45:41.837351 Set Vref, RX VrefLevel [Byte0]: 58
3472 11:45:41.840740 [Byte1]: 58
3473 11:45:41.844820
3474 11:45:41.845063 Set Vref, RX VrefLevel [Byte0]: 59
3475 11:45:41.848242 [Byte1]: 59
3476 11:45:41.852906
3477 11:45:41.853142 Set Vref, RX VrefLevel [Byte0]: 60
3478 11:45:41.855937 [Byte1]: 60
3479 11:45:41.860998
3480 11:45:41.861243 Set Vref, RX VrefLevel [Byte0]: 61
3481 11:45:41.864592 [Byte1]: 61
3482 11:45:41.869118
3483 11:45:41.869449 Set Vref, RX VrefLevel [Byte0]: 62
3484 11:45:41.872089 [Byte1]: 62
3485 11:45:41.876485
3486 11:45:41.876761 Set Vref, RX VrefLevel [Byte0]: 63
3487 11:45:41.879884 [Byte1]: 63
3488 11:45:41.884777
3489 11:45:41.885200 Set Vref, RX VrefLevel [Byte0]: 64
3490 11:45:41.888354 [Byte1]: 64
3491 11:45:41.892339
3492 11:45:41.892805 Set Vref, RX VrefLevel [Byte0]: 65
3493 11:45:41.895694 [Byte1]: 65
3494 11:45:41.900586
3495 11:45:41.901014 Set Vref, RX VrefLevel [Byte0]: 66
3496 11:45:41.903859 [Byte1]: 66
3497 11:45:41.908245
3498 11:45:41.908716 Set Vref, RX VrefLevel [Byte0]: 67
3499 11:45:41.911617 [Byte1]: 67
3500 11:45:41.916045
3501 11:45:41.916470 Set Vref, RX VrefLevel [Byte0]: 68
3502 11:45:41.919371 [Byte1]: 68
3503 11:45:41.923902
3504 11:45:41.924327 Set Vref, RX VrefLevel [Byte0]: 69
3505 11:45:41.927334 [Byte1]: 69
3506 11:45:41.932078
3507 11:45:41.932502 Final RX Vref Byte 0 = 49 to rank0
3508 11:45:41.935858 Final RX Vref Byte 1 = 52 to rank0
3509 11:45:41.938776 Final RX Vref Byte 0 = 49 to rank1
3510 11:45:41.941960 Final RX Vref Byte 1 = 52 to rank1==
3511 11:45:41.945494 Dram Type= 6, Freq= 0, CH_1, rank 0
3512 11:45:41.951792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 11:45:41.952223 ==
3514 11:45:41.952620 DQS Delay:
3515 11:45:41.952954 DQS0 = 0, DQS1 = 0
3516 11:45:41.955259 DQM Delay:
3517 11:45:41.955803 DQM0 = 117, DQM1 = 111
3518 11:45:41.958727 DQ Delay:
3519 11:45:41.961671 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =112
3520 11:45:41.965698 DQ4 =116, DQ5 =128, DQ6 =126, DQ7 =114
3521 11:45:41.968613 DQ8 =98, DQ9 =104, DQ10 =112, DQ11 =100
3522 11:45:41.972162 DQ12 =118, DQ13 =120, DQ14 =122, DQ15 =120
3523 11:45:41.972721
3524 11:45:41.973062
3525 11:45:41.981665 [DQSOSCAuto] RK0, (LSB)MR18= 0xfff3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3526 11:45:41.982234 CH1 RK0: MR19=303, MR18=FFF3
3527 11:45:41.988585 CH1_RK0: MR19=0x303, MR18=0xFFF3, DQSOSC=410, MR23=63, INC=39, DEC=26
3528 11:45:41.989033
3529 11:45:41.992026 ----->DramcWriteLeveling(PI) begin...
3530 11:45:41.992643 ==
3531 11:45:41.994807 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 11:45:42.001852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 11:45:42.002281 ==
3534 11:45:42.005138 Write leveling (Byte 0): 24 => 24
3535 11:45:42.005712 Write leveling (Byte 1): 29 => 29
3536 11:45:42.008474 DramcWriteLeveling(PI) end<-----
3537 11:45:42.008908
3538 11:45:42.011748 ==
3539 11:45:42.012167 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 11:45:42.018343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 11:45:42.018939 ==
3542 11:45:42.021411 [Gating] SW mode calibration
3543 11:45:42.027962 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3544 11:45:42.031270 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3545 11:45:42.038320 0 15 0 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
3546 11:45:42.041235 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3547 11:45:42.044751 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3548 11:45:42.051142 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 11:45:42.054790 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 11:45:42.058295 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 11:45:42.064706 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3552 11:45:42.068032 0 15 28 | B1->B0 | 2323 2e2e | 0 1 | (1 0) (1 0)
3553 11:45:42.070912 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3554 11:45:42.077597 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3555 11:45:42.080783 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 11:45:42.084167 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 11:45:42.090719 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 11:45:42.093979 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 11:45:42.097564 1 0 24 | B1->B0 | 3333 2a2a | 1 0 | (0 0) (0 0)
3560 11:45:42.103771 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3561 11:45:42.107142 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 11:45:42.110585 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 11:45:42.117336 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 11:45:42.120414 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 11:45:42.123837 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 11:45:42.130205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 11:45:42.133612 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3568 11:45:42.137153 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3569 11:45:42.143744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 11:45:42.147357 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 11:45:42.150126 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 11:45:42.156572 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 11:45:42.160156 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 11:45:42.163460 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 11:45:42.170022 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 11:45:42.173490 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 11:45:42.177073 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 11:45:42.183629 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 11:45:42.186912 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 11:45:42.190381 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 11:45:42.196677 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 11:45:42.200119 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 11:45:42.203263 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3584 11:45:42.209599 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3585 11:45:42.213082 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3586 11:45:42.216360 Total UI for P1: 0, mck2ui 16
3587 11:45:42.219859 best dqsien dly found for B0: ( 1, 3, 26)
3588 11:45:42.223045 Total UI for P1: 0, mck2ui 16
3589 11:45:42.226630 best dqsien dly found for B1: ( 1, 3, 26)
3590 11:45:42.229728 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3591 11:45:42.233063 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3592 11:45:42.233493
3593 11:45:42.236130 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3594 11:45:42.239231 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3595 11:45:42.242747 [Gating] SW calibration Done
3596 11:45:42.243299 ==
3597 11:45:42.246200 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 11:45:42.249126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 11:45:42.252692 ==
3600 11:45:42.253396 RX Vref Scan: 0
3601 11:45:42.254044
3602 11:45:42.255797 RX Vref 0 -> 0, step: 1
3603 11:45:42.256309
3604 11:45:42.259355 RX Delay -40 -> 252, step: 8
3605 11:45:42.262293 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3606 11:45:42.265661 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3607 11:45:42.268861 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3608 11:45:42.272378 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3609 11:45:42.278702 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3610 11:45:42.282441 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3611 11:45:42.285704 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3612 11:45:42.288706 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3613 11:45:42.292061 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3614 11:45:42.298611 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3615 11:45:42.301969 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3616 11:45:42.305409 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3617 11:45:42.308768 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3618 11:45:42.311953 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3619 11:45:42.318905 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3620 11:45:42.321932 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3621 11:45:42.322897 ==
3622 11:45:42.325013 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 11:45:42.328582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 11:45:42.329015 ==
3625 11:45:42.331672 DQS Delay:
3626 11:45:42.332092 DQS0 = 0, DQS1 = 0
3627 11:45:42.332506 DQM Delay:
3628 11:45:42.335107 DQM0 = 117, DQM1 = 111
3629 11:45:42.335525 DQ Delay:
3630 11:45:42.338400 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =111
3631 11:45:42.341735 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3632 11:45:42.345217 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3633 11:45:42.351754 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3634 11:45:42.352185
3635 11:45:42.352555
3636 11:45:42.352899 ==
3637 11:45:42.355191 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 11:45:42.358139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 11:45:42.358583 ==
3640 11:45:42.359003
3641 11:45:42.359356
3642 11:45:42.361662 TX Vref Scan disable
3643 11:45:42.362084 == TX Byte 0 ==
3644 11:45:42.367940 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3645 11:45:42.371467 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3646 11:45:42.374376 == TX Byte 1 ==
3647 11:45:42.377750 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3648 11:45:42.380864 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3649 11:45:42.381169 ==
3650 11:45:42.384174 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 11:45:42.387758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 11:45:42.390760 ==
3653 11:45:42.401513 TX Vref=22, minBit 9, minWin=25, winSum=422
3654 11:45:42.404473 TX Vref=24, minBit 0, minWin=26, winSum=427
3655 11:45:42.407867 TX Vref=26, minBit 10, minWin=26, winSum=434
3656 11:45:42.411293 TX Vref=28, minBit 0, minWin=27, winSum=435
3657 11:45:42.414189 TX Vref=30, minBit 5, minWin=26, winSum=434
3658 11:45:42.420794 TX Vref=32, minBit 0, minWin=26, winSum=431
3659 11:45:42.424122 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 28
3660 11:45:42.424636
3661 11:45:42.427567 Final TX Range 1 Vref 28
3662 11:45:42.427893
3663 11:45:42.428145 ==
3664 11:45:42.430915 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 11:45:42.434309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 11:45:42.437709 ==
3667 11:45:42.438035
3668 11:45:42.438277
3669 11:45:42.438500 TX Vref Scan disable
3670 11:45:42.441116 == TX Byte 0 ==
3671 11:45:42.444255 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3672 11:45:42.451111 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3673 11:45:42.451410 == TX Byte 1 ==
3674 11:45:42.454021 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3675 11:45:42.460579 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3676 11:45:42.460919
3677 11:45:42.461159 [DATLAT]
3678 11:45:42.461379 Freq=1200, CH1 RK1
3679 11:45:42.461593
3680 11:45:42.464081 DATLAT Default: 0xd
3681 11:45:42.467240 0, 0xFFFF, sum = 0
3682 11:45:42.467543 1, 0xFFFF, sum = 0
3683 11:45:42.470691 2, 0xFFFF, sum = 0
3684 11:45:42.470990 3, 0xFFFF, sum = 0
3685 11:45:42.474182 4, 0xFFFF, sum = 0
3686 11:45:42.474483 5, 0xFFFF, sum = 0
3687 11:45:42.477266 6, 0xFFFF, sum = 0
3688 11:45:42.477566 7, 0xFFFF, sum = 0
3689 11:45:42.480176 8, 0xFFFF, sum = 0
3690 11:45:42.480478 9, 0xFFFF, sum = 0
3691 11:45:42.483734 10, 0xFFFF, sum = 0
3692 11:45:42.484173 11, 0xFFFF, sum = 0
3693 11:45:42.487188 12, 0x0, sum = 1
3694 11:45:42.487505 13, 0x0, sum = 2
3695 11:45:42.490662 14, 0x0, sum = 3
3696 11:45:42.490972 15, 0x0, sum = 4
3697 11:45:42.493584 best_step = 13
3698 11:45:42.493889
3699 11:45:42.494129 ==
3700 11:45:42.497022 Dram Type= 6, Freq= 0, CH_1, rank 1
3701 11:45:42.500399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3702 11:45:42.500764 ==
3703 11:45:42.503979 RX Vref Scan: 0
3704 11:45:42.504369
3705 11:45:42.504692 RX Vref 0 -> 0, step: 1
3706 11:45:42.504922
3707 11:45:42.506978 RX Delay -21 -> 252, step: 4
3708 11:45:42.513911 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3709 11:45:42.516628 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3710 11:45:42.520081 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3711 11:45:42.523469 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3712 11:45:42.527086 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3713 11:45:42.533356 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3714 11:45:42.536668 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3715 11:45:42.540403 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3716 11:45:42.543798 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3717 11:45:42.546625 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3718 11:45:42.553171 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3719 11:45:42.556308 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3720 11:45:42.559909 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3721 11:45:42.563402 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3722 11:45:42.569574 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3723 11:45:42.573306 iDelay=199, Bit 15, Center 120 (55 ~ 186) 132
3724 11:45:42.573698 ==
3725 11:45:42.576042 Dram Type= 6, Freq= 0, CH_1, rank 1
3726 11:45:42.579608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3727 11:45:42.579975 ==
3728 11:45:42.580331 DQS Delay:
3729 11:45:42.582962 DQS0 = 0, DQS1 = 0
3730 11:45:42.583351 DQM Delay:
3731 11:45:42.586572 DQM0 = 117, DQM1 = 111
3732 11:45:42.586953 DQ Delay:
3733 11:45:42.589303 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3734 11:45:42.592863 DQ4 =114, DQ5 =128, DQ6 =132, DQ7 =116
3735 11:45:42.596167 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3736 11:45:42.602541 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3737 11:45:42.602913
3738 11:45:42.603242
3739 11:45:42.609306 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3740 11:45:42.612784 CH1 RK1: MR19=303, MR18=F2ED
3741 11:45:42.619019 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3742 11:45:42.622577 [RxdqsGatingPostProcess] freq 1200
3743 11:45:42.626067 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3744 11:45:42.628817 best DQS0 dly(2T, 0.5T) = (0, 11)
3745 11:45:42.632126 best DQS1 dly(2T, 0.5T) = (0, 11)
3746 11:45:42.635488 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3747 11:45:42.638854 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3748 11:45:42.642202 best DQS0 dly(2T, 0.5T) = (0, 11)
3749 11:45:42.645693 best DQS1 dly(2T, 0.5T) = (0, 11)
3750 11:45:42.649297 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3751 11:45:42.652044 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3752 11:45:42.655666 Pre-setting of DQS Precalculation
3753 11:45:42.658585 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3754 11:45:42.668768 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3755 11:45:42.675256 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3756 11:45:42.675570
3757 11:45:42.675807
3758 11:45:42.678710 [Calibration Summary] 2400 Mbps
3759 11:45:42.679007 CH 0, Rank 0
3760 11:45:42.682244 SW Impedance : PASS
3761 11:45:42.682541 DUTY Scan : NO K
3762 11:45:42.684886 ZQ Calibration : PASS
3763 11:45:42.688176 Jitter Meter : NO K
3764 11:45:42.688470 CBT Training : PASS
3765 11:45:42.691837 Write leveling : PASS
3766 11:45:42.695159 RX DQS gating : PASS
3767 11:45:42.695459 RX DQ/DQS(RDDQC) : PASS
3768 11:45:42.698204 TX DQ/DQS : PASS
3769 11:45:42.701565 RX DATLAT : PASS
3770 11:45:42.701863 RX DQ/DQS(Engine): PASS
3771 11:45:42.705025 TX OE : NO K
3772 11:45:42.705326 All Pass.
3773 11:45:42.705565
3774 11:45:42.708044 CH 0, Rank 1
3775 11:45:42.708385 SW Impedance : PASS
3776 11:45:42.711127 DUTY Scan : NO K
3777 11:45:42.714682 ZQ Calibration : PASS
3778 11:45:42.714979 Jitter Meter : NO K
3779 11:45:42.718206 CBT Training : PASS
3780 11:45:42.721756 Write leveling : PASS
3781 11:45:42.722063 RX DQS gating : PASS
3782 11:45:42.724323 RX DQ/DQS(RDDQC) : PASS
3783 11:45:42.727734 TX DQ/DQS : PASS
3784 11:45:42.728163 RX DATLAT : PASS
3785 11:45:42.731172 RX DQ/DQS(Engine): PASS
3786 11:45:42.734626 TX OE : NO K
3787 11:45:42.734930 All Pass.
3788 11:45:42.735168
3789 11:45:42.735511 CH 1, Rank 0
3790 11:45:42.738210 SW Impedance : PASS
3791 11:45:42.741604 DUTY Scan : NO K
3792 11:45:42.741907 ZQ Calibration : PASS
3793 11:45:42.744309 Jitter Meter : NO K
3794 11:45:42.747973 CBT Training : PASS
3795 11:45:42.748362 Write leveling : PASS
3796 11:45:42.751510 RX DQS gating : PASS
3797 11:45:42.751901 RX DQ/DQS(RDDQC) : PASS
3798 11:45:42.754271 TX DQ/DQS : PASS
3799 11:45:42.757558 RX DATLAT : PASS
3800 11:45:42.757849 RX DQ/DQS(Engine): PASS
3801 11:45:42.761148 TX OE : NO K
3802 11:45:42.761470 All Pass.
3803 11:45:42.761715
3804 11:45:42.763899 CH 1, Rank 1
3805 11:45:42.764203 SW Impedance : PASS
3806 11:45:42.767533 DUTY Scan : NO K
3807 11:45:42.771035 ZQ Calibration : PASS
3808 11:45:42.771340 Jitter Meter : NO K
3809 11:45:42.773958 CBT Training : PASS
3810 11:45:42.777534 Write leveling : PASS
3811 11:45:42.778069 RX DQS gating : PASS
3812 11:45:42.780360 RX DQ/DQS(RDDQC) : PASS
3813 11:45:42.784012 TX DQ/DQS : PASS
3814 11:45:42.784437 RX DATLAT : PASS
3815 11:45:42.787424 RX DQ/DQS(Engine): PASS
3816 11:45:42.790330 TX OE : NO K
3817 11:45:42.790744 All Pass.
3818 11:45:42.791135
3819 11:45:42.793792 DramC Write-DBI off
3820 11:45:42.794203 PER_BANK_REFRESH: Hybrid Mode
3821 11:45:42.797385 TX_TRACKING: ON
3822 11:45:42.806630 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3823 11:45:42.810068 [FAST_K] Save calibration result to emmc
3824 11:45:42.813200 dramc_set_vcore_voltage set vcore to 650000
3825 11:45:42.813502 Read voltage for 600, 5
3826 11:45:42.816707 Vio18 = 0
3827 11:45:42.816937 Vcore = 650000
3828 11:45:42.817122 Vdram = 0
3829 11:45:42.820237 Vddq = 0
3830 11:45:42.820451 Vmddr = 0
3831 11:45:42.826680 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3832 11:45:42.829517 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3833 11:45:42.833471 MEM_TYPE=3, freq_sel=19
3834 11:45:42.836139 sv_algorithm_assistance_LP4_1600
3835 11:45:42.839762 ============ PULL DRAM RESETB DOWN ============
3836 11:45:42.843073 ========== PULL DRAM RESETB DOWN end =========
3837 11:45:42.849734 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3838 11:45:42.853028 ===================================
3839 11:45:42.853249 LPDDR4 DRAM CONFIGURATION
3840 11:45:42.856487 ===================================
3841 11:45:42.859521 EX_ROW_EN[0] = 0x0
3842 11:45:42.862884 EX_ROW_EN[1] = 0x0
3843 11:45:42.863089 LP4Y_EN = 0x0
3844 11:45:42.866199 WORK_FSP = 0x0
3845 11:45:42.866464 WL = 0x2
3846 11:45:42.869704 RL = 0x2
3847 11:45:42.869953 BL = 0x2
3848 11:45:42.872587 RPST = 0x0
3849 11:45:42.872919 RD_PRE = 0x0
3850 11:45:42.876170 WR_PRE = 0x1
3851 11:45:42.876413 WR_PST = 0x0
3852 11:45:42.879181 DBI_WR = 0x0
3853 11:45:42.879417 DBI_RD = 0x0
3854 11:45:42.882597 OTF = 0x1
3855 11:45:42.886032 ===================================
3856 11:45:42.889519 ===================================
3857 11:45:42.889863 ANA top config
3858 11:45:42.892403 ===================================
3859 11:45:42.895873 DLL_ASYNC_EN = 0
3860 11:45:42.899255 ALL_SLAVE_EN = 1
3861 11:45:42.902745 NEW_RANK_MODE = 1
3862 11:45:42.903039 DLL_IDLE_MODE = 1
3863 11:45:42.906189 LP45_APHY_COMB_EN = 1
3864 11:45:42.908951 TX_ODT_DIS = 1
3865 11:45:42.912465 NEW_8X_MODE = 1
3866 11:45:42.915943 ===================================
3867 11:45:42.919259 ===================================
3868 11:45:42.922203 data_rate = 1200
3869 11:45:42.922592 CKR = 1
3870 11:45:42.925681 DQ_P2S_RATIO = 8
3871 11:45:42.928905 ===================================
3872 11:45:42.932181 CA_P2S_RATIO = 8
3873 11:45:42.935672 DQ_CA_OPEN = 0
3874 11:45:42.938786 DQ_SEMI_OPEN = 0
3875 11:45:42.942063 CA_SEMI_OPEN = 0
3876 11:45:42.942556 CA_FULL_RATE = 0
3877 11:45:42.945577 DQ_CKDIV4_EN = 1
3878 11:45:42.949117 CA_CKDIV4_EN = 1
3879 11:45:42.952233 CA_PREDIV_EN = 0
3880 11:45:42.955628 PH8_DLY = 0
3881 11:45:42.958917 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3882 11:45:42.959431 DQ_AAMCK_DIV = 4
3883 11:45:42.962380 CA_AAMCK_DIV = 4
3884 11:45:42.965501 CA_ADMCK_DIV = 4
3885 11:45:42.968776 DQ_TRACK_CA_EN = 0
3886 11:45:42.972367 CA_PICK = 600
3887 11:45:42.975222 CA_MCKIO = 600
3888 11:45:42.978748 MCKIO_SEMI = 0
3889 11:45:42.979236 PLL_FREQ = 2288
3890 11:45:42.982326 DQ_UI_PI_RATIO = 32
3891 11:45:42.985316 CA_UI_PI_RATIO = 0
3892 11:45:42.988883 ===================================
3893 11:45:42.991746 ===================================
3894 11:45:42.995273 memory_type:LPDDR4
3895 11:45:42.998691 GP_NUM : 10
3896 11:45:42.999204 SRAM_EN : 1
3897 11:45:43.001537 MD32_EN : 0
3898 11:45:43.005078 ===================================
3899 11:45:43.005976 [ANA_INIT] >>>>>>>>>>>>>>
3900 11:45:43.008448 <<<<<< [CONFIGURE PHASE]: ANA_TX
3901 11:45:43.012377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3902 11:45:43.015109 ===================================
3903 11:45:43.018080 data_rate = 1200,PCW = 0X5800
3904 11:45:43.021313 ===================================
3905 11:45:43.024835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3906 11:45:43.031091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3907 11:45:43.037974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3908 11:45:43.041465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3909 11:45:43.044730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3910 11:45:43.047620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3911 11:45:43.051012 [ANA_INIT] flow start
3912 11:45:43.051463 [ANA_INIT] PLL >>>>>>>>
3913 11:45:43.054514 [ANA_INIT] PLL <<<<<<<<
3914 11:45:43.057914 [ANA_INIT] MIDPI >>>>>>>>
3915 11:45:43.058350 [ANA_INIT] MIDPI <<<<<<<<
3916 11:45:43.061215 [ANA_INIT] DLL >>>>>>>>
3917 11:45:43.064456 [ANA_INIT] flow end
3918 11:45:43.068034 ============ LP4 DIFF to SE enter ============
3919 11:45:43.071456 ============ LP4 DIFF to SE exit ============
3920 11:45:43.074799 [ANA_INIT] <<<<<<<<<<<<<
3921 11:45:43.077749 [Flow] Enable top DCM control >>>>>
3922 11:45:43.081088 [Flow] Enable top DCM control <<<<<
3923 11:45:43.084819 Enable DLL master slave shuffle
3924 11:45:43.087715 ==============================================================
3925 11:45:43.091335 Gating Mode config
3926 11:45:43.097786 ==============================================================
3927 11:45:43.098395 Config description:
3928 11:45:43.107522 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3929 11:45:43.114316 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3930 11:45:43.120599 SELPH_MODE 0: By rank 1: By Phase
3931 11:45:43.124067 ==============================================================
3932 11:45:43.127466 GAT_TRACK_EN = 1
3933 11:45:43.130533 RX_GATING_MODE = 2
3934 11:45:43.134083 RX_GATING_TRACK_MODE = 2
3935 11:45:43.136956 SELPH_MODE = 1
3936 11:45:43.140305 PICG_EARLY_EN = 1
3937 11:45:43.143756 VALID_LAT_VALUE = 1
3938 11:45:43.150084 ==============================================================
3939 11:45:43.153690 Enter into Gating configuration >>>>
3940 11:45:43.157057 Exit from Gating configuration <<<<
3941 11:45:43.157475 Enter into DVFS_PRE_config >>>>>
3942 11:45:43.170605 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3943 11:45:43.173342 Exit from DVFS_PRE_config <<<<<
3944 11:45:43.176324 Enter into PICG configuration >>>>
3945 11:45:43.179848 Exit from PICG configuration <<<<
3946 11:45:43.183459 [RX_INPUT] configuration >>>>>
3947 11:45:43.183931 [RX_INPUT] configuration <<<<<
3948 11:45:43.189561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3949 11:45:43.196352 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3950 11:45:43.199941 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3951 11:45:43.206607 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3952 11:45:43.212900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3953 11:45:43.219866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3954 11:45:43.222765 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3955 11:45:43.226344 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3956 11:45:43.232568 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3957 11:45:43.236016 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3958 11:45:43.239627 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3959 11:45:43.246406 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3960 11:45:43.249328 ===================================
3961 11:45:43.249752 LPDDR4 DRAM CONFIGURATION
3962 11:45:43.252785 ===================================
3963 11:45:43.256179 EX_ROW_EN[0] = 0x0
3964 11:45:43.256724 EX_ROW_EN[1] = 0x0
3965 11:45:43.259142 LP4Y_EN = 0x0
3966 11:45:43.262594 WORK_FSP = 0x0
3967 11:45:43.263147 WL = 0x2
3968 11:45:43.265802 RL = 0x2
3969 11:45:43.266223 BL = 0x2
3970 11:45:43.269156 RPST = 0x0
3971 11:45:43.269578 RD_PRE = 0x0
3972 11:45:43.272343 WR_PRE = 0x1
3973 11:45:43.272825 WR_PST = 0x0
3974 11:45:43.275958 DBI_WR = 0x0
3975 11:45:43.276389 DBI_RD = 0x0
3976 11:45:43.278794 OTF = 0x1
3977 11:45:43.282202 ===================================
3978 11:45:43.285624 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3979 11:45:43.289393 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3980 11:45:43.295823 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3981 11:45:43.298693 ===================================
3982 11:45:43.299129 LPDDR4 DRAM CONFIGURATION
3983 11:45:43.302151 ===================================
3984 11:45:43.305700 EX_ROW_EN[0] = 0x10
3985 11:45:43.308665 EX_ROW_EN[1] = 0x0
3986 11:45:43.309238 LP4Y_EN = 0x0
3987 11:45:43.312096 WORK_FSP = 0x0
3988 11:45:43.312566 WL = 0x2
3989 11:45:43.315473 RL = 0x2
3990 11:45:43.316000 BL = 0x2
3991 11:45:43.318742 RPST = 0x0
3992 11:45:43.319496 RD_PRE = 0x0
3993 11:45:43.321885 WR_PRE = 0x1
3994 11:45:43.322554 WR_PST = 0x0
3995 11:45:43.325280 DBI_WR = 0x0
3996 11:45:43.325705 DBI_RD = 0x0
3997 11:45:43.328330 OTF = 0x1
3998 11:45:43.331991 ===================================
3999 11:45:43.338223 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4000 11:45:43.341741 nWR fixed to 30
4001 11:45:43.342164 [ModeRegInit_LP4] CH0 RK0
4002 11:45:43.345258 [ModeRegInit_LP4] CH0 RK1
4003 11:45:43.348676 [ModeRegInit_LP4] CH1 RK0
4004 11:45:43.351503 [ModeRegInit_LP4] CH1 RK1
4005 11:45:43.351932 match AC timing 17
4006 11:45:43.358335 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4007 11:45:43.361865 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4008 11:45:43.364557 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4009 11:45:43.371258 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4010 11:45:43.374543 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4011 11:45:43.374771 ==
4012 11:45:43.377723 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 11:45:43.381367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 11:45:43.381594 ==
4015 11:45:43.388069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4016 11:45:43.394443 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4017 11:45:43.397525 [CA 0] Center 36 (6~66) winsize 61
4018 11:45:43.401070 [CA 1] Center 36 (6~66) winsize 61
4019 11:45:43.404541 [CA 2] Center 34 (4~65) winsize 62
4020 11:45:43.407460 [CA 3] Center 34 (4~65) winsize 62
4021 11:45:43.411008 [CA 4] Center 33 (3~64) winsize 62
4022 11:45:43.413971 [CA 5] Center 33 (3~64) winsize 62
4023 11:45:43.414372
4024 11:45:43.417361 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4025 11:45:43.417832
4026 11:45:43.420808 [CATrainingPosCal] consider 1 rank data
4027 11:45:43.423907 u2DelayCellTimex100 = 270/100 ps
4028 11:45:43.427944 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4029 11:45:43.430814 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4030 11:45:43.434389 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4031 11:45:43.437509 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4032 11:45:43.440935 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4033 11:45:43.444231 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4034 11:45:43.447131
4035 11:45:43.450551 CA PerBit enable=1, Macro0, CA PI delay=33
4036 11:45:43.450977
4037 11:45:43.454276 [CBTSetCACLKResult] CA Dly = 33
4038 11:45:43.454695 CS Dly: 4 (0~35)
4039 11:45:43.455032 ==
4040 11:45:43.457511 Dram Type= 6, Freq= 0, CH_0, rank 1
4041 11:45:43.460484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 11:45:43.460943 ==
4043 11:45:43.467356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4044 11:45:43.474182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4045 11:45:43.477469 [CA 0] Center 35 (5~66) winsize 62
4046 11:45:43.480473 [CA 1] Center 36 (6~66) winsize 61
4047 11:45:43.483639 [CA 2] Center 34 (4~64) winsize 61
4048 11:45:43.487064 [CA 3] Center 34 (4~64) winsize 61
4049 11:45:43.490460 [CA 4] Center 33 (2~64) winsize 63
4050 11:45:43.493845 [CA 5] Center 33 (2~64) winsize 63
4051 11:45:43.494267
4052 11:45:43.497287 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4053 11:45:43.497712
4054 11:45:43.500309 [CATrainingPosCal] consider 2 rank data
4055 11:45:43.503814 u2DelayCellTimex100 = 270/100 ps
4056 11:45:43.506684 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4057 11:45:43.510120 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4058 11:45:43.513720 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4059 11:45:43.519883 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4060 11:45:43.523371 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4061 11:45:43.526460 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4062 11:45:43.526887
4063 11:45:43.529707 CA PerBit enable=1, Macro0, CA PI delay=33
4064 11:45:43.530126
4065 11:45:43.533546 [CBTSetCACLKResult] CA Dly = 33
4066 11:45:43.533965 CS Dly: 5 (0~37)
4067 11:45:43.534302
4068 11:45:43.536360 ----->DramcWriteLeveling(PI) begin...
4069 11:45:43.539906 ==
4070 11:45:43.540457 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 11:45:43.546192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 11:45:43.546621 ==
4073 11:45:43.549676 Write leveling (Byte 0): 32 => 32
4074 11:45:43.553071 Write leveling (Byte 1): 30 => 30
4075 11:45:43.555914 DramcWriteLeveling(PI) end<-----
4076 11:45:43.556334
4077 11:45:43.556716 ==
4078 11:45:43.559468 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 11:45:43.563199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 11:45:43.563623 ==
4081 11:45:43.566374 [Gating] SW mode calibration
4082 11:45:43.572871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4083 11:45:43.579113 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4084 11:45:43.582271 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4085 11:45:43.586131 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4086 11:45:43.592216 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4087 11:45:43.595770 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4088 11:45:43.599233 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4089 11:45:43.605798 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4090 11:45:43.608866 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4091 11:45:43.612232 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 11:45:43.615904 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 11:45:43.622455 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 11:45:43.625355 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 11:45:43.629209 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4096 11:45:43.635396 0 10 16 | B1->B0 | 3030 3e3e | 1 0 | (0 0) (0 0)
4097 11:45:43.638990 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 11:45:43.642406 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 11:45:43.648633 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 11:45:43.651897 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 11:45:43.655396 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 11:45:43.661931 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 11:45:43.665235 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 11:45:43.668682 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4105 11:45:43.674853 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 11:45:43.678570 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 11:45:43.684453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 11:45:43.688318 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 11:45:43.691124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 11:45:43.697745 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 11:45:43.701092 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 11:45:43.704659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 11:45:43.711386 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 11:45:43.714353 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 11:45:43.717861 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 11:45:43.724374 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 11:45:43.727298 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 11:45:43.730877 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 11:45:43.737766 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4120 11:45:43.738210 Total UI for P1: 0, mck2ui 16
4121 11:45:43.744020 best dqsien dly found for B0: ( 0, 13, 10)
4122 11:45:43.747674 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4123 11:45:43.750916 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4124 11:45:43.753912 Total UI for P1: 0, mck2ui 16
4125 11:45:43.757365 best dqsien dly found for B1: ( 0, 13, 14)
4126 11:45:43.760181 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4127 11:45:43.763516 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4128 11:45:43.764096
4129 11:45:43.770646 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4130 11:45:43.773560 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4131 11:45:43.773985 [Gating] SW calibration Done
4132 11:45:43.776964 ==
4133 11:45:43.780139 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:45:43.783623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:45:43.783858 ==
4136 11:45:43.784040 RX Vref Scan: 0
4137 11:45:43.784210
4138 11:45:43.786449 RX Vref 0 -> 0, step: 1
4139 11:45:43.786729
4140 11:45:43.790131 RX Delay -230 -> 252, step: 16
4141 11:45:43.793709 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4142 11:45:43.796750 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4143 11:45:43.803477 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4144 11:45:43.806693 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4145 11:45:43.809667 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4146 11:45:43.813472 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4147 11:45:43.819955 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4148 11:45:43.823528 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4149 11:45:43.826603 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4150 11:45:43.830008 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4151 11:45:43.836258 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4152 11:45:43.839623 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4153 11:45:43.843282 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4154 11:45:43.846438 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4155 11:45:43.852972 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4156 11:45:43.856384 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4157 11:45:43.856851 ==
4158 11:45:43.859437 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 11:45:43.862727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 11:45:43.863154 ==
4161 11:45:43.866150 DQS Delay:
4162 11:45:43.866569 DQS0 = 0, DQS1 = 0
4163 11:45:43.866906 DQM Delay:
4164 11:45:43.869650 DQM0 = 42, DQM1 = 29
4165 11:45:43.870031 DQ Delay:
4166 11:45:43.873220 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4167 11:45:43.876495 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4168 11:45:43.879529 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4169 11:45:43.882702 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4170 11:45:43.883125
4171 11:45:43.883455
4172 11:45:43.883767 ==
4173 11:45:43.886046 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 11:45:43.892334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 11:45:43.892804 ==
4176 11:45:43.893145
4177 11:45:43.893458
4178 11:45:43.893758 TX Vref Scan disable
4179 11:45:43.896182 == TX Byte 0 ==
4180 11:45:43.899485 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4181 11:45:43.905879 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4182 11:45:43.906305 == TX Byte 1 ==
4183 11:45:43.909145 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4184 11:45:43.915555 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4185 11:45:43.915958 ==
4186 11:45:43.918990 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 11:45:43.922728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 11:45:43.923188 ==
4189 11:45:43.923526
4190 11:45:43.923843
4191 11:45:43.925571 TX Vref Scan disable
4192 11:45:43.929179 == TX Byte 0 ==
4193 11:45:43.932113 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4194 11:45:43.935643 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4195 11:45:43.938692 == TX Byte 1 ==
4196 11:45:43.942045 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4197 11:45:43.945576 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4198 11:45:43.946168
4199 11:45:43.948891 [DATLAT]
4200 11:45:43.949402 Freq=600, CH0 RK0
4201 11:45:43.949867
4202 11:45:43.951727 DATLAT Default: 0x9
4203 11:45:43.952237 0, 0xFFFF, sum = 0
4204 11:45:43.955155 1, 0xFFFF, sum = 0
4205 11:45:43.955659 2, 0xFFFF, sum = 0
4206 11:45:43.958819 3, 0xFFFF, sum = 0
4207 11:45:43.959326 4, 0xFFFF, sum = 0
4208 11:45:43.962287 5, 0xFFFF, sum = 0
4209 11:45:43.962837 6, 0xFFFF, sum = 0
4210 11:45:43.965625 7, 0xFFFF, sum = 0
4211 11:45:43.966147 8, 0x0, sum = 1
4212 11:45:43.968830 9, 0x0, sum = 2
4213 11:45:43.969256 10, 0x0, sum = 3
4214 11:45:43.971693 11, 0x0, sum = 4
4215 11:45:43.972117 best_step = 9
4216 11:45:43.972450
4217 11:45:43.972827 ==
4218 11:45:43.975385 Dram Type= 6, Freq= 0, CH_0, rank 0
4219 11:45:43.978227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 11:45:43.981670 ==
4221 11:45:43.982089 RX Vref Scan: 1
4222 11:45:43.982430
4223 11:45:43.984990 RX Vref 0 -> 0, step: 1
4224 11:45:43.985413
4225 11:45:43.988235 RX Delay -195 -> 252, step: 8
4226 11:45:43.988826
4227 11:45:43.991363 Set Vref, RX VrefLevel [Byte0]: 61
4228 11:45:43.994812 [Byte1]: 49
4229 11:45:43.995373
4230 11:45:43.997741 Final RX Vref Byte 0 = 61 to rank0
4231 11:45:44.001475 Final RX Vref Byte 1 = 49 to rank0
4232 11:45:44.004731 Final RX Vref Byte 0 = 61 to rank1
4233 11:45:44.007617 Final RX Vref Byte 1 = 49 to rank1==
4234 11:45:44.011146 Dram Type= 6, Freq= 0, CH_0, rank 0
4235 11:45:44.014202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 11:45:44.014756 ==
4237 11:45:44.017831 DQS Delay:
4238 11:45:44.018257 DQS0 = 0, DQS1 = 0
4239 11:45:44.018777 DQM Delay:
4240 11:45:44.021315 DQM0 = 43, DQM1 = 32
4241 11:45:44.021741 DQ Delay:
4242 11:45:44.024184 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4243 11:45:44.027913 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4244 11:45:44.030708 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4245 11:45:44.034238 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4246 11:45:44.034918
4247 11:45:44.035557
4248 11:45:44.044010 [DQSOSCAuto] RK0, (LSB)MR18= 0x6239, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4249 11:45:44.047461 CH0 RK0: MR19=808, MR18=6239
4250 11:45:44.053920 CH0_RK0: MR19=0x808, MR18=0x6239, DQSOSC=391, MR23=63, INC=171, DEC=114
4251 11:45:44.054351
4252 11:45:44.057228 ----->DramcWriteLeveling(PI) begin...
4253 11:45:44.057660 ==
4254 11:45:44.060273 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 11:45:44.063684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 11:45:44.064208 ==
4257 11:45:44.067056 Write leveling (Byte 0): 32 => 32
4258 11:45:44.070227 Write leveling (Byte 1): 31 => 31
4259 11:45:44.073517 DramcWriteLeveling(PI) end<-----
4260 11:45:44.073946
4261 11:45:44.074284 ==
4262 11:45:44.077046 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 11:45:44.080485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 11:45:44.080951 ==
4265 11:45:44.083163 [Gating] SW mode calibration
4266 11:45:44.089583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4267 11:45:44.096311 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4268 11:45:44.099526 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4269 11:45:44.102811 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4270 11:45:44.109445 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4271 11:45:44.113246 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4272 11:45:44.115905 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (1 1)
4273 11:45:44.122763 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4274 11:45:44.125898 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 11:45:44.129464 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 11:45:44.135998 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 11:45:44.139566 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 11:45:44.142458 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 11:45:44.149298 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4280 11:45:44.152275 0 10 16 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
4281 11:45:44.155716 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 11:45:44.162469 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 11:45:44.165866 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 11:45:44.168806 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 11:45:44.175717 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 11:45:44.179128 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 11:45:44.181932 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4288 11:45:44.188590 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 11:45:44.191852 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 11:45:44.195272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 11:45:44.202075 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 11:45:44.205300 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 11:45:44.208170 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 11:45:44.214705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 11:45:44.218619 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 11:45:44.222035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 11:45:44.228101 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 11:45:44.231611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 11:45:44.235240 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 11:45:44.241834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 11:45:44.244746 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 11:45:44.248229 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 11:45:44.254911 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 11:45:44.257976 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 11:45:44.261735 Total UI for P1: 0, mck2ui 16
4306 11:45:44.264972 best dqsien dly found for B0: ( 0, 13, 14)
4307 11:45:44.268024 Total UI for P1: 0, mck2ui 16
4308 11:45:44.271602 best dqsien dly found for B1: ( 0, 13, 14)
4309 11:45:44.274851 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4310 11:45:44.277840 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4311 11:45:44.278568
4312 11:45:44.281626 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4313 11:45:44.288049 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4314 11:45:44.288626 [Gating] SW calibration Done
4315 11:45:44.289178 ==
4316 11:45:44.290854 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 11:45:44.297901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 11:45:44.298457 ==
4319 11:45:44.298933 RX Vref Scan: 0
4320 11:45:44.299391
4321 11:45:44.301288 RX Vref 0 -> 0, step: 1
4322 11:45:44.301843
4323 11:45:44.304658 RX Delay -230 -> 252, step: 16
4324 11:45:44.307548 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4325 11:45:44.310805 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4326 11:45:44.314297 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4327 11:45:44.320998 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4328 11:45:44.324175 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4329 11:45:44.327556 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4330 11:45:44.330917 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4331 11:45:44.337974 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4332 11:45:44.340454 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4333 11:45:44.344278 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4334 11:45:44.347876 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4335 11:45:44.354167 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4336 11:45:44.357113 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4337 11:45:44.360746 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4338 11:45:44.363728 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4339 11:45:44.370542 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4340 11:45:44.370968 ==
4341 11:45:44.373645 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 11:45:44.376934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 11:45:44.377352 ==
4344 11:45:44.377682 DQS Delay:
4345 11:45:44.380387 DQS0 = 0, DQS1 = 0
4346 11:45:44.380970 DQM Delay:
4347 11:45:44.383923 DQM0 = 40, DQM1 = 33
4348 11:45:44.384295 DQ Delay:
4349 11:45:44.386598 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4350 11:45:44.390157 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4351 11:45:44.393719 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4352 11:45:44.397054 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4353 11:45:44.397438
4354 11:45:44.397844
4355 11:45:44.398355 ==
4356 11:45:44.400206 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 11:45:44.403748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 11:45:44.404272 ==
4359 11:45:44.404757
4360 11:45:44.407266
4361 11:45:44.407787 TX Vref Scan disable
4362 11:45:44.409981 == TX Byte 0 ==
4363 11:45:44.413392 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4364 11:45:44.416690 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4365 11:45:44.419919 == TX Byte 1 ==
4366 11:45:44.423080 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4367 11:45:44.426685 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4368 11:45:44.430014 ==
4369 11:45:44.430339 Dram Type= 6, Freq= 0, CH_0, rank 1
4370 11:45:44.436332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 11:45:44.436585 ==
4372 11:45:44.436738
4373 11:45:44.436883
4374 11:45:44.439225 TX Vref Scan disable
4375 11:45:44.439369 == TX Byte 0 ==
4376 11:45:44.446544 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4377 11:45:44.449582 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4378 11:45:44.449988 == TX Byte 1 ==
4379 11:45:44.456497 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4380 11:45:44.459556 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4381 11:45:44.460046
4382 11:45:44.460379 [DATLAT]
4383 11:45:44.463008 Freq=600, CH0 RK1
4384 11:45:44.463413
4385 11:45:44.463734 DATLAT Default: 0x9
4386 11:45:44.466172 0, 0xFFFF, sum = 0
4387 11:45:44.466687 1, 0xFFFF, sum = 0
4388 11:45:44.469883 2, 0xFFFF, sum = 0
4389 11:45:44.472685 3, 0xFFFF, sum = 0
4390 11:45:44.473199 4, 0xFFFF, sum = 0
4391 11:45:44.476044 5, 0xFFFF, sum = 0
4392 11:45:44.476477 6, 0xFFFF, sum = 0
4393 11:45:44.479447 7, 0xFFFF, sum = 0
4394 11:45:44.479993 8, 0x0, sum = 1
4395 11:45:44.482458 9, 0x0, sum = 2
4396 11:45:44.482869 10, 0x0, sum = 3
4397 11:45:44.483199 11, 0x0, sum = 4
4398 11:45:44.485963 best_step = 9
4399 11:45:44.486367
4400 11:45:44.486690 ==
4401 11:45:44.489259 Dram Type= 6, Freq= 0, CH_0, rank 1
4402 11:45:44.492762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 11:45:44.493234 ==
4404 11:45:44.495615 RX Vref Scan: 0
4405 11:45:44.496028
4406 11:45:44.496359 RX Vref 0 -> 0, step: 1
4407 11:45:44.499085
4408 11:45:44.499501 RX Delay -195 -> 252, step: 8
4409 11:45:44.506799 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4410 11:45:44.510040 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4411 11:45:44.513329 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4412 11:45:44.516263 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4413 11:45:44.522906 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4414 11:45:44.526168 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4415 11:45:44.529494 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4416 11:45:44.532993 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4417 11:45:44.539572 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4418 11:45:44.542545 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4419 11:45:44.546105 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4420 11:45:44.549106 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4421 11:45:44.555695 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4422 11:45:44.559079 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4423 11:45:44.562449 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4424 11:45:44.565778 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4425 11:45:44.566346 ==
4426 11:45:44.569026 Dram Type= 6, Freq= 0, CH_0, rank 1
4427 11:45:44.575538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 11:45:44.575951 ==
4429 11:45:44.576270 DQS Delay:
4430 11:45:44.578874 DQS0 = 0, DQS1 = 0
4431 11:45:44.579310 DQM Delay:
4432 11:45:44.582269 DQM0 = 41, DQM1 = 36
4433 11:45:44.582677 DQ Delay:
4434 11:45:44.585059 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4435 11:45:44.588416 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4436 11:45:44.591829 DQ8 =24, DQ9 =20, DQ10 =40, DQ11 =28
4437 11:45:44.595255 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4438 11:45:44.595825
4439 11:45:44.596348
4440 11:45:44.601876 [DQSOSCAuto] RK1, (LSB)MR18= 0x6014, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4441 11:45:44.604891 CH0 RK1: MR19=808, MR18=6014
4442 11:45:44.611728 CH0_RK1: MR19=0x808, MR18=0x6014, DQSOSC=391, MR23=63, INC=171, DEC=114
4443 11:45:44.615116 [RxdqsGatingPostProcess] freq 600
4444 11:45:44.621464 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4445 11:45:44.625280 Pre-setting of DQS Precalculation
4446 11:45:44.627762 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4447 11:45:44.628310 ==
4448 11:45:44.631455 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 11:45:44.634778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 11:45:44.635329 ==
4451 11:45:44.641293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4452 11:45:44.647537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4453 11:45:44.651058 [CA 0] Center 35 (5~66) winsize 62
4454 11:45:44.654860 [CA 1] Center 35 (5~66) winsize 62
4455 11:45:44.657724 [CA 2] Center 34 (4~65) winsize 62
4456 11:45:44.661202 [CA 3] Center 33 (3~64) winsize 62
4457 11:45:44.664124 [CA 4] Center 34 (4~64) winsize 61
4458 11:45:44.667679 [CA 5] Center 33 (3~64) winsize 62
4459 11:45:44.668105
4460 11:45:44.671184 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4461 11:45:44.671612
4462 11:45:44.673933 [CATrainingPosCal] consider 1 rank data
4463 11:45:44.677434 u2DelayCellTimex100 = 270/100 ps
4464 11:45:44.680731 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4465 11:45:44.684110 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4466 11:45:44.687571 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4467 11:45:44.690554 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4468 11:45:44.697343 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4469 11:45:44.700640 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4470 11:45:44.701065
4471 11:45:44.703615 CA PerBit enable=1, Macro0, CA PI delay=33
4472 11:45:44.704040
4473 11:45:44.707164 [CBTSetCACLKResult] CA Dly = 33
4474 11:45:44.707585 CS Dly: 5 (0~36)
4475 11:45:44.707924 ==
4476 11:45:44.710652 Dram Type= 6, Freq= 0, CH_1, rank 1
4477 11:45:44.716930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 11:45:44.717357 ==
4479 11:45:44.720295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4480 11:45:44.727078 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4481 11:45:44.730377 [CA 0] Center 35 (5~66) winsize 62
4482 11:45:44.733694 [CA 1] Center 36 (6~66) winsize 61
4483 11:45:44.737029 [CA 2] Center 34 (4~65) winsize 62
4484 11:45:44.740209 [CA 3] Center 34 (4~65) winsize 62
4485 11:45:44.743611 [CA 4] Center 34 (4~65) winsize 62
4486 11:45:44.746835 [CA 5] Center 34 (3~65) winsize 63
4487 11:45:44.747262
4488 11:45:44.749865 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4489 11:45:44.750308
4490 11:45:44.753310 [CATrainingPosCal] consider 2 rank data
4491 11:45:44.756799 u2DelayCellTimex100 = 270/100 ps
4492 11:45:44.759905 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4493 11:45:44.766360 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4494 11:45:44.769753 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4495 11:45:44.773392 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4496 11:45:44.776634 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4497 11:45:44.779475 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4498 11:45:44.779949
4499 11:45:44.782786 CA PerBit enable=1, Macro0, CA PI delay=33
4500 11:45:44.783209
4501 11:45:44.786330 [CBTSetCACLKResult] CA Dly = 33
4502 11:45:44.789561 CS Dly: 5 (0~36)
4503 11:45:44.789980
4504 11:45:44.793106 ----->DramcWriteLeveling(PI) begin...
4505 11:45:44.793533 ==
4506 11:45:44.796552 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 11:45:44.799373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 11:45:44.799799 ==
4509 11:45:44.802826 Write leveling (Byte 0): 29 => 29
4510 11:45:44.806156 Write leveling (Byte 1): 28 => 28
4511 11:45:44.809257 DramcWriteLeveling(PI) end<-----
4512 11:45:44.809695
4513 11:45:44.810276 ==
4514 11:45:44.812549 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 11:45:44.816455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 11:45:44.816936 ==
4517 11:45:44.819492 [Gating] SW mode calibration
4518 11:45:44.825733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4519 11:45:44.832659 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4520 11:45:44.835817 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4521 11:45:44.839129 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4522 11:45:44.845783 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4523 11:45:44.848668 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 1)
4524 11:45:44.852000 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4525 11:45:44.858828 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4526 11:45:44.862082 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4527 11:45:44.865665 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 11:45:44.871838 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 11:45:44.875419 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 11:45:44.878814 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4531 11:45:44.885696 0 10 12 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (0 0)
4532 11:45:44.888399 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 11:45:44.891605 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 11:45:44.898004 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 11:45:44.901587 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 11:45:44.905137 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 11:45:44.911826 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 11:45:44.914841 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 11:45:44.918421 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4540 11:45:44.925147 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 11:45:44.928030 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 11:45:44.931515 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 11:45:44.937845 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 11:45:44.941638 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 11:45:44.944277 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 11:45:44.951073 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 11:45:44.954497 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 11:45:44.957842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 11:45:44.964305 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 11:45:44.967725 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 11:45:44.970645 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 11:45:44.977755 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 11:45:44.980620 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 11:45:44.984149 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 11:45:44.991014 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4556 11:45:44.993909 Total UI for P1: 0, mck2ui 16
4557 11:45:44.997319 best dqsien dly found for B0: ( 0, 13, 10)
4558 11:45:45.000702 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4559 11:45:45.003725 Total UI for P1: 0, mck2ui 16
4560 11:45:45.007314 best dqsien dly found for B1: ( 0, 13, 12)
4561 11:45:45.010607 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4562 11:45:45.014042 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4563 11:45:45.014442
4564 11:45:45.017084 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4565 11:45:45.023698 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4566 11:45:45.024166 [Gating] SW calibration Done
4567 11:45:45.024715 ==
4568 11:45:45.026989 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 11:45:45.033802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 11:45:45.034233 ==
4571 11:45:45.034576 RX Vref Scan: 0
4572 11:45:45.034895
4573 11:45:45.037376 RX Vref 0 -> 0, step: 1
4574 11:45:45.037801
4575 11:45:45.040285 RX Delay -230 -> 252, step: 16
4576 11:45:45.043502 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4577 11:45:45.046912 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4578 11:45:45.050200 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4579 11:45:45.056801 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4580 11:45:45.060683 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4581 11:45:45.063395 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4582 11:45:45.066983 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4583 11:45:45.073547 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4584 11:45:45.076579 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4585 11:45:45.080065 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4586 11:45:45.082891 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4587 11:45:45.089841 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4588 11:45:45.093352 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4589 11:45:45.096177 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4590 11:45:45.099783 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4591 11:45:45.105879 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4592 11:45:45.106449 ==
4593 11:45:45.109416 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 11:45:45.113023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 11:45:45.113738 ==
4596 11:45:45.114370 DQS Delay:
4597 11:45:45.116261 DQS0 = 0, DQS1 = 0
4598 11:45:45.116991 DQM Delay:
4599 11:45:45.119133 DQM0 = 46, DQM1 = 37
4600 11:45:45.119626 DQ Delay:
4601 11:45:45.122636 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4602 11:45:45.126171 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4603 11:45:45.129061 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4604 11:45:45.132435 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4605 11:45:45.133116
4606 11:45:45.133880
4607 11:45:45.134295 ==
4608 11:45:45.135915 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 11:45:45.139171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 11:45:45.139751 ==
4611 11:45:45.142776
4612 11:45:45.143351
4613 11:45:45.143855 TX Vref Scan disable
4614 11:45:45.145563 == TX Byte 0 ==
4615 11:45:45.148955 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4616 11:45:45.152131 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4617 11:45:45.156094 == TX Byte 1 ==
4618 11:45:45.159493 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4619 11:45:45.162899 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4620 11:45:45.163318 ==
4621 11:45:45.165546 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 11:45:45.172594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 11:45:45.173057 ==
4624 11:45:45.173435
4625 11:45:45.173765
4626 11:45:45.175507 TX Vref Scan disable
4627 11:45:45.175886 == TX Byte 0 ==
4628 11:45:45.182210 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4629 11:45:45.185582 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4630 11:45:45.186092 == TX Byte 1 ==
4631 11:45:45.191971 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4632 11:45:45.195360 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4633 11:45:45.195999
4634 11:45:45.196616 [DATLAT]
4635 11:45:45.198824 Freq=600, CH1 RK0
4636 11:45:45.199404
4637 11:45:45.199890 DATLAT Default: 0x9
4638 11:45:45.201783 0, 0xFFFF, sum = 0
4639 11:45:45.202384 1, 0xFFFF, sum = 0
4640 11:45:45.205211 2, 0xFFFF, sum = 0
4641 11:45:45.205852 3, 0xFFFF, sum = 0
4642 11:45:45.208429 4, 0xFFFF, sum = 0
4643 11:45:45.211626 5, 0xFFFF, sum = 0
4644 11:45:45.212307 6, 0xFFFF, sum = 0
4645 11:45:45.214972 7, 0xFFFF, sum = 0
4646 11:45:45.215620 8, 0x0, sum = 1
4647 11:45:45.216182 9, 0x0, sum = 2
4648 11:45:45.218321 10, 0x0, sum = 3
4649 11:45:45.219071 11, 0x0, sum = 4
4650 11:45:45.221700 best_step = 9
4651 11:45:45.222204
4652 11:45:45.222665 ==
4653 11:45:45.224988 Dram Type= 6, Freq= 0, CH_1, rank 0
4654 11:45:45.228508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 11:45:45.229112 ==
4656 11:45:45.231422 RX Vref Scan: 1
4657 11:45:45.232001
4658 11:45:45.232637 RX Vref 0 -> 0, step: 1
4659 11:45:45.234981
4660 11:45:45.235609 RX Delay -179 -> 252, step: 8
4661 11:45:45.236113
4662 11:45:45.238360 Set Vref, RX VrefLevel [Byte0]: 49
4663 11:45:45.241720 [Byte1]: 52
4664 11:45:45.245634
4665 11:45:45.246056 Final RX Vref Byte 0 = 49 to rank0
4666 11:45:45.249261 Final RX Vref Byte 1 = 52 to rank0
4667 11:45:45.252063 Final RX Vref Byte 0 = 49 to rank1
4668 11:45:45.255942 Final RX Vref Byte 1 = 52 to rank1==
4669 11:45:45.259217 Dram Type= 6, Freq= 0, CH_1, rank 0
4670 11:45:45.265418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 11:45:45.266043 ==
4672 11:45:45.266580 DQS Delay:
4673 11:45:45.268772 DQS0 = 0, DQS1 = 0
4674 11:45:45.269363 DQM Delay:
4675 11:45:45.269880 DQM0 = 47, DQM1 = 36
4676 11:45:45.272138 DQ Delay:
4677 11:45:45.275114 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4678 11:45:45.278801 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4679 11:45:45.281639 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4680 11:45:45.285163 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4681 11:45:45.285582
4682 11:45:45.285913
4683 11:45:45.291535 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4684 11:45:45.295335 CH1 RK0: MR19=808, MR18=4B2F
4685 11:45:45.301852 CH1_RK0: MR19=0x808, MR18=0x4B2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4686 11:45:45.302289
4687 11:45:45.305005 ----->DramcWriteLeveling(PI) begin...
4688 11:45:45.305438 ==
4689 11:45:45.308433 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 11:45:45.311242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 11:45:45.311606 ==
4692 11:45:45.314736 Write leveling (Byte 0): 31 => 31
4693 11:45:45.318339 Write leveling (Byte 1): 29 => 29
4694 11:45:45.321076 DramcWriteLeveling(PI) end<-----
4695 11:45:45.321500
4696 11:45:45.321834 ==
4697 11:45:45.324606 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 11:45:45.331184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 11:45:45.331731 ==
4700 11:45:45.332236 [Gating] SW mode calibration
4701 11:45:45.341179 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4702 11:45:45.344580 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4703 11:45:45.350866 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4704 11:45:45.354259 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4705 11:45:45.357734 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4706 11:45:45.363969 0 9 12 | B1->B0 | 3030 3333 | 0 0 | (1 1) (0 0)
4707 11:45:45.367582 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 11:45:45.370799 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4709 11:45:45.373753 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4710 11:45:45.381001 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4711 11:45:45.384012 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 11:45:45.387393 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 11:45:45.393805 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 11:45:45.397389 0 10 12 | B1->B0 | 3737 2c2c | 0 0 | (1 1) (1 1)
4715 11:45:45.400267 0 10 16 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
4716 11:45:45.407121 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 11:45:45.410755 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4718 11:45:45.413499 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 11:45:45.420451 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 11:45:45.423780 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 11:45:45.426615 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 11:45:45.433572 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4723 11:45:45.437135 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4724 11:45:45.439734 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 11:45:45.446888 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 11:45:45.450342 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 11:45:45.453570 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 11:45:45.460594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 11:45:45.463234 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 11:45:45.466477 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 11:45:45.473116 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 11:45:45.476351 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 11:45:45.479892 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 11:45:45.486193 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 11:45:45.489876 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 11:45:45.492793 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 11:45:45.500099 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 11:45:45.502936 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4739 11:45:45.506307 Total UI for P1: 0, mck2ui 16
4740 11:45:45.509865 best dqsien dly found for B1: ( 0, 13, 10)
4741 11:45:45.512749 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4742 11:45:45.519523 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4743 11:45:45.523146 Total UI for P1: 0, mck2ui 16
4744 11:45:45.525846 best dqsien dly found for B0: ( 0, 13, 14)
4745 11:45:45.529417 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4746 11:45:45.532913 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4747 11:45:45.533338
4748 11:45:45.536242 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4749 11:45:45.539067 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4750 11:45:45.542518 [Gating] SW calibration Done
4751 11:45:45.542944 ==
4752 11:45:45.546111 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 11:45:45.549000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 11:45:45.549425 ==
4755 11:45:45.552502 RX Vref Scan: 0
4756 11:45:45.553275
4757 11:45:45.555746 RX Vref 0 -> 0, step: 1
4758 11:45:45.556258
4759 11:45:45.556715 RX Delay -230 -> 252, step: 16
4760 11:45:45.562788 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4761 11:45:45.566016 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4762 11:45:45.568778 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4763 11:45:45.572140 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4764 11:45:45.578786 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4765 11:45:45.581860 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4766 11:45:45.585969 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4767 11:45:45.588953 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4768 11:45:45.595298 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4769 11:45:45.598816 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4770 11:45:45.601857 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4771 11:45:45.605214 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4772 11:45:45.611705 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4773 11:45:45.615285 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4774 11:45:45.618710 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4775 11:45:45.621636 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4776 11:45:45.622059 ==
4777 11:45:45.625077 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 11:45:45.631643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 11:45:45.632068 ==
4780 11:45:45.632408 DQS Delay:
4781 11:45:45.635166 DQS0 = 0, DQS1 = 0
4782 11:45:45.635589 DQM Delay:
4783 11:45:45.635923 DQM0 = 44, DQM1 = 37
4784 11:45:45.638232 DQ Delay:
4785 11:45:45.641470 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4786 11:45:45.645090 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =41
4787 11:45:45.648461 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4788 11:45:45.651475 DQ12 =49, DQ13 =49, DQ14 =33, DQ15 =57
4789 11:45:45.651969
4790 11:45:45.652443
4791 11:45:45.652942 ==
4792 11:45:45.654881 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 11:45:45.658543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 11:45:45.658967 ==
4795 11:45:45.659306
4796 11:45:45.659618
4797 11:45:45.661721 TX Vref Scan disable
4798 11:45:45.664730 == TX Byte 0 ==
4799 11:45:45.668018 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4800 11:45:45.671400 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4801 11:45:45.674580 == TX Byte 1 ==
4802 11:45:45.677797 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4803 11:45:45.680836 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4804 11:45:45.681021 ==
4805 11:45:45.684281 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 11:45:45.687534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 11:45:45.690815 ==
4808 11:45:45.690946
4809 11:45:45.691049
4810 11:45:45.691145 TX Vref Scan disable
4811 11:45:45.694790 == TX Byte 0 ==
4812 11:45:45.697688 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4813 11:45:45.704698 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4814 11:45:45.704887 == TX Byte 1 ==
4815 11:45:45.707624 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4816 11:45:45.714643 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4817 11:45:45.714754
4818 11:45:45.714866 [DATLAT]
4819 11:45:45.715007 Freq=600, CH1 RK1
4820 11:45:45.715098
4821 11:45:45.717467 DATLAT Default: 0x9
4822 11:45:45.717537 0, 0xFFFF, sum = 0
4823 11:45:45.721063 1, 0xFFFF, sum = 0
4824 11:45:45.724664 2, 0xFFFF, sum = 0
4825 11:45:45.724771 3, 0xFFFF, sum = 0
4826 11:45:45.727985 4, 0xFFFF, sum = 0
4827 11:45:45.728097 5, 0xFFFF, sum = 0
4828 11:45:45.730627 6, 0xFFFF, sum = 0
4829 11:45:45.730730 7, 0xFFFF, sum = 0
4830 11:45:45.734385 8, 0x0, sum = 1
4831 11:45:45.734484 9, 0x0, sum = 2
4832 11:45:45.737236 10, 0x0, sum = 3
4833 11:45:45.737332 11, 0x0, sum = 4
4834 11:45:45.737421 best_step = 9
4835 11:45:45.737507
4836 11:45:45.740780 ==
4837 11:45:45.744353 Dram Type= 6, Freq= 0, CH_1, rank 1
4838 11:45:45.747949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4839 11:45:45.748577 ==
4840 11:45:45.748982 RX Vref Scan: 0
4841 11:45:45.749309
4842 11:45:45.751106 RX Vref 0 -> 0, step: 1
4843 11:45:45.751658
4844 11:45:45.754059 RX Delay -179 -> 252, step: 8
4845 11:45:45.761024 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4846 11:45:45.764599 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4847 11:45:45.767246 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4848 11:45:45.770841 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4849 11:45:45.774208 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4850 11:45:45.780371 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4851 11:45:45.784089 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4852 11:45:45.787012 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4853 11:45:45.790453 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4854 11:45:45.796861 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4855 11:45:45.800217 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4856 11:45:45.803258 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4857 11:45:45.806932 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4858 11:45:45.813338 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4859 11:45:45.817099 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4860 11:45:45.820007 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4861 11:45:45.820596 ==
4862 11:45:45.823628 Dram Type= 6, Freq= 0, CH_1, rank 1
4863 11:45:45.826589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4864 11:45:45.830099 ==
4865 11:45:45.830526 DQS Delay:
4866 11:45:45.830865 DQS0 = 0, DQS1 = 0
4867 11:45:45.833399 DQM Delay:
4868 11:45:45.833825 DQM0 = 45, DQM1 = 36
4869 11:45:45.836564 DQ Delay:
4870 11:45:45.836935 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4871 11:45:45.840088 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4872 11:45:45.843094 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4873 11:45:45.846243 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4874 11:45:45.846976
4875 11:45:45.849869
4876 11:45:45.856620 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4877 11:45:45.859673 CH1 RK1: MR19=808, MR18=2E23
4878 11:45:45.866398 CH1_RK1: MR19=0x808, MR18=0x2E23, DQSOSC=401, MR23=63, INC=163, DEC=108
4879 11:45:45.869684 [RxdqsGatingPostProcess] freq 600
4880 11:45:45.873134 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4881 11:45:45.875980 Pre-setting of DQS Precalculation
4882 11:45:45.882920 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4883 11:45:45.890031 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4884 11:45:45.896114 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4885 11:45:45.896652
4886 11:45:45.897155
4887 11:45:45.899379 [Calibration Summary] 1200 Mbps
4888 11:45:45.899801 CH 0, Rank 0
4889 11:45:45.902665 SW Impedance : PASS
4890 11:45:45.905740 DUTY Scan : NO K
4891 11:45:45.906163 ZQ Calibration : PASS
4892 11:45:45.909250 Jitter Meter : NO K
4893 11:45:45.912669 CBT Training : PASS
4894 11:45:45.913059 Write leveling : PASS
4895 11:45:45.916071 RX DQS gating : PASS
4896 11:45:45.919021 RX DQ/DQS(RDDQC) : PASS
4897 11:45:45.919442 TX DQ/DQS : PASS
4898 11:45:45.922605 RX DATLAT : PASS
4899 11:45:45.925506 RX DQ/DQS(Engine): PASS
4900 11:45:45.925895 TX OE : NO K
4901 11:45:45.926224 All Pass.
4902 11:45:45.929095
4903 11:45:45.929513 CH 0, Rank 1
4904 11:45:45.932420 SW Impedance : PASS
4905 11:45:45.932805 DUTY Scan : NO K
4906 11:45:45.935317 ZQ Calibration : PASS
4907 11:45:45.935739 Jitter Meter : NO K
4908 11:45:45.938658 CBT Training : PASS
4909 11:45:45.942219 Write leveling : PASS
4910 11:45:45.942643 RX DQS gating : PASS
4911 11:45:45.945126 RX DQ/DQS(RDDQC) : PASS
4912 11:45:45.948777 TX DQ/DQS : PASS
4913 11:45:45.949206 RX DATLAT : PASS
4914 11:45:45.952026 RX DQ/DQS(Engine): PASS
4915 11:45:45.955390 TX OE : NO K
4916 11:45:45.955812 All Pass.
4917 11:45:45.956148
4918 11:45:45.956462 CH 1, Rank 0
4919 11:45:45.958873 SW Impedance : PASS
4920 11:45:45.961884 DUTY Scan : NO K
4921 11:45:45.962305 ZQ Calibration : PASS
4922 11:45:45.965487 Jitter Meter : NO K
4923 11:45:45.968379 CBT Training : PASS
4924 11:45:45.968837 Write leveling : PASS
4925 11:45:45.971856 RX DQS gating : PASS
4926 11:45:45.975231 RX DQ/DQS(RDDQC) : PASS
4927 11:45:45.975653 TX DQ/DQS : PASS
4928 11:45:45.977974 RX DATLAT : PASS
4929 11:45:45.981762 RX DQ/DQS(Engine): PASS
4930 11:45:45.982185 TX OE : NO K
4931 11:45:45.984997 All Pass.
4932 11:45:45.985421
4933 11:45:45.985758 CH 1, Rank 1
4934 11:45:45.988311 SW Impedance : PASS
4935 11:45:45.988810 DUTY Scan : NO K
4936 11:45:45.991636 ZQ Calibration : PASS
4937 11:45:45.994991 Jitter Meter : NO K
4938 11:45:45.995412 CBT Training : PASS
4939 11:45:45.997996 Write leveling : PASS
4940 11:45:46.001774 RX DQS gating : PASS
4941 11:45:46.002200 RX DQ/DQS(RDDQC) : PASS
4942 11:45:46.005140 TX DQ/DQS : PASS
4943 11:45:46.005565 RX DATLAT : PASS
4944 11:45:46.007954 RX DQ/DQS(Engine): PASS
4945 11:45:46.011671 TX OE : NO K
4946 11:45:46.012093 All Pass.
4947 11:45:46.012431
4948 11:45:46.014436 DramC Write-DBI off
4949 11:45:46.018061 PER_BANK_REFRESH: Hybrid Mode
4950 11:45:46.018485 TX_TRACKING: ON
4951 11:45:46.027785 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4952 11:45:46.031189 [FAST_K] Save calibration result to emmc
4953 11:45:46.034570 dramc_set_vcore_voltage set vcore to 662500
4954 11:45:46.037847 Read voltage for 933, 3
4955 11:45:46.038233 Vio18 = 0
4956 11:45:46.038584 Vcore = 662500
4957 11:45:46.040952 Vdram = 0
4958 11:45:46.041409 Vddq = 0
4959 11:45:46.041744 Vmddr = 0
4960 11:45:46.047751 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4961 11:45:46.050802 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4962 11:45:46.054262 MEM_TYPE=3, freq_sel=17
4963 11:45:46.057658 sv_algorithm_assistance_LP4_1600
4964 11:45:46.060918 ============ PULL DRAM RESETB DOWN ============
4965 11:45:46.063942 ========== PULL DRAM RESETB DOWN end =========
4966 11:45:46.070886 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4967 11:45:46.073836 ===================================
4968 11:45:46.077221 LPDDR4 DRAM CONFIGURATION
4969 11:45:46.077657 ===================================
4970 11:45:46.080350 EX_ROW_EN[0] = 0x0
4971 11:45:46.084410 EX_ROW_EN[1] = 0x0
4972 11:45:46.084866 LP4Y_EN = 0x0
4973 11:45:46.087164 WORK_FSP = 0x0
4974 11:45:46.087586 WL = 0x3
4975 11:45:46.090519 RL = 0x3
4976 11:45:46.090942 BL = 0x2
4977 11:45:46.093920 RPST = 0x0
4978 11:45:46.094339 RD_PRE = 0x0
4979 11:45:46.097125 WR_PRE = 0x1
4980 11:45:46.097602 WR_PST = 0x0
4981 11:45:46.100278 DBI_WR = 0x0
4982 11:45:46.100750 DBI_RD = 0x0
4983 11:45:46.103527 OTF = 0x1
4984 11:45:46.106802 ===================================
4985 11:45:46.110124 ===================================
4986 11:45:46.110554 ANA top config
4987 11:45:46.113677 ===================================
4988 11:45:46.116862 DLL_ASYNC_EN = 0
4989 11:45:46.119712 ALL_SLAVE_EN = 1
4990 11:45:46.123453 NEW_RANK_MODE = 1
4991 11:45:46.126963 DLL_IDLE_MODE = 1
4992 11:45:46.127390 LP45_APHY_COMB_EN = 1
4993 11:45:46.129988 TX_ODT_DIS = 1
4994 11:45:46.133610 NEW_8X_MODE = 1
4995 11:45:46.136431 ===================================
4996 11:45:46.139720 ===================================
4997 11:45:46.143177 data_rate = 1866
4998 11:45:46.146125 CKR = 1
4999 11:45:46.146551 DQ_P2S_RATIO = 8
5000 11:45:46.149531 ===================================
5001 11:45:46.152776 CA_P2S_RATIO = 8
5002 11:45:46.156259 DQ_CA_OPEN = 0
5003 11:45:46.159246 DQ_SEMI_OPEN = 0
5004 11:45:46.162656 CA_SEMI_OPEN = 0
5005 11:45:46.165926 CA_FULL_RATE = 0
5006 11:45:46.166457 DQ_CKDIV4_EN = 1
5007 11:45:46.169449 CA_CKDIV4_EN = 1
5008 11:45:46.172288 CA_PREDIV_EN = 0
5009 11:45:46.176052 PH8_DLY = 0
5010 11:45:46.179253 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5011 11:45:46.182751 DQ_AAMCK_DIV = 4
5012 11:45:46.186028 CA_AAMCK_DIV = 4
5013 11:45:46.186582 CA_ADMCK_DIV = 4
5014 11:45:46.188926 DQ_TRACK_CA_EN = 0
5015 11:45:46.192297 CA_PICK = 933
5016 11:45:46.195717 CA_MCKIO = 933
5017 11:45:46.199017 MCKIO_SEMI = 0
5018 11:45:46.202269 PLL_FREQ = 3732
5019 11:45:46.205600 DQ_UI_PI_RATIO = 32
5020 11:45:46.206030 CA_UI_PI_RATIO = 0
5021 11:45:46.208601 ===================================
5022 11:45:46.211927 ===================================
5023 11:45:46.215233 memory_type:LPDDR4
5024 11:45:46.218803 GP_NUM : 10
5025 11:45:46.219363 SRAM_EN : 1
5026 11:45:46.222242 MD32_EN : 0
5027 11:45:46.225248 ===================================
5028 11:45:46.228907 [ANA_INIT] >>>>>>>>>>>>>>
5029 11:45:46.231835 <<<<<< [CONFIGURE PHASE]: ANA_TX
5030 11:45:46.235450 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5031 11:45:46.238224 ===================================
5032 11:45:46.238531 data_rate = 1866,PCW = 0X8f00
5033 11:45:46.241822 ===================================
5034 11:45:46.245068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5035 11:45:46.251114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5036 11:45:46.258105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5037 11:45:46.261181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5038 11:45:46.264403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5039 11:45:46.267903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5040 11:45:46.271310 [ANA_INIT] flow start
5041 11:45:46.274477 [ANA_INIT] PLL >>>>>>>>
5042 11:45:46.274572 [ANA_INIT] PLL <<<<<<<<
5043 11:45:46.278050 [ANA_INIT] MIDPI >>>>>>>>
5044 11:45:46.281178 [ANA_INIT] MIDPI <<<<<<<<
5045 11:45:46.281264 [ANA_INIT] DLL >>>>>>>>
5046 11:45:46.284741 [ANA_INIT] flow end
5047 11:45:46.287477 ============ LP4 DIFF to SE enter ============
5048 11:45:46.294445 ============ LP4 DIFF to SE exit ============
5049 11:45:46.294557 [ANA_INIT] <<<<<<<<<<<<<
5050 11:45:46.297789 [Flow] Enable top DCM control >>>>>
5051 11:45:46.300534 [Flow] Enable top DCM control <<<<<
5052 11:45:46.303892 Enable DLL master slave shuffle
5053 11:45:46.310657 ==============================================================
5054 11:45:46.310767 Gating Mode config
5055 11:45:46.317359 ==============================================================
5056 11:45:46.320661 Config description:
5057 11:45:46.327364 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5058 11:45:46.337339 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5059 11:45:46.340757 SELPH_MODE 0: By rank 1: By Phase
5060 11:45:46.347167 ==============================================================
5061 11:45:46.350436 GAT_TRACK_EN = 1
5062 11:45:46.350546 RX_GATING_MODE = 2
5063 11:45:46.353559 RX_GATING_TRACK_MODE = 2
5064 11:45:46.356980 SELPH_MODE = 1
5065 11:45:46.360782 PICG_EARLY_EN = 1
5066 11:45:46.363776 VALID_LAT_VALUE = 1
5067 11:45:46.370674 ==============================================================
5068 11:45:46.373964 Enter into Gating configuration >>>>
5069 11:45:46.376925 Exit from Gating configuration <<<<
5070 11:45:46.380562 Enter into DVFS_PRE_config >>>>>
5071 11:45:46.390213 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5072 11:45:46.393578 Exit from DVFS_PRE_config <<<<<
5073 11:45:46.396968 Enter into PICG configuration >>>>
5074 11:45:46.400461 Exit from PICG configuration <<<<
5075 11:45:46.403632 [RX_INPUT] configuration >>>>>
5076 11:45:46.406989 [RX_INPUT] configuration <<<<<
5077 11:45:46.410121 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5078 11:45:46.416703 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5079 11:45:46.423409 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5080 11:45:46.429851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5081 11:45:46.433298 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5082 11:45:46.439720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5083 11:45:46.443472 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5084 11:45:46.449849 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5085 11:45:46.453445 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5086 11:45:46.456793 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5087 11:45:46.459866 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5088 11:45:46.466395 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5089 11:45:46.469928 ===================================
5090 11:45:46.470355 LPDDR4 DRAM CONFIGURATION
5091 11:45:46.472855 ===================================
5092 11:45:46.476254 EX_ROW_EN[0] = 0x0
5093 11:45:46.479658 EX_ROW_EN[1] = 0x0
5094 11:45:46.480166 LP4Y_EN = 0x0
5095 11:45:46.483084 WORK_FSP = 0x0
5096 11:45:46.483571 WL = 0x3
5097 11:45:46.486226 RL = 0x3
5098 11:45:46.486584 BL = 0x2
5099 11:45:46.489819 RPST = 0x0
5100 11:45:46.490251 RD_PRE = 0x0
5101 11:45:46.492937 WR_PRE = 0x1
5102 11:45:46.493536 WR_PST = 0x0
5103 11:45:46.496380 DBI_WR = 0x0
5104 11:45:46.496924 DBI_RD = 0x0
5105 11:45:46.499711 OTF = 0x1
5106 11:45:46.502918 ===================================
5107 11:45:46.506253 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5108 11:45:46.509523 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5109 11:45:46.516041 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5110 11:45:46.519665 ===================================
5111 11:45:46.520089 LPDDR4 DRAM CONFIGURATION
5112 11:45:46.522639 ===================================
5113 11:45:46.525896 EX_ROW_EN[0] = 0x10
5114 11:45:46.529070 EX_ROW_EN[1] = 0x0
5115 11:45:46.529621 LP4Y_EN = 0x0
5116 11:45:46.532545 WORK_FSP = 0x0
5117 11:45:46.533041 WL = 0x3
5118 11:45:46.536154 RL = 0x3
5119 11:45:46.536655 BL = 0x2
5120 11:45:46.539399 RPST = 0x0
5121 11:45:46.539912 RD_PRE = 0x0
5122 11:45:46.542723 WR_PRE = 0x1
5123 11:45:46.543271 WR_PST = 0x0
5124 11:45:46.545639 DBI_WR = 0x0
5125 11:45:46.546127 DBI_RD = 0x0
5126 11:45:46.549298 OTF = 0x1
5127 11:45:46.552151 ===================================
5128 11:45:46.558904 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5129 11:45:46.562445 nWR fixed to 30
5130 11:45:46.565676 [ModeRegInit_LP4] CH0 RK0
5131 11:45:46.566108 [ModeRegInit_LP4] CH0 RK1
5132 11:45:46.568502 [ModeRegInit_LP4] CH1 RK0
5133 11:45:46.572218 [ModeRegInit_LP4] CH1 RK1
5134 11:45:46.572683 match AC timing 9
5135 11:45:46.579241 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5136 11:45:46.581984 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5137 11:45:46.585325 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5138 11:45:46.591836 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5139 11:45:46.595498 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5140 11:45:46.595922 ==
5141 11:45:46.598603 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 11:45:46.602084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 11:45:46.602512 ==
5144 11:45:46.608321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5145 11:45:46.615074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5146 11:45:46.618712 [CA 0] Center 37 (7~68) winsize 62
5147 11:45:46.621433 [CA 1] Center 37 (7~68) winsize 62
5148 11:45:46.624813 [CA 2] Center 34 (4~65) winsize 62
5149 11:45:46.628315 [CA 3] Center 35 (5~65) winsize 61
5150 11:45:46.631241 [CA 4] Center 33 (3~64) winsize 62
5151 11:45:46.634509 [CA 5] Center 33 (3~63) winsize 61
5152 11:45:46.635084
5153 11:45:46.638099 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5154 11:45:46.638807
5155 11:45:46.641667 [CATrainingPosCal] consider 1 rank data
5156 11:45:46.644411 u2DelayCellTimex100 = 270/100 ps
5157 11:45:46.647923 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5158 11:45:46.651356 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5159 11:45:46.654488 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5160 11:45:46.657897 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5161 11:45:46.664237 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5162 11:45:46.667557 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5163 11:45:46.668095
5164 11:45:46.671390 CA PerBit enable=1, Macro0, CA PI delay=33
5165 11:45:46.671818
5166 11:45:46.674392 [CBTSetCACLKResult] CA Dly = 33
5167 11:45:46.674850 CS Dly: 7 (0~38)
5168 11:45:46.675207 ==
5169 11:45:46.678054 Dram Type= 6, Freq= 0, CH_0, rank 1
5170 11:45:46.684086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 11:45:46.684541 ==
5172 11:45:46.687433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5173 11:45:46.694602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5174 11:45:46.697453 [CA 0] Center 37 (7~68) winsize 62
5175 11:45:46.700774 [CA 1] Center 37 (7~68) winsize 62
5176 11:45:46.703755 [CA 2] Center 34 (4~65) winsize 62
5177 11:45:46.707106 [CA 3] Center 34 (4~65) winsize 62
5178 11:45:46.710508 [CA 4] Center 33 (3~64) winsize 62
5179 11:45:46.713529 [CA 5] Center 33 (3~63) winsize 61
5180 11:45:46.713964
5181 11:45:46.717448 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5182 11:45:46.717875
5183 11:45:46.720202 [CATrainingPosCal] consider 2 rank data
5184 11:45:46.723472 u2DelayCellTimex100 = 270/100 ps
5185 11:45:46.726735 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5186 11:45:46.733662 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5187 11:45:46.736953 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5188 11:45:46.740169 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5189 11:45:46.743367 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5190 11:45:46.747034 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5191 11:45:46.747460
5192 11:45:46.749979 CA PerBit enable=1, Macro0, CA PI delay=33
5193 11:45:46.750407
5194 11:45:46.753262 [CBTSetCACLKResult] CA Dly = 33
5195 11:45:46.756756 CS Dly: 7 (0~39)
5196 11:45:46.757173
5197 11:45:46.760490 ----->DramcWriteLeveling(PI) begin...
5198 11:45:46.760963 ==
5199 11:45:46.763151 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 11:45:46.766532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 11:45:46.766960 ==
5202 11:45:46.770014 Write leveling (Byte 0): 35 => 35
5203 11:45:46.772967 Write leveling (Byte 1): 27 => 27
5204 11:45:46.776112 DramcWriteLeveling(PI) end<-----
5205 11:45:46.776641
5206 11:45:46.776980 ==
5207 11:45:46.779679 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 11:45:46.783305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 11:45:46.783671 ==
5210 11:45:46.786577 [Gating] SW mode calibration
5211 11:45:46.792775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5212 11:45:46.799264 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5213 11:45:46.803008 0 14 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
5214 11:45:46.809352 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5215 11:45:46.812477 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5216 11:45:46.816006 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5217 11:45:46.819635 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 11:45:46.825879 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 11:45:46.829169 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 11:45:46.832579 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5221 11:45:46.838578 0 15 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)
5222 11:45:46.841928 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5223 11:45:46.845407 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5224 11:45:46.851813 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 11:45:46.855461 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 11:45:46.862010 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 11:45:46.864855 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 11:45:46.868375 0 15 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5229 11:45:46.871421 1 0 0 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
5230 11:45:46.878284 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5231 11:45:46.881711 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 11:45:46.885403 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 11:45:46.891739 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 11:45:46.894471 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 11:45:46.898002 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 11:45:46.904673 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5237 11:45:46.908196 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5238 11:45:46.911464 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 11:45:46.917759 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 11:45:46.921296 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 11:45:46.924913 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 11:45:46.931111 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 11:45:46.934375 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 11:45:46.937375 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 11:45:46.943792 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 11:45:46.947397 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 11:45:46.950918 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 11:45:46.957434 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 11:45:46.960956 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 11:45:46.963945 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 11:45:46.970451 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 11:45:46.974158 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5253 11:45:46.977006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5254 11:45:46.983826 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5255 11:45:46.986917 Total UI for P1: 0, mck2ui 16
5256 11:45:46.990384 best dqsien dly found for B0: ( 1, 2, 30)
5257 11:45:46.993396 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5258 11:45:46.996903 Total UI for P1: 0, mck2ui 16
5259 11:45:47.000398 best dqsien dly found for B1: ( 1, 3, 2)
5260 11:45:47.003362 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5261 11:45:47.006941 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5262 11:45:47.007055
5263 11:45:47.009962 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5264 11:45:47.013757 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5265 11:45:47.017171 [Gating] SW calibration Done
5266 11:45:47.017282 ==
5267 11:45:47.019900 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 11:45:47.026997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 11:45:47.027580 ==
5270 11:45:47.028118 RX Vref Scan: 0
5271 11:45:47.028710
5272 11:45:47.030488 RX Vref 0 -> 0, step: 1
5273 11:45:47.030995
5274 11:45:47.033510 RX Delay -80 -> 252, step: 8
5275 11:45:47.037212 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5276 11:45:47.040620 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5277 11:45:47.043738 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5278 11:45:47.047005 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5279 11:45:47.050339 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5280 11:45:47.056713 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5281 11:45:47.060345 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5282 11:45:47.063223 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5283 11:45:47.066889 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5284 11:45:47.069797 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5285 11:45:47.076324 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5286 11:45:47.079843 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5287 11:45:47.083164 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5288 11:45:47.086537 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5289 11:45:47.093179 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5290 11:45:47.096000 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5291 11:45:47.096424 ==
5292 11:45:47.099590 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 11:45:47.103094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 11:45:47.103718 ==
5295 11:45:47.104270 DQS Delay:
5296 11:45:47.106032 DQS0 = 0, DQS1 = 0
5297 11:45:47.106654 DQM Delay:
5298 11:45:47.109621 DQM0 = 97, DQM1 = 85
5299 11:45:47.110041 DQ Delay:
5300 11:45:47.113166 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5301 11:45:47.116265 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5302 11:45:47.119544 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5303 11:45:47.122965 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5304 11:45:47.123523
5305 11:45:47.124101
5306 11:45:47.124684 ==
5307 11:45:47.125943 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 11:45:47.132334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 11:45:47.132903 ==
5310 11:45:47.133381
5311 11:45:47.133782
5312 11:45:47.134088 TX Vref Scan disable
5313 11:45:47.135680 == TX Byte 0 ==
5314 11:45:47.139050 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5315 11:45:47.145592 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5316 11:45:47.146033 == TX Byte 1 ==
5317 11:45:47.149135 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5318 11:45:47.155424 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5319 11:45:47.155724 ==
5320 11:45:47.158859 Dram Type= 6, Freq= 0, CH_0, rank 0
5321 11:45:47.162272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5322 11:45:47.162567 ==
5323 11:45:47.162822
5324 11:45:47.163066
5325 11:45:47.165310 TX Vref Scan disable
5326 11:45:47.168233 == TX Byte 0 ==
5327 11:45:47.171973 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5328 11:45:47.174936 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5329 11:45:47.178651 == TX Byte 1 ==
5330 11:45:47.181723 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5331 11:45:47.185233 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5332 11:45:47.185401
5333 11:45:47.185540 [DATLAT]
5334 11:45:47.188001 Freq=933, CH0 RK0
5335 11:45:47.188216
5336 11:45:47.191382 DATLAT Default: 0xd
5337 11:45:47.191569 0, 0xFFFF, sum = 0
5338 11:45:47.195012 1, 0xFFFF, sum = 0
5339 11:45:47.195198 2, 0xFFFF, sum = 0
5340 11:45:47.198155 3, 0xFFFF, sum = 0
5341 11:45:47.198342 4, 0xFFFF, sum = 0
5342 11:45:47.201559 5, 0xFFFF, sum = 0
5343 11:45:47.201728 6, 0xFFFF, sum = 0
5344 11:45:47.204507 7, 0xFFFF, sum = 0
5345 11:45:47.204769 8, 0xFFFF, sum = 0
5346 11:45:47.207946 9, 0xFFFF, sum = 0
5347 11:45:47.208173 10, 0x0, sum = 1
5348 11:45:47.211363 11, 0x0, sum = 2
5349 11:45:47.211549 12, 0x0, sum = 3
5350 11:45:47.214499 13, 0x0, sum = 4
5351 11:45:47.214685 best_step = 11
5352 11:45:47.214845
5353 11:45:47.215058 ==
5354 11:45:47.218305 Dram Type= 6, Freq= 0, CH_0, rank 0
5355 11:45:47.221819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 11:45:47.224665 ==
5357 11:45:47.225092 RX Vref Scan: 1
5358 11:45:47.225522
5359 11:45:47.228198 RX Vref 0 -> 0, step: 1
5360 11:45:47.228646
5361 11:45:47.231678 RX Delay -61 -> 252, step: 4
5362 11:45:47.232031
5363 11:45:47.234592 Set Vref, RX VrefLevel [Byte0]: 61
5364 11:45:47.237980 [Byte1]: 49
5365 11:45:47.238534
5366 11:45:47.241355 Final RX Vref Byte 0 = 61 to rank0
5367 11:45:47.244575 Final RX Vref Byte 1 = 49 to rank0
5368 11:45:47.248140 Final RX Vref Byte 0 = 61 to rank1
5369 11:45:47.251045 Final RX Vref Byte 1 = 49 to rank1==
5370 11:45:47.254088 Dram Type= 6, Freq= 0, CH_0, rank 0
5371 11:45:47.257580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 11:45:47.257964 ==
5373 11:45:47.260787 DQS Delay:
5374 11:45:47.261090 DQS0 = 0, DQS1 = 0
5375 11:45:47.261381 DQM Delay:
5376 11:45:47.264266 DQM0 = 97, DQM1 = 85
5377 11:45:47.264487 DQ Delay:
5378 11:45:47.267756 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5379 11:45:47.271340 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5380 11:45:47.274313 DQ8 =78, DQ9 =74, DQ10 =84, DQ11 =80
5381 11:45:47.277694 DQ12 =90, DQ13 =86, DQ14 =98, DQ15 =92
5382 11:45:47.277935
5383 11:45:47.278134
5384 11:45:47.287278 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c12, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5385 11:45:47.290773 CH0 RK0: MR19=505, MR18=2C12
5386 11:45:47.293925 CH0_RK0: MR19=0x505, MR18=0x2C12, DQSOSC=408, MR23=63, INC=65, DEC=43
5387 11:45:47.294105
5388 11:45:47.297470 ----->DramcWriteLeveling(PI) begin...
5389 11:45:47.300850 ==
5390 11:45:47.303901 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 11:45:47.307395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 11:45:47.307637 ==
5393 11:45:47.310650 Write leveling (Byte 0): 32 => 32
5394 11:45:47.313837 Write leveling (Byte 1): 31 => 31
5395 11:45:47.317453 DramcWriteLeveling(PI) end<-----
5396 11:45:47.317978
5397 11:45:47.318443 ==
5398 11:45:47.320851 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 11:45:47.323904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 11:45:47.324543 ==
5401 11:45:47.327404 [Gating] SW mode calibration
5402 11:45:47.334122 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5403 11:45:47.340469 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5404 11:45:47.343834 0 14 0 | B1->B0 | 2a2a 3333 | 1 1 | (1 1) (0 0)
5405 11:45:47.347370 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5406 11:45:47.354000 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 11:45:47.357669 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 11:45:47.360251 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 11:45:47.367007 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 11:45:47.369864 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 11:45:47.373260 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
5412 11:45:47.379669 0 15 0 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (0 0)
5413 11:45:47.383251 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 11:45:47.386160 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 11:45:47.392758 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 11:45:47.396399 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 11:45:47.399917 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 11:45:47.406569 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 11:45:47.410062 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5420 11:45:47.413012 1 0 0 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5421 11:45:47.419612 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 11:45:47.423051 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 11:45:47.426099 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 11:45:47.432629 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 11:45:47.436170 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 11:45:47.439785 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 11:45:47.442673 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5428 11:45:47.449141 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5429 11:45:47.452722 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 11:45:47.456031 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 11:45:47.462383 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 11:45:47.465921 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 11:45:47.469486 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 11:45:47.475630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 11:45:47.479198 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 11:45:47.482369 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 11:45:47.488833 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 11:45:47.492364 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 11:45:47.495918 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 11:45:47.502511 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 11:45:47.506119 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 11:45:47.508861 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 11:45:47.515387 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5444 11:45:47.519004 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5445 11:45:47.522362 Total UI for P1: 0, mck2ui 16
5446 11:45:47.525467 best dqsien dly found for B0: ( 1, 2, 28)
5447 11:45:47.529077 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5448 11:45:47.532016 Total UI for P1: 0, mck2ui 16
5449 11:45:47.535046 best dqsien dly found for B1: ( 1, 2, 30)
5450 11:45:47.538727 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5451 11:45:47.545244 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5452 11:45:47.545683
5453 11:45:47.548932 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5454 11:45:47.551702 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5455 11:45:47.554971 [Gating] SW calibration Done
5456 11:45:47.555428 ==
5457 11:45:47.558523 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 11:45:47.561847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 11:45:47.562300 ==
5460 11:45:47.565172 RX Vref Scan: 0
5461 11:45:47.565624
5462 11:45:47.565965 RX Vref 0 -> 0, step: 1
5463 11:45:47.566279
5464 11:45:47.568025 RX Delay -80 -> 252, step: 8
5465 11:45:47.571625 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5466 11:45:47.574975 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5467 11:45:47.581917 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5468 11:45:47.584877 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5469 11:45:47.588486 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5470 11:45:47.591683 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5471 11:45:47.595303 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5472 11:45:47.598177 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5473 11:45:47.604622 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5474 11:45:47.608094 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5475 11:45:47.611692 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5476 11:45:47.614787 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5477 11:45:47.618123 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5478 11:45:47.624855 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5479 11:45:47.627858 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5480 11:45:47.631477 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5481 11:45:47.631900 ==
5482 11:45:47.634481 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 11:45:47.638112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 11:45:47.638788 ==
5485 11:45:47.641201 DQS Delay:
5486 11:45:47.641634 DQS0 = 0, DQS1 = 0
5487 11:45:47.644782 DQM Delay:
5488 11:45:47.645551 DQM0 = 97, DQM1 = 89
5489 11:45:47.646235 DQ Delay:
5490 11:45:47.647533 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5491 11:45:47.651224 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5492 11:45:47.654188 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5493 11:45:47.657586 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5494 11:45:47.658009
5495 11:45:47.658344
5496 11:45:47.660610 ==
5497 11:45:47.664100 Dram Type= 6, Freq= 0, CH_0, rank 1
5498 11:45:47.667709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 11:45:47.668138 ==
5500 11:45:47.668477
5501 11:45:47.668921
5502 11:45:47.671164 TX Vref Scan disable
5503 11:45:47.671591 == TX Byte 0 ==
5504 11:45:47.677519 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5505 11:45:47.680728 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5506 11:45:47.681168 == TX Byte 1 ==
5507 11:45:47.687135 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5508 11:45:47.690292 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5509 11:45:47.690737 ==
5510 11:45:47.693676 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 11:45:47.697368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 11:45:47.697790 ==
5513 11:45:47.698121
5514 11:45:47.698424
5515 11:45:47.700483 TX Vref Scan disable
5516 11:45:47.703510 == TX Byte 0 ==
5517 11:45:47.707122 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5518 11:45:47.710151 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5519 11:45:47.713442 == TX Byte 1 ==
5520 11:45:47.717016 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5521 11:45:47.720037 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5522 11:45:47.720465
5523 11:45:47.723709 [DATLAT]
5524 11:45:47.724128 Freq=933, CH0 RK1
5525 11:45:47.724465
5526 11:45:47.726634 DATLAT Default: 0xb
5527 11:45:47.727054 0, 0xFFFF, sum = 0
5528 11:45:47.730061 1, 0xFFFF, sum = 0
5529 11:45:47.730488 2, 0xFFFF, sum = 0
5530 11:45:47.733761 3, 0xFFFF, sum = 0
5531 11:45:47.734191 4, 0xFFFF, sum = 0
5532 11:45:47.736684 5, 0xFFFF, sum = 0
5533 11:45:47.737154 6, 0xFFFF, sum = 0
5534 11:45:47.740142 7, 0xFFFF, sum = 0
5535 11:45:47.740625 8, 0xFFFF, sum = 0
5536 11:45:47.743047 9, 0xFFFF, sum = 0
5537 11:45:47.743477 10, 0x0, sum = 1
5538 11:45:47.746696 11, 0x0, sum = 2
5539 11:45:47.747199 12, 0x0, sum = 3
5540 11:45:47.750246 13, 0x0, sum = 4
5541 11:45:47.750676 best_step = 11
5542 11:45:47.751015
5543 11:45:47.751328 ==
5544 11:45:47.753398 Dram Type= 6, Freq= 0, CH_0, rank 1
5545 11:45:47.759909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 11:45:47.760335 ==
5547 11:45:47.760721 RX Vref Scan: 0
5548 11:45:47.761045
5549 11:45:47.763540 RX Vref 0 -> 0, step: 1
5550 11:45:47.764083
5551 11:45:47.766323 RX Delay -61 -> 252, step: 4
5552 11:45:47.769603 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5553 11:45:47.773406 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5554 11:45:47.779768 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5555 11:45:47.782828 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5556 11:45:47.786167 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5557 11:45:47.789593 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5558 11:45:47.792951 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5559 11:45:47.799713 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5560 11:45:47.802681 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5561 11:45:47.806302 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5562 11:45:47.809272 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5563 11:45:47.812944 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5564 11:45:47.819358 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5565 11:45:47.822357 iDelay=203, Bit 13, Center 94 (3 ~ 186) 184
5566 11:45:47.826140 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5567 11:45:47.829495 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5568 11:45:47.829947 ==
5569 11:45:47.832313 Dram Type= 6, Freq= 0, CH_0, rank 1
5570 11:45:47.835360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 11:45:47.839138 ==
5572 11:45:47.839564 DQS Delay:
5573 11:45:47.839898 DQS0 = 0, DQS1 = 0
5574 11:45:47.842153 DQM Delay:
5575 11:45:47.842575 DQM0 = 95, DQM1 = 86
5576 11:45:47.845767 DQ Delay:
5577 11:45:47.846186 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =94
5578 11:45:47.848776 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5579 11:45:47.852218 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5580 11:45:47.858755 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =94
5581 11:45:47.859177
5582 11:45:47.859514
5583 11:45:47.865315 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5584 11:45:47.868691 CH0 RK1: MR19=504, MR18=29FA
5585 11:45:47.875506 CH0_RK1: MR19=0x504, MR18=0x29FA, DQSOSC=408, MR23=63, INC=65, DEC=43
5586 11:45:47.878790 [RxdqsGatingPostProcess] freq 933
5587 11:45:47.881638 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5588 11:45:47.884999 best DQS0 dly(2T, 0.5T) = (0, 10)
5589 11:45:47.888624 best DQS1 dly(2T, 0.5T) = (0, 11)
5590 11:45:47.892069 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5591 11:45:47.894788 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5592 11:45:47.898510 best DQS0 dly(2T, 0.5T) = (0, 10)
5593 11:45:47.901450 best DQS1 dly(2T, 0.5T) = (0, 10)
5594 11:45:47.905007 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5595 11:45:47.908000 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5596 11:45:47.911688 Pre-setting of DQS Precalculation
5597 11:45:47.914610 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5598 11:45:47.915060 ==
5599 11:45:47.917938 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 11:45:47.924778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 11:45:47.925206 ==
5602 11:45:47.927659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5603 11:45:47.934427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5604 11:45:47.937873 [CA 0] Center 37 (7~67) winsize 61
5605 11:45:47.941547 [CA 1] Center 37 (7~68) winsize 62
5606 11:45:47.944374 [CA 2] Center 34 (4~65) winsize 62
5607 11:45:47.948060 [CA 3] Center 33 (3~64) winsize 62
5608 11:45:47.951382 [CA 4] Center 34 (4~64) winsize 61
5609 11:45:47.954429 [CA 5] Center 34 (4~64) winsize 61
5610 11:45:47.954853
5611 11:45:47.957582 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5612 11:45:47.958061
5613 11:45:47.961086 [CATrainingPosCal] consider 1 rank data
5614 11:45:47.964582 u2DelayCellTimex100 = 270/100 ps
5615 11:45:47.967711 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5616 11:45:47.974652 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5617 11:45:47.977502 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5618 11:45:47.980721 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 11:45:47.984028 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5620 11:45:47.987200 CA5 delay=34 (4~64),Diff = 1 PI (6 cell)
5621 11:45:47.987937
5622 11:45:47.990775 CA PerBit enable=1, Macro0, CA PI delay=33
5623 11:45:47.991153
5624 11:45:47.994188 [CBTSetCACLKResult] CA Dly = 33
5625 11:45:47.997602 CS Dly: 6 (0~37)
5626 11:45:47.998152 ==
5627 11:45:48.000349 Dram Type= 6, Freq= 0, CH_1, rank 1
5628 11:45:48.003852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 11:45:48.004513 ==
5630 11:45:48.010406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5631 11:45:48.014273 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5632 11:45:48.017757 [CA 0] Center 36 (6~67) winsize 62
5633 11:45:48.021200 [CA 1] Center 37 (7~67) winsize 61
5634 11:45:48.024627 [CA 2] Center 34 (4~65) winsize 62
5635 11:45:48.028010 [CA 3] Center 34 (3~65) winsize 63
5636 11:45:48.031054 [CA 4] Center 34 (4~65) winsize 62
5637 11:45:48.034954 [CA 5] Center 33 (3~64) winsize 62
5638 11:45:48.035497
5639 11:45:48.037682 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5640 11:45:48.038105
5641 11:45:48.041095 [CATrainingPosCal] consider 2 rank data
5642 11:45:48.044473 u2DelayCellTimex100 = 270/100 ps
5643 11:45:48.047553 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5644 11:45:48.054032 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5645 11:45:48.057585 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5646 11:45:48.060580 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5647 11:45:48.064598 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5648 11:45:48.067614 CA5 delay=34 (4~64),Diff = 1 PI (6 cell)
5649 11:45:48.068128
5650 11:45:48.070733 CA PerBit enable=1, Macro0, CA PI delay=33
5651 11:45:48.071161
5652 11:45:48.074092 [CBTSetCACLKResult] CA Dly = 33
5653 11:45:48.077514 CS Dly: 7 (0~39)
5654 11:45:48.077841
5655 11:45:48.080189 ----->DramcWriteLeveling(PI) begin...
5656 11:45:48.080506 ==
5657 11:45:48.083948 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 11:45:48.087324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 11:45:48.087732 ==
5660 11:45:48.090396 Write leveling (Byte 0): 25 => 25
5661 11:45:48.094076 Write leveling (Byte 1): 27 => 27
5662 11:45:48.096874 DramcWriteLeveling(PI) end<-----
5663 11:45:48.097219
5664 11:45:48.097528 ==
5665 11:45:48.100251 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 11:45:48.103665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 11:45:48.103981 ==
5668 11:45:48.106993 [Gating] SW mode calibration
5669 11:45:48.113084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5670 11:45:48.119572 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5671 11:45:48.123200 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5672 11:45:48.126708 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 11:45:48.133385 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 11:45:48.136573 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 11:45:48.142987 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 11:45:48.146558 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5677 11:45:48.149755 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5678 11:45:48.156383 0 14 28 | B1->B0 | 2f2f 2d2d | 0 0 | (1 1) (1 1)
5679 11:45:48.159370 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5680 11:45:48.162908 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 11:45:48.169081 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 11:45:48.173063 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 11:45:48.175915 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 11:45:48.182720 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 11:45:48.185770 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5686 11:45:48.189025 0 15 28 | B1->B0 | 3636 3f3e | 0 1 | (0 0) (0 0)
5687 11:45:48.195799 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 11:45:48.198789 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 11:45:48.202370 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 11:45:48.209101 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 11:45:48.211887 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 11:45:48.215582 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 11:45:48.222189 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5694 11:45:48.225661 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5695 11:45:48.228649 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 11:45:48.235471 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 11:45:48.238869 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 11:45:48.241799 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 11:45:48.248731 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 11:45:48.251702 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 11:45:48.255343 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 11:45:48.261943 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 11:45:48.264779 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 11:45:48.268357 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 11:45:48.274794 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 11:45:48.278538 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 11:45:48.281382 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 11:45:48.287881 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 11:45:48.291305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 11:45:48.294822 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5711 11:45:48.297772 Total UI for P1: 0, mck2ui 16
5712 11:45:48.301125 best dqsien dly found for B0: ( 1, 2, 26)
5713 11:45:48.304553 Total UI for P1: 0, mck2ui 16
5714 11:45:48.307370 best dqsien dly found for B1: ( 1, 2, 26)
5715 11:45:48.310781 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5716 11:45:48.314215 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5717 11:45:48.314638
5718 11:45:48.317244 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5719 11:45:48.324426 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5720 11:45:48.324922 [Gating] SW calibration Done
5721 11:45:48.327432 ==
5722 11:45:48.327860 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 11:45:48.334135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 11:45:48.334557 ==
5725 11:45:48.334894 RX Vref Scan: 0
5726 11:45:48.335205
5727 11:45:48.337669 RX Vref 0 -> 0, step: 1
5728 11:45:48.338091
5729 11:45:48.340562 RX Delay -80 -> 252, step: 8
5730 11:45:48.343963 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5731 11:45:48.347123 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5732 11:45:48.350508 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5733 11:45:48.354112 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5734 11:45:48.360484 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5735 11:45:48.363635 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5736 11:45:48.367070 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5737 11:45:48.370671 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5738 11:45:48.374218 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5739 11:45:48.380622 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5740 11:45:48.384637 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5741 11:45:48.387251 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5742 11:45:48.390823 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5743 11:45:48.393720 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5744 11:45:48.397155 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5745 11:45:48.403754 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5746 11:45:48.404178 ==
5747 11:45:48.407115 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 11:45:48.410104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 11:45:48.410531 ==
5750 11:45:48.410872 DQS Delay:
5751 11:45:48.413520 DQS0 = 0, DQS1 = 0
5752 11:45:48.414019 DQM Delay:
5753 11:45:48.417039 DQM0 = 101, DQM1 = 92
5754 11:45:48.417462 DQ Delay:
5755 11:45:48.420371 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5756 11:45:48.423442 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5757 11:45:48.427161 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =79
5758 11:45:48.430095 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5759 11:45:48.430515
5760 11:45:48.430849
5761 11:45:48.431155 ==
5762 11:45:48.433855 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 11:45:48.439924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 11:45:48.440479 ==
5765 11:45:48.440999
5766 11:45:48.441457
5767 11:45:48.441909 TX Vref Scan disable
5768 11:45:48.443478 == TX Byte 0 ==
5769 11:45:48.447001 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5770 11:45:48.453281 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5771 11:45:48.453706 == TX Byte 1 ==
5772 11:45:48.456487 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5773 11:45:48.463131 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5774 11:45:48.463565 ==
5775 11:45:48.466677 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 11:45:48.470105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 11:45:48.470577 ==
5778 11:45:48.470964
5779 11:45:48.471279
5780 11:45:48.473084 TX Vref Scan disable
5781 11:45:48.473642 == TX Byte 0 ==
5782 11:45:48.479835 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5783 11:45:48.482866 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5784 11:45:48.483286 == TX Byte 1 ==
5785 11:45:48.489821 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5786 11:45:48.492940 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5787 11:45:48.493361
5788 11:45:48.493756 [DATLAT]
5789 11:45:48.877521 Freq=933, CH1 RK0
5790 11:45:48.878414
5791 11:45:48.879442 DATLAT Default: 0xd
5792 11:45:48.880620 0, 0xFFFF, sum = 0
5793 11:45:48.881644 1, 0xFFFF, sum = 0
5794 11:45:48.882306 2, 0xFFFF, sum = 0
5795 11:45:48.882938 3, 0xFFFF, sum = 0
5796 11:45:48.883570 4, 0xFFFF, sum = 0
5797 11:45:48.884175 5, 0xFFFF, sum = 0
5798 11:45:48.884821 6, 0xFFFF, sum = 0
5799 11:45:48.885424 7, 0xFFFF, sum = 0
5800 11:45:48.886039 8, 0xFFFF, sum = 0
5801 11:45:48.886648 9, 0xFFFF, sum = 0
5802 11:45:48.887308 10, 0x0, sum = 1
5803 11:45:48.887809 11, 0x0, sum = 2
5804 11:45:48.888445 12, 0x0, sum = 3
5805 11:45:48.889125 13, 0x0, sum = 4
5806 11:45:48.889741 best_step = 11
5807 11:45:48.890110
5808 11:45:48.890484 ==
5809 11:45:48.890906 Dram Type= 6, Freq= 0, CH_1, rank 0
5810 11:45:48.891240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 11:45:48.891567 ==
5812 11:45:48.892047 RX Vref Scan: 1
5813 11:45:48.892388
5814 11:45:48.892822 RX Vref 0 -> 0, step: 1
5815 11:45:48.893240
5816 11:45:48.893701 RX Delay -61 -> 252, step: 4
5817 11:45:48.894017
5818 11:45:48.894430 Set Vref, RX VrefLevel [Byte0]: 49
5819 11:45:48.894771 [Byte1]: 52
5820 11:45:48.895134
5821 11:45:48.895454 Final RX Vref Byte 0 = 49 to rank0
5822 11:45:48.895805 Final RX Vref Byte 1 = 52 to rank0
5823 11:45:48.896193 Final RX Vref Byte 0 = 49 to rank1
5824 11:45:48.896839 Final RX Vref Byte 1 = 52 to rank1==
5825 11:45:48.897160 Dram Type= 6, Freq= 0, CH_1, rank 0
5826 11:45:48.897604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 11:45:48.897971 ==
5828 11:45:48.898328 DQS Delay:
5829 11:45:48.898622 DQS0 = 0, DQS1 = 0
5830 11:45:48.898912 DQM Delay:
5831 11:45:48.899233 DQM0 = 101, DQM1 = 95
5832 11:45:48.899525 DQ Delay:
5833 11:45:48.899810 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5834 11:45:48.900138 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5835 11:45:48.900634 DQ8 =80, DQ9 =86, DQ10 =96, DQ11 =86
5836 11:45:48.901041 DQ12 =102, DQ13 =98, DQ14 =106, DQ15 =106
5837 11:45:48.901443
5838 11:45:48.901773
5839 11:45:48.902111 [DQSOSCAuto] RK0, (LSB)MR18= 0x1807, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5840 11:45:48.902407 CH1 RK0: MR19=505, MR18=1807
5841 11:45:48.902800 CH1_RK0: MR19=0x505, MR18=0x1807, DQSOSC=414, MR23=63, INC=63, DEC=42
5842 11:45:48.903098
5843 11:45:48.903454 ----->DramcWriteLeveling(PI) begin...
5844 11:45:48.903906 ==
5845 11:45:48.904207 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 11:45:48.904564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 11:45:48.904937 ==
5848 11:45:48.905228 Write leveling (Byte 0): 25 => 25
5849 11:45:48.905562 Write leveling (Byte 1): 30 => 30
5850 11:45:48.905960 DramcWriteLeveling(PI) end<-----
5851 11:45:48.906265
5852 11:45:48.906474 ==
5853 11:45:48.906694 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 11:45:48.906903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 11:45:48.907190 ==
5856 11:45:48.907590 [Gating] SW mode calibration
5857 11:45:48.907916 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5858 11:45:48.908325 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5859 11:45:48.908694 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5860 11:45:48.909075 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 11:45:48.909354 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 11:45:48.909574 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 11:45:48.909827 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 11:45:48.910201 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 11:45:48.910441 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
5866 11:45:48.910655 0 14 28 | B1->B0 | 2626 3030 | 0 0 | (0 0) (0 0)
5867 11:45:48.910941 0 15 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5868 11:45:48.911180 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5869 11:45:48.911533 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 11:45:48.911780 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 11:45:48.911969 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 11:45:48.912140 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 11:45:48.912410 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5874 11:45:48.912747 0 15 28 | B1->B0 | 3d3d 2b2b | 0 0 | (1 1) (0 0)
5875 11:45:48.912943 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 11:45:48.913151 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 11:45:48.913338 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 11:45:48.913512 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 11:45:48.913676 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 11:45:48.913877 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 11:45:48.914042 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5882 11:45:48.914199 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5883 11:45:48.914352 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 11:45:48.914505 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 11:45:48.914658 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 11:45:48.914824 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 11:45:48.914979 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 11:45:48.915139 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 11:45:48.915295 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 11:45:48.915450 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 11:45:48.915603 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 11:45:48.915758 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 11:45:48.915913 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 11:45:48.916035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 11:45:48.916158 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 11:45:48.916279 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 11:45:48.916400 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 11:45:48.916537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5899 11:45:48.916665 Total UI for P1: 0, mck2ui 16
5900 11:45:48.916791 best dqsien dly found for B0: ( 1, 2, 26)
5901 11:45:48.916914 Total UI for P1: 0, mck2ui 16
5902 11:45:48.917038 best dqsien dly found for B1: ( 1, 2, 26)
5903 11:45:48.917161 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5904 11:45:48.917283 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5905 11:45:48.917415
5906 11:45:48.917544 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5907 11:45:48.917668 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5908 11:45:48.918016 [Gating] SW calibration Done
5909 11:45:48.918156 ==
5910 11:45:48.918310 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 11:45:48.918444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 11:45:48.918594 ==
5913 11:45:48.918743 RX Vref Scan: 0
5914 11:45:48.918894
5915 11:45:48.919029 RX Vref 0 -> 0, step: 1
5916 11:45:48.919153
5917 11:45:48.919274 RX Delay -80 -> 252, step: 8
5918 11:45:48.919398 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5919 11:45:48.919556 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5920 11:45:48.919682 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5921 11:45:48.919814 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5922 11:45:48.919938 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5923 11:45:48.920060 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5924 11:45:48.920183 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5925 11:45:48.920305 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5926 11:45:48.920427 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5927 11:45:48.920564 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5928 11:45:48.920688 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5929 11:45:48.920810 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5930 11:45:48.920948 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5931 11:45:48.923728 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5932 11:45:48.926616 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5933 11:45:48.929973 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5934 11:45:48.930109 ==
5935 11:45:48.933542 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 11:45:48.936735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 11:45:48.936873 ==
5938 11:45:48.940146 DQS Delay:
5939 11:45:48.940315 DQS0 = 0, DQS1 = 0
5940 11:45:48.942951 DQM Delay:
5941 11:45:48.943083 DQM0 = 100, DQM1 = 92
5942 11:45:48.943223 DQ Delay:
5943 11:45:48.946448 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5944 11:45:48.950085 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5945 11:45:48.953032 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =83
5946 11:45:48.956637 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5947 11:45:48.956770
5948 11:45:48.959517
5949 11:45:48.959648 ==
5950 11:45:48.963270 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 11:45:48.966226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 11:45:48.966375 ==
5953 11:45:48.966492
5954 11:45:48.966600
5955 11:45:48.969648 TX Vref Scan disable
5956 11:45:48.969796 == TX Byte 0 ==
5957 11:45:48.976008 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5958 11:45:48.979587 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5959 11:45:48.979664 == TX Byte 1 ==
5960 11:45:48.986387 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5961 11:45:48.989581 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5962 11:45:48.989676 ==
5963 11:45:48.992841 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 11:45:48.996411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 11:45:48.996524 ==
5966 11:45:48.996615
5967 11:45:48.996692
5968 11:45:48.999533 TX Vref Scan disable
5969 11:45:49.002501 == TX Byte 0 ==
5970 11:45:49.006409 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5971 11:45:49.009899 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5972 11:45:49.013016 == TX Byte 1 ==
5973 11:45:49.016063 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5974 11:45:49.019611 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5975 11:45:49.020144
5976 11:45:49.022926 [DATLAT]
5977 11:45:49.023432 Freq=933, CH1 RK1
5978 11:45:49.023812
5979 11:45:49.026293 DATLAT Default: 0xb
5980 11:45:49.026722 0, 0xFFFF, sum = 0
5981 11:45:49.029288 1, 0xFFFF, sum = 0
5982 11:45:49.029722 2, 0xFFFF, sum = 0
5983 11:45:49.032810 3, 0xFFFF, sum = 0
5984 11:45:49.033251 4, 0xFFFF, sum = 0
5985 11:45:49.036249 5, 0xFFFF, sum = 0
5986 11:45:49.036785 6, 0xFFFF, sum = 0
5987 11:45:49.039590 7, 0xFFFF, sum = 0
5988 11:45:49.040206 8, 0xFFFF, sum = 0
5989 11:45:49.042622 9, 0xFFFF, sum = 0
5990 11:45:49.043056 10, 0x0, sum = 1
5991 11:45:49.045976 11, 0x0, sum = 2
5992 11:45:49.046518 12, 0x0, sum = 3
5993 11:45:49.049468 13, 0x0, sum = 4
5994 11:45:49.049914 best_step = 11
5995 11:45:49.050470
5996 11:45:49.050901 ==
5997 11:45:49.052510 Dram Type= 6, Freq= 0, CH_1, rank 1
5998 11:45:49.059058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5999 11:45:49.059479 ==
6000 11:45:49.059949 RX Vref Scan: 0
6001 11:45:49.060402
6002 11:45:49.062145 RX Vref 0 -> 0, step: 1
6003 11:45:49.062511
6004 11:45:49.065742 RX Delay -61 -> 252, step: 4
6005 11:45:49.068748 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6006 11:45:49.075693 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
6007 11:45:49.078706 iDelay=207, Bit 2, Center 92 (7 ~ 178) 172
6008 11:45:49.082242 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6009 11:45:49.085870 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6010 11:45:49.088741 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6011 11:45:49.095720 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6012 11:45:49.098676 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6013 11:45:49.102375 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6014 11:45:49.105282 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6015 11:45:49.108763 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6016 11:45:49.111913 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6017 11:45:49.119041 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6018 11:45:49.121931 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6019 11:45:49.125326 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
6020 11:45:49.128141 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6021 11:45:49.128706 ==
6022 11:45:49.131752 Dram Type= 6, Freq= 0, CH_1, rank 1
6023 11:45:49.138381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6024 11:45:49.139060 ==
6025 11:45:49.139594 DQS Delay:
6026 11:45:49.142055 DQS0 = 0, DQS1 = 0
6027 11:45:49.142637 DQM Delay:
6028 11:45:49.143115 DQM0 = 101, DQM1 = 93
6029 11:45:49.144807 DQ Delay:
6030 11:45:49.148177 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
6031 11:45:49.151788 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
6032 11:45:49.154739 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
6033 11:45:49.158169 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =102
6034 11:45:49.158781
6035 11:45:49.159165
6036 11:45:49.165056 [DQSOSCAuto] RK1, (LSB)MR18= 0x4fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 420 ps
6037 11:45:49.167955 CH1 RK1: MR19=504, MR18=4FD
6038 11:45:49.174742 CH1_RK1: MR19=0x504, MR18=0x4FD, DQSOSC=420, MR23=63, INC=61, DEC=40
6039 11:45:49.178114 [RxdqsGatingPostProcess] freq 933
6040 11:45:49.184568 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6041 11:45:49.187814 best DQS0 dly(2T, 0.5T) = (0, 10)
6042 11:45:49.188137 best DQS1 dly(2T, 0.5T) = (0, 10)
6043 11:45:49.190806 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6044 11:45:49.194306 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6045 11:45:49.197528 best DQS0 dly(2T, 0.5T) = (0, 10)
6046 11:45:49.200465 best DQS1 dly(2T, 0.5T) = (0, 10)
6047 11:45:49.204172 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6048 11:45:49.207712 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6049 11:45:49.210615 Pre-setting of DQS Precalculation
6050 11:45:49.217212 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6051 11:45:49.224121 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6052 11:45:49.231005 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6053 11:45:49.231341
6054 11:45:49.231621
6055 11:45:49.233759 [Calibration Summary] 1866 Mbps
6056 11:45:49.234156 CH 0, Rank 0
6057 11:45:49.237130 SW Impedance : PASS
6058 11:45:49.240674 DUTY Scan : NO K
6059 11:45:49.240919 ZQ Calibration : PASS
6060 11:45:49.243492 Jitter Meter : NO K
6061 11:45:49.247039 CBT Training : PASS
6062 11:45:49.247373 Write leveling : PASS
6063 11:45:49.250614 RX DQS gating : PASS
6064 11:45:49.253511 RX DQ/DQS(RDDQC) : PASS
6065 11:45:49.253756 TX DQ/DQS : PASS
6066 11:45:49.256986 RX DATLAT : PASS
6067 11:45:49.260617 RX DQ/DQS(Engine): PASS
6068 11:45:49.260862 TX OE : NO K
6069 11:45:49.261057 All Pass.
6070 11:45:49.263545
6071 11:45:49.263787 CH 0, Rank 1
6072 11:45:49.267003 SW Impedance : PASS
6073 11:45:49.267246 DUTY Scan : NO K
6074 11:45:49.270049 ZQ Calibration : PASS
6075 11:45:49.273738 Jitter Meter : NO K
6076 11:45:49.274064 CBT Training : PASS
6077 11:45:49.276503 Write leveling : PASS
6078 11:45:49.276846 RX DQS gating : PASS
6079 11:45:49.280080 RX DQ/DQS(RDDQC) : PASS
6080 11:45:49.283518 TX DQ/DQS : PASS
6081 11:45:49.283824 RX DATLAT : PASS
6082 11:45:49.287042 RX DQ/DQS(Engine): PASS
6083 11:45:49.289988 TX OE : NO K
6084 11:45:49.290294 All Pass.
6085 11:45:49.290537
6086 11:45:49.290765 CH 1, Rank 0
6087 11:45:49.293092 SW Impedance : PASS
6088 11:45:49.296538 DUTY Scan : NO K
6089 11:45:49.296860 ZQ Calibration : PASS
6090 11:45:49.300253 Jitter Meter : NO K
6091 11:45:49.302986 CBT Training : PASS
6092 11:45:49.303322 Write leveling : PASS
6093 11:45:49.306671 RX DQS gating : PASS
6094 11:45:49.309665 RX DQ/DQS(RDDQC) : PASS
6095 11:45:49.309972 TX DQ/DQS : PASS
6096 11:45:49.313365 RX DATLAT : PASS
6097 11:45:49.316279 RX DQ/DQS(Engine): PASS
6098 11:45:49.316603 TX OE : NO K
6099 11:45:49.319979 All Pass.
6100 11:45:49.320293
6101 11:45:49.320665 CH 1, Rank 1
6102 11:45:49.323000 SW Impedance : PASS
6103 11:45:49.323303 DUTY Scan : NO K
6104 11:45:49.325894 ZQ Calibration : PASS
6105 11:45:49.329373 Jitter Meter : NO K
6106 11:45:49.329608 CBT Training : PASS
6107 11:45:49.332406 Write leveling : PASS
6108 11:45:49.335937 RX DQS gating : PASS
6109 11:45:49.336094 RX DQ/DQS(RDDQC) : PASS
6110 11:45:49.339424 TX DQ/DQS : PASS
6111 11:45:49.342311 RX DATLAT : PASS
6112 11:45:49.342444 RX DQ/DQS(Engine): PASS
6113 11:45:49.345837 TX OE : NO K
6114 11:45:49.345973 All Pass.
6115 11:45:49.346066
6116 11:45:49.349110 DramC Write-DBI off
6117 11:45:49.352186 PER_BANK_REFRESH: Hybrid Mode
6118 11:45:49.352343 TX_TRACKING: ON
6119 11:45:49.362133 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6120 11:45:49.365753 [FAST_K] Save calibration result to emmc
6121 11:45:49.369139 dramc_set_vcore_voltage set vcore to 650000
6122 11:45:49.372060 Read voltage for 400, 6
6123 11:45:49.372175 Vio18 = 0
6124 11:45:49.372263 Vcore = 650000
6125 11:45:49.375667 Vdram = 0
6126 11:45:49.375766 Vddq = 0
6127 11:45:49.375866 Vmddr = 0
6128 11:45:49.381818 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6129 11:45:49.385195 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6130 11:45:49.388807 MEM_TYPE=3, freq_sel=20
6131 11:45:49.392002 sv_algorithm_assistance_LP4_800
6132 11:45:49.395584 ============ PULL DRAM RESETB DOWN ============
6133 11:45:49.398753 ========== PULL DRAM RESETB DOWN end =========
6134 11:45:49.404975 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6135 11:45:49.408309 ===================================
6136 11:45:49.412255 LPDDR4 DRAM CONFIGURATION
6137 11:45:49.415208 ===================================
6138 11:45:49.415640 EX_ROW_EN[0] = 0x0
6139 11:45:49.418575 EX_ROW_EN[1] = 0x0
6140 11:45:49.418995 LP4Y_EN = 0x0
6141 11:45:49.421682 WORK_FSP = 0x0
6142 11:45:49.422182 WL = 0x2
6143 11:45:49.425331 RL = 0x2
6144 11:45:49.425772 BL = 0x2
6145 11:45:49.428405 RPST = 0x0
6146 11:45:49.428882 RD_PRE = 0x0
6147 11:45:49.431653 WR_PRE = 0x1
6148 11:45:49.431951 WR_PST = 0x0
6149 11:45:49.434784 DBI_WR = 0x0
6150 11:45:49.435086 DBI_RD = 0x0
6151 11:45:49.438207 OTF = 0x1
6152 11:45:49.441751 ===================================
6153 11:45:49.445107 ===================================
6154 11:45:49.445419 ANA top config
6155 11:45:49.448041 ===================================
6156 11:45:49.451477 DLL_ASYNC_EN = 0
6157 11:45:49.454780 ALL_SLAVE_EN = 1
6158 11:45:49.457669 NEW_RANK_MODE = 1
6159 11:45:49.457786 DLL_IDLE_MODE = 1
6160 11:45:49.461127 LP45_APHY_COMB_EN = 1
6161 11:45:49.464697 TX_ODT_DIS = 1
6162 11:45:49.467949 NEW_8X_MODE = 1
6163 11:45:49.471148 ===================================
6164 11:45:49.474631 ===================================
6165 11:45:49.477625 data_rate = 800
6166 11:45:49.481217 CKR = 1
6167 11:45:49.481311 DQ_P2S_RATIO = 4
6168 11:45:49.484653 ===================================
6169 11:45:49.487565 CA_P2S_RATIO = 4
6170 11:45:49.491360 DQ_CA_OPEN = 0
6171 11:45:49.494495 DQ_SEMI_OPEN = 1
6172 11:45:49.498176 CA_SEMI_OPEN = 1
6173 11:45:49.501432 CA_FULL_RATE = 0
6174 11:45:49.501980 DQ_CKDIV4_EN = 0
6175 11:45:49.504351 CA_CKDIV4_EN = 1
6176 11:45:49.507960 CA_PREDIV_EN = 0
6177 11:45:49.510844 PH8_DLY = 0
6178 11:45:49.514246 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6179 11:45:49.517708 DQ_AAMCK_DIV = 0
6180 11:45:49.518265 CA_AAMCK_DIV = 0
6181 11:45:49.520707 CA_ADMCK_DIV = 4
6182 11:45:49.524265 DQ_TRACK_CA_EN = 0
6183 11:45:49.527427 CA_PICK = 800
6184 11:45:49.531027 CA_MCKIO = 400
6185 11:45:49.533849 MCKIO_SEMI = 400
6186 11:45:49.537544 PLL_FREQ = 3016
6187 11:45:49.541070 DQ_UI_PI_RATIO = 32
6188 11:45:49.541656 CA_UI_PI_RATIO = 32
6189 11:45:49.543759 ===================================
6190 11:45:49.547237 ===================================
6191 11:45:49.550645 memory_type:LPDDR4
6192 11:45:49.554032 GP_NUM : 10
6193 11:45:49.554458 SRAM_EN : 1
6194 11:45:49.557034 MD32_EN : 0
6195 11:45:49.560439 ===================================
6196 11:45:49.563907 [ANA_INIT] >>>>>>>>>>>>>>
6197 11:45:49.566763 <<<<<< [CONFIGURE PHASE]: ANA_TX
6198 11:45:49.570362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6199 11:45:49.573872 ===================================
6200 11:45:49.574604 data_rate = 800,PCW = 0X7400
6201 11:45:49.576960 ===================================
6202 11:45:49.580366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6203 11:45:49.587037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6204 11:45:49.600465 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6205 11:45:49.603500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6206 11:45:49.606319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6207 11:45:49.610162 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6208 11:45:49.612986 [ANA_INIT] flow start
6209 11:45:49.613388 [ANA_INIT] PLL >>>>>>>>
6210 11:45:49.616259 [ANA_INIT] PLL <<<<<<<<
6211 11:45:49.619820 [ANA_INIT] MIDPI >>>>>>>>
6212 11:45:49.622771 [ANA_INIT] MIDPI <<<<<<<<
6213 11:45:49.623005 [ANA_INIT] DLL >>>>>>>>
6214 11:45:49.626290 [ANA_INIT] flow end
6215 11:45:49.629400 ============ LP4 DIFF to SE enter ============
6216 11:45:49.632891 ============ LP4 DIFF to SE exit ============
6217 11:45:49.636307 [ANA_INIT] <<<<<<<<<<<<<
6218 11:45:49.639214 [Flow] Enable top DCM control >>>>>
6219 11:45:49.642822 [Flow] Enable top DCM control <<<<<
6220 11:45:49.645846 Enable DLL master slave shuffle
6221 11:45:49.652776 ==============================================================
6222 11:45:49.652960 Gating Mode config
6223 11:45:49.658988 ==============================================================
6224 11:45:49.659174 Config description:
6225 11:45:49.669386 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6226 11:45:49.675712 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6227 11:45:49.682318 SELPH_MODE 0: By rank 1: By Phase
6228 11:45:49.685367 ==============================================================
6229 11:45:49.689120 GAT_TRACK_EN = 0
6230 11:45:49.692005 RX_GATING_MODE = 2
6231 11:45:49.695584 RX_GATING_TRACK_MODE = 2
6232 11:45:49.699219 SELPH_MODE = 1
6233 11:45:49.701969 PICG_EARLY_EN = 1
6234 11:45:49.705591 VALID_LAT_VALUE = 1
6235 11:45:49.712256 ==============================================================
6236 11:45:49.715132 Enter into Gating configuration >>>>
6237 11:45:49.718626 Exit from Gating configuration <<<<
6238 11:45:49.718771 Enter into DVFS_PRE_config >>>>>
6239 11:45:49.731779 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6240 11:45:49.735308 Exit from DVFS_PRE_config <<<<<
6241 11:45:49.738252 Enter into PICG configuration >>>>
6242 11:45:49.741732 Exit from PICG configuration <<<<
6243 11:45:49.745430 [RX_INPUT] configuration >>>>>
6244 11:45:49.745583 [RX_INPUT] configuration <<<<<
6245 11:45:49.752016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6246 11:45:49.758535 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6247 11:45:49.761376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6248 11:45:49.768391 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6249 11:45:49.774683 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6250 11:45:49.781853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6251 11:45:49.784752 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6252 11:45:49.788181 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6253 11:45:49.794598 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6254 11:45:49.798055 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6255 11:45:49.800991 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6256 11:45:49.807815 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6257 11:45:49.810793 ===================================
6258 11:45:49.811184 LPDDR4 DRAM CONFIGURATION
6259 11:45:49.813913 ===================================
6260 11:45:49.817485 EX_ROW_EN[0] = 0x0
6261 11:45:49.820998 EX_ROW_EN[1] = 0x0
6262 11:45:49.821387 LP4Y_EN = 0x0
6263 11:45:49.823986 WORK_FSP = 0x0
6264 11:45:49.824369 WL = 0x2
6265 11:45:49.827500 RL = 0x2
6266 11:45:49.827817 BL = 0x2
6267 11:45:49.830923 RPST = 0x0
6268 11:45:49.831221 RD_PRE = 0x0
6269 11:45:49.833839 WR_PRE = 0x1
6270 11:45:49.834140 WR_PST = 0x0
6271 11:45:49.837506 DBI_WR = 0x0
6272 11:45:49.837730 DBI_RD = 0x0
6273 11:45:49.840546 OTF = 0x1
6274 11:45:49.843809 ===================================
6275 11:45:49.846849 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6276 11:45:49.850303 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6277 11:45:49.857008 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6278 11:45:49.860237 ===================================
6279 11:45:49.860443 LPDDR4 DRAM CONFIGURATION
6280 11:45:49.863753 ===================================
6281 11:45:49.867099 EX_ROW_EN[0] = 0x10
6282 11:45:49.870037 EX_ROW_EN[1] = 0x0
6283 11:45:49.870265 LP4Y_EN = 0x0
6284 11:45:49.873430 WORK_FSP = 0x0
6285 11:45:49.873659 WL = 0x2
6286 11:45:49.877012 RL = 0x2
6287 11:45:49.877242 BL = 0x2
6288 11:45:49.879987 RPST = 0x0
6289 11:45:49.880213 RD_PRE = 0x0
6290 11:45:49.883389 WR_PRE = 0x1
6291 11:45:49.883572 WR_PST = 0x0
6292 11:45:49.886970 DBI_WR = 0x0
6293 11:45:49.887121 DBI_RD = 0x0
6294 11:45:49.889998 OTF = 0x1
6295 11:45:49.893419 ===================================
6296 11:45:49.900168 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6297 11:45:49.903210 nWR fixed to 30
6298 11:45:49.906608 [ModeRegInit_LP4] CH0 RK0
6299 11:45:49.906770 [ModeRegInit_LP4] CH0 RK1
6300 11:45:49.910200 [ModeRegInit_LP4] CH1 RK0
6301 11:45:49.912869 [ModeRegInit_LP4] CH1 RK1
6302 11:45:49.913024 match AC timing 19
6303 11:45:49.919575 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6304 11:45:49.923274 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6305 11:45:49.926682 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6306 11:45:49.933052 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6307 11:45:49.936153 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6308 11:45:49.936437 ==
6309 11:45:49.939678 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 11:45:49.942649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 11:45:49.942858 ==
6312 11:45:49.949298 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6313 11:45:49.956167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6314 11:45:49.959677 [CA 0] Center 36 (8~64) winsize 57
6315 11:45:49.962640 [CA 1] Center 36 (8~64) winsize 57
6316 11:45:49.966123 [CA 2] Center 36 (8~64) winsize 57
6317 11:45:49.969479 [CA 3] Center 36 (8~64) winsize 57
6318 11:45:49.969757 [CA 4] Center 36 (8~64) winsize 57
6319 11:45:49.972348 [CA 5] Center 36 (8~64) winsize 57
6320 11:45:49.972604
6321 11:45:49.978879 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6322 11:45:49.979054
6323 11:45:49.982772 [CATrainingPosCal] consider 1 rank data
6324 11:45:49.985733 u2DelayCellTimex100 = 270/100 ps
6325 11:45:49.989291 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 11:45:49.992266 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 11:45:49.995428 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 11:45:49.998936 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 11:45:50.002562 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 11:45:50.005519 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:45:50.005609
6332 11:45:50.008957 CA PerBit enable=1, Macro0, CA PI delay=36
6333 11:45:50.009037
6334 11:45:50.011943 [CBTSetCACLKResult] CA Dly = 36
6335 11:45:50.015493 CS Dly: 1 (0~32)
6336 11:45:50.015609 ==
6337 11:45:50.018546 Dram Type= 6, Freq= 0, CH_0, rank 1
6338 11:45:50.022100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 11:45:50.022188 ==
6340 11:45:50.028611 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6341 11:45:50.034827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6342 11:45:50.038301 [CA 0] Center 36 (8~64) winsize 57
6343 11:45:50.041968 [CA 1] Center 36 (8~64) winsize 57
6344 11:45:50.042048 [CA 2] Center 36 (8~64) winsize 57
6345 11:45:50.045007 [CA 3] Center 36 (8~64) winsize 57
6346 11:45:50.048627 [CA 4] Center 36 (8~64) winsize 57
6347 11:45:50.052200 [CA 5] Center 36 (8~64) winsize 57
6348 11:45:50.052283
6349 11:45:50.054980 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6350 11:45:50.055064
6351 11:45:50.061554 [CATrainingPosCal] consider 2 rank data
6352 11:45:50.061654 u2DelayCellTimex100 = 270/100 ps
6353 11:45:50.068034 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 11:45:50.071538 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 11:45:50.074901 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 11:45:50.078202 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 11:45:50.081194 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 11:45:50.084582 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 11:45:50.084688
6360 11:45:50.088068 CA PerBit enable=1, Macro0, CA PI delay=36
6361 11:45:50.088170
6362 11:45:50.091514 [CBTSetCACLKResult] CA Dly = 36
6363 11:45:50.094616 CS Dly: 1 (0~32)
6364 11:45:50.094703
6365 11:45:50.098076 ----->DramcWriteLeveling(PI) begin...
6366 11:45:50.098184 ==
6367 11:45:50.101208 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 11:45:50.104354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 11:45:50.104455 ==
6370 11:45:50.108033 Write leveling (Byte 0): 40 => 8
6371 11:45:50.111609 Write leveling (Byte 1): 32 => 0
6372 11:45:50.114428 DramcWriteLeveling(PI) end<-----
6373 11:45:50.114526
6374 11:45:50.114598 ==
6375 11:45:50.117928 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 11:45:50.120819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 11:45:50.120926 ==
6378 11:45:50.124427 [Gating] SW mode calibration
6379 11:45:50.131037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6380 11:45:50.137564 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6381 11:45:50.141079 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6382 11:45:50.144184 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6383 11:45:50.151168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 11:45:50.154154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6385 11:45:50.157802 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6386 11:45:50.164175 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6387 11:45:50.167170 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 11:45:50.170645 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 11:45:50.177526 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6390 11:45:50.180728 Total UI for P1: 0, mck2ui 16
6391 11:45:50.183660 best dqsien dly found for B0: ( 0, 14, 24)
6392 11:45:50.183762 Total UI for P1: 0, mck2ui 16
6393 11:45:50.190481 best dqsien dly found for B1: ( 0, 14, 24)
6394 11:45:50.193375 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6395 11:45:50.196994 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6396 11:45:50.197103
6397 11:45:50.199979 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6398 11:45:50.203632 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6399 11:45:50.206683 [Gating] SW calibration Done
6400 11:45:50.206779 ==
6401 11:45:50.210288 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 11:45:50.213338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 11:45:50.213447 ==
6404 11:45:50.216752 RX Vref Scan: 0
6405 11:45:50.216859
6406 11:45:50.219800 RX Vref 0 -> 0, step: 1
6407 11:45:50.219897
6408 11:45:50.219986 RX Delay -410 -> 252, step: 16
6409 11:45:50.226713 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6410 11:45:50.229699 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6411 11:45:50.233449 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6412 11:45:50.239881 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6413 11:45:50.243397 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6414 11:45:50.246679 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6415 11:45:50.249851 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6416 11:45:50.256373 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6417 11:45:50.259343 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6418 11:45:50.262900 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6419 11:45:50.266603 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6420 11:45:50.272801 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6421 11:45:50.276506 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6422 11:45:50.279889 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6423 11:45:50.282876 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6424 11:45:50.289991 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6425 11:45:50.290529 ==
6426 11:45:50.292919 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 11:45:50.296444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 11:45:50.297227 ==
6429 11:45:50.297908 DQS Delay:
6430 11:45:50.299672 DQS0 = 43, DQS1 = 59
6431 11:45:50.300327 DQM Delay:
6432 11:45:50.302741 DQM0 = 12, DQM1 = 12
6433 11:45:50.303463 DQ Delay:
6434 11:45:50.306360 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =0
6435 11:45:50.309366 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6436 11:45:50.312843 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6437 11:45:50.315847 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6438 11:45:50.316392
6439 11:45:50.316813
6440 11:45:50.317130 ==
6441 11:45:50.319519 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 11:45:50.323117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 11:45:50.323537 ==
6444 11:45:50.323869
6445 11:45:50.325959
6446 11:45:50.326443 TX Vref Scan disable
6447 11:45:50.329446 == TX Byte 0 ==
6448 11:45:50.333078 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 11:45:50.335841 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 11:45:50.339358 == TX Byte 1 ==
6451 11:45:50.342272 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6452 11:45:50.345896 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6453 11:45:50.346280 ==
6454 11:45:50.348838 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 11:45:50.355828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 11:45:50.356292 ==
6457 11:45:50.356723
6458 11:45:50.357099
6459 11:45:50.357500 TX Vref Scan disable
6460 11:45:50.358834 == TX Byte 0 ==
6461 11:45:50.362362 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6462 11:45:50.365447 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6463 11:45:50.368962 == TX Byte 1 ==
6464 11:45:50.372055 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6465 11:45:50.375292 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6466 11:45:50.375683
6467 11:45:50.378960 [DATLAT]
6468 11:45:50.379388 Freq=400, CH0 RK0
6469 11:45:50.379729
6470 11:45:50.381919 DATLAT Default: 0xf
6471 11:45:50.382376 0, 0xFFFF, sum = 0
6472 11:45:50.385347 1, 0xFFFF, sum = 0
6473 11:45:50.385790 2, 0xFFFF, sum = 0
6474 11:45:50.388810 3, 0xFFFF, sum = 0
6475 11:45:50.389424 4, 0xFFFF, sum = 0
6476 11:45:50.391694 5, 0xFFFF, sum = 0
6477 11:45:50.392290 6, 0xFFFF, sum = 0
6478 11:45:50.395152 7, 0xFFFF, sum = 0
6479 11:45:50.398160 8, 0xFFFF, sum = 0
6480 11:45:50.398778 9, 0xFFFF, sum = 0
6481 11:45:50.401682 10, 0xFFFF, sum = 0
6482 11:45:50.402117 11, 0xFFFF, sum = 0
6483 11:45:50.404861 12, 0xFFFF, sum = 0
6484 11:45:50.405296 13, 0x0, sum = 1
6485 11:45:50.408583 14, 0x0, sum = 2
6486 11:45:50.409017 15, 0x0, sum = 3
6487 11:45:50.411528 16, 0x0, sum = 4
6488 11:45:50.411969 best_step = 14
6489 11:45:50.412335
6490 11:45:50.412704 ==
6491 11:45:50.415399 Dram Type= 6, Freq= 0, CH_0, rank 0
6492 11:45:50.418309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 11:45:50.419058 ==
6494 11:45:50.421888 RX Vref Scan: 1
6495 11:45:50.422607
6496 11:45:50.424850 RX Vref 0 -> 0, step: 1
6497 11:45:50.425369
6498 11:45:50.427959 RX Delay -359 -> 252, step: 8
6499 11:45:50.428566
6500 11:45:50.431369 Set Vref, RX VrefLevel [Byte0]: 61
6501 11:45:50.434505 [Byte1]: 49
6502 11:45:50.434845
6503 11:45:50.437467 Final RX Vref Byte 0 = 61 to rank0
6504 11:45:50.440836 Final RX Vref Byte 1 = 49 to rank0
6505 11:45:50.443839 Final RX Vref Byte 0 = 61 to rank1
6506 11:45:50.447313 Final RX Vref Byte 1 = 49 to rank1==
6507 11:45:50.450719 Dram Type= 6, Freq= 0, CH_0, rank 0
6508 11:45:50.454219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 11:45:50.454397 ==
6510 11:45:50.457319 DQS Delay:
6511 11:45:50.457445 DQS0 = 48, DQS1 = 60
6512 11:45:50.461018 DQM Delay:
6513 11:45:50.461158 DQM0 = 12, DQM1 = 12
6514 11:45:50.463926 DQ Delay:
6515 11:45:50.464037 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6516 11:45:50.467369 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6517 11:45:50.470268 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6518 11:45:50.473868 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6519 11:45:50.473986
6520 11:45:50.474083
6521 11:45:50.483384 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6522 11:45:50.486966 CH0 RK0: MR19=C0C, MR18=BE81
6523 11:45:50.493287 CH0_RK0: MR19=0xC0C, MR18=0xBE81, DQSOSC=386, MR23=63, INC=396, DEC=264
6524 11:45:50.493373 ==
6525 11:45:50.496675 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 11:45:50.500258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 11:45:50.500382 ==
6528 11:45:50.503189 [Gating] SW mode calibration
6529 11:45:50.510239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6530 11:45:50.516358 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6531 11:45:50.519773 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6532 11:45:50.523610 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6533 11:45:50.530135 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 11:45:50.533281 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6535 11:45:50.536071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6536 11:45:50.543250 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6537 11:45:50.546374 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 11:45:50.549371 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 11:45:50.555912 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6540 11:45:50.556024 Total UI for P1: 0, mck2ui 16
6541 11:45:50.562861 best dqsien dly found for B0: ( 0, 14, 24)
6542 11:45:50.562954 Total UI for P1: 0, mck2ui 16
6543 11:45:50.565939 best dqsien dly found for B1: ( 0, 14, 24)
6544 11:45:50.572443 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6545 11:45:50.575820 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6546 11:45:50.575946
6547 11:45:50.579208 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6548 11:45:50.582696 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6549 11:45:50.585781 [Gating] SW calibration Done
6550 11:45:50.585971 ==
6551 11:45:50.589307 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 11:45:50.592774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 11:45:50.592961 ==
6554 11:45:50.595621 RX Vref Scan: 0
6555 11:45:50.595792
6556 11:45:50.595950 RX Vref 0 -> 0, step: 1
6557 11:45:50.596087
6558 11:45:50.599244 RX Delay -410 -> 252, step: 16
6559 11:45:50.605763 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6560 11:45:50.609197 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6561 11:45:50.612185 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6562 11:45:50.615630 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6563 11:45:50.622161 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6564 11:45:50.625441 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6565 11:45:50.628783 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6566 11:45:50.632457 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6567 11:45:50.639053 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6568 11:45:50.642300 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6569 11:45:50.645420 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6570 11:45:50.649023 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6571 11:45:50.654995 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6572 11:45:50.658464 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6573 11:45:50.661579 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6574 11:45:50.668317 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6575 11:45:50.668757 ==
6576 11:45:50.671818 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 11:45:50.674936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 11:45:50.675180 ==
6579 11:45:50.675399 DQS Delay:
6580 11:45:50.677885 DQS0 = 43, DQS1 = 59
6581 11:45:50.678132 DQM Delay:
6582 11:45:50.681630 DQM0 = 10, DQM1 = 16
6583 11:45:50.681940 DQ Delay:
6584 11:45:50.684501 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6585 11:45:50.688131 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6586 11:45:50.691583 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6587 11:45:50.694661 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6588 11:45:50.695037
6589 11:45:50.695382
6590 11:45:50.695717 ==
6591 11:45:50.698017 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 11:45:50.701536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 11:45:50.701933 ==
6594 11:45:50.702278
6595 11:45:50.702610
6596 11:45:50.704655 TX Vref Scan disable
6597 11:45:50.708305 == TX Byte 0 ==
6598 11:45:50.711198 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6599 11:45:50.714569 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6600 11:45:50.714822 == TX Byte 1 ==
6601 11:45:50.721005 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6602 11:45:50.724150 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6603 11:45:50.724362 ==
6604 11:45:50.727283 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 11:45:50.730788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 11:45:50.730970 ==
6607 11:45:50.731112
6608 11:45:50.734296
6609 11:45:50.734448 TX Vref Scan disable
6610 11:45:50.737418 == TX Byte 0 ==
6611 11:45:50.740939 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6612 11:45:50.743950 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6613 11:45:50.747440 == TX Byte 1 ==
6614 11:45:50.750513 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6615 11:45:50.754144 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6616 11:45:50.754294
6617 11:45:50.754420 [DATLAT]
6618 11:45:50.757032 Freq=400, CH0 RK1
6619 11:45:50.757166
6620 11:45:50.760739 DATLAT Default: 0xe
6621 11:45:50.760874 0, 0xFFFF, sum = 0
6622 11:45:50.763643 1, 0xFFFF, sum = 0
6623 11:45:50.763867 2, 0xFFFF, sum = 0
6624 11:45:50.767133 3, 0xFFFF, sum = 0
6625 11:45:50.767264 4, 0xFFFF, sum = 0
6626 11:45:50.770590 5, 0xFFFF, sum = 0
6627 11:45:50.770674 6, 0xFFFF, sum = 0
6628 11:45:50.773516 7, 0xFFFF, sum = 0
6629 11:45:50.773599 8, 0xFFFF, sum = 0
6630 11:45:50.777197 9, 0xFFFF, sum = 0
6631 11:45:50.777549 10, 0xFFFF, sum = 0
6632 11:45:50.780155 11, 0xFFFF, sum = 0
6633 11:45:50.780494 12, 0xFFFF, sum = 0
6634 11:45:50.783713 13, 0x0, sum = 1
6635 11:45:50.783963 14, 0x0, sum = 2
6636 11:45:50.787212 15, 0x0, sum = 3
6637 11:45:50.787474 16, 0x0, sum = 4
6638 11:45:50.790037 best_step = 14
6639 11:45:50.790281
6640 11:45:50.790478 ==
6641 11:45:50.793517 Dram Type= 6, Freq= 0, CH_0, rank 1
6642 11:45:50.796487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:45:50.796753 ==
6644 11:45:50.800538 RX Vref Scan: 0
6645 11:45:50.800789
6646 11:45:50.800984 RX Vref 0 -> 0, step: 1
6647 11:45:50.801167
6648 11:45:50.803456 RX Delay -359 -> 252, step: 8
6649 11:45:50.811620 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6650 11:45:50.814474 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6651 11:45:50.818229 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6652 11:45:50.824408 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6653 11:45:50.828087 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6654 11:45:50.831197 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6655 11:45:50.834628 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6656 11:45:50.841062 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6657 11:45:50.844376 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6658 11:45:50.847413 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6659 11:45:50.850867 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6660 11:45:50.857409 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6661 11:45:50.861069 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6662 11:45:50.864021 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6663 11:45:50.867118 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6664 11:45:50.874105 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6665 11:45:50.874445 ==
6666 11:45:50.877550 Dram Type= 6, Freq= 0, CH_0, rank 1
6667 11:45:50.880536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 11:45:50.880831 ==
6669 11:45:50.881095 DQS Delay:
6670 11:45:50.884139 DQS0 = 44, DQS1 = 60
6671 11:45:50.884418 DQM Delay:
6672 11:45:50.887062 DQM0 = 8, DQM1 = 16
6673 11:45:50.887346 DQ Delay:
6674 11:45:50.890574 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6675 11:45:50.893694 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6676 11:45:50.896988 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6677 11:45:50.900782 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6678 11:45:50.901215
6679 11:45:50.901529
6680 11:45:50.907054 [DQSOSCAuto] RK1, (LSB)MR18= 0xb23f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6681 11:45:50.910549 CH0 RK1: MR19=C0C, MR18=B23F
6682 11:45:50.917129 CH0_RK1: MR19=0xC0C, MR18=0xB23F, DQSOSC=387, MR23=63, INC=394, DEC=262
6683 11:45:50.920428 [RxdqsGatingPostProcess] freq 400
6684 11:45:50.926750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6685 11:45:50.930272 best DQS0 dly(2T, 0.5T) = (0, 10)
6686 11:45:50.933864 best DQS1 dly(2T, 0.5T) = (0, 10)
6687 11:45:50.936969 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6688 11:45:50.940449 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6689 11:45:50.940948 best DQS0 dly(2T, 0.5T) = (0, 10)
6690 11:45:50.943204 best DQS1 dly(2T, 0.5T) = (0, 10)
6691 11:45:50.946940 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6692 11:45:50.949895 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6693 11:45:50.953370 Pre-setting of DQS Precalculation
6694 11:45:50.959896 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6695 11:45:50.960300 ==
6696 11:45:50.963567 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 11:45:50.966827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 11:45:50.967380 ==
6699 11:45:50.973251 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6700 11:45:50.979628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6701 11:45:50.983182 [CA 0] Center 36 (8~64) winsize 57
6702 11:45:50.986305 [CA 1] Center 36 (8~64) winsize 57
6703 11:45:50.987001 [CA 2] Center 36 (8~64) winsize 57
6704 11:45:50.989829 [CA 3] Center 36 (8~64) winsize 57
6705 11:45:50.992812 [CA 4] Center 36 (8~64) winsize 57
6706 11:45:50.996309 [CA 5] Center 36 (8~64) winsize 57
6707 11:45:50.996823
6708 11:45:50.999380 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6709 11:45:51.002951
6710 11:45:51.006028 [CATrainingPosCal] consider 1 rank data
6711 11:45:51.006446 u2DelayCellTimex100 = 270/100 ps
6712 11:45:51.012899 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 11:45:51.016209 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 11:45:51.019309 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 11:45:51.022824 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 11:45:51.025638 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 11:45:51.028981 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:45:51.029513
6719 11:45:51.032417 CA PerBit enable=1, Macro0, CA PI delay=36
6720 11:45:51.033032
6721 11:45:51.035589 [CBTSetCACLKResult] CA Dly = 36
6722 11:45:51.039182 CS Dly: 1 (0~32)
6723 11:45:51.039727 ==
6724 11:45:51.042271 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 11:45:51.045397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 11:45:51.045902 ==
6727 11:45:51.052355 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6728 11:45:51.058794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6729 11:45:51.059531 [CA 0] Center 36 (8~64) winsize 57
6730 11:45:51.062320 [CA 1] Center 36 (8~64) winsize 57
6731 11:45:51.065388 [CA 2] Center 36 (8~64) winsize 57
6732 11:45:51.069036 [CA 3] Center 36 (8~64) winsize 57
6733 11:45:51.072018 [CA 4] Center 36 (8~64) winsize 57
6734 11:45:51.075152 [CA 5] Center 36 (8~64) winsize 57
6735 11:45:51.075879
6736 11:45:51.078576 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6737 11:45:51.079002
6738 11:45:51.085539 [CATrainingPosCal] consider 2 rank data
6739 11:45:51.085983 u2DelayCellTimex100 = 270/100 ps
6740 11:45:51.091394 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6741 11:45:51.094894 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6742 11:45:51.097964 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 11:45:51.101552 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 11:45:51.104399 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 11:45:51.107904 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 11:45:51.108000
6747 11:45:51.111032 CA PerBit enable=1, Macro0, CA PI delay=36
6748 11:45:51.111127
6749 11:45:51.114502 [CBTSetCACLKResult] CA Dly = 36
6750 11:45:51.117933 CS Dly: 1 (0~32)
6751 11:45:51.118059
6752 11:45:51.120807 ----->DramcWriteLeveling(PI) begin...
6753 11:45:51.120897 ==
6754 11:45:51.124218 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 11:45:51.127759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 11:45:51.127878 ==
6757 11:45:51.130994 Write leveling (Byte 0): 40 => 8
6758 11:45:51.134482 Write leveling (Byte 1): 32 => 0
6759 11:45:51.137384 DramcWriteLeveling(PI) end<-----
6760 11:45:51.137542
6761 11:45:51.137683 ==
6762 11:45:51.140861 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 11:45:51.143895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 11:45:51.144005 ==
6765 11:45:51.147630 [Gating] SW mode calibration
6766 11:45:51.153900 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6767 11:45:51.160808 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6768 11:45:51.164196 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6769 11:45:51.167562 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6770 11:45:51.174090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 11:45:51.177071 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6772 11:45:51.180723 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6773 11:45:51.187492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6774 11:45:51.191012 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 11:45:51.194064 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 11:45:51.200462 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6777 11:45:51.204439 Total UI for P1: 0, mck2ui 16
6778 11:45:51.206807 best dqsien dly found for B0: ( 0, 14, 24)
6779 11:45:51.210343 Total UI for P1: 0, mck2ui 16
6780 11:45:51.213865 best dqsien dly found for B1: ( 0, 14, 24)
6781 11:45:51.216764 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6782 11:45:51.220127 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6783 11:45:51.220716
6784 11:45:51.223700 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6785 11:45:51.226604 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6786 11:45:51.229927 [Gating] SW calibration Done
6787 11:45:51.230349 ==
6788 11:45:51.233587 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 11:45:51.236855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 11:45:51.237300 ==
6791 11:45:51.240118 RX Vref Scan: 0
6792 11:45:51.240569
6793 11:45:51.243438 RX Vref 0 -> 0, step: 1
6794 11:45:51.243883
6795 11:45:51.244226 RX Delay -410 -> 252, step: 16
6796 11:45:51.249881 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6797 11:45:51.253462 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6798 11:45:51.256596 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6799 11:45:51.259984 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6800 11:45:51.267092 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6801 11:45:51.270176 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6802 11:45:51.273434 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6803 11:45:51.276957 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6804 11:45:51.283573 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6805 11:45:51.286652 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6806 11:45:51.290185 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6807 11:45:51.296343 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6808 11:45:51.300142 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6809 11:45:51.303275 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6810 11:45:51.306351 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6811 11:45:51.312689 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6812 11:45:51.313122 ==
6813 11:45:51.316209 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 11:45:51.319424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 11:45:51.319855 ==
6816 11:45:51.320195 DQS Delay:
6817 11:45:51.322608 DQS0 = 43, DQS1 = 51
6818 11:45:51.323054 DQM Delay:
6819 11:45:51.326120 DQM0 = 12, DQM1 = 14
6820 11:45:51.326548 DQ Delay:
6821 11:45:51.329386 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6822 11:45:51.332299 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6823 11:45:51.335784 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6824 11:45:51.339497 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6825 11:45:51.339924
6826 11:45:51.340262
6827 11:45:51.340637 ==
6828 11:45:51.342456 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 11:45:51.345812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 11:45:51.346315 ==
6831 11:45:51.346725
6832 11:45:51.349072
6833 11:45:51.349592 TX Vref Scan disable
6834 11:45:51.352098 == TX Byte 0 ==
6835 11:45:51.355694 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 11:45:51.358645 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 11:45:51.362265 == TX Byte 1 ==
6838 11:45:51.365492 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6839 11:45:51.368764 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6840 11:45:51.369202 ==
6841 11:45:51.372101 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 11:45:51.378684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 11:45:51.379167 ==
6844 11:45:51.379772
6845 11:45:51.380295
6846 11:45:51.380836 TX Vref Scan disable
6847 11:45:51.382336 == TX Byte 0 ==
6848 11:45:51.385332 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6849 11:45:51.388765 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6850 11:45:51.391571 == TX Byte 1 ==
6851 11:45:51.394994 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6852 11:45:51.398460 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6853 11:45:51.398740
6854 11:45:51.401500 [DATLAT]
6855 11:45:51.401732 Freq=400, CH1 RK0
6856 11:45:51.401970
6857 11:45:51.405120 DATLAT Default: 0xf
6858 11:45:51.405353 0, 0xFFFF, sum = 0
6859 11:45:51.408117 1, 0xFFFF, sum = 0
6860 11:45:51.408355 2, 0xFFFF, sum = 0
6861 11:45:51.411555 3, 0xFFFF, sum = 0
6862 11:45:51.411791 4, 0xFFFF, sum = 0
6863 11:45:51.415133 5, 0xFFFF, sum = 0
6864 11:45:51.415370 6, 0xFFFF, sum = 0
6865 11:45:51.418031 7, 0xFFFF, sum = 0
6866 11:45:51.421460 8, 0xFFFF, sum = 0
6867 11:45:51.421700 9, 0xFFFF, sum = 0
6868 11:45:51.424481 10, 0xFFFF, sum = 0
6869 11:45:51.424735 11, 0xFFFF, sum = 0
6870 11:45:51.427985 12, 0xFFFF, sum = 0
6871 11:45:51.428220 13, 0x0, sum = 1
6872 11:45:51.431349 14, 0x0, sum = 2
6873 11:45:51.431660 15, 0x0, sum = 3
6874 11:45:51.434207 16, 0x0, sum = 4
6875 11:45:51.434440 best_step = 14
6876 11:45:51.434623
6877 11:45:51.434814 ==
6878 11:45:51.437614 Dram Type= 6, Freq= 0, CH_1, rank 0
6879 11:45:51.440884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 11:45:51.441134 ==
6881 11:45:51.444556 RX Vref Scan: 1
6882 11:45:51.444767
6883 11:45:51.447456 RX Vref 0 -> 0, step: 1
6884 11:45:51.447686
6885 11:45:51.447873 RX Delay -343 -> 252, step: 8
6886 11:45:51.451109
6887 11:45:51.451385 Set Vref, RX VrefLevel [Byte0]: 49
6888 11:45:51.454515 [Byte1]: 52
6889 11:45:51.459847
6890 11:45:51.460150 Final RX Vref Byte 0 = 49 to rank0
6891 11:45:51.463267 Final RX Vref Byte 1 = 52 to rank0
6892 11:45:51.467035 Final RX Vref Byte 0 = 49 to rank1
6893 11:45:51.469965 Final RX Vref Byte 1 = 52 to rank1==
6894 11:45:51.473015 Dram Type= 6, Freq= 0, CH_1, rank 0
6895 11:45:51.479839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 11:45:51.480010 ==
6897 11:45:51.480134 DQS Delay:
6898 11:45:51.482796 DQS0 = 44, DQS1 = 52
6899 11:45:51.482931 DQM Delay:
6900 11:45:51.483036 DQM0 = 8, DQM1 = 9
6901 11:45:51.486119 DQ Delay:
6902 11:45:51.489650 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6903 11:45:51.489781 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6904 11:45:51.492822 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6905 11:45:51.496270 DQ12 =20, DQ13 =12, DQ14 =16, DQ15 =16
6906 11:45:51.496374
6907 11:45:51.496451
6908 11:45:51.506262 [DQSOSCAuto] RK0, (LSB)MR18= 0x966c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6909 11:45:51.509789 CH1 RK0: MR19=C0C, MR18=966C
6910 11:45:51.516680 CH1_RK0: MR19=0xC0C, MR18=0x966C, DQSOSC=391, MR23=63, INC=386, DEC=257
6911 11:45:51.517128 ==
6912 11:45:51.519531 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 11:45:51.522914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 11:45:51.523348 ==
6915 11:45:51.526400 [Gating] SW mode calibration
6916 11:45:51.532772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6917 11:45:51.539032 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6918 11:45:51.542852 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6919 11:45:51.546187 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6920 11:45:51.552431 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 11:45:51.555973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6922 11:45:51.559077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6923 11:45:51.565757 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 11:45:51.568728 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 11:45:51.572050 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 11:45:51.578657 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6927 11:45:51.579229 Total UI for P1: 0, mck2ui 16
6928 11:45:51.585161 best dqsien dly found for B0: ( 0, 14, 24)
6929 11:45:51.585599 Total UI for P1: 0, mck2ui 16
6930 11:45:51.591582 best dqsien dly found for B1: ( 0, 14, 24)
6931 11:45:51.595036 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6932 11:45:51.598223 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6933 11:45:51.598635
6934 11:45:51.601712 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6935 11:45:51.605162 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6936 11:45:51.607982 [Gating] SW calibration Done
6937 11:45:51.608753 ==
6938 11:45:51.611610 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 11:45:51.614599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 11:45:51.615332 ==
6941 11:45:51.618176 RX Vref Scan: 0
6942 11:45:51.618772
6943 11:45:51.619350 RX Vref 0 -> 0, step: 1
6944 11:45:51.621317
6945 11:45:51.621752 RX Delay -410 -> 252, step: 16
6946 11:45:51.628334 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6947 11:45:51.631667 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6948 11:45:51.635155 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6949 11:45:51.638179 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6950 11:45:51.644949 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6951 11:45:51.647798 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6952 11:45:51.651358 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6953 11:45:51.654951 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6954 11:45:51.661055 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6955 11:45:51.664690 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6956 11:45:51.667787 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6957 11:45:51.674324 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6958 11:45:51.677300 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6959 11:45:51.680832 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6960 11:45:51.684407 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6961 11:45:51.690814 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6962 11:45:51.691243 ==
6963 11:45:51.693911 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 11:45:51.697343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 11:45:51.697724 ==
6966 11:45:51.698042 DQS Delay:
6967 11:45:51.700300 DQS0 = 51, DQS1 = 51
6968 11:45:51.700978 DQM Delay:
6969 11:45:51.703919 DQM0 = 20, DQM1 = 14
6970 11:45:51.704349 DQ Delay:
6971 11:45:51.706883 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6972 11:45:51.710479 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6973 11:45:51.714038 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6974 11:45:51.716858 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6975 11:45:51.717241
6976 11:45:51.717565
6977 11:45:51.717869 ==
6978 11:45:51.720066 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 11:45:51.723448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 11:45:51.727115 ==
6981 11:45:51.727672
6982 11:45:51.728151
6983 11:45:51.728658 TX Vref Scan disable
6984 11:45:51.730074 == TX Byte 0 ==
6985 11:45:51.733638 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6986 11:45:51.736585 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6987 11:45:51.740215 == TX Byte 1 ==
6988 11:45:51.743315 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6989 11:45:51.746531 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6990 11:45:51.746970 ==
6991 11:45:51.749767 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 11:45:51.756892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 11:45:51.757297 ==
6994 11:45:51.757630
6995 11:45:51.757937
6996 11:45:51.758305 TX Vref Scan disable
6997 11:45:51.759711 == TX Byte 0 ==
6998 11:45:51.763170 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6999 11:45:51.766615 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7000 11:45:51.769756 == TX Byte 1 ==
7001 11:45:51.773217 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
7002 11:45:51.776341 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
7003 11:45:51.776817
7004 11:45:51.779767 [DATLAT]
7005 11:45:51.780144 Freq=400, CH1 RK1
7006 11:45:51.780464
7007 11:45:51.782863 DATLAT Default: 0xe
7008 11:45:51.783228 0, 0xFFFF, sum = 0
7009 11:45:51.786623 1, 0xFFFF, sum = 0
7010 11:45:51.787048 2, 0xFFFF, sum = 0
7011 11:45:51.789613 3, 0xFFFF, sum = 0
7012 11:45:51.790152 4, 0xFFFF, sum = 0
7013 11:45:51.792965 5, 0xFFFF, sum = 0
7014 11:45:51.793606 6, 0xFFFF, sum = 0
7015 11:45:51.796384 7, 0xFFFF, sum = 0
7016 11:45:51.796859 8, 0xFFFF, sum = 0
7017 11:45:51.799209 9, 0xFFFF, sum = 0
7018 11:45:51.799751 10, 0xFFFF, sum = 0
7019 11:45:51.802843 11, 0xFFFF, sum = 0
7020 11:45:51.805930 12, 0xFFFF, sum = 0
7021 11:45:51.806390 13, 0x0, sum = 1
7022 11:45:51.809496 14, 0x0, sum = 2
7023 11:45:51.809925 15, 0x0, sum = 3
7024 11:45:51.810402 16, 0x0, sum = 4
7025 11:45:51.812493 best_step = 14
7026 11:45:51.812936
7027 11:45:51.813268 ==
7028 11:45:51.815847 Dram Type= 6, Freq= 0, CH_1, rank 1
7029 11:45:51.818873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7030 11:45:51.819318 ==
7031 11:45:51.822313 RX Vref Scan: 0
7032 11:45:51.822853
7033 11:45:51.825507 RX Vref 0 -> 0, step: 1
7034 11:45:51.825900
7035 11:45:51.826226 RX Delay -343 -> 252, step: 8
7036 11:45:51.834614 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7037 11:45:51.837401 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7038 11:45:51.841116 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7039 11:45:51.847452 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7040 11:45:51.850857 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7041 11:45:51.853708 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7042 11:45:51.857408 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7043 11:45:51.863987 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7044 11:45:51.867462 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7045 11:45:51.870280 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7046 11:45:51.873901 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7047 11:45:51.880440 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7048 11:45:51.883968 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7049 11:45:51.887207 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
7050 11:45:51.890763 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7051 11:45:51.897328 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7052 11:45:51.897814 ==
7053 11:45:51.900717 Dram Type= 6, Freq= 0, CH_1, rank 1
7054 11:45:51.903867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7055 11:45:51.904454 ==
7056 11:45:51.905018 DQS Delay:
7057 11:45:51.906923 DQS0 = 48, DQS1 = 56
7058 11:45:51.907436 DQM Delay:
7059 11:45:51.910173 DQM0 = 14, DQM1 = 11
7060 11:45:51.910561 DQ Delay:
7061 11:45:51.913464 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7062 11:45:51.916478 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =12
7063 11:45:51.919935 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7064 11:45:51.923518 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
7065 11:45:51.923926
7066 11:45:51.924305
7067 11:45:51.930340 [DQSOSCAuto] RK1, (LSB)MR18= 0x6452, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7068 11:45:51.933261 CH1 RK1: MR19=C0C, MR18=6452
7069 11:45:51.940272 CH1_RK1: MR19=0xC0C, MR18=0x6452, DQSOSC=397, MR23=63, INC=374, DEC=249
7070 11:45:51.943162 [RxdqsGatingPostProcess] freq 400
7071 11:45:51.949569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7072 11:45:51.953231 best DQS0 dly(2T, 0.5T) = (0, 10)
7073 11:45:51.956589 best DQS1 dly(2T, 0.5T) = (0, 10)
7074 11:45:51.960144 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7075 11:45:51.963079 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7076 11:45:51.966517 best DQS0 dly(2T, 0.5T) = (0, 10)
7077 11:45:51.966845 best DQS1 dly(2T, 0.5T) = (0, 10)
7078 11:45:51.969653 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7079 11:45:51.972818 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7080 11:45:51.976201 Pre-setting of DQS Precalculation
7081 11:45:51.982985 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7082 11:45:51.989398 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7083 11:45:51.995944 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7084 11:45:51.996727
7085 11:45:51.997428
7086 11:45:51.999334 [Calibration Summary] 800 Mbps
7087 11:45:52.002369 CH 0, Rank 0
7088 11:45:52.003020 SW Impedance : PASS
7089 11:45:52.005838 DUTY Scan : NO K
7090 11:45:52.008896 ZQ Calibration : PASS
7091 11:45:52.009616 Jitter Meter : NO K
7092 11:45:52.012702 CBT Training : PASS
7093 11:45:52.013407 Write leveling : PASS
7094 11:45:52.015519 RX DQS gating : PASS
7095 11:45:52.019045 RX DQ/DQS(RDDQC) : PASS
7096 11:45:52.019566 TX DQ/DQS : PASS
7097 11:45:52.021885 RX DATLAT : PASS
7098 11:45:52.025258 RX DQ/DQS(Engine): PASS
7099 11:45:52.025640 TX OE : NO K
7100 11:45:52.028661 All Pass.
7101 11:45:52.028962
7102 11:45:52.029243 CH 0, Rank 1
7103 11:45:52.032364 SW Impedance : PASS
7104 11:45:52.032633 DUTY Scan : NO K
7105 11:45:52.035386 ZQ Calibration : PASS
7106 11:45:52.038394 Jitter Meter : NO K
7107 11:45:52.038547 CBT Training : PASS
7108 11:45:52.041883 Write leveling : NO K
7109 11:45:52.045094 RX DQS gating : PASS
7110 11:45:52.045305 RX DQ/DQS(RDDQC) : PASS
7111 11:45:52.048542 TX DQ/DQS : PASS
7112 11:45:52.052090 RX DATLAT : PASS
7113 11:45:52.052188 RX DQ/DQS(Engine): PASS
7114 11:45:52.055361 TX OE : NO K
7115 11:45:52.055455 All Pass.
7116 11:45:52.055528
7117 11:45:52.058294 CH 1, Rank 0
7118 11:45:52.058388 SW Impedance : PASS
7119 11:45:52.061875 DUTY Scan : NO K
7120 11:45:52.064761 ZQ Calibration : PASS
7121 11:45:52.064846 Jitter Meter : NO K
7122 11:45:52.068737 CBT Training : PASS
7123 11:45:52.071556 Write leveling : PASS
7124 11:45:52.072115 RX DQS gating : PASS
7125 11:45:52.075165 RX DQ/DQS(RDDQC) : PASS
7126 11:45:52.078238 TX DQ/DQS : PASS
7127 11:45:52.078674 RX DATLAT : PASS
7128 11:45:52.081668 RX DQ/DQS(Engine): PASS
7129 11:45:52.082096 TX OE : NO K
7130 11:45:52.084617 All Pass.
7131 11:45:52.085136
7132 11:45:52.085654 CH 1, Rank 1
7133 11:45:52.088293 SW Impedance : PASS
7134 11:45:52.091667 DUTY Scan : NO K
7135 11:45:52.092086 ZQ Calibration : PASS
7136 11:45:52.094835 Jitter Meter : NO K
7137 11:45:52.095197 CBT Training : PASS
7138 11:45:52.098354 Write leveling : NO K
7139 11:45:52.101103 RX DQS gating : PASS
7140 11:45:52.101534 RX DQ/DQS(RDDQC) : PASS
7141 11:45:52.104622 TX DQ/DQS : PASS
7142 11:45:52.107484 RX DATLAT : PASS
7143 11:45:52.107841 RX DQ/DQS(Engine): PASS
7144 11:45:52.111048 TX OE : NO K
7145 11:45:52.111414 All Pass.
7146 11:45:52.111741
7147 11:45:52.114524 DramC Write-DBI off
7148 11:45:52.117522 PER_BANK_REFRESH: Hybrid Mode
7149 11:45:52.117970 TX_TRACKING: ON
7150 11:45:52.127538 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7151 11:45:52.130618 [FAST_K] Save calibration result to emmc
7152 11:45:52.134222 dramc_set_vcore_voltage set vcore to 725000
7153 11:45:52.137353 Read voltage for 1600, 0
7154 11:45:52.137583 Vio18 = 0
7155 11:45:52.140849 Vcore = 725000
7156 11:45:52.141078 Vdram = 0
7157 11:45:52.141259 Vddq = 0
7158 11:45:52.141430 Vmddr = 0
7159 11:45:52.147465 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7160 11:45:52.154166 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7161 11:45:52.154436 MEM_TYPE=3, freq_sel=13
7162 11:45:52.157104 sv_algorithm_assistance_LP4_3733
7163 11:45:52.160755 ============ PULL DRAM RESETB DOWN ============
7164 11:45:52.167219 ========== PULL DRAM RESETB DOWN end =========
7165 11:45:52.170557 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 11:45:52.173541 ===================================
7167 11:45:52.177149 LPDDR4 DRAM CONFIGURATION
7168 11:45:52.180451 ===================================
7169 11:45:52.180711 EX_ROW_EN[0] = 0x0
7170 11:45:52.183546 EX_ROW_EN[1] = 0x0
7171 11:45:52.183851 LP4Y_EN = 0x0
7172 11:45:52.187079 WORK_FSP = 0x1
7173 11:45:52.190015 WL = 0x5
7174 11:45:52.190269 RL = 0x5
7175 11:45:52.193637 BL = 0x2
7176 11:45:52.193865 RPST = 0x0
7177 11:45:52.196463 RD_PRE = 0x0
7178 11:45:52.196699 WR_PRE = 0x1
7179 11:45:52.200151 WR_PST = 0x1
7180 11:45:52.200357 DBI_WR = 0x0
7181 11:45:52.203374 DBI_RD = 0x0
7182 11:45:52.203601 OTF = 0x1
7183 11:45:52.206923 ===================================
7184 11:45:52.209909 ===================================
7185 11:45:52.213420 ANA top config
7186 11:45:52.216234 ===================================
7187 11:45:52.216550 DLL_ASYNC_EN = 0
7188 11:45:52.220117 ALL_SLAVE_EN = 0
7189 11:45:52.223032 NEW_RANK_MODE = 1
7190 11:45:52.226689 DLL_IDLE_MODE = 1
7191 11:45:52.229773 LP45_APHY_COMB_EN = 1
7192 11:45:52.230033 TX_ODT_DIS = 0
7193 11:45:52.233212 NEW_8X_MODE = 1
7194 11:45:52.236252 ===================================
7195 11:45:52.239207 ===================================
7196 11:45:52.242869 data_rate = 3200
7197 11:45:52.246537 CKR = 1
7198 11:45:52.250145 DQ_P2S_RATIO = 8
7199 11:45:52.253145 ===================================
7200 11:45:52.256015 CA_P2S_RATIO = 8
7201 11:45:52.256717 DQ_CA_OPEN = 0
7202 11:45:52.259624 DQ_SEMI_OPEN = 0
7203 11:45:52.262709 CA_SEMI_OPEN = 0
7204 11:45:52.266193 CA_FULL_RATE = 0
7205 11:45:52.269739 DQ_CKDIV4_EN = 0
7206 11:45:52.272385 CA_CKDIV4_EN = 0
7207 11:45:52.272913 CA_PREDIV_EN = 0
7208 11:45:52.276026 PH8_DLY = 12
7209 11:45:52.279364 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7210 11:45:52.282625 DQ_AAMCK_DIV = 4
7211 11:45:52.285866 CA_AAMCK_DIV = 4
7212 11:45:52.288781 CA_ADMCK_DIV = 4
7213 11:45:52.289012 DQ_TRACK_CA_EN = 0
7214 11:45:52.292155 CA_PICK = 1600
7215 11:45:52.295266 CA_MCKIO = 1600
7216 11:45:52.298872 MCKIO_SEMI = 0
7217 11:45:52.302450 PLL_FREQ = 3068
7218 11:45:52.305599 DQ_UI_PI_RATIO = 32
7219 11:45:52.308770 CA_UI_PI_RATIO = 0
7220 11:45:52.312182 ===================================
7221 11:45:52.315155 ===================================
7222 11:45:52.315345 memory_type:LPDDR4
7223 11:45:52.318632 GP_NUM : 10
7224 11:45:52.322062 SRAM_EN : 1
7225 11:45:52.322338 MD32_EN : 0
7226 11:45:52.325183 ===================================
7227 11:45:52.328746 [ANA_INIT] >>>>>>>>>>>>>>
7228 11:45:52.331728 <<<<<< [CONFIGURE PHASE]: ANA_TX
7229 11:45:52.335339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7230 11:45:52.338161 ===================================
7231 11:45:52.341862 data_rate = 3200,PCW = 0X7600
7232 11:45:52.344742 ===================================
7233 11:45:52.348268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7234 11:45:52.351860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7235 11:45:52.358257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7236 11:45:52.361756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7237 11:45:52.368228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7238 11:45:52.371929 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7239 11:45:52.372571 [ANA_INIT] flow start
7240 11:45:52.374858 [ANA_INIT] PLL >>>>>>>>
7241 11:45:52.378200 [ANA_INIT] PLL <<<<<<<<
7242 11:45:52.378942 [ANA_INIT] MIDPI >>>>>>>>
7243 11:45:52.381817 [ANA_INIT] MIDPI <<<<<<<<
7244 11:45:52.384724 [ANA_INIT] DLL >>>>>>>>
7245 11:45:52.385463 [ANA_INIT] DLL <<<<<<<<
7246 11:45:52.388294 [ANA_INIT] flow end
7247 11:45:52.391802 ============ LP4 DIFF to SE enter ============
7248 11:45:52.395000 ============ LP4 DIFF to SE exit ============
7249 11:45:52.397980 [ANA_INIT] <<<<<<<<<<<<<
7250 11:45:52.401567 [Flow] Enable top DCM control >>>>>
7251 11:45:52.404740 [Flow] Enable top DCM control <<<<<
7252 11:45:52.408311 Enable DLL master slave shuffle
7253 11:45:52.414415 ==============================================================
7254 11:45:52.414740 Gating Mode config
7255 11:45:52.420951 ==============================================================
7256 11:45:52.424474 Config description:
7257 11:45:52.431045 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7258 11:45:52.437659 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7259 11:45:52.443870 SELPH_MODE 0: By rank 1: By Phase
7260 11:45:52.450991 ==============================================================
7261 11:45:52.451219 GAT_TRACK_EN = 1
7262 11:45:52.454012 RX_GATING_MODE = 2
7263 11:45:52.457541 RX_GATING_TRACK_MODE = 2
7264 11:45:52.460425 SELPH_MODE = 1
7265 11:45:52.463617 PICG_EARLY_EN = 1
7266 11:45:52.467250 VALID_LAT_VALUE = 1
7267 11:45:52.474109 ==============================================================
7268 11:45:52.477048 Enter into Gating configuration >>>>
7269 11:45:52.480595 Exit from Gating configuration <<<<
7270 11:45:52.483930 Enter into DVFS_PRE_config >>>>>
7271 11:45:52.494013 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7272 11:45:52.497261 Exit from DVFS_PRE_config <<<<<
7273 11:45:52.500238 Enter into PICG configuration >>>>
7274 11:45:52.503751 Exit from PICG configuration <<<<
7275 11:45:52.507418 [RX_INPUT] configuration >>>>>
7276 11:45:52.510397 [RX_INPUT] configuration <<<<<
7277 11:45:52.514026 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7278 11:45:52.520512 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7279 11:45:52.526959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7280 11:45:52.530384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7281 11:45:52.536973 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7282 11:45:52.543481 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7283 11:45:52.546524 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7284 11:45:52.553227 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7285 11:45:52.556633 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7286 11:45:52.559753 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7287 11:45:52.562927 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7288 11:45:52.569685 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7289 11:45:52.573323 ===================================
7290 11:45:52.576248 LPDDR4 DRAM CONFIGURATION
7291 11:45:52.579665 ===================================
7292 11:45:52.580399 EX_ROW_EN[0] = 0x0
7293 11:45:52.583296 EX_ROW_EN[1] = 0x0
7294 11:45:52.583994 LP4Y_EN = 0x0
7295 11:45:52.586062 WORK_FSP = 0x1
7296 11:45:52.586781 WL = 0x5
7297 11:45:52.589440 RL = 0x5
7298 11:45:52.590166 BL = 0x2
7299 11:45:52.593029 RPST = 0x0
7300 11:45:52.593407 RD_PRE = 0x0
7301 11:45:52.595906 WR_PRE = 0x1
7302 11:45:52.596303 WR_PST = 0x1
7303 11:45:52.599457 DBI_WR = 0x0
7304 11:45:52.599770 DBI_RD = 0x0
7305 11:45:52.602744 OTF = 0x1
7306 11:45:52.605978 ===================================
7307 11:45:52.609671 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7308 11:45:52.612624 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7309 11:45:52.619600 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7310 11:45:52.622813 ===================================
7311 11:45:52.623380 LPDDR4 DRAM CONFIGURATION
7312 11:45:52.626071 ===================================
7313 11:45:52.629317 EX_ROW_EN[0] = 0x10
7314 11:45:52.633105 EX_ROW_EN[1] = 0x0
7315 11:45:52.633540 LP4Y_EN = 0x0
7316 11:45:52.636001 WORK_FSP = 0x1
7317 11:45:52.636592 WL = 0x5
7318 11:45:52.638846 RL = 0x5
7319 11:45:52.639334 BL = 0x2
7320 11:45:52.642416 RPST = 0x0
7321 11:45:52.642849 RD_PRE = 0x0
7322 11:45:52.646022 WR_PRE = 0x1
7323 11:45:52.646614 WR_PST = 0x1
7324 11:45:52.649056 DBI_WR = 0x0
7325 11:45:52.649551 DBI_RD = 0x0
7326 11:45:52.652383 OTF = 0x1
7327 11:45:52.655930 ===================================
7328 11:45:52.662013 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7329 11:45:52.662369 ==
7330 11:45:52.665562 Dram Type= 6, Freq= 0, CH_0, rank 0
7331 11:45:52.668394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 11:45:52.668622 ==
7333 11:45:52.671991 [Duty_Offset_Calibration]
7334 11:45:52.672154 B0:1 B1:-1 CA:0
7335 11:45:52.672293
7336 11:45:52.675027 [DutyScan_Calibration_Flow] k_type=0
7337 11:45:52.686272
7338 11:45:52.686509 ==CLK 0==
7339 11:45:52.689859 Final CLK duty delay cell = 0
7340 11:45:52.693210 [0] MAX Duty = 5156%(X100), DQS PI = 24
7341 11:45:52.696026 [0] MIN Duty = 4907%(X100), DQS PI = 4
7342 11:45:52.696284 [0] AVG Duty = 5031%(X100)
7343 11:45:52.699865
7344 11:45:52.702757 CH0 CLK Duty spec in!! Max-Min= 249%
7345 11:45:52.706217 [DutyScan_Calibration_Flow] ====Done====
7346 11:45:52.706539
7347 11:45:52.709879 [DutyScan_Calibration_Flow] k_type=1
7348 11:45:52.726148
7349 11:45:52.726630 ==DQS 0 ==
7350 11:45:52.729028 Final DQS duty delay cell = -4
7351 11:45:52.732577 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7352 11:45:52.735580 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7353 11:45:52.738515 [-4] AVG Duty = 4922%(X100)
7354 11:45:52.739117
7355 11:45:52.739598 ==DQS 1 ==
7356 11:45:52.742763 Final DQS duty delay cell = 0
7357 11:45:52.745697 [0] MAX Duty = 5187%(X100), DQS PI = 4
7358 11:45:52.748587 [0] MIN Duty = 5031%(X100), DQS PI = 18
7359 11:45:52.752153 [0] AVG Duty = 5109%(X100)
7360 11:45:52.752868
7361 11:45:52.755545 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7362 11:45:52.756048
7363 11:45:52.758502 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7364 11:45:52.762112 [DutyScan_Calibration_Flow] ====Done====
7365 11:45:52.762624
7366 11:45:52.765290 [DutyScan_Calibration_Flow] k_type=3
7367 11:45:52.783071
7368 11:45:52.783445 ==DQM 0 ==
7369 11:45:52.786575 Final DQM duty delay cell = 0
7370 11:45:52.789447 [0] MAX Duty = 5124%(X100), DQS PI = 22
7371 11:45:52.792842 [0] MIN Duty = 4907%(X100), DQS PI = 10
7372 11:45:52.796142 [0] AVG Duty = 5015%(X100)
7373 11:45:52.796377
7374 11:45:52.796598 ==DQM 1 ==
7375 11:45:52.799085 Final DQM duty delay cell = 0
7376 11:45:52.802633 [0] MAX Duty = 5000%(X100), DQS PI = 4
7377 11:45:52.806111 [0] MIN Duty = 4782%(X100), DQS PI = 20
7378 11:45:52.808962 [0] AVG Duty = 4891%(X100)
7379 11:45:52.809184
7380 11:45:52.812305 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7381 11:45:52.812533
7382 11:45:52.815830 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7383 11:45:52.818941 [DutyScan_Calibration_Flow] ====Done====
7384 11:45:52.819151
7385 11:45:52.822481 [DutyScan_Calibration_Flow] k_type=2
7386 11:45:52.839491
7387 11:45:52.840085 ==DQ 0 ==
7388 11:45:52.843081 Final DQ duty delay cell = -4
7389 11:45:52.846277 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7390 11:45:52.849207 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7391 11:45:52.852590 [-4] AVG Duty = 4953%(X100)
7392 11:45:52.853142
7393 11:45:52.853641 ==DQ 1 ==
7394 11:45:52.856167 Final DQ duty delay cell = 0
7395 11:45:52.858967 [0] MAX Duty = 5125%(X100), DQS PI = 2
7396 11:45:52.862574 [0] MIN Duty = 5000%(X100), DQS PI = 34
7397 11:45:52.865557 [0] AVG Duty = 5062%(X100)
7398 11:45:52.866103
7399 11:45:52.869442 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7400 11:45:52.870038
7401 11:45:52.872588 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7402 11:45:52.875556 [DutyScan_Calibration_Flow] ====Done====
7403 11:45:52.876101 ==
7404 11:45:52.879233 Dram Type= 6, Freq= 0, CH_1, rank 0
7405 11:45:52.882269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7406 11:45:52.882798 ==
7407 11:45:52.885772 [Duty_Offset_Calibration]
7408 11:45:52.886269 B0:-1 B1:1 CA:2
7409 11:45:52.886717
7410 11:45:52.888954 [DutyScan_Calibration_Flow] k_type=0
7411 11:45:52.899987
7412 11:45:52.900666 ==CLK 0==
7413 11:45:52.903329 Final CLK duty delay cell = 0
7414 11:45:52.906882 [0] MAX Duty = 5187%(X100), DQS PI = 22
7415 11:45:52.909783 [0] MIN Duty = 4969%(X100), DQS PI = 62
7416 11:45:52.913382 [0] AVG Duty = 5078%(X100)
7417 11:45:52.914250
7418 11:45:52.916915 CH1 CLK Duty spec in!! Max-Min= 218%
7419 11:45:52.920379 [DutyScan_Calibration_Flow] ====Done====
7420 11:45:52.921451
7421 11:45:52.923270 [DutyScan_Calibration_Flow] k_type=1
7422 11:45:52.939716
7423 11:45:52.940220 ==DQS 0 ==
7424 11:45:52.943049 Final DQS duty delay cell = 0
7425 11:45:52.946451 [0] MAX Duty = 5124%(X100), DQS PI = 16
7426 11:45:52.949454 [0] MIN Duty = 4907%(X100), DQS PI = 10
7427 11:45:52.953246 [0] AVG Duty = 5015%(X100)
7428 11:45:52.953485
7429 11:45:52.953783 ==DQS 1 ==
7430 11:45:52.956296 Final DQS duty delay cell = 0
7431 11:45:52.959710 [0] MAX Duty = 5093%(X100), DQS PI = 26
7432 11:45:52.962698 [0] MIN Duty = 4969%(X100), DQS PI = 56
7433 11:45:52.966225 [0] AVG Duty = 5031%(X100)
7434 11:45:52.966490
7435 11:45:52.969141 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7436 11:45:52.969383
7437 11:45:52.972783 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7438 11:45:52.976225 [DutyScan_Calibration_Flow] ====Done====
7439 11:45:52.976653
7440 11:45:52.979157 [DutyScan_Calibration_Flow] k_type=3
7441 11:45:52.996339
7442 11:45:52.996961 ==DQM 0 ==
7443 11:45:52.999766 Final DQM duty delay cell = -4
7444 11:45:53.002689 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7445 11:45:53.005617 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7446 11:45:53.008934 [-4] AVG Duty = 4937%(X100)
7447 11:45:53.009370
7448 11:45:53.009714 ==DQM 1 ==
7449 11:45:53.012573 Final DQM duty delay cell = 0
7450 11:45:53.016036 [0] MAX Duty = 5156%(X100), DQS PI = 6
7451 11:45:53.019245 [0] MIN Duty = 4969%(X100), DQS PI = 34
7452 11:45:53.022050 [0] AVG Duty = 5062%(X100)
7453 11:45:53.022695
7454 11:45:53.025683 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7455 11:45:53.026337
7456 11:45:53.028973 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7457 11:45:53.032232 [DutyScan_Calibration_Flow] ====Done====
7458 11:45:53.032877
7459 11:45:53.035558 [DutyScan_Calibration_Flow] k_type=2
7460 11:45:53.053236
7461 11:45:53.053709 ==DQ 0 ==
7462 11:45:53.056253 Final DQ duty delay cell = 0
7463 11:45:53.059737 [0] MAX Duty = 5156%(X100), DQS PI = 30
7464 11:45:53.062776 [0] MIN Duty = 4906%(X100), DQS PI = 8
7465 11:45:53.066202 [0] AVG Duty = 5031%(X100)
7466 11:45:53.066672
7467 11:45:53.067018 ==DQ 1 ==
7468 11:45:53.069172 Final DQ duty delay cell = 0
7469 11:45:53.072995 [0] MAX Duty = 5156%(X100), DQS PI = 8
7470 11:45:53.075803 [0] MIN Duty = 4969%(X100), DQS PI = 56
7471 11:45:53.076234 [0] AVG Duty = 5062%(X100)
7472 11:45:53.079584
7473 11:45:53.082524 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7474 11:45:53.082993
7475 11:45:53.086075 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7476 11:45:53.089542 [DutyScan_Calibration_Flow] ====Done====
7477 11:45:53.092324 nWR fixed to 30
7478 11:45:53.092814 [ModeRegInit_LP4] CH0 RK0
7479 11:45:53.096004 [ModeRegInit_LP4] CH0 RK1
7480 11:45:53.099620 [ModeRegInit_LP4] CH1 RK0
7481 11:45:53.102430 [ModeRegInit_LP4] CH1 RK1
7482 11:45:53.102903 match AC timing 5
7483 11:45:53.109478 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7484 11:45:53.112281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7485 11:45:53.115497 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7486 11:45:53.122486 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7487 11:45:53.125536 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7488 11:45:53.126002 [MiockJmeterHQA]
7489 11:45:53.126248
7490 11:45:53.128648 [DramcMiockJmeter] u1RxGatingPI = 0
7491 11:45:53.132174 0 : 4363, 4138
7492 11:45:53.132604 4 : 4252, 4027
7493 11:45:53.135310 8 : 4363, 4138
7494 11:45:53.135725 12 : 4253, 4026
7495 11:45:53.138256 16 : 4252, 4027
7496 11:45:53.138572 20 : 4368, 4140
7497 11:45:53.138817 24 : 4252, 4027
7498 11:45:53.142080 28 : 4253, 4027
7499 11:45:53.142572 32 : 4252, 4027
7500 11:45:53.145068 36 : 4255, 4029
7501 11:45:53.145598 40 : 4250, 4027
7502 11:45:53.148541 44 : 4249, 4027
7503 11:45:53.148830 48 : 4363, 4140
7504 11:45:53.151534 52 : 4250, 4027
7505 11:45:53.151838 56 : 4252, 4029
7506 11:45:53.152080 60 : 4250, 4026
7507 11:45:53.155223 64 : 4363, 4140
7508 11:45:53.155624 68 : 4250, 4027
7509 11:45:53.158345 72 : 4361, 4137
7510 11:45:53.158652 76 : 4249, 4027
7511 11:45:53.161795 80 : 4250, 4027
7512 11:45:53.162143 84 : 4250, 4027
7513 11:45:53.164737 88 : 4252, 4028
7514 11:45:53.165134 92 : 4250, 348
7515 11:45:53.165392 96 : 4250, 0
7516 11:45:53.168253 100 : 4360, 0
7517 11:45:53.168743 104 : 4360, 0
7518 11:45:53.171690 108 : 4248, 0
7519 11:45:53.172131 112 : 4250, 0
7520 11:45:53.172390 116 : 4360, 0
7521 11:45:53.175070 120 : 4250, 0
7522 11:45:53.175504 124 : 4250, 0
7523 11:45:53.175757 128 : 4249, 0
7524 11:45:53.178069 132 : 4250, 0
7525 11:45:53.178412 136 : 4250, 0
7526 11:45:53.181644 140 : 4249, 0
7527 11:45:53.181947 144 : 4250, 0
7528 11:45:53.182191 148 : 4250, 0
7529 11:45:53.184820 152 : 4249, 0
7530 11:45:53.185128 156 : 4360, 0
7531 11:45:53.187887 160 : 4250, 0
7532 11:45:53.188233 164 : 4250, 0
7533 11:45:53.188509 168 : 4250, 0
7534 11:45:53.191653 172 : 4250, 0
7535 11:45:53.191998 176 : 4250, 0
7536 11:45:53.194636 180 : 4250, 0
7537 11:45:53.194942 184 : 4250, 0
7538 11:45:53.195187 188 : 4250, 0
7539 11:45:53.198267 192 : 4361, 0
7540 11:45:53.198706 196 : 4250, 0
7541 11:45:53.201449 200 : 4250, 0
7542 11:45:53.201755 204 : 4249, 0
7543 11:45:53.202081 208 : 4361, 0
7544 11:45:53.204864 212 : 4250, 0
7545 11:45:53.205221 216 : 4249, 0
7546 11:45:53.205572 220 : 4360, 0
7547 11:45:53.208240 224 : 4250, 479
7548 11:45:53.208598 228 : 4250, 3370
7549 11:45:53.210991 232 : 4249, 4027
7550 11:45:53.211323 236 : 4250, 4027
7551 11:45:53.214630 240 : 4250, 4027
7552 11:45:53.214957 244 : 4250, 4027
7553 11:45:53.218031 248 : 4250, 4027
7554 11:45:53.218364 252 : 4252, 4029
7555 11:45:53.221001 256 : 4250, 4027
7556 11:45:53.221310 260 : 4360, 4138
7557 11:45:53.224626 264 : 4361, 4138
7558 11:45:53.224935 268 : 4250, 4027
7559 11:45:53.227384 272 : 4363, 4140
7560 11:45:53.227695 276 : 4360, 4138
7561 11:45:53.227942 280 : 4250, 4027
7562 11:45:53.230907 284 : 4250, 4027
7563 11:45:53.231216 288 : 4252, 4029
7564 11:45:53.234238 292 : 4250, 4027
7565 11:45:53.234728 296 : 4250, 4027
7566 11:45:53.237534 300 : 4249, 4027
7567 11:45:53.237964 304 : 4252, 4029
7568 11:45:53.241114 308 : 4250, 4027
7569 11:45:53.241423 312 : 4360, 4138
7570 11:45:53.244034 316 : 4360, 4138
7571 11:45:53.244339 320 : 4250, 4027
7572 11:45:53.247606 324 : 4363, 4140
7573 11:45:53.247890 328 : 4360, 4138
7574 11:45:53.250578 332 : 4250, 4027
7575 11:45:53.250845 336 : 4249, 3528
7576 11:45:53.254239 340 : 4252, 1622
7577 11:45:53.254513
7578 11:45:53.254740 MIOCK jitter meter ch=0
7579 11:45:53.254973
7580 11:45:53.257303 1T = (340-92) = 248 dly cells
7581 11:45:53.263593 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7582 11:45:53.263708 ==
7583 11:45:53.267268 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 11:45:53.270325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 11:45:53.270415 ==
7586 11:45:53.276882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7587 11:45:53.280363 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7588 11:45:53.283403 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7589 11:45:53.290502 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7590 11:45:53.300016 [CA 0] Center 43 (13~74) winsize 62
7591 11:45:53.303102 [CA 1] Center 43 (13~74) winsize 62
7592 11:45:53.306663 [CA 2] Center 39 (10~69) winsize 60
7593 11:45:53.310157 [CA 3] Center 38 (9~68) winsize 60
7594 11:45:53.313182 [CA 4] Center 37 (8~66) winsize 59
7595 11:45:53.316152 [CA 5] Center 36 (7~66) winsize 60
7596 11:45:53.316327
7597 11:45:53.320140 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7598 11:45:53.320313
7599 11:45:53.322925 [CATrainingPosCal] consider 1 rank data
7600 11:45:53.326638 u2DelayCellTimex100 = 262/100 ps
7601 11:45:53.333128 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7602 11:45:53.336031 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7603 11:45:53.340054 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7604 11:45:53.342945 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7605 11:45:53.346020 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7606 11:45:53.349756 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7607 11:45:53.349962
7608 11:45:53.352652 CA PerBit enable=1, Macro0, CA PI delay=36
7609 11:45:53.352810
7610 11:45:53.356392 [CBTSetCACLKResult] CA Dly = 36
7611 11:45:53.359243 CS Dly: 12 (0~43)
7612 11:45:53.362813 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7613 11:45:53.365720 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7614 11:45:53.365882 ==
7615 11:45:53.369483 Dram Type= 6, Freq= 0, CH_0, rank 1
7616 11:45:53.375915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 11:45:53.376102 ==
7618 11:45:53.379462 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7619 11:45:53.386137 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7620 11:45:53.388955 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7621 11:45:53.395461 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7622 11:45:53.403489 [CA 0] Center 43 (13~74) winsize 62
7623 11:45:53.407039 [CA 1] Center 44 (14~74) winsize 61
7624 11:45:53.410058 [CA 2] Center 38 (9~68) winsize 60
7625 11:45:53.413498 [CA 3] Center 38 (9~68) winsize 60
7626 11:45:53.417091 [CA 4] Center 36 (7~66) winsize 60
7627 11:45:53.419770 [CA 5] Center 36 (7~66) winsize 60
7628 11:45:53.419859
7629 11:45:53.423216 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7630 11:45:53.423302
7631 11:45:53.426647 [CATrainingPosCal] consider 2 rank data
7632 11:45:53.429837 u2DelayCellTimex100 = 262/100 ps
7633 11:45:53.436314 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7634 11:45:53.439707 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7635 11:45:53.443229 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7636 11:45:53.446154 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7637 11:45:53.449949 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7638 11:45:53.452989 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7639 11:45:53.453078
7640 11:45:53.456486 CA PerBit enable=1, Macro0, CA PI delay=36
7641 11:45:53.456585
7642 11:45:53.459434 [CBTSetCACLKResult] CA Dly = 36
7643 11:45:53.462972 CS Dly: 12 (0~43)
7644 11:45:53.465910 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7645 11:45:53.469073 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7646 11:45:53.469160
7647 11:45:53.472492 ----->DramcWriteLeveling(PI) begin...
7648 11:45:53.476250 ==
7649 11:45:53.476361 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 11:45:53.482723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 11:45:53.482808 ==
7652 11:45:53.485737 Write leveling (Byte 0): 36 => 36
7653 11:45:53.489436 Write leveling (Byte 1): 28 => 28
7654 11:45:53.492391 DramcWriteLeveling(PI) end<-----
7655 11:45:53.492474
7656 11:45:53.492564 ==
7657 11:45:53.495437 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 11:45:53.499008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 11:45:53.499136 ==
7660 11:45:53.502060 [Gating] SW mode calibration
7661 11:45:53.508764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7662 11:45:53.515604 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7663 11:45:53.518567 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 11:45:53.521731 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 11:45:53.527929 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 11:45:53.531381 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7667 11:45:53.534878 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7668 11:45:53.541573 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7669 11:45:53.544821 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7670 11:45:53.548276 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7671 11:45:53.555022 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7672 11:45:53.557978 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 11:45:53.560992 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7674 11:45:53.567627 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7675 11:45:53.571113 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7676 11:45:53.574709 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7677 11:45:53.581204 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7678 11:45:53.584359 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 11:45:53.587833 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 11:45:53.594291 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 11:45:53.597349 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 11:45:53.600972 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7683 11:45:53.607497 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7684 11:45:53.610655 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7685 11:45:53.614222 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7686 11:45:53.621024 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 11:45:53.624392 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 11:45:53.627336 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 11:45:53.633625 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 11:45:53.637026 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7691 11:45:53.640737 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7692 11:45:53.647118 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7693 11:45:53.650661 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7694 11:45:53.653593 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 11:45:53.660011 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 11:45:53.663716 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 11:45:53.666787 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 11:45:53.673381 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 11:45:53.676686 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 11:45:53.679581 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 11:45:53.686191 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 11:45:53.689693 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 11:45:53.693009 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 11:45:53.699518 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 11:45:53.703087 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 11:45:53.706061 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7707 11:45:53.712732 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7708 11:45:53.716182 Total UI for P1: 0, mck2ui 16
7709 11:45:53.719733 best dqsien dly found for B0: ( 1, 9, 12)
7710 11:45:53.722569 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7711 11:45:53.725533 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7712 11:45:53.732485 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7713 11:45:53.732626 Total UI for P1: 0, mck2ui 16
7714 11:45:53.739321 best dqsien dly found for B1: ( 1, 9, 22)
7715 11:45:53.742366 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7716 11:45:53.745380 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7717 11:45:53.745471
7718 11:45:53.748823 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7719 11:45:53.752085 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7720 11:45:53.755472 [Gating] SW calibration Done
7721 11:45:53.755560 ==
7722 11:45:53.758992 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 11:45:53.762036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 11:45:53.762120 ==
7725 11:45:53.765286 RX Vref Scan: 0
7726 11:45:53.765372
7727 11:45:53.768454 RX Vref 0 -> 0, step: 1
7728 11:45:53.768562
7729 11:45:53.768629 RX Delay 0 -> 252, step: 8
7730 11:45:53.775145 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7731 11:45:53.778697 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7732 11:45:53.781958 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7733 11:45:53.785134 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7734 11:45:53.788796 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7735 11:45:53.794824 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
7736 11:45:53.798267 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7737 11:45:53.801876 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7738 11:45:53.804947 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7739 11:45:53.808032 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7740 11:45:53.815604 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7741 11:45:53.818574 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7742 11:45:53.821507 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7743 11:45:53.824963 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7744 11:45:53.831456 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7745 11:45:53.834993 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7746 11:45:53.835413 ==
7747 11:45:53.837941 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 11:45:53.841388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 11:45:53.841905 ==
7750 11:45:53.842318 DQS Delay:
7751 11:45:53.844754 DQS0 = 0, DQS1 = 0
7752 11:45:53.845249 DQM Delay:
7753 11:45:53.848498 DQM0 = 135, DQM1 = 127
7754 11:45:53.849087 DQ Delay:
7755 11:45:53.851432 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7756 11:45:53.854785 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7757 11:45:53.857919 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7758 11:45:53.864793 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7759 11:45:53.865233
7760 11:45:53.865671
7761 11:45:53.866101 ==
7762 11:45:53.867864 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 11:45:53.871387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 11:45:53.871963 ==
7765 11:45:53.872453
7766 11:45:53.872899
7767 11:45:53.874356 TX Vref Scan disable
7768 11:45:53.874773 == TX Byte 0 ==
7769 11:45:53.881517 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7770 11:45:53.884335 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7771 11:45:53.884841 == TX Byte 1 ==
7772 11:45:53.890893 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7773 11:45:53.894407 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7774 11:45:53.894896 ==
7775 11:45:53.897254 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 11:45:53.900764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 11:45:53.901213 ==
7778 11:45:53.916901
7779 11:45:53.920030 TX Vref early break, caculate TX vref
7780 11:45:53.923458 TX Vref=16, minBit 6, minWin=22, winSum=372
7781 11:45:53.926556 TX Vref=18, minBit 4, minWin=22, winSum=379
7782 11:45:53.929983 TX Vref=20, minBit 3, minWin=23, winSum=389
7783 11:45:53.932770 TX Vref=22, minBit 1, minWin=24, winSum=401
7784 11:45:53.936377 TX Vref=24, minBit 7, minWin=24, winSum=412
7785 11:45:53.942682 TX Vref=26, minBit 0, minWin=25, winSum=417
7786 11:45:53.946158 TX Vref=28, minBit 1, minWin=25, winSum=419
7787 11:45:53.949463 TX Vref=30, minBit 0, minWin=24, winSum=412
7788 11:45:53.952933 TX Vref=32, minBit 0, minWin=24, winSum=402
7789 11:45:53.956335 TX Vref=34, minBit 4, minWin=23, winSum=398
7790 11:45:53.959294 TX Vref=36, minBit 0, minWin=23, winSum=379
7791 11:45:53.966310 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
7792 11:45:53.966480
7793 11:45:53.969190 Final TX Range 0 Vref 28
7794 11:45:53.969300
7795 11:45:53.969398 ==
7796 11:45:53.972333 Dram Type= 6, Freq= 0, CH_0, rank 0
7797 11:45:53.976019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7798 11:45:53.976149 ==
7799 11:45:53.979198
7800 11:45:53.979327
7801 11:45:53.979449 TX Vref Scan disable
7802 11:45:53.985986 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7803 11:45:53.986143 == TX Byte 0 ==
7804 11:45:53.989030 u2DelayCellOfst[0]=14 cells (4 PI)
7805 11:45:53.992601 u2DelayCellOfst[1]=18 cells (5 PI)
7806 11:45:53.995706 u2DelayCellOfst[2]=14 cells (4 PI)
7807 11:45:53.998670 u2DelayCellOfst[3]=14 cells (4 PI)
7808 11:45:54.002168 u2DelayCellOfst[4]=11 cells (3 PI)
7809 11:45:54.005379 u2DelayCellOfst[5]=0 cells (0 PI)
7810 11:45:54.009087 u2DelayCellOfst[6]=22 cells (6 PI)
7811 11:45:54.011908 u2DelayCellOfst[7]=22 cells (6 PI)
7812 11:45:54.015660 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7813 11:45:54.018762 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7814 11:45:54.022279 == TX Byte 1 ==
7815 11:45:54.025502 u2DelayCellOfst[8]=0 cells (0 PI)
7816 11:45:54.028480 u2DelayCellOfst[9]=3 cells (1 PI)
7817 11:45:54.032087 u2DelayCellOfst[10]=7 cells (2 PI)
7818 11:45:54.035024 u2DelayCellOfst[11]=0 cells (0 PI)
7819 11:45:54.038819 u2DelayCellOfst[12]=11 cells (3 PI)
7820 11:45:54.041745 u2DelayCellOfst[13]=11 cells (3 PI)
7821 11:45:54.045262 u2DelayCellOfst[14]=14 cells (4 PI)
7822 11:45:54.045420 u2DelayCellOfst[15]=11 cells (3 PI)
7823 11:45:54.052003 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7824 11:45:54.055036 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7825 11:45:54.058694 DramC Write-DBI on
7826 11:45:54.059006 ==
7827 11:45:54.061820 Dram Type= 6, Freq= 0, CH_0, rank 0
7828 11:45:54.065438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7829 11:45:54.065897 ==
7830 11:45:54.066163
7831 11:45:54.066406
7832 11:45:54.068423 TX Vref Scan disable
7833 11:45:54.068800 == TX Byte 0 ==
7834 11:45:54.075114 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7835 11:45:54.075458 == TX Byte 1 ==
7836 11:45:54.078750 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7837 11:45:54.081736 DramC Write-DBI off
7838 11:45:54.082070
7839 11:45:54.082334 [DATLAT]
7840 11:45:54.084824 Freq=1600, CH0 RK0
7841 11:45:54.085152
7842 11:45:54.085412 DATLAT Default: 0xf
7843 11:45:54.088030 0, 0xFFFF, sum = 0
7844 11:45:54.091698 1, 0xFFFF, sum = 0
7845 11:45:54.092031 2, 0xFFFF, sum = 0
7846 11:45:54.094703 3, 0xFFFF, sum = 0
7847 11:45:54.095038 4, 0xFFFF, sum = 0
7848 11:45:54.098438 5, 0xFFFF, sum = 0
7849 11:45:54.098801 6, 0xFFFF, sum = 0
7850 11:45:54.101433 7, 0xFFFF, sum = 0
7851 11:45:54.101796 8, 0xFFFF, sum = 0
7852 11:45:54.105062 9, 0xFFFF, sum = 0
7853 11:45:54.105443 10, 0xFFFF, sum = 0
7854 11:45:54.108088 11, 0xFFFF, sum = 0
7855 11:45:54.108649 12, 0xFFFF, sum = 0
7856 11:45:54.111646 13, 0xFFFF, sum = 0
7857 11:45:54.112134 14, 0x0, sum = 1
7858 11:45:54.114518 15, 0x0, sum = 2
7859 11:45:54.115060 16, 0x0, sum = 3
7860 11:45:54.117844 17, 0x0, sum = 4
7861 11:45:54.118284 best_step = 15
7862 11:45:54.118632
7863 11:45:54.118963 ==
7864 11:45:54.121645 Dram Type= 6, Freq= 0, CH_0, rank 0
7865 11:45:54.127656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7866 11:45:54.128143 ==
7867 11:45:54.128820 RX Vref Scan: 1
7868 11:45:54.129242
7869 11:45:54.131366 Set Vref Range= 24 -> 127
7870 11:45:54.131846
7871 11:45:54.134395 RX Vref 24 -> 127, step: 1
7872 11:45:54.134795
7873 11:45:54.135165 RX Delay 19 -> 252, step: 4
7874 11:45:54.137483
7875 11:45:54.137943 Set Vref, RX VrefLevel [Byte0]: 24
7876 11:45:54.140699 [Byte1]: 24
7877 11:45:54.144947
7878 11:45:54.145091 Set Vref, RX VrefLevel [Byte0]: 25
7879 11:45:54.148065 [Byte1]: 25
7880 11:45:54.152927
7881 11:45:54.155959 Set Vref, RX VrefLevel [Byte0]: 26
7882 11:45:54.158865 [Byte1]: 26
7883 11:45:54.158983
7884 11:45:54.162408 Set Vref, RX VrefLevel [Byte0]: 27
7885 11:45:54.165425 [Byte1]: 27
7886 11:45:54.165523
7887 11:45:54.168937 Set Vref, RX VrefLevel [Byte0]: 28
7888 11:45:54.172232 [Byte1]: 28
7889 11:45:54.172350
7890 11:45:54.175822 Set Vref, RX VrefLevel [Byte0]: 29
7891 11:45:54.178791 [Byte1]: 29
7892 11:45:54.182608
7893 11:45:54.182694 Set Vref, RX VrefLevel [Byte0]: 30
7894 11:45:54.186418 [Byte1]: 30
7895 11:45:54.190770
7896 11:45:54.190859 Set Vref, RX VrefLevel [Byte0]: 31
7897 11:45:54.193845 [Byte1]: 31
7898 11:45:54.198032
7899 11:45:54.198152 Set Vref, RX VrefLevel [Byte0]: 32
7900 11:45:54.201614 [Byte1]: 32
7901 11:45:54.205927
7902 11:45:54.206024 Set Vref, RX VrefLevel [Byte0]: 33
7903 11:45:54.209030 [Byte1]: 33
7904 11:45:54.212993
7905 11:45:54.213089 Set Vref, RX VrefLevel [Byte0]: 34
7906 11:45:54.217062 [Byte1]: 34
7907 11:45:54.221115
7908 11:45:54.221546 Set Vref, RX VrefLevel [Byte0]: 35
7909 11:45:54.224055 [Byte1]: 35
7910 11:45:54.228360
7911 11:45:54.228920 Set Vref, RX VrefLevel [Byte0]: 36
7912 11:45:54.231854 [Byte1]: 36
7913 11:45:54.236154
7914 11:45:54.236765 Set Vref, RX VrefLevel [Byte0]: 37
7915 11:45:54.239201 [Byte1]: 37
7916 11:45:54.244044
7917 11:45:54.244668 Set Vref, RX VrefLevel [Byte0]: 38
7918 11:45:54.247061 [Byte1]: 38
7919 11:45:54.251251
7920 11:45:54.251682 Set Vref, RX VrefLevel [Byte0]: 39
7921 11:45:54.254881 [Byte1]: 39
7922 11:45:54.258757
7923 11:45:54.259188 Set Vref, RX VrefLevel [Byte0]: 40
7924 11:45:54.261749 [Byte1]: 40
7925 11:45:54.266434
7926 11:45:54.266689 Set Vref, RX VrefLevel [Byte0]: 41
7927 11:45:54.269417 [Byte1]: 41
7928 11:45:54.273450
7929 11:45:54.273617 Set Vref, RX VrefLevel [Byte0]: 42
7930 11:45:54.276845 [Byte1]: 42
7931 11:45:54.281524
7932 11:45:54.281650 Set Vref, RX VrefLevel [Byte0]: 43
7933 11:45:54.287627 [Byte1]: 43
7934 11:45:54.287750
7935 11:45:54.290759 Set Vref, RX VrefLevel [Byte0]: 44
7936 11:45:54.294481 [Byte1]: 44
7937 11:45:54.294565
7938 11:45:54.297481 Set Vref, RX VrefLevel [Byte0]: 45
7939 11:45:54.300930 [Byte1]: 45
7940 11:45:54.301036
7941 11:45:54.303930 Set Vref, RX VrefLevel [Byte0]: 46
7942 11:45:54.307686 [Byte1]: 46
7943 11:45:54.311357
7944 11:45:54.311451 Set Vref, RX VrefLevel [Byte0]: 47
7945 11:45:54.314867 [Byte1]: 47
7946 11:45:54.319188
7947 11:45:54.319311 Set Vref, RX VrefLevel [Byte0]: 48
7948 11:45:54.322316 [Byte1]: 48
7949 11:45:54.326928
7950 11:45:54.327050 Set Vref, RX VrefLevel [Byte0]: 49
7951 11:45:54.330037 [Byte1]: 49
7952 11:45:54.334280
7953 11:45:54.334381 Set Vref, RX VrefLevel [Byte0]: 50
7954 11:45:54.337367 [Byte1]: 50
7955 11:45:54.342151
7956 11:45:54.342226 Set Vref, RX VrefLevel [Byte0]: 51
7957 11:45:54.345143 [Byte1]: 51
7958 11:45:54.349479
7959 11:45:54.349586 Set Vref, RX VrefLevel [Byte0]: 52
7960 11:45:54.352499 [Byte1]: 52
7961 11:45:54.357352
7962 11:45:54.357430 Set Vref, RX VrefLevel [Byte0]: 53
7963 11:45:54.360063 [Byte1]: 53
7964 11:45:54.364800
7965 11:45:54.364886 Set Vref, RX VrefLevel [Byte0]: 54
7966 11:45:54.367774 [Byte1]: 54
7967 11:45:54.372011
7968 11:45:54.372087 Set Vref, RX VrefLevel [Byte0]: 55
7969 11:45:54.375725 [Byte1]: 55
7970 11:45:54.379771
7971 11:45:54.379848 Set Vref, RX VrefLevel [Byte0]: 56
7972 11:45:54.386376 [Byte1]: 56
7973 11:45:54.386462
7974 11:45:54.389377 Set Vref, RX VrefLevel [Byte0]: 57
7975 11:45:54.392947 [Byte1]: 57
7976 11:45:54.393024
7977 11:45:54.396067 Set Vref, RX VrefLevel [Byte0]: 58
7978 11:45:54.399232 [Byte1]: 58
7979 11:45:54.399318
7980 11:45:54.402811 Set Vref, RX VrefLevel [Byte0]: 59
7981 11:45:54.405750 [Byte1]: 59
7982 11:45:54.410050
7983 11:45:54.410144 Set Vref, RX VrefLevel [Byte0]: 60
7984 11:45:54.413135 [Byte1]: 60
7985 11:45:54.417388
7986 11:45:54.417474 Set Vref, RX VrefLevel [Byte0]: 61
7987 11:45:54.421037 [Byte1]: 61
7988 11:45:54.425152
7989 11:45:54.425250 Set Vref, RX VrefLevel [Byte0]: 62
7990 11:45:54.428278 [Byte1]: 62
7991 11:45:54.432858
7992 11:45:54.432979 Set Vref, RX VrefLevel [Byte0]: 63
7993 11:45:54.435990 [Byte1]: 63
7994 11:45:54.440313
7995 11:45:54.440403 Set Vref, RX VrefLevel [Byte0]: 64
7996 11:45:54.443409 [Byte1]: 64
7997 11:45:54.447636
7998 11:45:54.447721 Set Vref, RX VrefLevel [Byte0]: 65
7999 11:45:54.451414 [Byte1]: 65
8000 11:45:54.455523
8001 11:45:54.455607 Set Vref, RX VrefLevel [Byte0]: 66
8002 11:45:54.458506 [Byte1]: 66
8003 11:45:54.463237
8004 11:45:54.463326 Set Vref, RX VrefLevel [Byte0]: 67
8005 11:45:54.466220 [Byte1]: 67
8006 11:45:54.470476
8007 11:45:54.470562 Set Vref, RX VrefLevel [Byte0]: 68
8008 11:45:54.473670 [Byte1]: 68
8009 11:45:54.477966
8010 11:45:54.478056 Set Vref, RX VrefLevel [Byte0]: 69
8011 11:45:54.481549 [Byte1]: 69
8012 11:45:54.485552
8013 11:45:54.485643 Set Vref, RX VrefLevel [Byte0]: 70
8014 11:45:54.489091 [Byte1]: 70
8015 11:45:54.493406
8016 11:45:54.493489 Set Vref, RX VrefLevel [Byte0]: 71
8017 11:45:54.496367 [Byte1]: 71
8018 11:45:54.501252
8019 11:45:54.501338 Set Vref, RX VrefLevel [Byte0]: 72
8020 11:45:54.504052 [Byte1]: 72
8021 11:45:54.508584
8022 11:45:54.508711 Set Vref, RX VrefLevel [Byte0]: 73
8023 11:45:54.511589 [Byte1]: 73
8024 11:45:54.515948
8025 11:45:54.516037 Set Vref, RX VrefLevel [Byte0]: 74
8026 11:45:54.519148 [Byte1]: 74
8027 11:45:54.523385
8028 11:45:54.523472 Set Vref, RX VrefLevel [Byte0]: 75
8029 11:45:54.526866 [Byte1]: 75
8030 11:45:54.531212
8031 11:45:54.531304 Set Vref, RX VrefLevel [Byte0]: 76
8032 11:45:54.534722 [Byte1]: 76
8033 11:45:54.538932
8034 11:45:54.539026 Set Vref, RX VrefLevel [Byte0]: 77
8035 11:45:54.542050 [Byte1]: 77
8036 11:45:54.546318
8037 11:45:54.546430 Set Vref, RX VrefLevel [Byte0]: 78
8038 11:45:54.549344 [Byte1]: 78
8039 11:45:54.553673
8040 11:45:54.553760 Final RX Vref Byte 0 = 67 to rank0
8041 11:45:54.557163 Final RX Vref Byte 1 = 58 to rank0
8042 11:45:54.560833 Final RX Vref Byte 0 = 67 to rank1
8043 11:45:54.563738 Final RX Vref Byte 1 = 58 to rank1==
8044 11:45:54.566721 Dram Type= 6, Freq= 0, CH_0, rank 0
8045 11:45:54.573924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 11:45:54.574044 ==
8047 11:45:54.574115 DQS Delay:
8048 11:45:54.576934 DQS0 = 0, DQS1 = 0
8049 11:45:54.577009 DQM Delay:
8050 11:45:54.577073 DQM0 = 133, DQM1 = 123
8051 11:45:54.580098 DQ Delay:
8052 11:45:54.583713 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8053 11:45:54.586694 DQ4 =134, DQ5 =122, DQ6 =142, DQ7 =142
8054 11:45:54.590262 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8055 11:45:54.593052 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8056 11:45:54.593143
8057 11:45:54.593218
8058 11:45:54.593282
8059 11:45:54.596749 [DramC_TX_OE_Calibration] TA2
8060 11:45:54.599724 Original DQ_B0 (3 6) =30, OEN = 27
8061 11:45:54.603440 Original DQ_B1 (3 6) =30, OEN = 27
8062 11:45:54.606505 24, 0x0, End_B0=24 End_B1=24
8063 11:45:54.610248 25, 0x0, End_B0=25 End_B1=25
8064 11:45:54.610355 26, 0x0, End_B0=26 End_B1=26
8065 11:45:54.613432 27, 0x0, End_B0=27 End_B1=27
8066 11:45:54.616743 28, 0x0, End_B0=28 End_B1=28
8067 11:45:54.619724 29, 0x0, End_B0=29 End_B1=29
8068 11:45:54.619808 30, 0x0, End_B0=30 End_B1=30
8069 11:45:54.623504 31, 0x4141, End_B0=30 End_B1=30
8070 11:45:54.626719 Byte0 end_step=30 best_step=27
8071 11:45:54.630472 Byte1 end_step=30 best_step=27
8072 11:45:54.633407 Byte0 TX OE(2T, 0.5T) = (3, 3)
8073 11:45:54.636337 Byte1 TX OE(2T, 0.5T) = (3, 3)
8074 11:45:54.636750
8075 11:45:54.636998
8076 11:45:54.642913 [DQSOSCAuto] RK0, (LSB)MR18= 0x2012, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8077 11:45:54.646676 CH0 RK0: MR19=303, MR18=2012
8078 11:45:54.652924 CH0_RK0: MR19=0x303, MR18=0x2012, DQSOSC=393, MR23=63, INC=23, DEC=15
8079 11:45:54.653503
8080 11:45:54.656346 ----->DramcWriteLeveling(PI) begin...
8081 11:45:54.656920 ==
8082 11:45:54.659488 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 11:45:54.663132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 11:45:54.663575 ==
8085 11:45:54.666246 Write leveling (Byte 0): 35 => 35
8086 11:45:54.669742 Write leveling (Byte 1): 29 => 29
8087 11:45:54.673255 DramcWriteLeveling(PI) end<-----
8088 11:45:54.673696
8089 11:45:54.674106 ==
8090 11:45:54.676486 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 11:45:54.679561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 11:45:54.682520 ==
8093 11:45:54.682828 [Gating] SW mode calibration
8094 11:45:54.692479 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8095 11:45:54.695756 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8096 11:45:54.698781 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 11:45:54.705827 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 11:45:54.708904 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 11:45:54.712114 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8100 11:45:54.718548 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8101 11:45:54.722089 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8102 11:45:54.725328 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 11:45:54.731623 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 11:45:54.735371 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 11:45:54.738693 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 11:45:54.745481 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8107 11:45:54.748545 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8108 11:45:54.751773 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8109 11:45:54.758139 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8110 11:45:54.761328 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 11:45:54.764971 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 11:45:54.771147 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 11:45:54.774981 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 11:45:54.778017 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 11:45:54.784828 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8116 11:45:54.787941 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8117 11:45:54.791503 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8118 11:45:54.798046 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 11:45:54.801157 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 11:45:54.804237 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 11:45:54.811222 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 11:45:54.814598 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8123 11:45:54.817700 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8124 11:45:54.824545 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8125 11:45:54.827903 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 11:45:54.830960 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 11:45:54.837793 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 11:45:54.840983 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 11:45:54.844209 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 11:45:54.850647 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 11:45:54.853897 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 11:45:54.857042 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 11:45:54.864153 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 11:45:54.867324 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 11:45:54.870477 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 11:45:54.877398 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 11:45:54.880466 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 11:45:54.883517 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 11:45:54.890472 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8140 11:45:54.893620 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8141 11:45:54.897135 Total UI for P1: 0, mck2ui 16
8142 11:45:54.900255 best dqsien dly found for B0: ( 1, 9, 12)
8143 11:45:54.903720 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 11:45:54.906581 Total UI for P1: 0, mck2ui 16
8145 11:45:54.910461 best dqsien dly found for B1: ( 1, 9, 16)
8146 11:45:54.913497 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8147 11:45:54.916695 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8148 11:45:54.916774
8149 11:45:54.923644 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8150 11:45:54.926818 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8151 11:45:54.929826 [Gating] SW calibration Done
8152 11:45:54.929917 ==
8153 11:45:54.933038 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 11:45:54.936734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 11:45:54.936829 ==
8156 11:45:54.936897 RX Vref Scan: 0
8157 11:45:54.939778
8158 11:45:54.939862 RX Vref 0 -> 0, step: 1
8159 11:45:54.939934
8160 11:45:54.942961 RX Delay 0 -> 252, step: 8
8161 11:45:54.946061 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8162 11:45:54.950041 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8163 11:45:54.956272 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8164 11:45:54.959562 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8165 11:45:54.962710 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8166 11:45:54.966415 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8167 11:45:54.969465 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8168 11:45:54.976214 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8169 11:45:54.979870 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8170 11:45:54.983010 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8171 11:45:54.986669 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8172 11:45:54.989530 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8173 11:45:54.996189 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8174 11:45:54.999491 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8175 11:45:55.002504 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8176 11:45:55.006286 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8177 11:45:55.009248 ==
8178 11:45:55.009675 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 11:45:55.015533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 11:45:55.016117 ==
8181 11:45:55.016688 DQS Delay:
8182 11:45:55.019523 DQS0 = 0, DQS1 = 0
8183 11:45:55.019912 DQM Delay:
8184 11:45:55.022570 DQM0 = 133, DQM1 = 128
8185 11:45:55.023131 DQ Delay:
8186 11:45:55.025694 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8187 11:45:55.028932 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8188 11:45:55.032084 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8189 11:45:55.035837 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8190 11:45:55.036394
8191 11:45:55.036961
8192 11:45:55.037344 ==
8193 11:45:55.039033 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 11:45:55.045707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 11:45:55.046316 ==
8196 11:45:55.046685
8197 11:45:55.046999
8198 11:45:55.047299 TX Vref Scan disable
8199 11:45:55.049343 == TX Byte 0 ==
8200 11:45:55.052604 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8201 11:45:55.059204 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8202 11:45:55.059625 == TX Byte 1 ==
8203 11:45:55.062525 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8204 11:45:55.069512 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8205 11:45:55.069939 ==
8206 11:45:55.072486 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 11:45:55.075831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 11:45:55.076238 ==
8209 11:45:55.088766
8210 11:45:55.092106 TX Vref early break, caculate TX vref
8211 11:45:55.095099 TX Vref=16, minBit 3, minWin=22, winSum=377
8212 11:45:55.098925 TX Vref=18, minBit 1, minWin=22, winSum=389
8213 11:45:55.101755 TX Vref=20, minBit 0, minWin=24, winSum=400
8214 11:45:55.105344 TX Vref=22, minBit 1, minWin=24, winSum=405
8215 11:45:55.108258 TX Vref=24, minBit 1, minWin=24, winSum=412
8216 11:45:55.115222 TX Vref=26, minBit 1, minWin=24, winSum=418
8217 11:45:55.118002 TX Vref=28, minBit 1, minWin=24, winSum=417
8218 11:45:55.121495 TX Vref=30, minBit 0, minWin=24, winSum=408
8219 11:45:55.124565 TX Vref=32, minBit 0, minWin=24, winSum=399
8220 11:45:55.127859 TX Vref=34, minBit 1, minWin=23, winSum=391
8221 11:45:55.134309 [TxChooseVref] Worse bit 1, Min win 24, Win sum 418, Final Vref 26
8222 11:45:55.134465
8223 11:45:55.138254 Final TX Range 0 Vref 26
8224 11:45:55.138371
8225 11:45:55.138462 ==
8226 11:45:55.141492 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 11:45:55.144452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 11:45:55.144568 ==
8229 11:45:55.144652
8230 11:45:55.144729
8231 11:45:55.147859 TX Vref Scan disable
8232 11:45:55.154364 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8233 11:45:55.154473 == TX Byte 0 ==
8234 11:45:55.157961 u2DelayCellOfst[0]=14 cells (4 PI)
8235 11:45:55.161180 u2DelayCellOfst[1]=18 cells (5 PI)
8236 11:45:55.164488 u2DelayCellOfst[2]=14 cells (4 PI)
8237 11:45:55.167719 u2DelayCellOfst[3]=14 cells (4 PI)
8238 11:45:55.170838 u2DelayCellOfst[4]=11 cells (3 PI)
8239 11:45:55.174145 u2DelayCellOfst[5]=0 cells (0 PI)
8240 11:45:55.177927 u2DelayCellOfst[6]=18 cells (5 PI)
8241 11:45:55.181157 u2DelayCellOfst[7]=22 cells (6 PI)
8242 11:45:55.184265 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8243 11:45:55.188001 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8244 11:45:55.191156 == TX Byte 1 ==
8245 11:45:55.194275 u2DelayCellOfst[8]=0 cells (0 PI)
8246 11:45:55.197268 u2DelayCellOfst[9]=3 cells (1 PI)
8247 11:45:55.197432 u2DelayCellOfst[10]=7 cells (2 PI)
8248 11:45:55.200994 u2DelayCellOfst[11]=3 cells (1 PI)
8249 11:45:55.204175 u2DelayCellOfst[12]=14 cells (4 PI)
8250 11:45:55.207279 u2DelayCellOfst[13]=14 cells (4 PI)
8251 11:45:55.210476 u2DelayCellOfst[14]=18 cells (5 PI)
8252 11:45:55.214231 u2DelayCellOfst[15]=11 cells (3 PI)
8253 11:45:55.220482 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8254 11:45:55.223954 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8255 11:45:55.224132 DramC Write-DBI on
8256 11:45:55.224272 ==
8257 11:45:55.226922 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 11:45:55.233620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 11:45:55.233875 ==
8260 11:45:55.234073
8261 11:45:55.234254
8262 11:45:55.236987 TX Vref Scan disable
8263 11:45:55.237290 == TX Byte 0 ==
8264 11:45:55.243792 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8265 11:45:55.244194 == TX Byte 1 ==
8266 11:45:55.246839 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8267 11:45:55.250089 DramC Write-DBI off
8268 11:45:55.250518
8269 11:45:55.250855 [DATLAT]
8270 11:45:55.253426 Freq=1600, CH0 RK1
8271 11:45:55.253829
8272 11:45:55.254160 DATLAT Default: 0xf
8273 11:45:55.256614 0, 0xFFFF, sum = 0
8274 11:45:55.256990 1, 0xFFFF, sum = 0
8275 11:45:55.260118 2, 0xFFFF, sum = 0
8276 11:45:55.260587 3, 0xFFFF, sum = 0
8277 11:45:55.263770 4, 0xFFFF, sum = 0
8278 11:45:55.264216 5, 0xFFFF, sum = 0
8279 11:45:55.266974 6, 0xFFFF, sum = 0
8280 11:45:55.267404 7, 0xFFFF, sum = 0
8281 11:45:55.270152 8, 0xFFFF, sum = 0
8282 11:45:55.273446 9, 0xFFFF, sum = 0
8283 11:45:55.273961 10, 0xFFFF, sum = 0
8284 11:45:55.276447 11, 0xFFFF, sum = 0
8285 11:45:55.276993 12, 0xFFFF, sum = 0
8286 11:45:55.279802 13, 0xFFFF, sum = 0
8287 11:45:55.280302 14, 0x0, sum = 1
8288 11:45:55.283544 15, 0x0, sum = 2
8289 11:45:55.284046 16, 0x0, sum = 3
8290 11:45:55.286798 17, 0x0, sum = 4
8291 11:45:55.287219 best_step = 15
8292 11:45:55.287557
8293 11:45:55.287868 ==
8294 11:45:55.289943 Dram Type= 6, Freq= 0, CH_0, rank 1
8295 11:45:55.293008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 11:45:55.296715 ==
8297 11:45:55.297141 RX Vref Scan: 0
8298 11:45:55.297481
8299 11:45:55.299820 RX Vref 0 -> 0, step: 1
8300 11:45:55.300248
8301 11:45:55.300629 RX Delay 11 -> 252, step: 4
8302 11:45:55.307323 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8303 11:45:55.310510 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8304 11:45:55.313619 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8305 11:45:55.316612 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8306 11:45:55.322942 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8307 11:45:55.326618 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8308 11:45:55.330075 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8309 11:45:55.333152 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8310 11:45:55.336437 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8311 11:45:55.342581 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8312 11:45:55.346201 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8313 11:45:55.349260 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8314 11:45:55.352388 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8315 11:45:55.359227 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8316 11:45:55.362346 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8317 11:45:55.365984 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8318 11:45:55.366164 ==
8319 11:45:55.369002 Dram Type= 6, Freq= 0, CH_0, rank 1
8320 11:45:55.372284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 11:45:55.372364 ==
8322 11:45:55.376201 DQS Delay:
8323 11:45:55.376300 DQS0 = 0, DQS1 = 0
8324 11:45:55.379342 DQM Delay:
8325 11:45:55.379449 DQM0 = 129, DQM1 = 125
8326 11:45:55.379543 DQ Delay:
8327 11:45:55.382474 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =128
8328 11:45:55.389486 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =140
8329 11:45:55.392667 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8330 11:45:55.395749 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8331 11:45:55.395848
8332 11:45:55.395918
8333 11:45:55.395982
8334 11:45:55.398835 [DramC_TX_OE_Calibration] TA2
8335 11:45:55.402702 Original DQ_B0 (3 6) =30, OEN = 27
8336 11:45:55.405682 Original DQ_B1 (3 6) =30, OEN = 27
8337 11:45:55.405765 24, 0x0, End_B0=24 End_B1=24
8338 11:45:55.409150 25, 0x0, End_B0=25 End_B1=25
8339 11:45:55.412242 26, 0x0, End_B0=26 End_B1=26
8340 11:45:55.415445 27, 0x0, End_B0=27 End_B1=27
8341 11:45:55.418668 28, 0x0, End_B0=28 End_B1=28
8342 11:45:55.418754 29, 0x0, End_B0=29 End_B1=29
8343 11:45:55.421764 30, 0x0, End_B0=30 End_B1=30
8344 11:45:55.425570 31, 0x4141, End_B0=30 End_B1=30
8345 11:45:55.428799 Byte0 end_step=30 best_step=27
8346 11:45:55.431848 Byte1 end_step=30 best_step=27
8347 11:45:55.435390 Byte0 TX OE(2T, 0.5T) = (3, 3)
8348 11:45:55.435516 Byte1 TX OE(2T, 0.5T) = (3, 3)
8349 11:45:55.435613
8350 11:45:55.435722
8351 11:45:55.445280 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8352 11:45:55.448355 CH0 RK1: MR19=303, MR18=1E01
8353 11:45:55.455320 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8354 11:45:55.455429 [RxdqsGatingPostProcess] freq 1600
8355 11:45:55.461420 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8356 11:45:55.465092 best DQS0 dly(2T, 0.5T) = (1, 1)
8357 11:45:55.468090 best DQS1 dly(2T, 0.5T) = (1, 1)
8358 11:45:55.471263 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8359 11:45:55.475063 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8360 11:45:55.478189 best DQS0 dly(2T, 0.5T) = (1, 1)
8361 11:45:55.481372 best DQS1 dly(2T, 0.5T) = (1, 1)
8362 11:45:55.484575 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8363 11:45:55.487797 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8364 11:45:55.491692 Pre-setting of DQS Precalculation
8365 11:45:55.494899 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8366 11:45:55.494999 ==
8367 11:45:55.497956 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 11:45:55.501247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 11:45:55.501399 ==
8370 11:45:55.507554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8371 11:45:55.511328 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8372 11:45:55.517360 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8373 11:45:55.520673 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8374 11:45:55.531344 [CA 0] Center 42 (13~72) winsize 60
8375 11:45:55.534554 [CA 1] Center 42 (13~72) winsize 60
8376 11:45:55.538064 [CA 2] Center 38 (9~67) winsize 59
8377 11:45:55.541110 [CA 3] Center 36 (7~66) winsize 60
8378 11:45:55.544274 [CA 4] Center 37 (8~67) winsize 60
8379 11:45:55.547343 [CA 5] Center 37 (8~67) winsize 60
8380 11:45:55.547451
8381 11:45:55.551221 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8382 11:45:55.551321
8383 11:45:55.554276 [CATrainingPosCal] consider 1 rank data
8384 11:45:55.557284 u2DelayCellTimex100 = 262/100 ps
8385 11:45:55.561008 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8386 11:45:55.567651 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8387 11:45:55.570804 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8388 11:45:55.573963 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8389 11:45:55.577725 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8390 11:45:55.580948 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8391 11:45:55.581057
8392 11:45:55.583974 CA PerBit enable=1, Macro0, CA PI delay=36
8393 11:45:55.584076
8394 11:45:55.587338 [CBTSetCACLKResult] CA Dly = 36
8395 11:45:55.590568 CS Dly: 9 (0~40)
8396 11:45:55.593806 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8397 11:45:55.597532 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8398 11:45:55.597615 ==
8399 11:45:55.600764 Dram Type= 6, Freq= 0, CH_1, rank 1
8400 11:45:55.606920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 11:45:55.607042 ==
8402 11:45:55.610669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8403 11:45:55.613665 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8404 11:45:55.620225 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8405 11:45:55.626584 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8406 11:45:55.633918 [CA 0] Center 42 (13~71) winsize 59
8407 11:45:55.637684 [CA 1] Center 42 (13~72) winsize 60
8408 11:45:55.640831 [CA 2] Center 37 (8~67) winsize 60
8409 11:45:55.643823 [CA 3] Center 37 (8~66) winsize 59
8410 11:45:55.647576 [CA 4] Center 37 (8~67) winsize 60
8411 11:45:55.650781 [CA 5] Center 36 (7~66) winsize 60
8412 11:45:55.650886
8413 11:45:55.653946 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8414 11:45:55.654071
8415 11:45:55.660787 [CATrainingPosCal] consider 2 rank data
8416 11:45:55.660909 u2DelayCellTimex100 = 262/100 ps
8417 11:45:55.667420 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8418 11:45:55.670570 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8419 11:45:55.673925 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8420 11:45:55.677007 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8421 11:45:55.680154 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8422 11:45:55.683412 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8423 11:45:55.683498
8424 11:45:55.687093 CA PerBit enable=1, Macro0, CA PI delay=37
8425 11:45:55.687186
8426 11:45:55.690179 [CBTSetCACLKResult] CA Dly = 37
8427 11:45:55.693448 CS Dly: 10 (0~43)
8428 11:45:55.696701 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8429 11:45:55.699919 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8430 11:45:55.700021
8431 11:45:55.703052 ----->DramcWriteLeveling(PI) begin...
8432 11:45:55.706305 ==
8433 11:45:55.706383 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 11:45:55.713026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 11:45:55.713152 ==
8436 11:45:55.716072 Write leveling (Byte 0): 24 => 24
8437 11:45:55.719667 Write leveling (Byte 1): 27 => 27
8438 11:45:55.722796 DramcWriteLeveling(PI) end<-----
8439 11:45:55.722903
8440 11:45:55.722998 ==
8441 11:45:55.725876 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 11:45:55.729643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 11:45:55.729750 ==
8444 11:45:55.732759 [Gating] SW mode calibration
8445 11:45:55.739462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8446 11:45:55.745682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8447 11:45:55.749446 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 11:45:55.752435 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 11:45:55.758798 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 11:45:55.762409 1 4 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8451 11:45:55.765492 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 11:45:55.772302 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 11:45:55.775457 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 11:45:55.779130 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 11:45:55.785554 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 11:45:55.788732 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 11:45:55.791949 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8458 11:45:55.798896 1 5 12 | B1->B0 | 2f2f 2424 | 0 0 | (1 0) (1 0)
8459 11:45:55.802032 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8460 11:45:55.805158 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 11:45:55.812193 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 11:45:55.815269 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 11:45:55.818379 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 11:45:55.825168 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 11:45:55.828724 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8466 11:45:55.831923 1 6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8467 11:45:55.838081 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 11:45:55.841365 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 11:45:55.845130 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 11:45:55.851215 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 11:45:55.854837 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 11:45:55.858084 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 11:45:55.864448 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 11:45:55.868293 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8475 11:45:55.871492 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 11:45:55.878003 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 11:45:55.881084 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 11:45:55.884962 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 11:45:55.891027 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 11:45:55.894948 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 11:45:55.897580 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 11:45:55.904773 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 11:45:55.907850 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 11:45:55.911083 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 11:45:55.917395 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 11:45:55.921069 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 11:45:55.924109 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 11:45:55.930891 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 11:45:55.934017 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8490 11:45:55.937233 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8491 11:45:55.944052 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8492 11:45:55.944143 Total UI for P1: 0, mck2ui 16
8493 11:45:55.947268 best dqsien dly found for B0: ( 1, 9, 10)
8494 11:45:55.954059 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 11:45:55.957007 Total UI for P1: 0, mck2ui 16
8496 11:45:55.960611 best dqsien dly found for B1: ( 1, 9, 12)
8497 11:45:55.963625 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8498 11:45:55.966811 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8499 11:45:55.966917
8500 11:45:55.970040 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8501 11:45:55.973317 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8502 11:45:55.976927 [Gating] SW calibration Done
8503 11:45:55.977029 ==
8504 11:45:55.980467 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 11:45:55.983547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 11:45:55.986771 ==
8507 11:45:55.986882 RX Vref Scan: 0
8508 11:45:55.986978
8509 11:45:55.989924 RX Vref 0 -> 0, step: 1
8510 11:45:55.990026
8511 11:45:55.990118 RX Delay 0 -> 252, step: 8
8512 11:45:55.996372 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8513 11:45:55.999704 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8514 11:45:56.003638 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8515 11:45:56.006766 iDelay=208, Bit 3, Center 135 (88 ~ 183) 96
8516 11:45:56.009864 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8517 11:45:56.016797 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8518 11:45:56.019848 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8519 11:45:56.022958 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8520 11:45:56.026533 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8521 11:45:56.030006 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8522 11:45:56.036766 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8523 11:45:56.039789 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8524 11:45:56.042931 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8525 11:45:56.046198 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8526 11:45:56.053082 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8527 11:45:56.056229 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8528 11:45:56.056451 ==
8529 11:45:56.059724 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 11:45:56.062966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 11:45:56.063232 ==
8532 11:45:56.066354 DQS Delay:
8533 11:45:56.066438 DQS0 = 0, DQS1 = 0
8534 11:45:56.066522 DQM Delay:
8535 11:45:56.069667 DQM0 = 137, DQM1 = 129
8536 11:45:56.069767 DQ Delay:
8537 11:45:56.072878 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8538 11:45:56.076158 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8539 11:45:56.079781 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8540 11:45:56.085878 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8541 11:45:56.085982
8542 11:45:56.086052
8543 11:45:56.086113 ==
8544 11:45:56.089595 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 11:45:56.092855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 11:45:56.092933 ==
8547 11:45:56.092998
8548 11:45:56.093057
8549 11:45:56.096014 TX Vref Scan disable
8550 11:45:56.096095 == TX Byte 0 ==
8551 11:45:56.102360 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8552 11:45:56.106130 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8553 11:45:56.106227 == TX Byte 1 ==
8554 11:45:56.112415 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8555 11:45:56.115604 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8556 11:45:56.115708 ==
8557 11:45:56.118756 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 11:45:56.122566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 11:45:56.122701 ==
8560 11:45:56.136133
8561 11:45:56.139282 TX Vref early break, caculate TX vref
8562 11:45:56.142931 TX Vref=16, minBit 0, minWin=22, winSum=379
8563 11:45:56.145904 TX Vref=18, minBit 0, minWin=22, winSum=382
8564 11:45:56.149548 TX Vref=20, minBit 0, minWin=24, winSum=396
8565 11:45:56.152711 TX Vref=22, minBit 0, minWin=24, winSum=404
8566 11:45:56.155691 TX Vref=24, minBit 0, minWin=25, winSum=414
8567 11:45:56.162529 TX Vref=26, minBit 0, minWin=24, winSum=415
8568 11:45:56.165551 TX Vref=28, minBit 0, minWin=25, winSum=421
8569 11:45:56.169193 TX Vref=30, minBit 0, minWin=24, winSum=412
8570 11:45:56.172394 TX Vref=32, minBit 0, minWin=23, winSum=401
8571 11:45:56.175561 TX Vref=34, minBit 0, minWin=23, winSum=395
8572 11:45:56.182565 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8573 11:45:56.182651
8574 11:45:56.185382 Final TX Range 0 Vref 28
8575 11:45:56.185467
8576 11:45:56.185533 ==
8577 11:45:56.189101 Dram Type= 6, Freq= 0, CH_1, rank 0
8578 11:45:56.192073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 11:45:56.192157 ==
8580 11:45:56.192223
8581 11:45:56.192284
8582 11:45:56.195501 TX Vref Scan disable
8583 11:45:56.201719 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8584 11:45:56.201809 == TX Byte 0 ==
8585 11:45:56.205488 u2DelayCellOfst[0]=18 cells (5 PI)
8586 11:45:56.208526 u2DelayCellOfst[1]=11 cells (3 PI)
8587 11:45:56.211707 u2DelayCellOfst[2]=0 cells (0 PI)
8588 11:45:56.214896 u2DelayCellOfst[3]=3 cells (1 PI)
8589 11:45:56.218804 u2DelayCellOfst[4]=7 cells (2 PI)
8590 11:45:56.221997 u2DelayCellOfst[5]=22 cells (6 PI)
8591 11:45:56.225191 u2DelayCellOfst[6]=18 cells (5 PI)
8592 11:45:56.228335 u2DelayCellOfst[7]=3 cells (1 PI)
8593 11:45:56.231526 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8594 11:45:56.234701 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8595 11:45:56.238406 == TX Byte 1 ==
8596 11:45:56.241495 u2DelayCellOfst[8]=0 cells (0 PI)
8597 11:45:56.244550 u2DelayCellOfst[9]=3 cells (1 PI)
8598 11:45:56.248365 u2DelayCellOfst[10]=11 cells (3 PI)
8599 11:45:56.248481 u2DelayCellOfst[11]=7 cells (2 PI)
8600 11:45:56.251222 u2DelayCellOfst[12]=14 cells (4 PI)
8601 11:45:56.254984 u2DelayCellOfst[13]=18 cells (5 PI)
8602 11:45:56.258155 u2DelayCellOfst[14]=22 cells (6 PI)
8603 11:45:56.261361 u2DelayCellOfst[15]=22 cells (6 PI)
8604 11:45:56.267444 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8605 11:45:56.271126 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8606 11:45:56.274198 DramC Write-DBI on
8607 11:45:56.274365 ==
8608 11:45:56.277353 Dram Type= 6, Freq= 0, CH_1, rank 0
8609 11:45:56.281100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8610 11:45:56.281176 ==
8611 11:45:56.281240
8612 11:45:56.281313
8613 11:45:56.284014 TX Vref Scan disable
8614 11:45:56.284086 == TX Byte 0 ==
8615 11:45:56.290579 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8616 11:45:56.290666 == TX Byte 1 ==
8617 11:45:56.294200 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8618 11:45:56.297355 DramC Write-DBI off
8619 11:45:56.297429
8620 11:45:56.297492 [DATLAT]
8621 11:45:56.300596 Freq=1600, CH1 RK0
8622 11:45:56.300669
8623 11:45:56.300730 DATLAT Default: 0xf
8624 11:45:56.304318 0, 0xFFFF, sum = 0
8625 11:45:56.304392 1, 0xFFFF, sum = 0
8626 11:45:56.307419 2, 0xFFFF, sum = 0
8627 11:45:56.307536 3, 0xFFFF, sum = 0
8628 11:45:56.310726 4, 0xFFFF, sum = 0
8629 11:45:56.313829 5, 0xFFFF, sum = 0
8630 11:45:56.313922 6, 0xFFFF, sum = 0
8631 11:45:56.317238 7, 0xFFFF, sum = 0
8632 11:45:56.317336 8, 0xFFFF, sum = 0
8633 11:45:56.320364 9, 0xFFFF, sum = 0
8634 11:45:56.320453 10, 0xFFFF, sum = 0
8635 11:45:56.323586 11, 0xFFFF, sum = 0
8636 11:45:56.323693 12, 0xFFFF, sum = 0
8637 11:45:56.327412 13, 0xFFFF, sum = 0
8638 11:45:56.327528 14, 0x0, sum = 1
8639 11:45:56.330521 15, 0x0, sum = 2
8640 11:45:56.330642 16, 0x0, sum = 3
8641 11:45:56.333558 17, 0x0, sum = 4
8642 11:45:56.333721 best_step = 15
8643 11:45:56.333890
8644 11:45:56.334019 ==
8645 11:45:56.337394 Dram Type= 6, Freq= 0, CH_1, rank 0
8646 11:45:56.340575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8647 11:45:56.343505 ==
8648 11:45:56.343662 RX Vref Scan: 1
8649 11:45:56.343810
8650 11:45:56.347298 Set Vref Range= 24 -> 127
8651 11:45:56.347480
8652 11:45:56.350444 RX Vref 24 -> 127, step: 1
8653 11:45:56.350686
8654 11:45:56.350936 RX Delay 11 -> 252, step: 4
8655 11:45:56.351170
8656 11:45:56.353456 Set Vref, RX VrefLevel [Byte0]: 24
8657 11:45:56.357024 [Byte1]: 24
8658 11:45:56.360685
8659 11:45:56.361014 Set Vref, RX VrefLevel [Byte0]: 25
8660 11:45:56.364595 [Byte1]: 25
8661 11:45:56.368954
8662 11:45:56.369492 Set Vref, RX VrefLevel [Byte0]: 26
8663 11:45:56.371923 [Byte1]: 26
8664 11:45:56.376225
8665 11:45:56.376726 Set Vref, RX VrefLevel [Byte0]: 27
8666 11:45:56.379628 [Byte1]: 27
8667 11:45:56.383906
8668 11:45:56.384438 Set Vref, RX VrefLevel [Byte0]: 28
8669 11:45:56.387039 [Byte1]: 28
8670 11:45:56.391538
8671 11:45:56.392034 Set Vref, RX VrefLevel [Byte0]: 29
8672 11:45:56.394729 [Byte1]: 29
8673 11:45:56.398864
8674 11:45:56.399464 Set Vref, RX VrefLevel [Byte0]: 30
8675 11:45:56.402118 [Byte1]: 30
8676 11:45:56.406651
8677 11:45:56.407074 Set Vref, RX VrefLevel [Byte0]: 31
8678 11:45:56.409660 [Byte1]: 31
8679 11:45:56.414185
8680 11:45:56.414603 Set Vref, RX VrefLevel [Byte0]: 32
8681 11:45:56.417784 [Byte1]: 32
8682 11:45:56.421580
8683 11:45:56.421997 Set Vref, RX VrefLevel [Byte0]: 33
8684 11:45:56.425489 [Byte1]: 33
8685 11:45:56.429305
8686 11:45:56.429876 Set Vref, RX VrefLevel [Byte0]: 34
8687 11:45:56.433063 [Byte1]: 34
8688 11:45:56.437397
8689 11:45:56.437944 Set Vref, RX VrefLevel [Byte0]: 35
8690 11:45:56.440488 [Byte1]: 35
8691 11:45:56.444896
8692 11:45:56.445319 Set Vref, RX VrefLevel [Byte0]: 36
8693 11:45:56.447993 [Byte1]: 36
8694 11:45:56.452399
8695 11:45:56.452868 Set Vref, RX VrefLevel [Byte0]: 37
8696 11:45:56.455291 [Byte1]: 37
8697 11:45:56.459602
8698 11:45:56.459998 Set Vref, RX VrefLevel [Byte0]: 38
8699 11:45:56.463331 [Byte1]: 38
8700 11:45:56.467907
8701 11:45:56.468471 Set Vref, RX VrefLevel [Byte0]: 39
8702 11:45:56.470881 [Byte1]: 39
8703 11:45:56.475288
8704 11:45:56.475851 Set Vref, RX VrefLevel [Byte0]: 40
8705 11:45:56.478216 [Byte1]: 40
8706 11:45:56.482749
8707 11:45:56.483167 Set Vref, RX VrefLevel [Byte0]: 41
8708 11:45:56.486234 [Byte1]: 41
8709 11:45:56.490613
8710 11:45:56.491035 Set Vref, RX VrefLevel [Byte0]: 42
8711 11:45:56.493711 [Byte1]: 42
8712 11:45:56.497806
8713 11:45:56.498366 Set Vref, RX VrefLevel [Byte0]: 43
8714 11:45:56.501110 [Byte1]: 43
8715 11:45:56.505400
8716 11:45:56.506015 Set Vref, RX VrefLevel [Byte0]: 44
8717 11:45:56.508690 [Byte1]: 44
8718 11:45:56.513076
8719 11:45:56.513522 Set Vref, RX VrefLevel [Byte0]: 45
8720 11:45:56.516196 [Byte1]: 45
8721 11:45:56.521195
8722 11:45:56.521604 Set Vref, RX VrefLevel [Byte0]: 46
8723 11:45:56.524402 [Byte1]: 46
8724 11:45:56.528223
8725 11:45:56.528699 Set Vref, RX VrefLevel [Byte0]: 47
8726 11:45:56.532037 [Byte1]: 47
8727 11:45:56.535888
8728 11:45:56.536365 Set Vref, RX VrefLevel [Byte0]: 48
8729 11:45:56.539604 [Byte1]: 48
8730 11:45:56.543598
8731 11:45:56.544235 Set Vref, RX VrefLevel [Byte0]: 49
8732 11:45:56.547241 [Byte1]: 49
8733 11:45:56.551035
8734 11:45:56.551514 Set Vref, RX VrefLevel [Byte0]: 50
8735 11:45:56.554898 [Byte1]: 50
8736 11:45:56.559039
8737 11:45:56.559615 Set Vref, RX VrefLevel [Byte0]: 51
8738 11:45:56.561913 [Byte1]: 51
8739 11:45:56.566339
8740 11:45:56.566768 Set Vref, RX VrefLevel [Byte0]: 52
8741 11:45:56.570065 [Byte1]: 52
8742 11:45:56.573960
8743 11:45:56.574523 Set Vref, RX VrefLevel [Byte0]: 53
8744 11:45:56.577184 [Byte1]: 53
8745 11:45:56.581646
8746 11:45:56.582100 Set Vref, RX VrefLevel [Byte0]: 54
8747 11:45:56.585257 [Byte1]: 54
8748 11:45:56.589586
8749 11:45:56.590041 Set Vref, RX VrefLevel [Byte0]: 55
8750 11:45:56.592632 [Byte1]: 55
8751 11:45:56.596910
8752 11:45:56.597367 Set Vref, RX VrefLevel [Byte0]: 56
8753 11:45:56.600082 [Byte1]: 56
8754 11:45:56.604404
8755 11:45:56.604890 Set Vref, RX VrefLevel [Byte0]: 57
8756 11:45:56.608036 [Byte1]: 57
8757 11:45:56.612403
8758 11:45:56.612910 Set Vref, RX VrefLevel [Byte0]: 58
8759 11:45:56.615668 [Byte1]: 58
8760 11:45:56.619566
8761 11:45:56.619655 Set Vref, RX VrefLevel [Byte0]: 59
8762 11:45:56.622571 [Byte1]: 59
8763 11:45:56.627420
8764 11:45:56.627533 Set Vref, RX VrefLevel [Byte0]: 60
8765 11:45:56.630613 [Byte1]: 60
8766 11:45:56.634494
8767 11:45:56.634619 Set Vref, RX VrefLevel [Byte0]: 61
8768 11:45:56.638231 [Byte1]: 61
8769 11:45:56.642039
8770 11:45:56.642145 Set Vref, RX VrefLevel [Byte0]: 62
8771 11:45:56.645771 [Byte1]: 62
8772 11:45:56.650074
8773 11:45:56.650185 Set Vref, RX VrefLevel [Byte0]: 63
8774 11:45:56.653374 [Byte1]: 63
8775 11:45:56.657615
8776 11:45:56.657700 Set Vref, RX VrefLevel [Byte0]: 64
8777 11:45:56.660732 [Byte1]: 64
8778 11:45:56.665170
8779 11:45:56.665253 Set Vref, RX VrefLevel [Byte0]: 65
8780 11:45:56.668667 [Byte1]: 65
8781 11:45:56.672993
8782 11:45:56.673080 Set Vref, RX VrefLevel [Byte0]: 66
8783 11:45:56.676059 [Byte1]: 66
8784 11:45:56.680466
8785 11:45:56.680560 Set Vref, RX VrefLevel [Byte0]: 67
8786 11:45:56.683700 [Byte1]: 67
8787 11:45:56.688090
8788 11:45:56.688217 Set Vref, RX VrefLevel [Byte0]: 68
8789 11:45:56.691115 [Byte1]: 68
8790 11:45:56.695850
8791 11:45:56.696011 Set Vref, RX VrefLevel [Byte0]: 69
8792 11:45:56.698938 [Byte1]: 69
8793 11:45:56.703314
8794 11:45:56.703420 Set Vref, RX VrefLevel [Byte0]: 70
8795 11:45:56.706639 [Byte1]: 70
8796 11:45:56.710852
8797 11:45:56.710964 Set Vref, RX VrefLevel [Byte0]: 71
8798 11:45:56.713951 [Byte1]: 71
8799 11:45:56.718530
8800 11:45:56.718638 Set Vref, RX VrefLevel [Byte0]: 72
8801 11:45:56.721613 [Byte1]: 72
8802 11:45:56.725985
8803 11:45:56.726120 Final RX Vref Byte 0 = 52 to rank0
8804 11:45:56.729544 Final RX Vref Byte 1 = 61 to rank0
8805 11:45:56.732764 Final RX Vref Byte 0 = 52 to rank1
8806 11:45:56.735656 Final RX Vref Byte 1 = 61 to rank1==
8807 11:45:56.739691 Dram Type= 6, Freq= 0, CH_1, rank 0
8808 11:45:56.746326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 11:45:56.746524 ==
8810 11:45:56.746630 DQS Delay:
8811 11:45:56.749195 DQS0 = 0, DQS1 = 0
8812 11:45:56.749311 DQM Delay:
8813 11:45:56.749415 DQM0 = 134, DQM1 = 129
8814 11:45:56.752343 DQ Delay:
8815 11:45:56.755639 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8816 11:45:56.759542 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
8817 11:45:56.762701 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
8818 11:45:56.766000 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8819 11:45:56.766217
8820 11:45:56.766411
8821 11:45:56.766620
8822 11:45:56.769418 [DramC_TX_OE_Calibration] TA2
8823 11:45:56.772509 Original DQ_B0 (3 6) =30, OEN = 27
8824 11:45:56.776091 Original DQ_B1 (3 6) =30, OEN = 27
8825 11:45:56.779305 24, 0x0, End_B0=24 End_B1=24
8826 11:45:56.779426 25, 0x0, End_B0=25 End_B1=25
8827 11:45:56.782416 26, 0x0, End_B0=26 End_B1=26
8828 11:45:56.785565 27, 0x0, End_B0=27 End_B1=27
8829 11:45:56.788782 28, 0x0, End_B0=28 End_B1=28
8830 11:45:56.792454 29, 0x0, End_B0=29 End_B1=29
8831 11:45:56.792569 30, 0x0, End_B0=30 End_B1=30
8832 11:45:56.795358 31, 0x4141, End_B0=30 End_B1=30
8833 11:45:56.798920 Byte0 end_step=30 best_step=27
8834 11:45:56.802307 Byte1 end_step=30 best_step=27
8835 11:45:56.805446 Byte0 TX OE(2T, 0.5T) = (3, 3)
8836 11:45:56.808701 Byte1 TX OE(2T, 0.5T) = (3, 3)
8837 11:45:56.808830
8838 11:45:56.808919
8839 11:45:56.815528 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8840 11:45:56.818687 CH1 RK0: MR19=303, MR18=1A10
8841 11:45:56.825320 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8842 11:45:56.825517
8843 11:45:56.828349 ----->DramcWriteLeveling(PI) begin...
8844 11:45:56.828458 ==
8845 11:45:56.832252 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 11:45:56.835185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 11:45:56.835374 ==
8848 11:45:56.838400 Write leveling (Byte 0): 23 => 23
8849 11:45:56.841865 Write leveling (Byte 1): 28 => 28
8850 11:45:56.845118 DramcWriteLeveling(PI) end<-----
8851 11:45:56.845195
8852 11:45:56.845258 ==
8853 11:45:56.848216 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 11:45:56.851893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 11:45:56.851977 ==
8856 11:45:56.855246 [Gating] SW mode calibration
8857 11:45:56.861797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8858 11:45:56.868074 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8859 11:45:56.871870 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 11:45:56.878630 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 11:45:56.881729 1 4 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8862 11:45:56.884747 1 4 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8863 11:45:56.891865 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8864 11:45:56.895118 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8865 11:45:56.898236 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8866 11:45:56.904667 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8867 11:45:56.908191 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 11:45:56.911232 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 11:45:56.918180 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8870 11:45:56.921226 1 5 12 | B1->B0 | 2727 3333 | 1 1 | (1 0) (0 1)
8871 11:45:56.924366 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 1)
8872 11:45:56.931054 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 11:45:56.934807 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 11:45:56.937941 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 11:45:56.944121 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 11:45:56.947928 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 11:45:56.951128 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 11:45:56.957862 1 6 12 | B1->B0 | 4646 2727 | 0 0 | (0 0) (0 0)
8879 11:45:56.961176 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 11:45:56.964267 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 11:45:56.971096 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 11:45:56.974209 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 11:45:56.977575 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 11:45:56.984241 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 11:45:56.987252 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8886 11:45:56.990500 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8887 11:45:56.997600 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8888 11:45:57.000596 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 11:45:57.003733 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 11:45:57.010612 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 11:45:57.013538 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 11:45:57.017401 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 11:45:57.023730 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 11:45:57.027104 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 11:45:57.030275 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 11:45:57.036679 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 11:45:57.040021 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 11:45:57.043643 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 11:45:57.050145 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 11:45:57.053387 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 11:45:57.057073 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8902 11:45:57.063327 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8903 11:45:57.063709 Total UI for P1: 0, mck2ui 16
8904 11:45:57.066494 best dqsien dly found for B1: ( 1, 9, 8)
8905 11:45:57.073678 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8906 11:45:57.076687 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8907 11:45:57.079738 Total UI for P1: 0, mck2ui 16
8908 11:45:57.083492 best dqsien dly found for B0: ( 1, 9, 12)
8909 11:45:57.086482 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8910 11:45:57.089587 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8911 11:45:57.089920
8912 11:45:57.092774 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8913 11:45:57.099630 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8914 11:45:57.099941 [Gating] SW calibration Done
8915 11:45:57.100185 ==
8916 11:45:57.102678 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 11:45:57.109486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 11:45:57.109811 ==
8919 11:45:57.110141 RX Vref Scan: 0
8920 11:45:57.110511
8921 11:45:57.113060 RX Vref 0 -> 0, step: 1
8922 11:45:57.113360
8923 11:45:57.116069 RX Delay 0 -> 252, step: 8
8924 11:45:57.119556 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8925 11:45:57.122936 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8926 11:45:57.126127 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8927 11:45:57.132818 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8928 11:45:57.135944 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8929 11:45:57.139069 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8930 11:45:57.142945 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8931 11:45:57.146132 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8932 11:45:57.149181 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8933 11:45:57.156192 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8934 11:45:57.159338 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8935 11:45:57.162660 iDelay=208, Bit 11, Center 115 (56 ~ 175) 120
8936 11:45:57.165732 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8937 11:45:57.172875 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8938 11:45:57.176062 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8939 11:45:57.179084 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8940 11:45:57.179398 ==
8941 11:45:57.182372 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 11:45:57.185972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 11:45:57.186286 ==
8944 11:45:57.189037 DQS Delay:
8945 11:45:57.189353 DQS0 = 0, DQS1 = 0
8946 11:45:57.191960 DQM Delay:
8947 11:45:57.192351 DQM0 = 136, DQM1 = 129
8948 11:45:57.195711 DQ Delay:
8949 11:45:57.198845 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8950 11:45:57.201958 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8951 11:45:57.205198 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =115
8952 11:45:57.208433 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8953 11:45:57.208767
8954 11:45:57.209002
8955 11:45:57.209279 ==
8956 11:45:57.212193 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 11:45:57.215167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 11:45:57.215479 ==
8959 11:45:57.215848
8960 11:45:57.218834
8961 11:45:57.219230 TX Vref Scan disable
8962 11:45:57.221851 == TX Byte 0 ==
8963 11:45:57.225044 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8964 11:45:57.228760 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8965 11:45:57.231975 == TX Byte 1 ==
8966 11:45:57.235000 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8967 11:45:57.238604 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8968 11:45:57.238915 ==
8969 11:45:57.241486 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 11:45:57.248309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 11:45:57.248429 ==
8972 11:45:57.260379
8973 11:45:57.263506 TX Vref early break, caculate TX vref
8974 11:45:57.266635 TX Vref=16, minBit 0, minWin=22, winSum=377
8975 11:45:57.269888 TX Vref=18, minBit 1, minWin=23, winSum=389
8976 11:45:57.273052 TX Vref=20, minBit 1, minWin=22, winSum=395
8977 11:45:57.276961 TX Vref=22, minBit 0, minWin=24, winSum=402
8978 11:45:57.280315 TX Vref=24, minBit 0, minWin=24, winSum=408
8979 11:45:57.286662 TX Vref=26, minBit 5, minWin=24, winSum=416
8980 11:45:57.289735 TX Vref=28, minBit 0, minWin=24, winSum=416
8981 11:45:57.293384 TX Vref=30, minBit 0, minWin=23, winSum=409
8982 11:45:57.296499 TX Vref=32, minBit 0, minWin=23, winSum=403
8983 11:45:57.300040 TX Vref=34, minBit 0, minWin=22, winSum=392
8984 11:45:57.306413 [TxChooseVref] Worse bit 5, Min win 24, Win sum 416, Final Vref 26
8985 11:45:57.306529
8986 11:45:57.309713 Final TX Range 0 Vref 26
8987 11:45:57.309796
8988 11:45:57.309862 ==
8989 11:45:57.312959 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 11:45:57.316649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 11:45:57.316728 ==
8992 11:45:57.316792
8993 11:45:57.316852
8994 11:45:57.319655 TX Vref Scan disable
8995 11:45:57.326367 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8996 11:45:57.326476 == TX Byte 0 ==
8997 11:45:57.329286 u2DelayCellOfst[0]=18 cells (5 PI)
8998 11:45:57.332471 u2DelayCellOfst[1]=11 cells (3 PI)
8999 11:45:57.336320 u2DelayCellOfst[2]=0 cells (0 PI)
9000 11:45:57.339371 u2DelayCellOfst[3]=3 cells (1 PI)
9001 11:45:57.342467 u2DelayCellOfst[4]=7 cells (2 PI)
9002 11:45:57.346316 u2DelayCellOfst[5]=18 cells (5 PI)
9003 11:45:57.349300 u2DelayCellOfst[6]=18 cells (5 PI)
9004 11:45:57.352386 u2DelayCellOfst[7]=3 cells (1 PI)
9005 11:45:57.356065 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9006 11:45:57.359422 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9007 11:45:57.362518 == TX Byte 1 ==
9008 11:45:57.365666 u2DelayCellOfst[8]=0 cells (0 PI)
9009 11:45:57.365783 u2DelayCellOfst[9]=7 cells (2 PI)
9010 11:45:57.368941 u2DelayCellOfst[10]=14 cells (4 PI)
9011 11:45:57.372713 u2DelayCellOfst[11]=7 cells (2 PI)
9012 11:45:57.375930 u2DelayCellOfst[12]=14 cells (4 PI)
9013 11:45:57.379206 u2DelayCellOfst[13]=18 cells (5 PI)
9014 11:45:57.382386 u2DelayCellOfst[14]=18 cells (5 PI)
9015 11:45:57.385613 u2DelayCellOfst[15]=18 cells (5 PI)
9016 11:45:57.392490 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9017 11:45:57.395458 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9018 11:45:57.395543 DramC Write-DBI on
9019 11:45:57.395610 ==
9020 11:45:57.398670 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 11:45:57.405140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 11:45:57.405269 ==
9023 11:45:57.405408
9024 11:45:57.405529
9025 11:45:57.405639 TX Vref Scan disable
9026 11:45:57.409611 == TX Byte 0 ==
9027 11:45:57.412916 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9028 11:45:57.415998 == TX Byte 1 ==
9029 11:45:57.419111 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9030 11:45:57.422921 DramC Write-DBI off
9031 11:45:57.423023
9032 11:45:57.423115 [DATLAT]
9033 11:45:57.423206 Freq=1600, CH1 RK1
9034 11:45:57.423295
9035 11:45:57.425926 DATLAT Default: 0xf
9036 11:45:57.429391 0, 0xFFFF, sum = 0
9037 11:45:57.429500 1, 0xFFFF, sum = 0
9038 11:45:57.432876 2, 0xFFFF, sum = 0
9039 11:45:57.432971 3, 0xFFFF, sum = 0
9040 11:45:57.435955 4, 0xFFFF, sum = 0
9041 11:45:57.436049 5, 0xFFFF, sum = 0
9042 11:45:57.439150 6, 0xFFFF, sum = 0
9043 11:45:57.439281 7, 0xFFFF, sum = 0
9044 11:45:57.442497 8, 0xFFFF, sum = 0
9045 11:45:57.442635 9, 0xFFFF, sum = 0
9046 11:45:57.446105 10, 0xFFFF, sum = 0
9047 11:45:57.446214 11, 0xFFFF, sum = 0
9048 11:45:57.449350 12, 0xFFFF, sum = 0
9049 11:45:57.449456 13, 0xFFFF, sum = 0
9050 11:45:57.452424 14, 0x0, sum = 1
9051 11:45:57.452577 15, 0x0, sum = 2
9052 11:45:57.455563 16, 0x0, sum = 3
9053 11:45:57.455684 17, 0x0, sum = 4
9054 11:45:57.459396 best_step = 15
9055 11:45:57.459525
9056 11:45:57.459633 ==
9057 11:45:57.462583 Dram Type= 6, Freq= 0, CH_1, rank 1
9058 11:45:57.465737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9059 11:45:57.465920 ==
9060 11:45:57.469452 RX Vref Scan: 0
9061 11:45:57.469627
9062 11:45:57.469766 RX Vref 0 -> 0, step: 1
9063 11:45:57.469896
9064 11:45:57.472531 RX Delay 11 -> 252, step: 4
9065 11:45:57.475739 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9066 11:45:57.482953 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9067 11:45:57.486087 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9068 11:45:57.489391 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9069 11:45:57.492541 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9070 11:45:57.496309 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9071 11:45:57.502819 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9072 11:45:57.505898 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9073 11:45:57.509471 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9074 11:45:57.512569 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9075 11:45:57.515928 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9076 11:45:57.522569 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9077 11:45:57.525880 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9078 11:45:57.529130 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9079 11:45:57.532635 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9080 11:45:57.539258 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9081 11:45:57.539847 ==
9082 11:45:57.542611 Dram Type= 6, Freq= 0, CH_1, rank 1
9083 11:45:57.545682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9084 11:45:57.546162 ==
9085 11:45:57.546595 DQS Delay:
9086 11:45:57.548449 DQS0 = 0, DQS1 = 0
9087 11:45:57.549020 DQM Delay:
9088 11:45:57.552257 DQM0 = 134, DQM1 = 127
9089 11:45:57.552838 DQ Delay:
9090 11:45:57.555347 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9091 11:45:57.558759 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9092 11:45:57.561891 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9093 11:45:57.565167 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9094 11:45:57.565599
9095 11:45:57.568780
9096 11:45:57.569208
9097 11:45:57.569760 [DramC_TX_OE_Calibration] TA2
9098 11:45:57.571721 Original DQ_B0 (3 6) =30, OEN = 27
9099 11:45:57.575024 Original DQ_B1 (3 6) =30, OEN = 27
9100 11:45:57.578314 24, 0x0, End_B0=24 End_B1=24
9101 11:45:57.581513 25, 0x0, End_B0=25 End_B1=25
9102 11:45:57.585177 26, 0x0, End_B0=26 End_B1=26
9103 11:45:57.585634 27, 0x0, End_B0=27 End_B1=27
9104 11:45:57.588263 28, 0x0, End_B0=28 End_B1=28
9105 11:45:57.592083 29, 0x0, End_B0=29 End_B1=29
9106 11:45:57.595286 30, 0x0, End_B0=30 End_B1=30
9107 11:45:57.598427 31, 0x4141, End_B0=30 End_B1=30
9108 11:45:57.598863 Byte0 end_step=30 best_step=27
9109 11:45:57.601977 Byte1 end_step=30 best_step=27
9110 11:45:57.605158 Byte0 TX OE(2T, 0.5T) = (3, 3)
9111 11:45:57.608245 Byte1 TX OE(2T, 0.5T) = (3, 3)
9112 11:45:57.608879
9113 11:45:57.609344
9114 11:45:57.618042 [DQSOSCAuto] RK1, (LSB)MR18= 0xc07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
9115 11:45:57.618476 CH1 RK1: MR19=303, MR18=C07
9116 11:45:57.624964 CH1_RK1: MR19=0x303, MR18=0xC07, DQSOSC=403, MR23=63, INC=22, DEC=15
9117 11:45:57.628206 [RxdqsGatingPostProcess] freq 1600
9118 11:45:57.635018 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9119 11:45:57.637945 best DQS0 dly(2T, 0.5T) = (1, 1)
9120 11:45:57.641197 best DQS1 dly(2T, 0.5T) = (1, 1)
9121 11:45:57.641788 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9122 11:45:57.644775 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9123 11:45:57.647899 best DQS0 dly(2T, 0.5T) = (1, 1)
9124 11:45:57.651057 best DQS1 dly(2T, 0.5T) = (1, 1)
9125 11:45:57.654637 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9126 11:45:57.657728 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9127 11:45:57.660794 Pre-setting of DQS Precalculation
9128 11:45:57.667270 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9129 11:45:57.674093 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9130 11:45:57.680464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9131 11:45:57.680725
9132 11:45:57.680911
9133 11:45:57.684207 [Calibration Summary] 3200 Mbps
9134 11:45:57.684436 CH 0, Rank 0
9135 11:45:57.687446 SW Impedance : PASS
9136 11:45:57.690646 DUTY Scan : NO K
9137 11:45:57.690931 ZQ Calibration : PASS
9138 11:45:57.693754 Jitter Meter : NO K
9139 11:45:57.696937 CBT Training : PASS
9140 11:45:57.697247 Write leveling : PASS
9141 11:45:57.700575 RX DQS gating : PASS
9142 11:45:57.703689 RX DQ/DQS(RDDQC) : PASS
9143 11:45:57.703970 TX DQ/DQS : PASS
9144 11:45:57.707364 RX DATLAT : PASS
9145 11:45:57.710314 RX DQ/DQS(Engine): PASS
9146 11:45:57.710598 TX OE : PASS
9147 11:45:57.710851 All Pass.
9148 11:45:57.713410
9149 11:45:57.713702 CH 0, Rank 1
9150 11:45:57.717088 SW Impedance : PASS
9151 11:45:57.717405 DUTY Scan : NO K
9152 11:45:57.720090 ZQ Calibration : PASS
9153 11:45:57.720370 Jitter Meter : NO K
9154 11:45:57.723284 CBT Training : PASS
9155 11:45:57.727045 Write leveling : PASS
9156 11:45:57.727338 RX DQS gating : PASS
9157 11:45:57.730150 RX DQ/DQS(RDDQC) : PASS
9158 11:45:57.733300 TX DQ/DQS : PASS
9159 11:45:57.733604 RX DATLAT : PASS
9160 11:45:57.736386 RX DQ/DQS(Engine): PASS
9161 11:45:57.739949 TX OE : PASS
9162 11:45:57.740235 All Pass.
9163 11:45:57.740494
9164 11:45:57.740764 CH 1, Rank 0
9165 11:45:57.743530 SW Impedance : PASS
9166 11:45:57.746526 DUTY Scan : NO K
9167 11:45:57.746825 ZQ Calibration : PASS
9168 11:45:57.750206 Jitter Meter : NO K
9169 11:45:57.753408 CBT Training : PASS
9170 11:45:57.753657 Write leveling : PASS
9171 11:45:57.756501 RX DQS gating : PASS
9172 11:45:57.759938 RX DQ/DQS(RDDQC) : PASS
9173 11:45:57.760168 TX DQ/DQS : PASS
9174 11:45:57.762993 RX DATLAT : PASS
9175 11:45:57.766197 RX DQ/DQS(Engine): PASS
9176 11:45:57.766513 TX OE : PASS
9177 11:45:57.769916 All Pass.
9178 11:45:57.770306
9179 11:45:57.770663 CH 1, Rank 1
9180 11:45:57.772956 SW Impedance : PASS
9181 11:45:57.773275 DUTY Scan : NO K
9182 11:45:57.776605 ZQ Calibration : PASS
9183 11:45:57.779578 Jitter Meter : NO K
9184 11:45:57.779930 CBT Training : PASS
9185 11:45:57.783237 Write leveling : PASS
9186 11:45:57.783649 RX DQS gating : PASS
9187 11:45:57.786436 RX DQ/DQS(RDDQC) : PASS
9188 11:45:57.789601 TX DQ/DQS : PASS
9189 11:45:57.789901 RX DATLAT : PASS
9190 11:45:57.792785 RX DQ/DQS(Engine): PASS
9191 11:45:57.796450 TX OE : PASS
9192 11:45:57.796846 All Pass.
9193 11:45:57.797184
9194 11:45:57.799700 DramC Write-DBI on
9195 11:45:57.800066 PER_BANK_REFRESH: Hybrid Mode
9196 11:45:57.802915 TX_TRACKING: ON
9197 11:45:57.812870 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9198 11:45:57.819155 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9199 11:45:57.825555 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9200 11:45:57.828675 [FAST_K] Save calibration result to emmc
9201 11:45:57.832472 sync common calibartion params.
9202 11:45:57.835679 sync cbt_mode0:1, 1:1
9203 11:45:57.838918 dram_init: ddr_geometry: 2
9204 11:45:57.839102 dram_init: ddr_geometry: 2
9205 11:45:57.842156 dram_init: ddr_geometry: 2
9206 11:45:57.845283 0:dram_rank_size:100000000
9207 11:45:57.845497 1:dram_rank_size:100000000
9208 11:45:57.852199 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9209 11:45:57.855353 DFS_SHUFFLE_HW_MODE: ON
9210 11:45:57.858643 dramc_set_vcore_voltage set vcore to 725000
9211 11:45:57.862363 Read voltage for 1600, 0
9212 11:45:57.862784 Vio18 = 0
9213 11:45:57.863268 Vcore = 725000
9214 11:45:57.865297 Vdram = 0
9215 11:45:57.865793 Vddq = 0
9216 11:45:57.866147 Vmddr = 0
9217 11:45:57.868453 switch to 3200 Mbps bootup
9218 11:45:57.871662 [DramcRunTimeConfig]
9219 11:45:57.872160 PHYPLL
9220 11:45:57.872665 DPM_CONTROL_AFTERK: ON
9221 11:45:57.875498 PER_BANK_REFRESH: ON
9222 11:45:57.878456 REFRESH_OVERHEAD_REDUCTION: ON
9223 11:45:57.878828 CMD_PICG_NEW_MODE: OFF
9224 11:45:57.882127 XRTWTW_NEW_MODE: ON
9225 11:45:57.885194 XRTRTR_NEW_MODE: ON
9226 11:45:57.885644 TX_TRACKING: ON
9227 11:45:57.888307 RDSEL_TRACKING: OFF
9228 11:45:57.888853 DQS Precalculation for DVFS: ON
9229 11:45:57.891534 RX_TRACKING: OFF
9230 11:45:57.891894 HW_GATING DBG: ON
9231 11:45:57.894856 ZQCS_ENABLE_LP4: ON
9232 11:45:57.895397 RX_PICG_NEW_MODE: ON
9233 11:45:57.898610 TX_PICG_NEW_MODE: ON
9234 11:45:57.902012 ENABLE_RX_DCM_DPHY: ON
9235 11:45:57.905164 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9236 11:45:57.905669 DUMMY_READ_FOR_TRACKING: OFF
9237 11:45:57.908241 !!! SPM_CONTROL_AFTERK: OFF
9238 11:45:57.911429 !!! SPM could not control APHY
9239 11:45:57.915173 IMPEDANCE_TRACKING: ON
9240 11:45:57.915404 TEMP_SENSOR: ON
9241 11:45:57.918199 HW_SAVE_FOR_SR: OFF
9242 11:45:57.918447 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9243 11:45:57.924409 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9244 11:45:57.924686 Read ODT Tracking: ON
9245 11:45:57.928186 Refresh Rate DeBounce: ON
9246 11:45:57.931141 DFS_NO_QUEUE_FLUSH: ON
9247 11:45:57.934379 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9248 11:45:57.934656 ENABLE_DFS_RUNTIME_MRW: OFF
9249 11:45:57.938073 DDR_RESERVE_NEW_MODE: ON
9250 11:45:57.941274 MR_CBT_SWITCH_FREQ: ON
9251 11:45:57.941567 =========================
9252 11:45:57.961150 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9253 11:45:57.963839 dram_init: ddr_geometry: 2
9254 11:45:57.982371 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9255 11:45:57.985475 dram_init: dram init end (result: 0)
9256 11:45:57.991889 DRAM-K: Full calibration passed in 24610 msecs
9257 11:45:57.995573 MRC: failed to locate region type 0.
9258 11:45:57.995681 DRAM rank0 size:0x100000000,
9259 11:45:57.998664 DRAM rank1 size=0x100000000
9260 11:45:58.008817 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9261 11:45:58.015369 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9262 11:45:58.021596 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9263 11:45:58.031649 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9264 11:45:58.031812 DRAM rank0 size:0x100000000,
9265 11:45:58.034775 DRAM rank1 size=0x100000000
9266 11:45:58.034929 CBMEM:
9267 11:45:58.038466 IMD: root @ 0xfffff000 254 entries.
9268 11:45:58.041808 IMD: root @ 0xffffec00 62 entries.
9269 11:45:58.045041 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9270 11:45:58.051884 WARNING: RO_VPD is uninitialized or empty.
9271 11:45:58.054735 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9272 11:45:58.062873 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9273 11:45:58.075076 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9274 11:45:58.086569 BS: romstage times (exec / console): total (unknown) / 24110 ms
9275 11:45:58.086702
9276 11:45:58.086802
9277 11:45:58.096580 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9278 11:45:58.099763 ARM64: Exception handlers installed.
9279 11:45:58.103492 ARM64: Testing exception
9280 11:45:58.106702 ARM64: Done test exception
9281 11:45:58.107254 Enumerating buses...
9282 11:45:58.110046 Show all devs... Before device enumeration.
9283 11:45:58.113117 Root Device: enabled 1
9284 11:45:58.116314 CPU_CLUSTER: 0: enabled 1
9285 11:45:58.116942 CPU: 00: enabled 1
9286 11:45:58.119528 Compare with tree...
9287 11:45:58.120118 Root Device: enabled 1
9288 11:45:58.122785 CPU_CLUSTER: 0: enabled 1
9289 11:45:58.126550 CPU: 00: enabled 1
9290 11:45:58.127101 Root Device scanning...
9291 11:45:58.129854 scan_static_bus for Root Device
9292 11:45:58.132873 CPU_CLUSTER: 0 enabled
9293 11:45:58.136401 scan_static_bus for Root Device done
9294 11:45:58.139549 scan_bus: bus Root Device finished in 8 msecs
9295 11:45:58.140110 done
9296 11:45:58.146020 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9297 11:45:58.149146 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9298 11:45:58.155702 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9299 11:45:58.162139 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9300 11:45:58.162377 Allocating resources...
9301 11:45:58.165642 Reading resources...
9302 11:45:58.168862 Root Device read_resources bus 0 link: 0
9303 11:45:58.172034 DRAM rank0 size:0x100000000,
9304 11:45:58.172168 DRAM rank1 size=0x100000000
9305 11:45:58.178830 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9306 11:45:58.178948 CPU: 00 missing read_resources
9307 11:45:58.185549 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9308 11:45:58.188651 Root Device read_resources bus 0 link: 0 done
9309 11:45:58.191820 Done reading resources.
9310 11:45:58.195001 Show resources in subtree (Root Device)...After reading.
9311 11:45:58.198364 Root Device child on link 0 CPU_CLUSTER: 0
9312 11:45:58.201989 CPU_CLUSTER: 0 child on link 0 CPU: 00
9313 11:45:58.211607 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9314 11:45:58.211699 CPU: 00
9315 11:45:58.218348 Root Device assign_resources, bus 0 link: 0
9316 11:45:58.221493 CPU_CLUSTER: 0 missing set_resources
9317 11:45:58.224780 Root Device assign_resources, bus 0 link: 0 done
9318 11:45:58.228119 Done setting resources.
9319 11:45:58.231122 Show resources in subtree (Root Device)...After assigning values.
9320 11:45:58.234791 Root Device child on link 0 CPU_CLUSTER: 0
9321 11:45:58.241363 CPU_CLUSTER: 0 child on link 0 CPU: 00
9322 11:45:58.247646 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9323 11:45:58.251463 CPU: 00
9324 11:45:58.251574 Done allocating resources.
9325 11:45:58.257845 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9326 11:45:58.257936 Enabling resources...
9327 11:45:58.261100 done.
9328 11:45:58.264153 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9329 11:45:58.267723 Initializing devices...
9330 11:45:58.267807 Root Device init
9331 11:45:58.270693 init hardware done!
9332 11:45:58.270777 0x00000018: ctrlr->caps
9333 11:45:58.274023 52.000 MHz: ctrlr->f_max
9334 11:45:58.277817 0.400 MHz: ctrlr->f_min
9335 11:45:58.277903 0x40ff8080: ctrlr->voltages
9336 11:45:58.280900 sclk: 390625
9337 11:45:58.280983 Bus Width = 1
9338 11:45:58.284343 sclk: 390625
9339 11:45:58.284426 Bus Width = 1
9340 11:45:58.287898 Early init status = 3
9341 11:45:58.290817 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9342 11:45:58.294020 in-header: 03 fc 00 00 01 00 00 00
9343 11:45:58.297448 in-data: 00
9344 11:45:58.300493 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9345 11:45:58.305519 in-header: 03 fd 00 00 00 00 00 00
9346 11:45:58.308855 in-data:
9347 11:45:58.311984 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9348 11:45:58.315831 in-header: 03 fc 00 00 01 00 00 00
9349 11:45:58.318967 in-data: 00
9350 11:45:58.322640 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9351 11:45:58.327475 in-header: 03 fd 00 00 00 00 00 00
9352 11:45:58.330629 in-data:
9353 11:45:58.334435 [SSUSB] Setting up USB HOST controller...
9354 11:45:58.337376 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9355 11:45:58.340313 [SSUSB] phy power-on done.
9356 11:45:58.343908 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9357 11:45:58.350694 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9358 11:45:58.353671 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9359 11:45:58.360141 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9360 11:45:58.366980 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9361 11:45:58.373690 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9362 11:45:58.380429 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9363 11:45:58.386605 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9364 11:45:58.390076 SPM: binary array size = 0x9dc
9365 11:45:58.393077 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9366 11:45:58.400359 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9367 11:45:58.406393 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9368 11:45:58.413157 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9369 11:45:58.416135 configure_display: Starting display init
9370 11:45:58.451001 anx7625_power_on_init: Init interface.
9371 11:45:58.454079 anx7625_disable_pd_protocol: Disabled PD feature.
9372 11:45:58.457120 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9373 11:45:58.485224 anx7625_start_dp_work: Secure OCM version=00
9374 11:45:58.488411 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9375 11:45:58.503337 sp_tx_get_edid_block: EDID Block = 1
9376 11:45:58.605916 Extracted contents:
9377 11:45:58.609092 header: 00 ff ff ff ff ff ff 00
9378 11:45:58.612133 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9379 11:45:58.615688 version: 01 04
9380 11:45:58.619073 basic params: 95 1f 11 78 0a
9381 11:45:58.622305 chroma info: 76 90 94 55 54 90 27 21 50 54
9382 11:45:58.625328 established: 00 00 00
9383 11:45:58.632167 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9384 11:45:58.638552 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9385 11:45:58.641568 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9386 11:45:58.648610 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9387 11:45:58.655228 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9388 11:45:58.658281 extensions: 00
9389 11:45:58.658793 checksum: fb
9390 11:45:58.659252
9391 11:45:58.661822 Manufacturer: IVO Model 57d Serial Number 0
9392 11:45:58.664998 Made week 0 of 2020
9393 11:45:58.668070 EDID version: 1.4
9394 11:45:58.668638 Digital display
9395 11:45:58.671408 6 bits per primary color channel
9396 11:45:58.671821 DisplayPort interface
9397 11:45:58.675139 Maximum image size: 31 cm x 17 cm
9398 11:45:58.678243 Gamma: 220%
9399 11:45:58.678650 Check DPMS levels
9400 11:45:58.684723 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9401 11:45:58.687774 First detailed timing is preferred timing
9402 11:45:58.691438 Established timings supported:
9403 11:45:58.691882 Standard timings supported:
9404 11:45:58.694385 Detailed timings
9405 11:45:58.698102 Hex of detail: 383680a07038204018303c0035ae10000019
9406 11:45:58.704430 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9407 11:45:58.707990 0780 0798 07c8 0820 hborder 0
9408 11:45:58.711108 0438 043b 0447 0458 vborder 0
9409 11:45:58.714310 -hsync -vsync
9410 11:45:58.714864 Did detailed timing
9411 11:45:58.721412 Hex of detail: 000000000000000000000000000000000000
9412 11:45:58.724605 Manufacturer-specified data, tag 0
9413 11:45:58.727859 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9414 11:45:58.730908 ASCII string: InfoVision
9415 11:45:58.734027 Hex of detail: 000000fe00523134304e574635205248200a
9416 11:45:58.737721 ASCII string: R140NWF5 RH
9417 11:45:58.738277 Checksum
9418 11:45:58.740971 Checksum: 0xfb (valid)
9419 11:45:58.744231 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9420 11:45:58.747424 DSI data_rate: 832800000 bps
9421 11:45:58.754160 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9422 11:45:58.757205 anx7625_parse_edid: pixelclock(138800).
9423 11:45:58.760225 hactive(1920), hsync(48), hfp(24), hbp(88)
9424 11:45:58.763925 vactive(1080), vsync(12), vfp(3), vbp(17)
9425 11:45:58.767011 anx7625_dsi_config: config dsi.
9426 11:45:58.773696 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9427 11:45:58.787458 anx7625_dsi_config: success to config DSI
9428 11:45:58.790924 anx7625_dp_start: MIPI phy setup OK.
9429 11:45:58.794588 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9430 11:45:58.797761 mtk_ddp_mode_set invalid vrefresh 60
9431 11:45:58.801457 main_disp_path_setup
9432 11:45:58.802019 ovl_layer_smi_id_en
9433 11:45:58.804556 ovl_layer_smi_id_en
9434 11:45:58.804978 ccorr_config
9435 11:45:58.805312 aal_config
9436 11:45:58.807769 gamma_config
9437 11:45:58.808186 postmask_config
9438 11:45:58.810724 dither_config
9439 11:45:58.814035 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9440 11:45:58.820986 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9441 11:45:58.824056 Root Device init finished in 552 msecs
9442 11:45:58.827223 CPU_CLUSTER: 0 init
9443 11:45:58.834090 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9444 11:45:58.837159 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9445 11:45:58.840332 APU_MBOX 0x190000b0 = 0x10001
9446 11:45:58.844160 APU_MBOX 0x190001b0 = 0x10001
9447 11:45:58.847209 APU_MBOX 0x190005b0 = 0x10001
9448 11:45:58.850523 APU_MBOX 0x190006b0 = 0x10001
9449 11:45:58.856804 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9450 11:45:58.866940 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9451 11:45:58.878979 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9452 11:45:58.885797 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9453 11:45:58.897194 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9454 11:45:58.906725 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9455 11:45:58.909786 CPU_CLUSTER: 0 init finished in 81 msecs
9456 11:45:58.912816 Devices initialized
9457 11:45:58.916604 Show all devs... After init.
9458 11:45:58.917114 Root Device: enabled 1
9459 11:45:58.919734 CPU_CLUSTER: 0: enabled 1
9460 11:45:58.923081 CPU: 00: enabled 1
9461 11:45:58.926284 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9462 11:45:58.929352 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9463 11:45:58.933150 ELOG: NV offset 0x57f000 size 0x1000
9464 11:45:58.939304 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9465 11:45:58.946340 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9466 11:45:58.949374 ELOG: Event(17) added with size 13 at 2023-06-15 11:45:58 UTC
9467 11:45:58.955785 out: cmd=0x121: 03 db 21 01 00 00 00 00
9468 11:45:58.959202 in-header: 03 cd 00 00 2c 00 00 00
9469 11:45:58.969278 in-data: 92 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9470 11:45:58.975868 ELOG: Event(A1) added with size 10 at 2023-06-15 11:45:58 UTC
9471 11:45:58.982599 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9472 11:45:58.989261 ELOG: Event(A0) added with size 9 at 2023-06-15 11:45:59 UTC
9473 11:45:58.992322 elog_add_boot_reason: Logged dev mode boot
9474 11:45:58.999168 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9475 11:45:58.999612 Finalize devices...
9476 11:45:59.001984 Devices finalized
9477 11:45:59.005797 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9478 11:45:59.008888 Writing coreboot table at 0xffe64000
9479 11:45:59.011862 0. 000000000010a000-0000000000113fff: RAMSTAGE
9480 11:45:59.018794 1. 0000000040000000-00000000400fffff: RAM
9481 11:45:59.022274 2. 0000000040100000-000000004032afff: RAMSTAGE
9482 11:45:59.025494 3. 000000004032b000-00000000545fffff: RAM
9483 11:45:59.028622 4. 0000000054600000-000000005465ffff: BL31
9484 11:45:59.031914 5. 0000000054660000-00000000ffe63fff: RAM
9485 11:45:59.038547 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9486 11:45:59.041797 7. 0000000100000000-000000023fffffff: RAM
9487 11:45:59.045004 Passing 5 GPIOs to payload:
9488 11:45:59.048760 NAME | PORT | POLARITY | VALUE
9489 11:45:59.055036 EC in RW | 0x000000aa | low | undefined
9490 11:45:59.058242 EC interrupt | 0x00000005 | low | undefined
9491 11:45:59.061957 TPM interrupt | 0x000000ab | high | undefined
9492 11:45:59.068057 SD card detect | 0x00000011 | high | undefined
9493 11:45:59.071835 speaker enable | 0x00000093 | high | undefined
9494 11:45:59.074784 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9495 11:45:59.078615 in-header: 03 f9 00 00 02 00 00 00
9496 11:45:59.081322 in-data: 02 00
9497 11:45:59.085160 ADC[4]: Raw value=904139 ID=7
9498 11:45:59.085588 ADC[3]: Raw value=213282 ID=1
9499 11:45:59.088102 RAM Code: 0x71
9500 11:45:59.091373 ADC[6]: Raw value=75036 ID=0
9501 11:45:59.091796 ADC[5]: Raw value=213652 ID=1
9502 11:45:59.094813 SKU Code: 0x1
9503 11:45:59.101726 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169
9504 11:45:59.102152 coreboot table: 964 bytes.
9505 11:45:59.104804 IMD ROOT 0. 0xfffff000 0x00001000
9506 11:45:59.107779 IMD SMALL 1. 0xffffe000 0x00001000
9507 11:45:59.111568 RO MCACHE 2. 0xffffc000 0x00001104
9508 11:45:59.114709 CONSOLE 3. 0xfff7c000 0x00080000
9509 11:45:59.117889 FMAP 4. 0xfff7b000 0x00000452
9510 11:45:59.121029 TIME STAMP 5. 0xfff7a000 0x00000910
9511 11:45:59.124802 VBOOT WORK 6. 0xfff66000 0x00014000
9512 11:45:59.127790 RAMOOPS 7. 0xffe66000 0x00100000
9513 11:45:59.131037 COREBOOT 8. 0xffe64000 0x00002000
9514 11:45:59.635546 IMD small region:
9515 11:45:59.636800 IMD ROOT 0. 0xffffec00 0x00000400
9516 11:45:59.637379 VPD 1. 0xffffeba0 0x0000004c
9517 11:45:59.637922 MMC STATUS 2. 0xffffeb80 0x00000004
9518 11:45:59.638435 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9519 11:45:59.638935 Probing TPM: done!
9520 11:45:59.639434 Connected to device vid:did:rid of 1ae0:0028:00
9521 11:45:59.639993 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9522 11:45:59.640665 Initialized TPM device CR50 revision 0
9523 11:45:59.641259 Checking cr50 for pending updates
9524 11:45:59.641884 Reading cr50 TPM mode
9525 11:45:59.642518 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9526 11:45:59.643144 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9527 11:45:59.643774 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9528 11:45:59.644400 Checking segment from ROM address 0x40100000
9529 11:45:59.645057 Checking segment from ROM address 0x4010001c
9530 11:45:59.645669 Loading segment from ROM address 0x40100000
9531 11:45:59.646295 code (compression=0)
9532 11:45:59.646915 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9533 11:45:59.647548 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9534 11:45:59.648175 it's not compressed!
9535 11:45:59.648832 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9536 11:45:59.649457 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9537 11:45:59.650091 Loading segment from ROM address 0x4010001c
9538 11:45:59.650702 Entry Point 0x80000000
9539 11:45:59.651293 Loaded segments
9540 11:45:59.651857 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9541 11:45:59.652430 Jumping to boot code at 0x80000000(0xffe64000)
9542 11:45:59.653010 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9543 11:45:59.653586 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9544 11:45:59.654141 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9545 11:45:59.654724 Checking segment from ROM address 0x40100000
9546 11:45:59.655293 Checking segment from ROM address 0x4010001c
9547 11:45:59.655861 Loading segment from ROM address 0x40100000
9548 11:45:59.656429 code (compression=1)
9549 11:45:59.657032 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9550 11:45:59.657610 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9551 11:45:59.658182 using LZMA
9552 11:45:59.658751 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9553 11:45:59.659316 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9554 11:45:59.659883 Loading segment from ROM address 0x4010001c
9555 11:45:59.660444 Entry Point 0x54601000
9556 11:45:59.661046 Loaded segments
9557 11:45:59.661606 NOTICE: MT8192 bl31_setup
9558 11:45:59.662184 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9559 11:45:59.662747 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9560 11:45:59.663316 WARNING: region 0:
9561 11:45:59.663888 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 11:45:59.664440 WARNING: region 1:
9563 11:45:59.665028 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9564 11:45:59.665604 WARNING: region 2:
9565 11:45:59.666180 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9566 11:45:59.666752 WARNING: region 3:
9567 11:45:59.667195 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9568 11:45:59.667501 WARNING: region 4:
9569 11:45:59.667902 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9570 11:45:59.668308 WARNING: region 5:
9571 11:45:59.668728 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9572 11:45:59.669130 WARNING: region 6:
9573 11:45:59.669538 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9574 11:45:59.669940 WARNING: region 7:
9575 11:45:59.670373 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 11:45:59.670772 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9577 11:45:59.671177 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9578 11:45:59.671586 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9579 11:45:59.671952 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9580 11:45:59.672260 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9581 11:45:59.672576 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9582 11:45:59.672890 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9583 11:45:59.673198 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9584 11:45:59.673507 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9585 11:45:59.673811 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9586 11:45:59.674115 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9587 11:45:59.674419 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9588 11:45:59.674709 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9589 11:45:59.674960 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9590 11:45:59.675205 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9591 11:45:59.675443 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9592 11:45:59.675700 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9593 11:45:59.675872 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9594 11:45:59.676029 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9595 11:45:59.676183 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9596 11:45:59.676337 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9597 11:45:59.676491 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9598 11:45:59.676680 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9599 11:45:59.676837 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9600 11:45:59.677218 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9601 11:45:59.677362 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9602 11:45:59.677494 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9603 11:45:59.677639 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9604 11:45:59.677769 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9605 11:45:59.677901 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9606 11:45:59.678027 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9607 11:45:59.678158 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9608 11:45:59.678288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9609 11:45:59.678414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9610 11:45:59.678547 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9611 11:45:59.678675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9612 11:45:59.678798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9613 11:45:59.678926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9614 11:45:59.679055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9615 11:45:59.679178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9616 11:45:59.679308 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9617 11:45:59.679431 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9618 11:45:59.679553 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9619 11:45:59.679677 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9620 11:45:59.679798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9621 11:45:59.679918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9622 11:45:59.680036 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9623 11:45:59.680156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9624 11:45:59.680276 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9625 11:45:59.680399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9626 11:45:59.680539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9627 11:45:59.680728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9628 11:45:59.682949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9629 11:45:59.686134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9630 11:45:59.693011 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9631 11:45:59.696130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9632 11:45:59.703127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9633 11:45:59.706312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9634 11:45:59.709386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9635 11:45:59.716072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9636 11:45:59.719248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9637 11:45:59.726234 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9638 11:45:59.729455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9639 11:45:59.736246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9640 11:45:59.739975 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9641 11:45:59.746567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9642 11:45:59.749744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9643 11:45:59.752751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9644 11:45:59.759873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9645 11:45:59.762490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9646 11:45:59.769640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9647 11:45:59.772915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9648 11:45:59.779204 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9649 11:45:59.783127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9650 11:45:59.786281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9651 11:45:59.792508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9652 11:45:59.795834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9653 11:45:59.802747 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9654 11:45:59.805841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9655 11:45:59.812240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9656 11:45:59.815739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9657 11:45:59.822078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9658 11:45:59.825730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9659 11:45:59.832033 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9660 11:45:59.835885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9661 11:45:59.838936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9662 11:45:59.845351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9663 11:45:59.848288 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9664 11:45:59.855273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9665 11:45:59.858316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9666 11:45:59.865183 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9667 11:45:59.868273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9668 11:45:59.875214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9669 11:45:59.878423 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9670 11:45:59.881574 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9671 11:45:59.887929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9672 11:45:59.891322 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9673 11:45:59.894657 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9674 11:45:59.901800 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9675 11:45:59.904844 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9676 11:45:59.907816 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9677 11:45:59.914776 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9678 11:45:59.917814 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9679 11:45:59.921001 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9680 11:45:59.928140 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9681 11:45:59.931092 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9682 11:45:59.938244 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9683 11:45:59.941418 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9684 11:45:59.944684 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9685 11:45:59.951107 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9686 11:45:59.954833 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9687 11:45:59.961078 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9688 11:45:59.964770 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9689 11:45:59.967910 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9690 11:45:59.974411 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9691 11:45:59.978275 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9692 11:45:59.981570 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9693 11:45:59.987578 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9694 11:45:59.991167 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9695 11:45:59.994312 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9696 11:46:00.001312 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9697 11:46:00.004709 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9698 11:46:00.008085 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9699 11:46:00.011349 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9700 11:46:00.017702 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9701 11:46:00.020867 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9702 11:46:00.027587 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9703 11:46:00.031160 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9704 11:46:00.034228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9705 11:46:00.041133 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9706 11:46:00.044338 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9707 11:46:00.050550 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9708 11:46:00.054267 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9709 11:46:00.057314 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9710 11:46:00.064429 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9711 11:46:00.067329 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9712 11:46:00.074215 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9713 11:46:00.077537 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9714 11:46:00.080593 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9715 11:46:00.087613 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9716 11:46:00.090881 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9717 11:46:00.097508 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9718 11:46:00.100583 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9719 11:46:00.104014 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9720 11:46:00.110342 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9721 11:46:00.113689 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9722 11:46:00.120150 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9723 11:46:00.123894 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9724 11:46:00.126972 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9725 11:46:00.133757 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9726 11:46:00.136855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9727 11:46:00.139865 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9728 11:46:00.146792 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9729 11:46:00.150024 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9730 11:46:00.156760 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9731 11:46:00.159887 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9732 11:46:00.163543 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9733 11:46:00.169900 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9734 11:46:00.173061 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9735 11:46:00.179950 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9736 11:46:00.183075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9737 11:46:00.186322 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9738 11:46:00.193042 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9739 11:46:00.196282 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9740 11:46:00.202962 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9741 11:46:00.206330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9742 11:46:00.209407 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9743 11:46:00.215788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9744 11:46:00.219249 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9745 11:46:00.226128 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9746 11:46:00.229290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9747 11:46:00.232950 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9748 11:46:00.239438 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9749 11:46:00.243035 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9750 11:46:00.249408 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9751 11:46:00.252588 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9752 11:46:00.255922 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9753 11:46:00.262421 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9754 11:46:00.266089 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9755 11:46:00.272200 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9756 11:46:00.275379 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9757 11:46:00.279145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9758 11:46:00.285338 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9759 11:46:00.288760 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9760 11:46:00.295242 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9761 11:46:00.298389 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9762 11:46:00.301543 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9763 11:46:00.308307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9764 11:46:00.311558 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9765 11:46:00.317882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9766 11:46:00.321812 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9767 11:46:00.328285 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9768 11:46:00.331398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9769 11:46:00.334569 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9770 11:46:00.340930 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9771 11:46:00.344779 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9772 11:46:00.350937 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9773 11:46:00.354804 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9774 11:46:00.361220 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9775 11:46:00.364395 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9776 11:46:00.367597 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9777 11:46:00.374520 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9778 11:46:00.377643 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9779 11:46:00.384576 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9780 11:46:00.387700 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9781 11:46:00.394209 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9782 11:46:00.397511 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9783 11:46:00.400645 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9784 11:46:00.407054 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9785 11:46:00.410960 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9786 11:46:00.417475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9787 11:46:00.420475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9788 11:46:00.427165 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9789 11:46:00.430138 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9790 11:46:00.433999 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9791 11:46:00.440401 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9792 11:46:00.443556 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9793 11:46:00.450449 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9794 11:46:00.453643 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9795 11:46:00.456770 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9796 11:46:00.463732 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9797 11:46:00.466792 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9798 11:46:00.473184 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9799 11:46:00.476984 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9800 11:46:00.483200 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9801 11:46:00.486867 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9802 11:46:00.489991 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9803 11:46:00.496340 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9804 11:46:00.499472 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9805 11:46:00.502756 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9806 11:46:00.509302 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9807 11:46:00.513168 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9808 11:46:00.516322 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9809 11:46:00.519584 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9810 11:46:00.526114 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9811 11:46:00.529379 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9812 11:46:00.535691 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9813 11:46:00.538938 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9814 11:46:00.542755 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9815 11:46:00.549049 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9816 11:46:00.552274 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9817 11:46:00.559051 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9818 11:46:00.562064 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9819 11:46:00.565999 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9820 11:46:00.572291 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9821 11:46:00.575534 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9822 11:46:00.578808 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9823 11:46:00.585875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9824 11:46:00.588494 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9825 11:46:00.592138 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9826 11:46:00.598649 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9827 11:46:00.601759 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9828 11:46:00.608303 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9829 11:46:00.611516 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9830 11:46:00.615460 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9831 11:46:00.621995 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9832 11:46:00.625201 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9833 11:46:00.628312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9834 11:46:00.634887 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9835 11:46:00.638152 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9836 11:46:00.645104 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9837 11:46:00.648179 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9838 11:46:00.651332 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9839 11:46:00.658122 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9840 11:46:00.661394 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9841 11:46:00.664476 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9842 11:46:00.671405 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9843 11:46:00.674463 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9844 11:46:00.681185 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9845 11:46:00.684442 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9846 11:46:00.687683 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9847 11:46:00.690827 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9848 11:46:00.694342 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9849 11:46:00.700718 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9850 11:46:00.703956 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9851 11:46:00.707263 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9852 11:46:00.710430 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9853 11:46:00.717539 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9854 11:46:00.720612 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9855 11:46:00.723795 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9856 11:46:00.730240 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9857 11:46:00.734123 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9858 11:46:00.737366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9859 11:46:00.743815 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9860 11:46:00.746975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9861 11:46:00.753906 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9862 11:46:00.756980 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9863 11:46:00.760125 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9864 11:46:00.767009 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9865 11:46:00.770001 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9866 11:46:00.776479 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9867 11:46:00.780175 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9868 11:46:00.783377 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9869 11:46:00.790096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9870 11:46:00.793065 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9871 11:46:00.799683 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9872 11:46:00.802834 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9873 11:46:00.806765 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9874 11:46:00.813226 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9875 11:46:00.816413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9876 11:46:00.822893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9877 11:46:00.826723 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9878 11:46:00.833092 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9879 11:46:00.836312 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9880 11:46:00.839682 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9881 11:46:00.846138 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9882 11:46:00.849935 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9883 11:46:00.856070 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9884 11:46:00.859219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9885 11:46:00.866144 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9886 11:46:00.869367 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9887 11:46:01.461072 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9888 11:46:01.462026 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9889 11:46:01.462393 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9890 11:46:01.462794 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9891 11:46:01.463114 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9892 11:46:01.463476 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9893 11:46:01.463934 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9894 11:46:01.464487 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9895 11:46:01.464929 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9896 11:46:01.465353 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9897 11:46:01.465886 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9898 11:46:01.466021 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9899 11:46:01.466107 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9900 11:46:01.466237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9901 11:46:01.466394 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9902 11:46:01.466484 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9903 11:46:01.466571 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9904 11:46:01.466657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9905 11:46:01.466742 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9906 11:46:01.466828 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9907 11:46:01.466923 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9908 11:46:01.467010 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9909 11:46:01.467103 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9910 11:46:01.467206 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9911 11:46:01.467313 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9912 11:46:01.467423 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9913 11:46:01.467538 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9914 11:46:01.467648 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9915 11:46:01.467762 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9916 11:46:01.467876 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9917 11:46:01.467985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9918 11:46:01.468092 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9919 11:46:01.468200 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9920 11:46:01.468308 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9921 11:46:01.468415 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9922 11:46:01.468530 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9923 11:46:01.468644 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9924 11:46:01.468755 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9925 11:46:01.468862 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9926 11:46:01.468978 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9927 11:46:01.469103 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9928 11:46:01.469222 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9929 11:46:01.469345 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9930 11:46:01.469459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9931 11:46:01.469577 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9932 11:46:01.469706 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9933 11:46:01.469831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9934 11:46:01.469957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9935 11:46:01.470078 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9936 11:46:01.470206 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9937 11:46:01.470331 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9938 11:46:01.470452 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9939 11:46:01.470579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9940 11:46:01.470706 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9941 11:46:01.470830 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9942 11:46:01.470956 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9943 11:46:01.471045 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9944 11:46:01.471157 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9945 11:46:01.471279 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9946 11:46:01.471397 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9947 11:46:01.471522 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9948 11:46:01.471645 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9949 11:46:01.471772 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9950 11:46:01.471895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9951 11:46:01.472015 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9952 11:46:01.472124 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9953 11:46:01.472240 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9954 11:46:01.472361 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9955 11:46:01.472481 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9956 11:46:01.472608 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9957 11:46:01.472728 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9958 11:46:01.472844 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9959 11:46:01.472962 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9960 11:46:01.473083 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9961 11:46:01.473200 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9962 11:46:01.473541 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9963 11:46:01.473967 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9964 11:46:01.474114 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9965 11:46:01.474247 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9966 11:46:01.474372 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9967 11:46:01.474495 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9968 11:46:01.474618 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9969 11:46:01.474745 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9970 11:46:01.474868 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9971 11:46:01.474989 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9972 11:46:01.475116 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9973 11:46:01.475241 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9974 11:46:01.475363 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9975 11:46:01.475480 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9976 11:46:01.475604 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9977 11:46:01.475706 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9978 11:46:01.475796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9979 11:46:01.475883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9980 11:46:01.475978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9981 11:46:01.476067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9982 11:46:01.476158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9983 11:46:01.476249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9984 11:46:01.476336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9985 11:46:01.476425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9986 11:46:01.476543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9987 11:46:01.476639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9988 11:46:01.476744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9989 11:46:01.476844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9990 11:46:01.476949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9991 11:46:01.477052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9992 11:46:01.477151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9993 11:46:01.477249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9994 11:46:01.477348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9995 11:46:01.477444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9996 11:46:01.477543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9997 11:46:01.477638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9998 11:46:01.477737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9999 11:46:01.477831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10000 11:46:01.477926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10001 11:46:01.478021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10002 11:46:01.478117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10003 11:46:01.478311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10004 11:46:01.478456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10005 11:46:01.478555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10006 11:46:01.478654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10007 11:46:01.478749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10008 11:46:01.478844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10009 11:46:01.478939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10010 11:46:01.479037 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10011 11:46:01.479131 INFO: [APUAPC] vio 0
10012 11:46:01.479226 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10013 11:46:01.479321 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10014 11:46:01.479443 INFO: [APUAPC] D0_APC_0: 0x400510
10015 11:46:01.479537 INFO: [APUAPC] D0_APC_1: 0x0
10016 11:46:01.482071 INFO: [APUAPC] D0_APC_2: 0x1540
10017 11:46:01.482174 INFO: [APUAPC] D0_APC_3: 0x0
10018 11:46:01.488342 INFO: [APUAPC] D1_APC_0: 0xffffffff
10019 11:46:01.491562 INFO: [APUAPC] D1_APC_1: 0xffffffff
10020 11:46:01.495373 INFO: [APUAPC] D1_APC_2: 0x3fffff
10021 11:46:01.495469 INFO: [APUAPC] D1_APC_3: 0x0
10022 11:46:01.498530 INFO: [APUAPC] D2_APC_0: 0xffffffff
10023 11:46:01.504785 INFO: [APUAPC] D2_APC_1: 0xffffffff
10024 11:46:01.508088 INFO: [APUAPC] D2_APC_2: 0x3fffff
10025 11:46:01.508208 INFO: [APUAPC] D2_APC_3: 0x0
10026 11:46:01.511858 INFO: [APUAPC] D3_APC_0: 0xffffffff
10027 11:46:01.514982 INFO: [APUAPC] D3_APC_1: 0xffffffff
10028 11:46:01.518116 INFO: [APUAPC] D3_APC_2: 0x3fffff
10029 11:46:01.522024 INFO: [APUAPC] D3_APC_3: 0x0
10030 11:46:01.525129 INFO: [APUAPC] D4_APC_0: 0xffffffff
10031 11:46:01.528232 INFO: [APUAPC] D4_APC_1: 0xffffffff
10032 11:46:01.531784 INFO: [APUAPC] D4_APC_2: 0x3fffff
10033 11:46:01.534929 INFO: [APUAPC] D4_APC_3: 0x0
10034 11:46:01.538076 INFO: [APUAPC] D5_APC_0: 0xffffffff
10035 11:46:01.541087 INFO: [APUAPC] D5_APC_1: 0xffffffff
10036 11:46:01.544936 INFO: [APUAPC] D5_APC_2: 0x3fffff
10037 11:46:01.548128 INFO: [APUAPC] D5_APC_3: 0x0
10038 11:46:01.551058 INFO: [APUAPC] D6_APC_0: 0xffffffff
10039 11:46:01.554442 INFO: [APUAPC] D6_APC_1: 0xffffffff
10040 11:46:01.558225 INFO: [APUAPC] D6_APC_2: 0x3fffff
10041 11:46:01.561583 INFO: [APUAPC] D6_APC_3: 0x0
10042 11:46:01.564727 INFO: [APUAPC] D7_APC_0: 0xffffffff
10043 11:46:01.567898 INFO: [APUAPC] D7_APC_1: 0xffffffff
10044 11:46:01.571245 INFO: [APUAPC] D7_APC_2: 0x3fffff
10045 11:46:01.574471 INFO: [APUAPC] D7_APC_3: 0x0
10046 11:46:01.578087 INFO: [APUAPC] D8_APC_0: 0xffffffff
10047 11:46:01.581340 INFO: [APUAPC] D8_APC_1: 0xffffffff
10048 11:46:01.584626 INFO: [APUAPC] D8_APC_2: 0x3fffff
10049 11:46:01.587693 INFO: [APUAPC] D8_APC_3: 0x0
10050 11:46:01.590808 INFO: [APUAPC] D9_APC_0: 0xffffffff
10051 11:46:01.594229 INFO: [APUAPC] D9_APC_1: 0xffffffff
10052 11:46:01.597817 INFO: [APUAPC] D9_APC_2: 0x3fffff
10053 11:46:01.600970 INFO: [APUAPC] D9_APC_3: 0x0
10054 11:46:01.604023 INFO: [APUAPC] D10_APC_0: 0xffffffff
10055 11:46:01.607731 INFO: [APUAPC] D10_APC_1: 0xffffffff
10056 11:46:01.610789 INFO: [APUAPC] D10_APC_2: 0x3fffff
10057 11:46:01.614008 INFO: [APUAPC] D10_APC_3: 0x0
10058 11:46:01.617215 INFO: [APUAPC] D11_APC_0: 0xffffffff
10059 11:46:01.620602 INFO: [APUAPC] D11_APC_1: 0xffffffff
10060 11:46:01.624177 INFO: [APUAPC] D11_APC_2: 0x3fffff
10061 11:46:01.627232 INFO: [APUAPC] D11_APC_3: 0x0
10062 11:46:01.630730 INFO: [APUAPC] D12_APC_0: 0xffffffff
10063 11:46:01.633920 INFO: [APUAPC] D12_APC_1: 0xffffffff
10064 11:46:01.637608 INFO: [APUAPC] D12_APC_2: 0x3fffff
10065 11:46:01.640620 INFO: [APUAPC] D12_APC_3: 0x0
10066 11:46:01.643867 INFO: [APUAPC] D13_APC_0: 0xffffffff
10067 11:46:01.647081 INFO: [APUAPC] D13_APC_1: 0xffffffff
10068 11:46:01.650433 INFO: [APUAPC] D13_APC_2: 0x3fffff
10069 11:46:01.653707 INFO: [APUAPC] D13_APC_3: 0x0
10070 11:46:01.657385 INFO: [APUAPC] D14_APC_0: 0xffffffff
10071 11:46:01.660544 INFO: [APUAPC] D14_APC_1: 0xffffffff
10072 11:46:01.663568 INFO: [APUAPC] D14_APC_2: 0x3fffff
10073 11:46:01.666828 INFO: [APUAPC] D14_APC_3: 0x0
10074 11:46:01.670020 INFO: [APUAPC] D15_APC_0: 0xffffffff
10075 11:46:01.673171 INFO: [APUAPC] D15_APC_1: 0xffffffff
10076 11:46:01.676443 INFO: [APUAPC] D15_APC_2: 0x3fffff
10077 11:46:01.679627 INFO: [APUAPC] D15_APC_3: 0x0
10078 11:46:01.683667 INFO: [APUAPC] APC_CON: 0x4
10079 11:46:01.686972 INFO: [NOCDAPC] D0_APC_0: 0x0
10080 11:46:01.690190 INFO: [NOCDAPC] D0_APC_1: 0x0
10081 11:46:01.693294 INFO: [NOCDAPC] D1_APC_0: 0x0
10082 11:46:01.696276 INFO: [NOCDAPC] D1_APC_1: 0xfff
10083 11:46:01.700262 INFO: [NOCDAPC] D2_APC_0: 0x0
10084 11:46:01.702934 INFO: [NOCDAPC] D2_APC_1: 0xfff
10085 11:46:01.703203 INFO: [NOCDAPC] D3_APC_0: 0x0
10086 11:46:01.706678 INFO: [NOCDAPC] D3_APC_1: 0xfff
10087 11:46:01.709933 INFO: [NOCDAPC] D4_APC_0: 0x0
10088 11:46:01.713179 INFO: [NOCDAPC] D4_APC_1: 0xfff
10089 11:46:01.716311 INFO: [NOCDAPC] D5_APC_0: 0x0
10090 11:46:01.719402 INFO: [NOCDAPC] D5_APC_1: 0xfff
10091 11:46:01.722777 INFO: [NOCDAPC] D6_APC_0: 0x0
10092 11:46:01.726410 INFO: [NOCDAPC] D6_APC_1: 0xfff
10093 11:46:01.729563 INFO: [NOCDAPC] D7_APC_0: 0x0
10094 11:46:01.732501 INFO: [NOCDAPC] D7_APC_1: 0xfff
10095 11:46:01.736570 INFO: [NOCDAPC] D8_APC_0: 0x0
10096 11:46:01.736954 INFO: [NOCDAPC] D8_APC_1: 0xfff
10097 11:46:01.739798 INFO: [NOCDAPC] D9_APC_0: 0x0
10098 11:46:01.742901 INFO: [NOCDAPC] D9_APC_1: 0xfff
10099 11:46:01.746164 INFO: [NOCDAPC] D10_APC_0: 0x0
10100 11:46:01.749391 INFO: [NOCDAPC] D10_APC_1: 0xfff
10101 11:46:01.752984 INFO: [NOCDAPC] D11_APC_0: 0x0
10102 11:46:01.756115 INFO: [NOCDAPC] D11_APC_1: 0xfff
10103 11:46:01.759162 INFO: [NOCDAPC] D12_APC_0: 0x0
10104 11:46:01.762851 INFO: [NOCDAPC] D12_APC_1: 0xfff
10105 11:46:01.765999 INFO: [NOCDAPC] D13_APC_0: 0x0
10106 11:46:01.769210 INFO: [NOCDAPC] D13_APC_1: 0xfff
10107 11:46:01.772265 INFO: [NOCDAPC] D14_APC_0: 0x0
10108 11:46:01.775572 INFO: [NOCDAPC] D14_APC_1: 0xfff
10109 11:46:01.778772 INFO: [NOCDAPC] D15_APC_0: 0x0
10110 11:46:01.782560 INFO: [NOCDAPC] D15_APC_1: 0xfff
10111 11:46:01.785817 INFO: [NOCDAPC] APC_CON: 0x4
10112 11:46:01.789104 INFO: [APUAPC] set_apusys_apc done
10113 11:46:01.789522 INFO: [DEVAPC] devapc_init done
10114 11:46:01.795437 INFO: GICv3 without legacy support detected.
10115 11:46:01.798567 INFO: ARM GICv3 driver initialized in EL3
10116 11:46:01.802400 INFO: Maximum SPI INTID supported: 639
10117 11:46:01.805490 INFO: BL31: Initializing runtime services
10118 11:46:01.811923 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10119 11:46:01.815083 INFO: SPM: enable CPC mode
10120 11:46:01.818316 INFO: mcdi ready for mcusys-off-idle and system suspend
10121 11:46:01.825135 INFO: BL31: Preparing for EL3 exit to normal world
10122 11:46:01.828218 INFO: Entry point address = 0x80000000
10123 11:46:01.831987 INFO: SPSR = 0x8
10124 11:46:01.835862
10125 11:46:01.836391
10126 11:46:01.836825
10127 11:46:01.839672 Starting depthcharge on Spherion...
10128 11:46:01.840120
10129 11:46:01.840493 Wipe memory regions:
10130 11:46:01.840872
10131 11:46:01.843714 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10132 11:46:01.844397 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10133 11:46:01.845094 Setting prompt string to ['asurada:']
10134 11:46:01.845684 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10135 11:46:01.846542 [0x00000040000000, 0x00000054600000)
10136 11:46:01.965563
10137 11:46:01.966063 [0x00000054660000, 0x00000080000000)
10138 11:46:02.225473
10139 11:46:02.226032 [0x000000821a7280, 0x000000ffe64000)
10140 11:46:02.969681
10141 11:46:02.969826 [0x00000100000000, 0x00000240000000)
10142 11:46:04.859757
10143 11:46:04.862786 Initializing XHCI USB controller at 0x11200000.
10144 11:46:05.844899
10145 11:46:05.845424 R8152: Initializing
10146 11:46:05.845807
10147 11:46:05.848125 Version 9 (ocp_data = 6010)
10148 11:46:05.848631
10149 11:46:05.851288 R8152: Done initializing
10150 11:46:05.851829
10151 11:46:05.852258 Adding net device
10152 11:46:06.372483
10153 11:46:06.375711 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10154 11:46:06.376334
10155 11:46:06.376827
10156 11:46:06.377256
10157 11:46:06.378152 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10159 11:46:06.479713 asurada: tftpboot 192.168.201.1 10742248/tftp-deploy-n56okomi/kernel/image.itb 10742248/tftp-deploy-n56okomi/kernel/cmdline
10160 11:46:06.479913 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10161 11:46:06.480027 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10162 11:46:06.483895 tftpboot 192.168.201.1 10742248/tftp-deploy-n56okomi/kernel/image.itp-deploy-n56okomi/kernel/cmdline
10163 11:46:06.483983
10164 11:46:06.484050 Waiting for link
10165 11:46:06.686053
10166 11:46:06.686192 done.
10167 11:46:06.686263
10168 11:46:06.686326 MAC: f4:f5:e8:50:de:0a
10169 11:46:06.686388
10170 11:46:06.689245 Sending DHCP discover... done.
10171 11:46:06.689332
10172 11:46:06.693162 Waiting for reply... done.
10173 11:46:06.693297
10174 11:46:06.696346 Sending DHCP request... done.
10175 11:46:06.696451
10176 11:46:06.776677 Waiting for reply... done.
10177 11:46:06.776809
10178 11:46:06.776880 My ip is 192.168.201.14
10179 11:46:06.776943
10180 11:46:06.779891 The DHCP server ip is 192.168.201.1
10181 11:46:06.779978
10182 11:46:06.786207 TFTP server IP predefined by user: 192.168.201.1
10183 11:46:06.786319
10184 11:46:06.793458 Bootfile predefined by user: 10742248/tftp-deploy-n56okomi/kernel/image.itb
10185 11:46:06.793541
10186 11:46:06.796742 Sending tftp read request... done.
10187 11:46:06.796846
10188 11:46:06.800056 Waiting for the transfer...
10189 11:46:06.800179
10190 11:46:07.042333 00000000 ################################################################
10191 11:46:07.042506
10192 11:46:07.282877 00080000 ################################################################
10193 11:46:07.283018
10194 11:46:07.506526 00100000 ################################################################
10195 11:46:07.506661
10196 11:46:07.734710 00180000 ################################################################
10197 11:46:07.734848
10198 11:46:07.968627 00200000 ################################################################
10199 11:46:07.968768
10200 11:46:08.202215 00280000 ################################################################
10201 11:46:08.202380
10202 11:46:08.442063 00300000 ################################################################
10203 11:46:08.442224
10204 11:46:08.712795 00380000 ################################################################
10205 11:46:08.712944
10206 11:46:09.018441 00400000 ################################################################
10207 11:46:09.018581
10208 11:46:09.264342 00480000 ################################################################
10209 11:46:09.264501
10210 11:46:09.513878 00500000 ################################################################
10211 11:46:09.514015
10212 11:46:09.740422 00580000 ################################################################
10213 11:46:09.740589
10214 11:46:10.014281 00600000 ################################################################
10215 11:46:10.014443
10216 11:46:10.282930 00680000 ################################################################
10217 11:46:10.283064
10218 11:46:10.524050 00700000 ################################################################
10219 11:46:10.524213
10220 11:46:10.793376 00780000 ################################################################
10221 11:46:10.793521
10222 11:46:11.044771 00800000 ################################################################
10223 11:46:11.044956
10224 11:46:11.307970 00880000 ################################################################
10225 11:46:11.308099
10226 11:46:11.581806 00900000 ################################################################
10227 11:46:11.581979
10228 11:46:11.841185 00980000 ################################################################
10229 11:46:11.841349
10230 11:46:12.085268 00a00000 ################################################################
10231 11:46:12.085401
10232 11:46:12.309138 00a80000 ################################################################
10233 11:46:12.309274
10234 11:46:12.532154 00b00000 ################################################################
10235 11:46:12.532318
10236 11:46:12.766152 00b80000 ################################################################
10237 11:46:12.766311
10238 11:46:12.989465 00c00000 ################################################################
10239 11:46:12.989609
10240 11:46:13.215029 00c80000 ################################################################
10241 11:46:13.215186
10242 11:46:13.434580 00d00000 ################################################################
10243 11:46:13.434741
10244 11:46:13.659842 00d80000 ################################################################
10245 11:46:13.660024
10246 11:46:13.893787 00e00000 ################################################################
10247 11:46:13.893945
10248 11:46:14.113667 00e80000 ################################################################
10249 11:46:14.113805
10250 11:46:14.335477 00f00000 ################################################################
10251 11:46:14.335630
10252 11:46:14.560534 00f80000 ################################################################
10253 11:46:14.560694
10254 11:46:14.788217 01000000 ################################################################
10255 11:46:14.788379
10256 11:46:15.018310 01080000 ################################################################
10257 11:46:15.018450
10258 11:46:15.248460 01100000 ################################################################
10259 11:46:15.248612
10260 11:46:15.469220 01180000 ################################################################
10261 11:46:15.469365
10262 11:46:15.687386 01200000 ################################################################
10263 11:46:15.687560
10264 11:46:15.913024 01280000 ################################################################
10265 11:46:15.913220
10266 11:46:16.146583 01300000 ################################################################
10267 11:46:16.146765
10268 11:46:16.381839 01380000 ################################################################
10269 11:46:16.382016
10270 11:46:16.609165 01400000 ################################################################
10271 11:46:16.609314
10272 11:46:16.833015 01480000 ################################################################
10273 11:46:16.833152
10274 11:46:17.058119 01500000 ################################################################
10275 11:46:17.058260
10276 11:46:17.279132 01580000 ################################################################
10277 11:46:17.279298
10278 11:46:17.503495 01600000 ################################################################
10279 11:46:17.503658
10280 11:46:17.733873 01680000 ################################################################
10281 11:46:17.734009
10282 11:46:17.958637 01700000 ################################################################
10283 11:46:17.958776
10284 11:46:18.196100 01780000 ################################################################
10285 11:46:18.196265
10286 11:46:18.427334 01800000 ################################################################
10287 11:46:18.427478
10288 11:46:18.650946 01880000 ################################################################
10289 11:46:18.651100
10290 11:46:18.877997 01900000 ################################################################
10291 11:46:18.878157
10292 11:46:19.110889 01980000 ################################################################
10293 11:46:19.111024
10294 11:46:19.350572 01a00000 ################################################################
10295 11:46:19.350708
10296 11:46:19.507763 01a80000 ########################################### done.
10297 11:46:19.507895
10298 11:46:19.511717 The bootfile was 28137702 bytes long.
10299 11:46:19.511807
10300 11:46:19.514847 Sending tftp read request... done.
10301 11:46:19.514930
10302 11:46:19.514996 Waiting for the transfer...
10303 11:46:19.515058
10304 11:46:19.518020 00000000 # done.
10305 11:46:19.518108
10306 11:46:19.524979 Command line loaded dynamically from TFTP file: 10742248/tftp-deploy-n56okomi/kernel/cmdline
10307 11:46:19.525083
10308 11:46:19.541192 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742248/extract-nfsrootfs-g598sjkx,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10309 11:46:19.541308
10310 11:46:19.544717 Loading FIT.
10311 11:46:19.544797
10312 11:46:19.547963 Image ramdisk-1 has 17645382 bytes.
10313 11:46:19.548048
10314 11:46:19.548135 Image fdt-1 has 46924 bytes.
10315 11:46:19.548200
10316 11:46:19.551230 Image kernel-1 has 10443363 bytes.
10317 11:46:19.551322
10318 11:46:19.560821 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10319 11:46:19.560921
10320 11:46:19.577434 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10321 11:46:19.577551
10322 11:46:19.584391 Choosing best match conf-1 for compat google,spherion-rev2.
10323 11:46:19.588189
10324 11:46:19.592042 Connected to device vid:did:rid of 1ae0:0028:00
10325 11:46:19.599415
10326 11:46:19.602691 tpm_get_response: command 0x17b, return code 0x0
10327 11:46:19.602800
10328 11:46:19.606008 ec_init: CrosEC protocol v3 supported (256, 248)
10329 11:46:19.609811
10330 11:46:19.613575 tpm_cleanup: add release locality here.
10331 11:46:19.613687
10332 11:46:19.613785 Shutting down all USB controllers.
10333 11:46:19.616846
10334 11:46:19.616922 Removing current net device
10335 11:46:19.617003
10336 11:46:19.623247 Exiting depthcharge with code 4 at timestamp: 47191118
10337 11:46:19.623366
10338 11:46:19.626521 LZMA decompressing kernel-1 to 0x821a6718
10339 11:46:19.626625
10340 11:46:19.630146 LZMA decompressing kernel-1 to 0x40000000
10341 11:46:20.941126
10342 11:46:20.941289 jumping to kernel
10343 11:46:20.942031 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
10344 11:46:20.942194 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10345 11:46:20.942296 Setting prompt string to ['Linux version [0-9]']
10346 11:46:20.942391 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10347 11:46:20.942486 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10348 11:46:21.491313
10349 11:46:21.494999 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10350 11:46:21.498539 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
10351 11:46:21.498633 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10352 11:46:21.498721 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10353 11:46:21.498800 Using line separator: #'\n'#
10354 11:46:21.498861 No login prompt set.
10355 11:46:21.498924 Parsing kernel messages
10356 11:46:21.498980 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10357 11:46:21.499081 [login-action] Waiting for messages, (timeout 00:04:05)
10358 11:46:21.518224 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10359 11:46:21.521388 [ 0.000000] random: crng init done
10360 11:46:21.527992 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10361 11:46:21.528078 [ 0.000000] efi: UEFI not found.
10362 11:46:21.537902 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10363 11:46:21.544368 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10364 11:46:21.553935 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10365 11:46:21.563998 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10366 11:46:21.567188 [ 0.000000] NUMA: No NUMA configuration found
10367 11:46:21.577322 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10368 11:46:21.580742 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10369 11:46:21.583687 [ 0.000000] Zone ranges:
10370 11:46:21.590693 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10371 11:46:21.593795 [ 0.000000] DMA32 empty
10372 11:46:21.600456 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10373 11:46:21.603635 [ 0.000000] Movable zone start for each node
10374 11:46:21.606852 [ 0.000000] Early memory node ranges
10375 11:46:21.613962 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10376 11:46:21.620328 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10377 11:46:21.627083 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10378 11:46:21.630064 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10379 11:46:21.636684 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10380 11:46:21.643295 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10381 11:46:21.649709 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10382 11:46:21.656825 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10383 11:46:21.663242 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10384 11:46:21.666396 [ 0.000000] psci: probing for conduit method from DT.
10385 11:46:21.673437 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10386 11:46:21.676505 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10387 11:46:21.682813 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10388 11:46:21.686658 [ 0.000000] psci: SMC Calling Convention v1.2
10389 11:46:21.693026 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10390 11:46:21.695939 [ 0.000000] Detected VIPT I-cache on CPU0
10391 11:46:21.702638 [ 0.000000] CPU features: detected: GIC system register CPU interface
10392 11:46:21.709228 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10393 11:46:21.716039 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10394 11:46:21.722463 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10395 11:46:21.729249 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10396 11:46:21.739293 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10397 11:46:21.742270 [ 0.000000] alternatives: applying boot alternatives
10398 11:46:21.745599 [ 0.000000] Fallback order for Node 0: 0
10399 11:46:21.752685 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10400 11:46:21.755873 [ 0.000000] Policy zone: Normal
10401 11:46:21.775688 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742248/extract-nfsrootfs-g598sjkx,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10402 11:46:21.785460 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10403 11:46:21.791860 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10404 11:46:21.801758 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10405 11:46:21.804931 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10406 11:46:21.811962 [ 0.000000] software IO TLB: area num 8.
10407 11:46:21.818446 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10408 11:46:21.831792 [ 0.000000] Memory: 7953920K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398848K reserved, 32768K cma-reserved)
10409 11:46:21.838249 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10410 11:46:21.844959 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10411 11:46:21.848017 [ 0.000000] rcu: RCU event tracing is enabled.
10412 11:46:21.855017 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10413 11:46:21.861347 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10414 11:46:21.864437 [ 0.000000] Tracing variant of Tasks RCU enabled.
10415 11:46:21.874781 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10416 11:46:21.880999 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10417 11:46:21.884234 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10418 11:46:21.891094 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10419 11:46:21.894225 [ 0.000000] GICv3: 608 SPIs implemented
10420 11:46:21.897825 [ 0.000000] GICv3: 0 Extended SPIs implemented
10421 11:46:21.904164 [ 0.000000] Root IRQ handler: gic_handle_irq
10422 11:46:21.907806 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10423 11:46:21.914454 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10424 11:46:21.927152 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10425 11:46:21.937150 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10426 11:46:21.944009 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10427 11:46:21.950690 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10428 11:46:21.963424 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10429 11:46:21.970429 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10430 11:46:21.973547 [ 0.000947] Console: colour dummy device 80x25
10431 11:46:21.983522 [ 0.001013] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10432 11:46:21.989897 [ 0.001021] pid_max: default: 32768 minimum: 301
10433 11:46:21.993063 [ 0.001061] LSM: Security Framework initializing
10434 11:46:21.999921 [ 0.001169] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 11:46:22.009941 [ 0.001221] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10436 11:46:22.016177 [ 0.002462] cblist_init_generic: Setting adjustable number of callback queues.
10437 11:46:22.023269 [ 0.002473] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 11:46:22.029620 [ 0.002515] cblist_init_generic: Setting shift to 3 and lim to 1.
10439 11:46:22.032746 [ 0.002621] rcu: Hierarchical SRCU implementation.
10440 11:46:22.039603 [ 0.002624] rcu: Max phase no-delay instances is 1000.
10441 11:46:22.042698 [ 0.004251] EFI services will not be available.
10442 11:46:22.049360 [ 0.004469] smp: Bringing up secondary CPUs ...
10443 11:46:22.053068 [ 0.004764] Detected VIPT I-cache on CPU1
10444 11:46:22.059293 [ 0.004836] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10445 11:46:22.066229 [ 0.004868] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10446 11:46:22.069333 [ 0.005213] Detected VIPT I-cache on CPU2
10447 11:46:22.076203 [ 0.005266] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10448 11:46:22.082493 [ 0.005281] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10449 11:46:22.085750 [ 0.005541] Detected VIPT I-cache on CPU3
10450 11:46:22.092687 [ 0.005587] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10451 11:46:22.098902 [ 0.005601] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10452 11:46:22.105715 [ 0.005908] CPU features: detected: Spectre-v4
10453 11:46:22.108830 [ 0.005915] CPU features: detected: Spectre-BHB
10454 11:46:22.112382 [ 0.005920] Detected PIPT I-cache on CPU4
10455 11:46:22.119056 [ 0.005977] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10456 11:46:22.125477 [ 0.005994] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10457 11:46:22.132405 [ 0.006288] Detected PIPT I-cache on CPU5
10458 11:46:22.138855 [ 0.006350] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10459 11:46:22.145686 [ 0.006366] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10460 11:46:22.148750 [ 0.006650] Detected PIPT I-cache on CPU6
10461 11:46:22.155333 [ 0.006717] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10462 11:46:22.161863 [ 0.006734] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10463 11:46:22.165084 [ 0.007029] Detected PIPT I-cache on CPU7
10464 11:46:22.171942 [ 0.007095] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10465 11:46:22.178141 [ 0.007111] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10466 11:46:22.185226 [ 0.007158] smp: Brought up 1 node, 8 CPUs
10467 11:46:22.188349 [ 0.007165] SMP: Total of 8 processors activated.
10468 11:46:22.194843 [ 0.007168] CPU features: detected: 32-bit EL0 Support
10469 11:46:22.201227 [ 0.007171] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10470 11:46:22.207991 [ 0.007173] CPU features: detected: Common not Private translations
10471 11:46:22.214400 [ 0.007175] CPU features: detected: CRC32 instructions
10472 11:46:22.218149 [ 0.007178] CPU features: detected: RCpc load-acquire (LDAPR)
10473 11:46:22.224320 [ 0.007180] CPU features: detected: LSE atomic instructions
10474 11:46:22.231464 [ 0.007182] CPU features: detected: Privileged Access Never
10475 11:46:22.234710 [ 0.007183] CPU features: detected: RAS Extension Support
10476 11:46:22.244093 [ 0.007186] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10477 11:46:22.247801 [ 0.007260] CPU: All CPU(s) started at EL2
10478 11:46:22.250936 [ 0.007262] alternatives: applying system-wide alternatives
10479 11:46:22.254068 [ 0.012227] devtmpfs: initialized
10480 11:46:22.263953 [ 0.017559] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10481 11:46:22.270905 [ 0.017574] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10482 11:46:22.277298 [ 0.018638] pinctrl core: initialized pinctrl subsystem
10483 11:46:22.281047 [ 0.019861] DMI not present or invalid.
10484 11:46:22.287522 [ 0.020197] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10485 11:46:22.293917 [ 0.020937] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10486 11:46:22.304077 [ 0.021157] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10487 11:46:22.310479 [ 0.021343] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10488 11:46:22.316795 [ 0.021369] audit: initializing netlink subsys (disabled)
10489 11:46:22.323738 [ 0.021442] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10490 11:46:22.329963 [ 0.022149] thermal_sys: Registered thermal governor 'step_wise'
10491 11:46:22.336537 [ 0.022152] thermal_sys: Registered thermal governor 'power_allocator'
10492 11:46:22.340467 [ 0.022182] cpuidle: using governor menu
10493 11:46:22.343131 [ 0.022261] NET: Registered PF_QIPCRTR protocol family
10494 11:46:22.353557 [ 0.022381] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10495 11:46:22.356629 [ 0.022471] ASID allocator initialised with 32768 entries
10496 11:46:22.359745 [ 0.023420] Serial: AMBA PL011 UART driver
10497 11:46:22.366527 [ 0.027813] Trying to register duplicate clock ID: 134
10498 11:46:22.369679 [ 0.082085] KASLR enabled
10499 11:46:22.376421 [ 0.086959] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10500 11:46:22.382815 [ 0.086963] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10501 11:46:22.389957 [ 0.086968] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10502 11:46:22.396267 [ 0.086970] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10503 11:46:22.402819 [ 0.086973] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10504 11:46:22.409834 [ 0.086975] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10505 11:46:22.416126 [ 0.086979] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10506 11:46:22.422525 [ 0.086981] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10507 11:46:22.425688 [ 0.087965] ACPI: Interpreter disabled.
10508 11:46:22.429345 [ 0.090280] iommu: Default domain type: Translated
10509 11:46:22.435999 [ 0.090284] iommu: DMA domain TLB invalidation policy: strict mode
10510 11:46:22.439260 [ 0.090473] SCSI subsystem initialized
10511 11:46:22.445608 [ 0.090664] usbcore: registered new interface driver usbfs
10512 11:46:22.448821 [ 0.090681] usbcore: registered new interface driver hub
10513 11:46:22.455501 [ 0.090695] usbcore: registered new device driver usb
10514 11:46:22.459202 [ 0.091514] pps_core: LinuxPPS API ver. 1 registered
10515 11:46:22.469145 [ 0.091517] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10516 11:46:22.472162 [ 0.091524] PTP clock support registered
10517 11:46:22.475763 [ 0.091607] EDAC MC: Ver: 3.0.0
10518 11:46:22.478800 [ 0.093382] FPGA manager framework
10519 11:46:22.485739 [ 0.093423] Advanced Linux Sound Architecture Driver Initialized.
10520 11:46:22.488893 [ 0.093868] vgaarb: loaded
10521 11:46:22.495173 [ 0.094073] clocksource: Switched to clocksource arch_sys_counter
10522 11:46:22.498479 [ 0.094188] VFS: Disk quotas dquot_6.6.0
10523 11:46:22.505453 [ 0.094215] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10524 11:46:22.508700 [ 0.094329] pnp: PnP ACPI: disabled
10525 11:46:22.515262 [ 0.097199] NET: Registered PF_INET protocol family
10526 11:46:22.521620 [ 0.097680] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10527 11:46:22.531518 [ 0.102206] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10528 11:46:22.538484 [ 0.102280] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10529 11:46:22.544831 [ 0.102294] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10530 11:46:22.554661 [ 0.102866] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10531 11:46:22.557804 [ 0.105004] TCP: Hash tables configured (established 65536 bind 65536)
10532 11:46:22.567890 [ 0.105118] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 11:46:22.574255 [ 0.105310] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10534 11:46:22.578000 [ 0.105570] NET: Registered PF_UNIX/PF_LOCAL protocol family
10535 11:46:22.584717 [ 0.105864] RPC: Registered named UNIX socket transport module.
10536 11:46:22.590987 [ 0.105868] RPC: Registered udp transport module.
10537 11:46:22.594220 [ 0.105870] RPC: Registered tcp transport module.
10538 11:46:22.601296 [ 0.105872] RPC: Registered tcp NFSv4.1 backchannel transport module.
10539 11:46:22.604391 [ 0.105883] PCI: CLS 0 bytes, default 64
10540 11:46:22.607538 [ 0.106121] Unpacking initramfs...
10541 11:46:22.617273 [ 0.114698] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10542 11:46:22.623930 [ 0.114926] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10543 11:46:22.627048 [ 0.115362] kvm [1]: IPA Size Limit: 40 bits
10544 11:46:22.634005 [ 0.115386] kvm [1]: GICv3: no GICV resource entry
10545 11:46:22.637110 [ 0.115390] kvm [1]: disabling GICv2 emulation
10546 11:46:22.643559 [ 0.115404] kvm [1]: GIC system register CPU interface enabled
10547 11:46:22.647546 [ 0.115497] kvm [1]: vgic interrupt IRQ18
10548 11:46:22.653973 [ 0.115602] kvm [1]: VHE mode initialized successfully
10549 11:46:22.657117 [ 0.116509] Initialise system trusted keyrings
10550 11:46:22.663410 [ 0.116609] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10551 11:46:22.670091 [ 0.119916] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10552 11:46:22.673745 [ 0.120215] NFS: Registering the id_resolver key type
10553 11:46:22.680292 [ 0.120231] Key type id_resolver registered
10554 11:46:22.683393 [ 0.120234] Key type id_legacy registered
10555 11:46:22.690093 [ 0.120274] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10556 11:46:22.696836 [ 0.120278] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10557 11:46:22.703138 [ 0.120353] 9p: Installing v9fs 9p2000 file system support
10558 11:46:22.706428 [ 0.152283] Key type asymmetric registered
10559 11:46:22.709567 [ 0.152290] Asymmetric key parser 'x509' registered
10560 11:46:22.719840 [ 0.152342] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10561 11:46:22.723115 [ 0.152346] io scheduler mq-deadline registered
10562 11:46:22.726191 [ 0.152352] io scheduler kyber registered
10563 11:46:22.729424 [ 0.166326] EINJ: ACPI disabled.
10564 11:46:22.739655 [ 0.188593] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 11:46:22.749277 [ 0.188738] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 11:46:22.756337 [ 0.198652] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10567 11:46:22.762565 [ 0.200032] printk: console [ttyS0] disabled
10568 11:46:22.769552 [ 0.220190] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10569 11:46:22.775814 [ 0.833766] Freeing initrd memory: 17228K
10570 11:46:22.779424 [ 0.835550] printk: console [ttyS0] enabled
10571 11:46:22.785790 [ 1.510598] SuperH (H)SCI(F) driver initialized
10572 11:46:22.788762 [ 1.515593] msm_serial: driver initialized
10573 11:46:22.801653 [ 1.524176] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10574 11:46:22.811662 [ 1.532462] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10575 11:46:22.818018 [ 1.540744] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10576 11:46:22.828148 [ 1.549113] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10577 11:46:22.834557 [ 1.557558] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10578 11:46:22.844822 [ 1.566010] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10579 11:46:22.850907 [ 1.574294] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10580 11:46:22.861220 [ 1.582831] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10581 11:46:22.867438 [ 1.591112] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10582 11:46:22.876844 [ 1.605956] loop: module loaded
10583 11:46:22.886249 [ 1.611652] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10584 11:46:22.908758 [ 1.634394] mtk-pmic-keys: Failed to locate of_node [id: -1]
10585 11:46:22.915415 [ 1.640720] megasas: 07.719.03.00-rc1
10586 11:46:22.924284 [ 1.649904] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10587 11:46:22.933383 [ 1.658171] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10588 11:46:22.939981 [ 1.660906] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10589 11:46:22.949326 [ 1.674963] tun: Universal TUN/TAP device driver, 1.6
10590 11:46:22.956914 [ 1.675782] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10591 11:46:22.960809 [ 1.680754] thunder_xcv, ver 1.0
10592 11:46:22.960912 [ 1.689426] thunder_bgx, ver 1.0
10593 11:46:22.965253 [ 1.692661] nicpf, ver 1.0
10594 11:46:22.972956 [ 1.696430] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10595 11:46:22.990201 [ 1.703646] hns3: Copyright (c) 2017 Huawei Corporation.
10596 11:46:22.990515 [ 1.708970] hclge is initializing
10597 11:46:22.990592 [ 1.712283] e1000: Intel(R) PRO/1000 Network Driver
10598 11:46:22.995194 [ 1.717152] e1000: Copyright (c) 1999-2006 Intel Corporation.
10599 11:46:23.000682 [ 1.722906] e1000e: Intel(R) PRO/1000 Network Driver
10600 11:46:23.007821 [ 1.727861] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10601 11:46:23.013051 [ 1.733787] igb: Intel(R) Gigabit Ethernet Network Driver
10602 11:46:23.016572 [ 1.739177] igb: Copyright (c) 2007-2014 Intel Corporation.
10603 11:46:23.020177 [ 1.744757] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10604 11:46:23.030113 [ 1.746357] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10605 11:46:23.036330 [ 1.751015] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10606 11:46:23.039607 [ 1.751307] sky2: driver version 1.30
10607 11:46:23.046525 [ 1.772419] VFIO - User Level meta-driver version: 0.3
10608 11:46:23.054693 [ 1.780368] usbcore: registered new interface driver usb-storage
10609 11:46:23.061666 [ 1.786555] usbcore: registered new device driver onboard-usb-hub
10610 11:46:23.069984 [ 1.795383] mt6397-rtc mt6359-rtc: registered as rtc0
10611 11:46:23.079634 [ 1.800588] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:46:23 UTC (1686829583)
10612 11:46:23.082862 [ 1.809909] i2c_dev: i2c /dev entries driver
10613 11:46:23.098981 [ 1.821187] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10614 11:46:23.105293 [ 1.831121] sdhci: Secure Digital Host Controller Interface driver
10615 11:46:23.112144 [ 1.837297] sdhci: Copyright(c) Pierre Ossman
10616 11:46:23.118829 [ 1.842463] Synopsys Designware Multimedia Card Interface Driver
10617 11:46:23.121961 [ 1.848917] mmc0: CQHCI version 5.10
10618 11:46:23.128483 [ 1.849355] sdhci-pltfm: SDHCI platform and OF driver helper
10619 11:46:23.135139 [ 1.860230] ledtrig-cpu: registered to indicate activity on CPUs
10620 11:46:23.142201 [ 1.867268] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10621 11:46:23.148786 [ 1.874410] usbcore: registered new interface driver usbhid
10622 11:46:23.152052 [ 1.879978] usbhid: USB HID core driver
10623 11:46:23.158742 [ 1.883978] spi_master spi0: will run message pump with realtime priority
10624 11:46:23.204450 [ 1.923228] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10625 11:46:23.219470 [ 1.938231] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10626 11:46:23.226583 [ 1.951609] mmc0: Command Queue Engine enabled
10627 11:46:23.229547 [ 1.955188] cros-ec-spi spi0.0: Chrome EC device registered
10628 11:46:23.236772 [ 1.956076] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10629 11:46:23.243437 [ 1.968798] mmcblk0: mmc0:0001 DA4128 116 GiB
10630 11:46:23.254911 [ 1.977565] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10631 11:46:23.261806 [ 1.982158] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10632 11:46:23.268438 [ 1.988715] NET: Registered PF_PACKET protocol family
10633 11:46:23.271748 [ 1.993953] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10634 11:46:23.274953 [ 1.997434] 9pnet: Installing 9P2000 support
10635 11:46:23.281362 [ 2.003203] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10636 11:46:23.284986 [ 2.006588] Key type dns_resolver registered
10637 11:46:23.291069 [ 2.012255] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10638 11:46:23.294321 [ 2.016310] registered taskstats version 1
10639 11:46:23.301242 [ 2.026158] Loading compiled-in X.509 certificates
10640 11:46:23.334044 [ 2.053035] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10641 11:46:23.343645 [ 2.063510] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 11:46:23.353773 [ 2.075844] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10643 11:46:23.364963 [ 2.090674] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10644 11:46:23.371362 [ 2.097238] xhci-mtk 11200000.usb: xHCI Host Controller
10645 11:46:23.378557 [ 2.102479] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10646 11:46:23.388127 [ 2.110199] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10647 11:46:23.394532 [ 2.119382] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10648 11:46:23.398469 [ 2.125216] xhci-mtk 11200000.usb: xHCI Host Controller
10649 11:46:23.408052 [ 2.130439] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10650 11:46:23.415019 [ 2.137830] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10651 11:46:23.417953 [ 2.145430] hub 1-0:1.0: USB hub found
10652 11:46:23.421247 [ 2.149201] hub 1-0:1.0: 1 port detected
10653 11:46:23.431346 [ 2.153287] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10654 11:46:23.434583 [ 2.161789] hub 2-0:1.0: USB hub found
10655 11:46:23.437799 [ 2.165558] hub 2-0:1.0: 1 port detected
10656 11:46:23.447024 [ 2.172706] mtk-msdc 11f70000.mmc: Got CD GPIO
10657 11:46:23.463911 [ 2.186332] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10658 11:46:23.470335 [ 2.194093] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10659 11:46:23.480550 [ 2.201810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10660 11:46:23.487453 [ 2.211215] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10661 11:46:23.497284 [ 2.219037] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10662 11:46:23.503548 [ 2.226810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10663 11:46:23.510570 [ 2.234464] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10664 11:46:23.520155 [ 2.242025] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10665 11:46:23.527243 [ 2.249585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10666 11:46:23.537462 [ 2.259986] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10667 11:46:23.544554 [ 2.268097] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10668 11:46:23.554239 [ 2.276189] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10669 11:46:23.560842 [ 2.284272] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10670 11:46:23.570474 [ 2.292355] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10671 11:46:23.577294 [ 2.300437] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10672 11:46:23.587295 [ 2.308520] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10673 11:46:23.593567 [ 2.316602] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10674 11:46:23.603856 [ 2.324684] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10675 11:46:23.610268 [ 2.332767] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10676 11:46:23.616656 [ 2.340850] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10677 11:46:23.626849 [ 2.348932] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10678 11:46:23.633654 [ 2.357015] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10679 11:46:23.643363 [ 2.365097] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10680 11:46:23.649823 [ 2.373181] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10681 11:46:23.656253 [ 2.381836] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10682 11:46:23.663160 [ 2.389050] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10683 11:46:23.670007 [ 2.395922] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10684 11:46:23.676855 [ 2.402825] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10685 11:46:23.684229 [ 2.409905] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10686 11:46:23.694281 [ 2.416576] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10687 11:46:23.703893 [ 2.425456] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10688 11:46:23.714078 [ 2.434323] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10689 11:46:23.720939 [ 2.443365] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10690 11:46:23.731027 [ 2.452578] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10691 11:46:23.740283 [ 2.461792] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10692 11:46:23.750290 [ 2.470658] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10693 11:46:23.757280 [ 2.479877] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10694 11:46:23.767416 [ 2.488744] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10695 11:46:23.776826 [ 2.497784] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10696 11:46:23.787176 [ 2.507689] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10697 11:46:23.796988 [ 2.518804] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10698 11:46:23.803532 [ 2.528472] Trying to probe devices needed for running init ...
10699 11:46:23.824502 [ 2.550335] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10700 11:46:23.854841 [ 2.580743] hub 2-1:1.0: USB hub found
10701 11:46:23.857948 [ 2.584873] hub 2-1:1.0: 3 ports detected
10702 11:46:23.976350 [ 2.702314] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10703 11:46:24.131814 [ 2.857756] hub 1-1:1.0: USB hub found
10704 11:46:24.135510 [ 2.861755] hub 1-1:1.0: 4 ports detected
10705 11:46:24.455616 [ 3.178206] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10706 11:46:24.586603 [ 3.312264] hub 1-1.1:1.0: USB hub found
10707 11:46:24.589822 [ 3.316283] hub 1-1.1:1.0: 4 ports detected
10708 11:46:24.703256 [ 3.426123] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10709 11:46:24.836503 [ 3.562547] hub 1-1.4:1.0: USB hub found
10710 11:46:24.839643 [ 3.566946] hub 1-1.4:1.0: 2 ports detected
10711 11:46:24.915760 [ 3.638346] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10712 11:46:25.100167 [ 3.822347] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10713 11:46:25.197603 [ 3.910546] usb 1-1.1.4: device descriptor read/64, error -32
10714 11:46:25.376335 [ 4.102549] usb 1-1.1.4: device descriptor read/64, error -32
10715 11:46:25.571664 [ 4.294347] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10716 11:46:25.760181 [ 4.482345] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10717 11:46:25.845078 [ 4.570557] usb 1-1.1.4: device descriptor read/64, error -32
10718 11:46:26.037187 [ 4.762584] usb 1-1.1.4: device descriptor read/64, error -32
10719 11:46:26.148553 [ 4.874767] usb 1-1.1-port4: attempt power cycle
10720 11:46:26.235764 [ 4.958347] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10721 11:46:26.759634 [ 5.482347] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10722 11:46:26.763330 [ 5.489541] usb 1-1.1.4: Device not responding to setup address.
10723 11:46:26.976785 [ 5.702618] usb 1-1.1.4: Device not responding to setup address.
10724 11:46:27.188391 [ 5.914364] usb 1-1.1.4: device not accepting address 10, error -71
10725 11:46:27.275937 [ 5.998345] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10726 11:46:27.279048 [ 6.005537] usb 1-1.1.4: Device not responding to setup address.
10727 11:46:27.492351 [ 6.218608] usb 1-1.1.4: Device not responding to setup address.
10728 11:46:27.704370 [ 6.430334] usb 1-1.1.4: device not accepting address 11, error -71
10729 11:46:27.711163 [ 6.437157] usb 1-1.1-port4: unable to enumerate USB device
10730 11:46:36.088988 [ 14.818901] ALSA device list:
10731 11:46:36.091847 [ 14.821876] No soundcards found.
10732 11:46:36.107242 [ 14.834076] Freeing unused kernel memory: 8384K
10733 11:46:36.110231 [ 14.838713] Run /init as init process
10734 11:46:36.120825 Loading, please wait...
10735 11:46:36.140865 Starting version 247.3-7+deb11u2
10736 11:46:36.460101 [ 15.184043] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10737 11:46:36.476031 [ 15.203139] remoteproc remoteproc0: scp is available
10738 11:46:36.486115 [ 15.208827] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10739 11:46:36.492595 [ 15.218460] remoteproc remoteproc0: powering up scp
10740 11:46:36.502583 [ 15.224294] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10741 11:46:36.509533 [ 15.224425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 11:46:36.515700 [ 15.234123] remoteproc remoteproc0: request_firmware failed: -2
10743 11:46:36.522564 [ 15.241766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 11:46:36.532629 [ 15.255685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 11:46:36.549222 [ 15.272934] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10746 11:46:36.559520 [ 15.282304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 11:46:36.565792 [ 15.290214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 11:46:36.572790 [ 15.291312] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10749 11:46:36.582683 [ 15.298095] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 11:46:36.589211 [ 15.302979] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10751 11:46:36.596144 [ 15.302979] Fallback method does not support PEC.
10752 11:46:36.602359 [ 15.305522] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10753 11:46:36.609149 [ 15.306604] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10754 11:46:36.613048 [ 15.309513] mc: Linux media interface: v0.10
10755 11:46:36.622902 [ 15.313180] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10756 11:46:36.629177 [ 15.313244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 11:46:36.639088 [ 15.320293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10758 11:46:36.645329 [ 15.326402] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10759 11:46:36.652358 [ 15.334791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 11:46:36.658894 [ 15.336927] videodev: Linux video capture interface: v2.00
10761 11:46:36.665679 [ 15.337901] usbcore: registered new interface driver r8152
10762 11:46:36.672144 [ 15.346816] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10763 11:46:36.682314 [ 15.353573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 11:46:36.691809 [ 15.390540] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10765 11:46:36.698923 [ 15.391302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 11:46:36.708407 [ 15.397215] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10767 11:46:36.715363 [ 15.405244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 11:46:36.721563 [ 15.418599] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10769 11:46:36.731395 [ 15.422895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 11:46:36.738332 [ 15.426511] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10771 11:46:36.744490 [ 15.462644] usbcore: registered new interface driver cdc_ether
10772 11:46:36.751514 [ 15.464097] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10773 11:46:36.757974 [ 15.464104] pci_bus 0000:00: root bus resource [bus 00-ff]
10774 11:46:36.764451 [ 15.464114] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10775 11:46:36.774617 [ 15.464119] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10776 11:46:36.781285 [ 15.464156] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10777 11:46:36.788085 [ 15.464181] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10778 11:46:36.791064 [ 15.464272] pci 0000:00:00.0: supports D1 D2
10779 11:46:36.797728 [ 15.464276] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10780 11:46:36.807818 [ 15.465843] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10781 11:46:36.810820 [ 15.465961] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10782 11:46:36.820994 [ 15.465992] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10783 11:46:36.827621 [ 15.466013] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10784 11:46:36.833859 [ 15.466032] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10785 11:46:36.837673 [ 15.466166] pci 0000:01:00.0: supports D1 D2
10786 11:46:36.844007 [ 15.466170] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10787 11:46:36.853398 [ 15.471353] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 11:46:36.857043 [ 15.472183] Bluetooth: Core ver 2.22
10789 11:46:36.860023 [ 15.472255] NET: Registered PF_BLUETOOTH protocol family
10790 11:46:36.866565 [ 15.472260] Bluetooth: HCI device and connection manager initialized
10791 11:46:36.873419 [ 15.472283] Bluetooth: HCI socket layer initialized
10792 11:46:36.877014 [ 15.472290] Bluetooth: L2CAP socket layer initialized
10793 11:46:36.883323 [ 15.472302] Bluetooth: SCO socket layer initialized
10794 11:46:36.889851 [ 15.478138] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10795 11:46:36.896437 [ 15.483737] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 11:46:36.903409 [ 15.484373] usbcore: registered new interface driver r8153_ecm
10797 11:46:36.909798 [ 15.485266] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10798 11:46:36.923370 [ 15.487154] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10799 11:46:36.926520 [ 15.487434] usbcore: registered new interface driver uvcvideo
10800 11:46:36.936545 [ 15.489268] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10801 11:46:36.942834 [ 15.496098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10802 11:46:36.949989 [ 15.496109] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10803 11:46:36.959406 [ 15.496115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10804 11:46:36.966292 [ 15.496156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10805 11:46:36.973050 [ 15.513050] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10806 11:46:36.979832 [ 15.519072] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10807 11:46:36.989136 [ 15.519114] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10808 11:46:36.995671 [ 15.519133] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10809 11:46:37.002191 [ 15.519826] usbcore: registered new interface driver btusb
10810 11:46:37.012117 [ 15.520746] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10811 11:46:37.018996 [ 15.520758] Bluetooth: hci0: Failed to load firmware file (-2)
10812 11:46:37.022456 [ 15.520762] Bluetooth: hci0: Failed to set up firmware (-2)
10813 11:46:37.032565 [ 15.520767] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10814 11:46:37.041850 [ 15.533777] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10815 11:46:37.048782 [ 15.538515] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10816 11:46:37.058669 [ 15.544095] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10817 11:46:37.061863 [ 15.551221] pci 0000:00:00.0: PCI bridge to [bus 01]
10818 11:46:37.068613 [ 15.610385] r8152 1-1.1.1:1.0 eth0: v1.12.13
10819 11:46:37.074837 [ 15.614308] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10820 11:46:37.082124 [ 15.614481] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10821 11:46:37.088035 [ 15.630933] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10822 11:46:37.091616 [ 15.635423] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10823 11:46:37.098301 [ 15.825198] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10824 11:46:37.132688 [ 15.856277] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10825 11:46:37.148420 [ 15.875502] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10826 11:46:37.159117 [ 15.882321] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10827 11:46:37.165685 [ 15.890949] cfg80211: failed to load regulatory.db
10828 11:46:37.210518 [ 15.933950] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10829 11:46:37.216862 [ 15.941225] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10830 11:46:37.240796 [ 15.967655] mt7921e 0000:01:00.0: ASIC revision: 79610010
10831 11:46:37.346282 [ 16.066220] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10832 11:46:37.362983 Begin: Loading essential drivers ... done.
10833 11:46:37.366855 Begin: Running /scripts/init-premount ... done.
10834 11:46:37.373161 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10835 11:46:37.383210 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10836 11:46:37.386242 Device /sys/class/net/enxf4f5e850de0a found
10837 11:46:37.386669 done.
10838 11:46:37.430369 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10839 11:46:37.464597 [ 16.184862] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 11:46:37.583845 [ 16.304058] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10841 11:46:37.699388 [ 16.419930] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10842 11:46:37.815457 [ 16.535833] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 11:46:37.931624 [ 16.651730] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10844 11:46:38.047195 [ 16.767825] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 11:46:38.162871 [ 16.883643] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10846 11:46:38.279493 [ 16.999671] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10847 11:46:38.395004 [ 17.115554] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10848 11:46:38.502348 [ 17.229504] mt7921e 0000:01:00.0: hardware init failed
10849 11:46:38.543766 [ 17.270533] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10850 11:46:38.573620 IP-Config: no response after 2 secs - giving up
10851 11:46:38.626176 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10852 11:46:40.697033 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10853 11:46:40.703862 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10854 11:46:40.710230 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10855 11:46:40.717250 host : mt8192-asurada-spherion-r0-cbg-9
10856 11:46:40.723420 domain : lava-rack
10857 11:46:40.730196 rootserver: 192.168.201.1 rootpath:
10858 11:46:40.730620 filename :
10859 11:46:40.785199 done.
10860 11:46:40.788292 Begin: Running /scripts/nfs-bottom ... done.
10861 11:46:40.809120 Begin: Running /scripts/init-bottom ... done.
10862 11:46:41.976868 [ 20.704427] NET: Registered PF_INET6 protocol family
10863 11:46:41.983669 [ 20.711157] Segment Routing with IPv6
10864 11:46:41.986561 [ 20.714859] In-situ OAM (IOAM) with IPv6
10865 11:46:42.091080 [ 20.802404] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10866 11:46:42.097799 [ 20.825819] systemd[1]: Detected architecture arm64.
10867 11:46:42.117130
10868 11:46:42.120225 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10869 11:46:42.120309
10870 11:46:42.136149 [ 20.863856] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10871 11:46:43.455266 [ 22.180032] systemd[1]: Queued start job for default target Graphical Interface.
10872 11:46:43.479784 [ 22.207396] systemd[1]: Created slice system-getty.slice.
10873 11:46:43.486168 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10874 11:46:43.503676 [ 22.231000] systemd[1]: Created slice system-modprobe.slice.
10875 11:46:43.510143 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10876 11:46:43.527031 [ 22.254949] systemd[1]: Created slice system-serial\x2dgetty.slice.
10877 11:46:43.534107 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10878 11:46:43.551918 [ 22.279361] systemd[1]: Created slice User and Session Slice.
10879 11:46:43.558111 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10880 11:46:43.578556 [ 22.302915] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10881 11:46:43.585531 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10882 11:46:43.602080 [ 22.326452] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10883 11:46:43.608788 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10884 11:46:43.629695 [ 22.350459] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10885 11:46:43.635772 [ 22.362149] systemd[1]: Reached target Local Encrypted Volumes.
10886 11:46:43.642570 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10887 11:46:43.655338 [ 22.382705] systemd[1]: Reached target Paths.
10888 11:46:43.658483 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10889 11:46:43.675014 [ 22.402376] systemd[1]: Reached target Remote File Systems.
10890 11:46:43.681223 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10891 11:46:43.694413 [ 22.422328] systemd[1]: Reached target Slices.
10892 11:46:43.698177 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10893 11:46:43.714674 [ 22.442390] systemd[1]: Reached target Swap.
10894 11:46:43.717863 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10895 11:46:43.734948 [ 22.462696] systemd[1]: Listening on initctl Compatibility Named Pipe.
10896 11:46:43.744915 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10897 11:46:43.751661 [ 22.477912] systemd[1]: Listening on Journal Audit Socket.
10898 11:46:43.757920 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10899 11:46:43.772072 [ 22.499525] systemd[1]: Listening on Journal Socket (/dev/log).
10900 11:46:43.778441 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10901 11:46:43.795244 [ 22.523186] systemd[1]: Listening on Journal Socket.
10902 11:46:43.802082 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10903 11:46:43.816606 [ 22.544182] systemd[1]: Listening on Network Service Netlink Socket.
10904 11:46:43.826461 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10905 11:46:43.841340 [ 22.568675] systemd[1]: Listening on udev Control Socket.
10906 11:46:43.847561 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10907 11:46:43.862857 [ 22.590622] systemd[1]: Listening on udev Kernel Socket.
10908 11:46:43.869611 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10909 11:46:43.919111 [ 22.646521] systemd[1]: Mounting Huge Pages File System...
10910 11:46:43.925306 Mounting [0;1;39mHuge Pages File System[0m...
10911 11:46:43.940681 [ 22.668533] systemd[1]: Mounting POSIX Message Queue File System...
10912 11:46:43.946944 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10913 11:46:43.964592 [ 22.692541] systemd[1]: Mounting Kernel Debug File System...
10914 11:46:43.971445 Mounting [0;1;39mKernel Debug File System[0m...
10915 11:46:43.990102 [ 22.714563] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10916 11:46:44.003233 [ 22.727819] systemd[1]: Starting Create list of static device nodes for the current kernel...
10917 11:46:44.009532 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10918 11:46:44.029432 [ 22.757024] systemd[1]: Starting Load Kernel Module configfs...
10919 11:46:44.036149 Starting [0;1;39mLoad Kernel Module configfs[0m...
10920 11:46:44.053125 [ 22.780952] systemd[1]: Starting Load Kernel Module drm...
10921 11:46:44.060068 Starting [0;1;39mLoad Kernel Module drm[0m...
10922 11:46:44.077285 [ 22.804986] systemd[1]: Starting Load Kernel Module fuse...
10923 11:46:44.084186 Starting [0;1;39mLoad Kernel Module fuse[0m...
10924 11:46:44.113553 [ 22.840830] fuse: init (API version 7.37)
10925 11:46:44.122821 [ 22.846635] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10926 11:46:44.132623 [ 22.860207] systemd[1]: Starting Journal Service...
10927 11:46:44.135735 Starting [0;1;39mJournal Service[0m...
10928 11:46:44.157234 [ 22.884972] systemd[1]: Starting Load Kernel Modules...
10929 11:46:44.163702 Starting [0;1;39mLoad Kernel Modules[0m...
10930 11:46:44.183887 [ 22.908827] systemd[1]: Starting Remount Root and Kernel File Systems...
10931 11:46:44.190320 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10932 11:46:44.205806 [ 22.933676] systemd[1]: Starting Coldplug All udev Devices...
10933 11:46:44.211964 Starting [0;1;39mColdplug All udev Devices[0m...
10934 11:46:44.229636 [ 22.957610] systemd[1]: Mounted Huge Pages File System.
10935 11:46:44.236175 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10936 11:46:44.250614 [ 22.978744] systemd[1]: Mounted POSIX Message Queue File System.
10937 11:46:44.257437 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10938 11:46:44.275140 [ 23.002800] systemd[1]: Mounted Kernel Debug File System.
10939 11:46:44.288087 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu[ 23.012176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 11:46:44.288190 g File System[0m.
10941 11:46:44.311370 [ 23.035234] systemd[1]: Finished Create list of static device nodes for the current kernel.
10942 11:46:44.321115 [[0;32m OK [0m] Finished [0[ 23.045217] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 11:46:44.327915 ;1;39mCreate list of st… nodes for the current kernel[0m.
10944 11:46:44.343404 [ 23.071508] systemd[1]: modprobe@configfs.service: Succeeded.
10945 11:46:44.349721 [ 23.077884] systemd[1]: Finished Load Kernel Module configfs.
10946 11:46:44.356671 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10947 11:46:44.371662 [ 23.096581] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 11:46:44.378595 [ 23.106429] systemd[1]: modprobe@drm.service: Succeeded.
10949 11:46:44.385031 [ 23.112354] systemd[1]: Finished Load Kernel Module drm.
10950 11:46:44.392179 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10951 11:46:44.403591 [ 23.127865] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:46:44.409504 [ 23.137659] systemd[1]: modprobe@fuse.service: Succeeded.
10953 11:46:44.416461 [ 23.143907] systemd[1]: Finished Load Kernel Module fuse.
10954 11:46:44.422690 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10955 11:46:44.435545 [ 23.160493] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 11:46:44.442850 [ 23.170699] systemd[1]: Finished Load Kernel Modules.
10957 11:46:44.449333 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10958 11:46:44.463871 [ 23.191714] systemd[1]: Finished Remount Root and Kernel File Systems.
10959 11:46:44.473812 [ 23.192873] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 11:46:44.480280 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10961 11:46:44.507780 [ 23.232578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:46:44.541195 [ 23.266210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 11:46:44.554246 [ 23.282233] systemd[1]: Mounting FUSE Control File System...
10964 11:46:44.560681 Mounting [0;1;39mFUSE Control File System[0m...
10965 11:46:44.570701 [ 23.295778] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 11:46:44.579201 [ 23.307299] systemd[1]: Mounting Kernel Configuration File System...
10967 11:46:44.585511 Mounting [0;1;39mKernel Configuration File System[0m...
10968 11:46:44.600823 [ 23.325497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 11:46:44.614422 [ 23.339371] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10970 11:46:44.624634 [ 23.348081] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10971 11:46:44.655263 [ 23.382922] systemd[1]: Starting Load/Save Random Seed...
10972 11:46:44.661629 Starting [0;1;39mLoad/Save Random Seed[0m...
10973 11:46:44.677998 [ 23.405519] systemd[1]: Starting Apply Kernel Variables...
10974 11:46:44.684131 Starting [0;1;39mApply Kernel Variables[0m...
10975 11:46:44.701937 [ 23.429652] systemd[1]: Starting Create System Users...
10976 11:46:44.708701 Starting [0;1;39mCreate System Users[0m...
10977 11:46:44.724804 [ 23.452597] systemd[1]: Started Journal Service.
10978 11:46:44.727942 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10979 11:46:44.744472 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10980 11:46:44.762414 [ 23.479716] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10981 11:46:44.768684 [ 23.495115] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10982 11:46:44.775035 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10983 11:46:44.792419 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10984 11:46:44.815354 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10985 11:46:44.830735 See 'systemctl status systemd-udev-trigger.service' for details.
10986 11:46:44.875690 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10987 11:46:44.916572 [ 23.640735] systemd-journald[294]: Received client request to flush runtime journal.
10988 11:46:47.100449 [[0m[0;31m* [0m] (1 of 4) A start job is running for…Persistent Storage (3s / 1min 31s)
10989 11:46:47.214194 M
10990 11:46:47.217412 [K[[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10991 11:46:51.391847 [K[[0;1;31m*[0m[0;31m* [0m] (1 of 3) A start job is running for…Persistent Storage (6s / 1min 31s)
10992 11:46:51.392591 M
10993 11:46:51.393231 [K[[0;31m*[0;1;31m*[0m[0;31m* [0m] (1 of 3) A start job is running for…Persistent Storage (6s / 1min 31s)
10994 11:46:51.393824 M
10995 11:46:51.394409 [K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] (2 of 3) A start job is running for /dev/ttyS0 (7s / 1min 30s)
10996 11:46:51.394970 M
10997 11:46:51.395258 [K[ [0;31m*[0;1;31m*[0m[0;31m* [0m] (2 of 3) A start job is running for /dev/ttyS0 (7s / 1min 30s)
10998 11:46:51.697075 M
10999 11:46:51.703596 [K[[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11000 11:46:53.063108 [K[[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11001 11:46:53.138917 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11002 11:46:53.251536 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11003 11:46:53.266085 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11004 11:46:53.281568 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11005 11:46:53.322702 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11006 11:46:53.349593 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11007 11:46:53.599796 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11008 11:46:53.646228 Starting [0;1;39mNetwork Service[0m...
11009 11:46:53.779861 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11010 11:46:54.173869 [ 32.801103] power_supply_show_property: 5 callbacks suppressed
11011 11:46:54.174073 [ 32.801175] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 11:46:54.174188 [ 32.816662] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11013 11:46:54.174324 [ 32.839754] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 11:46:54.174460 [ 32.876078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 11:46:54.182819 [ 32.908660] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 11:46:54.210914 [ 32.936560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11017 11:46:54.243983 [ 32.970158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11018 11:46:54.254339 [ 32.983384] remoteproc remoteproc0: powering up scp
11019 11:46:54.275410 [ 33.001173] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11020 11:46:54.282382 [ 33.011306] remoteproc remoteproc0: request_firmware failed: -2
11021 11:46:54.289270 [ 33.017261] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11022 11:46:54.304385 [ 33.030184] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 11:46:54.310636 Starting [0;1;39mNetwork Time Synchronization[0m...
11024 11:46:54.338122 [ 33.063640] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11025 11:46:54.370483 [ 33.096450] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 11:46:54.377293 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11027 11:46:54.409247 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11028 11:46:54.430008 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11029 11:46:54.561259 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11030 11:46:54.632569 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11031 11:46:54.645855 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11032 11:46:54.662001 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11033 11:46:54.677796 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11034 11:46:54.697014 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11035 11:46:54.733227 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11036 11:46:54.757058 Starting [0;1;39mNetwork Name Resolution[0m...
11037 11:46:54.778760 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11038 11:46:54.817785 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11039 11:46:55.156425 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11040 11:46:55.169906 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11041 11:46:55.221732 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11042 11:46:55.263001 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11043 11:46:55.282937 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11044 11:46:55.302778 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11045 11:46:55.320519 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11046 11:46:55.332900 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11047 11:46:55.448365 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11048 11:46:55.449631 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11049 11:46:55.450263 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11050 11:46:55.450842 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11051 11:46:55.483060 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11052 11:46:55.596718 Starting [0;1;39mUser Login Management[0m...
11053 11:46:55.610208 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11054 11:46:55.626507 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11055 11:46:55.641847 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11056 11:46:55.666075 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11057 11:46:55.702026 Starting [0;1;39mPermit User Sessions[0m...
11058 11:46:55.784341 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11059 11:46:55.811061 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11060 11:46:55.857916 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11061 11:46:56.135045 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11062 11:46:56.135955 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11063 11:46:56.163621 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11064 11:46:56.241691 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11065 11:46:56.242531 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11066 11:46:56.243212 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11067 11:46:56.313500 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11068 11:46:56.462860
11069 11:46:56.463027
11070 11:46:56.465868 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11071 11:46:56.465960
11072 11:46:56.469626 debian-bullseye-arm64 login: root (automatic login)
11073 11:46:56.469717
11074 11:46:56.469788
11075 11:46:56.866870 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
11076 11:46:56.867008
11077 11:46:56.873655 The programs included with the Debian GNU/Linux system are free software;
11078 11:46:56.879995 the exact distribution terms for each program are described in the
11079 11:46:56.883706 individual files in /usr/share/doc/*/copyright.
11080 11:46:56.883784
11081 11:46:56.889960 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11082 11:46:56.893159 permitted by applicable law.
11083 11:46:57.729838 Matched prompt #10: / #
11085 11:46:57.730165 Setting prompt string to ['/ #']
11086 11:46:57.730259 end: 2.2.5.1 login-action (duration 00:00:36) [common]
11088 11:46:57.730453 end: 2.2.5 auto-login-action (duration 00:00:37) [common]
11089 11:46:57.730541 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
11090 11:46:57.730612 Setting prompt string to ['/ #']
11091 11:46:57.730672 Forcing a shell prompt, looking for ['/ #']
11093 11:46:57.780893 / #
11094 11:46:57.781036 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11095 11:46:57.781128 Waiting using forced prompt support (timeout 00:02:30)
11096 11:46:57.785468
11097 11:46:57.785742 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11098 11:46:57.785834 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
11100 11:46:57.886202 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742248/extract-nfsrootfs-g598sjkx'
11101 11:46:57.891155 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742248/extract-nfsrootfs-g598sjkx'
11103 11:46:57.991706 / # export NFS_SERVER_IP='192.168.201.1'
11104 11:46:57.996454 export NFS_SERVER_IP='192.168.201.1'
11105 11:46:57.996775 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11106 11:46:57.996877 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
11107 11:46:57.996970 end: 2 depthcharge-action (duration 00:01:31) [common]
11108 11:46:57.997059 start: 3 lava-test-retry (timeout 00:06:32) [common]
11109 11:46:57.997149 start: 3.1 lava-test-shell (timeout 00:06:32) [common]
11110 11:46:57.997224 Using namespace: common
11112 11:46:58.097577 / # #
11113 11:46:58.097755 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11114 11:46:58.102570 #
11115 11:46:58.102839 Using /lava-10742248
11117 11:46:58.203205 / # export SHELL=/bin/bash
11118 11:46:58.208069 export SHELL=/bin/bash
11120 11:46:58.308581 / # . /lava-10742248/environment
11121 11:46:58.313914 . /lava-10742248/environment
11123 11:46:58.418716 / # /lava-10742248/bin/lava-test-runner /lava-10742248/0
11124 11:46:58.418893 Test shell timeout: 10s (minimum of the action and connection timeout)
11125 11:46:58.424040 /lava-10742248/bin/lava-test-runner /lava-10742248/0
11126 11:46:58.632902 + export TESTRUN_ID=0_timesync-off
11127 11:46:58.636036 + TESTRUN_ID=0_timesync-off
11128 11:46:58.639034 + cd /lava-10742248/0/tests/0_timesync-off
11129 11:46:58.642141 ++ cat uuid
11130 11:46:58.642253 + UUID=10742248_1.6.2.3.1
11131 11:46:58.645828 + set +x
11132 11:46:58.648961 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10742248_1.6.2.3.1>
11133 11:46:58.649246 Received signal: <STARTRUN> 0_timesync-off 10742248_1.6.2.3.1
11134 11:46:58.649350 Starting test lava.0_timesync-off (10742248_1.6.2.3.1)
11135 11:46:58.649474 Skipping test definition patterns.
11136 11:46:58.652115 + systemctl stop systemd-timesyncd
11137 11:46:58.679500 + set +x
11138 11:46:58.682639 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10742248_1.6.2.3.1>
11139 11:46:58.682920 Received signal: <ENDRUN> 0_timesync-off 10742248_1.6.2.3.1
11140 11:46:58.683034 Ending use of test pattern.
11141 11:46:58.683134 Ending test lava.0_timesync-off (10742248_1.6.2.3.1), duration 0.03
11143 11:46:59.275801 + export TESTRUN_ID=1_kselftest-rtc
11144 11:46:59.276183 + TESTRUN_ID=1_kselftest-rtc
11145 11:46:59.276653 + cd /lava-10742248/0/tests/1_kselftest-rtc
11146 11:46:59.279420 ++ cat uuid
11147 11:46:59.282652 + UUID=10742248_1.6.2.3.5
11148 11:46:59.282821 + set +x
11149 11:46:59.289510 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10742248_1.6.2.3.5>
11150 11:46:59.289859 Received signal: <STARTRUN> 1_kselftest-rtc 10742248_1.6.2.3.5
11151 11:46:59.289986 Starting test lava.1_kselftest-rtc (10742248_1.6.2.3.5)
11152 11:46:59.290121 Skipping test definition patterns.
11153 11:46:59.292556 + cd ./automated/linux/kselftest/
11154 11:46:59.387644 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11155 11:46:59.417534 INFO: install_deps skipped
11156 11:46:59.554198 --2023-06-15 11:46:59-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11157 11:46:59.554685 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11158 11:46:59.656864 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11159 11:46:59.783156 HTTP request sent, awaiting response... 200 OK
11160 11:46:59.786106 Length: 2884276 (2.8M) [application/octet-stream]
11161 11:46:59.789524 Saving to: 'kselftest.tar.xz'
11162 11:46:59.789634
11163 11:46:59.789736
11164 11:47:00.732291 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11165 11:47:00.732580 kselftest.tar.xz 1%[ ] 46.39K 186KB/s
11166 11:47:00.732749 kselftest.tar.xz 3%[ ] 100.13K 167KB/s
11167 11:47:01.143069 kselftest.tar.xz 7%[> ] 220.32K 259KB/s
11168 11:47:01.753168 kselftest.tar.xz 29%[====> ] 829.78K 611KB/s
11169 11:47:01.980277 kselftest.tar.xz 76%[==============> ] 2.11M 1.07MB/s
11170 11:47:02.014644 kselftest.tar.xz 85%[================> ] 2.35M 1.07MB/s
11171 11:47:02.021260 kselftest.tar.xz 100%[===================>] 2.75M 1.23MB/s in 2.2s
11172 11:47:02.021350
11173 11:47:02.271045 2023-06-15 11:47:02 (1.23 MB/s) - 'kselftest.tar.xz' saved [2884276/2884276]
11174 11:47:02.271240
11175 11:47:07.316812 [ 46.050480] vpu: disabling
11176 11:47:07.319954 [ 46.053272] vproc2: disabling
11177 11:47:07.323082 [ 46.056295] vproc1: disabling
11178 11:47:07.326183 [ 46.059298] vaud18: disabling
11179 11:47:07.329939 [ 46.062443] vsram_others: disabling
11180 11:47:07.333012 [ 46.066047] va09: disabling
11181 11:47:07.336564 [ 46.068893] vsram_md: disabling
11182 11:47:07.339520 [ 46.072158] Vgpu: disabling
11183 11:48:17.274263 skiplist:
11184 11:48:17.277448 ========================================
11185 11:48:17.280952 ========================================
11186 11:48:17.313617 rtc:rtctest
11187 11:48:17.631123 ============== Tests to run ===============
11188 11:48:17.631277 rtc:rtctest
11189 11:48:17.634317 ===========End Tests to run ===============
11190 11:48:17.716617 [ 116.455436] kselftest: Running tests in rtc
11191 11:48:17.724842 TAP version 13
11192 11:48:17.735773 1..1
11193 11:48:17.762338 # selftests: rtc: rtctest
11194 11:48:18.102366 # TAP version 13
11195 11:48:18.102501 # 1..8
11196 11:48:18.105620 # # Starting 8 tests from 2 test cases.
11197 11:48:18.109313 # # RUN rtc.date_read ...
11198 11:48:18.115891 # # rtctest.c:49:date_read:Current RTC date/time is 15/06/2023 11:48:17.
11199 11:48:18.119048 # # OK rtc.date_read
11200 11:48:18.122205 # ok 1 rtc.date_read
11201 11:48:18.125421 # # RUN rtc.date_read_loop ...
11202 11:48:18.135600 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11203 11:48:48.011130 # # rtctest.c:115:date_read_loop:Performed 2659 RTC time reads.
11204 11:48:48.014302 # # OK rtc.date_read_loop
11205 11:48:48.017552 # ok 2 rtc.date_read_loop
11206 11:48:48.020710 # # RUN rtc.uie_read ...
11207 11:48:50.987850 # # OK rtc.uie_read
11208 11:48:50.990694 # ok 3 rtc.uie_read
11209 11:48:50.994632 # # RUN rtc.uie_select ...
11210 11:48:53.987161 # # OK rtc.uie_select
11211 11:48:53.990210 # ok 4 rtc.uie_select
11212 11:48:53.993527 # # RUN rtc.alarm_alm_set ...
11213 11:48:54.000380 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 11:48:57.
11214 11:48:54.003603 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11215 11:48:54.010016 # # alarm_alm_set: Test terminated by assertion
11216 11:48:54.012991 # # FAIL rtc.alarm_alm_set
11217 11:48:54.016778 # not ok 5 rtc.alarm_alm_set
11218 11:48:54.020066 # # RUN rtc.alarm_wkalm_set ...
11219 11:48:54.026338 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 15/06/2023 11:48:57.
11220 11:48:56.989712 # # OK rtc.alarm_wkalm_set
11221 11:48:56.990216 # ok 6 rtc.alarm_wkalm_set
11222 11:48:56.996406 # # RUN rtc.alarm_alm_set_minute ...
11223 11:48:56.999486 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 11:49:00.
11224 11:48:57.006091 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11225 11:48:57.013235 # # alarm_alm_set_minute: Test terminated by assertion
11226 11:48:57.016142 # # FAIL rtc.alarm_alm_set_minute
11227 11:48:57.019786 # not ok 7 rtc.alarm_alm_set_minute
11228 11:48:57.022965 # # RUN rtc.alarm_wkalm_set_minute ...
11229 11:48:57.029839 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 15/06/2023 11:49:00.
11230 11:48:59.989797 # # OK rtc.alarm_wkalm_set_minute
11231 11:48:59.993036 # ok 8 rtc.alarm_wkalm_set_minute
11232 11:48:59.996358 # # FAILED: 6 / 8 tests passed.
11233 11:48:59.999530 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11234 11:49:00.002762 not ok 1 selftests: rtc: rtctest # exit=1
11235 11:49:00.515304 rtc_rtctest_rtc_date_read pass
11236 11:49:00.518395 rtc_rtctest_rtc_date_read_loop pass
11237 11:49:00.522248 rtc_rtctest_rtc_uie_read pass
11238 11:49:00.525291 rtc_rtctest_rtc_uie_select pass
11239 11:49:00.528602 rtc_rtctest_rtc_alarm_alm_set fail
11240 11:49:00.531661 rtc_rtctest_rtc_alarm_wkalm_set pass
11241 11:49:00.535348 rtc_rtctest_rtc_alarm_alm_set_minute fail
11242 11:49:00.538272 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11243 11:49:00.542181 rtc_rtctest fail
11244 11:49:00.545275 + ../../utils/send-to-lava.sh ./output/result.txt
11245 11:49:00.620871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11246 11:49:00.621657 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11248 11:49:00.674406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11249 11:49:00.675149 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11251 11:49:00.728842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11252 11:49:00.729576 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11254 11:49:00.769907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11255 11:49:00.770181 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11257 11:49:00.814932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11258 11:49:00.815200 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11260 11:49:00.853147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11261 11:49:00.853443 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11263 11:49:00.884552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11264 11:49:00.884833 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11266 11:49:00.916713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11267 11:49:00.916994 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11269 11:49:00.954074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11270 11:49:00.954171 + set +x
11271 11:49:00.954409 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11273 11:49:00.960392 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10742248_1.6.2.3.5>
11274 11:49:00.960678 Received signal: <ENDRUN> 1_kselftest-rtc 10742248_1.6.2.3.5
11275 11:49:00.960755 Ending use of test pattern.
11276 11:49:00.960818 Ending test lava.1_kselftest-rtc (10742248_1.6.2.3.5), duration 121.67
11278 11:49:00.961045 ok: lava_test_shell seems to have completed
11279 11:49:00.961173 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11280 11:49:00.961266 end: 3.1 lava-test-shell (duration 00:02:03) [common]
11281 11:49:00.961351 end: 3 lava-test-retry (duration 00:02:03) [common]
11282 11:49:00.961498 start: 4 finalize (timeout 00:04:29) [common]
11283 11:49:00.961602 start: 4.1 power-off (timeout 00:00:30) [common]
11284 11:49:00.961849 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11285 11:49:01.040711 >> Command sent successfully.
11286 11:49:01.045041 Returned 0 in 0 seconds
11287 11:49:01.145879 end: 4.1 power-off (duration 00:00:00) [common]
11289 11:49:01.147424 start: 4.2 read-feedback (timeout 00:04:29) [common]
11291 11:49:01.149812 Listened to connection for namespace 'common' for up to 1s
11292 11:49:02.148778 Finalising connection for namespace 'common'
11293 11:49:02.149447 Disconnecting from shell: Finalise
11294 11:49:02.149869 / #
11295 11:49:02.250839 end: 4.2 read-feedback (duration 00:00:01) [common]
11296 11:49:02.251503 end: 4 finalize (duration 00:00:01) [common]
11297 11:49:02.252059 Cleaning after the job
11298 11:49:02.252817 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/ramdisk
11299 11:49:02.262796 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/kernel
11300 11:49:02.292958 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/dtb
11301 11:49:02.293336 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/nfsrootfs
11302 11:49:02.367452 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742248/tftp-deploy-n56okomi/modules
11303 11:49:02.373249 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742248
11304 11:49:02.905329 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742248
11305 11:49:02.905513 Job finished correctly