Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 43
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 29
- Errors: 0
1 11:39:35.896843 lava-dispatcher, installed at version: 2023.05.1
2 11:39:35.897071 start: 0 validate
3 11:39:35.897211 Start time: 2023-06-15 11:39:35.897204+00:00 (UTC)
4 11:39:35.897347 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:39:35.897483 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 11:39:36.153629 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:39:36.153823 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:40:06.431875 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:40:06.432631 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:40:06.703343 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:40:06.704308 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:40:06.968922 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:40:06.969601 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:40:09.479947 validate duration: 33.58
16 11:40:09.481810 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:40:09.482553 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:40:09.483294 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:40:09.484111 Not decompressing ramdisk as can be used compressed.
20 11:40:09.484781 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/initrd.cpio.gz
21 11:40:09.485317 saving as /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/ramdisk/initrd.cpio.gz
22 11:40:09.485839 total size: 4665397 (4MB)
23 11:40:09.754754 progress 0% (0MB)
24 11:40:09.756230 progress 5% (0MB)
25 11:40:09.757462 progress 10% (0MB)
26 11:40:09.758692 progress 15% (0MB)
27 11:40:09.759929 progress 20% (0MB)
28 11:40:09.761136 progress 25% (1MB)
29 11:40:09.762337 progress 30% (1MB)
30 11:40:09.763580 progress 35% (1MB)
31 11:40:09.764799 progress 40% (1MB)
32 11:40:09.766158 progress 45% (2MB)
33 11:40:09.767420 progress 50% (2MB)
34 11:40:09.768681 progress 55% (2MB)
35 11:40:09.769889 progress 60% (2MB)
36 11:40:09.771125 progress 65% (2MB)
37 11:40:09.772442 progress 70% (3MB)
38 11:40:09.773656 progress 75% (3MB)
39 11:40:09.774865 progress 80% (3MB)
40 11:40:09.776230 progress 85% (3MB)
41 11:40:09.777429 progress 90% (4MB)
42 11:40:09.778626 progress 95% (4MB)
43 11:40:09.779863 progress 100% (4MB)
44 11:40:09.780019 4MB downloaded in 0.29s (15.12MB/s)
45 11:40:09.780174 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:40:09.780414 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:40:09.780506 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:40:09.780594 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:40:09.780727 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:40:09.780818 saving as /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/kernel/Image
52 11:40:09.780895 total size: 47581696 (45MB)
53 11:40:09.780956 No compression specified
54 11:40:09.782113 progress 0% (0MB)
55 11:40:09.794161 progress 5% (2MB)
56 11:40:09.806239 progress 10% (4MB)
57 11:40:09.818214 progress 15% (6MB)
58 11:40:09.830353 progress 20% (9MB)
59 11:40:09.842497 progress 25% (11MB)
60 11:40:09.854502 progress 30% (13MB)
61 11:40:09.866679 progress 35% (15MB)
62 11:40:09.878674 progress 40% (18MB)
63 11:40:09.890766 progress 45% (20MB)
64 11:40:09.902795 progress 50% (22MB)
65 11:40:09.914691 progress 55% (24MB)
66 11:40:09.926964 progress 60% (27MB)
67 11:40:09.938841 progress 65% (29MB)
68 11:40:09.951052 progress 70% (31MB)
69 11:40:09.963272 progress 75% (34MB)
70 11:40:09.975336 progress 80% (36MB)
71 11:40:09.987447 progress 85% (38MB)
72 11:40:09.999477 progress 90% (40MB)
73 11:40:10.011486 progress 95% (43MB)
74 11:40:10.023488 progress 100% (45MB)
75 11:40:10.023654 45MB downloaded in 0.24s (186.93MB/s)
76 11:40:10.023813 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:40:10.024054 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:40:10.024147 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:40:10.024238 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:40:10.024377 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:40:10.024451 saving as /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/dtb/mt8192-asurada-spherion-r0.dtb
83 11:40:10.024513 total size: 46924 (0MB)
84 11:40:10.024573 No compression specified
85 11:40:10.025694 progress 69% (0MB)
86 11:40:10.025963 progress 100% (0MB)
87 11:40:10.026120 0MB downloaded in 0.00s (27.89MB/s)
88 11:40:10.026241 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:40:10.026469 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:40:10.026554 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:40:10.026638 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:40:10.026750 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230609.0/arm64/full.rootfs.tar.xz
94 11:40:10.026819 saving as /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/nfsrootfs/full.rootfs.tar
95 11:40:10.026929 total size: 200816996 (191MB)
96 11:40:10.026990 Using unxz to decompress xz
97 11:40:10.030536 progress 0% (0MB)
98 11:40:10.683577 progress 5% (9MB)
99 11:40:11.189328 progress 10% (19MB)
100 11:40:11.773104 progress 15% (28MB)
101 11:40:12.147553 progress 20% (38MB)
102 11:40:12.465410 progress 25% (47MB)
103 11:40:13.050775 progress 30% (57MB)
104 11:40:13.601433 progress 35% (67MB)
105 11:40:14.199930 progress 40% (76MB)
106 11:40:14.762844 progress 45% (86MB)
107 11:40:15.341487 progress 50% (95MB)
108 11:40:15.985823 progress 55% (105MB)
109 11:40:16.673240 progress 60% (114MB)
110 11:40:16.799962 progress 65% (124MB)
111 11:40:16.939497 progress 70% (134MB)
112 11:40:17.024063 progress 75% (143MB)
113 11:40:17.096242 progress 80% (153MB)
114 11:40:17.173169 progress 85% (162MB)
115 11:40:17.281753 progress 90% (172MB)
116 11:40:17.571811 progress 95% (181MB)
117 11:40:18.168661 progress 100% (191MB)
118 11:40:18.174006 191MB downloaded in 8.15s (23.51MB/s)
119 11:40:18.174290 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:40:18.174566 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:40:18.174679 start: 1.5 download-retry (timeout 00:09:51) [common]
123 11:40:18.174800 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 11:40:18.175028 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:40:18.175130 saving as /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/modules/modules.tar
126 11:40:18.175223 total size: 8555256 (8MB)
127 11:40:18.175317 Using unxz to decompress xz
128 11:40:18.444171 progress 0% (0MB)
129 11:40:18.688529 progress 5% (0MB)
130 11:40:18.713112 progress 10% (0MB)
131 11:40:18.737095 progress 15% (1MB)
132 11:40:18.762530 progress 20% (1MB)
133 11:40:18.786648 progress 25% (2MB)
134 11:40:18.809475 progress 30% (2MB)
135 11:40:18.835097 progress 35% (2MB)
136 11:40:18.859510 progress 40% (3MB)
137 11:40:18.883261 progress 45% (3MB)
138 11:40:18.910568 progress 50% (4MB)
139 11:40:18.935716 progress 55% (4MB)
140 11:40:18.963864 progress 60% (4MB)
141 11:40:18.989601 progress 65% (5MB)
142 11:40:19.014420 progress 70% (5MB)
143 11:40:19.038305 progress 75% (6MB)
144 11:40:19.061810 progress 80% (6MB)
145 11:40:19.085551 progress 85% (6MB)
146 11:40:19.113936 progress 90% (7MB)
147 11:40:19.141130 progress 95% (7MB)
148 11:40:19.166096 progress 100% (8MB)
149 11:40:19.170438 8MB downloaded in 1.00s (8.20MB/s)
150 11:40:19.170717 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:40:19.171011 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:40:19.171120 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:40:19.171235 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:40:24.859993 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10742234/extract-nfsrootfs-751xmu20
156 11:40:24.860182 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
157 11:40:24.860282 start: 1.6.2 lava-overlay (timeout 00:09:45) [common]
158 11:40:24.860452 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0
159 11:40:24.860580 makedir: /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin
160 11:40:24.860681 makedir: /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/tests
161 11:40:24.860779 makedir: /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/results
162 11:40:24.860878 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-add-keys
163 11:40:24.861019 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-add-sources
164 11:40:24.861145 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-background-process-start
165 11:40:24.861269 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-background-process-stop
166 11:40:24.861391 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-common-functions
167 11:40:24.861513 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-echo-ipv4
168 11:40:24.861634 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-install-packages
169 11:40:24.861754 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-installed-packages
170 11:40:24.861873 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-os-build
171 11:40:24.861993 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-probe-channel
172 11:40:24.862114 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-probe-ip
173 11:40:24.862233 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-target-ip
174 11:40:24.862365 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-target-mac
175 11:40:24.862516 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-target-storage
176 11:40:24.862646 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-test-case
177 11:40:24.862770 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-test-event
178 11:40:24.862934 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-test-feedback
179 11:40:24.863073 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-test-raise
180 11:40:24.863206 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-test-reference
181 11:40:24.863331 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-test-runner
182 11:40:24.863456 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-test-set
183 11:40:24.863586 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-test-shell
184 11:40:24.863710 Updating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-add-keys (debian)
185 11:40:24.865281 Updating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-add-sources (debian)
186 11:40:24.879123 Updating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-install-packages (debian)
187 11:40:24.884273 Updating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-installed-packages (debian)
188 11:40:24.903016 Updating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/bin/lava-os-build (debian)
189 11:40:24.916697 Creating /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/environment
190 11:40:24.916947 LAVA metadata
191 11:40:24.917100 - LAVA_JOB_ID=10742234
192 11:40:24.917215 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:40:24.917402 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:45) [common]
194 11:40:24.917521 skipped lava-vland-overlay
195 11:40:24.917655 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:40:24.917778 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:45) [common]
197 11:40:24.917854 skipped lava-multinode-overlay
198 11:40:24.917941 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:40:24.918034 start: 1.6.2.3 test-definition (timeout 00:09:45) [common]
200 11:40:24.918130 Loading test definitions
201 11:40:24.918240 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:45) [common]
202 11:40:24.918326 Using /lava-10742234 at stage 0
203 11:40:24.918665 uuid=10742234_1.6.2.3.1 testdef=None
204 11:40:24.918769 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:40:24.918883 start: 1.6.2.3.2 test-overlay (timeout 00:09:45) [common]
206 11:40:24.919395 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:40:24.919651 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:45) [common]
209 11:40:24.935754 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:40:24.937430 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:45) [common]
212 11:40:24.972452 runner path: /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/0/tests/0_timesync-off test_uuid 10742234_1.6.2.3.1
213 11:40:24.972805 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:40:24.973259 start: 1.6.2.3.5 git-repo-action (timeout 00:09:45) [common]
216 11:40:24.973403 Using /lava-10742234 at stage 0
217 11:40:24.973610 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:40:24.973766 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/0/tests/1_kselftest-tpm2'
219 11:40:37.140710 Running '/usr/bin/git checkout kernelci.org
220 11:40:37.244783 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 11:40:37.245533 uuid=10742234_1.6.2.3.5 testdef=None
222 11:40:37.245694 end: 1.6.2.3.5 git-repo-action (duration 00:00:12) [common]
224 11:40:37.245943 start: 1.6.2.3.6 test-overlay (timeout 00:09:32) [common]
225 11:40:37.246675 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:40:37.246952 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:32) [common]
228 11:40:37.247903 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:40:37.248138 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:32) [common]
231 11:40:37.249048 runner path: /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/0/tests/1_kselftest-tpm2 test_uuid 10742234_1.6.2.3.5
232 11:40:37.249141 BOARD='mt8192-asurada-spherion-r0'
233 11:40:37.249207 BRANCH='cip'
234 11:40:37.249267 SKIPFILE='/dev/null'
235 11:40:37.249326 SKIP_INSTALL='True'
236 11:40:37.249383 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:40:37.249440 TST_CASENAME=''
238 11:40:37.249495 TST_CMDFILES='tpm2'
239 11:40:37.249635 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:40:37.249841 Creating lava-test-runner.conf files
242 11:40:37.249905 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742234/lava-overlay-8hyfzvb0/lava-10742234/0 for stage 0
243 11:40:37.249996 - 0_timesync-off
244 11:40:37.250069 - 1_kselftest-tpm2
245 11:40:37.250163 end: 1.6.2.3 test-definition (duration 00:00:12) [common]
246 11:40:37.250252 start: 1.6.2.4 compress-overlay (timeout 00:09:32) [common]
247 11:40:44.863864 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:40:44.864035 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:25) [common]
249 11:40:44.864131 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:40:44.864237 end: 1.6.2 lava-overlay (duration 00:00:20) [common]
251 11:40:44.864330 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:25) [common]
252 11:40:44.981866 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:40:44.982235 start: 1.6.4 extract-modules (timeout 00:09:24) [common]
254 11:40:44.982353 extracting modules file /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742234/extract-nfsrootfs-751xmu20
255 11:40:45.184494 extracting modules file /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742234/extract-overlay-ramdisk-76vnruut/ramdisk
256 11:40:45.398616 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:40:45.398867 start: 1.6.5 apply-overlay-tftp (timeout 00:09:24) [common]
258 11:40:45.399023 [common] Applying overlay to NFS
259 11:40:45.399096 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742234/compress-overlay-xadaianr/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742234/extract-nfsrootfs-751xmu20
260 11:40:46.348978 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:40:46.349209 start: 1.6.6 configure-preseed-file (timeout 00:09:23) [common]
262 11:40:46.349344 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:40:46.349475 start: 1.6.7 compress-ramdisk (timeout 00:09:23) [common]
264 11:40:46.349601 Building ramdisk /var/lib/lava/dispatcher/tmp/10742234/extract-overlay-ramdisk-76vnruut/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742234/extract-overlay-ramdisk-76vnruut/ramdisk
265 11:40:46.621085 >> 117806 blocks
266 11:40:48.549489 rename /var/lib/lava/dispatcher/tmp/10742234/extract-overlay-ramdisk-76vnruut/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/ramdisk/ramdisk.cpio.gz
267 11:40:48.549971 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:40:48.550139 start: 1.6.8 prepare-kernel (timeout 00:09:21) [common]
269 11:40:48.550287 start: 1.6.8.1 prepare-fit (timeout 00:09:21) [common]
270 11:40:48.550433 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/kernel/Image'
271 11:41:00.817143 Returned 0 in 12 seconds
272 11:41:00.917796 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/kernel/image.itb
273 11:41:01.235611 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:41:01.235971 output: Created: Thu Jun 15 12:41:01 2023
275 11:41:01.236082 output: Image 0 (kernel-1)
276 11:41:01.236181 output: Description:
277 11:41:01.236277 output: Created: Thu Jun 15 12:41:01 2023
278 11:41:01.236373 output: Type: Kernel Image
279 11:41:01.236462 output: Compression: lzma compressed
280 11:41:01.236549 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
281 11:41:01.236639 output: Architecture: AArch64
282 11:41:01.236725 output: OS: Linux
283 11:41:01.236816 output: Load Address: 0x00000000
284 11:41:01.236933 output: Entry Point: 0x00000000
285 11:41:01.237021 output: Hash algo: crc32
286 11:41:01.237106 output: Hash value: cd22d0e5
287 11:41:01.237190 output: Image 1 (fdt-1)
288 11:41:01.237273 output: Description: mt8192-asurada-spherion-r0
289 11:41:01.237360 output: Created: Thu Jun 15 12:41:01 2023
290 11:41:01.237443 output: Type: Flat Device Tree
291 11:41:01.237528 output: Compression: uncompressed
292 11:41:01.237611 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 11:41:01.237694 output: Architecture: AArch64
294 11:41:01.237771 output: Hash algo: crc32
295 11:41:01.237826 output: Hash value: 1df858fa
296 11:41:01.237878 output: Image 2 (ramdisk-1)
297 11:41:01.237931 output: Description: unavailable
298 11:41:01.237983 output: Created: Thu Jun 15 12:41:01 2023
299 11:41:01.238036 output: Type: RAMDisk Image
300 11:41:01.238143 output: Compression: Unknown Compression
301 11:41:01.238229 output: Data Size: 17643229 Bytes = 17229.72 KiB = 16.83 MiB
302 11:41:01.238313 output: Architecture: AArch64
303 11:41:01.238394 output: OS: Linux
304 11:41:01.238476 output: Load Address: unavailable
305 11:41:01.238561 output: Entry Point: unavailable
306 11:41:01.238645 output: Hash algo: crc32
307 11:41:01.238731 output: Hash value: 348a93af
308 11:41:01.238814 output: Default Configuration: 'conf-1'
309 11:41:01.238953 output: Configuration 0 (conf-1)
310 11:41:01.239045 output: Description: mt8192-asurada-spherion-r0
311 11:41:01.239133 output: Kernel: kernel-1
312 11:41:01.239243 output: Init Ramdisk: ramdisk-1
313 11:41:01.239326 output: FDT: fdt-1
314 11:41:01.239408 output: Loadables: kernel-1
315 11:41:01.239492 output:
316 11:41:01.239724 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:41:01.239860 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:41:01.239996 end: 1.6 prepare-tftp-overlay (duration 00:00:42) [common]
319 11:41:01.240105 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:08) [common]
320 11:41:01.240186 No LXC device requested
321 11:41:01.240265 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:41:01.240353 start: 1.8 deploy-device-env (timeout 00:09:08) [common]
323 11:41:01.240434 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:41:01.240506 Checking files for TFTP limit of 4294967296 bytes.
325 11:41:01.241190 end: 1 tftp-deploy (duration 00:00:52) [common]
326 11:41:01.241360 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:41:01.241482 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:41:01.241650 substitutions:
329 11:41:01.241748 - {DTB}: 10742234/tftp-deploy-rew3k99n/dtb/mt8192-asurada-spherion-r0.dtb
330 11:41:01.241842 - {INITRD}: 10742234/tftp-deploy-rew3k99n/ramdisk/ramdisk.cpio.gz
331 11:41:01.241921 - {KERNEL}: 10742234/tftp-deploy-rew3k99n/kernel/Image
332 11:41:01.241979 - {LAVA_MAC}: None
333 11:41:01.242035 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10742234/extract-nfsrootfs-751xmu20
334 11:41:01.242097 - {NFS_SERVER_IP}: 192.168.201.1
335 11:41:01.242154 - {PRESEED_CONFIG}: None
336 11:41:01.242207 - {PRESEED_LOCAL}: None
337 11:41:01.242292 - {RAMDISK}: 10742234/tftp-deploy-rew3k99n/ramdisk/ramdisk.cpio.gz
338 11:41:01.242394 - {ROOT_PART}: None
339 11:41:01.242478 - {ROOT}: None
340 11:41:01.242566 - {SERVER_IP}: 192.168.201.1
341 11:41:01.242649 - {TEE}: None
342 11:41:01.242747 Parsed boot commands:
343 11:41:01.242836 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:41:01.243038 Parsed boot commands: tftpboot 192.168.201.1 10742234/tftp-deploy-rew3k99n/kernel/image.itb 10742234/tftp-deploy-rew3k99n/kernel/cmdline
345 11:41:01.243134 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:41:01.243220 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:41:01.243309 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:41:01.243399 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:41:01.243470 Not connected, no need to disconnect.
350 11:41:01.243551 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:41:01.243637 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:41:01.243706 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
353 11:41:01.247628 Setting prompt string to ['lava-test: # ']
354 11:41:01.247999 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:41:01.248137 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:41:01.248274 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:41:01.248397 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:41:01.248723 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 11:41:06.385923 >> Command sent successfully.
360 11:41:06.388205 Returned 0 in 5 seconds
361 11:41:06.488593 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:41:06.489029 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:41:06.489170 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:41:06.489291 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:41:06.489392 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:41:06.489490 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:41:06.489854 [Enter `^Ec?' for help]
369 11:41:06.660723
370 11:41:06.660880
371 11:41:06.660959 F0: 102B 0000
372 11:41:06.661025
373 11:41:06.661086 F3: 1001 0000 [0200]
374 11:41:06.663616
375 11:41:06.663722 F3: 1001 0000
376 11:41:06.663816
377 11:41:06.663915 F7: 102D 0000
378 11:41:06.664005
379 11:41:06.666967 F1: 0000 0000
380 11:41:06.667039
381 11:41:06.667105 V0: 0000 0000 [0001]
382 11:41:06.667166
383 11:41:06.670348 00: 0007 8000
384 11:41:06.670446
385 11:41:06.670535 01: 0000 0000
386 11:41:06.670627
387 11:41:06.673847 BP: 0C00 0209 [0000]
388 11:41:06.673920
389 11:41:06.673980 G0: 1182 0000
390 11:41:06.674037
391 11:41:06.677481 EC: 0000 0021 [4000]
392 11:41:06.677580
393 11:41:06.677671 S7: 0000 0000 [0000]
394 11:41:06.677758
395 11:41:06.681102 CC: 0000 0000 [0001]
396 11:41:06.681208
397 11:41:06.681301 T0: 0000 0040 [010F]
398 11:41:06.681395
399 11:41:06.681483 Jump to BL
400 11:41:06.681568
401 11:41:06.707636
402 11:41:06.707752
403 11:41:06.707847
404 11:41:06.714333 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:41:06.717757 ARM64: Exception handlers installed.
406 11:41:06.721350 ARM64: Testing exception
407 11:41:06.724915 ARM64: Done test exception
408 11:41:06.731366 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:41:06.741754 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:41:06.748572 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:41:06.758249 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:41:06.764866 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:41:06.775441 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:41:06.785595 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:41:06.792560 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:41:06.810402 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:41:06.813459 WDT: Last reset was cold boot
418 11:41:06.817046 SPI1(PAD0) initialized at 2873684 Hz
419 11:41:06.820264 SPI5(PAD0) initialized at 992727 Hz
420 11:41:06.823883 VBOOT: Loading verstage.
421 11:41:06.830077 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:41:06.833860 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:41:06.837143 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:41:06.840443 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:41:06.847848 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:41:06.854360 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:41:06.865655 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
428 11:41:06.865744
429 11:41:06.865829
430 11:41:06.875488 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:41:06.878349 ARM64: Exception handlers installed.
432 11:41:06.881826 ARM64: Testing exception
433 11:41:06.885317 ARM64: Done test exception
434 11:41:06.888732 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:41:06.892076 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:41:06.906729 Probing TPM: . done!
437 11:41:06.906814 TPM ready after 0 ms
438 11:41:06.912885 Connected to device vid:did:rid of 1ae0:0028:00
439 11:41:06.962609 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 11:41:06.962739 Initialized TPM device CR50 revision 0
441 11:41:06.974360 tlcl_send_startup: Startup return code is 0
442 11:41:06.974447 TPM: setup succeeded
443 11:41:06.985398 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:41:06.994127 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:41:07.006107 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:41:07.015273 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:41:07.018745 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:41:07.022330 in-header: 03 07 00 00 08 00 00 00
449 11:41:07.026233 in-data: aa e4 47 04 13 02 00 00
450 11:41:07.029883 Chrome EC: UHEPI supported
451 11:41:07.036142 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:41:07.040222 in-header: 03 9d 00 00 08 00 00 00
453 11:41:07.043983 in-data: 10 20 20 08 00 00 00 00
454 11:41:07.044069 Phase 1
455 11:41:07.047211 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:41:07.054348 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:41:07.058141 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:41:07.061818 Recovery requested (1009000e)
459 11:41:07.069791 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:41:07.075244 tlcl_extend: response is 0
461 11:41:07.083361 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:41:07.088741 tlcl_extend: response is 0
463 11:41:07.095006 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:41:07.116517 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
465 11:41:07.123638 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:41:07.123724
467 11:41:07.123789
468 11:41:07.134440 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:41:07.134527 ARM64: Exception handlers installed.
470 11:41:07.137851 ARM64: Testing exception
471 11:41:07.141094 ARM64: Done test exception
472 11:41:07.161836 pmic_efuse_setting: Set efuses in 11 msecs
473 11:41:07.165109 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:41:07.168852 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:41:07.176717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:41:07.179897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:41:07.184038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:41:07.190866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:41:07.194838 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:41:07.198508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:41:07.205845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:41:07.209257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:41:07.212260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:41:07.218747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:41:07.222391 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:41:07.225535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:41:07.232890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:41:07.239348 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:41:07.246114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:41:07.249199 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:41:07.255835 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:41:07.263262 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:41:07.266758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:41:07.273664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:41:07.277413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:41:07.284406 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:41:07.291334 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:41:07.294707 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:41:07.301168 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:41:07.304618 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:41:07.311585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:41:07.315514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:41:07.318819 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:41:07.325602 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:41:07.328940 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:41:07.336247 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:41:07.340121 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:41:07.344075 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:41:07.350769 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:41:07.354188 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:41:07.360846 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:41:07.364433 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:41:07.367350 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:41:07.373845 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:41:07.377758 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:41:07.380790 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:41:07.387224 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:41:07.390528 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:41:07.393984 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:41:07.400229 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:41:07.404070 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:41:07.407073 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:41:07.413415 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:41:07.416873 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:41:07.423745 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:41:07.433868 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:41:07.437077 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:41:07.446779 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:41:07.453772 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:41:07.456893 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:41:07.463208 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:41:07.466613 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:41:07.473757 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2b
534 11:41:07.480834 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:41:07.484129 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:41:07.487556 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:41:07.499111 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 11:41:07.502524 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 11:41:07.508790 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 11:41:07.512590 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 11:41:07.516040 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 11:41:07.518694 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 11:41:07.522272 ADC[4]: Raw value=897780 ID=7
544 11:41:07.525669 ADC[3]: Raw value=212700 ID=1
545 11:41:07.528479 RAM Code: 0x71
546 11:41:07.531940 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 11:41:07.538258 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 11:41:07.545954 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 11:41:07.552577 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 11:41:07.556057 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 11:41:07.559250 in-header: 03 07 00 00 08 00 00 00
552 11:41:07.562776 in-data: aa e4 47 04 13 02 00 00
553 11:41:07.566154 Chrome EC: UHEPI supported
554 11:41:07.569597 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 11:41:07.573473 in-header: 03 d5 00 00 08 00 00 00
556 11:41:07.577532 in-data: 98 20 60 08 00 00 00 00
557 11:41:07.581048 MRC: failed to locate region type 0.
558 11:41:07.588266 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 11:41:07.591611 DRAM-K: Running full calibration
560 11:41:07.598701 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 11:41:07.599192 header.status = 0x0
562 11:41:07.601606 header.version = 0x6 (expected: 0x6)
563 11:41:07.604818 header.size = 0xd00 (expected: 0xd00)
564 11:41:07.608675 header.flags = 0x0
565 11:41:07.612141 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 11:41:07.631211 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
567 11:41:07.637778 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 11:41:07.640944 dram_init: ddr_geometry: 2
569 11:41:07.644203 [EMI] MDL number = 2
570 11:41:07.644637 [EMI] Get MDL freq = 0
571 11:41:07.647443 dram_init: ddr_type: 0
572 11:41:07.647874 is_discrete_lpddr4: 1
573 11:41:07.651082 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 11:41:07.651515
575 11:41:07.651857
576 11:41:07.654274 [Bian_co] ETT version 0.0.0.1
577 11:41:07.660507 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 11:41:07.660940
579 11:41:07.664328 dramc_set_vcore_voltage set vcore to 650000
580 11:41:07.667817 Read voltage for 800, 4
581 11:41:07.668252 Vio18 = 0
582 11:41:07.668593 Vcore = 650000
583 11:41:07.668913 Vdram = 0
584 11:41:07.671182 Vddq = 0
585 11:41:07.671657 Vmddr = 0
586 11:41:07.674979 dram_init: config_dvfs: 1
587 11:41:07.678640 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 11:41:07.685862 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 11:41:07.686518 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 11:41:07.693446 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 11:41:07.696891 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 11:41:07.700920 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 11:41:07.701587 MEM_TYPE=3, freq_sel=18
594 11:41:07.704278 sv_algorithm_assistance_LP4_1600
595 11:41:07.707782 ============ PULL DRAM RESETB DOWN ============
596 11:41:07.711112 ========== PULL DRAM RESETB DOWN end =========
597 11:41:07.718568 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 11:41:07.722767 ===================================
599 11:41:07.723341 LPDDR4 DRAM CONFIGURATION
600 11:41:07.726151 ===================================
601 11:41:07.729592 EX_ROW_EN[0] = 0x0
602 11:41:07.730033 EX_ROW_EN[1] = 0x0
603 11:41:07.733365 LP4Y_EN = 0x0
604 11:41:07.733799 WORK_FSP = 0x0
605 11:41:07.734141 WL = 0x2
606 11:41:07.737491 RL = 0x2
607 11:41:07.737930 BL = 0x2
608 11:41:07.740783 RPST = 0x0
609 11:41:07.741267 RD_PRE = 0x0
610 11:41:07.744713 WR_PRE = 0x1
611 11:41:07.745193 WR_PST = 0x0
612 11:41:07.748418 DBI_WR = 0x0
613 11:41:07.748898 DBI_RD = 0x0
614 11:41:07.751418 OTF = 0x1
615 11:41:07.755086 ===================================
616 11:41:07.758875 ===================================
617 11:41:07.759456 ANA top config
618 11:41:07.761734 ===================================
619 11:41:07.765007 DLL_ASYNC_EN = 0
620 11:41:07.768494 ALL_SLAVE_EN = 1
621 11:41:07.768955 NEW_RANK_MODE = 1
622 11:41:07.772158 DLL_IDLE_MODE = 1
623 11:41:07.775230 LP45_APHY_COMB_EN = 1
624 11:41:07.778623 TX_ODT_DIS = 1
625 11:41:07.779204 NEW_8X_MODE = 1
626 11:41:07.781953 ===================================
627 11:41:07.784992 ===================================
628 11:41:07.788338 data_rate = 1600
629 11:41:07.791750 CKR = 1
630 11:41:07.794947 DQ_P2S_RATIO = 8
631 11:41:07.798278 ===================================
632 11:41:07.801535 CA_P2S_RATIO = 8
633 11:41:07.804726 DQ_CA_OPEN = 0
634 11:41:07.808426 DQ_SEMI_OPEN = 0
635 11:41:07.809060 CA_SEMI_OPEN = 0
636 11:41:07.811687 CA_FULL_RATE = 0
637 11:41:07.814681 DQ_CKDIV4_EN = 1
638 11:41:07.817806 CA_CKDIV4_EN = 1
639 11:41:07.821088 CA_PREDIV_EN = 0
640 11:41:07.824603 PH8_DLY = 0
641 11:41:07.825124 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 11:41:07.828287 DQ_AAMCK_DIV = 4
643 11:41:07.831958 CA_AAMCK_DIV = 4
644 11:41:07.834415 CA_ADMCK_DIV = 4
645 11:41:07.837867 DQ_TRACK_CA_EN = 0
646 11:41:07.841326 CA_PICK = 800
647 11:41:07.841757 CA_MCKIO = 800
648 11:41:07.844802 MCKIO_SEMI = 0
649 11:41:07.848089 PLL_FREQ = 3068
650 11:41:07.851122 DQ_UI_PI_RATIO = 32
651 11:41:07.854562 CA_UI_PI_RATIO = 0
652 11:41:07.857801 ===================================
653 11:41:07.861023 ===================================
654 11:41:07.864268 memory_type:LPDDR4
655 11:41:07.864701 GP_NUM : 10
656 11:41:07.867570 SRAM_EN : 1
657 11:41:07.868005 MD32_EN : 0
658 11:41:07.870788 ===================================
659 11:41:07.874708 [ANA_INIT] >>>>>>>>>>>>>>
660 11:41:07.877524 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 11:41:07.881186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 11:41:07.884639 ===================================
663 11:41:07.887574 data_rate = 1600,PCW = 0X7600
664 11:41:07.890922 ===================================
665 11:41:07.894252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 11:41:07.901053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 11:41:07.904165 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 11:41:07.911174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 11:41:07.914590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 11:41:07.917934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 11:41:07.918388 [ANA_INIT] flow start
672 11:41:07.921542 [ANA_INIT] PLL >>>>>>>>
673 11:41:07.922016 [ANA_INIT] PLL <<<<<<<<
674 11:41:07.925185 [ANA_INIT] MIDPI >>>>>>>>
675 11:41:07.928903 [ANA_INIT] MIDPI <<<<<<<<
676 11:41:07.929575 [ANA_INIT] DLL >>>>>>>>
677 11:41:07.932710 [ANA_INIT] flow end
678 11:41:07.936640 ============ LP4 DIFF to SE enter ============
679 11:41:07.940008 ============ LP4 DIFF to SE exit ============
680 11:41:07.943492 [ANA_INIT] <<<<<<<<<<<<<
681 11:41:07.947668 [Flow] Enable top DCM control >>>>>
682 11:41:07.950909 [Flow] Enable top DCM control <<<<<
683 11:41:07.951654 Enable DLL master slave shuffle
684 11:41:07.958279 ==============================================================
685 11:41:07.959413 Gating Mode config
686 11:41:07.964913 ==============================================================
687 11:41:07.968434 Config description:
688 11:41:07.975149 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 11:41:07.981546 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 11:41:07.988210 SELPH_MODE 0: By rank 1: By Phase
691 11:41:07.994974 ==============================================================
692 11:41:07.995475 GAT_TRACK_EN = 1
693 11:41:07.998518 RX_GATING_MODE = 2
694 11:41:08.001851 RX_GATING_TRACK_MODE = 2
695 11:41:08.005194 SELPH_MODE = 1
696 11:41:08.008408 PICG_EARLY_EN = 1
697 11:41:08.011597 VALID_LAT_VALUE = 1
698 11:41:08.018040 ==============================================================
699 11:41:08.021520 Enter into Gating configuration >>>>
700 11:41:08.024689 Exit from Gating configuration <<<<
701 11:41:08.028269 Enter into DVFS_PRE_config >>>>>
702 11:41:08.038223 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 11:41:08.041632 Exit from DVFS_PRE_config <<<<<
704 11:41:08.044983 Enter into PICG configuration >>>>
705 11:41:08.047886 Exit from PICG configuration <<<<
706 11:41:08.050991 [RX_INPUT] configuration >>>>>
707 11:41:08.051474 [RX_INPUT] configuration <<<<<
708 11:41:08.058041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 11:41:08.064198 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 11:41:08.071215 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 11:41:08.074937 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 11:41:08.081209 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 11:41:08.088279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 11:41:08.091140 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 11:41:08.094155 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 11:41:08.101220 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 11:41:08.104478 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 11:41:08.107314 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 11:41:08.113833 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 11:41:08.117662 ===================================
721 11:41:08.118095 LPDDR4 DRAM CONFIGURATION
722 11:41:08.120516 ===================================
723 11:41:08.124023 EX_ROW_EN[0] = 0x0
724 11:41:08.127581 EX_ROW_EN[1] = 0x0
725 11:41:08.128010 LP4Y_EN = 0x0
726 11:41:08.130826 WORK_FSP = 0x0
727 11:41:08.131356 WL = 0x2
728 11:41:08.134088 RL = 0x2
729 11:41:08.134521 BL = 0x2
730 11:41:08.137298 RPST = 0x0
731 11:41:08.137730 RD_PRE = 0x0
732 11:41:08.140547 WR_PRE = 0x1
733 11:41:08.140983 WR_PST = 0x0
734 11:41:08.144214 DBI_WR = 0x0
735 11:41:08.144672 DBI_RD = 0x0
736 11:41:08.147611 OTF = 0x1
737 11:41:08.150636 ===================================
738 11:41:08.153695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 11:41:08.157186 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 11:41:08.163930 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 11:41:08.166979 ===================================
742 11:41:08.167415 LPDDR4 DRAM CONFIGURATION
743 11:41:08.170402 ===================================
744 11:41:08.173915 EX_ROW_EN[0] = 0x10
745 11:41:08.174394 EX_ROW_EN[1] = 0x0
746 11:41:08.177435 LP4Y_EN = 0x0
747 11:41:08.180506 WORK_FSP = 0x0
748 11:41:08.180942 WL = 0x2
749 11:41:08.183985 RL = 0x2
750 11:41:08.184418 BL = 0x2
751 11:41:08.187393 RPST = 0x0
752 11:41:08.188057 RD_PRE = 0x0
753 11:41:08.190662 WR_PRE = 0x1
754 11:41:08.191132 WR_PST = 0x0
755 11:41:08.194109 DBI_WR = 0x0
756 11:41:08.194543 DBI_RD = 0x0
757 11:41:08.197063 OTF = 0x1
758 11:41:08.200195 ===================================
759 11:41:08.207293 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 11:41:08.210507 nWR fixed to 40
761 11:41:08.211231 [ModeRegInit_LP4] CH0 RK0
762 11:41:08.213583 [ModeRegInit_LP4] CH0 RK1
763 11:41:08.217027 [ModeRegInit_LP4] CH1 RK0
764 11:41:08.217461 [ModeRegInit_LP4] CH1 RK1
765 11:41:08.220436 match AC timing 13
766 11:41:08.223704 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 11:41:08.227285 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 11:41:08.233543 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 11:41:08.236987 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 11:41:08.243861 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 11:41:08.244294 [EMI DOE] emi_dcm 0
772 11:41:08.247012 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 11:41:08.250319 ==
774 11:41:08.253530 Dram Type= 6, Freq= 0, CH_0, rank 0
775 11:41:08.257159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 11:41:08.257811 ==
777 11:41:08.260568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 11:41:08.267688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 11:41:08.277774 [CA 0] Center 38 (7~69) winsize 63
780 11:41:08.280946 [CA 1] Center 38 (7~69) winsize 63
781 11:41:08.284538 [CA 2] Center 35 (5~66) winsize 62
782 11:41:08.287954 [CA 3] Center 35 (5~66) winsize 62
783 11:41:08.291486 [CA 4] Center 34 (4~65) winsize 62
784 11:41:08.295457 [CA 5] Center 34 (3~65) winsize 63
785 11:41:08.295966
786 11:41:08.299406 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 11:41:08.300056
788 11:41:08.302598 [CATrainingPosCal] consider 1 rank data
789 11:41:08.306040 u2DelayCellTimex100 = 270/100 ps
790 11:41:08.310124 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 11:41:08.313897 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
792 11:41:08.317391 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 11:41:08.320990 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 11:41:08.324581 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 11:41:08.328131 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
796 11:41:08.328561
797 11:41:08.332233 CA PerBit enable=1, Macro0, CA PI delay=34
798 11:41:08.332663
799 11:41:08.333002 [CBTSetCACLKResult] CA Dly = 34
800 11:41:08.335631 CS Dly: 6 (0~37)
801 11:41:08.336064 ==
802 11:41:08.339701 Dram Type= 6, Freq= 0, CH_0, rank 1
803 11:41:08.343193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 11:41:08.343629 ==
805 11:41:08.347474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 11:41:08.354445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 11:41:08.363728 [CA 0] Center 38 (7~69) winsize 63
808 11:41:08.367084 [CA 1] Center 38 (7~69) winsize 63
809 11:41:08.370934 [CA 2] Center 35 (5~66) winsize 62
810 11:41:08.374941 [CA 3] Center 35 (5~66) winsize 62
811 11:41:08.378357 [CA 4] Center 34 (4~65) winsize 62
812 11:41:08.381924 [CA 5] Center 34 (4~65) winsize 62
813 11:41:08.382435
814 11:41:08.385619 [CmdBusTrainingLP45] Vref(ca) range 1: 34
815 11:41:08.386049
816 11:41:08.389596 [CATrainingPosCal] consider 2 rank data
817 11:41:08.390025 u2DelayCellTimex100 = 270/100 ps
818 11:41:08.393347 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 11:41:08.397398 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
820 11:41:08.400645 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 11:41:08.404624 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 11:41:08.407889 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 11:41:08.412040 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 11:41:08.412518
825 11:41:08.415438 CA PerBit enable=1, Macro0, CA PI delay=34
826 11:41:08.415927
827 11:41:08.419265 [CBTSetCACLKResult] CA Dly = 34
828 11:41:08.422950 CS Dly: 6 (0~38)
829 11:41:08.423395
830 11:41:08.426145 ----->DramcWriteLeveling(PI) begin...
831 11:41:08.426596 ==
832 11:41:08.429833 Dram Type= 6, Freq= 0, CH_0, rank 0
833 11:41:08.433568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 11:41:08.434006 ==
835 11:41:08.437394 Write leveling (Byte 0): 32 => 32
836 11:41:08.437824 Write leveling (Byte 1): 32 => 32
837 11:41:08.440849 DramcWriteLeveling(PI) end<-----
838 11:41:08.441278
839 11:41:08.441614 ==
840 11:41:08.444852 Dram Type= 6, Freq= 0, CH_0, rank 0
841 11:41:08.448274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 11:41:08.448706 ==
843 11:41:08.451540 [Gating] SW mode calibration
844 11:41:08.459010 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 11:41:08.465966 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 11:41:08.469878 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 11:41:08.473359 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 11:41:08.477219 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 11:41:08.480774 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 11:41:08.488542 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 11:41:08.492065 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 11:41:08.496366 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:41:08.499412 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:41:08.503182 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:41:08.510878 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:41:08.514416 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:41:08.517778 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:41:08.521537 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:41:08.524988 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:41:08.532797 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:41:08.536760 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:41:08.539980 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:41:08.543535 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:41:08.547127 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
865 11:41:08.554429 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
866 11:41:08.558514 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:41:08.561820 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:41:08.565645 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:41:08.569478 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:41:08.576068 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:41:08.579175 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 11:41:08.582298 0 9 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
873 11:41:08.589069 0 9 12 | B1->B0 | 2b2b 3131 | 1 1 | (0 0) (1 1)
874 11:41:08.592663 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 11:41:08.595922 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 11:41:08.599376 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 11:41:08.606073 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 11:41:08.608911 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 11:41:08.612254 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
880 11:41:08.619178 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
881 11:41:08.622473 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
882 11:41:08.626116 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 11:41:08.632884 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 11:41:08.636292 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 11:41:08.639480 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 11:41:08.646002 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 11:41:08.648938 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 11:41:08.652422 0 11 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
889 11:41:08.658669 0 11 12 | B1->B0 | 3737 4040 | 0 0 | (0 0) (0 0)
890 11:41:08.662296 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 11:41:08.665951 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 11:41:08.672112 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 11:41:08.675413 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 11:41:08.678610 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 11:41:08.685217 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 11:41:08.688483 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 11:41:08.692218 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 11:41:08.698389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 11:41:08.701829 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 11:41:08.705347 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 11:41:08.712212 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 11:41:08.715105 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 11:41:08.718507 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 11:41:08.721860 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:41:08.728631 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:41:08.731975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:41:08.735371 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:41:08.741733 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:41:08.745236 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:41:08.748291 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:41:08.755002 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:41:08.758884 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 11:41:08.762051 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 11:41:08.764890 Total UI for P1: 0, mck2ui 16
915 11:41:08.768525 best dqsien dly found for B0: ( 0, 14, 8)
916 11:41:08.775488 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 11:41:08.775607 Total UI for P1: 0, mck2ui 16
918 11:41:08.782025 best dqsien dly found for B1: ( 0, 14, 12)
919 11:41:08.784903 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 11:41:08.788139 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 11:41:08.788222
922 11:41:08.791312 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 11:41:08.794685 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 11:41:08.797800 [Gating] SW calibration Done
925 11:41:08.797883 ==
926 11:41:08.801104 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:41:08.804490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:41:08.804574 ==
929 11:41:08.807949 RX Vref Scan: 0
930 11:41:08.808032
931 11:41:08.808098 RX Vref 0 -> 0, step: 1
932 11:41:08.811282
933 11:41:08.811390 RX Delay -130 -> 252, step: 16
934 11:41:08.818313 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 11:41:08.821509 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
936 11:41:08.824434 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 11:41:08.827939 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 11:41:08.831116 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
939 11:41:08.837840 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 11:41:08.841193 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 11:41:08.844621 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 11:41:08.847702 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 11:41:08.851045 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
944 11:41:08.857613 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 11:41:08.861246 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 11:41:08.864234 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 11:41:08.867435 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 11:41:08.873889 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 11:41:08.877426 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 11:41:08.877511 ==
951 11:41:08.880868 Dram Type= 6, Freq= 0, CH_0, rank 0
952 11:41:08.884020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 11:41:08.884105 ==
954 11:41:08.884172 DQS Delay:
955 11:41:08.887351 DQS0 = 0, DQS1 = 0
956 11:41:08.887445 DQM Delay:
957 11:41:08.890787 DQM0 = 79, DQM1 = 70
958 11:41:08.890933 DQ Delay:
959 11:41:08.893826 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
960 11:41:08.896914 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
961 11:41:08.900496 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 11:41:08.903889 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 11:41:08.903977
964 11:41:08.904043
965 11:41:08.904105 ==
966 11:41:08.907109 Dram Type= 6, Freq= 0, CH_0, rank 0
967 11:41:08.911410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 11:41:08.911499 ==
969 11:41:08.914546
970 11:41:08.914629
971 11:41:08.914695 TX Vref Scan disable
972 11:41:08.917904 == TX Byte 0 ==
973 11:41:08.921250 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
974 11:41:08.924744 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
975 11:41:08.927533 == TX Byte 1 ==
976 11:41:08.931073 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
977 11:41:08.934419 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
978 11:41:08.934518 ==
979 11:41:08.937592 Dram Type= 6, Freq= 0, CH_0, rank 0
980 11:41:08.943922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 11:41:08.944007 ==
982 11:41:08.955813 TX Vref=22, minBit 7, minWin=26, winSum=436
983 11:41:08.959194 TX Vref=24, minBit 7, minWin=26, winSum=438
984 11:41:08.962547 TX Vref=26, minBit 4, minWin=27, winSum=440
985 11:41:08.966003 TX Vref=28, minBit 8, minWin=27, winSum=443
986 11:41:08.969277 TX Vref=30, minBit 8, minWin=27, winSum=445
987 11:41:08.975888 TX Vref=32, minBit 8, minWin=27, winSum=443
988 11:41:08.979232 [TxChooseVref] Worse bit 8, Min win 27, Win sum 445, Final Vref 30
989 11:41:08.979316
990 11:41:08.982418 Final TX Range 1 Vref 30
991 11:41:08.982501
992 11:41:08.982567 ==
993 11:41:08.985852 Dram Type= 6, Freq= 0, CH_0, rank 0
994 11:41:08.989612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 11:41:08.989706 ==
996 11:41:08.992559
997 11:41:08.992643
998 11:41:08.992709 TX Vref Scan disable
999 11:41:08.995899 == TX Byte 0 ==
1000 11:41:08.999271 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1001 11:41:09.002543 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1002 11:41:09.005800 == TX Byte 1 ==
1003 11:41:09.009201 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1004 11:41:09.012405 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1005 11:41:09.015715
1006 11:41:09.015798 [DATLAT]
1007 11:41:09.015864 Freq=800, CH0 RK0
1008 11:41:09.015926
1009 11:41:09.019117 DATLAT Default: 0xa
1010 11:41:09.019200 0, 0xFFFF, sum = 0
1011 11:41:09.022652 1, 0xFFFF, sum = 0
1012 11:41:09.022768 2, 0xFFFF, sum = 0
1013 11:41:09.026242 3, 0xFFFF, sum = 0
1014 11:41:09.026326 4, 0xFFFF, sum = 0
1015 11:41:09.029103 5, 0xFFFF, sum = 0
1016 11:41:09.032550 6, 0xFFFF, sum = 0
1017 11:41:09.032635 7, 0xFFFF, sum = 0
1018 11:41:09.035891 8, 0xFFFF, sum = 0
1019 11:41:09.035977 9, 0x0, sum = 1
1020 11:41:09.036044 10, 0x0, sum = 2
1021 11:41:09.039038 11, 0x0, sum = 3
1022 11:41:09.039123 12, 0x0, sum = 4
1023 11:41:09.042377 best_step = 10
1024 11:41:09.042461
1025 11:41:09.042538 ==
1026 11:41:09.045833 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 11:41:09.049265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 11:41:09.049348 ==
1029 11:41:09.052132 RX Vref Scan: 1
1030 11:41:09.052215
1031 11:41:09.052280 Set Vref Range= 32 -> 127
1032 11:41:09.055548
1033 11:41:09.055630 RX Vref 32 -> 127, step: 1
1034 11:41:09.055696
1035 11:41:09.059012 RX Delay -111 -> 252, step: 8
1036 11:41:09.059095
1037 11:41:09.062244 Set Vref, RX VrefLevel [Byte0]: 32
1038 11:41:09.066009 [Byte1]: 32
1039 11:41:09.066092
1040 11:41:09.068943 Set Vref, RX VrefLevel [Byte0]: 33
1041 11:41:09.072288 [Byte1]: 33
1042 11:41:09.076158
1043 11:41:09.076240 Set Vref, RX VrefLevel [Byte0]: 34
1044 11:41:09.079636 [Byte1]: 34
1045 11:41:09.084116
1046 11:41:09.084212 Set Vref, RX VrefLevel [Byte0]: 35
1047 11:41:09.087459 [Byte1]: 35
1048 11:41:09.091564
1049 11:41:09.091645 Set Vref, RX VrefLevel [Byte0]: 36
1050 11:41:09.095087 [Byte1]: 36
1051 11:41:09.099245
1052 11:41:09.099327 Set Vref, RX VrefLevel [Byte0]: 37
1053 11:41:09.102577 [Byte1]: 37
1054 11:41:09.106875
1055 11:41:09.106957 Set Vref, RX VrefLevel [Byte0]: 38
1056 11:41:09.110231 [Byte1]: 38
1057 11:41:09.114284
1058 11:41:09.114365 Set Vref, RX VrefLevel [Byte0]: 39
1059 11:41:09.117550 [Byte1]: 39
1060 11:41:09.122333
1061 11:41:09.122415 Set Vref, RX VrefLevel [Byte0]: 40
1062 11:41:09.125727 [Byte1]: 40
1063 11:41:09.129629
1064 11:41:09.129736 Set Vref, RX VrefLevel [Byte0]: 41
1065 11:41:09.132948 [Byte1]: 41
1066 11:41:09.137323
1067 11:41:09.137405 Set Vref, RX VrefLevel [Byte0]: 42
1068 11:41:09.140755 [Byte1]: 42
1069 11:41:09.145293
1070 11:41:09.145375 Set Vref, RX VrefLevel [Byte0]: 43
1071 11:41:09.148251 [Byte1]: 43
1072 11:41:09.152847
1073 11:41:09.152931 Set Vref, RX VrefLevel [Byte0]: 44
1074 11:41:09.156338 [Byte1]: 44
1075 11:41:09.160443
1076 11:41:09.160525 Set Vref, RX VrefLevel [Byte0]: 45
1077 11:41:09.163780 [Byte1]: 45
1078 11:41:09.168134
1079 11:41:09.168224 Set Vref, RX VrefLevel [Byte0]: 46
1080 11:41:09.174586 [Byte1]: 46
1081 11:41:09.174670
1082 11:41:09.178251 Set Vref, RX VrefLevel [Byte0]: 47
1083 11:41:09.181735 [Byte1]: 47
1084 11:41:09.181818
1085 11:41:09.185209 Set Vref, RX VrefLevel [Byte0]: 48
1086 11:41:09.188996 [Byte1]: 48
1087 11:41:09.189136
1088 11:41:09.192524 Set Vref, RX VrefLevel [Byte0]: 49
1089 11:41:09.195750 [Byte1]: 49
1090 11:41:09.195834
1091 11:41:09.199741 Set Vref, RX VrefLevel [Byte0]: 50
1092 11:41:09.203009 [Byte1]: 50
1093 11:41:09.206272
1094 11:41:09.206370 Set Vref, RX VrefLevel [Byte0]: 51
1095 11:41:09.209544 [Byte1]: 51
1096 11:41:09.213816
1097 11:41:09.213913 Set Vref, RX VrefLevel [Byte0]: 52
1098 11:41:09.216950 [Byte1]: 52
1099 11:41:09.221367
1100 11:41:09.221463 Set Vref, RX VrefLevel [Byte0]: 53
1101 11:41:09.224550 [Byte1]: 53
1102 11:41:09.229228
1103 11:41:09.229310 Set Vref, RX VrefLevel [Byte0]: 54
1104 11:41:09.232213 [Byte1]: 54
1105 11:41:09.236550
1106 11:41:09.236632 Set Vref, RX VrefLevel [Byte0]: 55
1107 11:41:09.240237 [Byte1]: 55
1108 11:41:09.244271
1109 11:41:09.244353 Set Vref, RX VrefLevel [Byte0]: 56
1110 11:41:09.247669 [Byte1]: 56
1111 11:41:09.252169
1112 11:41:09.252251 Set Vref, RX VrefLevel [Byte0]: 57
1113 11:41:09.255086 [Byte1]: 57
1114 11:41:09.259719
1115 11:41:09.259801 Set Vref, RX VrefLevel [Byte0]: 58
1116 11:41:09.263115 [Byte1]: 58
1117 11:41:09.267687
1118 11:41:09.267771 Set Vref, RX VrefLevel [Byte0]: 59
1119 11:41:09.270502 [Byte1]: 59
1120 11:41:09.274845
1121 11:41:09.274920 Set Vref, RX VrefLevel [Byte0]: 60
1122 11:41:09.278499 [Byte1]: 60
1123 11:41:09.282668
1124 11:41:09.282742 Set Vref, RX VrefLevel [Byte0]: 61
1125 11:41:09.286156 [Byte1]: 61
1126 11:41:09.290220
1127 11:41:09.290293 Set Vref, RX VrefLevel [Byte0]: 62
1128 11:41:09.293528 [Byte1]: 62
1129 11:41:09.298040
1130 11:41:09.298115 Set Vref, RX VrefLevel [Byte0]: 63
1131 11:41:09.301634 [Byte1]: 63
1132 11:41:09.305414
1133 11:41:09.305518 Set Vref, RX VrefLevel [Byte0]: 64
1134 11:41:09.308698 [Byte1]: 64
1135 11:41:09.313402
1136 11:41:09.313489 Set Vref, RX VrefLevel [Byte0]: 65
1137 11:41:09.316321 [Byte1]: 65
1138 11:41:09.320574
1139 11:41:09.323816 Set Vref, RX VrefLevel [Byte0]: 66
1140 11:41:09.327295 [Byte1]: 66
1141 11:41:09.327377
1142 11:41:09.330620 Set Vref, RX VrefLevel [Byte0]: 67
1143 11:41:09.333806 [Byte1]: 67
1144 11:41:09.333889
1145 11:41:09.337162 Set Vref, RX VrefLevel [Byte0]: 68
1146 11:41:09.340575 [Byte1]: 68
1147 11:41:09.340658
1148 11:41:09.343950 Set Vref, RX VrefLevel [Byte0]: 69
1149 11:41:09.347301 [Byte1]: 69
1150 11:41:09.351359
1151 11:41:09.351444 Set Vref, RX VrefLevel [Byte0]: 70
1152 11:41:09.354586 [Byte1]: 70
1153 11:41:09.359348
1154 11:41:09.359429 Set Vref, RX VrefLevel [Byte0]: 71
1155 11:41:09.362211 [Byte1]: 71
1156 11:41:09.366801
1157 11:41:09.366903 Set Vref, RX VrefLevel [Byte0]: 72
1158 11:41:09.369843 [Byte1]: 72
1159 11:41:09.374397
1160 11:41:09.374478 Set Vref, RX VrefLevel [Byte0]: 73
1161 11:41:09.377755 [Byte1]: 73
1162 11:41:09.381791
1163 11:41:09.381873 Set Vref, RX VrefLevel [Byte0]: 74
1164 11:41:09.385084 [Byte1]: 74
1165 11:41:09.389483
1166 11:41:09.389564 Set Vref, RX VrefLevel [Byte0]: 75
1167 11:41:09.393141 [Byte1]: 75
1168 11:41:09.397508
1169 11:41:09.397588 Set Vref, RX VrefLevel [Byte0]: 76
1170 11:41:09.400961 [Byte1]: 76
1171 11:41:09.404773
1172 11:41:09.404855 Set Vref, RX VrefLevel [Byte0]: 77
1173 11:41:09.408192 [Byte1]: 77
1174 11:41:09.412717
1175 11:41:09.412798 Set Vref, RX VrefLevel [Byte0]: 78
1176 11:41:09.415880 [Byte1]: 78
1177 11:41:09.420528
1178 11:41:09.420609 Set Vref, RX VrefLevel [Byte0]: 79
1179 11:41:09.423673 [Byte1]: 79
1180 11:41:09.427875
1181 11:41:09.427957 Final RX Vref Byte 0 = 62 to rank0
1182 11:41:09.431337 Final RX Vref Byte 1 = 56 to rank0
1183 11:41:09.434655 Final RX Vref Byte 0 = 62 to rank1
1184 11:41:09.437750 Final RX Vref Byte 1 = 56 to rank1==
1185 11:41:09.440912 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 11:41:09.447889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 11:41:09.447972 ==
1188 11:41:09.448038 DQS Delay:
1189 11:41:09.448099 DQS0 = 0, DQS1 = 0
1190 11:41:09.451342 DQM Delay:
1191 11:41:09.451424 DQM0 = 81, DQM1 = 67
1192 11:41:09.454193 DQ Delay:
1193 11:41:09.457560 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1194 11:41:09.461262 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1195 11:41:09.464366 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1196 11:41:09.467737 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1197 11:41:09.467820
1198 11:41:09.467885
1199 11:41:09.474361 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1200 11:41:09.477580 CH0 RK0: MR19=606, MR18=2726
1201 11:41:09.484240 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1202 11:41:09.484351
1203 11:41:09.487694 ----->DramcWriteLeveling(PI) begin...
1204 11:41:09.487804 ==
1205 11:41:09.490946 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 11:41:09.494446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 11:41:09.494561 ==
1208 11:41:09.497536 Write leveling (Byte 0): 33 => 33
1209 11:41:09.500753 Write leveling (Byte 1): 29 => 29
1210 11:41:09.504247 DramcWriteLeveling(PI) end<-----
1211 11:41:09.504351
1212 11:41:09.504448 ==
1213 11:41:09.507534 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 11:41:09.510940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 11:41:09.511047 ==
1216 11:41:09.513768 [Gating] SW mode calibration
1217 11:41:09.520698 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 11:41:09.527303 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 11:41:09.530592 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 11:41:09.537287 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 11:41:09.540599 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 11:41:09.543614 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1223 11:41:09.547356 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:41:09.553912 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:41:09.557346 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:41:09.560340 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:41:09.567456 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:41:09.570558 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:41:09.574043 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:41:09.580382 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:41:09.583585 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:41:09.623955 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:41:09.624792 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:41:09.625071 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:41:09.625172 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:41:09.625268 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 11:41:09.625559 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1238 11:41:09.626169 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1239 11:41:09.626792 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:41:09.626922 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:41:09.631129 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:41:09.634430 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:41:09.638062 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:41:09.641068 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:41:09.644983 0 9 8 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
1246 11:41:09.651311 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1247 11:41:09.654618 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:41:09.657765 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:41:09.664470 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:41:09.667762 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:41:09.671167 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:41:09.677945 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1253 11:41:09.681474 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (1 0)
1254 11:41:09.684371 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1255 11:41:09.687671 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:41:09.694541 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:41:09.697987 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:41:09.701308 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:41:09.707535 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:41:09.710991 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:41:09.714477 0 11 8 | B1->B0 | 3030 4242 | 0 0 | (0 0) (0 0)
1262 11:41:09.720665 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1263 11:41:09.724320 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:41:09.727577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:41:09.734061 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:41:09.737447 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:41:09.741167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:41:09.747584 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1269 11:41:09.751441 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1270 11:41:09.755108 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:41:09.758404 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:41:09.765213 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:41:09.768847 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:41:09.772082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:41:09.778695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:41:09.781913 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:41:09.785229 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:41:09.792115 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:41:09.795313 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:41:09.798636 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:41:09.805494 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:41:09.808292 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:41:09.811925 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:41:09.818336 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:41:09.822061 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1286 11:41:09.825308 Total UI for P1: 0, mck2ui 16
1287 11:41:09.828132 best dqsien dly found for B0: ( 0, 14, 6)
1288 11:41:09.831655 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 11:41:09.834808 Total UI for P1: 0, mck2ui 16
1290 11:41:09.838604 best dqsien dly found for B1: ( 0, 14, 8)
1291 11:41:09.841683 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1292 11:41:09.844954 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 11:41:09.845036
1294 11:41:09.848393 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1295 11:41:09.855564 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 11:41:09.855677 [Gating] SW calibration Done
1297 11:41:09.855743 ==
1298 11:41:09.858284 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 11:41:09.864546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 11:41:09.864630 ==
1301 11:41:09.864696 RX Vref Scan: 0
1302 11:41:09.864762
1303 11:41:09.867812 RX Vref 0 -> 0, step: 1
1304 11:41:09.867915
1305 11:41:09.871492 RX Delay -130 -> 252, step: 16
1306 11:41:09.874689 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1307 11:41:09.877863 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1308 11:41:09.881569 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1309 11:41:09.888166 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1310 11:41:09.891073 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1311 11:41:09.894513 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1312 11:41:09.897961 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1313 11:41:09.901406 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1314 11:41:09.907657 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1315 11:41:09.911032 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1316 11:41:09.914533 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1317 11:41:09.917873 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1318 11:41:09.920765 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1319 11:41:09.927742 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1320 11:41:09.930861 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1321 11:41:09.934426 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1322 11:41:09.934535 ==
1323 11:41:09.937315 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 11:41:09.940664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 11:41:09.944256 ==
1326 11:41:09.944330 DQS Delay:
1327 11:41:09.944409 DQS0 = 0, DQS1 = 0
1328 11:41:09.947195 DQM Delay:
1329 11:41:09.947278 DQM0 = 78, DQM1 = 69
1330 11:41:09.950679 DQ Delay:
1331 11:41:09.950806 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1332 11:41:09.954091 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
1333 11:41:09.957457 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1334 11:41:09.960991 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1335 11:41:09.961076
1336 11:41:09.963914
1337 11:41:09.963996 ==
1338 11:41:09.967422 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 11:41:09.970723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 11:41:09.970842 ==
1341 11:41:09.970957
1342 11:41:09.971019
1343 11:41:09.974006 TX Vref Scan disable
1344 11:41:09.974110 == TX Byte 0 ==
1345 11:41:09.980406 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1346 11:41:09.983934 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1347 11:41:09.984052 == TX Byte 1 ==
1348 11:41:09.990184 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1349 11:41:09.994073 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1350 11:41:09.994183 ==
1351 11:41:09.996873 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 11:41:10.000276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 11:41:10.000392 ==
1354 11:41:10.014323 TX Vref=22, minBit 11, minWin=26, winSum=433
1355 11:41:10.017854 TX Vref=24, minBit 1, minWin=27, winSum=440
1356 11:41:10.021643 TX Vref=26, minBit 11, minWin=26, winSum=438
1357 11:41:10.024183 TX Vref=28, minBit 1, minWin=27, winSum=441
1358 11:41:10.027498 TX Vref=30, minBit 2, minWin=27, winSum=443
1359 11:41:10.034305 TX Vref=32, minBit 8, minWin=27, winSum=444
1360 11:41:10.037466 [TxChooseVref] Worse bit 8, Min win 27, Win sum 444, Final Vref 32
1361 11:41:10.037569
1362 11:41:10.040896 Final TX Range 1 Vref 32
1363 11:41:10.040996
1364 11:41:10.041086 ==
1365 11:41:10.044262 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 11:41:10.047550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 11:41:10.050658 ==
1368 11:41:10.050754
1369 11:41:10.050880
1370 11:41:10.050943 TX Vref Scan disable
1371 11:41:10.054540 == TX Byte 0 ==
1372 11:41:10.058064 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1373 11:41:10.064543 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1374 11:41:10.064642 == TX Byte 1 ==
1375 11:41:10.067579 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1376 11:41:10.074035 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1377 11:41:10.074110
1378 11:41:10.074174 [DATLAT]
1379 11:41:10.074261 Freq=800, CH0 RK1
1380 11:41:10.074351
1381 11:41:10.077575 DATLAT Default: 0xa
1382 11:41:10.080713 0, 0xFFFF, sum = 0
1383 11:41:10.080813 1, 0xFFFF, sum = 0
1384 11:41:10.084292 2, 0xFFFF, sum = 0
1385 11:41:10.084393 3, 0xFFFF, sum = 0
1386 11:41:10.087569 4, 0xFFFF, sum = 0
1387 11:41:10.087667 5, 0xFFFF, sum = 0
1388 11:41:10.090949 6, 0xFFFF, sum = 0
1389 11:41:10.091047 7, 0xFFFF, sum = 0
1390 11:41:10.094139 8, 0xFFFF, sum = 0
1391 11:41:10.094215 9, 0x0, sum = 1
1392 11:41:10.097437 10, 0x0, sum = 2
1393 11:41:10.097509 11, 0x0, sum = 3
1394 11:41:10.100595 12, 0x0, sum = 4
1395 11:41:10.100663 best_step = 10
1396 11:41:10.100724
1397 11:41:10.100780 ==
1398 11:41:10.104301 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 11:41:10.107245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 11:41:10.107317 ==
1401 11:41:10.110672 RX Vref Scan: 0
1402 11:41:10.110770
1403 11:41:10.114103 RX Vref 0 -> 0, step: 1
1404 11:41:10.114221
1405 11:41:10.114318 RX Delay -111 -> 252, step: 8
1406 11:41:10.121393 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1407 11:41:10.124219 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1408 11:41:10.127733 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1409 11:41:10.131474 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1410 11:41:10.137675 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1411 11:41:10.140902 iDelay=209, Bit 5, Center 68 (-47 ~ 184) 232
1412 11:41:10.144387 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1413 11:41:10.147357 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1414 11:41:10.150633 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1415 11:41:10.157201 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1416 11:41:10.160615 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1417 11:41:10.163581 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1418 11:41:10.167051 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1419 11:41:10.173798 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1420 11:41:10.177237 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1421 11:41:10.180049 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1422 11:41:10.180128 ==
1423 11:41:10.183605 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 11:41:10.186972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 11:41:10.187052 ==
1426 11:41:10.190313 DQS Delay:
1427 11:41:10.190402 DQS0 = 0, DQS1 = 0
1428 11:41:10.193551 DQM Delay:
1429 11:41:10.193631 DQM0 = 78, DQM1 = 69
1430 11:41:10.193693 DQ Delay:
1431 11:41:10.197004 DQ0 =76, DQ1 =80, DQ2 =76, DQ3 =72
1432 11:41:10.199906 DQ4 =76, DQ5 =68, DQ6 =88, DQ7 =88
1433 11:41:10.203907 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1434 11:41:10.206862 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1435 11:41:10.206962
1436 11:41:10.207044
1437 11:41:10.216591 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1438 11:41:10.219906 CH0 RK1: MR19=606, MR18=4B26
1439 11:41:10.226780 CH0_RK1: MR19=0x606, MR18=0x4B26, DQSOSC=391, MR23=63, INC=96, DEC=64
1440 11:41:10.226899 [RxdqsGatingPostProcess] freq 800
1441 11:41:10.233526 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 11:41:10.236895 Pre-setting of DQS Precalculation
1443 11:41:10.239813 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 11:41:10.243332 ==
1445 11:41:10.246286 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 11:41:10.249730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 11:41:10.249815 ==
1448 11:41:10.253203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 11:41:10.259652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 11:41:10.269897 [CA 0] Center 36 (6~66) winsize 61
1451 11:41:10.272822 [CA 1] Center 36 (6~67) winsize 62
1452 11:41:10.276399 [CA 2] Center 34 (5~64) winsize 60
1453 11:41:10.279852 [CA 3] Center 34 (4~64) winsize 61
1454 11:41:10.282982 [CA 4] Center 34 (4~64) winsize 61
1455 11:41:10.286528 [CA 5] Center 34 (4~64) winsize 61
1456 11:41:10.286611
1457 11:41:10.289354 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1458 11:41:10.289460
1459 11:41:10.292931 [CATrainingPosCal] consider 1 rank data
1460 11:41:10.296330 u2DelayCellTimex100 = 270/100 ps
1461 11:41:10.299577 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1462 11:41:10.306181 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 11:41:10.309488 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1464 11:41:10.313104 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 11:41:10.316031 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 11:41:10.319785 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 11:41:10.319871
1468 11:41:10.322580 CA PerBit enable=1, Macro0, CA PI delay=34
1469 11:41:10.322715
1470 11:41:10.325908 [CBTSetCACLKResult] CA Dly = 34
1471 11:41:10.325985 CS Dly: 5 (0~36)
1472 11:41:10.329464 ==
1473 11:41:10.332695 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 11:41:10.335912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 11:41:10.336040 ==
1476 11:41:10.339689 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 11:41:10.346128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 11:41:10.356030 [CA 0] Center 36 (6~67) winsize 62
1479 11:41:10.359003 [CA 1] Center 36 (6~67) winsize 62
1480 11:41:10.362324 [CA 2] Center 34 (4~65) winsize 62
1481 11:41:10.365569 [CA 3] Center 33 (3~64) winsize 62
1482 11:41:10.369081 [CA 4] Center 35 (5~65) winsize 61
1483 11:41:10.372367 [CA 5] Center 33 (3~64) winsize 62
1484 11:41:10.372444
1485 11:41:10.375896 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 11:41:10.376026
1487 11:41:10.378759 [CATrainingPosCal] consider 2 rank data
1488 11:41:10.382247 u2DelayCellTimex100 = 270/100 ps
1489 11:41:10.385774 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1490 11:41:10.392330 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 11:41:10.395473 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1492 11:41:10.398998 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1493 11:41:10.402706 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1494 11:41:10.405880 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 11:41:10.405969
1496 11:41:10.409807 CA PerBit enable=1, Macro0, CA PI delay=34
1497 11:41:10.409895
1498 11:41:10.413049 [CBTSetCACLKResult] CA Dly = 34
1499 11:41:10.413127 CS Dly: 6 (0~38)
1500 11:41:10.413192
1501 11:41:10.416576 ----->DramcWriteLeveling(PI) begin...
1502 11:41:10.416687 ==
1503 11:41:10.420052 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 11:41:10.423839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 11:41:10.423949 ==
1506 11:41:10.427575 Write leveling (Byte 0): 27 => 27
1507 11:41:10.431118 Write leveling (Byte 1): 31 => 31
1508 11:41:10.434948 DramcWriteLeveling(PI) end<-----
1509 11:41:10.435033
1510 11:41:10.435124 ==
1511 11:41:10.438361 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 11:41:10.441283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 11:41:10.441389 ==
1514 11:41:10.444783 [Gating] SW mode calibration
1515 11:41:10.451221 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 11:41:10.457995 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 11:41:10.461520 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 11:41:10.464461 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 11:41:10.471056 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 11:41:10.474240 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:41:10.477720 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:41:10.484502 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:41:10.487565 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:41:10.491064 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:41:10.497366 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:41:10.500633 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:41:10.504065 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:41:10.510666 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:41:10.513964 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:41:10.517247 0 7 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1531 11:41:10.523799 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:41:10.527021 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:41:10.530258 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:41:10.537158 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:41:10.540230 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:41:10.543992 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:41:10.550350 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:41:10.553823 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:41:10.556832 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:41:10.563730 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:41:10.567064 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:41:10.570556 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:41:10.576941 0 9 8 | B1->B0 | 2424 2727 | 1 1 | (0 0) (1 1)
1544 11:41:10.580301 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1545 11:41:10.583704 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:41:10.590385 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:41:10.593543 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:41:10.596675 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:41:10.603776 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:41:10.606403 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 11:41:10.610016 0 10 8 | B1->B0 | 2b2b 2929 | 0 1 | (0 1) (1 0)
1552 11:41:10.616298 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:41:10.619735 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:41:10.623419 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:41:10.629763 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:41:10.633262 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:41:10.636472 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:41:10.643145 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1559 11:41:10.646243 0 11 8 | B1->B0 | 3a3a 3939 | 1 0 | (0 0) (0 0)
1560 11:41:10.649859 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:41:10.656366 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:41:10.659476 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:41:10.663272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:41:10.669285 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:41:10.672753 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:41:10.676209 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1567 11:41:10.682477 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1568 11:41:10.686331 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:41:10.689153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:41:10.695720 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:41:10.699313 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:41:10.703083 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:41:10.709399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:41:10.712849 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:41:10.715775 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:41:10.719183 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:41:10.725705 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:41:10.729290 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:41:10.732606 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:41:10.738984 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:41:10.742251 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:41:10.745520 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1583 11:41:10.752079 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1584 11:41:10.755788 Total UI for P1: 0, mck2ui 16
1585 11:41:10.759030 best dqsien dly found for B0: ( 0, 14, 4)
1586 11:41:10.762107 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 11:41:10.765465 Total UI for P1: 0, mck2ui 16
1588 11:41:10.768969 best dqsien dly found for B1: ( 0, 14, 8)
1589 11:41:10.771798 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1590 11:41:10.775473 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1591 11:41:10.775591
1592 11:41:10.778651 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 11:41:10.782153 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1594 11:41:10.785183 [Gating] SW calibration Done
1595 11:41:10.785258 ==
1596 11:41:10.788249 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:41:10.794959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:41:10.795037 ==
1599 11:41:10.795108 RX Vref Scan: 0
1600 11:41:10.795170
1601 11:41:10.798215 RX Vref 0 -> 0, step: 1
1602 11:41:10.798285
1603 11:41:10.801507 RX Delay -130 -> 252, step: 16
1604 11:41:10.805189 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1605 11:41:10.808522 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1606 11:41:10.811751 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1607 11:41:10.818425 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1608 11:41:10.821481 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1609 11:41:10.825187 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1610 11:41:10.828114 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1611 11:41:10.831588 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1612 11:41:10.834938 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1613 11:41:10.841780 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1614 11:41:10.845029 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1615 11:41:10.848157 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1616 11:41:10.851780 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1617 11:41:10.858650 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1618 11:41:10.861315 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1619 11:41:10.865079 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1620 11:41:10.865188 ==
1621 11:41:10.868201 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 11:41:10.871616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 11:41:10.871693 ==
1624 11:41:10.874817 DQS Delay:
1625 11:41:10.874907 DQS0 = 0, DQS1 = 0
1626 11:41:10.878280 DQM Delay:
1627 11:41:10.878355 DQM0 = 79, DQM1 = 70
1628 11:41:10.878422 DQ Delay:
1629 11:41:10.881231 DQ0 =77, DQ1 =77, DQ2 =61, DQ3 =77
1630 11:41:10.884628 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1631 11:41:10.888063 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1632 11:41:10.891603 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1633 11:41:10.891703
1634 11:41:10.891804
1635 11:41:10.894707 ==
1636 11:41:10.898216 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 11:41:10.901148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 11:41:10.901254 ==
1639 11:41:10.901346
1640 11:41:10.901443
1641 11:41:10.904526 TX Vref Scan disable
1642 11:41:10.904634 == TX Byte 0 ==
1643 11:41:10.908658 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1644 11:41:10.914296 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1645 11:41:10.914375 == TX Byte 1 ==
1646 11:41:10.921041 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1647 11:41:10.924497 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1648 11:41:10.924574 ==
1649 11:41:10.927852 Dram Type= 6, Freq= 0, CH_1, rank 0
1650 11:41:10.930978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1651 11:41:10.931081 ==
1652 11:41:10.944589 TX Vref=22, minBit 1, minWin=27, winSum=441
1653 11:41:10.948240 TX Vref=24, minBit 1, minWin=27, winSum=442
1654 11:41:10.951351 TX Vref=26, minBit 1, minWin=27, winSum=444
1655 11:41:10.954490 TX Vref=28, minBit 5, minWin=27, winSum=447
1656 11:41:10.958061 TX Vref=30, minBit 6, minWin=27, winSum=447
1657 11:41:10.961237 TX Vref=32, minBit 5, minWin=27, winSum=445
1658 11:41:10.968047 [TxChooseVref] Worse bit 5, Min win 27, Win sum 447, Final Vref 28
1659 11:41:10.968172
1660 11:41:10.971231 Final TX Range 1 Vref 28
1661 11:41:10.971305
1662 11:41:10.971368 ==
1663 11:41:10.974526 Dram Type= 6, Freq= 0, CH_1, rank 0
1664 11:41:10.977644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1665 11:41:10.977744 ==
1666 11:41:10.981061
1667 11:41:10.981163
1668 11:41:10.981254 TX Vref Scan disable
1669 11:41:10.985169 == TX Byte 0 ==
1670 11:41:10.988092 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1671 11:41:10.991506 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1672 11:41:10.994819 == TX Byte 1 ==
1673 11:41:10.998128 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1674 11:41:11.001380 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1675 11:41:11.001496
1676 11:41:11.004796 [DATLAT]
1677 11:41:11.004896 Freq=800, CH1 RK0
1678 11:41:11.004994
1679 11:41:11.008344 DATLAT Default: 0xa
1680 11:41:11.008452 0, 0xFFFF, sum = 0
1681 11:41:11.011445 1, 0xFFFF, sum = 0
1682 11:41:11.011548 2, 0xFFFF, sum = 0
1683 11:41:11.014756 3, 0xFFFF, sum = 0
1684 11:41:11.014860 4, 0xFFFF, sum = 0
1685 11:41:11.017690 5, 0xFFFF, sum = 0
1686 11:41:11.021534 6, 0xFFFF, sum = 0
1687 11:41:11.021641 7, 0xFFFF, sum = 0
1688 11:41:11.024541 8, 0xFFFF, sum = 0
1689 11:41:11.024644 9, 0x0, sum = 1
1690 11:41:11.024737 10, 0x0, sum = 2
1691 11:41:11.027902 11, 0x0, sum = 3
1692 11:41:11.028005 12, 0x0, sum = 4
1693 11:41:11.031095 best_step = 10
1694 11:41:11.031195
1695 11:41:11.031286 ==
1696 11:41:11.034172 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 11:41:11.037560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 11:41:11.037659 ==
1699 11:41:11.040929 RX Vref Scan: 1
1700 11:41:11.041034
1701 11:41:11.041127 Set Vref Range= 32 -> 127
1702 11:41:11.044365
1703 11:41:11.044469 RX Vref 32 -> 127, step: 1
1704 11:41:11.044561
1705 11:41:11.047827 RX Delay -111 -> 252, step: 8
1706 11:41:11.047925
1707 11:41:11.051132 Set Vref, RX VrefLevel [Byte0]: 32
1708 11:41:11.054438 [Byte1]: 32
1709 11:41:11.057472
1710 11:41:11.057570 Set Vref, RX VrefLevel [Byte0]: 33
1711 11:41:11.060615 [Byte1]: 33
1712 11:41:11.064803
1713 11:41:11.064907 Set Vref, RX VrefLevel [Byte0]: 34
1714 11:41:11.068565 [Byte1]: 34
1715 11:41:11.072816
1716 11:41:11.072918 Set Vref, RX VrefLevel [Byte0]: 35
1717 11:41:11.075904 [Byte1]: 35
1718 11:41:11.080112
1719 11:41:11.080265 Set Vref, RX VrefLevel [Byte0]: 36
1720 11:41:11.083541 [Byte1]: 36
1721 11:41:11.087929
1722 11:41:11.088033 Set Vref, RX VrefLevel [Byte0]: 37
1723 11:41:11.091459 [Byte1]: 37
1724 11:41:11.095910
1725 11:41:11.096047 Set Vref, RX VrefLevel [Byte0]: 38
1726 11:41:11.098682 [Byte1]: 38
1727 11:41:11.103071
1728 11:41:11.103153 Set Vref, RX VrefLevel [Byte0]: 39
1729 11:41:11.106567 [Byte1]: 39
1730 11:41:11.111123
1731 11:41:11.111228 Set Vref, RX VrefLevel [Byte0]: 40
1732 11:41:11.113989 [Byte1]: 40
1733 11:41:11.118406
1734 11:41:11.118507 Set Vref, RX VrefLevel [Byte0]: 41
1735 11:41:11.121839 [Byte1]: 41
1736 11:41:11.126280
1737 11:41:11.126385 Set Vref, RX VrefLevel [Byte0]: 42
1738 11:41:11.129648 [Byte1]: 42
1739 11:41:11.133611
1740 11:41:11.133716 Set Vref, RX VrefLevel [Byte0]: 43
1741 11:41:11.137254 [Byte1]: 43
1742 11:41:11.141763
1743 11:41:11.141868 Set Vref, RX VrefLevel [Byte0]: 44
1744 11:41:11.144768 [Byte1]: 44
1745 11:41:11.149521
1746 11:41:11.149625 Set Vref, RX VrefLevel [Byte0]: 45
1747 11:41:11.152509 [Byte1]: 45
1748 11:41:11.156907
1749 11:41:11.157012 Set Vref, RX VrefLevel [Byte0]: 46
1750 11:41:11.160446 [Byte1]: 46
1751 11:41:11.164600
1752 11:41:11.164708 Set Vref, RX VrefLevel [Byte0]: 47
1753 11:41:11.167622 [Byte1]: 47
1754 11:41:11.172305
1755 11:41:11.172408 Set Vref, RX VrefLevel [Byte0]: 48
1756 11:41:11.175484 [Byte1]: 48
1757 11:41:11.179665
1758 11:41:11.179774 Set Vref, RX VrefLevel [Byte0]: 49
1759 11:41:11.182858 [Byte1]: 49
1760 11:41:11.187578
1761 11:41:11.187682 Set Vref, RX VrefLevel [Byte0]: 50
1762 11:41:11.190728 [Byte1]: 50
1763 11:41:11.195199
1764 11:41:11.195282 Set Vref, RX VrefLevel [Byte0]: 51
1765 11:41:11.198615 [Byte1]: 51
1766 11:41:11.202540
1767 11:41:11.202623 Set Vref, RX VrefLevel [Byte0]: 52
1768 11:41:11.205950 [Byte1]: 52
1769 11:41:11.210399
1770 11:41:11.210482 Set Vref, RX VrefLevel [Byte0]: 53
1771 11:41:11.214058 [Byte1]: 53
1772 11:41:11.217776
1773 11:41:11.217886 Set Vref, RX VrefLevel [Byte0]: 54
1774 11:41:11.221581 [Byte1]: 54
1775 11:41:11.225880
1776 11:41:11.225973 Set Vref, RX VrefLevel [Byte0]: 55
1777 11:41:11.229163 [Byte1]: 55
1778 11:41:11.233225
1779 11:41:11.233306 Set Vref, RX VrefLevel [Byte0]: 56
1780 11:41:11.236692 [Byte1]: 56
1781 11:41:11.240680
1782 11:41:11.240762 Set Vref, RX VrefLevel [Byte0]: 57
1783 11:41:11.244172 [Byte1]: 57
1784 11:41:11.248500
1785 11:41:11.248611 Set Vref, RX VrefLevel [Byte0]: 58
1786 11:41:11.251954 [Byte1]: 58
1787 11:41:11.256545
1788 11:41:11.256629 Set Vref, RX VrefLevel [Byte0]: 59
1789 11:41:11.259474 [Byte1]: 59
1790 11:41:11.263909
1791 11:41:11.263992 Set Vref, RX VrefLevel [Byte0]: 60
1792 11:41:11.267330 [Byte1]: 60
1793 11:41:11.271757
1794 11:41:11.271840 Set Vref, RX VrefLevel [Byte0]: 61
1795 11:41:11.274618 [Byte1]: 61
1796 11:41:11.279399
1797 11:41:11.279483 Set Vref, RX VrefLevel [Byte0]: 62
1798 11:41:11.285812 [Byte1]: 62
1799 11:41:11.285896
1800 11:41:11.289218 Set Vref, RX VrefLevel [Byte0]: 63
1801 11:41:11.292287 [Byte1]: 63
1802 11:41:11.292371
1803 11:41:11.295506 Set Vref, RX VrefLevel [Byte0]: 64
1804 11:41:11.298682 [Byte1]: 64
1805 11:41:11.302044
1806 11:41:11.302129 Set Vref, RX VrefLevel [Byte0]: 65
1807 11:41:11.305439 [Byte1]: 65
1808 11:41:11.309958
1809 11:41:11.310042 Set Vref, RX VrefLevel [Byte0]: 66
1810 11:41:11.313225 [Byte1]: 66
1811 11:41:11.317327
1812 11:41:11.317437 Set Vref, RX VrefLevel [Byte0]: 67
1813 11:41:11.320814 [Byte1]: 67
1814 11:41:11.325010
1815 11:41:11.325094 Set Vref, RX VrefLevel [Byte0]: 68
1816 11:41:11.328381 [Byte1]: 68
1817 11:41:11.332623
1818 11:41:11.332736 Set Vref, RX VrefLevel [Byte0]: 69
1819 11:41:11.336693 [Byte1]: 69
1820 11:41:11.340435
1821 11:41:11.340547 Set Vref, RX VrefLevel [Byte0]: 70
1822 11:41:11.343895 [Byte1]: 70
1823 11:41:11.348011
1824 11:41:11.348084 Set Vref, RX VrefLevel [Byte0]: 71
1825 11:41:11.351476 [Byte1]: 71
1826 11:41:11.355748
1827 11:41:11.355823 Set Vref, RX VrefLevel [Byte0]: 72
1828 11:41:11.359239 [Byte1]: 72
1829 11:41:11.363285
1830 11:41:11.363357 Set Vref, RX VrefLevel [Byte0]: 73
1831 11:41:11.366649 [Byte1]: 73
1832 11:41:11.370750
1833 11:41:11.370822 Set Vref, RX VrefLevel [Byte0]: 74
1834 11:41:11.374388 [Byte1]: 74
1835 11:41:11.378804
1836 11:41:11.378889 Final RX Vref Byte 0 = 60 to rank0
1837 11:41:11.381757 Final RX Vref Byte 1 = 55 to rank0
1838 11:41:11.384951 Final RX Vref Byte 0 = 60 to rank1
1839 11:41:11.388649 Final RX Vref Byte 1 = 55 to rank1==
1840 11:41:11.391556 Dram Type= 6, Freq= 0, CH_1, rank 0
1841 11:41:11.398396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 11:41:11.398512 ==
1843 11:41:11.398609 DQS Delay:
1844 11:41:11.401725 DQS0 = 0, DQS1 = 0
1845 11:41:11.401826 DQM Delay:
1846 11:41:11.401917 DQM0 = 81, DQM1 = 71
1847 11:41:11.405006 DQ Delay:
1848 11:41:11.408221 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1849 11:41:11.411623 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1850 11:41:11.415006 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1851 11:41:11.418349 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1852 11:41:11.418432
1853 11:41:11.418497
1854 11:41:11.424717 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1855 11:41:11.428207 CH1 RK0: MR19=606, MR18=F19
1856 11:41:11.434435 CH1_RK0: MR19=0x606, MR18=0xF19, DQSOSC=403, MR23=63, INC=90, DEC=60
1857 11:41:11.434544
1858 11:41:11.438165 ----->DramcWriteLeveling(PI) begin...
1859 11:41:11.438249 ==
1860 11:41:11.441338 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 11:41:11.444769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 11:41:11.444852 ==
1863 11:41:11.448375 Write leveling (Byte 0): 25 => 25
1864 11:41:11.451047 Write leveling (Byte 1): 30 => 30
1865 11:41:11.454657 DramcWriteLeveling(PI) end<-----
1866 11:41:11.454740
1867 11:41:11.454805 ==
1868 11:41:11.458288 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 11:41:11.461499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 11:41:11.461581 ==
1871 11:41:11.464857 [Gating] SW mode calibration
1872 11:41:11.470957 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1873 11:41:11.477822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1874 11:41:11.481426 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1875 11:41:11.487718 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1876 11:41:11.490969 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:41:11.494175 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1878 11:41:11.497867 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:41:11.504348 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:41:11.507570 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:41:11.510962 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:41:11.517653 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:41:11.520856 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:41:11.523855 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:41:11.530662 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:41:11.534076 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:41:11.537494 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:41:11.543690 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:41:11.547003 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:41:11.550452 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1891 11:41:11.557267 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1892 11:41:11.560157 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:41:11.563680 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:41:11.570425 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:41:11.573743 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:41:11.576790 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:41:11.583487 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:41:11.586940 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:41:11.589993 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1900 11:41:11.596472 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1901 11:41:11.599645 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 11:41:11.603601 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 11:41:11.610063 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 11:41:11.613209 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 11:41:11.616476 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 11:41:11.623139 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1907 11:41:11.626437 0 10 4 | B1->B0 | 3333 2e2e | 1 0 | (0 0) (0 1)
1908 11:41:11.629422 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1909 11:41:11.636332 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:41:11.639792 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:41:11.642993 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:41:11.649990 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:41:11.652980 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:41:11.656262 0 11 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
1915 11:41:11.662981 0 11 4 | B1->B0 | 2626 3d3d | 0 0 | (0 0) (0 0)
1916 11:41:11.665870 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1917 11:41:11.669268 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 11:41:11.675973 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 11:41:11.679585 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 11:41:11.682703 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 11:41:11.689203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 11:41:11.692693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 11:41:11.696010 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1924 11:41:11.702722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:41:11.705740 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:41:11.709096 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:41:11.715547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:41:11.719235 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:41:11.722100 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:41:11.729042 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:41:11.732122 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:41:11.735908 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:41:11.742466 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:41:11.745572 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:41:11.748482 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:41:11.755302 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:41:11.758759 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:41:11.761707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:41:11.768364 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1940 11:41:11.771839 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1941 11:41:11.775461 Total UI for P1: 0, mck2ui 16
1942 11:41:11.778747 best dqsien dly found for B0: ( 0, 14, 4)
1943 11:41:11.782081 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 11:41:11.784744 Total UI for P1: 0, mck2ui 16
1945 11:41:11.788666 best dqsien dly found for B1: ( 0, 14, 8)
1946 11:41:11.791597 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1947 11:41:11.795086 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1948 11:41:11.795171
1949 11:41:11.801634 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1950 11:41:11.804789 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1951 11:41:11.804871 [Gating] SW calibration Done
1952 11:41:11.808247 ==
1953 11:41:11.808332 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 11:41:11.814723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 11:41:11.814842 ==
1956 11:41:11.814927 RX Vref Scan: 0
1957 11:41:11.814990
1958 11:41:11.817898 RX Vref 0 -> 0, step: 1
1959 11:41:11.817981
1960 11:41:11.821752 RX Delay -130 -> 252, step: 16
1961 11:41:11.824803 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1962 11:41:11.827972 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1963 11:41:11.831362 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1964 11:41:11.838056 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1965 11:41:11.841397 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1966 11:41:11.844207 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1967 11:41:11.847675 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1968 11:41:11.854578 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1969 11:41:11.858143 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1970 11:41:11.861482 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1971 11:41:11.864399 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1972 11:41:11.867869 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1973 11:41:11.874207 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1974 11:41:11.877700 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1975 11:41:11.880645 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1976 11:41:11.884548 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1977 11:41:11.884624 ==
1978 11:41:11.887172 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 11:41:11.894296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 11:41:11.894384 ==
1981 11:41:11.894488 DQS Delay:
1982 11:41:11.897196 DQS0 = 0, DQS1 = 0
1983 11:41:11.897283 DQM Delay:
1984 11:41:11.897368 DQM0 = 78, DQM1 = 73
1985 11:41:11.900648 DQ Delay:
1986 11:41:11.904000 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1987 11:41:11.907459 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1988 11:41:11.910272 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1989 11:41:11.913852 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1990 11:41:11.913935
1991 11:41:11.914002
1992 11:41:11.914062 ==
1993 11:41:11.917009 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 11:41:11.920214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 11:41:11.920298 ==
1996 11:41:11.920364
1997 11:41:11.920425
1998 11:41:11.923780 TX Vref Scan disable
1999 11:41:11.927069 == TX Byte 0 ==
2000 11:41:11.930283 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2001 11:41:11.933787 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2002 11:41:11.937157 == TX Byte 1 ==
2003 11:41:11.940364 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2004 11:41:11.943581 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2005 11:41:11.943672 ==
2006 11:41:11.946732 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 11:41:11.950188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 11:41:11.952989 ==
2009 11:41:11.965084 TX Vref=22, minBit 0, minWin=28, winSum=453
2010 11:41:11.968522 TX Vref=24, minBit 1, minWin=28, winSum=457
2011 11:41:11.971765 TX Vref=26, minBit 5, minWin=28, winSum=460
2012 11:41:11.975017 TX Vref=28, minBit 5, minWin=28, winSum=464
2013 11:41:11.978221 TX Vref=30, minBit 0, minWin=29, winSum=466
2014 11:41:11.985046 TX Vref=32, minBit 5, minWin=28, winSum=464
2015 11:41:11.987911 [TxChooseVref] Worse bit 0, Min win 29, Win sum 466, Final Vref 30
2016 11:41:11.987988
2017 11:41:11.991378 Final TX Range 1 Vref 30
2018 11:41:11.991467
2019 11:41:11.991532 ==
2020 11:41:11.995092 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 11:41:11.998064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 11:41:11.998165 ==
2023 11:41:12.001415
2024 11:41:12.001505
2025 11:41:12.001587 TX Vref Scan disable
2026 11:41:12.005029 == TX Byte 0 ==
2027 11:41:12.008485 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2028 11:41:12.011943 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2029 11:41:12.014822 == TX Byte 1 ==
2030 11:41:12.018541 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2031 11:41:12.025296 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2032 11:41:12.025382
2033 11:41:12.025467 [DATLAT]
2034 11:41:12.025548 Freq=800, CH1 RK1
2035 11:41:12.025628
2036 11:41:12.028182 DATLAT Default: 0xa
2037 11:41:12.028272 0, 0xFFFF, sum = 0
2038 11:41:12.031488 1, 0xFFFF, sum = 0
2039 11:41:12.031576 2, 0xFFFF, sum = 0
2040 11:41:12.034762 3, 0xFFFF, sum = 0
2041 11:41:12.037973 4, 0xFFFF, sum = 0
2042 11:41:12.038061 5, 0xFFFF, sum = 0
2043 11:41:12.041227 6, 0xFFFF, sum = 0
2044 11:41:12.041314 7, 0xFFFF, sum = 0
2045 11:41:12.044481 8, 0xFFFF, sum = 0
2046 11:41:12.044569 9, 0x0, sum = 1
2047 11:41:12.048276 10, 0x0, sum = 2
2048 11:41:12.048367 11, 0x0, sum = 3
2049 11:41:12.048457 12, 0x0, sum = 4
2050 11:41:12.051478 best_step = 10
2051 11:41:12.051613
2052 11:41:12.051707 ==
2053 11:41:12.054574 Dram Type= 6, Freq= 0, CH_1, rank 1
2054 11:41:12.058201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2055 11:41:12.058288 ==
2056 11:41:12.061573 RX Vref Scan: 0
2057 11:41:12.061660
2058 11:41:12.061745 RX Vref 0 -> 0, step: 1
2059 11:41:12.064474
2060 11:41:12.064551 RX Delay -111 -> 252, step: 8
2061 11:41:12.071857 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2062 11:41:12.074881 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2063 11:41:12.078160 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2064 11:41:12.081412 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2065 11:41:12.085140 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2066 11:41:12.091990 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2067 11:41:12.094706 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2068 11:41:12.098164 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2069 11:41:12.101543 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2070 11:41:12.104775 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2071 11:41:12.111456 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2072 11:41:12.115030 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2073 11:41:12.117871 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2074 11:41:12.121226 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2075 11:41:12.128092 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2076 11:41:12.131555 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2077 11:41:12.131641 ==
2078 11:41:12.135166 Dram Type= 6, Freq= 0, CH_1, rank 1
2079 11:41:12.138190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2080 11:41:12.138282 ==
2081 11:41:12.141499 DQS Delay:
2082 11:41:12.141586 DQS0 = 0, DQS1 = 0
2083 11:41:12.141718 DQM Delay:
2084 11:41:12.144685 DQM0 = 78, DQM1 = 73
2085 11:41:12.144773 DQ Delay:
2086 11:41:12.147916 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2087 11:41:12.151002 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2088 11:41:12.154812 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2089 11:41:12.157946 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2090 11:41:12.158027
2091 11:41:12.158110
2092 11:41:12.168175 [DQSOSCAuto] RK1, (LSB)MR18= 0x2038, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2093 11:41:12.168262 CH1 RK1: MR19=606, MR18=2038
2094 11:41:12.174230 CH1_RK1: MR19=0x606, MR18=0x2038, DQSOSC=395, MR23=63, INC=94, DEC=63
2095 11:41:12.177655 [RxdqsGatingPostProcess] freq 800
2096 11:41:12.184529 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2097 11:41:12.187781 Pre-setting of DQS Precalculation
2098 11:41:12.191234 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2099 11:41:12.197673 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2100 11:41:12.207446 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2101 11:41:12.207576
2102 11:41:12.207673
2103 11:41:12.210917 [Calibration Summary] 1600 Mbps
2104 11:41:12.210993 CH 0, Rank 0
2105 11:41:12.214284 SW Impedance : PASS
2106 11:41:12.214384 DUTY Scan : NO K
2107 11:41:12.217467 ZQ Calibration : PASS
2108 11:41:12.220915 Jitter Meter : NO K
2109 11:41:12.221001 CBT Training : PASS
2110 11:41:12.224550 Write leveling : PASS
2111 11:41:12.224635 RX DQS gating : PASS
2112 11:41:12.227535 RX DQ/DQS(RDDQC) : PASS
2113 11:41:12.230868 TX DQ/DQS : PASS
2114 11:41:12.230968 RX DATLAT : PASS
2115 11:41:12.234413 RX DQ/DQS(Engine): PASS
2116 11:41:12.237818 TX OE : NO K
2117 11:41:12.237893 All Pass.
2118 11:41:12.237959
2119 11:41:12.238020 CH 0, Rank 1
2120 11:41:12.241050 SW Impedance : PASS
2121 11:41:12.244374 DUTY Scan : NO K
2122 11:41:12.244453 ZQ Calibration : PASS
2123 11:41:12.247507 Jitter Meter : NO K
2124 11:41:12.250922 CBT Training : PASS
2125 11:41:12.250992 Write leveling : PASS
2126 11:41:12.253845 RX DQS gating : PASS
2127 11:41:12.257072 RX DQ/DQS(RDDQC) : PASS
2128 11:41:12.257143 TX DQ/DQS : PASS
2129 11:41:12.260803 RX DATLAT : PASS
2130 11:41:12.264030 RX DQ/DQS(Engine): PASS
2131 11:41:12.264100 TX OE : NO K
2132 11:41:12.267557 All Pass.
2133 11:41:12.267624
2134 11:41:12.267684 CH 1, Rank 0
2135 11:41:12.270669 SW Impedance : PASS
2136 11:41:12.270766 DUTY Scan : NO K
2137 11:41:12.274216 ZQ Calibration : PASS
2138 11:41:12.278027 Jitter Meter : NO K
2139 11:41:12.278128 CBT Training : PASS
2140 11:41:12.280744 Write leveling : PASS
2141 11:41:12.280812 RX DQS gating : PASS
2142 11:41:12.283942 RX DQ/DQS(RDDQC) : PASS
2143 11:41:12.287422 TX DQ/DQS : PASS
2144 11:41:12.287524 RX DATLAT : PASS
2145 11:41:12.291174 RX DQ/DQS(Engine): PASS
2146 11:41:12.293665 TX OE : NO K
2147 11:41:12.293738 All Pass.
2148 11:41:12.293798
2149 11:41:12.293857 CH 1, Rank 1
2150 11:41:12.296978 SW Impedance : PASS
2151 11:41:12.300327 DUTY Scan : NO K
2152 11:41:12.300398 ZQ Calibration : PASS
2153 11:41:12.303717 Jitter Meter : NO K
2154 11:41:12.307211 CBT Training : PASS
2155 11:41:12.307313 Write leveling : PASS
2156 11:41:12.310155 RX DQS gating : PASS
2157 11:41:12.313601 RX DQ/DQS(RDDQC) : PASS
2158 11:41:12.313677 TX DQ/DQS : PASS
2159 11:41:12.316973 RX DATLAT : PASS
2160 11:41:12.320286 RX DQ/DQS(Engine): PASS
2161 11:41:12.320361 TX OE : NO K
2162 11:41:12.323649 All Pass.
2163 11:41:12.323720
2164 11:41:12.323780 DramC Write-DBI off
2165 11:41:12.327207 PER_BANK_REFRESH: Hybrid Mode
2166 11:41:12.327303 TX_TRACKING: ON
2167 11:41:12.330104 [GetDramInforAfterCalByMRR] Vendor 6.
2168 11:41:12.336921 [GetDramInforAfterCalByMRR] Revision 606.
2169 11:41:12.340425 [GetDramInforAfterCalByMRR] Revision 2 0.
2170 11:41:12.340502 MR0 0x3b3b
2171 11:41:12.340567 MR8 0x5151
2172 11:41:12.343350 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 11:41:12.343429
2174 11:41:12.347437 MR0 0x3b3b
2175 11:41:12.347511 MR8 0x5151
2176 11:41:12.350501 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 11:41:12.350604
2178 11:41:12.360472 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2179 11:41:12.363587 [FAST_K] Save calibration result to emmc
2180 11:41:12.366905 [FAST_K] Save calibration result to emmc
2181 11:41:12.370176 dram_init: config_dvfs: 1
2182 11:41:12.373273 dramc_set_vcore_voltage set vcore to 662500
2183 11:41:12.376617 Read voltage for 1200, 2
2184 11:41:12.376691 Vio18 = 0
2185 11:41:12.376754 Vcore = 662500
2186 11:41:12.380078 Vdram = 0
2187 11:41:12.380150 Vddq = 0
2188 11:41:12.380210 Vmddr = 0
2189 11:41:12.386944 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2190 11:41:12.390289 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2191 11:41:12.393183 MEM_TYPE=3, freq_sel=15
2192 11:41:12.396641 sv_algorithm_assistance_LP4_1600
2193 11:41:12.399892 ============ PULL DRAM RESETB DOWN ============
2194 11:41:12.403266 ========== PULL DRAM RESETB DOWN end =========
2195 11:41:12.410174 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2196 11:41:12.413465 ===================================
2197 11:41:12.413547 LPDDR4 DRAM CONFIGURATION
2198 11:41:12.416378 ===================================
2199 11:41:12.419798 EX_ROW_EN[0] = 0x0
2200 11:41:12.423224 EX_ROW_EN[1] = 0x0
2201 11:41:12.423298 LP4Y_EN = 0x0
2202 11:41:12.426972 WORK_FSP = 0x0
2203 11:41:12.427042 WL = 0x4
2204 11:41:12.430051 RL = 0x4
2205 11:41:12.430125 BL = 0x2
2206 11:41:12.433063 RPST = 0x0
2207 11:41:12.433149 RD_PRE = 0x0
2208 11:41:12.436241 WR_PRE = 0x1
2209 11:41:12.436309 WR_PST = 0x0
2210 11:41:12.439537 DBI_WR = 0x0
2211 11:41:12.439612 DBI_RD = 0x0
2212 11:41:12.443024 OTF = 0x1
2213 11:41:12.446503 ===================================
2214 11:41:12.449906 ===================================
2215 11:41:12.449981 ANA top config
2216 11:41:12.452966 ===================================
2217 11:41:12.455903 DLL_ASYNC_EN = 0
2218 11:41:12.459181 ALL_SLAVE_EN = 0
2219 11:41:12.463075 NEW_RANK_MODE = 1
2220 11:41:12.463146 DLL_IDLE_MODE = 1
2221 11:41:12.466355 LP45_APHY_COMB_EN = 1
2222 11:41:12.469610 TX_ODT_DIS = 1
2223 11:41:12.473118 NEW_8X_MODE = 1
2224 11:41:12.475919 ===================================
2225 11:41:12.479251 ===================================
2226 11:41:12.482393 data_rate = 2400
2227 11:41:12.482465 CKR = 1
2228 11:41:12.485662 DQ_P2S_RATIO = 8
2229 11:41:12.489154 ===================================
2230 11:41:12.492638 CA_P2S_RATIO = 8
2231 11:41:12.496093 DQ_CA_OPEN = 0
2232 11:41:12.499011 DQ_SEMI_OPEN = 0
2233 11:41:12.502466 CA_SEMI_OPEN = 0
2234 11:41:12.502537 CA_FULL_RATE = 0
2235 11:41:12.506091 DQ_CKDIV4_EN = 0
2236 11:41:12.508954 CA_CKDIV4_EN = 0
2237 11:41:12.512453 CA_PREDIV_EN = 0
2238 11:41:12.515901 PH8_DLY = 17
2239 11:41:12.518681 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2240 11:41:12.522556 DQ_AAMCK_DIV = 4
2241 11:41:12.522635 CA_AAMCK_DIV = 4
2242 11:41:12.525818 CA_ADMCK_DIV = 4
2243 11:41:12.528939 DQ_TRACK_CA_EN = 0
2244 11:41:12.532302 CA_PICK = 1200
2245 11:41:12.535320 CA_MCKIO = 1200
2246 11:41:12.538946 MCKIO_SEMI = 0
2247 11:41:12.542203 PLL_FREQ = 2366
2248 11:41:12.542276 DQ_UI_PI_RATIO = 32
2249 11:41:12.545748 CA_UI_PI_RATIO = 0
2250 11:41:12.549144 ===================================
2251 11:41:12.551939 ===================================
2252 11:41:12.555359 memory_type:LPDDR4
2253 11:41:12.558719 GP_NUM : 10
2254 11:41:12.558791 SRAM_EN : 1
2255 11:41:12.561966 MD32_EN : 0
2256 11:41:12.565203 ===================================
2257 11:41:12.568547 [ANA_INIT] >>>>>>>>>>>>>>
2258 11:41:12.568617 <<<<<< [CONFIGURE PHASE]: ANA_TX
2259 11:41:12.571875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2260 11:41:12.574928 ===================================
2261 11:41:12.578611 data_rate = 2400,PCW = 0X5b00
2262 11:41:12.581868 ===================================
2263 11:41:12.585320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2264 11:41:12.592001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2265 11:41:12.598423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 11:41:12.601965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2267 11:41:12.605225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2268 11:41:12.608641 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2269 11:41:12.611405 [ANA_INIT] flow start
2270 11:41:12.611488 [ANA_INIT] PLL >>>>>>>>
2271 11:41:12.615047 [ANA_INIT] PLL <<<<<<<<
2272 11:41:12.618494 [ANA_INIT] MIDPI >>>>>>>>
2273 11:41:12.618597 [ANA_INIT] MIDPI <<<<<<<<
2274 11:41:12.622064 [ANA_INIT] DLL >>>>>>>>
2275 11:41:12.625268 [ANA_INIT] DLL <<<<<<<<
2276 11:41:12.625355 [ANA_INIT] flow end
2277 11:41:12.631484 ============ LP4 DIFF to SE enter ============
2278 11:41:12.634966 ============ LP4 DIFF to SE exit ============
2279 11:41:12.638470 [ANA_INIT] <<<<<<<<<<<<<
2280 11:41:12.641786 [Flow] Enable top DCM control >>>>>
2281 11:41:12.645216 [Flow] Enable top DCM control <<<<<
2282 11:41:12.645332 Enable DLL master slave shuffle
2283 11:41:12.651309 ==============================================================
2284 11:41:12.654815 Gating Mode config
2285 11:41:12.658247 ==============================================================
2286 11:41:12.661743 Config description:
2287 11:41:12.671077 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2288 11:41:12.677653 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2289 11:41:12.681280 SELPH_MODE 0: By rank 1: By Phase
2290 11:41:12.687844 ==============================================================
2291 11:41:12.691052 GAT_TRACK_EN = 1
2292 11:41:12.694312 RX_GATING_MODE = 2
2293 11:41:12.698040 RX_GATING_TRACK_MODE = 2
2294 11:41:12.700996 SELPH_MODE = 1
2295 11:41:12.704440 PICG_EARLY_EN = 1
2296 11:41:12.704513 VALID_LAT_VALUE = 1
2297 11:41:12.711396 ==============================================================
2298 11:41:12.714219 Enter into Gating configuration >>>>
2299 11:41:12.717497 Exit from Gating configuration <<<<
2300 11:41:12.720763 Enter into DVFS_PRE_config >>>>>
2301 11:41:12.730760 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2302 11:41:12.734243 Exit from DVFS_PRE_config <<<<<
2303 11:41:12.737679 Enter into PICG configuration >>>>
2304 11:41:12.741017 Exit from PICG configuration <<<<
2305 11:41:12.743740 [RX_INPUT] configuration >>>>>
2306 11:41:12.747218 [RX_INPUT] configuration <<<<<
2307 11:41:12.754093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2308 11:41:12.757530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2309 11:41:12.764003 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 11:41:12.770253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 11:41:12.776942 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 11:41:12.783388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 11:41:12.786682 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2314 11:41:12.790252 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2315 11:41:12.793543 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2316 11:41:12.800331 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2317 11:41:12.803227 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2318 11:41:12.807013 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2319 11:41:12.810411 ===================================
2320 11:41:12.813296 LPDDR4 DRAM CONFIGURATION
2321 11:41:12.816779 ===================================
2322 11:41:12.816861 EX_ROW_EN[0] = 0x0
2323 11:41:12.820271 EX_ROW_EN[1] = 0x0
2324 11:41:12.823046 LP4Y_EN = 0x0
2325 11:41:12.823128 WORK_FSP = 0x0
2326 11:41:12.826422 WL = 0x4
2327 11:41:12.826504 RL = 0x4
2328 11:41:12.830088 BL = 0x2
2329 11:41:12.830172 RPST = 0x0
2330 11:41:12.832994 RD_PRE = 0x0
2331 11:41:12.833075 WR_PRE = 0x1
2332 11:41:12.836277 WR_PST = 0x0
2333 11:41:12.836389 DBI_WR = 0x0
2334 11:41:12.839697 DBI_RD = 0x0
2335 11:41:12.839780 OTF = 0x1
2336 11:41:12.843067 ===================================
2337 11:41:12.846281 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2338 11:41:12.853159 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2339 11:41:12.856465 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2340 11:41:12.859877 ===================================
2341 11:41:12.862678 LPDDR4 DRAM CONFIGURATION
2342 11:41:12.866128 ===================================
2343 11:41:12.866211 EX_ROW_EN[0] = 0x10
2344 11:41:12.869626 EX_ROW_EN[1] = 0x0
2345 11:41:12.873381 LP4Y_EN = 0x0
2346 11:41:12.873463 WORK_FSP = 0x0
2347 11:41:12.876467 WL = 0x4
2348 11:41:12.876550 RL = 0x4
2349 11:41:12.879745 BL = 0x2
2350 11:41:12.879828 RPST = 0x0
2351 11:41:12.883030 RD_PRE = 0x0
2352 11:41:12.883115 WR_PRE = 0x1
2353 11:41:12.886302 WR_PST = 0x0
2354 11:41:12.886383 DBI_WR = 0x0
2355 11:41:12.889661 DBI_RD = 0x0
2356 11:41:12.889743 OTF = 0x1
2357 11:41:12.892891 ===================================
2358 11:41:12.899165 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2359 11:41:12.899250 ==
2360 11:41:12.902947 Dram Type= 6, Freq= 0, CH_0, rank 0
2361 11:41:12.906496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2362 11:41:12.909257 ==
2363 11:41:12.909338 [Duty_Offset_Calibration]
2364 11:41:12.912885 B0:2 B1:0 CA:3
2365 11:41:12.912966
2366 11:41:12.915918 [DutyScan_Calibration_Flow] k_type=0
2367 11:41:12.924566
2368 11:41:12.924647 ==CLK 0==
2369 11:41:12.927507 Final CLK duty delay cell = 0
2370 11:41:12.930799 [0] MAX Duty = 5062%(X100), DQS PI = 20
2371 11:41:12.934706 [0] MIN Duty = 4906%(X100), DQS PI = 54
2372 11:41:12.937654 [0] AVG Duty = 4984%(X100)
2373 11:41:12.937735
2374 11:41:12.940826 CH0 CLK Duty spec in!! Max-Min= 156%
2375 11:41:12.944531 [DutyScan_Calibration_Flow] ====Done====
2376 11:41:12.944650
2377 11:41:12.947794 [DutyScan_Calibration_Flow] k_type=1
2378 11:41:12.963840
2379 11:41:12.963948 ==DQS 0 ==
2380 11:41:12.967213 Final DQS duty delay cell = 0
2381 11:41:12.970766 [0] MAX Duty = 5093%(X100), DQS PI = 28
2382 11:41:12.973616 [0] MIN Duty = 4907%(X100), DQS PI = 2
2383 11:41:12.973718 [0] AVG Duty = 5000%(X100)
2384 11:41:12.977182
2385 11:41:12.977284 ==DQS 1 ==
2386 11:41:12.980696 Final DQS duty delay cell = 0
2387 11:41:12.983503 [0] MAX Duty = 5125%(X100), DQS PI = 34
2388 11:41:12.986773 [0] MIN Duty = 5031%(X100), DQS PI = 0
2389 11:41:12.986903 [0] AVG Duty = 5078%(X100)
2390 11:41:12.990076
2391 11:41:12.993386 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2392 11:41:12.993486
2393 11:41:12.996618 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2394 11:41:12.999891 [DutyScan_Calibration_Flow] ====Done====
2395 11:41:12.999989
2396 11:41:13.003490 [DutyScan_Calibration_Flow] k_type=3
2397 11:41:13.020593
2398 11:41:13.020701 ==DQM 0 ==
2399 11:41:13.024083 Final DQM duty delay cell = 0
2400 11:41:13.027559 [0] MAX Duty = 5093%(X100), DQS PI = 12
2401 11:41:13.030883 [0] MIN Duty = 4907%(X100), DQS PI = 0
2402 11:41:13.034276 [0] AVG Duty = 5000%(X100)
2403 11:41:13.034376
2404 11:41:13.034468 ==DQM 1 ==
2405 11:41:13.037177 Final DQM duty delay cell = 4
2406 11:41:13.040413 [4] MAX Duty = 5124%(X100), DQS PI = 50
2407 11:41:13.043805 [4] MIN Duty = 5031%(X100), DQS PI = 12
2408 11:41:13.047270 [4] AVG Duty = 5077%(X100)
2409 11:41:13.047387
2410 11:41:13.050438 CH0 DQM 0 Duty spec in!! Max-Min= 186%
2411 11:41:13.050545
2412 11:41:13.053972 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2413 11:41:13.057002 [DutyScan_Calibration_Flow] ====Done====
2414 11:41:13.057082
2415 11:41:13.060359 [DutyScan_Calibration_Flow] k_type=2
2416 11:41:13.075868
2417 11:41:13.075947 ==DQ 0 ==
2418 11:41:13.078708 Final DQ duty delay cell = -4
2419 11:41:13.082331 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2420 11:41:13.085748 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2421 11:41:13.089318 [-4] AVG Duty = 4953%(X100)
2422 11:41:13.089388
2423 11:41:13.089447 ==DQ 1 ==
2424 11:41:13.092492 Final DQ duty delay cell = -4
2425 11:41:13.095693 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2426 11:41:13.098868 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2427 11:41:13.102176 [-4] AVG Duty = 4938%(X100)
2428 11:41:13.102251
2429 11:41:13.105485 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2430 11:41:13.105611
2431 11:41:13.108665 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2432 11:41:13.111995 [DutyScan_Calibration_Flow] ====Done====
2433 11:41:13.112095 ==
2434 11:41:13.115107 Dram Type= 6, Freq= 0, CH_1, rank 0
2435 11:41:13.118366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2436 11:41:13.118476 ==
2437 11:41:13.121792 [Duty_Offset_Calibration]
2438 11:41:13.121893 B0:1 B1:-3 CA:0
2439 11:41:13.121986
2440 11:41:13.125387 [DutyScan_Calibration_Flow] k_type=0
2441 11:41:13.136049
2442 11:41:13.136152 ==CLK 0==
2443 11:41:13.139708 Final CLK duty delay cell = 0
2444 11:41:13.142381 [0] MAX Duty = 5031%(X100), DQS PI = 50
2445 11:41:13.145947 [0] MIN Duty = 4875%(X100), DQS PI = 24
2446 11:41:13.149041 [0] AVG Duty = 4953%(X100)
2447 11:41:13.149150
2448 11:41:13.152885 CH1 CLK Duty spec in!! Max-Min= 156%
2449 11:41:13.156146 [DutyScan_Calibration_Flow] ====Done====
2450 11:41:13.156229
2451 11:41:13.159401 [DutyScan_Calibration_Flow] k_type=1
2452 11:41:13.174781
2453 11:41:13.174900 ==DQS 0 ==
2454 11:41:13.177700 Final DQS duty delay cell = -4
2455 11:41:13.181228 [-4] MAX Duty = 5031%(X100), DQS PI = 56
2456 11:41:13.184516 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2457 11:41:13.188030 [-4] AVG Duty = 4969%(X100)
2458 11:41:13.188150
2459 11:41:13.188252 ==DQS 1 ==
2460 11:41:13.191207 Final DQS duty delay cell = 0
2461 11:41:13.194371 [0] MAX Duty = 5094%(X100), DQS PI = 32
2462 11:41:13.197673 [0] MIN Duty = 4844%(X100), DQS PI = 58
2463 11:41:13.201050 [0] AVG Duty = 4969%(X100)
2464 11:41:13.201169
2465 11:41:13.204716 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2466 11:41:13.204801
2467 11:41:13.207563 CH1 DQS 1 Duty spec in!! Max-Min= 250%
2468 11:41:13.211352 [DutyScan_Calibration_Flow] ====Done====
2469 11:41:13.211438
2470 11:41:13.214511 [DutyScan_Calibration_Flow] k_type=3
2471 11:41:13.231161
2472 11:41:13.231316 ==DQM 0 ==
2473 11:41:13.234536 Final DQM duty delay cell = 0
2474 11:41:13.238105 [0] MAX Duty = 5000%(X100), DQS PI = 54
2475 11:41:13.241421 [0] MIN Duty = 4876%(X100), DQS PI = 20
2476 11:41:13.244988 [0] AVG Duty = 4938%(X100)
2477 11:41:13.245071
2478 11:41:13.245137 ==DQM 1 ==
2479 11:41:13.247874 Final DQM duty delay cell = 0
2480 11:41:13.251278 [0] MAX Duty = 5031%(X100), DQS PI = 6
2481 11:41:13.255142 [0] MIN Duty = 4907%(X100), DQS PI = 46
2482 11:41:13.255226 [0] AVG Duty = 4969%(X100)
2483 11:41:13.258067
2484 11:41:13.261242 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2485 11:41:13.261325
2486 11:41:13.264516 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2487 11:41:13.268049 [DutyScan_Calibration_Flow] ====Done====
2488 11:41:13.268133
2489 11:41:13.271181 [DutyScan_Calibration_Flow] k_type=2
2490 11:41:13.287856
2491 11:41:13.288018 ==DQ 0 ==
2492 11:41:13.291334 Final DQ duty delay cell = 0
2493 11:41:13.294173 [0] MAX Duty = 5062%(X100), DQS PI = 0
2494 11:41:13.297661 [0] MIN Duty = 4938%(X100), DQS PI = 24
2495 11:41:13.297759 [0] AVG Duty = 5000%(X100)
2496 11:41:13.297881
2497 11:41:13.301324 ==DQ 1 ==
2498 11:41:13.304208 Final DQ duty delay cell = 0
2499 11:41:13.307408 [0] MAX Duty = 5124%(X100), DQS PI = 14
2500 11:41:13.311127 [0] MIN Duty = 4938%(X100), DQS PI = 58
2501 11:41:13.311238 [0] AVG Duty = 5031%(X100)
2502 11:41:13.311333
2503 11:41:13.317605 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2504 11:41:13.317716
2505 11:41:13.320758 CH1 DQ 1 Duty spec in!! Max-Min= 186%
2506 11:41:13.324025 [DutyScan_Calibration_Flow] ====Done====
2507 11:41:13.327182 nWR fixed to 30
2508 11:41:13.327295 [ModeRegInit_LP4] CH0 RK0
2509 11:41:13.330871 [ModeRegInit_LP4] CH0 RK1
2510 11:41:13.334007 [ModeRegInit_LP4] CH1 RK0
2511 11:41:13.337381 [ModeRegInit_LP4] CH1 RK1
2512 11:41:13.337505 match AC timing 7
2513 11:41:13.344138 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2514 11:41:13.347081 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2515 11:41:13.350538 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2516 11:41:13.357614 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2517 11:41:13.360829 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2518 11:41:13.360942 ==
2519 11:41:13.364107 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 11:41:13.367180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 11:41:13.367295 ==
2522 11:41:13.374075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2523 11:41:13.380168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2524 11:41:13.387738 [CA 0] Center 40 (10~71) winsize 62
2525 11:41:13.390992 [CA 1] Center 39 (9~70) winsize 62
2526 11:41:13.394051 [CA 2] Center 36 (6~66) winsize 61
2527 11:41:13.397628 [CA 3] Center 35 (5~66) winsize 62
2528 11:41:13.401082 [CA 4] Center 34 (4~65) winsize 62
2529 11:41:13.403973 [CA 5] Center 33 (3~63) winsize 61
2530 11:41:13.404041
2531 11:41:13.407337 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2532 11:41:13.407405
2533 11:41:13.410803 [CATrainingPosCal] consider 1 rank data
2534 11:41:13.414423 u2DelayCellTimex100 = 270/100 ps
2535 11:41:13.417649 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2536 11:41:13.424221 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2537 11:41:13.427530 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2538 11:41:13.430664 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 11:41:13.433848 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2540 11:41:13.437208 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2541 11:41:13.437293
2542 11:41:13.440550 CA PerBit enable=1, Macro0, CA PI delay=33
2543 11:41:13.440635
2544 11:41:13.444017 [CBTSetCACLKResult] CA Dly = 33
2545 11:41:13.447451 CS Dly: 7 (0~38)
2546 11:41:13.447536 ==
2547 11:41:13.451036 Dram Type= 6, Freq= 0, CH_0, rank 1
2548 11:41:13.453646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2549 11:41:13.453731 ==
2550 11:41:13.460651 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2551 11:41:13.463552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2552 11:41:13.473606 [CA 0] Center 40 (10~70) winsize 61
2553 11:41:13.476932 [CA 1] Center 39 (9~70) winsize 62
2554 11:41:13.480602 [CA 2] Center 35 (5~66) winsize 62
2555 11:41:13.483476 [CA 3] Center 35 (5~66) winsize 62
2556 11:41:13.486695 [CA 4] Center 34 (4~65) winsize 62
2557 11:41:13.490161 [CA 5] Center 33 (3~64) winsize 62
2558 11:41:13.490245
2559 11:41:13.493620 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2560 11:41:13.493712
2561 11:41:13.497089 [CATrainingPosCal] consider 2 rank data
2562 11:41:13.500715 u2DelayCellTimex100 = 270/100 ps
2563 11:41:13.503550 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2564 11:41:13.510500 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2565 11:41:13.513573 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2566 11:41:13.516962 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2567 11:41:13.520167 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2568 11:41:13.523472 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2569 11:41:13.523599
2570 11:41:13.526562 CA PerBit enable=1, Macro0, CA PI delay=33
2571 11:41:13.526668
2572 11:41:13.529889 [CBTSetCACLKResult] CA Dly = 33
2573 11:41:13.533253 CS Dly: 8 (0~40)
2574 11:41:13.533336
2575 11:41:13.536690 ----->DramcWriteLeveling(PI) begin...
2576 11:41:13.536810 ==
2577 11:41:13.539922 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 11:41:13.543239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 11:41:13.543319 ==
2580 11:41:13.546850 Write leveling (Byte 0): 32 => 32
2581 11:41:13.549922 Write leveling (Byte 1): 30 => 30
2582 11:41:13.553131 DramcWriteLeveling(PI) end<-----
2583 11:41:13.553218
2584 11:41:13.553286 ==
2585 11:41:13.556691 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 11:41:13.559543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 11:41:13.559627 ==
2588 11:41:13.563075 [Gating] SW mode calibration
2589 11:41:13.569910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2590 11:41:13.576634 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2591 11:41:13.579869 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 11:41:13.583174 0 15 4 | B1->B0 | 2727 3333 | 0 1 | (0 0) (1 1)
2593 11:41:13.589432 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 11:41:13.593171 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 11:41:13.596005 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 11:41:13.602986 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 11:41:13.606493 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 11:41:13.609446 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2599 11:41:13.616479 1 0 0 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (0 0)
2600 11:41:13.619647 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 11:41:13.622977 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 11:41:13.629240 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 11:41:13.633074 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 11:41:13.636288 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 11:41:13.642804 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 11:41:13.646249 1 0 28 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
2607 11:41:13.649121 1 1 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2608 11:41:13.655827 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2609 11:41:13.659207 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 11:41:13.662511 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 11:41:13.669097 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 11:41:13.672505 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 11:41:13.675976 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 11:41:13.682162 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2615 11:41:13.685561 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2616 11:41:13.689192 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2617 11:41:13.695669 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:41:13.699085 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:41:13.702717 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:41:13.708928 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:41:13.712245 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:41:13.715760 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 11:41:13.718685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:41:13.725570 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:41:13.728777 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:41:13.732108 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:41:13.738763 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:41:13.741968 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:41:13.745701 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:41:13.752036 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2631 11:41:13.755272 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2632 11:41:13.759026 Total UI for P1: 0, mck2ui 16
2633 11:41:13.762155 best dqsien dly found for B0: ( 1, 3, 28)
2634 11:41:13.765523 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 11:41:13.768460 Total UI for P1: 0, mck2ui 16
2636 11:41:13.771841 best dqsien dly found for B1: ( 1, 4, 0)
2637 11:41:13.775347 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2638 11:41:13.778268 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2639 11:41:13.778376
2640 11:41:13.785515 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2641 11:41:13.788466 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2642 11:41:13.791707 [Gating] SW calibration Done
2643 11:41:13.791792 ==
2644 11:41:13.794937 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 11:41:13.798658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 11:41:13.798770 ==
2647 11:41:13.798868 RX Vref Scan: 0
2648 11:41:13.798934
2649 11:41:13.801560 RX Vref 0 -> 0, step: 1
2650 11:41:13.801676
2651 11:41:13.804976 RX Delay -40 -> 252, step: 8
2652 11:41:13.808362 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2653 11:41:13.811839 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2654 11:41:13.818203 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2655 11:41:13.821743 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2656 11:41:13.825240 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2657 11:41:13.828017 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2658 11:41:13.831448 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2659 11:41:13.834729 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2660 11:41:13.841306 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2661 11:41:13.844664 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2662 11:41:13.847953 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2663 11:41:13.851424 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2664 11:41:13.854588 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2665 11:41:13.861092 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2666 11:41:13.864756 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2667 11:41:13.868100 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2668 11:41:13.868175 ==
2669 11:41:13.871380 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 11:41:13.874771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 11:41:13.877721 ==
2672 11:41:13.877798 DQS Delay:
2673 11:41:13.877862 DQS0 = 0, DQS1 = 0
2674 11:41:13.881253 DQM Delay:
2675 11:41:13.881321 DQM0 = 112, DQM1 = 101
2676 11:41:13.884757 DQ Delay:
2677 11:41:13.887893 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2678 11:41:13.891142 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2679 11:41:13.894626 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2680 11:41:13.897871 DQ12 =111, DQ13 =107, DQ14 =111, DQ15 =111
2681 11:41:13.897947
2682 11:41:13.898013
2683 11:41:13.898072 ==
2684 11:41:13.901157 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 11:41:13.904258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 11:41:13.904349 ==
2687 11:41:13.904415
2688 11:41:13.904477
2689 11:41:13.907909 TX Vref Scan disable
2690 11:41:13.911414 == TX Byte 0 ==
2691 11:41:13.914481 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2692 11:41:13.917598 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2693 11:41:13.921069 == TX Byte 1 ==
2694 11:41:13.924056 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2695 11:41:13.927553 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2696 11:41:13.927634 ==
2697 11:41:13.930783 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 11:41:13.937213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 11:41:13.937297 ==
2700 11:41:13.948057 TX Vref=22, minBit 5, minWin=25, winSum=421
2701 11:41:13.951245 TX Vref=24, minBit 7, minWin=26, winSum=432
2702 11:41:13.954561 TX Vref=26, minBit 1, minWin=26, winSum=435
2703 11:41:13.957726 TX Vref=28, minBit 5, minWin=27, winSum=445
2704 11:41:13.961007 TX Vref=30, minBit 8, minWin=26, winSum=440
2705 11:41:13.967494 TX Vref=32, minBit 1, minWin=26, winSum=437
2706 11:41:13.970782 [TxChooseVref] Worse bit 5, Min win 27, Win sum 445, Final Vref 28
2707 11:41:13.970887
2708 11:41:13.974111 Final TX Range 1 Vref 28
2709 11:41:13.974194
2710 11:41:13.974299 ==
2711 11:41:13.977750 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 11:41:13.981114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 11:41:13.984104 ==
2714 11:41:13.984208
2715 11:41:13.984290
2716 11:41:13.984382 TX Vref Scan disable
2717 11:41:13.987582 == TX Byte 0 ==
2718 11:41:13.991030 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2719 11:41:13.997464 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2720 11:41:13.997564 == TX Byte 1 ==
2721 11:41:14.000821 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2722 11:41:14.007626 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2723 11:41:14.007709
2724 11:41:14.007789 [DATLAT]
2725 11:41:14.007916 Freq=1200, CH0 RK0
2726 11:41:14.008024
2727 11:41:14.010678 DATLAT Default: 0xd
2728 11:41:14.013705 0, 0xFFFF, sum = 0
2729 11:41:14.013790 1, 0xFFFF, sum = 0
2730 11:41:14.017685 2, 0xFFFF, sum = 0
2731 11:41:14.017784 3, 0xFFFF, sum = 0
2732 11:41:14.021055 4, 0xFFFF, sum = 0
2733 11:41:14.021157 5, 0xFFFF, sum = 0
2734 11:41:14.023869 6, 0xFFFF, sum = 0
2735 11:41:14.023970 7, 0xFFFF, sum = 0
2736 11:41:14.027351 8, 0xFFFF, sum = 0
2737 11:41:14.027451 9, 0xFFFF, sum = 0
2738 11:41:14.030272 10, 0xFFFF, sum = 0
2739 11:41:14.030356 11, 0xFFFF, sum = 0
2740 11:41:14.033780 12, 0x0, sum = 1
2741 11:41:14.033888 13, 0x0, sum = 2
2742 11:41:14.037276 14, 0x0, sum = 3
2743 11:41:14.037355 15, 0x0, sum = 4
2744 11:41:14.040757 best_step = 13
2745 11:41:14.040881
2746 11:41:14.040983 ==
2747 11:41:14.043877 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 11:41:14.047446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 11:41:14.047556 ==
2750 11:41:14.050199 RX Vref Scan: 1
2751 11:41:14.050272
2752 11:41:14.050334 Set Vref Range= 32 -> 127
2753 11:41:14.050397
2754 11:41:14.053457 RX Vref 32 -> 127, step: 1
2755 11:41:14.053556
2756 11:41:14.056649 RX Delay -37 -> 252, step: 4
2757 11:41:14.056801
2758 11:41:14.059971 Set Vref, RX VrefLevel [Byte0]: 32
2759 11:41:14.063266 [Byte1]: 32
2760 11:41:14.063345
2761 11:41:14.066951 Set Vref, RX VrefLevel [Byte0]: 33
2762 11:41:14.069912 [Byte1]: 33
2763 11:41:14.074384
2764 11:41:14.074458 Set Vref, RX VrefLevel [Byte0]: 34
2765 11:41:14.077669 [Byte1]: 34
2766 11:41:14.082373
2767 11:41:14.082459 Set Vref, RX VrefLevel [Byte0]: 35
2768 11:41:14.085713 [Byte1]: 35
2769 11:41:14.090214
2770 11:41:14.090319 Set Vref, RX VrefLevel [Byte0]: 36
2771 11:41:14.097013 [Byte1]: 36
2772 11:41:14.097097
2773 11:41:14.100451 Set Vref, RX VrefLevel [Byte0]: 37
2774 11:41:14.103352 [Byte1]: 37
2775 11:41:14.103433
2776 11:41:14.106726 Set Vref, RX VrefLevel [Byte0]: 38
2777 11:41:14.110058 [Byte1]: 38
2778 11:41:14.114599
2779 11:41:14.114700 Set Vref, RX VrefLevel [Byte0]: 39
2780 11:41:14.117826 [Byte1]: 39
2781 11:41:14.122292
2782 11:41:14.122372 Set Vref, RX VrefLevel [Byte0]: 40
2783 11:41:14.125487 [Byte1]: 40
2784 11:41:14.130315
2785 11:41:14.130405 Set Vref, RX VrefLevel [Byte0]: 41
2786 11:41:14.133675 [Byte1]: 41
2787 11:41:14.138117
2788 11:41:14.138191 Set Vref, RX VrefLevel [Byte0]: 42
2789 11:41:14.141836 [Byte1]: 42
2790 11:41:14.146187
2791 11:41:14.146263 Set Vref, RX VrefLevel [Byte0]: 43
2792 11:41:14.149628 [Byte1]: 43
2793 11:41:14.154120
2794 11:41:14.154203 Set Vref, RX VrefLevel [Byte0]: 44
2795 11:41:14.157420 [Byte1]: 44
2796 11:41:14.162183
2797 11:41:14.162299 Set Vref, RX VrefLevel [Byte0]: 45
2798 11:41:14.165814 [Byte1]: 45
2799 11:41:14.170141
2800 11:41:14.170244 Set Vref, RX VrefLevel [Byte0]: 46
2801 11:41:14.173259 [Byte1]: 46
2802 11:41:14.178232
2803 11:41:14.178312 Set Vref, RX VrefLevel [Byte0]: 47
2804 11:41:14.181918 [Byte1]: 47
2805 11:41:14.186293
2806 11:41:14.186407 Set Vref, RX VrefLevel [Byte0]: 48
2807 11:41:14.189568 [Byte1]: 48
2808 11:41:14.194210
2809 11:41:14.194283 Set Vref, RX VrefLevel [Byte0]: 49
2810 11:41:14.197854 [Byte1]: 49
2811 11:41:14.202462
2812 11:41:14.202563 Set Vref, RX VrefLevel [Byte0]: 50
2813 11:41:14.205222 [Byte1]: 50
2814 11:41:14.209968
2815 11:41:14.210045 Set Vref, RX VrefLevel [Byte0]: 51
2816 11:41:14.213387 [Byte1]: 51
2817 11:41:14.218383
2818 11:41:14.218493 Set Vref, RX VrefLevel [Byte0]: 52
2819 11:41:14.221738 [Byte1]: 52
2820 11:41:14.226176
2821 11:41:14.226287 Set Vref, RX VrefLevel [Byte0]: 53
2822 11:41:14.229595 [Byte1]: 53
2823 11:41:14.234024
2824 11:41:14.234137 Set Vref, RX VrefLevel [Byte0]: 54
2825 11:41:14.237462 [Byte1]: 54
2826 11:41:14.242082
2827 11:41:14.242159 Set Vref, RX VrefLevel [Byte0]: 55
2828 11:41:14.245427 [Byte1]: 55
2829 11:41:14.250118
2830 11:41:14.250192 Set Vref, RX VrefLevel [Byte0]: 56
2831 11:41:14.253603 [Byte1]: 56
2832 11:41:14.258122
2833 11:41:14.261409 Set Vref, RX VrefLevel [Byte0]: 57
2834 11:41:14.264582 [Byte1]: 57
2835 11:41:14.264688
2836 11:41:14.267916 Set Vref, RX VrefLevel [Byte0]: 58
2837 11:41:14.271078 [Byte1]: 58
2838 11:41:14.271157
2839 11:41:14.274407 Set Vref, RX VrefLevel [Byte0]: 59
2840 11:41:14.277869 [Byte1]: 59
2841 11:41:14.282130
2842 11:41:14.282227 Set Vref, RX VrefLevel [Byte0]: 60
2843 11:41:14.285421 [Byte1]: 60
2844 11:41:14.290159
2845 11:41:14.290273 Set Vref, RX VrefLevel [Byte0]: 61
2846 11:41:14.293449 [Byte1]: 61
2847 11:41:14.298590
2848 11:41:14.298697 Set Vref, RX VrefLevel [Byte0]: 62
2849 11:41:14.301493 [Byte1]: 62
2850 11:41:14.306714
2851 11:41:14.306816 Set Vref, RX VrefLevel [Byte0]: 63
2852 11:41:14.309618 [Byte1]: 63
2853 11:41:14.314177
2854 11:41:14.314269 Set Vref, RX VrefLevel [Byte0]: 64
2855 11:41:14.317248 [Byte1]: 64
2856 11:41:14.322459
2857 11:41:14.322535 Set Vref, RX VrefLevel [Byte0]: 65
2858 11:41:14.325279 [Byte1]: 65
2859 11:41:14.330174
2860 11:41:14.330283 Set Vref, RX VrefLevel [Byte0]: 66
2861 11:41:14.333828 [Byte1]: 66
2862 11:41:14.338219
2863 11:41:14.338322 Set Vref, RX VrefLevel [Byte0]: 67
2864 11:41:14.341776 [Byte1]: 67
2865 11:41:14.346227
2866 11:41:14.346319 Set Vref, RX VrefLevel [Byte0]: 68
2867 11:41:14.349543 [Byte1]: 68
2868 11:41:14.354088
2869 11:41:14.354220 Set Vref, RX VrefLevel [Byte0]: 69
2870 11:41:14.360487 [Byte1]: 69
2871 11:41:14.360591
2872 11:41:14.363858 Set Vref, RX VrefLevel [Byte0]: 70
2873 11:41:14.367226 [Byte1]: 70
2874 11:41:14.367330
2875 11:41:14.370467 Set Vref, RX VrefLevel [Byte0]: 71
2876 11:41:14.374239 [Byte1]: 71
2877 11:41:14.378469
2878 11:41:14.378570 Set Vref, RX VrefLevel [Byte0]: 72
2879 11:41:14.381586 [Byte1]: 72
2880 11:41:14.386778
2881 11:41:14.386915 Set Vref, RX VrefLevel [Byte0]: 73
2882 11:41:14.389685 [Byte1]: 73
2883 11:41:14.394606
2884 11:41:14.394726 Set Vref, RX VrefLevel [Byte0]: 74
2885 11:41:14.397799 [Byte1]: 74
2886 11:41:14.402041
2887 11:41:14.402143 Final RX Vref Byte 0 = 62 to rank0
2888 11:41:14.405883 Final RX Vref Byte 1 = 53 to rank0
2889 11:41:14.408929 Final RX Vref Byte 0 = 62 to rank1
2890 11:41:14.411973 Final RX Vref Byte 1 = 53 to rank1==
2891 11:41:14.415338 Dram Type= 6, Freq= 0, CH_0, rank 0
2892 11:41:14.422115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2893 11:41:14.422194 ==
2894 11:41:14.422259 DQS Delay:
2895 11:41:14.422333 DQS0 = 0, DQS1 = 0
2896 11:41:14.425409 DQM Delay:
2897 11:41:14.425515 DQM0 = 111, DQM1 = 101
2898 11:41:14.429134 DQ Delay:
2899 11:41:14.432165 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2900 11:41:14.435445 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2901 11:41:14.438538 DQ8 =90, DQ9 =86, DQ10 =102, DQ11 =94
2902 11:41:14.441831 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2903 11:41:14.441906
2904 11:41:14.441975
2905 11:41:14.452105 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2906 11:41:14.452195 CH0 RK0: MR19=303, MR18=F9F9
2907 11:41:14.458425 CH0_RK0: MR19=0x303, MR18=0xF9F9, DQSOSC=412, MR23=63, INC=38, DEC=25
2908 11:41:14.458529
2909 11:41:14.461922 ----->DramcWriteLeveling(PI) begin...
2910 11:41:14.462005 ==
2911 11:41:14.464902 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 11:41:14.471683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 11:41:14.471787 ==
2914 11:41:14.475016 Write leveling (Byte 0): 32 => 32
2915 11:41:14.475127 Write leveling (Byte 1): 30 => 30
2916 11:41:14.478231 DramcWriteLeveling(PI) end<-----
2917 11:41:14.478334
2918 11:41:14.481436 ==
2919 11:41:14.481539 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 11:41:14.488610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 11:41:14.488714 ==
2922 11:41:14.491782 [Gating] SW mode calibration
2923 11:41:14.497892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2924 11:41:14.501076 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2925 11:41:14.508171 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2926 11:41:14.511455 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 11:41:14.514628 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 11:41:14.521130 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 11:41:14.524921 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 11:41:14.527982 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 11:41:14.534618 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 11:41:14.537639 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2933 11:41:14.541110 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2934 11:41:14.547435 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 11:41:14.550735 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 11:41:14.554261 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 11:41:14.560657 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 11:41:14.564118 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 11:41:14.567629 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2940 11:41:14.574041 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2941 11:41:14.577243 1 1 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2942 11:41:14.580590 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 11:41:14.587676 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:41:14.590902 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 11:41:14.594221 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 11:41:14.600748 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:41:14.603982 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 11:41:14.607064 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2949 11:41:14.614291 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2950 11:41:14.617046 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:41:14.620591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:41:14.627018 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:41:14.630459 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:41:14.634030 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:41:14.640040 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:41:14.643453 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:41:14.646706 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:41:14.653803 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 11:41:14.656568 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 11:41:14.660538 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 11:41:14.666778 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 11:41:14.670261 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 11:41:14.673375 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2964 11:41:14.680134 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2965 11:41:14.683229 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2966 11:41:14.686491 Total UI for P1: 0, mck2ui 16
2967 11:41:14.689784 best dqsien dly found for B0: ( 1, 3, 26)
2968 11:41:14.693129 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 11:41:14.696760 Total UI for P1: 0, mck2ui 16
2970 11:41:14.699912 best dqsien dly found for B1: ( 1, 4, 0)
2971 11:41:14.703126 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2972 11:41:14.706735 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2973 11:41:14.706872
2974 11:41:14.709601 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2975 11:41:14.713322 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2976 11:41:14.716576 [Gating] SW calibration Done
2977 11:41:14.716682 ==
2978 11:41:14.719849 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 11:41:14.726566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 11:41:14.726673 ==
2981 11:41:14.726768 RX Vref Scan: 0
2982 11:41:14.726868
2983 11:41:14.729472 RX Vref 0 -> 0, step: 1
2984 11:41:14.729571
2985 11:41:14.732963 RX Delay -40 -> 252, step: 8
2986 11:41:14.736199 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2987 11:41:14.739627 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2988 11:41:14.743079 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2989 11:41:14.746367 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2990 11:41:14.752735 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2991 11:41:14.756574 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2992 11:41:14.759558 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2993 11:41:14.763336 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2994 11:41:14.766158 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2995 11:41:14.772999 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2996 11:41:14.775864 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2997 11:41:14.779338 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2998 11:41:14.782851 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2999 11:41:14.785754 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3000 11:41:14.792493 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3001 11:41:14.796153 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3002 11:41:14.796258 ==
3003 11:41:14.799468 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 11:41:14.802534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 11:41:14.802627 ==
3006 11:41:14.805694 DQS Delay:
3007 11:41:14.805797 DQS0 = 0, DQS1 = 0
3008 11:41:14.805890 DQM Delay:
3009 11:41:14.809462 DQM0 = 112, DQM1 = 101
3010 11:41:14.809568 DQ Delay:
3011 11:41:14.812218 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3012 11:41:14.815519 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3013 11:41:14.818749 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3014 11:41:14.826178 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
3015 11:41:14.826285
3016 11:41:14.826378
3017 11:41:14.826465 ==
3018 11:41:14.829055 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 11:41:14.831989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 11:41:14.832071 ==
3021 11:41:14.832169
3022 11:41:14.832228
3023 11:41:14.835462 TX Vref Scan disable
3024 11:41:14.835543 == TX Byte 0 ==
3025 11:41:14.842164 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3026 11:41:14.845739 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3027 11:41:14.845835 == TX Byte 1 ==
3028 11:41:14.852339 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3029 11:41:14.855409 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3030 11:41:14.855491 ==
3031 11:41:14.858744 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 11:41:14.862333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 11:41:14.862417 ==
3034 11:41:14.874850 TX Vref=22, minBit 0, minWin=26, winSum=428
3035 11:41:14.878460 TX Vref=24, minBit 0, minWin=26, winSum=433
3036 11:41:14.881813 TX Vref=26, minBit 1, minWin=27, winSum=440
3037 11:41:14.885432 TX Vref=28, minBit 1, minWin=27, winSum=443
3038 11:41:14.888213 TX Vref=30, minBit 2, minWin=26, winSum=444
3039 11:41:14.895086 TX Vref=32, minBit 2, minWin=27, winSum=443
3040 11:41:14.898417 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 28
3041 11:41:14.898493
3042 11:41:14.901775 Final TX Range 1 Vref 28
3043 11:41:14.901871
3044 11:41:14.901933 ==
3045 11:41:14.904851 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 11:41:14.908446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 11:41:14.908524 ==
3048 11:41:14.911839
3049 11:41:14.911915
3050 11:41:14.911978 TX Vref Scan disable
3051 11:41:14.915069 == TX Byte 0 ==
3052 11:41:14.918386 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3053 11:41:14.921543 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3054 11:41:14.924700 == TX Byte 1 ==
3055 11:41:14.928364 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3056 11:41:14.934879 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3057 11:41:14.934978
3058 11:41:14.935045 [DATLAT]
3059 11:41:14.935108 Freq=1200, CH0 RK1
3060 11:41:14.935182
3061 11:41:14.938253 DATLAT Default: 0xd
3062 11:41:14.938354 0, 0xFFFF, sum = 0
3063 11:41:14.941751 1, 0xFFFF, sum = 0
3064 11:41:14.944525 2, 0xFFFF, sum = 0
3065 11:41:14.944641 3, 0xFFFF, sum = 0
3066 11:41:14.947893 4, 0xFFFF, sum = 0
3067 11:41:14.947979 5, 0xFFFF, sum = 0
3068 11:41:14.951339 6, 0xFFFF, sum = 0
3069 11:41:14.951426 7, 0xFFFF, sum = 0
3070 11:41:14.954991 8, 0xFFFF, sum = 0
3071 11:41:14.955069 9, 0xFFFF, sum = 0
3072 11:41:14.957755 10, 0xFFFF, sum = 0
3073 11:41:14.957830 11, 0xFFFF, sum = 0
3074 11:41:14.961085 12, 0x0, sum = 1
3075 11:41:14.961205 13, 0x0, sum = 2
3076 11:41:14.964574 14, 0x0, sum = 3
3077 11:41:14.964644 15, 0x0, sum = 4
3078 11:41:14.967757 best_step = 13
3079 11:41:14.967830
3080 11:41:14.967895 ==
3081 11:41:14.971190 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 11:41:14.974440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:41:14.974532 ==
3084 11:41:14.974624 RX Vref Scan: 0
3085 11:41:14.977789
3086 11:41:14.977864 RX Vref 0 -> 0, step: 1
3087 11:41:14.977926
3088 11:41:14.981235 RX Delay -37 -> 252, step: 4
3089 11:41:14.987426 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3090 11:41:14.990816 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3091 11:41:14.994326 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3092 11:41:14.997872 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3093 11:41:15.000737 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3094 11:41:15.007490 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3095 11:41:15.010857 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3096 11:41:15.014142 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3097 11:41:15.017758 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3098 11:41:15.020926 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3099 11:41:15.024181 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3100 11:41:15.030628 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3101 11:41:15.034459 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3102 11:41:15.037648 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3103 11:41:15.040788 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3104 11:41:15.047360 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3105 11:41:15.047447 ==
3106 11:41:15.050683 Dram Type= 6, Freq= 0, CH_0, rank 1
3107 11:41:15.054203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 11:41:15.054277 ==
3109 11:41:15.054339 DQS Delay:
3110 11:41:15.057674 DQS0 = 0, DQS1 = 0
3111 11:41:15.057750 DQM Delay:
3112 11:41:15.060690 DQM0 = 111, DQM1 = 101
3113 11:41:15.060764 DQ Delay:
3114 11:41:15.064124 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =110
3115 11:41:15.067535 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3116 11:41:15.070635 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3117 11:41:15.073724 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3118 11:41:15.073797
3119 11:41:15.073861
3120 11:41:15.083813 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3121 11:41:15.087172 CH0 RK1: MR19=403, MR18=13FB
3122 11:41:15.090662 CH0_RK1: MR19=0x403, MR18=0x13FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3123 11:41:15.093968 [RxdqsGatingPostProcess] freq 1200
3124 11:41:15.100439 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3125 11:41:15.103826 best DQS0 dly(2T, 0.5T) = (0, 11)
3126 11:41:15.107398 best DQS1 dly(2T, 0.5T) = (0, 12)
3127 11:41:15.110699 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3128 11:41:15.113634 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3129 11:41:15.117161 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 11:41:15.120569 best DQS1 dly(2T, 0.5T) = (0, 12)
3131 11:41:15.124050 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 11:41:15.126786 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3133 11:41:15.126911 Pre-setting of DQS Precalculation
3134 11:41:15.133807 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3135 11:41:15.133883 ==
3136 11:41:15.137145 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 11:41:15.140449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 11:41:15.140525 ==
3139 11:41:15.147021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 11:41:15.153547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3141 11:41:15.160887 [CA 0] Center 37 (7~67) winsize 61
3142 11:41:15.164129 [CA 1] Center 38 (8~68) winsize 61
3143 11:41:15.167748 [CA 2] Center 34 (4~65) winsize 62
3144 11:41:15.171166 [CA 3] Center 34 (4~64) winsize 61
3145 11:41:15.174041 [CA 4] Center 35 (5~65) winsize 61
3146 11:41:15.177797 [CA 5] Center 32 (3~62) winsize 60
3147 11:41:15.177871
3148 11:41:15.180925 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3149 11:41:15.181029
3150 11:41:15.184136 [CATrainingPosCal] consider 1 rank data
3151 11:41:15.187455 u2DelayCellTimex100 = 270/100 ps
3152 11:41:15.190760 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
3153 11:41:15.197951 CA1 delay=38 (8~68),Diff = 6 PI (28 cell)
3154 11:41:15.201224 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
3155 11:41:15.204146 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
3156 11:41:15.207476 CA4 delay=35 (5~65),Diff = 3 PI (14 cell)
3157 11:41:15.211000 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
3158 11:41:15.211082
3159 11:41:15.214527 CA PerBit enable=1, Macro0, CA PI delay=32
3160 11:41:15.214609
3161 11:41:15.217205 [CBTSetCACLKResult] CA Dly = 32
3162 11:41:15.220959 CS Dly: 7 (0~38)
3163 11:41:15.221058 ==
3164 11:41:15.224099 Dram Type= 6, Freq= 0, CH_1, rank 1
3165 11:41:15.227523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 11:41:15.227622 ==
3167 11:41:15.233847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3168 11:41:15.237069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3169 11:41:15.246607 [CA 0] Center 38 (8~68) winsize 61
3170 11:41:15.249798 [CA 1] Center 37 (7~68) winsize 62
3171 11:41:15.253504 [CA 2] Center 35 (5~65) winsize 61
3172 11:41:15.257021 [CA 3] Center 33 (3~64) winsize 62
3173 11:41:15.259793 [CA 4] Center 34 (4~65) winsize 62
3174 11:41:15.263371 [CA 5] Center 33 (3~64) winsize 62
3175 11:41:15.263462
3176 11:41:15.266792 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3177 11:41:15.266898
3178 11:41:15.269734 [CATrainingPosCal] consider 2 rank data
3179 11:41:15.273223 u2DelayCellTimex100 = 270/100 ps
3180 11:41:15.276747 CA0 delay=37 (8~67),Diff = 5 PI (24 cell)
3181 11:41:15.283069 CA1 delay=38 (8~68),Diff = 6 PI (28 cell)
3182 11:41:15.286438 CA2 delay=35 (5~65),Diff = 3 PI (14 cell)
3183 11:41:15.289460 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
3184 11:41:15.293043 CA4 delay=35 (5~65),Diff = 3 PI (14 cell)
3185 11:41:15.296271 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
3186 11:41:15.296374
3187 11:41:15.299682 CA PerBit enable=1, Macro0, CA PI delay=32
3188 11:41:15.299759
3189 11:41:15.302977 [CBTSetCACLKResult] CA Dly = 32
3190 11:41:15.306337 CS Dly: 8 (0~40)
3191 11:41:15.306437
3192 11:41:15.309491 ----->DramcWriteLeveling(PI) begin...
3193 11:41:15.309593 ==
3194 11:41:15.312415 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 11:41:15.315900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 11:41:15.315989 ==
3197 11:41:15.319244 Write leveling (Byte 0): 24 => 24
3198 11:41:15.322521 Write leveling (Byte 1): 28 => 28
3199 11:41:15.326011 DramcWriteLeveling(PI) end<-----
3200 11:41:15.326114
3201 11:41:15.326188 ==
3202 11:41:15.328908 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 11:41:15.332320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 11:41:15.332425 ==
3205 11:41:15.335678 [Gating] SW mode calibration
3206 11:41:15.342349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3207 11:41:15.349000 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3208 11:41:15.352230 0 15 0 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
3209 11:41:15.358692 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 11:41:15.361997 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 11:41:15.365479 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 11:41:15.369038 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 11:41:15.375270 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 11:41:15.378656 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 11:41:15.382121 0 15 28 | B1->B0 | 3232 3232 | 1 1 | (0 1) (1 0)
3216 11:41:15.388535 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3217 11:41:15.391926 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 11:41:15.395090 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 11:41:15.401984 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 11:41:15.405607 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 11:41:15.408348 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 11:41:15.414744 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 11:41:15.418321 1 0 28 | B1->B0 | 4040 3636 | 0 0 | (1 1) (0 0)
3224 11:41:15.421756 1 1 0 | B1->B0 | 3f3f 4242 | 1 0 | (0 0) (0 0)
3225 11:41:15.428503 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:41:15.431356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:41:15.434811 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 11:41:15.441684 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 11:41:15.445023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 11:41:15.448595 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 11:41:15.454694 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3232 11:41:15.458058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:41:15.461138 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:41:15.468196 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:41:15.471403 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:41:15.474506 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:41:15.481474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:41:15.485177 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:41:15.487776 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:41:15.494615 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:41:15.497969 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 11:41:15.501277 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 11:41:15.613834 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 11:41:15.614025 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 11:41:15.614144 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 11:41:15.614251 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 11:41:15.614361 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3248 11:41:15.614466 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 11:41:15.614561 Total UI for P1: 0, mck2ui 16
3250 11:41:15.614653 best dqsien dly found for B0: ( 1, 3, 28)
3251 11:41:15.614749 Total UI for P1: 0, mck2ui 16
3252 11:41:15.614860 best dqsien dly found for B1: ( 1, 3, 28)
3253 11:41:15.614925 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3254 11:41:15.614991 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3255 11:41:15.615050
3256 11:41:15.615108 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3257 11:41:15.615165 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3258 11:41:15.615228 [Gating] SW calibration Done
3259 11:41:15.615286 ==
3260 11:41:15.615342 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 11:41:15.615399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 11:41:15.615461 ==
3263 11:41:15.615519 RX Vref Scan: 0
3264 11:41:15.615575
3265 11:41:15.615631 RX Vref 0 -> 0, step: 1
3266 11:41:15.615687
3267 11:41:15.615747 RX Delay -40 -> 252, step: 8
3268 11:41:15.615804 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3269 11:41:15.615860 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3270 11:41:15.615916 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3271 11:41:15.615972 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3272 11:41:15.616034 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3273 11:41:15.616090 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3274 11:41:15.616145 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3275 11:41:15.616201 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3276 11:41:15.616256 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3277 11:41:15.616317 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3278 11:41:15.617057 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3279 11:41:15.620494 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3280 11:41:15.626657 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3281 11:41:15.630095 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3282 11:41:15.633502 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3283 11:41:15.637005 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3284 11:41:15.637125 ==
3285 11:41:15.639881 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 11:41:15.646682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 11:41:15.646860 ==
3288 11:41:15.646947 DQS Delay:
3289 11:41:15.647023 DQS0 = 0, DQS1 = 0
3290 11:41:15.650047 DQM Delay:
3291 11:41:15.650153 DQM0 = 115, DQM1 = 106
3292 11:41:15.653582 DQ Delay:
3293 11:41:15.656515 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3294 11:41:15.659948 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3295 11:41:15.663240 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3296 11:41:15.666709 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3297 11:41:15.666833
3298 11:41:15.666929
3299 11:41:15.667032 ==
3300 11:41:15.670271 Dram Type= 6, Freq= 0, CH_1, rank 0
3301 11:41:15.673577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3302 11:41:15.673661 ==
3303 11:41:15.673731
3304 11:41:15.676367
3305 11:41:15.676456 TX Vref Scan disable
3306 11:41:15.679590 == TX Byte 0 ==
3307 11:41:15.683232 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3308 11:41:15.686515 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3309 11:41:15.689796 == TX Byte 1 ==
3310 11:41:15.692922 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3311 11:41:15.696758 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3312 11:41:15.696834 ==
3313 11:41:15.699840 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 11:41:15.706063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 11:41:15.706167 ==
3316 11:41:15.717084 TX Vref=22, minBit 1, minWin=24, winSum=403
3317 11:41:15.720974 TX Vref=24, minBit 2, minWin=24, winSum=410
3318 11:41:15.723965 TX Vref=26, minBit 0, minWin=25, winSum=411
3319 11:41:15.727100 TX Vref=28, minBit 1, minWin=25, winSum=417
3320 11:41:15.730848 TX Vref=30, minBit 1, minWin=25, winSum=419
3321 11:41:15.737218 TX Vref=32, minBit 1, minWin=25, winSum=414
3322 11:41:15.740116 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 30
3323 11:41:15.740209
3324 11:41:15.743862 Final TX Range 1 Vref 30
3325 11:41:15.743948
3326 11:41:15.744019 ==
3327 11:41:15.747195 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 11:41:15.750573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 11:41:15.750659 ==
3330 11:41:15.753901
3331 11:41:15.753986
3332 11:41:15.754053 TX Vref Scan disable
3333 11:41:15.756807 == TX Byte 0 ==
3334 11:41:15.760244 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3335 11:41:15.763837 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3336 11:41:15.767228 == TX Byte 1 ==
3337 11:41:15.769998 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3338 11:41:15.776758 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3339 11:41:15.776846
3340 11:41:15.776914 [DATLAT]
3341 11:41:15.776977 Freq=1200, CH1 RK0
3342 11:41:15.777040
3343 11:41:15.780282 DATLAT Default: 0xd
3344 11:41:15.780362 0, 0xFFFF, sum = 0
3345 11:41:15.783477 1, 0xFFFF, sum = 0
3346 11:41:15.786676 2, 0xFFFF, sum = 0
3347 11:41:15.786778 3, 0xFFFF, sum = 0
3348 11:41:15.790259 4, 0xFFFF, sum = 0
3349 11:41:15.790341 5, 0xFFFF, sum = 0
3350 11:41:15.793530 6, 0xFFFF, sum = 0
3351 11:41:15.793615 7, 0xFFFF, sum = 0
3352 11:41:15.796778 8, 0xFFFF, sum = 0
3353 11:41:15.796885 9, 0xFFFF, sum = 0
3354 11:41:15.799798 10, 0xFFFF, sum = 0
3355 11:41:15.799874 11, 0xFFFF, sum = 0
3356 11:41:15.803269 12, 0x0, sum = 1
3357 11:41:15.803351 13, 0x0, sum = 2
3358 11:41:15.806642 14, 0x0, sum = 3
3359 11:41:15.806746 15, 0x0, sum = 4
3360 11:41:15.806848 best_step = 13
3361 11:41:15.810034
3362 11:41:15.810138 ==
3363 11:41:15.813199 Dram Type= 6, Freq= 0, CH_1, rank 0
3364 11:41:15.816802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3365 11:41:15.816909 ==
3366 11:41:15.817006 RX Vref Scan: 1
3367 11:41:15.817096
3368 11:41:15.820476 Set Vref Range= 32 -> 127
3369 11:41:15.820578
3370 11:41:15.823259 RX Vref 32 -> 127, step: 1
3371 11:41:15.823336
3372 11:41:15.826525 RX Delay -21 -> 252, step: 4
3373 11:41:15.826623
3374 11:41:15.829911 Set Vref, RX VrefLevel [Byte0]: 32
3375 11:41:15.833097 [Byte1]: 32
3376 11:41:15.833180
3377 11:41:15.836784 Set Vref, RX VrefLevel [Byte0]: 33
3378 11:41:15.840058 [Byte1]: 33
3379 11:41:15.843442
3380 11:41:15.843558 Set Vref, RX VrefLevel [Byte0]: 34
3381 11:41:15.846638 [Byte1]: 34
3382 11:41:15.851508
3383 11:41:15.851614 Set Vref, RX VrefLevel [Byte0]: 35
3384 11:41:15.854615 [Byte1]: 35
3385 11:41:15.859383
3386 11:41:15.859481 Set Vref, RX VrefLevel [Byte0]: 36
3387 11:41:15.862276 [Byte1]: 36
3388 11:41:15.867458
3389 11:41:15.867545 Set Vref, RX VrefLevel [Byte0]: 37
3390 11:41:15.870293 [Byte1]: 37
3391 11:41:15.874878
3392 11:41:15.874961 Set Vref, RX VrefLevel [Byte0]: 38
3393 11:41:15.878338 [Byte1]: 38
3394 11:41:15.882715
3395 11:41:15.882825 Set Vref, RX VrefLevel [Byte0]: 39
3396 11:41:15.886262 [Byte1]: 39
3397 11:41:15.891096
3398 11:41:15.891180 Set Vref, RX VrefLevel [Byte0]: 40
3399 11:41:15.894130 [Byte1]: 40
3400 11:41:15.898891
3401 11:41:15.898975 Set Vref, RX VrefLevel [Byte0]: 41
3402 11:41:15.902118 [Byte1]: 41
3403 11:41:15.907006
3404 11:41:15.907090 Set Vref, RX VrefLevel [Byte0]: 42
3405 11:41:15.909934 [Byte1]: 42
3406 11:41:15.914824
3407 11:41:15.914915 Set Vref, RX VrefLevel [Byte0]: 43
3408 11:41:15.918437 [Byte1]: 43
3409 11:41:15.922316
3410 11:41:15.922399 Set Vref, RX VrefLevel [Byte0]: 44
3411 11:41:15.925581 [Byte1]: 44
3412 11:41:15.930286
3413 11:41:15.930370 Set Vref, RX VrefLevel [Byte0]: 45
3414 11:41:15.933681 [Byte1]: 45
3415 11:41:15.938243
3416 11:41:15.938326 Set Vref, RX VrefLevel [Byte0]: 46
3417 11:41:15.941431 [Byte1]: 46
3418 11:41:15.946431
3419 11:41:15.946545 Set Vref, RX VrefLevel [Byte0]: 47
3420 11:41:15.949733 [Byte1]: 47
3421 11:41:15.954345
3422 11:41:15.954466 Set Vref, RX VrefLevel [Byte0]: 48
3423 11:41:15.957256 [Byte1]: 48
3424 11:41:15.962274
3425 11:41:15.962358 Set Vref, RX VrefLevel [Byte0]: 49
3426 11:41:15.965190 [Byte1]: 49
3427 11:41:15.970178
3428 11:41:15.970257 Set Vref, RX VrefLevel [Byte0]: 50
3429 11:41:15.973163 [Byte1]: 50
3430 11:41:15.977579
3431 11:41:15.981141 Set Vref, RX VrefLevel [Byte0]: 51
3432 11:41:15.981248 [Byte1]: 51
3433 11:41:15.985660
3434 11:41:15.985761 Set Vref, RX VrefLevel [Byte0]: 52
3435 11:41:15.989346 [Byte1]: 52
3436 11:41:15.994195
3437 11:41:15.994275 Set Vref, RX VrefLevel [Byte0]: 53
3438 11:41:15.997598 [Byte1]: 53
3439 11:41:16.001982
3440 11:41:16.002063 Set Vref, RX VrefLevel [Byte0]: 54
3441 11:41:16.005203 [Byte1]: 54
3442 11:41:16.009851
3443 11:41:16.009940 Set Vref, RX VrefLevel [Byte0]: 55
3444 11:41:16.013179 [Byte1]: 55
3445 11:41:16.017352
3446 11:41:16.017430 Set Vref, RX VrefLevel [Byte0]: 56
3447 11:41:16.021112 [Byte1]: 56
3448 11:41:16.025617
3449 11:41:16.025702 Set Vref, RX VrefLevel [Byte0]: 57
3450 11:41:16.029034 [Byte1]: 57
3451 11:41:16.033889
3452 11:41:16.033996 Set Vref, RX VrefLevel [Byte0]: 58
3453 11:41:16.036375 [Byte1]: 58
3454 11:41:16.041467
3455 11:41:16.041572 Set Vref, RX VrefLevel [Byte0]: 59
3456 11:41:16.044799 [Byte1]: 59
3457 11:41:16.049169
3458 11:41:16.049254 Set Vref, RX VrefLevel [Byte0]: 60
3459 11:41:16.052518 [Byte1]: 60
3460 11:41:16.057404
3461 11:41:16.057489 Set Vref, RX VrefLevel [Byte0]: 61
3462 11:41:16.060234 [Byte1]: 61
3463 11:41:16.065181
3464 11:41:16.065266 Set Vref, RX VrefLevel [Byte0]: 62
3465 11:41:16.068761 [Byte1]: 62
3466 11:41:16.073204
3467 11:41:16.073325 Set Vref, RX VrefLevel [Byte0]: 63
3468 11:41:16.076456 [Byte1]: 63
3469 11:41:16.080639
3470 11:41:16.080762 Set Vref, RX VrefLevel [Byte0]: 64
3471 11:41:16.084036 [Byte1]: 64
3472 11:41:16.088666
3473 11:41:16.088751 Set Vref, RX VrefLevel [Byte0]: 65
3474 11:41:16.092025 [Byte1]: 65
3475 11:41:16.096722
3476 11:41:16.096806 Set Vref, RX VrefLevel [Byte0]: 66
3477 11:41:16.100195 [Byte1]: 66
3478 11:41:16.104516
3479 11:41:16.104601 Set Vref, RX VrefLevel [Byte0]: 67
3480 11:41:16.108080 [Byte1]: 67
3481 11:41:16.112898
3482 11:41:16.112982 Set Vref, RX VrefLevel [Byte0]: 68
3483 11:41:16.116038 [Byte1]: 68
3484 11:41:16.120325
3485 11:41:16.120422 Final RX Vref Byte 0 = 56 to rank0
3486 11:41:16.123979 Final RX Vref Byte 1 = 51 to rank0
3487 11:41:16.127106 Final RX Vref Byte 0 = 56 to rank1
3488 11:41:16.130360 Final RX Vref Byte 1 = 51 to rank1==
3489 11:41:16.133979 Dram Type= 6, Freq= 0, CH_1, rank 0
3490 11:41:16.140317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 11:41:16.140427 ==
3492 11:41:16.140527 DQS Delay:
3493 11:41:16.140618 DQS0 = 0, DQS1 = 0
3494 11:41:16.143654 DQM Delay:
3495 11:41:16.143737 DQM0 = 116, DQM1 = 107
3496 11:41:16.147014 DQ Delay:
3497 11:41:16.150595 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3498 11:41:16.153489 DQ4 =110, DQ5 =124, DQ6 =128, DQ7 =114
3499 11:41:16.156796 DQ8 =94, DQ9 =100, DQ10 =106, DQ11 =102
3500 11:41:16.160469 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =116
3501 11:41:16.160553
3502 11:41:16.160619
3503 11:41:16.170398 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3504 11:41:16.170537 CH1 RK0: MR19=303, MR18=ECF3
3505 11:41:16.177183 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3506 11:41:16.177266
3507 11:41:16.180248 ----->DramcWriteLeveling(PI) begin...
3508 11:41:16.180331 ==
3509 11:41:16.183672 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 11:41:16.190516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 11:41:16.190624 ==
3512 11:41:16.194007 Write leveling (Byte 0): 26 => 26
3513 11:41:16.194105 Write leveling (Byte 1): 26 => 26
3514 11:41:16.196802 DramcWriteLeveling(PI) end<-----
3515 11:41:16.196887
3516 11:41:16.196958 ==
3517 11:41:16.200152 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 11:41:16.207346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 11:41:16.207430 ==
3520 11:41:16.210454 [Gating] SW mode calibration
3521 11:41:16.216470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3522 11:41:16.220102 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3523 11:41:16.226379 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3524 11:41:16.229623 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 11:41:16.233676 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 11:41:16.239707 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 11:41:16.243365 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 11:41:16.246318 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 11:41:16.253404 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 1)
3530 11:41:16.256705 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3531 11:41:16.259557 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 11:41:16.266327 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 11:41:16.270509 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 11:41:16.273180 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 11:41:16.279739 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 11:41:16.283257 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3537 11:41:16.286064 1 0 24 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
3538 11:41:16.292924 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:41:16.296374 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 11:41:16.299551 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 11:41:16.306082 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 11:41:16.309839 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 11:41:16.312414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 11:41:16.319323 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 11:41:16.322192 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3546 11:41:16.325506 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3547 11:41:16.332353 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:41:16.335875 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:41:16.338962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:41:16.345252 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:41:16.348903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:41:16.352325 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:41:16.358818 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:41:16.361824 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:41:16.365528 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 11:41:16.371711 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 11:41:16.375263 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 11:41:16.378489 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 11:41:16.385090 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 11:41:16.388108 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3561 11:41:16.391426 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3562 11:41:16.398218 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 11:41:16.398295 Total UI for P1: 0, mck2ui 16
3564 11:41:16.405174 best dqsien dly found for B0: ( 1, 3, 22)
3565 11:41:16.405252 Total UI for P1: 0, mck2ui 16
3566 11:41:16.411263 best dqsien dly found for B1: ( 1, 3, 24)
3567 11:41:16.414678 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3568 11:41:16.418059 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3569 11:41:16.418145
3570 11:41:16.420982 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3571 11:41:16.424427 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3572 11:41:16.427826 [Gating] SW calibration Done
3573 11:41:16.427925 ==
3574 11:41:16.431118 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 11:41:16.434488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 11:41:16.434591 ==
3577 11:41:16.437543 RX Vref Scan: 0
3578 11:41:16.437627
3579 11:41:16.437693 RX Vref 0 -> 0, step: 1
3580 11:41:16.437754
3581 11:41:16.441127 RX Delay -40 -> 252, step: 8
3582 11:41:16.444501 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3583 11:41:16.450815 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3584 11:41:16.453927 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3585 11:41:16.457723 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3586 11:41:16.460571 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3587 11:41:16.464181 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3588 11:41:16.470481 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3589 11:41:16.473890 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3590 11:41:16.477479 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3591 11:41:16.480662 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3592 11:41:16.484224 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3593 11:41:16.490389 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3594 11:41:16.493964 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3595 11:41:16.497121 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3596 11:41:16.500903 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3597 11:41:16.506955 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3598 11:41:16.507154 ==
3599 11:41:16.510401 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 11:41:16.513800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 11:41:16.513909 ==
3602 11:41:16.513975 DQS Delay:
3603 11:41:16.516720 DQS0 = 0, DQS1 = 0
3604 11:41:16.516806 DQM Delay:
3605 11:41:16.520134 DQM0 = 111, DQM1 = 109
3606 11:41:16.520220 DQ Delay:
3607 11:41:16.523592 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =111
3608 11:41:16.526724 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3609 11:41:16.530259 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3610 11:41:16.533659 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3611 11:41:16.533744
3612 11:41:16.533812
3613 11:41:16.533874 ==
3614 11:41:16.537125 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:41:16.543510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:41:16.543597 ==
3617 11:41:16.543666
3618 11:41:16.543728
3619 11:41:16.546555 TX Vref Scan disable
3620 11:41:16.546641 == TX Byte 0 ==
3621 11:41:16.549679 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 11:41:16.556877 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 11:41:16.556963 == TX Byte 1 ==
3624 11:41:16.559629 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3625 11:41:16.566702 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3626 11:41:16.566815 ==
3627 11:41:16.569614 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 11:41:16.572919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 11:41:16.573006 ==
3630 11:41:16.585251 TX Vref=22, minBit 1, minWin=25, winSum=415
3631 11:41:16.588011 TX Vref=24, minBit 1, minWin=25, winSum=422
3632 11:41:16.591651 TX Vref=26, minBit 0, minWin=26, winSum=426
3633 11:41:16.594780 TX Vref=28, minBit 7, minWin=25, winSum=426
3634 11:41:16.598155 TX Vref=30, minBit 0, minWin=26, winSum=425
3635 11:41:16.604675 TX Vref=32, minBit 0, minWin=26, winSum=425
3636 11:41:16.607901 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
3637 11:41:16.607987
3638 11:41:16.611255 Final TX Range 1 Vref 26
3639 11:41:16.611342
3640 11:41:16.611414 ==
3641 11:41:16.614599 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 11:41:16.617980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 11:41:16.620883 ==
3644 11:41:16.620994
3645 11:41:16.621095
3646 11:41:16.621188 TX Vref Scan disable
3647 11:41:16.625185 == TX Byte 0 ==
3648 11:41:16.628141 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3649 11:41:16.634559 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3650 11:41:16.634691 == TX Byte 1 ==
3651 11:41:16.638042 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3652 11:41:16.644486 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3653 11:41:16.644624
3654 11:41:16.644753 [DATLAT]
3655 11:41:16.644833 Freq=1200, CH1 RK1
3656 11:41:16.644961
3657 11:41:16.647750 DATLAT Default: 0xd
3658 11:41:16.651060 0, 0xFFFF, sum = 0
3659 11:41:16.651160 1, 0xFFFF, sum = 0
3660 11:41:16.654141 2, 0xFFFF, sum = 0
3661 11:41:16.654241 3, 0xFFFF, sum = 0
3662 11:41:16.657337 4, 0xFFFF, sum = 0
3663 11:41:16.657438 5, 0xFFFF, sum = 0
3664 11:41:16.661092 6, 0xFFFF, sum = 0
3665 11:41:16.661176 7, 0xFFFF, sum = 0
3666 11:41:16.664226 8, 0xFFFF, sum = 0
3667 11:41:16.664311 9, 0xFFFF, sum = 0
3668 11:41:16.667491 10, 0xFFFF, sum = 0
3669 11:41:16.667591 11, 0xFFFF, sum = 0
3670 11:41:16.670509 12, 0x0, sum = 1
3671 11:41:16.670610 13, 0x0, sum = 2
3672 11:41:16.674415 14, 0x0, sum = 3
3673 11:41:16.674489 15, 0x0, sum = 4
3674 11:41:16.677136 best_step = 13
3675 11:41:16.677208
3676 11:41:16.677269 ==
3677 11:41:16.680688 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 11:41:16.683699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 11:41:16.683776 ==
3680 11:41:16.687479 RX Vref Scan: 0
3681 11:41:16.687551
3682 11:41:16.687611 RX Vref 0 -> 0, step: 1
3683 11:41:16.687673
3684 11:41:16.690451 RX Delay -21 -> 252, step: 4
3685 11:41:16.697095 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3686 11:41:16.700201 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3687 11:41:16.703758 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3688 11:41:16.707021 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3689 11:41:16.709906 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3690 11:41:16.716622 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3691 11:41:16.720126 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3692 11:41:16.723464 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3693 11:41:16.726416 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3694 11:41:16.729749 iDelay=195, Bit 9, Center 102 (35 ~ 170) 136
3695 11:41:16.736548 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3696 11:41:16.740334 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3697 11:41:16.742910 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3698 11:41:16.746399 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3699 11:41:16.753254 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3700 11:41:16.756574 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3701 11:41:16.756654 ==
3702 11:41:16.759698 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 11:41:16.762741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 11:41:16.762873 ==
3705 11:41:16.766460 DQS Delay:
3706 11:41:16.766540 DQS0 = 0, DQS1 = 0
3707 11:41:16.766612 DQM Delay:
3708 11:41:16.769711 DQM0 = 112, DQM1 = 110
3709 11:41:16.769828 DQ Delay:
3710 11:41:16.772946 DQ0 =116, DQ1 =108, DQ2 =102, DQ3 =108
3711 11:41:16.776247 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =110
3712 11:41:16.779458 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =104
3713 11:41:16.786072 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3714 11:41:16.786166
3715 11:41:16.786233
3716 11:41:16.792460 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3717 11:41:16.795596 CH1 RK1: MR19=304, MR18=F808
3718 11:41:16.802297 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3719 11:41:16.805439 [RxdqsGatingPostProcess] freq 1200
3720 11:41:16.812005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3721 11:41:16.812086 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 11:41:16.815598 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 11:41:16.819075 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 11:41:16.821951 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 11:41:16.825468 best DQS0 dly(2T, 0.5T) = (0, 11)
3726 11:41:16.829227 best DQS1 dly(2T, 0.5T) = (0, 11)
3727 11:41:16.831639 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3728 11:41:16.835084 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3729 11:41:16.838450 Pre-setting of DQS Precalculation
3730 11:41:16.844979 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3731 11:41:16.851560 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3732 11:41:16.857999 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3733 11:41:16.858093
3734 11:41:16.858157
3735 11:41:16.861509 [Calibration Summary] 2400 Mbps
3736 11:41:16.861593 CH 0, Rank 0
3737 11:41:16.864688 SW Impedance : PASS
3738 11:41:16.868227 DUTY Scan : NO K
3739 11:41:16.868312 ZQ Calibration : PASS
3740 11:41:16.871392 Jitter Meter : NO K
3741 11:41:16.874690 CBT Training : PASS
3742 11:41:16.874802 Write leveling : PASS
3743 11:41:16.878252 RX DQS gating : PASS
3744 11:41:16.881580 RX DQ/DQS(RDDQC) : PASS
3745 11:41:16.881664 TX DQ/DQS : PASS
3746 11:41:16.884750 RX DATLAT : PASS
3747 11:41:16.888037 RX DQ/DQS(Engine): PASS
3748 11:41:16.888121 TX OE : NO K
3749 11:41:16.891314 All Pass.
3750 11:41:16.891399
3751 11:41:16.891465 CH 0, Rank 1
3752 11:41:16.895041 SW Impedance : PASS
3753 11:41:16.895124 DUTY Scan : NO K
3754 11:41:16.897465 ZQ Calibration : PASS
3755 11:41:16.901131 Jitter Meter : NO K
3756 11:41:16.901214 CBT Training : PASS
3757 11:41:16.904335 Write leveling : PASS
3758 11:41:16.907463 RX DQS gating : PASS
3759 11:41:16.907546 RX DQ/DQS(RDDQC) : PASS
3760 11:41:16.911095 TX DQ/DQS : PASS
3761 11:41:16.914351 RX DATLAT : PASS
3762 11:41:16.914436 RX DQ/DQS(Engine): PASS
3763 11:41:16.917215 TX OE : NO K
3764 11:41:16.917300 All Pass.
3765 11:41:16.917367
3766 11:41:16.920943 CH 1, Rank 0
3767 11:41:16.921028 SW Impedance : PASS
3768 11:41:16.924063 DUTY Scan : NO K
3769 11:41:16.924147 ZQ Calibration : PASS
3770 11:41:16.927331 Jitter Meter : NO K
3771 11:41:16.930805 CBT Training : PASS
3772 11:41:16.930899 Write leveling : PASS
3773 11:41:16.933653 RX DQS gating : PASS
3774 11:41:16.937035 RX DQ/DQS(RDDQC) : PASS
3775 11:41:16.937120 TX DQ/DQS : PASS
3776 11:41:16.940365 RX DATLAT : PASS
3777 11:41:16.943844 RX DQ/DQS(Engine): PASS
3778 11:41:16.943929 TX OE : NO K
3779 11:41:16.946618 All Pass.
3780 11:41:16.946701
3781 11:41:16.946767 CH 1, Rank 1
3782 11:41:16.950307 SW Impedance : PASS
3783 11:41:16.950391 DUTY Scan : NO K
3784 11:41:16.953562 ZQ Calibration : PASS
3785 11:41:16.956480 Jitter Meter : NO K
3786 11:41:16.956565 CBT Training : PASS
3787 11:41:16.959973 Write leveling : PASS
3788 11:41:16.963633 RX DQS gating : PASS
3789 11:41:16.963718 RX DQ/DQS(RDDQC) : PASS
3790 11:41:16.966858 TX DQ/DQS : PASS
3791 11:41:16.970171 RX DATLAT : PASS
3792 11:41:16.970256 RX DQ/DQS(Engine): PASS
3793 11:41:16.973080 TX OE : NO K
3794 11:41:16.973164 All Pass.
3795 11:41:16.973230
3796 11:41:16.976462 DramC Write-DBI off
3797 11:41:16.980370 PER_BANK_REFRESH: Hybrid Mode
3798 11:41:16.980455 TX_TRACKING: ON
3799 11:41:16.989934 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3800 11:41:16.993232 [FAST_K] Save calibration result to emmc
3801 11:41:16.996606 dramc_set_vcore_voltage set vcore to 650000
3802 11:41:17.000035 Read voltage for 600, 5
3803 11:41:17.000119 Vio18 = 0
3804 11:41:17.000186 Vcore = 650000
3805 11:41:17.002776 Vdram = 0
3806 11:41:17.002882 Vddq = 0
3807 11:41:17.002950 Vmddr = 0
3808 11:41:17.009557 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3809 11:41:17.012934 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3810 11:41:17.016228 MEM_TYPE=3, freq_sel=19
3811 11:41:17.019404 sv_algorithm_assistance_LP4_1600
3812 11:41:17.022600 ============ PULL DRAM RESETB DOWN ============
3813 11:41:17.026083 ========== PULL DRAM RESETB DOWN end =========
3814 11:41:17.033207 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3815 11:41:17.035796 ===================================
3816 11:41:17.039236 LPDDR4 DRAM CONFIGURATION
3817 11:41:17.042701 ===================================
3818 11:41:17.042788 EX_ROW_EN[0] = 0x0
3819 11:41:17.046006 EX_ROW_EN[1] = 0x0
3820 11:41:17.046090 LP4Y_EN = 0x0
3821 11:41:17.049491 WORK_FSP = 0x0
3822 11:41:17.049601 WL = 0x2
3823 11:41:17.052484 RL = 0x2
3824 11:41:17.052567 BL = 0x2
3825 11:41:17.055996 RPST = 0x0
3826 11:41:17.056079 RD_PRE = 0x0
3827 11:41:17.058765 WR_PRE = 0x1
3828 11:41:17.062326 WR_PST = 0x0
3829 11:41:17.062410 DBI_WR = 0x0
3830 11:41:17.065719 DBI_RD = 0x0
3831 11:41:17.065802 OTF = 0x1
3832 11:41:17.069123 ===================================
3833 11:41:17.071974 ===================================
3834 11:41:17.072055 ANA top config
3835 11:41:17.075828 ===================================
3836 11:41:17.078682 DLL_ASYNC_EN = 0
3837 11:41:17.081913 ALL_SLAVE_EN = 1
3838 11:41:17.085683 NEW_RANK_MODE = 1
3839 11:41:17.088933 DLL_IDLE_MODE = 1
3840 11:41:17.089009 LP45_APHY_COMB_EN = 1
3841 11:41:17.092117 TX_ODT_DIS = 1
3842 11:41:17.095193 NEW_8X_MODE = 1
3843 11:41:17.098516 ===================================
3844 11:41:17.101928 ===================================
3845 11:41:17.105242 data_rate = 1200
3846 11:41:17.108596 CKR = 1
3847 11:41:17.112046 DQ_P2S_RATIO = 8
3848 11:41:17.115326 ===================================
3849 11:41:17.115411 CA_P2S_RATIO = 8
3850 11:41:17.118177 DQ_CA_OPEN = 0
3851 11:41:17.121649 DQ_SEMI_OPEN = 0
3852 11:41:17.124767 CA_SEMI_OPEN = 0
3853 11:41:17.128907 CA_FULL_RATE = 0
3854 11:41:17.131354 DQ_CKDIV4_EN = 1
3855 11:41:17.131500 CA_CKDIV4_EN = 1
3856 11:41:17.135107 CA_PREDIV_EN = 0
3857 11:41:17.137853 PH8_DLY = 0
3858 11:41:17.141348 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3859 11:41:17.144856 DQ_AAMCK_DIV = 4
3860 11:41:17.148232 CA_AAMCK_DIV = 4
3861 11:41:17.148337 CA_ADMCK_DIV = 4
3862 11:41:17.151029 DQ_TRACK_CA_EN = 0
3863 11:41:17.154441 CA_PICK = 600
3864 11:41:17.157842 CA_MCKIO = 600
3865 11:41:17.161462 MCKIO_SEMI = 0
3866 11:41:17.164190 PLL_FREQ = 2288
3867 11:41:17.167677 DQ_UI_PI_RATIO = 32
3868 11:41:17.171169 CA_UI_PI_RATIO = 0
3869 11:41:17.171330 ===================================
3870 11:41:17.174411 ===================================
3871 11:41:17.177309 memory_type:LPDDR4
3872 11:41:17.180681 GP_NUM : 10
3873 11:41:17.180820 SRAM_EN : 1
3874 11:41:17.184047 MD32_EN : 0
3875 11:41:17.187467 ===================================
3876 11:41:17.190677 [ANA_INIT] >>>>>>>>>>>>>>
3877 11:41:17.194003 <<<<<< [CONFIGURE PHASE]: ANA_TX
3878 11:41:17.197211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3879 11:41:17.200835 ===================================
3880 11:41:17.204474 data_rate = 1200,PCW = 0X5800
3881 11:41:17.207170 ===================================
3882 11:41:17.210473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3883 11:41:17.213920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3884 11:41:17.220814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3885 11:41:17.223738 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3886 11:41:17.227110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3887 11:41:17.230201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3888 11:41:17.233761 [ANA_INIT] flow start
3889 11:41:17.236979 [ANA_INIT] PLL >>>>>>>>
3890 11:41:17.237091 [ANA_INIT] PLL <<<<<<<<
3891 11:41:17.240338 [ANA_INIT] MIDPI >>>>>>>>
3892 11:41:17.243700 [ANA_INIT] MIDPI <<<<<<<<
3893 11:41:17.246903 [ANA_INIT] DLL >>>>>>>>
3894 11:41:17.246980 [ANA_INIT] flow end
3895 11:41:17.250249 ============ LP4 DIFF to SE enter ============
3896 11:41:17.256830 ============ LP4 DIFF to SE exit ============
3897 11:41:17.256941 [ANA_INIT] <<<<<<<<<<<<<
3898 11:41:17.259674 [Flow] Enable top DCM control >>>>>
3899 11:41:17.263220 [Flow] Enable top DCM control <<<<<
3900 11:41:17.266736 Enable DLL master slave shuffle
3901 11:41:17.273077 ==============================================================
3902 11:41:17.273162 Gating Mode config
3903 11:41:17.279861 ==============================================================
3904 11:41:17.283159 Config description:
3905 11:41:17.292810 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3906 11:41:17.299474 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3907 11:41:17.302751 SELPH_MODE 0: By rank 1: By Phase
3908 11:41:17.309088 ==============================================================
3909 11:41:17.312742 GAT_TRACK_EN = 1
3910 11:41:17.316008 RX_GATING_MODE = 2
3911 11:41:17.319006 RX_GATING_TRACK_MODE = 2
3912 11:41:17.319084 SELPH_MODE = 1
3913 11:41:17.322279 PICG_EARLY_EN = 1
3914 11:41:17.325905 VALID_LAT_VALUE = 1
3915 11:41:17.332123 ==============================================================
3916 11:41:17.335449 Enter into Gating configuration >>>>
3917 11:41:17.338848 Exit from Gating configuration <<<<
3918 11:41:17.341954 Enter into DVFS_PRE_config >>>>>
3919 11:41:17.351849 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3920 11:41:17.355278 Exit from DVFS_PRE_config <<<<<
3921 11:41:17.358612 Enter into PICG configuration >>>>
3922 11:41:17.361878 Exit from PICG configuration <<<<
3923 11:41:17.364786 [RX_INPUT] configuration >>>>>
3924 11:41:17.368205 [RX_INPUT] configuration <<<<<
3925 11:41:17.374672 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3926 11:41:17.378193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3927 11:41:17.384368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3928 11:41:17.391161 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3929 11:41:17.397549 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3930 11:41:17.404229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3931 11:41:17.407494 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3932 11:41:17.410803 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3933 11:41:17.414087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3934 11:41:17.420617 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3935 11:41:17.423999 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3936 11:41:17.427393 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 11:41:17.430964 ===================================
3938 11:41:17.433766 LPDDR4 DRAM CONFIGURATION
3939 11:41:17.437101 ===================================
3940 11:41:17.440421 EX_ROW_EN[0] = 0x0
3941 11:41:17.440515 EX_ROW_EN[1] = 0x0
3942 11:41:17.443745 LP4Y_EN = 0x0
3943 11:41:17.443822 WORK_FSP = 0x0
3944 11:41:17.447248 WL = 0x2
3945 11:41:17.447320 RL = 0x2
3946 11:41:17.450561 BL = 0x2
3947 11:41:17.450743 RPST = 0x0
3948 11:41:17.453856 RD_PRE = 0x0
3949 11:41:17.453956 WR_PRE = 0x1
3950 11:41:17.456820 WR_PST = 0x0
3951 11:41:17.456899 DBI_WR = 0x0
3952 11:41:17.460435 DBI_RD = 0x0
3953 11:41:17.460546 OTF = 0x1
3954 11:41:17.463407 ===================================
3955 11:41:17.470190 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3956 11:41:17.473390 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3957 11:41:17.476885 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3958 11:41:17.480213 ===================================
3959 11:41:17.483226 LPDDR4 DRAM CONFIGURATION
3960 11:41:17.486838 ===================================
3961 11:41:17.490104 EX_ROW_EN[0] = 0x10
3962 11:41:17.490177 EX_ROW_EN[1] = 0x0
3963 11:41:17.493246 LP4Y_EN = 0x0
3964 11:41:17.493358 WORK_FSP = 0x0
3965 11:41:17.496760 WL = 0x2
3966 11:41:17.496865 RL = 0x2
3967 11:41:17.499787 BL = 0x2
3968 11:41:17.499866 RPST = 0x0
3969 11:41:17.503177 RD_PRE = 0x0
3970 11:41:17.503250 WR_PRE = 0x1
3971 11:41:17.506701 WR_PST = 0x0
3972 11:41:17.506804 DBI_WR = 0x0
3973 11:41:17.510079 DBI_RD = 0x0
3974 11:41:17.510152 OTF = 0x1
3975 11:41:17.513027 ===================================
3976 11:41:17.520027 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3977 11:41:17.524601 nWR fixed to 30
3978 11:41:17.527808 [ModeRegInit_LP4] CH0 RK0
3979 11:41:17.527905 [ModeRegInit_LP4] CH0 RK1
3980 11:41:17.531526 [ModeRegInit_LP4] CH1 RK0
3981 11:41:17.534697 [ModeRegInit_LP4] CH1 RK1
3982 11:41:17.534808 match AC timing 17
3983 11:41:17.541148 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3984 11:41:17.544363 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3985 11:41:17.547577 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3986 11:41:17.554320 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3987 11:41:17.557761 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3988 11:41:17.557840 ==
3989 11:41:17.560524 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 11:41:17.564116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 11:41:17.564193 ==
3992 11:41:17.570402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 11:41:17.577534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3994 11:41:17.580422 [CA 0] Center 37 (7~67) winsize 61
3995 11:41:17.583791 [CA 1] Center 37 (7~67) winsize 61
3996 11:41:17.587170 [CA 2] Center 35 (5~65) winsize 61
3997 11:41:17.590532 [CA 3] Center 35 (5~65) winsize 61
3998 11:41:17.593810 [CA 4] Center 34 (4~65) winsize 62
3999 11:41:17.596767 [CA 5] Center 34 (4~64) winsize 61
4000 11:41:17.596843
4001 11:41:17.600225 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4002 11:41:17.600318
4003 11:41:17.603741 [CATrainingPosCal] consider 1 rank data
4004 11:41:17.607272 u2DelayCellTimex100 = 270/100 ps
4005 11:41:17.610170 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4006 11:41:17.613554 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4007 11:41:17.616742 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4008 11:41:17.623786 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4009 11:41:17.627023 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4010 11:41:17.630143 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4011 11:41:17.630212
4012 11:41:17.633444 CA PerBit enable=1, Macro0, CA PI delay=34
4013 11:41:17.633519
4014 11:41:17.636571 [CBTSetCACLKResult] CA Dly = 34
4015 11:41:17.636668 CS Dly: 6 (0~37)
4016 11:41:17.636763 ==
4017 11:41:17.640235 Dram Type= 6, Freq= 0, CH_0, rank 1
4018 11:41:17.646560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 11:41:17.646669 ==
4020 11:41:17.649828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4021 11:41:17.656522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4022 11:41:17.660028 [CA 0] Center 37 (7~67) winsize 61
4023 11:41:17.663444 [CA 1] Center 37 (7~67) winsize 61
4024 11:41:17.666518 [CA 2] Center 35 (5~65) winsize 61
4025 11:41:17.669651 [CA 3] Center 34 (4~65) winsize 62
4026 11:41:17.673347 [CA 4] Center 34 (4~64) winsize 61
4027 11:41:17.676561 [CA 5] Center 33 (3~64) winsize 62
4028 11:41:17.676650
4029 11:41:17.679739 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4030 11:41:17.679822
4031 11:41:17.683021 [CATrainingPosCal] consider 2 rank data
4032 11:41:17.686286 u2DelayCellTimex100 = 270/100 ps
4033 11:41:17.692710 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4034 11:41:17.696077 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4035 11:41:17.699242 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4036 11:41:17.702950 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4037 11:41:17.706174 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4038 11:41:17.709103 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4039 11:41:17.709178
4040 11:41:17.712549 CA PerBit enable=1, Macro0, CA PI delay=34
4041 11:41:17.712624
4042 11:41:17.715930 [CBTSetCACLKResult] CA Dly = 34
4043 11:41:17.719361 CS Dly: 6 (0~38)
4044 11:41:17.719437
4045 11:41:17.722595 ----->DramcWriteLeveling(PI) begin...
4046 11:41:17.722695 ==
4047 11:41:17.725776 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 11:41:17.729001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 11:41:17.729108 ==
4050 11:41:17.732183 Write leveling (Byte 0): 35 => 35
4051 11:41:17.735319 Write leveling (Byte 1): 32 => 32
4052 11:41:17.738611 DramcWriteLeveling(PI) end<-----
4053 11:41:17.738717
4054 11:41:17.738813 ==
4055 11:41:17.741872 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 11:41:17.745542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 11:41:17.745647 ==
4058 11:41:17.748643 [Gating] SW mode calibration
4059 11:41:17.755496 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4060 11:41:17.761927 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4061 11:41:17.765261 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 11:41:17.768690 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4063 11:41:17.775459 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 11:41:17.778286 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4065 11:41:17.785477 0 9 16 | B1->B0 | 3131 2828 | 0 0 | (0 1) (0 0)
4066 11:41:17.788023 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:41:17.791780 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:41:17.798251 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 11:41:17.801544 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 11:41:17.804912 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 11:41:17.807819 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 11:41:17.814743 0 10 12 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
4073 11:41:17.818144 0 10 16 | B1->B0 | 2d2d 3b3b | 0 0 | (0 0) (0 0)
4074 11:41:17.820989 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:41:17.827687 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:41:17.831205 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 11:41:17.838017 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 11:41:17.841041 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 11:41:17.844204 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 11:41:17.850663 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 11:41:17.854105 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4082 11:41:17.857370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4083 11:41:17.864075 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:41:17.867237 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:41:17.870575 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:41:17.876922 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:41:17.880396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:41:17.883812 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:41:17.890108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:41:17.893793 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:41:17.896838 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:41:17.903593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 11:41:17.906774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 11:41:17.910219 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 11:41:17.916530 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 11:41:17.920009 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 11:41:17.923824 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4098 11:41:17.929706 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 11:41:17.929805 Total UI for P1: 0, mck2ui 16
4100 11:41:17.933120 best dqsien dly found for B0: ( 0, 13, 16)
4101 11:41:17.936997 Total UI for P1: 0, mck2ui 16
4102 11:41:17.940008 best dqsien dly found for B1: ( 0, 13, 18)
4103 11:41:17.946594 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4104 11:41:17.949841 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4105 11:41:17.949924
4106 11:41:17.953259 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4107 11:41:17.956341 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4108 11:41:17.959753 [Gating] SW calibration Done
4109 11:41:17.959837 ==
4110 11:41:17.962461 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 11:41:17.966362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 11:41:17.966460 ==
4113 11:41:17.969285 RX Vref Scan: 0
4114 11:41:17.969368
4115 11:41:17.969433 RX Vref 0 -> 0, step: 1
4116 11:41:17.969495
4117 11:41:17.972640 RX Delay -230 -> 252, step: 16
4118 11:41:17.979111 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4119 11:41:17.982602 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4120 11:41:17.985894 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4121 11:41:17.988787 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4122 11:41:17.995694 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4123 11:41:17.999070 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4124 11:41:18.002436 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4125 11:41:18.005286 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4126 11:41:18.008670 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4127 11:41:18.015486 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4128 11:41:18.018872 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4129 11:41:18.022376 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4130 11:41:18.025367 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4131 11:41:18.032163 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4132 11:41:18.035646 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4133 11:41:18.038807 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4134 11:41:18.038952 ==
4135 11:41:18.042068 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 11:41:18.045281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 11:41:18.048991 ==
4138 11:41:18.049095 DQS Delay:
4139 11:41:18.049174 DQS0 = 0, DQS1 = 0
4140 11:41:18.051759 DQM Delay:
4141 11:41:18.051873 DQM0 = 38, DQM1 = 29
4142 11:41:18.055210 DQ Delay:
4143 11:41:18.058563 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4144 11:41:18.058646 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4145 11:41:18.061785 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4146 11:41:18.068225 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4147 11:41:18.068310
4148 11:41:18.068391
4149 11:41:18.068467 ==
4150 11:41:18.071825 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 11:41:18.075119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 11:41:18.075203 ==
4153 11:41:18.075269
4154 11:41:18.075329
4155 11:41:18.078247 TX Vref Scan disable
4156 11:41:18.078329 == TX Byte 0 ==
4157 11:41:18.084624 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4158 11:41:18.088380 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4159 11:41:18.088468 == TX Byte 1 ==
4160 11:41:18.094711 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4161 11:41:18.098261 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4162 11:41:18.098344 ==
4163 11:41:18.101247 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 11:41:18.104660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 11:41:18.104743 ==
4166 11:41:18.104809
4167 11:41:18.107829
4168 11:41:18.107911 TX Vref Scan disable
4169 11:41:18.111659 == TX Byte 0 ==
4170 11:41:18.114521 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4171 11:41:18.121476 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4172 11:41:18.121562 == TX Byte 1 ==
4173 11:41:18.124813 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4174 11:41:18.131097 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4175 11:41:18.131181
4176 11:41:18.131246 [DATLAT]
4177 11:41:18.131307 Freq=600, CH0 RK0
4178 11:41:18.131366
4179 11:41:18.134768 DATLAT Default: 0x9
4180 11:41:18.137780 0, 0xFFFF, sum = 0
4181 11:41:18.137880 1, 0xFFFF, sum = 0
4182 11:41:18.141181 2, 0xFFFF, sum = 0
4183 11:41:18.141264 3, 0xFFFF, sum = 0
4184 11:41:18.144586 4, 0xFFFF, sum = 0
4185 11:41:18.144670 5, 0xFFFF, sum = 0
4186 11:41:18.147363 6, 0xFFFF, sum = 0
4187 11:41:18.147458 7, 0xFFFF, sum = 0
4188 11:41:18.150793 8, 0x0, sum = 1
4189 11:41:18.150918 9, 0x0, sum = 2
4190 11:41:18.154583 10, 0x0, sum = 3
4191 11:41:18.154666 11, 0x0, sum = 4
4192 11:41:18.154769 best_step = 9
4193 11:41:18.154886
4194 11:41:18.157541 ==
4195 11:41:18.160893 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 11:41:18.164144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 11:41:18.164227 ==
4198 11:41:18.164293 RX Vref Scan: 1
4199 11:41:18.164353
4200 11:41:18.167344 RX Vref 0 -> 0, step: 1
4201 11:41:18.167427
4202 11:41:18.170977 RX Delay -195 -> 252, step: 8
4203 11:41:18.171075
4204 11:41:18.174100 Set Vref, RX VrefLevel [Byte0]: 62
4205 11:41:18.177331 [Byte1]: 53
4206 11:41:18.177414
4207 11:41:18.180988 Final RX Vref Byte 0 = 62 to rank0
4208 11:41:18.184000 Final RX Vref Byte 1 = 53 to rank0
4209 11:41:18.187252 Final RX Vref Byte 0 = 62 to rank1
4210 11:41:18.190475 Final RX Vref Byte 1 = 53 to rank1==
4211 11:41:18.193954 Dram Type= 6, Freq= 0, CH_0, rank 0
4212 11:41:18.197190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 11:41:18.200121 ==
4214 11:41:18.200204 DQS Delay:
4215 11:41:18.200270 DQS0 = 0, DQS1 = 0
4216 11:41:18.203575 DQM Delay:
4217 11:41:18.203658 DQM0 = 34, DQM1 = 29
4218 11:41:18.206553 DQ Delay:
4219 11:41:18.209897 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =28
4220 11:41:18.213271 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4221 11:41:18.217245 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4222 11:41:18.220088 DQ12 =32, DQ13 =36, DQ14 =44, DQ15 =36
4223 11:41:18.220167
4224 11:41:18.220231
4225 11:41:18.227078 [DQSOSCAuto] RK0, (LSB)MR18= 0x4140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4226 11:41:18.229662 CH0 RK0: MR19=808, MR18=4140
4227 11:41:18.236674 CH0_RK0: MR19=0x808, MR18=0x4140, DQSOSC=397, MR23=63, INC=166, DEC=110
4228 11:41:18.236766
4229 11:41:18.239792 ----->DramcWriteLeveling(PI) begin...
4230 11:41:18.239868 ==
4231 11:41:18.243321 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 11:41:18.246238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 11:41:18.246337 ==
4234 11:41:18.249639 Write leveling (Byte 0): 33 => 33
4235 11:41:18.253189 Write leveling (Byte 1): 33 => 33
4236 11:41:18.256064 DramcWriteLeveling(PI) end<-----
4237 11:41:18.256154
4238 11:41:18.256235 ==
4239 11:41:18.259465 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 11:41:18.262795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 11:41:18.266199 ==
4242 11:41:18.266299 [Gating] SW mode calibration
4243 11:41:18.275904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4244 11:41:18.279252 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4245 11:41:18.282280 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4246 11:41:18.289191 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4247 11:41:18.292286 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4248 11:41:18.295565 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4249 11:41:18.302243 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4250 11:41:18.305640 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:41:18.308737 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 11:41:18.315235 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 11:41:18.318810 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 11:41:18.322234 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 11:41:18.328572 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4256 11:41:18.331946 0 10 12 | B1->B0 | 2525 3333 | 0 0 | (0 0) (1 1)
4257 11:41:18.335411 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4258 11:41:18.341938 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:41:18.345303 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:41:18.348480 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 11:41:18.354891 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 11:41:18.358410 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 11:41:18.361395 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 11:41:18.368313 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4265 11:41:18.371907 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4266 11:41:18.374901 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:41:18.381351 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:41:18.385106 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:41:18.387848 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:41:18.394751 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:41:18.398200 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:41:18.401471 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:41:18.407678 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:41:18.411264 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:41:18.414689 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 11:41:18.421436 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 11:41:18.424309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 11:41:18.427741 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 11:41:18.434393 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 11:41:18.437865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4281 11:41:18.440889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 11:41:18.444032 Total UI for P1: 0, mck2ui 16
4283 11:41:18.447561 best dqsien dly found for B0: ( 0, 13, 12)
4284 11:41:18.450918 Total UI for P1: 0, mck2ui 16
4285 11:41:18.453719 best dqsien dly found for B1: ( 0, 13, 12)
4286 11:41:18.457238 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4287 11:41:18.460612 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4288 11:41:18.464087
4289 11:41:18.467030 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4290 11:41:18.470281 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4291 11:41:18.473824 [Gating] SW calibration Done
4292 11:41:18.473903 ==
4293 11:41:18.477253 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 11:41:18.480270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 11:41:18.480374 ==
4296 11:41:18.483589 RX Vref Scan: 0
4297 11:41:18.483687
4298 11:41:18.483763 RX Vref 0 -> 0, step: 1
4299 11:41:18.483822
4300 11:41:18.486998 RX Delay -230 -> 252, step: 16
4301 11:41:18.490098 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4302 11:41:18.496920 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4303 11:41:18.499769 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4304 11:41:18.503070 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4305 11:41:18.506276 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4306 11:41:18.512889 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4307 11:41:18.516301 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4308 11:41:18.519694 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4309 11:41:18.522795 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4310 11:41:18.526233 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4311 11:41:18.533125 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4312 11:41:18.536400 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4313 11:41:18.539595 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4314 11:41:18.542968 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4315 11:41:18.549389 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4316 11:41:18.552698 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4317 11:41:18.552810 ==
4318 11:41:18.556084 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 11:41:18.559056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 11:41:18.559166 ==
4321 11:41:18.562449 DQS Delay:
4322 11:41:18.562550 DQS0 = 0, DQS1 = 0
4323 11:41:18.565796 DQM Delay:
4324 11:41:18.565913 DQM0 = 36, DQM1 = 30
4325 11:41:18.566003 DQ Delay:
4326 11:41:18.569295 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4327 11:41:18.572735 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4328 11:41:18.576254 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4329 11:41:18.579012 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4330 11:41:18.579088
4331 11:41:18.579152
4332 11:41:18.582600 ==
4333 11:41:18.582703 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 11:41:18.589558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 11:41:18.589661 ==
4336 11:41:18.589762
4337 11:41:18.589854
4338 11:41:18.592896 TX Vref Scan disable
4339 11:41:18.592996 == TX Byte 0 ==
4340 11:41:18.595679 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4341 11:41:18.602219 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4342 11:41:18.602341 == TX Byte 1 ==
4343 11:41:18.608765 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4344 11:41:18.612300 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4345 11:41:18.612412 ==
4346 11:41:18.615554 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 11:41:18.618678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 11:41:18.618782 ==
4349 11:41:18.618917
4350 11:41:18.619045
4351 11:41:18.622069 TX Vref Scan disable
4352 11:41:18.625463 == TX Byte 0 ==
4353 11:41:18.628562 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4354 11:41:18.631880 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4355 11:41:18.634762 == TX Byte 1 ==
4356 11:41:18.638273 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4357 11:41:18.641515 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4358 11:41:18.641591
4359 11:41:18.645337 [DATLAT]
4360 11:41:18.645420 Freq=600, CH0 RK1
4361 11:41:18.645485
4362 11:41:18.648389 DATLAT Default: 0x9
4363 11:41:18.648471 0, 0xFFFF, sum = 0
4364 11:41:18.651683 1, 0xFFFF, sum = 0
4365 11:41:18.651768 2, 0xFFFF, sum = 0
4366 11:41:18.655215 3, 0xFFFF, sum = 0
4367 11:41:18.655299 4, 0xFFFF, sum = 0
4368 11:41:18.658053 5, 0xFFFF, sum = 0
4369 11:41:18.661525 6, 0xFFFF, sum = 0
4370 11:41:18.661637 7, 0xFFFF, sum = 0
4371 11:41:18.664810 8, 0x0, sum = 1
4372 11:41:18.664893 9, 0x0, sum = 2
4373 11:41:18.664959 10, 0x0, sum = 3
4374 11:41:18.667774 11, 0x0, sum = 4
4375 11:41:18.667857 best_step = 9
4376 11:41:18.667922
4377 11:41:18.667981 ==
4378 11:41:18.671187 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 11:41:18.678019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 11:41:18.678103 ==
4381 11:41:18.678167 RX Vref Scan: 0
4382 11:41:18.678228
4383 11:41:18.681471 RX Vref 0 -> 0, step: 1
4384 11:41:18.681577
4385 11:41:18.684397 RX Delay -195 -> 252, step: 8
4386 11:41:18.687816 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4387 11:41:18.694555 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4388 11:41:18.697902 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4389 11:41:18.701182 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4390 11:41:18.704319 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4391 11:41:18.711012 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4392 11:41:18.714084 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4393 11:41:18.717306 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4394 11:41:18.721092 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4395 11:41:18.724222 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4396 11:41:18.731047 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4397 11:41:18.734091 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4398 11:41:18.737499 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4399 11:41:18.743929 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4400 11:41:18.747431 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4401 11:41:18.750228 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4402 11:41:18.750309 ==
4403 11:41:18.753473 Dram Type= 6, Freq= 0, CH_0, rank 1
4404 11:41:18.756848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:41:18.756931 ==
4406 11:41:18.760447 DQS Delay:
4407 11:41:18.760528 DQS0 = 0, DQS1 = 0
4408 11:41:18.763300 DQM Delay:
4409 11:41:18.763396 DQM0 = 33, DQM1 = 27
4410 11:41:18.766623 DQ Delay:
4411 11:41:18.766703 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4412 11:41:18.770260 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4413 11:41:18.773496 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4414 11:41:18.776701 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4415 11:41:18.776782
4416 11:41:18.779950
4417 11:41:18.786650 [DQSOSCAuto] RK1, (LSB)MR18= 0x6938, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4418 11:41:18.790101 CH0 RK1: MR19=808, MR18=6938
4419 11:41:18.796550 CH0_RK1: MR19=0x808, MR18=0x6938, DQSOSC=390, MR23=63, INC=172, DEC=114
4420 11:41:18.799829 [RxdqsGatingPostProcess] freq 600
4421 11:41:18.803186 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4422 11:41:18.806515 Pre-setting of DQS Precalculation
4423 11:41:18.813111 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4424 11:41:18.813219 ==
4425 11:41:18.816335 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 11:41:18.819491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 11:41:18.819606 ==
4428 11:41:18.826229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4429 11:41:18.829300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4430 11:41:18.833557 [CA 0] Center 35 (5~66) winsize 62
4431 11:41:18.836928 [CA 1] Center 35 (5~66) winsize 62
4432 11:41:18.840144 [CA 2] Center 34 (4~65) winsize 62
4433 11:41:18.843443 [CA 3] Center 34 (4~65) winsize 62
4434 11:41:18.847149 [CA 4] Center 34 (4~65) winsize 62
4435 11:41:18.850436 [CA 5] Center 34 (4~64) winsize 61
4436 11:41:18.850548
4437 11:41:18.853292 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4438 11:41:18.853412
4439 11:41:18.856655 [CATrainingPosCal] consider 1 rank data
4440 11:41:18.860010 u2DelayCellTimex100 = 270/100 ps
4441 11:41:18.863120 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4442 11:41:18.869785 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4443 11:41:18.873176 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4444 11:41:18.876147 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4445 11:41:18.879680 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4446 11:41:18.883091 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4447 11:41:18.883176
4448 11:41:18.886098 CA PerBit enable=1, Macro0, CA PI delay=34
4449 11:41:18.886183
4450 11:41:18.889520 [CBTSetCACLKResult] CA Dly = 34
4451 11:41:18.893086 CS Dly: 4 (0~35)
4452 11:41:18.893195 ==
4453 11:41:18.895946 Dram Type= 6, Freq= 0, CH_1, rank 1
4454 11:41:18.899489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 11:41:18.899574 ==
4456 11:41:18.906243 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4457 11:41:18.909104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4458 11:41:18.914114 [CA 0] Center 35 (5~66) winsize 62
4459 11:41:18.916954 [CA 1] Center 36 (6~66) winsize 61
4460 11:41:18.920286 [CA 2] Center 34 (4~65) winsize 62
4461 11:41:18.923515 [CA 3] Center 34 (3~65) winsize 63
4462 11:41:18.926950 [CA 4] Center 34 (4~65) winsize 62
4463 11:41:18.930115 [CA 5] Center 33 (3~64) winsize 62
4464 11:41:18.930276
4465 11:41:18.933313 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4466 11:41:18.933397
4467 11:41:18.937070 [CATrainingPosCal] consider 2 rank data
4468 11:41:18.940104 u2DelayCellTimex100 = 270/100 ps
4469 11:41:18.943373 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4470 11:41:18.950031 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4471 11:41:18.953375 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4472 11:41:18.956897 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4473 11:41:18.959736 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4474 11:41:18.963015 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4475 11:41:18.963100
4476 11:41:18.966342 CA PerBit enable=1, Macro0, CA PI delay=34
4477 11:41:18.966424
4478 11:41:18.969574 [CBTSetCACLKResult] CA Dly = 34
4479 11:41:18.972899 CS Dly: 4 (0~36)
4480 11:41:18.972975
4481 11:41:18.976241 ----->DramcWriteLeveling(PI) begin...
4482 11:41:18.976332 ==
4483 11:41:18.979809 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 11:41:18.982710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 11:41:18.982813 ==
4486 11:41:18.986181 Write leveling (Byte 0): 28 => 28
4487 11:41:18.989600 Write leveling (Byte 1): 29 => 29
4488 11:41:18.992935 DramcWriteLeveling(PI) end<-----
4489 11:41:18.993020
4490 11:41:18.993082 ==
4491 11:41:18.996337 Dram Type= 6, Freq= 0, CH_1, rank 0
4492 11:41:18.999421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4493 11:41:18.999495 ==
4494 11:41:19.002841 [Gating] SW mode calibration
4495 11:41:19.009858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4496 11:41:19.015640 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4497 11:41:19.019169 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4498 11:41:19.022535 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4499 11:41:19.029515 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4500 11:41:19.032132 0 9 12 | B1->B0 | 3131 3131 | 1 1 | (1 1) (1 0)
4501 11:41:19.035458 0 9 16 | B1->B0 | 2424 2828 | 0 0 | (0 0) (1 1)
4502 11:41:19.042716 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 11:41:19.045775 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:41:19.048827 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 11:41:19.055257 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 11:41:19.058703 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 11:41:19.061874 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 11:41:19.068682 0 10 12 | B1->B0 | 3131 3030 | 1 0 | (0 0) (0 0)
4509 11:41:19.072414 0 10 16 | B1->B0 | 4343 4141 | 0 1 | (0 0) (0 0)
4510 11:41:19.075582 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:41:19.082262 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:41:19.084909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:41:19.088366 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 11:41:19.095039 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 11:41:19.098495 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 11:41:19.101331 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4517 11:41:19.108171 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:41:19.111534 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:41:19.114479 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:41:19.121157 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:41:19.124672 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:41:19.127963 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:41:19.134630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:41:19.137664 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:41:19.141227 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:41:19.147626 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:41:19.151076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:41:19.154016 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 11:41:19.160488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 11:41:19.163969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 11:41:19.167203 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4532 11:41:19.173936 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4533 11:41:19.177149 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 11:41:19.180511 Total UI for P1: 0, mck2ui 16
4535 11:41:19.183523 best dqsien dly found for B0: ( 0, 13, 14)
4536 11:41:19.187087 Total UI for P1: 0, mck2ui 16
4537 11:41:19.190476 best dqsien dly found for B1: ( 0, 13, 10)
4538 11:41:19.193917 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4539 11:41:19.197257 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4540 11:41:19.197339
4541 11:41:19.199994 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4542 11:41:19.207005 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4543 11:41:19.207089 [Gating] SW calibration Done
4544 11:41:19.209822 ==
4545 11:41:19.209904 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 11:41:19.216411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 11:41:19.216497 ==
4548 11:41:19.216572 RX Vref Scan: 0
4549 11:41:19.216636
4550 11:41:19.219989 RX Vref 0 -> 0, step: 1
4551 11:41:19.220074
4552 11:41:19.223346 RX Delay -230 -> 252, step: 16
4553 11:41:19.226586 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4554 11:41:19.230063 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4555 11:41:19.236548 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4556 11:41:19.239469 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4557 11:41:19.242798 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4558 11:41:19.246458 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4559 11:41:19.252603 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4560 11:41:19.255897 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4561 11:41:19.259566 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4562 11:41:19.262739 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4563 11:41:19.269730 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4564 11:41:19.272810 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4565 11:41:19.275836 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4566 11:41:19.278999 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4567 11:41:19.285940 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4568 11:41:19.289303 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4569 11:41:19.289423 ==
4570 11:41:19.292495 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 11:41:19.295788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 11:41:19.295873 ==
4573 11:41:19.298729 DQS Delay:
4574 11:41:19.298815 DQS0 = 0, DQS1 = 0
4575 11:41:19.298906 DQM Delay:
4576 11:41:19.301961 DQM0 = 39, DQM1 = 28
4577 11:41:19.302045 DQ Delay:
4578 11:41:19.305579 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4579 11:41:19.308968 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4580 11:41:19.311972 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4581 11:41:19.315468 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4582 11:41:19.315552
4583 11:41:19.315635
4584 11:41:19.315727 ==
4585 11:41:19.319002 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 11:41:19.325175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 11:41:19.325261 ==
4588 11:41:19.325360
4589 11:41:19.325421
4590 11:41:19.325480 TX Vref Scan disable
4591 11:41:19.329062 == TX Byte 0 ==
4592 11:41:19.332345 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4593 11:41:19.339014 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4594 11:41:19.339101 == TX Byte 1 ==
4595 11:41:19.341993 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4596 11:41:19.348833 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4597 11:41:19.348921 ==
4598 11:41:19.351710 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 11:41:19.355415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 11:41:19.355502 ==
4601 11:41:19.355569
4602 11:41:19.355630
4603 11:41:19.358586 TX Vref Scan disable
4604 11:41:19.361827 == TX Byte 0 ==
4605 11:41:19.365114 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4606 11:41:19.368257 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4607 11:41:19.371495 == TX Byte 1 ==
4608 11:41:19.374790 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4609 11:41:19.378360 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4610 11:41:19.378445
4611 11:41:19.381714 [DATLAT]
4612 11:41:19.381799 Freq=600, CH1 RK0
4613 11:41:19.381865
4614 11:41:19.384604 DATLAT Default: 0x9
4615 11:41:19.384690 0, 0xFFFF, sum = 0
4616 11:41:19.387992 1, 0xFFFF, sum = 0
4617 11:41:19.388077 2, 0xFFFF, sum = 0
4618 11:41:19.391800 3, 0xFFFF, sum = 0
4619 11:41:19.391885 4, 0xFFFF, sum = 0
4620 11:41:19.394571 5, 0xFFFF, sum = 0
4621 11:41:19.394656 6, 0xFFFF, sum = 0
4622 11:41:19.398039 7, 0xFFFF, sum = 0
4623 11:41:19.398125 8, 0x0, sum = 1
4624 11:41:19.401576 9, 0x0, sum = 2
4625 11:41:19.401661 10, 0x0, sum = 3
4626 11:41:19.404800 11, 0x0, sum = 4
4627 11:41:19.404885 best_step = 9
4628 11:41:19.404951
4629 11:41:19.405012 ==
4630 11:41:19.408084 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 11:41:19.411120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 11:41:19.414520 ==
4633 11:41:19.414607 RX Vref Scan: 1
4634 11:41:19.414674
4635 11:41:19.417873 RX Vref 0 -> 0, step: 1
4636 11:41:19.417959
4637 11:41:19.420755 RX Delay -195 -> 252, step: 8
4638 11:41:19.420839
4639 11:41:19.424145 Set Vref, RX VrefLevel [Byte0]: 56
4640 11:41:19.427562 [Byte1]: 51
4641 11:41:19.427647
4642 11:41:19.430992 Final RX Vref Byte 0 = 56 to rank0
4643 11:41:19.434329 Final RX Vref Byte 1 = 51 to rank0
4644 11:41:19.437239 Final RX Vref Byte 0 = 56 to rank1
4645 11:41:19.440602 Final RX Vref Byte 1 = 51 to rank1==
4646 11:41:19.444050 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 11:41:19.447797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 11:41:19.447883 ==
4649 11:41:19.450331 DQS Delay:
4650 11:41:19.450415 DQS0 = 0, DQS1 = 0
4651 11:41:19.450481 DQM Delay:
4652 11:41:19.453888 DQM0 = 39, DQM1 = 28
4653 11:41:19.453972 DQ Delay:
4654 11:41:19.457359 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4655 11:41:19.460295 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4656 11:41:19.463541 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4657 11:41:19.467472 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4658 11:41:19.467558
4659 11:41:19.467624
4660 11:41:19.476698 [DQSOSCAuto] RK0, (LSB)MR18= 0x2432, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4661 11:41:19.480200 CH1 RK0: MR19=808, MR18=2432
4662 11:41:19.486674 CH1_RK0: MR19=0x808, MR18=0x2432, DQSOSC=400, MR23=63, INC=163, DEC=109
4663 11:41:19.486755
4664 11:41:19.489771 ----->DramcWriteLeveling(PI) begin...
4665 11:41:19.489888 ==
4666 11:41:19.493058 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 11:41:19.496474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 11:41:19.496583 ==
4669 11:41:19.499819 Write leveling (Byte 0): 28 => 28
4670 11:41:19.502737 Write leveling (Byte 1): 31 => 31
4671 11:41:19.506722 DramcWriteLeveling(PI) end<-----
4672 11:41:19.506852
4673 11:41:19.506936 ==
4674 11:41:19.509742 Dram Type= 6, Freq= 0, CH_1, rank 1
4675 11:41:19.513373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 11:41:19.513451 ==
4677 11:41:19.515998 [Gating] SW mode calibration
4678 11:41:19.522424 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4679 11:41:19.529598 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4680 11:41:19.532748 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 11:41:19.535811 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4682 11:41:19.542547 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4683 11:41:19.545684 0 9 12 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 0)
4684 11:41:19.548801 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4685 11:41:19.555705 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 11:41:19.559191 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 11:41:19.562398 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 11:41:19.568934 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4689 11:41:19.572266 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 11:41:19.575537 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4691 11:41:19.582384 0 10 12 | B1->B0 | 2c2c 3d3d | 0 1 | (0 0) (0 0)
4692 11:41:19.585387 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4693 11:41:19.588244 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 11:41:19.595196 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:41:19.598410 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 11:41:19.601611 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 11:41:19.608303 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 11:41:19.611782 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 11:41:19.615134 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4700 11:41:19.621350 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:41:19.624834 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:41:19.628361 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:41:19.635005 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:41:19.638270 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:41:19.641626 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:41:19.647903 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:41:19.651299 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:41:19.654737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:41:19.661187 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:41:19.664701 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:41:19.667464 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 11:41:19.674460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 11:41:19.677595 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 11:41:19.681138 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4715 11:41:19.687690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4716 11:41:19.691017 Total UI for P1: 0, mck2ui 16
4717 11:41:19.694566 best dqsien dly found for B0: ( 0, 13, 8)
4718 11:41:19.697519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 11:41:19.700753 Total UI for P1: 0, mck2ui 16
4720 11:41:19.703733 best dqsien dly found for B1: ( 0, 13, 12)
4721 11:41:19.707568 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4722 11:41:19.710549 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4723 11:41:19.710646
4724 11:41:19.713940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4725 11:41:19.717309 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4726 11:41:19.720766 [Gating] SW calibration Done
4727 11:41:19.720849 ==
4728 11:41:19.723514 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 11:41:19.730571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 11:41:19.730654 ==
4731 11:41:19.730720 RX Vref Scan: 0
4732 11:41:19.730782
4733 11:41:19.733536 RX Vref 0 -> 0, step: 1
4734 11:41:19.733610
4735 11:41:19.737375 RX Delay -230 -> 252, step: 16
4736 11:41:19.740461 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4737 11:41:19.743415 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4738 11:41:19.749980 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4739 11:41:19.753429 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4740 11:41:19.756678 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4741 11:41:19.760141 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4742 11:41:19.763182 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4743 11:41:19.770406 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4744 11:41:19.773098 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4745 11:41:19.776511 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4746 11:41:19.779904 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4747 11:41:19.786244 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4748 11:41:19.789522 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4749 11:41:19.792922 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4750 11:41:19.796650 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4751 11:41:19.802526 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4752 11:41:19.802603 ==
4753 11:41:19.806524 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 11:41:19.809635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 11:41:19.809711 ==
4756 11:41:19.809773 DQS Delay:
4757 11:41:19.813074 DQS0 = 0, DQS1 = 0
4758 11:41:19.813148 DQM Delay:
4759 11:41:19.816005 DQM0 = 37, DQM1 = 29
4760 11:41:19.816075 DQ Delay:
4761 11:41:19.819209 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4762 11:41:19.822619 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4763 11:41:19.825997 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4764 11:41:19.829313 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4765 11:41:19.829391
4766 11:41:19.829454
4767 11:41:19.829516 ==
4768 11:41:19.832446 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 11:41:19.835791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 11:41:19.839192 ==
4771 11:41:19.839265
4772 11:41:19.839326
4773 11:41:19.839384 TX Vref Scan disable
4774 11:41:19.842024 == TX Byte 0 ==
4775 11:41:19.845960 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4776 11:41:19.848810 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4777 11:41:19.852221 == TX Byte 1 ==
4778 11:41:19.855577 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4779 11:41:19.862644 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4780 11:41:19.862741 ==
4781 11:41:19.865759 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 11:41:19.868386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 11:41:19.868486 ==
4784 11:41:19.868582
4785 11:41:19.868674
4786 11:41:19.871869 TX Vref Scan disable
4787 11:41:19.875373 == TX Byte 0 ==
4788 11:41:19.878193 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4789 11:41:19.881737 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4790 11:41:19.885070 == TX Byte 1 ==
4791 11:41:19.888529 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4792 11:41:19.891460 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4793 11:41:19.891560
4794 11:41:19.894971 [DATLAT]
4795 11:41:19.895069 Freq=600, CH1 RK1
4796 11:41:19.895166
4797 11:41:19.898268 DATLAT Default: 0x9
4798 11:41:19.898363 0, 0xFFFF, sum = 0
4799 11:41:19.901789 1, 0xFFFF, sum = 0
4800 11:41:19.901886 2, 0xFFFF, sum = 0
4801 11:41:19.905087 3, 0xFFFF, sum = 0
4802 11:41:19.905206 4, 0xFFFF, sum = 0
4803 11:41:19.908028 5, 0xFFFF, sum = 0
4804 11:41:19.908126 6, 0xFFFF, sum = 0
4805 11:41:19.911488 7, 0xFFFF, sum = 0
4806 11:41:19.911595 8, 0x0, sum = 1
4807 11:41:19.914657 9, 0x0, sum = 2
4808 11:41:19.914742 10, 0x0, sum = 3
4809 11:41:19.917766 11, 0x0, sum = 4
4810 11:41:19.917851 best_step = 9
4811 11:41:19.917917
4812 11:41:19.917976 ==
4813 11:41:19.921440 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 11:41:19.924282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 11:41:19.927480 ==
4816 11:41:19.927564 RX Vref Scan: 0
4817 11:41:19.927630
4818 11:41:19.930814 RX Vref 0 -> 0, step: 1
4819 11:41:19.930908
4820 11:41:19.934170 RX Delay -195 -> 252, step: 8
4821 11:41:19.937800 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4822 11:41:19.944139 iDelay=205, Bit 1, Center 28 (-131 ~ 188) 320
4823 11:41:19.947390 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4824 11:41:19.950805 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4825 11:41:19.954080 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4826 11:41:19.957495 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4827 11:41:19.963993 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4828 11:41:19.967251 iDelay=205, Bit 7, Center 28 (-131 ~ 188) 320
4829 11:41:19.970906 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4830 11:41:19.973613 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4831 11:41:19.980524 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4832 11:41:19.983469 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4833 11:41:19.986902 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4834 11:41:19.990233 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4835 11:41:19.997057 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4836 11:41:19.999931 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4837 11:41:20.000041 ==
4838 11:41:20.003204 Dram Type= 6, Freq= 0, CH_1, rank 1
4839 11:41:20.006660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4840 11:41:20.006766 ==
4841 11:41:20.010632 DQS Delay:
4842 11:41:20.010732 DQS0 = 0, DQS1 = 0
4843 11:41:20.010826 DQM Delay:
4844 11:41:20.013597 DQM0 = 34, DQM1 = 29
4845 11:41:20.013717 DQ Delay:
4846 11:41:20.017146 DQ0 =40, DQ1 =28, DQ2 =24, DQ3 =32
4847 11:41:20.019900 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =28
4848 11:41:20.023070 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4849 11:41:20.026225 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4850 11:41:20.026310
4851 11:41:20.026375
4852 11:41:20.036499 [DQSOSCAuto] RK1, (LSB)MR18= 0x3656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4853 11:41:20.039771 CH1 RK1: MR19=808, MR18=3656
4854 11:41:20.043039 CH1_RK1: MR19=0x808, MR18=0x3656, DQSOSC=393, MR23=63, INC=169, DEC=113
4855 11:41:20.046251 [RxdqsGatingPostProcess] freq 600
4856 11:41:20.053293 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4857 11:41:20.055963 Pre-setting of DQS Precalculation
4858 11:41:20.059325 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4859 11:41:20.069325 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4860 11:41:20.075676 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4861 11:41:20.075765
4862 11:41:20.075831
4863 11:41:20.079157 [Calibration Summary] 1200 Mbps
4864 11:41:20.079240 CH 0, Rank 0
4865 11:41:20.082228 SW Impedance : PASS
4866 11:41:20.082310 DUTY Scan : NO K
4867 11:41:20.085574 ZQ Calibration : PASS
4868 11:41:20.089079 Jitter Meter : NO K
4869 11:41:20.089162 CBT Training : PASS
4870 11:41:20.092518 Write leveling : PASS
4871 11:41:20.095805 RX DQS gating : PASS
4872 11:41:20.095887 RX DQ/DQS(RDDQC) : PASS
4873 11:41:20.098698 TX DQ/DQS : PASS
4874 11:41:20.102223 RX DATLAT : PASS
4875 11:41:20.102305 RX DQ/DQS(Engine): PASS
4876 11:41:20.105492 TX OE : NO K
4877 11:41:20.105575 All Pass.
4878 11:41:20.105639
4879 11:41:20.108943 CH 0, Rank 1
4880 11:41:20.109026 SW Impedance : PASS
4881 11:41:20.112464 DUTY Scan : NO K
4882 11:41:20.115176 ZQ Calibration : PASS
4883 11:41:20.115260 Jitter Meter : NO K
4884 11:41:20.118556 CBT Training : PASS
4885 11:41:20.122197 Write leveling : PASS
4886 11:41:20.122282 RX DQS gating : PASS
4887 11:41:20.125473 RX DQ/DQS(RDDQC) : PASS
4888 11:41:20.128409 TX DQ/DQS : PASS
4889 11:41:20.128494 RX DATLAT : PASS
4890 11:41:20.131768 RX DQ/DQS(Engine): PASS
4891 11:41:20.134889 TX OE : NO K
4892 11:41:20.134974 All Pass.
4893 11:41:20.135040
4894 11:41:20.135102 CH 1, Rank 0
4895 11:41:20.138245 SW Impedance : PASS
4896 11:41:20.141534 DUTY Scan : NO K
4897 11:41:20.141618 ZQ Calibration : PASS
4898 11:41:20.144789 Jitter Meter : NO K
4899 11:41:20.148237 CBT Training : PASS
4900 11:41:20.148321 Write leveling : PASS
4901 11:41:20.151531 RX DQS gating : PASS
4902 11:41:20.151614 RX DQ/DQS(RDDQC) : PASS
4903 11:41:20.155071 TX DQ/DQS : PASS
4904 11:41:20.157925 RX DATLAT : PASS
4905 11:41:20.158010 RX DQ/DQS(Engine): PASS
4906 11:41:20.161445 TX OE : NO K
4907 11:41:20.161530 All Pass.
4908 11:41:20.161597
4909 11:41:20.165094 CH 1, Rank 1
4910 11:41:20.165178 SW Impedance : PASS
4911 11:41:20.168227 DUTY Scan : NO K
4912 11:41:20.171317 ZQ Calibration : PASS
4913 11:41:20.171401 Jitter Meter : NO K
4914 11:41:20.174592 CBT Training : PASS
4915 11:41:20.177877 Write leveling : PASS
4916 11:41:20.177961 RX DQS gating : PASS
4917 11:41:20.181382 RX DQ/DQS(RDDQC) : PASS
4918 11:41:20.184195 TX DQ/DQS : PASS
4919 11:41:20.184280 RX DATLAT : PASS
4920 11:41:20.187628 RX DQ/DQS(Engine): PASS
4921 11:41:20.191189 TX OE : NO K
4922 11:41:20.191303 All Pass.
4923 11:41:20.191399
4924 11:41:20.194280 DramC Write-DBI off
4925 11:41:20.194364 PER_BANK_REFRESH: Hybrid Mode
4926 11:41:20.197432 TX_TRACKING: ON
4927 11:41:20.207128 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4928 11:41:20.210458 [FAST_K] Save calibration result to emmc
4929 11:41:20.214117 dramc_set_vcore_voltage set vcore to 662500
4930 11:41:20.214246 Read voltage for 933, 3
4931 11:41:20.217493 Vio18 = 0
4932 11:41:20.217577 Vcore = 662500
4933 11:41:20.217644 Vdram = 0
4934 11:41:20.220856 Vddq = 0
4935 11:41:20.220940 Vmddr = 0
4936 11:41:20.226977 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4937 11:41:20.230445 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4938 11:41:20.234151 MEM_TYPE=3, freq_sel=17
4939 11:41:20.236921 sv_algorithm_assistance_LP4_1600
4940 11:41:20.240653 ============ PULL DRAM RESETB DOWN ============
4941 11:41:20.243598 ========== PULL DRAM RESETB DOWN end =========
4942 11:41:20.250084 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4943 11:41:20.253813 ===================================
4944 11:41:20.253896 LPDDR4 DRAM CONFIGURATION
4945 11:41:20.257074 ===================================
4946 11:41:20.260223 EX_ROW_EN[0] = 0x0
4947 11:41:20.263656 EX_ROW_EN[1] = 0x0
4948 11:41:20.263741 LP4Y_EN = 0x0
4949 11:41:20.267042 WORK_FSP = 0x0
4950 11:41:20.267124 WL = 0x3
4951 11:41:20.270374 RL = 0x3
4952 11:41:20.270457 BL = 0x2
4953 11:41:20.273250 RPST = 0x0
4954 11:41:20.273333 RD_PRE = 0x0
4955 11:41:20.276757 WR_PRE = 0x1
4956 11:41:20.276840 WR_PST = 0x0
4957 11:41:20.280108 DBI_WR = 0x0
4958 11:41:20.280191 DBI_RD = 0x0
4959 11:41:20.283214 OTF = 0x1
4960 11:41:20.286570 ===================================
4961 11:41:20.290052 ===================================
4962 11:41:20.290156 ANA top config
4963 11:41:20.293503 ===================================
4964 11:41:20.296463 DLL_ASYNC_EN = 0
4965 11:41:20.299960 ALL_SLAVE_EN = 1
4966 11:41:20.303513 NEW_RANK_MODE = 1
4967 11:41:20.303620 DLL_IDLE_MODE = 1
4968 11:41:20.306092 LP45_APHY_COMB_EN = 1
4969 11:41:20.310059 TX_ODT_DIS = 1
4970 11:41:20.313225 NEW_8X_MODE = 1
4971 11:41:20.316329 ===================================
4972 11:41:20.320015 ===================================
4973 11:41:20.322511 data_rate = 1866
4974 11:41:20.322619 CKR = 1
4975 11:41:20.325951 DQ_P2S_RATIO = 8
4976 11:41:20.329332 ===================================
4977 11:41:20.333044 CA_P2S_RATIO = 8
4978 11:41:20.335754 DQ_CA_OPEN = 0
4979 11:41:20.339070 DQ_SEMI_OPEN = 0
4980 11:41:20.342653 CA_SEMI_OPEN = 0
4981 11:41:20.342760 CA_FULL_RATE = 0
4982 11:41:20.345821 DQ_CKDIV4_EN = 1
4983 11:41:20.349017 CA_CKDIV4_EN = 1
4984 11:41:20.352642 CA_PREDIV_EN = 0
4985 11:41:20.356166 PH8_DLY = 0
4986 11:41:20.359109 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4987 11:41:20.359188 DQ_AAMCK_DIV = 4
4988 11:41:20.362497 CA_AAMCK_DIV = 4
4989 11:41:20.365708 CA_ADMCK_DIV = 4
4990 11:41:20.368573 DQ_TRACK_CA_EN = 0
4991 11:41:20.372721 CA_PICK = 933
4992 11:41:20.375270 CA_MCKIO = 933
4993 11:41:20.378821 MCKIO_SEMI = 0
4994 11:41:20.382212 PLL_FREQ = 3732
4995 11:41:20.382300 DQ_UI_PI_RATIO = 32
4996 11:41:20.385465 CA_UI_PI_RATIO = 0
4997 11:41:20.388612 ===================================
4998 11:41:20.392099 ===================================
4999 11:41:20.395063 memory_type:LPDDR4
5000 11:41:20.398461 GP_NUM : 10
5001 11:41:20.398548 SRAM_EN : 1
5002 11:41:20.402128 MD32_EN : 0
5003 11:41:20.405115 ===================================
5004 11:41:20.408501 [ANA_INIT] >>>>>>>>>>>>>>
5005 11:41:20.408588 <<<<<< [CONFIGURE PHASE]: ANA_TX
5006 11:41:20.411926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5007 11:41:20.414917 ===================================
5008 11:41:20.418333 data_rate = 1866,PCW = 0X8f00
5009 11:41:20.421139 ===================================
5010 11:41:20.424737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5011 11:41:20.431124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5012 11:41:20.437860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5013 11:41:20.441229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5014 11:41:20.444706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5015 11:41:20.447548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5016 11:41:20.450819 [ANA_INIT] flow start
5017 11:41:20.453990 [ANA_INIT] PLL >>>>>>>>
5018 11:41:20.454073 [ANA_INIT] PLL <<<<<<<<
5019 11:41:20.457477 [ANA_INIT] MIDPI >>>>>>>>
5020 11:41:20.460679 [ANA_INIT] MIDPI <<<<<<<<
5021 11:41:20.460764 [ANA_INIT] DLL >>>>>>>>
5022 11:41:20.463875 [ANA_INIT] flow end
5023 11:41:20.467632 ============ LP4 DIFF to SE enter ============
5024 11:41:20.470740 ============ LP4 DIFF to SE exit ============
5025 11:41:20.473872 [ANA_INIT] <<<<<<<<<<<<<
5026 11:41:20.477635 [Flow] Enable top DCM control >>>>>
5027 11:41:20.480802 [Flow] Enable top DCM control <<<<<
5028 11:41:20.483819 Enable DLL master slave shuffle
5029 11:41:20.490362 ==============================================================
5030 11:41:20.490448 Gating Mode config
5031 11:41:20.497362 ==============================================================
5032 11:41:20.500779 Config description:
5033 11:41:20.507503 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5034 11:41:20.513763 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5035 11:41:20.520093 SELPH_MODE 0: By rank 1: By Phase
5036 11:41:20.526433 ==============================================================
5037 11:41:20.529971 GAT_TRACK_EN = 1
5038 11:41:20.530050 RX_GATING_MODE = 2
5039 11:41:20.533545 RX_GATING_TRACK_MODE = 2
5040 11:41:20.536844 SELPH_MODE = 1
5041 11:41:20.540288 PICG_EARLY_EN = 1
5042 11:41:20.543423 VALID_LAT_VALUE = 1
5043 11:41:20.550130 ==============================================================
5044 11:41:20.553055 Enter into Gating configuration >>>>
5045 11:41:20.556506 Exit from Gating configuration <<<<
5046 11:41:20.560024 Enter into DVFS_PRE_config >>>>>
5047 11:41:20.569701 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5048 11:41:20.572755 Exit from DVFS_PRE_config <<<<<
5049 11:41:20.576134 Enter into PICG configuration >>>>
5050 11:41:20.579749 Exit from PICG configuration <<<<
5051 11:41:20.583217 [RX_INPUT] configuration >>>>>
5052 11:41:20.585710 [RX_INPUT] configuration <<<<<
5053 11:41:20.589827 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5054 11:41:20.595613 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5055 11:41:20.602284 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5056 11:41:20.609074 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5057 11:41:20.615709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5058 11:41:20.618613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5059 11:41:20.625570 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5060 11:41:20.629060 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5061 11:41:20.631971 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5062 11:41:20.635493 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5063 11:41:20.641839 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5064 11:41:20.645404 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5065 11:41:20.649092 ===================================
5066 11:41:20.651849 LPDDR4 DRAM CONFIGURATION
5067 11:41:20.654963 ===================================
5068 11:41:20.655076 EX_ROW_EN[0] = 0x0
5069 11:41:20.658506 EX_ROW_EN[1] = 0x0
5070 11:41:20.658589 LP4Y_EN = 0x0
5071 11:41:20.661866 WORK_FSP = 0x0
5072 11:41:20.661950 WL = 0x3
5073 11:41:20.665142 RL = 0x3
5074 11:41:20.665226 BL = 0x2
5075 11:41:20.668081 RPST = 0x0
5076 11:41:20.668166 RD_PRE = 0x0
5077 11:41:20.671452 WR_PRE = 0x1
5078 11:41:20.675165 WR_PST = 0x0
5079 11:41:20.675249 DBI_WR = 0x0
5080 11:41:20.678247 DBI_RD = 0x0
5081 11:41:20.678331 OTF = 0x1
5082 11:41:20.681480 ===================================
5083 11:41:20.684767 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5084 11:41:20.691521 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5085 11:41:20.694571 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5086 11:41:20.698319 ===================================
5087 11:41:20.701082 LPDDR4 DRAM CONFIGURATION
5088 11:41:20.704640 ===================================
5089 11:41:20.704733 EX_ROW_EN[0] = 0x10
5090 11:41:20.707887 EX_ROW_EN[1] = 0x0
5091 11:41:20.707965 LP4Y_EN = 0x0
5092 11:41:20.710911 WORK_FSP = 0x0
5093 11:41:20.710988 WL = 0x3
5094 11:41:20.714291 RL = 0x3
5095 11:41:20.717523 BL = 0x2
5096 11:41:20.717618 RPST = 0x0
5097 11:41:20.720892 RD_PRE = 0x0
5098 11:41:20.721016 WR_PRE = 0x1
5099 11:41:20.724276 WR_PST = 0x0
5100 11:41:20.724375 DBI_WR = 0x0
5101 11:41:20.727382 DBI_RD = 0x0
5102 11:41:20.727467 OTF = 0x1
5103 11:41:20.730673 ===================================
5104 11:41:20.736900 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5105 11:41:20.741528 nWR fixed to 30
5106 11:41:20.744793 [ModeRegInit_LP4] CH0 RK0
5107 11:41:20.744894 [ModeRegInit_LP4] CH0 RK1
5108 11:41:20.748407 [ModeRegInit_LP4] CH1 RK0
5109 11:41:20.751070 [ModeRegInit_LP4] CH1 RK1
5110 11:41:20.751144 match AC timing 9
5111 11:41:20.757985 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5112 11:41:20.761427 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5113 11:41:20.764399 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5114 11:41:20.771302 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5115 11:41:20.774639 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5116 11:41:20.774738 ==
5117 11:41:20.777791 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 11:41:20.781063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 11:41:20.781162 ==
5120 11:41:20.787649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5121 11:41:20.794675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5122 11:41:20.797458 [CA 0] Center 38 (8~69) winsize 62
5123 11:41:20.801028 [CA 1] Center 38 (7~69) winsize 63
5124 11:41:20.804069 [CA 2] Center 35 (6~65) winsize 60
5125 11:41:20.807495 [CA 3] Center 35 (5~65) winsize 61
5126 11:41:20.810789 [CA 4] Center 34 (4~65) winsize 62
5127 11:41:20.814057 [CA 5] Center 34 (4~64) winsize 61
5128 11:41:20.814131
5129 11:41:20.817305 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5130 11:41:20.817382
5131 11:41:20.820708 [CATrainingPosCal] consider 1 rank data
5132 11:41:20.823988 u2DelayCellTimex100 = 270/100 ps
5133 11:41:20.827054 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5134 11:41:20.830494 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5135 11:41:20.833824 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5136 11:41:20.837266 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5137 11:41:20.843723 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5138 11:41:20.847192 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5139 11:41:20.847277
5140 11:41:20.850046 CA PerBit enable=1, Macro0, CA PI delay=34
5141 11:41:20.850129
5142 11:41:20.853416 [CBTSetCACLKResult] CA Dly = 34
5143 11:41:20.853500 CS Dly: 6 (0~37)
5144 11:41:20.853566 ==
5145 11:41:20.856952 Dram Type= 6, Freq= 0, CH_0, rank 1
5146 11:41:20.863299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:41:20.863384 ==
5148 11:41:20.866816 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5149 11:41:20.873076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5150 11:41:20.876469 [CA 0] Center 38 (8~69) winsize 62
5151 11:41:20.880031 [CA 1] Center 38 (8~69) winsize 62
5152 11:41:20.883339 [CA 2] Center 35 (5~66) winsize 62
5153 11:41:20.886206 [CA 3] Center 35 (5~66) winsize 62
5154 11:41:20.889466 [CA 4] Center 34 (4~65) winsize 62
5155 11:41:20.893140 [CA 5] Center 33 (3~64) winsize 62
5156 11:41:20.893242
5157 11:41:20.896765 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5158 11:41:20.896848
5159 11:41:20.899433 [CATrainingPosCal] consider 2 rank data
5160 11:41:20.903056 u2DelayCellTimex100 = 270/100 ps
5161 11:41:20.905968 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5162 11:41:20.912478 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5163 11:41:20.916209 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5164 11:41:20.919461 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5165 11:41:20.922714 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5166 11:41:20.926071 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5167 11:41:20.926154
5168 11:41:20.929396 CA PerBit enable=1, Macro0, CA PI delay=34
5169 11:41:20.929479
5170 11:41:20.932387 [CBTSetCACLKResult] CA Dly = 34
5171 11:41:20.935959 CS Dly: 7 (0~39)
5172 11:41:20.936041
5173 11:41:20.939230 ----->DramcWriteLeveling(PI) begin...
5174 11:41:20.939314 ==
5175 11:41:20.942974 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 11:41:20.945701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 11:41:20.945784 ==
5178 11:41:20.948960 Write leveling (Byte 0): 32 => 32
5179 11:41:20.952673 Write leveling (Byte 1): 30 => 30
5180 11:41:20.955717 DramcWriteLeveling(PI) end<-----
5181 11:41:20.955799
5182 11:41:20.955864 ==
5183 11:41:20.959169 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 11:41:20.962937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 11:41:20.963021 ==
5186 11:41:20.965537 [Gating] SW mode calibration
5187 11:41:20.971862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5188 11:41:20.978962 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5189 11:41:20.982020 0 14 0 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
5190 11:41:20.985469 0 14 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
5191 11:41:20.992099 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 11:41:20.995296 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 11:41:20.998565 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 11:41:21.004890 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 11:41:21.008168 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 11:41:21.011539 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 11:41:21.018377 0 15 0 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 0)
5198 11:41:21.021618 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
5199 11:41:21.025044 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 11:41:21.031106 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 11:41:21.034680 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 11:41:21.041429 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 11:41:21.044162 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 11:41:21.047608 0 15 28 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5205 11:41:21.051024 1 0 0 | B1->B0 | 2828 3a3a | 0 1 | (0 0) (0 0)
5206 11:41:21.057374 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5207 11:41:21.060754 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:41:21.067641 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 11:41:21.070565 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 11:41:21.073948 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 11:41:21.080173 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 11:41:21.083516 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 11:41:21.086805 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5214 11:41:21.093719 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:41:21.097331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:41:21.100447 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:41:21.106673 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:41:21.110226 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:41:21.113064 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:41:21.119782 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:41:21.123119 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:41:21.126604 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:41:21.133204 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:41:21.136453 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 11:41:21.139760 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 11:41:21.146706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 11:41:21.149630 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 11:41:21.153063 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 11:41:21.159354 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5230 11:41:21.162849 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5231 11:41:21.166151 Total UI for P1: 0, mck2ui 16
5232 11:41:21.169573 best dqsien dly found for B0: ( 1, 3, 0)
5233 11:41:21.172550 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 11:41:21.176243 Total UI for P1: 0, mck2ui 16
5235 11:41:21.178984 best dqsien dly found for B1: ( 1, 3, 4)
5236 11:41:21.182355 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5237 11:41:21.185724 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5238 11:41:21.185806
5239 11:41:21.189172 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5240 11:41:21.195795 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5241 11:41:21.195878 [Gating] SW calibration Done
5242 11:41:21.195981 ==
5243 11:41:21.199056 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 11:41:21.205519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 11:41:21.205618 ==
5246 11:41:21.205692 RX Vref Scan: 0
5247 11:41:21.205755
5248 11:41:21.208905 RX Vref 0 -> 0, step: 1
5249 11:41:21.208982
5250 11:41:21.212313 RX Delay -80 -> 252, step: 8
5251 11:41:21.215169 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5252 11:41:21.218584 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5253 11:41:21.221697 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5254 11:41:21.228801 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5255 11:41:21.231905 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5256 11:41:21.235496 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5257 11:41:21.238605 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5258 11:41:21.241933 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5259 11:41:21.245147 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5260 11:41:21.251461 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5261 11:41:21.255053 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5262 11:41:21.258513 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5263 11:41:21.261750 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5264 11:41:21.268009 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5265 11:41:21.271461 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5266 11:41:21.274968 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5267 11:41:21.275043 ==
5268 11:41:21.278014 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 11:41:21.281485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 11:41:21.281563 ==
5271 11:41:21.284864 DQS Delay:
5272 11:41:21.284980 DQS0 = 0, DQS1 = 0
5273 11:41:21.287744 DQM Delay:
5274 11:41:21.287825 DQM0 = 93, DQM1 = 82
5275 11:41:21.287891 DQ Delay:
5276 11:41:21.291121 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5277 11:41:21.294433 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5278 11:41:21.297521 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5279 11:41:21.300900 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5280 11:41:21.300983
5281 11:41:21.304450
5282 11:41:21.304531 ==
5283 11:41:21.307746 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 11:41:21.311138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:41:21.311221 ==
5286 11:41:21.311285
5287 11:41:21.311344
5288 11:41:21.314426 TX Vref Scan disable
5289 11:41:21.314534 == TX Byte 0 ==
5290 11:41:21.320661 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5291 11:41:21.324251 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5292 11:41:21.324358 == TX Byte 1 ==
5293 11:41:21.330527 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5294 11:41:21.334022 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5295 11:41:21.334133 ==
5296 11:41:21.337453 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 11:41:21.340776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 11:41:21.340886 ==
5299 11:41:21.341004
5300 11:41:21.341113
5301 11:41:21.344257 TX Vref Scan disable
5302 11:41:21.347089 == TX Byte 0 ==
5303 11:41:21.350922 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5304 11:41:21.354167 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5305 11:41:21.356849 == TX Byte 1 ==
5306 11:41:21.360294 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5307 11:41:21.363543 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5308 11:41:21.363622
5309 11:41:21.366737 [DATLAT]
5310 11:41:21.366845 Freq=933, CH0 RK0
5311 11:41:21.366914
5312 11:41:21.370489 DATLAT Default: 0xd
5313 11:41:21.370566 0, 0xFFFF, sum = 0
5314 11:41:21.373674 1, 0xFFFF, sum = 0
5315 11:41:21.373778 2, 0xFFFF, sum = 0
5316 11:41:21.376563 3, 0xFFFF, sum = 0
5317 11:41:21.376663 4, 0xFFFF, sum = 0
5318 11:41:21.380014 5, 0xFFFF, sum = 0
5319 11:41:21.380092 6, 0xFFFF, sum = 0
5320 11:41:21.383695 7, 0xFFFF, sum = 0
5321 11:41:21.386760 8, 0xFFFF, sum = 0
5322 11:41:21.386902 9, 0xFFFF, sum = 0
5323 11:41:21.390149 10, 0x0, sum = 1
5324 11:41:21.390231 11, 0x0, sum = 2
5325 11:41:21.390296 12, 0x0, sum = 3
5326 11:41:21.393570 13, 0x0, sum = 4
5327 11:41:21.393674 best_step = 11
5328 11:41:21.393768
5329 11:41:21.393857 ==
5330 11:41:21.396486 Dram Type= 6, Freq= 0, CH_0, rank 0
5331 11:41:21.403234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 11:41:21.403317 ==
5333 11:41:21.403381 RX Vref Scan: 1
5334 11:41:21.403442
5335 11:41:21.406759 RX Vref 0 -> 0, step: 1
5336 11:41:21.406862
5337 11:41:21.409596 RX Delay -69 -> 252, step: 4
5338 11:41:21.409696
5339 11:41:21.413459 Set Vref, RX VrefLevel [Byte0]: 62
5340 11:41:21.416615 [Byte1]: 53
5341 11:41:21.416717
5342 11:41:21.419550 Final RX Vref Byte 0 = 62 to rank0
5343 11:41:21.423376 Final RX Vref Byte 1 = 53 to rank0
5344 11:41:21.426113 Final RX Vref Byte 0 = 62 to rank1
5345 11:41:21.430090 Final RX Vref Byte 1 = 53 to rank1==
5346 11:41:21.432929 Dram Type= 6, Freq= 0, CH_0, rank 0
5347 11:41:21.436393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 11:41:21.439933 ==
5349 11:41:21.440043 DQS Delay:
5350 11:41:21.440136 DQS0 = 0, DQS1 = 0
5351 11:41:21.442837 DQM Delay:
5352 11:41:21.442968 DQM0 = 95, DQM1 = 82
5353 11:41:21.445983 DQ Delay:
5354 11:41:21.449205 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5355 11:41:21.452803 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5356 11:41:21.452882 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =76
5357 11:41:21.459357 DQ12 =86, DQ13 =88, DQ14 =92, DQ15 =90
5358 11:41:21.459445
5359 11:41:21.459552
5360 11:41:21.465868 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5361 11:41:21.469016 CH0 RK0: MR19=505, MR18=1211
5362 11:41:21.475932 CH0_RK0: MR19=0x505, MR18=0x1211, DQSOSC=416, MR23=63, INC=62, DEC=41
5363 11:41:21.476049
5364 11:41:21.478723 ----->DramcWriteLeveling(PI) begin...
5365 11:41:21.478823 ==
5366 11:41:21.482140 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 11:41:21.485637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 11:41:21.485719 ==
5369 11:41:21.489148 Write leveling (Byte 0): 30 => 30
5370 11:41:21.492062 Write leveling (Byte 1): 30 => 30
5371 11:41:21.495507 DramcWriteLeveling(PI) end<-----
5372 11:41:21.495589
5373 11:41:21.495652 ==
5374 11:41:21.498823 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 11:41:21.502245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 11:41:21.502353 ==
5377 11:41:21.505156 [Gating] SW mode calibration
5378 11:41:21.512229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5379 11:41:21.518427 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5380 11:41:21.521952 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5381 11:41:21.528191 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 11:41:21.531591 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 11:41:21.534919 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 11:41:21.541418 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 11:41:21.545143 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 11:41:21.548383 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 11:41:21.554514 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 1)
5388 11:41:21.558283 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5389 11:41:21.561191 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 11:41:21.567924 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 11:41:21.571180 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 11:41:21.575201 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 11:41:21.581069 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 11:41:21.584637 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 11:41:21.587634 0 15 28 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5396 11:41:21.594742 1 0 0 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
5397 11:41:21.597969 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 11:41:21.600858 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 11:41:21.607425 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 11:41:21.610885 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 11:41:21.614271 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 11:41:21.621161 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 11:41:21.623959 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5404 11:41:21.627354 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5405 11:41:21.634260 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:41:21.637480 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:41:21.640799 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:41:21.647023 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:41:21.650626 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:41:21.654194 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:41:21.660163 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:41:21.663654 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:41:21.667037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 11:41:21.673737 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 11:41:21.676625 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 11:41:21.679931 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 11:41:21.686643 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 11:41:21.689888 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 11:41:21.693272 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5420 11:41:21.699669 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5421 11:41:21.699752 Total UI for P1: 0, mck2ui 16
5422 11:41:21.706430 best dqsien dly found for B0: ( 1, 2, 28)
5423 11:41:21.710098 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 11:41:21.712849 Total UI for P1: 0, mck2ui 16
5425 11:41:21.716299 best dqsien dly found for B1: ( 1, 3, 0)
5426 11:41:21.719430 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5427 11:41:21.722682 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5428 11:41:21.722765
5429 11:41:21.725971 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5430 11:41:21.729395 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5431 11:41:21.732756 [Gating] SW calibration Done
5432 11:41:21.732838 ==
5433 11:41:21.735710 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 11:41:21.742368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 11:41:21.742471 ==
5436 11:41:21.742550 RX Vref Scan: 0
5437 11:41:21.742611
5438 11:41:21.745750 RX Vref 0 -> 0, step: 1
5439 11:41:21.745833
5440 11:41:21.749253 RX Delay -80 -> 252, step: 8
5441 11:41:21.752072 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5442 11:41:21.755418 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5443 11:41:21.758967 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5444 11:41:21.762158 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5445 11:41:21.768573 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5446 11:41:21.772184 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5447 11:41:21.775333 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5448 11:41:21.778428 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5449 11:41:21.782214 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5450 11:41:21.788714 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5451 11:41:21.792088 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5452 11:41:21.794632 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5453 11:41:21.798028 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5454 11:41:21.805035 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5455 11:41:21.807904 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5456 11:41:21.811218 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5457 11:41:21.811296 ==
5458 11:41:21.814504 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 11:41:21.818037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 11:41:21.818147 ==
5461 11:41:21.821568 DQS Delay:
5462 11:41:21.821675 DQS0 = 0, DQS1 = 0
5463 11:41:21.824561 DQM Delay:
5464 11:41:21.824662 DQM0 = 92, DQM1 = 83
5465 11:41:21.824752 DQ Delay:
5466 11:41:21.827407 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5467 11:41:21.831023 DQ4 =91, DQ5 =79, DQ6 =107, DQ7 =107
5468 11:41:21.834138 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5469 11:41:21.837622 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5470 11:41:21.837704
5471 11:41:21.837771
5472 11:41:21.841123 ==
5473 11:41:21.844043 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 11:41:21.847285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 11:41:21.847386 ==
5476 11:41:21.847468
5477 11:41:21.847559
5478 11:41:21.850785 TX Vref Scan disable
5479 11:41:21.850904 == TX Byte 0 ==
5480 11:41:21.857049 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5481 11:41:21.860333 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5482 11:41:21.860434 == TX Byte 1 ==
5483 11:41:21.867426 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5484 11:41:21.870267 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5485 11:41:21.870368 ==
5486 11:41:21.873590 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 11:41:21.876671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 11:41:21.876780 ==
5489 11:41:21.876874
5490 11:41:21.876965
5491 11:41:21.880273 TX Vref Scan disable
5492 11:41:21.883410 == TX Byte 0 ==
5493 11:41:21.886785 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5494 11:41:21.890174 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5495 11:41:21.893717 == TX Byte 1 ==
5496 11:41:21.897153 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5497 11:41:21.899633 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5498 11:41:21.902988
5499 11:41:21.903061 [DATLAT]
5500 11:41:21.903124 Freq=933, CH0 RK1
5501 11:41:21.903198
5502 11:41:21.906284 DATLAT Default: 0xb
5503 11:41:21.906387 0, 0xFFFF, sum = 0
5504 11:41:21.909649 1, 0xFFFF, sum = 0
5505 11:41:21.909750 2, 0xFFFF, sum = 0
5506 11:41:21.913089 3, 0xFFFF, sum = 0
5507 11:41:21.913174 4, 0xFFFF, sum = 0
5508 11:41:21.916576 5, 0xFFFF, sum = 0
5509 11:41:21.919674 6, 0xFFFF, sum = 0
5510 11:41:21.919757 7, 0xFFFF, sum = 0
5511 11:41:21.922940 8, 0xFFFF, sum = 0
5512 11:41:21.923040 9, 0xFFFF, sum = 0
5513 11:41:21.926325 10, 0x0, sum = 1
5514 11:41:21.926436 11, 0x0, sum = 2
5515 11:41:21.929510 12, 0x0, sum = 3
5516 11:41:21.929593 13, 0x0, sum = 4
5517 11:41:21.929659 best_step = 11
5518 11:41:21.929748
5519 11:41:21.932752 ==
5520 11:41:21.936292 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 11:41:21.939316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 11:41:21.939399 ==
5523 11:41:21.939464 RX Vref Scan: 0
5524 11:41:21.939527
5525 11:41:21.942550 RX Vref 0 -> 0, step: 1
5526 11:41:21.942631
5527 11:41:21.946041 RX Delay -77 -> 252, step: 4
5528 11:41:21.952985 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5529 11:41:21.956214 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5530 11:41:21.959044 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5531 11:41:21.962357 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5532 11:41:21.965874 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5533 11:41:21.968773 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5534 11:41:21.975349 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5535 11:41:21.978958 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5536 11:41:21.982424 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5537 11:41:21.985288 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5538 11:41:21.988461 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5539 11:41:21.995470 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5540 11:41:21.998520 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5541 11:41:22.002228 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5542 11:41:22.005295 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5543 11:41:22.008224 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5544 11:41:22.011718 ==
5545 11:41:22.015427 Dram Type= 6, Freq= 0, CH_0, rank 1
5546 11:41:22.018045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 11:41:22.018147 ==
5548 11:41:22.018240 DQS Delay:
5549 11:41:22.021445 DQS0 = 0, DQS1 = 0
5550 11:41:22.021557 DQM Delay:
5551 11:41:22.024863 DQM0 = 92, DQM1 = 84
5552 11:41:22.024966 DQ Delay:
5553 11:41:22.028300 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5554 11:41:22.031117 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =102
5555 11:41:22.034856 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =78
5556 11:41:22.037968 DQ12 =90, DQ13 =92, DQ14 =94, DQ15 =92
5557 11:41:22.038082
5558 11:41:22.038150
5559 11:41:22.044664 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5560 11:41:22.048071 CH0 RK1: MR19=505, MR18=3213
5561 11:41:22.054783 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5562 11:41:22.057728 [RxdqsGatingPostProcess] freq 933
5563 11:41:22.064607 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5564 11:41:22.067937 best DQS0 dly(2T, 0.5T) = (0, 11)
5565 11:41:22.070806 best DQS1 dly(2T, 0.5T) = (0, 11)
5566 11:41:22.074279 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5567 11:41:22.074386 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5568 11:41:22.077693 best DQS0 dly(2T, 0.5T) = (0, 10)
5569 11:41:22.081130 best DQS1 dly(2T, 0.5T) = (0, 11)
5570 11:41:22.084254 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5571 11:41:22.087526 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5572 11:41:22.090617 Pre-setting of DQS Precalculation
5573 11:41:22.097546 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5574 11:41:22.097658 ==
5575 11:41:22.101184 Dram Type= 6, Freq= 0, CH_1, rank 0
5576 11:41:22.104178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 11:41:22.104265 ==
5578 11:41:22.110547 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5579 11:41:22.116841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5580 11:41:22.120414 [CA 0] Center 37 (7~67) winsize 61
5581 11:41:22.123825 [CA 1] Center 37 (7~67) winsize 61
5582 11:41:22.127123 [CA 2] Center 34 (5~64) winsize 60
5583 11:41:22.130673 [CA 3] Center 34 (5~64) winsize 60
5584 11:41:22.133502 [CA 4] Center 34 (5~64) winsize 60
5585 11:41:22.136896 [CA 5] Center 33 (4~63) winsize 60
5586 11:41:22.136995
5587 11:41:22.140333 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5588 11:41:22.140407
5589 11:41:22.143585 [CATrainingPosCal] consider 1 rank data
5590 11:41:22.146677 u2DelayCellTimex100 = 270/100 ps
5591 11:41:22.149753 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5592 11:41:22.153158 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5593 11:41:22.156637 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5594 11:41:22.159989 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5595 11:41:22.163382 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5596 11:41:22.166790 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5597 11:41:22.166913
5598 11:41:22.173030 CA PerBit enable=1, Macro0, CA PI delay=33
5599 11:41:22.173132
5600 11:41:22.176553 [CBTSetCACLKResult] CA Dly = 33
5601 11:41:22.176652 CS Dly: 5 (0~36)
5602 11:41:22.176741 ==
5603 11:41:22.179772 Dram Type= 6, Freq= 0, CH_1, rank 1
5604 11:41:22.182880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 11:41:22.182950 ==
5606 11:41:22.189908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5607 11:41:22.196292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5608 11:41:22.199496 [CA 0] Center 37 (7~67) winsize 61
5609 11:41:22.202638 [CA 1] Center 37 (7~68) winsize 62
5610 11:41:22.206028 [CA 2] Center 34 (5~64) winsize 60
5611 11:41:22.209408 [CA 3] Center 34 (4~64) winsize 61
5612 11:41:22.213001 [CA 4] Center 35 (5~65) winsize 61
5613 11:41:22.215725 [CA 5] Center 33 (3~64) winsize 62
5614 11:41:22.215824
5615 11:41:22.218873 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5616 11:41:22.218962
5617 11:41:22.222456 [CATrainingPosCal] consider 2 rank data
5618 11:41:22.225659 u2DelayCellTimex100 = 270/100 ps
5619 11:41:22.229172 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5620 11:41:22.232580 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5621 11:41:22.235488 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5622 11:41:22.239016 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5623 11:41:22.245486 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5624 11:41:22.248775 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5625 11:41:22.248878
5626 11:41:22.252288 CA PerBit enable=1, Macro0, CA PI delay=33
5627 11:41:22.252362
5628 11:41:22.255559 [CBTSetCACLKResult] CA Dly = 33
5629 11:41:22.255629 CS Dly: 6 (0~39)
5630 11:41:22.255699
5631 11:41:22.258972 ----->DramcWriteLeveling(PI) begin...
5632 11:41:22.259075 ==
5633 11:41:22.261772 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 11:41:22.268694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 11:41:22.268804 ==
5636 11:41:22.271555 Write leveling (Byte 0): 27 => 27
5637 11:41:22.274926 Write leveling (Byte 1): 27 => 27
5638 11:41:22.278303 DramcWriteLeveling(PI) end<-----
5639 11:41:22.278386
5640 11:41:22.278451 ==
5641 11:41:22.281808 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 11:41:22.284690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 11:41:22.284774 ==
5644 11:41:22.288107 [Gating] SW mode calibration
5645 11:41:22.294952 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5646 11:41:22.301618 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5647 11:41:22.304986 0 14 0 | B1->B0 | 3131 3030 | 1 0 | (0 0) (0 0)
5648 11:41:22.308102 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 11:41:22.314572 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 11:41:22.317830 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 11:41:22.321075 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 11:41:22.327866 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 11:41:22.331103 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 11:41:22.334452 0 14 28 | B1->B0 | 2f2f 2f2f | 0 1 | (0 1) (1 0)
5655 11:41:22.340863 0 15 0 | B1->B0 | 2424 2a2a | 0 0 | (1 0) (0 0)
5656 11:41:22.344302 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 11:41:22.348018 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 11:41:22.353966 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 11:41:22.357448 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 11:41:22.360775 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 11:41:22.367551 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 11:41:22.370968 0 15 28 | B1->B0 | 3130 2f2f | 1 1 | (0 0) (0 0)
5663 11:41:22.373800 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:41:22.380623 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 11:41:22.384045 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:41:22.387214 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 11:41:22.393789 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 11:41:22.397116 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 11:41:22.399987 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 11:41:22.406814 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5671 11:41:22.410272 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5672 11:41:22.413742 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:41:22.420151 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:41:22.423696 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:41:22.426661 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:41:22.433082 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:41:22.436642 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:41:22.439553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:41:22.446217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 11:41:22.449633 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 11:41:22.453288 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:41:22.459291 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 11:41:22.462596 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 11:41:22.466031 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 11:41:22.472649 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5686 11:41:22.476095 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5687 11:41:22.479677 Total UI for P1: 0, mck2ui 16
5688 11:41:22.482494 best dqsien dly found for B1: ( 1, 2, 26)
5689 11:41:22.485919 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 11:41:22.489533 Total UI for P1: 0, mck2ui 16
5691 11:41:22.492705 best dqsien dly found for B0: ( 1, 2, 26)
5692 11:41:22.496151 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5693 11:41:22.499412 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5694 11:41:22.499497
5695 11:41:22.502301 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5696 11:41:22.509022 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5697 11:41:22.509109 [Gating] SW calibration Done
5698 11:41:22.512333 ==
5699 11:41:22.512419 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 11:41:22.519393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 11:41:22.519479 ==
5702 11:41:22.519583 RX Vref Scan: 0
5703 11:41:22.519684
5704 11:41:22.522049 RX Vref 0 -> 0, step: 1
5705 11:41:22.522151
5706 11:41:22.525359 RX Delay -80 -> 252, step: 8
5707 11:41:22.528648 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5708 11:41:22.532360 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5709 11:41:22.535354 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5710 11:41:22.542303 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5711 11:41:22.545740 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5712 11:41:22.548834 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5713 11:41:22.552011 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5714 11:41:22.555285 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5715 11:41:22.558738 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5716 11:41:22.565011 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5717 11:41:22.568323 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5718 11:41:22.571807 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5719 11:41:22.575034 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5720 11:41:22.577927 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5721 11:41:22.584888 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5722 11:41:22.588484 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5723 11:41:22.588568 ==
5724 11:41:22.591052 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 11:41:22.594570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 11:41:22.594648 ==
5727 11:41:22.597973 DQS Delay:
5728 11:41:22.598045 DQS0 = 0, DQS1 = 0
5729 11:41:22.598107 DQM Delay:
5730 11:41:22.601587 DQM0 = 95, DQM1 = 90
5731 11:41:22.601670 DQ Delay:
5732 11:41:22.604927 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5733 11:41:22.607737 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5734 11:41:22.611240 DQ8 =83, DQ9 =83, DQ10 =87, DQ11 =87
5735 11:41:22.614539 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5736 11:41:22.614611
5737 11:41:22.614673
5738 11:41:22.614736 ==
5739 11:41:22.617701 Dram Type= 6, Freq= 0, CH_1, rank 0
5740 11:41:22.624426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:41:22.624509 ==
5742 11:41:22.624574
5743 11:41:22.624632
5744 11:41:22.624689 TX Vref Scan disable
5745 11:41:22.627738 == TX Byte 0 ==
5746 11:41:22.631048 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5747 11:41:22.637941 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5748 11:41:22.638056 == TX Byte 1 ==
5749 11:41:22.641300 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5750 11:41:22.647725 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5751 11:41:22.647807 ==
5752 11:41:22.651091 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 11:41:22.654312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 11:41:22.654411 ==
5755 11:41:22.654505
5756 11:41:22.654593
5757 11:41:22.657330 TX Vref Scan disable
5758 11:41:22.660643 == TX Byte 0 ==
5759 11:41:22.663910 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5760 11:41:22.667036 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5761 11:41:22.670519 == TX Byte 1 ==
5762 11:41:22.673918 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5763 11:41:22.677471 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5764 11:41:22.677571
5765 11:41:22.677650 [DATLAT]
5766 11:41:22.680576 Freq=933, CH1 RK0
5767 11:41:22.680659
5768 11:41:22.684034 DATLAT Default: 0xd
5769 11:41:22.684115 0, 0xFFFF, sum = 0
5770 11:41:22.686951 1, 0xFFFF, sum = 0
5771 11:41:22.687034 2, 0xFFFF, sum = 0
5772 11:41:22.690713 3, 0xFFFF, sum = 0
5773 11:41:22.690795 4, 0xFFFF, sum = 0
5774 11:41:22.693601 5, 0xFFFF, sum = 0
5775 11:41:22.693684 6, 0xFFFF, sum = 0
5776 11:41:22.697096 7, 0xFFFF, sum = 0
5777 11:41:22.697179 8, 0xFFFF, sum = 0
5778 11:41:22.700554 9, 0xFFFF, sum = 0
5779 11:41:22.700637 10, 0x0, sum = 1
5780 11:41:22.703430 11, 0x0, sum = 2
5781 11:41:22.703513 12, 0x0, sum = 3
5782 11:41:22.706983 13, 0x0, sum = 4
5783 11:41:22.707066 best_step = 11
5784 11:41:22.707131
5785 11:41:22.707190 ==
5786 11:41:22.710133 Dram Type= 6, Freq= 0, CH_1, rank 0
5787 11:41:22.713812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 11:41:22.716989 ==
5789 11:41:22.717073 RX Vref Scan: 1
5790 11:41:22.717137
5791 11:41:22.719801 RX Vref 0 -> 0, step: 1
5792 11:41:22.719883
5793 11:41:22.723197 RX Delay -53 -> 252, step: 4
5794 11:41:22.723278
5795 11:41:22.726643 Set Vref, RX VrefLevel [Byte0]: 56
5796 11:41:22.729995 [Byte1]: 51
5797 11:41:22.730083
5798 11:41:22.733139 Final RX Vref Byte 0 = 56 to rank0
5799 11:41:22.736516 Final RX Vref Byte 1 = 51 to rank0
5800 11:41:22.739668 Final RX Vref Byte 0 = 56 to rank1
5801 11:41:22.743381 Final RX Vref Byte 1 = 51 to rank1==
5802 11:41:22.746721 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 11:41:22.749714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 11:41:22.749797 ==
5805 11:41:22.752997 DQS Delay:
5806 11:41:22.753078 DQS0 = 0, DQS1 = 0
5807 11:41:22.753143 DQM Delay:
5808 11:41:22.756678 DQM0 = 95, DQM1 = 88
5809 11:41:22.756760 DQ Delay:
5810 11:41:22.759610 DQ0 =100, DQ1 =88, DQ2 =86, DQ3 =92
5811 11:41:22.762944 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5812 11:41:22.766209 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =82
5813 11:41:22.769582 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5814 11:41:22.769664
5815 11:41:22.769761
5816 11:41:22.779218 [DQSOSCAuto] RK0, (LSB)MR18= 0x30c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5817 11:41:22.782526 CH1 RK0: MR19=505, MR18=30C
5818 11:41:22.786077 CH1_RK0: MR19=0x505, MR18=0x30C, DQSOSC=418, MR23=63, INC=62, DEC=41
5819 11:41:22.786176
5820 11:41:22.789324 ----->DramcWriteLeveling(PI) begin...
5821 11:41:22.792218 ==
5822 11:41:22.795681 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:41:22.799044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:41:22.799128 ==
5825 11:41:22.802320 Write leveling (Byte 0): 26 => 26
5826 11:41:22.805898 Write leveling (Byte 1): 26 => 26
5827 11:41:22.808879 DramcWriteLeveling(PI) end<-----
5828 11:41:22.808962
5829 11:41:22.809027 ==
5830 11:41:22.812318 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 11:41:22.815109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 11:41:22.815192 ==
5833 11:41:22.818452 [Gating] SW mode calibration
5834 11:41:22.825293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5835 11:41:22.831826 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5836 11:41:22.835076 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5837 11:41:22.838650 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 11:41:22.844815 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 11:41:22.848160 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 11:41:22.851474 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 11:41:22.857712 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 11:41:22.861530 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
5843 11:41:22.864593 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5844 11:41:22.871336 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 11:41:22.874159 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 11:41:22.877888 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 11:41:22.884167 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 11:41:22.887218 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 11:41:22.890938 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 11:41:22.898040 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
5851 11:41:22.900908 0 15 28 | B1->B0 | 3c3c 4141 | 0 0 | (0 0) (0 0)
5852 11:41:22.904011 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 11:41:22.910674 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 11:41:22.913660 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 11:41:22.920676 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 11:41:22.923320 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 11:41:22.926721 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 11:41:22.933705 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5859 11:41:22.936618 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5860 11:41:22.940064 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:41:22.946645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:41:22.950027 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:41:22.952948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:41:22.959688 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:41:22.963202 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:41:22.966675 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:41:22.972933 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:41:22.976536 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:41:22.979864 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:41:22.985800 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 11:41:22.989527 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 11:41:22.992646 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 11:41:22.999244 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 11:41:23.002636 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5875 11:41:23.005768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5876 11:41:23.012670 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 11:41:23.012756 Total UI for P1: 0, mck2ui 16
5878 11:41:23.015866 best dqsien dly found for B0: ( 1, 2, 26)
5879 11:41:23.019035 Total UI for P1: 0, mck2ui 16
5880 11:41:23.022558 best dqsien dly found for B1: ( 1, 2, 28)
5881 11:41:23.025883 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5882 11:41:23.032183 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5883 11:41:23.032268
5884 11:41:23.035677 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5885 11:41:23.039244 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5886 11:41:23.042117 [Gating] SW calibration Done
5887 11:41:23.042245 ==
5888 11:41:23.045680 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 11:41:23.048566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 11:41:23.048660 ==
5891 11:41:23.052266 RX Vref Scan: 0
5892 11:41:23.052366
5893 11:41:23.052458 RX Vref 0 -> 0, step: 1
5894 11:41:23.052551
5895 11:41:23.055475 RX Delay -80 -> 252, step: 8
5896 11:41:23.058459 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5897 11:41:23.065270 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5898 11:41:23.068456 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5899 11:41:23.071993 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5900 11:41:23.075222 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5901 11:41:23.078327 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5902 11:41:23.081602 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5903 11:41:23.088308 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5904 11:41:23.092073 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5905 11:41:23.094854 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5906 11:41:23.098420 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5907 11:41:23.101693 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5908 11:41:23.107922 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5909 11:41:23.111131 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5910 11:41:23.114580 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5911 11:41:23.118177 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5912 11:41:23.118262 ==
5913 11:41:23.121052 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 11:41:23.127854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 11:41:23.127941 ==
5916 11:41:23.128007 DQS Delay:
5917 11:41:23.128069 DQS0 = 0, DQS1 = 0
5918 11:41:23.130990 DQM Delay:
5919 11:41:23.131073 DQM0 = 94, DQM1 = 90
5920 11:41:23.134737 DQ Delay:
5921 11:41:23.137654 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5922 11:41:23.141160 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5923 11:41:23.144034 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5924 11:41:23.147460 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5925 11:41:23.147544
5926 11:41:23.147627
5927 11:41:23.147690 ==
5928 11:41:23.150914 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 11:41:23.154434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 11:41:23.154538 ==
5931 11:41:23.154625
5932 11:41:23.154695
5933 11:41:23.157537 TX Vref Scan disable
5934 11:41:23.157613 == TX Byte 0 ==
5935 11:41:23.163913 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5936 11:41:23.167218 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5937 11:41:23.170558 == TX Byte 1 ==
5938 11:41:23.173713 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5939 11:41:23.177244 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5940 11:41:23.177328 ==
5941 11:41:23.180465 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 11:41:23.183919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 11:41:23.186642 ==
5944 11:41:23.186747
5945 11:41:23.186861
5946 11:41:23.186961 TX Vref Scan disable
5947 11:41:23.190452 == TX Byte 0 ==
5948 11:41:23.194081 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5949 11:41:23.200032 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5950 11:41:23.200135 == TX Byte 1 ==
5951 11:41:23.203860 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5952 11:41:23.210407 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5953 11:41:23.210499
5954 11:41:23.210584 [DATLAT]
5955 11:41:23.210658 Freq=933, CH1 RK1
5956 11:41:23.210739
5957 11:41:23.213465 DATLAT Default: 0xb
5958 11:41:23.216678 0, 0xFFFF, sum = 0
5959 11:41:23.216797 1, 0xFFFF, sum = 0
5960 11:41:23.220182 2, 0xFFFF, sum = 0
5961 11:41:23.220257 3, 0xFFFF, sum = 0
5962 11:41:23.223088 4, 0xFFFF, sum = 0
5963 11:41:23.223161 5, 0xFFFF, sum = 0
5964 11:41:23.226785 6, 0xFFFF, sum = 0
5965 11:41:23.226921 7, 0xFFFF, sum = 0
5966 11:41:23.230003 8, 0xFFFF, sum = 0
5967 11:41:23.230113 9, 0xFFFF, sum = 0
5968 11:41:23.233344 10, 0x0, sum = 1
5969 11:41:23.233422 11, 0x0, sum = 2
5970 11:41:23.236230 12, 0x0, sum = 3
5971 11:41:23.236304 13, 0x0, sum = 4
5972 11:41:23.239873 best_step = 11
5973 11:41:23.239973
5974 11:41:23.240063 ==
5975 11:41:23.243039 Dram Type= 6, Freq= 0, CH_1, rank 1
5976 11:41:23.246508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5977 11:41:23.246593 ==
5978 11:41:23.246659 RX Vref Scan: 0
5979 11:41:23.249919
5980 11:41:23.250002 RX Vref 0 -> 0, step: 1
5981 11:41:23.250068
5982 11:41:23.253140 RX Delay -61 -> 252, step: 4
5983 11:41:23.259615 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5984 11:41:23.263062 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5985 11:41:23.265943 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5986 11:41:23.269345 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5987 11:41:23.272580 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5988 11:41:23.279245 iDelay=203, Bit 5, Center 104 (11 ~ 198) 188
5989 11:41:23.282537 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5990 11:41:23.286120 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5991 11:41:23.289502 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5992 11:41:23.292437 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5993 11:41:23.298797 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5994 11:41:23.302462 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5995 11:41:23.305577 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5996 11:41:23.308685 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5997 11:41:23.311957 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5998 11:41:23.319146 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5999 11:41:23.319234 ==
6000 11:41:23.322132 Dram Type= 6, Freq= 0, CH_1, rank 1
6001 11:41:23.325601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6002 11:41:23.325708 ==
6003 11:41:23.325801 DQS Delay:
6004 11:41:23.328488 DQS0 = 0, DQS1 = 0
6005 11:41:23.328562 DQM Delay:
6006 11:41:23.332038 DQM0 = 93, DQM1 = 89
6007 11:41:23.332123 DQ Delay:
6008 11:41:23.335524 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =90
6009 11:41:23.339152 DQ4 =90, DQ5 =104, DQ6 =104, DQ7 =90
6010 11:41:23.342175 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =82
6011 11:41:23.345285 DQ12 =100, DQ13 =94, DQ14 =96, DQ15 =94
6012 11:41:23.345384
6013 11:41:23.345481
6014 11:41:23.354803 [DQSOSCAuto] RK1, (LSB)MR18= 0xe22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
6015 11:41:23.354931 CH1 RK1: MR19=505, MR18=E22
6016 11:41:23.361784 CH1_RK1: MR19=0x505, MR18=0xE22, DQSOSC=411, MR23=63, INC=64, DEC=42
6017 11:41:23.365037 [RxdqsGatingPostProcess] freq 933
6018 11:41:23.371361 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6019 11:41:23.374779 best DQS0 dly(2T, 0.5T) = (0, 10)
6020 11:41:23.378371 best DQS1 dly(2T, 0.5T) = (0, 10)
6021 11:41:23.381258 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6022 11:41:23.384447 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6023 11:41:23.387567 best DQS0 dly(2T, 0.5T) = (0, 10)
6024 11:41:23.387671 best DQS1 dly(2T, 0.5T) = (0, 10)
6025 11:41:23.391267 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6026 11:41:23.394494 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6027 11:41:23.397610 Pre-setting of DQS Precalculation
6028 11:41:23.404327 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6029 11:41:23.410782 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6030 11:41:23.417755 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6031 11:41:23.417861
6032 11:41:23.417955
6033 11:41:23.421195 [Calibration Summary] 1866 Mbps
6034 11:41:23.424506 CH 0, Rank 0
6035 11:41:23.424608 SW Impedance : PASS
6036 11:41:23.427407 DUTY Scan : NO K
6037 11:41:23.427484 ZQ Calibration : PASS
6038 11:41:23.430763 Jitter Meter : NO K
6039 11:41:23.434306 CBT Training : PASS
6040 11:41:23.434407 Write leveling : PASS
6041 11:41:23.437805 RX DQS gating : PASS
6042 11:41:23.440548 RX DQ/DQS(RDDQC) : PASS
6043 11:41:23.440630 TX DQ/DQS : PASS
6044 11:41:23.443933 RX DATLAT : PASS
6045 11:41:23.447273 RX DQ/DQS(Engine): PASS
6046 11:41:23.447356 TX OE : NO K
6047 11:41:23.450687 All Pass.
6048 11:41:23.450783
6049 11:41:23.450870 CH 0, Rank 1
6050 11:41:23.454159 SW Impedance : PASS
6051 11:41:23.454266 DUTY Scan : NO K
6052 11:41:23.457109 ZQ Calibration : PASS
6053 11:41:23.460587 Jitter Meter : NO K
6054 11:41:23.460670 CBT Training : PASS
6055 11:41:23.463466 Write leveling : PASS
6056 11:41:23.466794 RX DQS gating : PASS
6057 11:41:23.466914 RX DQ/DQS(RDDQC) : PASS
6058 11:41:23.470068 TX DQ/DQS : PASS
6059 11:41:23.473511 RX DATLAT : PASS
6060 11:41:23.473610 RX DQ/DQS(Engine): PASS
6061 11:41:23.477252 TX OE : NO K
6062 11:41:23.477335 All Pass.
6063 11:41:23.477400
6064 11:41:23.480288 CH 1, Rank 0
6065 11:41:23.480370 SW Impedance : PASS
6066 11:41:23.484007 DUTY Scan : NO K
6067 11:41:23.486982 ZQ Calibration : PASS
6068 11:41:23.487065 Jitter Meter : NO K
6069 11:41:23.490225 CBT Training : PASS
6070 11:41:23.493315 Write leveling : PASS
6071 11:41:23.493414 RX DQS gating : PASS
6072 11:41:23.496680 RX DQ/DQS(RDDQC) : PASS
6073 11:41:23.500304 TX DQ/DQS : PASS
6074 11:41:23.500387 RX DATLAT : PASS
6075 11:41:23.503007 RX DQ/DQS(Engine): PASS
6076 11:41:23.503090 TX OE : NO K
6077 11:41:23.506420 All Pass.
6078 11:41:23.506502
6079 11:41:23.506606 CH 1, Rank 1
6080 11:41:23.509794 SW Impedance : PASS
6081 11:41:23.512930 DUTY Scan : NO K
6082 11:41:23.513013 ZQ Calibration : PASS
6083 11:41:23.516326 Jitter Meter : NO K
6084 11:41:23.516409 CBT Training : PASS
6085 11:41:23.519534 Write leveling : PASS
6086 11:41:23.522725 RX DQS gating : PASS
6087 11:41:23.522871 RX DQ/DQS(RDDQC) : PASS
6088 11:41:23.526058 TX DQ/DQS : PASS
6089 11:41:23.529331 RX DATLAT : PASS
6090 11:41:23.529429 RX DQ/DQS(Engine): PASS
6091 11:41:23.532626 TX OE : NO K
6092 11:41:23.532712 All Pass.
6093 11:41:23.532778
6094 11:41:23.536303 DramC Write-DBI off
6095 11:41:23.539124 PER_BANK_REFRESH: Hybrid Mode
6096 11:41:23.539207 TX_TRACKING: ON
6097 11:41:23.549540 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6098 11:41:23.552399 [FAST_K] Save calibration result to emmc
6099 11:41:23.555772 dramc_set_vcore_voltage set vcore to 650000
6100 11:41:23.559204 Read voltage for 400, 6
6101 11:41:23.559288 Vio18 = 0
6102 11:41:23.562099 Vcore = 650000
6103 11:41:23.562183 Vdram = 0
6104 11:41:23.562248 Vddq = 0
6105 11:41:23.562308 Vmddr = 0
6106 11:41:23.569086 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6107 11:41:23.575233 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6108 11:41:23.575320 MEM_TYPE=3, freq_sel=20
6109 11:41:23.578797 sv_algorithm_assistance_LP4_800
6110 11:41:23.582307 ============ PULL DRAM RESETB DOWN ============
6111 11:41:23.588579 ========== PULL DRAM RESETB DOWN end =========
6112 11:41:23.591829 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6113 11:41:23.595173 ===================================
6114 11:41:23.598339 LPDDR4 DRAM CONFIGURATION
6115 11:41:23.602088 ===================================
6116 11:41:23.602167 EX_ROW_EN[0] = 0x0
6117 11:41:23.604915 EX_ROW_EN[1] = 0x0
6118 11:41:23.604992 LP4Y_EN = 0x0
6119 11:41:23.608258 WORK_FSP = 0x0
6120 11:41:23.611989 WL = 0x2
6121 11:41:23.612064 RL = 0x2
6122 11:41:23.614900 BL = 0x2
6123 11:41:23.614969 RPST = 0x0
6124 11:41:23.618123 RD_PRE = 0x0
6125 11:41:23.618197 WR_PRE = 0x1
6126 11:41:23.621527 WR_PST = 0x0
6127 11:41:23.621598 DBI_WR = 0x0
6128 11:41:23.624844 DBI_RD = 0x0
6129 11:41:23.624922 OTF = 0x1
6130 11:41:23.628383 ===================================
6131 11:41:23.631688 ===================================
6132 11:41:23.635033 ANA top config
6133 11:41:23.637997 ===================================
6134 11:41:23.638075 DLL_ASYNC_EN = 0
6135 11:41:23.641330 ALL_SLAVE_EN = 1
6136 11:41:23.644566 NEW_RANK_MODE = 1
6137 11:41:23.647959 DLL_IDLE_MODE = 1
6138 11:41:23.651331 LP45_APHY_COMB_EN = 1
6139 11:41:23.651430 TX_ODT_DIS = 1
6140 11:41:23.654663 NEW_8X_MODE = 1
6141 11:41:23.658091 ===================================
6142 11:41:23.661532 ===================================
6143 11:41:23.664556 data_rate = 800
6144 11:41:23.668064 CKR = 1
6145 11:41:23.670971 DQ_P2S_RATIO = 4
6146 11:41:23.674544 ===================================
6147 11:41:23.677739 CA_P2S_RATIO = 4
6148 11:41:23.677822 DQ_CA_OPEN = 0
6149 11:41:23.680891 DQ_SEMI_OPEN = 1
6150 11:41:23.684165 CA_SEMI_OPEN = 1
6151 11:41:23.687970 CA_FULL_RATE = 0
6152 11:41:23.690567 DQ_CKDIV4_EN = 0
6153 11:41:23.694327 CA_CKDIV4_EN = 1
6154 11:41:23.694410 CA_PREDIV_EN = 0
6155 11:41:23.697556 PH8_DLY = 0
6156 11:41:23.700644 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6157 11:41:23.703875 DQ_AAMCK_DIV = 0
6158 11:41:23.707014 CA_AAMCK_DIV = 0
6159 11:41:23.710698 CA_ADMCK_DIV = 4
6160 11:41:23.710780 DQ_TRACK_CA_EN = 0
6161 11:41:23.713545 CA_PICK = 800
6162 11:41:23.717062 CA_MCKIO = 400
6163 11:41:23.720599 MCKIO_SEMI = 400
6164 11:41:23.723757 PLL_FREQ = 3016
6165 11:41:23.727492 DQ_UI_PI_RATIO = 32
6166 11:41:23.730249 CA_UI_PI_RATIO = 32
6167 11:41:23.733367 ===================================
6168 11:41:23.736655 ===================================
6169 11:41:23.736739 memory_type:LPDDR4
6170 11:41:23.740177 GP_NUM : 10
6171 11:41:23.743020 SRAM_EN : 1
6172 11:41:23.743103 MD32_EN : 0
6173 11:41:23.746693 ===================================
6174 11:41:23.749923 [ANA_INIT] >>>>>>>>>>>>>>
6175 11:41:23.753455 <<<<<< [CONFIGURE PHASE]: ANA_TX
6176 11:41:23.756147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6177 11:41:23.759500 ===================================
6178 11:41:23.762970 data_rate = 800,PCW = 0X7400
6179 11:41:23.766455 ===================================
6180 11:41:23.769918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6181 11:41:23.776266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6182 11:41:23.785895 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6183 11:41:23.789245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6184 11:41:23.792803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6185 11:41:23.799238 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6186 11:41:23.799322 [ANA_INIT] flow start
6187 11:41:23.802699 [ANA_INIT] PLL >>>>>>>>
6188 11:41:23.802781 [ANA_INIT] PLL <<<<<<<<
6189 11:41:23.806141 [ANA_INIT] MIDPI >>>>>>>>
6190 11:41:23.808971 [ANA_INIT] MIDPI <<<<<<<<
6191 11:41:23.812400 [ANA_INIT] DLL >>>>>>>>
6192 11:41:23.812482 [ANA_INIT] flow end
6193 11:41:23.816318 ============ LP4 DIFF to SE enter ============
6194 11:41:23.822252 ============ LP4 DIFF to SE exit ============
6195 11:41:23.822336 [ANA_INIT] <<<<<<<<<<<<<
6196 11:41:23.825586 [Flow] Enable top DCM control >>>>>
6197 11:41:23.828719 [Flow] Enable top DCM control <<<<<
6198 11:41:23.831938 Enable DLL master slave shuffle
6199 11:41:23.839025 ==============================================================
6200 11:41:23.842183 Gating Mode config
6201 11:41:23.845430 ==============================================================
6202 11:41:23.848966 Config description:
6203 11:41:23.858471 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6204 11:41:23.865278 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6205 11:41:23.868215 SELPH_MODE 0: By rank 1: By Phase
6206 11:41:23.874686 ==============================================================
6207 11:41:23.878264 GAT_TRACK_EN = 0
6208 11:41:23.881307 RX_GATING_MODE = 2
6209 11:41:23.884726 RX_GATING_TRACK_MODE = 2
6210 11:41:23.888389 SELPH_MODE = 1
6211 11:41:23.888473 PICG_EARLY_EN = 1
6212 11:41:23.891334 VALID_LAT_VALUE = 1
6213 11:41:23.897829 ==============================================================
6214 11:41:23.901428 Enter into Gating configuration >>>>
6215 11:41:23.904365 Exit from Gating configuration <<<<
6216 11:41:23.907863 Enter into DVFS_PRE_config >>>>>
6217 11:41:23.917818 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6218 11:41:23.921211 Exit from DVFS_PRE_config <<<<<
6219 11:41:23.924413 Enter into PICG configuration >>>>
6220 11:41:23.927907 Exit from PICG configuration <<<<
6221 11:41:23.930665 [RX_INPUT] configuration >>>>>
6222 11:41:23.934114 [RX_INPUT] configuration <<<<<
6223 11:41:23.940521 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6224 11:41:23.944136 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6225 11:41:23.950645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6226 11:41:23.957123 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6227 11:41:23.964156 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6228 11:41:23.970158 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6229 11:41:23.973587 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6230 11:41:23.977081 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6231 11:41:23.980563 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6232 11:41:23.986814 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6233 11:41:23.990117 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6234 11:41:23.993584 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 11:41:23.996524 ===================================
6236 11:41:23.999903 LPDDR4 DRAM CONFIGURATION
6237 11:41:24.003374 ===================================
6238 11:41:24.006768 EX_ROW_EN[0] = 0x0
6239 11:41:24.006878 EX_ROW_EN[1] = 0x0
6240 11:41:24.010213 LP4Y_EN = 0x0
6241 11:41:24.010297 WORK_FSP = 0x0
6242 11:41:24.013517 WL = 0x2
6243 11:41:24.013601 RL = 0x2
6244 11:41:24.016884 BL = 0x2
6245 11:41:24.016992 RPST = 0x0
6246 11:41:24.020054 RD_PRE = 0x0
6247 11:41:24.020138 WR_PRE = 0x1
6248 11:41:24.023420 WR_PST = 0x0
6249 11:41:24.023502 DBI_WR = 0x0
6250 11:41:24.026676 DBI_RD = 0x0
6251 11:41:24.026759 OTF = 0x1
6252 11:41:24.029951 ===================================
6253 11:41:24.036216 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6254 11:41:24.039402 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6255 11:41:24.042819 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6256 11:41:24.046170 ===================================
6257 11:41:24.049408 LPDDR4 DRAM CONFIGURATION
6258 11:41:24.052602 ===================================
6259 11:41:24.055828 EX_ROW_EN[0] = 0x10
6260 11:41:24.055913 EX_ROW_EN[1] = 0x0
6261 11:41:24.059093 LP4Y_EN = 0x0
6262 11:41:24.059177 WORK_FSP = 0x0
6263 11:41:24.062645 WL = 0x2
6264 11:41:24.062757 RL = 0x2
6265 11:41:24.065902 BL = 0x2
6266 11:41:24.066026 RPST = 0x0
6267 11:41:24.069165 RD_PRE = 0x0
6268 11:41:24.069249 WR_PRE = 0x1
6269 11:41:24.072511 WR_PST = 0x0
6270 11:41:24.072595 DBI_WR = 0x0
6271 11:41:24.075758 DBI_RD = 0x0
6272 11:41:24.075842 OTF = 0x1
6273 11:41:24.079137 ===================================
6274 11:41:24.085568 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6275 11:41:24.090937 nWR fixed to 30
6276 11:41:24.093962 [ModeRegInit_LP4] CH0 RK0
6277 11:41:24.094047 [ModeRegInit_LP4] CH0 RK1
6278 11:41:24.097726 [ModeRegInit_LP4] CH1 RK0
6279 11:41:24.100958 [ModeRegInit_LP4] CH1 RK1
6280 11:41:24.101042 match AC timing 19
6281 11:41:24.107302 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6282 11:41:24.109984 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6283 11:41:24.113426 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6284 11:41:24.120294 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6285 11:41:24.123536 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6286 11:41:24.123619 ==
6287 11:41:24.126564 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 11:41:24.129874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 11:41:24.129959 ==
6290 11:41:24.136547 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6291 11:41:24.143178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6292 11:41:24.146527 [CA 0] Center 36 (8~64) winsize 57
6293 11:41:24.149624 [CA 1] Center 36 (8~64) winsize 57
6294 11:41:24.153327 [CA 2] Center 36 (8~64) winsize 57
6295 11:41:24.156100 [CA 3] Center 36 (8~64) winsize 57
6296 11:41:24.159824 [CA 4] Center 36 (8~64) winsize 57
6297 11:41:24.162923 [CA 5] Center 36 (8~64) winsize 57
6298 11:41:24.163005
6299 11:41:24.166104 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6300 11:41:24.166186
6301 11:41:24.169880 [CATrainingPosCal] consider 1 rank data
6302 11:41:24.172838 u2DelayCellTimex100 = 270/100 ps
6303 11:41:24.176093 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:41:24.179257 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:41:24.182922 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:41:24.186034 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:41:24.189309 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:41:24.192794 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 11:41:24.192876
6310 11:41:24.199493 CA PerBit enable=1, Macro0, CA PI delay=36
6311 11:41:24.199576
6312 11:41:24.199641 [CBTSetCACLKResult] CA Dly = 36
6313 11:41:24.202586 CS Dly: 1 (0~32)
6314 11:41:24.202668 ==
6315 11:41:24.205776 Dram Type= 6, Freq= 0, CH_0, rank 1
6316 11:41:24.209281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 11:41:24.209364 ==
6318 11:41:24.215588 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6319 11:41:24.222502 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6320 11:41:24.225328 [CA 0] Center 36 (8~64) winsize 57
6321 11:41:24.228631 [CA 1] Center 36 (8~64) winsize 57
6322 11:41:24.231858 [CA 2] Center 36 (8~64) winsize 57
6323 11:41:24.235624 [CA 3] Center 36 (8~64) winsize 57
6324 11:41:24.238773 [CA 4] Center 36 (8~64) winsize 57
6325 11:41:24.238907 [CA 5] Center 36 (8~64) winsize 57
6326 11:41:24.241833
6327 11:41:24.245035 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6328 11:41:24.245118
6329 11:41:24.248360 [CATrainingPosCal] consider 2 rank data
6330 11:41:24.251862 u2DelayCellTimex100 = 270/100 ps
6331 11:41:24.255373 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:41:24.258589 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:41:24.261960 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 11:41:24.264902 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 11:41:24.268256 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 11:41:24.271390 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 11:41:24.271473
6338 11:41:24.275109 CA PerBit enable=1, Macro0, CA PI delay=36
6339 11:41:24.278256
6340 11:41:24.278339 [CBTSetCACLKResult] CA Dly = 36
6341 11:41:24.281350 CS Dly: 1 (0~32)
6342 11:41:24.281433
6343 11:41:24.284594 ----->DramcWriteLeveling(PI) begin...
6344 11:41:24.284678 ==
6345 11:41:24.288176 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 11:41:24.291165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 11:41:24.291251 ==
6348 11:41:24.294654 Write leveling (Byte 0): 40 => 8
6349 11:41:24.298330 Write leveling (Byte 1): 32 => 0
6350 11:41:24.301063 DramcWriteLeveling(PI) end<-----
6351 11:41:24.301162
6352 11:41:24.301251 ==
6353 11:41:24.304402 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 11:41:24.308041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 11:41:24.311299 ==
6356 11:41:24.311381 [Gating] SW mode calibration
6357 11:41:24.317908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6358 11:41:24.324583 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6359 11:41:24.327561 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6360 11:41:24.334414 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6361 11:41:24.337896 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 11:41:24.340864 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6363 11:41:24.347287 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 11:41:24.350520 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 11:41:24.353856 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 11:41:24.361119 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6367 11:41:24.363584 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6368 11:41:24.366974 Total UI for P1: 0, mck2ui 16
6369 11:41:24.370710 best dqsien dly found for B0: ( 0, 14, 24)
6370 11:41:24.373950 Total UI for P1: 0, mck2ui 16
6371 11:41:24.377161 best dqsien dly found for B1: ( 0, 14, 24)
6372 11:41:24.380406 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6373 11:41:24.383715 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6374 11:41:24.383811
6375 11:41:24.386986 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6376 11:41:24.393304 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6377 11:41:24.393385 [Gating] SW calibration Done
6378 11:41:24.393448 ==
6379 11:41:24.396600 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 11:41:24.403091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 11:41:24.403171 ==
6382 11:41:24.403235 RX Vref Scan: 0
6383 11:41:24.403294
6384 11:41:24.406348 RX Vref 0 -> 0, step: 1
6385 11:41:24.406427
6386 11:41:24.409605 RX Delay -410 -> 252, step: 16
6387 11:41:24.413178 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6388 11:41:24.416628 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6389 11:41:24.423130 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6390 11:41:24.426552 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6391 11:41:24.429527 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6392 11:41:24.433204 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6393 11:41:24.439400 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6394 11:41:24.443155 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6395 11:41:24.446155 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6396 11:41:24.449154 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6397 11:41:24.456189 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6398 11:41:24.459343 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6399 11:41:24.462773 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6400 11:41:24.469232 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6401 11:41:24.472658 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6402 11:41:24.475968 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6403 11:41:24.476049 ==
6404 11:41:24.479222 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 11:41:24.482560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 11:41:24.485579 ==
6407 11:41:24.485659 DQS Delay:
6408 11:41:24.485722 DQS0 = 59, DQS1 = 59
6409 11:41:24.489124 DQM Delay:
6410 11:41:24.489204 DQM0 = 17, DQM1 = 10
6411 11:41:24.492313 DQ Delay:
6412 11:41:24.495497 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6413 11:41:24.495577 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6414 11:41:24.498670 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6415 11:41:24.502285 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6416 11:41:24.502365
6417 11:41:24.505119
6418 11:41:24.505199 ==
6419 11:41:24.508925 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 11:41:24.512053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:41:24.512136 ==
6422 11:41:24.512201
6423 11:41:24.512260
6424 11:41:24.515137 TX Vref Scan disable
6425 11:41:24.515218 == TX Byte 0 ==
6426 11:41:24.518496 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 11:41:24.525654 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 11:41:24.525734 == TX Byte 1 ==
6429 11:41:24.528786 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6430 11:41:24.535198 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6431 11:41:24.535278 ==
6432 11:41:24.538109 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 11:41:24.541604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 11:41:24.541684 ==
6435 11:41:24.541747
6436 11:41:24.541805
6437 11:41:24.545055 TX Vref Scan disable
6438 11:41:24.545134 == TX Byte 0 ==
6439 11:41:24.551718 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6440 11:41:24.554528 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6441 11:41:24.554609 == TX Byte 1 ==
6442 11:41:24.561839 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6443 11:41:24.564680 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6444 11:41:24.564761
6445 11:41:24.564825 [DATLAT]
6446 11:41:24.568028 Freq=400, CH0 RK0
6447 11:41:24.568110
6448 11:41:24.568174 DATLAT Default: 0xf
6449 11:41:24.571015 0, 0xFFFF, sum = 0
6450 11:41:24.571099 1, 0xFFFF, sum = 0
6451 11:41:24.574370 2, 0xFFFF, sum = 0
6452 11:41:24.574453 3, 0xFFFF, sum = 0
6453 11:41:24.577748 4, 0xFFFF, sum = 0
6454 11:41:24.577873 5, 0xFFFF, sum = 0
6455 11:41:24.581283 6, 0xFFFF, sum = 0
6456 11:41:24.584199 7, 0xFFFF, sum = 0
6457 11:41:24.584286 8, 0xFFFF, sum = 0
6458 11:41:24.587426 9, 0xFFFF, sum = 0
6459 11:41:24.587513 10, 0xFFFF, sum = 0
6460 11:41:24.591218 11, 0xFFFF, sum = 0
6461 11:41:24.591305 12, 0xFFFF, sum = 0
6462 11:41:24.594345 13, 0x0, sum = 1
6463 11:41:24.594432 14, 0x0, sum = 2
6464 11:41:24.597407 15, 0x0, sum = 3
6465 11:41:24.597494 16, 0x0, sum = 4
6466 11:41:24.600632 best_step = 14
6467 11:41:24.600717
6468 11:41:24.600804 ==
6469 11:41:24.604203 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 11:41:24.607373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 11:41:24.607459 ==
6472 11:41:24.607545 RX Vref Scan: 1
6473 11:41:24.610421
6474 11:41:24.610506 RX Vref 0 -> 0, step: 1
6475 11:41:24.610591
6476 11:41:24.614082 RX Delay -359 -> 252, step: 8
6477 11:41:24.614166
6478 11:41:24.617248 Set Vref, RX VrefLevel [Byte0]: 62
6479 11:41:24.620502 [Byte1]: 53
6480 11:41:24.624586
6481 11:41:24.624673 Final RX Vref Byte 0 = 62 to rank0
6482 11:41:24.628049 Final RX Vref Byte 1 = 53 to rank0
6483 11:41:24.631462 Final RX Vref Byte 0 = 62 to rank1
6484 11:41:24.635174 Final RX Vref Byte 1 = 53 to rank1==
6485 11:41:24.637769 Dram Type= 6, Freq= 0, CH_0, rank 0
6486 11:41:24.644224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 11:41:24.644308 ==
6488 11:41:24.644374 DQS Delay:
6489 11:41:24.647566 DQS0 = 60, DQS1 = 68
6490 11:41:24.647675 DQM Delay:
6491 11:41:24.647769 DQM0 = 14, DQM1 = 14
6492 11:41:24.651075 DQ Delay:
6493 11:41:24.654526 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6494 11:41:24.657348 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6495 11:41:24.661112 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6496 11:41:24.664292 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6497 11:41:24.664376
6498 11:41:24.664442
6499 11:41:24.670820 [DQSOSCAuto] RK0, (LSB)MR18= 0x8381, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6500 11:41:24.673996 CH0 RK0: MR19=C0C, MR18=8381
6501 11:41:24.680951 CH0_RK0: MR19=0xC0C, MR18=0x8381, DQSOSC=393, MR23=63, INC=382, DEC=254
6502 11:41:24.681034 ==
6503 11:41:24.684445 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 11:41:24.687274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 11:41:24.687357 ==
6506 11:41:24.690691 [Gating] SW mode calibration
6507 11:41:24.697234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6508 11:41:24.704004 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6509 11:41:24.707158 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6510 11:41:24.710342 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6511 11:41:24.717028 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 11:41:24.720610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6513 11:41:24.723785 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 11:41:24.730154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 11:41:24.733906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 11:41:24.736851 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6517 11:41:24.743174 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 11:41:24.746555 Total UI for P1: 0, mck2ui 16
6519 11:41:24.749884 best dqsien dly found for B0: ( 0, 14, 24)
6520 11:41:24.753448 Total UI for P1: 0, mck2ui 16
6521 11:41:24.756787 best dqsien dly found for B1: ( 0, 14, 24)
6522 11:41:24.760366 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6523 11:41:24.763014 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6524 11:41:24.763103
6525 11:41:24.766821 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6526 11:41:24.769859 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6527 11:41:24.773429 [Gating] SW calibration Done
6528 11:41:24.773514 ==
6529 11:41:24.776927 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 11:41:24.779529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 11:41:24.779614 ==
6532 11:41:24.782831 RX Vref Scan: 0
6533 11:41:24.782916
6534 11:41:24.786478 RX Vref 0 -> 0, step: 1
6535 11:41:24.786563
6536 11:41:24.786647 RX Delay -410 -> 252, step: 16
6537 11:41:24.792798 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6538 11:41:24.796258 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6539 11:41:24.799748 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6540 11:41:24.806380 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6541 11:41:24.809546 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6542 11:41:24.813044 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6543 11:41:24.816159 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6544 11:41:24.822636 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6545 11:41:24.826067 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6546 11:41:24.829416 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6547 11:41:24.832727 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6548 11:41:24.838959 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6549 11:41:24.842257 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6550 11:41:24.845676 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6551 11:41:24.849226 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6552 11:41:24.855662 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6553 11:41:24.855747 ==
6554 11:41:24.859076 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 11:41:24.862400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 11:41:24.862486 ==
6557 11:41:24.865704 DQS Delay:
6558 11:41:24.865789 DQS0 = 59, DQS1 = 59
6559 11:41:24.865874 DQM Delay:
6560 11:41:24.868948 DQM0 = 16, DQM1 = 10
6561 11:41:24.869032 DQ Delay:
6562 11:41:24.872166 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6563 11:41:24.874992 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6564 11:41:24.878778 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6565 11:41:24.882174 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6566 11:41:24.882259
6567 11:41:24.882344
6568 11:41:24.882423 ==
6569 11:41:24.885404 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 11:41:24.891596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 11:41:24.891682 ==
6572 11:41:24.891767
6573 11:41:24.891846
6574 11:41:24.891923 TX Vref Scan disable
6575 11:41:24.894685 == TX Byte 0 ==
6576 11:41:24.898128 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6577 11:41:24.901576 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6578 11:41:24.905056 == TX Byte 1 ==
6579 11:41:24.907875 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6580 11:41:24.911226 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6581 11:41:24.911311 ==
6582 11:41:24.915019 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 11:41:24.921209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 11:41:24.921294 ==
6585 11:41:24.921378
6586 11:41:24.921457
6587 11:41:24.924439 TX Vref Scan disable
6588 11:41:24.924523 == TX Byte 0 ==
6589 11:41:24.927537 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6590 11:41:24.934344 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6591 11:41:24.934429 == TX Byte 1 ==
6592 11:41:24.937605 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6593 11:41:24.940695 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6594 11:41:24.944546
6595 11:41:24.944630 [DATLAT]
6596 11:41:24.944714 Freq=400, CH0 RK1
6597 11:41:24.944814
6598 11:41:24.947574 DATLAT Default: 0xe
6599 11:41:24.947658 0, 0xFFFF, sum = 0
6600 11:41:24.950914 1, 0xFFFF, sum = 0
6601 11:41:24.951029 2, 0xFFFF, sum = 0
6602 11:41:24.954332 3, 0xFFFF, sum = 0
6603 11:41:24.957230 4, 0xFFFF, sum = 0
6604 11:41:24.957316 5, 0xFFFF, sum = 0
6605 11:41:24.961020 6, 0xFFFF, sum = 0
6606 11:41:24.961106 7, 0xFFFF, sum = 0
6607 11:41:24.964132 8, 0xFFFF, sum = 0
6608 11:41:24.964217 9, 0xFFFF, sum = 0
6609 11:41:24.967389 10, 0xFFFF, sum = 0
6610 11:41:24.967475 11, 0xFFFF, sum = 0
6611 11:41:24.970817 12, 0xFFFF, sum = 0
6612 11:41:24.970941 13, 0x0, sum = 1
6613 11:41:24.973668 14, 0x0, sum = 2
6614 11:41:24.973770 15, 0x0, sum = 3
6615 11:41:24.977174 16, 0x0, sum = 4
6616 11:41:24.977260 best_step = 14
6617 11:41:24.977345
6618 11:41:24.977424 ==
6619 11:41:24.980518 Dram Type= 6, Freq= 0, CH_0, rank 1
6620 11:41:24.983887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 11:41:24.987315 ==
6622 11:41:24.987400 RX Vref Scan: 0
6623 11:41:24.987484
6624 11:41:24.990473 RX Vref 0 -> 0, step: 1
6625 11:41:24.990559
6626 11:41:24.993657 RX Delay -359 -> 252, step: 8
6627 11:41:25.000478 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6628 11:41:25.003392 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6629 11:41:25.006723 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6630 11:41:25.010091 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6631 11:41:25.016417 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6632 11:41:25.019843 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6633 11:41:25.023372 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6634 11:41:25.026727 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6635 11:41:25.033120 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6636 11:41:25.036264 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6637 11:41:25.039516 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6638 11:41:25.042744 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6639 11:41:25.049768 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6640 11:41:25.052776 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6641 11:41:25.055985 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6642 11:41:25.062658 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6643 11:41:25.062742 ==
6644 11:41:25.066075 Dram Type= 6, Freq= 0, CH_0, rank 1
6645 11:41:25.069403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 11:41:25.069487 ==
6647 11:41:25.069553 DQS Delay:
6648 11:41:25.072698 DQS0 = 60, DQS1 = 72
6649 11:41:25.072781 DQM Delay:
6650 11:41:25.076134 DQM0 = 12, DQM1 = 18
6651 11:41:25.076217 DQ Delay:
6652 11:41:25.079096 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6653 11:41:25.082406 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6654 11:41:25.085786 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =8
6655 11:41:25.089117 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6656 11:41:25.089199
6657 11:41:25.089265
6658 11:41:25.095918 [DQSOSCAuto] RK1, (LSB)MR18= 0xc379, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6659 11:41:25.098784 CH0 RK1: MR19=C0C, MR18=C379
6660 11:41:25.105504 CH0_RK1: MR19=0xC0C, MR18=0xC379, DQSOSC=385, MR23=63, INC=398, DEC=265
6661 11:41:25.109051 [RxdqsGatingPostProcess] freq 400
6662 11:41:25.115578 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6663 11:41:25.118806 best DQS0 dly(2T, 0.5T) = (0, 10)
6664 11:41:25.122347 best DQS1 dly(2T, 0.5T) = (0, 10)
6665 11:41:25.125238 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6666 11:41:25.128610 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6667 11:41:25.128693 best DQS0 dly(2T, 0.5T) = (0, 10)
6668 11:41:25.131783 best DQS1 dly(2T, 0.5T) = (0, 10)
6669 11:41:25.135468 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6670 11:41:25.138743 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6671 11:41:25.141907 Pre-setting of DQS Precalculation
6672 11:41:25.148422 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6673 11:41:25.148533 ==
6674 11:41:25.151827 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 11:41:25.155157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 11:41:25.155244 ==
6677 11:41:25.161569 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6678 11:41:25.168537 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6679 11:41:25.171481 [CA 0] Center 36 (8~64) winsize 57
6680 11:41:25.171565 [CA 1] Center 36 (8~64) winsize 57
6681 11:41:25.174794 [CA 2] Center 36 (8~64) winsize 57
6682 11:41:25.178199 [CA 3] Center 36 (8~64) winsize 57
6683 11:41:25.181020 [CA 4] Center 36 (8~64) winsize 57
6684 11:41:25.184457 [CA 5] Center 36 (8~64) winsize 57
6685 11:41:25.184540
6686 11:41:25.187805 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6687 11:41:25.187887
6688 11:41:25.194413 [CATrainingPosCal] consider 1 rank data
6689 11:41:25.194496 u2DelayCellTimex100 = 270/100 ps
6690 11:41:25.201537 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:41:25.204772 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:41:25.207892 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:41:25.210871 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:41:25.214368 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:41:25.217644 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 11:41:25.217726
6697 11:41:25.221058 CA PerBit enable=1, Macro0, CA PI delay=36
6698 11:41:25.221140
6699 11:41:25.223965 [CBTSetCACLKResult] CA Dly = 36
6700 11:41:25.227474 CS Dly: 1 (0~32)
6701 11:41:25.227555 ==
6702 11:41:25.231040 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 11:41:25.233973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 11:41:25.234057 ==
6705 11:41:25.240694 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6706 11:41:25.247108 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6707 11:41:25.247195 [CA 0] Center 36 (8~64) winsize 57
6708 11:41:25.250309 [CA 1] Center 36 (8~64) winsize 57
6709 11:41:25.253728 [CA 2] Center 36 (8~64) winsize 57
6710 11:41:25.256776 [CA 3] Center 36 (8~64) winsize 57
6711 11:41:25.260510 [CA 4] Center 36 (8~64) winsize 57
6712 11:41:25.263966 [CA 5] Center 36 (8~64) winsize 57
6713 11:41:25.264050
6714 11:41:25.267089 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6715 11:41:25.267173
6716 11:41:25.270179 [CATrainingPosCal] consider 2 rank data
6717 11:41:25.273662 u2DelayCellTimex100 = 270/100 ps
6718 11:41:25.276841 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:41:25.283532 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:41:25.286509 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 11:41:25.289936 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 11:41:25.293382 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 11:41:25.296844 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 11:41:25.296927
6725 11:41:25.299773 CA PerBit enable=1, Macro0, CA PI delay=36
6726 11:41:25.299857
6727 11:41:25.303366 [CBTSetCACLKResult] CA Dly = 36
6728 11:41:25.306426 CS Dly: 1 (0~32)
6729 11:41:25.306510
6730 11:41:25.309925 ----->DramcWriteLeveling(PI) begin...
6731 11:41:25.310009 ==
6732 11:41:25.313624 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 11:41:25.316601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 11:41:25.316686 ==
6735 11:41:25.320012 Write leveling (Byte 0): 40 => 8
6736 11:41:25.323655 Write leveling (Byte 1): 40 => 8
6737 11:41:25.326079 DramcWriteLeveling(PI) end<-----
6738 11:41:25.326161
6739 11:41:25.326227 ==
6740 11:41:25.329735 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 11:41:25.332946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 11:41:25.333029 ==
6743 11:41:25.336395 [Gating] SW mode calibration
6744 11:41:25.343140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6745 11:41:25.349622 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6746 11:41:25.352855 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6747 11:41:25.356143 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6748 11:41:25.362813 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 11:41:25.365595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6750 11:41:25.368998 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 11:41:25.375902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 11:41:25.379171 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 11:41:25.382673 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6754 11:41:25.388875 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6755 11:41:25.388967 Total UI for P1: 0, mck2ui 16
6756 11:41:25.395647 best dqsien dly found for B0: ( 0, 14, 24)
6757 11:41:25.395735 Total UI for P1: 0, mck2ui 16
6758 11:41:25.402257 best dqsien dly found for B1: ( 0, 14, 24)
6759 11:41:25.405618 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6760 11:41:25.408879 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6761 11:41:25.408968
6762 11:41:25.411732 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6763 11:41:25.415184 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6764 11:41:25.418701 [Gating] SW calibration Done
6765 11:41:25.418788 ==
6766 11:41:25.422148 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 11:41:25.424975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 11:41:25.425061 ==
6769 11:41:25.428335 RX Vref Scan: 0
6770 11:41:25.428420
6771 11:41:25.431801 RX Vref 0 -> 0, step: 1
6772 11:41:25.431887
6773 11:41:25.431957 RX Delay -410 -> 252, step: 16
6774 11:41:25.438616 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6775 11:41:25.441787 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6776 11:41:25.445047 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6777 11:41:25.451671 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6778 11:41:25.454998 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6779 11:41:25.457742 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6780 11:41:25.461603 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6781 11:41:25.467953 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6782 11:41:25.471372 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6783 11:41:25.474585 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6784 11:41:25.477965 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6785 11:41:25.484321 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6786 11:41:25.487572 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6787 11:41:25.490848 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6788 11:41:25.494386 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6789 11:41:25.500739 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6790 11:41:25.500829 ==
6791 11:41:25.504507 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 11:41:25.507393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 11:41:25.507479 ==
6794 11:41:25.507545 DQS Delay:
6795 11:41:25.510794 DQS0 = 51, DQS1 = 59
6796 11:41:25.510893 DQM Delay:
6797 11:41:25.514126 DQM0 = 12, DQM1 = 12
6798 11:41:25.514228 DQ Delay:
6799 11:41:25.517524 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6800 11:41:25.520822 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6801 11:41:25.523709 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6802 11:41:25.527150 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6803 11:41:25.527244
6804 11:41:25.527309
6805 11:41:25.527370 ==
6806 11:41:25.530501 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 11:41:25.533705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:41:25.537132 ==
6809 11:41:25.537216
6810 11:41:25.537280
6811 11:41:25.537341 TX Vref Scan disable
6812 11:41:25.540318 == TX Byte 0 ==
6813 11:41:25.543444 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 11:41:25.546738 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 11:41:25.550233 == TX Byte 1 ==
6816 11:41:25.553624 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 11:41:25.556971 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 11:41:25.557065 ==
6819 11:41:25.560198 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 11:41:25.566630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 11:41:25.566761 ==
6822 11:41:25.566878
6823 11:41:25.566958
6824 11:41:25.567018 TX Vref Scan disable
6825 11:41:25.569756 == TX Byte 0 ==
6826 11:41:25.573517 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 11:41:25.577193 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 11:41:25.579986 == TX Byte 1 ==
6829 11:41:25.583349 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6830 11:41:25.586594 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6831 11:41:25.586679
6832 11:41:25.589452 [DATLAT]
6833 11:41:25.589565 Freq=400, CH1 RK0
6834 11:41:25.589645
6835 11:41:25.593053 DATLAT Default: 0xf
6836 11:41:25.593141 0, 0xFFFF, sum = 0
6837 11:41:25.596419 1, 0xFFFF, sum = 0
6838 11:41:25.596504 2, 0xFFFF, sum = 0
6839 11:41:25.599542 3, 0xFFFF, sum = 0
6840 11:41:25.599625 4, 0xFFFF, sum = 0
6841 11:41:25.602650 5, 0xFFFF, sum = 0
6842 11:41:25.602734 6, 0xFFFF, sum = 0
6843 11:41:25.606051 7, 0xFFFF, sum = 0
6844 11:41:25.606134 8, 0xFFFF, sum = 0
6845 11:41:25.609205 9, 0xFFFF, sum = 0
6846 11:41:25.612579 10, 0xFFFF, sum = 0
6847 11:41:25.612667 11, 0xFFFF, sum = 0
6848 11:41:25.616276 12, 0xFFFF, sum = 0
6849 11:41:25.616367 13, 0x0, sum = 1
6850 11:41:25.619354 14, 0x0, sum = 2
6851 11:41:25.619455 15, 0x0, sum = 3
6852 11:41:25.622241 16, 0x0, sum = 4
6853 11:41:25.622340 best_step = 14
6854 11:41:25.622410
6855 11:41:25.622471 ==
6856 11:41:25.625561 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 11:41:25.629066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 11:41:25.629201 ==
6859 11:41:25.632526 RX Vref Scan: 1
6860 11:41:25.632616
6861 11:41:25.636059 RX Vref 0 -> 0, step: 1
6862 11:41:25.636180
6863 11:41:25.636246 RX Delay -359 -> 252, step: 8
6864 11:41:25.639003
6865 11:41:25.639087 Set Vref, RX VrefLevel [Byte0]: 56
6866 11:41:25.642225 [Byte1]: 51
6867 11:41:25.647913
6868 11:41:25.648053 Final RX Vref Byte 0 = 56 to rank0
6869 11:41:25.651501 Final RX Vref Byte 1 = 51 to rank0
6870 11:41:25.654613 Final RX Vref Byte 0 = 56 to rank1
6871 11:41:25.658089 Final RX Vref Byte 1 = 51 to rank1==
6872 11:41:25.660864 Dram Type= 6, Freq= 0, CH_1, rank 0
6873 11:41:25.667548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 11:41:25.667641 ==
6875 11:41:25.667816 DQS Delay:
6876 11:41:25.670805 DQS0 = 56, DQS1 = 64
6877 11:41:25.670929 DQM Delay:
6878 11:41:25.671096 DQM0 = 13, DQM1 = 10
6879 11:41:25.674155 DQ Delay:
6880 11:41:25.677325 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6881 11:41:25.680713 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6882 11:41:25.680866 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6883 11:41:25.687520 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6884 11:41:25.687650
6885 11:41:25.687744
6886 11:41:25.693956 [DQSOSCAuto] RK0, (LSB)MR18= 0x586b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6887 11:41:25.697190 CH1 RK0: MR19=C0C, MR18=586B
6888 11:41:25.703742 CH1_RK0: MR19=0xC0C, MR18=0x586B, DQSOSC=396, MR23=63, INC=376, DEC=251
6889 11:41:25.703858 ==
6890 11:41:25.707084 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 11:41:25.710266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 11:41:25.710365 ==
6893 11:41:25.713648 [Gating] SW mode calibration
6894 11:41:25.720503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6895 11:41:25.726677 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6896 11:41:25.730273 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6897 11:41:25.733838 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6898 11:41:25.740284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 11:41:25.743238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6900 11:41:25.746766 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 11:41:25.753159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 11:41:25.756475 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 11:41:25.759972 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6904 11:41:25.766234 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6905 11:41:25.769624 Total UI for P1: 0, mck2ui 16
6906 11:41:25.772780 best dqsien dly found for B0: ( 0, 14, 24)
6907 11:41:25.775985 Total UI for P1: 0, mck2ui 16
6908 11:41:25.779635 best dqsien dly found for B1: ( 0, 14, 24)
6909 11:41:25.782961 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6910 11:41:25.786204 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6911 11:41:25.786289
6912 11:41:25.789586 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6913 11:41:25.792647 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6914 11:41:25.795848 [Gating] SW calibration Done
6915 11:41:25.795937 ==
6916 11:41:25.799041 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 11:41:25.802695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 11:41:25.802782 ==
6919 11:41:25.806036 RX Vref Scan: 0
6920 11:41:25.806122
6921 11:41:25.809099 RX Vref 0 -> 0, step: 1
6922 11:41:25.809185
6923 11:41:25.812569 RX Delay -410 -> 252, step: 16
6924 11:41:25.815830 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6925 11:41:25.818709 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6926 11:41:25.822347 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6927 11:41:25.828783 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6928 11:41:25.832019 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6929 11:41:25.835645 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6930 11:41:25.838666 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6931 11:41:25.845223 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6932 11:41:25.848811 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6933 11:41:25.851445 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6934 11:41:25.855011 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6935 11:41:25.861356 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6936 11:41:25.864915 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6937 11:41:25.867936 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6938 11:41:25.874843 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6939 11:41:25.877724 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6940 11:41:25.877836 ==
6941 11:41:25.881187 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 11:41:25.884689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 11:41:25.884782 ==
6944 11:41:25.887771 DQS Delay:
6945 11:41:25.887882 DQS0 = 59, DQS1 = 59
6946 11:41:25.891196 DQM Delay:
6947 11:41:25.891294 DQM0 = 19, DQM1 = 12
6948 11:41:25.891382 DQ Delay:
6949 11:41:25.894252 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6950 11:41:25.897629 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6951 11:41:25.900975 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6952 11:41:25.904300 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6953 11:41:25.904404
6954 11:41:25.904494
6955 11:41:25.904570 ==
6956 11:41:25.907301 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 11:41:25.914183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 11:41:25.914305 ==
6959 11:41:25.914375
6960 11:41:25.914435
6961 11:41:25.917604 TX Vref Scan disable
6962 11:41:25.917692 == TX Byte 0 ==
6963 11:41:25.920957 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6964 11:41:25.927202 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6965 11:41:25.927360 == TX Byte 1 ==
6966 11:41:25.930601 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6967 11:41:25.933657 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6968 11:41:25.937127 ==
6969 11:41:25.940226 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 11:41:25.944005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 11:41:25.944110 ==
6972 11:41:25.944215
6973 11:41:25.944276
6974 11:41:25.946710 TX Vref Scan disable
6975 11:41:25.946806 == TX Byte 0 ==
6976 11:41:25.950167 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6977 11:41:25.957445 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6978 11:41:25.957528 == TX Byte 1 ==
6979 11:41:25.960565 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6980 11:41:25.966613 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6981 11:41:25.966698
6982 11:41:25.966763 [DATLAT]
6983 11:41:25.966876 Freq=400, CH1 RK1
6984 11:41:25.966937
6985 11:41:25.970027 DATLAT Default: 0xe
6986 11:41:25.973579 0, 0xFFFF, sum = 0
6987 11:41:25.973657 1, 0xFFFF, sum = 0
6988 11:41:25.976486 2, 0xFFFF, sum = 0
6989 11:41:25.976569 3, 0xFFFF, sum = 0
6990 11:41:25.979784 4, 0xFFFF, sum = 0
6991 11:41:25.979869 5, 0xFFFF, sum = 0
6992 11:41:25.983112 6, 0xFFFF, sum = 0
6993 11:41:25.983192 7, 0xFFFF, sum = 0
6994 11:41:25.986489 8, 0xFFFF, sum = 0
6995 11:41:25.986567 9, 0xFFFF, sum = 0
6996 11:41:25.989539 10, 0xFFFF, sum = 0
6997 11:41:25.989623 11, 0xFFFF, sum = 0
6998 11:41:25.992952 12, 0xFFFF, sum = 0
6999 11:41:25.993063 13, 0x0, sum = 1
7000 11:41:25.996376 14, 0x0, sum = 2
7001 11:41:25.996481 15, 0x0, sum = 3
7002 11:41:25.999588 16, 0x0, sum = 4
7003 11:41:25.999679 best_step = 14
7004 11:41:25.999752
7005 11:41:25.999819 ==
7006 11:41:26.002735 Dram Type= 6, Freq= 0, CH_1, rank 1
7007 11:41:26.009617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7008 11:41:26.009766 ==
7009 11:41:26.009873 RX Vref Scan: 0
7010 11:41:26.009967
7011 11:41:26.012422 RX Vref 0 -> 0, step: 1
7012 11:41:26.012508
7013 11:41:26.016106 RX Delay -359 -> 252, step: 8
7014 11:41:26.022531 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7015 11:41:26.025429 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7016 11:41:26.029144 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7017 11:41:26.035319 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7018 11:41:26.038977 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7019 11:41:26.042384 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7020 11:41:26.045496 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7021 11:41:26.051951 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7022 11:41:26.055545 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7023 11:41:26.058586 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7024 11:41:26.062210 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7025 11:41:26.068545 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7026 11:41:26.072123 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7027 11:41:26.075153 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7028 11:41:26.078223 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7029 11:41:26.084624 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7030 11:41:26.084738 ==
7031 11:41:26.088105 Dram Type= 6, Freq= 0, CH_1, rank 1
7032 11:41:26.091315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7033 11:41:26.091416 ==
7034 11:41:26.094822 DQS Delay:
7035 11:41:26.094963 DQS0 = 60, DQS1 = 64
7036 11:41:26.095054 DQM Delay:
7037 11:41:26.097961 DQM0 = 12, DQM1 = 10
7038 11:41:26.098037 DQ Delay:
7039 11:41:26.101178 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7040 11:41:26.104680 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7041 11:41:26.108130 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7042 11:41:26.111316 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7043 11:41:26.111394
7044 11:41:26.111458
7045 11:41:26.121152 [DQSOSCAuto] RK1, (LSB)MR18= 0x7bab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7046 11:41:26.121234 CH1 RK1: MR19=C0C, MR18=7BAB
7047 11:41:26.127544 CH1_RK1: MR19=0xC0C, MR18=0x7BAB, DQSOSC=388, MR23=63, INC=392, DEC=261
7048 11:41:26.131396 [RxdqsGatingPostProcess] freq 400
7049 11:41:26.137501 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7050 11:41:26.141025 best DQS0 dly(2T, 0.5T) = (0, 10)
7051 11:41:26.144311 best DQS1 dly(2T, 0.5T) = (0, 10)
7052 11:41:26.147862 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7053 11:41:26.150624 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7054 11:41:26.154491 best DQS0 dly(2T, 0.5T) = (0, 10)
7055 11:41:26.157679 best DQS1 dly(2T, 0.5T) = (0, 10)
7056 11:41:26.157771 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7057 11:41:26.160821 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7058 11:41:26.164037 Pre-setting of DQS Precalculation
7059 11:41:26.170741 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7060 11:41:26.177372 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7061 11:41:26.183830 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7062 11:41:26.183922
7063 11:41:26.183990
7064 11:41:26.187651 [Calibration Summary] 800 Mbps
7065 11:41:26.190175 CH 0, Rank 0
7066 11:41:26.190260 SW Impedance : PASS
7067 11:41:26.193702 DUTY Scan : NO K
7068 11:41:26.197211 ZQ Calibration : PASS
7069 11:41:26.197331 Jitter Meter : NO K
7070 11:41:26.200515 CBT Training : PASS
7071 11:41:26.203712 Write leveling : PASS
7072 11:41:26.203798 RX DQS gating : PASS
7073 11:41:26.207015 RX DQ/DQS(RDDQC) : PASS
7074 11:41:26.207101 TX DQ/DQS : PASS
7075 11:41:26.210093 RX DATLAT : PASS
7076 11:41:26.213379 RX DQ/DQS(Engine): PASS
7077 11:41:26.213502 TX OE : NO K
7078 11:41:26.217076 All Pass.
7079 11:41:26.217200
7080 11:41:26.217311 CH 0, Rank 1
7081 11:41:26.219907 SW Impedance : PASS
7082 11:41:26.220043 DUTY Scan : NO K
7083 11:41:26.223076 ZQ Calibration : PASS
7084 11:41:26.226344 Jitter Meter : NO K
7085 11:41:26.226478 CBT Training : PASS
7086 11:41:26.229827 Write leveling : NO K
7087 11:41:26.233021 RX DQS gating : PASS
7088 11:41:26.233161 RX DQ/DQS(RDDQC) : PASS
7089 11:41:26.236816 TX DQ/DQS : PASS
7090 11:41:26.240149 RX DATLAT : PASS
7091 11:41:26.240272 RX DQ/DQS(Engine): PASS
7092 11:41:26.243003 TX OE : NO K
7093 11:41:26.243125 All Pass.
7094 11:41:26.243238
7095 11:41:26.246502 CH 1, Rank 0
7096 11:41:26.246624 SW Impedance : PASS
7097 11:41:26.249481 DUTY Scan : NO K
7098 11:41:26.253229 ZQ Calibration : PASS
7099 11:41:26.253391 Jitter Meter : NO K
7100 11:41:26.256283 CBT Training : PASS
7101 11:41:26.259881 Write leveling : PASS
7102 11:41:26.259957 RX DQS gating : PASS
7103 11:41:26.262901 RX DQ/DQS(RDDQC) : PASS
7104 11:41:26.266324 TX DQ/DQS : PASS
7105 11:41:26.266407 RX DATLAT : PASS
7106 11:41:26.269122 RX DQ/DQS(Engine): PASS
7107 11:41:26.272672 TX OE : NO K
7108 11:41:26.272759 All Pass.
7109 11:41:26.272825
7110 11:41:26.272885 CH 1, Rank 1
7111 11:41:26.276126 SW Impedance : PASS
7112 11:41:26.279553 DUTY Scan : NO K
7113 11:41:26.279661 ZQ Calibration : PASS
7114 11:41:26.282841 Jitter Meter : NO K
7115 11:41:26.285854 CBT Training : PASS
7116 11:41:26.285937 Write leveling : NO K
7117 11:41:26.289355 RX DQS gating : PASS
7118 11:41:26.292321 RX DQ/DQS(RDDQC) : PASS
7119 11:41:26.292404 TX DQ/DQS : PASS
7120 11:41:26.295630 RX DATLAT : PASS
7121 11:41:26.295720 RX DQ/DQS(Engine): PASS
7122 11:41:26.299244 TX OE : NO K
7123 11:41:26.299327 All Pass.
7124 11:41:26.299391
7125 11:41:26.302657 DramC Write-DBI off
7126 11:41:26.305292 PER_BANK_REFRESH: Hybrid Mode
7127 11:41:26.305381 TX_TRACKING: ON
7128 11:41:26.315617 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7129 11:41:26.318438 [FAST_K] Save calibration result to emmc
7130 11:41:26.321661 dramc_set_vcore_voltage set vcore to 725000
7131 11:41:26.325145 Read voltage for 1600, 0
7132 11:41:26.325258 Vio18 = 0
7133 11:41:26.328378 Vcore = 725000
7134 11:41:26.328463 Vdram = 0
7135 11:41:26.328548 Vddq = 0
7136 11:41:26.331711 Vmddr = 0
7137 11:41:26.335147 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7138 11:41:26.341625 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7139 11:41:26.341745 MEM_TYPE=3, freq_sel=13
7140 11:41:26.344928 sv_algorithm_assistance_LP4_3733
7141 11:41:26.351752 ============ PULL DRAM RESETB DOWN ============
7142 11:41:26.354701 ========== PULL DRAM RESETB DOWN end =========
7143 11:41:26.358073 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7144 11:41:26.361734 ===================================
7145 11:41:26.364867 LPDDR4 DRAM CONFIGURATION
7146 11:41:26.368110 ===================================
7147 11:41:26.368190 EX_ROW_EN[0] = 0x0
7148 11:41:26.371088 EX_ROW_EN[1] = 0x0
7149 11:41:26.374988 LP4Y_EN = 0x0
7150 11:41:26.375068 WORK_FSP = 0x1
7151 11:41:26.377688 WL = 0x5
7152 11:41:26.377785 RL = 0x5
7153 11:41:26.381296 BL = 0x2
7154 11:41:26.381409 RPST = 0x0
7155 11:41:26.384575 RD_PRE = 0x0
7156 11:41:26.384687 WR_PRE = 0x1
7157 11:41:26.387444 WR_PST = 0x1
7158 11:41:26.387556 DBI_WR = 0x0
7159 11:41:26.391214 DBI_RD = 0x0
7160 11:41:26.391390 OTF = 0x1
7161 11:41:26.394546 ===================================
7162 11:41:26.397487 ===================================
7163 11:41:26.401196 ANA top config
7164 11:41:26.404511 ===================================
7165 11:41:26.407528 DLL_ASYNC_EN = 0
7166 11:41:26.407640 ALL_SLAVE_EN = 0
7167 11:41:26.410782 NEW_RANK_MODE = 1
7168 11:41:26.414258 DLL_IDLE_MODE = 1
7169 11:41:26.417477 LP45_APHY_COMB_EN = 1
7170 11:41:26.417561 TX_ODT_DIS = 0
7171 11:41:26.420604 NEW_8X_MODE = 1
7172 11:41:26.423980 ===================================
7173 11:41:26.427539 ===================================
7174 11:41:26.430500 data_rate = 3200
7175 11:41:26.433752 CKR = 1
7176 11:41:26.437190 DQ_P2S_RATIO = 8
7177 11:41:26.440433 ===================================
7178 11:41:26.443757 CA_P2S_RATIO = 8
7179 11:41:26.447117 DQ_CA_OPEN = 0
7180 11:41:26.447203 DQ_SEMI_OPEN = 0
7181 11:41:26.450053 CA_SEMI_OPEN = 0
7182 11:41:26.453340 CA_FULL_RATE = 0
7183 11:41:26.456923 DQ_CKDIV4_EN = 0
7184 11:41:26.460229 CA_CKDIV4_EN = 0
7185 11:41:26.463813 CA_PREDIV_EN = 0
7186 11:41:26.463897 PH8_DLY = 12
7187 11:41:26.466928 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7188 11:41:26.470213 DQ_AAMCK_DIV = 4
7189 11:41:26.473077 CA_AAMCK_DIV = 4
7190 11:41:26.476600 CA_ADMCK_DIV = 4
7191 11:41:26.480528 DQ_TRACK_CA_EN = 0
7192 11:41:26.483051 CA_PICK = 1600
7193 11:41:26.483134 CA_MCKIO = 1600
7194 11:41:26.486782 MCKIO_SEMI = 0
7195 11:41:26.489707 PLL_FREQ = 3068
7196 11:41:26.493012 DQ_UI_PI_RATIO = 32
7197 11:41:26.496688 CA_UI_PI_RATIO = 0
7198 11:41:26.499921 ===================================
7199 11:41:26.502854 ===================================
7200 11:41:26.506531 memory_type:LPDDR4
7201 11:41:26.506644 GP_NUM : 10
7202 11:41:26.509402 SRAM_EN : 1
7203 11:41:26.509484 MD32_EN : 0
7204 11:41:26.513050 ===================================
7205 11:41:26.516335 [ANA_INIT] >>>>>>>>>>>>>>
7206 11:41:26.519640 <<<<<< [CONFIGURE PHASE]: ANA_TX
7207 11:41:26.523087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7208 11:41:26.526024 ===================================
7209 11:41:26.529590 data_rate = 3200,PCW = 0X7600
7210 11:41:26.533055 ===================================
7211 11:41:26.536247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7212 11:41:26.542748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7213 11:41:26.545780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7214 11:41:26.552577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7215 11:41:26.555882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7216 11:41:26.559198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7217 11:41:26.559281 [ANA_INIT] flow start
7218 11:41:26.562277 [ANA_INIT] PLL >>>>>>>>
7219 11:41:26.565867 [ANA_INIT] PLL <<<<<<<<
7220 11:41:26.568728 [ANA_INIT] MIDPI >>>>>>>>
7221 11:41:26.568812 [ANA_INIT] MIDPI <<<<<<<<
7222 11:41:26.572360 [ANA_INIT] DLL >>>>>>>>
7223 11:41:26.575776 [ANA_INIT] DLL <<<<<<<<
7224 11:41:26.575883 [ANA_INIT] flow end
7225 11:41:26.579062 ============ LP4 DIFF to SE enter ============
7226 11:41:26.585424 ============ LP4 DIFF to SE exit ============
7227 11:41:26.585507 [ANA_INIT] <<<<<<<<<<<<<
7228 11:41:26.588789 [Flow] Enable top DCM control >>>>>
7229 11:41:26.591720 [Flow] Enable top DCM control <<<<<
7230 11:41:26.595232 Enable DLL master slave shuffle
7231 11:41:26.601818 ==============================================================
7232 11:41:26.605267 Gating Mode config
7233 11:41:26.608543 ==============================================================
7234 11:41:26.612185 Config description:
7235 11:41:26.621393 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7236 11:41:26.627946 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7237 11:41:26.631286 SELPH_MODE 0: By rank 1: By Phase
7238 11:41:26.637748 ==============================================================
7239 11:41:26.641256 GAT_TRACK_EN = 1
7240 11:41:26.644569 RX_GATING_MODE = 2
7241 11:41:26.647790 RX_GATING_TRACK_MODE = 2
7242 11:41:26.651158 SELPH_MODE = 1
7243 11:41:26.651272 PICG_EARLY_EN = 1
7244 11:41:26.654707 VALID_LAT_VALUE = 1
7245 11:41:26.660858 ==============================================================
7246 11:41:26.664055 Enter into Gating configuration >>>>
7247 11:41:26.667406 Exit from Gating configuration <<<<
7248 11:41:26.671011 Enter into DVFS_PRE_config >>>>>
7249 11:41:26.680590 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7250 11:41:26.684065 Exit from DVFS_PRE_config <<<<<
7251 11:41:26.687587 Enter into PICG configuration >>>>
7252 11:41:26.690976 Exit from PICG configuration <<<<
7253 11:41:26.693818 [RX_INPUT] configuration >>>>>
7254 11:41:26.697370 [RX_INPUT] configuration <<<<<
7255 11:41:26.704277 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7256 11:41:26.707317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7257 11:41:26.713989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7258 11:41:26.720528 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7259 11:41:26.726773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7260 11:41:26.733885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7261 11:41:26.737180 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7262 11:41:26.740374 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7263 11:41:26.743630 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7264 11:41:26.750251 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7265 11:41:26.753535 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7266 11:41:26.756375 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 11:41:26.759677 ===================================
7268 11:41:26.762927 LPDDR4 DRAM CONFIGURATION
7269 11:41:26.766952 ===================================
7270 11:41:26.769872 EX_ROW_EN[0] = 0x0
7271 11:41:26.769953 EX_ROW_EN[1] = 0x0
7272 11:41:26.773051 LP4Y_EN = 0x0
7273 11:41:26.773132 WORK_FSP = 0x1
7274 11:41:26.775936 WL = 0x5
7275 11:41:26.776034 RL = 0x5
7276 11:41:26.779676 BL = 0x2
7277 11:41:26.779759 RPST = 0x0
7278 11:41:26.783183 RD_PRE = 0x0
7279 11:41:26.783266 WR_PRE = 0x1
7280 11:41:26.785936 WR_PST = 0x1
7281 11:41:26.786022 DBI_WR = 0x0
7282 11:41:26.789446 DBI_RD = 0x0
7283 11:41:26.789529 OTF = 0x1
7284 11:41:26.792861 ===================================
7285 11:41:26.799292 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7286 11:41:26.802777 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7287 11:41:26.805685 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7288 11:41:26.809117 ===================================
7289 11:41:26.812484 LPDDR4 DRAM CONFIGURATION
7290 11:41:26.815819 ===================================
7291 11:41:26.819182 EX_ROW_EN[0] = 0x10
7292 11:41:26.819266 EX_ROW_EN[1] = 0x0
7293 11:41:26.822399 LP4Y_EN = 0x0
7294 11:41:26.822482 WORK_FSP = 0x1
7295 11:41:26.825373 WL = 0x5
7296 11:41:26.825456 RL = 0x5
7297 11:41:26.829007 BL = 0x2
7298 11:41:26.829090 RPST = 0x0
7299 11:41:26.832424 RD_PRE = 0x0
7300 11:41:26.832507 WR_PRE = 0x1
7301 11:41:26.835366 WR_PST = 0x1
7302 11:41:26.835449 DBI_WR = 0x0
7303 11:41:26.838796 DBI_RD = 0x0
7304 11:41:26.838901 OTF = 0x1
7305 11:41:26.842257 ===================================
7306 11:41:26.848818 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7307 11:41:26.848903 ==
7308 11:41:26.851627 Dram Type= 6, Freq= 0, CH_0, rank 0
7309 11:41:26.858674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7310 11:41:26.858774 ==
7311 11:41:26.858865 [Duty_Offset_Calibration]
7312 11:41:26.861933 B0:2 B1:0 CA:3
7313 11:41:26.862016
7314 11:41:26.865066 [DutyScan_Calibration_Flow] k_type=0
7315 11:41:26.874414
7316 11:41:26.874497 ==CLK 0==
7317 11:41:26.877895 Final CLK duty delay cell = 0
7318 11:41:26.881049 [0] MAX Duty = 5031%(X100), DQS PI = 12
7319 11:41:26.884253 [0] MIN Duty = 4907%(X100), DQS PI = 6
7320 11:41:26.887218 [0] AVG Duty = 4969%(X100)
7321 11:41:26.887301
7322 11:41:26.890763 CH0 CLK Duty spec in!! Max-Min= 124%
7323 11:41:26.893860 [DutyScan_Calibration_Flow] ====Done====
7324 11:41:26.893943
7325 11:41:26.897432 [DutyScan_Calibration_Flow] k_type=1
7326 11:41:26.914253
7327 11:41:26.914336 ==DQS 0 ==
7328 11:41:26.917742 Final DQS duty delay cell = 0
7329 11:41:26.920862 [0] MAX Duty = 5125%(X100), DQS PI = 30
7330 11:41:26.924008 [0] MIN Duty = 4875%(X100), DQS PI = 48
7331 11:41:26.927342 [0] AVG Duty = 5000%(X100)
7332 11:41:26.927425
7333 11:41:26.927490 ==DQS 1 ==
7334 11:41:26.930785 Final DQS duty delay cell = 0
7335 11:41:26.934410 [0] MAX Duty = 5156%(X100), DQS PI = 32
7336 11:41:26.937536 [0] MIN Duty = 5031%(X100), DQS PI = 10
7337 11:41:26.940915 [0] AVG Duty = 5093%(X100)
7338 11:41:26.941013
7339 11:41:26.943915 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7340 11:41:26.943998
7341 11:41:26.947188 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7342 11:41:26.950701 [DutyScan_Calibration_Flow] ====Done====
7343 11:41:26.950800
7344 11:41:26.954191 [DutyScan_Calibration_Flow] k_type=3
7345 11:41:26.971886
7346 11:41:26.972026 ==DQM 0 ==
7347 11:41:26.975186 Final DQM duty delay cell = 0
7348 11:41:26.978430 [0] MAX Duty = 5156%(X100), DQS PI = 30
7349 11:41:26.981679 [0] MIN Duty = 4875%(X100), DQS PI = 0
7350 11:41:26.985209 [0] AVG Duty = 5015%(X100)
7351 11:41:26.985302
7352 11:41:26.985369 ==DQM 1 ==
7353 11:41:26.988484 Final DQM duty delay cell = 4
7354 11:41:26.991751 [4] MAX Duty = 5187%(X100), DQS PI = 60
7355 11:41:26.994952 [4] MIN Duty = 5031%(X100), DQS PI = 12
7356 11:41:26.998543 [4] AVG Duty = 5109%(X100)
7357 11:41:26.998664
7358 11:41:27.001438 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7359 11:41:27.001523
7360 11:41:27.004978 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7361 11:41:27.008121 [DutyScan_Calibration_Flow] ====Done====
7362 11:41:27.008203
7363 11:41:27.011127 [DutyScan_Calibration_Flow] k_type=2
7364 11:41:27.028662
7365 11:41:27.028753 ==DQ 0 ==
7366 11:41:27.031498 Final DQ duty delay cell = -4
7367 11:41:27.035088 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7368 11:41:27.038237 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7369 11:41:27.041222 [-4] AVG Duty = 4938%(X100)
7370 11:41:27.041361
7371 11:41:27.041485 ==DQ 1 ==
7372 11:41:27.044846 Final DQ duty delay cell = 0
7373 11:41:27.048246 [0] MAX Duty = 5156%(X100), DQS PI = 60
7374 11:41:27.051118 [0] MIN Duty = 5000%(X100), DQS PI = 16
7375 11:41:27.054656 [0] AVG Duty = 5078%(X100)
7376 11:41:27.054823
7377 11:41:27.058153 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7378 11:41:27.058306
7379 11:41:27.061499 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7380 11:41:27.064354 [DutyScan_Calibration_Flow] ====Done====
7381 11:41:27.064436 ==
7382 11:41:27.067663 Dram Type= 6, Freq= 0, CH_1, rank 0
7383 11:41:27.071371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7384 11:41:27.071732 ==
7385 11:41:27.074674 [Duty_Offset_Calibration]
7386 11:41:27.075061 B0:1 B1:-2 CA:0
7387 11:41:27.077631
7388 11:41:27.081032 [DutyScan_Calibration_Flow] k_type=0
7389 11:41:27.088780
7390 11:41:27.088949 ==CLK 0==
7391 11:41:27.091918 Final CLK duty delay cell = 0
7392 11:41:27.095300 [0] MAX Duty = 5062%(X100), DQS PI = 20
7393 11:41:27.098783 [0] MIN Duty = 4844%(X100), DQS PI = 4
7394 11:41:27.101857 [0] AVG Duty = 4953%(X100)
7395 11:41:27.101937
7396 11:41:27.105597 CH1 CLK Duty spec in!! Max-Min= 218%
7397 11:41:27.108691 [DutyScan_Calibration_Flow] ====Done====
7398 11:41:27.108771
7399 11:41:27.111509 [DutyScan_Calibration_Flow] k_type=1
7400 11:41:27.127920
7401 11:41:27.128088 ==DQS 0 ==
7402 11:41:27.130863 Final DQS duty delay cell = -4
7403 11:41:27.134256 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7404 11:41:27.137697 [-4] MIN Duty = 4844%(X100), DQS PI = 44
7405 11:41:27.140819 [-4] AVG Duty = 4906%(X100)
7406 11:41:27.141020
7407 11:41:27.141127 ==DQS 1 ==
7408 11:41:27.144170 Final DQS duty delay cell = 0
7409 11:41:27.147053 [0] MAX Duty = 5093%(X100), DQS PI = 0
7410 11:41:27.150669 [0] MIN Duty = 4844%(X100), DQS PI = 24
7411 11:41:27.154114 [0] AVG Duty = 4968%(X100)
7412 11:41:27.154195
7413 11:41:27.157010 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7414 11:41:27.157090
7415 11:41:27.160157 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7416 11:41:27.163559 [DutyScan_Calibration_Flow] ====Done====
7417 11:41:27.163673
7418 11:41:27.167060 [DutyScan_Calibration_Flow] k_type=3
7419 11:41:27.184366
7420 11:41:27.184462 ==DQM 0 ==
7421 11:41:27.187826 Final DQM duty delay cell = 0
7422 11:41:27.191243 [0] MAX Duty = 5031%(X100), DQS PI = 24
7423 11:41:27.194583 [0] MIN Duty = 4813%(X100), DQS PI = 54
7424 11:41:27.197922 [0] AVG Duty = 4922%(X100)
7425 11:41:27.198013
7426 11:41:27.198105 ==DQM 1 ==
7427 11:41:27.201290 Final DQM duty delay cell = 0
7428 11:41:27.204287 [0] MAX Duty = 5062%(X100), DQS PI = 34
7429 11:41:27.207768 [0] MIN Duty = 4875%(X100), DQS PI = 24
7430 11:41:27.211140 [0] AVG Duty = 4968%(X100)
7431 11:41:27.211293
7432 11:41:27.214127 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7433 11:41:27.214275
7434 11:41:27.217789 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7435 11:41:27.221180 [DutyScan_Calibration_Flow] ====Done====
7436 11:41:27.221412
7437 11:41:27.223874 [DutyScan_Calibration_Flow] k_type=2
7438 11:41:27.241602
7439 11:41:27.241685 ==DQ 0 ==
7440 11:41:27.244470 Final DQ duty delay cell = 0
7441 11:41:27.247998 [0] MAX Duty = 5093%(X100), DQS PI = 22
7442 11:41:27.251065 [0] MIN Duty = 4907%(X100), DQS PI = 62
7443 11:41:27.251167 [0] AVG Duty = 5000%(X100)
7444 11:41:27.254565
7445 11:41:27.254637 ==DQ 1 ==
7446 11:41:27.258068 Final DQ duty delay cell = 0
7447 11:41:27.261376 [0] MAX Duty = 5125%(X100), DQS PI = 34
7448 11:41:27.265089 [0] MIN Duty = 4969%(X100), DQS PI = 26
7449 11:41:27.265265 [0] AVG Duty = 5047%(X100)
7450 11:41:27.267812
7451 11:41:27.271207 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7452 11:41:27.271320
7453 11:41:27.274483 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7454 11:41:27.277749 [DutyScan_Calibration_Flow] ====Done====
7455 11:41:27.281103 nWR fixed to 30
7456 11:41:27.281283 [ModeRegInit_LP4] CH0 RK0
7457 11:41:27.284725 [ModeRegInit_LP4] CH0 RK1
7458 11:41:27.287958 [ModeRegInit_LP4] CH1 RK0
7459 11:41:27.290750 [ModeRegInit_LP4] CH1 RK1
7460 11:41:27.290958 match AC timing 5
7461 11:41:27.297705 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7462 11:41:27.300552 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7463 11:41:27.304395 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7464 11:41:27.310528 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7465 11:41:27.314416 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7466 11:41:27.314935 [MiockJmeterHQA]
7467 11:41:27.315283
7468 11:41:27.317296 [DramcMiockJmeter] u1RxGatingPI = 0
7469 11:41:27.321019 0 : 4257, 4032
7470 11:41:27.321463 4 : 4255, 4029
7471 11:41:27.323869 8 : 4258, 4029
7472 11:41:27.324340 12 : 4368, 4140
7473 11:41:27.327393 16 : 4257, 4029
7474 11:41:27.327866 20 : 4365, 4140
7475 11:41:27.328210 24 : 4253, 4026
7476 11:41:27.330910 28 : 4250, 4027
7477 11:41:27.331358 32 : 4365, 4140
7478 11:41:27.333779 36 : 4255, 4029
7479 11:41:27.334237 40 : 4255, 4029
7480 11:41:27.337629 44 : 4254, 4029
7481 11:41:27.338062 48 : 4258, 4032
7482 11:41:27.340480 52 : 4252, 4030
7483 11:41:27.340974 56 : 4252, 4029
7484 11:41:27.341353 60 : 4366, 4142
7485 11:41:27.344033 64 : 4255, 4030
7486 11:41:27.344522 68 : 4255, 4029
7487 11:41:27.347414 72 : 4360, 4138
7488 11:41:27.347863 76 : 4252, 4029
7489 11:41:27.350492 80 : 4253, 4029
7490 11:41:27.351092 84 : 4249, 4027
7491 11:41:27.354201 88 : 4368, 4142
7492 11:41:27.354888 92 : 4250, 4027
7493 11:41:27.355291 96 : 4253, 4029
7494 11:41:27.357178 100 : 4253, 4029
7495 11:41:27.357765 104 : 4361, 3845
7496 11:41:27.360100 108 : 4253, 1
7497 11:41:27.360570 112 : 4250, 0
7498 11:41:27.363776 116 : 4255, 0
7499 11:41:27.364181 120 : 4253, 0
7500 11:41:27.364519 124 : 4252, 0
7501 11:41:27.367004 128 : 4368, 0
7502 11:41:27.367646 132 : 4255, 0
7503 11:41:27.370438 136 : 4252, 0
7504 11:41:27.370869 140 : 4253, 0
7505 11:41:27.371204 144 : 4252, 0
7506 11:41:27.373534 148 : 4252, 0
7507 11:41:27.373936 152 : 4253, 0
7508 11:41:27.376549 156 : 4257, 0
7509 11:41:27.376951 160 : 4253, 0
7510 11:41:27.377273 164 : 4363, 0
7511 11:41:27.379912 168 : 4363, 0
7512 11:41:27.380315 172 : 4252, 0
7513 11:41:27.383189 176 : 4363, 0
7514 11:41:27.383592 180 : 4255, 0
7515 11:41:27.383910 184 : 4363, 0
7516 11:41:27.386324 188 : 4363, 0
7517 11:41:27.386956 192 : 4368, 0
7518 11:41:27.387474 196 : 4250, 0
7519 11:41:27.390159 200 : 4363, 0
7520 11:41:27.390695 204 : 4363, 0
7521 11:41:27.392969 208 : 4248, 0
7522 11:41:27.393461 212 : 4363, 0
7523 11:41:27.393939 216 : 4252, 0
7524 11:41:27.396268 220 : 4363, 0
7525 11:41:27.396659 224 : 4253, 0
7526 11:41:27.399693 228 : 4252, 0
7527 11:41:27.400085 232 : 4257, 1
7528 11:41:27.400396 236 : 4363, 969
7529 11:41:27.403265 240 : 4253, 4029
7530 11:41:27.403657 244 : 4365, 4139
7531 11:41:27.405881 248 : 4363, 4140
7532 11:41:27.406272 252 : 4252, 4030
7533 11:41:27.409737 256 : 4253, 4029
7534 11:41:27.410125 260 : 4252, 4030
7535 11:41:27.412494 264 : 4253, 4029
7536 11:41:27.412883 268 : 4253, 4029
7537 11:41:27.416227 272 : 4368, 4142
7538 11:41:27.416620 276 : 4255, 4029
7539 11:41:27.419675 280 : 4252, 4030
7540 11:41:27.420294 284 : 4252, 4029
7541 11:41:27.422589 288 : 4257, 4032
7542 11:41:27.423253 292 : 4365, 4139
7543 11:41:27.425921 296 : 4252, 4029
7544 11:41:27.426408 300 : 4363, 4140
7545 11:41:27.429389 304 : 4253, 4029
7546 11:41:27.429780 308 : 4255, 4029
7547 11:41:27.430091 312 : 4255, 4029
7548 11:41:27.432395 316 : 4253, 4029
7549 11:41:27.432788 320 : 4365, 4140
7550 11:41:27.435963 324 : 4361, 4137
7551 11:41:27.436357 328 : 4255, 4030
7552 11:41:27.438706 332 : 4252, 4030
7553 11:41:27.439142 336 : 4363, 4140
7554 11:41:27.442614 340 : 4255, 4029
7555 11:41:27.443166 344 : 4255, 4029
7556 11:41:27.445836 348 : 4365, 4139
7557 11:41:27.446231 352 : 4252, 4020
7558 11:41:27.449002 356 : 4252, 2878
7559 11:41:27.449398 360 : 4255, 1
7560 11:41:27.449714
7561 11:41:27.452164 MIOCK jitter meter ch=0
7562 11:41:27.452553
7563 11:41:27.455662 1T = (360-108) = 252 dly cells
7564 11:41:27.459027 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7565 11:41:27.459456 ==
7566 11:41:27.461930 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 11:41:27.468955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 11:41:27.469482 ==
7569 11:41:27.472093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7570 11:41:27.478787 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7571 11:41:27.481873 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7572 11:41:27.488606 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7573 11:41:27.496873 [CA 0] Center 44 (14~75) winsize 62
7574 11:41:27.500320 [CA 1] Center 43 (13~74) winsize 62
7575 11:41:27.503605 [CA 2] Center 40 (11~69) winsize 59
7576 11:41:27.506313 [CA 3] Center 39 (10~68) winsize 59
7577 11:41:27.510074 [CA 4] Center 37 (8~67) winsize 60
7578 11:41:27.513302 [CA 5] Center 37 (7~67) winsize 61
7579 11:41:27.513698
7580 11:41:27.516575 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7581 11:41:27.517007
7582 11:41:27.523190 [CATrainingPosCal] consider 1 rank data
7583 11:41:27.523620 u2DelayCellTimex100 = 258/100 ps
7584 11:41:27.529848 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7585 11:41:27.533125 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7586 11:41:27.536645 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7587 11:41:27.539671 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7588 11:41:27.543513 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7589 11:41:27.546127 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7590 11:41:27.546557
7591 11:41:27.549713 CA PerBit enable=1, Macro0, CA PI delay=37
7592 11:41:27.550162
7593 11:41:27.552530 [CBTSetCACLKResult] CA Dly = 37
7594 11:41:27.556233 CS Dly: 11 (0~42)
7595 11:41:27.559759 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7596 11:41:27.562439 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7597 11:41:27.565703 ==
7598 11:41:27.566233 Dram Type= 6, Freq= 0, CH_0, rank 1
7599 11:41:27.572893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 11:41:27.573423 ==
7601 11:41:27.575502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7602 11:41:27.582317 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7603 11:41:27.585671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7604 11:41:27.592019 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7605 11:41:27.600738 [CA 0] Center 43 (13~74) winsize 62
7606 11:41:27.604118 [CA 1] Center 43 (13~74) winsize 62
7607 11:41:27.606949 [CA 2] Center 39 (10~68) winsize 59
7608 11:41:27.610223 [CA 3] Center 39 (10~68) winsize 59
7609 11:41:27.613617 [CA 4] Center 36 (6~66) winsize 61
7610 11:41:27.616919 [CA 5] Center 36 (6~66) winsize 61
7611 11:41:27.617361
7612 11:41:27.620074 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7613 11:41:27.623425
7614 11:41:27.626696 [CATrainingPosCal] consider 2 rank data
7615 11:41:27.629969 u2DelayCellTimex100 = 258/100 ps
7616 11:41:27.633313 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7617 11:41:27.636513 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7618 11:41:27.639800 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7619 11:41:27.643283 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7620 11:41:27.646429 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7621 11:41:27.650098 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7622 11:41:27.650527
7623 11:41:27.656681 CA PerBit enable=1, Macro0, CA PI delay=36
7624 11:41:27.657109
7625 11:41:27.657442 [CBTSetCACLKResult] CA Dly = 36
7626 11:41:27.659625 CS Dly: 11 (0~43)
7627 11:41:27.663269 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7628 11:41:27.666385 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7629 11:41:27.669728
7630 11:41:27.673312 ----->DramcWriteLeveling(PI) begin...
7631 11:41:27.673872 ==
7632 11:41:27.675959 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 11:41:27.679378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 11:41:27.679812 ==
7635 11:41:27.682955 Write leveling (Byte 0): 36 => 36
7636 11:41:27.685976 Write leveling (Byte 1): 30 => 30
7637 11:41:27.689551 DramcWriteLeveling(PI) end<-----
7638 11:41:27.689980
7639 11:41:27.690321 ==
7640 11:41:27.692551 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 11:41:27.695799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 11:41:27.696233 ==
7643 11:41:27.699008 [Gating] SW mode calibration
7644 11:41:27.705726 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7645 11:41:27.712268 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7646 11:41:27.715486 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 11:41:27.718578 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 11:41:27.725210 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 11:41:27.728600 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 11:41:27.732003 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7651 11:41:27.738398 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7652 11:41:27.741768 1 4 24 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7653 11:41:27.745072 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 11:41:27.751594 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 11:41:27.755257 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7656 11:41:27.758228 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 11:41:27.764968 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7658 11:41:27.768522 1 5 16 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
7659 11:41:27.771680 1 5 20 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 1)
7660 11:41:27.777836 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7661 11:41:27.781220 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 11:41:27.784567 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 11:41:27.790994 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 11:41:27.794477 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 11:41:27.797981 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 11:41:27.804674 1 6 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7667 11:41:27.807946 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7668 11:41:27.811020 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7669 11:41:27.818250 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 11:41:27.820682 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 11:41:27.824365 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 11:41:27.830920 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 11:41:27.834304 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 11:41:27.840173 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7675 11:41:27.843509 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7676 11:41:27.847471 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7677 11:41:27.853651 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 11:41:27.857110 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 11:41:27.860538 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 11:41:27.866924 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 11:41:27.870545 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 11:41:27.873571 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 11:41:27.880084 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 11:41:27.882944 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 11:41:27.886381 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 11:41:27.893183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 11:41:27.896091 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 11:41:27.899846 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 11:41:27.906464 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7690 11:41:27.909986 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7691 11:41:27.912944 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7692 11:41:27.916420 Total UI for P1: 0, mck2ui 16
7693 11:41:27.919495 best dqsien dly found for B0: ( 1, 9, 14)
7694 11:41:27.925997 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7695 11:41:27.929336 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7696 11:41:27.932569 Total UI for P1: 0, mck2ui 16
7697 11:41:27.935840 best dqsien dly found for B1: ( 1, 9, 22)
7698 11:41:27.939261 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7699 11:41:27.942492 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7700 11:41:27.943021
7701 11:41:27.945822 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7702 11:41:27.949134 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7703 11:41:27.952475 [Gating] SW calibration Done
7704 11:41:27.952905 ==
7705 11:41:27.955928 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 11:41:27.959525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 11:41:27.962515 ==
7708 11:41:27.962987 RX Vref Scan: 0
7709 11:41:27.963330
7710 11:41:27.966144 RX Vref 0 -> 0, step: 1
7711 11:41:27.966571
7712 11:41:27.966946 RX Delay 0 -> 252, step: 8
7713 11:41:27.972337 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7714 11:41:27.975531 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7715 11:41:27.979089 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7716 11:41:27.982074 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7717 11:41:27.988685 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7718 11:41:27.992093 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7719 11:41:27.995027 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7720 11:41:27.998584 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7721 11:41:28.001612 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7722 11:41:28.008154 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7723 11:41:28.011787 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7724 11:41:28.014728 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7725 11:41:28.018175 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7726 11:41:28.021199 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
7727 11:41:28.027824 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7728 11:41:28.031386 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7729 11:41:28.031476 ==
7730 11:41:28.034382 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 11:41:28.037893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 11:41:28.037995 ==
7733 11:41:28.041355 DQS Delay:
7734 11:41:28.041458 DQS0 = 0, DQS1 = 0
7735 11:41:28.044507 DQM Delay:
7736 11:41:28.044598 DQM0 = 127, DQM1 = 123
7737 11:41:28.044666 DQ Delay:
7738 11:41:28.047474 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7739 11:41:28.054093 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7740 11:41:28.057898 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7741 11:41:28.060733 DQ12 =127, DQ13 =127, DQ14 =135, DQ15 =131
7742 11:41:28.060814
7743 11:41:28.060879
7744 11:41:28.060941 ==
7745 11:41:28.064424 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 11:41:28.067567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 11:41:28.067651 ==
7748 11:41:28.067716
7749 11:41:28.067775
7750 11:41:28.070982 TX Vref Scan disable
7751 11:41:28.074391 == TX Byte 0 ==
7752 11:41:28.077403 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7753 11:41:28.080817 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7754 11:41:28.084491 == TX Byte 1 ==
7755 11:41:28.087202 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7756 11:41:28.090903 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7757 11:41:28.091103 ==
7758 11:41:28.093991 Dram Type= 6, Freq= 0, CH_0, rank 0
7759 11:41:28.100252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7760 11:41:28.100450 ==
7761 11:41:28.112867
7762 11:41:28.115900 TX Vref early break, caculate TX vref
7763 11:41:28.119017 TX Vref=16, minBit 5, minWin=22, winSum=370
7764 11:41:28.122744 TX Vref=18, minBit 4, minWin=22, winSum=383
7765 11:41:28.125757 TX Vref=20, minBit 4, minWin=23, winSum=384
7766 11:41:28.129597 TX Vref=22, minBit 4, minWin=24, winSum=401
7767 11:41:28.132570 TX Vref=24, minBit 4, minWin=24, winSum=407
7768 11:41:28.139202 TX Vref=26, minBit 4, minWin=24, winSum=417
7769 11:41:28.142291 TX Vref=28, minBit 0, minWin=25, winSum=412
7770 11:41:28.145521 TX Vref=30, minBit 4, minWin=25, winSum=417
7771 11:41:28.149120 TX Vref=32, minBit 8, minWin=24, winSum=400
7772 11:41:28.152493 TX Vref=34, minBit 4, minWin=24, winSum=395
7773 11:41:28.159221 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 30
7774 11:41:28.159610
7775 11:41:28.162029 Final TX Range 0 Vref 30
7776 11:41:28.162559
7777 11:41:28.163010 ==
7778 11:41:28.165242 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 11:41:28.168570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 11:41:28.169063 ==
7781 11:41:28.169431
7782 11:41:28.169739
7783 11:41:28.171897 TX Vref Scan disable
7784 11:41:28.178328 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7785 11:41:28.178727 == TX Byte 0 ==
7786 11:41:28.181462 u2DelayCellOfst[0]=15 cells (4 PI)
7787 11:41:28.185357 u2DelayCellOfst[1]=18 cells (5 PI)
7788 11:41:28.188819 u2DelayCellOfst[2]=15 cells (4 PI)
7789 11:41:28.191742 u2DelayCellOfst[3]=15 cells (4 PI)
7790 11:41:28.194593 u2DelayCellOfst[4]=11 cells (3 PI)
7791 11:41:28.198166 u2DelayCellOfst[5]=0 cells (0 PI)
7792 11:41:28.201291 u2DelayCellOfst[6]=18 cells (5 PI)
7793 11:41:28.204853 u2DelayCellOfst[7]=18 cells (5 PI)
7794 11:41:28.208313 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7795 11:41:28.211660 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7796 11:41:28.215075 == TX Byte 1 ==
7797 11:41:28.217957 u2DelayCellOfst[8]=0 cells (0 PI)
7798 11:41:28.221550 u2DelayCellOfst[9]=3 cells (1 PI)
7799 11:41:28.224640 u2DelayCellOfst[10]=11 cells (3 PI)
7800 11:41:28.227949 u2DelayCellOfst[11]=7 cells (2 PI)
7801 11:41:28.231566 u2DelayCellOfst[12]=15 cells (4 PI)
7802 11:41:28.234666 u2DelayCellOfst[13]=15 cells (4 PI)
7803 11:41:28.235221 u2DelayCellOfst[14]=15 cells (4 PI)
7804 11:41:28.238085 u2DelayCellOfst[15]=11 cells (3 PI)
7805 11:41:28.244541 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7806 11:41:28.247575 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7807 11:41:28.250940 DramC Write-DBI on
7808 11:41:28.251388 ==
7809 11:41:28.254363 Dram Type= 6, Freq= 0, CH_0, rank 0
7810 11:41:28.257248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7811 11:41:28.257705 ==
7812 11:41:28.258185
7813 11:41:28.258515
7814 11:41:28.260618 TX Vref Scan disable
7815 11:41:28.261045 == TX Byte 0 ==
7816 11:41:28.267429 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7817 11:41:28.267955 == TX Byte 1 ==
7818 11:41:28.274038 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7819 11:41:28.274555 DramC Write-DBI off
7820 11:41:28.274941
7821 11:41:28.275270 [DATLAT]
7822 11:41:28.277410 Freq=1600, CH0 RK0
7823 11:41:28.277841
7824 11:41:28.280518 DATLAT Default: 0xf
7825 11:41:28.280952 0, 0xFFFF, sum = 0
7826 11:41:28.283897 1, 0xFFFF, sum = 0
7827 11:41:28.284338 2, 0xFFFF, sum = 0
7828 11:41:28.287104 3, 0xFFFF, sum = 0
7829 11:41:28.287534 4, 0xFFFF, sum = 0
7830 11:41:28.290461 5, 0xFFFF, sum = 0
7831 11:41:28.290932 6, 0xFFFF, sum = 0
7832 11:41:28.293737 7, 0xFFFF, sum = 0
7833 11:41:28.294166 8, 0xFFFF, sum = 0
7834 11:41:28.297297 9, 0xFFFF, sum = 0
7835 11:41:28.297834 10, 0xFFFF, sum = 0
7836 11:41:28.300290 11, 0xFFFF, sum = 0
7837 11:41:28.300725 12, 0xFFFF, sum = 0
7838 11:41:28.303295 13, 0xFFFF, sum = 0
7839 11:41:28.303747 14, 0x0, sum = 1
7840 11:41:28.306891 15, 0x0, sum = 2
7841 11:41:28.307455 16, 0x0, sum = 3
7842 11:41:28.310382 17, 0x0, sum = 4
7843 11:41:28.310810 best_step = 15
7844 11:41:28.311197
7845 11:41:28.311512 ==
7846 11:41:28.313285 Dram Type= 6, Freq= 0, CH_0, rank 0
7847 11:41:28.320596 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7848 11:41:28.321158 ==
7849 11:41:28.321561 RX Vref Scan: 1
7850 11:41:28.321881
7851 11:41:28.323487 Set Vref Range= 24 -> 127
7852 11:41:28.323909
7853 11:41:28.327209 RX Vref 24 -> 127, step: 1
7854 11:41:28.327728
7855 11:41:28.330042 RX Delay 11 -> 252, step: 4
7856 11:41:28.330566
7857 11:41:28.333506 Set Vref, RX VrefLevel [Byte0]: 24
7858 11:41:28.336248 [Byte1]: 24
7859 11:41:28.336774
7860 11:41:28.339713 Set Vref, RX VrefLevel [Byte0]: 25
7861 11:41:28.343349 [Byte1]: 25
7862 11:41:28.343771
7863 11:41:28.346370 Set Vref, RX VrefLevel [Byte0]: 26
7864 11:41:28.349796 [Byte1]: 26
7865 11:41:28.352733
7866 11:41:28.353258 Set Vref, RX VrefLevel [Byte0]: 27
7867 11:41:28.356130 [Byte1]: 27
7868 11:41:28.360246
7869 11:41:28.360667 Set Vref, RX VrefLevel [Byte0]: 28
7870 11:41:28.363636 [Byte1]: 28
7871 11:41:28.368362
7872 11:41:28.368899 Set Vref, RX VrefLevel [Byte0]: 29
7873 11:41:28.371374 [Byte1]: 29
7874 11:41:28.376021
7875 11:41:28.376543 Set Vref, RX VrefLevel [Byte0]: 30
7876 11:41:28.379106 [Byte1]: 30
7877 11:41:28.383432
7878 11:41:28.383852 Set Vref, RX VrefLevel [Byte0]: 31
7879 11:41:28.387011 [Byte1]: 31
7880 11:41:28.391261
7881 11:41:28.391863 Set Vref, RX VrefLevel [Byte0]: 32
7882 11:41:28.394096 [Byte1]: 32
7883 11:41:28.398495
7884 11:41:28.399058 Set Vref, RX VrefLevel [Byte0]: 33
7885 11:41:28.402074 [Byte1]: 33
7886 11:41:28.406357
7887 11:41:28.406928 Set Vref, RX VrefLevel [Byte0]: 34
7888 11:41:28.409624 [Byte1]: 34
7889 11:41:28.413791
7890 11:41:28.414349 Set Vref, RX VrefLevel [Byte0]: 35
7891 11:41:28.417376 [Byte1]: 35
7892 11:41:28.421954
7893 11:41:28.422483 Set Vref, RX VrefLevel [Byte0]: 36
7894 11:41:28.424853 [Byte1]: 36
7895 11:41:28.429071
7896 11:41:28.429592 Set Vref, RX VrefLevel [Byte0]: 37
7897 11:41:28.432272 [Byte1]: 37
7898 11:41:28.436673
7899 11:41:28.437222 Set Vref, RX VrefLevel [Byte0]: 38
7900 11:41:28.440082 [Byte1]: 38
7901 11:41:28.444347
7902 11:41:28.444891 Set Vref, RX VrefLevel [Byte0]: 39
7903 11:41:28.447739 [Byte1]: 39
7904 11:41:28.451617
7905 11:41:28.452057 Set Vref, RX VrefLevel [Byte0]: 40
7906 11:41:28.455180 [Byte1]: 40
7907 11:41:28.459292
7908 11:41:28.459800 Set Vref, RX VrefLevel [Byte0]: 41
7909 11:41:28.462609 [Byte1]: 41
7910 11:41:28.467449
7911 11:41:28.467973 Set Vref, RX VrefLevel [Byte0]: 42
7912 11:41:28.470381 [Byte1]: 42
7913 11:41:28.474903
7914 11:41:28.475323 Set Vref, RX VrefLevel [Byte0]: 43
7915 11:41:28.478069 [Byte1]: 43
7916 11:41:28.482128
7917 11:41:28.482573 Set Vref, RX VrefLevel [Byte0]: 44
7918 11:41:28.485639 [Byte1]: 44
7919 11:41:28.489967
7920 11:41:28.490521 Set Vref, RX VrefLevel [Byte0]: 45
7921 11:41:28.493034 [Byte1]: 45
7922 11:41:28.497520
7923 11:41:28.498037 Set Vref, RX VrefLevel [Byte0]: 46
7924 11:41:28.500892 [Byte1]: 46
7925 11:41:28.505109
7926 11:41:28.505633 Set Vref, RX VrefLevel [Byte0]: 47
7927 11:41:28.508466 [Byte1]: 47
7928 11:41:28.513104
7929 11:41:28.513623 Set Vref, RX VrefLevel [Byte0]: 48
7930 11:41:28.516389 [Byte1]: 48
7931 11:41:28.520405
7932 11:41:28.520924 Set Vref, RX VrefLevel [Byte0]: 49
7933 11:41:28.523587 [Byte1]: 49
7934 11:41:28.528443
7935 11:41:28.528967 Set Vref, RX VrefLevel [Byte0]: 50
7936 11:41:28.531308 [Byte1]: 50
7937 11:41:28.535701
7938 11:41:28.536248 Set Vref, RX VrefLevel [Byte0]: 51
7939 11:41:28.538713 [Byte1]: 51
7940 11:41:28.543339
7941 11:41:28.543800 Set Vref, RX VrefLevel [Byte0]: 52
7942 11:41:28.546411 [Byte1]: 52
7943 11:41:28.550616
7944 11:41:28.551066 Set Vref, RX VrefLevel [Byte0]: 53
7945 11:41:28.554152 [Byte1]: 53
7946 11:41:28.558408
7947 11:41:28.558886 Set Vref, RX VrefLevel [Byte0]: 54
7948 11:41:28.561460 [Byte1]: 54
7949 11:41:28.566118
7950 11:41:28.566536 Set Vref, RX VrefLevel [Byte0]: 55
7951 11:41:28.569240 [Byte1]: 55
7952 11:41:28.573891
7953 11:41:28.574341 Set Vref, RX VrefLevel [Byte0]: 56
7954 11:41:28.576926 [Byte1]: 56
7955 11:41:28.581134
7956 11:41:28.581561 Set Vref, RX VrefLevel [Byte0]: 57
7957 11:41:28.584664 [Byte1]: 57
7958 11:41:28.589011
7959 11:41:28.589438 Set Vref, RX VrefLevel [Byte0]: 58
7960 11:41:28.592316 [Byte1]: 58
7961 11:41:28.596647
7962 11:41:28.597073 Set Vref, RX VrefLevel [Byte0]: 59
7963 11:41:28.599794 [Byte1]: 59
7964 11:41:28.604317
7965 11:41:28.604740 Set Vref, RX VrefLevel [Byte0]: 60
7966 11:41:28.607502 [Byte1]: 60
7967 11:41:28.611391
7968 11:41:28.611812 Set Vref, RX VrefLevel [Byte0]: 61
7969 11:41:28.614709 [Byte1]: 61
7970 11:41:28.619393
7971 11:41:28.619891 Set Vref, RX VrefLevel [Byte0]: 62
7972 11:41:28.622917 [Byte1]: 62
7973 11:41:28.626932
7974 11:41:28.627365 Set Vref, RX VrefLevel [Byte0]: 63
7975 11:41:28.630325 [Byte1]: 63
7976 11:41:28.634701
7977 11:41:28.635190 Set Vref, RX VrefLevel [Byte0]: 64
7978 11:41:28.637700 [Byte1]: 64
7979 11:41:28.641848
7980 11:41:28.642284 Set Vref, RX VrefLevel [Byte0]: 65
7981 11:41:28.644986 [Byte1]: 65
7982 11:41:28.649700
7983 11:41:28.650153 Set Vref, RX VrefLevel [Byte0]: 66
7984 11:41:28.653144 [Byte1]: 66
7985 11:41:28.657335
7986 11:41:28.657928 Set Vref, RX VrefLevel [Byte0]: 67
7987 11:41:28.660342 [Byte1]: 67
7988 11:41:28.664711
7989 11:41:28.665134 Set Vref, RX VrefLevel [Byte0]: 68
7990 11:41:28.668272 [Byte1]: 68
7991 11:41:28.672407
7992 11:41:28.672830 Set Vref, RX VrefLevel [Byte0]: 69
7993 11:41:28.675956 [Byte1]: 69
7994 11:41:28.680127
7995 11:41:28.680571 Set Vref, RX VrefLevel [Byte0]: 70
7996 11:41:28.683674 [Byte1]: 70
7997 11:41:28.687842
7998 11:41:28.688284 Set Vref, RX VrefLevel [Byte0]: 71
7999 11:41:28.691193 [Byte1]: 71
8000 11:41:28.695088
8001 11:41:28.695530 Set Vref, RX VrefLevel [Byte0]: 72
8002 11:41:28.698406 [Byte1]: 72
8003 11:41:28.702955
8004 11:41:28.703380 Set Vref, RX VrefLevel [Byte0]: 73
8005 11:41:28.706273 [Byte1]: 73
8006 11:41:28.710749
8007 11:41:28.711211 Set Vref, RX VrefLevel [Byte0]: 74
8008 11:41:28.714160 [Byte1]: 74
8009 11:41:28.718024
8010 11:41:28.718445 Set Vref, RX VrefLevel [Byte0]: 75
8011 11:41:28.721226 [Byte1]: 75
8012 11:41:28.725767
8013 11:41:28.726196 Set Vref, RX VrefLevel [Byte0]: 76
8014 11:41:28.728818 [Byte1]: 76
8015 11:41:28.733307
8016 11:41:28.733729 Set Vref, RX VrefLevel [Byte0]: 77
8017 11:41:28.736665 [Byte1]: 77
8018 11:41:28.740859
8019 11:41:28.741326 Final RX Vref Byte 0 = 65 to rank0
8020 11:41:28.743983 Final RX Vref Byte 1 = 58 to rank0
8021 11:41:28.747477 Final RX Vref Byte 0 = 65 to rank1
8022 11:41:28.750636 Final RX Vref Byte 1 = 58 to rank1==
8023 11:41:28.753927 Dram Type= 6, Freq= 0, CH_0, rank 0
8024 11:41:28.760962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 11:41:28.761391 ==
8026 11:41:28.761813 DQS Delay:
8027 11:41:28.763877 DQS0 = 0, DQS1 = 0
8028 11:41:28.764302 DQM Delay:
8029 11:41:28.764634 DQM0 = 126, DQM1 = 120
8030 11:41:28.766976 DQ Delay:
8031 11:41:28.770622 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8032 11:41:28.774023 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8033 11:41:28.776911 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8034 11:41:28.780702 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
8035 11:41:28.781131
8036 11:41:28.781467
8037 11:41:28.781782
8038 11:41:28.783611 [DramC_TX_OE_Calibration] TA2
8039 11:41:28.787008 Original DQ_B0 (3 6) =30, OEN = 27
8040 11:41:28.790671 Original DQ_B1 (3 6) =30, OEN = 27
8041 11:41:28.793616 24, 0x0, End_B0=24 End_B1=24
8042 11:41:28.796527 25, 0x0, End_B0=25 End_B1=25
8043 11:41:28.796961 26, 0x0, End_B0=26 End_B1=26
8044 11:41:28.800090 27, 0x0, End_B0=27 End_B1=27
8045 11:41:28.803241 28, 0x0, End_B0=28 End_B1=28
8046 11:41:28.806559 29, 0x0, End_B0=29 End_B1=29
8047 11:41:28.809902 30, 0x0, End_B0=30 End_B1=30
8048 11:41:28.810016 31, 0x4545, End_B0=30 End_B1=30
8049 11:41:28.813079 Byte0 end_step=30 best_step=27
8050 11:41:28.815926 Byte1 end_step=30 best_step=27
8051 11:41:28.819410 Byte0 TX OE(2T, 0.5T) = (3, 3)
8052 11:41:28.822964 Byte1 TX OE(2T, 0.5T) = (3, 3)
8053 11:41:28.823048
8054 11:41:28.823113
8055 11:41:28.829052 [DQSOSCAuto] RK0, (LSB)MR18= 0x100f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8056 11:41:28.832560 CH0 RK0: MR19=303, MR18=100F
8057 11:41:28.839047 CH0_RK0: MR19=0x303, MR18=0x100F, DQSOSC=401, MR23=63, INC=22, DEC=15
8058 11:41:28.839161
8059 11:41:28.842477 ----->DramcWriteLeveling(PI) begin...
8060 11:41:28.842560 ==
8061 11:41:28.845542 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 11:41:28.849103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 11:41:28.852363 ==
8064 11:41:28.852451 Write leveling (Byte 0): 34 => 34
8065 11:41:28.855691 Write leveling (Byte 1): 26 => 26
8066 11:41:28.858724 DramcWriteLeveling(PI) end<-----
8067 11:41:28.858818
8068 11:41:28.858904 ==
8069 11:41:28.862177 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 11:41:28.868732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 11:41:28.868844 ==
8072 11:41:28.872236 [Gating] SW mode calibration
8073 11:41:28.878660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8074 11:41:28.881969 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8075 11:41:28.888598 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 11:41:28.892110 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 11:41:28.895647 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 11:41:28.902271 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8079 11:41:28.905556 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (1 1) (1 1)
8080 11:41:28.908775 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 11:41:28.915506 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 11:41:28.918598 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 11:41:28.921844 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 11:41:28.928471 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 11:41:28.931826 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8086 11:41:28.935085 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8087 11:41:28.941784 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8088 11:41:28.945128 1 5 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8089 11:41:28.948007 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 11:41:28.954462 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 11:41:28.958154 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 11:41:28.960893 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 11:41:28.967931 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8094 11:41:28.971396 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8095 11:41:28.974383 1 6 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8096 11:41:28.980854 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
8097 11:41:28.984433 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 11:41:28.987228 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 11:41:28.993917 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 11:41:28.997377 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 11:41:29.000427 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 11:41:29.006977 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8103 11:41:29.010681 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8104 11:41:29.013865 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8105 11:41:29.020078 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:41:29.023634 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:41:29.026980 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 11:41:29.033418 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 11:41:29.036835 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 11:41:29.040181 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 11:41:29.046279 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 11:41:29.049778 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 11:41:29.053201 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 11:41:29.059585 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 11:41:29.063164 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 11:41:29.066218 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 11:41:29.073153 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8118 11:41:29.076210 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8119 11:41:29.079611 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8120 11:41:29.082718 Total UI for P1: 0, mck2ui 16
8121 11:41:29.086473 best dqsien dly found for B0: ( 1, 9, 10)
8122 11:41:29.092882 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8123 11:41:29.095906 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 11:41:29.099313 Total UI for P1: 0, mck2ui 16
8125 11:41:29.102292 best dqsien dly found for B1: ( 1, 9, 18)
8126 11:41:29.105496 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8127 11:41:29.109027 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8128 11:41:29.109110
8129 11:41:29.112708 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8130 11:41:29.118688 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8131 11:41:29.118797 [Gating] SW calibration Done
8132 11:41:29.118912 ==
8133 11:41:29.122111 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 11:41:29.128926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 11:41:29.129009 ==
8136 11:41:29.129075 RX Vref Scan: 0
8137 11:41:29.129136
8138 11:41:29.131988 RX Vref 0 -> 0, step: 1
8139 11:41:29.132071
8140 11:41:29.135421 RX Delay 0 -> 252, step: 8
8141 11:41:29.138629 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8142 11:41:29.141970 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8143 11:41:29.145200 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8144 11:41:29.151978 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8145 11:41:29.155267 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8146 11:41:29.158765 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8147 11:41:29.161921 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8148 11:41:29.164812 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8149 11:41:29.171661 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8150 11:41:29.175248 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8151 11:41:29.178212 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8152 11:41:29.181469 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8153 11:41:29.185158 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8154 11:41:29.191793 iDelay=200, Bit 13, Center 123 (64 ~ 183) 120
8155 11:41:29.195318 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8156 11:41:29.198222 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8157 11:41:29.198614 ==
8158 11:41:29.201868 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 11:41:29.205242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 11:41:29.208065 ==
8161 11:41:29.208490 DQS Delay:
8162 11:41:29.208827 DQS0 = 0, DQS1 = 0
8163 11:41:29.211497 DQM Delay:
8164 11:41:29.211921 DQM0 = 127, DQM1 = 120
8165 11:41:29.215050 DQ Delay:
8166 11:41:29.218057 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8167 11:41:29.221498 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8168 11:41:29.224470 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8169 11:41:29.228080 DQ12 =127, DQ13 =123, DQ14 =131, DQ15 =127
8170 11:41:29.228545
8171 11:41:29.228881
8172 11:41:29.229197 ==
8173 11:41:29.231062 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 11:41:29.234465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 11:41:29.237701 ==
8176 11:41:29.238127
8177 11:41:29.238462
8178 11:41:29.238775 TX Vref Scan disable
8179 11:41:29.240971 == TX Byte 0 ==
8180 11:41:29.244229 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8181 11:41:29.247402 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8182 11:41:29.250774 == TX Byte 1 ==
8183 11:41:29.254415 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8184 11:41:29.257616 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8185 11:41:29.261133 ==
8186 11:41:29.264067 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 11:41:29.267312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 11:41:29.267747 ==
8189 11:41:29.280615
8190 11:41:29.283483 TX Vref early break, caculate TX vref
8191 11:41:29.287048 TX Vref=16, minBit 0, minWin=22, winSum=365
8192 11:41:29.290324 TX Vref=18, minBit 8, minWin=22, winSum=370
8193 11:41:29.293764 TX Vref=20, minBit 1, minWin=23, winSum=384
8194 11:41:29.296664 TX Vref=22, minBit 8, minWin=23, winSum=388
8195 11:41:29.300472 TX Vref=24, minBit 0, minWin=24, winSum=400
8196 11:41:29.306880 TX Vref=26, minBit 8, minWin=24, winSum=404
8197 11:41:29.310286 TX Vref=28, minBit 13, minWin=24, winSum=411
8198 11:41:29.313840 TX Vref=30, minBit 8, minWin=24, winSum=403
8199 11:41:29.316790 TX Vref=32, minBit 8, minWin=23, winSum=395
8200 11:41:29.320420 TX Vref=34, minBit 8, minWin=22, winSum=387
8201 11:41:29.326695 [TxChooseVref] Worse bit 13, Min win 24, Win sum 411, Final Vref 28
8202 11:41:29.327148
8203 11:41:29.330244 Final TX Range 0 Vref 28
8204 11:41:29.330672
8205 11:41:29.331047 ==
8206 11:41:29.333218 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 11:41:29.336637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 11:41:29.337135 ==
8209 11:41:29.337478
8210 11:41:29.337792
8211 11:41:29.339552 TX Vref Scan disable
8212 11:41:29.346926 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8213 11:41:29.347357 == TX Byte 0 ==
8214 11:41:29.349527 u2DelayCellOfst[0]=15 cells (4 PI)
8215 11:41:29.352831 u2DelayCellOfst[1]=15 cells (4 PI)
8216 11:41:29.356455 u2DelayCellOfst[2]=11 cells (3 PI)
8217 11:41:29.359600 u2DelayCellOfst[3]=11 cells (3 PI)
8218 11:41:29.362799 u2DelayCellOfst[4]=7 cells (2 PI)
8219 11:41:29.366191 u2DelayCellOfst[5]=0 cells (0 PI)
8220 11:41:29.369425 u2DelayCellOfst[6]=18 cells (5 PI)
8221 11:41:29.372887 u2DelayCellOfst[7]=18 cells (5 PI)
8222 11:41:29.375950 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8223 11:41:29.379364 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8224 11:41:29.382663 == TX Byte 1 ==
8225 11:41:29.386069 u2DelayCellOfst[8]=0 cells (0 PI)
8226 11:41:29.389420 u2DelayCellOfst[9]=0 cells (0 PI)
8227 11:41:29.393421 u2DelayCellOfst[10]=7 cells (2 PI)
8228 11:41:29.396224 u2DelayCellOfst[11]=3 cells (1 PI)
8229 11:41:29.396751 u2DelayCellOfst[12]=15 cells (4 PI)
8230 11:41:29.398960 u2DelayCellOfst[13]=15 cells (4 PI)
8231 11:41:29.402409 u2DelayCellOfst[14]=15 cells (4 PI)
8232 11:41:29.405628 u2DelayCellOfst[15]=15 cells (4 PI)
8233 11:41:29.412090 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8234 11:41:29.415635 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8235 11:41:29.418748 DramC Write-DBI on
8236 11:41:29.419305 ==
8237 11:41:29.422156 Dram Type= 6, Freq= 0, CH_0, rank 1
8238 11:41:29.425044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 11:41:29.425483 ==
8240 11:41:29.425827
8241 11:41:29.426144
8242 11:41:29.428504 TX Vref Scan disable
8243 11:41:29.428950 == TX Byte 0 ==
8244 11:41:29.435094 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8245 11:41:29.435527 == TX Byte 1 ==
8246 11:41:29.438437 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8247 11:41:29.441605 DramC Write-DBI off
8248 11:41:29.442104
8249 11:41:29.442483 [DATLAT]
8250 11:41:29.445138 Freq=1600, CH0 RK1
8251 11:41:29.445568
8252 11:41:29.445906 DATLAT Default: 0xf
8253 11:41:29.448559 0, 0xFFFF, sum = 0
8254 11:41:29.448997 1, 0xFFFF, sum = 0
8255 11:41:29.451464 2, 0xFFFF, sum = 0
8256 11:41:29.455101 3, 0xFFFF, sum = 0
8257 11:41:29.455533 4, 0xFFFF, sum = 0
8258 11:41:29.458456 5, 0xFFFF, sum = 0
8259 11:41:29.458922 6, 0xFFFF, sum = 0
8260 11:41:29.461217 7, 0xFFFF, sum = 0
8261 11:41:29.461649 8, 0xFFFF, sum = 0
8262 11:41:29.464956 9, 0xFFFF, sum = 0
8263 11:41:29.465390 10, 0xFFFF, sum = 0
8264 11:41:29.467959 11, 0xFFFF, sum = 0
8265 11:41:29.468042 12, 0xFFFF, sum = 0
8266 11:41:29.471109 13, 0xCFFF, sum = 0
8267 11:41:29.471213 14, 0x0, sum = 1
8268 11:41:29.474418 15, 0x0, sum = 2
8269 11:41:29.474492 16, 0x0, sum = 3
8270 11:41:29.477836 17, 0x0, sum = 4
8271 11:41:29.477912 best_step = 15
8272 11:41:29.477973
8273 11:41:29.478031 ==
8274 11:41:29.481103 Dram Type= 6, Freq= 0, CH_0, rank 1
8275 11:41:29.487527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 11:41:29.487603 ==
8277 11:41:29.487666 RX Vref Scan: 0
8278 11:41:29.487725
8279 11:41:29.490774 RX Vref 0 -> 0, step: 1
8280 11:41:29.490881
8281 11:41:29.493858 RX Delay 3 -> 252, step: 4
8282 11:41:29.497565 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
8283 11:41:29.500839 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8284 11:41:29.504088 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8285 11:41:29.510542 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8286 11:41:29.514183 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
8287 11:41:29.516943 iDelay=195, Bit 5, Center 112 (59 ~ 166) 108
8288 11:41:29.520488 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8289 11:41:29.527040 iDelay=195, Bit 7, Center 136 (79 ~ 194) 116
8290 11:41:29.530395 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8291 11:41:29.533483 iDelay=195, Bit 9, Center 104 (47 ~ 162) 116
8292 11:41:29.536976 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
8293 11:41:29.540479 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8294 11:41:29.546989 iDelay=195, Bit 12, Center 124 (67 ~ 182) 116
8295 11:41:29.550331 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
8296 11:41:29.553262 iDelay=195, Bit 14, Center 128 (71 ~ 186) 116
8297 11:41:29.556721 iDelay=195, Bit 15, Center 124 (67 ~ 182) 116
8298 11:41:29.557142 ==
8299 11:41:29.560108 Dram Type= 6, Freq= 0, CH_0, rank 1
8300 11:41:29.566491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 11:41:29.567049 ==
8302 11:41:29.567398 DQS Delay:
8303 11:41:29.570109 DQS0 = 0, DQS1 = 0
8304 11:41:29.570634 DQM Delay:
8305 11:41:29.573169 DQM0 = 125, DQM1 = 118
8306 11:41:29.573683 DQ Delay:
8307 11:41:29.576583 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8308 11:41:29.579984 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =136
8309 11:41:29.582933 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8310 11:41:29.586254 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8311 11:41:29.586675
8312 11:41:29.587145
8313 11:41:29.587475
8314 11:41:29.590067 [DramC_TX_OE_Calibration] TA2
8315 11:41:29.593262 Original DQ_B0 (3 6) =30, OEN = 27
8316 11:41:29.596012 Original DQ_B1 (3 6) =30, OEN = 27
8317 11:41:29.599516 24, 0x0, End_B0=24 End_B1=24
8318 11:41:29.602999 25, 0x0, End_B0=25 End_B1=25
8319 11:41:29.603429 26, 0x0, End_B0=26 End_B1=26
8320 11:41:29.606922 27, 0x0, End_B0=27 End_B1=27
8321 11:41:29.609579 28, 0x0, End_B0=28 End_B1=28
8322 11:41:29.612515 29, 0x0, End_B0=29 End_B1=29
8323 11:41:29.615936 30, 0x0, End_B0=30 End_B1=30
8324 11:41:29.616426 31, 0x4141, End_B0=30 End_B1=30
8325 11:41:29.619373 Byte0 end_step=30 best_step=27
8326 11:41:29.622396 Byte1 end_step=30 best_step=27
8327 11:41:29.625606 Byte0 TX OE(2T, 0.5T) = (3, 3)
8328 11:41:29.629419 Byte1 TX OE(2T, 0.5T) = (3, 3)
8329 11:41:29.629945
8330 11:41:29.630277
8331 11:41:29.635725 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8332 11:41:29.639213 CH0 RK1: MR19=303, MR18=210F
8333 11:41:29.645667 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8334 11:41:29.649269 [RxdqsGatingPostProcess] freq 1600
8335 11:41:29.655253 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8336 11:41:29.658882 best DQS0 dly(2T, 0.5T) = (1, 1)
8337 11:41:29.661720 best DQS1 dly(2T, 0.5T) = (1, 1)
8338 11:41:29.665407 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8339 11:41:29.665953 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8340 11:41:29.668932 best DQS0 dly(2T, 0.5T) = (1, 1)
8341 11:41:29.671609 best DQS1 dly(2T, 0.5T) = (1, 1)
8342 11:41:29.675288 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8343 11:41:29.678072 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8344 11:41:29.681496 Pre-setting of DQS Precalculation
8345 11:41:29.688378 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8346 11:41:29.688988 ==
8347 11:41:29.691502 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 11:41:29.694912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 11:41:29.695349 ==
8350 11:41:29.701516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8351 11:41:29.704940 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8352 11:41:29.707899 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8353 11:41:29.714040 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8354 11:41:29.723153 [CA 0] Center 41 (12~70) winsize 59
8355 11:41:29.726739 [CA 1] Center 42 (12~72) winsize 61
8356 11:41:29.730333 [CA 2] Center 37 (8~66) winsize 59
8357 11:41:29.732956 [CA 3] Center 36 (7~66) winsize 60
8358 11:41:29.736480 [CA 4] Center 37 (8~67) winsize 60
8359 11:41:29.739837 [CA 5] Center 36 (7~65) winsize 59
8360 11:41:29.740257
8361 11:41:29.743351 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8362 11:41:29.743797
8363 11:41:29.749698 [CATrainingPosCal] consider 1 rank data
8364 11:41:29.750120 u2DelayCellTimex100 = 258/100 ps
8365 11:41:29.756095 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8366 11:41:29.759487 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8367 11:41:29.762971 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8368 11:41:29.765783 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8369 11:41:29.769544 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8370 11:41:29.772661 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8371 11:41:29.773138
8372 11:41:29.776580 CA PerBit enable=1, Macro0, CA PI delay=36
8373 11:41:29.777103
8374 11:41:29.779087 [CBTSetCACLKResult] CA Dly = 36
8375 11:41:29.782973 CS Dly: 10 (0~41)
8376 11:41:29.785613 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8377 11:41:29.789414 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8378 11:41:29.789836 ==
8379 11:41:29.792426 Dram Type= 6, Freq= 0, CH_1, rank 1
8380 11:41:29.798929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 11:41:29.799355 ==
8382 11:41:29.802476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8383 11:41:29.808607 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8384 11:41:29.812083 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8385 11:41:29.818770 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8386 11:41:29.826515 [CA 0] Center 41 (12~71) winsize 60
8387 11:41:29.829920 [CA 1] Center 42 (12~72) winsize 61
8388 11:41:29.833225 [CA 2] Center 37 (8~67) winsize 60
8389 11:41:29.836534 [CA 3] Center 36 (7~66) winsize 60
8390 11:41:29.839743 [CA 4] Center 37 (8~67) winsize 60
8391 11:41:29.842605 [CA 5] Center 36 (6~66) winsize 61
8392 11:41:29.843084
8393 11:41:29.846228 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8394 11:41:29.846648
8395 11:41:29.852575 [CATrainingPosCal] consider 2 rank data
8396 11:41:29.852994 u2DelayCellTimex100 = 258/100 ps
8397 11:41:29.859410 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8398 11:41:29.862587 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8399 11:41:29.866225 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8400 11:41:29.869446 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8401 11:41:29.872660 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8402 11:41:29.875455 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8403 11:41:29.875922
8404 11:41:29.879553 CA PerBit enable=1, Macro0, CA PI delay=36
8405 11:41:29.880401
8406 11:41:29.882735 [CBTSetCACLKResult] CA Dly = 36
8407 11:41:29.885592 CS Dly: 11 (0~43)
8408 11:41:29.889095 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8409 11:41:29.892140 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8410 11:41:29.892572
8411 11:41:29.895602 ----->DramcWriteLeveling(PI) begin...
8412 11:41:29.898892 ==
8413 11:41:29.899327 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 11:41:29.905386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 11:41:29.905941 ==
8416 11:41:29.908666 Write leveling (Byte 0): 25 => 25
8417 11:41:29.911991 Write leveling (Byte 1): 28 => 28
8418 11:41:29.915246 DramcWriteLeveling(PI) end<-----
8419 11:41:29.915849
8420 11:41:29.916209 ==
8421 11:41:29.918426 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 11:41:29.921612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 11:41:29.922045 ==
8424 11:41:29.925001 [Gating] SW mode calibration
8425 11:41:29.931851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8426 11:41:29.938542 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8427 11:41:29.941582 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 11:41:29.944989 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 11:41:29.951452 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 11:41:29.954450 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 11:41:29.958193 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (0 0)
8432 11:41:29.964426 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 11:41:29.967692 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 11:41:29.971305 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8435 11:41:29.978104 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8436 11:41:29.981328 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8437 11:41:29.984150 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8438 11:41:29.991072 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8439 11:41:29.994136 1 5 16 | B1->B0 | 2828 2525 | 0 0 | (1 0) (1 0)
8440 11:41:29.997558 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 11:41:30.004106 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 11:41:30.007435 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 11:41:30.010632 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 11:41:30.017580 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 11:41:30.020332 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 11:41:30.023700 1 6 12 | B1->B0 | 2c2c 2525 | 0 0 | (1 1) (0 0)
8447 11:41:30.030073 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8448 11:41:30.033436 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 11:41:30.036855 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 11:41:30.043753 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 11:41:30.046572 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8452 11:41:30.050255 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 11:41:30.056564 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8454 11:41:30.060306 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8455 11:41:30.063199 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8456 11:41:30.070057 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8457 11:41:30.072854 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 11:41:30.076487 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 11:41:30.083234 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:41:30.086201 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 11:41:30.089636 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 11:41:30.096755 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 11:41:30.099783 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 11:41:30.103190 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 11:41:30.109781 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 11:41:30.112889 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 11:41:30.116142 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 11:41:30.122590 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 11:41:30.125832 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 11:41:30.129342 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8471 11:41:30.135964 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8472 11:41:30.139277 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 11:41:30.142543 Total UI for P1: 0, mck2ui 16
8474 11:41:30.145601 best dqsien dly found for B0: ( 1, 9, 14)
8475 11:41:30.149127 Total UI for P1: 0, mck2ui 16
8476 11:41:30.151985 best dqsien dly found for B1: ( 1, 9, 16)
8477 11:41:30.155259 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8478 11:41:30.158571 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8479 11:41:30.159095
8480 11:41:30.162076 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8481 11:41:30.165723 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8482 11:41:30.168662 [Gating] SW calibration Done
8483 11:41:30.169086 ==
8484 11:41:30.172161 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 11:41:30.178392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 11:41:30.179046 ==
8487 11:41:30.179583 RX Vref Scan: 0
8488 11:41:30.180097
8489 11:41:30.181780 RX Vref 0 -> 0, step: 1
8490 11:41:30.182343
8491 11:41:30.184630 RX Delay 0 -> 252, step: 8
8492 11:41:30.188193 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8493 11:41:30.191806 iDelay=208, Bit 1, Center 123 (64 ~ 183) 120
8494 11:41:30.194800 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8495 11:41:30.198222 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8496 11:41:30.204418 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8497 11:41:30.208001 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8498 11:41:30.210977 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8499 11:41:30.214389 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8500 11:41:30.217485 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8501 11:41:30.224112 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8502 11:41:30.227745 iDelay=208, Bit 10, Center 127 (80 ~ 175) 96
8503 11:41:30.230944 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8504 11:41:30.233829 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8505 11:41:30.240866 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8506 11:41:30.244020 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8507 11:41:30.247344 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8508 11:41:30.247429 ==
8509 11:41:30.250888 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 11:41:30.253850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 11:41:30.253953 ==
8512 11:41:30.257621 DQS Delay:
8513 11:41:30.257730 DQS0 = 0, DQS1 = 0
8514 11:41:30.260497 DQM Delay:
8515 11:41:30.260608 DQM0 = 132, DQM1 = 126
8516 11:41:30.264258 DQ Delay:
8517 11:41:30.267240 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8518 11:41:30.270599 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8519 11:41:30.273592 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8520 11:41:30.277021 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8521 11:41:30.277124
8522 11:41:30.277217
8523 11:41:30.277314 ==
8524 11:41:30.280466 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 11:41:30.283378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 11:41:30.283462 ==
8527 11:41:30.283541
8528 11:41:30.283615
8529 11:41:30.286836 TX Vref Scan disable
8530 11:41:30.290463 == TX Byte 0 ==
8531 11:41:30.293303 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8532 11:41:30.296751 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8533 11:41:30.300286 == TX Byte 1 ==
8534 11:41:30.303380 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8535 11:41:30.306933 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8536 11:41:30.307042 ==
8537 11:41:30.310013 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 11:41:30.316509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 11:41:30.316592 ==
8540 11:41:30.327971
8541 11:41:30.331666 TX Vref early break, caculate TX vref
8542 11:41:30.334687 TX Vref=16, minBit 5, minWin=21, winSum=359
8543 11:41:30.338033 TX Vref=18, minBit 11, minWin=22, winSum=373
8544 11:41:30.341119 TX Vref=20, minBit 1, minWin=22, winSum=380
8545 11:41:30.344723 TX Vref=22, minBit 9, minWin=23, winSum=394
8546 11:41:30.347791 TX Vref=24, minBit 1, minWin=24, winSum=404
8547 11:41:30.354729 TX Vref=26, minBit 5, minWin=24, winSum=410
8548 11:41:30.357985 TX Vref=28, minBit 0, minWin=25, winSum=413
8549 11:41:30.361320 TX Vref=30, minBit 0, minWin=24, winSum=409
8550 11:41:30.364565 TX Vref=32, minBit 9, minWin=22, winSum=402
8551 11:41:30.367882 TX Vref=34, minBit 0, minWin=23, winSum=389
8552 11:41:30.374234 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8553 11:41:30.374320
8554 11:41:30.377746 Final TX Range 0 Vref 28
8555 11:41:30.377832
8556 11:41:30.377920 ==
8557 11:41:30.381187 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 11:41:30.384127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 11:41:30.384213 ==
8560 11:41:30.384298
8561 11:41:30.384377
8562 11:41:30.387587 TX Vref Scan disable
8563 11:41:30.394041 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8564 11:41:30.394126 == TX Byte 0 ==
8565 11:41:30.397501 u2DelayCellOfst[0]=18 cells (5 PI)
8566 11:41:30.401050 u2DelayCellOfst[1]=15 cells (4 PI)
8567 11:41:30.404005 u2DelayCellOfst[2]=0 cells (0 PI)
8568 11:41:30.407454 u2DelayCellOfst[3]=3 cells (1 PI)
8569 11:41:30.410446 u2DelayCellOfst[4]=7 cells (2 PI)
8570 11:41:30.413939 u2DelayCellOfst[5]=22 cells (6 PI)
8571 11:41:30.417468 u2DelayCellOfst[6]=18 cells (5 PI)
8572 11:41:30.420489 u2DelayCellOfst[7]=3 cells (1 PI)
8573 11:41:30.423441 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8574 11:41:30.427046 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8575 11:41:30.429992 == TX Byte 1 ==
8576 11:41:30.433493 u2DelayCellOfst[8]=0 cells (0 PI)
8577 11:41:30.437081 u2DelayCellOfst[9]=11 cells (3 PI)
8578 11:41:30.440296 u2DelayCellOfst[10]=18 cells (5 PI)
8579 11:41:30.443716 u2DelayCellOfst[11]=11 cells (3 PI)
8580 11:41:30.443817 u2DelayCellOfst[12]=18 cells (5 PI)
8581 11:41:30.446730 u2DelayCellOfst[13]=22 cells (6 PI)
8582 11:41:30.450124 u2DelayCellOfst[14]=22 cells (6 PI)
8583 11:41:30.453287 u2DelayCellOfst[15]=22 cells (6 PI)
8584 11:41:30.459877 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8585 11:41:30.463091 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8586 11:41:30.463172 DramC Write-DBI on
8587 11:41:30.466667 ==
8588 11:41:30.470119 Dram Type= 6, Freq= 0, CH_1, rank 0
8589 11:41:30.472908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8590 11:41:30.472994 ==
8591 11:41:30.473078
8592 11:41:30.473157
8593 11:41:30.476232 TX Vref Scan disable
8594 11:41:30.476317 == TX Byte 0 ==
8595 11:41:30.483138 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8596 11:41:30.483311 == TX Byte 1 ==
8597 11:41:30.486123 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8598 11:41:30.489631 DramC Write-DBI off
8599 11:41:30.489791
8600 11:41:30.489888 [DATLAT]
8601 11:41:30.492913 Freq=1600, CH1 RK0
8602 11:41:30.493025
8603 11:41:30.493106 DATLAT Default: 0xf
8604 11:41:30.496447 0, 0xFFFF, sum = 0
8605 11:41:30.496560 1, 0xFFFF, sum = 0
8606 11:41:30.499469 2, 0xFFFF, sum = 0
8607 11:41:30.499593 3, 0xFFFF, sum = 0
8608 11:41:30.502814 4, 0xFFFF, sum = 0
8609 11:41:30.502948 5, 0xFFFF, sum = 0
8610 11:41:30.506645 6, 0xFFFF, sum = 0
8611 11:41:30.509306 7, 0xFFFF, sum = 0
8612 11:41:30.509504 8, 0xFFFF, sum = 0
8613 11:41:30.513020 9, 0xFFFF, sum = 0
8614 11:41:30.513257 10, 0xFFFF, sum = 0
8615 11:41:30.516319 11, 0xFFFF, sum = 0
8616 11:41:30.516583 12, 0xFFFF, sum = 0
8617 11:41:30.519661 13, 0x8FFF, sum = 0
8618 11:41:30.519958 14, 0x0, sum = 1
8619 11:41:30.523016 15, 0x0, sum = 2
8620 11:41:30.523226 16, 0x0, sum = 3
8621 11:41:30.526645 17, 0x0, sum = 4
8622 11:41:30.527013 best_step = 15
8623 11:41:30.527226
8624 11:41:30.527412 ==
8625 11:41:30.529181 Dram Type= 6, Freq= 0, CH_1, rank 0
8626 11:41:30.532787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8627 11:41:30.532870 ==
8628 11:41:30.536286 RX Vref Scan: 1
8629 11:41:30.536374
8630 11:41:30.539397 Set Vref Range= 24 -> 127
8631 11:41:30.539573
8632 11:41:30.539661 RX Vref 24 -> 127, step: 1
8633 11:41:30.542844
8634 11:41:30.543025 RX Delay 11 -> 252, step: 4
8635 11:41:30.543109
8636 11:41:30.546095 Set Vref, RX VrefLevel [Byte0]: 24
8637 11:41:30.549466 [Byte1]: 24
8638 11:41:30.552786
8639 11:41:30.552897 Set Vref, RX VrefLevel [Byte0]: 25
8640 11:41:30.556103 [Byte1]: 25
8641 11:41:30.560582
8642 11:41:30.560800 Set Vref, RX VrefLevel [Byte0]: 26
8643 11:41:30.563777 [Byte1]: 26
8644 11:41:30.568223
8645 11:41:30.568377 Set Vref, RX VrefLevel [Byte0]: 27
8646 11:41:30.571455 [Byte1]: 27
8647 11:41:30.576093
8648 11:41:30.576294 Set Vref, RX VrefLevel [Byte0]: 28
8649 11:41:30.579271 [Byte1]: 28
8650 11:41:30.583736
8651 11:41:30.584067 Set Vref, RX VrefLevel [Byte0]: 29
8652 11:41:30.586700 [Byte1]: 29
8653 11:41:30.591380
8654 11:41:30.591887 Set Vref, RX VrefLevel [Byte0]: 30
8655 11:41:30.594733 [Byte1]: 30
8656 11:41:30.599195
8657 11:41:30.599625 Set Vref, RX VrefLevel [Byte0]: 31
8658 11:41:30.602000 [Byte1]: 31
8659 11:41:30.606791
8660 11:41:30.607350 Set Vref, RX VrefLevel [Byte0]: 32
8661 11:41:30.612983 [Byte1]: 32
8662 11:41:30.613515
8663 11:41:30.616508 Set Vref, RX VrefLevel [Byte0]: 33
8664 11:41:30.619398 [Byte1]: 33
8665 11:41:30.619849
8666 11:41:30.622926 Set Vref, RX VrefLevel [Byte0]: 34
8667 11:41:30.625917 [Byte1]: 34
8668 11:41:30.629486
8669 11:41:30.629917 Set Vref, RX VrefLevel [Byte0]: 35
8670 11:41:30.632488 [Byte1]: 35
8671 11:41:30.637542
8672 11:41:30.638072 Set Vref, RX VrefLevel [Byte0]: 36
8673 11:41:30.640296 [Byte1]: 36
8674 11:41:30.644606
8675 11:41:30.645130 Set Vref, RX VrefLevel [Byte0]: 37
8676 11:41:30.647922 [Byte1]: 37
8677 11:41:30.652487
8678 11:41:30.653048 Set Vref, RX VrefLevel [Byte0]: 38
8679 11:41:30.655800 [Byte1]: 38
8680 11:41:30.659968
8681 11:41:30.660476 Set Vref, RX VrefLevel [Byte0]: 39
8682 11:41:30.663526 [Byte1]: 39
8683 11:41:30.667324
8684 11:41:30.667845 Set Vref, RX VrefLevel [Byte0]: 40
8685 11:41:30.670536 [Byte1]: 40
8686 11:41:30.674675
8687 11:41:30.675200 Set Vref, RX VrefLevel [Byte0]: 41
8688 11:41:30.678608 [Byte1]: 41
8689 11:41:30.682549
8690 11:41:30.683016 Set Vref, RX VrefLevel [Byte0]: 42
8691 11:41:30.685853 [Byte1]: 42
8692 11:41:30.690186
8693 11:41:30.690737 Set Vref, RX VrefLevel [Byte0]: 43
8694 11:41:30.693841 [Byte1]: 43
8695 11:41:30.698077
8696 11:41:30.698515 Set Vref, RX VrefLevel [Byte0]: 44
8697 11:41:30.701298 [Byte1]: 44
8698 11:41:30.705228
8699 11:41:30.705649 Set Vref, RX VrefLevel [Byte0]: 45
8700 11:41:30.712063 [Byte1]: 45
8701 11:41:30.712484
8702 11:41:30.715086 Set Vref, RX VrefLevel [Byte0]: 46
8703 11:41:30.718402 [Byte1]: 46
8704 11:41:30.718905
8705 11:41:30.721469 Set Vref, RX VrefLevel [Byte0]: 47
8706 11:41:30.725102 [Byte1]: 47
8707 11:41:30.728277
8708 11:41:30.728791 Set Vref, RX VrefLevel [Byte0]: 48
8709 11:41:30.731555 [Byte1]: 48
8710 11:41:30.735725
8711 11:41:30.736143 Set Vref, RX VrefLevel [Byte0]: 49
8712 11:41:30.739246 [Byte1]: 49
8713 11:41:30.743483
8714 11:41:30.743909 Set Vref, RX VrefLevel [Byte0]: 50
8715 11:41:30.746858 [Byte1]: 50
8716 11:41:30.750870
8717 11:41:30.751292 Set Vref, RX VrefLevel [Byte0]: 51
8718 11:41:30.754167 [Byte1]: 51
8719 11:41:30.758781
8720 11:41:30.759243 Set Vref, RX VrefLevel [Byte0]: 52
8721 11:41:30.762247 [Byte1]: 52
8722 11:41:30.766734
8723 11:41:30.767201 Set Vref, RX VrefLevel [Byte0]: 53
8724 11:41:30.770023 [Byte1]: 53
8725 11:41:30.773875
8726 11:41:30.774455 Set Vref, RX VrefLevel [Byte0]: 54
8727 11:41:30.777441 [Byte1]: 54
8728 11:41:30.781651
8729 11:41:30.782222 Set Vref, RX VrefLevel [Byte0]: 55
8730 11:41:30.785085 [Byte1]: 55
8731 11:41:30.789487
8732 11:41:30.789951 Set Vref, RX VrefLevel [Byte0]: 56
8733 11:41:30.792664 [Byte1]: 56
8734 11:41:30.796838
8735 11:41:30.797258 Set Vref, RX VrefLevel [Byte0]: 57
8736 11:41:30.800639 [Byte1]: 57
8737 11:41:30.804716
8738 11:41:30.805136 Set Vref, RX VrefLevel [Byte0]: 58
8739 11:41:30.811124 [Byte1]: 58
8740 11:41:30.811676
8741 11:41:30.813915 Set Vref, RX VrefLevel [Byte0]: 59
8742 11:41:30.817388 [Byte1]: 59
8743 11:41:30.817809
8744 11:41:30.821199 Set Vref, RX VrefLevel [Byte0]: 60
8745 11:41:30.824567 [Byte1]: 60
8746 11:41:30.827253
8747 11:41:30.827676 Set Vref, RX VrefLevel [Byte0]: 61
8748 11:41:30.830944 [Byte1]: 61
8749 11:41:30.834910
8750 11:41:30.835327 Set Vref, RX VrefLevel [Byte0]: 62
8751 11:41:30.838066 [Byte1]: 62
8752 11:41:30.842681
8753 11:41:30.843258 Set Vref, RX VrefLevel [Byte0]: 63
8754 11:41:30.845485 [Byte1]: 63
8755 11:41:30.850188
8756 11:41:30.850609 Set Vref, RX VrefLevel [Byte0]: 64
8757 11:41:30.853622 [Byte1]: 64
8758 11:41:30.857987
8759 11:41:30.858512 Set Vref, RX VrefLevel [Byte0]: 65
8760 11:41:30.861107 [Byte1]: 65
8761 11:41:30.865165
8762 11:41:30.865586 Set Vref, RX VrefLevel [Byte0]: 66
8763 11:41:30.868440 [Byte1]: 66
8764 11:41:30.872942
8765 11:41:30.873476 Set Vref, RX VrefLevel [Byte0]: 67
8766 11:41:30.876075 [Byte1]: 67
8767 11:41:30.880833
8768 11:41:30.881373 Set Vref, RX VrefLevel [Byte0]: 68
8769 11:41:30.883887 [Byte1]: 68
8770 11:41:30.888228
8771 11:41:30.888648 Set Vref, RX VrefLevel [Byte0]: 69
8772 11:41:30.891466 [Byte1]: 69
8773 11:41:30.895886
8774 11:41:30.896306 Set Vref, RX VrefLevel [Byte0]: 70
8775 11:41:30.899339 [Byte1]: 70
8776 11:41:30.903100
8777 11:41:30.903521 Set Vref, RX VrefLevel [Byte0]: 71
8778 11:41:30.910364 [Byte1]: 71
8779 11:41:30.910938
8780 11:41:30.912950 Set Vref, RX VrefLevel [Byte0]: 72
8781 11:41:30.916470 [Byte1]: 72
8782 11:41:30.916893
8783 11:41:30.919500 Set Vref, RX VrefLevel [Byte0]: 73
8784 11:41:30.923373 [Byte1]: 73
8785 11:41:30.926554
8786 11:41:30.927123 Final RX Vref Byte 0 = 56 to rank0
8787 11:41:30.930110 Final RX Vref Byte 1 = 56 to rank0
8788 11:41:30.933170 Final RX Vref Byte 0 = 56 to rank1
8789 11:41:30.936190 Final RX Vref Byte 1 = 56 to rank1==
8790 11:41:30.939762 Dram Type= 6, Freq= 0, CH_1, rank 0
8791 11:41:30.946504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 11:41:30.947080 ==
8793 11:41:30.947429 DQS Delay:
8794 11:41:30.947747 DQS0 = 0, DQS1 = 0
8795 11:41:30.949135 DQM Delay:
8796 11:41:30.949603 DQM0 = 131, DQM1 = 123
8797 11:41:30.952631 DQ Delay:
8798 11:41:30.956127 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8799 11:41:30.959016 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8800 11:41:30.962673 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =116
8801 11:41:30.965526 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =130
8802 11:41:30.965946
8803 11:41:30.966358
8804 11:41:30.966679
8805 11:41:30.969281 [DramC_TX_OE_Calibration] TA2
8806 11:41:30.972614 Original DQ_B0 (3 6) =30, OEN = 27
8807 11:41:30.975650 Original DQ_B1 (3 6) =30, OEN = 27
8808 11:41:30.978979 24, 0x0, End_B0=24 End_B1=24
8809 11:41:30.982045 25, 0x0, End_B0=25 End_B1=25
8810 11:41:30.982514 26, 0x0, End_B0=26 End_B1=26
8811 11:41:30.985469 27, 0x0, End_B0=27 End_B1=27
8812 11:41:30.988658 28, 0x0, End_B0=28 End_B1=28
8813 11:41:30.992020 29, 0x0, End_B0=29 End_B1=29
8814 11:41:30.992449 30, 0x0, End_B0=30 End_B1=30
8815 11:41:30.995398 31, 0x4141, End_B0=30 End_B1=30
8816 11:41:30.998640 Byte0 end_step=30 best_step=27
8817 11:41:31.002061 Byte1 end_step=30 best_step=27
8818 11:41:31.005435 Byte0 TX OE(2T, 0.5T) = (3, 3)
8819 11:41:31.008696 Byte1 TX OE(2T, 0.5T) = (3, 3)
8820 11:41:31.009115
8821 11:41:31.009466
8822 11:41:31.015149 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8823 11:41:31.018495 CH1 RK0: MR19=303, MR18=70C
8824 11:41:31.025240 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8825 11:41:31.025755
8826 11:41:31.028521 ----->DramcWriteLeveling(PI) begin...
8827 11:41:31.029078 ==
8828 11:41:31.031482 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 11:41:31.034806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 11:41:31.035273 ==
8831 11:41:31.038434 Write leveling (Byte 0): 26 => 26
8832 11:41:31.041417 Write leveling (Byte 1): 27 => 27
8833 11:41:31.045249 DramcWriteLeveling(PI) end<-----
8834 11:41:31.045773
8835 11:41:31.046219 ==
8836 11:41:31.048506 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 11:41:31.051392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 11:41:31.054902 ==
8839 11:41:31.055326 [Gating] SW mode calibration
8840 11:41:31.061460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8841 11:41:31.067988 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8842 11:41:31.071434 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 11:41:31.077851 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 11:41:31.081363 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8845 11:41:31.084387 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8846 11:41:31.091063 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 11:41:31.094273 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 11:41:31.097623 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 11:41:31.104418 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 11:41:31.107407 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 11:41:31.110884 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8852 11:41:31.117449 1 5 8 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
8853 11:41:31.120257 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8854 11:41:31.123664 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8855 11:41:31.130774 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 11:41:31.133524 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 11:41:31.136985 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 11:41:31.143633 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 11:41:31.147177 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8860 11:41:31.150130 1 6 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8861 11:41:31.156598 1 6 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
8862 11:41:31.160159 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 11:41:31.163087 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 11:41:31.170296 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 11:41:31.173299 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 11:41:31.176865 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 11:41:31.183429 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 11:41:31.186561 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8869 11:41:31.190012 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8870 11:41:31.196322 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:41:31.199248 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:41:31.203007 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 11:41:31.209474 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 11:41:31.213044 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:41:31.216216 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 11:41:31.222492 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 11:41:31.226260 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 11:41:31.229308 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 11:41:31.235915 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 11:41:31.239469 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 11:41:31.242635 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 11:41:31.248968 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 11:41:31.252354 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 11:41:31.255874 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8885 11:41:31.262300 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8886 11:41:31.265964 Total UI for P1: 0, mck2ui 16
8887 11:41:31.268742 best dqsien dly found for B0: ( 1, 9, 8)
8888 11:41:31.272311 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 11:41:31.275234 Total UI for P1: 0, mck2ui 16
8890 11:41:31.278678 best dqsien dly found for B1: ( 1, 9, 12)
8891 11:41:31.282216 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8892 11:41:31.285163 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8893 11:41:31.285615
8894 11:41:31.288660 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8895 11:41:31.294851 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8896 11:41:31.295281 [Gating] SW calibration Done
8897 11:41:31.295620 ==
8898 11:41:31.298112 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 11:41:31.304624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 11:41:31.305053 ==
8901 11:41:31.305392 RX Vref Scan: 0
8902 11:41:31.305707
8903 11:41:31.308074 RX Vref 0 -> 0, step: 1
8904 11:41:31.308651
8905 11:41:31.311171 RX Delay 0 -> 252, step: 8
8906 11:41:31.314459 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8907 11:41:31.318292 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8908 11:41:31.321005 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8909 11:41:31.327904 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8910 11:41:31.331020 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8911 11:41:31.334394 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8912 11:41:31.337779 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8913 11:41:31.340582 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8914 11:41:31.347124 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8915 11:41:31.350681 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8916 11:41:31.354063 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8917 11:41:31.357596 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8918 11:41:31.360891 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8919 11:41:31.367370 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8920 11:41:31.370874 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8921 11:41:31.373854 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8922 11:41:31.374305 ==
8923 11:41:31.377462 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 11:41:31.380344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 11:41:31.383896 ==
8926 11:41:31.384318 DQS Delay:
8927 11:41:31.384652 DQS0 = 0, DQS1 = 0
8928 11:41:31.387348 DQM Delay:
8929 11:41:31.387772 DQM0 = 132, DQM1 = 128
8930 11:41:31.390248 DQ Delay:
8931 11:41:31.393812 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8932 11:41:31.397441 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8933 11:41:31.400543 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8934 11:41:31.403364 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8935 11:41:31.403787
8936 11:41:31.404121
8937 11:41:31.404432 ==
8938 11:41:31.406529 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 11:41:31.410031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 11:41:31.413439 ==
8941 11:41:31.413974
8942 11:41:31.414325
8943 11:41:31.414639 TX Vref Scan disable
8944 11:41:31.416607 == TX Byte 0 ==
8945 11:41:31.420066 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8946 11:41:31.423192 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8947 11:41:31.426512 == TX Byte 1 ==
8948 11:41:31.429921 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8949 11:41:31.436518 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8950 11:41:31.437035 ==
8951 11:41:31.439924 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 11:41:31.443276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 11:41:31.443738 ==
8954 11:41:31.457079
8955 11:41:31.459875 TX Vref early break, caculate TX vref
8956 11:41:31.463161 TX Vref=16, minBit 0, minWin=23, winSum=384
8957 11:41:31.465923 TX Vref=18, minBit 0, minWin=23, winSum=391
8958 11:41:31.469566 TX Vref=20, minBit 0, minWin=23, winSum=401
8959 11:41:31.473291 TX Vref=22, minBit 0, minWin=24, winSum=406
8960 11:41:31.476167 TX Vref=24, minBit 0, minWin=24, winSum=420
8961 11:41:31.482688 TX Vref=26, minBit 0, minWin=25, winSum=421
8962 11:41:31.486229 TX Vref=28, minBit 0, minWin=24, winSum=423
8963 11:41:31.489399 TX Vref=30, minBit 1, minWin=25, winSum=422
8964 11:41:31.492911 TX Vref=32, minBit 1, minWin=24, winSum=413
8965 11:41:31.496089 TX Vref=34, minBit 1, minWin=23, winSum=406
8966 11:41:31.502569 TX Vref=36, minBit 1, minWin=23, winSum=394
8967 11:41:31.505429 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 30
8968 11:41:31.505860
8969 11:41:31.508689 Final TX Range 0 Vref 30
8970 11:41:31.509121
8971 11:41:31.509464 ==
8972 11:41:31.512130 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 11:41:31.515479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 11:41:31.518653 ==
8975 11:41:31.519189
8976 11:41:31.519530
8977 11:41:31.519845 TX Vref Scan disable
8978 11:41:31.525941 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8979 11:41:31.526372 == TX Byte 0 ==
8980 11:41:31.529297 u2DelayCellOfst[0]=22 cells (6 PI)
8981 11:41:31.532166 u2DelayCellOfst[1]=15 cells (4 PI)
8982 11:41:31.535353 u2DelayCellOfst[2]=0 cells (0 PI)
8983 11:41:31.538718 u2DelayCellOfst[3]=7 cells (2 PI)
8984 11:41:31.542066 u2DelayCellOfst[4]=11 cells (3 PI)
8985 11:41:31.545603 u2DelayCellOfst[5]=26 cells (7 PI)
8986 11:41:31.548703 u2DelayCellOfst[6]=22 cells (6 PI)
8987 11:41:31.552056 u2DelayCellOfst[7]=7 cells (2 PI)
8988 11:41:31.555422 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8989 11:41:31.558995 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8990 11:41:31.561832 == TX Byte 1 ==
8991 11:41:31.565383 u2DelayCellOfst[8]=0 cells (0 PI)
8992 11:41:31.569064 u2DelayCellOfst[9]=7 cells (2 PI)
8993 11:41:31.572325 u2DelayCellOfst[10]=15 cells (4 PI)
8994 11:41:31.575300 u2DelayCellOfst[11]=7 cells (2 PI)
8995 11:41:31.578971 u2DelayCellOfst[12]=18 cells (5 PI)
8996 11:41:31.582416 u2DelayCellOfst[13]=18 cells (5 PI)
8997 11:41:31.583041 u2DelayCellOfst[14]=22 cells (6 PI)
8998 11:41:31.585124 u2DelayCellOfst[15]=22 cells (6 PI)
8999 11:41:31.591546 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9000 11:41:31.595273 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9001 11:41:31.598341 DramC Write-DBI on
9002 11:41:31.598953 ==
9003 11:41:31.601802 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 11:41:31.605420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 11:41:31.605996 ==
9006 11:41:31.606373
9007 11:41:31.606718
9008 11:41:31.608069 TX Vref Scan disable
9009 11:41:31.608555 == TX Byte 0 ==
9010 11:41:31.614630 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9011 11:41:31.615149 == TX Byte 1 ==
9012 11:41:31.618113 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9013 11:41:31.621362 DramC Write-DBI off
9014 11:41:31.621827
9015 11:41:31.622193 [DATLAT]
9016 11:41:31.624578 Freq=1600, CH1 RK1
9017 11:41:31.625071
9018 11:41:31.625444 DATLAT Default: 0xf
9019 11:41:31.627972 0, 0xFFFF, sum = 0
9020 11:41:31.631215 1, 0xFFFF, sum = 0
9021 11:41:31.631654 2, 0xFFFF, sum = 0
9022 11:41:31.634757 3, 0xFFFF, sum = 0
9023 11:41:31.635219 4, 0xFFFF, sum = 0
9024 11:41:31.638213 5, 0xFFFF, sum = 0
9025 11:41:31.638647 6, 0xFFFF, sum = 0
9026 11:41:31.641000 7, 0xFFFF, sum = 0
9027 11:41:31.641449 8, 0xFFFF, sum = 0
9028 11:41:31.644085 9, 0xFFFF, sum = 0
9029 11:41:31.644515 10, 0xFFFF, sum = 0
9030 11:41:31.647511 11, 0xFFFF, sum = 0
9031 11:41:31.648063 12, 0xFFFF, sum = 0
9032 11:41:31.650933 13, 0x8FFF, sum = 0
9033 11:41:31.651362 14, 0x0, sum = 1
9034 11:41:31.654237 15, 0x0, sum = 2
9035 11:41:31.654667 16, 0x0, sum = 3
9036 11:41:31.657424 17, 0x0, sum = 4
9037 11:41:31.657917 best_step = 15
9038 11:41:31.658251
9039 11:41:31.658564 ==
9040 11:41:31.660699 Dram Type= 6, Freq= 0, CH_1, rank 1
9041 11:41:31.667211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9042 11:41:31.667634 ==
9043 11:41:31.668056 RX Vref Scan: 0
9044 11:41:31.668375
9045 11:41:31.670528 RX Vref 0 -> 0, step: 1
9046 11:41:31.670974
9047 11:41:31.674578 RX Delay 11 -> 252, step: 4
9048 11:41:31.677306 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9049 11:41:31.680369 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9050 11:41:31.683983 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9051 11:41:31.690479 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9052 11:41:31.693827 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9053 11:41:31.697445 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9054 11:41:31.700136 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9055 11:41:31.706812 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9056 11:41:31.710343 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9057 11:41:31.713193 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9058 11:41:31.716687 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9059 11:41:31.720066 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9060 11:41:31.726749 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9061 11:41:31.729856 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9062 11:41:31.733021 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9063 11:41:31.736516 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9064 11:41:31.736993 ==
9065 11:41:31.739697 Dram Type= 6, Freq= 0, CH_1, rank 1
9066 11:41:31.746452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9067 11:41:31.747079 ==
9068 11:41:31.747469 DQS Delay:
9069 11:41:31.749616 DQS0 = 0, DQS1 = 0
9070 11:41:31.750094 DQM Delay:
9071 11:41:31.752916 DQM0 = 130, DQM1 = 125
9072 11:41:31.753391 DQ Delay:
9073 11:41:31.756363 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
9074 11:41:31.759058 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =128
9075 11:41:31.762422 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9076 11:41:31.766265 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9077 11:41:31.766739
9078 11:41:31.767160
9079 11:41:31.767509
9080 11:41:31.769107 [DramC_TX_OE_Calibration] TA2
9081 11:41:31.772648 Original DQ_B0 (3 6) =30, OEN = 27
9082 11:41:31.776083 Original DQ_B1 (3 6) =30, OEN = 27
9083 11:41:31.779079 24, 0x0, End_B0=24 End_B1=24
9084 11:41:31.782435 25, 0x0, End_B0=25 End_B1=25
9085 11:41:31.782978 26, 0x0, End_B0=26 End_B1=26
9086 11:41:31.785902 27, 0x0, End_B0=27 End_B1=27
9087 11:41:31.789380 28, 0x0, End_B0=28 End_B1=28
9088 11:41:31.792240 29, 0x0, End_B0=29 End_B1=29
9089 11:41:31.795800 30, 0x0, End_B0=30 End_B1=30
9090 11:41:31.796239 31, 0x4141, End_B0=30 End_B1=30
9091 11:41:31.798594 Byte0 end_step=30 best_step=27
9092 11:41:31.802154 Byte1 end_step=30 best_step=27
9093 11:41:31.805804 Byte0 TX OE(2T, 0.5T) = (3, 3)
9094 11:41:31.808691 Byte1 TX OE(2T, 0.5T) = (3, 3)
9095 11:41:31.809120
9096 11:41:31.809457
9097 11:41:31.815532 [DQSOSCAuto] RK1, (LSB)MR18= 0xd19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 403 ps
9098 11:41:31.818400 CH1 RK1: MR19=303, MR18=D19
9099 11:41:31.824853 CH1_RK1: MR19=0x303, MR18=0xD19, DQSOSC=397, MR23=63, INC=23, DEC=15
9100 11:41:31.828170 [RxdqsGatingPostProcess] freq 1600
9101 11:41:31.835069 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9102 11:41:31.838703 best DQS0 dly(2T, 0.5T) = (1, 1)
9103 11:41:31.839377 best DQS1 dly(2T, 0.5T) = (1, 1)
9104 11:41:31.841736 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9105 11:41:31.845168 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9106 11:41:31.848419 best DQS0 dly(2T, 0.5T) = (1, 1)
9107 11:41:31.851209 best DQS1 dly(2T, 0.5T) = (1, 1)
9108 11:41:31.854536 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9109 11:41:31.857781 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9110 11:41:31.861573 Pre-setting of DQS Precalculation
9111 11:41:31.867510 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9112 11:41:31.874208 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9113 11:41:31.881442 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9114 11:41:31.882028
9115 11:41:31.882411
9116 11:41:31.884197 [Calibration Summary] 3200 Mbps
9117 11:41:31.884767 CH 0, Rank 0
9118 11:41:31.887571 SW Impedance : PASS
9119 11:41:31.890586 DUTY Scan : NO K
9120 11:41:31.891101 ZQ Calibration : PASS
9121 11:41:31.893922 Jitter Meter : NO K
9122 11:41:31.897442 CBT Training : PASS
9123 11:41:31.897912 Write leveling : PASS
9124 11:41:31.900311 RX DQS gating : PASS
9125 11:41:31.903984 RX DQ/DQS(RDDQC) : PASS
9126 11:41:31.904549 TX DQ/DQS : PASS
9127 11:41:31.906894 RX DATLAT : PASS
9128 11:41:31.910356 RX DQ/DQS(Engine): PASS
9129 11:41:31.910825 TX OE : PASS
9130 11:41:31.911243 All Pass.
9131 11:41:31.913742
9132 11:41:31.914260 CH 0, Rank 1
9133 11:41:31.916761 SW Impedance : PASS
9134 11:41:31.917231 DUTY Scan : NO K
9135 11:41:31.920642 ZQ Calibration : PASS
9136 11:41:31.923348 Jitter Meter : NO K
9137 11:41:31.923820 CBT Training : PASS
9138 11:41:31.926941 Write leveling : PASS
9139 11:41:31.927413 RX DQS gating : PASS
9140 11:41:31.929841 RX DQ/DQS(RDDQC) : PASS
9141 11:41:31.933362 TX DQ/DQS : PASS
9142 11:41:31.933948 RX DATLAT : PASS
9143 11:41:31.936519 RX DQ/DQS(Engine): PASS
9144 11:41:31.939958 TX OE : PASS
9145 11:41:31.940438 All Pass.
9146 11:41:31.940871
9147 11:41:31.941218 CH 1, Rank 0
9148 11:41:31.943134 SW Impedance : PASS
9149 11:41:31.946315 DUTY Scan : NO K
9150 11:41:31.946780 ZQ Calibration : PASS
9151 11:41:31.949877 Jitter Meter : NO K
9152 11:41:31.953017 CBT Training : PASS
9153 11:41:31.953536 Write leveling : PASS
9154 11:41:31.956169 RX DQS gating : PASS
9155 11:41:31.959599 RX DQ/DQS(RDDQC) : PASS
9156 11:41:31.960063 TX DQ/DQS : PASS
9157 11:41:31.962932 RX DATLAT : PASS
9158 11:41:31.966375 RX DQ/DQS(Engine): PASS
9159 11:41:31.966816 TX OE : PASS
9160 11:41:31.969438 All Pass.
9161 11:41:31.969866
9162 11:41:31.970205 CH 1, Rank 1
9163 11:41:31.972937 SW Impedance : PASS
9164 11:41:31.973481 DUTY Scan : NO K
9165 11:41:31.976097 ZQ Calibration : PASS
9166 11:41:31.979452 Jitter Meter : NO K
9167 11:41:31.979926 CBT Training : PASS
9168 11:41:31.982676 Write leveling : PASS
9169 11:41:31.985656 RX DQS gating : PASS
9170 11:41:31.986131 RX DQ/DQS(RDDQC) : PASS
9171 11:41:31.989271 TX DQ/DQS : PASS
9172 11:41:31.992814 RX DATLAT : PASS
9173 11:41:31.993287 RX DQ/DQS(Engine): PASS
9174 11:41:31.995712 TX OE : PASS
9175 11:41:31.996145 All Pass.
9176 11:41:31.996486
9177 11:41:31.999329 DramC Write-DBI on
9178 11:41:32.002489 PER_BANK_REFRESH: Hybrid Mode
9179 11:41:32.002950 TX_TRACKING: ON
9180 11:41:32.012690 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9181 11:41:32.018947 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9182 11:41:32.025459 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9183 11:41:32.029271 [FAST_K] Save calibration result to emmc
9184 11:41:32.032031 sync common calibartion params.
9185 11:41:32.035393 sync cbt_mode0:1, 1:1
9186 11:41:32.038955 dram_init: ddr_geometry: 2
9187 11:41:32.039529 dram_init: ddr_geometry: 2
9188 11:41:32.041721 dram_init: ddr_geometry: 2
9189 11:41:32.045034 0:dram_rank_size:100000000
9190 11:41:32.048690 1:dram_rank_size:100000000
9191 11:41:32.052531 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9192 11:41:32.055194 DFS_SHUFFLE_HW_MODE: ON
9193 11:41:32.058466 dramc_set_vcore_voltage set vcore to 725000
9194 11:41:32.061554 Read voltage for 1600, 0
9195 11:41:32.062049 Vio18 = 0
9196 11:41:32.065021 Vcore = 725000
9197 11:41:32.065492 Vdram = 0
9198 11:41:32.065860 Vddq = 0
9199 11:41:32.066206 Vmddr = 0
9200 11:41:32.068451 switch to 3200 Mbps bootup
9201 11:41:32.071735 [DramcRunTimeConfig]
9202 11:41:32.072329 PHYPLL
9203 11:41:32.074505 DPM_CONTROL_AFTERK: ON
9204 11:41:32.075150 PER_BANK_REFRESH: ON
9205 11:41:32.077901 REFRESH_OVERHEAD_REDUCTION: ON
9206 11:41:32.081321 CMD_PICG_NEW_MODE: OFF
9207 11:41:32.081787 XRTWTW_NEW_MODE: ON
9208 11:41:32.084376 XRTRTR_NEW_MODE: ON
9209 11:41:32.084895 TX_TRACKING: ON
9210 11:41:32.087641 RDSEL_TRACKING: OFF
9211 11:41:32.090980 DQS Precalculation for DVFS: ON
9212 11:41:32.091446 RX_TRACKING: OFF
9213 11:41:32.094761 HW_GATING DBG: ON
9214 11:41:32.095359 ZQCS_ENABLE_LP4: ON
9215 11:41:32.097657 RX_PICG_NEW_MODE: ON
9216 11:41:32.098076 TX_PICG_NEW_MODE: ON
9217 11:41:32.101223 ENABLE_RX_DCM_DPHY: ON
9218 11:41:32.104932 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9219 11:41:32.107353 DUMMY_READ_FOR_TRACKING: OFF
9220 11:41:32.107811 !!! SPM_CONTROL_AFTERK: OFF
9221 11:41:32.110881 !!! SPM could not control APHY
9222 11:41:32.113885 IMPEDANCE_TRACKING: ON
9223 11:41:32.114315 TEMP_SENSOR: ON
9224 11:41:32.117474 HW_SAVE_FOR_SR: OFF
9225 11:41:32.121027 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9226 11:41:32.124203 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9227 11:41:32.124741 Read ODT Tracking: ON
9228 11:41:32.127502 Refresh Rate DeBounce: ON
9229 11:41:32.130763 DFS_NO_QUEUE_FLUSH: ON
9230 11:41:32.134314 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9231 11:41:32.137361 ENABLE_DFS_RUNTIME_MRW: OFF
9232 11:41:32.137893 DDR_RESERVE_NEW_MODE: ON
9233 11:41:32.140591 MR_CBT_SWITCH_FREQ: ON
9234 11:41:32.141017 =========================
9235 11:41:32.161060 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9236 11:41:32.163909 dram_init: ddr_geometry: 2
9237 11:41:32.182498 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9238 11:41:32.185429 dram_init: dram init end (result: 0)
9239 11:41:32.192454 DRAM-K: Full calibration passed in 24589 msecs
9240 11:41:32.195591 MRC: failed to locate region type 0.
9241 11:41:32.196178 DRAM rank0 size:0x100000000,
9242 11:41:32.199117 DRAM rank1 size=0x100000000
9243 11:41:32.208727 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9244 11:41:32.215733 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9245 11:41:32.221958 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9246 11:41:32.231878 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9247 11:41:32.232486 DRAM rank0 size:0x100000000,
9248 11:41:32.234801 DRAM rank1 size=0x100000000
9249 11:41:32.235251 CBMEM:
9250 11:41:32.238392 IMD: root @ 0xfffff000 254 entries.
9251 11:41:32.242006 IMD: root @ 0xffffec00 62 entries.
9252 11:41:32.244884 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9253 11:41:32.251946 WARNING: RO_VPD is uninitialized or empty.
9254 11:41:32.255125 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9255 11:41:32.262402 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9256 11:41:32.275261 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9257 11:41:32.286974 BS: romstage times (exec / console): total (unknown) / 24050 ms
9258 11:41:32.287408
9259 11:41:32.287746
9260 11:41:32.296310 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9261 11:41:32.299865 ARM64: Exception handlers installed.
9262 11:41:32.303068 ARM64: Testing exception
9263 11:41:32.306529 ARM64: Done test exception
9264 11:41:32.307077 Enumerating buses...
9265 11:41:32.309276 Show all devs... Before device enumeration.
9266 11:41:32.312767 Root Device: enabled 1
9267 11:41:32.316534 CPU_CLUSTER: 0: enabled 1
9268 11:41:32.317025 CPU: 00: enabled 1
9269 11:41:32.319717 Compare with tree...
9270 11:41:32.320138 Root Device: enabled 1
9271 11:41:32.322619 CPU_CLUSTER: 0: enabled 1
9272 11:41:32.325919 CPU: 00: enabled 1
9273 11:41:32.326374 Root Device scanning...
9274 11:41:32.329534 scan_static_bus for Root Device
9275 11:41:32.333065 CPU_CLUSTER: 0 enabled
9276 11:41:32.335884 scan_static_bus for Root Device done
9277 11:41:32.339286 scan_bus: bus Root Device finished in 8 msecs
9278 11:41:32.339751 done
9279 11:41:32.345931 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9280 11:41:32.349053 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9281 11:41:32.355839 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9282 11:41:32.362125 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9283 11:41:32.362895 Allocating resources...
9284 11:41:32.365641 Reading resources...
9285 11:41:32.369120 Root Device read_resources bus 0 link: 0
9286 11:41:32.372084 DRAM rank0 size:0x100000000,
9287 11:41:32.372644 DRAM rank1 size=0x100000000
9288 11:41:32.378891 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9289 11:41:32.379352 CPU: 00 missing read_resources
9290 11:41:32.385186 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9291 11:41:32.388528 Root Device read_resources bus 0 link: 0 done
9292 11:41:32.392007 Done reading resources.
9293 11:41:32.394943 Show resources in subtree (Root Device)...After reading.
9294 11:41:32.398379 Root Device child on link 0 CPU_CLUSTER: 0
9295 11:41:32.401463 CPU_CLUSTER: 0 child on link 0 CPU: 00
9296 11:41:32.411490 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9297 11:41:32.412038 CPU: 00
9298 11:41:32.418750 Root Device assign_resources, bus 0 link: 0
9299 11:41:32.421613 CPU_CLUSTER: 0 missing set_resources
9300 11:41:32.424949 Root Device assign_resources, bus 0 link: 0 done
9301 11:41:32.428244 Done setting resources.
9302 11:41:32.431127 Show resources in subtree (Root Device)...After assigning values.
9303 11:41:32.434540 Root Device child on link 0 CPU_CLUSTER: 0
9304 11:41:32.440997 CPU_CLUSTER: 0 child on link 0 CPU: 00
9305 11:41:32.447518 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9306 11:41:32.451027 CPU: 00
9307 11:41:32.451462 Done allocating resources.
9308 11:41:32.457499 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9309 11:41:32.457983 Enabling resources...
9310 11:41:32.461001 done.
9311 11:41:32.464060 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9312 11:41:32.467554 Initializing devices...
9313 11:41:32.467984 Root Device init
9314 11:41:32.471189 init hardware done!
9315 11:41:32.471657 0x00000018: ctrlr->caps
9316 11:41:32.474041 52.000 MHz: ctrlr->f_max
9317 11:41:32.477402 0.400 MHz: ctrlr->f_min
9318 11:41:32.480648 0x40ff8080: ctrlr->voltages
9319 11:41:32.481326 sclk: 390625
9320 11:41:32.481918 Bus Width = 1
9321 11:41:32.483887 sclk: 390625
9322 11:41:32.484455 Bus Width = 1
9323 11:41:32.487885 Early init status = 3
9324 11:41:32.490575 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9325 11:41:32.494060 in-header: 03 fc 00 00 01 00 00 00
9326 11:41:32.497390 in-data: 00
9327 11:41:32.500845 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9328 11:41:32.505487 in-header: 03 fd 00 00 00 00 00 00
9329 11:41:32.508505 in-data:
9330 11:41:32.512208 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9331 11:41:32.516082 in-header: 03 fc 00 00 01 00 00 00
9332 11:41:32.519067 in-data: 00
9333 11:41:32.522655 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9334 11:41:32.527865 in-header: 03 fd 00 00 00 00 00 00
9335 11:41:32.530789 in-data:
9336 11:41:32.534123 [SSUSB] Setting up USB HOST controller...
9337 11:41:32.537977 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9338 11:41:32.541200 [SSUSB] phy power-on done.
9339 11:41:32.544076 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9340 11:41:32.551335 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9341 11:41:32.554466 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9342 11:41:32.561035 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9343 11:41:32.567600 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9344 11:41:32.574055 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9345 11:41:32.580548 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9346 11:41:32.587170 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9347 11:41:32.590505 SPM: binary array size = 0x9dc
9348 11:41:32.593705 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9349 11:41:32.600037 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9350 11:41:32.606924 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9351 11:41:32.613672 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9352 11:41:32.616362 configure_display: Starting display init
9353 11:41:32.651381 anx7625_power_on_init: Init interface.
9354 11:41:32.654050 anx7625_disable_pd_protocol: Disabled PD feature.
9355 11:41:32.657496 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9356 11:41:32.685508 anx7625_start_dp_work: Secure OCM version=00
9357 11:41:32.688376 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9358 11:41:32.703758 sp_tx_get_edid_block: EDID Block = 1
9359 11:41:32.806211 Extracted contents:
9360 11:41:32.808984 header: 00 ff ff ff ff ff ff 00
9361 11:41:32.812217 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9362 11:41:32.816112 version: 01 04
9363 11:41:32.818902 basic params: 95 1f 11 78 0a
9364 11:41:32.822222 chroma info: 76 90 94 55 54 90 27 21 50 54
9365 11:41:32.825692 established: 00 00 00
9366 11:41:32.832227 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9367 11:41:32.838665 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9368 11:41:32.842269 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 11:41:32.848954 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9370 11:41:32.855139 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9371 11:41:32.858776 extensions: 00
9372 11:41:32.859300 checksum: fb
9373 11:41:32.859633
9374 11:41:32.865079 Manufacturer: IVO Model 57d Serial Number 0
9375 11:41:32.865495 Made week 0 of 2020
9376 11:41:32.868757 EDID version: 1.4
9377 11:41:32.869172 Digital display
9378 11:41:32.871715 6 bits per primary color channel
9379 11:41:32.875177 DisplayPort interface
9380 11:41:32.875590 Maximum image size: 31 cm x 17 cm
9381 11:41:32.878091 Gamma: 220%
9382 11:41:32.878504 Check DPMS levels
9383 11:41:32.885100 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9384 11:41:32.888159 First detailed timing is preferred timing
9385 11:41:32.891336 Established timings supported:
9386 11:41:32.891752 Standard timings supported:
9387 11:41:32.894470 Detailed timings
9388 11:41:32.898016 Hex of detail: 383680a07038204018303c0035ae10000019
9389 11:41:32.904446 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9390 11:41:32.907808 0780 0798 07c8 0820 hborder 0
9391 11:41:32.911174 0438 043b 0447 0458 vborder 0
9392 11:41:32.914501 -hsync -vsync
9393 11:41:32.915068 Did detailed timing
9394 11:41:32.920893 Hex of detail: 000000000000000000000000000000000000
9395 11:41:32.924204 Manufacturer-specified data, tag 0
9396 11:41:32.927643 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9397 11:41:32.930825 ASCII string: InfoVision
9398 11:41:32.934289 Hex of detail: 000000fe00523134304e574635205248200a
9399 11:41:32.937526 ASCII string: R140NWF5 RH
9400 11:41:32.937936 Checksum
9401 11:41:32.940977 Checksum: 0xfb (valid)
9402 11:41:32.944204 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9403 11:41:32.947389 DSI data_rate: 832800000 bps
9404 11:41:32.953758 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9405 11:41:32.957115 anx7625_parse_edid: pixelclock(138800).
9406 11:41:32.960372 hactive(1920), hsync(48), hfp(24), hbp(88)
9407 11:41:32.963906 vactive(1080), vsync(12), vfp(3), vbp(17)
9408 11:41:32.967028 anx7625_dsi_config: config dsi.
9409 11:41:32.973921 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9410 11:41:32.987543 anx7625_dsi_config: success to config DSI
9411 11:41:32.991125 anx7625_dp_start: MIPI phy setup OK.
9412 11:41:32.994107 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9413 11:41:32.997608 mtk_ddp_mode_set invalid vrefresh 60
9414 11:41:33.000447 main_disp_path_setup
9415 11:41:33.000529 ovl_layer_smi_id_en
9416 11:41:33.004387 ovl_layer_smi_id_en
9417 11:41:33.004469 ccorr_config
9418 11:41:33.004535 aal_config
9419 11:41:33.007036 gamma_config
9420 11:41:33.007144 postmask_config
9421 11:41:33.010810 dither_config
9422 11:41:33.013654 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9423 11:41:33.020239 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9424 11:41:33.023690 Root Device init finished in 552 msecs
9425 11:41:33.026796 CPU_CLUSTER: 0 init
9426 11:41:33.033562 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9427 11:41:33.039997 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9428 11:41:33.040080 APU_MBOX 0x190000b0 = 0x10001
9429 11:41:33.043212 APU_MBOX 0x190001b0 = 0x10001
9430 11:41:33.046571 APU_MBOX 0x190005b0 = 0x10001
9431 11:41:33.050036 APU_MBOX 0x190006b0 = 0x10001
9432 11:41:33.056677 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9433 11:41:33.066912 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9434 11:41:33.079242 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9435 11:41:33.085649 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9436 11:41:33.097207 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9437 11:41:33.106575 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9438 11:41:33.109464 CPU_CLUSTER: 0 init finished in 81 msecs
9439 11:41:33.113436 Devices initialized
9440 11:41:33.116423 Show all devs... After init.
9441 11:41:33.116518 Root Device: enabled 1
9442 11:41:33.119586 CPU_CLUSTER: 0: enabled 1
9443 11:41:33.123049 CPU: 00: enabled 1
9444 11:41:33.126424 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9445 11:41:33.129710 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9446 11:41:33.133286 ELOG: NV offset 0x57f000 size 0x1000
9447 11:41:33.139830 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9448 11:41:33.146260 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9449 11:41:33.149479 ELOG: Event(17) added with size 13 at 2023-06-15 11:41:33 UTC
9450 11:41:33.156410 out: cmd=0x121: 03 db 21 01 00 00 00 00
9451 11:41:33.159684 in-header: 03 47 00 00 2c 00 00 00
9452 11:41:33.169282 in-data: 17 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9453 11:41:33.176312 ELOG: Event(A1) added with size 10 at 2023-06-15 11:41:33 UTC
9454 11:41:33.182779 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9455 11:41:33.189070 ELOG: Event(A0) added with size 9 at 2023-06-15 11:41:33 UTC
9456 11:41:33.192526 elog_add_boot_reason: Logged dev mode boot
9457 11:41:33.199262 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9458 11:41:33.199691 Finalize devices...
9459 11:41:33.202545 Devices finalized
9460 11:41:33.205553 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9461 11:41:33.208966 Writing coreboot table at 0xffe64000
9462 11:41:33.212552 0. 000000000010a000-0000000000113fff: RAMSTAGE
9463 11:41:33.218746 1. 0000000040000000-00000000400fffff: RAM
9464 11:41:33.222257 2. 0000000040100000-000000004032afff: RAMSTAGE
9465 11:41:33.225377 3. 000000004032b000-00000000545fffff: RAM
9466 11:41:33.228619 4. 0000000054600000-000000005465ffff: BL31
9467 11:41:33.232056 5. 0000000054660000-00000000ffe63fff: RAM
9468 11:41:33.238328 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9469 11:41:33.241652 7. 0000000100000000-000000023fffffff: RAM
9470 11:41:33.244907 Passing 5 GPIOs to payload:
9471 11:41:33.248427 NAME | PORT | POLARITY | VALUE
9472 11:41:33.255052 EC in RW | 0x000000aa | low | undefined
9473 11:41:33.258377 EC interrupt | 0x00000005 | low | undefined
9474 11:41:33.264878 TPM interrupt | 0x000000ab | high | undefined
9475 11:41:33.268320 SD card detect | 0x00000011 | high | undefined
9476 11:41:33.271350 speaker enable | 0x00000093 | high | undefined
9477 11:41:33.274759 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9478 11:41:33.278389 in-header: 03 f9 00 00 02 00 00 00
9479 11:41:33.281897 in-data: 02 00
9480 11:41:33.284865 ADC[4]: Raw value=896300 ID=7
9481 11:41:33.288329 ADC[3]: Raw value=213070 ID=1
9482 11:41:33.288753 RAM Code: 0x71
9483 11:41:33.291287 ADC[6]: Raw value=75092 ID=0
9484 11:41:33.294723 ADC[5]: Raw value=212700 ID=1
9485 11:41:33.295214 SKU Code: 0x1
9486 11:41:33.301257 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9487 11:41:33.301696 coreboot table: 964 bytes.
9488 11:41:33.304665 IMD ROOT 0. 0xfffff000 0x00001000
9489 11:41:33.308184 IMD SMALL 1. 0xffffe000 0x00001000
9490 11:41:33.311063 RO MCACHE 2. 0xffffc000 0x00001104
9491 11:41:33.314505 CONSOLE 3. 0xfff7c000 0x00080000
9492 11:41:33.317506 FMAP 4. 0xfff7b000 0x00000452
9493 11:41:33.320976 TIME STAMP 5. 0xfff7a000 0x00000910
9494 11:41:33.324228 VBOOT WORK 6. 0xfff66000 0x00014000
9495 11:41:33.327537 RAMOOPS 7. 0xffe66000 0x00100000
9496 11:41:33.330948 COREBOOT 8. 0xffe64000 0x00002000
9497 11:41:33.333927 IMD small region:
9498 11:41:33.337426 IMD ROOT 0. 0xffffec00 0x00000400
9499 11:41:33.340578 VPD 1. 0xffffeba0 0x0000004c
9500 11:41:33.343947 MMC STATUS 2. 0xffffeb80 0x00000004
9501 11:41:33.350691 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9502 11:41:33.351201 Probing TPM: done!
9503 11:41:33.357405 Connected to device vid:did:rid of 1ae0:0028:00
9504 11:41:33.364778 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9505 11:41:33.367510 Initialized TPM device CR50 revision 0
9506 11:41:33.370624 Checking cr50 for pending updates
9507 11:41:33.376509 Reading cr50 TPM mode
9508 11:41:33.385091 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9509 11:41:33.391831 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9510 11:41:33.431351 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9511 11:41:33.434982 Checking segment from ROM address 0x40100000
9512 11:41:33.438766 Checking segment from ROM address 0x4010001c
9513 11:41:33.444793 Loading segment from ROM address 0x40100000
9514 11:41:33.445290 code (compression=0)
9515 11:41:33.454682 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9516 11:41:33.461357 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9517 11:41:33.461793 it's not compressed!
9518 11:41:33.468548 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9519 11:41:33.474435 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9520 11:41:33.492102 Loading segment from ROM address 0x4010001c
9521 11:41:33.492703 Entry Point 0x80000000
9522 11:41:33.495370 Loaded segments
9523 11:41:33.498870 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9524 11:41:33.505349 Jumping to boot code at 0x80000000(0xffe64000)
9525 11:41:33.512067 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9526 11:41:33.518289 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9527 11:41:33.526539 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9528 11:41:33.529487 Checking segment from ROM address 0x40100000
9529 11:41:33.533165 Checking segment from ROM address 0x4010001c
9530 11:41:33.539658 Loading segment from ROM address 0x40100000
9531 11:41:33.540129 code (compression=1)
9532 11:41:33.546230 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9533 11:41:33.555722 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9534 11:41:33.556213 using LZMA
9535 11:41:33.565032 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9536 11:41:33.571928 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9537 11:41:33.575360 Loading segment from ROM address 0x4010001c
9538 11:41:33.575926 Entry Point 0x54601000
9539 11:41:33.578304 Loaded segments
9540 11:41:33.581542 NOTICE: MT8192 bl31_setup
9541 11:41:33.588535 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9542 11:41:33.591783 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9543 11:41:33.595244 WARNING: region 0:
9544 11:41:33.598542 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 11:41:33.599048 WARNING: region 1:
9546 11:41:33.605147 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9547 11:41:33.608497 WARNING: region 2:
9548 11:41:33.612172 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9549 11:41:33.615056 WARNING: region 3:
9550 11:41:33.618280 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9551 11:41:33.621717 WARNING: region 4:
9552 11:41:33.628228 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9553 11:41:33.628312 WARNING: region 5:
9554 11:41:33.630734 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9555 11:41:33.634183 WARNING: region 6:
9556 11:41:33.637710 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9557 11:41:33.641268 WARNING: region 7:
9558 11:41:33.644477 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9559 11:41:33.650673 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9560 11:41:33.653941 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9561 11:41:33.660530 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9562 11:41:33.664153 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9563 11:41:33.667556 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9564 11:41:33.674577 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9565 11:41:33.677702 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9566 11:41:33.681131 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9567 11:41:33.687481 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9568 11:41:33.690721 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9569 11:41:33.694328 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9570 11:41:33.701254 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9571 11:41:33.704661 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9572 11:41:33.711633 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9573 11:41:33.714558 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9574 11:41:33.717839 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9575 11:41:33.724548 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9576 11:41:33.727296 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9577 11:41:33.734522 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9578 11:41:33.737472 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9579 11:41:33.740893 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9580 11:41:33.747291 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9581 11:41:33.750263 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9582 11:41:33.757460 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9583 11:41:33.760426 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9584 11:41:33.763974 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9585 11:41:33.770670 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9586 11:41:33.773480 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9587 11:41:33.780135 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9588 11:41:33.783234 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9589 11:41:33.786709 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9590 11:41:33.793058 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9591 11:41:33.796812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9592 11:41:33.800157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9593 11:41:33.806364 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9594 11:41:33.809858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9595 11:41:33.813166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9596 11:41:33.816757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9597 11:41:33.823378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9598 11:41:33.826302 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9599 11:41:33.829915 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9600 11:41:33.833556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9601 11:41:33.839756 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9602 11:41:33.843270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9603 11:41:33.846091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9604 11:41:33.849633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9605 11:41:33.855967 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9606 11:41:33.859766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9607 11:41:33.862956 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9608 11:41:33.869388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9609 11:41:33.872918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9610 11:41:33.879430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9611 11:41:33.882569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9612 11:41:33.889155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9613 11:41:33.892573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9614 11:41:33.895923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9615 11:41:33.902822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9616 11:41:33.906016 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9617 11:41:33.912622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9618 11:41:33.915404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9619 11:41:33.922359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9620 11:41:33.925335 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9621 11:41:33.932380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9622 11:41:33.935368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9623 11:41:33.941890 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9624 11:41:33.945046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9625 11:41:33.948677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9626 11:41:33.955242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9627 11:41:33.958600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9628 11:41:33.965220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9629 11:41:33.968654 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9630 11:41:33.975441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9631 11:41:33.978139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9632 11:41:33.984834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9633 11:41:33.987790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9634 11:41:33.991814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9635 11:41:33.997781 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9636 11:41:34.001829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9637 11:41:34.008147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9638 11:41:34.010947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9639 11:41:34.017629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9640 11:41:34.021260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9641 11:41:34.027686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9642 11:41:34.031186 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9643 11:41:34.034084 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9644 11:41:34.041027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9645 11:41:34.044427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9646 11:41:34.051009 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9647 11:41:34.054426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9648 11:41:34.060767 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9649 11:41:34.063767 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9650 11:41:34.070943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9651 11:41:34.074243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9652 11:41:34.080847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9653 11:41:34.084002 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9654 11:41:34.086982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9655 11:41:34.093792 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9656 11:41:34.097257 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9657 11:41:34.100563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9658 11:41:34.103430 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9659 11:41:34.110468 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9660 11:41:34.113547 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9661 11:41:34.120486 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9662 11:41:34.123522 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9663 11:41:34.126969 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9664 11:41:34.133586 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9665 11:41:34.136738 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9666 11:41:34.143127 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9667 11:41:34.146294 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9668 11:41:34.149906 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9669 11:41:34.156778 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9670 11:41:34.159705 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9671 11:41:34.166634 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9672 11:41:34.169572 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9673 11:41:34.173125 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9674 11:41:34.179838 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9675 11:41:34.183275 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9676 11:41:34.186595 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9677 11:41:34.193109 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9678 11:41:34.196438 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9679 11:41:34.199807 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9680 11:41:34.203174 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9681 11:41:34.209826 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9682 11:41:34.212604 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9683 11:41:34.215951 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9684 11:41:34.222658 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9685 11:41:34.225920 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9686 11:41:34.232606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9687 11:41:34.236322 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9688 11:41:34.239523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9689 11:41:34.245866 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9690 11:41:34.248835 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9691 11:41:34.255797 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9692 11:41:34.259243 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9693 11:41:34.262170 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9694 11:41:34.269181 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9695 11:41:34.272676 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9696 11:41:34.279040 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9697 11:41:34.282381 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9698 11:41:34.285516 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9699 11:41:34.292437 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9700 11:41:34.295223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9701 11:41:34.301964 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9702 11:41:34.305199 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9703 11:41:34.308390 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9704 11:41:34.315199 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9705 11:41:34.318614 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9706 11:41:34.325274 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9707 11:41:34.328664 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9708 11:41:34.331465 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9709 11:41:34.338401 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9710 11:41:34.341701 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9711 11:41:34.348070 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9712 11:41:34.351577 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9713 11:41:34.354709 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9714 11:41:34.361853 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9715 11:41:34.364621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9716 11:41:34.371490 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9717 11:41:34.374361 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9718 11:41:34.377874 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9719 11:41:34.384444 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9720 11:41:34.387843 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9721 11:41:34.394680 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9722 11:41:34.398130 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9723 11:41:34.400778 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9724 11:41:34.407348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9725 11:41:34.410446 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9726 11:41:34.417137 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9727 11:41:34.420525 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9728 11:41:34.424111 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9729 11:41:34.430549 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9730 11:41:34.433648 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9731 11:41:34.440180 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9732 11:41:34.443448 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9733 11:41:34.447123 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9734 11:41:34.453335 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9735 11:41:34.456931 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9736 11:41:34.463314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9737 11:41:34.467071 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9738 11:41:34.469962 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9739 11:41:34.476844 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9740 11:41:34.480030 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9741 11:41:34.486502 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9742 11:41:34.489988 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9743 11:41:34.493014 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9744 11:41:34.499738 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9745 11:41:34.503078 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9746 11:41:34.509694 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9747 11:41:34.513193 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9748 11:41:34.515930 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9749 11:41:34.522509 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9750 11:41:34.525904 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9751 11:41:34.532324 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9752 11:41:34.535898 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9753 11:41:34.542555 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9754 11:41:34.545881 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9755 11:41:34.549295 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9756 11:41:34.555515 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9757 11:41:34.559015 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9758 11:41:34.565467 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9759 11:41:34.568867 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9760 11:41:34.575507 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9761 11:41:34.578347 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9762 11:41:34.581987 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9763 11:41:34.588410 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9764 11:41:34.592079 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9765 11:41:34.598734 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9766 11:41:34.601969 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9767 11:41:34.608463 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9768 11:41:34.611689 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9769 11:41:34.615149 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9770 11:41:34.621339 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9771 11:41:34.624625 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9772 11:41:34.631616 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9773 11:41:34.634902 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9774 11:41:34.641282 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9775 11:41:34.644927 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9776 11:41:34.647722 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9777 11:41:34.654404 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9778 11:41:34.657994 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9779 11:41:34.664371 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9780 11:41:34.667733 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9781 11:41:34.674343 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9782 11:41:34.677338 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9783 11:41:34.681023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9784 11:41:34.687375 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9785 11:41:34.690907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9786 11:41:34.697373 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9787 11:41:34.700288 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9788 11:41:34.703801 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9789 11:41:34.710185 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9790 11:41:34.713490 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9791 11:41:34.716877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9792 11:41:34.720378 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9793 11:41:34.727323 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9794 11:41:34.730063 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9795 11:41:34.733722 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9796 11:41:34.740125 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9797 11:41:34.743475 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9798 11:41:34.750393 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9799 11:41:34.753162 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9800 11:41:34.756729 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9801 11:41:34.763156 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9802 11:41:34.766454 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9803 11:41:34.769853 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9804 11:41:34.776792 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9805 11:41:34.779549 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9806 11:41:34.785989 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9807 11:41:34.789599 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9808 11:41:34.792693 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9809 11:41:34.799695 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9810 11:41:34.802753 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9811 11:41:34.809218 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9812 11:41:34.812907 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9813 11:41:34.815856 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9814 11:41:34.822883 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9815 11:41:34.825443 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9816 11:41:34.828737 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9817 11:41:34.835610 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9818 11:41:34.839287 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9819 11:41:34.842444 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9820 11:41:34.848985 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9821 11:41:34.851922 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9822 11:41:34.858976 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9823 11:41:34.861769 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9824 11:41:34.865262 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9825 11:41:34.871881 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9826 11:41:34.875091 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9827 11:41:34.878399 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9828 11:41:34.885018 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9829 11:41:34.888195 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9830 11:41:34.891882 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9831 11:41:34.894938 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9832 11:41:34.898044 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9833 11:41:34.905107 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9834 11:41:34.908136 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9835 11:41:34.911508 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9836 11:41:34.918230 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9837 11:41:34.921010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9838 11:41:34.924497 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9839 11:41:34.931032 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9840 11:41:34.934356 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9841 11:41:34.937726 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9842 11:41:34.944580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9843 11:41:34.947921 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9844 11:41:34.954064 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9845 11:41:34.957422 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9846 11:41:34.960566 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9847 11:41:34.967208 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9848 11:41:34.970869 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9849 11:41:34.976976 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9850 11:41:34.980253 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9851 11:41:34.984106 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9852 11:41:34.990279 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9853 11:41:34.993745 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9854 11:41:35.000070 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9855 11:41:35.003684 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9856 11:41:35.009826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9857 11:41:35.013361 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9858 11:41:35.016839 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9859 11:41:35.023773 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9860 11:41:35.026815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9861 11:41:35.033410 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9862 11:41:35.036287 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9863 11:41:35.043275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9864 11:41:35.046145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9865 11:41:35.049857 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9866 11:41:35.055955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9867 11:41:35.059776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9868 11:41:35.066065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9869 11:41:35.069485 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9870 11:41:35.076214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9871 11:41:35.079028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9872 11:41:35.082485 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9873 11:41:35.089419 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9874 11:41:35.092608 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9875 11:41:35.098817 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9876 11:41:35.102444 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9877 11:41:35.105482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9878 11:41:35.112098 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9879 11:41:35.115581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9880 11:41:35.122043 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9881 11:41:35.125611 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9882 11:41:35.128574 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9883 11:41:35.135450 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9884 11:41:35.138374 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9885 11:41:35.145206 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9886 11:41:35.148598 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9887 11:41:35.155051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9888 11:41:35.158257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9889 11:41:35.161307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9890 11:41:35.168370 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9891 11:41:35.171358 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9892 11:41:35.177793 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9893 11:41:35.180932 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9894 11:41:35.187486 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9895 11:41:35.191078 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9896 11:41:35.194453 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9897 11:41:35.201225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9898 11:41:35.204434 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9899 11:41:35.210764 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9900 11:41:35.214352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9901 11:41:35.217708 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9902 11:41:35.224369 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9903 11:41:35.227191 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9904 11:41:35.234283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9905 11:41:35.237186 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9906 11:41:35.240594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9907 11:41:35.247466 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9908 11:41:35.250985 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9909 11:41:35.257355 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9910 11:41:35.260120 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9911 11:41:35.266867 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9912 11:41:35.270545 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9913 11:41:35.273618 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9914 11:41:35.279958 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9915 11:41:35.283171 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9916 11:41:35.289948 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9917 11:41:35.293646 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9918 11:41:35.299955 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9919 11:41:35.303281 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9920 11:41:35.310371 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9921 11:41:35.313274 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9922 11:41:35.316222 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9923 11:41:35.322818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9924 11:41:35.326491 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9925 11:41:35.333186 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9926 11:41:35.336568 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9927 11:41:35.342930 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9928 11:41:35.346460 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9929 11:41:35.349478 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9930 11:41:35.356387 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9931 11:41:35.359476 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9932 11:41:35.365944 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9933 11:41:35.369630 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9934 11:41:35.375738 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9935 11:41:35.379239 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9936 11:41:35.385682 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9937 11:41:35.388894 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9938 11:41:35.392635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9939 11:41:35.398953 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9940 11:41:35.402626 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9941 11:41:35.408827 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9942 11:41:35.412035 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9943 11:41:35.419114 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9944 11:41:35.422131 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9945 11:41:35.428762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9946 11:41:35.432250 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9947 11:41:35.435731 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9948 11:41:35.441647 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9949 11:41:35.445319 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9950 11:41:35.451813 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9951 11:41:35.454728 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9952 11:41:35.461618 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9953 11:41:35.465302 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9954 11:41:35.471472 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9955 11:41:35.474592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9956 11:41:35.481757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9957 11:41:35.484934 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9958 11:41:35.487835 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9959 11:41:35.494626 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9960 11:41:35.497887 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9961 11:41:35.504499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9962 11:41:35.507888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9963 11:41:35.514322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9964 11:41:35.517719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9965 11:41:35.524472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9966 11:41:35.527616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9967 11:41:35.533880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9968 11:41:35.537339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9969 11:41:35.543875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9970 11:41:35.546897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9971 11:41:35.550462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9972 11:41:35.557012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9973 11:41:35.560489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9974 11:41:35.567099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9975 11:41:35.569979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9976 11:41:35.576459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9977 11:41:35.580153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9978 11:41:35.586811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9979 11:41:35.590026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9980 11:41:35.596563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9981 11:41:35.599822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9982 11:41:35.605833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9983 11:41:35.612453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9984 11:41:35.615611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9985 11:41:35.622121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9986 11:41:35.625555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9987 11:41:35.631950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9988 11:41:35.635830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9989 11:41:35.642005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9990 11:41:35.645593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9991 11:41:35.652227 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9992 11:41:35.655195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9993 11:41:35.658540 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9994 11:41:35.662166 INFO: [APUAPC] vio 0
9995 11:41:35.668546 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9996 11:41:35.671568 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9997 11:41:35.675357 INFO: [APUAPC] D0_APC_0: 0x400510
9998 11:41:35.678137 INFO: [APUAPC] D0_APC_1: 0x0
9999 11:41:35.681835 INFO: [APUAPC] D0_APC_2: 0x1540
10000 11:41:35.684775 INFO: [APUAPC] D0_APC_3: 0x0
10001 11:41:35.688308 INFO: [APUAPC] D1_APC_0: 0xffffffff
10002 11:41:35.691261 INFO: [APUAPC] D1_APC_1: 0xffffffff
10003 11:41:35.694812 INFO: [APUAPC] D1_APC_2: 0x3fffff
10004 11:41:35.698399 INFO: [APUAPC] D1_APC_3: 0x0
10005 11:41:35.701298 INFO: [APUAPC] D2_APC_0: 0xffffffff
10006 11:41:35.704707 INFO: [APUAPC] D2_APC_1: 0xffffffff
10007 11:41:35.707850 INFO: [APUAPC] D2_APC_2: 0x3fffff
10008 11:41:35.711635 INFO: [APUAPC] D2_APC_3: 0x0
10009 11:41:35.714811 INFO: [APUAPC] D3_APC_0: 0xffffffff
10010 11:41:35.718257 INFO: [APUAPC] D3_APC_1: 0xffffffff
10011 11:41:35.720977 INFO: [APUAPC] D3_APC_2: 0x3fffff
10012 11:41:35.724294 INFO: [APUAPC] D3_APC_3: 0x0
10013 11:41:35.727629 INFO: [APUAPC] D4_APC_0: 0xffffffff
10014 11:41:35.730854 INFO: [APUAPC] D4_APC_1: 0xffffffff
10015 11:41:35.734613 INFO: [APUAPC] D4_APC_2: 0x3fffff
10016 11:41:35.734787 INFO: [APUAPC] D4_APC_3: 0x0
10017 11:41:35.741136 INFO: [APUAPC] D5_APC_0: 0xffffffff
10018 11:41:35.744781 INFO: [APUAPC] D5_APC_1: 0xffffffff
10019 11:41:35.748222 INFO: [APUAPC] D5_APC_2: 0x3fffff
10020 11:41:35.748523 INFO: [APUAPC] D5_APC_3: 0x0
10021 11:41:35.754314 INFO: [APUAPC] D6_APC_0: 0xffffffff
10022 11:41:35.757858 INFO: [APUAPC] D6_APC_1: 0xffffffff
10023 11:41:35.761238 INFO: [APUAPC] D6_APC_2: 0x3fffff
10024 11:41:35.761669 INFO: [APUAPC] D6_APC_3: 0x0
10025 11:41:35.764083 INFO: [APUAPC] D7_APC_0: 0xffffffff
10026 11:41:35.767571 INFO: [APUAPC] D7_APC_1: 0xffffffff
10027 11:41:35.771095 INFO: [APUAPC] D7_APC_2: 0x3fffff
10028 11:41:35.773957 INFO: [APUAPC] D7_APC_3: 0x0
10029 11:41:35.777547 INFO: [APUAPC] D8_APC_0: 0xffffffff
10030 11:41:35.780636 INFO: [APUAPC] D8_APC_1: 0xffffffff
10031 11:41:35.784061 INFO: [APUAPC] D8_APC_2: 0x3fffff
10032 11:41:35.787502 INFO: [APUAPC] D8_APC_3: 0x0
10033 11:41:35.790401 INFO: [APUAPC] D9_APC_0: 0xffffffff
10034 11:41:35.793836 INFO: [APUAPC] D9_APC_1: 0xffffffff
10035 11:41:35.797125 INFO: [APUAPC] D9_APC_2: 0x3fffff
10036 11:41:35.800648 INFO: [APUAPC] D9_APC_3: 0x0
10037 11:41:35.803533 INFO: [APUAPC] D10_APC_0: 0xffffffff
10038 11:41:35.807272 INFO: [APUAPC] D10_APC_1: 0xffffffff
10039 11:41:35.810089 INFO: [APUAPC] D10_APC_2: 0x3fffff
10040 11:41:35.813397 INFO: [APUAPC] D10_APC_3: 0x0
10041 11:41:35.816646 INFO: [APUAPC] D11_APC_0: 0xffffffff
10042 11:41:35.819981 INFO: [APUAPC] D11_APC_1: 0xffffffff
10043 11:41:35.823242 INFO: [APUAPC] D11_APC_2: 0x3fffff
10044 11:41:35.826776 INFO: [APUAPC] D11_APC_3: 0x0
10045 11:41:35.830247 INFO: [APUAPC] D12_APC_0: 0xffffffff
10046 11:41:35.836828 INFO: [APUAPC] D12_APC_1: 0xffffffff
10047 11:41:35.839785 INFO: [APUAPC] D12_APC_2: 0x3fffff
10048 11:41:35.840303 INFO: [APUAPC] D12_APC_3: 0x0
10049 11:41:35.846399 INFO: [APUAPC] D13_APC_0: 0xffffffff
10050 11:41:35.849851 INFO: [APUAPC] D13_APC_1: 0xffffffff
10051 11:41:35.853116 INFO: [APUAPC] D13_APC_2: 0x3fffff
10052 11:41:35.853549 INFO: [APUAPC] D13_APC_3: 0x0
10053 11:41:35.860131 INFO: [APUAPC] D14_APC_0: 0xffffffff
10054 11:41:35.862895 INFO: [APUAPC] D14_APC_1: 0xffffffff
10055 11:41:35.866253 INFO: [APUAPC] D14_APC_2: 0x3fffff
10056 11:41:35.869743 INFO: [APUAPC] D14_APC_3: 0x0
10057 11:41:35.872920 INFO: [APUAPC] D15_APC_0: 0xffffffff
10058 11:41:35.876339 INFO: [APUAPC] D15_APC_1: 0xffffffff
10059 11:41:35.880120 INFO: [APUAPC] D15_APC_2: 0x3fffff
10060 11:41:35.882824 INFO: [APUAPC] D15_APC_3: 0x0
10061 11:41:35.883323 INFO: [APUAPC] APC_CON: 0x4
10062 11:41:35.886354 INFO: [NOCDAPC] D0_APC_0: 0x0
10063 11:41:35.889271 INFO: [NOCDAPC] D0_APC_1: 0x0
10064 11:41:35.892746 INFO: [NOCDAPC] D1_APC_0: 0x0
10065 11:41:35.896194 INFO: [NOCDAPC] D1_APC_1: 0xfff
10066 11:41:35.899211 INFO: [NOCDAPC] D2_APC_0: 0x0
10067 11:41:35.902629 INFO: [NOCDAPC] D2_APC_1: 0xfff
10068 11:41:35.905586 INFO: [NOCDAPC] D3_APC_0: 0x0
10069 11:41:35.909100 INFO: [NOCDAPC] D3_APC_1: 0xfff
10070 11:41:35.912484 INFO: [NOCDAPC] D4_APC_0: 0x0
10071 11:41:35.915597 INFO: [NOCDAPC] D4_APC_1: 0xfff
10072 11:41:35.916022 INFO: [NOCDAPC] D5_APC_0: 0x0
10073 11:41:35.918817 INFO: [NOCDAPC] D5_APC_1: 0xfff
10074 11:41:35.922080 INFO: [NOCDAPC] D6_APC_0: 0x0
10075 11:41:35.925338 INFO: [NOCDAPC] D6_APC_1: 0xfff
10076 11:41:35.928841 INFO: [NOCDAPC] D7_APC_0: 0x0
10077 11:41:35.932044 INFO: [NOCDAPC] D7_APC_1: 0xfff
10078 11:41:35.935382 INFO: [NOCDAPC] D8_APC_0: 0x0
10079 11:41:35.938726 INFO: [NOCDAPC] D8_APC_1: 0xfff
10080 11:41:35.941554 INFO: [NOCDAPC] D9_APC_0: 0x0
10081 11:41:35.944907 INFO: [NOCDAPC] D9_APC_1: 0xfff
10082 11:41:35.948687 INFO: [NOCDAPC] D10_APC_0: 0x0
10083 11:41:35.951666 INFO: [NOCDAPC] D10_APC_1: 0xfff
10084 11:41:35.955027 INFO: [NOCDAPC] D11_APC_0: 0x0
10085 11:41:35.958096 INFO: [NOCDAPC] D11_APC_1: 0xfff
10086 11:41:35.958516 INFO: [NOCDAPC] D12_APC_0: 0x0
10087 11:41:35.961881 INFO: [NOCDAPC] D12_APC_1: 0xfff
10088 11:41:35.964853 INFO: [NOCDAPC] D13_APC_0: 0x0
10089 11:41:35.968124 INFO: [NOCDAPC] D13_APC_1: 0xfff
10090 11:41:35.971495 INFO: [NOCDAPC] D14_APC_0: 0x0
10091 11:41:35.974622 INFO: [NOCDAPC] D14_APC_1: 0xfff
10092 11:41:35.978010 INFO: [NOCDAPC] D15_APC_0: 0x0
10093 11:41:35.980983 INFO: [NOCDAPC] D15_APC_1: 0xfff
10094 11:41:35.983930 INFO: [NOCDAPC] APC_CON: 0x4
10095 11:41:35.987311 INFO: [APUAPC] set_apusys_apc done
10096 11:41:35.990802 INFO: [DEVAPC] devapc_init done
10097 11:41:35.993935 INFO: GICv3 without legacy support detected.
10098 11:41:35.997446 INFO: ARM GICv3 driver initialized in EL3
10099 11:41:36.003920 INFO: Maximum SPI INTID supported: 639
10100 11:41:36.007443 INFO: BL31: Initializing runtime services
10101 11:41:36.013876 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10102 11:41:36.013961 INFO: SPM: enable CPC mode
10103 11:41:36.020405 INFO: mcdi ready for mcusys-off-idle and system suspend
10104 11:41:36.024007 INFO: BL31: Preparing for EL3 exit to normal world
10105 11:41:36.027606 INFO: Entry point address = 0x80000000
10106 11:41:36.030439 INFO: SPSR = 0x8
10107 11:41:36.036345
10108 11:41:36.036440
10109 11:41:36.036517
10110 11:41:36.039813 Starting depthcharge on Spherion...
10111 11:41:36.039917
10112 11:41:36.039998 Wipe memory regions:
10113 11:41:36.040075
10114 11:41:36.040790 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10115 11:41:36.040914 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10116 11:41:36.041017 Setting prompt string to ['asurada:']
10117 11:41:36.041117 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10118 11:41:36.043291 [0x00000040000000, 0x00000054600000)
10119 11:41:36.165380
10120 11:41:36.165970 [0x00000054660000, 0x00000080000000)
10121 11:41:36.425891
10122 11:41:36.426385 [0x000000821a7280, 0x000000ffe64000)
10123 11:41:37.170929
10124 11:41:37.171495 [0x00000100000000, 0x00000240000000)
10125 11:41:39.061163
10126 11:41:39.064313 Initializing XHCI USB controller at 0x11200000.
10127 11:41:40.101693
10128 11:41:40.104914 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10129 11:41:40.105022
10130 11:41:40.105114
10131 11:41:40.105207
10132 11:41:40.105519 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10134 11:41:40.205869 asurada: tftpboot 192.168.201.1 10742234/tftp-deploy-rew3k99n/kernel/image.itb 10742234/tftp-deploy-rew3k99n/kernel/cmdline
10135 11:41:40.206037 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10136 11:41:40.206155 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10137 11:41:40.210631 tftpboot 192.168.201.1 10742234/tftp-deploy-rew3k99n/kernel/image.itp-deploy-rew3k99n/kernel/cmdline
10138 11:41:40.210744
10139 11:41:40.210868 Waiting for link
10140 11:41:40.370683
10141 11:41:40.370902 R8152: Initializing
10142 11:41:40.370981
10143 11:41:40.374088 Version 6 (ocp_data = 5c30)
10144 11:41:40.374192
10145 11:41:40.377469 R8152: Done initializing
10146 11:41:40.377577
10147 11:41:40.377669 Adding net device
10148 11:41:42.438544
10149 11:41:42.438725 done.
10150 11:41:42.438854
10151 11:41:42.438936 MAC: 00:24:32:30:78:ff
10152 11:41:42.439004
10153 11:41:42.441399 Sending DHCP discover... done.
10154 11:41:42.441498
10155 11:41:45.644001 Waiting for reply... done.
10156 11:41:45.644182
10157 11:41:45.644281 Sending DHCP request... done.
10158 11:41:45.647232
10159 11:41:45.655075 Waiting for reply... done.
10160 11:41:45.655197
10161 11:41:45.655302 My ip is 192.168.201.21
10162 11:41:45.655403
10163 11:41:45.658324 The DHCP server ip is 192.168.201.1
10164 11:41:45.658422
10165 11:41:45.665191 TFTP server IP predefined by user: 192.168.201.1
10166 11:41:45.665297
10167 11:41:45.671766 Bootfile predefined by user: 10742234/tftp-deploy-rew3k99n/kernel/image.itb
10168 11:41:45.671866
10169 11:41:45.674932 Sending tftp read request... done.
10170 11:41:45.675037
10171 11:41:45.678336 Waiting for the transfer...
10172 11:41:45.678437
10173 11:41:46.222088 00000000 ################################################################
10174 11:41:46.222243
10175 11:41:46.802477 00080000 ################################################################
10176 11:41:46.802614
10177 11:41:47.383415 00100000 ################################################################
10178 11:41:47.383565
10179 11:41:47.925501 00180000 ################################################################
10180 11:41:47.925673
10181 11:41:48.463535 00200000 ################################################################
10182 11:41:48.463676
10183 11:41:49.011856 00280000 ################################################################
10184 11:41:49.011994
10185 11:41:49.549296 00300000 ################################################################
10186 11:41:49.549452
10187 11:41:50.088338 00380000 ################################################################
10188 11:41:50.088509
10189 11:41:50.633977 00400000 ################################################################
10190 11:41:50.634156
10191 11:41:51.180367 00480000 ################################################################
10192 11:41:51.180514
10193 11:41:51.813386 00500000 ################################################################
10194 11:41:51.813696
10195 11:41:52.394164 00580000 ################################################################
10196 11:41:52.394304
10197 11:41:52.949036 00600000 ################################################################
10198 11:41:52.949192
10199 11:41:53.496969 00680000 ################################################################
10200 11:41:53.497106
10201 11:41:54.045428 00700000 ################################################################
10202 11:41:54.045584
10203 11:41:54.613299 00780000 ################################################################
10204 11:41:54.613461
10205 11:41:55.196210 00800000 ################################################################
10206 11:41:55.196911
10207 11:41:55.814326 00880000 ################################################################
10208 11:41:55.814461
10209 11:41:56.379375 00900000 ################################################################
10210 11:41:56.379919
10211 11:41:57.051973 00980000 ################################################################
10212 11:41:57.052708
10213 11:41:57.679532 00a00000 ################################################################
10214 11:41:57.680068
10215 11:41:58.320760 00a80000 ################################################################
10216 11:41:58.320941
10217 11:41:58.894997 00b00000 ################################################################
10218 11:41:58.895148
10219 11:41:59.459666 00b80000 ################################################################
10220 11:41:59.459822
10221 11:42:00.061612 00c00000 ################################################################
10222 11:42:00.061789
10223 11:42:00.651500 00c80000 ################################################################
10224 11:42:00.651653
10225 11:42:01.207075 00d00000 ################################################################
10226 11:42:01.207225
10227 11:42:01.793973 00d80000 ################################################################
10228 11:42:01.794126
10229 11:42:02.338335 00e00000 ################################################################
10230 11:42:02.338510
10231 11:42:02.896204 00e80000 ################################################################
10232 11:42:02.896366
10233 11:42:03.446514 00f00000 ################################################################
10234 11:42:03.446692
10235 11:42:03.998289 00f80000 ################################################################
10236 11:42:03.998463
10237 11:42:04.552305 01000000 ################################################################
10238 11:42:04.552476
10239 11:42:05.106070 01080000 ################################################################
10240 11:42:05.106210
10241 11:42:05.705295 01100000 ################################################################
10242 11:42:05.705487
10243 11:42:06.314612 01180000 ################################################################
10244 11:42:06.315293
10245 11:42:06.896317 01200000 ################################################################
10246 11:42:06.896495
10247 11:42:07.551844 01280000 ################################################################
10248 11:42:07.552412
10249 11:42:08.224811 01300000 ################################################################
10250 11:42:08.225391
10251 11:42:08.919641 01380000 ################################################################
10252 11:42:08.920367
10253 11:42:09.495531 01400000 ################################################################
10254 11:42:09.495671
10255 11:42:10.117069 01480000 ################################################################
10256 11:42:10.117607
10257 11:42:10.742013 01500000 ################################################################
10258 11:42:10.742153
10259 11:42:11.352449 01580000 ################################################################
10260 11:42:11.352651
10261 11:42:12.025309 01600000 ################################################################
10262 11:42:12.025907
10263 11:42:12.713139 01680000 ################################################################
10264 11:42:12.713869
10265 11:42:13.405289 01700000 ################################################################
10266 11:42:13.405850
10267 11:42:14.106191 01780000 ################################################################
10268 11:42:14.106713
10269 11:42:14.781205 01800000 ################################################################
10270 11:42:14.781735
10271 11:42:15.351550 01880000 ################################################################
10272 11:42:15.351707
10273 11:42:15.910872 01900000 ################################################################
10274 11:42:15.911011
10275 11:42:16.454093 01980000 ################################################################
10276 11:42:16.454232
10277 11:42:17.020716 01a00000 ################################################################
10278 11:42:17.020854
10279 11:42:17.394469 01a80000 ########################################### done.
10280 11:42:17.394620
10281 11:42:17.398073 The bootfile was 28135550 bytes long.
10282 11:42:17.398156
10283 11:42:17.401024 Sending tftp read request... done.
10284 11:42:17.401106
10285 11:42:17.401168 Waiting for the transfer...
10286 11:42:17.401227
10287 11:42:17.404225 00000000 # done.
10288 11:42:17.404309
10289 11:42:17.411091 Command line loaded dynamically from TFTP file: 10742234/tftp-deploy-rew3k99n/kernel/cmdline
10290 11:42:17.411175
10291 11:42:17.430690 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742234/extract-nfsrootfs-751xmu20,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10292 11:42:17.430786
10293 11:42:17.433743 Loading FIT.
10294 11:42:17.433838
10295 11:42:17.437297 Image ramdisk-1 has 17643229 bytes.
10296 11:42:17.437382
10297 11:42:17.437449 Image fdt-1 has 46924 bytes.
10298 11:42:17.440573
10299 11:42:17.440657 Image kernel-1 has 10443363 bytes.
10300 11:42:17.440724
10301 11:42:17.450646 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10302 11:42:17.450744
10303 11:42:17.467605 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10304 11:42:17.471108
10305 11:42:17.473677 Choosing best match conf-1 for compat google,spherion-rev2.
10306 11:42:17.478243
10307 11:42:17.482185 Connected to device vid:did:rid of 1ae0:0028:00
10308 11:42:17.489620
10309 11:42:17.492689 tpm_get_response: command 0x17b, return code 0x0
10310 11:42:17.492773
10311 11:42:17.496312 ec_init: CrosEC protocol v3 supported (256, 248)
10312 11:42:17.500163
10313 11:42:17.503047 tpm_cleanup: add release locality here.
10314 11:42:17.503144
10315 11:42:17.503244 Shutting down all USB controllers.
10316 11:42:17.506741
10317 11:42:17.506883 Removing current net device
10318 11:42:17.506970
10319 11:42:17.513138 Exiting depthcharge with code 4 at timestamp: 70801981
10320 11:42:17.513252
10321 11:42:17.516477 LZMA decompressing kernel-1 to 0x821a6718
10322 11:42:17.516648
10323 11:42:17.519908 LZMA decompressing kernel-1 to 0x40000000
10324 11:42:18.831527
10325 11:42:18.832091 jumping to kernel
10326 11:42:18.833673 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10327 11:42:18.834287 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10328 11:42:18.834769 Setting prompt string to ['Linux version [0-9]']
10329 11:42:18.835243 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10330 11:42:18.835640 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10331 11:42:18.913325
10332 11:42:18.916391 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10333 11:42:18.919962 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10334 11:42:18.920726 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10335 11:42:18.921244 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10336 11:42:18.921699 Using line separator: #'\n'#
10337 11:42:18.922093 No login prompt set.
10338 11:42:18.922454 Parsing kernel messages
10339 11:42:18.922977 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10340 11:42:18.923599 [login-action] Waiting for messages, (timeout 00:03:42)
10341 11:42:18.939618 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10342 11:42:18.943115 [ 0.000000] random: crng init done
10343 11:42:18.946257 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10344 11:42:18.949746 [ 0.000000] efi: UEFI not found.
10345 11:42:18.959728 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10346 11:42:18.965749 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10347 11:42:18.976159 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10348 11:42:18.985696 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10349 11:42:18.992317 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10350 11:42:18.998751 [ 0.000000] printk: bootconsole [mtk8250] enabled
10351 11:42:19.005416 [ 0.000000] NUMA: No NUMA configuration found
10352 11:42:19.011951 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10353 11:42:19.015373 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10354 11:42:19.018272 [ 0.000000] Zone ranges:
10355 11:42:19.025396 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10356 11:42:19.028278 [ 0.000000] DMA32 empty
10357 11:42:19.034958 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10358 11:42:19.038385 [ 0.000000] Movable zone start for each node
10359 11:42:19.041691 [ 0.000000] Early memory node ranges
10360 11:42:19.048407 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10361 11:42:19.054622 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10362 11:42:19.061599 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10363 11:42:19.068157 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10364 11:42:19.071218 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10365 11:42:19.081092 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10366 11:42:19.136031 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10367 11:42:19.142721 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10368 11:42:19.149031 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10369 11:42:19.152379 [ 0.000000] psci: probing for conduit method from DT.
10370 11:42:19.158899 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10371 11:42:19.162105 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10372 11:42:19.168757 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10373 11:42:19.171935 [ 0.000000] psci: SMC Calling Convention v1.2
10374 11:42:19.178740 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10375 11:42:19.181846 [ 0.000000] Detected VIPT I-cache on CPU0
10376 11:42:19.188277 [ 0.000000] CPU features: detected: GIC system register CPU interface
10377 11:42:19.195238 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10378 11:42:19.201672 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10379 11:42:19.208455 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10380 11:42:19.218248 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10381 11:42:19.225055 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10382 11:42:19.228030 [ 0.000000] alternatives: applying boot alternatives
10383 11:42:19.234698 [ 0.000000] Fallback order for Node 0: 0
10384 11:42:19.241477 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10385 11:42:19.244736 [ 0.000000] Policy zone: Normal
10386 11:42:19.264310 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742234/extract-nfsrootfs-751xmu20,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10387 11:42:19.274259 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10388 11:42:19.286280 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10389 11:42:19.296415 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10390 11:42:19.302622 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10391 11:42:19.306231 <6>[ 0.000000] software IO TLB: area num 8.
10392 11:42:19.363505 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10393 11:42:19.513061 <6>[ 0.000000] Memory: 7953932K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398836K reserved, 32768K cma-reserved)
10394 11:42:19.519637 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10395 11:42:19.526416 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10396 11:42:19.529712 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10397 11:42:19.535974 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10398 11:42:19.542775 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10399 11:42:19.545925 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10400 11:42:19.555438 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10401 11:42:19.563022 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10402 11:42:19.569226 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10403 11:42:19.575515 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10404 11:42:19.578529 <6>[ 0.000000] GICv3: 608 SPIs implemented
10405 11:42:19.582194 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10406 11:42:19.588705 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10407 11:42:19.592047 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10408 11:42:19.598408 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10409 11:42:19.611526 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10410 11:42:19.624938 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10411 11:42:19.631522 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10412 11:42:19.639414 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10413 11:42:19.652743 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10414 11:42:19.659028 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10415 11:42:19.665723 <6>[ 0.009175] Console: colour dummy device 80x25
10416 11:42:19.675731 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10417 11:42:19.682209 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10418 11:42:19.685918 <6>[ 0.029218] LSM: Security Framework initializing
10419 11:42:19.692493 <6>[ 0.034185] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10420 11:42:19.702336 <6>[ 0.041999] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10421 11:42:19.712297 <6>[ 0.051428] cblist_init_generic: Setting adjustable number of callback queues.
10422 11:42:19.715453 <6>[ 0.058926] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 11:42:19.722322 <6>[ 0.065265] cblist_init_generic: Setting shift to 3 and lim to 1.
10424 11:42:19.729041 <6>[ 0.071715] rcu: Hierarchical SRCU implementation.
10425 11:42:19.734929 <6>[ 0.076759] rcu: Max phase no-delay instances is 1000.
10426 11:42:19.741794 <6>[ 0.083772] EFI services will not be available.
10427 11:42:19.745187 <6>[ 0.088748] smp: Bringing up secondary CPUs ...
10428 11:42:19.753009 <6>[ 0.093799] Detected VIPT I-cache on CPU1
10429 11:42:19.759552 <6>[ 0.093874] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10430 11:42:19.766864 <6>[ 0.093905] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10431 11:42:19.769845 <6>[ 0.094236] Detected VIPT I-cache on CPU2
10432 11:42:19.779628 <6>[ 0.094289] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10433 11:42:19.786056 <6>[ 0.094308] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10434 11:42:19.789166 <6>[ 0.094570] Detected VIPT I-cache on CPU3
10435 11:42:19.795550 <6>[ 0.094617] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10436 11:42:19.802548 <6>[ 0.094632] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10437 11:42:19.808999 <6>[ 0.094935] CPU features: detected: Spectre-v4
10438 11:42:19.812322 <6>[ 0.094943] CPU features: detected: Spectre-BHB
10439 11:42:19.815464 <6>[ 0.094949] Detected PIPT I-cache on CPU4
10440 11:42:19.822396 <6>[ 0.095007] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10441 11:42:19.829039 <6>[ 0.095024] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10442 11:42:19.835179 <6>[ 0.095313] Detected PIPT I-cache on CPU5
10443 11:42:19.842581 <6>[ 0.095375] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10444 11:42:19.848732 <6>[ 0.095392] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10445 11:42:19.852095 <6>[ 0.095677] Detected PIPT I-cache on CPU6
10446 11:42:19.862202 <6>[ 0.095745] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10447 11:42:19.868543 <6>[ 0.095762] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10448 11:42:19.871754 <6>[ 0.096058] Detected PIPT I-cache on CPU7
10449 11:42:19.877933 <6>[ 0.096123] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10450 11:42:19.884903 <6>[ 0.096139] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10451 11:42:19.888596 <6>[ 0.096186] smp: Brought up 1 node, 8 CPUs
10452 11:42:19.895162 <6>[ 0.237520] SMP: Total of 8 processors activated.
10453 11:42:19.901928 <6>[ 0.242471] CPU features: detected: 32-bit EL0 Support
10454 11:42:19.908086 <6>[ 0.247834] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10455 11:42:19.914450 <6>[ 0.256634] CPU features: detected: Common not Private translations
10456 11:42:19.920825 <6>[ 0.263110] CPU features: detected: CRC32 instructions
10457 11:42:19.927536 <6>[ 0.268461] CPU features: detected: RCpc load-acquire (LDAPR)
10458 11:42:19.930787 <6>[ 0.274421] CPU features: detected: LSE atomic instructions
10459 11:42:19.937860 <6>[ 0.280237] CPU features: detected: Privileged Access Never
10460 11:42:19.944404 <6>[ 0.286017] CPU features: detected: RAS Extension Support
10461 11:42:19.950488 <6>[ 0.291626] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10462 11:42:19.954092 <6>[ 0.298845] CPU: All CPU(s) started at EL2
10463 11:42:19.960203 <6>[ 0.303188] alternatives: applying system-wide alternatives
10464 11:42:19.970803 <6>[ 0.313903] devtmpfs: initialized
10465 11:42:19.986266 <6>[ 0.322688] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10466 11:42:19.992901 <6>[ 0.332652] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10467 11:42:19.999451 <6>[ 0.340852] pinctrl core: initialized pinctrl subsystem
10468 11:42:20.002440 <6>[ 0.347519] DMI not present or invalid.
10469 11:42:20.009004 <6>[ 0.351924] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10470 11:42:20.018773 <6>[ 0.358793] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10471 11:42:20.025575 <6>[ 0.366366] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10472 11:42:20.035324 <6>[ 0.374586] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10473 11:42:20.038407 <6>[ 0.382830] audit: initializing netlink subsys (disabled)
10474 11:42:20.048645 <5>[ 0.388521] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10475 11:42:20.055850 <6>[ 0.389217] thermal_sys: Registered thermal governor 'step_wise'
10476 11:42:20.062230 <6>[ 0.396489] thermal_sys: Registered thermal governor 'power_allocator'
10477 11:42:20.065282 <6>[ 0.402743] cpuidle: using governor menu
10478 11:42:20.071575 <6>[ 0.413699] NET: Registered PF_QIPCRTR protocol family
10479 11:42:20.078487 <6>[ 0.419183] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10480 11:42:20.084774 <6>[ 0.426283] ASID allocator initialised with 32768 entries
10481 11:42:20.088515 <6>[ 0.432846] Serial: AMBA PL011 UART driver
10482 11:42:20.098588 <4>[ 0.441524] Trying to register duplicate clock ID: 134
10483 11:42:20.152509 <6>[ 0.498813] KASLR enabled
10484 11:42:20.167037 <6>[ 0.506473] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10485 11:42:20.173230 <6>[ 0.513487] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10486 11:42:20.180152 <6>[ 0.519977] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10487 11:42:20.186795 <6>[ 0.526983] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10488 11:42:20.193258 <6>[ 0.533472] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10489 11:42:20.199901 <6>[ 0.540478] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10490 11:42:20.206162 <6>[ 0.546965] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10491 11:42:20.212954 <6>[ 0.553970] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10492 11:42:20.216338 <6>[ 0.561430] ACPI: Interpreter disabled.
10493 11:42:20.224813 <6>[ 0.567813] iommu: Default domain type: Translated
10494 11:42:20.231839 <6>[ 0.572926] iommu: DMA domain TLB invalidation policy: strict mode
10495 11:42:20.234870 <5>[ 0.579589] SCSI subsystem initialized
10496 11:42:20.241423 <6>[ 0.583822] usbcore: registered new interface driver usbfs
10497 11:42:20.248086 <6>[ 0.589550] usbcore: registered new interface driver hub
10498 11:42:20.251477 <6>[ 0.595104] usbcore: registered new device driver usb
10499 11:42:20.258334 <6>[ 0.601195] pps_core: LinuxPPS API ver. 1 registered
10500 11:42:20.268251 <6>[ 0.606387] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10501 11:42:20.271658 <6>[ 0.615734] PTP clock support registered
10502 11:42:20.274765 <6>[ 0.619972] EDAC MC: Ver: 3.0.0
10503 11:42:20.282439 <6>[ 0.625148] FPGA manager framework
10504 11:42:20.289216 <6>[ 0.628823] Advanced Linux Sound Architecture Driver Initialized.
10505 11:42:20.291914 <6>[ 0.635580] vgaarb: loaded
10506 11:42:20.298799 <6>[ 0.638741] clocksource: Switched to clocksource arch_sys_counter
10507 11:42:20.302340 <5>[ 0.645191] VFS: Disk quotas dquot_6.6.0
10508 11:42:20.308654 <6>[ 0.649378] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10509 11:42:20.311959 <6>[ 0.656568] pnp: PnP ACPI: disabled
10510 11:42:20.320079 <6>[ 0.663206] NET: Registered PF_INET protocol family
10511 11:42:20.330472 <6>[ 0.668749] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10512 11:42:20.341619 <6>[ 0.681067] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10513 11:42:20.351207 <6>[ 0.689882] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10514 11:42:20.357987 <6>[ 0.697851] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10515 11:42:20.368015 <6>[ 0.706550] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10516 11:42:20.374270 <6>[ 0.716303] TCP: Hash tables configured (established 65536 bind 65536)
10517 11:42:20.380959 <6>[ 0.723168] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10518 11:42:20.390865 <6>[ 0.730365] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10519 11:42:20.398249 <6>[ 0.738072] NET: Registered PF_UNIX/PF_LOCAL protocol family
10520 11:42:20.403975 <6>[ 0.744215] RPC: Registered named UNIX socket transport module.
10521 11:42:20.407136 <6>[ 0.750370] RPC: Registered udp transport module.
10522 11:42:20.413822 <6>[ 0.755304] RPC: Registered tcp transport module.
10523 11:42:20.420626 <6>[ 0.760236] RPC: Registered tcp NFSv4.1 backchannel transport module.
10524 11:42:20.423823 <6>[ 0.766903] PCI: CLS 0 bytes, default 64
10525 11:42:20.427121 <6>[ 0.771238] Unpacking initramfs...
10526 11:42:20.436980 <6>[ 0.775023] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10527 11:42:20.443605 <6>[ 0.783642] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10528 11:42:20.450553 <6>[ 0.792424] kvm [1]: IPA Size Limit: 40 bits
10529 11:42:20.453438 <6>[ 0.796951] kvm [1]: GICv3: no GICV resource entry
10530 11:42:20.460089 <6>[ 0.801970] kvm [1]: disabling GICv2 emulation
10531 11:42:20.466740 <6>[ 0.806654] kvm [1]: GIC system register CPU interface enabled
10532 11:42:20.469524 <6>[ 0.812818] kvm [1]: vgic interrupt IRQ18
10533 11:42:20.476117 <6>[ 0.817173] kvm [1]: VHE mode initialized successfully
10534 11:42:20.479271 <5>[ 0.823662] Initialise system trusted keyrings
10535 11:42:20.485873 <6>[ 0.828456] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10536 11:42:20.495125 <6>[ 0.838402] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10537 11:42:20.501857 <5>[ 0.844771] NFS: Registering the id_resolver key type
10538 11:42:20.504836 <5>[ 0.850068] Key type id_resolver registered
10539 11:42:20.511786 <5>[ 0.854482] Key type id_legacy registered
10540 11:42:20.518459 <6>[ 0.858765] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10541 11:42:20.524838 <6>[ 0.865689] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10542 11:42:20.531577 <6>[ 0.873423] 9p: Installing v9fs 9p2000 file system support
10543 11:42:20.568480 <5>[ 0.911836] Key type asymmetric registered
10544 11:42:20.571796 <5>[ 0.916167] Asymmetric key parser 'x509' registered
10545 11:42:20.581795 <6>[ 0.921326] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10546 11:42:20.585093 <6>[ 0.928939] io scheduler mq-deadline registered
10547 11:42:20.588279 <6>[ 0.933700] io scheduler kyber registered
10548 11:42:20.607081 <6>[ 0.950512] EINJ: ACPI disabled.
10549 11:42:20.638972 <4>[ 0.975632] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 11:42:20.648344 <4>[ 0.986256] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 11:42:20.663076 <6>[ 1.006771] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10552 11:42:20.671084 <6>[ 1.014630] printk: console [ttyS0] disabled
10553 11:42:20.698949 <6>[ 1.039272] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10554 11:42:20.705939 <6>[ 1.048740] printk: console [ttyS0] enabled
10555 11:42:20.709237 <6>[ 1.048740] printk: console [ttyS0] enabled
10556 11:42:20.715830 <6>[ 1.057637] printk: bootconsole [mtk8250] disabled
10557 11:42:20.719382 <6>[ 1.057637] printk: bootconsole [mtk8250] disabled
10558 11:42:20.725423 <6>[ 1.068624] SuperH (H)SCI(F) driver initialized
10559 11:42:20.728645 <6>[ 1.073875] msm_serial: driver initialized
10560 11:42:20.743103 <6>[ 1.082721] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10561 11:42:20.752865 <6>[ 1.091270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10562 11:42:20.759588 <6>[ 1.099812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10563 11:42:20.769469 <6>[ 1.108440] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10564 11:42:20.779624 <6>[ 1.117149] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10565 11:42:20.786168 <6>[ 1.125868] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10566 11:42:20.795746 <6>[ 1.134408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10567 11:42:20.802561 <6>[ 1.143219] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10568 11:42:20.812071 <6>[ 1.151761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10569 11:42:20.823776 <6>[ 1.167041] loop: module loaded
10570 11:42:20.830336 <6>[ 1.172917] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10571 11:42:20.853423 <4>[ 1.196248] mtk-pmic-keys: Failed to locate of_node [id: -1]
10572 11:42:20.859755 <6>[ 1.202889] megasas: 07.719.03.00-rc1
10573 11:42:20.869303 <6>[ 1.212413] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10574 11:42:20.878980 <6>[ 1.222115] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10575 11:42:20.895562 <6>[ 1.238516] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10576 11:42:20.955948 <6>[ 1.292138] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10577 11:42:21.160698 <6>[ 1.504255] Freeing initrd memory: 17224K
10578 11:42:21.170747 <6>[ 1.514530] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10579 11:42:21.181910 <6>[ 1.525344] tun: Universal TUN/TAP device driver, 1.6
10580 11:42:21.185489 <6>[ 1.531392] thunder_xcv, ver 1.0
10581 11:42:21.188844 <6>[ 1.534893] thunder_bgx, ver 1.0
10582 11:42:21.191609 <6>[ 1.538385] nicpf, ver 1.0
10583 11:42:21.202185 <6>[ 1.542377] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10584 11:42:21.205865 <6>[ 1.549853] hns3: Copyright (c) 2017 Huawei Corporation.
10585 11:42:21.212594 <6>[ 1.555458] hclge is initializing
10586 11:42:21.215384 <6>[ 1.559038] e1000: Intel(R) PRO/1000 Network Driver
10587 11:42:21.222235 <6>[ 1.564167] e1000: Copyright (c) 1999-2006 Intel Corporation.
10588 11:42:21.225599 <6>[ 1.570178] e1000e: Intel(R) PRO/1000 Network Driver
10589 11:42:21.232240 <6>[ 1.575394] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10590 11:42:21.238573 <6>[ 1.581580] igb: Intel(R) Gigabit Ethernet Network Driver
10591 11:42:21.245115 <6>[ 1.587229] igb: Copyright (c) 2007-2014 Intel Corporation.
10592 11:42:21.251699 <6>[ 1.593064] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10593 11:42:21.258466 <6>[ 1.599582] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10594 11:42:21.262103 <6>[ 1.606041] sky2: driver version 1.30
10595 11:42:21.268727 <6>[ 1.611010] VFIO - User Level meta-driver version: 0.3
10596 11:42:21.275820 <6>[ 1.619226] usbcore: registered new interface driver usb-storage
10597 11:42:21.282416 <6>[ 1.625665] usbcore: registered new device driver onboard-usb-hub
10598 11:42:21.291788 <6>[ 1.634701] mt6397-rtc mt6359-rtc: registered as rtc0
10599 11:42:21.301339 <6>[ 1.640165] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:42:21 UTC (1686829341)
10600 11:42:21.304666 <6>[ 1.649725] i2c_dev: i2c /dev entries driver
10601 11:42:21.321742 <6>[ 1.661284] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10602 11:42:21.328386 <6>[ 1.671475] sdhci: Secure Digital Host Controller Interface driver
10603 11:42:21.335423 <6>[ 1.677911] sdhci: Copyright(c) Pierre Ossman
10604 11:42:21.341594 <6>[ 1.683305] Synopsys Designware Multimedia Card Interface Driver
10605 11:42:21.344858 <6>[ 1.689907] mmc0: CQHCI version 5.10
10606 11:42:21.351620 <6>[ 1.690456] sdhci-pltfm: SDHCI platform and OF driver helper
10607 11:42:21.358786 <6>[ 1.701979] ledtrig-cpu: registered to indicate activity on CPUs
10608 11:42:21.369631 <6>[ 1.709480] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10609 11:42:21.373066 <6>[ 1.716878] usbcore: registered new interface driver usbhid
10610 11:42:21.379807 <6>[ 1.722710] usbhid: USB HID core driver
10611 11:42:21.386017 <6>[ 1.726949] spi_master spi0: will run message pump with realtime priority
10612 11:42:21.434091 <6>[ 1.770429] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10613 11:42:21.453744 <6>[ 1.786238] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10614 11:42:21.456769 <6>[ 1.799800] mmc0: Command Queue Engine enabled
10615 11:42:21.464076 <6>[ 1.801704] cros-ec-spi spi0.0: Chrome EC device registered
10616 11:42:21.470823 <6>[ 1.804540] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10617 11:42:21.473544 <6>[ 1.817656] mmcblk0: mmc0:0001 DA4128 116 GiB
10618 11:42:21.490200 <6>[ 1.830090] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10619 11:42:21.497447 <6>[ 1.830377] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10620 11:42:21.503954 <6>[ 1.841401] NET: Registered PF_PACKET protocol family
10621 11:42:21.507278 <6>[ 1.846634] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 11:42:21.513832 <6>[ 1.850742] 9pnet: Installing 9P2000 support
10623 11:42:21.517098 <6>[ 1.856613] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10624 11:42:21.523513 <5>[ 1.860417] Key type dns_resolver registered
10625 11:42:21.530222 <6>[ 1.866204] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10626 11:42:21.533821 <6>[ 1.870598] registered taskstats version 1
10627 11:42:21.537088 <5>[ 1.881025] Loading compiled-in X.509 certificates
10628 11:42:21.571760 <4>[ 1.908469] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10629 11:42:21.582187 <4>[ 1.919155] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 11:42:21.592086 <3>[ 1.931999] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10631 11:42:21.604180 <6>[ 1.947321] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10632 11:42:21.610866 <6>[ 1.954078] xhci-mtk 11200000.usb: xHCI Host Controller
10633 11:42:21.618003 <6>[ 1.959586] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10634 11:42:21.627926 <6>[ 1.967441] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10635 11:42:21.633994 <6>[ 1.976870] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10636 11:42:21.640898 <6>[ 1.983061] xhci-mtk 11200000.usb: xHCI Host Controller
10637 11:42:21.647426 <6>[ 1.988582] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10638 11:42:21.654272 <6>[ 1.996243] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10639 11:42:21.661076 <6>[ 2.004132] hub 1-0:1.0: USB hub found
10640 11:42:21.664576 <6>[ 2.008165] hub 1-0:1.0: 1 port detected
10641 11:42:21.674187 <6>[ 2.012501] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10642 11:42:21.677937 <6>[ 2.021337] hub 2-0:1.0: USB hub found
10643 11:42:21.680995 <6>[ 2.025371] hub 2-0:1.0: 1 port detected
10644 11:42:21.689699 <6>[ 2.032630] mtk-msdc 11f70000.mmc: Got CD GPIO
10645 11:42:21.707392 <6>[ 2.047205] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10646 11:42:21.714223 <6>[ 2.055349] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10647 11:42:21.724114 <4>[ 2.063351] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10648 11:42:21.734000 <6>[ 2.073045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10649 11:42:21.740854 <6>[ 2.081131] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10650 11:42:21.750381 <6>[ 2.089191] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10651 11:42:21.757097 <6>[ 2.097114] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10652 11:42:21.763899 <6>[ 2.104968] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10653 11:42:21.773539 <6>[ 2.112792] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10654 11:42:21.784151 <6>[ 2.123573] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10655 11:42:21.793823 <6>[ 2.131939] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10656 11:42:21.800808 <6>[ 2.140339] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10657 11:42:21.810878 <6>[ 2.148685] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10658 11:42:21.817308 <6>[ 2.157053] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10659 11:42:21.826950 <6>[ 2.165398] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10660 11:42:21.833899 <6>[ 2.173765] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10661 11:42:21.844102 <6>[ 2.182109] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10662 11:42:21.850911 <6>[ 2.190472] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10663 11:42:21.860896 <6>[ 2.198816] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10664 11:42:21.867248 <6>[ 2.207160] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10665 11:42:21.876605 <6>[ 2.215503] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10666 11:42:21.883649 <6>[ 2.223851] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10667 11:42:21.893614 <6>[ 2.232196] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10668 11:42:21.899998 <6>[ 2.240539] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10669 11:42:21.906580 <6>[ 2.249456] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10670 11:42:21.913442 <6>[ 2.256907] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10671 11:42:21.920971 <6>[ 2.263923] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10672 11:42:21.931098 <6>[ 2.271012] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10673 11:42:21.938012 <6>[ 2.278280] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10674 11:42:21.947772 <6>[ 2.285169] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10675 11:42:21.954171 <6>[ 2.294309] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10676 11:42:21.963653 <6>[ 2.303468] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10677 11:42:21.973205 <6>[ 2.312781] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10678 11:42:21.983704 <6>[ 2.322257] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10679 11:42:21.993401 <6>[ 2.331730] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10680 11:42:22.003034 <6>[ 2.340857] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10681 11:42:22.009663 <6>[ 2.350334] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10682 11:42:22.019656 <6>[ 2.359462] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10683 11:42:22.029649 <6>[ 2.368762] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10684 11:42:22.039179 <6>[ 2.378928] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10685 11:42:22.050871 <6>[ 2.391272] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10686 11:42:22.057848 <6>[ 2.401204] Trying to probe devices needed for running init ...
10687 11:42:22.074701 <6>[ 2.415020] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10688 11:42:22.101957 <6>[ 2.445498] hub 2-1:1.0: USB hub found
10689 11:42:22.105281 <6>[ 2.449904] hub 2-1:1.0: 3 ports detected
10690 11:42:22.226444 <6>[ 2.567013] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10691 11:42:22.381377 <6>[ 2.724694] hub 1-1:1.0: USB hub found
10692 11:42:22.384571 <6>[ 2.729163] hub 1-1:1.0: 4 ports detected
10693 11:42:22.463064 <6>[ 2.803260] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10694 11:42:22.707235 <6>[ 3.047018] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10695 11:42:22.839775 <6>[ 3.183118] hub 1-1.4:1.0: USB hub found
10696 11:42:22.842534 <6>[ 3.187771] hub 1-1.4:1.0: 2 ports detected
10697 11:42:23.139454 <6>[ 3.479013] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10698 11:42:23.330915 <6>[ 3.671015] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10699 11:42:34.351877 <6>[ 14.699569] ALSA device list:
10700 11:42:34.358221 <6>[ 14.702825] No soundcards found.
10701 11:42:34.370557 <6>[ 14.715254] Freeing unused kernel memory: 8384K
10702 11:42:34.373829 <6>[ 14.720176] Run /init as init process
10703 11:42:34.385185 Loading, please wait...
10704 11:42:34.404214 Starting version 247.3-7+deb11u2
10705 11:42:34.722756 <6>[ 15.063554] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10706 11:42:34.734939 <6>[ 15.079203] remoteproc remoteproc0: scp is available
10707 11:42:34.744824 <4>[ 15.085755] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10708 11:42:34.751175 <6>[ 15.095717] remoteproc remoteproc0: powering up scp
10709 11:42:34.761213 <4>[ 15.100912] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10710 11:42:34.767632 <3>[ 15.110751] remoteproc remoteproc0: request_firmware failed: -2
10711 11:42:34.785789 <6>[ 15.126727] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10712 11:42:34.795249 <6>[ 15.134655] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10713 11:42:34.802314 <3>[ 15.134679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 11:42:34.812099 <6>[ 15.143639] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10715 11:42:34.818279 <3>[ 15.151473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 11:42:34.828361 <3>[ 15.151485] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 11:42:34.840496 <4>[ 15.181844] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10718 11:42:34.847472 <3>[ 15.189473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 11:42:34.853682 <4>[ 15.193278] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10720 11:42:34.860658 <6>[ 15.194582] mc: Linux media interface: v0.10
10721 11:42:34.867023 <3>[ 15.197630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 11:42:34.876647 <6>[ 15.211369] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10723 11:42:34.883369 <3>[ 15.217582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 11:42:34.894011 <3>[ 15.217614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 11:42:34.900806 <3>[ 15.217635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 11:42:34.907299 <3>[ 15.217871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 11:42:34.917185 <3>[ 15.217946] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 11:42:34.924127 <6>[ 15.220284] usbcore: registered new interface driver r8152
10729 11:42:34.926545 <6>[ 15.234527] videodev: Linux video capture interface: v2.00
10730 11:42:34.937399 <4>[ 15.236963] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10731 11:42:34.941021 <4>[ 15.236963] Fallback method does not support PEC.
10732 11:42:34.950656 <3>[ 15.241712] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 11:42:34.957083 <3>[ 15.241721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 11:42:34.967024 <3>[ 15.241970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 11:42:34.973742 <3>[ 15.253578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10736 11:42:34.983572 <3>[ 15.257935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 11:42:34.989743 <3>[ 15.257947] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 11:42:34.999654 <3>[ 15.257975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 11:42:35.006481 <3>[ 15.257987] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 11:42:35.016921 <3>[ 15.258102] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 11:42:35.022876 <6>[ 15.285232] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10742 11:42:35.029523 <3>[ 15.288100] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10743 11:42:35.039601 <6>[ 15.299074] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10744 11:42:35.042917 <6>[ 15.299459] pci_bus 0000:00: root bus resource [bus 00-ff]
10745 11:42:35.052569 <6>[ 15.321165] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10746 11:42:35.059274 <6>[ 15.324597] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10747 11:42:35.069240 <6>[ 15.335738] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10748 11:42:35.078947 <4>[ 15.336425] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10749 11:42:35.089026 <4>[ 15.336434] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10750 11:42:35.098667 <6>[ 15.340497] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10751 11:42:35.105665 <6>[ 15.348965] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10752 11:42:35.112217 <6>[ 15.356695] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10753 11:42:35.115638 <6>[ 15.382867] r8152 2-1.3:1.0 eth0: v1.12.13
10754 11:42:35.125793 <6>[ 15.387581] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10755 11:42:35.131637 <6>[ 15.388108] usbcore: registered new interface driver cdc_ether
10756 11:42:35.135138 <6>[ 15.393660] usbcore: registered new interface driver r8153_ecm
10757 11:42:35.142018 <6>[ 15.402740] pci 0000:00:00.0: supports D1 D2
10758 11:42:35.145097 <6>[ 15.410671] Bluetooth: Core ver 2.22
10759 11:42:35.151922 <6>[ 15.419674] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10760 11:42:35.158061 <6>[ 15.419862] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10761 11:42:35.164813 <6>[ 15.421454] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10762 11:42:35.174780 <6>[ 15.421766] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10763 11:42:35.178057 <6>[ 15.421904] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10764 11:42:35.188164 <6>[ 15.421933] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10765 11:42:35.194637 <6>[ 15.421953] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10766 11:42:35.200662 <6>[ 15.421970] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10767 11:42:35.207626 <6>[ 15.422085] pci 0000:01:00.0: supports D1 D2
10768 11:42:35.213788 <6>[ 15.422089] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10769 11:42:35.217547 <6>[ 15.428992] NET: Registered PF_BLUETOOTH protocol family
10770 11:42:35.227455 <6>[ 15.430888] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10771 11:42:35.233608 <6>[ 15.430918] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10772 11:42:35.240564 <6>[ 15.430926] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10773 11:42:35.250326 <6>[ 15.430939] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10774 11:42:35.257034 <6>[ 15.430955] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10775 11:42:35.267000 <6>[ 15.430971] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10776 11:42:35.270220 <6>[ 15.430986] pci 0000:00:00.0: PCI bridge to [bus 01]
10777 11:42:35.280501 <6>[ 15.430994] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10778 11:42:35.286439 <6>[ 15.431150] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10779 11:42:35.289890 <6>[ 15.431992] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10780 11:42:35.296411 <6>[ 15.432324] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10781 11:42:35.310192 <6>[ 15.438615] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10782 11:42:35.316286 <6>[ 15.446907] Bluetooth: HCI device and connection manager initialized
10783 11:42:35.319597 <6>[ 15.446926] Bluetooth: HCI socket layer initialized
10784 11:42:35.326251 <6>[ 15.446945] Bluetooth: L2CAP socket layer initialized
10785 11:42:35.333453 <6>[ 15.456260] usbcore: registered new interface driver uvcvideo
10786 11:42:35.336732 <6>[ 15.462245] Bluetooth: SCO socket layer initialized
10787 11:42:35.342623 <6>[ 15.463024] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10788 11:42:35.354064 <6>[ 15.698959] usbcore: registered new interface driver btusb
10789 11:42:35.364523 <4>[ 15.699950] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10790 11:42:35.370880 <3>[ 15.715317] Bluetooth: hci0: Failed to load firmware file (-2)
10791 11:42:35.377499 <3>[ 15.721407] Bluetooth: hci0: Failed to set up firmware (-2)
10792 11:42:35.387187 <4>[ 15.727521] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10793 11:42:35.397199 <5>[ 15.732776] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10794 11:42:35.416056 <5>[ 15.757138] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10795 11:42:35.422432 <4>[ 15.764128] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10796 11:42:35.428839 <6>[ 15.773012] cfg80211: failed to load regulatory.db
10797 11:42:35.474265 <6>[ 15.815609] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10798 11:42:35.480830 <6>[ 15.823193] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10799 11:42:35.505695 <6>[ 15.849995] mt7921e 0000:01:00.0: ASIC revision: 79610010
10800 11:42:35.613174 <4>[ 15.951368] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 11:42:35.616302 Begin: Loading essential drivers ... done.
10802 11:42:35.622660 Begin: Running /scripts/init-premount ... done.
10803 11:42:35.629463 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10804 11:42:35.636152 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10805 11:42:35.642296 Device /sys/class/net/enx0024323078ff found
10806 11:42:35.642399 done.
10807 11:42:35.697429 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10808 11:42:35.735098 <4>[ 16.073368] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 11:42:35.854721 <4>[ 16.192833] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 11:42:35.970039 <4>[ 16.308647] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 11:42:36.086448 <4>[ 16.424558] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 11:42:36.202138 <4>[ 16.540447] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 11:42:36.318312 <4>[ 16.656515] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 11:42:36.433804 <4>[ 16.772418] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 11:42:36.549930 <4>[ 16.888367] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 11:42:36.665624 <4>[ 17.004331] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 11:42:36.685503 <6>[ 17.030796] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10818 11:42:36.772977 <3>[ 17.118143] mt7921e 0000:01:00.0: hardware init failed
10819 11:42:36.794938 IP-Config: no response after 2 secs - giving up
10820 11:42:36.828964 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10821 11:42:36.832464 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10822 11:42:36.839302 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10823 11:42:36.849479 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10824 11:42:36.855401 host : mt8192-asurada-spherion-r0-cbg-8
10825 11:42:36.861875 domain : lava-rack
10826 11:42:36.865491 rootserver: 192.168.201.1 rootpath:
10827 11:42:36.865676 filename :
10828 11:42:36.889796 done.
10829 11:42:36.898216 Begin: Running /scripts/nfs-bottom ... done.
10830 11:42:36.915286 Begin: Running /scripts/init-bottom ... done.
10831 11:42:38.048968 <6>[ 18.394359] NET: Registered PF_INET6 protocol family
10832 11:42:38.055913 <6>[ 18.401242] Segment Routing with IPv6
10833 11:42:38.058810 <6>[ 18.405232] In-situ OAM (IOAM) with IPv6
10834 11:42:38.173900 <30>[ 18.499409] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10835 11:42:38.177282 <30>[ 18.523226] systemd[1]: Detected architecture arm64.
10836 11:42:38.196756
10837 11:42:38.199952 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10838 11:42:38.200141
10839 11:42:38.215643 <30>[ 18.561250] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10840 11:42:38.780344 <30>[ 19.122514] systemd[1]: Queued start job for default target Graphical Interface.
10841 11:42:38.818709 <30>[ 19.164099] systemd[1]: Created slice system-getty.slice.
10842 11:42:38.825239 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10843 11:42:38.841949 <30>[ 19.187577] systemd[1]: Created slice system-modprobe.slice.
10844 11:42:38.848539 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10845 11:42:38.867136 <30>[ 19.212160] systemd[1]: Created slice system-serial\x2dgetty.slice.
10846 11:42:38.876896 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10847 11:42:38.890173 <30>[ 19.235522] systemd[1]: Created slice User and Session Slice.
10848 11:42:38.896742 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10849 11:42:38.917350 <30>[ 19.259594] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10850 11:42:38.927200 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10851 11:42:38.945022 <30>[ 19.287193] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10852 11:42:38.951686 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10853 11:42:38.972465 <30>[ 19.311116] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10854 11:42:38.978937 <30>[ 19.323155] systemd[1]: Reached target Local Encrypted Volumes.
10855 11:42:38.985918 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10856 11:42:39.001673 <30>[ 19.347092] systemd[1]: Reached target Paths.
10857 11:42:39.004975 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10858 11:42:39.021957 <30>[ 19.367056] systemd[1]: Reached target Remote File Systems.
10859 11:42:39.028125 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10860 11:42:39.041584 <30>[ 19.387036] systemd[1]: Reached target Slices.
10861 11:42:39.048116 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10862 11:42:39.061573 <30>[ 19.407059] systemd[1]: Reached target Swap.
10863 11:42:39.064795 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10864 11:42:39.085163 <30>[ 19.427303] systemd[1]: Listening on initctl Compatibility Named Pipe.
10865 11:42:39.091636 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10866 11:42:39.098480 <30>[ 19.442694] systemd[1]: Listening on Journal Audit Socket.
10867 11:42:39.104696 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10868 11:42:39.118552 <30>[ 19.463937] systemd[1]: Listening on Journal Socket (/dev/log).
10869 11:42:39.124837 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10870 11:42:39.142872 <30>[ 19.487828] systemd[1]: Listening on Journal Socket.
10871 11:42:39.149326 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10872 11:42:39.166341 <30>[ 19.508380] systemd[1]: Listening on Network Service Netlink Socket.
10873 11:42:39.172864 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10874 11:42:39.188297 <30>[ 19.533620] systemd[1]: Listening on udev Control Socket.
10875 11:42:39.194522 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10876 11:42:39.209950 <30>[ 19.555242] systemd[1]: Listening on udev Kernel Socket.
10877 11:42:39.216644 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10878 11:42:39.265903 <30>[ 19.611314] systemd[1]: Mounting Huge Pages File System...
10879 11:42:39.272309 Mounting [0;1;39mHuge Pages File System[0m...
10880 11:42:39.288147 <30>[ 19.633295] systemd[1]: Mounting POSIX Message Queue File System...
10881 11:42:39.294310 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10882 11:42:39.312235 <30>[ 19.657734] systemd[1]: Mounting Kernel Debug File System...
10883 11:42:39.318800 Mounting [0;1;39mKernel Debug File System[0m...
10884 11:42:39.337013 <30>[ 19.679359] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10885 11:42:39.354269 <30>[ 19.696342] systemd[1]: Starting Create list of static device nodes for the current kernel...
10886 11:42:39.360923 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10887 11:42:39.380358 <30>[ 19.725683] systemd[1]: Starting Load Kernel Module configfs...
10888 11:42:39.386672 Starting [0;1;39mLoad Kernel Module configfs[0m...
10889 11:42:39.403869 <30>[ 19.749634] systemd[1]: Starting Load Kernel Module drm...
10890 11:42:39.410425 Starting [0;1;39mLoad Kernel Module drm[0m...
10891 11:42:39.428264 <30>[ 19.773640] systemd[1]: Starting Load Kernel Module fuse...
10892 11:42:39.434680 Starting [0;1;39mLoad Kernel Module fuse[0m...
10893 11:42:39.467174 <6>[ 19.812228] fuse: init (API version 7.37)
10894 11:42:39.476549 <30>[ 19.817629] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10895 11:42:39.530399 <30>[ 19.875518] systemd[1]: Starting Journal Service...
10896 11:42:39.533052 Starting [0;1;39mJournal Service[0m...
10897 11:42:39.557879 <30>[ 19.902974] systemd[1]: Starting Load Kernel Modules...
10898 11:42:39.563947 Starting [0;1;39mLoad Kernel Modules[0m...
10899 11:42:39.583286 <30>[ 19.925219] systemd[1]: Starting Remount Root and Kernel File Systems...
10900 11:42:39.589594 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10901 11:42:39.604776 <30>[ 19.950068] systemd[1]: Starting Coldplug All udev Devices...
10902 11:42:39.610954 Starting [0;1;39mColdplug All udev Devices[0m...
10903 11:42:39.629060 <30>[ 19.974492] systemd[1]: Mounted Huge Pages File System.
10904 11:42:39.635400 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10905 11:42:39.649939 <30>[ 19.995408] systemd[1]: Mounted POSIX Message Queue File System.
10906 11:42:39.656546 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10907 11:42:39.673870 <30>[ 20.019498] systemd[1]: Mounted Kernel Debug File System.
10908 11:42:39.680605 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10909 11:42:39.698566 <3>[ 20.040815] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 11:42:39.708808 <30>[ 20.050834] systemd[1]: Finished Create list of static device nodes for the current kernel.
10911 11:42:39.719288 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10912 11:42:39.728851 <3>[ 20.070722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 11:42:39.735610 <30>[ 20.080675] systemd[1]: modprobe@configfs.service: Succeeded.
10914 11:42:39.742302 <30>[ 20.087455] systemd[1]: Finished Load Kernel Module configfs.
10915 11:42:39.748884 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10916 11:42:39.766671 <30>[ 20.112000] systemd[1]: modprobe@drm.service: Succeeded.
10917 11:42:39.777127 <3>[ 20.117546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 11:42:39.783270 <30>[ 20.118299] systemd[1]: Finished Load Kernel Module drm.
10919 11:42:39.786549 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10920 11:42:39.804679 <3>[ 20.147026] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:42:39.811648 <30>[ 20.147890] systemd[1]: modprobe@fuse.service: Succeeded.
10922 11:42:39.818386 <30>[ 20.162535] systemd[1]: Finished Load Kernel Module fuse.
10923 11:42:39.824763 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10924 11:42:39.834941 <3>[ 20.177031] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:42:39.842021 <30>[ 20.187388] systemd[1]: Finished Load Kernel Modules.
10926 11:42:39.848283 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10927 11:42:39.863923 <3>[ 20.206294] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 11:42:39.875053 <30>[ 20.217143] systemd[1]: Finished Remount Root and Kernel File Systems.
10929 11:42:39.881234 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10930 11:42:39.894143 <3>[ 20.236024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 11:42:39.918114 <30>[ 20.263127] systemd[1]: Mounting FUSE Control File System...
10932 11:42:39.927813 <3>[ 20.268238] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 11:42:39.934824 Mounting [0;1;39mFUSE Control File System[0m...
10934 11:42:39.948653 <30>[ 20.293553] systemd[1]: Mounting Kernel Configuration File System...
10935 11:42:39.958744 <3>[ 20.299234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 11:42:39.964720 Mounting [0;1;39mKernel Configuration File System[0m...
10937 11:42:39.986963 <3>[ 20.329393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 11:42:39.997213 <30>[ 20.332288] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10939 11:42:40.007891 <30>[ 20.347178] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10940 11:42:40.017390 <3>[ 20.359246] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 11:42:40.042618 <30>[ 20.387623] systemd[1]: Starting Load/Save Random Seed...
10942 11:42:40.052244 <3>[ 20.393255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10943 11:42:40.055907 Starting [0;1;39mLoad/Save Random Seed[0m...
10944 11:42:40.073432 <30>[ 20.418712] systemd[1]: Starting Apply Kernel Variables...
10945 11:42:40.084220 <3>[ 20.419552] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 11:42:40.096905 Starting [0;1;39mApply Kernel Variable<3>[ 20.436571] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 11:42:40.097086 s[0m...
10948 11:42:40.117498 <30>[ 20.462678] systemd[1]: Starting Create System Users...
10949 11:42:40.124404 Starting [0;1;39mCreate System Users[0m...
10950 11:42:40.134233 <3>[ 20.476776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 11:42:40.142623 <30>[ 20.487483] systemd[1]: Mounted FUSE Control File System.
10952 11:42:40.156255 [[0;32m OK [0m] Mounted [0;1;39mFUSE Contro<3>[ 20.496096] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 11:42:40.172917 l File System[0<4>[ 20.506380] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10954 11:42:40.173106 m.
10955 11:42:40.182747 <3>[ 20.517011] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 11:42:40.189690 <3>[ 20.523362] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10957 11:42:40.196145 <30>[ 20.541146] systemd[1]: Mounted Kernel Configuration File System.
10958 11:42:40.202925 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10959 11:42:40.221601 <29>[ 20.563479] systemd[1]: systemd-udev-trigger.service: Main process exited, code=exited, status=1/FAILURE
10960 11:42:40.231748 <28>[ 20.573699] systemd[1]: systemd-udev-trigger.service: Failed with result 'exit-code'.
10961 11:42:40.238239 <27>[ 20.582483] systemd[1]: Failed to start Coldplug All udev Devices.
10962 11:42:40.245019 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10963 11:42:40.261774 See 'systemctl status systemd-udev-trigger.service' for details.
10964 11:42:40.278645 <30>[ 20.623885] systemd[1]: Finished Load/Save Random Seed.
10965 11:42:40.285284 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10966 11:42:40.303070 <30>[ 20.647828] systemd[1]: Finished Apply Kernel Variables.
10967 11:42:40.309689 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10968 11:42:40.325999 <30>[ 20.671552] systemd[1]: Started Journal Service.
10969 11:42:40.332305 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10970 11:42:40.347528 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10971 11:42:40.390751 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10972 11:42:40.407878 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10973 11:42:40.458441 <46>[ 20.800493] systemd-journald[294]: Received client request to flush runtime journal.
10974 11:42:40.496168 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10975 11:42:40.510384 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10976 11:42:40.525605 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10977 11:42:40.581440 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10978 11:42:41.342748 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10979 11:42:41.419252 Starting [0;1;39mNetwork Service[0m...
10980 11:42:41.762512 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10981 11:42:41.785369 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10982 11:42:41.837083 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10983 11:42:42.166966 <6>[ 22.512588] remoteproc remoteproc0: powering up scp
10984 11:42:42.198196 <4>[ 22.540553] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10985 11:42:42.204674 <3>[ 22.550463] remoteproc remoteproc0: request_firmware failed: -2
10986 11:42:42.214053 <3>[ 22.556653] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10987 11:42:42.242583 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10988 11:42:42.260982 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10989 11:42:42.302066 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10990 11:42:42.322181 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10991 11:42:42.454458 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10992 11:42:42.485912 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10993 11:42:42.572900 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10994 11:42:42.683136 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10995 11:42:43.254824 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10996 11:42:43.309505 Starting [0;1;39mNetwork Name Resolution[0m...
10997 11:42:43.333836 Starting [0;1;39mNetwork Time Synchronization[0m...
10998 11:42:43.352127 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10999 11:42:43.577613 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11000 11:42:43.593931 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11001 11:42:43.609193 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11002 11:42:43.952021 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11003 11:42:43.974697 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11004 11:42:43.993789 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11005 11:42:44.014932 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11006 11:42:44.037392 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11007 11:42:44.062529 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11008 11:42:44.086126 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11009 11:42:44.106823 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11010 11:42:44.127318 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11011 11:42:44.145139 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11012 11:42:44.158693 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11013 11:42:44.180056 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11014 11:42:44.191663 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11015 11:42:44.207983 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11016 11:42:44.241180 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11017 11:42:44.272329 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11018 11:42:44.397731 Starting [0;1;39mUser Login Management[0m...
11019 11:42:44.416297 Starting [0;1;39mPermit User Sessions[0m...
11020 11:42:44.571631 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11021 11:42:44.603379 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11022 11:42:44.623615 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11023 11:42:44.640339 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11024 11:42:44.661616 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11025 11:42:44.679200 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11026 11:42:44.698408 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11027 11:42:44.714151 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11028 11:42:44.755111 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11029 11:42:45.286119 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11030 11:42:46.178824
11031 11:42:46.179093
11032 11:42:46.182029 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11033 11:42:46.182138
11034 11:42:46.185215 debian-bullseye-arm64 login: root (automatic login)
11035 11:42:46.185325
11036 11:42:46.185421
11037 11:42:46.516967 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
11038 11:42:46.517172
11039 11:42:46.523556 The programs included with the Debian GNU/Linux system are free software;
11040 11:42:46.530218 the exact distribution terms for each program are described in the
11041 11:42:46.533667 individual files in /usr/share/doc/*/copyright.
11042 11:42:46.533799
11043 11:42:46.540425 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11044 11:42:46.543179 permitted by applicable law.
11045 11:42:51.130490 Matched prompt #10: / #
11047 11:42:51.130815 Setting prompt string to ['/ #']
11048 11:42:51.130931 end: 2.2.5.1 login-action (duration 00:00:32) [common]
11050 11:42:51.131143 end: 2.2.5 auto-login-action (duration 00:00:32) [common]
11051 11:42:51.131237 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
11052 11:42:51.131312 Setting prompt string to ['/ #']
11053 11:42:51.131375 Forcing a shell prompt, looking for ['/ #']
11055 11:42:51.181613 / #
11056 11:42:51.181816 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11057 11:42:51.181902 Waiting using forced prompt support (timeout 00:02:30)
11058 11:42:51.186751
11059 11:42:51.187141 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11060 11:42:51.187249 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
11062 11:42:51.287654 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742234/extract-nfsrootfs-751xmu20'
11063 11:42:51.292472 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742234/extract-nfsrootfs-751xmu20'
11065 11:42:51.393165 / # export NFS_SERVER_IP='192.168.201.1'
11066 11:42:51.398117 export NFS_SERVER_IP='192.168.201.1'
11067 11:42:51.398530 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11068 11:42:51.398685 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11069 11:42:51.398815 end: 2 depthcharge-action (duration 00:01:50) [common]
11070 11:42:51.398939 start: 3 lava-test-retry (timeout 00:07:18) [common]
11071 11:42:51.399029 start: 3.1 lava-test-shell (timeout 00:07:18) [common]
11072 11:42:51.399135 Using namespace: common
11074 11:42:51.499503 / # #
11075 11:42:51.499685 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11076 11:42:51.504247 #
11077 11:42:51.504518 Using /lava-10742234
11079 11:42:51.604893 / # export SHELL=/bin/bash
11080 11:42:51.609956 export SHELL=/bin/bash
11082 11:42:51.710617 / # . /lava-10742234/environment
11083 11:42:51.715757 . /lava-10742234/environment
11085 11:42:51.821367 / # /lava-10742234/bin/lava-test-runner /lava-10742234/0
11086 11:42:51.821609 Test shell timeout: 10s (minimum of the action and connection timeout)
11087 11:42:51.827186 /lava-10742234/bin/lava-test-runner /lava-10742234/0
11088 11:42:52.098909 + export TESTRUN_ID=0_timesync-off
11089 11:42:52.102072 + TESTRUN_ID=0_timesync-off
11090 11:42:52.105173 + cd /lava-10742234/0/tests/0_timesync-off
11091 11:42:52.108869 ++ cat uuid
11092 11:42:52.112083 + UUID=10742234_1.6.2.3.1
11093 11:42:52.112214 + set +x
11094 11:42:52.118656 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10742234_1.6.2.3.1>
11095 11:42:52.119066 Received signal: <STARTRUN> 0_timesync-off 10742234_1.6.2.3.1
11096 11:42:52.119191 Starting test lava.0_timesync-off (10742234_1.6.2.3.1)
11097 11:42:52.119343 Skipping test definition patterns.
11098 11:42:52.121957 + systemctl stop systemd-timesyncd
11099 11:42:52.156171 + set +x
11100 11:42:52.159601 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10742234_1.6.2.3.1>
11101 11:42:52.160010 Received signal: <ENDRUN> 0_timesync-off 10742234_1.6.2.3.1
11102 11:42:52.160166 Ending use of test pattern.
11103 11:42:52.160276 Ending test lava.0_timesync-off (10742234_1.6.2.3.1), duration 0.04
11105 11:42:52.234004 + export TESTRUN_ID=1_kselftest-tpm2
11106 11:42:52.237607 + TESTRUN_ID=1_kselftest-tpm2
11107 11:42:52.244009 + cd /lava-10742234/0/tests/1_kselftest-tpm2
11108 11:42:52.244195 ++ cat uuid
11109 11:42:52.247514 + UUID=10742234_1.6.2.3.5
11110 11:42:52.247640 + set +x
11111 11:42:52.254005 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10742234_1.6.2.3.5>
11112 11:42:52.254365 Received signal: <STARTRUN> 1_kselftest-tpm2 10742234_1.6.2.3.5
11113 11:42:52.254504 Starting test lava.1_kselftest-tpm2 (10742234_1.6.2.3.5)
11114 11:42:52.254652 Skipping test definition patterns.
11115 11:42:52.256891 + cd ./automated/linux/kselftest/
11116 11:42:52.283426 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11117 11:42:52.468924 INFO: install_deps skipped
11118 11:42:52.580940 --2023-06-15 11:42:52-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11119 11:42:52.583916 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11120 11:42:52.714762 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11121 11:42:52.843586 HTTP request sent, awaiting response... 200 OK
11122 11:42:52.846674 Length: 2884276 (2.8M) [application/octet-stream]
11123 11:42:52.849935 Saving to: 'kselftest.tar.xz'
11124 11:42:52.850074
11125 11:42:52.850202
11126 11:42:53.101706 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11127 11:42:53.359763 kselftest.tar.xz 1%[ ] 47.81K 188KB/s
11128 11:42:53.639149 kselftest.tar.xz 7%[> ] 217.50K 426KB/s
11129 11:42:53.879207 kselftest.tar.xz 20%[===> ] 564.87K 717KB/s
11130 11:42:54.137003 kselftest.tar.xz 62%[===========> ] 1.72M 1.68MB/s
11131 11:42:54.159329 kselftest.tar.xz 92%[=================> ] 2.54M 1.98MB/s
11132 11:42:54.165421 kselftest.tar.xz 100%[===================>] 2.75M 2.11MB/s in 1.3s
11133 11:42:54.165530
11134 11:42:54.427912 2023-06-15 11:42:54 (2.11 MB/s) - 'kselftest.tar.xz' saved [2884276/2884276]
11135 11:42:54.428630
11136 11:43:06.010014 <6>[ 46.361913] vpu: disabling
11137 11:43:06.013622 <6>[ 46.364963] vproc2: disabling
11138 11:43:06.016599 <6>[ 46.368243] vproc1: disabling
11139 11:43:06.019811 <6>[ 46.371502] vaud18: disabling
11140 11:43:06.026776 <6>[ 46.374907] vsram_others: disabling
11141 11:43:06.029672 <6>[ 46.378779] va09: disabling
11142 11:43:06.033179 <6>[ 46.381884] vsram_md: disabling
11143 11:43:06.036392 <6>[ 46.385369] Vgpu: disabling
11144 11:43:44.057252 skiplist:
11145 11:43:44.060772 ========================================
11146 11:43:44.064073 ========================================
11147 11:43:44.124450 tpm2:test_smoke.sh
11148 11:43:44.127894 tpm2:test_space.sh
11149 11:43:44.170664 ============== Tests to run ===============
11150 11:43:44.173861 tpm2:test_smoke.sh
11151 11:43:44.173940 tpm2:test_space.sh
11152 11:43:44.177333 ===========End Tests to run ===============
11153 11:43:44.310992 <12>[ 84.663629] kselftest: Running tests in tpm2
11154 11:43:44.320343 TAP version 13
11155 11:43:44.334061 1..2
11156 11:43:44.368190 # selftests: tpm2: test_smoke.sh
11157 11:43:46.978111 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11158 11:43:46.981392 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11159 11:43:46.988122 # Exception ignored in: <function Client.__del__ at 0xffffbeb6fd30>
11160 11:43:46.990888 # Traceback (most recent call last):
11161 11:43:47.001213 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11162 11:43:47.004115 # if self.tpm:
11163 11:43:47.007296 # AttributeError: 'Client' object has no attribute 'tpm'
11164 11:43:47.014231 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11165 11:43:47.017307 # Exception ignored in: <function Client.__del__ at 0xffffbeb6fd30>
11166 11:43:47.020487 # Traceback (most recent call last):
11167 11:43:47.030856 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11168 11:43:47.034188 # if self.tpm:
11169 11:43:47.037333 # AttributeError: 'Client' object has no attribute 'tpm'
11170 11:43:47.043774 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11171 11:43:47.050815 # Exception ignored in: <function Client.__del__ at 0xffffbeb6fd30>
11172 11:43:47.053677 # Traceback (most recent call last):
11173 11:43:47.064056 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11174 11:43:47.064486 # if self.tpm:
11175 11:43:47.070289 # AttributeError: 'Client' object has no attribute 'tpm'
11176 11:43:47.073613 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11177 11:43:47.080034 # Exception ignored in: <function Client.__del__ at 0xffffbeb6fd30>
11178 11:43:47.083533 # Traceback (most recent call last):
11179 11:43:47.093652 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11180 11:43:47.096581 # if self.tpm:
11181 11:43:47.100553 # AttributeError: 'Client' object has no attribute 'tpm'
11182 11:43:47.107042 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11183 11:43:47.113188 # Exception ignored in: <function Client.__del__ at 0xffffbeb6fd30>
11184 11:43:47.116753 # Traceback (most recent call last):
11185 11:43:47.123348 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11186 11:43:47.126697 # if self.tpm:
11187 11:43:47.133211 # AttributeError: 'Client' object has no attribute 'tpm'
11188 11:43:47.136661 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11189 11:43:47.143157 # Exception ignored in: <function Client.__del__ at 0xffffbeb6fd30>
11190 11:43:47.146322 # Traceback (most recent call last):
11191 11:43:47.156212 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11192 11:43:47.156687 # if self.tpm:
11193 11:43:47.163214 # AttributeError: 'Client' object has no attribute 'tpm'
11194 11:43:47.166720 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11195 11:43:47.173022 # Exception ignored in: <function Client.__del__ at 0xffffbeb6fd30>
11196 11:43:47.176609 # Traceback (most recent call last):
11197 11:43:47.186446 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11198 11:43:47.189367 # if self.tpm:
11199 11:43:47.192468 # AttributeError: 'Client' object has no attribute 'tpm'
11200 11:43:47.199309 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11201 11:43:47.206225 # Exception ignored in: <function Client.__del__ at 0xffffbeb6fd30>
11202 11:43:47.209153 # Traceback (most recent call last):
11203 11:43:47.219821 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11204 11:43:47.220596 # if self.tpm:
11205 11:43:47.225750 # AttributeError: 'Client' object has no attribute 'tpm'
11206 11:43:47.226389 #
11207 11:43:47.232901 # ======================================================================
11208 11:43:47.239313 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11209 11:43:47.242423 # ----------------------------------------------------------------------
11210 11:43:47.245712 # Traceback (most recent call last):
11211 11:43:47.258900 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11212 11:43:47.262281 # self.root_key = self.client.create_root_key()
11213 11:43:47.272159 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11214 11:43:47.279002 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11215 11:43:47.289290 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11216 11:43:47.289768 # raise ProtocolError(cc, rc)
11217 11:43:47.296115 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11218 11:43:47.296545 #
11219 11:43:47.302607 # ======================================================================
11220 11:43:47.309874 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11221 11:43:47.315982 # ----------------------------------------------------------------------
11222 11:43:47.319921 # Traceback (most recent call last):
11223 11:43:47.329346 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11224 11:43:47.332622 # self.client = tpm2.Client()
11225 11:43:47.342432 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11226 11:43:47.346378 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11227 11:43:47.352805 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11228 11:43:47.353594 #
11229 11:43:47.359545 # ======================================================================
11230 11:43:47.362649 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11231 11:43:47.369000 # ----------------------------------------------------------------------
11232 11:43:47.372258 # Traceback (most recent call last):
11233 11:43:47.382079 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11234 11:43:47.385532 # self.client = tpm2.Client()
11235 11:43:47.395552 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11236 11:43:47.398333 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11237 11:43:47.404869 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11238 11:43:47.405020 #
11239 11:43:47.411902 # ======================================================================
11240 11:43:47.418434 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11241 11:43:47.425174 # ----------------------------------------------------------------------
11242 11:43:47.428763 # Traceback (most recent call last):
11243 11:43:47.438494 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11244 11:43:47.439234 # self.client = tpm2.Client()
11245 11:43:47.448313 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11246 11:43:47.455531 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11247 11:43:47.461843 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11248 11:43:47.462316 #
11249 11:43:47.468498 # ======================================================================
11250 11:43:47.471205 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11251 11:43:47.478025 # ----------------------------------------------------------------------
11252 11:43:47.481520 # Traceback (most recent call last):
11253 11:43:47.491491 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11254 11:43:47.494929 # self.client = tpm2.Client()
11255 11:43:47.504146 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11256 11:43:47.510734 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11257 11:43:47.514377 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11258 11:43:47.514871 #
11259 11:43:47.521262 # ======================================================================
11260 11:43:47.527397 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11261 11:43:47.531062 # ----------------------------------------------------------------------
11262 11:43:47.533967 # Traceback (most recent call last):
11263 11:43:47.547153 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11264 11:43:47.547340 # self.client = tpm2.Client()
11265 11:43:47.556772 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11266 11:43:47.563567 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11267 11:43:47.570384 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11268 11:43:47.570520 #
11269 11:43:47.577271 # ======================================================================
11270 11:43:47.580245 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11271 11:43:47.587267 # ----------------------------------------------------------------------
11272 11:43:47.590648 # Traceback (most recent call last):
11273 11:43:47.600537 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11274 11:43:47.603852 # self.client = tpm2.Client()
11275 11:43:47.613781 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11276 11:43:47.616792 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11277 11:43:47.623697 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11278 11:43:47.624176 #
11279 11:43:47.630276 # ======================================================================
11280 11:43:47.633427 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11281 11:43:47.640348 # ----------------------------------------------------------------------
11282 11:43:47.643355 # Traceback (most recent call last):
11283 11:43:47.653464 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11284 11:43:47.658815 # self.client = tpm2.Client()
11285 11:43:47.669436 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11286 11:43:47.675755 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11287 11:43:47.678624 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11288 11:43:47.679124 #
11289 11:43:47.689829 # ======================================================================
11290 11:43:47.693903 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11291 11:43:47.701004 # ----------------------------------------------------------------------
11292 11:43:47.701475 # Traceback (most recent call last):
11293 11:43:47.711253 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11294 11:43:47.714442 # self.client = tpm2.Client()
11295 11:43:47.724105 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11296 11:43:47.727704 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11297 11:43:47.733847 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11298 11:43:47.734319 #
11299 11:43:47.740949 # ----------------------------------------------------------------------
11300 11:43:47.741444 # Ran 9 tests in 0.031s
11301 11:43:47.741821 #
11302 11:43:47.743961 # FAILED (errors=9)
11303 11:43:47.747473 # test_async (tpm2_tests.AsyncTest) ... ok
11304 11:43:47.753750 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11305 11:43:47.754267 #
11306 11:43:47.760708 # ----------------------------------------------------------------------
11307 11:43:47.761179 # Ran 2 tests in 0.034s
11308 11:43:47.764131 #
11309 11:43:47.764553 # OK
11310 11:43:47.767251 ok 1 selftests: tpm2: test_smoke.sh
11311 11:43:47.770348 # selftests: tpm2: test_space.sh
11312 11:43:47.773679 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11313 11:43:47.777025 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11314 11:43:47.783818 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11315 11:43:47.787114 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11316 11:43:47.787538 #
11317 11:43:47.793905 # ======================================================================
11318 11:43:47.800164 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11319 11:43:47.806927 # ----------------------------------------------------------------------
11320 11:43:47.809815 # Traceback (most recent call last):
11321 11:43:47.820055 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11322 11:43:47.822857 # root1 = space1.create_root_key()
11323 11:43:47.833438 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11324 11:43:47.839820 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11325 11:43:47.849414 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11326 11:43:47.852968 # raise ProtocolError(cc, rc)
11327 11:43:47.859618 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11328 11:43:47.859721 #
11329 11:43:47.866013 # ======================================================================
11330 11:43:47.868925 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11331 11:43:47.875519 # ----------------------------------------------------------------------
11332 11:43:47.879357 # Traceback (most recent call last):
11333 11:43:47.888671 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11334 11:43:47.892034 # space1.create_root_key()
11335 11:43:47.905385 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11336 11:43:47.908929 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11337 11:43:47.918459 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11338 11:43:47.921908 # raise ProtocolError(cc, rc)
11339 11:43:47.928529 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11340 11:43:47.928635 #
11341 11:43:47.935069 # ======================================================================
11342 11:43:47.938809 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11343 11:43:47.945074 # ----------------------------------------------------------------------
11344 11:43:47.948629 # Traceback (most recent call last):
11345 11:43:47.961718 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11346 11:43:47.965176 # root1 = space1.create_root_key()
11347 11:43:47.975275 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11348 11:43:47.978477 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11349 11:43:47.988420 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11350 11:43:47.991509 # raise ProtocolError(cc, rc)
11351 11:43:47.998286 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11352 11:43:47.998773 #
11353 11:43:48.004869 # ======================================================================
11354 11:43:48.011398 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11355 11:43:48.017895 # ----------------------------------------------------------------------
11356 11:43:48.021297 # Traceback (most recent call last):
11357 11:43:48.031414 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11358 11:43:48.034418 # root1 = space1.create_root_key()
11359 11:43:48.044666 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11360 11:43:48.050934 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11361 11:43:48.060884 # File "/lava-10742234/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11362 11:43:48.064243 # raise ProtocolError(cc, rc)
11363 11:43:48.070864 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11364 11:43:48.071364 #
11365 11:43:48.077527 # ----------------------------------------------------------------------
11366 11:43:48.078002 # Ran 4 tests in 0.062s
11367 11:43:48.078378 #
11368 11:43:48.080664 # FAILED (errors=4)
11369 11:43:48.084481 not ok 2 selftests: tpm2: test_space.sh # exit=1
11370 11:43:48.761345 tpm2_test_smoke_sh pass
11371 11:43:48.765102 tpm2_test_space_sh fail
11372 11:43:48.782591 + ../../utils/send-to-lava.sh ./output/result.txt
11373 11:43:48.855231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11374 11:43:48.856279 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11376 11:43:48.909049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11377 11:43:48.909578 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11379 11:43:48.912438 + set +x
11380 11:43:48.915284 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10742234_1.6.2.3.5>
11381 11:43:48.915712 Received signal: <ENDRUN> 1_kselftest-tpm2 10742234_1.6.2.3.5
11382 11:43:48.915947 Ending use of test pattern.
11383 11:43:48.916146 Ending test lava.1_kselftest-tpm2 (10742234_1.6.2.3.5), duration 56.66
11385 11:43:48.918676 <LAVA_TEST_RUNNER EXIT>
11386 11:43:48.919173 ok: lava_test_shell seems to have completed
11387 11:43:48.919449 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11388 11:43:48.919679 end: 3.1 lava-test-shell (duration 00:00:58) [common]
11389 11:43:48.919911 end: 3 lava-test-retry (duration 00:00:58) [common]
11390 11:43:48.920145 start: 4 finalize (timeout 00:06:21) [common]
11391 11:43:48.920389 start: 4.1 power-off (timeout 00:00:30) [common]
11392 11:43:48.920783 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11393 11:43:49.029829 >> Command sent successfully.
11394 11:43:49.041019 Returned 0 in 0 seconds
11395 11:43:49.142282 end: 4.1 power-off (duration 00:00:00) [common]
11397 11:43:49.143976 start: 4.2 read-feedback (timeout 00:06:20) [common]
11398 11:43:49.145150 Listened to connection for namespace 'common' for up to 1s
11399 11:43:50.145847 Finalising connection for namespace 'common'
11400 11:43:50.146523 Disconnecting from shell: Finalise
11401 11:43:50.147134 / #
11402 11:43:50.248108 end: 4.2 read-feedback (duration 00:00:01) [common]
11403 11:43:50.248813 end: 4 finalize (duration 00:00:01) [common]
11404 11:43:50.249430 Cleaning after the job
11405 11:43:50.249941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/ramdisk
11406 11:43:50.261285 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/kernel
11407 11:43:50.291048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/dtb
11408 11:43:50.291425 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/nfsrootfs
11409 11:43:50.365663 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742234/tftp-deploy-rew3k99n/modules
11410 11:43:50.371288 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742234
11411 11:43:50.895763 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742234
11412 11:43:50.895974 Job finished correctly