Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
- Errors: 0
1 11:40:00.478409 lava-dispatcher, installed at version: 2023.05.1
2 11:40:00.478695 start: 0 validate
3 11:40:00.478849 Start time: 2023-06-15 11:40:00.478840+00:00 (UTC)
4 11:40:00.478988 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:40:00.479123 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230609.0%2Farm64%2Finitrd.cpio.gz exists
6 11:40:00.803416 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:40:00.803631 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:40:18.026705 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:40:18.026879 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:40:18.299245 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:40:18.299406 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230609.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:40:18.831431 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:40:18.831587 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:40:22.831800 validate duration: 22.35
16 11:40:22.832070 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:40:22.832188 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:40:22.832300 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:40:22.832429 Not decompressing ramdisk as can be used compressed.
20 11:40:22.832518 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230609.0/arm64/initrd.cpio.gz
21 11:40:22.832583 saving as /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/ramdisk/initrd.cpio.gz
22 11:40:22.832644 total size: 4665406 (4MB)
23 11:40:23.091185 progress 0% (0MB)
24 11:40:23.093501 progress 5% (0MB)
25 11:40:23.095512 progress 10% (0MB)
26 11:40:23.097563 progress 15% (0MB)
27 11:40:23.099560 progress 20% (0MB)
28 11:40:23.101583 progress 25% (1MB)
29 11:40:23.103560 progress 30% (1MB)
30 11:40:23.105590 progress 35% (1MB)
31 11:40:23.107570 progress 40% (1MB)
32 11:40:23.109848 progress 45% (2MB)
33 11:40:23.111831 progress 50% (2MB)
34 11:40:23.113865 progress 55% (2MB)
35 11:40:23.115839 progress 60% (2MB)
36 11:40:23.117874 progress 65% (2MB)
37 11:40:23.119852 progress 70% (3MB)
38 11:40:23.121883 progress 75% (3MB)
39 11:40:23.123855 progress 80% (3MB)
40 11:40:23.126145 progress 85% (3MB)
41 11:40:23.128137 progress 90% (4MB)
42 11:40:23.130170 progress 95% (4MB)
43 11:40:23.132167 progress 100% (4MB)
44 11:40:23.132395 4MB downloaded in 0.30s (14.84MB/s)
45 11:40:23.132617 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:40:23.133045 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:40:23.133178 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:40:23.133302 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:40:23.133487 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:40:23.133602 saving as /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/kernel/Image
52 11:40:23.133703 total size: 47581696 (45MB)
53 11:40:23.133797 No compression specified
54 11:40:23.135292 progress 0% (0MB)
55 11:40:23.154153 progress 5% (2MB)
56 11:40:23.166436 progress 10% (4MB)
57 11:40:23.178494 progress 15% (6MB)
58 11:40:23.190937 progress 20% (9MB)
59 11:40:23.203210 progress 25% (11MB)
60 11:40:23.215252 progress 30% (13MB)
61 11:40:23.227433 progress 35% (15MB)
62 11:40:23.239405 progress 40% (18MB)
63 11:40:23.251471 progress 45% (20MB)
64 11:40:23.263761 progress 50% (22MB)
65 11:40:23.276006 progress 55% (24MB)
66 11:40:23.288273 progress 60% (27MB)
67 11:40:23.300404 progress 65% (29MB)
68 11:40:23.312479 progress 70% (31MB)
69 11:40:23.324528 progress 75% (34MB)
70 11:40:23.336450 progress 80% (36MB)
71 11:40:23.348591 progress 85% (38MB)
72 11:40:23.360546 progress 90% (40MB)
73 11:40:23.372586 progress 95% (43MB)
74 11:40:23.384732 progress 100% (45MB)
75 11:40:23.384927 45MB downloaded in 0.25s (180.63MB/s)
76 11:40:23.385094 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:40:23.385337 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:40:23.385424 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:40:23.385515 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:40:23.385649 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:40:23.385718 saving as /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/dtb/mt8192-asurada-spherion-r0.dtb
83 11:40:23.385791 total size: 46924 (0MB)
84 11:40:23.385863 No compression specified
85 11:40:23.387002 progress 69% (0MB)
86 11:40:23.387269 progress 100% (0MB)
87 11:40:23.387420 0MB downloaded in 0.00s (27.50MB/s)
88 11:40:23.387548 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:40:23.387766 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:40:23.387849 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:40:23.387929 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:40:23.388047 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230609.0/arm64/full.rootfs.tar.xz
94 11:40:23.388115 saving as /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/nfsrootfs/full.rootfs.tar
95 11:40:23.388175 total size: 89385828 (85MB)
96 11:40:23.388237 Using unxz to decompress xz
97 11:40:23.391565 progress 0% (0MB)
98 11:40:23.604559 progress 5% (4MB)
99 11:40:23.821197 progress 10% (8MB)
100 11:40:24.074362 progress 15% (12MB)
101 11:40:24.268056 progress 20% (17MB)
102 11:40:24.362988 progress 25% (21MB)
103 11:40:24.615918 progress 30% (25MB)
104 11:40:24.906853 progress 35% (29MB)
105 11:40:25.174960 progress 40% (34MB)
106 11:40:25.443643 progress 45% (38MB)
107 11:40:25.699091 progress 50% (42MB)
108 11:40:25.967772 progress 55% (46MB)
109 11:40:26.220932 progress 60% (51MB)
110 11:40:26.483896 progress 65% (55MB)
111 11:40:26.780158 progress 70% (59MB)
112 11:40:27.076186 progress 75% (63MB)
113 11:40:27.372731 progress 80% (68MB)
114 11:40:27.621272 progress 85% (72MB)
115 11:40:27.846544 progress 90% (76MB)
116 11:40:28.097221 progress 95% (81MB)
117 11:40:28.353398 progress 100% (85MB)
118 11:40:28.359417 85MB downloaded in 4.97s (17.15MB/s)
119 11:40:28.359706 end: 1.4.1 http-download (duration 00:00:05) [common]
121 11:40:28.359972 end: 1.4 download-retry (duration 00:00:05) [common]
122 11:40:28.360063 start: 1.5 download-retry (timeout 00:09:54) [common]
123 11:40:28.360149 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 11:40:28.360297 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:40:28.360370 saving as /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/modules/modules.tar
126 11:40:28.360432 total size: 8555256 (8MB)
127 11:40:28.360494 Using unxz to decompress xz
128 11:40:28.363883 progress 0% (0MB)
129 11:40:28.386450 progress 5% (0MB)
130 11:40:28.411024 progress 10% (0MB)
131 11:40:28.434917 progress 15% (1MB)
132 11:40:28.459534 progress 20% (1MB)
133 11:40:28.483876 progress 25% (2MB)
134 11:40:28.506689 progress 30% (2MB)
135 11:40:28.532071 progress 35% (2MB)
136 11:40:28.556491 progress 40% (3MB)
137 11:40:28.579962 progress 45% (3MB)
138 11:40:28.607013 progress 50% (4MB)
139 11:40:28.631682 progress 55% (4MB)
140 11:40:28.657099 progress 60% (4MB)
141 11:40:28.682702 progress 65% (5MB)
142 11:40:28.707533 progress 70% (5MB)
143 11:40:28.731378 progress 75% (6MB)
144 11:40:28.754810 progress 80% (6MB)
145 11:40:28.778905 progress 85% (6MB)
146 11:40:28.807634 progress 90% (7MB)
147 11:40:28.834638 progress 95% (7MB)
148 11:40:28.859508 progress 100% (8MB)
149 11:40:28.863822 8MB downloaded in 0.50s (16.21MB/s)
150 11:40:28.864098 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:40:28.864366 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:40:28.864462 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 11:40:28.864555 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 11:40:30.482826 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10742228/extract-nfsrootfs-kz1ohlq0
156 11:40:30.483022 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:40:30.483126 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 11:40:30.483300 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m
159 11:40:30.483428 makedir: /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin
160 11:40:30.483530 makedir: /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/tests
161 11:40:30.483629 makedir: /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/results
162 11:40:30.483734 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-add-keys
163 11:40:30.483881 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-add-sources
164 11:40:30.484011 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-background-process-start
165 11:40:30.484138 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-background-process-stop
166 11:40:30.484263 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-common-functions
167 11:40:30.484387 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-echo-ipv4
168 11:40:30.484512 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-install-packages
169 11:40:30.484635 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-installed-packages
170 11:40:30.484758 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-os-build
171 11:40:30.485143 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-probe-channel
172 11:40:30.485273 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-probe-ip
173 11:40:30.485406 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-target-ip
174 11:40:30.485532 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-target-mac
175 11:40:30.485657 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-target-storage
176 11:40:30.485785 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-test-case
177 11:40:30.485913 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-test-event
178 11:40:30.486039 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-test-feedback
179 11:40:30.486164 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-test-raise
180 11:40:30.486288 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-test-reference
181 11:40:30.486413 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-test-runner
182 11:40:30.486536 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-test-set
183 11:40:30.486660 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-test-shell
184 11:40:30.486791 Updating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-install-packages (oe)
185 11:40:30.486942 Updating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/bin/lava-installed-packages (oe)
186 11:40:30.487073 Creating /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/environment
187 11:40:30.487175 LAVA metadata
188 11:40:30.487248 - LAVA_JOB_ID=10742228
189 11:40:30.487315 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:40:30.487422 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 11:40:30.487491 skipped lava-vland-overlay
192 11:40:30.487569 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:40:30.487650 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 11:40:30.487713 skipped lava-multinode-overlay
195 11:40:30.487789 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:40:30.487868 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 11:40:30.487944 Loading test definitions
198 11:40:30.488036 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 11:40:30.488112 Using /lava-10742228 at stage 0
200 11:40:30.488408 uuid=10742228_1.6.2.3.1 testdef=None
201 11:40:30.488499 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:40:30.488586 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 11:40:30.489080 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:40:30.489309 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 11:40:30.489915 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:40:30.490151 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 11:40:30.490736 runner path: /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/0/tests/0_lc-compliance test_uuid 10742228_1.6.2.3.1
210 11:40:30.490893 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:40:30.491104 Creating lava-test-runner.conf files
213 11:40:30.491169 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742228/lava-overlay-sezdca3m/lava-10742228/0 for stage 0
214 11:40:30.491258 - 0_lc-compliance
215 11:40:30.491357 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:40:30.491442 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 11:40:30.497274 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:40:30.497400 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 11:40:30.497491 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:40:30.497579 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:40:30.497666 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 11:40:30.617822 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:40:30.618191 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 11:40:30.618313 extracting modules file /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742228/extract-nfsrootfs-kz1ohlq0
225 11:40:30.829536 extracting modules file /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742228/extract-overlay-ramdisk-ch6tef6b/ramdisk
226 11:40:31.037147 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:40:31.037319 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 11:40:31.037414 [common] Applying overlay to NFS
229 11:40:31.037486 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742228/compress-overlay-bfinf304/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742228/extract-nfsrootfs-kz1ohlq0
230 11:40:31.043879 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:40:31.044021 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 11:40:31.044119 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:40:31.044212 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 11:40:31.044297 Building ramdisk /var/lib/lava/dispatcher/tmp/10742228/extract-overlay-ramdisk-ch6tef6b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742228/extract-overlay-ramdisk-ch6tef6b/ramdisk
235 11:40:31.314088 >> 117806 blocks
236 11:40:33.236582 rename /var/lib/lava/dispatcher/tmp/10742228/extract-overlay-ramdisk-ch6tef6b/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/ramdisk/ramdisk.cpio.gz
237 11:40:33.237049 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:40:33.237170 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 11:40:33.237313 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 11:40:33.237420 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/kernel/Image'
241 11:40:46.029572 Returned 0 in 12 seconds
242 11:40:46.130508 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/kernel/image.itb
243 11:40:46.477132 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:40:46.477498 output: Created: Thu Jun 15 12:40:46 2023
245 11:40:46.477575 output: Image 0 (kernel-1)
246 11:40:46.477644 output: Description:
247 11:40:46.477709 output: Created: Thu Jun 15 12:40:46 2023
248 11:40:46.477771 output: Type: Kernel Image
249 11:40:46.477834 output: Compression: lzma compressed
250 11:40:46.477895 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
251 11:40:46.477957 output: Architecture: AArch64
252 11:40:46.478015 output: OS: Linux
253 11:40:46.478072 output: Load Address: 0x00000000
254 11:40:46.478132 output: Entry Point: 0x00000000
255 11:40:46.478223 output: Hash algo: crc32
256 11:40:46.478279 output: Hash value: cd22d0e5
257 11:40:46.478333 output: Image 1 (fdt-1)
258 11:40:46.478387 output: Description: mt8192-asurada-spherion-r0
259 11:40:46.478440 output: Created: Thu Jun 15 12:40:46 2023
260 11:40:46.478493 output: Type: Flat Device Tree
261 11:40:46.478547 output: Compression: uncompressed
262 11:40:46.478601 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
263 11:40:46.478654 output: Architecture: AArch64
264 11:40:46.478707 output: Hash algo: crc32
265 11:40:46.478760 output: Hash value: 1df858fa
266 11:40:46.478814 output: Image 2 (ramdisk-1)
267 11:40:46.478867 output: Description: unavailable
268 11:40:46.478920 output: Created: Thu Jun 15 12:40:46 2023
269 11:40:46.478974 output: Type: RAMDisk Image
270 11:40:46.479027 output: Compression: Unknown Compression
271 11:40:46.479080 output: Data Size: 17641909 Bytes = 17228.43 KiB = 16.82 MiB
272 11:40:46.479133 output: Architecture: AArch64
273 11:40:46.479186 output: OS: Linux
274 11:40:46.479239 output: Load Address: unavailable
275 11:40:46.479292 output: Entry Point: unavailable
276 11:40:46.479344 output: Hash algo: crc32
277 11:40:46.479397 output: Hash value: 433ba115
278 11:40:46.479450 output: Default Configuration: 'conf-1'
279 11:40:46.479503 output: Configuration 0 (conf-1)
280 11:40:46.479556 output: Description: mt8192-asurada-spherion-r0
281 11:40:46.479608 output: Kernel: kernel-1
282 11:40:46.479662 output: Init Ramdisk: ramdisk-1
283 11:40:46.479714 output: FDT: fdt-1
284 11:40:46.479767 output: Loadables: kernel-1
285 11:40:46.479820 output:
286 11:40:46.480013 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 11:40:46.480108 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 11:40:46.480207 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 11:40:46.480300 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:36) [common]
290 11:40:46.480378 No LXC device requested
291 11:40:46.480459 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:40:46.480544 start: 1.8 deploy-device-env (timeout 00:09:36) [common]
293 11:40:46.480620 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:40:46.480690 Checking files for TFTP limit of 4294967296 bytes.
295 11:40:46.481178 end: 1 tftp-deploy (duration 00:00:24) [common]
296 11:40:46.481283 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:40:46.481376 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:40:46.481499 substitutions:
299 11:40:46.481567 - {DTB}: 10742228/tftp-deploy-t5m_fu4a/dtb/mt8192-asurada-spherion-r0.dtb
300 11:40:46.481633 - {INITRD}: 10742228/tftp-deploy-t5m_fu4a/ramdisk/ramdisk.cpio.gz
301 11:40:46.481693 - {KERNEL}: 10742228/tftp-deploy-t5m_fu4a/kernel/Image
302 11:40:46.481752 - {LAVA_MAC}: None
303 11:40:46.481807 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10742228/extract-nfsrootfs-kz1ohlq0
304 11:40:46.481863 - {NFS_SERVER_IP}: 192.168.201.1
305 11:40:46.481918 - {PRESEED_CONFIG}: None
306 11:40:46.481972 - {PRESEED_LOCAL}: None
307 11:40:46.482026 - {RAMDISK}: 10742228/tftp-deploy-t5m_fu4a/ramdisk/ramdisk.cpio.gz
308 11:40:46.482081 - {ROOT_PART}: None
309 11:40:46.482135 - {ROOT}: None
310 11:40:46.482188 - {SERVER_IP}: 192.168.201.1
311 11:40:46.482241 - {TEE}: None
312 11:40:46.482295 Parsed boot commands:
313 11:40:46.482349 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:40:46.482526 Parsed boot commands: tftpboot 192.168.201.1 10742228/tftp-deploy-t5m_fu4a/kernel/image.itb 10742228/tftp-deploy-t5m_fu4a/kernel/cmdline
315 11:40:46.482617 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:40:46.482705 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:40:46.482801 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:40:46.482889 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:40:46.482959 Not connected, no need to disconnect.
320 11:40:46.483034 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:40:46.483113 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:40:46.483182 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
323 11:40:46.486542 Setting prompt string to ['lava-test: # ']
324 11:40:46.486907 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:40:46.487014 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:40:46.487111 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:40:46.487204 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:40:46.487397 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
329 11:40:51.638107 >> Command sent successfully.
330 11:40:51.647865 Returned 0 in 5 seconds
331 11:40:51.748748 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 11:40:51.749187 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 11:40:51.749311 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 11:40:51.749403 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:40:51.749476 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:40:51.749579 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:40:51.749953 [Enter `^Ec?' for help]
339 11:40:51.913154
340 11:40:51.913328
341 11:40:51.913429 F0: 102B 0000
342 11:40:51.913524
343 11:40:51.913614 F3: 1001 0000 [0200]
344 11:40:51.913703
345 11:40:51.916925 F3: 1001 0000
346 11:40:51.917027
347 11:40:51.917120 F7: 102D 0000
348 11:40:51.917209
349 11:40:51.917297 F1: 0000 0000
350 11:40:51.917386
351 11:40:51.920833 V0: 0000 0000 [0001]
352 11:40:51.920922
353 11:40:51.920985 00: 0007 8000
354 11:40:51.921079
355 11:40:51.924653 01: 0000 0000
356 11:40:51.924769
357 11:40:51.924906 BP: 0C00 0209 [0000]
358 11:40:51.924988
359 11:40:51.925051 G0: 1182 0000
360 11:40:51.925114
361 11:40:51.928412 EC: 0000 0021 [4000]
362 11:40:51.928504
363 11:40:51.928638 S7: 0000 0000 [0000]
364 11:40:51.928734
365 11:40:51.932549 CC: 0000 0000 [0001]
366 11:40:51.932634
367 11:40:51.932701 T0: 0000 0040 [010F]
368 11:40:51.935793
369 11:40:51.935877 Jump to BL
370 11:40:51.935944
371 11:40:51.960100
372 11:40:51.960185
373 11:40:51.960251
374 11:40:51.967349 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 11:40:51.970977 ARM64: Exception handlers installed.
376 11:40:51.975135 ARM64: Testing exception
377 11:40:51.978691 ARM64: Done test exception
378 11:40:51.985946 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 11:40:51.993325 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 11:40:51.999857 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 11:40:52.010747 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 11:40:52.017876 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 11:40:52.027517 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 11:40:52.038281 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 11:40:52.045583 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 11:40:52.062686 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 11:40:52.066017 WDT: Last reset was cold boot
388 11:40:52.069939 SPI1(PAD0) initialized at 2873684 Hz
389 11:40:52.072749 SPI5(PAD0) initialized at 992727 Hz
390 11:40:52.076337 VBOOT: Loading verstage.
391 11:40:52.082992 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 11:40:52.086019 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 11:40:52.089586 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 11:40:52.092545 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 11:40:52.100374 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 11:40:52.106949 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 11:40:52.117727 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 11:40:52.117811
399 11:40:52.117878
400 11:40:52.128516 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 11:40:52.131846 ARM64: Exception handlers installed.
402 11:40:52.131934 ARM64: Testing exception
403 11:40:52.135082 ARM64: Done test exception
404 11:40:52.141953 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 11:40:52.145266 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 11:40:52.159153 Probing TPM: . done!
407 11:40:52.159237 TPM ready after 0 ms
408 11:40:52.166439 Connected to device vid:did:rid of 1ae0:0028:00
409 11:40:52.173021 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
410 11:40:52.233570 Initialized TPM device CR50 revision 0
411 11:40:52.245153 tlcl_send_startup: Startup return code is 0
412 11:40:52.245250 TPM: setup succeeded
413 11:40:52.256384 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 11:40:52.265623 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 11:40:52.277509 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 11:40:52.287472 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 11:40:52.291375 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 11:40:52.295175 in-header: 03 07 00 00 08 00 00 00
419 11:40:52.299247 in-data: aa e4 47 04 13 02 00 00
420 11:40:52.302989 Chrome EC: UHEPI supported
421 11:40:52.306057 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 11:40:52.310780 in-header: 03 95 00 00 08 00 00 00
423 11:40:52.314514 in-data: 18 20 20 08 00 00 00 00
424 11:40:52.314599 Phase 1
425 11:40:52.318283 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 11:40:52.325268 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 11:40:52.332755 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 11:40:52.332877 Recovery requested (1009000e)
429 11:40:52.345470 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 11:40:52.349219 tlcl_extend: response is 0
431 11:40:52.359152 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 11:40:52.363791 tlcl_extend: response is 0
433 11:40:52.371095 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 11:40:52.390862 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 11:40:52.397370 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 11:40:52.397455
437 11:40:52.397522
438 11:40:52.407465 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 11:40:52.410995 ARM64: Exception handlers installed.
440 11:40:52.414114 ARM64: Testing exception
441 11:40:52.414198 ARM64: Done test exception
442 11:40:52.436324 pmic_efuse_setting: Set efuses in 11 msecs
443 11:40:52.439837 pmwrap_interface_init: Select PMIF_VLD_RDY
444 11:40:52.446454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 11:40:52.449584 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 11:40:52.453418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 11:40:52.460753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 11:40:52.464623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 11:40:52.468647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 11:40:52.476421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 11:40:52.480432 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 11:40:52.483644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 11:40:52.487554 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 11:40:52.494705 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 11:40:52.498726 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 11:40:52.502018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 11:40:52.509036 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 11:40:52.513091 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 11:40:52.520120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 11:40:52.523601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 11:40:52.531740 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 11:40:52.538539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 11:40:52.542426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 11:40:52.550016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 11:40:52.553701 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 11:40:52.561089 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 11:40:52.565072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 11:40:52.569166 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 11:40:52.576445 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 11:40:52.579911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 11:40:52.587145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 11:40:52.591018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 11:40:52.594608 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 11:40:52.601868 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 11:40:52.605169 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 11:40:52.609040 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 11:40:52.616019 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 11:40:52.619887 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 11:40:52.626768 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 11:40:52.630998 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 11:40:52.634830 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 11:40:52.638429 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 11:40:52.645376 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 11:40:52.649342 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 11:40:52.653069 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 11:40:52.656754 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 11:40:52.660493 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 11:40:52.664289 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 11:40:52.671816 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 11:40:52.675101 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 11:40:52.678955 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 11:40:52.683093 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 11:40:52.686347 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 11:40:52.689625 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 11:40:52.697528 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 11:40:52.708660 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 11:40:52.712631 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 11:40:52.719719 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 11:40:52.730645 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 11:40:52.734429 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 11:40:52.738275 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:40:52.741922 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 11:40:52.749995 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 11:40:52.753149 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 11:40:52.761335 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 11:40:52.764459 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 11:40:52.774240 [RTC]rtc_get_frequency_meter,154: input=15, output=758
508 11:40:52.783291 [RTC]rtc_get_frequency_meter,154: input=23, output=944
509 11:40:52.792771 [RTC]rtc_get_frequency_meter,154: input=19, output=849
510 11:40:52.801524 [RTC]rtc_get_frequency_meter,154: input=17, output=805
511 11:40:52.812236 [RTC]rtc_get_frequency_meter,154: input=16, output=782
512 11:40:52.821421 [RTC]rtc_get_frequency_meter,154: input=16, output=781
513 11:40:52.830855 [RTC]rtc_get_frequency_meter,154: input=17, output=805
514 11:40:52.834929 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 11:40:52.838067 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 11:40:52.845752 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 11:40:52.850079 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 11:40:52.853263 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 11:40:52.857040 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 11:40:52.860911 ADC[4]: Raw value=906203 ID=7
521 11:40:52.860996 ADC[3]: Raw value=213810 ID=1
522 11:40:52.864743 RAM Code: 0x71
523 11:40:52.868502 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 11:40:52.872247 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 11:40:52.883443 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 11:40:52.887673 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 11:40:52.891004 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 11:40:52.894415 in-header: 03 07 00 00 08 00 00 00
529 11:40:52.898387 in-data: aa e4 47 04 13 02 00 00
530 11:40:52.902307 Chrome EC: UHEPI supported
531 11:40:52.905712 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 11:40:52.911522 in-header: 03 95 00 00 08 00 00 00
533 11:40:52.914870 in-data: 18 20 20 08 00 00 00 00
534 11:40:52.918831 MRC: failed to locate region type 0.
535 11:40:52.925873 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 11:40:52.929843 DRAM-K: Running full calibration
537 11:40:52.933802 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 11:40:52.937049 header.status = 0x0
539 11:40:52.940643 header.version = 0x6 (expected: 0x6)
540 11:40:52.944473 header.size = 0xd00 (expected: 0xd00)
541 11:40:52.944587 header.flags = 0x0
542 11:40:52.951888 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 11:40:52.968945 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
544 11:40:52.976481 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 11:40:52.980403 dram_init: ddr_geometry: 2
546 11:40:52.980529 [EMI] MDL number = 2
547 11:40:52.983865 [EMI] Get MDL freq = 0
548 11:40:52.983980 dram_init: ddr_type: 0
549 11:40:52.988286 is_discrete_lpddr4: 1
550 11:40:52.988395 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 11:40:52.991675
552 11:40:52.991793
553 11:40:52.991891 [Bian_co] ETT version 0.0.0.1
554 11:40:52.995796 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 11:40:52.999678
556 11:40:52.999784 dramc_set_vcore_voltage set vcore to 650000
557 11:40:53.003647 Read voltage for 800, 4
558 11:40:53.003765 Vio18 = 0
559 11:40:53.006996 Vcore = 650000
560 11:40:53.007112 Vdram = 0
561 11:40:53.007214 Vddq = 0
562 11:40:53.007309 Vmddr = 0
563 11:40:53.011018 dram_init: config_dvfs: 1
564 11:40:53.014347 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 11:40:53.022286 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 11:40:53.026167 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
567 11:40:53.030129 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
568 11:40:53.033399 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 11:40:53.036573 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 11:40:53.039876 MEM_TYPE=3, freq_sel=18
571 11:40:53.043045 sv_algorithm_assistance_LP4_1600
572 11:40:53.046777 ============ PULL DRAM RESETB DOWN ============
573 11:40:53.049954 ========== PULL DRAM RESETB DOWN end =========
574 11:40:53.053670 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 11:40:53.057540 ===================================
576 11:40:53.061172 LPDDR4 DRAM CONFIGURATION
577 11:40:53.064845 ===================================
578 11:40:53.064932 EX_ROW_EN[0] = 0x0
579 11:40:53.068271 EX_ROW_EN[1] = 0x0
580 11:40:53.068383 LP4Y_EN = 0x0
581 11:40:53.071756 WORK_FSP = 0x0
582 11:40:53.071875 WL = 0x2
583 11:40:53.075003 RL = 0x2
584 11:40:53.075115 BL = 0x2
585 11:40:53.078237 RPST = 0x0
586 11:40:53.078341 RD_PRE = 0x0
587 11:40:53.082269 WR_PRE = 0x1
588 11:40:53.082375 WR_PST = 0x0
589 11:40:53.085092 DBI_WR = 0x0
590 11:40:53.085186 DBI_RD = 0x0
591 11:40:53.088646 OTF = 0x1
592 11:40:53.091678 ===================================
593 11:40:53.096100 ===================================
594 11:40:53.096219 ANA top config
595 11:40:53.099553 ===================================
596 11:40:53.102838 DLL_ASYNC_EN = 0
597 11:40:53.105997 ALL_SLAVE_EN = 1
598 11:40:53.106103 NEW_RANK_MODE = 1
599 11:40:53.109857 DLL_IDLE_MODE = 1
600 11:40:53.113074 LP45_APHY_COMB_EN = 1
601 11:40:53.116342 TX_ODT_DIS = 1
602 11:40:53.116440 NEW_8X_MODE = 1
603 11:40:53.120231 ===================================
604 11:40:53.123567 ===================================
605 11:40:53.127430 data_rate = 1600
606 11:40:53.130062 CKR = 1
607 11:40:53.133284 DQ_P2S_RATIO = 8
608 11:40:53.136687 ===================================
609 11:40:53.140706 CA_P2S_RATIO = 8
610 11:40:53.140815 DQ_CA_OPEN = 0
611 11:40:53.143941 DQ_SEMI_OPEN = 0
612 11:40:53.147246 CA_SEMI_OPEN = 0
613 11:40:53.150178 CA_FULL_RATE = 0
614 11:40:53.153393 DQ_CKDIV4_EN = 1
615 11:40:53.153473 CA_CKDIV4_EN = 1
616 11:40:53.156876 CA_PREDIV_EN = 0
617 11:40:53.160482 PH8_DLY = 0
618 11:40:53.163588 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 11:40:53.166605 DQ_AAMCK_DIV = 4
620 11:40:53.170277 CA_AAMCK_DIV = 4
621 11:40:53.170414 CA_ADMCK_DIV = 4
622 11:40:53.173409 DQ_TRACK_CA_EN = 0
623 11:40:53.176651 CA_PICK = 800
624 11:40:53.180462 CA_MCKIO = 800
625 11:40:53.184205 MCKIO_SEMI = 0
626 11:40:53.188046 PLL_FREQ = 3068
627 11:40:53.188152 DQ_UI_PI_RATIO = 32
628 11:40:53.191696 CA_UI_PI_RATIO = 0
629 11:40:53.195497 ===================================
630 11:40:53.199232 ===================================
631 11:40:53.199316 memory_type:LPDDR4
632 11:40:53.203048 GP_NUM : 10
633 11:40:53.207075 SRAM_EN : 1
634 11:40:53.207157 MD32_EN : 0
635 11:40:53.210398 ===================================
636 11:40:53.214199 [ANA_INIT] >>>>>>>>>>>>>>
637 11:40:53.214284 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 11:40:53.217794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 11:40:53.221035 ===================================
640 11:40:53.224370 data_rate = 1600,PCW = 0X7600
641 11:40:53.228407 ===================================
642 11:40:53.231720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 11:40:53.238204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 11:40:53.241417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 11:40:53.247963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 11:40:53.251337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 11:40:53.254461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 11:40:53.254541 [ANA_INIT] flow start
649 11:40:53.258121 [ANA_INIT] PLL >>>>>>>>
650 11:40:53.261395 [ANA_INIT] PLL <<<<<<<<
651 11:40:53.261478 [ANA_INIT] MIDPI >>>>>>>>
652 11:40:53.264474 [ANA_INIT] MIDPI <<<<<<<<
653 11:40:53.268383 [ANA_INIT] DLL >>>>>>>>
654 11:40:53.268473 [ANA_INIT] flow end
655 11:40:53.274499 ============ LP4 DIFF to SE enter ============
656 11:40:53.278171 ============ LP4 DIFF to SE exit ============
657 11:40:53.281351 [ANA_INIT] <<<<<<<<<<<<<
658 11:40:53.284410 [Flow] Enable top DCM control >>>>>
659 11:40:53.288167 [Flow] Enable top DCM control <<<<<
660 11:40:53.288276 Enable DLL master slave shuffle
661 11:40:53.295127 ==============================================================
662 11:40:53.298166 Gating Mode config
663 11:40:53.301800 ==============================================================
664 11:40:53.305008 Config description:
665 11:40:53.314615 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 11:40:53.321691 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 11:40:53.325010 SELPH_MODE 0: By rank 1: By Phase
668 11:40:53.331445 ==============================================================
669 11:40:53.334824 GAT_TRACK_EN = 1
670 11:40:53.338687 RX_GATING_MODE = 2
671 11:40:53.341871 RX_GATING_TRACK_MODE = 2
672 11:40:53.341978 SELPH_MODE = 1
673 11:40:53.345148 PICG_EARLY_EN = 1
674 11:40:53.348465 VALID_LAT_VALUE = 1
675 11:40:53.354991 ==============================================================
676 11:40:53.358308 Enter into Gating configuration >>>>
677 11:40:53.362029 Exit from Gating configuration <<<<
678 11:40:53.365070 Enter into DVFS_PRE_config >>>>>
679 11:40:53.375067 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 11:40:53.378258 Exit from DVFS_PRE_config <<<<<
681 11:40:53.382038 Enter into PICG configuration >>>>
682 11:40:53.385205 Exit from PICG configuration <<<<
683 11:40:53.388381 [RX_INPUT] configuration >>>>>
684 11:40:53.391646 [RX_INPUT] configuration <<<<<
685 11:40:53.395466 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 11:40:53.401662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 11:40:53.408837 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 11:40:53.411866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 11:40:53.419130 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 11:40:53.425681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 11:40:53.428940 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 11:40:53.432286 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 11:40:53.438945 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 11:40:53.442294 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 11:40:53.445514 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 11:40:53.452112 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:40:53.455337 ===================================
698 11:40:53.455442 LPDDR4 DRAM CONFIGURATION
699 11:40:53.458747 ===================================
700 11:40:53.461941 EX_ROW_EN[0] = 0x0
701 11:40:53.462030 EX_ROW_EN[1] = 0x0
702 11:40:53.465872 LP4Y_EN = 0x0
703 11:40:53.465962 WORK_FSP = 0x0
704 11:40:53.469085 WL = 0x2
705 11:40:53.472024 RL = 0x2
706 11:40:53.472137 BL = 0x2
707 11:40:53.475130 RPST = 0x0
708 11:40:53.475233 RD_PRE = 0x0
709 11:40:53.478802 WR_PRE = 0x1
710 11:40:53.478906 WR_PST = 0x0
711 11:40:53.482016 DBI_WR = 0x0
712 11:40:53.482154 DBI_RD = 0x0
713 11:40:53.485917 OTF = 0x1
714 11:40:53.488736 ===================================
715 11:40:53.492564 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 11:40:53.495647 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 11:40:53.498847 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 11:40:53.502034 ===================================
719 11:40:53.505950 LPDDR4 DRAM CONFIGURATION
720 11:40:53.508974 ===================================
721 11:40:53.511954 EX_ROW_EN[0] = 0x10
722 11:40:53.512056 EX_ROW_EN[1] = 0x0
723 11:40:53.515798 LP4Y_EN = 0x0
724 11:40:53.515883 WORK_FSP = 0x0
725 11:40:53.518818 WL = 0x2
726 11:40:53.518921 RL = 0x2
727 11:40:53.522124 BL = 0x2
728 11:40:53.522226 RPST = 0x0
729 11:40:53.525856 RD_PRE = 0x0
730 11:40:53.525959 WR_PRE = 0x1
731 11:40:53.529145 WR_PST = 0x0
732 11:40:53.529265 DBI_WR = 0x0
733 11:40:53.532355 DBI_RD = 0x0
734 11:40:53.532441 OTF = 0x1
735 11:40:53.535642 ===================================
736 11:40:53.542366 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 11:40:53.546987 nWR fixed to 40
738 11:40:53.550669 [ModeRegInit_LP4] CH0 RK0
739 11:40:53.550769 [ModeRegInit_LP4] CH0 RK1
740 11:40:53.554040 [ModeRegInit_LP4] CH1 RK0
741 11:40:53.557435 [ModeRegInit_LP4] CH1 RK1
742 11:40:53.557519 match AC timing 13
743 11:40:53.564087 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 11:40:53.567286 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 11:40:53.570598 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 11:40:53.577588 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 11:40:53.580568 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 11:40:53.580654 [EMI DOE] emi_dcm 0
749 11:40:53.587636 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 11:40:53.587724 ==
751 11:40:53.590602 Dram Type= 6, Freq= 0, CH_0, rank 0
752 11:40:53.593686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 11:40:53.593773 ==
754 11:40:53.600572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 11:40:53.606971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 11:40:53.614431 [CA 0] Center 36 (6~67) winsize 62
757 11:40:53.618095 [CA 1] Center 36 (6~67) winsize 62
758 11:40:53.621247 [CA 2] Center 34 (4~65) winsize 62
759 11:40:53.624917 [CA 3] Center 34 (4~64) winsize 61
760 11:40:53.628122 [CA 4] Center 33 (3~64) winsize 62
761 11:40:53.631712 [CA 5] Center 32 (3~62) winsize 60
762 11:40:53.631831
763 11:40:53.634466 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 11:40:53.634545
765 11:40:53.637753 [CATrainingPosCal] consider 1 rank data
766 11:40:53.641089 u2DelayCellTimex100 = 270/100 ps
767 11:40:53.644430 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
768 11:40:53.647714 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
769 11:40:53.654880 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
770 11:40:53.658124 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
771 11:40:53.661415 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
772 11:40:53.664748 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
773 11:40:53.664858
774 11:40:53.668017 CA PerBit enable=1, Macro0, CA PI delay=32
775 11:40:53.668096
776 11:40:53.671343 [CBTSetCACLKResult] CA Dly = 32
777 11:40:53.671417 CS Dly: 5 (0~36)
778 11:40:53.671488 ==
779 11:40:53.674736 Dram Type= 6, Freq= 0, CH_0, rank 1
780 11:40:53.681165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 11:40:53.681252 ==
782 11:40:53.684869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 11:40:53.691169 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 11:40:53.700930 [CA 0] Center 36 (6~67) winsize 62
785 11:40:53.703992 [CA 1] Center 36 (6~67) winsize 62
786 11:40:53.707775 [CA 2] Center 34 (4~65) winsize 62
787 11:40:53.710894 [CA 3] Center 33 (3~64) winsize 62
788 11:40:53.714136 [CA 4] Center 32 (2~63) winsize 62
789 11:40:53.717255 [CA 5] Center 32 (2~63) winsize 62
790 11:40:53.717344
791 11:40:53.721061 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 11:40:53.721177
793 11:40:53.724065 [CATrainingPosCal] consider 2 rank data
794 11:40:53.727864 u2DelayCellTimex100 = 270/100 ps
795 11:40:53.730915 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
796 11:40:53.733991 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
797 11:40:53.740603 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
798 11:40:53.743858 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
799 11:40:53.747226 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
800 11:40:53.751004 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
801 11:40:53.751081
802 11:40:53.754308 CA PerBit enable=1, Macro0, CA PI delay=32
803 11:40:53.754392
804 11:40:53.757529 [CBTSetCACLKResult] CA Dly = 32
805 11:40:53.757612 CS Dly: 5 (0~37)
806 11:40:53.757695
807 11:40:53.760814 ----->DramcWriteLeveling(PI) begin...
808 11:40:53.760894 ==
809 11:40:53.764844 Dram Type= 6, Freq= 0, CH_0, rank 0
810 11:40:53.769173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:40:53.769264 ==
812 11:40:53.772883 Write leveling (Byte 0): 32 => 32
813 11:40:53.776112 Write leveling (Byte 1): 28 => 28
814 11:40:53.779419 DramcWriteLeveling(PI) end<-----
815 11:40:53.779498
816 11:40:53.779573 ==
817 11:40:53.782711 Dram Type= 6, Freq= 0, CH_0, rank 0
818 11:40:53.786503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 11:40:53.786581 ==
820 11:40:53.790659 [Gating] SW mode calibration
821 11:40:53.797483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 11:40:53.800527 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 11:40:53.807526 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 11:40:53.810584 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
825 11:40:53.814268 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
826 11:40:53.820602 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:40:53.824242 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:40:53.827465 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:40:53.834125 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:40:53.837195 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:40:53.840609 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:40:53.847463 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:40:53.850826 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:40:53.854183 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 11:40:53.861099 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:40:53.864498 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:40:53.867772 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:40:53.874377 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:40:53.877735 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:40:53.880829 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 11:40:53.884206 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
842 11:40:53.890876 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
843 11:40:53.894399 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 11:40:53.897525 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 11:40:53.904595 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 11:40:53.907297 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 11:40:53.911026 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 11:40:53.917219 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 11:40:53.920680 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
850 11:40:53.924381 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
851 11:40:53.931110 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 11:40:53.934287 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 11:40:53.937984 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 11:40:53.944059 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 11:40:53.947738 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 11:40:53.951431 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
857 11:40:53.957394 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (1 0) (0 0)
858 11:40:53.961285 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:40:53.964431 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:40:53.967687 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:40:53.974299 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:40:53.977723 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:40:53.981014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:40:53.988165 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
865 11:40:53.991593 0 11 8 | B1->B0 | 2c2c 403f | 0 1 | (0 0) (0 0)
866 11:40:53.994696 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 11:40:54.001033 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 11:40:54.004751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 11:40:54.007824 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 11:40:54.014663 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 11:40:54.017962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:40:54.021093 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 11:40:54.028223 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
874 11:40:54.031331 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 11:40:54.034441 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:40:54.038688 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:40:54.044582 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:40:54.047765 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:40:54.051753 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:40:54.058038 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:40:54.061367 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:40:54.064592 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 11:40:54.071801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 11:40:54.075238 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 11:40:54.078460 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 11:40:54.085164 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 11:40:54.088551 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 11:40:54.091787 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
889 11:40:54.098378 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
890 11:40:54.101589 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 11:40:54.105158 Total UI for P1: 0, mck2ui 16
892 11:40:54.108339 best dqsien dly found for B0: ( 0, 14, 6)
893 11:40:54.111958 Total UI for P1: 0, mck2ui 16
894 11:40:54.115107 best dqsien dly found for B1: ( 0, 14, 10)
895 11:40:54.118984 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
896 11:40:54.122706 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 11:40:54.122857
898 11:40:54.125843 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
899 11:40:54.128824 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 11:40:54.132645 [Gating] SW calibration Done
901 11:40:54.132753 ==
902 11:40:54.135778 Dram Type= 6, Freq= 0, CH_0, rank 0
903 11:40:54.139177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 11:40:54.139282 ==
905 11:40:54.142368 RX Vref Scan: 0
906 11:40:54.142473
907 11:40:54.142574 RX Vref 0 -> 0, step: 1
908 11:40:54.142671
909 11:40:54.145988 RX Delay -130 -> 252, step: 16
910 11:40:54.149237 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
911 11:40:54.152789 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
912 11:40:54.159241 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
913 11:40:54.162408 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
914 11:40:54.166052 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
915 11:40:54.169343 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
916 11:40:54.173239 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
917 11:40:54.179876 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
918 11:40:54.183160 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
919 11:40:54.186426 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
920 11:40:54.189691 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
921 11:40:54.193136 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
922 11:40:54.199723 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
923 11:40:54.203059 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
924 11:40:54.206348 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
925 11:40:54.209735 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
926 11:40:54.209815 ==
927 11:40:54.212985 Dram Type= 6, Freq= 0, CH_0, rank 0
928 11:40:54.216658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 11:40:54.219827 ==
930 11:40:54.219939 DQS Delay:
931 11:40:54.220034 DQS0 = 0, DQS1 = 0
932 11:40:54.223119 DQM Delay:
933 11:40:54.223217 DQM0 = 88, DQM1 = 81
934 11:40:54.226264 DQ Delay:
935 11:40:54.226370 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
936 11:40:54.230017 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
937 11:40:54.233003 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
938 11:40:54.236695 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
939 11:40:54.236798
940 11:40:54.236938
941 11:40:54.239771 ==
942 11:40:54.242941 Dram Type= 6, Freq= 0, CH_0, rank 0
943 11:40:54.247037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 11:40:54.247149 ==
945 11:40:54.247259
946 11:40:54.247353
947 11:40:54.249821 TX Vref Scan disable
948 11:40:54.249923 == TX Byte 0 ==
949 11:40:54.252978 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
950 11:40:54.259731 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
951 11:40:54.259834 == TX Byte 1 ==
952 11:40:54.263481 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
953 11:40:54.269836 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
954 11:40:54.269922 ==
955 11:40:54.273454 Dram Type= 6, Freq= 0, CH_0, rank 0
956 11:40:54.276479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 11:40:54.276565 ==
958 11:40:54.290056 TX Vref=22, minBit 8, minWin=27, winSum=451
959 11:40:54.293382 TX Vref=24, minBit 7, minWin=27, winSum=449
960 11:40:54.296712 TX Vref=26, minBit 0, minWin=28, winSum=455
961 11:40:54.300032 TX Vref=28, minBit 0, minWin=28, winSum=459
962 11:40:54.303258 TX Vref=30, minBit 8, minWin=28, winSum=459
963 11:40:54.306641 TX Vref=32, minBit 2, minWin=28, winSum=455
964 11:40:54.313695 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
965 11:40:54.313801
966 11:40:54.317230 Final TX Range 1 Vref 28
967 11:40:54.317315
968 11:40:54.317383 ==
969 11:40:54.320390 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:40:54.323543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:40:54.323632 ==
972 11:40:54.323704
973 11:40:54.327059
974 11:40:54.327186 TX Vref Scan disable
975 11:40:54.330316 == TX Byte 0 ==
976 11:40:54.333315 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 11:40:54.336971 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 11:40:54.340160 == TX Byte 1 ==
979 11:40:54.343341 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
980 11:40:54.347132 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
981 11:40:54.347237
982 11:40:54.350140 [DATLAT]
983 11:40:54.350218 Freq=800, CH0 RK0
984 11:40:54.350283
985 11:40:54.354042 DATLAT Default: 0xa
986 11:40:54.354125 0, 0xFFFF, sum = 0
987 11:40:54.357118 1, 0xFFFF, sum = 0
988 11:40:54.357199 2, 0xFFFF, sum = 0
989 11:40:54.360195 3, 0xFFFF, sum = 0
990 11:40:54.360272 4, 0xFFFF, sum = 0
991 11:40:54.363952 5, 0xFFFF, sum = 0
992 11:40:54.364028 6, 0xFFFF, sum = 0
993 11:40:54.367088 7, 0xFFFF, sum = 0
994 11:40:54.367170 8, 0xFFFF, sum = 0
995 11:40:54.370222 9, 0x0, sum = 1
996 11:40:54.370300 10, 0x0, sum = 2
997 11:40:54.374060 11, 0x0, sum = 3
998 11:40:54.374142 12, 0x0, sum = 4
999 11:40:54.377275 best_step = 10
1000 11:40:54.377349
1001 11:40:54.377413 ==
1002 11:40:54.380377 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 11:40:54.383873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 11:40:54.383948 ==
1005 11:40:54.387021 RX Vref Scan: 1
1006 11:40:54.387104
1007 11:40:54.387169 Set Vref Range= 32 -> 127
1008 11:40:54.387231
1009 11:40:54.390246 RX Vref 32 -> 127, step: 1
1010 11:40:54.390319
1011 11:40:54.394295 RX Delay -95 -> 252, step: 8
1012 11:40:54.394374
1013 11:40:54.396916 Set Vref, RX VrefLevel [Byte0]: 32
1014 11:40:54.400261 [Byte1]: 32
1015 11:40:54.400333
1016 11:40:54.403594 Set Vref, RX VrefLevel [Byte0]: 33
1017 11:40:54.407455 [Byte1]: 33
1018 11:40:54.407534
1019 11:40:54.410720 Set Vref, RX VrefLevel [Byte0]: 34
1020 11:40:54.414036 [Byte1]: 34
1021 11:40:54.417959
1022 11:40:54.418037 Set Vref, RX VrefLevel [Byte0]: 35
1023 11:40:54.421160 [Byte1]: 35
1024 11:40:54.426468
1025 11:40:54.426590 Set Vref, RX VrefLevel [Byte0]: 36
1026 11:40:54.429478 [Byte1]: 36
1027 11:40:54.433413
1028 11:40:54.433494 Set Vref, RX VrefLevel [Byte0]: 37
1029 11:40:54.436534 [Byte1]: 37
1030 11:40:54.441533
1031 11:40:54.441618 Set Vref, RX VrefLevel [Byte0]: 38
1032 11:40:54.444684 [Byte1]: 38
1033 11:40:54.448599
1034 11:40:54.448751 Set Vref, RX VrefLevel [Byte0]: 39
1035 11:40:54.451733 [Byte1]: 39
1036 11:40:54.456214
1037 11:40:54.456342 Set Vref, RX VrefLevel [Byte0]: 40
1038 11:40:54.459387 [Byte1]: 40
1039 11:40:54.463806
1040 11:40:54.463907 Set Vref, RX VrefLevel [Byte0]: 41
1041 11:40:54.466901 [Byte1]: 41
1042 11:40:54.471115
1043 11:40:54.471215 Set Vref, RX VrefLevel [Byte0]: 42
1044 11:40:54.474266 [Byte1]: 42
1045 11:40:54.478970
1046 11:40:54.479062 Set Vref, RX VrefLevel [Byte0]: 43
1047 11:40:54.482317 [Byte1]: 43
1048 11:40:54.486810
1049 11:40:54.486926 Set Vref, RX VrefLevel [Byte0]: 44
1050 11:40:54.490053 [Byte1]: 44
1051 11:40:54.494042
1052 11:40:54.494135 Set Vref, RX VrefLevel [Byte0]: 45
1053 11:40:54.497304 [Byte1]: 45
1054 11:40:54.501276
1055 11:40:54.501365 Set Vref, RX VrefLevel [Byte0]: 46
1056 11:40:54.504540 [Byte1]: 46
1057 11:40:54.509208
1058 11:40:54.509294 Set Vref, RX VrefLevel [Byte0]: 47
1059 11:40:54.512491 [Byte1]: 47
1060 11:40:54.516556
1061 11:40:54.516641 Set Vref, RX VrefLevel [Byte0]: 48
1062 11:40:54.520406 [Byte1]: 48
1063 11:40:54.524513
1064 11:40:54.524598 Set Vref, RX VrefLevel [Byte0]: 49
1065 11:40:54.527779 [Byte1]: 49
1066 11:40:54.531714
1067 11:40:54.531863 Set Vref, RX VrefLevel [Byte0]: 50
1068 11:40:54.534994 [Byte1]: 50
1069 11:40:54.539432
1070 11:40:54.539547 Set Vref, RX VrefLevel [Byte0]: 51
1071 11:40:54.542616 [Byte1]: 51
1072 11:40:54.547477
1073 11:40:54.547617 Set Vref, RX VrefLevel [Byte0]: 52
1074 11:40:54.550727 [Byte1]: 52
1075 11:40:54.554439
1076 11:40:54.554538 Set Vref, RX VrefLevel [Byte0]: 53
1077 11:40:54.558337 [Byte1]: 53
1078 11:40:54.562646
1079 11:40:54.562746 Set Vref, RX VrefLevel [Byte0]: 54
1080 11:40:54.565840 [Byte1]: 54
1081 11:40:54.569877
1082 11:40:54.569977 Set Vref, RX VrefLevel [Byte0]: 55
1083 11:40:54.573561 [Byte1]: 55
1084 11:40:54.577769
1085 11:40:54.577852 Set Vref, RX VrefLevel [Byte0]: 56
1086 11:40:54.580862 [Byte1]: 56
1087 11:40:54.585502
1088 11:40:54.585601 Set Vref, RX VrefLevel [Byte0]: 57
1089 11:40:54.588620 [Byte1]: 57
1090 11:40:54.592526
1091 11:40:54.592625 Set Vref, RX VrefLevel [Byte0]: 58
1092 11:40:54.596244 [Byte1]: 58
1093 11:40:54.600536
1094 11:40:54.600636 Set Vref, RX VrefLevel [Byte0]: 59
1095 11:40:54.603741 [Byte1]: 59
1096 11:40:54.607684
1097 11:40:54.607784 Set Vref, RX VrefLevel [Byte0]: 60
1098 11:40:54.611033 [Byte1]: 60
1099 11:40:54.615654
1100 11:40:54.615752 Set Vref, RX VrefLevel [Byte0]: 61
1101 11:40:54.618980 [Byte1]: 61
1102 11:40:54.622933
1103 11:40:54.623033 Set Vref, RX VrefLevel [Byte0]: 62
1104 11:40:54.626267 [Byte1]: 62
1105 11:40:54.630835
1106 11:40:54.630937 Set Vref, RX VrefLevel [Byte0]: 63
1107 11:40:54.634090 [Byte1]: 63
1108 11:40:54.638622
1109 11:40:54.638751 Set Vref, RX VrefLevel [Byte0]: 64
1110 11:40:54.641804 [Byte1]: 64
1111 11:40:54.646069
1112 11:40:54.646165 Set Vref, RX VrefLevel [Byte0]: 65
1113 11:40:54.649092 [Byte1]: 65
1114 11:40:54.653393
1115 11:40:54.653489 Set Vref, RX VrefLevel [Byte0]: 66
1116 11:40:54.657369 [Byte1]: 66
1117 11:40:54.661248
1118 11:40:54.661346 Set Vref, RX VrefLevel [Byte0]: 67
1119 11:40:54.664681 [Byte1]: 67
1120 11:40:54.669125
1121 11:40:54.669207 Set Vref, RX VrefLevel [Byte0]: 68
1122 11:40:54.672318 [Byte1]: 68
1123 11:40:54.676061
1124 11:40:54.676158 Set Vref, RX VrefLevel [Byte0]: 69
1125 11:40:54.679718 [Byte1]: 69
1126 11:40:54.684002
1127 11:40:54.684099 Set Vref, RX VrefLevel [Byte0]: 70
1128 11:40:54.687194 [Byte1]: 70
1129 11:40:54.691681
1130 11:40:54.691781 Set Vref, RX VrefLevel [Byte0]: 71
1131 11:40:54.694952 [Byte1]: 71
1132 11:40:54.699241
1133 11:40:54.699323 Set Vref, RX VrefLevel [Byte0]: 72
1134 11:40:54.702215 [Byte1]: 72
1135 11:40:54.706701
1136 11:40:54.706784 Set Vref, RX VrefLevel [Byte0]: 73
1137 11:40:54.710056 [Byte1]: 73
1138 11:40:54.714570
1139 11:40:54.714683 Set Vref, RX VrefLevel [Byte0]: 74
1140 11:40:54.717940 [Byte1]: 74
1141 11:40:54.722017
1142 11:40:54.722100 Set Vref, RX VrefLevel [Byte0]: 75
1143 11:40:54.725282 [Byte1]: 75
1144 11:40:54.729328
1145 11:40:54.729448 Set Vref, RX VrefLevel [Byte0]: 76
1146 11:40:54.732697 [Byte1]: 76
1147 11:40:54.737303
1148 11:40:54.737385 Set Vref, RX VrefLevel [Byte0]: 77
1149 11:40:54.740529 [Byte1]: 77
1150 11:40:54.745015
1151 11:40:54.745097 Set Vref, RX VrefLevel [Byte0]: 78
1152 11:40:54.748319 [Byte1]: 78
1153 11:40:54.752550
1154 11:40:54.752633 Set Vref, RX VrefLevel [Byte0]: 79
1155 11:40:54.755624 [Byte1]: 79
1156 11:40:54.759934
1157 11:40:54.760017 Final RX Vref Byte 0 = 52 to rank0
1158 11:40:54.763203 Final RX Vref Byte 1 = 60 to rank0
1159 11:40:54.766874 Final RX Vref Byte 0 = 52 to rank1
1160 11:40:54.769971 Final RX Vref Byte 1 = 60 to rank1==
1161 11:40:54.773476 Dram Type= 6, Freq= 0, CH_0, rank 0
1162 11:40:54.776568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1163 11:40:54.780368 ==
1164 11:40:54.780463 DQS Delay:
1165 11:40:54.780528 DQS0 = 0, DQS1 = 0
1166 11:40:54.783568 DQM Delay:
1167 11:40:54.783639 DQM0 = 91, DQM1 = 86
1168 11:40:54.786688 DQ Delay:
1169 11:40:54.790363 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1170 11:40:54.790458 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1171 11:40:54.793462 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1172 11:40:54.796685 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1173 11:40:54.799876
1174 11:40:54.799958
1175 11:40:54.806829 [DQSOSCAuto] RK0, (LSB)MR18= 0x473e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
1176 11:40:54.809905 CH0 RK0: MR19=606, MR18=473E
1177 11:40:54.816973 CH0_RK0: MR19=0x606, MR18=0x473E, DQSOSC=392, MR23=63, INC=96, DEC=64
1178 11:40:54.817056
1179 11:40:54.820227 ----->DramcWriteLeveling(PI) begin...
1180 11:40:54.820305 ==
1181 11:40:54.823500 Dram Type= 6, Freq= 0, CH_0, rank 1
1182 11:40:54.826752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 11:40:54.826832 ==
1184 11:40:54.830150 Write leveling (Byte 0): 33 => 33
1185 11:40:54.833526 Write leveling (Byte 1): 33 => 33
1186 11:40:54.877906 DramcWriteLeveling(PI) end<-----
1187 11:40:54.878080
1188 11:40:54.878195 ==
1189 11:40:54.878319 Dram Type= 6, Freq= 0, CH_0, rank 1
1190 11:40:54.878664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 11:40:54.878762 ==
1192 11:40:54.878930 [Gating] SW mode calibration
1193 11:40:54.879062 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1194 11:40:54.879158 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1195 11:40:54.879247 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1196 11:40:54.879337 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1197 11:40:54.879439 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1198 11:40:54.879538 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:40:54.921753 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:40:54.922079 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:40:54.922203 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:40:54.922275 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:40:54.922354 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:40:54.922460 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:40:54.922558 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:40:54.922651 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:40:54.922749 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:40:54.922818 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 11:40:54.925808 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 11:40:54.929677 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:40:54.932959 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:40:54.939610 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1213 11:40:54.943017 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1214 11:40:54.946271 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:40:54.949491 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:40:54.956049 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:40:54.959792 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:40:54.962865 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:40:54.969579 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:40:54.973285 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1221 11:40:54.976470 0 9 8 | B1->B0 | 2d2d 2b2b | 0 0 | (0 0) (0 0)
1222 11:40:54.983417 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 11:40:54.986648 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 11:40:54.989645 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 11:40:54.996536 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 11:40:54.999757 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 11:40:55.003368 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 11:40:55.007319 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1229 11:40:55.014646 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
1230 11:40:55.017751 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1231 11:40:55.021275 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:40:55.024152 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:40:55.031106 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:40:55.034489 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:40:55.038632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:40:55.044992 0 11 4 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
1237 11:40:55.048282 0 11 8 | B1->B0 | 3c3c 3a3a | 0 0 | (0 0) (0 0)
1238 11:40:55.051553 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 11:40:55.058197 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 11:40:55.061450 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 11:40:55.065250 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 11:40:55.071542 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 11:40:55.075278 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 11:40:55.078433 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 11:40:55.081498 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1246 11:40:55.088519 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 11:40:55.091732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 11:40:55.094760 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 11:40:55.101728 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 11:40:55.104775 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 11:40:55.107951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 11:40:55.114836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 11:40:55.118282 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 11:40:55.121349 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 11:40:55.128432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 11:40:55.131437 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 11:40:55.134720 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 11:40:55.141924 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 11:40:55.145255 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 11:40:55.148358 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 11:40:55.154950 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1262 11:40:55.158324 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:40:55.162031 Total UI for P1: 0, mck2ui 16
1264 11:40:55.165238 best dqsien dly found for B0: ( 0, 14, 8)
1265 11:40:55.168632 Total UI for P1: 0, mck2ui 16
1266 11:40:55.171749 best dqsien dly found for B1: ( 0, 14, 8)
1267 11:40:55.175489 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1268 11:40:55.178685 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1269 11:40:55.178768
1270 11:40:55.181800 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1271 11:40:55.184982 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1272 11:40:55.188762 [Gating] SW calibration Done
1273 11:40:55.188870 ==
1274 11:40:55.192156 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:40:55.195126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 11:40:55.195211 ==
1277 11:40:55.198255 RX Vref Scan: 0
1278 11:40:55.198341
1279 11:40:55.198406 RX Vref 0 -> 0, step: 1
1280 11:40:55.198490
1281 11:40:55.202118 RX Delay -130 -> 252, step: 16
1282 11:40:55.205301 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1283 11:40:55.212137 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1284 11:40:55.215011 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1285 11:40:55.218724 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1286 11:40:55.222163 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1287 11:40:55.225396 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1288 11:40:55.231572 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1289 11:40:55.234922 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1290 11:40:55.238841 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1291 11:40:55.241938 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1292 11:40:55.245251 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1293 11:40:55.251737 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1294 11:40:55.255147 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1295 11:40:55.258552 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1296 11:40:55.261722 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1297 11:40:55.264984 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1298 11:40:55.268446 ==
1299 11:40:55.272396 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:40:55.275670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:40:55.275772 ==
1302 11:40:55.275867 DQS Delay:
1303 11:40:55.279114 DQS0 = 0, DQS1 = 0
1304 11:40:55.279196 DQM Delay:
1305 11:40:55.282106 DQM0 = 93, DQM1 = 85
1306 11:40:55.282188 DQ Delay:
1307 11:40:55.285052 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1308 11:40:55.288815 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1309 11:40:55.291882 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1310 11:40:55.295576 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1311 11:40:55.295673
1312 11:40:55.295768
1313 11:40:55.295829 ==
1314 11:40:55.298683 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 11:40:55.301779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 11:40:55.301862 ==
1317 11:40:55.301928
1318 11:40:55.301989
1319 11:40:55.305024 TX Vref Scan disable
1320 11:40:55.308746 == TX Byte 0 ==
1321 11:40:55.311889 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1322 11:40:55.315159 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1323 11:40:55.318833 == TX Byte 1 ==
1324 11:40:55.321929 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1325 11:40:55.325092 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1326 11:40:55.325174 ==
1327 11:40:55.328253 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 11:40:55.332171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 11:40:55.335299 ==
1330 11:40:55.346570 TX Vref=22, minBit 8, minWin=27, winSum=446
1331 11:40:55.349748 TX Vref=24, minBit 1, minWin=28, winSum=455
1332 11:40:55.353007 TX Vref=26, minBit 1, minWin=28, winSum=459
1333 11:40:55.356379 TX Vref=28, minBit 11, minWin=27, winSum=457
1334 11:40:55.359775 TX Vref=30, minBit 11, minWin=27, winSum=456
1335 11:40:55.366603 TX Vref=32, minBit 12, minWin=27, winSum=451
1336 11:40:55.369839 [TxChooseVref] Worse bit 1, Min win 28, Win sum 459, Final Vref 26
1337 11:40:55.369922
1338 11:40:55.373033 Final TX Range 1 Vref 26
1339 11:40:55.373115
1340 11:40:55.373180 ==
1341 11:40:55.376315 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 11:40:55.379653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 11:40:55.379735 ==
1344 11:40:55.382933
1345 11:40:55.383014
1346 11:40:55.383079 TX Vref Scan disable
1347 11:40:55.386314 == TX Byte 0 ==
1348 11:40:55.389976 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1349 11:40:55.393503 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1350 11:40:55.396650 == TX Byte 1 ==
1351 11:40:55.399798 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1352 11:40:55.403506 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1353 11:40:55.406527
1354 11:40:55.406609 [DATLAT]
1355 11:40:55.406673 Freq=800, CH0 RK1
1356 11:40:55.406734
1357 11:40:55.409753 DATLAT Default: 0xa
1358 11:40:55.409849 0, 0xFFFF, sum = 0
1359 11:40:55.413501 1, 0xFFFF, sum = 0
1360 11:40:55.413614 2, 0xFFFF, sum = 0
1361 11:40:55.416692 3, 0xFFFF, sum = 0
1362 11:40:55.416777 4, 0xFFFF, sum = 0
1363 11:40:55.419965 5, 0xFFFF, sum = 0
1364 11:40:55.420078 6, 0xFFFF, sum = 0
1365 11:40:55.422999 7, 0xFFFF, sum = 0
1366 11:40:55.426692 8, 0xFFFF, sum = 0
1367 11:40:55.426777 9, 0x0, sum = 1
1368 11:40:55.426845 10, 0x0, sum = 2
1369 11:40:55.430384 11, 0x0, sum = 3
1370 11:40:55.430470 12, 0x0, sum = 4
1371 11:40:55.433612 best_step = 10
1372 11:40:55.433723
1373 11:40:55.433822 ==
1374 11:40:55.436929 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 11:40:55.440099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 11:40:55.440204 ==
1377 11:40:55.443360 RX Vref Scan: 0
1378 11:40:55.443449
1379 11:40:55.443512 RX Vref 0 -> 0, step: 1
1380 11:40:55.443569
1381 11:40:55.446497 RX Delay -95 -> 252, step: 8
1382 11:40:55.453547 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1383 11:40:55.456663 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1384 11:40:55.459854 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1385 11:40:55.463260 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1386 11:40:55.466517 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1387 11:40:55.473679 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1388 11:40:55.477135 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1389 11:40:55.480418 iDelay=209, Bit 7, Center 108 (9 ~ 208) 200
1390 11:40:55.483542 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1391 11:40:55.486760 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1392 11:40:55.490008 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1393 11:40:55.496989 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1394 11:40:55.500599 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1395 11:40:55.503543 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1396 11:40:55.506584 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1397 11:40:55.513434 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1398 11:40:55.513513 ==
1399 11:40:55.516782 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 11:40:55.520479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 11:40:55.520581 ==
1402 11:40:55.520690 DQS Delay:
1403 11:40:55.523657 DQS0 = 0, DQS1 = 0
1404 11:40:55.523758 DQM Delay:
1405 11:40:55.526710 DQM0 = 94, DQM1 = 83
1406 11:40:55.526815 DQ Delay:
1407 11:40:55.530513 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =92
1408 11:40:55.533569 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =108
1409 11:40:55.537264 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1410 11:40:55.540040 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1411 11:40:55.540122
1412 11:40:55.540187
1413 11:40:55.547268 [DQSOSCAuto] RK1, (LSB)MR18= 0x4414, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1414 11:40:55.550453 CH0 RK1: MR19=606, MR18=4414
1415 11:40:55.557085 CH0_RK1: MR19=0x606, MR18=0x4414, DQSOSC=392, MR23=63, INC=96, DEC=64
1416 11:40:55.560327 [RxdqsGatingPostProcess] freq 800
1417 11:40:55.566674 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1418 11:40:55.566758 Pre-setting of DQS Precalculation
1419 11:40:55.573346 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1420 11:40:55.573430 ==
1421 11:40:55.576683 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 11:40:55.579988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 11:40:55.580071 ==
1424 11:40:55.586717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1425 11:40:55.593331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1426 11:40:55.601780 [CA 0] Center 36 (6~67) winsize 62
1427 11:40:55.605062 [CA 1] Center 36 (6~67) winsize 62
1428 11:40:55.608075 [CA 2] Center 35 (5~66) winsize 62
1429 11:40:55.611560 [CA 3] Center 34 (4~65) winsize 62
1430 11:40:55.614638 [CA 4] Center 34 (4~65) winsize 62
1431 11:40:55.618459 [CA 5] Center 34 (4~65) winsize 62
1432 11:40:55.618533
1433 11:40:55.621496 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1434 11:40:55.621607
1435 11:40:55.624603 [CATrainingPosCal] consider 1 rank data
1436 11:40:55.628391 u2DelayCellTimex100 = 270/100 ps
1437 11:40:55.631527 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1438 11:40:55.635358 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 11:40:55.641871 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1440 11:40:55.644876 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1441 11:40:55.648059 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1442 11:40:55.652014 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 11:40:55.652097
1444 11:40:55.655279 CA PerBit enable=1, Macro0, CA PI delay=34
1445 11:40:55.655362
1446 11:40:55.658553 [CBTSetCACLKResult] CA Dly = 34
1447 11:40:55.658636 CS Dly: 6 (0~37)
1448 11:40:55.658703 ==
1449 11:40:55.661549 Dram Type= 6, Freq= 0, CH_1, rank 1
1450 11:40:55.669051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 11:40:55.669135 ==
1452 11:40:55.672379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 11:40:55.679623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 11:40:55.687705 [CA 0] Center 36 (6~67) winsize 62
1455 11:40:55.691255 [CA 1] Center 36 (6~67) winsize 62
1456 11:40:55.695089 [CA 2] Center 35 (5~66) winsize 62
1457 11:40:55.698477 [CA 3] Center 34 (4~65) winsize 62
1458 11:40:55.702553 [CA 4] Center 35 (4~66) winsize 63
1459 11:40:55.705835 [CA 5] Center 34 (4~65) winsize 62
1460 11:40:55.705908
1461 11:40:55.708977 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1462 11:40:55.709051
1463 11:40:55.712196 [CATrainingPosCal] consider 2 rank data
1464 11:40:55.715991 u2DelayCellTimex100 = 270/100 ps
1465 11:40:55.719062 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 11:40:55.722592 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 11:40:55.725899 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1468 11:40:55.728847 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 11:40:55.732602 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 11:40:55.735742 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 11:40:55.735825
1472 11:40:55.742069 CA PerBit enable=1, Macro0, CA PI delay=34
1473 11:40:55.742185
1474 11:40:55.742284 [CBTSetCACLKResult] CA Dly = 34
1475 11:40:55.745756 CS Dly: 7 (0~39)
1476 11:40:55.745872
1477 11:40:55.748735 ----->DramcWriteLeveling(PI) begin...
1478 11:40:55.748854 ==
1479 11:40:55.752570 Dram Type= 6, Freq= 0, CH_1, rank 0
1480 11:40:55.756135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1481 11:40:55.756243 ==
1482 11:40:55.759420 Write leveling (Byte 0): 27 => 27
1483 11:40:55.762597 Write leveling (Byte 1): 27 => 27
1484 11:40:55.765770 DramcWriteLeveling(PI) end<-----
1485 11:40:55.765877
1486 11:40:55.765972 ==
1487 11:40:55.768814 Dram Type= 6, Freq= 0, CH_1, rank 0
1488 11:40:55.772590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1489 11:40:55.775666 ==
1490 11:40:55.775777 [Gating] SW mode calibration
1491 11:40:55.782271 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1492 11:40:55.788866 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1493 11:40:55.792727 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1494 11:40:55.799546 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1495 11:40:55.802809 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:40:55.805981 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:40:55.812484 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:40:55.816499 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:40:55.819822 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:40:55.823053 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:40:55.829559 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:40:55.832663 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:40:55.836270 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:40:55.843103 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:40:55.846191 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:40:55.849312 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 11:40:55.856171 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 11:40:55.859759 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:40:55.862758 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1510 11:40:55.869310 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1511 11:40:55.873113 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:40:55.876142 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:40:55.883148 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:40:55.886486 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:40:55.889909 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:40:55.893165 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:40:55.899749 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:40:55.903048 0 9 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
1519 11:40:55.906277 0 9 8 | B1->B0 | 3131 3333 | 0 1 | (0 0) (1 1)
1520 11:40:55.912920 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 11:40:55.916741 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 11:40:55.920167 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 11:40:55.926721 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 11:40:55.929892 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 11:40:55.933132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1526 11:40:55.939786 0 10 4 | B1->B0 | 3232 2e2e | 1 0 | (0 0) (0 1)
1527 11:40:55.943498 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1528 11:40:55.946541 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:40:55.952905 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:40:55.956782 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:40:55.959748 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:40:55.966624 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:40:55.969536 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1534 11:40:55.973276 0 11 4 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
1535 11:40:55.976349 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1536 11:40:55.983239 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 11:40:55.986393 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 11:40:55.990251 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 11:40:55.996766 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 11:40:56.000276 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 11:40:56.003427 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 11:40:56.010124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1543 11:40:56.013380 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1544 11:40:56.016644 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 11:40:56.023716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 11:40:56.027029 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 11:40:56.030423 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 11:40:56.033754 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 11:40:56.040060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 11:40:56.043657 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 11:40:56.046783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 11:40:56.053370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 11:40:56.057343 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 11:40:56.060132 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 11:40:56.066780 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 11:40:56.070579 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 11:40:56.073750 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 11:40:56.080399 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1559 11:40:56.083631 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:40:56.087247 Total UI for P1: 0, mck2ui 16
1561 11:40:56.090337 best dqsien dly found for B0: ( 0, 14, 4)
1562 11:40:56.094036 Total UI for P1: 0, mck2ui 16
1563 11:40:56.097376 best dqsien dly found for B1: ( 0, 14, 4)
1564 11:40:56.100684 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1565 11:40:56.103978 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1566 11:40:56.104061
1567 11:40:56.107248 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1568 11:40:56.110425 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1569 11:40:56.113745 [Gating] SW calibration Done
1570 11:40:56.113817 ==
1571 11:40:56.117032 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 11:40:56.121068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 11:40:56.121166 ==
1574 11:40:56.124255 RX Vref Scan: 0
1575 11:40:56.124333
1576 11:40:56.124394 RX Vref 0 -> 0, step: 1
1577 11:40:56.124453
1578 11:40:56.127368 RX Delay -130 -> 252, step: 16
1579 11:40:56.130743 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1580 11:40:56.137361 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1581 11:40:56.140591 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1582 11:40:56.143816 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1583 11:40:56.147073 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1584 11:40:56.150860 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1585 11:40:56.157226 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1586 11:40:56.160740 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1587 11:40:56.163816 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1588 11:40:56.167622 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1589 11:40:56.170910 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1590 11:40:56.177570 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1591 11:40:56.180711 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1592 11:40:56.184312 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1593 11:40:56.187489 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1594 11:40:56.190971 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1595 11:40:56.194190 ==
1596 11:40:56.194272 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:40:56.200668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:40:56.200748 ==
1599 11:40:56.200881 DQS Delay:
1600 11:40:56.204131 DQS0 = 0, DQS1 = 0
1601 11:40:56.204209 DQM Delay:
1602 11:40:56.207387 DQM0 = 94, DQM1 = 88
1603 11:40:56.207465 DQ Delay:
1604 11:40:56.210766 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1605 11:40:56.214128 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1606 11:40:56.217438 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1607 11:40:56.220819 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1608 11:40:56.220900
1609 11:40:56.220993
1610 11:40:56.221072 ==
1611 11:40:56.224073 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 11:40:56.227947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 11:40:56.228034 ==
1614 11:40:56.228118
1615 11:40:56.228205
1616 11:40:56.231167 TX Vref Scan disable
1617 11:40:56.234518 == TX Byte 0 ==
1618 11:40:56.237732 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1619 11:40:56.240995 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1620 11:40:56.244268 == TX Byte 1 ==
1621 11:40:56.247513 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1622 11:40:56.251416 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1623 11:40:56.251521 ==
1624 11:40:56.255210 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 11:40:56.258491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 11:40:56.258568 ==
1627 11:40:56.272219 TX Vref=22, minBit 2, minWin=26, winSum=436
1628 11:40:56.275363 TX Vref=24, minBit 0, minWin=26, winSum=439
1629 11:40:56.278567 TX Vref=26, minBit 0, minWin=26, winSum=444
1630 11:40:56.282428 TX Vref=28, minBit 0, minWin=26, winSum=443
1631 11:40:56.285516 TX Vref=30, minBit 3, minWin=26, winSum=446
1632 11:40:56.288619 TX Vref=32, minBit 2, minWin=26, winSum=445
1633 11:40:56.295302 [TxChooseVref] Worse bit 3, Min win 26, Win sum 446, Final Vref 30
1634 11:40:56.295399
1635 11:40:56.298972 Final TX Range 1 Vref 30
1636 11:40:56.299050
1637 11:40:56.299121 ==
1638 11:40:56.302050 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 11:40:56.305458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 11:40:56.305627 ==
1641 11:40:56.305745
1642 11:40:56.305836
1643 11:40:56.309016 TX Vref Scan disable
1644 11:40:56.312101 == TX Byte 0 ==
1645 11:40:56.315366 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1646 11:40:56.318606 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1647 11:40:56.321929 == TX Byte 1 ==
1648 11:40:56.325354 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1649 11:40:56.328673 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1650 11:40:56.328794
1651 11:40:56.332392 [DATLAT]
1652 11:40:56.332512 Freq=800, CH1 RK0
1653 11:40:56.332619
1654 11:40:56.335480 DATLAT Default: 0xa
1655 11:40:56.335583 0, 0xFFFF, sum = 0
1656 11:40:56.338866 1, 0xFFFF, sum = 0
1657 11:40:56.338967 2, 0xFFFF, sum = 0
1658 11:40:56.342186 3, 0xFFFF, sum = 0
1659 11:40:56.342261 4, 0xFFFF, sum = 0
1660 11:40:56.345475 5, 0xFFFF, sum = 0
1661 11:40:56.345578 6, 0xFFFF, sum = 0
1662 11:40:56.348674 7, 0xFFFF, sum = 0
1663 11:40:56.348777 8, 0xFFFF, sum = 0
1664 11:40:56.351977 9, 0x0, sum = 1
1665 11:40:56.352053 10, 0x0, sum = 2
1666 11:40:56.355807 11, 0x0, sum = 3
1667 11:40:56.355908 12, 0x0, sum = 4
1668 11:40:56.359149 best_step = 10
1669 11:40:56.359259
1670 11:40:56.359351 ==
1671 11:40:56.362388 Dram Type= 6, Freq= 0, CH_1, rank 0
1672 11:40:56.365507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1673 11:40:56.365649 ==
1674 11:40:56.369131 RX Vref Scan: 1
1675 11:40:56.369267
1676 11:40:56.369332 Set Vref Range= 32 -> 127
1677 11:40:56.369391
1678 11:40:56.372004 RX Vref 32 -> 127, step: 1
1679 11:40:56.372081
1680 11:40:56.375791 RX Delay -79 -> 252, step: 8
1681 11:40:56.375903
1682 11:40:56.378853 Set Vref, RX VrefLevel [Byte0]: 32
1683 11:40:56.382604 [Byte1]: 32
1684 11:40:56.382709
1685 11:40:56.385745 Set Vref, RX VrefLevel [Byte0]: 33
1686 11:40:56.389094 [Byte1]: 33
1687 11:40:56.392338
1688 11:40:56.392440 Set Vref, RX VrefLevel [Byte0]: 34
1689 11:40:56.395321 [Byte1]: 34
1690 11:40:56.399838
1691 11:40:56.399916 Set Vref, RX VrefLevel [Byte0]: 35
1692 11:40:56.402821 [Byte1]: 35
1693 11:40:56.407009
1694 11:40:56.410680 Set Vref, RX VrefLevel [Byte0]: 36
1695 11:40:56.413855 [Byte1]: 36
1696 11:40:56.413930
1697 11:40:56.417382 Set Vref, RX VrefLevel [Byte0]: 37
1698 11:40:56.420500 [Byte1]: 37
1699 11:40:56.420600
1700 11:40:56.423715 Set Vref, RX VrefLevel [Byte0]: 38
1701 11:40:56.427029 [Byte1]: 38
1702 11:40:56.427130
1703 11:40:56.430429 Set Vref, RX VrefLevel [Byte0]: 39
1704 11:40:56.433700 [Byte1]: 39
1705 11:40:56.437443
1706 11:40:56.437523 Set Vref, RX VrefLevel [Byte0]: 40
1707 11:40:56.440714 [Byte1]: 40
1708 11:40:56.444815
1709 11:40:56.444905 Set Vref, RX VrefLevel [Byte0]: 41
1710 11:40:56.448661 [Byte1]: 41
1711 11:40:56.452719
1712 11:40:56.452842 Set Vref, RX VrefLevel [Byte0]: 42
1713 11:40:56.456022 [Byte1]: 42
1714 11:40:56.460381
1715 11:40:56.460484 Set Vref, RX VrefLevel [Byte0]: 43
1716 11:40:56.463704 [Byte1]: 43
1717 11:40:56.467639
1718 11:40:56.467743 Set Vref, RX VrefLevel [Byte0]: 44
1719 11:40:56.470734 [Byte1]: 44
1720 11:40:56.475290
1721 11:40:56.475402 Set Vref, RX VrefLevel [Byte0]: 45
1722 11:40:56.478591 [Byte1]: 45
1723 11:40:56.482812
1724 11:40:56.482917 Set Vref, RX VrefLevel [Byte0]: 46
1725 11:40:56.485827 [Byte1]: 46
1726 11:40:56.490152
1727 11:40:56.490268 Set Vref, RX VrefLevel [Byte0]: 47
1728 11:40:56.493748 [Byte1]: 47
1729 11:40:56.497759
1730 11:40:56.497867 Set Vref, RX VrefLevel [Byte0]: 48
1731 11:40:56.501419 [Byte1]: 48
1732 11:40:56.505718
1733 11:40:56.505818 Set Vref, RX VrefLevel [Byte0]: 49
1734 11:40:56.508934 [Byte1]: 49
1735 11:40:56.513263
1736 11:40:56.513367 Set Vref, RX VrefLevel [Byte0]: 50
1737 11:40:56.516528 [Byte1]: 50
1738 11:40:56.520377
1739 11:40:56.520491 Set Vref, RX VrefLevel [Byte0]: 51
1740 11:40:56.524106 [Byte1]: 51
1741 11:40:56.528227
1742 11:40:56.528329 Set Vref, RX VrefLevel [Byte0]: 52
1743 11:40:56.531576 [Byte1]: 52
1744 11:40:56.535604
1745 11:40:56.535704 Set Vref, RX VrefLevel [Byte0]: 53
1746 11:40:56.538828 [Byte1]: 53
1747 11:40:56.543417
1748 11:40:56.543518 Set Vref, RX VrefLevel [Byte0]: 54
1749 11:40:56.546106 [Byte1]: 54
1750 11:40:56.550685
1751 11:40:56.550780 Set Vref, RX VrefLevel [Byte0]: 55
1752 11:40:56.554074 [Byte1]: 55
1753 11:40:56.557983
1754 11:40:56.558084 Set Vref, RX VrefLevel [Byte0]: 56
1755 11:40:56.561284 [Byte1]: 56
1756 11:40:56.565625
1757 11:40:56.565720 Set Vref, RX VrefLevel [Byte0]: 57
1758 11:40:56.568997 [Byte1]: 57
1759 11:40:56.573032
1760 11:40:56.573116 Set Vref, RX VrefLevel [Byte0]: 58
1761 11:40:56.576395 [Byte1]: 58
1762 11:40:56.580619
1763 11:40:56.580701 Set Vref, RX VrefLevel [Byte0]: 59
1764 11:40:56.584323 [Byte1]: 59
1765 11:40:56.588926
1766 11:40:56.589008 Set Vref, RX VrefLevel [Byte0]: 60
1767 11:40:56.591798 [Byte1]: 60
1768 11:40:56.596098
1769 11:40:56.596182 Set Vref, RX VrefLevel [Byte0]: 61
1770 11:40:56.599109 [Byte1]: 61
1771 11:40:56.603423
1772 11:40:56.603506 Set Vref, RX VrefLevel [Byte0]: 62
1773 11:40:56.606589 [Byte1]: 62
1774 11:40:56.610753
1775 11:40:56.610834 Set Vref, RX VrefLevel [Byte0]: 63
1776 11:40:56.614588 [Byte1]: 63
1777 11:40:56.618755
1778 11:40:56.618839 Set Vref, RX VrefLevel [Byte0]: 64
1779 11:40:56.621793 [Byte1]: 64
1780 11:40:56.626222
1781 11:40:56.626311 Set Vref, RX VrefLevel [Byte0]: 65
1782 11:40:56.629431 [Byte1]: 65
1783 11:40:56.633716
1784 11:40:56.633796 Set Vref, RX VrefLevel [Byte0]: 66
1785 11:40:56.637063 [Byte1]: 66
1786 11:40:56.641024
1787 11:40:56.641102 Set Vref, RX VrefLevel [Byte0]: 67
1788 11:40:56.644288 [Byte1]: 67
1789 11:40:56.648841
1790 11:40:56.648936 Set Vref, RX VrefLevel [Byte0]: 68
1791 11:40:56.652203 [Byte1]: 68
1792 11:40:56.656074
1793 11:40:56.656190 Set Vref, RX VrefLevel [Byte0]: 69
1794 11:40:56.659248 [Byte1]: 69
1795 11:40:56.664054
1796 11:40:56.664166 Set Vref, RX VrefLevel [Byte0]: 70
1797 11:40:56.667342 [Byte1]: 70
1798 11:40:56.671158
1799 11:40:56.671272 Set Vref, RX VrefLevel [Byte0]: 71
1800 11:40:56.674356 [Byte1]: 71
1801 11:40:56.679056
1802 11:40:56.679163 Set Vref, RX VrefLevel [Byte0]: 72
1803 11:40:56.682385 [Byte1]: 72
1804 11:40:56.686673
1805 11:40:56.686777 Final RX Vref Byte 0 = 58 to rank0
1806 11:40:56.689900 Final RX Vref Byte 1 = 57 to rank0
1807 11:40:56.692983 Final RX Vref Byte 0 = 58 to rank1
1808 11:40:56.696200 Final RX Vref Byte 1 = 57 to rank1==
1809 11:40:56.699986 Dram Type= 6, Freq= 0, CH_1, rank 0
1810 11:40:56.702950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 11:40:56.706806 ==
1812 11:40:56.706922 DQS Delay:
1813 11:40:56.707021 DQS0 = 0, DQS1 = 0
1814 11:40:56.710054 DQM Delay:
1815 11:40:56.710157 DQM0 = 96, DQM1 = 91
1816 11:40:56.713556 DQ Delay:
1817 11:40:56.713659 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1818 11:40:56.716408 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1819 11:40:56.719982 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
1820 11:40:56.726699 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =96
1821 11:40:56.726803
1822 11:40:56.726908
1823 11:40:56.733387 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a46, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1824 11:40:56.736575 CH1 RK0: MR19=606, MR18=2A46
1825 11:40:56.742697 CH1_RK0: MR19=0x606, MR18=0x2A46, DQSOSC=392, MR23=63, INC=96, DEC=64
1826 11:40:56.742786
1827 11:40:56.746513 ----->DramcWriteLeveling(PI) begin...
1828 11:40:56.746587 ==
1829 11:40:56.749851 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 11:40:56.753189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 11:40:56.753260 ==
1832 11:40:56.756523 Write leveling (Byte 0): 27 => 27
1833 11:40:56.759764 Write leveling (Byte 1): 28 => 28
1834 11:40:56.763053 DramcWriteLeveling(PI) end<-----
1835 11:40:56.763136
1836 11:40:56.763213 ==
1837 11:40:56.766277 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 11:40:56.769533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 11:40:56.769640 ==
1840 11:40:56.772775 [Gating] SW mode calibration
1841 11:40:56.779483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1842 11:40:56.786112 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1843 11:40:56.789775 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1844 11:40:56.792920 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1845 11:40:56.799407 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:40:56.803251 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:40:56.806229 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:40:56.813046 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:40:56.816263 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:40:56.819568 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:40:56.826459 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:40:56.829534 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:40:56.833115 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:40:56.840125 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:40:56.843218 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:40:56.846444 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:40:56.853395 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:40:56.856614 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1859 11:40:56.859909 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:40:56.863215 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1861 11:40:56.869746 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:40:56.873682 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:40:56.876871 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:40:56.883390 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:40:56.886768 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:40:56.890071 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:40:56.896599 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:40:56.900450 0 9 4 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
1869 11:40:56.903738 0 9 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
1870 11:40:56.910053 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 11:40:56.913264 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 11:40:56.916812 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 11:40:56.924065 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 11:40:56.927129 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 11:40:56.930333 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
1876 11:40:56.933642 0 10 4 | B1->B0 | 2b2b 3131 | 1 1 | (1 0) (1 0)
1877 11:40:56.939944 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1878 11:40:56.943676 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:40:56.946828 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:40:56.953565 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:40:56.956551 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:40:56.960317 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:40:56.967001 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:40:56.970326 0 11 4 | B1->B0 | 3b3b 2e2e | 0 0 | (1 1) (0 0)
1885 11:40:56.973533 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 11:40:56.979972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 11:40:56.983315 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 11:40:56.987238 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 11:40:56.993794 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 11:40:56.997006 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 11:40:57.000346 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 11:40:57.003461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1893 11:40:57.010555 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 11:40:57.013606 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 11:40:57.017376 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 11:40:57.023390 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 11:40:57.027206 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 11:40:57.030422 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 11:40:57.037060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 11:40:57.040188 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 11:40:57.043555 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 11:40:57.050434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 11:40:57.053656 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 11:40:57.056742 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 11:40:57.063478 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 11:40:57.067243 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 11:40:57.070513 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1908 11:40:57.077274 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1909 11:40:57.077380 Total UI for P1: 0, mck2ui 16
1910 11:40:57.083677 best dqsien dly found for B1: ( 0, 14, 0)
1911 11:40:57.086940 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 11:40:57.090721 Total UI for P1: 0, mck2ui 16
1913 11:40:57.094087 best dqsien dly found for B0: ( 0, 14, 4)
1914 11:40:57.097414 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1915 11:40:57.100704 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1916 11:40:57.100812
1917 11:40:57.104015 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1918 11:40:57.107425 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1919 11:40:57.110451 [Gating] SW calibration Done
1920 11:40:57.110553 ==
1921 11:40:57.113701 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 11:40:57.116916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 11:40:57.117019 ==
1924 11:40:57.120560 RX Vref Scan: 0
1925 11:40:57.120682
1926 11:40:57.120776 RX Vref 0 -> 0, step: 1
1927 11:40:57.123827
1928 11:40:57.123927 RX Delay -130 -> 252, step: 16
1929 11:40:57.130420 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1930 11:40:57.134075 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1931 11:40:57.137268 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1932 11:40:57.140605 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1933 11:40:57.144302 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1934 11:40:57.147502 iDelay=222, Bit 5, Center 117 (14 ~ 221) 208
1935 11:40:57.153774 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1936 11:40:57.156951 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1937 11:40:57.160869 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1938 11:40:57.164316 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1939 11:40:57.167189 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1940 11:40:57.174048 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1941 11:40:57.177039 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1942 11:40:57.180367 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1943 11:40:57.184267 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1944 11:40:57.190869 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1945 11:40:57.191007 ==
1946 11:40:57.194039 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 11:40:57.197603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 11:40:57.197706 ==
1949 11:40:57.197810 DQS Delay:
1950 11:40:57.200753 DQS0 = 0, DQS1 = 0
1951 11:40:57.200893 DQM Delay:
1952 11:40:57.204201 DQM0 = 94, DQM1 = 89
1953 11:40:57.204300 DQ Delay:
1954 11:40:57.207423 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1955 11:40:57.210470 DQ4 =85, DQ5 =117, DQ6 =101, DQ7 =93
1956 11:40:57.213714 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1957 11:40:57.217789 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1958 11:40:57.217893
1959 11:40:57.217995
1960 11:40:57.218090 ==
1961 11:40:57.221078 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 11:40:57.224233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 11:40:57.224337 ==
1964 11:40:57.224428
1965 11:40:57.224532
1966 11:40:57.227203 TX Vref Scan disable
1967 11:40:57.231044 == TX Byte 0 ==
1968 11:40:57.234060 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 11:40:57.237659 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 11:40:57.240872 == TX Byte 1 ==
1971 11:40:57.243865 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1972 11:40:57.247742 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1973 11:40:57.247842 ==
1974 11:40:57.250889 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 11:40:57.254115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 11:40:57.257305 ==
1977 11:40:57.268792 TX Vref=22, minBit 3, minWin=26, winSum=440
1978 11:40:57.271994 TX Vref=24, minBit 3, minWin=25, winSum=441
1979 11:40:57.275721 TX Vref=26, minBit 1, minWin=27, winSum=447
1980 11:40:57.278673 TX Vref=28, minBit 1, minWin=27, winSum=448
1981 11:40:57.282624 TX Vref=30, minBit 1, minWin=27, winSum=452
1982 11:40:57.285824 TX Vref=32, minBit 0, minWin=27, winSum=448
1983 11:40:57.292100 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1984 11:40:57.292184
1985 11:40:57.295489 Final TX Range 1 Vref 30
1986 11:40:57.295572
1987 11:40:57.295637 ==
1988 11:40:57.298823 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 11:40:57.302073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 11:40:57.302157 ==
1991 11:40:57.302222
1992 11:40:57.305307
1993 11:40:57.305389 TX Vref Scan disable
1994 11:40:57.308605 == TX Byte 0 ==
1995 11:40:57.312458 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1996 11:40:57.315588 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1997 11:40:57.318794 == TX Byte 1 ==
1998 11:40:57.322186 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1999 11:40:57.325534 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2000 11:40:57.328662
2001 11:40:57.328744 [DATLAT]
2002 11:40:57.328835 Freq=800, CH1 RK1
2003 11:40:57.328959
2004 11:40:57.332416 DATLAT Default: 0xa
2005 11:40:57.332499 0, 0xFFFF, sum = 0
2006 11:40:57.335545 1, 0xFFFF, sum = 0
2007 11:40:57.335673 2, 0xFFFF, sum = 0
2008 11:40:57.338786 3, 0xFFFF, sum = 0
2009 11:40:57.338871 4, 0xFFFF, sum = 0
2010 11:40:57.342525 5, 0xFFFF, sum = 0
2011 11:40:57.342609 6, 0xFFFF, sum = 0
2012 11:40:57.345853 7, 0xFFFF, sum = 0
2013 11:40:57.345937 8, 0xFFFF, sum = 0
2014 11:40:57.348989 9, 0x0, sum = 1
2015 11:40:57.349110 10, 0x0, sum = 2
2016 11:40:57.352097 11, 0x0, sum = 3
2017 11:40:57.352182 12, 0x0, sum = 4
2018 11:40:57.355589 best_step = 10
2019 11:40:57.355677
2020 11:40:57.355744 ==
2021 11:40:57.358828 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 11:40:57.362773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 11:40:57.362875 ==
2024 11:40:57.365989 RX Vref Scan: 0
2025 11:40:57.366072
2026 11:40:57.366139 RX Vref 0 -> 0, step: 1
2027 11:40:57.366201
2028 11:40:57.369149 RX Delay -79 -> 252, step: 8
2029 11:40:57.372418 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2030 11:40:57.378958 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2031 11:40:57.382658 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2032 11:40:57.386255 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2033 11:40:57.389227 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2034 11:40:57.392771 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2035 11:40:57.399120 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2036 11:40:57.402300 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2037 11:40:57.406180 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2038 11:40:57.409492 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2039 11:40:57.412851 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2040 11:40:57.416023 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2041 11:40:57.422366 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2042 11:40:57.425710 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2043 11:40:57.429721 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2044 11:40:57.432421 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2045 11:40:57.432526 ==
2046 11:40:57.436057 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 11:40:57.442924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 11:40:57.443026 ==
2049 11:40:57.443096 DQS Delay:
2050 11:40:57.443159 DQS0 = 0, DQS1 = 0
2051 11:40:57.445974 DQM Delay:
2052 11:40:57.446046 DQM0 = 97, DQM1 = 91
2053 11:40:57.449205 DQ Delay:
2054 11:40:57.452918 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2055 11:40:57.456151 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2056 11:40:57.459336 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2057 11:40:57.462918 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2058 11:40:57.463006
2059 11:40:57.463076
2060 11:40:57.469520 [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2061 11:40:57.473168 CH1 RK1: MR19=606, MR18=4610
2062 11:40:57.479852 CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64
2063 11:40:57.483039 [RxdqsGatingPostProcess] freq 800
2064 11:40:57.486116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2065 11:40:57.489318 Pre-setting of DQS Precalculation
2066 11:40:57.496374 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2067 11:40:57.503016 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2068 11:40:57.509227 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2069 11:40:57.509343
2070 11:40:57.509459
2071 11:40:57.512659 [Calibration Summary] 1600 Mbps
2072 11:40:57.512774 CH 0, Rank 0
2073 11:40:57.516040 SW Impedance : PASS
2074 11:40:57.519304 DUTY Scan : NO K
2075 11:40:57.519415 ZQ Calibration : PASS
2076 11:40:57.523044 Jitter Meter : NO K
2077 11:40:57.523167 CBT Training : PASS
2078 11:40:57.526407 Write leveling : PASS
2079 11:40:57.529643 RX DQS gating : PASS
2080 11:40:57.529764 RX DQ/DQS(RDDQC) : PASS
2081 11:40:57.532983 TX DQ/DQS : PASS
2082 11:40:57.536188 RX DATLAT : PASS
2083 11:40:57.536295 RX DQ/DQS(Engine): PASS
2084 11:40:57.539520 TX OE : NO K
2085 11:40:57.539644 All Pass.
2086 11:40:57.539751
2087 11:40:57.542716 CH 0, Rank 1
2088 11:40:57.542826 SW Impedance : PASS
2089 11:40:57.546457 DUTY Scan : NO K
2090 11:40:57.549410 ZQ Calibration : PASS
2091 11:40:57.549490 Jitter Meter : NO K
2092 11:40:57.553145 CBT Training : PASS
2093 11:40:57.556169 Write leveling : PASS
2094 11:40:57.556244 RX DQS gating : PASS
2095 11:40:57.559789 RX DQ/DQS(RDDQC) : PASS
2096 11:40:57.563003 TX DQ/DQS : PASS
2097 11:40:57.563080 RX DATLAT : PASS
2098 11:40:57.566007 RX DQ/DQS(Engine): PASS
2099 11:40:57.566087 TX OE : NO K
2100 11:40:57.569920 All Pass.
2101 11:40:57.570008
2102 11:40:57.570115 CH 1, Rank 0
2103 11:40:57.573265 SW Impedance : PASS
2104 11:40:57.573342 DUTY Scan : NO K
2105 11:40:57.576455 ZQ Calibration : PASS
2106 11:40:57.579519 Jitter Meter : NO K
2107 11:40:57.579597 CBT Training : PASS
2108 11:40:57.582858 Write leveling : PASS
2109 11:40:57.586266 RX DQS gating : PASS
2110 11:40:57.586346 RX DQ/DQS(RDDQC) : PASS
2111 11:40:57.589989 TX DQ/DQS : PASS
2112 11:40:57.593315 RX DATLAT : PASS
2113 11:40:57.593397 RX DQ/DQS(Engine): PASS
2114 11:40:57.596554 TX OE : NO K
2115 11:40:57.596632 All Pass.
2116 11:40:57.596696
2117 11:40:57.599611 CH 1, Rank 1
2118 11:40:57.599684 SW Impedance : PASS
2119 11:40:57.603360 DUTY Scan : NO K
2120 11:40:57.603436 ZQ Calibration : PASS
2121 11:40:57.606510 Jitter Meter : NO K
2122 11:40:57.610269 CBT Training : PASS
2123 11:40:57.610353 Write leveling : PASS
2124 11:40:57.613394 RX DQS gating : PASS
2125 11:40:57.616418 RX DQ/DQS(RDDQC) : PASS
2126 11:40:57.616494 TX DQ/DQS : PASS
2127 11:40:57.620014 RX DATLAT : PASS
2128 11:40:57.623482 RX DQ/DQS(Engine): PASS
2129 11:40:57.623559 TX OE : NO K
2130 11:40:57.626674 All Pass.
2131 11:40:57.626749
2132 11:40:57.626810 DramC Write-DBI off
2133 11:40:57.629881 PER_BANK_REFRESH: Hybrid Mode
2134 11:40:57.629979 TX_TRACKING: ON
2135 11:40:57.633185 [GetDramInforAfterCalByMRR] Vendor 6.
2136 11:40:57.639961 [GetDramInforAfterCalByMRR] Revision 606.
2137 11:40:57.643195 [GetDramInforAfterCalByMRR] Revision 2 0.
2138 11:40:57.643298 MR0 0x3b3b
2139 11:40:57.643402 MR8 0x5151
2140 11:40:57.646691 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 11:40:57.646773
2142 11:40:57.649708 MR0 0x3b3b
2143 11:40:57.649818 MR8 0x5151
2144 11:40:57.653620 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 11:40:57.653707
2146 11:40:57.663509 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2147 11:40:57.666690 [FAST_K] Save calibration result to emmc
2148 11:40:57.669863 [FAST_K] Save calibration result to emmc
2149 11:40:57.673387 dram_init: config_dvfs: 1
2150 11:40:57.676686 dramc_set_vcore_voltage set vcore to 662500
2151 11:40:57.679965 Read voltage for 1200, 2
2152 11:40:57.680044 Vio18 = 0
2153 11:40:57.680120 Vcore = 662500
2154 11:40:57.683273 Vdram = 0
2155 11:40:57.683347 Vddq = 0
2156 11:40:57.683417 Vmddr = 0
2157 11:40:57.690304 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2158 11:40:57.693552 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2159 11:40:57.696739 MEM_TYPE=3, freq_sel=15
2160 11:40:57.700105 sv_algorithm_assistance_LP4_1600
2161 11:40:57.703408 ============ PULL DRAM RESETB DOWN ============
2162 11:40:57.706577 ========== PULL DRAM RESETB DOWN end =========
2163 11:40:57.713392 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 11:40:57.716684 ===================================
2165 11:40:57.716812 LPDDR4 DRAM CONFIGURATION
2166 11:40:57.719759 ===================================
2167 11:40:57.723566 EX_ROW_EN[0] = 0x0
2168 11:40:57.723695 EX_ROW_EN[1] = 0x0
2169 11:40:57.726783 LP4Y_EN = 0x0
2170 11:40:57.730008 WORK_FSP = 0x0
2171 11:40:57.730126 WL = 0x4
2172 11:40:57.733354 RL = 0x4
2173 11:40:57.733439 BL = 0x2
2174 11:40:57.736518 RPST = 0x0
2175 11:40:57.736623 RD_PRE = 0x0
2176 11:40:57.740359 WR_PRE = 0x1
2177 11:40:57.740462 WR_PST = 0x0
2178 11:40:57.743685 DBI_WR = 0x0
2179 11:40:57.743793 DBI_RD = 0x0
2180 11:40:57.747038 OTF = 0x1
2181 11:40:57.750187 ===================================
2182 11:40:57.753459 ===================================
2183 11:40:57.753543 ANA top config
2184 11:40:57.756704 ===================================
2185 11:40:57.760391 DLL_ASYNC_EN = 0
2186 11:40:57.763527 ALL_SLAVE_EN = 0
2187 11:40:57.763604 NEW_RANK_MODE = 1
2188 11:40:57.766652 DLL_IDLE_MODE = 1
2189 11:40:57.770462 LP45_APHY_COMB_EN = 1
2190 11:40:57.773807 TX_ODT_DIS = 1
2191 11:40:57.773886 NEW_8X_MODE = 1
2192 11:40:57.776971 ===================================
2193 11:40:57.779935 ===================================
2194 11:40:57.783301 data_rate = 2400
2195 11:40:57.786598 CKR = 1
2196 11:40:57.789814 DQ_P2S_RATIO = 8
2197 11:40:57.793429 ===================================
2198 11:40:57.796766 CA_P2S_RATIO = 8
2199 11:40:57.799977 DQ_CA_OPEN = 0
2200 11:40:57.800111 DQ_SEMI_OPEN = 0
2201 11:40:57.803227 CA_SEMI_OPEN = 0
2202 11:40:57.807304 CA_FULL_RATE = 0
2203 11:40:57.810295 DQ_CKDIV4_EN = 0
2204 11:40:57.813475 CA_CKDIV4_EN = 0
2205 11:40:57.816615 CA_PREDIV_EN = 0
2206 11:40:57.816718 PH8_DLY = 17
2207 11:40:57.820453 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2208 11:40:57.823571 DQ_AAMCK_DIV = 4
2209 11:40:57.826660 CA_AAMCK_DIV = 4
2210 11:40:57.830573 CA_ADMCK_DIV = 4
2211 11:40:57.830702 DQ_TRACK_CA_EN = 0
2212 11:40:57.833682 CA_PICK = 1200
2213 11:40:57.836769 CA_MCKIO = 1200
2214 11:40:57.840200 MCKIO_SEMI = 0
2215 11:40:57.843972 PLL_FREQ = 2366
2216 11:40:57.846747 DQ_UI_PI_RATIO = 32
2217 11:40:57.850832 CA_UI_PI_RATIO = 0
2218 11:40:57.853935 ===================================
2219 11:40:57.857321 ===================================
2220 11:40:57.857426 memory_type:LPDDR4
2221 11:40:57.860448 GP_NUM : 10
2222 11:40:57.863678 SRAM_EN : 1
2223 11:40:57.863782 MD32_EN : 0
2224 11:40:57.867278 ===================================
2225 11:40:57.870290 [ANA_INIT] >>>>>>>>>>>>>>
2226 11:40:57.873480 <<<<<< [CONFIGURE PHASE]: ANA_TX
2227 11:40:57.877205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2228 11:40:57.880497 ===================================
2229 11:40:57.883654 data_rate = 2400,PCW = 0X5b00
2230 11:40:57.887458 ===================================
2231 11:40:57.890026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2232 11:40:57.893974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2233 11:40:57.900207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 11:40:57.903524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2235 11:40:57.906945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2236 11:40:57.910272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2237 11:40:57.914032 [ANA_INIT] flow start
2238 11:40:57.917289 [ANA_INIT] PLL >>>>>>>>
2239 11:40:57.917366 [ANA_INIT] PLL <<<<<<<<
2240 11:40:57.920664 [ANA_INIT] MIDPI >>>>>>>>
2241 11:40:57.923783 [ANA_INIT] MIDPI <<<<<<<<
2242 11:40:57.923871 [ANA_INIT] DLL >>>>>>>>
2243 11:40:57.926878 [ANA_INIT] DLL <<<<<<<<
2244 11:40:57.930086 [ANA_INIT] flow end
2245 11:40:57.933625 ============ LP4 DIFF to SE enter ============
2246 11:40:57.936767 ============ LP4 DIFF to SE exit ============
2247 11:40:57.940553 [ANA_INIT] <<<<<<<<<<<<<
2248 11:40:57.943742 [Flow] Enable top DCM control >>>>>
2249 11:40:57.947004 [Flow] Enable top DCM control <<<<<
2250 11:40:57.950551 Enable DLL master slave shuffle
2251 11:40:57.953921 ==============================================================
2252 11:40:57.957021 Gating Mode config
2253 11:40:57.963676 ==============================================================
2254 11:40:57.963789 Config description:
2255 11:40:57.973770 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2256 11:40:57.980339 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2257 11:40:57.983442 SELPH_MODE 0: By rank 1: By Phase
2258 11:40:57.990787 ==============================================================
2259 11:40:57.993813 GAT_TRACK_EN = 1
2260 11:40:57.997050 RX_GATING_MODE = 2
2261 11:40:58.000476 RX_GATING_TRACK_MODE = 2
2262 11:40:58.003681 SELPH_MODE = 1
2263 11:40:58.007389 PICG_EARLY_EN = 1
2264 11:40:58.010408 VALID_LAT_VALUE = 1
2265 11:40:58.013703 ==============================================================
2266 11:40:58.017510 Enter into Gating configuration >>>>
2267 11:40:58.020944 Exit from Gating configuration <<<<
2268 11:40:58.024078 Enter into DVFS_PRE_config >>>>>
2269 11:40:58.033685 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2270 11:40:58.037328 Exit from DVFS_PRE_config <<<<<
2271 11:40:58.040463 Enter into PICG configuration >>>>
2272 11:40:58.044136 Exit from PICG configuration <<<<
2273 11:40:58.047149 [RX_INPUT] configuration >>>>>
2274 11:40:58.050512 [RX_INPUT] configuration <<<<<
2275 11:40:58.053696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2276 11:40:58.060380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2277 11:40:58.066974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 11:40:58.073735 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 11:40:58.080603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 11:40:58.083576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 11:40:58.091098 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2282 11:40:58.094213 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2283 11:40:58.097240 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2284 11:40:58.100963 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2285 11:40:58.107317 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2286 11:40:58.110624 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 11:40:58.114445 ===================================
2288 11:40:58.117541 LPDDR4 DRAM CONFIGURATION
2289 11:40:58.120546 ===================================
2290 11:40:58.120652 EX_ROW_EN[0] = 0x0
2291 11:40:58.124306 EX_ROW_EN[1] = 0x0
2292 11:40:58.124422 LP4Y_EN = 0x0
2293 11:40:58.127693 WORK_FSP = 0x0
2294 11:40:58.127804 WL = 0x4
2295 11:40:58.130936 RL = 0x4
2296 11:40:58.131047 BL = 0x2
2297 11:40:58.133983 RPST = 0x0
2298 11:40:58.134103 RD_PRE = 0x0
2299 11:40:58.137788 WR_PRE = 0x1
2300 11:40:58.137891 WR_PST = 0x0
2301 11:40:58.141044 DBI_WR = 0x0
2302 11:40:58.141122 DBI_RD = 0x0
2303 11:40:58.144101 OTF = 0x1
2304 11:40:58.147696 ===================================
2305 11:40:58.150799 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2306 11:40:58.154029 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2307 11:40:58.160698 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 11:40:58.164021 ===================================
2309 11:40:58.164109 LPDDR4 DRAM CONFIGURATION
2310 11:40:58.168050 ===================================
2311 11:40:58.171223 EX_ROW_EN[0] = 0x10
2312 11:40:58.174461 EX_ROW_EN[1] = 0x0
2313 11:40:58.174549 LP4Y_EN = 0x0
2314 11:40:58.177795 WORK_FSP = 0x0
2315 11:40:58.177883 WL = 0x4
2316 11:40:58.181083 RL = 0x4
2317 11:40:58.181171 BL = 0x2
2318 11:40:58.184353 RPST = 0x0
2319 11:40:58.184467 RD_PRE = 0x0
2320 11:40:58.188018 WR_PRE = 0x1
2321 11:40:58.188124 WR_PST = 0x0
2322 11:40:58.191100 DBI_WR = 0x0
2323 11:40:58.191231 DBI_RD = 0x0
2324 11:40:58.194076 OTF = 0x1
2325 11:40:58.197915 ===================================
2326 11:40:58.204295 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2327 11:40:58.204397 ==
2328 11:40:58.207960 Dram Type= 6, Freq= 0, CH_0, rank 0
2329 11:40:58.211105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2330 11:40:58.211194 ==
2331 11:40:58.214535 [Duty_Offset_Calibration]
2332 11:40:58.214603 B0:2 B1:1 CA:1
2333 11:40:58.214664
2334 11:40:58.217758 [DutyScan_Calibration_Flow] k_type=0
2335 11:40:58.227568
2336 11:40:58.227671 ==CLK 0==
2337 11:40:58.231135 Final CLK duty delay cell = 0
2338 11:40:58.234310 [0] MAX Duty = 5187%(X100), DQS PI = 24
2339 11:40:58.237578 [0] MIN Duty = 4844%(X100), DQS PI = 48
2340 11:40:58.237652 [0] AVG Duty = 5015%(X100)
2341 11:40:58.240757
2342 11:40:58.240862 CH0 CLK Duty spec in!! Max-Min= 343%
2343 11:40:58.247619 [DutyScan_Calibration_Flow] ====Done====
2344 11:40:58.247714
2345 11:40:58.250824 [DutyScan_Calibration_Flow] k_type=1
2346 11:40:58.266420
2347 11:40:58.266524 ==DQS 0 ==
2348 11:40:58.269196 Final DQS duty delay cell = -4
2349 11:40:58.273125 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2350 11:40:58.276311 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2351 11:40:58.279641 [-4] AVG Duty = 4953%(X100)
2352 11:40:58.279746
2353 11:40:58.279845 ==DQS 1 ==
2354 11:40:58.282997 Final DQS duty delay cell = 0
2355 11:40:58.286397 [0] MAX Duty = 5187%(X100), DQS PI = 62
2356 11:40:58.289562 [0] MIN Duty = 5000%(X100), DQS PI = 34
2357 11:40:58.292794 [0] AVG Duty = 5093%(X100)
2358 11:40:58.292915
2359 11:40:58.296661 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2360 11:40:58.296767
2361 11:40:58.299751 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2362 11:40:58.302906 [DutyScan_Calibration_Flow] ====Done====
2363 11:40:58.303004
2364 11:40:58.306052 [DutyScan_Calibration_Flow] k_type=3
2365 11:40:58.323329
2366 11:40:58.323405 ==DQM 0 ==
2367 11:40:58.326533 Final DQM duty delay cell = 0
2368 11:40:58.329915 [0] MAX Duty = 5156%(X100), DQS PI = 30
2369 11:40:58.332910 [0] MIN Duty = 4906%(X100), DQS PI = 52
2370 11:40:58.336632 [0] AVG Duty = 5031%(X100)
2371 11:40:58.336737
2372 11:40:58.336864 ==DQM 1 ==
2373 11:40:58.339862 Final DQM duty delay cell = 0
2374 11:40:58.343016 [0] MAX Duty = 5125%(X100), DQS PI = 60
2375 11:40:58.346448 [0] MIN Duty = 5031%(X100), DQS PI = 20
2376 11:40:58.346562 [0] AVG Duty = 5078%(X100)
2377 11:40:58.349614
2378 11:40:58.353213 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2379 11:40:58.353323
2380 11:40:58.356233 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2381 11:40:58.360063 [DutyScan_Calibration_Flow] ====Done====
2382 11:40:58.360164
2383 11:40:58.363184 [DutyScan_Calibration_Flow] k_type=2
2384 11:40:58.379842
2385 11:40:58.379927 ==DQ 0 ==
2386 11:40:58.383041 Final DQ duty delay cell = 0
2387 11:40:58.386383 [0] MAX Duty = 5031%(X100), DQS PI = 24
2388 11:40:58.389519 [0] MIN Duty = 4906%(X100), DQS PI = 0
2389 11:40:58.389618 [0] AVG Duty = 4968%(X100)
2390 11:40:58.389707
2391 11:40:58.393011 ==DQ 1 ==
2392 11:40:58.396045 Final DQ duty delay cell = 0
2393 11:40:58.399948 [0] MAX Duty = 5093%(X100), DQS PI = 24
2394 11:40:58.402993 [0] MIN Duty = 4969%(X100), DQS PI = 2
2395 11:40:58.403092 [0] AVG Duty = 5031%(X100)
2396 11:40:58.403181
2397 11:40:58.406105 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2398 11:40:58.406181
2399 11:40:58.409363 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2400 11:40:58.416318 [DutyScan_Calibration_Flow] ====Done====
2401 11:40:58.416407 ==
2402 11:40:58.419469 Dram Type= 6, Freq= 0, CH_1, rank 0
2403 11:40:58.423093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2404 11:40:58.423165 ==
2405 11:40:58.426413 [Duty_Offset_Calibration]
2406 11:40:58.426522 B0:1 B1:0 CA:0
2407 11:40:58.426584
2408 11:40:58.429670 [DutyScan_Calibration_Flow] k_type=0
2409 11:40:58.438332
2410 11:40:58.438417 ==CLK 0==
2411 11:40:58.442025 Final CLK duty delay cell = -4
2412 11:40:58.445251 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2413 11:40:58.448304 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2414 11:40:58.452023 [-4] AVG Duty = 4953%(X100)
2415 11:40:58.452123
2416 11:40:58.455281 CH1 CLK Duty spec in!! Max-Min= 93%
2417 11:40:58.458599 [DutyScan_Calibration_Flow] ====Done====
2418 11:40:58.458670
2419 11:40:58.461686 [DutyScan_Calibration_Flow] k_type=1
2420 11:40:58.478131
2421 11:40:58.478245 ==DQS 0 ==
2422 11:40:58.481521 Final DQS duty delay cell = 0
2423 11:40:58.484754 [0] MAX Duty = 5062%(X100), DQS PI = 54
2424 11:40:58.488162 [0] MIN Duty = 4875%(X100), DQS PI = 30
2425 11:40:58.488269 [0] AVG Duty = 4968%(X100)
2426 11:40:58.491472
2427 11:40:58.491555 ==DQS 1 ==
2428 11:40:58.494739 Final DQS duty delay cell = 0
2429 11:40:58.498518 [0] MAX Duty = 5218%(X100), DQS PI = 52
2430 11:40:58.501766 [0] MIN Duty = 4969%(X100), DQS PI = 4
2431 11:40:58.501850 [0] AVG Duty = 5093%(X100)
2432 11:40:58.501916
2433 11:40:58.508249 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2434 11:40:58.508333
2435 11:40:58.511407 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2436 11:40:58.515145 [DutyScan_Calibration_Flow] ====Done====
2437 11:40:58.515228
2438 11:40:58.518305 [DutyScan_Calibration_Flow] k_type=3
2439 11:40:58.535001
2440 11:40:58.535092 ==DQM 0 ==
2441 11:40:58.538025 Final DQM duty delay cell = 0
2442 11:40:58.541466 [0] MAX Duty = 5156%(X100), DQS PI = 4
2443 11:40:58.544702 [0] MIN Duty = 5031%(X100), DQS PI = 30
2444 11:40:58.544789 [0] AVG Duty = 5093%(X100)
2445 11:40:58.548037
2446 11:40:58.548108 ==DQM 1 ==
2447 11:40:58.551435 Final DQM duty delay cell = 0
2448 11:40:58.554483 [0] MAX Duty = 5062%(X100), DQS PI = 12
2449 11:40:58.557996 [0] MIN Duty = 4875%(X100), DQS PI = 4
2450 11:40:58.558080 [0] AVG Duty = 4968%(X100)
2451 11:40:58.561384
2452 11:40:58.564549 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2453 11:40:58.564640
2454 11:40:58.568140 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2455 11:40:58.571312 [DutyScan_Calibration_Flow] ====Done====
2456 11:40:58.571388
2457 11:40:58.574779 [DutyScan_Calibration_Flow] k_type=2
2458 11:40:58.590680
2459 11:40:58.590768 ==DQ 0 ==
2460 11:40:58.594030 Final DQ duty delay cell = -4
2461 11:40:58.597309 [-4] MAX Duty = 5062%(X100), DQS PI = 24
2462 11:40:58.600400 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2463 11:40:58.603569 [-4] AVG Duty = 5000%(X100)
2464 11:40:58.603642
2465 11:40:58.603709 ==DQ 1 ==
2466 11:40:58.606972 Final DQ duty delay cell = 0
2467 11:40:58.610280 [0] MAX Duty = 5093%(X100), DQS PI = 10
2468 11:40:58.614040 [0] MIN Duty = 4938%(X100), DQS PI = 2
2469 11:40:58.614117 [0] AVG Duty = 5015%(X100)
2470 11:40:58.617193
2471 11:40:58.620446 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2472 11:40:58.620521
2473 11:40:58.623563 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2474 11:40:58.627400 [DutyScan_Calibration_Flow] ====Done====
2475 11:40:58.630272 nWR fixed to 30
2476 11:40:58.630354 [ModeRegInit_LP4] CH0 RK0
2477 11:40:58.633872 [ModeRegInit_LP4] CH0 RK1
2478 11:40:58.636831 [ModeRegInit_LP4] CH1 RK0
2479 11:40:58.640445 [ModeRegInit_LP4] CH1 RK1
2480 11:40:58.640518 match AC timing 7
2481 11:40:58.643481 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2482 11:40:58.650650 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2483 11:40:58.653879 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2484 11:40:58.657327 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2485 11:40:58.663645 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2486 11:40:58.663727 ==
2487 11:40:58.667445 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 11:40:58.670660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 11:40:58.670768 ==
2490 11:40:58.677161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 11:40:58.683375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2492 11:40:58.690662 [CA 0] Center 39 (8~70) winsize 63
2493 11:40:58.693905 [CA 1] Center 39 (8~70) winsize 63
2494 11:40:58.697275 [CA 2] Center 35 (5~66) winsize 62
2495 11:40:58.700533 [CA 3] Center 34 (4~65) winsize 62
2496 11:40:58.703775 [CA 4] Center 33 (3~64) winsize 62
2497 11:40:58.707568 [CA 5] Center 32 (3~62) winsize 60
2498 11:40:58.707667
2499 11:40:58.710815 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2500 11:40:58.710914
2501 11:40:58.714253 [CATrainingPosCal] consider 1 rank data
2502 11:40:58.717395 u2DelayCellTimex100 = 270/100 ps
2503 11:40:58.720551 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2504 11:40:58.724361 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2505 11:40:58.730683 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2506 11:40:58.733740 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2507 11:40:58.736987 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2508 11:40:58.740593 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2509 11:40:58.740706
2510 11:40:58.743741 CA PerBit enable=1, Macro0, CA PI delay=32
2511 11:40:58.743841
2512 11:40:58.746990 [CBTSetCACLKResult] CA Dly = 32
2513 11:40:58.747079 CS Dly: 6 (0~37)
2514 11:40:58.750960 ==
2515 11:40:58.751032 Dram Type= 6, Freq= 0, CH_0, rank 1
2516 11:40:58.757511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 11:40:58.757595 ==
2518 11:40:58.760967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 11:40:58.767428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2520 11:40:58.776226 [CA 0] Center 38 (8~69) winsize 62
2521 11:40:58.779448 [CA 1] Center 38 (8~69) winsize 62
2522 11:40:58.782600 [CA 2] Center 35 (5~66) winsize 62
2523 11:40:58.785925 [CA 3] Center 34 (4~65) winsize 62
2524 11:40:58.789673 [CA 4] Center 33 (3~64) winsize 62
2525 11:40:58.792711 [CA 5] Center 32 (3~62) winsize 60
2526 11:40:58.792857
2527 11:40:58.796397 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2528 11:40:58.796532
2529 11:40:58.799624 [CATrainingPosCal] consider 2 rank data
2530 11:40:58.802855 u2DelayCellTimex100 = 270/100 ps
2531 11:40:58.806101 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2532 11:40:58.809344 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2533 11:40:58.816526 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2534 11:40:58.819741 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2535 11:40:58.823003 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2536 11:40:58.826280 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2537 11:40:58.826364
2538 11:40:58.829252 CA PerBit enable=1, Macro0, CA PI delay=32
2539 11:40:58.829336
2540 11:40:58.832815 [CBTSetCACLKResult] CA Dly = 32
2541 11:40:58.832918 CS Dly: 7 (0~39)
2542 11:40:58.833011
2543 11:40:58.835952 ----->DramcWriteLeveling(PI) begin...
2544 11:40:58.839860 ==
2545 11:40:58.842876 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 11:40:58.846759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 11:40:58.846849 ==
2548 11:40:58.849963 Write leveling (Byte 0): 33 => 33
2549 11:40:58.853310 Write leveling (Byte 1): 30 => 30
2550 11:40:58.856381 DramcWriteLeveling(PI) end<-----
2551 11:40:58.856466
2552 11:40:58.856533 ==
2553 11:40:58.859677 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 11:40:58.862915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 11:40:58.863001 ==
2556 11:40:58.866256 [Gating] SW mode calibration
2557 11:40:58.873397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2558 11:40:58.876717 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2559 11:40:58.883054 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2560 11:40:58.886310 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 11:40:58.890058 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 11:40:58.896330 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 11:40:58.899452 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 11:40:58.903175 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 11:40:58.909553 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2566 11:40:58.913301 0 15 28 | B1->B0 | 3333 2424 | 1 0 | (1 1) (0 0)
2567 11:40:58.916492 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2568 11:40:58.923179 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 11:40:58.926435 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 11:40:58.929831 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 11:40:58.936224 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 11:40:58.939847 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 11:40:58.943306 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2574 11:40:58.946373 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2575 11:40:58.953121 1 1 0 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
2576 11:40:58.956745 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 11:40:58.960000 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 11:40:58.966316 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 11:40:58.969762 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 11:40:58.973089 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 11:40:58.980094 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 11:40:58.983464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2583 11:40:58.986563 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2584 11:40:58.993439 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 11:40:58.996750 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 11:40:58.999956 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 11:40:59.006630 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 11:40:59.009853 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 11:40:59.013678 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 11:40:59.020079 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 11:40:59.023389 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 11:40:59.026672 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 11:40:59.029950 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 11:40:59.037148 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 11:40:59.039828 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 11:40:59.043015 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 11:40:59.049820 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2598 11:40:59.053065 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2599 11:40:59.056596 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2600 11:40:59.060250 Total UI for P1: 0, mck2ui 16
2601 11:40:59.063347 best dqsien dly found for B0: ( 1, 3, 26)
2602 11:40:59.070005 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:40:59.070116 Total UI for P1: 0, mck2ui 16
2604 11:40:59.076651 best dqsien dly found for B1: ( 1, 4, 0)
2605 11:40:59.079821 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2606 11:40:59.083055 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2607 11:40:59.083132
2608 11:40:59.086449 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2609 11:40:59.089752 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2610 11:40:59.093504 [Gating] SW calibration Done
2611 11:40:59.093614 ==
2612 11:40:59.096632 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 11:40:59.100366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 11:40:59.100471 ==
2615 11:40:59.103734 RX Vref Scan: 0
2616 11:40:59.103838
2617 11:40:59.103938 RX Vref 0 -> 0, step: 1
2618 11:40:59.104032
2619 11:40:59.106811 RX Delay -40 -> 252, step: 8
2620 11:40:59.110454 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2621 11:40:59.116712 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2622 11:40:59.120583 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2623 11:40:59.123726 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2624 11:40:59.127097 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2625 11:40:59.130389 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2626 11:40:59.133659 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2627 11:40:59.140738 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2628 11:40:59.143413 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2629 11:40:59.146710 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2630 11:40:59.150414 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2631 11:40:59.153670 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2632 11:40:59.160516 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2633 11:40:59.163468 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2634 11:40:59.167378 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2635 11:40:59.170295 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2636 11:40:59.170406 ==
2637 11:40:59.173933 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 11:40:59.180671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 11:40:59.180809 ==
2640 11:40:59.180894 DQS Delay:
2641 11:40:59.180956 DQS0 = 0, DQS1 = 0
2642 11:40:59.183724 DQM Delay:
2643 11:40:59.183822 DQM0 = 121, DQM1 = 113
2644 11:40:59.187008 DQ Delay:
2645 11:40:59.190435 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2646 11:40:59.193757 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2647 11:40:59.197536 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2648 11:40:59.200654 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2649 11:40:59.200764
2650 11:40:59.200867
2651 11:40:59.200928 ==
2652 11:40:59.203743 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 11:40:59.207598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 11:40:59.207704 ==
2655 11:40:59.207800
2656 11:40:59.207889
2657 11:40:59.210865 TX Vref Scan disable
2658 11:40:59.214059 == TX Byte 0 ==
2659 11:40:59.217310 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2660 11:40:59.220735 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2661 11:40:59.223677 == TX Byte 1 ==
2662 11:40:59.227372 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2663 11:40:59.230654 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2664 11:40:59.230732 ==
2665 11:40:59.233833 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 11:40:59.240374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 11:40:59.240485 ==
2668 11:40:59.250883 TX Vref=22, minBit 12, minWin=24, winSum=408
2669 11:40:59.254540 TX Vref=24, minBit 0, minWin=25, winSum=412
2670 11:40:59.257622 TX Vref=26, minBit 7, minWin=25, winSum=421
2671 11:40:59.260807 TX Vref=28, minBit 1, minWin=26, winSum=427
2672 11:40:59.264161 TX Vref=30, minBit 0, minWin=26, winSum=427
2673 11:40:59.268016 TX Vref=32, minBit 2, minWin=26, winSum=422
2674 11:40:59.274240 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
2675 11:40:59.274349
2676 11:40:59.277994 Final TX Range 1 Vref 28
2677 11:40:59.278100
2678 11:40:59.278206 ==
2679 11:40:59.280982 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 11:40:59.284330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 11:40:59.284437 ==
2682 11:40:59.284537
2683 11:40:59.287478
2684 11:40:59.287594 TX Vref Scan disable
2685 11:40:59.291388 == TX Byte 0 ==
2686 11:40:59.294640 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2687 11:40:59.298014 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2688 11:40:59.301266 == TX Byte 1 ==
2689 11:40:59.304595 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2690 11:40:59.307598 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2691 11:40:59.307704
2692 11:40:59.311282 [DATLAT]
2693 11:40:59.311390 Freq=1200, CH0 RK0
2694 11:40:59.311486
2695 11:40:59.314275 DATLAT Default: 0xd
2696 11:40:59.314383 0, 0xFFFF, sum = 0
2697 11:40:59.317414 1, 0xFFFF, sum = 0
2698 11:40:59.317523 2, 0xFFFF, sum = 0
2699 11:40:59.321314 3, 0xFFFF, sum = 0
2700 11:40:59.321417 4, 0xFFFF, sum = 0
2701 11:40:59.324590 5, 0xFFFF, sum = 0
2702 11:40:59.324708 6, 0xFFFF, sum = 0
2703 11:40:59.327700 7, 0xFFFF, sum = 0
2704 11:40:59.327804 8, 0xFFFF, sum = 0
2705 11:40:59.330731 9, 0xFFFF, sum = 0
2706 11:40:59.334273 10, 0xFFFF, sum = 0
2707 11:40:59.334377 11, 0xFFFF, sum = 0
2708 11:40:59.337814 12, 0x0, sum = 1
2709 11:40:59.337919 13, 0x0, sum = 2
2710 11:40:59.338016 14, 0x0, sum = 3
2711 11:40:59.340962 15, 0x0, sum = 4
2712 11:40:59.341051 best_step = 13
2713 11:40:59.341156
2714 11:40:59.344440 ==
2715 11:40:59.344541 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 11:40:59.351067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 11:40:59.351176 ==
2718 11:40:59.351282 RX Vref Scan: 1
2719 11:40:59.351386
2720 11:40:59.354310 Set Vref Range= 32 -> 127
2721 11:40:59.354409
2722 11:40:59.357654 RX Vref 32 -> 127, step: 1
2723 11:40:59.357769
2724 11:40:59.360854 RX Delay -13 -> 252, step: 4
2725 11:40:59.360953
2726 11:40:59.364626 Set Vref, RX VrefLevel [Byte0]: 32
2727 11:40:59.367957 [Byte1]: 32
2728 11:40:59.368057
2729 11:40:59.371098 Set Vref, RX VrefLevel [Byte0]: 33
2730 11:40:59.374327 [Byte1]: 33
2731 11:40:59.374406
2732 11:40:59.377464 Set Vref, RX VrefLevel [Byte0]: 34
2733 11:40:59.381091 [Byte1]: 34
2734 11:40:59.384921
2735 11:40:59.385004 Set Vref, RX VrefLevel [Byte0]: 35
2736 11:40:59.388589 [Byte1]: 35
2737 11:40:59.392900
2738 11:40:59.392982 Set Vref, RX VrefLevel [Byte0]: 36
2739 11:40:59.396097 [Byte1]: 36
2740 11:40:59.400540
2741 11:40:59.400622 Set Vref, RX VrefLevel [Byte0]: 37
2742 11:40:59.403864 [Byte1]: 37
2743 11:40:59.408523
2744 11:40:59.408622 Set Vref, RX VrefLevel [Byte0]: 38
2745 11:40:59.412336 [Byte1]: 38
2746 11:40:59.416541
2747 11:40:59.416623 Set Vref, RX VrefLevel [Byte0]: 39
2748 11:40:59.419825 [Byte1]: 39
2749 11:40:59.424883
2750 11:40:59.424965 Set Vref, RX VrefLevel [Byte0]: 40
2751 11:40:59.428013 [Byte1]: 40
2752 11:40:59.432714
2753 11:40:59.432835 Set Vref, RX VrefLevel [Byte0]: 41
2754 11:40:59.435776 [Byte1]: 41
2755 11:40:59.440227
2756 11:40:59.440341 Set Vref, RX VrefLevel [Byte0]: 42
2757 11:40:59.443570 [Byte1]: 42
2758 11:40:59.448010
2759 11:40:59.448126 Set Vref, RX VrefLevel [Byte0]: 43
2760 11:40:59.451281 [Byte1]: 43
2761 11:40:59.456059
2762 11:40:59.456141 Set Vref, RX VrefLevel [Byte0]: 44
2763 11:40:59.459425 [Byte1]: 44
2764 11:40:59.463947
2765 11:40:59.464029 Set Vref, RX VrefLevel [Byte0]: 45
2766 11:40:59.467245 [Byte1]: 45
2767 11:40:59.471686
2768 11:40:59.471769 Set Vref, RX VrefLevel [Byte0]: 46
2769 11:40:59.474907 [Byte1]: 46
2770 11:40:59.479503
2771 11:40:59.479585 Set Vref, RX VrefLevel [Byte0]: 47
2772 11:40:59.483315 [Byte1]: 47
2773 11:40:59.487638
2774 11:40:59.487720 Set Vref, RX VrefLevel [Byte0]: 48
2775 11:40:59.490749 [Byte1]: 48
2776 11:40:59.495612
2777 11:40:59.495694 Set Vref, RX VrefLevel [Byte0]: 49
2778 11:40:59.498882 [Byte1]: 49
2779 11:40:59.503262
2780 11:40:59.503345 Set Vref, RX VrefLevel [Byte0]: 50
2781 11:40:59.506428 [Byte1]: 50
2782 11:40:59.511193
2783 11:40:59.511275 Set Vref, RX VrefLevel [Byte0]: 51
2784 11:40:59.514444 [Byte1]: 51
2785 11:40:59.519421
2786 11:40:59.519503 Set Vref, RX VrefLevel [Byte0]: 52
2787 11:40:59.522615 [Byte1]: 52
2788 11:40:59.527124
2789 11:40:59.527206 Set Vref, RX VrefLevel [Byte0]: 53
2790 11:40:59.530202 [Byte1]: 53
2791 11:40:59.534711
2792 11:40:59.534793 Set Vref, RX VrefLevel [Byte0]: 54
2793 11:40:59.537928 [Byte1]: 54
2794 11:40:59.543030
2795 11:40:59.543109 Set Vref, RX VrefLevel [Byte0]: 55
2796 11:40:59.546242 [Byte1]: 55
2797 11:40:59.550647
2798 11:40:59.550724 Set Vref, RX VrefLevel [Byte0]: 56
2799 11:40:59.553779 [Byte1]: 56
2800 11:40:59.558817
2801 11:40:59.558932 Set Vref, RX VrefLevel [Byte0]: 57
2802 11:40:59.562049 [Byte1]: 57
2803 11:40:59.566508
2804 11:40:59.566616 Set Vref, RX VrefLevel [Byte0]: 58
2805 11:40:59.569807 [Byte1]: 58
2806 11:40:59.574334
2807 11:40:59.574441 Set Vref, RX VrefLevel [Byte0]: 59
2808 11:40:59.577630 [Byte1]: 59
2809 11:40:59.582346
2810 11:40:59.582453 Set Vref, RX VrefLevel [Byte0]: 60
2811 11:40:59.585593 [Byte1]: 60
2812 11:40:59.590173
2813 11:40:59.590294 Set Vref, RX VrefLevel [Byte0]: 61
2814 11:40:59.593190 [Byte1]: 61
2815 11:40:59.598036
2816 11:40:59.598119 Set Vref, RX VrefLevel [Byte0]: 62
2817 11:40:59.601121 [Byte1]: 62
2818 11:40:59.606067
2819 11:40:59.606151 Set Vref, RX VrefLevel [Byte0]: 63
2820 11:40:59.609333 [Byte1]: 63
2821 11:40:59.613866
2822 11:40:59.613949 Set Vref, RX VrefLevel [Byte0]: 64
2823 11:40:59.617116 [Byte1]: 64
2824 11:40:59.621671
2825 11:40:59.621755 Set Vref, RX VrefLevel [Byte0]: 65
2826 11:40:59.624935 [Byte1]: 65
2827 11:40:59.629569
2828 11:40:59.629652 Set Vref, RX VrefLevel [Byte0]: 66
2829 11:40:59.633297 [Byte1]: 66
2830 11:40:59.637455
2831 11:40:59.637643 Set Vref, RX VrefLevel [Byte0]: 67
2832 11:40:59.640747 [Byte1]: 67
2833 11:40:59.645341
2834 11:40:59.645447 Set Vref, RX VrefLevel [Byte0]: 68
2835 11:40:59.648506 [Byte1]: 68
2836 11:40:59.652958
2837 11:40:59.653068 Set Vref, RX VrefLevel [Byte0]: 69
2838 11:40:59.656649 [Byte1]: 69
2839 11:40:59.661006
2840 11:40:59.661083 Final RX Vref Byte 0 = 56 to rank0
2841 11:40:59.664776 Final RX Vref Byte 1 = 54 to rank0
2842 11:40:59.668052 Final RX Vref Byte 0 = 56 to rank1
2843 11:40:59.671138 Final RX Vref Byte 1 = 54 to rank1==
2844 11:40:59.674296 Dram Type= 6, Freq= 0, CH_0, rank 0
2845 11:40:59.681107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 11:40:59.681212 ==
2847 11:40:59.681309 DQS Delay:
2848 11:40:59.681401 DQS0 = 0, DQS1 = 0
2849 11:40:59.684426 DQM Delay:
2850 11:40:59.684529 DQM0 = 120, DQM1 = 113
2851 11:40:59.687693 DQ Delay:
2852 11:40:59.690950 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =118
2853 11:40:59.694815 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2854 11:40:59.697875 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2855 11:40:59.700984 DQ12 =120, DQ13 =116, DQ14 =126, DQ15 =122
2856 11:40:59.701062
2857 11:40:59.701125
2858 11:40:59.711079 [DQSOSCAuto] RK0, (LSB)MR18= 0x120c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2859 11:40:59.711187 CH0 RK0: MR19=404, MR18=120C
2860 11:40:59.717850 CH0_RK0: MR19=0x404, MR18=0x120C, DQSOSC=403, MR23=63, INC=40, DEC=26
2861 11:40:59.717955
2862 11:40:59.721035 ----->DramcWriteLeveling(PI) begin...
2863 11:40:59.721136 ==
2864 11:40:59.724974 Dram Type= 6, Freq= 0, CH_0, rank 1
2865 11:40:59.728057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 11:40:59.731447 ==
2867 11:40:59.731548 Write leveling (Byte 0): 34 => 34
2868 11:40:59.734777 Write leveling (Byte 1): 29 => 29
2869 11:40:59.738041 DramcWriteLeveling(PI) end<-----
2870 11:40:59.738145
2871 11:40:59.738239 ==
2872 11:40:59.741779 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 11:40:59.744667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 11:40:59.748194 ==
2875 11:40:59.748302 [Gating] SW mode calibration
2876 11:40:59.758223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2877 11:40:59.761456 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2878 11:40:59.765216 0 15 0 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
2879 11:40:59.771745 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 11:40:59.774827 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 11:40:59.778666 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 11:40:59.784799 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 11:40:59.788564 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 11:40:59.791943 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 11:40:59.798311 0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (0 0) (0 0)
2886 11:40:59.801570 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2887 11:40:59.805270 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 11:40:59.812057 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 11:40:59.815004 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 11:40:59.818176 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 11:40:59.821725 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 11:40:59.828339 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 11:40:59.832125 1 0 28 | B1->B0 | 3838 3a3a | 0 0 | (0 0) (0 0)
2894 11:40:59.835413 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2895 11:40:59.841949 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 11:40:59.845168 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 11:40:59.848349 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 11:40:59.855230 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 11:40:59.858280 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 11:40:59.861986 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 11:40:59.868269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2902 11:40:59.871449 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2903 11:40:59.875168 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 11:40:59.881647 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 11:40:59.884981 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 11:40:59.888285 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 11:40:59.895511 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 11:40:59.898197 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 11:40:59.902041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 11:40:59.905209 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 11:40:59.911536 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 11:40:59.915261 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 11:40:59.918764 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 11:40:59.924998 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 11:40:59.928752 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 11:40:59.932113 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 11:40:59.938460 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2918 11:40:59.941819 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 11:40:59.945146 Total UI for P1: 0, mck2ui 16
2920 11:40:59.948435 best dqsien dly found for B0: ( 1, 3, 28)
2921 11:40:59.951635 Total UI for P1: 0, mck2ui 16
2922 11:40:59.955547 best dqsien dly found for B1: ( 1, 3, 28)
2923 11:40:59.958891 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2924 11:40:59.962265 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2925 11:40:59.962397
2926 11:40:59.965220 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2927 11:40:59.968769 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2928 11:40:59.971787 [Gating] SW calibration Done
2929 11:40:59.971896 ==
2930 11:40:59.975160 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 11:40:59.978919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 11:40:59.979023 ==
2933 11:40:59.981948 RX Vref Scan: 0
2934 11:40:59.982047
2935 11:40:59.985165 RX Vref 0 -> 0, step: 1
2936 11:40:59.985239
2937 11:40:59.985300 RX Delay -40 -> 252, step: 8
2938 11:40:59.991752 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2939 11:40:59.995563 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2940 11:40:59.998800 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2941 11:41:00.002058 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2942 11:41:00.005426 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2943 11:41:00.012522 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2944 11:41:00.015694 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2945 11:41:00.018914 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2946 11:41:00.022313 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2947 11:41:00.025615 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2948 11:41:00.032060 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2949 11:41:00.035986 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2950 11:41:00.039314 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2951 11:41:00.042448 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2952 11:41:00.045785 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2953 11:41:00.052363 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2954 11:41:00.052440 ==
2955 11:41:00.055634 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 11:41:00.058831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 11:41:00.058920 ==
2958 11:41:00.058987 DQS Delay:
2959 11:41:00.062603 DQS0 = 0, DQS1 = 0
2960 11:41:00.062691 DQM Delay:
2961 11:41:00.066024 DQM0 = 122, DQM1 = 113
2962 11:41:00.066093 DQ Delay:
2963 11:41:00.069216 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2964 11:41:00.072444 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2965 11:41:00.075357 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
2966 11:41:00.078847 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2967 11:41:00.078922
2968 11:41:00.078983
2969 11:41:00.079040 ==
2970 11:41:00.082132 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 11:41:00.088906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 11:41:00.088999 ==
2973 11:41:00.089082
2974 11:41:00.089172
2975 11:41:00.089249 TX Vref Scan disable
2976 11:41:00.092627 == TX Byte 0 ==
2977 11:41:00.096253 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2978 11:41:00.099552 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2979 11:41:00.102737 == TX Byte 1 ==
2980 11:41:00.106046 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2981 11:41:00.109383 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2982 11:41:00.112670 ==
2983 11:41:00.116106 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 11:41:00.119222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 11:41:00.119305 ==
2986 11:41:00.130851 TX Vref=22, minBit 5, minWin=24, winSum=409
2987 11:41:00.134454 TX Vref=24, minBit 2, minWin=25, winSum=414
2988 11:41:00.137448 TX Vref=26, minBit 3, minWin=25, winSum=420
2989 11:41:00.141243 TX Vref=28, minBit 1, minWin=26, winSum=424
2990 11:41:00.144256 TX Vref=30, minBit 2, minWin=26, winSum=425
2991 11:41:00.147632 TX Vref=32, minBit 5, minWin=25, winSum=423
2992 11:41:00.154152 [TxChooseVref] Worse bit 2, Min win 26, Win sum 425, Final Vref 30
2993 11:41:00.154235
2994 11:41:00.158004 Final TX Range 1 Vref 30
2995 11:41:00.158117
2996 11:41:00.158185 ==
2997 11:41:00.161336 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 11:41:00.164440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 11:41:00.164524 ==
3000 11:41:00.164606
3001 11:41:00.167772
3002 11:41:00.167854 TX Vref Scan disable
3003 11:41:00.171094 == TX Byte 0 ==
3004 11:41:00.174340 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3005 11:41:00.178141 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3006 11:41:00.181396 == TX Byte 1 ==
3007 11:41:00.184516 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3008 11:41:00.187446 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3009 11:41:00.187545
3010 11:41:00.190926 [DATLAT]
3011 11:41:00.191010 Freq=1200, CH0 RK1
3012 11:41:00.191090
3013 11:41:00.194894 DATLAT Default: 0xd
3014 11:41:00.194976 0, 0xFFFF, sum = 0
3015 11:41:00.198156 1, 0xFFFF, sum = 0
3016 11:41:00.198240 2, 0xFFFF, sum = 0
3017 11:41:00.201106 3, 0xFFFF, sum = 0
3018 11:41:00.201190 4, 0xFFFF, sum = 0
3019 11:41:00.204724 5, 0xFFFF, sum = 0
3020 11:41:00.204853 6, 0xFFFF, sum = 0
3021 11:41:00.207901 7, 0xFFFF, sum = 0
3022 11:41:00.207984 8, 0xFFFF, sum = 0
3023 11:41:00.211223 9, 0xFFFF, sum = 0
3024 11:41:00.214599 10, 0xFFFF, sum = 0
3025 11:41:00.214682 11, 0xFFFF, sum = 0
3026 11:41:00.217910 12, 0x0, sum = 1
3027 11:41:00.217992 13, 0x0, sum = 2
3028 11:41:00.218058 14, 0x0, sum = 3
3029 11:41:00.221268 15, 0x0, sum = 4
3030 11:41:00.221351 best_step = 13
3031 11:41:00.221417
3032 11:41:00.221477 ==
3033 11:41:00.224491 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 11:41:00.231333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 11:41:00.231430 ==
3036 11:41:00.231512 RX Vref Scan: 0
3037 11:41:00.231588
3038 11:41:00.234686 RX Vref 0 -> 0, step: 1
3039 11:41:00.234862
3040 11:41:00.237852 RX Delay -13 -> 252, step: 4
3041 11:41:00.241070 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3042 11:41:00.244636 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3043 11:41:00.250877 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3044 11:41:00.254188 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3045 11:41:00.257489 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3046 11:41:00.260708 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3047 11:41:00.264163 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3048 11:41:00.271240 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3049 11:41:00.274677 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3050 11:41:00.277418 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3051 11:41:00.281371 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3052 11:41:00.284722 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3053 11:41:00.291116 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3054 11:41:00.294249 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3055 11:41:00.297338 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3056 11:41:00.301033 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3057 11:41:00.301115 ==
3058 11:41:00.304196 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 11:41:00.311209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 11:41:00.311314 ==
3061 11:41:00.311415 DQS Delay:
3062 11:41:00.311505 DQS0 = 0, DQS1 = 0
3063 11:41:00.314335 DQM Delay:
3064 11:41:00.314412 DQM0 = 121, DQM1 = 111
3065 11:41:00.317653 DQ Delay:
3066 11:41:00.320925 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3067 11:41:00.324227 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3068 11:41:00.327515 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3069 11:41:00.330852 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3070 11:41:00.330970
3071 11:41:00.331112
3072 11:41:00.337805 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3073 11:41:00.340867 CH0 RK1: MR19=403, MR18=CED
3074 11:41:00.347636 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3075 11:41:00.350940 [RxdqsGatingPostProcess] freq 1200
3076 11:41:00.357631 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3077 11:41:00.360925 best DQS0 dly(2T, 0.5T) = (0, 11)
3078 11:41:00.361002 best DQS1 dly(2T, 0.5T) = (0, 12)
3079 11:41:00.364700 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3080 11:41:00.367968 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3081 11:41:00.371067 best DQS0 dly(2T, 0.5T) = (0, 11)
3082 11:41:00.374343 best DQS1 dly(2T, 0.5T) = (0, 11)
3083 11:41:00.377695 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3084 11:41:00.381031 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3085 11:41:00.384280 Pre-setting of DQS Precalculation
3086 11:41:00.391293 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3087 11:41:00.391374 ==
3088 11:41:00.394795 Dram Type= 6, Freq= 0, CH_1, rank 0
3089 11:41:00.398021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 11:41:00.398095 ==
3091 11:41:00.401384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 11:41:00.407660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3093 11:41:00.417226 [CA 0] Center 37 (7~68) winsize 62
3094 11:41:00.420345 [CA 1] Center 37 (7~68) winsize 62
3095 11:41:00.423774 [CA 2] Center 35 (5~65) winsize 61
3096 11:41:00.427776 [CA 3] Center 34 (4~64) winsize 61
3097 11:41:00.431036 [CA 4] Center 34 (4~64) winsize 61
3098 11:41:00.434288 [CA 5] Center 33 (3~63) winsize 61
3099 11:41:00.434399
3100 11:41:00.437474 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3101 11:41:00.437553
3102 11:41:00.440670 [CATrainingPosCal] consider 1 rank data
3103 11:41:00.443805 u2DelayCellTimex100 = 270/100 ps
3104 11:41:00.447533 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 11:41:00.450580 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 11:41:00.454204 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3107 11:41:00.461138 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 11:41:00.464281 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3109 11:41:00.467332 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3110 11:41:00.467434
3111 11:41:00.470696 CA PerBit enable=1, Macro0, CA PI delay=33
3112 11:41:00.470784
3113 11:41:00.473943 [CBTSetCACLKResult] CA Dly = 33
3114 11:41:00.474018 CS Dly: 7 (0~38)
3115 11:41:00.474081 ==
3116 11:41:00.477718 Dram Type= 6, Freq= 0, CH_1, rank 1
3117 11:41:00.484388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 11:41:00.484494 ==
3119 11:41:00.487546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 11:41:00.494004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 11:41:00.503007 [CA 0] Center 37 (7~68) winsize 62
3122 11:41:00.506133 [CA 1] Center 37 (7~68) winsize 62
3123 11:41:00.509265 [CA 2] Center 35 (5~66) winsize 62
3124 11:41:00.513210 [CA 3] Center 34 (4~65) winsize 62
3125 11:41:00.516199 [CA 4] Center 34 (4~65) winsize 62
3126 11:41:00.519349 [CA 5] Center 34 (4~64) winsize 61
3127 11:41:00.519453
3128 11:41:00.522768 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3129 11:41:00.522876
3130 11:41:00.526542 [CATrainingPosCal] consider 2 rank data
3131 11:41:00.529884 u2DelayCellTimex100 = 270/100 ps
3132 11:41:00.532590 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 11:41:00.536534 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 11:41:00.543067 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3135 11:41:00.546548 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 11:41:00.549984 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 11:41:00.553061 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3138 11:41:00.553139
3139 11:41:00.556283 CA PerBit enable=1, Macro0, CA PI delay=33
3140 11:41:00.556381
3141 11:41:00.559258 [CBTSetCACLKResult] CA Dly = 33
3142 11:41:00.559374 CS Dly: 8 (0~40)
3143 11:41:00.559473
3144 11:41:00.562913 ----->DramcWriteLeveling(PI) begin...
3145 11:41:00.565971 ==
3146 11:41:00.569664 Dram Type= 6, Freq= 0, CH_1, rank 0
3147 11:41:00.572868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3148 11:41:00.572940 ==
3149 11:41:00.575988 Write leveling (Byte 0): 26 => 26
3150 11:41:00.579724 Write leveling (Byte 1): 28 => 28
3151 11:41:00.582950 DramcWriteLeveling(PI) end<-----
3152 11:41:00.583056
3153 11:41:00.583125 ==
3154 11:41:00.586392 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 11:41:00.589681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 11:41:00.589766 ==
3157 11:41:00.592984 [Gating] SW mode calibration
3158 11:41:00.599392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3159 11:41:00.602686 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3160 11:41:00.609854 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 11:41:00.613195 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 11:41:00.616292 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 11:41:00.623059 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 11:41:00.626373 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 11:41:00.629595 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3166 11:41:00.636443 0 15 24 | B1->B0 | 3434 2727 | 1 1 | (1 0) (1 1)
3167 11:41:00.639510 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3168 11:41:00.642814 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 11:41:00.649978 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 11:41:00.653190 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 11:41:00.656522 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 11:41:00.662724 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 11:41:00.666425 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3174 11:41:00.669650 1 0 24 | B1->B0 | 2828 3b3b | 0 0 | (0 0) (0 0)
3175 11:41:00.676372 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 11:41:00.679668 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 11:41:00.682780 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 11:41:00.686408 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 11:41:00.693070 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 11:41:00.696481 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 11:41:00.699261 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 11:41:00.705988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3183 11:41:00.709230 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3184 11:41:00.713034 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 11:41:00.719641 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 11:41:00.722762 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 11:41:00.726457 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 11:41:00.732924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 11:41:00.736147 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 11:41:00.739430 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 11:41:00.746259 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 11:41:00.749600 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 11:41:00.752921 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 11:41:00.759529 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 11:41:00.763395 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 11:41:00.766464 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 11:41:00.769627 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 11:41:00.776652 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3199 11:41:00.779607 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3200 11:41:00.782838 Total UI for P1: 0, mck2ui 16
3201 11:41:00.786639 best dqsien dly found for B0: ( 1, 3, 24)
3202 11:41:00.789704 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:41:00.793402 Total UI for P1: 0, mck2ui 16
3204 11:41:00.796792 best dqsien dly found for B1: ( 1, 3, 26)
3205 11:41:00.800074 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3206 11:41:00.803415 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3207 11:41:00.803515
3208 11:41:00.810381 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3209 11:41:00.813753 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3210 11:41:00.813836 [Gating] SW calibration Done
3211 11:41:00.816988 ==
3212 11:41:00.817071 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 11:41:00.823510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 11:41:00.823593 ==
3215 11:41:00.823660 RX Vref Scan: 0
3216 11:41:00.823720
3217 11:41:00.826726 RX Vref 0 -> 0, step: 1
3218 11:41:00.826810
3219 11:41:00.829918 RX Delay -40 -> 252, step: 8
3220 11:41:00.833383 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3221 11:41:00.836529 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3222 11:41:00.839743 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3223 11:41:00.846362 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3224 11:41:00.850056 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3225 11:41:00.853280 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3226 11:41:00.856482 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3227 11:41:00.859817 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3228 11:41:00.866835 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3229 11:41:00.870144 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3230 11:41:00.873497 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3231 11:41:00.876590 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3232 11:41:00.879924 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3233 11:41:00.886798 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3234 11:41:00.889864 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3235 11:41:00.893600 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3236 11:41:00.893704 ==
3237 11:41:00.896629 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 11:41:00.899638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 11:41:00.899721 ==
3240 11:41:00.903559 DQS Delay:
3241 11:41:00.903639 DQS0 = 0, DQS1 = 0
3242 11:41:00.906850 DQM Delay:
3243 11:41:00.906927 DQM0 = 119, DQM1 = 116
3244 11:41:00.907002 DQ Delay:
3245 11:41:00.913074 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3246 11:41:00.916877 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3247 11:41:00.920153 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3248 11:41:00.923339 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3249 11:41:00.923439
3250 11:41:00.923536
3251 11:41:00.923624 ==
3252 11:41:00.926761 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 11:41:00.930059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 11:41:00.930182 ==
3255 11:41:00.930278
3256 11:41:00.930364
3257 11:41:00.933518 TX Vref Scan disable
3258 11:41:00.936737 == TX Byte 0 ==
3259 11:41:00.939869 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3260 11:41:00.943666 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3261 11:41:00.946788 == TX Byte 1 ==
3262 11:41:00.949971 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3263 11:41:00.953306 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3264 11:41:00.953378 ==
3265 11:41:00.956452 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 11:41:00.960364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 11:41:00.963002 ==
3268 11:41:00.973347 TX Vref=22, minBit 9, minWin=24, winSum=405
3269 11:41:00.976594 TX Vref=24, minBit 2, minWin=25, winSum=414
3270 11:41:00.979781 TX Vref=26, minBit 1, minWin=26, winSum=426
3271 11:41:00.983486 TX Vref=28, minBit 1, minWin=26, winSum=427
3272 11:41:00.986700 TX Vref=30, minBit 1, minWin=26, winSum=430
3273 11:41:00.989917 TX Vref=32, minBit 2, minWin=26, winSum=427
3274 11:41:00.996553 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3275 11:41:00.996665
3276 11:41:01.000340 Final TX Range 1 Vref 30
3277 11:41:01.000498
3278 11:41:01.000608 ==
3279 11:41:01.003520 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 11:41:01.006478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 11:41:01.006579 ==
3282 11:41:01.006677
3283 11:41:01.006769
3284 11:41:01.010088 TX Vref Scan disable
3285 11:41:01.013609 == TX Byte 0 ==
3286 11:41:01.016785 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3287 11:41:01.020243 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3288 11:41:01.023532 == TX Byte 1 ==
3289 11:41:01.026748 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3290 11:41:01.030081 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3291 11:41:01.030183
3292 11:41:01.033169 [DATLAT]
3293 11:41:01.033269 Freq=1200, CH1 RK0
3294 11:41:01.033359
3295 11:41:01.036458 DATLAT Default: 0xd
3296 11:41:01.036529 0, 0xFFFF, sum = 0
3297 11:41:01.040298 1, 0xFFFF, sum = 0
3298 11:41:01.040374 2, 0xFFFF, sum = 0
3299 11:41:01.043407 3, 0xFFFF, sum = 0
3300 11:41:01.043482 4, 0xFFFF, sum = 0
3301 11:41:01.046709 5, 0xFFFF, sum = 0
3302 11:41:01.046789 6, 0xFFFF, sum = 0
3303 11:41:01.049690 7, 0xFFFF, sum = 0
3304 11:41:01.049795 8, 0xFFFF, sum = 0
3305 11:41:01.053344 9, 0xFFFF, sum = 0
3306 11:41:01.053477 10, 0xFFFF, sum = 0
3307 11:41:01.056627 11, 0xFFFF, sum = 0
3308 11:41:01.056742 12, 0x0, sum = 1
3309 11:41:01.059714 13, 0x0, sum = 2
3310 11:41:01.059803 14, 0x0, sum = 3
3311 11:41:01.063523 15, 0x0, sum = 4
3312 11:41:01.063612 best_step = 13
3313 11:41:01.063700
3314 11:41:01.063783 ==
3315 11:41:01.066832 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 11:41:01.073223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 11:41:01.073342 ==
3318 11:41:01.073428 RX Vref Scan: 1
3319 11:41:01.073541
3320 11:41:01.076388 Set Vref Range= 32 -> 127
3321 11:41:01.076472
3322 11:41:01.079765 RX Vref 32 -> 127, step: 1
3323 11:41:01.079880
3324 11:41:01.083122 RX Delay -5 -> 252, step: 4
3325 11:41:01.083206
3326 11:41:01.086910 Set Vref, RX VrefLevel [Byte0]: 32
3327 11:41:01.086994 [Byte1]: 32
3328 11:41:01.091303
3329 11:41:01.091386 Set Vref, RX VrefLevel [Byte0]: 33
3330 11:41:01.094504 [Byte1]: 33
3331 11:41:01.098976
3332 11:41:01.099057 Set Vref, RX VrefLevel [Byte0]: 34
3333 11:41:01.102632 [Byte1]: 34
3334 11:41:01.107107
3335 11:41:01.107193 Set Vref, RX VrefLevel [Byte0]: 35
3336 11:41:01.110351 [Byte1]: 35
3337 11:41:01.114789
3338 11:41:01.114873 Set Vref, RX VrefLevel [Byte0]: 36
3339 11:41:01.117932 [Byte1]: 36
3340 11:41:01.122437
3341 11:41:01.122521 Set Vref, RX VrefLevel [Byte0]: 37
3342 11:41:01.125699 [Byte1]: 37
3343 11:41:01.130824
3344 11:41:01.130907 Set Vref, RX VrefLevel [Byte0]: 38
3345 11:41:01.134112 [Byte1]: 38
3346 11:41:01.138233
3347 11:41:01.138317 Set Vref, RX VrefLevel [Byte0]: 39
3348 11:41:01.141338 [Byte1]: 39
3349 11:41:01.146611
3350 11:41:01.146700 Set Vref, RX VrefLevel [Byte0]: 40
3351 11:41:01.149773 [Byte1]: 40
3352 11:41:01.153996
3353 11:41:01.154080 Set Vref, RX VrefLevel [Byte0]: 41
3354 11:41:01.157262 [Byte1]: 41
3355 11:41:01.161659
3356 11:41:01.161743 Set Vref, RX VrefLevel [Byte0]: 42
3357 11:41:01.164812 [Byte1]: 42
3358 11:41:01.169769
3359 11:41:01.169853 Set Vref, RX VrefLevel [Byte0]: 43
3360 11:41:01.173024 [Byte1]: 43
3361 11:41:01.177473
3362 11:41:01.177557 Set Vref, RX VrefLevel [Byte0]: 44
3363 11:41:01.180731 [Byte1]: 44
3364 11:41:01.185491
3365 11:41:01.185569 Set Vref, RX VrefLevel [Byte0]: 45
3366 11:41:01.188667 [Byte1]: 45
3367 11:41:01.193297
3368 11:41:01.193383 Set Vref, RX VrefLevel [Byte0]: 46
3369 11:41:01.196407 [Byte1]: 46
3370 11:41:01.201351
3371 11:41:01.201427 Set Vref, RX VrefLevel [Byte0]: 47
3372 11:41:01.204514 [Byte1]: 47
3373 11:41:01.208897
3374 11:41:01.208969 Set Vref, RX VrefLevel [Byte0]: 48
3375 11:41:01.212028 [Byte1]: 48
3376 11:41:01.217206
3377 11:41:01.217287 Set Vref, RX VrefLevel [Byte0]: 49
3378 11:41:01.220445 [Byte1]: 49
3379 11:41:01.224753
3380 11:41:01.224872 Set Vref, RX VrefLevel [Byte0]: 50
3381 11:41:01.228021 [Byte1]: 50
3382 11:41:01.232602
3383 11:41:01.232677 Set Vref, RX VrefLevel [Byte0]: 51
3384 11:41:01.235678 [Byte1]: 51
3385 11:41:01.240301
3386 11:41:01.240377 Set Vref, RX VrefLevel [Byte0]: 52
3387 11:41:01.243646 [Byte1]: 52
3388 11:41:01.248222
3389 11:41:01.248332 Set Vref, RX VrefLevel [Byte0]: 53
3390 11:41:01.251613 [Byte1]: 53
3391 11:41:01.256090
3392 11:41:01.256166 Set Vref, RX VrefLevel [Byte0]: 54
3393 11:41:01.259219 [Byte1]: 54
3394 11:41:01.264348
3395 11:41:01.264456 Set Vref, RX VrefLevel [Byte0]: 55
3396 11:41:01.267464 [Byte1]: 55
3397 11:41:01.271974
3398 11:41:01.272074 Set Vref, RX VrefLevel [Byte0]: 56
3399 11:41:01.275002 [Byte1]: 56
3400 11:41:01.279632
3401 11:41:01.279735 Set Vref, RX VrefLevel [Byte0]: 57
3402 11:41:01.283425 [Byte1]: 57
3403 11:41:01.287259
3404 11:41:01.287359 Set Vref, RX VrefLevel [Byte0]: 58
3405 11:41:01.291086 [Byte1]: 58
3406 11:41:01.295140
3407 11:41:01.295221 Set Vref, RX VrefLevel [Byte0]: 59
3408 11:41:01.298890 [Byte1]: 59
3409 11:41:01.303205
3410 11:41:01.303297 Set Vref, RX VrefLevel [Byte0]: 60
3411 11:41:01.306229 [Byte1]: 60
3412 11:41:01.311358
3413 11:41:01.311431 Set Vref, RX VrefLevel [Byte0]: 61
3414 11:41:01.314216 [Byte1]: 61
3415 11:41:01.319297
3416 11:41:01.319429 Set Vref, RX VrefLevel [Byte0]: 62
3417 11:41:01.322361 [Byte1]: 62
3418 11:41:01.326856
3419 11:41:01.326973 Set Vref, RX VrefLevel [Byte0]: 63
3420 11:41:01.329872 [Byte1]: 63
3421 11:41:01.334353
3422 11:41:01.334456 Set Vref, RX VrefLevel [Byte0]: 64
3423 11:41:01.338044 [Byte1]: 64
3424 11:41:01.342710
3425 11:41:01.342829 Set Vref, RX VrefLevel [Byte0]: 65
3426 11:41:01.346111 [Byte1]: 65
3427 11:41:01.350762
3428 11:41:01.350885 Set Vref, RX VrefLevel [Byte0]: 66
3429 11:41:01.354002 [Byte1]: 66
3430 11:41:01.357921
3431 11:41:01.358023 Set Vref, RX VrefLevel [Byte0]: 67
3432 11:41:01.361180 [Byte1]: 67
3433 11:41:01.365984
3434 11:41:01.366123 Set Vref, RX VrefLevel [Byte0]: 68
3435 11:41:01.369091 [Byte1]: 68
3436 11:41:01.374238
3437 11:41:01.374313 Final RX Vref Byte 0 = 55 to rank0
3438 11:41:01.377378 Final RX Vref Byte 1 = 52 to rank0
3439 11:41:01.380560 Final RX Vref Byte 0 = 55 to rank1
3440 11:41:01.383815 Final RX Vref Byte 1 = 52 to rank1==
3441 11:41:01.387509 Dram Type= 6, Freq= 0, CH_1, rank 0
3442 11:41:01.390815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 11:41:01.394215 ==
3444 11:41:01.394316 DQS Delay:
3445 11:41:01.394406 DQS0 = 0, DQS1 = 0
3446 11:41:01.397477 DQM Delay:
3447 11:41:01.397581 DQM0 = 120, DQM1 = 117
3448 11:41:01.400765 DQ Delay:
3449 11:41:01.403915 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3450 11:41:01.407522 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3451 11:41:01.410706 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3452 11:41:01.413983 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3453 11:41:01.414061
3454 11:41:01.414126
3455 11:41:01.420868 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3456 11:41:01.423890 CH1 RK0: MR19=404, MR18=114
3457 11:41:01.430889 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3458 11:41:01.430996
3459 11:41:01.434007 ----->DramcWriteLeveling(PI) begin...
3460 11:41:01.434120 ==
3461 11:41:01.437567 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 11:41:01.440738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3463 11:41:01.440834 ==
3464 11:41:01.443958 Write leveling (Byte 0): 26 => 26
3465 11:41:01.447245 Write leveling (Byte 1): 30 => 30
3466 11:41:01.450474 DramcWriteLeveling(PI) end<-----
3467 11:41:01.450558
3468 11:41:01.450624 ==
3469 11:41:01.453725 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 11:41:01.457734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 11:41:01.461022 ==
3472 11:41:01.461106 [Gating] SW mode calibration
3473 11:41:01.467633 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3474 11:41:01.473867 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3475 11:41:01.477590 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 11:41:01.484171 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 11:41:01.487126 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 11:41:01.490864 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 11:41:01.497458 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 11:41:01.500845 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3481 11:41:01.504245 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (1 0) (0 0)
3482 11:41:01.510714 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3483 11:41:01.513880 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 11:41:01.517470 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 11:41:01.524297 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 11:41:01.527624 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 11:41:01.530672 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 11:41:01.533952 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3489 11:41:01.540794 1 0 24 | B1->B0 | 3c3c 2727 | 0 0 | (0 0) (0 0)
3490 11:41:01.543815 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3491 11:41:01.547023 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 11:41:01.554304 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 11:41:01.557391 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 11:41:01.560714 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 11:41:01.567398 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 11:41:01.570715 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 11:41:01.573981 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3498 11:41:01.580792 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3499 11:41:01.583996 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 11:41:01.587109 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 11:41:01.594239 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 11:41:01.597292 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 11:41:01.600394 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 11:41:01.607652 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 11:41:01.610985 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 11:41:01.614194 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 11:41:01.620613 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 11:41:01.624305 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 11:41:01.627477 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 11:41:01.633806 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 11:41:01.636977 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 11:41:01.640732 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3513 11:41:01.643972 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3514 11:41:01.650747 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3515 11:41:01.653852 Total UI for P1: 0, mck2ui 16
3516 11:41:01.657034 best dqsien dly found for B1: ( 1, 3, 22)
3517 11:41:01.660285 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 11:41:01.663530 Total UI for P1: 0, mck2ui 16
3519 11:41:01.666802 best dqsien dly found for B0: ( 1, 3, 28)
3520 11:41:01.670630 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3521 11:41:01.673843 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3522 11:41:01.673959
3523 11:41:01.677078 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3524 11:41:01.680292 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3525 11:41:01.683912 [Gating] SW calibration Done
3526 11:41:01.684021 ==
3527 11:41:01.687089 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 11:41:01.693542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 11:41:01.693654 ==
3530 11:41:01.693763 RX Vref Scan: 0
3531 11:41:01.693865
3532 11:41:01.696756 RX Vref 0 -> 0, step: 1
3533 11:41:01.696884
3534 11:41:01.699956 RX Delay -40 -> 252, step: 8
3535 11:41:01.703573 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3536 11:41:01.707289 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3537 11:41:01.710005 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3538 11:41:01.716653 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3539 11:41:01.720019 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3540 11:41:01.723275 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3541 11:41:01.726986 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3542 11:41:01.730217 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3543 11:41:01.733404 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3544 11:41:01.740258 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3545 11:41:01.743299 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3546 11:41:01.746433 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3547 11:41:01.750077 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3548 11:41:01.756790 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3549 11:41:01.760037 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3550 11:41:01.763624 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3551 11:41:01.763706 ==
3552 11:41:01.767007 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 11:41:01.770261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 11:41:01.770360 ==
3555 11:41:01.772988 DQS Delay:
3556 11:41:01.773071 DQS0 = 0, DQS1 = 0
3557 11:41:01.776847 DQM Delay:
3558 11:41:01.776930 DQM0 = 121, DQM1 = 117
3559 11:41:01.776996 DQ Delay:
3560 11:41:01.780109 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3561 11:41:01.786649 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3562 11:41:01.789833 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3563 11:41:01.793071 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3564 11:41:01.793145
3565 11:41:01.793210
3566 11:41:01.793270 ==
3567 11:41:01.796240 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 11:41:01.799478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 11:41:01.799576 ==
3570 11:41:01.799666
3571 11:41:01.799752
3572 11:41:01.803433 TX Vref Scan disable
3573 11:41:01.806656 == TX Byte 0 ==
3574 11:41:01.809642 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3575 11:41:01.813269 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3576 11:41:01.816434 == TX Byte 1 ==
3577 11:41:01.819653 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3578 11:41:01.822920 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3579 11:41:01.823017 ==
3580 11:41:01.826367 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 11:41:01.832723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 11:41:01.832860 ==
3583 11:41:01.843572 TX Vref=22, minBit 9, minWin=25, winSum=416
3584 11:41:01.846563 TX Vref=24, minBit 9, minWin=25, winSum=423
3585 11:41:01.849702 TX Vref=26, minBit 0, minWin=26, winSum=426
3586 11:41:01.852887 TX Vref=28, minBit 1, minWin=26, winSum=427
3587 11:41:01.856648 TX Vref=30, minBit 1, minWin=26, winSum=433
3588 11:41:01.859742 TX Vref=32, minBit 1, minWin=26, winSum=435
3589 11:41:01.866451 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 32
3590 11:41:01.866546
3591 11:41:01.869999 Final TX Range 1 Vref 32
3592 11:41:01.870077
3593 11:41:01.870141 ==
3594 11:41:01.873405 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 11:41:01.876542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 11:41:01.876649 ==
3597 11:41:01.876749
3598 11:41:01.879915
3599 11:41:01.880021 TX Vref Scan disable
3600 11:41:01.883201 == TX Byte 0 ==
3601 11:41:01.886501 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3602 11:41:01.889803 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3603 11:41:01.892988 == TX Byte 1 ==
3604 11:41:01.896646 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3605 11:41:01.899822 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3606 11:41:01.899995
3607 11:41:01.902961 [DATLAT]
3608 11:41:01.903035 Freq=1200, CH1 RK1
3609 11:41:01.903099
3610 11:41:01.906382 DATLAT Default: 0xd
3611 11:41:01.906454 0, 0xFFFF, sum = 0
3612 11:41:01.909617 1, 0xFFFF, sum = 0
3613 11:41:01.909692 2, 0xFFFF, sum = 0
3614 11:41:01.912812 3, 0xFFFF, sum = 0
3615 11:41:01.912915 4, 0xFFFF, sum = 0
3616 11:41:01.916631 5, 0xFFFF, sum = 0
3617 11:41:01.916738 6, 0xFFFF, sum = 0
3618 11:41:01.919801 7, 0xFFFF, sum = 0
3619 11:41:01.919904 8, 0xFFFF, sum = 0
3620 11:41:01.922967 9, 0xFFFF, sum = 0
3621 11:41:01.926341 10, 0xFFFF, sum = 0
3622 11:41:01.926435 11, 0xFFFF, sum = 0
3623 11:41:01.929733 12, 0x0, sum = 1
3624 11:41:01.929808 13, 0x0, sum = 2
3625 11:41:01.929872 14, 0x0, sum = 3
3626 11:41:01.933078 15, 0x0, sum = 4
3627 11:41:01.933157 best_step = 13
3628 11:41:01.933228
3629 11:41:01.936675 ==
3630 11:41:01.936782 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 11:41:01.943521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 11:41:01.943611 ==
3633 11:41:01.943693 RX Vref Scan: 0
3634 11:41:01.943764
3635 11:41:01.946564 RX Vref 0 -> 0, step: 1
3636 11:41:01.946648
3637 11:41:01.949763 RX Delay -5 -> 252, step: 4
3638 11:41:01.953403 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3639 11:41:01.956503 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3640 11:41:01.963009 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3641 11:41:01.966044 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3642 11:41:01.969701 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3643 11:41:01.973010 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3644 11:41:01.976178 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3645 11:41:01.982725 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3646 11:41:01.986712 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3647 11:41:01.989470 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3648 11:41:01.993446 iDelay=195, Bit 10, Center 118 (55 ~ 182) 128
3649 11:41:01.996673 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3650 11:41:02.002957 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3651 11:41:02.006043 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3652 11:41:02.009880 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3653 11:41:02.013079 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3654 11:41:02.013182 ==
3655 11:41:02.016394 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 11:41:02.023437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 11:41:02.023546 ==
3658 11:41:02.023643 DQS Delay:
3659 11:41:02.023748 DQS0 = 0, DQS1 = 0
3660 11:41:02.026489 DQM Delay:
3661 11:41:02.026603 DQM0 = 119, DQM1 = 118
3662 11:41:02.029734 DQ Delay:
3663 11:41:02.033071 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3664 11:41:02.036257 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3665 11:41:02.039622 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3666 11:41:02.042965 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3667 11:41:02.043081
3668 11:41:02.043179
3669 11:41:02.052572 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3670 11:41:02.052699 CH1 RK1: MR19=403, MR18=10EE
3671 11:41:02.059409 CH1_RK1: MR19=0x403, MR18=0x10EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3672 11:41:02.062639 [RxdqsGatingPostProcess] freq 1200
3673 11:41:02.069576 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3674 11:41:02.072690 best DQS0 dly(2T, 0.5T) = (0, 11)
3675 11:41:02.075833 best DQS1 dly(2T, 0.5T) = (0, 11)
3676 11:41:02.078955 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3677 11:41:02.082579 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3678 11:41:02.085847 best DQS0 dly(2T, 0.5T) = (0, 11)
3679 11:41:02.089175 best DQS1 dly(2T, 0.5T) = (0, 11)
3680 11:41:02.092417 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3681 11:41:02.092518 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3682 11:41:02.095733 Pre-setting of DQS Precalculation
3683 11:41:02.102374 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3684 11:41:02.108754 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3685 11:41:02.115699 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3686 11:41:02.115783
3687 11:41:02.115849
3688 11:41:02.119041 [Calibration Summary] 2400 Mbps
3689 11:41:02.122408 CH 0, Rank 0
3690 11:41:02.122525 SW Impedance : PASS
3691 11:41:02.125489 DUTY Scan : NO K
3692 11:41:02.128903 ZQ Calibration : PASS
3693 11:41:02.128986 Jitter Meter : NO K
3694 11:41:02.132394 CBT Training : PASS
3695 11:41:02.132489 Write leveling : PASS
3696 11:41:02.135501 RX DQS gating : PASS
3697 11:41:02.138758 RX DQ/DQS(RDDQC) : PASS
3698 11:41:02.138839 TX DQ/DQS : PASS
3699 11:41:02.142079 RX DATLAT : PASS
3700 11:41:02.145548 RX DQ/DQS(Engine): PASS
3701 11:41:02.145631 TX OE : NO K
3702 11:41:02.148731 All Pass.
3703 11:41:02.148822
3704 11:41:02.148934 CH 0, Rank 1
3705 11:41:02.151907 SW Impedance : PASS
3706 11:41:02.151991 DUTY Scan : NO K
3707 11:41:02.155063 ZQ Calibration : PASS
3708 11:41:02.158795 Jitter Meter : NO K
3709 11:41:02.158893 CBT Training : PASS
3710 11:41:02.161870 Write leveling : PASS
3711 11:41:02.165167 RX DQS gating : PASS
3712 11:41:02.165300 RX DQ/DQS(RDDQC) : PASS
3713 11:41:02.168919 TX DQ/DQS : PASS
3714 11:41:02.171985 RX DATLAT : PASS
3715 11:41:02.172072 RX DQ/DQS(Engine): PASS
3716 11:41:02.175167 TX OE : NO K
3717 11:41:02.175256 All Pass.
3718 11:41:02.175344
3719 11:41:02.178356 CH 1, Rank 0
3720 11:41:02.178444 SW Impedance : PASS
3721 11:41:02.182154 DUTY Scan : NO K
3722 11:41:02.185257 ZQ Calibration : PASS
3723 11:41:02.185344 Jitter Meter : NO K
3724 11:41:02.188435 CBT Training : PASS
3725 11:41:02.188521 Write leveling : PASS
3726 11:41:02.192350 RX DQS gating : PASS
3727 11:41:02.195000 RX DQ/DQS(RDDQC) : PASS
3728 11:41:02.195086 TX DQ/DQS : PASS
3729 11:41:02.198366 RX DATLAT : PASS
3730 11:41:02.202351 RX DQ/DQS(Engine): PASS
3731 11:41:02.202439 TX OE : NO K
3732 11:41:02.205657 All Pass.
3733 11:41:02.205746
3734 11:41:02.205833 CH 1, Rank 1
3735 11:41:02.208342 SW Impedance : PASS
3736 11:41:02.208430 DUTY Scan : NO K
3737 11:41:02.212164 ZQ Calibration : PASS
3738 11:41:02.215447 Jitter Meter : NO K
3739 11:41:02.215536 CBT Training : PASS
3740 11:41:02.218726 Write leveling : PASS
3741 11:41:02.221614 RX DQS gating : PASS
3742 11:41:02.221726 RX DQ/DQS(RDDQC) : PASS
3743 11:41:02.224897 TX DQ/DQS : PASS
3744 11:41:02.228766 RX DATLAT : PASS
3745 11:41:02.228860 RX DQ/DQS(Engine): PASS
3746 11:41:02.232027 TX OE : NO K
3747 11:41:02.232111 All Pass.
3748 11:41:02.232178
3749 11:41:02.235350 DramC Write-DBI off
3750 11:41:02.238697 PER_BANK_REFRESH: Hybrid Mode
3751 11:41:02.238783 TX_TRACKING: ON
3752 11:41:02.248518 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3753 11:41:02.251735 [FAST_K] Save calibration result to emmc
3754 11:41:02.255069 dramc_set_vcore_voltage set vcore to 650000
3755 11:41:02.258204 Read voltage for 600, 5
3756 11:41:02.258291 Vio18 = 0
3757 11:41:02.258368 Vcore = 650000
3758 11:41:02.261870 Vdram = 0
3759 11:41:02.261955 Vddq = 0
3760 11:41:02.262024 Vmddr = 0
3761 11:41:02.268331 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3762 11:41:02.271520 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3763 11:41:02.275453 MEM_TYPE=3, freq_sel=19
3764 11:41:02.278486 sv_algorithm_assistance_LP4_1600
3765 11:41:02.281623 ============ PULL DRAM RESETB DOWN ============
3766 11:41:02.285422 ========== PULL DRAM RESETB DOWN end =========
3767 11:41:02.291815 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3768 11:41:02.294970 ===================================
3769 11:41:02.295050 LPDDR4 DRAM CONFIGURATION
3770 11:41:02.298380 ===================================
3771 11:41:02.301628 EX_ROW_EN[0] = 0x0
3772 11:41:02.305120 EX_ROW_EN[1] = 0x0
3773 11:41:02.305195 LP4Y_EN = 0x0
3774 11:41:02.308409 WORK_FSP = 0x0
3775 11:41:02.308485 WL = 0x2
3776 11:41:02.311639 RL = 0x2
3777 11:41:02.311716 BL = 0x2
3778 11:41:02.314816 RPST = 0x0
3779 11:41:02.314893 RD_PRE = 0x0
3780 11:41:02.318439 WR_PRE = 0x1
3781 11:41:02.318537 WR_PST = 0x0
3782 11:41:02.321632 DBI_WR = 0x0
3783 11:41:02.321710 DBI_RD = 0x0
3784 11:41:02.324829 OTF = 0x1
3785 11:41:02.328487 ===================================
3786 11:41:02.331814 ===================================
3787 11:41:02.331894 ANA top config
3788 11:41:02.335119 ===================================
3789 11:41:02.338173 DLL_ASYNC_EN = 0
3790 11:41:02.341480 ALL_SLAVE_EN = 1
3791 11:41:02.341561 NEW_RANK_MODE = 1
3792 11:41:02.345251 DLL_IDLE_MODE = 1
3793 11:41:02.348543 LP45_APHY_COMB_EN = 1
3794 11:41:02.351719 TX_ODT_DIS = 1
3795 11:41:02.354995 NEW_8X_MODE = 1
3796 11:41:02.358441 ===================================
3797 11:41:02.361761 ===================================
3798 11:41:02.361838 data_rate = 1200
3799 11:41:02.365040 CKR = 1
3800 11:41:02.368190 DQ_P2S_RATIO = 8
3801 11:41:02.371087 ===================================
3802 11:41:02.374817 CA_P2S_RATIO = 8
3803 11:41:02.377971 DQ_CA_OPEN = 0
3804 11:41:02.381590 DQ_SEMI_OPEN = 0
3805 11:41:02.381698 CA_SEMI_OPEN = 0
3806 11:41:02.384502 CA_FULL_RATE = 0
3807 11:41:02.388279 DQ_CKDIV4_EN = 1
3808 11:41:02.391255 CA_CKDIV4_EN = 1
3809 11:41:02.394325 CA_PREDIV_EN = 0
3810 11:41:02.398176 PH8_DLY = 0
3811 11:41:02.398262 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3812 11:41:02.401268 DQ_AAMCK_DIV = 4
3813 11:41:02.404485 CA_AAMCK_DIV = 4
3814 11:41:02.407785 CA_ADMCK_DIV = 4
3815 11:41:02.411024 DQ_TRACK_CA_EN = 0
3816 11:41:02.414418 CA_PICK = 600
3817 11:41:02.414503 CA_MCKIO = 600
3818 11:41:02.417674 MCKIO_SEMI = 0
3819 11:41:02.420992 PLL_FREQ = 2288
3820 11:41:02.424689 DQ_UI_PI_RATIO = 32
3821 11:41:02.427780 CA_UI_PI_RATIO = 0
3822 11:41:02.431665 ===================================
3823 11:41:02.434900 ===================================
3824 11:41:02.438058 memory_type:LPDDR4
3825 11:41:02.438141 GP_NUM : 10
3826 11:41:02.441275 SRAM_EN : 1
3827 11:41:02.441359 MD32_EN : 0
3828 11:41:02.444574 ===================================
3829 11:41:02.447708 [ANA_INIT] >>>>>>>>>>>>>>
3830 11:41:02.450926 <<<<<< [CONFIGURE PHASE]: ANA_TX
3831 11:41:02.454635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3832 11:41:02.457779 ===================================
3833 11:41:02.461139 data_rate = 1200,PCW = 0X5800
3834 11:41:02.464435 ===================================
3835 11:41:02.467645 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3836 11:41:02.470986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 11:41:02.478018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3838 11:41:02.481007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3839 11:41:02.488485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3840 11:41:02.491278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3841 11:41:02.491357 [ANA_INIT] flow start
3842 11:41:02.494585 [ANA_INIT] PLL >>>>>>>>
3843 11:41:02.498273 [ANA_INIT] PLL <<<<<<<<
3844 11:41:02.498353 [ANA_INIT] MIDPI >>>>>>>>
3845 11:41:02.501428 [ANA_INIT] MIDPI <<<<<<<<
3846 11:41:02.504557 [ANA_INIT] DLL >>>>>>>>
3847 11:41:02.504636 [ANA_INIT] flow end
3848 11:41:02.507652 ============ LP4 DIFF to SE enter ============
3849 11:41:02.514665 ============ LP4 DIFF to SE exit ============
3850 11:41:02.514743 [ANA_INIT] <<<<<<<<<<<<<
3851 11:41:02.518025 [Flow] Enable top DCM control >>>>>
3852 11:41:02.521305 [Flow] Enable top DCM control <<<<<
3853 11:41:02.524702 Enable DLL master slave shuffle
3854 11:41:02.531092 ==============================================================
3855 11:41:02.531170 Gating Mode config
3856 11:41:02.538282 ==============================================================
3857 11:41:02.541529 Config description:
3858 11:41:02.551086 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3859 11:41:02.557622 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3860 11:41:02.561434 SELPH_MODE 0: By rank 1: By Phase
3861 11:41:02.567824 ==============================================================
3862 11:41:02.571202 GAT_TRACK_EN = 1
3863 11:41:02.571302 RX_GATING_MODE = 2
3864 11:41:02.574366 RX_GATING_TRACK_MODE = 2
3865 11:41:02.577699 SELPH_MODE = 1
3866 11:41:02.581460 PICG_EARLY_EN = 1
3867 11:41:02.584650 VALID_LAT_VALUE = 1
3868 11:41:02.591462 ==============================================================
3869 11:41:02.594263 Enter into Gating configuration >>>>
3870 11:41:02.597878 Exit from Gating configuration <<<<
3871 11:41:02.600995 Enter into DVFS_PRE_config >>>>>
3872 11:41:02.610876 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3873 11:41:02.614386 Exit from DVFS_PRE_config <<<<<
3874 11:41:02.617957 Enter into PICG configuration >>>>
3875 11:41:02.620699 Exit from PICG configuration <<<<
3876 11:41:02.624545 [RX_INPUT] configuration >>>>>
3877 11:41:02.627953 [RX_INPUT] configuration <<<<<
3878 11:41:02.631112 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3879 11:41:02.637628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3880 11:41:02.644503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3881 11:41:02.647532 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3882 11:41:02.654366 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3883 11:41:02.660927 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3884 11:41:02.664212 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3885 11:41:02.667534 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3886 11:41:02.673959 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3887 11:41:02.678058 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3888 11:41:02.680635 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3889 11:41:02.687828 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 11:41:02.691166 ===================================
3891 11:41:02.691276 LPDDR4 DRAM CONFIGURATION
3892 11:41:02.694613 ===================================
3893 11:41:02.697605 EX_ROW_EN[0] = 0x0
3894 11:41:02.697715 EX_ROW_EN[1] = 0x0
3895 11:41:02.700730 LP4Y_EN = 0x0
3896 11:41:02.704478 WORK_FSP = 0x0
3897 11:41:02.704582 WL = 0x2
3898 11:41:02.708115 RL = 0x2
3899 11:41:02.708217 BL = 0x2
3900 11:41:02.711378 RPST = 0x0
3901 11:41:02.711476 RD_PRE = 0x0
3902 11:41:02.714409 WR_PRE = 0x1
3903 11:41:02.714480 WR_PST = 0x0
3904 11:41:02.717902 DBI_WR = 0x0
3905 11:41:02.717974 DBI_RD = 0x0
3906 11:41:02.720779 OTF = 0x1
3907 11:41:02.724555 ===================================
3908 11:41:02.727767 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3909 11:41:02.731114 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3910 11:41:02.734467 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3911 11:41:02.737722 ===================================
3912 11:41:02.740919 LPDDR4 DRAM CONFIGURATION
3913 11:41:02.744291 ===================================
3914 11:41:02.748060 EX_ROW_EN[0] = 0x10
3915 11:41:02.748142 EX_ROW_EN[1] = 0x0
3916 11:41:02.751038 LP4Y_EN = 0x0
3917 11:41:02.751122 WORK_FSP = 0x0
3918 11:41:02.754416 WL = 0x2
3919 11:41:02.754506 RL = 0x2
3920 11:41:02.757674 BL = 0x2
3921 11:41:02.757772 RPST = 0x0
3922 11:41:02.760663 RD_PRE = 0x0
3923 11:41:02.760765 WR_PRE = 0x1
3924 11:41:02.764411 WR_PST = 0x0
3925 11:41:02.767495 DBI_WR = 0x0
3926 11:41:02.767595 DBI_RD = 0x0
3927 11:41:02.770858 OTF = 0x1
3928 11:41:02.774595 ===================================
3929 11:41:02.777240 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3930 11:41:02.783134 nWR fixed to 30
3931 11:41:02.786256 [ModeRegInit_LP4] CH0 RK0
3932 11:41:02.786331 [ModeRegInit_LP4] CH0 RK1
3933 11:41:02.789438 [ModeRegInit_LP4] CH1 RK0
3934 11:41:02.792625 [ModeRegInit_LP4] CH1 RK1
3935 11:41:02.792728 match AC timing 17
3936 11:41:02.799170 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3937 11:41:02.802561 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3938 11:41:02.806464 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3939 11:41:02.812799 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3940 11:41:02.815987 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3941 11:41:02.816071 ==
3942 11:41:02.819595 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 11:41:02.822717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 11:41:02.822801 ==
3945 11:41:02.829619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 11:41:02.835857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3947 11:41:02.838965 [CA 0] Center 36 (5~67) winsize 63
3948 11:41:02.842327 [CA 1] Center 36 (5~67) winsize 63
3949 11:41:02.845581 [CA 2] Center 34 (3~65) winsize 63
3950 11:41:02.848921 [CA 3] Center 33 (3~64) winsize 62
3951 11:41:02.852274 [CA 4] Center 33 (2~64) winsize 63
3952 11:41:02.856152 [CA 5] Center 32 (2~63) winsize 62
3953 11:41:02.856235
3954 11:41:02.859085 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3955 11:41:02.859171
3956 11:41:02.862409 [CATrainingPosCal] consider 1 rank data
3957 11:41:02.865844 u2DelayCellTimex100 = 270/100 ps
3958 11:41:02.868913 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3959 11:41:02.872666 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3960 11:41:02.875822 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3961 11:41:02.879072 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3962 11:41:02.882199 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3963 11:41:02.889340 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3964 11:41:02.889419
3965 11:41:02.892487 CA PerBit enable=1, Macro0, CA PI delay=32
3966 11:41:02.892566
3967 11:41:02.895572 [CBTSetCACLKResult] CA Dly = 32
3968 11:41:02.895658 CS Dly: 4 (0~35)
3969 11:41:02.895757 ==
3970 11:41:02.898966 Dram Type= 6, Freq= 0, CH_0, rank 1
3971 11:41:02.902250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 11:41:02.905486 ==
3973 11:41:02.909416 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3974 11:41:02.915906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3975 11:41:02.919025 [CA 0] Center 35 (5~66) winsize 62
3976 11:41:02.922140 [CA 1] Center 35 (5~66) winsize 62
3977 11:41:02.925359 [CA 2] Center 34 (3~65) winsize 63
3978 11:41:02.929000 [CA 3] Center 33 (3~64) winsize 62
3979 11:41:02.932314 [CA 4] Center 33 (2~64) winsize 63
3980 11:41:02.935480 [CA 5] Center 32 (2~63) winsize 62
3981 11:41:02.935583
3982 11:41:02.939224 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3983 11:41:02.939309
3984 11:41:02.942437 [CATrainingPosCal] consider 2 rank data
3985 11:41:02.945191 u2DelayCellTimex100 = 270/100 ps
3986 11:41:02.949080 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3987 11:41:02.952297 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3988 11:41:02.955544 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3989 11:41:02.958942 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3990 11:41:02.965284 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3991 11:41:02.969285 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3992 11:41:02.969363
3993 11:41:02.972372 CA PerBit enable=1, Macro0, CA PI delay=32
3994 11:41:02.972480
3995 11:41:02.975390 [CBTSetCACLKResult] CA Dly = 32
3996 11:41:02.975466 CS Dly: 4 (0~36)
3997 11:41:02.975529
3998 11:41:02.979046 ----->DramcWriteLeveling(PI) begin...
3999 11:41:02.979125 ==
4000 11:41:02.982028 Dram Type= 6, Freq= 0, CH_0, rank 0
4001 11:41:02.988847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 11:41:02.988933 ==
4003 11:41:02.992021 Write leveling (Byte 0): 34 => 34
4004 11:41:02.992104 Write leveling (Byte 1): 29 => 29
4005 11:41:02.995282 DramcWriteLeveling(PI) end<-----
4006 11:41:02.995365
4007 11:41:02.998411 ==
4008 11:41:03.001630 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 11:41:03.005551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 11:41:03.005635 ==
4011 11:41:03.008690 [Gating] SW mode calibration
4012 11:41:03.015243 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4013 11:41:03.018496 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4014 11:41:03.025112 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 11:41:03.028448 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 11:41:03.031656 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 11:41:03.038658 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
4018 11:41:03.041778 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
4019 11:41:03.045501 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 11:41:03.051555 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 11:41:03.055400 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 11:41:03.058728 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 11:41:03.065388 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 11:41:03.068619 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 11:41:03.071956 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
4026 11:41:03.078444 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4027 11:41:03.081565 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 11:41:03.085286 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 11:41:03.088402 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 11:41:03.095060 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 11:41:03.098463 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 11:41:03.102285 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 11:41:03.108512 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4034 11:41:03.111720 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 11:41:03.115003 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 11:41:03.121589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 11:41:03.124808 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 11:41:03.128640 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 11:41:03.135186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 11:41:03.138196 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 11:41:03.141767 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 11:41:03.148165 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 11:41:03.151801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 11:41:03.155098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 11:41:03.161647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 11:41:03.164833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 11:41:03.168093 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 11:41:03.174632 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 11:41:03.177932 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4050 11:41:03.181411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4051 11:41:03.188318 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 11:41:03.188407 Total UI for P1: 0, mck2ui 16
4053 11:41:03.195078 best dqsien dly found for B0: ( 0, 13, 14)
4054 11:41:03.195162 Total UI for P1: 0, mck2ui 16
4055 11:41:03.198236 best dqsien dly found for B1: ( 0, 13, 18)
4056 11:41:03.204515 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4057 11:41:03.207954 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4058 11:41:03.208038
4059 11:41:03.211667 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4060 11:41:03.214854 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4061 11:41:03.217953 [Gating] SW calibration Done
4062 11:41:03.218054 ==
4063 11:41:03.221392 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 11:41:03.224617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 11:41:03.224701 ==
4066 11:41:03.227960 RX Vref Scan: 0
4067 11:41:03.228043
4068 11:41:03.228108 RX Vref 0 -> 0, step: 1
4069 11:41:03.228168
4070 11:41:03.231273 RX Delay -230 -> 252, step: 16
4071 11:41:03.234515 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4072 11:41:03.241451 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4073 11:41:03.244549 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4074 11:41:03.247800 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4075 11:41:03.251604 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4076 11:41:03.257741 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4077 11:41:03.261048 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4078 11:41:03.264975 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4079 11:41:03.268246 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4080 11:41:03.271628 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4081 11:41:03.277888 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4082 11:41:03.281144 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4083 11:41:03.284576 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4084 11:41:03.287724 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4085 11:41:03.294940 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4086 11:41:03.297935 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4087 11:41:03.298018 ==
4088 11:41:03.301178 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 11:41:03.304449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 11:41:03.304533 ==
4091 11:41:03.308259 DQS Delay:
4092 11:41:03.308343 DQS0 = 0, DQS1 = 0
4093 11:41:03.308409 DQM Delay:
4094 11:41:03.311494 DQM0 = 49, DQM1 = 44
4095 11:41:03.311576 DQ Delay:
4096 11:41:03.314530 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4097 11:41:03.318000 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4098 11:41:03.321773 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4099 11:41:03.325032 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4100 11:41:03.325116
4101 11:41:03.325181
4102 11:41:03.325241 ==
4103 11:41:03.328269 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 11:41:03.331499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 11:41:03.334701 ==
4106 11:41:03.334783
4107 11:41:03.334849
4108 11:41:03.334910 TX Vref Scan disable
4109 11:41:03.338537 == TX Byte 0 ==
4110 11:41:03.341724 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4111 11:41:03.344731 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4112 11:41:03.348567 == TX Byte 1 ==
4113 11:41:03.351574 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4114 11:41:03.354838 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4115 11:41:03.357969 ==
4116 11:41:03.361080 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 11:41:03.364962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 11:41:03.365046 ==
4119 11:41:03.365112
4120 11:41:03.365173
4121 11:41:03.368234 TX Vref Scan disable
4122 11:41:03.368317 == TX Byte 0 ==
4123 11:41:03.374750 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4124 11:41:03.378139 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4125 11:41:03.381252 == TX Byte 1 ==
4126 11:41:03.384458 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4127 11:41:03.387862 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4128 11:41:03.387970
4129 11:41:03.388069 [DATLAT]
4130 11:41:03.391102 Freq=600, CH0 RK0
4131 11:41:03.391186
4132 11:41:03.391252 DATLAT Default: 0x9
4133 11:41:03.394482 0, 0xFFFF, sum = 0
4134 11:41:03.397734 1, 0xFFFF, sum = 0
4135 11:41:03.397819 2, 0xFFFF, sum = 0
4136 11:41:03.400823 3, 0xFFFF, sum = 0
4137 11:41:03.400922 4, 0xFFFF, sum = 0
4138 11:41:03.404069 5, 0xFFFF, sum = 0
4139 11:41:03.404154 6, 0xFFFF, sum = 0
4140 11:41:03.408061 7, 0xFFFF, sum = 0
4141 11:41:03.408145 8, 0x0, sum = 1
4142 11:41:03.410917 9, 0x0, sum = 2
4143 11:41:03.411002 10, 0x0, sum = 3
4144 11:41:03.411069 11, 0x0, sum = 4
4145 11:41:03.414006 best_step = 9
4146 11:41:03.414088
4147 11:41:03.414154 ==
4148 11:41:03.417396 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 11:41:03.420561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 11:41:03.420676 ==
4151 11:41:03.424237 RX Vref Scan: 1
4152 11:41:03.424320
4153 11:41:03.424386 RX Vref 0 -> 0, step: 1
4154 11:41:03.427131
4155 11:41:03.427213 RX Delay -179 -> 252, step: 8
4156 11:41:03.427280
4157 11:41:03.430701 Set Vref, RX VrefLevel [Byte0]: 56
4158 11:41:03.434157 [Byte1]: 54
4159 11:41:03.438602
4160 11:41:03.438710 Final RX Vref Byte 0 = 56 to rank0
4161 11:41:03.442048 Final RX Vref Byte 1 = 54 to rank0
4162 11:41:03.445274 Final RX Vref Byte 0 = 56 to rank1
4163 11:41:03.448318 Final RX Vref Byte 1 = 54 to rank1==
4164 11:41:03.451432 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 11:41:03.458305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 11:41:03.458390 ==
4167 11:41:03.458500 DQS Delay:
4168 11:41:03.458575 DQS0 = 0, DQS1 = 0
4169 11:41:03.461511 DQM Delay:
4170 11:41:03.461594 DQM0 = 53, DQM1 = 47
4171 11:41:03.465265 DQ Delay:
4172 11:41:03.468324 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4173 11:41:03.471893 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4174 11:41:03.475279 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4175 11:41:03.478521 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4176 11:41:03.478603
4177 11:41:03.478687
4178 11:41:03.484907 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4179 11:41:03.488086 CH0 RK0: MR19=808, MR18=6A5D
4180 11:41:03.494651 CH0_RK0: MR19=0x808, MR18=0x6A5D, DQSOSC=389, MR23=63, INC=173, DEC=115
4181 11:41:03.494762
4182 11:41:03.497987 ----->DramcWriteLeveling(PI) begin...
4183 11:41:03.498091 ==
4184 11:41:03.501334 Dram Type= 6, Freq= 0, CH_0, rank 1
4185 11:41:03.504649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 11:41:03.504778 ==
4187 11:41:03.508326 Write leveling (Byte 0): 36 => 36
4188 11:41:03.511529 Write leveling (Byte 1): 30 => 30
4189 11:41:03.515032 DramcWriteLeveling(PI) end<-----
4190 11:41:03.515116
4191 11:41:03.515181 ==
4192 11:41:03.517868 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 11:41:03.521682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 11:41:03.521781 ==
4195 11:41:03.524979 [Gating] SW mode calibration
4196 11:41:03.531521 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4197 11:41:03.538161 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4198 11:41:03.541466 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 11:41:03.544915 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 11:41:03.551166 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 11:41:03.554835 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4202 11:41:03.558090 0 9 16 | B1->B0 | 2b2b 2525 | 0 1 | (0 0) (1 0)
4203 11:41:03.564965 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 11:41:03.568059 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 11:41:03.571685 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 11:41:03.577975 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 11:41:03.581205 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 11:41:03.584456 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 11:41:03.591354 0 10 12 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)
4210 11:41:03.594588 0 10 16 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
4211 11:41:03.597927 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 11:41:03.604680 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 11:41:03.608042 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 11:41:03.611355 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 11:41:03.618193 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 11:41:03.621358 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 11:41:03.624451 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4218 11:41:03.631418 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4219 11:41:03.634801 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 11:41:03.638301 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 11:41:03.644489 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 11:41:03.647595 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 11:41:03.651467 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 11:41:03.657852 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 11:41:03.660921 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 11:41:03.664171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 11:41:03.670812 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 11:41:03.674548 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 11:41:03.677836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 11:41:03.680809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 11:41:03.687728 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 11:41:03.690899 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 11:41:03.694081 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4234 11:41:03.700711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 11:41:03.703969 Total UI for P1: 0, mck2ui 16
4236 11:41:03.707368 best dqsien dly found for B0: ( 0, 13, 12)
4237 11:41:03.710779 Total UI for P1: 0, mck2ui 16
4238 11:41:03.714042 best dqsien dly found for B1: ( 0, 13, 14)
4239 11:41:03.717227 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4240 11:41:03.721012 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4241 11:41:03.721096
4242 11:41:03.724021 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4243 11:41:03.727251 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4244 11:41:03.730990 [Gating] SW calibration Done
4245 11:41:03.731117 ==
4246 11:41:03.734036 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 11:41:03.737202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 11:41:03.737319 ==
4249 11:41:03.740606 RX Vref Scan: 0
4250 11:41:03.740679
4251 11:41:03.743852 RX Vref 0 -> 0, step: 1
4252 11:41:03.743929
4253 11:41:03.743993 RX Delay -230 -> 252, step: 16
4254 11:41:03.750702 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4255 11:41:03.754015 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4256 11:41:03.757713 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4257 11:41:03.760635 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4258 11:41:03.766993 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4259 11:41:03.770708 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4260 11:41:03.773889 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4261 11:41:03.777006 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4262 11:41:03.780264 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4263 11:41:03.787074 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4264 11:41:03.790427 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4265 11:41:03.793885 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4266 11:41:03.797327 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4267 11:41:03.803848 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4268 11:41:03.807084 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4269 11:41:03.810436 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4270 11:41:03.810519 ==
4271 11:41:03.813644 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 11:41:03.816904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 11:41:03.820392 ==
4274 11:41:03.820473 DQS Delay:
4275 11:41:03.820546 DQS0 = 0, DQS1 = 0
4276 11:41:03.823543 DQM Delay:
4277 11:41:03.823620 DQM0 = 52, DQM1 = 43
4278 11:41:03.823701 DQ Delay:
4279 11:41:03.826833 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4280 11:41:03.830536 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4281 11:41:03.833658 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4282 11:41:03.836785 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4283 11:41:03.836880
4284 11:41:03.840496
4285 11:41:03.840600 ==
4286 11:41:03.843601 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 11:41:03.846959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 11:41:03.847036 ==
4289 11:41:03.847110
4290 11:41:03.847170
4291 11:41:03.850086 TX Vref Scan disable
4292 11:41:03.850163 == TX Byte 0 ==
4293 11:41:03.857249 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4294 11:41:03.860415 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4295 11:41:03.860491 == TX Byte 1 ==
4296 11:41:03.867087 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4297 11:41:03.870340 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4298 11:41:03.870414 ==
4299 11:41:03.873452 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 11:41:03.877108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 11:41:03.877214 ==
4302 11:41:03.877285
4303 11:41:03.877349
4304 11:41:03.880361 TX Vref Scan disable
4305 11:41:03.883512 == TX Byte 0 ==
4306 11:41:03.886644 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4307 11:41:03.889947 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4308 11:41:03.893625 == TX Byte 1 ==
4309 11:41:03.896739 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4310 11:41:03.899868 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4311 11:41:03.903612
4312 11:41:03.903698 [DATLAT]
4313 11:41:03.903765 Freq=600, CH0 RK1
4314 11:41:03.903829
4315 11:41:03.906972 DATLAT Default: 0x9
4316 11:41:03.907086 0, 0xFFFF, sum = 0
4317 11:41:03.910287 1, 0xFFFF, sum = 0
4318 11:41:03.910399 2, 0xFFFF, sum = 0
4319 11:41:03.913698 3, 0xFFFF, sum = 0
4320 11:41:03.913805 4, 0xFFFF, sum = 0
4321 11:41:03.917020 5, 0xFFFF, sum = 0
4322 11:41:03.917099 6, 0xFFFF, sum = 0
4323 11:41:03.920244 7, 0xFFFF, sum = 0
4324 11:41:03.920347 8, 0x0, sum = 1
4325 11:41:03.923620 9, 0x0, sum = 2
4326 11:41:03.923727 10, 0x0, sum = 3
4327 11:41:03.926893 11, 0x0, sum = 4
4328 11:41:03.927000 best_step = 9
4329 11:41:03.927093
4330 11:41:03.927184 ==
4331 11:41:03.929999 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 11:41:03.936338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 11:41:03.936452 ==
4334 11:41:03.936548 RX Vref Scan: 0
4335 11:41:03.936639
4336 11:41:03.940091 RX Vref 0 -> 0, step: 1
4337 11:41:03.940164
4338 11:41:03.943152 RX Delay -163 -> 252, step: 8
4339 11:41:03.946296 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4340 11:41:03.950073 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4341 11:41:03.956706 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4342 11:41:03.960051 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4343 11:41:03.963258 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4344 11:41:03.966413 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4345 11:41:03.969644 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4346 11:41:03.976757 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4347 11:41:03.979752 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4348 11:41:03.983077 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4349 11:41:03.986159 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4350 11:41:03.989808 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4351 11:41:03.996173 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4352 11:41:03.999865 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4353 11:41:04.002913 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4354 11:41:04.006685 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4355 11:41:04.006791 ==
4356 11:41:04.009802 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 11:41:04.016433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 11:41:04.016546 ==
4359 11:41:04.016641 DQS Delay:
4360 11:41:04.019656 DQS0 = 0, DQS1 = 0
4361 11:41:04.019768 DQM Delay:
4362 11:41:04.023103 DQM0 = 53, DQM1 = 46
4363 11:41:04.023215 DQ Delay:
4364 11:41:04.026311 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4365 11:41:04.029670 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =64
4366 11:41:04.033056 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4367 11:41:04.036225 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4368 11:41:04.036334
4369 11:41:04.036428
4370 11:41:04.043256 [DQSOSCAuto] RK1, (LSB)MR18= 0x6728, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4371 11:41:04.046561 CH0 RK1: MR19=808, MR18=6728
4372 11:41:04.053280 CH0_RK1: MR19=0x808, MR18=0x6728, DQSOSC=390, MR23=63, INC=172, DEC=114
4373 11:41:04.056409 [RxdqsGatingPostProcess] freq 600
4374 11:41:04.059644 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4375 11:41:04.063114 Pre-setting of DQS Precalculation
4376 11:41:04.069416 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4377 11:41:04.069525 ==
4378 11:41:04.073264 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 11:41:04.076564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 11:41:04.076683 ==
4381 11:41:04.083039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 11:41:04.089817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4383 11:41:04.093229 [CA 0] Center 35 (5~66) winsize 62
4384 11:41:04.096237 [CA 1] Center 35 (5~66) winsize 62
4385 11:41:04.099354 [CA 2] Center 34 (4~65) winsize 62
4386 11:41:04.103233 [CA 3] Center 34 (4~65) winsize 62
4387 11:41:04.106510 [CA 4] Center 34 (4~65) winsize 62
4388 11:41:04.109585 [CA 5] Center 33 (3~64) winsize 62
4389 11:41:04.109701
4390 11:41:04.112709 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4391 11:41:04.112829
4392 11:41:04.115843 [CATrainingPosCal] consider 1 rank data
4393 11:41:04.119161 u2DelayCellTimex100 = 270/100 ps
4394 11:41:04.122410 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 11:41:04.126307 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4396 11:41:04.129043 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4397 11:41:04.132895 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 11:41:04.136161 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 11:41:04.139534 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4400 11:41:04.139643
4401 11:41:04.142777 CA PerBit enable=1, Macro0, CA PI delay=33
4402 11:41:04.145960
4403 11:41:04.146079 [CBTSetCACLKResult] CA Dly = 33
4404 11:41:04.149010 CS Dly: 6 (0~37)
4405 11:41:04.149130 ==
4406 11:41:04.152772 Dram Type= 6, Freq= 0, CH_1, rank 1
4407 11:41:04.155995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 11:41:04.156112 ==
4409 11:41:04.162897 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4410 11:41:04.169385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4411 11:41:04.172523 [CA 0] Center 36 (5~67) winsize 63
4412 11:41:04.175685 [CA 1] Center 36 (5~67) winsize 63
4413 11:41:04.178909 [CA 2] Center 34 (4~65) winsize 62
4414 11:41:04.182234 [CA 3] Center 34 (4~65) winsize 62
4415 11:41:04.186076 [CA 4] Center 35 (4~66) winsize 63
4416 11:41:04.189354 [CA 5] Center 34 (4~65) winsize 62
4417 11:41:04.189477
4418 11:41:04.192268 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4419 11:41:04.192375
4420 11:41:04.195923 [CATrainingPosCal] consider 2 rank data
4421 11:41:04.198937 u2DelayCellTimex100 = 270/100 ps
4422 11:41:04.202686 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4423 11:41:04.205605 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4424 11:41:04.209430 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4425 11:41:04.212636 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4426 11:41:04.216175 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4427 11:41:04.219074 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4428 11:41:04.219182
4429 11:41:04.222852 CA PerBit enable=1, Macro0, CA PI delay=34
4430 11:41:04.226115
4431 11:41:04.226219 [CBTSetCACLKResult] CA Dly = 34
4432 11:41:04.229656 CS Dly: 6 (0~38)
4433 11:41:04.229761
4434 11:41:04.232727 ----->DramcWriteLeveling(PI) begin...
4435 11:41:04.232842 ==
4436 11:41:04.235992 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 11:41:04.239312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 11:41:04.239416 ==
4439 11:41:04.242534 Write leveling (Byte 0): 30 => 30
4440 11:41:04.245892 Write leveling (Byte 1): 30 => 30
4441 11:41:04.249299 DramcWriteLeveling(PI) end<-----
4442 11:41:04.249398
4443 11:41:04.249494 ==
4444 11:41:04.252255 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 11:41:04.256010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 11:41:04.256128 ==
4447 11:41:04.259072 [Gating] SW mode calibration
4448 11:41:04.266026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4449 11:41:04.272332 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4450 11:41:04.275671 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 11:41:04.282106 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 11:41:04.285440 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4453 11:41:04.289316 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 1)
4454 11:41:04.295914 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4455 11:41:04.299180 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 11:41:04.302293 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 11:41:04.308734 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 11:41:04.312435 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 11:41:04.315800 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 11:41:04.318994 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4461 11:41:04.325749 0 10 12 | B1->B0 | 3636 3737 | 0 0 | (0 0) (0 0)
4462 11:41:04.328658 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 11:41:04.332386 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 11:41:04.339063 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 11:41:04.342382 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 11:41:04.345735 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 11:41:04.352334 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 11:41:04.355583 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 11:41:04.358766 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4470 11:41:04.365637 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 11:41:04.368760 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 11:41:04.372002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 11:41:04.378852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 11:41:04.382127 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 11:41:04.385470 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 11:41:04.392310 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 11:41:04.395641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 11:41:04.398965 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 11:41:04.405510 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 11:41:04.408680 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 11:41:04.412638 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 11:41:04.418524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 11:41:04.422249 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 11:41:04.425308 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 11:41:04.432091 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4486 11:41:04.435170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 11:41:04.439005 Total UI for P1: 0, mck2ui 16
4488 11:41:04.442153 best dqsien dly found for B0: ( 0, 13, 12)
4489 11:41:04.445509 Total UI for P1: 0, mck2ui 16
4490 11:41:04.448681 best dqsien dly found for B1: ( 0, 13, 12)
4491 11:41:04.452113 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4492 11:41:04.455335 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4493 11:41:04.455439
4494 11:41:04.458625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4495 11:41:04.461904 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4496 11:41:04.464899 [Gating] SW calibration Done
4497 11:41:04.465005 ==
4498 11:41:04.468533 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 11:41:04.471731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 11:41:04.471856 ==
4501 11:41:04.475310 RX Vref Scan: 0
4502 11:41:04.475411
4503 11:41:04.478517 RX Vref 0 -> 0, step: 1
4504 11:41:04.478616
4505 11:41:04.478707 RX Delay -230 -> 252, step: 16
4506 11:41:04.485489 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4507 11:41:04.488760 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4508 11:41:04.491950 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4509 11:41:04.495022 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4510 11:41:04.501479 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4511 11:41:04.505355 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4512 11:41:04.508713 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4513 11:41:04.511713 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4514 11:41:04.515094 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4515 11:41:04.521844 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4516 11:41:04.525148 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4517 11:41:04.528315 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4518 11:41:04.531916 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4519 11:41:04.538313 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4520 11:41:04.541628 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4521 11:41:04.545076 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4522 11:41:04.545164 ==
4523 11:41:04.548151 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 11:41:04.551464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 11:41:04.555449 ==
4526 11:41:04.555528 DQS Delay:
4527 11:41:04.555602 DQS0 = 0, DQS1 = 0
4528 11:41:04.558138 DQM Delay:
4529 11:41:04.558215 DQM0 = 52, DQM1 = 48
4530 11:41:04.561499 DQ Delay:
4531 11:41:04.561575 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4532 11:41:04.565380 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4533 11:41:04.568484 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4534 11:41:04.571546 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4535 11:41:04.571618
4536 11:41:04.575339
4537 11:41:04.575419 ==
4538 11:41:04.578499 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 11:41:04.581513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 11:41:04.581620 ==
4541 11:41:04.581716
4542 11:41:04.581806
4543 11:41:04.584743 TX Vref Scan disable
4544 11:41:04.584855 == TX Byte 0 ==
4545 11:41:04.591772 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 11:41:04.595139 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 11:41:04.595241 == TX Byte 1 ==
4548 11:41:04.601586 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4549 11:41:04.605401 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4550 11:41:04.605507 ==
4551 11:41:04.607977 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 11:41:04.611286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 11:41:04.611389 ==
4554 11:41:04.611482
4555 11:41:04.611577
4556 11:41:04.615121 TX Vref Scan disable
4557 11:41:04.618360 == TX Byte 0 ==
4558 11:41:04.621590 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4559 11:41:04.624889 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4560 11:41:04.628544 == TX Byte 1 ==
4561 11:41:04.631613 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4562 11:41:04.634745 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4563 11:41:04.634851
4564 11:41:04.638398 [DATLAT]
4565 11:41:04.638504 Freq=600, CH1 RK0
4566 11:41:04.638598
4567 11:41:04.641634 DATLAT Default: 0x9
4568 11:41:04.641736 0, 0xFFFF, sum = 0
4569 11:41:04.644742 1, 0xFFFF, sum = 0
4570 11:41:04.644851 2, 0xFFFF, sum = 0
4571 11:41:04.648358 3, 0xFFFF, sum = 0
4572 11:41:04.648471 4, 0xFFFF, sum = 0
4573 11:41:04.651437 5, 0xFFFF, sum = 0
4574 11:41:04.651542 6, 0xFFFF, sum = 0
4575 11:41:04.654764 7, 0xFFFF, sum = 0
4576 11:41:04.654873 8, 0x0, sum = 1
4577 11:41:04.658091 9, 0x0, sum = 2
4578 11:41:04.658195 10, 0x0, sum = 3
4579 11:41:04.661492 11, 0x0, sum = 4
4580 11:41:04.661593 best_step = 9
4581 11:41:04.661684
4582 11:41:04.661778 ==
4583 11:41:04.664767 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 11:41:04.668064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 11:41:04.671401 ==
4586 11:41:04.671501 RX Vref Scan: 1
4587 11:41:04.671596
4588 11:41:04.674627 RX Vref 0 -> 0, step: 1
4589 11:41:04.674728
4590 11:41:04.678465 RX Delay -163 -> 252, step: 8
4591 11:41:04.678577
4592 11:41:04.681681 Set Vref, RX VrefLevel [Byte0]: 55
4593 11:41:04.684647 [Byte1]: 52
4594 11:41:04.684753
4595 11:41:04.687679 Final RX Vref Byte 0 = 55 to rank0
4596 11:41:04.691486 Final RX Vref Byte 1 = 52 to rank0
4597 11:41:04.694660 Final RX Vref Byte 0 = 55 to rank1
4598 11:41:04.697900 Final RX Vref Byte 1 = 52 to rank1==
4599 11:41:04.701214 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 11:41:04.704532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 11:41:04.704637 ==
4602 11:41:04.704738 DQS Delay:
4603 11:41:04.708182 DQS0 = 0, DQS1 = 0
4604 11:41:04.708283 DQM Delay:
4605 11:41:04.711383 DQM0 = 48, DQM1 = 45
4606 11:41:04.711486 DQ Delay:
4607 11:41:04.714526 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4608 11:41:04.717922 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4609 11:41:04.721241 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4610 11:41:04.724561 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4611 11:41:04.724664
4612 11:41:04.724756
4613 11:41:04.734732 [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4614 11:41:04.734843 CH1 RK0: MR19=808, MR18=476C
4615 11:41:04.741155 CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115
4616 11:41:04.741265
4617 11:41:04.744805 ----->DramcWriteLeveling(PI) begin...
4618 11:41:04.744919 ==
4619 11:41:04.747941 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 11:41:04.754875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 11:41:04.754984 ==
4622 11:41:04.757707 Write leveling (Byte 0): 30 => 30
4623 11:41:04.760875 Write leveling (Byte 1): 30 => 30
4624 11:41:04.760961 DramcWriteLeveling(PI) end<-----
4625 11:41:04.761029
4626 11:41:04.764141 ==
4627 11:41:04.767998 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 11:41:04.771241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 11:41:04.771350 ==
4630 11:41:04.774547 [Gating] SW mode calibration
4631 11:41:04.781175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4632 11:41:04.784669 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4633 11:41:04.791041 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 11:41:04.794268 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 11:41:04.797814 0 9 8 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
4636 11:41:04.804140 0 9 12 | B1->B0 | 2c2c 2f2f | 1 1 | (1 0) (1 0)
4637 11:41:04.807519 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
4638 11:41:04.810749 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 11:41:04.817602 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 11:41:04.821014 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 11:41:04.824267 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 11:41:04.831171 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 11:41:04.834593 0 10 8 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
4644 11:41:04.837666 0 10 12 | B1->B0 | 3737 3434 | 0 0 | (0 0) (0 0)
4645 11:41:04.844414 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 11:41:04.847261 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 11:41:04.850991 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 11:41:04.857357 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 11:41:04.861179 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 11:41:04.864130 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 11:41:04.867374 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 11:41:04.873899 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4653 11:41:04.877203 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4654 11:41:04.880459 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 11:41:04.887627 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 11:41:04.890818 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 11:41:04.894146 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 11:41:04.900954 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 11:41:04.904098 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 11:41:04.907500 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 11:41:04.914442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 11:41:04.917727 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 11:41:04.920788 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 11:41:04.927231 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 11:41:04.930454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 11:41:04.934258 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 11:41:04.940751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4668 11:41:04.943910 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:41:04.947047 Total UI for P1: 0, mck2ui 16
4670 11:41:04.950621 best dqsien dly found for B0: ( 0, 13, 8)
4671 11:41:04.953719 Total UI for P1: 0, mck2ui 16
4672 11:41:04.957494 best dqsien dly found for B1: ( 0, 13, 10)
4673 11:41:04.960537 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4674 11:41:04.963801 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4675 11:41:04.963887
4676 11:41:04.966933 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4677 11:41:04.970617 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4678 11:41:04.974034 [Gating] SW calibration Done
4679 11:41:04.974129 ==
4680 11:41:04.977296 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 11:41:04.980505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 11:41:04.983870 ==
4683 11:41:04.983955 RX Vref Scan: 0
4684 11:41:04.984024
4685 11:41:04.987086 RX Vref 0 -> 0, step: 1
4686 11:41:04.987175
4687 11:41:04.990382 RX Delay -230 -> 252, step: 16
4688 11:41:04.993719 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4689 11:41:04.996737 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4690 11:41:05.000165 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4691 11:41:05.003851 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4692 11:41:05.010853 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4693 11:41:05.014014 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4694 11:41:05.017288 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4695 11:41:05.020620 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4696 11:41:05.027138 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4697 11:41:05.030216 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4698 11:41:05.033851 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4699 11:41:05.037054 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4700 11:41:05.043661 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4701 11:41:05.046972 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4702 11:41:05.050369 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4703 11:41:05.053565 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4704 11:41:05.053652 ==
4705 11:41:05.056524 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 11:41:05.063023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 11:41:05.063110 ==
4708 11:41:05.063179 DQS Delay:
4709 11:41:05.066871 DQS0 = 0, DQS1 = 0
4710 11:41:05.066956 DQM Delay:
4711 11:41:05.067024 DQM0 = 50, DQM1 = 48
4712 11:41:05.069955 DQ Delay:
4713 11:41:05.073043 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4714 11:41:05.076684 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4715 11:41:05.079653 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4716 11:41:05.082992 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4717 11:41:05.083078
4718 11:41:05.083147
4719 11:41:05.083210 ==
4720 11:41:05.086861 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 11:41:05.090235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 11:41:05.090322 ==
4723 11:41:05.090390
4724 11:41:05.090454
4725 11:41:05.093557 TX Vref Scan disable
4726 11:41:05.093643 == TX Byte 0 ==
4727 11:41:05.100175 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4728 11:41:05.103218 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4729 11:41:05.103303 == TX Byte 1 ==
4730 11:41:05.110117 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4731 11:41:05.113317 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4732 11:41:05.113404 ==
4733 11:41:05.116497 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 11:41:05.120263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 11:41:05.120350 ==
4736 11:41:05.120419
4737 11:41:05.120482
4738 11:41:05.123466 TX Vref Scan disable
4739 11:41:05.126199 == TX Byte 0 ==
4740 11:41:05.130048 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4741 11:41:05.133306 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4742 11:41:05.136400 == TX Byte 1 ==
4743 11:41:05.140088 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4744 11:41:05.146659 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4745 11:41:05.146749
4746 11:41:05.146818 [DATLAT]
4747 11:41:05.146882 Freq=600, CH1 RK1
4748 11:41:05.146943
4749 11:41:05.149945 DATLAT Default: 0x9
4750 11:41:05.150031 0, 0xFFFF, sum = 0
4751 11:41:05.153286 1, 0xFFFF, sum = 0
4752 11:41:05.153373 2, 0xFFFF, sum = 0
4753 11:41:05.156555 3, 0xFFFF, sum = 0
4754 11:41:05.156642 4, 0xFFFF, sum = 0
4755 11:41:05.159859 5, 0xFFFF, sum = 0
4756 11:41:05.163024 6, 0xFFFF, sum = 0
4757 11:41:05.163111 7, 0xFFFF, sum = 0
4758 11:41:05.163181 8, 0x0, sum = 1
4759 11:41:05.166159 9, 0x0, sum = 2
4760 11:41:05.166246 10, 0x0, sum = 3
4761 11:41:05.169828 11, 0x0, sum = 4
4762 11:41:05.169915 best_step = 9
4763 11:41:05.169983
4764 11:41:05.170045 ==
4765 11:41:05.172856 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 11:41:05.179467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 11:41:05.179555 ==
4768 11:41:05.179624 RX Vref Scan: 0
4769 11:41:05.179687
4770 11:41:05.183233 RX Vref 0 -> 0, step: 1
4771 11:41:05.183318
4772 11:41:05.186296 RX Delay -163 -> 252, step: 8
4773 11:41:05.189579 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4774 11:41:05.196071 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4775 11:41:05.199448 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4776 11:41:05.202674 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4777 11:41:05.206468 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4778 11:41:05.209692 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4779 11:41:05.213451 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4780 11:41:05.219580 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4781 11:41:05.223564 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4782 11:41:05.226483 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4783 11:41:05.229765 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4784 11:41:05.236228 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4785 11:41:05.239517 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4786 11:41:05.242772 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4787 11:41:05.246265 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4788 11:41:05.249410 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4789 11:41:05.252660 ==
4790 11:41:05.255977 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 11:41:05.259302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 11:41:05.259386 ==
4793 11:41:05.259452 DQS Delay:
4794 11:41:05.262585 DQS0 = 0, DQS1 = 0
4795 11:41:05.262658 DQM Delay:
4796 11:41:05.266400 DQM0 = 49, DQM1 = 45
4797 11:41:05.266475 DQ Delay:
4798 11:41:05.269755 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4799 11:41:05.272996 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4800 11:41:05.276052 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4801 11:41:05.279203 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4802 11:41:05.279286
4803 11:41:05.279373
4804 11:41:05.285876 [DQSOSCAuto] RK1, (LSB)MR18= 0x6820, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4805 11:41:05.289637 CH1 RK1: MR19=808, MR18=6820
4806 11:41:05.295865 CH1_RK1: MR19=0x808, MR18=0x6820, DQSOSC=390, MR23=63, INC=172, DEC=114
4807 11:41:05.299240 [RxdqsGatingPostProcess] freq 600
4808 11:41:05.305810 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4809 11:41:05.305895 Pre-setting of DQS Precalculation
4810 11:41:05.312775 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4811 11:41:05.319098 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4812 11:41:05.325855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4813 11:41:05.325939
4814 11:41:05.326007
4815 11:41:05.329056 [Calibration Summary] 1200 Mbps
4816 11:41:05.332702 CH 0, Rank 0
4817 11:41:05.332784 SW Impedance : PASS
4818 11:41:05.335960 DUTY Scan : NO K
4819 11:41:05.339430 ZQ Calibration : PASS
4820 11:41:05.339509 Jitter Meter : NO K
4821 11:41:05.342637 CBT Training : PASS
4822 11:41:05.342719 Write leveling : PASS
4823 11:41:05.346005 RX DQS gating : PASS
4824 11:41:05.348715 RX DQ/DQS(RDDQC) : PASS
4825 11:41:05.348798 TX DQ/DQS : PASS
4826 11:41:05.352514 RX DATLAT : PASS
4827 11:41:05.355579 RX DQ/DQS(Engine): PASS
4828 11:41:05.355656 TX OE : NO K
4829 11:41:05.359230 All Pass.
4830 11:41:05.359312
4831 11:41:05.359377 CH 0, Rank 1
4832 11:41:05.362455 SW Impedance : PASS
4833 11:41:05.362530 DUTY Scan : NO K
4834 11:41:05.365763 ZQ Calibration : PASS
4835 11:41:05.368858 Jitter Meter : NO K
4836 11:41:05.368938 CBT Training : PASS
4837 11:41:05.372045 Write leveling : PASS
4838 11:41:05.375397 RX DQS gating : PASS
4839 11:41:05.375483 RX DQ/DQS(RDDQC) : PASS
4840 11:41:05.378663 TX DQ/DQS : PASS
4841 11:41:05.382381 RX DATLAT : PASS
4842 11:41:05.382458 RX DQ/DQS(Engine): PASS
4843 11:41:05.385626 TX OE : NO K
4844 11:41:05.385710 All Pass.
4845 11:41:05.385776
4846 11:41:05.388597 CH 1, Rank 0
4847 11:41:05.388680 SW Impedance : PASS
4848 11:41:05.392276 DUTY Scan : NO K
4849 11:41:05.392360 ZQ Calibration : PASS
4850 11:41:05.395345 Jitter Meter : NO K
4851 11:41:05.398911 CBT Training : PASS
4852 11:41:05.398995 Write leveling : PASS
4853 11:41:05.402295 RX DQS gating : PASS
4854 11:41:05.405615 RX DQ/DQS(RDDQC) : PASS
4855 11:41:05.405694 TX DQ/DQS : PASS
4856 11:41:05.409003 RX DATLAT : PASS
4857 11:41:05.412300 RX DQ/DQS(Engine): PASS
4858 11:41:05.412377 TX OE : NO K
4859 11:41:05.415621 All Pass.
4860 11:41:05.415697
4861 11:41:05.415761 CH 1, Rank 1
4862 11:41:05.418750 SW Impedance : PASS
4863 11:41:05.418843 DUTY Scan : NO K
4864 11:41:05.421972 ZQ Calibration : PASS
4865 11:41:05.425152 Jitter Meter : NO K
4866 11:41:05.425232 CBT Training : PASS
4867 11:41:05.428725 Write leveling : PASS
4868 11:41:05.431818 RX DQS gating : PASS
4869 11:41:05.431900 RX DQ/DQS(RDDQC) : PASS
4870 11:41:05.434960 TX DQ/DQS : PASS
4871 11:41:05.438984 RX DATLAT : PASS
4872 11:41:05.439061 RX DQ/DQS(Engine): PASS
4873 11:41:05.441937 TX OE : NO K
4874 11:41:05.442082 All Pass.
4875 11:41:05.442181
4876 11:41:05.445044 DramC Write-DBI off
4877 11:41:05.448292 PER_BANK_REFRESH: Hybrid Mode
4878 11:41:05.448382 TX_TRACKING: ON
4879 11:41:05.458615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4880 11:41:05.461664 [FAST_K] Save calibration result to emmc
4881 11:41:05.465395 dramc_set_vcore_voltage set vcore to 662500
4882 11:41:05.465483 Read voltage for 933, 3
4883 11:41:05.468636 Vio18 = 0
4884 11:41:05.468731 Vcore = 662500
4885 11:41:05.468867 Vdram = 0
4886 11:41:05.471981 Vddq = 0
4887 11:41:05.472064 Vmddr = 0
4888 11:41:05.478919 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4889 11:41:05.481619 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4890 11:41:05.485597 MEM_TYPE=3, freq_sel=17
4891 11:41:05.488713 sv_algorithm_assistance_LP4_1600
4892 11:41:05.491761 ============ PULL DRAM RESETB DOWN ============
4893 11:41:05.494809 ========== PULL DRAM RESETB DOWN end =========
4894 11:41:05.501747 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4895 11:41:05.505293 ===================================
4896 11:41:05.505410 LPDDR4 DRAM CONFIGURATION
4897 11:41:05.508450 ===================================
4898 11:41:05.511663 EX_ROW_EN[0] = 0x0
4899 11:41:05.514870 EX_ROW_EN[1] = 0x0
4900 11:41:05.514974 LP4Y_EN = 0x0
4901 11:41:05.518383 WORK_FSP = 0x0
4902 11:41:05.518486 WL = 0x3
4903 11:41:05.521574 RL = 0x3
4904 11:41:05.521657 BL = 0x2
4905 11:41:05.524756 RPST = 0x0
4906 11:41:05.524860 RD_PRE = 0x0
4907 11:41:05.528585 WR_PRE = 0x1
4908 11:41:05.528664 WR_PST = 0x0
4909 11:41:05.531683 DBI_WR = 0x0
4910 11:41:05.531761 DBI_RD = 0x0
4911 11:41:05.534962 OTF = 0x1
4912 11:41:05.538166 ===================================
4913 11:41:05.541386 ===================================
4914 11:41:05.541501 ANA top config
4915 11:41:05.545184 ===================================
4916 11:41:05.548078 DLL_ASYNC_EN = 0
4917 11:41:05.551337 ALL_SLAVE_EN = 1
4918 11:41:05.551451 NEW_RANK_MODE = 1
4919 11:41:05.555261 DLL_IDLE_MODE = 1
4920 11:41:05.558105 LP45_APHY_COMB_EN = 1
4921 11:41:05.561861 TX_ODT_DIS = 1
4922 11:41:05.565068 NEW_8X_MODE = 1
4923 11:41:05.568196 ===================================
4924 11:41:05.571312 ===================================
4925 11:41:05.571428 data_rate = 1866
4926 11:41:05.574692 CKR = 1
4927 11:41:05.578508 DQ_P2S_RATIO = 8
4928 11:41:05.581703 ===================================
4929 11:41:05.585102 CA_P2S_RATIO = 8
4930 11:41:05.588391 DQ_CA_OPEN = 0
4931 11:41:05.591704 DQ_SEMI_OPEN = 0
4932 11:41:05.591790 CA_SEMI_OPEN = 0
4933 11:41:05.594796 CA_FULL_RATE = 0
4934 11:41:05.598342 DQ_CKDIV4_EN = 1
4935 11:41:05.601429 CA_CKDIV4_EN = 1
4936 11:41:05.604448 CA_PREDIV_EN = 0
4937 11:41:05.608359 PH8_DLY = 0
4938 11:41:05.608439 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4939 11:41:05.611360 DQ_AAMCK_DIV = 4
4940 11:41:05.614644 CA_AAMCK_DIV = 4
4941 11:41:05.617932 CA_ADMCK_DIV = 4
4942 11:41:05.621266 DQ_TRACK_CA_EN = 0
4943 11:41:05.624696 CA_PICK = 933
4944 11:41:05.624827 CA_MCKIO = 933
4945 11:41:05.627938 MCKIO_SEMI = 0
4946 11:41:05.631127 PLL_FREQ = 3732
4947 11:41:05.634941 DQ_UI_PI_RATIO = 32
4948 11:41:05.638056 CA_UI_PI_RATIO = 0
4949 11:41:05.641285 ===================================
4950 11:41:05.644379 ===================================
4951 11:41:05.647723 memory_type:LPDDR4
4952 11:41:05.647817 GP_NUM : 10
4953 11:41:05.651311 SRAM_EN : 1
4954 11:41:05.651389 MD32_EN : 0
4955 11:41:05.654570 ===================================
4956 11:41:05.657804 [ANA_INIT] >>>>>>>>>>>>>>
4957 11:41:05.661108 <<<<<< [CONFIGURE PHASE]: ANA_TX
4958 11:41:05.664508 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4959 11:41:05.667638 ===================================
4960 11:41:05.670950 data_rate = 1866,PCW = 0X8f00
4961 11:41:05.674185 ===================================
4962 11:41:05.678074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4963 11:41:05.684352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4964 11:41:05.687483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4965 11:41:05.694832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4966 11:41:05.697952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4967 11:41:05.701054 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4968 11:41:05.701138 [ANA_INIT] flow start
4969 11:41:05.704262 [ANA_INIT] PLL >>>>>>>>
4970 11:41:05.707583 [ANA_INIT] PLL <<<<<<<<
4971 11:41:05.707669 [ANA_INIT] MIDPI >>>>>>>>
4972 11:41:05.710628 [ANA_INIT] MIDPI <<<<<<<<
4973 11:41:05.714391 [ANA_INIT] DLL >>>>>>>>
4974 11:41:05.714480 [ANA_INIT] flow end
4975 11:41:05.720767 ============ LP4 DIFF to SE enter ============
4976 11:41:05.724086 ============ LP4 DIFF to SE exit ============
4977 11:41:05.727379 [ANA_INIT] <<<<<<<<<<<<<
4978 11:41:05.727464 [Flow] Enable top DCM control >>>>>
4979 11:41:05.730745 [Flow] Enable top DCM control <<<<<
4980 11:41:05.734059 Enable DLL master slave shuffle
4981 11:41:05.741152 ==============================================================
4982 11:41:05.744478 Gating Mode config
4983 11:41:05.747756 ==============================================================
4984 11:41:05.750852 Config description:
4985 11:41:05.760699 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4986 11:41:05.767330 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4987 11:41:05.771311 SELPH_MODE 0: By rank 1: By Phase
4988 11:41:05.777770 ==============================================================
4989 11:41:05.780986 GAT_TRACK_EN = 1
4990 11:41:05.784637 RX_GATING_MODE = 2
4991 11:41:05.784757 RX_GATING_TRACK_MODE = 2
4992 11:41:05.787667 SELPH_MODE = 1
4993 11:41:05.790868 PICG_EARLY_EN = 1
4994 11:41:05.794206 VALID_LAT_VALUE = 1
4995 11:41:05.800611 ==============================================================
4996 11:41:05.803833 Enter into Gating configuration >>>>
4997 11:41:05.807419 Exit from Gating configuration <<<<
4998 11:41:05.810480 Enter into DVFS_PRE_config >>>>>
4999 11:41:05.821021 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5000 11:41:05.824144 Exit from DVFS_PRE_config <<<<<
5001 11:41:05.827423 Enter into PICG configuration >>>>
5002 11:41:05.830683 Exit from PICG configuration <<<<
5003 11:41:05.834113 [RX_INPUT] configuration >>>>>
5004 11:41:05.837416 [RX_INPUT] configuration <<<<<
5005 11:41:05.840681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5006 11:41:05.847106 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5007 11:41:05.854162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5008 11:41:05.860922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5009 11:41:05.864328 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5010 11:41:05.870525 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5011 11:41:05.873729 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5012 11:41:05.880904 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5013 11:41:05.884244 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5014 11:41:05.887494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5015 11:41:05.890634 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5016 11:41:05.897573 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5017 11:41:05.900353 ===================================
5018 11:41:05.900430 LPDDR4 DRAM CONFIGURATION
5019 11:41:05.903557 ===================================
5020 11:41:05.907557 EX_ROW_EN[0] = 0x0
5021 11:41:05.910714 EX_ROW_EN[1] = 0x0
5022 11:41:05.910799 LP4Y_EN = 0x0
5023 11:41:05.913703 WORK_FSP = 0x0
5024 11:41:05.913782 WL = 0x3
5025 11:41:05.917371 RL = 0x3
5026 11:41:05.917454 BL = 0x2
5027 11:41:05.920477 RPST = 0x0
5028 11:41:05.920554 RD_PRE = 0x0
5029 11:41:05.923607 WR_PRE = 0x1
5030 11:41:05.923686 WR_PST = 0x0
5031 11:41:05.927190 DBI_WR = 0x0
5032 11:41:05.927284 DBI_RD = 0x0
5033 11:41:05.930213 OTF = 0x1
5034 11:41:05.933571 ===================================
5035 11:41:05.936953 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5036 11:41:05.940354 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5037 11:41:05.946945 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5038 11:41:05.950310 ===================================
5039 11:41:05.950401 LPDDR4 DRAM CONFIGURATION
5040 11:41:05.954019 ===================================
5041 11:41:05.957322 EX_ROW_EN[0] = 0x10
5042 11:41:05.960474 EX_ROW_EN[1] = 0x0
5043 11:41:05.960575 LP4Y_EN = 0x0
5044 11:41:05.963590 WORK_FSP = 0x0
5045 11:41:05.963692 WL = 0x3
5046 11:41:05.966972 RL = 0x3
5047 11:41:05.967049 BL = 0x2
5048 11:41:05.970392 RPST = 0x0
5049 11:41:05.970475 RD_PRE = 0x0
5050 11:41:05.973839 WR_PRE = 0x1
5051 11:41:05.973933 WR_PST = 0x0
5052 11:41:05.977224 DBI_WR = 0x0
5053 11:41:05.977312 DBI_RD = 0x0
5054 11:41:05.980333 OTF = 0x1
5055 11:41:05.983581 ===================================
5056 11:41:05.990208 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5057 11:41:05.993468 nWR fixed to 30
5058 11:41:05.993559 [ModeRegInit_LP4] CH0 RK0
5059 11:41:05.996556 [ModeRegInit_LP4] CH0 RK1
5060 11:41:06.000254 [ModeRegInit_LP4] CH1 RK0
5061 11:41:06.003452 [ModeRegInit_LP4] CH1 RK1
5062 11:41:06.003561 match AC timing 9
5063 11:41:06.006674 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5064 11:41:06.013296 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5065 11:41:06.016504 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5066 11:41:06.020173 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5067 11:41:06.026913 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5068 11:41:06.027021 ==
5069 11:41:06.030083 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 11:41:06.033251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 11:41:06.033329 ==
5072 11:41:06.040357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 11:41:06.046245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5074 11:41:06.050164 [CA 0] Center 37 (6~68) winsize 63
5075 11:41:06.053482 [CA 1] Center 37 (7~68) winsize 62
5076 11:41:06.056663 [CA 2] Center 34 (4~65) winsize 62
5077 11:41:06.059889 [CA 3] Center 33 (3~64) winsize 62
5078 11:41:06.063818 [CA 4] Center 33 (3~64) winsize 62
5079 11:41:06.063926 [CA 5] Center 32 (2~62) winsize 61
5080 11:41:06.064028
5081 11:41:06.069740 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5082 11:41:06.069852
5083 11:41:06.073528 [CATrainingPosCal] consider 1 rank data
5084 11:41:06.076701 u2DelayCellTimex100 = 270/100 ps
5085 11:41:06.079857 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5086 11:41:06.083550 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5087 11:41:06.086837 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5088 11:41:06.090010 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5089 11:41:06.093374 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5090 11:41:06.096634 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5091 11:41:06.096747
5092 11:41:06.099872 CA PerBit enable=1, Macro0, CA PI delay=32
5093 11:41:06.103073
5094 11:41:06.103212 [CBTSetCACLKResult] CA Dly = 32
5095 11:41:06.106628 CS Dly: 5 (0~36)
5096 11:41:06.106712 ==
5097 11:41:06.109990 Dram Type= 6, Freq= 0, CH_0, rank 1
5098 11:41:06.113406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 11:41:06.113491 ==
5100 11:41:06.119905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5101 11:41:06.126689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5102 11:41:06.129203 [CA 0] Center 37 (7~68) winsize 62
5103 11:41:06.132812 [CA 1] Center 37 (7~68) winsize 62
5104 11:41:06.136421 [CA 2] Center 34 (4~65) winsize 62
5105 11:41:06.139500 [CA 3] Center 34 (4~65) winsize 62
5106 11:41:06.142573 [CA 4] Center 33 (3~63) winsize 61
5107 11:41:06.145837 [CA 5] Center 32 (2~62) winsize 61
5108 11:41:06.145971
5109 11:41:06.149720 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5110 11:41:06.149809
5111 11:41:06.152450 [CATrainingPosCal] consider 2 rank data
5112 11:41:06.155847 u2DelayCellTimex100 = 270/100 ps
5113 11:41:06.159078 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5114 11:41:06.163012 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5115 11:41:06.166489 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5116 11:41:06.169242 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5117 11:41:06.172425 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5118 11:41:06.176020 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5119 11:41:06.176120
5120 11:41:06.182906 CA PerBit enable=1, Macro0, CA PI delay=32
5121 11:41:06.183010
5122 11:41:06.186074 [CBTSetCACLKResult] CA Dly = 32
5123 11:41:06.186157 CS Dly: 5 (0~37)
5124 11:41:06.186223
5125 11:41:06.189214 ----->DramcWriteLeveling(PI) begin...
5126 11:41:06.189327 ==
5127 11:41:06.192919 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 11:41:06.196158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 11:41:06.196237 ==
5130 11:41:06.199414 Write leveling (Byte 0): 30 => 30
5131 11:41:06.202801 Write leveling (Byte 1): 28 => 28
5132 11:41:06.206058 DramcWriteLeveling(PI) end<-----
5133 11:41:06.206133
5134 11:41:06.206197 ==
5135 11:41:06.209057 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 11:41:06.212702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 11:41:06.215899 ==
5138 11:41:06.215972 [Gating] SW mode calibration
5139 11:41:06.225956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5140 11:41:06.229082 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5141 11:41:06.232741 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5142 11:41:06.238951 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 11:41:06.242743 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 11:41:06.245852 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 11:41:06.252754 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 11:41:06.256071 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 11:41:06.259369 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5148 11:41:06.265988 0 14 28 | B1->B0 | 3333 2727 | 1 1 | (1 0) (1 0)
5149 11:41:06.269386 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5150 11:41:06.272745 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 11:41:06.279137 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 11:41:06.282667 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 11:41:06.285787 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 11:41:06.292520 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 11:41:06.296216 0 15 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5156 11:41:06.299214 0 15 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5157 11:41:06.302960 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5158 11:41:06.309428 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 11:41:06.312745 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 11:41:06.316011 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 11:41:06.322703 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 11:41:06.326059 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 11:41:06.329280 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 11:41:06.335805 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5165 11:41:06.339509 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5166 11:41:06.342606 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 11:41:06.349378 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 11:41:06.352526 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 11:41:06.355644 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 11:41:06.362854 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 11:41:06.365568 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 11:41:06.369887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 11:41:06.375949 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 11:41:06.379305 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 11:41:06.382724 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 11:41:06.389097 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 11:41:06.392170 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 11:41:06.395815 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 11:41:06.402593 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5180 11:41:06.405756 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5181 11:41:06.408965 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 11:41:06.412526 Total UI for P1: 0, mck2ui 16
5183 11:41:06.415876 best dqsien dly found for B0: ( 1, 2, 26)
5184 11:41:06.419196 Total UI for P1: 0, mck2ui 16
5185 11:41:06.422469 best dqsien dly found for B1: ( 1, 2, 30)
5186 11:41:06.426105 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5187 11:41:06.429213 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5188 11:41:06.429294
5189 11:41:06.432483 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5190 11:41:06.438932 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5191 11:41:06.439009 [Gating] SW calibration Done
5192 11:41:06.439078 ==
5193 11:41:06.442103 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 11:41:06.448955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 11:41:06.449045 ==
5196 11:41:06.449115 RX Vref Scan: 0
5197 11:41:06.449226
5198 11:41:06.452693 RX Vref 0 -> 0, step: 1
5199 11:41:06.452822
5200 11:41:06.455930 RX Delay -80 -> 252, step: 8
5201 11:41:06.459211 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5202 11:41:06.462414 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5203 11:41:06.465607 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5204 11:41:06.468890 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5205 11:41:06.475512 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5206 11:41:06.478703 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5207 11:41:06.482009 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5208 11:41:06.485373 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5209 11:41:06.488608 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5210 11:41:06.495221 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5211 11:41:06.498388 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5212 11:41:06.501975 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5213 11:41:06.505150 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5214 11:41:06.508608 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5215 11:41:06.511703 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5216 11:41:06.518726 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5217 11:41:06.518810 ==
5218 11:41:06.521635 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 11:41:06.524996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 11:41:06.525093 ==
5221 11:41:06.525166 DQS Delay:
5222 11:41:06.528330 DQS0 = 0, DQS1 = 0
5223 11:41:06.528417 DQM Delay:
5224 11:41:06.532044 DQM0 = 104, DQM1 = 94
5225 11:41:06.532126 DQ Delay:
5226 11:41:06.535193 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5227 11:41:06.538682 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5228 11:41:06.542006 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5229 11:41:06.545330 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5230 11:41:06.545412
5231 11:41:06.545478
5232 11:41:06.545539 ==
5233 11:41:06.548431 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 11:41:06.551787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 11:41:06.551917 ==
5236 11:41:06.555044
5237 11:41:06.555126
5238 11:41:06.555191 TX Vref Scan disable
5239 11:41:06.558034 == TX Byte 0 ==
5240 11:41:06.561565 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5241 11:41:06.564996 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5242 11:41:06.568264 == TX Byte 1 ==
5243 11:41:06.571554 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5244 11:41:06.574734 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5245 11:41:06.574833 ==
5246 11:41:06.578037 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 11:41:06.584678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 11:41:06.584796 ==
5249 11:41:06.584951
5250 11:41:06.585039
5251 11:41:06.585174 TX Vref Scan disable
5252 11:41:06.589312 == TX Byte 0 ==
5253 11:41:06.592648 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5254 11:41:06.599248 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5255 11:41:06.599354 == TX Byte 1 ==
5256 11:41:06.602510 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5257 11:41:06.609185 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5258 11:41:06.609288
5259 11:41:06.609385 [DATLAT]
5260 11:41:06.609506 Freq=933, CH0 RK0
5261 11:41:06.609619
5262 11:41:06.612397 DATLAT Default: 0xd
5263 11:41:06.612464 0, 0xFFFF, sum = 0
5264 11:41:06.615496 1, 0xFFFF, sum = 0
5265 11:41:06.618655 2, 0xFFFF, sum = 0
5266 11:41:06.618768 3, 0xFFFF, sum = 0
5267 11:41:06.622208 4, 0xFFFF, sum = 0
5268 11:41:06.622322 5, 0xFFFF, sum = 0
5269 11:41:06.625861 6, 0xFFFF, sum = 0
5270 11:41:06.625963 7, 0xFFFF, sum = 0
5271 11:41:06.628852 8, 0xFFFF, sum = 0
5272 11:41:06.628960 9, 0xFFFF, sum = 0
5273 11:41:06.632279 10, 0x0, sum = 1
5274 11:41:06.632407 11, 0x0, sum = 2
5275 11:41:06.635537 12, 0x0, sum = 3
5276 11:41:06.635634 13, 0x0, sum = 4
5277 11:41:06.635731 best_step = 11
5278 11:41:06.635818
5279 11:41:06.638703 ==
5280 11:41:06.642344 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 11:41:06.645944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 11:41:06.646056 ==
5283 11:41:06.646150 RX Vref Scan: 1
5284 11:41:06.646258
5285 11:41:06.649287 RX Vref 0 -> 0, step: 1
5286 11:41:06.649385
5287 11:41:06.652497 RX Delay -53 -> 252, step: 4
5288 11:41:06.652592
5289 11:41:06.655689 Set Vref, RX VrefLevel [Byte0]: 56
5290 11:41:06.659169 [Byte1]: 54
5291 11:41:06.659269
5292 11:41:06.662052 Final RX Vref Byte 0 = 56 to rank0
5293 11:41:06.665906 Final RX Vref Byte 1 = 54 to rank0
5294 11:41:06.668962 Final RX Vref Byte 0 = 56 to rank1
5295 11:41:06.671984 Final RX Vref Byte 1 = 54 to rank1==
5296 11:41:06.675661 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 11:41:06.678819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 11:41:06.678906 ==
5299 11:41:06.682000 DQS Delay:
5300 11:41:06.682083 DQS0 = 0, DQS1 = 0
5301 11:41:06.685457 DQM Delay:
5302 11:41:06.685569 DQM0 = 105, DQM1 = 97
5303 11:41:06.688660 DQ Delay:
5304 11:41:06.691950 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =104
5305 11:41:06.695183 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5306 11:41:06.698505 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5307 11:41:06.701833 DQ12 =100, DQ13 =104, DQ14 =108, DQ15 =106
5308 11:41:06.701947
5309 11:41:06.702039
5310 11:41:06.708980 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5311 11:41:06.712112 CH0 RK0: MR19=505, MR18=3129
5312 11:41:06.718774 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5313 11:41:06.718882
5314 11:41:06.722081 ----->DramcWriteLeveling(PI) begin...
5315 11:41:06.722183 ==
5316 11:41:06.725493 Dram Type= 6, Freq= 0, CH_0, rank 1
5317 11:41:06.728615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 11:41:06.728701 ==
5319 11:41:06.732297 Write leveling (Byte 0): 32 => 32
5320 11:41:06.735340 Write leveling (Byte 1): 31 => 31
5321 11:41:06.738711 DramcWriteLeveling(PI) end<-----
5322 11:41:06.738805
5323 11:41:06.738873 ==
5324 11:41:06.741951 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 11:41:06.745310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 11:41:06.745411 ==
5327 11:41:06.749029 [Gating] SW mode calibration
5328 11:41:06.755553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5329 11:41:06.762026 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5330 11:41:06.765491 0 14 0 | B1->B0 | 3333 3433 | 1 1 | (1 1) (0 0)
5331 11:41:06.772158 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 11:41:06.775647 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 11:41:06.778749 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 11:41:06.785729 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 11:41:06.788581 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 11:41:06.791991 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 1)
5337 11:41:06.798626 0 14 28 | B1->B0 | 2525 2c2c | 0 1 | (0 0) (1 0)
5338 11:41:06.801912 0 15 0 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 0)
5339 11:41:06.805252 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 11:41:06.808574 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 11:41:06.814975 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 11:41:06.818219 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 11:41:06.825108 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 11:41:06.828193 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5345 11:41:06.831765 0 15 28 | B1->B0 | 3939 3535 | 0 0 | (0 0) (0 0)
5346 11:41:06.835082 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5347 11:41:06.841870 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 11:41:06.845205 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 11:41:06.848476 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 11:41:06.854484 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 11:41:06.858355 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 11:41:06.861331 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 11:41:06.868247 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5354 11:41:06.871409 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5355 11:41:06.874765 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:41:06.881360 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 11:41:06.884476 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 11:41:06.888221 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 11:41:06.894290 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 11:41:06.898081 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 11:41:06.901395 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 11:41:06.907926 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 11:41:06.911380 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 11:41:06.914587 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 11:41:06.921203 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 11:41:06.924337 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 11:41:06.928005 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 11:41:06.934344 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 11:41:06.937929 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5370 11:41:06.941216 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5371 11:41:06.944779 Total UI for P1: 0, mck2ui 16
5372 11:41:06.948033 best dqsien dly found for B1: ( 1, 2, 30)
5373 11:41:06.951554 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 11:41:06.954716 Total UI for P1: 0, mck2ui 16
5375 11:41:06.957960 best dqsien dly found for B0: ( 1, 2, 30)
5376 11:41:06.961026 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5377 11:41:06.968011 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5378 11:41:06.968116
5379 11:41:06.971015 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5380 11:41:06.974715 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5381 11:41:06.977772 [Gating] SW calibration Done
5382 11:41:06.977874 ==
5383 11:41:06.981178 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 11:41:06.984328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 11:41:06.984427 ==
5386 11:41:06.987582 RX Vref Scan: 0
5387 11:41:06.987682
5388 11:41:06.987776 RX Vref 0 -> 0, step: 1
5389 11:41:06.987863
5390 11:41:06.991461 RX Delay -80 -> 252, step: 8
5391 11:41:06.994268 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5392 11:41:06.998031 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5393 11:41:07.004543 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5394 11:41:07.007795 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5395 11:41:07.011060 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5396 11:41:07.014360 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5397 11:41:07.017667 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5398 11:41:07.024441 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5399 11:41:07.027701 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5400 11:41:07.031050 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5401 11:41:07.034186 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5402 11:41:07.037932 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5403 11:41:07.041083 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5404 11:41:07.044658 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5405 11:41:07.050889 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5406 11:41:07.054621 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5407 11:41:07.054734 ==
5408 11:41:07.058014 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 11:41:07.060620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 11:41:07.060724 ==
5411 11:41:07.064025 DQS Delay:
5412 11:41:07.064099 DQS0 = 0, DQS1 = 0
5413 11:41:07.064170 DQM Delay:
5414 11:41:07.067493 DQM0 = 105, DQM1 = 93
5415 11:41:07.067596 DQ Delay:
5416 11:41:07.070696 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5417 11:41:07.074150 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5418 11:41:07.077244 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5419 11:41:07.081174 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5420 11:41:07.081257
5421 11:41:07.081323
5422 11:41:07.084182 ==
5423 11:41:07.087449 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 11:41:07.090645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 11:41:07.090755 ==
5426 11:41:07.090867
5427 11:41:07.090964
5428 11:41:07.093892 TX Vref Scan disable
5429 11:41:07.094001 == TX Byte 0 ==
5430 11:41:07.097613 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5431 11:41:07.104161 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5432 11:41:07.104246 == TX Byte 1 ==
5433 11:41:07.107154 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5434 11:41:07.113863 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5435 11:41:07.113976 ==
5436 11:41:07.117192 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 11:41:07.120545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 11:41:07.120649 ==
5439 11:41:07.120748
5440 11:41:07.120843
5441 11:41:07.123908 TX Vref Scan disable
5442 11:41:07.127171 == TX Byte 0 ==
5443 11:41:07.130520 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5444 11:41:07.134449 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5445 11:41:07.137677 == TX Byte 1 ==
5446 11:41:07.141085 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5447 11:41:07.143939 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5448 11:41:07.144050
5449 11:41:07.144147 [DATLAT]
5450 11:41:07.147672 Freq=933, CH0 RK1
5451 11:41:07.147783
5452 11:41:07.150695 DATLAT Default: 0xb
5453 11:41:07.150815 0, 0xFFFF, sum = 0
5454 11:41:07.154312 1, 0xFFFF, sum = 0
5455 11:41:07.154432 2, 0xFFFF, sum = 0
5456 11:41:07.157351 3, 0xFFFF, sum = 0
5457 11:41:07.157472 4, 0xFFFF, sum = 0
5458 11:41:07.161249 5, 0xFFFF, sum = 0
5459 11:41:07.161373 6, 0xFFFF, sum = 0
5460 11:41:07.164456 7, 0xFFFF, sum = 0
5461 11:41:07.164561 8, 0xFFFF, sum = 0
5462 11:41:07.167802 9, 0xFFFF, sum = 0
5463 11:41:07.167898 10, 0x0, sum = 1
5464 11:41:07.171109 11, 0x0, sum = 2
5465 11:41:07.171217 12, 0x0, sum = 3
5466 11:41:07.174302 13, 0x0, sum = 4
5467 11:41:07.174422 best_step = 11
5468 11:41:07.174522
5469 11:41:07.174620 ==
5470 11:41:07.177498 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 11:41:07.180891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 11:41:07.181001 ==
5473 11:41:07.184188 RX Vref Scan: 0
5474 11:41:07.184292
5475 11:41:07.187309 RX Vref 0 -> 0, step: 1
5476 11:41:07.187413
5477 11:41:07.187512 RX Delay -53 -> 252, step: 4
5478 11:41:07.195437 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5479 11:41:07.198817 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5480 11:41:07.202013 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5481 11:41:07.205286 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5482 11:41:07.208378 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5483 11:41:07.215076 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5484 11:41:07.218712 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5485 11:41:07.221945 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5486 11:41:07.225156 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5487 11:41:07.228569 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5488 11:41:07.231865 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5489 11:41:07.238423 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5490 11:41:07.241697 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5491 11:41:07.245013 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5492 11:41:07.248169 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5493 11:41:07.255108 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5494 11:41:07.255207 ==
5495 11:41:07.258253 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 11:41:07.262077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 11:41:07.262162 ==
5498 11:41:07.262229 DQS Delay:
5499 11:41:07.265188 DQS0 = 0, DQS1 = 0
5500 11:41:07.265272 DQM Delay:
5501 11:41:07.268524 DQM0 = 104, DQM1 = 95
5502 11:41:07.268608 DQ Delay:
5503 11:41:07.271856 DQ0 =100, DQ1 =104, DQ2 =100, DQ3 =102
5504 11:41:07.275262 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5505 11:41:07.278526 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =90
5506 11:41:07.281806 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =102
5507 11:41:07.281890
5508 11:41:07.281956
5509 11:41:07.291676 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5510 11:41:07.291765 CH0 RK1: MR19=505, MR18=2B03
5511 11:41:07.297951 CH0_RK1: MR19=0x505, MR18=0x2B03, DQSOSC=408, MR23=63, INC=65, DEC=43
5512 11:41:07.301622 [RxdqsGatingPostProcess] freq 933
5513 11:41:07.307937 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5514 11:41:07.311195 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 11:41:07.315087 best DQS1 dly(2T, 0.5T) = (0, 10)
5516 11:41:07.318057 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 11:41:07.321435 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5518 11:41:07.325219 best DQS0 dly(2T, 0.5T) = (0, 10)
5519 11:41:07.325304 best DQS1 dly(2T, 0.5T) = (0, 10)
5520 11:41:07.328143 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5521 11:41:07.331811 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5522 11:41:07.335152 Pre-setting of DQS Precalculation
5523 11:41:07.341610 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5524 11:41:07.341710 ==
5525 11:41:07.344983 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 11:41:07.348418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 11:41:07.348502 ==
5528 11:41:07.354995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 11:41:07.361730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5530 11:41:07.364754 [CA 0] Center 36 (6~67) winsize 62
5531 11:41:07.367856 [CA 1] Center 36 (6~67) winsize 62
5532 11:41:07.371739 [CA 2] Center 34 (4~65) winsize 62
5533 11:41:07.375065 [CA 3] Center 34 (4~65) winsize 62
5534 11:41:07.378344 [CA 4] Center 34 (4~64) winsize 61
5535 11:41:07.381518 [CA 5] Center 33 (3~63) winsize 61
5536 11:41:07.381600
5537 11:41:07.384622 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5538 11:41:07.384731
5539 11:41:07.387956 [CATrainingPosCal] consider 1 rank data
5540 11:41:07.391287 u2DelayCellTimex100 = 270/100 ps
5541 11:41:07.394649 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5542 11:41:07.397947 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 11:41:07.401227 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5544 11:41:07.404339 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5545 11:41:07.407689 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5546 11:41:07.411182 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5547 11:41:07.411258
5548 11:41:07.417688 CA PerBit enable=1, Macro0, CA PI delay=33
5549 11:41:07.417767
5550 11:41:07.417838 [CBTSetCACLKResult] CA Dly = 33
5551 11:41:07.421545 CS Dly: 7 (0~38)
5552 11:41:07.421614 ==
5553 11:41:07.424611 Dram Type= 6, Freq= 0, CH_1, rank 1
5554 11:41:07.427678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 11:41:07.427751 ==
5556 11:41:07.434458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 11:41:07.441369 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5558 11:41:07.444626 [CA 0] Center 37 (7~67) winsize 61
5559 11:41:07.447954 [CA 1] Center 37 (7~68) winsize 62
5560 11:41:07.451357 [CA 2] Center 35 (5~65) winsize 61
5561 11:41:07.454672 [CA 3] Center 34 (4~65) winsize 62
5562 11:41:07.457871 [CA 4] Center 34 (4~65) winsize 62
5563 11:41:07.460946 [CA 5] Center 34 (4~64) winsize 61
5564 11:41:07.461037
5565 11:41:07.464149 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5566 11:41:07.464234
5567 11:41:07.467697 [CATrainingPosCal] consider 2 rank data
5568 11:41:07.470881 u2DelayCellTimex100 = 270/100 ps
5569 11:41:07.474283 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5570 11:41:07.477697 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5571 11:41:07.481015 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5572 11:41:07.484348 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5573 11:41:07.487610 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5574 11:41:07.490821 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5575 11:41:07.494122
5576 11:41:07.497573 CA PerBit enable=1, Macro0, CA PI delay=33
5577 11:41:07.497655
5578 11:41:07.500774 [CBTSetCACLKResult] CA Dly = 33
5579 11:41:07.500866 CS Dly: 7 (0~39)
5580 11:41:07.500932
5581 11:41:07.504010 ----->DramcWriteLeveling(PI) begin...
5582 11:41:07.504093 ==
5583 11:41:07.507229 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 11:41:07.510669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 11:41:07.513965 ==
5586 11:41:07.514038 Write leveling (Byte 0): 25 => 25
5587 11:41:07.517143 Write leveling (Byte 1): 27 => 27
5588 11:41:07.521088 DramcWriteLeveling(PI) end<-----
5589 11:41:07.521172
5590 11:41:07.521238 ==
5591 11:41:07.524386 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 11:41:07.530723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 11:41:07.530807 ==
5594 11:41:07.530880 [Gating] SW mode calibration
5595 11:41:07.540568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5596 11:41:07.543837 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5597 11:41:07.550596 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 11:41:07.553981 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 11:41:07.557341 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 11:41:07.560566 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 11:41:07.566960 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 11:41:07.570707 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5603 11:41:07.573731 0 14 24 | B1->B0 | 3333 2c2c | 1 1 | (1 0) (1 0)
5604 11:41:07.580476 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (1 0)
5605 11:41:07.583626 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 11:41:07.586928 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 11:41:07.594070 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 11:41:07.596735 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 11:41:07.600057 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 11:41:07.607341 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 11:41:07.610462 0 15 24 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
5612 11:41:07.613709 0 15 28 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5613 11:41:07.620405 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 11:41:07.623537 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 11:41:07.626723 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 11:41:07.633795 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 11:41:07.636987 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 11:41:07.640213 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 11:41:07.647106 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5620 11:41:07.650214 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5621 11:41:07.653393 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:41:07.660436 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:41:07.663858 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 11:41:07.667112 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 11:41:07.673281 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 11:41:07.677145 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 11:41:07.680287 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 11:41:07.686960 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 11:41:07.689975 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 11:41:07.693359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 11:41:07.699711 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 11:41:07.703811 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 11:41:07.707035 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 11:41:07.710245 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 11:41:07.716647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5636 11:41:07.719787 Total UI for P1: 0, mck2ui 16
5637 11:41:07.723105 best dqsien dly found for B1: ( 1, 2, 22)
5638 11:41:07.726914 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 11:41:07.729993 Total UI for P1: 0, mck2ui 16
5640 11:41:07.733437 best dqsien dly found for B0: ( 1, 2, 24)
5641 11:41:07.736561 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5642 11:41:07.740041 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5643 11:41:07.740125
5644 11:41:07.743762 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5645 11:41:07.747000 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5646 11:41:07.750041 [Gating] SW calibration Done
5647 11:41:07.750126 ==
5648 11:41:07.753643 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 11:41:07.759985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 11:41:07.760072 ==
5651 11:41:07.760139 RX Vref Scan: 0
5652 11:41:07.760201
5653 11:41:07.763157 RX Vref 0 -> 0, step: 1
5654 11:41:07.763241
5655 11:41:07.766639 RX Delay -80 -> 252, step: 8
5656 11:41:07.769897 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5657 11:41:07.773422 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5658 11:41:07.776653 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5659 11:41:07.780316 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5660 11:41:07.783405 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5661 11:41:07.790380 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5662 11:41:07.793404 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5663 11:41:07.796545 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5664 11:41:07.799659 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5665 11:41:07.802873 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5666 11:41:07.806195 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5667 11:41:07.813374 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5668 11:41:07.816557 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5669 11:41:07.819648 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5670 11:41:07.823536 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5671 11:41:07.826161 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5672 11:41:07.830086 ==
5673 11:41:07.833303 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 11:41:07.836336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 11:41:07.836426 ==
5676 11:41:07.836494 DQS Delay:
5677 11:41:07.839666 DQS0 = 0, DQS1 = 0
5678 11:41:07.839750 DQM Delay:
5679 11:41:07.843537 DQM0 = 103, DQM1 = 99
5680 11:41:07.843621 DQ Delay:
5681 11:41:07.846714 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5682 11:41:07.849980 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5683 11:41:07.853371 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5684 11:41:07.856484 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5685 11:41:07.856623
5686 11:41:07.856729
5687 11:41:07.856836 ==
5688 11:41:07.859400 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 11:41:07.863157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 11:41:07.863240 ==
5691 11:41:07.866324
5692 11:41:07.866401
5693 11:41:07.866464 TX Vref Scan disable
5694 11:41:07.870081 == TX Byte 0 ==
5695 11:41:07.873294 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5696 11:41:07.875917 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5697 11:41:07.879316 == TX Byte 1 ==
5698 11:41:07.883154 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5699 11:41:07.886223 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5700 11:41:07.889349 ==
5701 11:41:07.889456 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 11:41:07.896243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 11:41:07.896336 ==
5704 11:41:07.896404
5705 11:41:07.896468
5706 11:41:07.899164 TX Vref Scan disable
5707 11:41:07.899281 == TX Byte 0 ==
5708 11:41:07.906199 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5709 11:41:07.909379 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5710 11:41:07.909460 == TX Byte 1 ==
5711 11:41:07.915952 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5712 11:41:07.919335 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5713 11:41:07.919455
5714 11:41:07.919553 [DATLAT]
5715 11:41:07.922507 Freq=933, CH1 RK0
5716 11:41:07.922617
5717 11:41:07.922713 DATLAT Default: 0xd
5718 11:41:07.925726 0, 0xFFFF, sum = 0
5719 11:41:07.925833 1, 0xFFFF, sum = 0
5720 11:41:07.928966 2, 0xFFFF, sum = 0
5721 11:41:07.929075 3, 0xFFFF, sum = 0
5722 11:41:07.932272 4, 0xFFFF, sum = 0
5723 11:41:07.932388 5, 0xFFFF, sum = 0
5724 11:41:07.935700 6, 0xFFFF, sum = 0
5725 11:41:07.935810 7, 0xFFFF, sum = 0
5726 11:41:07.939059 8, 0xFFFF, sum = 0
5727 11:41:07.942073 9, 0xFFFF, sum = 0
5728 11:41:07.942195 10, 0x0, sum = 1
5729 11:41:07.942306 11, 0x0, sum = 2
5730 11:41:07.945247 12, 0x0, sum = 3
5731 11:41:07.945342 13, 0x0, sum = 4
5732 11:41:07.948778 best_step = 11
5733 11:41:07.948870
5734 11:41:07.948938 ==
5735 11:41:07.952202 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 11:41:07.955552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 11:41:07.955663 ==
5738 11:41:07.958730 RX Vref Scan: 1
5739 11:41:07.958826
5740 11:41:07.958894 RX Vref 0 -> 0, step: 1
5741 11:41:07.962017
5742 11:41:07.962137 RX Delay -45 -> 252, step: 4
5743 11:41:07.962238
5744 11:41:07.965750 Set Vref, RX VrefLevel [Byte0]: 55
5745 11:41:07.968653 [Byte1]: 52
5746 11:41:07.972861
5747 11:41:07.972938 Final RX Vref Byte 0 = 55 to rank0
5748 11:41:07.976528 Final RX Vref Byte 1 = 52 to rank0
5749 11:41:07.979666 Final RX Vref Byte 0 = 55 to rank1
5750 11:41:07.982980 Final RX Vref Byte 1 = 52 to rank1==
5751 11:41:07.986260 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 11:41:07.992603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 11:41:07.992724 ==
5754 11:41:07.992834 DQS Delay:
5755 11:41:07.992931 DQS0 = 0, DQS1 = 0
5756 11:41:07.996453 DQM Delay:
5757 11:41:07.996575 DQM0 = 103, DQM1 = 98
5758 11:41:07.999547 DQ Delay:
5759 11:41:08.002610 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5760 11:41:08.006564 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5761 11:41:08.009371 DQ8 =86, DQ9 =92, DQ10 =98, DQ11 =92
5762 11:41:08.012576 DQ12 =104, DQ13 =102, DQ14 =104, DQ15 =106
5763 11:41:08.012683
5764 11:41:08.012782
5765 11:41:08.019639 [DQSOSCAuto] RK0, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5766 11:41:08.022955 CH1 RK0: MR19=505, MR18=162D
5767 11:41:08.028874 CH1_RK0: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43
5768 11:41:08.028963
5769 11:41:08.032660 ----->DramcWriteLeveling(PI) begin...
5770 11:41:08.032768 ==
5771 11:41:08.036127 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 11:41:08.039308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 11:41:08.042745 ==
5774 11:41:08.042849 Write leveling (Byte 0): 25 => 25
5775 11:41:08.045834 Write leveling (Byte 1): 26 => 26
5776 11:41:08.049058 DramcWriteLeveling(PI) end<-----
5777 11:41:08.049165
5778 11:41:08.049259 ==
5779 11:41:08.052587 Dram Type= 6, Freq= 0, CH_1, rank 1
5780 11:41:08.059081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 11:41:08.059188 ==
5782 11:41:08.059286 [Gating] SW mode calibration
5783 11:41:08.068984 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5784 11:41:08.072221 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5785 11:41:08.076051 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 11:41:08.082023 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 11:41:08.085774 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 11:41:08.089013 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 11:41:08.095615 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 11:41:08.098686 0 14 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5791 11:41:08.101793 0 14 24 | B1->B0 | 2c2c 3030 | 0 1 | (0 0) (1 0)
5792 11:41:08.108664 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5793 11:41:08.111919 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 11:41:08.115631 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 11:41:08.122014 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 11:41:08.125439 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 11:41:08.128706 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 11:41:08.135814 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 11:41:08.138999 0 15 24 | B1->B0 | 3737 2929 | 0 1 | (0 0) (0 0)
5800 11:41:08.142446 0 15 28 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
5801 11:41:08.149144 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 11:41:08.152077 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 11:41:08.155204 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 11:41:08.162035 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 11:41:08.165327 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 11:41:08.168682 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 11:41:08.175656 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5808 11:41:08.179030 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 11:41:08.182310 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 11:41:08.188496 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 11:41:08.192284 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 11:41:08.195242 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 11:41:08.201943 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 11:41:08.205038 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 11:41:08.208728 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 11:41:08.215042 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 11:41:08.218722 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 11:41:08.221806 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 11:41:08.228582 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 11:41:08.231774 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 11:41:08.235122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 11:41:08.238346 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 11:41:08.245018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5824 11:41:08.248407 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 11:41:08.251483 Total UI for P1: 0, mck2ui 16
5826 11:41:08.254877 best dqsien dly found for B0: ( 1, 2, 24)
5827 11:41:08.258226 Total UI for P1: 0, mck2ui 16
5828 11:41:08.262074 best dqsien dly found for B1: ( 1, 2, 24)
5829 11:41:08.265147 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5830 11:41:08.268032 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5831 11:41:08.268116
5832 11:41:08.271356 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5833 11:41:08.274680 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5834 11:41:08.278509 [Gating] SW calibration Done
5835 11:41:08.278592 ==
5836 11:41:08.281914 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 11:41:08.288472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 11:41:08.288654 ==
5839 11:41:08.288766 RX Vref Scan: 0
5840 11:41:08.288895
5841 11:41:08.291590 RX Vref 0 -> 0, step: 1
5842 11:41:08.291663
5843 11:41:08.294622 RX Delay -80 -> 252, step: 8
5844 11:41:08.298188 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5845 11:41:08.301378 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5846 11:41:08.304583 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5847 11:41:08.307947 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5848 11:41:08.314308 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5849 11:41:08.317960 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5850 11:41:08.321091 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5851 11:41:08.324774 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5852 11:41:08.327797 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5853 11:41:08.331363 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5854 11:41:08.337560 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5855 11:41:08.340733 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5856 11:41:08.343902 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5857 11:41:08.347259 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5858 11:41:08.351208 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5859 11:41:08.357274 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5860 11:41:08.357357 ==
5861 11:41:08.360603 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 11:41:08.363944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 11:41:08.364029 ==
5864 11:41:08.364095 DQS Delay:
5865 11:41:08.367293 DQS0 = 0, DQS1 = 0
5866 11:41:08.367377 DQM Delay:
5867 11:41:08.370439 DQM0 = 102, DQM1 = 99
5868 11:41:08.370522 DQ Delay:
5869 11:41:08.374270 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95
5870 11:41:08.377258 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5871 11:41:08.380503 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =95
5872 11:41:08.384274 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5873 11:41:08.384357
5874 11:41:08.384423
5875 11:41:08.384483 ==
5876 11:41:08.387639 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 11:41:08.394216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 11:41:08.394300 ==
5879 11:41:08.394365
5880 11:41:08.394425
5881 11:41:08.394482 TX Vref Scan disable
5882 11:41:08.397561 == TX Byte 0 ==
5883 11:41:08.400578 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5884 11:41:08.404407 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5885 11:41:08.407349 == TX Byte 1 ==
5886 11:41:08.410537 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5887 11:41:08.413786 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5888 11:41:08.417609 ==
5889 11:41:08.420599 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 11:41:08.424061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 11:41:08.424144 ==
5892 11:41:08.424211
5893 11:41:08.424273
5894 11:41:08.427123 TX Vref Scan disable
5895 11:41:08.427207 == TX Byte 0 ==
5896 11:41:08.434022 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5897 11:41:08.437125 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5898 11:41:08.437209 == TX Byte 1 ==
5899 11:41:08.443535 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5900 11:41:08.446779 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5901 11:41:08.446864
5902 11:41:08.446930 [DATLAT]
5903 11:41:08.450313 Freq=933, CH1 RK1
5904 11:41:08.450397
5905 11:41:08.450464 DATLAT Default: 0xb
5906 11:41:08.453429 0, 0xFFFF, sum = 0
5907 11:41:08.453515 1, 0xFFFF, sum = 0
5908 11:41:08.457335 2, 0xFFFF, sum = 0
5909 11:41:08.457420 3, 0xFFFF, sum = 0
5910 11:41:08.460622 4, 0xFFFF, sum = 0
5911 11:41:08.460707 5, 0xFFFF, sum = 0
5912 11:41:08.463897 6, 0xFFFF, sum = 0
5913 11:41:08.467056 7, 0xFFFF, sum = 0
5914 11:41:08.467141 8, 0xFFFF, sum = 0
5915 11:41:08.470388 9, 0xFFFF, sum = 0
5916 11:41:08.470473 10, 0x0, sum = 1
5917 11:41:08.473520 11, 0x0, sum = 2
5918 11:41:08.473605 12, 0x0, sum = 3
5919 11:41:08.473673 13, 0x0, sum = 4
5920 11:41:08.476678 best_step = 11
5921 11:41:08.476761
5922 11:41:08.476866 ==
5923 11:41:08.480515 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 11:41:08.483602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 11:41:08.483687 ==
5926 11:41:08.486709 RX Vref Scan: 0
5927 11:41:08.486806
5928 11:41:08.486887 RX Vref 0 -> 0, step: 1
5929 11:41:08.490115
5930 11:41:08.490198 RX Delay -45 -> 252, step: 4
5931 11:41:08.497961 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5932 11:41:08.501185 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5933 11:41:08.504453 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5934 11:41:08.507690 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5935 11:41:08.510790 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5936 11:41:08.517538 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5937 11:41:08.520700 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5938 11:41:08.523983 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5939 11:41:08.527223 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5940 11:41:08.531061 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5941 11:41:08.534286 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5942 11:41:08.541085 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5943 11:41:08.544053 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5944 11:41:08.547297 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5945 11:41:08.550498 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5946 11:41:08.554220 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5947 11:41:08.557467 ==
5948 11:41:08.560568 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 11:41:08.563924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 11:41:08.564010 ==
5951 11:41:08.564077 DQS Delay:
5952 11:41:08.567226 DQS0 = 0, DQS1 = 0
5953 11:41:08.567309 DQM Delay:
5954 11:41:08.570462 DQM0 = 104, DQM1 = 98
5955 11:41:08.570546 DQ Delay:
5956 11:41:08.573813 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5957 11:41:08.577063 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5958 11:41:08.581050 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5959 11:41:08.584126 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5960 11:41:08.584210
5961 11:41:08.584276
5962 11:41:08.593706 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5963 11:41:08.593793 CH1 RK1: MR19=504, MR18=29FD
5964 11:41:08.600406 CH1_RK1: MR19=0x504, MR18=0x29FD, DQSOSC=408, MR23=63, INC=65, DEC=43
5965 11:41:08.603625 [RxdqsGatingPostProcess] freq 933
5966 11:41:08.610229 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5967 11:41:08.613939 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 11:41:08.617167 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 11:41:08.620290 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 11:41:08.623912 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 11:41:08.627051 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 11:41:08.627135 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 11:41:08.630834 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 11:41:08.633959 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 11:41:08.637198 Pre-setting of DQS Precalculation
5976 11:41:08.644071 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5977 11:41:08.650525 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5978 11:41:08.657264 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5979 11:41:08.657354
5980 11:41:08.657421
5981 11:41:08.660676 [Calibration Summary] 1866 Mbps
5982 11:41:08.660762 CH 0, Rank 0
5983 11:41:08.664346 SW Impedance : PASS
5984 11:41:08.667496 DUTY Scan : NO K
5985 11:41:08.667580 ZQ Calibration : PASS
5986 11:41:08.670731 Jitter Meter : NO K
5987 11:41:08.674098 CBT Training : PASS
5988 11:41:08.674182 Write leveling : PASS
5989 11:41:08.677418 RX DQS gating : PASS
5990 11:41:08.680590 RX DQ/DQS(RDDQC) : PASS
5991 11:41:08.680673 TX DQ/DQS : PASS
5992 11:41:08.683871 RX DATLAT : PASS
5993 11:41:08.687083 RX DQ/DQS(Engine): PASS
5994 11:41:08.687167 TX OE : NO K
5995 11:41:08.687234 All Pass.
5996 11:41:08.690345
5997 11:41:08.690428 CH 0, Rank 1
5998 11:41:08.694072 SW Impedance : PASS
5999 11:41:08.694156 DUTY Scan : NO K
6000 11:41:08.697013 ZQ Calibration : PASS
6001 11:41:08.699984 Jitter Meter : NO K
6002 11:41:08.700068 CBT Training : PASS
6003 11:41:08.704074 Write leveling : PASS
6004 11:41:08.704158 RX DQS gating : PASS
6005 11:41:08.707403 RX DQ/DQS(RDDQC) : PASS
6006 11:41:08.710070 TX DQ/DQS : PASS
6007 11:41:08.710154 RX DATLAT : PASS
6008 11:41:08.713982 RX DQ/DQS(Engine): PASS
6009 11:41:08.717442 TX OE : NO K
6010 11:41:08.717526 All Pass.
6011 11:41:08.717592
6012 11:41:08.717652 CH 1, Rank 0
6013 11:41:08.720693 SW Impedance : PASS
6014 11:41:08.723667 DUTY Scan : NO K
6015 11:41:08.723750 ZQ Calibration : PASS
6016 11:41:08.726758 Jitter Meter : NO K
6017 11:41:08.730006 CBT Training : PASS
6018 11:41:08.730089 Write leveling : PASS
6019 11:41:08.733816 RX DQS gating : PASS
6020 11:41:08.737001 RX DQ/DQS(RDDQC) : PASS
6021 11:41:08.737085 TX DQ/DQS : PASS
6022 11:41:08.740041 RX DATLAT : PASS
6023 11:41:08.743388 RX DQ/DQS(Engine): PASS
6024 11:41:08.743472 TX OE : NO K
6025 11:41:08.743539 All Pass.
6026 11:41:08.747075
6027 11:41:08.747191 CH 1, Rank 1
6028 11:41:08.750210 SW Impedance : PASS
6029 11:41:08.750299 DUTY Scan : NO K
6030 11:41:08.753222 ZQ Calibration : PASS
6031 11:41:08.753306 Jitter Meter : NO K
6032 11:41:08.757145 CBT Training : PASS
6033 11:41:08.759987 Write leveling : PASS
6034 11:41:08.760097 RX DQS gating : PASS
6035 11:41:08.763188 RX DQ/DQS(RDDQC) : PASS
6036 11:41:08.766484 TX DQ/DQS : PASS
6037 11:41:08.766588 RX DATLAT : PASS
6038 11:41:08.770228 RX DQ/DQS(Engine): PASS
6039 11:41:08.773369 TX OE : NO K
6040 11:41:08.773480 All Pass.
6041 11:41:08.773574
6042 11:41:08.776720 DramC Write-DBI off
6043 11:41:08.776865 PER_BANK_REFRESH: Hybrid Mode
6044 11:41:08.779986 TX_TRACKING: ON
6045 11:41:08.786588 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6046 11:41:08.793888 [FAST_K] Save calibration result to emmc
6047 11:41:08.796512 dramc_set_vcore_voltage set vcore to 650000
6048 11:41:08.796617 Read voltage for 400, 6
6049 11:41:08.799810 Vio18 = 0
6050 11:41:08.799923 Vcore = 650000
6051 11:41:08.800020 Vdram = 0
6052 11:41:08.803562 Vddq = 0
6053 11:41:08.803668 Vmddr = 0
6054 11:41:08.806397 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6055 11:41:08.813561 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6056 11:41:08.816713 MEM_TYPE=3, freq_sel=20
6057 11:41:08.820102 sv_algorithm_assistance_LP4_800
6058 11:41:08.823460 ============ PULL DRAM RESETB DOWN ============
6059 11:41:08.826675 ========== PULL DRAM RESETB DOWN end =========
6060 11:41:08.829802 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6061 11:41:08.833469 ===================================
6062 11:41:08.836656 LPDDR4 DRAM CONFIGURATION
6063 11:41:08.839855 ===================================
6064 11:41:08.842987 EX_ROW_EN[0] = 0x0
6065 11:41:08.843097 EX_ROW_EN[1] = 0x0
6066 11:41:08.846753 LP4Y_EN = 0x0
6067 11:41:08.846825 WORK_FSP = 0x0
6068 11:41:08.849942 WL = 0x2
6069 11:41:08.850024 RL = 0x2
6070 11:41:08.853109 BL = 0x2
6071 11:41:08.853197 RPST = 0x0
6072 11:41:08.856474 RD_PRE = 0x0
6073 11:41:08.856579 WR_PRE = 0x1
6074 11:41:08.859995 WR_PST = 0x0
6075 11:41:08.863206 DBI_WR = 0x0
6076 11:41:08.863290 DBI_RD = 0x0
6077 11:41:08.866343 OTF = 0x1
6078 11:41:08.869594 ===================================
6079 11:41:08.873180 ===================================
6080 11:41:08.873265 ANA top config
6081 11:41:08.876376 ===================================
6082 11:41:08.879984 DLL_ASYNC_EN = 0
6083 11:41:08.880068 ALL_SLAVE_EN = 1
6084 11:41:08.883435 NEW_RANK_MODE = 1
6085 11:41:08.886174 DLL_IDLE_MODE = 1
6086 11:41:08.889982 LP45_APHY_COMB_EN = 1
6087 11:41:08.893221 TX_ODT_DIS = 1
6088 11:41:08.893307 NEW_8X_MODE = 1
6089 11:41:08.896557 ===================================
6090 11:41:08.899899 ===================================
6091 11:41:08.903090 data_rate = 800
6092 11:41:08.906318 CKR = 1
6093 11:41:08.909541 DQ_P2S_RATIO = 4
6094 11:41:08.912829 ===================================
6095 11:41:08.916416 CA_P2S_RATIO = 4
6096 11:41:08.919765 DQ_CA_OPEN = 0
6097 11:41:08.919886 DQ_SEMI_OPEN = 1
6098 11:41:08.923231 CA_SEMI_OPEN = 1
6099 11:41:08.926510 CA_FULL_RATE = 0
6100 11:41:08.929684 DQ_CKDIV4_EN = 0
6101 11:41:08.932875 CA_CKDIV4_EN = 1
6102 11:41:08.936075 CA_PREDIV_EN = 0
6103 11:41:08.936148 PH8_DLY = 0
6104 11:41:08.939365 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6105 11:41:08.943029 DQ_AAMCK_DIV = 0
6106 11:41:08.946133 CA_AAMCK_DIV = 0
6107 11:41:08.949315 CA_ADMCK_DIV = 4
6108 11:41:08.953079 DQ_TRACK_CA_EN = 0
6109 11:41:08.953159 CA_PICK = 800
6110 11:41:08.956371 CA_MCKIO = 400
6111 11:41:08.959547 MCKIO_SEMI = 400
6112 11:41:08.962842 PLL_FREQ = 3016
6113 11:41:08.966379 DQ_UI_PI_RATIO = 32
6114 11:41:08.969642 CA_UI_PI_RATIO = 32
6115 11:41:08.972711 ===================================
6116 11:41:08.976558 ===================================
6117 11:41:08.976642 memory_type:LPDDR4
6118 11:41:08.979810 GP_NUM : 10
6119 11:41:08.982849 SRAM_EN : 1
6120 11:41:08.982932 MD32_EN : 0
6121 11:41:08.986023 ===================================
6122 11:41:08.989385 [ANA_INIT] >>>>>>>>>>>>>>
6123 11:41:08.992673 <<<<<< [CONFIGURE PHASE]: ANA_TX
6124 11:41:08.996479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6125 11:41:08.999775 ===================================
6126 11:41:09.003004 data_rate = 800,PCW = 0X7400
6127 11:41:09.006247 ===================================
6128 11:41:09.009754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6129 11:41:09.012824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6130 11:41:09.026361 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 11:41:09.029695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6132 11:41:09.033050 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6133 11:41:09.036256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6134 11:41:09.039635 [ANA_INIT] flow start
6135 11:41:09.042724 [ANA_INIT] PLL >>>>>>>>
6136 11:41:09.042799 [ANA_INIT] PLL <<<<<<<<
6137 11:41:09.045749 [ANA_INIT] MIDPI >>>>>>>>
6138 11:41:09.049475 [ANA_INIT] MIDPI <<<<<<<<
6139 11:41:09.049585 [ANA_INIT] DLL >>>>>>>>
6140 11:41:09.052736 [ANA_INIT] flow end
6141 11:41:09.055959 ============ LP4 DIFF to SE enter ============
6142 11:41:09.059205 ============ LP4 DIFF to SE exit ============
6143 11:41:09.062333 [ANA_INIT] <<<<<<<<<<<<<
6144 11:41:09.065570 [Flow] Enable top DCM control >>>>>
6145 11:41:09.069311 [Flow] Enable top DCM control <<<<<
6146 11:41:09.072570 Enable DLL master slave shuffle
6147 11:41:09.079462 ==============================================================
6148 11:41:09.079572 Gating Mode config
6149 11:41:09.085577 ==============================================================
6150 11:41:09.085684 Config description:
6151 11:41:09.095635 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6152 11:41:09.102228 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6153 11:41:09.108758 SELPH_MODE 0: By rank 1: By Phase
6154 11:41:09.112189 ==============================================================
6155 11:41:09.115492 GAT_TRACK_EN = 0
6156 11:41:09.119294 RX_GATING_MODE = 2
6157 11:41:09.122556 RX_GATING_TRACK_MODE = 2
6158 11:41:09.125819 SELPH_MODE = 1
6159 11:41:09.128732 PICG_EARLY_EN = 1
6160 11:41:09.132086 VALID_LAT_VALUE = 1
6161 11:41:09.138601 ==============================================================
6162 11:41:09.141939 Enter into Gating configuration >>>>
6163 11:41:09.145097 Exit from Gating configuration <<<<
6164 11:41:09.149068 Enter into DVFS_PRE_config >>>>>
6165 11:41:09.158368 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6166 11:41:09.162108 Exit from DVFS_PRE_config <<<<<
6167 11:41:09.165144 Enter into PICG configuration >>>>
6168 11:41:09.168394 Exit from PICG configuration <<<<
6169 11:41:09.171610 [RX_INPUT] configuration >>>>>
6170 11:41:09.171715 [RX_INPUT] configuration <<<<<
6171 11:41:09.178572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6172 11:41:09.184793 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6173 11:41:09.188636 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 11:41:09.194978 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 11:41:09.201397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 11:41:09.208432 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 11:41:09.211766 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6178 11:41:09.215166 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6179 11:41:09.221686 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6180 11:41:09.225040 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6181 11:41:09.228100 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6182 11:41:09.235051 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 11:41:09.238387 ===================================
6184 11:41:09.238489 LPDDR4 DRAM CONFIGURATION
6185 11:41:09.241578 ===================================
6186 11:41:09.244955 EX_ROW_EN[0] = 0x0
6187 11:41:09.245032 EX_ROW_EN[1] = 0x0
6188 11:41:09.248383 LP4Y_EN = 0x0
6189 11:41:09.251567 WORK_FSP = 0x0
6190 11:41:09.251675 WL = 0x2
6191 11:41:09.254647 RL = 0x2
6192 11:41:09.254750 BL = 0x2
6193 11:41:09.257808 RPST = 0x0
6194 11:41:09.257911 RD_PRE = 0x0
6195 11:41:09.261450 WR_PRE = 0x1
6196 11:41:09.261553 WR_PST = 0x0
6197 11:41:09.264717 DBI_WR = 0x0
6198 11:41:09.264855 DBI_RD = 0x0
6199 11:41:09.267844 OTF = 0x1
6200 11:41:09.270983 ===================================
6201 11:41:09.274910 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6202 11:41:09.278357 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6203 11:41:09.284510 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6204 11:41:09.288203 ===================================
6205 11:41:09.288310 LPDDR4 DRAM CONFIGURATION
6206 11:41:09.290963 ===================================
6207 11:41:09.294851 EX_ROW_EN[0] = 0x10
6208 11:41:09.294934 EX_ROW_EN[1] = 0x0
6209 11:41:09.298065 LP4Y_EN = 0x0
6210 11:41:09.298168 WORK_FSP = 0x0
6211 11:41:09.301024 WL = 0x2
6212 11:41:09.301140 RL = 0x2
6213 11:41:09.304199 BL = 0x2
6214 11:41:09.308045 RPST = 0x0
6215 11:41:09.308153 RD_PRE = 0x0
6216 11:41:09.311478 WR_PRE = 0x1
6217 11:41:09.311585 WR_PST = 0x0
6218 11:41:09.314733 DBI_WR = 0x0
6219 11:41:09.314835 DBI_RD = 0x0
6220 11:41:09.318193 OTF = 0x1
6221 11:41:09.321497 ===================================
6222 11:41:09.324653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6223 11:41:09.329934 nWR fixed to 30
6224 11:41:09.333160 [ModeRegInit_LP4] CH0 RK0
6225 11:41:09.333268 [ModeRegInit_LP4] CH0 RK1
6226 11:41:09.336358 [ModeRegInit_LP4] CH1 RK0
6227 11:41:09.340145 [ModeRegInit_LP4] CH1 RK1
6228 11:41:09.340256 match AC timing 19
6229 11:41:09.346690 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6230 11:41:09.350017 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6231 11:41:09.353318 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6232 11:41:09.359377 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6233 11:41:09.363177 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6234 11:41:09.363276 ==
6235 11:41:09.366038 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 11:41:09.369700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 11:41:09.369801 ==
6238 11:41:09.376457 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 11:41:09.382755 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6240 11:41:09.385987 [CA 0] Center 36 (8~64) winsize 57
6241 11:41:09.389701 [CA 1] Center 36 (8~64) winsize 57
6242 11:41:09.392829 [CA 2] Center 36 (8~64) winsize 57
6243 11:41:09.396281 [CA 3] Center 36 (8~64) winsize 57
6244 11:41:09.396369 [CA 4] Center 36 (8~64) winsize 57
6245 11:41:09.399638 [CA 5] Center 36 (8~64) winsize 57
6246 11:41:09.399753
6247 11:41:09.406445 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6248 11:41:09.406529
6249 11:41:09.409660 [CATrainingPosCal] consider 1 rank data
6250 11:41:09.412828 u2DelayCellTimex100 = 270/100 ps
6251 11:41:09.415993 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:41:09.419339 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:41:09.422833 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:41:09.426063 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:41:09.429240 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 11:41:09.432541 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 11:41:09.432625
6258 11:41:09.435939 CA PerBit enable=1, Macro0, CA PI delay=36
6259 11:41:09.436023
6260 11:41:09.439337 [CBTSetCACLKResult] CA Dly = 36
6261 11:41:09.442610 CS Dly: 1 (0~32)
6262 11:41:09.442694 ==
6263 11:41:09.446269 Dram Type= 6, Freq= 0, CH_0, rank 1
6264 11:41:09.449411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 11:41:09.449496 ==
6266 11:41:09.456031 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 11:41:09.459214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6268 11:41:09.462630 [CA 0] Center 36 (8~64) winsize 57
6269 11:41:09.465949 [CA 1] Center 36 (8~64) winsize 57
6270 11:41:09.469164 [CA 2] Center 36 (8~64) winsize 57
6271 11:41:09.472332 [CA 3] Center 36 (8~64) winsize 57
6272 11:41:09.476193 [CA 4] Center 36 (8~64) winsize 57
6273 11:41:09.479248 [CA 5] Center 36 (8~64) winsize 57
6274 11:41:09.479335
6275 11:41:09.482347 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6276 11:41:09.482426
6277 11:41:09.485926 [CATrainingPosCal] consider 2 rank data
6278 11:41:09.489359 u2DelayCellTimex100 = 270/100 ps
6279 11:41:09.492518 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:41:09.495656 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 11:41:09.502475 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 11:41:09.505541 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 11:41:09.509353 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 11:41:09.512388 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 11:41:09.512503
6286 11:41:09.515533 CA PerBit enable=1, Macro0, CA PI delay=36
6287 11:41:09.515655
6288 11:41:09.518751 [CBTSetCACLKResult] CA Dly = 36
6289 11:41:09.518835 CS Dly: 1 (0~32)
6290 11:41:09.518902
6291 11:41:09.522467 ----->DramcWriteLeveling(PI) begin...
6292 11:41:09.525724 ==
6293 11:41:09.529107 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 11:41:09.532474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 11:41:09.532585 ==
6296 11:41:09.535866 Write leveling (Byte 0): 40 => 8
6297 11:41:09.539169 Write leveling (Byte 1): 40 => 8
6298 11:41:09.542514 DramcWriteLeveling(PI) end<-----
6299 11:41:09.542600
6300 11:41:09.542667 ==
6301 11:41:09.545864 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 11:41:09.549119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 11:41:09.549204 ==
6304 11:41:09.552339 [Gating] SW mode calibration
6305 11:41:09.558764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6306 11:41:09.562172 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6307 11:41:09.568700 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6308 11:41:09.572081 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 11:41:09.575240 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 11:41:09.582463 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 11:41:09.585592 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 11:41:09.588636 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 11:41:09.595349 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 11:41:09.599034 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 11:41:09.602086 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 11:41:09.605169 Total UI for P1: 0, mck2ui 16
6317 11:41:09.608674 best dqsien dly found for B0: ( 0, 14, 24)
6318 11:41:09.611871 Total UI for P1: 0, mck2ui 16
6319 11:41:09.615514 best dqsien dly found for B1: ( 0, 14, 24)
6320 11:41:09.618949 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6321 11:41:09.621956 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6322 11:41:09.622033
6323 11:41:09.628769 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6324 11:41:09.631997 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 11:41:09.635312 [Gating] SW calibration Done
6326 11:41:09.635430 ==
6327 11:41:09.638489 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 11:41:09.641794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 11:41:09.641885 ==
6330 11:41:09.642015 RX Vref Scan: 0
6331 11:41:09.642117
6332 11:41:09.645087 RX Vref 0 -> 0, step: 1
6333 11:41:09.645192
6334 11:41:09.648373 RX Delay -410 -> 252, step: 16
6335 11:41:09.651798 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6336 11:41:09.658786 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6337 11:41:09.662114 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6338 11:41:09.665415 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6339 11:41:09.668677 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6340 11:41:09.675349 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6341 11:41:09.678508 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6342 11:41:09.681689 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6343 11:41:09.685045 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6344 11:41:09.688322 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6345 11:41:09.695015 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6346 11:41:09.698175 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6347 11:41:09.701873 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6348 11:41:09.708339 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6349 11:41:09.711595 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6350 11:41:09.715167 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6351 11:41:09.715249 ==
6352 11:41:09.718377 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 11:41:09.722023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 11:41:09.722107 ==
6355 11:41:09.725017 DQS Delay:
6356 11:41:09.725091 DQS0 = 27, DQS1 = 35
6357 11:41:09.728195 DQM Delay:
6358 11:41:09.728279 DQM0 = 10, DQM1 = 11
6359 11:41:09.731953 DQ Delay:
6360 11:41:09.732027 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6361 11:41:09.735151 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6362 11:41:09.738451 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6363 11:41:09.741595 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6364 11:41:09.741677
6365 11:41:09.741740
6366 11:41:09.741799 ==
6367 11:41:09.744766 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 11:41:09.751430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 11:41:09.751512 ==
6370 11:41:09.751579
6371 11:41:09.751639
6372 11:41:09.751697 TX Vref Scan disable
6373 11:41:09.754848 == TX Byte 0 ==
6374 11:41:09.758111 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 11:41:09.761342 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 11:41:09.764605 == TX Byte 1 ==
6377 11:41:09.768488 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 11:41:09.771877 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 11:41:09.775197 ==
6380 11:41:09.775279 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 11:41:09.781857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 11:41:09.781940 ==
6383 11:41:09.782005
6384 11:41:09.782066
6385 11:41:09.784918 TX Vref Scan disable
6386 11:41:09.784999 == TX Byte 0 ==
6387 11:41:09.788117 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 11:41:09.794565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 11:41:09.794647 == TX Byte 1 ==
6390 11:41:09.797812 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6391 11:41:09.801242 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6392 11:41:09.804366
6393 11:41:09.804445 [DATLAT]
6394 11:41:09.804509 Freq=400, CH0 RK0
6395 11:41:09.804570
6396 11:41:09.808177 DATLAT Default: 0xf
6397 11:41:09.808258 0, 0xFFFF, sum = 0
6398 11:41:09.811161 1, 0xFFFF, sum = 0
6399 11:41:09.811244 2, 0xFFFF, sum = 0
6400 11:41:09.814380 3, 0xFFFF, sum = 0
6401 11:41:09.814500 4, 0xFFFF, sum = 0
6402 11:41:09.818089 5, 0xFFFF, sum = 0
6403 11:41:09.821043 6, 0xFFFF, sum = 0
6404 11:41:09.821125 7, 0xFFFF, sum = 0
6405 11:41:09.824335 8, 0xFFFF, sum = 0
6406 11:41:09.824419 9, 0xFFFF, sum = 0
6407 11:41:09.828001 10, 0xFFFF, sum = 0
6408 11:41:09.828095 11, 0xFFFF, sum = 0
6409 11:41:09.831255 12, 0xFFFF, sum = 0
6410 11:41:09.831338 13, 0x0, sum = 1
6411 11:41:09.834258 14, 0x0, sum = 2
6412 11:41:09.834341 15, 0x0, sum = 3
6413 11:41:09.837506 16, 0x0, sum = 4
6414 11:41:09.837590 best_step = 14
6415 11:41:09.837655
6416 11:41:09.837716 ==
6417 11:41:09.841279 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 11:41:09.844283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 11:41:09.844365 ==
6420 11:41:09.847828 RX Vref Scan: 1
6421 11:41:09.847910
6422 11:41:09.851157 RX Vref 0 -> 0, step: 1
6423 11:41:09.851238
6424 11:41:09.851303 RX Delay -311 -> 252, step: 8
6425 11:41:09.854450
6426 11:41:09.854532 Set Vref, RX VrefLevel [Byte0]: 56
6427 11:41:09.857838 [Byte1]: 54
6428 11:41:09.863123
6429 11:41:09.863205 Final RX Vref Byte 0 = 56 to rank0
6430 11:41:09.866520 Final RX Vref Byte 1 = 54 to rank0
6431 11:41:09.869736 Final RX Vref Byte 0 = 56 to rank1
6432 11:41:09.872839 Final RX Vref Byte 1 = 54 to rank1==
6433 11:41:09.876207 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 11:41:09.882947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 11:41:09.883030 ==
6436 11:41:09.883094 DQS Delay:
6437 11:41:09.886845 DQS0 = 28, DQS1 = 36
6438 11:41:09.886930 DQM Delay:
6439 11:41:09.886997 DQM0 = 10, DQM1 = 12
6440 11:41:09.890065 DQ Delay:
6441 11:41:09.893217 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6442 11:41:09.893312 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6443 11:41:09.896482 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6444 11:41:09.899610 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6445 11:41:09.899752
6446 11:41:09.899870
6447 11:41:09.909667 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9b7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6448 11:41:09.913349 CH0 RK0: MR19=C0C, MR18=C9B7
6449 11:41:09.919547 CH0_RK0: MR19=0xC0C, MR18=0xC9B7, DQSOSC=384, MR23=63, INC=400, DEC=267
6450 11:41:09.919694 ==
6451 11:41:09.922654 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 11:41:09.926333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 11:41:09.926571 ==
6454 11:41:09.929385 [Gating] SW mode calibration
6455 11:41:09.936500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6456 11:41:09.942815 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6457 11:41:09.946676 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6458 11:41:09.949551 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 11:41:09.953253 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 11:41:09.959853 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 11:41:09.963261 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 11:41:09.966519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 11:41:09.972766 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 11:41:09.975990 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 11:41:09.979052 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 11:41:09.983041 Total UI for P1: 0, mck2ui 16
6467 11:41:09.986452 best dqsien dly found for B0: ( 0, 14, 24)
6468 11:41:09.989694 Total UI for P1: 0, mck2ui 16
6469 11:41:09.993061 best dqsien dly found for B1: ( 0, 14, 24)
6470 11:41:09.996070 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6471 11:41:09.999336 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6472 11:41:10.002575
6473 11:41:10.005787 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6474 11:41:10.009082 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 11:41:10.012379 [Gating] SW calibration Done
6476 11:41:10.012499 ==
6477 11:41:10.016195 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 11:41:10.019334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 11:41:10.019422 ==
6480 11:41:10.019489 RX Vref Scan: 0
6481 11:41:10.019564
6482 11:41:10.022710 RX Vref 0 -> 0, step: 1
6483 11:41:10.022812
6484 11:41:10.026069 RX Delay -410 -> 252, step: 16
6485 11:41:10.029216 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6486 11:41:10.036033 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6487 11:41:10.039019 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6488 11:41:10.042779 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6489 11:41:10.045935 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6490 11:41:10.052621 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6491 11:41:10.055846 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6492 11:41:10.058980 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6493 11:41:10.062740 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6494 11:41:10.065707 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6495 11:41:10.072334 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6496 11:41:10.075659 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6497 11:41:10.078833 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6498 11:41:10.085750 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6499 11:41:10.089184 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6500 11:41:10.092549 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6501 11:41:10.092639 ==
6502 11:41:10.095567 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 11:41:10.099507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 11:41:10.099585 ==
6505 11:41:10.102217 DQS Delay:
6506 11:41:10.102294 DQS0 = 19, DQS1 = 27
6507 11:41:10.106119 DQM Delay:
6508 11:41:10.106190 DQM0 = 5, DQM1 = 6
6509 11:41:10.106252 DQ Delay:
6510 11:41:10.109442 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6511 11:41:10.112620 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6512 11:41:10.115922 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6513 11:41:10.119236 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6514 11:41:10.119316
6515 11:41:10.119381
6516 11:41:10.119440 ==
6517 11:41:10.122591 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 11:41:10.125839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 11:41:10.129210 ==
6520 11:41:10.129288
6521 11:41:10.129352
6522 11:41:10.129410 TX Vref Scan disable
6523 11:41:10.132539 == TX Byte 0 ==
6524 11:41:10.135627 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6525 11:41:10.138684 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6526 11:41:10.142534 == TX Byte 1 ==
6527 11:41:10.145741 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6528 11:41:10.149042 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6529 11:41:10.149117 ==
6530 11:41:10.152261 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 11:41:10.155673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 11:41:10.158682 ==
6533 11:41:10.158760
6534 11:41:10.158832
6535 11:41:10.158894 TX Vref Scan disable
6536 11:41:10.162505 == TX Byte 0 ==
6537 11:41:10.165657 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6538 11:41:10.168572 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6539 11:41:10.172563 == TX Byte 1 ==
6540 11:41:10.175423 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6541 11:41:10.178679 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6542 11:41:10.178754
6543 11:41:10.182040 [DATLAT]
6544 11:41:10.182113 Freq=400, CH0 RK1
6545 11:41:10.182190
6546 11:41:10.185300 DATLAT Default: 0xe
6547 11:41:10.185372 0, 0xFFFF, sum = 0
6548 11:41:10.188976 1, 0xFFFF, sum = 0
6549 11:41:10.189066 2, 0xFFFF, sum = 0
6550 11:41:10.192342 3, 0xFFFF, sum = 0
6551 11:41:10.192420 4, 0xFFFF, sum = 0
6552 11:41:10.195614 5, 0xFFFF, sum = 0
6553 11:41:10.195702 6, 0xFFFF, sum = 0
6554 11:41:10.198836 7, 0xFFFF, sum = 0
6555 11:41:10.198922 8, 0xFFFF, sum = 0
6556 11:41:10.202504 9, 0xFFFF, sum = 0
6557 11:41:10.202602 10, 0xFFFF, sum = 0
6558 11:41:10.205718 11, 0xFFFF, sum = 0
6559 11:41:10.205802 12, 0xFFFF, sum = 0
6560 11:41:10.209022 13, 0x0, sum = 1
6561 11:41:10.209105 14, 0x0, sum = 2
6562 11:41:10.212489 15, 0x0, sum = 3
6563 11:41:10.212599 16, 0x0, sum = 4
6564 11:41:10.215891 best_step = 14
6565 11:41:10.215973
6566 11:41:10.216038 ==
6567 11:41:10.219016 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 11:41:10.222404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 11:41:10.222512 ==
6570 11:41:10.225575 RX Vref Scan: 0
6571 11:41:10.225657
6572 11:41:10.225722 RX Vref 0 -> 0, step: 1
6573 11:41:10.225783
6574 11:41:10.228634 RX Delay -295 -> 252, step: 8
6575 11:41:10.236709 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6576 11:41:10.239918 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6577 11:41:10.243064 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6578 11:41:10.246392 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6579 11:41:10.253138 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6580 11:41:10.256362 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6581 11:41:10.259490 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6582 11:41:10.263217 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6583 11:41:10.269899 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6584 11:41:10.273072 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6585 11:41:10.276188 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6586 11:41:10.279404 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6587 11:41:10.286176 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6588 11:41:10.289396 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6589 11:41:10.292716 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6590 11:41:10.299591 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6591 11:41:10.299699 ==
6592 11:41:10.302873 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 11:41:10.306069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 11:41:10.306171 ==
6595 11:41:10.306263 DQS Delay:
6596 11:41:10.309859 DQS0 = 24, DQS1 = 32
6597 11:41:10.309961 DQM Delay:
6598 11:41:10.312988 DQM0 = 9, DQM1 = 10
6599 11:41:10.313088 DQ Delay:
6600 11:41:10.316385 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6601 11:41:10.319704 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6602 11:41:10.322825 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =0
6603 11:41:10.326087 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6604 11:41:10.326161
6605 11:41:10.326245
6606 11:41:10.332540 [DQSOSCAuto] RK1, (LSB)MR18= 0xb756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6607 11:41:10.335852 CH0 RK1: MR19=C0C, MR18=B756
6608 11:41:10.343072 CH0_RK1: MR19=0xC0C, MR18=0xB756, DQSOSC=387, MR23=63, INC=394, DEC=262
6609 11:41:10.346327 [RxdqsGatingPostProcess] freq 400
6610 11:41:10.349450 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6611 11:41:10.352532 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 11:41:10.355951 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 11:41:10.359726 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 11:41:10.363101 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 11:41:10.366186 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 11:41:10.369606 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 11:41:10.372698 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 11:41:10.376247 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 11:41:10.379461 Pre-setting of DQS Precalculation
6620 11:41:10.382422 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6621 11:41:10.386163 ==
6622 11:41:10.386272 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 11:41:10.393068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 11:41:10.393153 ==
6625 11:41:10.396236 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 11:41:10.402606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6627 11:41:10.405853 [CA 0] Center 36 (8~64) winsize 57
6628 11:41:10.409062 [CA 1] Center 36 (8~64) winsize 57
6629 11:41:10.412271 [CA 2] Center 36 (8~64) winsize 57
6630 11:41:10.416058 [CA 3] Center 36 (8~64) winsize 57
6631 11:41:10.419633 [CA 4] Center 36 (8~64) winsize 57
6632 11:41:10.422665 [CA 5] Center 36 (8~64) winsize 57
6633 11:41:10.422750
6634 11:41:10.425911 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6635 11:41:10.425999
6636 11:41:10.429386 [CATrainingPosCal] consider 1 rank data
6637 11:41:10.432447 u2DelayCellTimex100 = 270/100 ps
6638 11:41:10.435685 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:41:10.438915 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:41:10.442310 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:41:10.445540 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:41:10.452227 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 11:41:10.455371 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 11:41:10.455453
6645 11:41:10.459033 CA PerBit enable=1, Macro0, CA PI delay=36
6646 11:41:10.459119
6647 11:41:10.462137 [CBTSetCACLKResult] CA Dly = 36
6648 11:41:10.462221 CS Dly: 1 (0~32)
6649 11:41:10.462288 ==
6650 11:41:10.465535 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 11:41:10.468729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 11:41:10.471870 ==
6653 11:41:10.475174 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 11:41:10.481881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6655 11:41:10.485837 [CA 0] Center 36 (8~64) winsize 57
6656 11:41:10.488687 [CA 1] Center 36 (8~64) winsize 57
6657 11:41:10.492460 [CA 2] Center 36 (8~64) winsize 57
6658 11:41:10.495412 [CA 3] Center 36 (8~64) winsize 57
6659 11:41:10.499104 [CA 4] Center 36 (8~64) winsize 57
6660 11:41:10.502198 [CA 5] Center 36 (8~64) winsize 57
6661 11:41:10.502281
6662 11:41:10.505523 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6663 11:41:10.505648
6664 11:41:10.508831 [CATrainingPosCal] consider 2 rank data
6665 11:41:10.512309 u2DelayCellTimex100 = 270/100 ps
6666 11:41:10.515490 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:41:10.518616 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 11:41:10.522038 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 11:41:10.525693 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 11:41:10.528351 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 11:41:10.531709 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 11:41:10.531797
6673 11:41:10.538864 CA PerBit enable=1, Macro0, CA PI delay=36
6674 11:41:10.538999
6675 11:41:10.539184 [CBTSetCACLKResult] CA Dly = 36
6676 11:41:10.542238 CS Dly: 1 (0~32)
6677 11:41:10.542361
6678 11:41:10.545567 ----->DramcWriteLeveling(PI) begin...
6679 11:41:10.545650 ==
6680 11:41:10.548773 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 11:41:10.552101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 11:41:10.552183 ==
6683 11:41:10.555296 Write leveling (Byte 0): 40 => 8
6684 11:41:10.558630 Write leveling (Byte 1): 40 => 8
6685 11:41:10.561874 DramcWriteLeveling(PI) end<-----
6686 11:41:10.561990
6687 11:41:10.562054 ==
6688 11:41:10.565436 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 11:41:10.568533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 11:41:10.568641 ==
6691 11:41:10.571807 [Gating] SW mode calibration
6692 11:41:10.579054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6693 11:41:10.585381 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6694 11:41:10.588524 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6695 11:41:10.595255 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 11:41:10.598913 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 11:41:10.602037 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 11:41:10.605633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 11:41:10.611670 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 11:41:10.615450 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 11:41:10.618521 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 11:41:10.625379 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 11:41:10.628695 Total UI for P1: 0, mck2ui 16
6704 11:41:10.631997 best dqsien dly found for B0: ( 0, 14, 24)
6705 11:41:10.635201 Total UI for P1: 0, mck2ui 16
6706 11:41:10.638520 best dqsien dly found for B1: ( 0, 14, 24)
6707 11:41:10.641730 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6708 11:41:10.645065 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6709 11:41:10.645164
6710 11:41:10.648310 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6711 11:41:10.651756 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 11:41:10.655031 [Gating] SW calibration Done
6713 11:41:10.655139 ==
6714 11:41:10.658289 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 11:41:10.661608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 11:41:10.661691 ==
6717 11:41:10.665476 RX Vref Scan: 0
6718 11:41:10.665559
6719 11:41:10.668508 RX Vref 0 -> 0, step: 1
6720 11:41:10.668590
6721 11:41:10.668654 RX Delay -410 -> 252, step: 16
6722 11:41:10.674882 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6723 11:41:10.678123 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6724 11:41:10.681474 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6725 11:41:10.684846 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6726 11:41:10.691966 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6727 11:41:10.695300 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6728 11:41:10.698507 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6729 11:41:10.701649 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6730 11:41:10.708314 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6731 11:41:10.711395 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6732 11:41:10.715095 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6733 11:41:10.718384 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6734 11:41:10.724785 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6735 11:41:10.727884 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6736 11:41:10.731633 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6737 11:41:10.737670 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6738 11:41:10.737755 ==
6739 11:41:10.741189 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 11:41:10.744416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 11:41:10.744499 ==
6742 11:41:10.744565 DQS Delay:
6743 11:41:10.748112 DQS0 = 27, DQS1 = 35
6744 11:41:10.748194 DQM Delay:
6745 11:41:10.751484 DQM0 = 10, DQM1 = 13
6746 11:41:10.751566 DQ Delay:
6747 11:41:10.754816 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6748 11:41:10.758321 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6749 11:41:10.761524 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6750 11:41:10.764822 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6751 11:41:10.764910
6752 11:41:10.764980
6753 11:41:10.765045 ==
6754 11:41:10.768159 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 11:41:10.771431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 11:41:10.771527 ==
6757 11:41:10.771602
6758 11:41:10.771672
6759 11:41:10.774527 TX Vref Scan disable
6760 11:41:10.774621 == TX Byte 0 ==
6761 11:41:10.781520 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 11:41:10.784714 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 11:41:10.784879 == TX Byte 1 ==
6764 11:41:10.791210 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 11:41:10.794414 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 11:41:10.794501 ==
6767 11:41:10.797684 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 11:41:10.801031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 11:41:10.801114 ==
6770 11:41:10.801179
6771 11:41:10.801237
6772 11:41:10.804227 TX Vref Scan disable
6773 11:41:10.804308 == TX Byte 0 ==
6774 11:41:10.811295 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 11:41:10.814353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 11:41:10.814439 == TX Byte 1 ==
6777 11:41:10.821173 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 11:41:10.824469 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 11:41:10.824552
6780 11:41:10.824617 [DATLAT]
6781 11:41:10.827851 Freq=400, CH1 RK0
6782 11:41:10.827933
6783 11:41:10.827998 DATLAT Default: 0xf
6784 11:41:10.831102 0, 0xFFFF, sum = 0
6785 11:41:10.831186 1, 0xFFFF, sum = 0
6786 11:41:10.834208 2, 0xFFFF, sum = 0
6787 11:41:10.834292 3, 0xFFFF, sum = 0
6788 11:41:10.837242 4, 0xFFFF, sum = 0
6789 11:41:10.837326 5, 0xFFFF, sum = 0
6790 11:41:10.841039 6, 0xFFFF, sum = 0
6791 11:41:10.843874 7, 0xFFFF, sum = 0
6792 11:41:10.843957 8, 0xFFFF, sum = 0
6793 11:41:10.847742 9, 0xFFFF, sum = 0
6794 11:41:10.847826 10, 0xFFFF, sum = 0
6795 11:41:10.850908 11, 0xFFFF, sum = 0
6796 11:41:10.850990 12, 0xFFFF, sum = 0
6797 11:41:10.854206 13, 0x0, sum = 1
6798 11:41:10.854304 14, 0x0, sum = 2
6799 11:41:10.857489 15, 0x0, sum = 3
6800 11:41:10.857572 16, 0x0, sum = 4
6801 11:41:10.857639 best_step = 14
6802 11:41:10.860723
6803 11:41:10.860849 ==
6804 11:41:10.864153 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 11:41:10.867437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 11:41:10.867520 ==
6807 11:41:10.867586 RX Vref Scan: 1
6808 11:41:10.867646
6809 11:41:10.870722 RX Vref 0 -> 0, step: 1
6810 11:41:10.870804
6811 11:41:10.874062 RX Delay -311 -> 252, step: 8
6812 11:41:10.874151
6813 11:41:10.877457 Set Vref, RX VrefLevel [Byte0]: 55
6814 11:41:10.880449 [Byte1]: 52
6815 11:41:10.884148
6816 11:41:10.884229 Final RX Vref Byte 0 = 55 to rank0
6817 11:41:10.887810 Final RX Vref Byte 1 = 52 to rank0
6818 11:41:10.890801 Final RX Vref Byte 0 = 55 to rank1
6819 11:41:10.894180 Final RX Vref Byte 1 = 52 to rank1==
6820 11:41:10.897971 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 11:41:10.904460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 11:41:10.904550 ==
6823 11:41:10.904617 DQS Delay:
6824 11:41:10.904678 DQS0 = 28, DQS1 = 32
6825 11:41:10.907780 DQM Delay:
6826 11:41:10.907862 DQM0 = 10, DQM1 = 10
6827 11:41:10.911080 DQ Delay:
6828 11:41:10.914149 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6829 11:41:10.914232 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6830 11:41:10.917612 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6831 11:41:10.920680 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6832 11:41:10.920791
6833 11:41:10.920916
6834 11:41:10.931057 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps
6835 11:41:10.934233 CH1 RK0: MR19=C0C, MR18=90C8
6836 11:41:10.941149 CH1_RK0: MR19=0xC0C, MR18=0x90C8, DQSOSC=385, MR23=63, INC=398, DEC=265
6837 11:41:10.941234 ==
6838 11:41:10.944101 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 11:41:10.947327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 11:41:10.947411 ==
6841 11:41:10.951114 [Gating] SW mode calibration
6842 11:41:10.957791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6843 11:41:10.961044 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6844 11:41:10.967630 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6845 11:41:10.970881 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 11:41:10.974347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 11:41:10.980778 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 11:41:10.984229 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 11:41:10.987484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 11:41:10.994224 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 11:41:10.997252 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 11:41:11.000695 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 11:41:11.004134 Total UI for P1: 0, mck2ui 16
6854 11:41:11.007418 best dqsien dly found for B0: ( 0, 14, 24)
6855 11:41:11.010524 Total UI for P1: 0, mck2ui 16
6856 11:41:11.013769 best dqsien dly found for B1: ( 0, 14, 24)
6857 11:41:11.017072 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6858 11:41:11.021030 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6859 11:41:11.024186
6860 11:41:11.027395 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6861 11:41:11.030584 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 11:41:11.033758 [Gating] SW calibration Done
6863 11:41:11.033842 ==
6864 11:41:11.036885 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 11:41:11.040778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 11:41:11.040887 ==
6867 11:41:11.040972 RX Vref Scan: 0
6868 11:41:11.043346
6869 11:41:11.043516 RX Vref 0 -> 0, step: 1
6870 11:41:11.043597
6871 11:41:11.046939 RX Delay -410 -> 252, step: 16
6872 11:41:11.049977 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6873 11:41:11.057149 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6874 11:41:11.060268 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6875 11:41:11.063793 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6876 11:41:11.066586 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6877 11:41:11.073219 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6878 11:41:11.076476 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6879 11:41:11.079801 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6880 11:41:11.083092 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6881 11:41:11.090361 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6882 11:41:11.093541 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6883 11:41:11.096746 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6884 11:41:11.099770 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6885 11:41:11.106680 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6886 11:41:11.109763 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6887 11:41:11.113375 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6888 11:41:11.113464 ==
6889 11:41:11.116790 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 11:41:11.120010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 11:41:11.123200 ==
6892 11:41:11.123306 DQS Delay:
6893 11:41:11.123375 DQS0 = 35, DQS1 = 35
6894 11:41:11.126685 DQM Delay:
6895 11:41:11.126769 DQM0 = 18, DQM1 = 14
6896 11:41:11.129882 DQ Delay:
6897 11:41:11.133021 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6898 11:41:11.133106 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6899 11:41:11.137118 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6900 11:41:11.139772 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6901 11:41:11.139859
6902 11:41:11.139933
6903 11:41:11.143561 ==
6904 11:41:11.146689 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 11:41:11.150376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 11:41:11.150462 ==
6907 11:41:11.150529
6908 11:41:11.150592
6909 11:41:11.153404 TX Vref Scan disable
6910 11:41:11.153489 == TX Byte 0 ==
6911 11:41:11.156547 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6912 11:41:11.163672 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6913 11:41:11.163786 == TX Byte 1 ==
6914 11:41:11.166865 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6915 11:41:11.170040 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6916 11:41:11.173732 ==
6917 11:41:11.176445 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 11:41:11.179730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 11:41:11.179833 ==
6920 11:41:11.179903
6921 11:41:11.179965
6922 11:41:11.183717 TX Vref Scan disable
6923 11:41:11.183791 == TX Byte 0 ==
6924 11:41:11.186412 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6925 11:41:11.193675 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6926 11:41:11.193754 == TX Byte 1 ==
6927 11:41:11.196357 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6928 11:41:11.203433 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6929 11:41:11.203517
6930 11:41:11.203583 [DATLAT]
6931 11:41:11.203647 Freq=400, CH1 RK1
6932 11:41:11.203706
6933 11:41:11.206625 DATLAT Default: 0xe
6934 11:41:11.206708 0, 0xFFFF, sum = 0
6935 11:41:11.209849 1, 0xFFFF, sum = 0
6936 11:41:11.213359 2, 0xFFFF, sum = 0
6937 11:41:11.213443 3, 0xFFFF, sum = 0
6938 11:41:11.216943 4, 0xFFFF, sum = 0
6939 11:41:11.217028 5, 0xFFFF, sum = 0
6940 11:41:11.219973 6, 0xFFFF, sum = 0
6941 11:41:11.220074 7, 0xFFFF, sum = 0
6942 11:41:11.222988 8, 0xFFFF, sum = 0
6943 11:41:11.223074 9, 0xFFFF, sum = 0
6944 11:41:11.226673 10, 0xFFFF, sum = 0
6945 11:41:11.226758 11, 0xFFFF, sum = 0
6946 11:41:11.230054 12, 0xFFFF, sum = 0
6947 11:41:11.230177 13, 0x0, sum = 1
6948 11:41:11.233360 14, 0x0, sum = 2
6949 11:41:11.233447 15, 0x0, sum = 3
6950 11:41:11.236531 16, 0x0, sum = 4
6951 11:41:11.236617 best_step = 14
6952 11:41:11.236684
6953 11:41:11.236745 ==
6954 11:41:11.239728 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 11:41:11.242939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 11:41:11.246482 ==
6957 11:41:11.246557 RX Vref Scan: 0
6958 11:41:11.246620
6959 11:41:11.249608 RX Vref 0 -> 0, step: 1
6960 11:41:11.249691
6961 11:41:11.253318 RX Delay -311 -> 252, step: 8
6962 11:41:11.256541 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6963 11:41:11.262893 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6964 11:41:11.266150 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6965 11:41:11.269954 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6966 11:41:11.273176 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6967 11:41:11.279499 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6968 11:41:11.282732 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6969 11:41:11.286125 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6970 11:41:11.289521 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6971 11:41:11.296149 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6972 11:41:11.299519 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6973 11:41:11.302752 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6974 11:41:11.305890 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6975 11:41:11.313108 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6976 11:41:11.316333 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6977 11:41:11.319721 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6978 11:41:11.319805 ==
6979 11:41:11.322909 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 11:41:11.329475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 11:41:11.329560 ==
6982 11:41:11.329627 DQS Delay:
6983 11:41:11.332658 DQS0 = 28, DQS1 = 36
6984 11:41:11.332742 DQM Delay:
6985 11:41:11.332832 DQM0 = 11, DQM1 = 15
6986 11:41:11.335866 DQ Delay:
6987 11:41:11.339109 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6988 11:41:11.339192 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6989 11:41:11.342370 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6990 11:41:11.345618 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6991 11:41:11.345724
6992 11:41:11.348913
6993 11:41:11.355937 [DQSOSCAuto] RK1, (LSB)MR18= 0xc556, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6994 11:41:11.358974 CH1 RK1: MR19=C0C, MR18=C556
6995 11:41:11.365902 CH1_RK1: MR19=0xC0C, MR18=0xC556, DQSOSC=385, MR23=63, INC=398, DEC=265
6996 11:41:11.369128 [RxdqsGatingPostProcess] freq 400
6997 11:41:11.372225 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6998 11:41:11.375925 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 11:41:11.379083 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 11:41:11.382484 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 11:41:11.386191 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 11:41:11.389356 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 11:41:11.392680 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 11:41:11.395979 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 11:41:11.399339 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 11:41:11.402698 Pre-setting of DQS Precalculation
7007 11:41:11.406012 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7008 11:41:11.412611 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7009 11:41:11.419053 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7010 11:41:11.422382
7011 11:41:11.422466
7012 11:41:11.422532 [Calibration Summary] 800 Mbps
7013 11:41:11.425709 CH 0, Rank 0
7014 11:41:11.425793 SW Impedance : PASS
7015 11:41:11.429391 DUTY Scan : NO K
7016 11:41:11.432450 ZQ Calibration : PASS
7017 11:41:11.432534 Jitter Meter : NO K
7018 11:41:11.436113 CBT Training : PASS
7019 11:41:11.439033 Write leveling : PASS
7020 11:41:11.439117 RX DQS gating : PASS
7021 11:41:11.442247 RX DQ/DQS(RDDQC) : PASS
7022 11:41:11.445674 TX DQ/DQS : PASS
7023 11:41:11.445759 RX DATLAT : PASS
7024 11:41:11.448998 RX DQ/DQS(Engine): PASS
7025 11:41:11.452674 TX OE : NO K
7026 11:41:11.452758 All Pass.
7027 11:41:11.452851
7028 11:41:11.452928 CH 0, Rank 1
7029 11:41:11.455493 SW Impedance : PASS
7030 11:41:11.458716 DUTY Scan : NO K
7031 11:41:11.458802 ZQ Calibration : PASS
7032 11:41:11.462688 Jitter Meter : NO K
7033 11:41:11.462773 CBT Training : PASS
7034 11:41:11.465568 Write leveling : NO K
7035 11:41:11.469323 RX DQS gating : PASS
7036 11:41:11.469428 RX DQ/DQS(RDDQC) : PASS
7037 11:41:11.472470 TX DQ/DQS : PASS
7038 11:41:11.476055 RX DATLAT : PASS
7039 11:41:11.476137 RX DQ/DQS(Engine): PASS
7040 11:41:11.479131 TX OE : NO K
7041 11:41:11.479215 All Pass.
7042 11:41:11.479282
7043 11:41:11.482218 CH 1, Rank 0
7044 11:41:11.482302 SW Impedance : PASS
7045 11:41:11.486036 DUTY Scan : NO K
7046 11:41:11.489319 ZQ Calibration : PASS
7047 11:41:11.489403 Jitter Meter : NO K
7048 11:41:11.492407 CBT Training : PASS
7049 11:41:11.495590 Write leveling : PASS
7050 11:41:11.495674 RX DQS gating : PASS
7051 11:41:11.499024 RX DQ/DQS(RDDQC) : PASS
7052 11:41:11.502400 TX DQ/DQS : PASS
7053 11:41:11.502485 RX DATLAT : PASS
7054 11:41:11.505640 RX DQ/DQS(Engine): PASS
7055 11:41:11.508836 TX OE : NO K
7056 11:41:11.508933 All Pass.
7057 11:41:11.509000
7058 11:41:11.509092 CH 1, Rank 1
7059 11:41:11.512159 SW Impedance : PASS
7060 11:41:11.515716 DUTY Scan : NO K
7061 11:41:11.515821 ZQ Calibration : PASS
7062 11:41:11.518513 Jitter Meter : NO K
7063 11:41:11.518596 CBT Training : PASS
7064 11:41:11.522745 Write leveling : NO K
7065 11:41:11.525718 RX DQS gating : PASS
7066 11:41:11.525811 RX DQ/DQS(RDDQC) : PASS
7067 11:41:11.529159 TX DQ/DQS : PASS
7068 11:41:11.532279 RX DATLAT : PASS
7069 11:41:11.532374 RX DQ/DQS(Engine): PASS
7070 11:41:11.535386 TX OE : NO K
7071 11:41:11.535503 All Pass.
7072 11:41:11.535575
7073 11:41:11.538763 DramC Write-DBI off
7074 11:41:11.542123 PER_BANK_REFRESH: Hybrid Mode
7075 11:41:11.542215 TX_TRACKING: ON
7076 11:41:11.551981 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7077 11:41:11.555575 [FAST_K] Save calibration result to emmc
7078 11:41:11.558588 dramc_set_vcore_voltage set vcore to 725000
7079 11:41:11.561770 Read voltage for 1600, 0
7080 11:41:11.561864 Vio18 = 0
7081 11:41:11.561930 Vcore = 725000
7082 11:41:11.565191 Vdram = 0
7083 11:41:11.565280 Vddq = 0
7084 11:41:11.565351 Vmddr = 0
7085 11:41:11.572355 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7086 11:41:11.575426 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7087 11:41:11.578510 MEM_TYPE=3, freq_sel=13
7088 11:41:11.581955 sv_algorithm_assistance_LP4_3733
7089 11:41:11.585507 ============ PULL DRAM RESETB DOWN ============
7090 11:41:11.588511 ========== PULL DRAM RESETB DOWN end =========
7091 11:41:11.595096 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7092 11:41:11.598763 ===================================
7093 11:41:11.602038 LPDDR4 DRAM CONFIGURATION
7094 11:41:11.605400 ===================================
7095 11:41:11.605577 EX_ROW_EN[0] = 0x0
7096 11:41:11.608749 EX_ROW_EN[1] = 0x0
7097 11:41:11.608977 LP4Y_EN = 0x0
7098 11:41:11.612096 WORK_FSP = 0x1
7099 11:41:11.612344 WL = 0x5
7100 11:41:11.615219 RL = 0x5
7101 11:41:11.615464 BL = 0x2
7102 11:41:11.618517 RPST = 0x0
7103 11:41:11.618823 RD_PRE = 0x0
7104 11:41:11.622546 WR_PRE = 0x1
7105 11:41:11.622962 WR_PST = 0x1
7106 11:41:11.626037 DBI_WR = 0x0
7107 11:41:11.626468 DBI_RD = 0x0
7108 11:41:11.629017 OTF = 0x1
7109 11:41:11.632044 ===================================
7110 11:41:11.635537 ===================================
7111 11:41:11.635972 ANA top config
7112 11:41:11.638723 ===================================
7113 11:41:11.641990 DLL_ASYNC_EN = 0
7114 11:41:11.645300 ALL_SLAVE_EN = 0
7115 11:41:11.648471 NEW_RANK_MODE = 1
7116 11:41:11.648945 DLL_IDLE_MODE = 1
7117 11:41:11.652492 LP45_APHY_COMB_EN = 1
7118 11:41:11.655733 TX_ODT_DIS = 0
7119 11:41:11.658876 NEW_8X_MODE = 1
7120 11:41:11.661841 ===================================
7121 11:41:11.665436 ===================================
7122 11:41:11.668920 data_rate = 3200
7123 11:41:11.669401 CKR = 1
7124 11:41:11.672205 DQ_P2S_RATIO = 8
7125 11:41:11.675591 ===================================
7126 11:41:11.678738 CA_P2S_RATIO = 8
7127 11:41:11.681833 DQ_CA_OPEN = 0
7128 11:41:11.685224 DQ_SEMI_OPEN = 0
7129 11:41:11.688167 CA_SEMI_OPEN = 0
7130 11:41:11.688624 CA_FULL_RATE = 0
7131 11:41:11.691849 DQ_CKDIV4_EN = 0
7132 11:41:11.695134 CA_CKDIV4_EN = 0
7133 11:41:11.698124 CA_PREDIV_EN = 0
7134 11:41:11.701800 PH8_DLY = 12
7135 11:41:11.704773 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7136 11:41:11.705479 DQ_AAMCK_DIV = 4
7137 11:41:11.708512 CA_AAMCK_DIV = 4
7138 11:41:11.711707 CA_ADMCK_DIV = 4
7139 11:41:11.714961 DQ_TRACK_CA_EN = 0
7140 11:41:11.718292 CA_PICK = 1600
7141 11:41:11.721726 CA_MCKIO = 1600
7142 11:41:11.724778 MCKIO_SEMI = 0
7143 11:41:11.727997 PLL_FREQ = 3068
7144 11:41:11.728443 DQ_UI_PI_RATIO = 32
7145 11:41:11.731325 CA_UI_PI_RATIO = 0
7146 11:41:11.735260 ===================================
7147 11:41:11.738068 ===================================
7148 11:41:11.741310 memory_type:LPDDR4
7149 11:41:11.744724 GP_NUM : 10
7150 11:41:11.745207 SRAM_EN : 1
7151 11:41:11.748385 MD32_EN : 0
7152 11:41:11.751768 ===================================
7153 11:41:11.752193 [ANA_INIT] >>>>>>>>>>>>>>
7154 11:41:11.755025 <<<<<< [CONFIGURE PHASE]: ANA_TX
7155 11:41:11.758409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7156 11:41:11.761752 ===================================
7157 11:41:11.764851 data_rate = 3200,PCW = 0X7600
7158 11:41:11.767879 ===================================
7159 11:41:11.771633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7160 11:41:11.778117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7161 11:41:11.781628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 11:41:11.787807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7163 11:41:11.790894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7164 11:41:11.794704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7165 11:41:11.797885 [ANA_INIT] flow start
7166 11:41:11.797968 [ANA_INIT] PLL >>>>>>>>
7167 11:41:11.801424 [ANA_INIT] PLL <<<<<<<<
7168 11:41:11.804494 [ANA_INIT] MIDPI >>>>>>>>
7169 11:41:11.804576 [ANA_INIT] MIDPI <<<<<<<<
7170 11:41:11.807673 [ANA_INIT] DLL >>>>>>>>
7171 11:41:11.810897 [ANA_INIT] DLL <<<<<<<<
7172 11:41:11.810979 [ANA_INIT] flow end
7173 11:41:11.817892 ============ LP4 DIFF to SE enter ============
7174 11:41:11.821232 ============ LP4 DIFF to SE exit ============
7175 11:41:11.821315 [ANA_INIT] <<<<<<<<<<<<<
7176 11:41:11.824637 [Flow] Enable top DCM control >>>>>
7177 11:41:11.827721 [Flow] Enable top DCM control <<<<<
7178 11:41:11.830903 Enable DLL master slave shuffle
7179 11:41:11.837820 ==============================================================
7180 11:41:11.840754 Gating Mode config
7181 11:41:11.844133 ==============================================================
7182 11:41:11.847527 Config description:
7183 11:41:11.858006 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7184 11:41:11.864524 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7185 11:41:11.867822 SELPH_MODE 0: By rank 1: By Phase
7186 11:41:11.874419 ==============================================================
7187 11:41:11.877579 GAT_TRACK_EN = 1
7188 11:41:11.881298 RX_GATING_MODE = 2
7189 11:41:11.881381 RX_GATING_TRACK_MODE = 2
7190 11:41:11.884472 SELPH_MODE = 1
7191 11:41:11.887573 PICG_EARLY_EN = 1
7192 11:41:11.891441 VALID_LAT_VALUE = 1
7193 11:41:11.897716 ==============================================================
7194 11:41:11.900795 Enter into Gating configuration >>>>
7195 11:41:11.904052 Exit from Gating configuration <<<<
7196 11:41:11.907640 Enter into DVFS_PRE_config >>>>>
7197 11:41:11.917502 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7198 11:41:11.920645 Exit from DVFS_PRE_config <<<<<
7199 11:41:11.924348 Enter into PICG configuration >>>>
7200 11:41:11.927587 Exit from PICG configuration <<<<
7201 11:41:11.930911 [RX_INPUT] configuration >>>>>
7202 11:41:11.934062 [RX_INPUT] configuration <<<<<
7203 11:41:11.937237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7204 11:41:11.944376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7205 11:41:11.950777 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 11:41:11.957769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 11:41:11.961178 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 11:41:11.967684 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 11:41:11.971131 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7210 11:41:11.977534 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7211 11:41:11.980741 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7212 11:41:11.983895 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7213 11:41:11.987248 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7214 11:41:11.993920 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 11:41:11.997669 ===================================
7216 11:41:11.997755 LPDDR4 DRAM CONFIGURATION
7217 11:41:12.000729 ===================================
7218 11:41:12.004127 EX_ROW_EN[0] = 0x0
7219 11:41:12.007462 EX_ROW_EN[1] = 0x0
7220 11:41:12.007545 LP4Y_EN = 0x0
7221 11:41:12.010762 WORK_FSP = 0x1
7222 11:41:12.010841 WL = 0x5
7223 11:41:12.013825 RL = 0x5
7224 11:41:12.013901 BL = 0x2
7225 11:41:12.017343 RPST = 0x0
7226 11:41:12.017420 RD_PRE = 0x0
7227 11:41:12.020344 WR_PRE = 0x1
7228 11:41:12.020421 WR_PST = 0x1
7229 11:41:12.024003 DBI_WR = 0x0
7230 11:41:12.024093 DBI_RD = 0x0
7231 11:41:12.027087 OTF = 0x1
7232 11:41:12.030657 ===================================
7233 11:41:12.033682 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7234 11:41:12.037382 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7235 11:41:12.044024 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7236 11:41:12.047441 ===================================
7237 11:41:12.047525 LPDDR4 DRAM CONFIGURATION
7238 11:41:12.050652 ===================================
7239 11:41:12.053793 EX_ROW_EN[0] = 0x10
7240 11:41:12.057110 EX_ROW_EN[1] = 0x0
7241 11:41:12.057193 LP4Y_EN = 0x0
7242 11:41:12.060283 WORK_FSP = 0x1
7243 11:41:12.060366 WL = 0x5
7244 11:41:12.064148 RL = 0x5
7245 11:41:12.064232 BL = 0x2
7246 11:41:12.067575 RPST = 0x0
7247 11:41:12.067657 RD_PRE = 0x0
7248 11:41:12.070311 WR_PRE = 0x1
7249 11:41:12.070394 WR_PST = 0x1
7250 11:41:12.074131 DBI_WR = 0x0
7251 11:41:12.074213 DBI_RD = 0x0
7252 11:41:12.077346 OTF = 0x1
7253 11:41:12.080517 ===================================
7254 11:41:12.087097 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7255 11:41:12.087180 ==
7256 11:41:12.090464 Dram Type= 6, Freq= 0, CH_0, rank 0
7257 11:41:12.093638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7258 11:41:12.093721 ==
7259 11:41:12.096763 [Duty_Offset_Calibration]
7260 11:41:12.096896 B0:2 B1:1 CA:1
7261 11:41:12.096963
7262 11:41:12.100494 [DutyScan_Calibration_Flow] k_type=0
7263 11:41:12.110797
7264 11:41:12.110880 ==CLK 0==
7265 11:41:12.114153 Final CLK duty delay cell = 0
7266 11:41:12.117465 [0] MAX Duty = 5156%(X100), DQS PI = 22
7267 11:41:12.120582 [0] MIN Duty = 4907%(X100), DQS PI = 0
7268 11:41:12.120669 [0] AVG Duty = 5031%(X100)
7269 11:41:12.123827
7270 11:41:12.123912 CH0 CLK Duty spec in!! Max-Min= 249%
7271 11:41:12.130469 [DutyScan_Calibration_Flow] ====Done====
7272 11:41:12.130555
7273 11:41:12.134000 [DutyScan_Calibration_Flow] k_type=1
7274 11:41:12.149827
7275 11:41:12.149916 ==DQS 0 ==
7276 11:41:12.153113 Final DQS duty delay cell = -4
7277 11:41:12.156395 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7278 11:41:12.159698 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7279 11:41:12.162922 [-4] AVG Duty = 4906%(X100)
7280 11:41:12.163006
7281 11:41:12.163073 ==DQS 1 ==
7282 11:41:12.166097 Final DQS duty delay cell = 0
7283 11:41:12.169348 [0] MAX Duty = 5187%(X100), DQS PI = 4
7284 11:41:12.172772 [0] MIN Duty = 5031%(X100), DQS PI = 52
7285 11:41:12.176717 [0] AVG Duty = 5109%(X100)
7286 11:41:12.176800
7287 11:41:12.179368 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7288 11:41:12.179451
7289 11:41:12.183148 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7290 11:41:12.186501 [DutyScan_Calibration_Flow] ====Done====
7291 11:41:12.186584
7292 11:41:12.189701 [DutyScan_Calibration_Flow] k_type=3
7293 11:41:12.206324
7294 11:41:12.206410 ==DQM 0 ==
7295 11:41:12.209852 Final DQM duty delay cell = 0
7296 11:41:12.212788 [0] MAX Duty = 5187%(X100), DQS PI = 26
7297 11:41:12.216443 [0] MIN Duty = 4907%(X100), DQS PI = 56
7298 11:41:12.219669 [0] AVG Duty = 5047%(X100)
7299 11:41:12.219752
7300 11:41:12.219818 ==DQM 1 ==
7301 11:41:12.222758 Final DQM duty delay cell = -4
7302 11:41:12.226057 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7303 11:41:12.229312 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7304 11:41:12.232506 [-4] AVG Duty = 4906%(X100)
7305 11:41:12.232591
7306 11:41:12.236242 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7307 11:41:12.236326
7308 11:41:12.239390 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7309 11:41:12.242487 [DutyScan_Calibration_Flow] ====Done====
7310 11:41:12.242570
7311 11:41:12.246322 [DutyScan_Calibration_Flow] k_type=2
7312 11:41:12.263806
7313 11:41:12.263902 ==DQ 0 ==
7314 11:41:12.267333 Final DQ duty delay cell = 0
7315 11:41:12.270469 [0] MAX Duty = 5062%(X100), DQS PI = 24
7316 11:41:12.273831 [0] MIN Duty = 4907%(X100), DQS PI = 0
7317 11:41:12.273916 [0] AVG Duty = 4984%(X100)
7318 11:41:12.273983
7319 11:41:12.277007 ==DQ 1 ==
7320 11:41:12.280352 Final DQ duty delay cell = 0
7321 11:41:12.283661 [0] MAX Duty = 5125%(X100), DQS PI = 6
7322 11:41:12.286921 [0] MIN Duty = 4907%(X100), DQS PI = 34
7323 11:41:12.287006 [0] AVG Duty = 5016%(X100)
7324 11:41:12.287072
7325 11:41:12.290201 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7326 11:41:12.290286
7327 11:41:12.294071 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7328 11:41:12.300696 [DutyScan_Calibration_Flow] ====Done====
7329 11:41:12.300780 ==
7330 11:41:12.304018 Dram Type= 6, Freq= 0, CH_1, rank 0
7331 11:41:12.307360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 11:41:12.307443 ==
7333 11:41:12.310563 [Duty_Offset_Calibration]
7334 11:41:12.310645 B0:1 B1:0 CA:0
7335 11:41:12.310709
7336 11:41:12.313718 [DutyScan_Calibration_Flow] k_type=0
7337 11:41:12.322980
7338 11:41:12.323062 ==CLK 0==
7339 11:41:12.326725 Final CLK duty delay cell = -4
7340 11:41:12.329459 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7341 11:41:12.332667 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7342 11:41:12.336038 [-4] AVG Duty = 4922%(X100)
7343 11:41:12.336119
7344 11:41:12.339792 CH1 CLK Duty spec in!! Max-Min= 156%
7345 11:41:12.342979 [DutyScan_Calibration_Flow] ====Done====
7346 11:41:12.343061
7347 11:41:12.346044 [DutyScan_Calibration_Flow] k_type=1
7348 11:41:12.363483
7349 11:41:12.363572 ==DQS 0 ==
7350 11:41:12.366607 Final DQS duty delay cell = 0
7351 11:41:12.369674 [0] MAX Duty = 5094%(X100), DQS PI = 12
7352 11:41:12.372955 [0] MIN Duty = 4844%(X100), DQS PI = 48
7353 11:41:12.376308 [0] AVG Duty = 4969%(X100)
7354 11:41:12.376390
7355 11:41:12.376454 ==DQS 1 ==
7356 11:41:12.379537 Final DQS duty delay cell = 0
7357 11:41:12.383474 [0] MAX Duty = 5249%(X100), DQS PI = 16
7358 11:41:12.386738 [0] MIN Duty = 4938%(X100), DQS PI = 8
7359 11:41:12.389986 [0] AVG Duty = 5093%(X100)
7360 11:41:12.390068
7361 11:41:12.393080 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7362 11:41:12.393161
7363 11:41:12.396485 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7364 11:41:12.399560 [DutyScan_Calibration_Flow] ====Done====
7365 11:41:12.399641
7366 11:41:12.402871 [DutyScan_Calibration_Flow] k_type=3
7367 11:41:12.420281
7368 11:41:12.420364 ==DQM 0 ==
7369 11:41:12.423497 Final DQM duty delay cell = 0
7370 11:41:12.426533 [0] MAX Duty = 5218%(X100), DQS PI = 14
7371 11:41:12.430162 [0] MIN Duty = 4969%(X100), DQS PI = 48
7372 11:41:12.433263 [0] AVG Duty = 5093%(X100)
7373 11:41:12.433346
7374 11:41:12.433411 ==DQM 1 ==
7375 11:41:12.436412 Final DQM duty delay cell = 0
7376 11:41:12.439741 [0] MAX Duty = 5093%(X100), DQS PI = 16
7377 11:41:12.443201 [0] MIN Duty = 4907%(X100), DQS PI = 50
7378 11:41:12.446528 [0] AVG Duty = 5000%(X100)
7379 11:41:12.446635
7380 11:41:12.449852 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7381 11:41:12.449946
7382 11:41:12.453600 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7383 11:41:12.456429 [DutyScan_Calibration_Flow] ====Done====
7384 11:41:12.456543
7385 11:41:12.459748 [DutyScan_Calibration_Flow] k_type=2
7386 11:41:12.476405
7387 11:41:12.476584 ==DQ 0 ==
7388 11:41:12.479615 Final DQ duty delay cell = -4
7389 11:41:12.482691 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7390 11:41:12.486163 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7391 11:41:12.489429 [-4] AVG Duty = 4953%(X100)
7392 11:41:12.489677
7393 11:41:12.489873 ==DQ 1 ==
7394 11:41:12.492795 Final DQ duty delay cell = 0
7395 11:41:12.496655 [0] MAX Duty = 5124%(X100), DQS PI = 16
7396 11:41:12.499909 [0] MIN Duty = 4938%(X100), DQS PI = 8
7397 11:41:12.503105 [0] AVG Duty = 5031%(X100)
7398 11:41:12.503540
7399 11:41:12.506242 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7400 11:41:12.506674
7401 11:41:12.509412 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7402 11:41:12.512700 [DutyScan_Calibration_Flow] ====Done====
7403 11:41:12.516032 nWR fixed to 30
7404 11:41:12.519885 [ModeRegInit_LP4] CH0 RK0
7405 11:41:12.520315 [ModeRegInit_LP4] CH0 RK1
7406 11:41:12.523022 [ModeRegInit_LP4] CH1 RK0
7407 11:41:12.526289 [ModeRegInit_LP4] CH1 RK1
7408 11:41:12.526722 match AC timing 5
7409 11:41:12.532537 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7410 11:41:12.536028 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7411 11:41:12.539102 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7412 11:41:12.546063 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7413 11:41:12.549357 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7414 11:41:12.549441 [MiockJmeterHQA]
7415 11:41:12.549507
7416 11:41:12.552067 [DramcMiockJmeter] u1RxGatingPI = 0
7417 11:41:12.555908 0 : 4255, 4029
7418 11:41:12.555993 4 : 4253, 4027
7419 11:41:12.559110 8 : 4363, 4138
7420 11:41:12.559196 12 : 4255, 4029
7421 11:41:12.562209 16 : 4253, 4027
7422 11:41:12.562294 20 : 4252, 4027
7423 11:41:12.562362 24 : 4252, 4027
7424 11:41:12.565855 28 : 4253, 4026
7425 11:41:12.565968 32 : 4252, 4027
7426 11:41:12.568767 36 : 4255, 4029
7427 11:41:12.568879 40 : 4252, 4027
7428 11:41:12.572107 44 : 4363, 4140
7429 11:41:12.572215 48 : 4361, 4137
7430 11:41:12.572316 52 : 4250, 4027
7431 11:41:12.575639 56 : 4252, 4029
7432 11:41:12.575750 60 : 4361, 4137
7433 11:41:12.578934 64 : 4250, 4027
7434 11:41:12.579045 68 : 4252, 4029
7435 11:41:12.582305 72 : 4250, 4027
7436 11:41:12.582395 76 : 4250, 4027
7437 11:41:12.585284 80 : 4250, 4027
7438 11:41:12.585374 84 : 4250, 4026
7439 11:41:12.585450 88 : 4361, 112
7440 11:41:12.588814 92 : 4253, 0
7441 11:41:12.588916 96 : 4253, 0
7442 11:41:12.592117 100 : 4252, 0
7443 11:41:12.592255 104 : 4250, 0
7444 11:41:12.592374 108 : 4253, 0
7445 11:41:12.595436 112 : 4250, 0
7446 11:41:12.595581 116 : 4250, 0
7447 11:41:12.598598 120 : 4253, 0
7448 11:41:12.598752 124 : 4360, 0
7449 11:41:12.598887 128 : 4360, 0
7450 11:41:12.601923 132 : 4250, 0
7451 11:41:12.602071 136 : 4250, 0
7452 11:41:12.602207 140 : 4363, 0
7453 11:41:12.605135 144 : 4250, 0
7454 11:41:12.605260 148 : 4250, 0
7455 11:41:12.609056 152 : 4250, 0
7456 11:41:12.609195 156 : 4255, 0
7457 11:41:12.609305 160 : 4250, 0
7458 11:41:12.612553 164 : 4250, 0
7459 11:41:12.613200 168 : 4250, 0
7460 11:41:12.615905 172 : 4250, 0
7461 11:41:12.616348 176 : 4360, 0
7462 11:41:12.616901 180 : 4252, 0
7463 11:41:12.619215 184 : 4361, 0
7464 11:41:12.619717 188 : 4254, 0
7465 11:41:12.622355 192 : 4361, 0
7466 11:41:12.622901 196 : 4360, 0
7467 11:41:12.623403 200 : 4250, 0
7468 11:41:12.625712 204 : 4252, 1301
7469 11:41:12.626142 208 : 4250, 3998
7470 11:41:12.628988 212 : 4250, 4027
7471 11:41:12.629419 216 : 4250, 4026
7472 11:41:12.632191 220 : 4250, 4026
7473 11:41:12.632621 224 : 4363, 4139
7474 11:41:12.635431 228 : 4250, 4027
7475 11:41:12.635998 232 : 4363, 4140
7476 11:41:12.638880 236 : 4361, 4137
7477 11:41:12.639310 240 : 4361, 4137
7478 11:41:12.639657 244 : 4250, 4026
7479 11:41:12.642329 248 : 4363, 4140
7480 11:41:12.642860 252 : 4250, 4026
7481 11:41:12.645398 256 : 4250, 4027
7482 11:41:12.645865 260 : 4250, 4027
7483 11:41:12.648585 264 : 4252, 4030
7484 11:41:12.649122 268 : 4250, 4026
7485 11:41:12.652048 272 : 4363, 4140
7486 11:41:12.652691 276 : 4250, 4027
7487 11:41:12.655869 280 : 4252, 4029
7488 11:41:12.656377 284 : 4250, 4026
7489 11:41:12.659080 288 : 4363, 4140
7490 11:41:12.659701 292 : 4361, 4137
7491 11:41:12.660183 296 : 4250, 4027
7492 11:41:12.662532 300 : 4363, 4140
7493 11:41:12.663153 304 : 4252, 4029
7494 11:41:12.665784 308 : 4250, 3933
7495 11:41:12.666422 312 : 4250, 2062
7496 11:41:12.666930
7497 11:41:12.668876 MIOCK jitter meter ch=0
7498 11:41:12.669568
7499 11:41:12.671943 1T = (312-88) = 224 dly cells
7500 11:41:12.678653 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7501 11:41:12.679293 ==
7502 11:41:12.682150 Dram Type= 6, Freq= 0, CH_0, rank 0
7503 11:41:12.685102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 11:41:12.685788 ==
7505 11:41:12.692207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 11:41:12.695463 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 11:41:12.698486 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 11:41:12.705337 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 11:41:12.714336 [CA 0] Center 42 (12~73) winsize 62
7510 11:41:12.717122 [CA 1] Center 42 (12~73) winsize 62
7511 11:41:12.721176 [CA 2] Center 38 (8~68) winsize 61
7512 11:41:12.724300 [CA 3] Center 37 (8~67) winsize 60
7513 11:41:12.727445 [CA 4] Center 36 (6~66) winsize 61
7514 11:41:12.730720 [CA 5] Center 35 (6~64) winsize 59
7515 11:41:12.731357
7516 11:41:12.734022 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7517 11:41:12.734626
7518 11:41:12.737212 [CATrainingPosCal] consider 1 rank data
7519 11:41:12.740315 u2DelayCellTimex100 = 290/100 ps
7520 11:41:12.746650 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7521 11:41:12.750437 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 11:41:12.753670 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7523 11:41:12.756909 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 11:41:12.759942 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7525 11:41:12.763157 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7526 11:41:12.763241
7527 11:41:12.766479 CA PerBit enable=1, Macro0, CA PI delay=35
7528 11:41:12.766563
7529 11:41:12.770443 [CBTSetCACLKResult] CA Dly = 35
7530 11:41:12.773698 CS Dly: 9 (0~40)
7531 11:41:12.776862 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 11:41:12.780175 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 11:41:12.780259 ==
7534 11:41:12.783673 Dram Type= 6, Freq= 0, CH_0, rank 1
7535 11:41:12.787399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 11:41:12.787484 ==
7537 11:41:12.793318 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 11:41:12.796557 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 11:41:12.803325 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 11:41:12.806976 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 11:41:12.816754 [CA 0] Center 42 (12~73) winsize 62
7542 11:41:12.820066 [CA 1] Center 42 (12~73) winsize 62
7543 11:41:12.823502 [CA 2] Center 37 (8~67) winsize 60
7544 11:41:12.826736 [CA 3] Center 37 (7~68) winsize 62
7545 11:41:12.830061 [CA 4] Center 35 (5~65) winsize 61
7546 11:41:12.833897 [CA 5] Center 35 (5~65) winsize 61
7547 11:41:12.833979
7548 11:41:12.837211 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7549 11:41:12.837293
7550 11:41:12.840335 [CATrainingPosCal] consider 2 rank data
7551 11:41:12.843448 u2DelayCellTimex100 = 290/100 ps
7552 11:41:12.850106 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7553 11:41:12.853203 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7554 11:41:12.857185 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7555 11:41:12.859875 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7556 11:41:12.863561 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7557 11:41:12.866751 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7558 11:41:12.866833
7559 11:41:12.870038 CA PerBit enable=1, Macro0, CA PI delay=35
7560 11:41:12.870121
7561 11:41:12.873449 [CBTSetCACLKResult] CA Dly = 35
7562 11:41:12.876691 CS Dly: 10 (0~42)
7563 11:41:12.880039 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 11:41:12.883859 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 11:41:12.883942
7566 11:41:12.886793 ----->DramcWriteLeveling(PI) begin...
7567 11:41:12.886876 ==
7568 11:41:12.890027 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 11:41:12.893281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 11:41:12.897130 ==
7571 11:41:12.900251 Write leveling (Byte 0): 36 => 36
7572 11:41:12.900333 Write leveling (Byte 1): 29 => 29
7573 11:41:12.903429 DramcWriteLeveling(PI) end<-----
7574 11:41:12.903510
7575 11:41:12.903575 ==
7576 11:41:12.906701 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 11:41:12.913633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 11:41:12.913716 ==
7579 11:41:12.916787 [Gating] SW mode calibration
7580 11:41:12.923485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7581 11:41:12.926596 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7582 11:41:12.933250 1 4 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7583 11:41:12.936415 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7584 11:41:12.939563 1 4 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7585 11:41:12.946211 1 4 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
7586 11:41:12.950060 1 4 16 | B1->B0 | 2323 3736 | 0 1 | (1 1) (0 0)
7587 11:41:12.953299 1 4 20 | B1->B0 | 3333 3939 | 0 0 | (0 0) (1 1)
7588 11:41:12.959504 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7589 11:41:12.962870 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7590 11:41:12.966264 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7591 11:41:12.973156 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7592 11:41:12.976419 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
7593 11:41:12.979752 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7594 11:41:12.986258 1 5 16 | B1->B0 | 3434 2e2d | 1 1 | (1 1) (0 1)
7595 11:41:12.989706 1 5 20 | B1->B0 | 2929 2b2b | 1 1 | (1 0) (0 0)
7596 11:41:12.993213 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7597 11:41:12.996106 1 5 28 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7598 11:41:13.002749 1 6 0 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7599 11:41:13.006392 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7600 11:41:13.009423 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7601 11:41:13.016246 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7602 11:41:13.019551 1 6 16 | B1->B0 | 2828 4645 | 0 1 | (0 0) (0 0)
7603 11:41:13.022786 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7604 11:41:13.029614 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 11:41:13.032621 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7606 11:41:13.036506 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 11:41:13.043086 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 11:41:13.046559 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 11:41:13.049582 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 11:41:13.056146 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7611 11:41:13.059387 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 11:41:13.062438 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 11:41:13.069651 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 11:41:13.072769 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 11:41:13.075972 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 11:41:13.082554 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 11:41:13.085695 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 11:41:13.089088 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 11:41:13.096254 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 11:41:13.099573 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 11:41:13.102495 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 11:41:13.106128 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 11:41:13.112474 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 11:41:13.116370 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 11:41:13.119384 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 11:41:13.126336 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 11:41:13.129404 Total UI for P1: 0, mck2ui 16
7628 11:41:13.132654 best dqsien dly found for B0: ( 1, 9, 12)
7629 11:41:13.136427 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 11:41:13.139355 Total UI for P1: 0, mck2ui 16
7631 11:41:13.143024 best dqsien dly found for B1: ( 1, 9, 16)
7632 11:41:13.146126 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7633 11:41:13.149373 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7634 11:41:13.149458
7635 11:41:13.152457 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7636 11:41:13.155694 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7637 11:41:13.159518 [Gating] SW calibration Done
7638 11:41:13.159604 ==
7639 11:41:13.162913 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 11:41:13.169444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 11:41:13.169530 ==
7642 11:41:13.169615 RX Vref Scan: 0
7643 11:41:13.169694
7644 11:41:13.172606 RX Vref 0 -> 0, step: 1
7645 11:41:13.172690
7646 11:41:13.175810 RX Delay 0 -> 252, step: 8
7647 11:41:13.179216 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7648 11:41:13.182124 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7649 11:41:13.185330 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7650 11:41:13.188673 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7651 11:41:13.195361 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7652 11:41:13.198600 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7653 11:41:13.201976 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7654 11:41:13.205187 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7655 11:41:13.208910 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7656 11:41:13.215735 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7657 11:41:13.219102 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7658 11:41:13.222173 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7659 11:41:13.225723 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7660 11:41:13.228729 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7661 11:41:13.235656 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7662 11:41:13.238991 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7663 11:41:13.239075 ==
7664 11:41:13.242175 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 11:41:13.245299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 11:41:13.245383 ==
7667 11:41:13.248426 DQS Delay:
7668 11:41:13.248509 DQS0 = 0, DQS1 = 0
7669 11:41:13.248576 DQM Delay:
7670 11:41:13.251919 DQM0 = 137, DQM1 = 131
7671 11:41:13.252021 DQ Delay:
7672 11:41:13.255128 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7673 11:41:13.258225 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7674 11:41:13.265310 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7675 11:41:13.268699 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7676 11:41:13.268800
7677 11:41:13.268916
7678 11:41:13.268980 ==
7679 11:41:13.271936 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 11:41:13.275089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 11:41:13.275190 ==
7682 11:41:13.275285
7683 11:41:13.275377
7684 11:41:13.278494 TX Vref Scan disable
7685 11:41:13.281796 == TX Byte 0 ==
7686 11:41:13.285105 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7687 11:41:13.288142 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7688 11:41:13.292036 == TX Byte 1 ==
7689 11:41:13.294704 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7690 11:41:13.298036 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7691 11:41:13.298144 ==
7692 11:41:13.301275 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 11:41:13.304651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 11:41:13.307910 ==
7695 11:41:13.318370
7696 11:41:13.322477 TX Vref early break, caculate TX vref
7697 11:41:13.325289 TX Vref=16, minBit 4, minWin=22, winSum=378
7698 11:41:13.328345 TX Vref=18, minBit 0, minWin=24, winSum=389
7699 11:41:13.331988 TX Vref=20, minBit 1, minWin=23, winSum=397
7700 11:41:13.335546 TX Vref=22, minBit 0, minWin=24, winSum=405
7701 11:41:13.338581 TX Vref=24, minBit 0, minWin=26, winSum=420
7702 11:41:13.345293 TX Vref=26, minBit 2, minWin=25, winSum=424
7703 11:41:13.348446 TX Vref=28, minBit 1, minWin=25, winSum=425
7704 11:41:13.351678 TX Vref=30, minBit 2, minWin=24, winSum=412
7705 11:41:13.355029 TX Vref=32, minBit 6, minWin=23, winSum=400
7706 11:41:13.361755 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 24
7707 11:41:13.361867
7708 11:41:13.361966 Final TX Range 0 Vref 24
7709 11:41:13.365499
7710 11:41:13.365600 ==
7711 11:41:13.368592 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 11:41:13.371943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 11:41:13.372019 ==
7714 11:41:13.372116
7715 11:41:13.372206
7716 11:41:13.375064 TX Vref Scan disable
7717 11:41:13.378337 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7718 11:41:13.381598 == TX Byte 0 ==
7719 11:41:13.384963 u2DelayCellOfst[0]=13 cells (4 PI)
7720 11:41:13.388286 u2DelayCellOfst[1]=16 cells (5 PI)
7721 11:41:13.392192 u2DelayCellOfst[2]=13 cells (4 PI)
7722 11:41:13.395453 u2DelayCellOfst[3]=13 cells (4 PI)
7723 11:41:13.398477 u2DelayCellOfst[4]=10 cells (3 PI)
7724 11:41:13.398584 u2DelayCellOfst[5]=0 cells (0 PI)
7725 11:41:13.401853 u2DelayCellOfst[6]=20 cells (6 PI)
7726 11:41:13.404940 u2DelayCellOfst[7]=20 cells (6 PI)
7727 11:41:13.411543 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7728 11:41:13.415390 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7729 11:41:13.415493 == TX Byte 1 ==
7730 11:41:13.418631 u2DelayCellOfst[8]=3 cells (1 PI)
7731 11:41:13.421951 u2DelayCellOfst[9]=0 cells (0 PI)
7732 11:41:13.425195 u2DelayCellOfst[10]=6 cells (2 PI)
7733 11:41:13.428454 u2DelayCellOfst[11]=3 cells (1 PI)
7734 11:41:13.432155 u2DelayCellOfst[12]=10 cells (3 PI)
7735 11:41:13.435263 u2DelayCellOfst[13]=10 cells (3 PI)
7736 11:41:13.438220 u2DelayCellOfst[14]=13 cells (4 PI)
7737 11:41:13.442118 u2DelayCellOfst[15]=10 cells (3 PI)
7738 11:41:13.444997 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7739 11:41:13.448231 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7740 11:41:13.451946 DramC Write-DBI on
7741 11:41:13.452043 ==
7742 11:41:13.455028 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 11:41:13.458333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 11:41:13.458438 ==
7745 11:41:13.458531
7746 11:41:13.458619
7747 11:41:13.461571 TX Vref Scan disable
7748 11:41:13.465341 == TX Byte 0 ==
7749 11:41:13.468419 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7750 11:41:13.468502 == TX Byte 1 ==
7751 11:41:13.475501 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7752 11:41:13.475591 DramC Write-DBI off
7753 11:41:13.475673
7754 11:41:13.478564 [DATLAT]
7755 11:41:13.478673 Freq=1600, CH0 RK0
7756 11:41:13.478768
7757 11:41:13.481970 DATLAT Default: 0xf
7758 11:41:13.482071 0, 0xFFFF, sum = 0
7759 11:41:13.485338 1, 0xFFFF, sum = 0
7760 11:41:13.485441 2, 0xFFFF, sum = 0
7761 11:41:13.488610 3, 0xFFFF, sum = 0
7762 11:41:13.488713 4, 0xFFFF, sum = 0
7763 11:41:13.492051 5, 0xFFFF, sum = 0
7764 11:41:13.492153 6, 0xFFFF, sum = 0
7765 11:41:13.495404 7, 0xFFFF, sum = 0
7766 11:41:13.495499 8, 0xFFFF, sum = 0
7767 11:41:13.498677 9, 0xFFFF, sum = 0
7768 11:41:13.498782 10, 0xFFFF, sum = 0
7769 11:41:13.501671 11, 0xFFFF, sum = 0
7770 11:41:13.501743 12, 0xFFFF, sum = 0
7771 11:41:13.505432 13, 0xFFFF, sum = 0
7772 11:41:13.505515 14, 0x0, sum = 1
7773 11:41:13.508170 15, 0x0, sum = 2
7774 11:41:13.508282 16, 0x0, sum = 3
7775 11:41:13.511981 17, 0x0, sum = 4
7776 11:41:13.512102 best_step = 15
7777 11:41:13.512196
7778 11:41:13.512288 ==
7779 11:41:13.514679 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 11:41:13.521938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 11:41:13.522050 ==
7782 11:41:13.522144 RX Vref Scan: 1
7783 11:41:13.522247
7784 11:41:13.525065 Set Vref Range= 24 -> 127
7785 11:41:13.525176
7786 11:41:13.528385 RX Vref 24 -> 127, step: 1
7787 11:41:13.528484
7788 11:41:13.531660 RX Delay 27 -> 252, step: 4
7789 11:41:13.531774
7790 11:41:13.531868 Set Vref, RX VrefLevel [Byte0]: 24
7791 11:41:13.535068 [Byte1]: 24
7792 11:41:13.539291
7793 11:41:13.539407 Set Vref, RX VrefLevel [Byte0]: 25
7794 11:41:13.542347 [Byte1]: 25
7795 11:41:13.546644
7796 11:41:13.546725 Set Vref, RX VrefLevel [Byte0]: 26
7797 11:41:13.550416 [Byte1]: 26
7798 11:41:13.554210
7799 11:41:13.554291 Set Vref, RX VrefLevel [Byte0]: 27
7800 11:41:13.558007 [Byte1]: 27
7801 11:41:13.562354
7802 11:41:13.562449 Set Vref, RX VrefLevel [Byte0]: 28
7803 11:41:13.565046 [Byte1]: 28
7804 11:41:13.569710
7805 11:41:13.569793 Set Vref, RX VrefLevel [Byte0]: 29
7806 11:41:13.572839 [Byte1]: 29
7807 11:41:13.577637
7808 11:41:13.577805 Set Vref, RX VrefLevel [Byte0]: 30
7809 11:41:13.580593 [Byte1]: 30
7810 11:41:13.584977
7811 11:41:13.585127 Set Vref, RX VrefLevel [Byte0]: 31
7812 11:41:13.588359 [Byte1]: 31
7813 11:41:13.592388
7814 11:41:13.592576 Set Vref, RX VrefLevel [Byte0]: 32
7815 11:41:13.595648 [Byte1]: 32
7816 11:41:13.599413
7817 11:41:13.599558 Set Vref, RX VrefLevel [Byte0]: 33
7818 11:41:13.602689 [Byte1]: 33
7819 11:41:13.607228
7820 11:41:13.607366 Set Vref, RX VrefLevel [Byte0]: 34
7821 11:41:13.610396 [Byte1]: 34
7822 11:41:13.614858
7823 11:41:13.615034 Set Vref, RX VrefLevel [Byte0]: 35
7824 11:41:13.618288 [Byte1]: 35
7825 11:41:13.622355
7826 11:41:13.622621 Set Vref, RX VrefLevel [Byte0]: 36
7827 11:41:13.625764 [Byte1]: 36
7828 11:41:13.629783
7829 11:41:13.630087 Set Vref, RX VrefLevel [Byte0]: 37
7830 11:41:13.633133 [Byte1]: 37
7831 11:41:13.638178
7832 11:41:13.638605 Set Vref, RX VrefLevel [Byte0]: 38
7833 11:41:13.641020 [Byte1]: 38
7834 11:41:13.644991
7835 11:41:13.645419 Set Vref, RX VrefLevel [Byte0]: 39
7836 11:41:13.648655 [Byte1]: 39
7837 11:41:13.652948
7838 11:41:13.653439 Set Vref, RX VrefLevel [Byte0]: 40
7839 11:41:13.656157 [Byte1]: 40
7840 11:41:13.660302
7841 11:41:13.660889 Set Vref, RX VrefLevel [Byte0]: 41
7842 11:41:13.663459 [Byte1]: 41
7843 11:41:13.667915
7844 11:41:13.668323 Set Vref, RX VrefLevel [Byte0]: 42
7845 11:41:13.671111 [Byte1]: 42
7846 11:41:13.675028
7847 11:41:13.675425 Set Vref, RX VrefLevel [Byte0]: 43
7848 11:41:13.678810 [Byte1]: 43
7849 11:41:13.682588
7850 11:41:13.682967 Set Vref, RX VrefLevel [Byte0]: 44
7851 11:41:13.686313 [Byte1]: 44
7852 11:41:13.690170
7853 11:41:13.690538 Set Vref, RX VrefLevel [Byte0]: 45
7854 11:41:13.693883 [Byte1]: 45
7855 11:41:13.697530
7856 11:41:13.697944 Set Vref, RX VrefLevel [Byte0]: 46
7857 11:41:13.701546 [Byte1]: 46
7858 11:41:13.705595
7859 11:41:13.705969 Set Vref, RX VrefLevel [Byte0]: 47
7860 11:41:13.708790 [Byte1]: 47
7861 11:41:13.712740
7862 11:41:13.713174 Set Vref, RX VrefLevel [Byte0]: 48
7863 11:41:13.716399 [Byte1]: 48
7864 11:41:13.720850
7865 11:41:13.721245 Set Vref, RX VrefLevel [Byte0]: 49
7866 11:41:13.723527 [Byte1]: 49
7867 11:41:13.727976
7868 11:41:13.728357 Set Vref, RX VrefLevel [Byte0]: 50
7869 11:41:13.731325 [Byte1]: 50
7870 11:41:13.735230
7871 11:41:13.735591 Set Vref, RX VrefLevel [Byte0]: 51
7872 11:41:13.739164 [Byte1]: 51
7873 11:41:13.743211
7874 11:41:13.746261 Set Vref, RX VrefLevel [Byte0]: 52
7875 11:41:13.749617 [Byte1]: 52
7876 11:41:13.750002
7877 11:41:13.752995 Set Vref, RX VrefLevel [Byte0]: 53
7878 11:41:13.755984 [Byte1]: 53
7879 11:41:13.756343
7880 11:41:13.759675 Set Vref, RX VrefLevel [Byte0]: 54
7881 11:41:13.762512 [Byte1]: 54
7882 11:41:13.762912
7883 11:41:13.766014 Set Vref, RX VrefLevel [Byte0]: 55
7884 11:41:13.769312 [Byte1]: 55
7885 11:41:13.773196
7886 11:41:13.773567 Set Vref, RX VrefLevel [Byte0]: 56
7887 11:41:13.776250 [Byte1]: 56
7888 11:41:13.780781
7889 11:41:13.781188 Set Vref, RX VrefLevel [Byte0]: 57
7890 11:41:13.784003 [Byte1]: 57
7891 11:41:13.788446
7892 11:41:13.788869 Set Vref, RX VrefLevel [Byte0]: 58
7893 11:41:13.791420 [Byte1]: 58
7894 11:41:13.795751
7895 11:41:13.796111 Set Vref, RX VrefLevel [Byte0]: 59
7896 11:41:13.798865 [Byte1]: 59
7897 11:41:13.803647
7898 11:41:13.804067 Set Vref, RX VrefLevel [Byte0]: 60
7899 11:41:13.807046 [Byte1]: 60
7900 11:41:13.810976
7901 11:41:13.811408 Set Vref, RX VrefLevel [Byte0]: 61
7902 11:41:13.814219 [Byte1]: 61
7903 11:41:13.818249
7904 11:41:13.818669 Set Vref, RX VrefLevel [Byte0]: 62
7905 11:41:13.821424 [Byte1]: 62
7906 11:41:13.825779
7907 11:41:13.826208 Set Vref, RX VrefLevel [Byte0]: 63
7908 11:41:13.828918 [Byte1]: 63
7909 11:41:13.833659
7910 11:41:13.834089 Set Vref, RX VrefLevel [Byte0]: 64
7911 11:41:13.836688 [Byte1]: 64
7912 11:41:13.841403
7913 11:41:13.841856 Set Vref, RX VrefLevel [Byte0]: 65
7914 11:41:13.844065 [Byte1]: 65
7915 11:41:13.848582
7916 11:41:13.849050 Set Vref, RX VrefLevel [Byte0]: 66
7917 11:41:13.851772 [Byte1]: 66
7918 11:41:13.856289
7919 11:41:13.856721 Set Vref, RX VrefLevel [Byte0]: 67
7920 11:41:13.859388 [Byte1]: 67
7921 11:41:13.863696
7922 11:41:13.864131 Set Vref, RX VrefLevel [Byte0]: 68
7923 11:41:13.866847 [Byte1]: 68
7924 11:41:13.871053
7925 11:41:13.871484 Set Vref, RX VrefLevel [Byte0]: 69
7926 11:41:13.874130 [Byte1]: 69
7927 11:41:13.878498
7928 11:41:13.878932 Set Vref, RX VrefLevel [Byte0]: 70
7929 11:41:13.882260 [Byte1]: 70
7930 11:41:13.886279
7931 11:41:13.886708 Set Vref, RX VrefLevel [Byte0]: 71
7932 11:41:13.889552 [Byte1]: 71
7933 11:41:13.893574
7934 11:41:13.894030 Set Vref, RX VrefLevel [Byte0]: 72
7935 11:41:13.896665 [Byte1]: 72
7936 11:41:13.900965
7937 11:41:13.901398 Final RX Vref Byte 0 = 58 to rank0
7938 11:41:13.904453 Final RX Vref Byte 1 = 61 to rank0
7939 11:41:13.907589 Final RX Vref Byte 0 = 58 to rank1
7940 11:41:13.911318 Final RX Vref Byte 1 = 61 to rank1==
7941 11:41:13.914275 Dram Type= 6, Freq= 0, CH_0, rank 0
7942 11:41:13.921388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7943 11:41:13.921855 ==
7944 11:41:13.922377 DQS Delay:
7945 11:41:13.922710 DQS0 = 0, DQS1 = 0
7946 11:41:13.924791 DQM Delay:
7947 11:41:13.925233 DQM0 = 134, DQM1 = 127
7948 11:41:13.928209 DQ Delay:
7949 11:41:13.931382 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7950 11:41:13.934437 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7951 11:41:13.937573 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7952 11:41:13.941388 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7953 11:41:13.941812
7954 11:41:13.942145
7955 11:41:13.942466
7956 11:41:13.944751 [DramC_TX_OE_Calibration] TA2
7957 11:41:13.948046 Original DQ_B0 (3 6) =30, OEN = 27
7958 11:41:13.951440 Original DQ_B1 (3 6) =30, OEN = 27
7959 11:41:13.954422 24, 0x0, End_B0=24 End_B1=24
7960 11:41:13.954857 25, 0x0, End_B0=25 End_B1=25
7961 11:41:13.957766 26, 0x0, End_B0=26 End_B1=26
7962 11:41:13.961021 27, 0x0, End_B0=27 End_B1=27
7963 11:41:13.964404 28, 0x0, End_B0=28 End_B1=28
7964 11:41:13.964895 29, 0x0, End_B0=29 End_B1=29
7965 11:41:13.967539 30, 0x0, End_B0=30 End_B1=30
7966 11:41:13.971185 31, 0x5151, End_B0=30 End_B1=30
7967 11:41:13.974537 Byte0 end_step=30 best_step=27
7968 11:41:13.977727 Byte1 end_step=30 best_step=27
7969 11:41:13.980964 Byte0 TX OE(2T, 0.5T) = (3, 3)
7970 11:41:13.981412 Byte1 TX OE(2T, 0.5T) = (3, 3)
7971 11:41:13.984486
7972 11:41:13.984949
7973 11:41:13.991158 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7974 11:41:13.994420 CH0 RK0: MR19=303, MR18=2622
7975 11:41:14.000956 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7976 11:41:14.001383
7977 11:41:14.004173 ----->DramcWriteLeveling(PI) begin...
7978 11:41:14.004624 ==
7979 11:41:14.007692 Dram Type= 6, Freq= 0, CH_0, rank 1
7980 11:41:14.010782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 11:41:14.011204 ==
7982 11:41:14.014515 Write leveling (Byte 0): 36 => 36
7983 11:41:14.018137 Write leveling (Byte 1): 28 => 28
7984 11:41:14.021086 DramcWriteLeveling(PI) end<-----
7985 11:41:14.021511
7986 11:41:14.021849 ==
7987 11:41:14.024445 Dram Type= 6, Freq= 0, CH_0, rank 1
7988 11:41:14.027762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 11:41:14.028190 ==
7990 11:41:14.031034 [Gating] SW mode calibration
7991 11:41:14.037585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7992 11:41:14.044238 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7993 11:41:14.047658 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7994 11:41:14.050947 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7995 11:41:14.057979 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7996 11:41:14.061306 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7997 11:41:14.064417 1 4 16 | B1->B0 | 2f2f 3737 | 0 0 | (0 0) (0 0)
7998 11:41:14.071019 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7999 11:41:14.074226 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8000 11:41:14.077298 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
8001 11:41:14.084102 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
8002 11:41:14.087634 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 11:41:14.090827 1 5 8 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8004 11:41:14.097817 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8005 11:41:14.101062 1 5 16 | B1->B0 | 2d2d 2b2a | 1 1 | (1 0) (1 0)
8006 11:41:14.104441 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8007 11:41:14.110879 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8008 11:41:14.114134 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (1 1)
8009 11:41:14.117165 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8010 11:41:14.121077 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8011 11:41:14.127600 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 11:41:14.130667 1 6 12 | B1->B0 | 2424 3333 | 0 1 | (0 0) (1 1)
8013 11:41:14.133934 1 6 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8014 11:41:14.140644 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8015 11:41:14.143844 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 11:41:14.147138 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8017 11:41:14.153891 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 11:41:14.157095 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 11:41:14.160702 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 11:41:14.166849 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8021 11:41:14.169998 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 11:41:14.173449 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 11:41:14.180597 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 11:41:14.183495 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 11:41:14.186771 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 11:41:14.193403 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 11:41:14.196713 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 11:41:14.200437 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 11:41:14.206743 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 11:41:14.209998 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 11:41:14.213298 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 11:41:14.220421 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 11:41:14.223835 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 11:41:14.226979 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 11:41:14.233579 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8036 11:41:14.236575 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8037 11:41:14.240375 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8038 11:41:14.246767 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 11:41:14.247198 Total UI for P1: 0, mck2ui 16
8040 11:41:14.253435 best dqsien dly found for B0: ( 1, 9, 12)
8041 11:41:14.253891 Total UI for P1: 0, mck2ui 16
8042 11:41:14.260046 best dqsien dly found for B1: ( 1, 9, 14)
8043 11:41:14.263226 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8044 11:41:14.266555 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8045 11:41:14.266981
8046 11:41:14.269682 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8047 11:41:14.272882 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8048 11:41:14.276185 [Gating] SW calibration Done
8049 11:41:14.276610 ==
8050 11:41:14.279563 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 11:41:14.282711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 11:41:14.283140 ==
8053 11:41:14.285970 RX Vref Scan: 0
8054 11:41:14.286396
8055 11:41:14.286738 RX Vref 0 -> 0, step: 1
8056 11:41:14.287056
8057 11:41:14.289883 RX Delay 0 -> 252, step: 8
8058 11:41:14.292891 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8059 11:41:14.299768 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8060 11:41:14.302925 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8061 11:41:14.306069 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8062 11:41:14.309240 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8063 11:41:14.312554 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8064 11:41:14.319209 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8065 11:41:14.322382 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8066 11:41:14.325643 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8067 11:41:14.328944 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8068 11:41:14.332327 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8069 11:41:14.339366 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8070 11:41:14.342512 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8071 11:41:14.345503 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8072 11:41:14.349091 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8073 11:41:14.355640 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8074 11:41:14.355724 ==
8075 11:41:14.359050 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 11:41:14.362220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 11:41:14.362305 ==
8078 11:41:14.362371 DQS Delay:
8079 11:41:14.365984 DQS0 = 0, DQS1 = 0
8080 11:41:14.366071 DQM Delay:
8081 11:41:14.369037 DQM0 = 137, DQM1 = 129
8082 11:41:14.369121 DQ Delay:
8083 11:41:14.372083 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8084 11:41:14.375497 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8085 11:41:14.378692 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8086 11:41:14.382052 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8087 11:41:14.382136
8088 11:41:14.382202
8089 11:41:14.382263 ==
8090 11:41:14.385324 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 11:41:14.392022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 11:41:14.392106 ==
8093 11:41:14.392173
8094 11:41:14.392235
8095 11:41:14.392294 TX Vref Scan disable
8096 11:41:14.395751 == TX Byte 0 ==
8097 11:41:14.399639 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8098 11:41:14.405686 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8099 11:41:14.405771 == TX Byte 1 ==
8100 11:41:14.409481 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8101 11:41:14.412633 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8102 11:41:14.416272 ==
8103 11:41:14.419586 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 11:41:14.422712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 11:41:14.422797 ==
8106 11:41:14.435662
8107 11:41:14.439127 TX Vref early break, caculate TX vref
8108 11:41:14.442217 TX Vref=16, minBit 1, minWin=22, winSum=384
8109 11:41:14.445573 TX Vref=18, minBit 1, minWin=23, winSum=394
8110 11:41:14.449400 TX Vref=20, minBit 1, minWin=23, winSum=401
8111 11:41:14.452452 TX Vref=22, minBit 1, minWin=24, winSum=410
8112 11:41:14.455979 TX Vref=24, minBit 3, minWin=25, winSum=418
8113 11:41:14.462453 TX Vref=26, minBit 1, minWin=25, winSum=423
8114 11:41:14.465731 TX Vref=28, minBit 0, minWin=25, winSum=423
8115 11:41:14.468952 TX Vref=30, minBit 0, minWin=25, winSum=417
8116 11:41:14.472179 TX Vref=32, minBit 4, minWin=24, winSum=409
8117 11:41:14.475886 TX Vref=34, minBit 4, minWin=23, winSum=397
8118 11:41:14.482189 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 26
8119 11:41:14.482273
8120 11:41:14.485552 Final TX Range 0 Vref 26
8121 11:41:14.485636
8122 11:41:14.485703 ==
8123 11:41:14.488843 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 11:41:14.492134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 11:41:14.492235 ==
8126 11:41:14.492326
8127 11:41:14.492417
8128 11:41:14.496056 TX Vref Scan disable
8129 11:41:14.502247 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8130 11:41:14.502361 == TX Byte 0 ==
8131 11:41:14.506015 u2DelayCellOfst[0]=16 cells (5 PI)
8132 11:41:14.508961 u2DelayCellOfst[1]=20 cells (6 PI)
8133 11:41:14.512086 u2DelayCellOfst[2]=10 cells (3 PI)
8134 11:41:14.515907 u2DelayCellOfst[3]=13 cells (4 PI)
8135 11:41:14.519070 u2DelayCellOfst[4]=10 cells (3 PI)
8136 11:41:14.522652 u2DelayCellOfst[5]=0 cells (0 PI)
8137 11:41:14.526222 u2DelayCellOfst[6]=16 cells (5 PI)
8138 11:41:14.526329 u2DelayCellOfst[7]=16 cells (5 PI)
8139 11:41:14.532504 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8140 11:41:14.535889 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8141 11:41:14.535960 == TX Byte 1 ==
8142 11:41:14.539067 u2DelayCellOfst[8]=3 cells (1 PI)
8143 11:41:14.542393 u2DelayCellOfst[9]=0 cells (0 PI)
8144 11:41:14.545599 u2DelayCellOfst[10]=6 cells (2 PI)
8145 11:41:14.549482 u2DelayCellOfst[11]=3 cells (1 PI)
8146 11:41:14.552692 u2DelayCellOfst[12]=10 cells (3 PI)
8147 11:41:14.556067 u2DelayCellOfst[13]=13 cells (4 PI)
8148 11:41:14.559361 u2DelayCellOfst[14]=13 cells (4 PI)
8149 11:41:14.562547 u2DelayCellOfst[15]=10 cells (3 PI)
8150 11:41:14.566284 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8151 11:41:14.569468 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8152 11:41:14.572740 DramC Write-DBI on
8153 11:41:14.572864 ==
8154 11:41:14.576013 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 11:41:14.579147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 11:41:14.579233 ==
8157 11:41:14.579319
8158 11:41:14.582004
8159 11:41:14.582090 TX Vref Scan disable
8160 11:41:14.585639 == TX Byte 0 ==
8161 11:41:14.589055 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8162 11:41:14.592409 == TX Byte 1 ==
8163 11:41:14.595768 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8164 11:41:14.595854 DramC Write-DBI off
8165 11:41:14.599058
8166 11:41:14.599168 [DATLAT]
8167 11:41:14.599257 Freq=1600, CH0 RK1
8168 11:41:14.599340
8169 11:41:14.602505 DATLAT Default: 0xf
8170 11:41:14.602590 0, 0xFFFF, sum = 0
8171 11:41:14.605694 1, 0xFFFF, sum = 0
8172 11:41:14.605781 2, 0xFFFF, sum = 0
8173 11:41:14.608904 3, 0xFFFF, sum = 0
8174 11:41:14.611935 4, 0xFFFF, sum = 0
8175 11:41:14.612042 5, 0xFFFF, sum = 0
8176 11:41:14.615495 6, 0xFFFF, sum = 0
8177 11:41:14.615638 7, 0xFFFF, sum = 0
8178 11:41:14.618635 8, 0xFFFF, sum = 0
8179 11:41:14.618726 9, 0xFFFF, sum = 0
8180 11:41:14.621727 10, 0xFFFF, sum = 0
8181 11:41:14.621812 11, 0xFFFF, sum = 0
8182 11:41:14.625459 12, 0xFFFF, sum = 0
8183 11:41:14.625543 13, 0xFFFF, sum = 0
8184 11:41:14.628582 14, 0x0, sum = 1
8185 11:41:14.628668 15, 0x0, sum = 2
8186 11:41:14.631797 16, 0x0, sum = 3
8187 11:41:14.631871 17, 0x0, sum = 4
8188 11:41:14.635419 best_step = 15
8189 11:41:14.635496
8190 11:41:14.635559 ==
8191 11:41:14.638718 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 11:41:14.642057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 11:41:14.642141 ==
8194 11:41:14.642206 RX Vref Scan: 0
8195 11:41:14.645462
8196 11:41:14.645535 RX Vref 0 -> 0, step: 1
8197 11:41:14.645598
8198 11:41:14.648609 RX Delay 19 -> 252, step: 4
8199 11:41:14.651777 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8200 11:41:14.658280 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8201 11:41:14.661593 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8202 11:41:14.665341 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8203 11:41:14.668592 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8204 11:41:14.671634 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8205 11:41:14.678812 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8206 11:41:14.682222 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8207 11:41:14.685398 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8208 11:41:14.688426 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8209 11:41:14.691950 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8210 11:41:14.698369 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8211 11:41:14.701595 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8212 11:41:14.704964 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8213 11:41:14.708431 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8214 11:41:14.715079 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8215 11:41:14.715154 ==
8216 11:41:14.718255 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 11:41:14.721326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 11:41:14.721427 ==
8219 11:41:14.721517 DQS Delay:
8220 11:41:14.725029 DQS0 = 0, DQS1 = 0
8221 11:41:14.725099 DQM Delay:
8222 11:41:14.728130 DQM0 = 134, DQM1 = 127
8223 11:41:14.728204 DQ Delay:
8224 11:41:14.731626 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8225 11:41:14.734805 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8226 11:41:14.737911 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8227 11:41:14.741588 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8228 11:41:14.741689
8229 11:41:14.741769
8230 11:41:14.741831
8231 11:41:14.744599 [DramC_TX_OE_Calibration] TA2
8232 11:41:14.748406 Original DQ_B0 (3 6) =30, OEN = 27
8233 11:41:14.751723 Original DQ_B1 (3 6) =30, OEN = 27
8234 11:41:14.754894 24, 0x0, End_B0=24 End_B1=24
8235 11:41:14.757829 25, 0x0, End_B0=25 End_B1=25
8236 11:41:14.757914 26, 0x0, End_B0=26 End_B1=26
8237 11:41:14.761151 27, 0x0, End_B0=27 End_B1=27
8238 11:41:14.764392 28, 0x0, End_B0=28 End_B1=28
8239 11:41:14.768097 29, 0x0, End_B0=29 End_B1=29
8240 11:41:14.771487 30, 0x0, End_B0=30 End_B1=30
8241 11:41:14.771573 31, 0x4141, End_B0=30 End_B1=30
8242 11:41:14.774757 Byte0 end_step=30 best_step=27
8243 11:41:14.777789 Byte1 end_step=30 best_step=27
8244 11:41:14.781049 Byte0 TX OE(2T, 0.5T) = (3, 3)
8245 11:41:14.784265 Byte1 TX OE(2T, 0.5T) = (3, 3)
8246 11:41:14.784349
8247 11:41:14.784415
8248 11:41:14.791030 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8249 11:41:14.794244 CH0 RK1: MR19=303, MR18=210A
8250 11:41:14.800751 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8251 11:41:14.804734 [RxdqsGatingPostProcess] freq 1600
8252 11:41:14.811487 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8253 11:41:14.811571 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 11:41:14.814785 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 11:41:14.818054 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 11:41:14.821332 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 11:41:14.824328 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 11:41:14.827587 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 11:41:14.831379 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 11:41:14.834487 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 11:41:14.837644 Pre-setting of DQS Precalculation
8262 11:41:14.841264 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8263 11:41:14.841348 ==
8264 11:41:14.844453 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 11:41:14.851040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 11:41:14.851149 ==
8267 11:41:14.854182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 11:41:14.861372 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 11:41:14.864269 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 11:41:14.870653 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 11:41:14.878484 [CA 0] Center 41 (12~71) winsize 60
8272 11:41:14.881776 [CA 1] Center 41 (12~71) winsize 60
8273 11:41:14.885458 [CA 2] Center 38 (9~68) winsize 60
8274 11:41:14.888447 [CA 3] Center 37 (8~66) winsize 59
8275 11:41:14.891707 [CA 4] Center 37 (8~67) winsize 60
8276 11:41:14.895094 [CA 5] Center 36 (7~66) winsize 60
8277 11:41:14.895179
8278 11:41:14.898305 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8279 11:41:14.898388
8280 11:41:14.901517 [CATrainingPosCal] consider 1 rank data
8281 11:41:14.905242 u2DelayCellTimex100 = 290/100 ps
8282 11:41:14.908437 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8283 11:41:14.915034 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8284 11:41:14.918430 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8285 11:41:14.921735 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8286 11:41:14.925045 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8287 11:41:14.928192 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8288 11:41:14.928275
8289 11:41:14.931564 CA PerBit enable=1, Macro0, CA PI delay=36
8290 11:41:14.931647
8291 11:41:14.934937 [CBTSetCACLKResult] CA Dly = 36
8292 11:41:14.938466 CS Dly: 11 (0~42)
8293 11:41:14.941719 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 11:41:14.944945 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 11:41:14.945028 ==
8296 11:41:14.948609 Dram Type= 6, Freq= 0, CH_1, rank 1
8297 11:41:14.951940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 11:41:14.952059 ==
8299 11:41:14.958380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8300 11:41:14.962049 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8301 11:41:14.968193 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8302 11:41:14.971510 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8303 11:41:14.981938 [CA 0] Center 42 (13~72) winsize 60
8304 11:41:14.985224 [CA 1] Center 41 (12~71) winsize 60
8305 11:41:14.988336 [CA 2] Center 38 (9~68) winsize 60
8306 11:41:14.991509 [CA 3] Center 38 (8~68) winsize 61
8307 11:41:14.995329 [CA 4] Center 38 (8~68) winsize 61
8308 11:41:14.998389 [CA 5] Center 36 (7~66) winsize 60
8309 11:41:14.998493
8310 11:41:15.001741 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8311 11:41:15.001841
8312 11:41:15.004927 [CATrainingPosCal] consider 2 rank data
8313 11:41:15.008178 u2DelayCellTimex100 = 290/100 ps
8314 11:41:15.012095 CA0 delay=42 (13~71),Diff = 6 PI (20 cell)
8315 11:41:15.018475 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8316 11:41:15.022090 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8317 11:41:15.025272 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8318 11:41:15.028512 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8319 11:41:15.031612 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8320 11:41:15.031719
8321 11:41:15.034891 CA PerBit enable=1, Macro0, CA PI delay=36
8322 11:41:15.034973
8323 11:41:15.038146 [CBTSetCACLKResult] CA Dly = 36
8324 11:41:15.041923 CS Dly: 12 (0~44)
8325 11:41:15.044995 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8326 11:41:15.048055 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8327 11:41:15.048171
8328 11:41:15.052145 ----->DramcWriteLeveling(PI) begin...
8329 11:41:15.052228 ==
8330 11:41:15.054910 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 11:41:15.058253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 11:41:15.061258 ==
8333 11:41:15.061338 Write leveling (Byte 0): 26 => 26
8334 11:41:15.065053 Write leveling (Byte 1): 28 => 28
8335 11:41:15.068302 DramcWriteLeveling(PI) end<-----
8336 11:41:15.068421
8337 11:41:15.068517 ==
8338 11:41:15.072101 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 11:41:15.078386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 11:41:15.078497 ==
8341 11:41:15.078594 [Gating] SW mode calibration
8342 11:41:15.088138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8343 11:41:15.091410 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8344 11:41:15.094634 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 11:41:15.101622 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 11:41:15.104761 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8347 11:41:15.108077 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8348 11:41:15.114645 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 11:41:15.118355 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 11:41:15.121513 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 11:41:15.128182 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 11:41:15.131412 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 11:41:15.134717 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 11:41:15.141766 1 5 8 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 0)
8355 11:41:15.145090 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8356 11:41:15.148369 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:41:15.154553 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:41:15.157788 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 11:41:15.161531 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:41:15.167748 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 11:41:15.171573 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 11:41:15.174679 1 6 8 | B1->B0 | 2626 2b2b | 0 1 | (0 0) (0 0)
8363 11:41:15.181420 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8364 11:41:15.184522 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 11:41:15.187827 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 11:41:15.194367 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 11:41:15.197718 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 11:41:15.201056 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 11:41:15.208105 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 11:41:15.211395 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 11:41:15.214284 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 11:41:15.217639 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:41:15.224663 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:41:15.227744 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 11:41:15.231038 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 11:41:15.237663 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 11:41:15.241444 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 11:41:15.244706 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 11:41:15.251306 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 11:41:15.254761 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 11:41:15.257459 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 11:41:15.264369 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 11:41:15.267485 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 11:41:15.270948 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 11:41:15.277803 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 11:41:15.281082 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 11:41:15.283978 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8388 11:41:15.290816 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 11:41:15.290899 Total UI for P1: 0, mck2ui 16
8390 11:41:15.297374 best dqsien dly found for B0: ( 1, 9, 10)
8391 11:41:15.297456 Total UI for P1: 0, mck2ui 16
8392 11:41:15.304036 best dqsien dly found for B1: ( 1, 9, 10)
8393 11:41:15.307344 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8394 11:41:15.310582 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8395 11:41:15.310664
8396 11:41:15.314457 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8397 11:41:15.317794 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8398 11:41:15.320701 [Gating] SW calibration Done
8399 11:41:15.320846 ==
8400 11:41:15.324004 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 11:41:15.327466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 11:41:15.327549 ==
8403 11:41:15.330561 RX Vref Scan: 0
8404 11:41:15.330644
8405 11:41:15.330709 RX Vref 0 -> 0, step: 1
8406 11:41:15.330771
8407 11:41:15.333690 RX Delay 0 -> 252, step: 8
8408 11:41:15.337044 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8409 11:41:15.344123 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8410 11:41:15.347419 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8411 11:41:15.350612 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8412 11:41:15.353946 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8413 11:41:15.357392 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8414 11:41:15.363616 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8415 11:41:15.366941 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8416 11:41:15.370431 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8417 11:41:15.373931 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8418 11:41:15.376745 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8419 11:41:15.383766 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8420 11:41:15.386957 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8421 11:41:15.390123 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8422 11:41:15.393797 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8423 11:41:15.396823 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8424 11:41:15.400209 ==
8425 11:41:15.403450 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 11:41:15.406782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 11:41:15.406866 ==
8428 11:41:15.406933 DQS Delay:
8429 11:41:15.410196 DQS0 = 0, DQS1 = 0
8430 11:41:15.410279 DQM Delay:
8431 11:41:15.413319 DQM0 = 137, DQM1 = 133
8432 11:41:15.413401 DQ Delay:
8433 11:41:15.416612 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8434 11:41:15.420024 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8435 11:41:15.423092 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8436 11:41:15.426951 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8437 11:41:15.427039
8438 11:41:15.427104
8439 11:41:15.427166 ==
8440 11:41:15.430001 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 11:41:15.436418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 11:41:15.436502 ==
8443 11:41:15.436569
8444 11:41:15.436630
8445 11:41:15.436689 TX Vref Scan disable
8446 11:41:15.440432 == TX Byte 0 ==
8447 11:41:15.443781 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8448 11:41:15.447072 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8449 11:41:15.450108 == TX Byte 1 ==
8450 11:41:15.453389 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8451 11:41:15.456687 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8452 11:41:15.460792 ==
8453 11:41:15.463428 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 11:41:15.466691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 11:41:15.466775 ==
8456 11:41:15.479276
8457 11:41:15.482780 TX Vref early break, caculate TX vref
8458 11:41:15.485680 TX Vref=16, minBit 6, minWin=22, winSum=377
8459 11:41:15.489424 TX Vref=18, minBit 1, minWin=23, winSum=383
8460 11:41:15.492668 TX Vref=20, minBit 0, minWin=23, winSum=393
8461 11:41:15.495765 TX Vref=22, minBit 0, minWin=24, winSum=407
8462 11:41:15.498869 TX Vref=24, minBit 5, minWin=25, winSum=419
8463 11:41:15.505699 TX Vref=26, minBit 1, minWin=25, winSum=424
8464 11:41:15.509083 TX Vref=28, minBit 0, minWin=25, winSum=426
8465 11:41:15.512380 TX Vref=30, minBit 0, minWin=25, winSum=417
8466 11:41:15.515652 TX Vref=32, minBit 0, minWin=25, winSum=413
8467 11:41:15.518893 TX Vref=34, minBit 0, minWin=24, winSum=401
8468 11:41:15.525482 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8469 11:41:15.525567
8470 11:41:15.528572 Final TX Range 0 Vref 28
8471 11:41:15.528656
8472 11:41:15.528723 ==
8473 11:41:15.532436 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 11:41:15.535480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 11:41:15.535564 ==
8476 11:41:15.535632
8477 11:41:15.535693
8478 11:41:15.538758 TX Vref Scan disable
8479 11:41:15.545591 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8480 11:41:15.545675 == TX Byte 0 ==
8481 11:41:15.549008 u2DelayCellOfst[0]=16 cells (5 PI)
8482 11:41:15.552143 u2DelayCellOfst[1]=10 cells (3 PI)
8483 11:41:15.555321 u2DelayCellOfst[2]=0 cells (0 PI)
8484 11:41:15.558709 u2DelayCellOfst[3]=6 cells (2 PI)
8485 11:41:15.561900 u2DelayCellOfst[4]=6 cells (2 PI)
8486 11:41:15.565333 u2DelayCellOfst[5]=16 cells (5 PI)
8487 11:41:15.568633 u2DelayCellOfst[6]=16 cells (5 PI)
8488 11:41:15.568743 u2DelayCellOfst[7]=3 cells (1 PI)
8489 11:41:15.575202 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8490 11:41:15.578362 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8491 11:41:15.578446 == TX Byte 1 ==
8492 11:41:15.581902 u2DelayCellOfst[8]=0 cells (0 PI)
8493 11:41:15.585358 u2DelayCellOfst[9]=6 cells (2 PI)
8494 11:41:15.588523 u2DelayCellOfst[10]=13 cells (4 PI)
8495 11:41:15.591864 u2DelayCellOfst[11]=6 cells (2 PI)
8496 11:41:15.594854 u2DelayCellOfst[12]=16 cells (5 PI)
8497 11:41:15.598614 u2DelayCellOfst[13]=16 cells (5 PI)
8498 11:41:15.601798 u2DelayCellOfst[14]=20 cells (6 PI)
8499 11:41:15.604783 u2DelayCellOfst[15]=16 cells (5 PI)
8500 11:41:15.608455 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8501 11:41:15.614969 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8502 11:41:15.615055 DramC Write-DBI on
8503 11:41:15.615121 ==
8504 11:41:15.618109 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 11:41:15.621432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 11:41:15.621514 ==
8507 11:41:15.625211
8508 11:41:15.625282
8509 11:41:15.625343 TX Vref Scan disable
8510 11:41:15.627978 == TX Byte 0 ==
8511 11:41:15.631854 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8512 11:41:15.635042 == TX Byte 1 ==
8513 11:41:15.638053 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8514 11:41:15.638127 DramC Write-DBI off
8515 11:41:15.641914
8516 11:41:15.641989 [DATLAT]
8517 11:41:15.642050 Freq=1600, CH1 RK0
8518 11:41:15.642116
8519 11:41:15.645120 DATLAT Default: 0xf
8520 11:41:15.645187 0, 0xFFFF, sum = 0
8521 11:41:15.648293 1, 0xFFFF, sum = 0
8522 11:41:15.648362 2, 0xFFFF, sum = 0
8523 11:41:15.651295 3, 0xFFFF, sum = 0
8524 11:41:15.654611 4, 0xFFFF, sum = 0
8525 11:41:15.654681 5, 0xFFFF, sum = 0
8526 11:41:15.658308 6, 0xFFFF, sum = 0
8527 11:41:15.658394 7, 0xFFFF, sum = 0
8528 11:41:15.661577 8, 0xFFFF, sum = 0
8529 11:41:15.661647 9, 0xFFFF, sum = 0
8530 11:41:15.664926 10, 0xFFFF, sum = 0
8531 11:41:15.665012 11, 0xFFFF, sum = 0
8532 11:41:15.668337 12, 0xFFFF, sum = 0
8533 11:41:15.668420 13, 0xFFFF, sum = 0
8534 11:41:15.671694 14, 0x0, sum = 1
8535 11:41:15.671777 15, 0x0, sum = 2
8536 11:41:15.674347 16, 0x0, sum = 3
8537 11:41:15.674417 17, 0x0, sum = 4
8538 11:41:15.678191 best_step = 15
8539 11:41:15.678267
8540 11:41:15.678327 ==
8541 11:41:15.681440 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 11:41:15.684545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 11:41:15.684621 ==
8544 11:41:15.688278 RX Vref Scan: 1
8545 11:41:15.688358
8546 11:41:15.688422 Set Vref Range= 24 -> 127
8547 11:41:15.688482
8548 11:41:15.691310 RX Vref 24 -> 127, step: 1
8549 11:41:15.691380
8550 11:41:15.694559 RX Delay 27 -> 252, step: 4
8551 11:41:15.694633
8552 11:41:15.697812 Set Vref, RX VrefLevel [Byte0]: 24
8553 11:41:15.701552 [Byte1]: 24
8554 11:41:15.701628
8555 11:41:15.704645 Set Vref, RX VrefLevel [Byte0]: 25
8556 11:41:15.707859 [Byte1]: 25
8557 11:41:15.707932
8558 11:41:15.711355 Set Vref, RX VrefLevel [Byte0]: 26
8559 11:41:15.714378 [Byte1]: 26
8560 11:41:15.718250
8561 11:41:15.718335 Set Vref, RX VrefLevel [Byte0]: 27
8562 11:41:15.721493 [Byte1]: 27
8563 11:41:15.726020
8564 11:41:15.726102 Set Vref, RX VrefLevel [Byte0]: 28
8565 11:41:15.729295 [Byte1]: 28
8566 11:41:15.733328
8567 11:41:15.733399 Set Vref, RX VrefLevel [Byte0]: 29
8568 11:41:15.736560 [Byte1]: 29
8569 11:41:15.741116
8570 11:41:15.741198 Set Vref, RX VrefLevel [Byte0]: 30
8571 11:41:15.744153 [Byte1]: 30
8572 11:41:15.748569
8573 11:41:15.748650 Set Vref, RX VrefLevel [Byte0]: 31
8574 11:41:15.751943 [Byte1]: 31
8575 11:41:15.755847
8576 11:41:15.755928 Set Vref, RX VrefLevel [Byte0]: 32
8577 11:41:15.759427 [Byte1]: 32
8578 11:41:15.763287
8579 11:41:15.763369 Set Vref, RX VrefLevel [Byte0]: 33
8580 11:41:15.767248 [Byte1]: 33
8581 11:41:15.771195
8582 11:41:15.771277 Set Vref, RX VrefLevel [Byte0]: 34
8583 11:41:15.774617 [Byte1]: 34
8584 11:41:15.778625
8585 11:41:15.778706 Set Vref, RX VrefLevel [Byte0]: 35
8586 11:41:15.781865 [Byte1]: 35
8587 11:41:15.785825
8588 11:41:15.789457 Set Vref, RX VrefLevel [Byte0]: 36
8589 11:41:15.789540 [Byte1]: 36
8590 11:41:15.793856
8591 11:41:15.793938 Set Vref, RX VrefLevel [Byte0]: 37
8592 11:41:15.797052 [Byte1]: 37
8593 11:41:15.801514
8594 11:41:15.801595 Set Vref, RX VrefLevel [Byte0]: 38
8595 11:41:15.804637 [Byte1]: 38
8596 11:41:15.808964
8597 11:41:15.809060 Set Vref, RX VrefLevel [Byte0]: 39
8598 11:41:15.812367 [Byte1]: 39
8599 11:41:15.816033
8600 11:41:15.816116 Set Vref, RX VrefLevel [Byte0]: 40
8601 11:41:15.819584 [Byte1]: 40
8602 11:41:15.824143
8603 11:41:15.824226 Set Vref, RX VrefLevel [Byte0]: 41
8604 11:41:15.827376 [Byte1]: 41
8605 11:41:15.831235
8606 11:41:15.831317 Set Vref, RX VrefLevel [Byte0]: 42
8607 11:41:15.834592 [Byte1]: 42
8608 11:41:15.839135
8609 11:41:15.839216 Set Vref, RX VrefLevel [Byte0]: 43
8610 11:41:15.841919 [Byte1]: 43
8611 11:41:15.846327
8612 11:41:15.846408 Set Vref, RX VrefLevel [Byte0]: 44
8613 11:41:15.849535 [Byte1]: 44
8614 11:41:15.853746
8615 11:41:15.853860 Set Vref, RX VrefLevel [Byte0]: 45
8616 11:41:15.857055 [Byte1]: 45
8617 11:41:15.861608
8618 11:41:15.861690 Set Vref, RX VrefLevel [Byte0]: 46
8619 11:41:15.864703 [Byte1]: 46
8620 11:41:15.868701
8621 11:41:15.868834 Set Vref, RX VrefLevel [Byte0]: 47
8622 11:41:15.872661 [Byte1]: 47
8623 11:41:15.876614
8624 11:41:15.876710 Set Vref, RX VrefLevel [Byte0]: 48
8625 11:41:15.879943 [Byte1]: 48
8626 11:41:15.884031
8627 11:41:15.884114 Set Vref, RX VrefLevel [Byte0]: 49
8628 11:41:15.887391 [Byte1]: 49
8629 11:41:15.891876
8630 11:41:15.891959 Set Vref, RX VrefLevel [Byte0]: 50
8631 11:41:15.894587 [Byte1]: 50
8632 11:41:15.899256
8633 11:41:15.899339 Set Vref, RX VrefLevel [Byte0]: 51
8634 11:41:15.902123 [Byte1]: 51
8635 11:41:15.906402
8636 11:41:15.906486 Set Vref, RX VrefLevel [Byte0]: 52
8637 11:41:15.910171 [Byte1]: 52
8638 11:41:15.914463
8639 11:41:15.914545 Set Vref, RX VrefLevel [Byte0]: 53
8640 11:41:15.917680 [Byte1]: 53
8641 11:41:15.921393
8642 11:41:15.921476 Set Vref, RX VrefLevel [Byte0]: 54
8643 11:41:15.924995 [Byte1]: 54
8644 11:41:15.929484
8645 11:41:15.929566 Set Vref, RX VrefLevel [Byte0]: 55
8646 11:41:15.932683 [Byte1]: 55
8647 11:41:15.936692
8648 11:41:15.936774 Set Vref, RX VrefLevel [Byte0]: 56
8649 11:41:15.939927 [Byte1]: 56
8650 11:41:15.944065
8651 11:41:15.944147 Set Vref, RX VrefLevel [Byte0]: 57
8652 11:41:15.947361 [Byte1]: 57
8653 11:41:15.951828
8654 11:41:15.951910 Set Vref, RX VrefLevel [Byte0]: 58
8655 11:41:15.954924 [Byte1]: 58
8656 11:41:15.959277
8657 11:41:15.959359 Set Vref, RX VrefLevel [Byte0]: 59
8658 11:41:15.962594 [Byte1]: 59
8659 11:41:15.967013
8660 11:41:15.967096 Set Vref, RX VrefLevel [Byte0]: 60
8661 11:41:15.970162 [Byte1]: 60
8662 11:41:15.974333
8663 11:41:15.974418 Set Vref, RX VrefLevel [Byte0]: 61
8664 11:41:15.977840 [Byte1]: 61
8665 11:41:15.981674
8666 11:41:15.981758 Set Vref, RX VrefLevel [Byte0]: 62
8667 11:41:15.985640 [Byte1]: 62
8668 11:41:15.989649
8669 11:41:15.989732 Set Vref, RX VrefLevel [Byte0]: 63
8670 11:41:15.993028 [Byte1]: 63
8671 11:41:15.997043
8672 11:41:15.997127 Set Vref, RX VrefLevel [Byte0]: 64
8673 11:41:16.000204 [Byte1]: 64
8674 11:41:16.004642
8675 11:41:16.004778 Set Vref, RX VrefLevel [Byte0]: 65
8676 11:41:16.007873 [Byte1]: 65
8677 11:41:16.012000
8678 11:41:16.012104 Set Vref, RX VrefLevel [Byte0]: 66
8679 11:41:16.015695 [Byte1]: 66
8680 11:41:16.019414
8681 11:41:16.019523 Set Vref, RX VrefLevel [Byte0]: 67
8682 11:41:16.022697 [Byte1]: 67
8683 11:41:16.026979
8684 11:41:16.027084 Set Vref, RX VrefLevel [Byte0]: 68
8685 11:41:16.030684 [Byte1]: 68
8686 11:41:16.035021
8687 11:41:16.035121 Set Vref, RX VrefLevel [Byte0]: 69
8688 11:41:16.038252 [Byte1]: 69
8689 11:41:16.042204
8690 11:41:16.042275 Set Vref, RX VrefLevel [Byte0]: 70
8691 11:41:16.045445 [Byte1]: 70
8692 11:41:16.050016
8693 11:41:16.050088 Set Vref, RX VrefLevel [Byte0]: 71
8694 11:41:16.053344 [Byte1]: 71
8695 11:41:16.057399
8696 11:41:16.057470 Set Vref, RX VrefLevel [Byte0]: 72
8697 11:41:16.060559 [Byte1]: 72
8698 11:41:16.064721
8699 11:41:16.064799 Set Vref, RX VrefLevel [Byte0]: 73
8700 11:41:16.068067 [Byte1]: 73
8701 11:41:16.072594
8702 11:41:16.072695 Final RX Vref Byte 0 = 57 to rank0
8703 11:41:16.076128 Final RX Vref Byte 1 = 55 to rank0
8704 11:41:16.079239 Final RX Vref Byte 0 = 57 to rank1
8705 11:41:16.082348 Final RX Vref Byte 1 = 55 to rank1==
8706 11:41:16.085464 Dram Type= 6, Freq= 0, CH_1, rank 0
8707 11:41:16.092063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8708 11:41:16.092136 ==
8709 11:41:16.092198 DQS Delay:
8710 11:41:16.092257 DQS0 = 0, DQS1 = 0
8711 11:41:16.095450 DQM Delay:
8712 11:41:16.095521 DQM0 = 134, DQM1 = 131
8713 11:41:16.098781 DQ Delay:
8714 11:41:16.102588 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8715 11:41:16.105225 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8716 11:41:16.109040 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8717 11:41:16.112297 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8718 11:41:16.112365
8719 11:41:16.112425
8720 11:41:16.112482
8721 11:41:16.115747 [DramC_TX_OE_Calibration] TA2
8722 11:41:16.118510 Original DQ_B0 (3 6) =30, OEN = 27
8723 11:41:16.122313 Original DQ_B1 (3 6) =30, OEN = 27
8724 11:41:16.125417 24, 0x0, End_B0=24 End_B1=24
8725 11:41:16.125521 25, 0x0, End_B0=25 End_B1=25
8726 11:41:16.128597 26, 0x0, End_B0=26 End_B1=26
8727 11:41:16.131873 27, 0x0, End_B0=27 End_B1=27
8728 11:41:16.135574 28, 0x0, End_B0=28 End_B1=28
8729 11:41:16.138433 29, 0x0, End_B0=29 End_B1=29
8730 11:41:16.138518 30, 0x0, End_B0=30 End_B1=30
8731 11:41:16.142114 31, 0x4141, End_B0=30 End_B1=30
8732 11:41:16.145509 Byte0 end_step=30 best_step=27
8733 11:41:16.148747 Byte1 end_step=30 best_step=27
8734 11:41:16.152067 Byte0 TX OE(2T, 0.5T) = (3, 3)
8735 11:41:16.155490 Byte1 TX OE(2T, 0.5T) = (3, 3)
8736 11:41:16.155574
8737 11:41:16.155640
8738 11:41:16.162032 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8739 11:41:16.165276 CH1 RK0: MR19=303, MR18=1623
8740 11:41:16.171940 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8741 11:41:16.172052
8742 11:41:16.174981 ----->DramcWriteLeveling(PI) begin...
8743 11:41:16.175066 ==
8744 11:41:16.178532 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 11:41:16.182050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 11:41:16.182135 ==
8747 11:41:16.185104 Write leveling (Byte 0): 25 => 25
8748 11:41:16.188579 Write leveling (Byte 1): 29 => 29
8749 11:41:16.191573 DramcWriteLeveling(PI) end<-----
8750 11:41:16.191657
8751 11:41:16.191723 ==
8752 11:41:16.195599 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 11:41:16.198757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8754 11:41:16.199195 ==
8755 11:41:16.202393 [Gating] SW mode calibration
8756 11:41:16.208742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8757 11:41:16.215321 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8758 11:41:16.218350 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 11:41:16.224892 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 11:41:16.228722 1 4 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8761 11:41:16.231828 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 11:41:16.238489 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 11:41:16.241682 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 11:41:16.244889 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 11:41:16.248483 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 11:41:16.255091 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 11:41:16.258835 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8768 11:41:16.261994 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8769 11:41:16.268788 1 5 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 1)
8770 11:41:16.271780 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 11:41:16.275069 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 11:41:16.281768 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 11:41:16.284855 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 11:41:16.288053 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 11:41:16.294530 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 11:41:16.298316 1 6 8 | B1->B0 | 3333 2323 | 1 0 | (0 0) (0 0)
8777 11:41:16.301289 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8778 11:41:16.308465 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 11:41:16.311740 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 11:41:16.315161 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 11:41:16.321810 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 11:41:16.324726 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 11:41:16.328079 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8784 11:41:16.334801 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8785 11:41:16.337912 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8786 11:41:16.341394 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:41:16.348267 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:41:16.351414 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:41:16.354634 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:41:16.361179 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:41:16.364527 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:41:16.367844 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 11:41:16.374350 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 11:41:16.377793 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 11:41:16.381602 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 11:41:16.384595 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 11:41:16.391369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 11:41:16.394753 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 11:41:16.397708 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8800 11:41:16.404740 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8801 11:41:16.408319 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8802 11:41:16.411130 Total UI for P1: 0, mck2ui 16
8803 11:41:16.414430 best dqsien dly found for B1: ( 1, 9, 6)
8804 11:41:16.417765 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8805 11:41:16.424349 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 11:41:16.424799 Total UI for P1: 0, mck2ui 16
8807 11:41:16.431371 best dqsien dly found for B0: ( 1, 9, 14)
8808 11:41:16.434781 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8809 11:41:16.437779 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8810 11:41:16.438186
8811 11:41:16.441324 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8812 11:41:16.444542 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8813 11:41:16.447978 [Gating] SW calibration Done
8814 11:41:16.448512 ==
8815 11:41:16.451023 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 11:41:16.454746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 11:41:16.455192 ==
8818 11:41:16.457831 RX Vref Scan: 0
8819 11:41:16.458287
8820 11:41:16.458678 RX Vref 0 -> 0, step: 1
8821 11:41:16.459121
8822 11:41:16.461591 RX Delay 0 -> 252, step: 8
8823 11:41:16.464754 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8824 11:41:16.471192 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8825 11:41:16.474616 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8826 11:41:16.477883 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8827 11:41:16.481276 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8828 11:41:16.484505 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8829 11:41:16.487714 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8830 11:41:16.494547 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8831 11:41:16.498323 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8832 11:41:16.501209 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8833 11:41:16.504423 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8834 11:41:16.507617 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8835 11:41:16.514828 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8836 11:41:16.517955 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8837 11:41:16.521102 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8838 11:41:16.524416 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8839 11:41:16.524900 ==
8840 11:41:16.527735 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 11:41:16.534342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 11:41:16.534776 ==
8843 11:41:16.535136 DQS Delay:
8844 11:41:16.538004 DQS0 = 0, DQS1 = 0
8845 11:41:16.538447 DQM Delay:
8846 11:41:16.541244 DQM0 = 136, DQM1 = 133
8847 11:41:16.541673 DQ Delay:
8848 11:41:16.544332 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8849 11:41:16.548010 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8850 11:41:16.551106 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8851 11:41:16.554709 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8852 11:41:16.555142
8853 11:41:16.555507
8854 11:41:16.555827 ==
8855 11:41:16.557975 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 11:41:16.564704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 11:41:16.565181 ==
8858 11:41:16.565527
8859 11:41:16.565894
8860 11:41:16.566242 TX Vref Scan disable
8861 11:41:16.567842 == TX Byte 0 ==
8862 11:41:16.571206 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8863 11:41:16.574760 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8864 11:41:16.578172 == TX Byte 1 ==
8865 11:41:16.580868 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8866 11:41:16.584618 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8867 11:41:16.587913 ==
8868 11:41:16.591288 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 11:41:16.594231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 11:41:16.594688 ==
8871 11:41:16.607504
8872 11:41:16.610982 TX Vref early break, caculate TX vref
8873 11:41:16.614187 TX Vref=16, minBit 0, minWin=23, winSum=384
8874 11:41:16.618000 TX Vref=18, minBit 0, minWin=23, winSum=391
8875 11:41:16.621268 TX Vref=20, minBit 0, minWin=23, winSum=403
8876 11:41:16.624154 TX Vref=22, minBit 0, minWin=24, winSum=409
8877 11:41:16.627554 TX Vref=24, minBit 2, minWin=25, winSum=419
8878 11:41:16.634131 TX Vref=26, minBit 0, minWin=25, winSum=425
8879 11:41:16.637428 TX Vref=28, minBit 0, minWin=25, winSum=424
8880 11:41:16.640797 TX Vref=30, minBit 0, minWin=25, winSum=419
8881 11:41:16.644487 TX Vref=32, minBit 0, minWin=25, winSum=414
8882 11:41:16.647621 TX Vref=34, minBit 0, minWin=24, winSum=405
8883 11:41:16.650768 TX Vref=36, minBit 6, minWin=23, winSum=397
8884 11:41:16.657435 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8885 11:41:16.657900
8886 11:41:16.661119 Final TX Range 0 Vref 26
8887 11:41:16.661696
8888 11:41:16.662364 ==
8889 11:41:16.664174 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 11:41:16.667941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 11:41:16.668517 ==
8892 11:41:16.669040
8893 11:41:16.669479
8894 11:41:16.670912 TX Vref Scan disable
8895 11:41:16.677780 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8896 11:41:16.678394 == TX Byte 0 ==
8897 11:41:16.681047 u2DelayCellOfst[0]=16 cells (5 PI)
8898 11:41:16.684335 u2DelayCellOfst[1]=13 cells (4 PI)
8899 11:41:16.687656 u2DelayCellOfst[2]=0 cells (0 PI)
8900 11:41:16.690907 u2DelayCellOfst[3]=6 cells (2 PI)
8901 11:41:16.694214 u2DelayCellOfst[4]=10 cells (3 PI)
8902 11:41:16.697335 u2DelayCellOfst[5]=16 cells (5 PI)
8903 11:41:16.701060 u2DelayCellOfst[6]=16 cells (5 PI)
8904 11:41:16.704307 u2DelayCellOfst[7]=6 cells (2 PI)
8905 11:41:16.707565 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8906 11:41:16.710935 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8907 11:41:16.714072 == TX Byte 1 ==
8908 11:41:16.717701 u2DelayCellOfst[8]=0 cells (0 PI)
8909 11:41:16.718320 u2DelayCellOfst[9]=3 cells (1 PI)
8910 11:41:16.720908 u2DelayCellOfst[10]=10 cells (3 PI)
8911 11:41:16.723691 u2DelayCellOfst[11]=6 cells (2 PI)
8912 11:41:16.727609 u2DelayCellOfst[12]=13 cells (4 PI)
8913 11:41:16.730642 u2DelayCellOfst[13]=16 cells (5 PI)
8914 11:41:16.733996 u2DelayCellOfst[14]=16 cells (5 PI)
8915 11:41:16.737243 u2DelayCellOfst[15]=16 cells (5 PI)
8916 11:41:16.740501 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8917 11:41:16.747133 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8918 11:41:16.747728 DramC Write-DBI on
8919 11:41:16.748234 ==
8920 11:41:16.750903 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 11:41:16.757099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 11:41:16.757656 ==
8923 11:41:16.758187
8924 11:41:16.758666
8925 11:41:16.759139 TX Vref Scan disable
8926 11:41:16.760655 == TX Byte 0 ==
8927 11:41:16.764040 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8928 11:41:16.767863 == TX Byte 1 ==
8929 11:41:16.770997 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8930 11:41:16.774202 DramC Write-DBI off
8931 11:41:16.774703
8932 11:41:16.775202 [DATLAT]
8933 11:41:16.775745 Freq=1600, CH1 RK1
8934 11:41:16.776259
8935 11:41:16.777204 DATLAT Default: 0xf
8936 11:41:16.777662 0, 0xFFFF, sum = 0
8937 11:41:16.780969 1, 0xFFFF, sum = 0
8938 11:41:16.784157 2, 0xFFFF, sum = 0
8939 11:41:16.784596 3, 0xFFFF, sum = 0
8940 11:41:16.787281 4, 0xFFFF, sum = 0
8941 11:41:16.787721 5, 0xFFFF, sum = 0
8942 11:41:16.790611 6, 0xFFFF, sum = 0
8943 11:41:16.791052 7, 0xFFFF, sum = 0
8944 11:41:16.794024 8, 0xFFFF, sum = 0
8945 11:41:16.794464 9, 0xFFFF, sum = 0
8946 11:41:16.797834 10, 0xFFFF, sum = 0
8947 11:41:16.798275 11, 0xFFFF, sum = 0
8948 11:41:16.800964 12, 0xFFFF, sum = 0
8949 11:41:16.801438 13, 0xFFFF, sum = 0
8950 11:41:16.804057 14, 0x0, sum = 1
8951 11:41:16.804498 15, 0x0, sum = 2
8952 11:41:16.807436 16, 0x0, sum = 3
8953 11:41:16.807877 17, 0x0, sum = 4
8954 11:41:16.810862 best_step = 15
8955 11:41:16.811293
8956 11:41:16.811724 ==
8957 11:41:16.814095 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 11:41:16.817213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 11:41:16.817649 ==
8960 11:41:16.821107 RX Vref Scan: 0
8961 11:41:16.821646
8962 11:41:16.822077 RX Vref 0 -> 0, step: 1
8963 11:41:16.822567
8964 11:41:16.824314 RX Delay 19 -> 252, step: 4
8965 11:41:16.827565 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8966 11:41:16.833854 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8967 11:41:16.837528 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8968 11:41:16.841013 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8969 11:41:16.844241 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8970 11:41:16.847572 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8971 11:41:16.850849 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8972 11:41:16.857251 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8973 11:41:16.860769 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8974 11:41:16.864245 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8975 11:41:16.867274 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8976 11:41:16.870473 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8977 11:41:16.877238 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8978 11:41:16.880255 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8979 11:41:16.883747 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8980 11:41:16.887466 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8981 11:41:16.890559 ==
8982 11:41:16.890979 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 11:41:16.897038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 11:41:16.897496 ==
8985 11:41:16.897835 DQS Delay:
8986 11:41:16.900286 DQS0 = 0, DQS1 = 0
8987 11:41:16.900719 DQM Delay:
8988 11:41:16.903586 DQM0 = 133, DQM1 = 130
8989 11:41:16.904005 DQ Delay:
8990 11:41:16.906775 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =128
8991 11:41:16.910679 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8992 11:41:16.913955 DQ8 =116, DQ9 =120, DQ10 =130, DQ11 =124
8993 11:41:16.917219 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8994 11:41:16.917644
8995 11:41:16.917979
8996 11:41:16.918293
8997 11:41:16.920446 [DramC_TX_OE_Calibration] TA2
8998 11:41:16.923545 Original DQ_B0 (3 6) =30, OEN = 27
8999 11:41:16.926642 Original DQ_B1 (3 6) =30, OEN = 27
9000 11:41:16.930408 24, 0x0, End_B0=24 End_B1=24
9001 11:41:16.933831 25, 0x0, End_B0=25 End_B1=25
9002 11:41:16.934261 26, 0x0, End_B0=26 End_B1=26
9003 11:41:16.936758 27, 0x0, End_B0=27 End_B1=27
9004 11:41:16.939864 28, 0x0, End_B0=28 End_B1=28
9005 11:41:16.943649 29, 0x0, End_B0=29 End_B1=29
9006 11:41:16.944085 30, 0x0, End_B0=30 End_B1=30
9007 11:41:16.946881 31, 0x5151, End_B0=30 End_B1=30
9008 11:41:16.950367 Byte0 end_step=30 best_step=27
9009 11:41:16.953718 Byte1 end_step=30 best_step=27
9010 11:41:16.956891 Byte0 TX OE(2T, 0.5T) = (3, 3)
9011 11:41:16.960247 Byte1 TX OE(2T, 0.5T) = (3, 3)
9012 11:41:16.960670
9013 11:41:16.961061
9014 11:41:16.966569 [DQSOSCAuto] RK1, (LSB)MR18= 0x2005, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
9015 11:41:16.969618 CH1 RK1: MR19=303, MR18=2005
9016 11:41:16.976001 CH1_RK1: MR19=0x303, MR18=0x2005, DQSOSC=393, MR23=63, INC=23, DEC=15
9017 11:41:16.979524 [RxdqsGatingPostProcess] freq 1600
9018 11:41:16.985732 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9019 11:41:16.985815 best DQS0 dly(2T, 0.5T) = (1, 1)
9020 11:41:16.989415 best DQS1 dly(2T, 0.5T) = (1, 1)
9021 11:41:16.992310 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9022 11:41:16.996169 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9023 11:41:16.999271 best DQS0 dly(2T, 0.5T) = (1, 1)
9024 11:41:17.002477 best DQS1 dly(2T, 0.5T) = (1, 1)
9025 11:41:17.005879 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9026 11:41:17.009247 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9027 11:41:17.012298 Pre-setting of DQS Precalculation
9028 11:41:17.015675 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9029 11:41:17.026126 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9030 11:41:17.032457 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9031 11:41:17.032539
9032 11:41:17.032605
9033 11:41:17.035830 [Calibration Summary] 3200 Mbps
9034 11:41:17.035913 CH 0, Rank 0
9035 11:41:17.039009 SW Impedance : PASS
9036 11:41:17.039092 DUTY Scan : NO K
9037 11:41:17.042830 ZQ Calibration : PASS
9038 11:41:17.046059 Jitter Meter : NO K
9039 11:41:17.046142 CBT Training : PASS
9040 11:41:17.049232 Write leveling : PASS
9041 11:41:17.052298 RX DQS gating : PASS
9042 11:41:17.052381 RX DQ/DQS(RDDQC) : PASS
9043 11:41:17.055651 TX DQ/DQS : PASS
9044 11:41:17.058967 RX DATLAT : PASS
9045 11:41:17.059050 RX DQ/DQS(Engine): PASS
9046 11:41:17.062206 TX OE : PASS
9047 11:41:17.062289 All Pass.
9048 11:41:17.062355
9049 11:41:17.065696 CH 0, Rank 1
9050 11:41:17.065779 SW Impedance : PASS
9051 11:41:17.068728 DUTY Scan : NO K
9052 11:41:17.068873 ZQ Calibration : PASS
9053 11:41:17.072496 Jitter Meter : NO K
9054 11:41:17.075898 CBT Training : PASS
9055 11:41:17.075981 Write leveling : PASS
9056 11:41:17.078840 RX DQS gating : PASS
9057 11:41:17.082691 RX DQ/DQS(RDDQC) : PASS
9058 11:41:17.082774 TX DQ/DQS : PASS
9059 11:41:17.085866 RX DATLAT : PASS
9060 11:41:17.089034 RX DQ/DQS(Engine): PASS
9061 11:41:17.089117 TX OE : PASS
9062 11:41:17.092494 All Pass.
9063 11:41:17.092576
9064 11:41:17.092641 CH 1, Rank 0
9065 11:41:17.095522 SW Impedance : PASS
9066 11:41:17.095605 DUTY Scan : NO K
9067 11:41:17.098678 ZQ Calibration : PASS
9068 11:41:17.102511 Jitter Meter : NO K
9069 11:41:17.102594 CBT Training : PASS
9070 11:41:17.105516 Write leveling : PASS
9071 11:41:17.108772 RX DQS gating : PASS
9072 11:41:17.108880 RX DQ/DQS(RDDQC) : PASS
9073 11:41:17.112002 TX DQ/DQS : PASS
9074 11:41:17.112085 RX DATLAT : PASS
9075 11:41:17.115932 RX DQ/DQS(Engine): PASS
9076 11:41:17.119042 TX OE : PASS
9077 11:41:17.119125 All Pass.
9078 11:41:17.119191
9079 11:41:17.119250 CH 1, Rank 1
9080 11:41:17.122360 SW Impedance : PASS
9081 11:41:17.125765 DUTY Scan : NO K
9082 11:41:17.125851 ZQ Calibration : PASS
9083 11:41:17.128987 Jitter Meter : NO K
9084 11:41:17.132292 CBT Training : PASS
9085 11:41:17.132374 Write leveling : PASS
9086 11:41:17.135393 RX DQS gating : PASS
9087 11:41:17.138664 RX DQ/DQS(RDDQC) : PASS
9088 11:41:17.138747 TX DQ/DQS : PASS
9089 11:41:17.141894 RX DATLAT : PASS
9090 11:41:17.145703 RX DQ/DQS(Engine): PASS
9091 11:41:17.145791 TX OE : PASS
9092 11:41:17.148781 All Pass.
9093 11:41:17.148911
9094 11:41:17.148995 DramC Write-DBI on
9095 11:41:17.151886 PER_BANK_REFRESH: Hybrid Mode
9096 11:41:17.151970 TX_TRACKING: ON
9097 11:41:17.162119 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9098 11:41:17.172056 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9099 11:41:17.178976 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9100 11:41:17.182100 [FAST_K] Save calibration result to emmc
9101 11:41:17.185246 sync common calibartion params.
9102 11:41:17.185330 sync cbt_mode0:1, 1:1
9103 11:41:17.188467 dram_init: ddr_geometry: 2
9104 11:41:17.192293 dram_init: ddr_geometry: 2
9105 11:41:17.192376 dram_init: ddr_geometry: 2
9106 11:41:17.195091 0:dram_rank_size:100000000
9107 11:41:17.198357 1:dram_rank_size:100000000
9108 11:41:17.204965 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9109 11:41:17.205050 DFS_SHUFFLE_HW_MODE: ON
9110 11:41:17.208193 dramc_set_vcore_voltage set vcore to 725000
9111 11:41:17.212144 Read voltage for 1600, 0
9112 11:41:17.212228 Vio18 = 0
9113 11:41:17.215261 Vcore = 725000
9114 11:41:17.215345 Vdram = 0
9115 11:41:17.215411 Vddq = 0
9116 11:41:17.218765 Vmddr = 0
9117 11:41:17.218847 switch to 3200 Mbps bootup
9118 11:41:17.221634 [DramcRunTimeConfig]
9119 11:41:17.221717 PHYPLL
9120 11:41:17.224703 DPM_CONTROL_AFTERK: ON
9121 11:41:17.224834 PER_BANK_REFRESH: ON
9122 11:41:17.228149 REFRESH_OVERHEAD_REDUCTION: ON
9123 11:41:17.231402 CMD_PICG_NEW_MODE: OFF
9124 11:41:17.231478 XRTWTW_NEW_MODE: ON
9125 11:41:17.234861 XRTRTR_NEW_MODE: ON
9126 11:41:17.234945 TX_TRACKING: ON
9127 11:41:17.238068 RDSEL_TRACKING: OFF
9128 11:41:17.241848 DQS Precalculation for DVFS: ON
9129 11:41:17.241930 RX_TRACKING: OFF
9130 11:41:17.244506 HW_GATING DBG: ON
9131 11:41:17.244589 ZQCS_ENABLE_LP4: ON
9132 11:41:17.248503 RX_PICG_NEW_MODE: ON
9133 11:41:17.248586 TX_PICG_NEW_MODE: ON
9134 11:41:17.251682 ENABLE_RX_DCM_DPHY: ON
9135 11:41:17.254579 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9136 11:41:17.258573 DUMMY_READ_FOR_TRACKING: OFF
9137 11:41:17.258682 !!! SPM_CONTROL_AFTERK: OFF
9138 11:41:17.261715 !!! SPM could not control APHY
9139 11:41:17.264888 IMPEDANCE_TRACKING: ON
9140 11:41:17.264988 TEMP_SENSOR: ON
9141 11:41:17.268149 HW_SAVE_FOR_SR: OFF
9142 11:41:17.271336 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9143 11:41:17.274678 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9144 11:41:17.278059 Read ODT Tracking: ON
9145 11:41:17.278148 Refresh Rate DeBounce: ON
9146 11:41:17.281278 DFS_NO_QUEUE_FLUSH: ON
9147 11:41:17.285053 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9148 11:41:17.288317 ENABLE_DFS_RUNTIME_MRW: OFF
9149 11:41:17.288399 DDR_RESERVE_NEW_MODE: ON
9150 11:41:17.291496 MR_CBT_SWITCH_FREQ: ON
9151 11:41:17.294377 =========================
9152 11:41:17.311608 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9153 11:41:17.314860 dram_init: ddr_geometry: 2
9154 11:41:17.333687 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9155 11:41:17.336994 dram_init: dram init end (result: 0)
9156 11:41:17.343625 DRAM-K: Full calibration passed in 24403 msecs
9157 11:41:17.346787 MRC: failed to locate region type 0.
9158 11:41:17.346871 DRAM rank0 size:0x100000000,
9159 11:41:17.350160 DRAM rank1 size=0x100000000
9160 11:41:17.359769 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9161 11:41:17.366762 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9162 11:41:17.373246 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9163 11:41:17.379788 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9164 11:41:17.383090 DRAM rank0 size:0x100000000,
9165 11:41:17.386493 DRAM rank1 size=0x100000000
9166 11:41:17.386576 CBMEM:
9167 11:41:17.390234 IMD: root @ 0xfffff000 254 entries.
9168 11:41:17.393381 IMD: root @ 0xffffec00 62 entries.
9169 11:41:17.396430 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9170 11:41:17.399594 WARNING: RO_VPD is uninitialized or empty.
9171 11:41:17.406518 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9172 11:41:17.413337 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9173 11:41:17.426374 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9174 11:41:17.437522 BS: romstage times (exec / console): total (unknown) / 23941 ms
9175 11:41:17.437607
9176 11:41:17.437673
9177 11:41:17.447380 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9178 11:41:17.451048 ARM64: Exception handlers installed.
9179 11:41:17.454484 ARM64: Testing exception
9180 11:41:17.457636 ARM64: Done test exception
9181 11:41:17.457720 Enumerating buses...
9182 11:41:17.461061 Show all devs... Before device enumeration.
9183 11:41:17.464155 Root Device: enabled 1
9184 11:41:17.467239 CPU_CLUSTER: 0: enabled 1
9185 11:41:17.467322 CPU: 00: enabled 1
9186 11:41:17.470484 Compare with tree...
9187 11:41:17.470568 Root Device: enabled 1
9188 11:41:17.474270 CPU_CLUSTER: 0: enabled 1
9189 11:41:17.477288 CPU: 00: enabled 1
9190 11:41:17.477372 Root Device scanning...
9191 11:41:17.480640 scan_static_bus for Root Device
9192 11:41:17.484470 CPU_CLUSTER: 0 enabled
9193 11:41:17.487223 scan_static_bus for Root Device done
9194 11:41:17.491125 scan_bus: bus Root Device finished in 8 msecs
9195 11:41:17.491208 done
9196 11:41:17.497615 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9197 11:41:17.501233 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9198 11:41:17.507320 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9199 11:41:17.511006 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9200 11:41:17.514091 Allocating resources...
9201 11:41:17.517284 Reading resources...
9202 11:41:17.521037 Root Device read_resources bus 0 link: 0
9203 11:41:17.521121 DRAM rank0 size:0x100000000,
9204 11:41:17.524087 DRAM rank1 size=0x100000000
9205 11:41:17.527597 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9206 11:41:17.530715 CPU: 00 missing read_resources
9207 11:41:17.533813 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9208 11:41:17.540771 Root Device read_resources bus 0 link: 0 done
9209 11:41:17.540890 Done reading resources.
9210 11:41:17.547150 Show resources in subtree (Root Device)...After reading.
9211 11:41:17.550265 Root Device child on link 0 CPU_CLUSTER: 0
9212 11:41:17.554202 CPU_CLUSTER: 0 child on link 0 CPU: 00
9213 11:41:17.563915 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9214 11:41:17.563994 CPU: 00
9215 11:41:17.567125 Root Device assign_resources, bus 0 link: 0
9216 11:41:17.570401 CPU_CLUSTER: 0 missing set_resources
9217 11:41:17.573810 Root Device assign_resources, bus 0 link: 0 done
9218 11:41:17.577071 Done setting resources.
9219 11:41:17.583994 Show resources in subtree (Root Device)...After assigning values.
9220 11:41:17.587383 Root Device child on link 0 CPU_CLUSTER: 0
9221 11:41:17.590625 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 11:41:17.600500 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 11:41:17.600583 CPU: 00
9224 11:41:17.603661 Done allocating resources.
9225 11:41:17.607067 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9226 11:41:17.610164 Enabling resources...
9227 11:41:17.610246 done.
9228 11:41:17.616775 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9229 11:41:17.616921 Initializing devices...
9230 11:41:17.620607 Root Device init
9231 11:41:17.620681 init hardware done!
9232 11:41:17.623596 0x00000018: ctrlr->caps
9233 11:41:17.626924 52.000 MHz: ctrlr->f_max
9234 11:41:17.627008 0.400 MHz: ctrlr->f_min
9235 11:41:17.630551 0x40ff8080: ctrlr->voltages
9236 11:41:17.630635 sclk: 390625
9237 11:41:17.633457 Bus Width = 1
9238 11:41:17.633539 sclk: 390625
9239 11:41:17.637101 Bus Width = 1
9240 11:41:17.637186 Early init status = 3
9241 11:41:17.643359 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9242 11:41:17.646497 in-header: 03 fc 00 00 01 00 00 00
9243 11:41:17.650270 in-data: 00
9244 11:41:17.653621 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9245 11:41:17.658746 in-header: 03 fd 00 00 00 00 00 00
9246 11:41:17.662039 in-data:
9247 11:41:17.664572 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9248 11:41:17.669182 in-header: 03 fc 00 00 01 00 00 00
9249 11:41:17.672635 in-data: 00
9250 11:41:17.675911 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9251 11:41:17.681490 in-header: 03 fd 00 00 00 00 00 00
9252 11:41:17.684665 in-data:
9253 11:41:17.687924 [SSUSB] Setting up USB HOST controller...
9254 11:41:17.691714 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9255 11:41:17.695161 [SSUSB] phy power-on done.
9256 11:41:17.698336 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9257 11:41:17.705039 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9258 11:41:17.708224 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9259 11:41:17.714693 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9260 11:41:17.721601 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9261 11:41:17.727871 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9262 11:41:17.734568 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9263 11:41:17.741440 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9264 11:41:17.741523 SPM: binary array size = 0x9dc
9265 11:41:17.747926 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9266 11:41:17.755184 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9267 11:41:17.761158 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9268 11:41:17.764396 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9269 11:41:17.771055 configure_display: Starting display init
9270 11:41:17.805037 anx7625_power_on_init: Init interface.
9271 11:41:17.808297 anx7625_disable_pd_protocol: Disabled PD feature.
9272 11:41:17.811554 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9273 11:41:17.838773 anx7625_start_dp_work: Secure OCM version=00
9274 11:41:17.842508 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9275 11:41:17.857139 sp_tx_get_edid_block: EDID Block = 1
9276 11:41:17.959869 Extracted contents:
9277 11:41:17.962974 header: 00 ff ff ff ff ff ff 00
9278 11:41:17.966579 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9279 11:41:17.969837 version: 01 04
9280 11:41:17.972950 basic params: 95 1f 11 78 0a
9281 11:41:17.976593 chroma info: 76 90 94 55 54 90 27 21 50 54
9282 11:41:17.979877 established: 00 00 00
9283 11:41:17.986427 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9284 11:41:17.989632 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9285 11:41:17.996648 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9286 11:41:18.003021 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9287 11:41:18.009407 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9288 11:41:18.012604 extensions: 00
9289 11:41:18.012686 checksum: fb
9290 11:41:18.012752
9291 11:41:18.016409 Manufacturer: IVO Model 57d Serial Number 0
9292 11:41:18.019529 Made week 0 of 2020
9293 11:41:18.019612 EDID version: 1.4
9294 11:41:18.022818 Digital display
9295 11:41:18.026078 6 bits per primary color channel
9296 11:41:18.026163 DisplayPort interface
9297 11:41:18.029499 Maximum image size: 31 cm x 17 cm
9298 11:41:18.032647 Gamma: 220%
9299 11:41:18.032754 Check DPMS levels
9300 11:41:18.036016 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9301 11:41:18.039356 First detailed timing is preferred timing
9302 11:41:18.042398 Established timings supported:
9303 11:41:18.046160 Standard timings supported:
9304 11:41:18.049181 Detailed timings
9305 11:41:18.052908 Hex of detail: 383680a07038204018303c0035ae10000019
9306 11:41:18.055830 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9307 11:41:18.062464 0780 0798 07c8 0820 hborder 0
9308 11:41:18.066196 0438 043b 0447 0458 vborder 0
9309 11:41:18.069235 -hsync -vsync
9310 11:41:18.069342 Did detailed timing
9311 11:41:18.075992 Hex of detail: 000000000000000000000000000000000000
9312 11:41:18.076077 Manufacturer-specified data, tag 0
9313 11:41:18.082718 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9314 11:41:18.085663 ASCII string: InfoVision
9315 11:41:18.088968 Hex of detail: 000000fe00523134304e574635205248200a
9316 11:41:18.092717 ASCII string: R140NWF5 RH
9317 11:41:18.092861 Checksum
9318 11:41:18.092929 Checksum: 0xfb (valid)
9319 11:41:18.099512 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9320 11:41:18.102599 DSI data_rate: 832800000 bps
9321 11:41:18.105595 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9322 11:41:18.112704 anx7625_parse_edid: pixelclock(138800).
9323 11:41:18.115903 hactive(1920), hsync(48), hfp(24), hbp(88)
9324 11:41:18.119299 vactive(1080), vsync(12), vfp(3), vbp(17)
9325 11:41:18.122468 anx7625_dsi_config: config dsi.
9326 11:41:18.128814 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9327 11:41:18.142099 anx7625_dsi_config: success to config DSI
9328 11:41:18.145519 anx7625_dp_start: MIPI phy setup OK.
9329 11:41:18.148555 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9330 11:41:18.151670 mtk_ddp_mode_set invalid vrefresh 60
9331 11:41:18.154945 main_disp_path_setup
9332 11:41:18.155025 ovl_layer_smi_id_en
9333 11:41:18.158658 ovl_layer_smi_id_en
9334 11:41:18.158738 ccorr_config
9335 11:41:18.158802 aal_config
9336 11:41:18.161766 gamma_config
9337 11:41:18.161844 postmask_config
9338 11:41:18.165457 dither_config
9339 11:41:18.168508 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9340 11:41:18.175302 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9341 11:41:18.178437 Root Device init finished in 555 msecs
9342 11:41:18.178519 CPU_CLUSTER: 0 init
9343 11:41:18.188183 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9344 11:41:18.191117 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9345 11:41:18.194768 APU_MBOX 0x190000b0 = 0x10001
9346 11:41:18.198097 APU_MBOX 0x190001b0 = 0x10001
9347 11:41:18.201340 APU_MBOX 0x190005b0 = 0x10001
9348 11:41:18.204637 APU_MBOX 0x190006b0 = 0x10001
9349 11:41:18.207853 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9350 11:41:18.221015 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9351 11:41:18.233304 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9352 11:41:18.240013 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9353 11:41:18.251708 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9354 11:41:18.260377 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9355 11:41:18.264214 CPU_CLUSTER: 0 init finished in 81 msecs
9356 11:41:18.267208 Devices initialized
9357 11:41:18.270833 Show all devs... After init.
9358 11:41:18.270928 Root Device: enabled 1
9359 11:41:18.273840 CPU_CLUSTER: 0: enabled 1
9360 11:41:18.276961 CPU: 00: enabled 1
9361 11:41:18.280593 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9362 11:41:18.283772 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9363 11:41:18.287399 ELOG: NV offset 0x57f000 size 0x1000
9364 11:41:18.293528 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9365 11:41:18.300267 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9366 11:41:18.303955 ELOG: Event(17) added with size 13 at 2023-06-15 11:41:03 UTC
9367 11:41:18.310611 out: cmd=0x121: 03 db 21 01 00 00 00 00
9368 11:41:18.313828 in-header: 03 0b 00 00 2c 00 00 00
9369 11:41:18.323273 in-data: 54 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 11:41:18.330291 ELOG: Event(A1) added with size 10 at 2023-06-15 11:41:03 UTC
9371 11:41:18.336796 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9372 11:41:18.343315 ELOG: Event(A0) added with size 9 at 2023-06-15 11:41:03 UTC
9373 11:41:18.346671 elog_add_boot_reason: Logged dev mode boot
9374 11:41:18.350157 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9375 11:41:18.353290 Finalize devices...
9376 11:41:18.356438 Devices finalized
9377 11:41:18.359604 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9378 11:41:18.362986 Writing coreboot table at 0xffe64000
9379 11:41:18.366492 0. 000000000010a000-0000000000113fff: RAMSTAGE
9380 11:41:18.369552 1. 0000000040000000-00000000400fffff: RAM
9381 11:41:18.376635 2. 0000000040100000-000000004032afff: RAMSTAGE
9382 11:41:18.379787 3. 000000004032b000-00000000545fffff: RAM
9383 11:41:18.383250 4. 0000000054600000-000000005465ffff: BL31
9384 11:41:18.386415 5. 0000000054660000-00000000ffe63fff: RAM
9385 11:41:18.393242 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9386 11:41:18.396217 7. 0000000100000000-000000023fffffff: RAM
9387 11:41:18.399733 Passing 5 GPIOs to payload:
9388 11:41:18.402938 NAME | PORT | POLARITY | VALUE
9389 11:41:18.406553 EC in RW | 0x000000aa | low | undefined
9390 11:41:18.413385 EC interrupt | 0x00000005 | low | undefined
9391 11:41:18.416101 TPM interrupt | 0x000000ab | high | undefined
9392 11:41:18.423065 SD card detect | 0x00000011 | high | undefined
9393 11:41:18.426239 speaker enable | 0x00000093 | high | undefined
9394 11:41:18.429424 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9395 11:41:18.433301 in-header: 03 f9 00 00 02 00 00 00
9396 11:41:18.436595 in-data: 02 00
9397 11:41:18.436676 ADC[4]: Raw value=903988 ID=7
9398 11:41:18.439526 ADC[3]: Raw value=213441 ID=1
9399 11:41:18.442940 RAM Code: 0x71
9400 11:41:18.443022 ADC[6]: Raw value=75701 ID=0
9401 11:41:18.446317 ADC[5]: Raw value=213072 ID=1
9402 11:41:18.449423 SKU Code: 0x1
9403 11:41:18.452752 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9404 11:41:18.455912 coreboot table: 964 bytes.
9405 11:41:18.459331 IMD ROOT 0. 0xfffff000 0x00001000
9406 11:41:18.462611 IMD SMALL 1. 0xffffe000 0x00001000
9407 11:41:18.465989 RO MCACHE 2. 0xffffc000 0x00001104
9408 11:41:18.469178 CONSOLE 3. 0xfff7c000 0x00080000
9409 11:41:18.473052 FMAP 4. 0xfff7b000 0x00000452
9410 11:41:18.476247 TIME STAMP 5. 0xfff7a000 0x00000910
9411 11:41:18.479564 VBOOT WORK 6. 0xfff66000 0x00014000
9412 11:41:18.482637 RAMOOPS 7. 0xffe66000 0x00100000
9413 11:41:18.485913 COREBOOT 8. 0xffe64000 0x00002000
9414 11:41:18.485996 IMD small region:
9415 11:41:18.492619 IMD ROOT 0. 0xffffec00 0x00000400
9416 11:41:18.496690 VPD 1. 0xffffeba0 0x0000004c
9417 11:41:18.499715 MMC STATUS 2. 0xffffeb80 0x00000004
9418 11:41:18.502768 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9419 11:41:18.506313 Probing TPM: done!
9420 11:41:18.509396 Connected to device vid:did:rid of 1ae0:0028:00
9421 11:41:18.519700 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9422 11:41:18.523131 Initialized TPM device CR50 revision 0
9423 11:41:18.526658 Checking cr50 for pending updates
9424 11:41:18.530467 Reading cr50 TPM mode
9425 11:41:18.538781 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9426 11:41:18.545626 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9427 11:41:18.585931 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9428 11:41:18.589999 Checking segment from ROM address 0x40100000
9429 11:41:18.593020 Checking segment from ROM address 0x4010001c
9430 11:41:18.599311 Loading segment from ROM address 0x40100000
9431 11:41:18.599484 code (compression=0)
9432 11:41:18.609263 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9433 11:41:18.615998 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9434 11:41:18.616202 it's not compressed!
9435 11:41:18.622609 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9436 11:41:18.625610 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9437 11:41:18.646393 Loading segment from ROM address 0x4010001c
9438 11:41:18.646785 Entry Point 0x80000000
9439 11:41:18.650284 Loaded segments
9440 11:41:18.653411 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9441 11:41:18.660167 Jumping to boot code at 0x80000000(0xffe64000)
9442 11:41:18.666767 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9443 11:41:18.673558 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9444 11:41:18.680910 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9445 11:41:18.684589 Checking segment from ROM address 0x40100000
9446 11:41:18.687971 Checking segment from ROM address 0x4010001c
9447 11:41:18.694575 Loading segment from ROM address 0x40100000
9448 11:41:18.695050 code (compression=1)
9449 11:41:18.701267 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9450 11:41:18.711184 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9451 11:41:18.711823 using LZMA
9452 11:41:18.719477 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9453 11:41:18.725592 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9454 11:41:18.729268 Loading segment from ROM address 0x4010001c
9455 11:41:18.729872 Entry Point 0x54601000
9456 11:41:18.732672 Loaded segments
9457 11:41:18.735526 NOTICE: MT8192 bl31_setup
9458 11:41:18.743008 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9459 11:41:18.746115 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9460 11:41:18.749382 WARNING: region 0:
9461 11:41:18.752520 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 11:41:18.753098 WARNING: region 1:
9463 11:41:18.759779 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9464 11:41:18.762786 WARNING: region 2:
9465 11:41:18.766324 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9466 11:41:18.769511 WARNING: region 3:
9467 11:41:18.772842 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9468 11:41:18.776130 WARNING: region 4:
9469 11:41:18.783191 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9470 11:41:18.783725 WARNING: region 5:
9471 11:41:18.786050 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9472 11:41:18.789773 WARNING: region 6:
9473 11:41:18.793305 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 11:41:18.796181 WARNING: region 7:
9475 11:41:18.799395 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 11:41:18.806113 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9477 11:41:18.810028 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9478 11:41:18.813121 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9479 11:41:18.819618 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9480 11:41:18.823071 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9481 11:41:18.826265 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9482 11:41:18.833197 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9483 11:41:18.836118 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9484 11:41:18.839723 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9485 11:41:18.846314 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9486 11:41:18.849650 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9487 11:41:18.856676 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9488 11:41:18.860047 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9489 11:41:18.862980 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9490 11:41:18.869887 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9491 11:41:18.873052 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9492 11:41:18.876454 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9493 11:41:18.883652 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9494 11:41:18.887169 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9495 11:41:18.890109 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9496 11:41:18.896514 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9497 11:41:18.899886 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9498 11:41:18.907118 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9499 11:41:18.909787 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9500 11:41:18.913733 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9501 11:41:18.920277 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9502 11:41:18.923702 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9503 11:41:18.929850 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9504 11:41:18.933666 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9505 11:41:18.936534 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9506 11:41:18.943903 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9507 11:41:18.947046 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9508 11:41:18.950276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9509 11:41:18.956800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9510 11:41:18.959957 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9511 11:41:18.963657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9512 11:41:18.966926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9513 11:41:18.973496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9514 11:41:18.977117 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9515 11:41:18.980360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9516 11:41:18.983458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9517 11:41:18.990490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9518 11:41:18.993477 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9519 11:41:18.996858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9520 11:41:19.000020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9521 11:41:19.007035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9522 11:41:19.010480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9523 11:41:19.013811 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9524 11:41:19.020609 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9525 11:41:19.023992 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9526 11:41:19.026988 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9527 11:41:19.033559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9528 11:41:19.036832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9529 11:41:19.043546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9530 11:41:19.046899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9531 11:41:19.049837 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9532 11:41:19.056682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9533 11:41:19.060466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9534 11:41:19.066857 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9535 11:41:19.069804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9536 11:41:19.076777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9537 11:41:19.080145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9538 11:41:19.086348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9539 11:41:19.089608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9540 11:41:19.092943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9541 11:41:19.100235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9542 11:41:19.103440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9543 11:41:19.110359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9544 11:41:19.112940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9545 11:41:19.120254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9546 11:41:19.123373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9547 11:41:19.126659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9548 11:41:19.133490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9549 11:41:19.136750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9550 11:41:19.143224 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9551 11:41:19.146364 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9552 11:41:19.153172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9553 11:41:19.156998 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9554 11:41:19.160140 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9555 11:41:19.166438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9556 11:41:19.170169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9557 11:41:19.176668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9558 11:41:19.180639 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9559 11:41:19.186553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9560 11:41:19.190326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9561 11:41:19.193629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9562 11:41:19.200449 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9563 11:41:19.203826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9564 11:41:19.210611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9565 11:41:19.214001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9566 11:41:19.216952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9567 11:41:19.223605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9568 11:41:19.226967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9569 11:41:19.233454 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9570 11:41:19.237448 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9571 11:41:19.243441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9572 11:41:19.247373 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9573 11:41:19.250558 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9574 11:41:19.253808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9575 11:41:19.260700 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9576 11:41:19.263805 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9577 11:41:19.266926 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9578 11:41:19.274141 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9579 11:41:19.277324 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9580 11:41:19.283813 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9581 11:41:19.287939 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9582 11:41:19.290807 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9583 11:41:19.297533 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9584 11:41:19.300636 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9585 11:41:19.304335 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9586 11:41:19.310907 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9587 11:41:19.314126 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9588 11:41:19.321172 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9589 11:41:19.324490 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9590 11:41:19.327751 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9591 11:41:19.334271 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9592 11:41:19.337445 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9593 11:41:19.341444 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9594 11:41:19.347556 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9595 11:41:19.351469 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9596 11:41:19.354831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9597 11:41:19.357915 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9598 11:41:19.361130 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9599 11:41:19.368079 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9600 11:41:19.371202 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9601 11:41:19.377649 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9602 11:41:19.381380 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9603 11:41:19.384297 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9604 11:41:19.391544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9605 11:41:19.394627 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9606 11:41:19.400785 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9607 11:41:19.404687 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9608 11:41:19.407735 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9609 11:41:19.414361 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9610 11:41:19.417539 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9611 11:41:19.421327 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9612 11:41:19.428024 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9613 11:41:19.431178 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9614 11:41:19.437843 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9615 11:41:19.440908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9616 11:41:19.444235 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9617 11:41:19.451532 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9618 11:41:19.454639 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9619 11:41:19.461430 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9620 11:41:19.464615 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9621 11:41:19.467803 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9622 11:41:19.474548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9623 11:41:19.478276 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9624 11:41:19.481476 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9625 11:41:19.488150 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9626 11:41:19.491432 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9627 11:41:19.494589 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9628 11:41:19.501435 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9629 11:41:19.504512 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9630 11:41:19.511466 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9631 11:41:19.514726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9632 11:41:19.521369 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9633 11:41:19.524610 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9634 11:41:19.527693 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9635 11:41:19.534275 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9636 11:41:19.537593 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9637 11:41:19.541460 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9638 11:41:19.547840 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9639 11:41:19.551180 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9640 11:41:19.557741 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9641 11:41:19.561073 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9642 11:41:19.564280 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9643 11:41:19.571190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9644 11:41:19.574477 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9645 11:41:19.580578 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9646 11:41:19.584551 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9647 11:41:19.587570 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9648 11:41:19.594447 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9649 11:41:19.598189 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9650 11:41:19.603944 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9651 11:41:19.607440 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9652 11:41:19.610832 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9653 11:41:19.617245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9654 11:41:19.620566 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9655 11:41:19.623966 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9656 11:41:19.630710 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9657 11:41:19.634144 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9658 11:41:19.640722 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9659 11:41:19.643928 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9660 11:41:19.650346 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9661 11:41:19.653558 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9662 11:41:19.656907 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9663 11:41:19.663997 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9664 11:41:19.667396 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9665 11:41:19.673840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9666 11:41:19.677078 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9667 11:41:19.680273 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9668 11:41:19.687372 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9669 11:41:19.690124 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9670 11:41:19.697117 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9671 11:41:19.700141 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9672 11:41:19.703381 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9673 11:41:19.710003 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9674 11:41:19.713983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9675 11:41:19.720465 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9676 11:41:19.723810 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9677 11:41:19.729994 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9678 11:41:19.733316 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9679 11:41:19.736520 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9680 11:41:19.743126 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9681 11:41:19.747053 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9682 11:41:19.753335 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9683 11:41:19.756702 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9684 11:41:19.760035 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9685 11:41:19.766690 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9686 11:41:19.770099 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9687 11:41:19.776527 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9688 11:41:19.780028 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9689 11:41:19.786669 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9690 11:41:19.789753 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9691 11:41:19.792764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9692 11:41:19.799277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9693 11:41:19.803166 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9694 11:41:19.809335 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9695 11:41:19.813071 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9696 11:41:19.819900 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9697 11:41:19.823328 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9698 11:41:19.826538 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9699 11:41:19.832478 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9700 11:41:19.835886 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9701 11:41:19.842914 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9702 11:41:19.846240 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9703 11:41:19.849351 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9704 11:41:19.855944 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9705 11:41:19.859885 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9706 11:41:19.862764 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9707 11:41:19.865940 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9708 11:41:19.872724 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9709 11:41:19.875942 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9710 11:41:19.879248 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9711 11:41:19.886006 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9712 11:41:19.889306 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9713 11:41:19.892565 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9714 11:41:19.899251 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9715 11:41:19.903028 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9716 11:41:19.906367 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9717 11:41:19.912611 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9718 11:41:19.915841 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9719 11:41:19.919620 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9720 11:41:19.926674 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9721 11:41:19.929620 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9722 11:41:19.935789 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9723 11:41:19.939642 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9724 11:41:19.943001 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9725 11:41:19.949407 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9726 11:41:19.952773 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9727 11:41:19.955590 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9728 11:41:19.962398 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9729 11:41:19.966209 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9730 11:41:19.969567 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9731 11:41:19.976085 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9732 11:41:19.979435 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9733 11:41:19.986051 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9734 11:41:19.989301 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9735 11:41:19.992621 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9736 11:41:19.999226 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9737 11:41:20.002412 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9738 11:41:20.005572 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9739 11:41:20.012370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9740 11:41:20.015682 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9741 11:41:20.018841 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9742 11:41:20.025711 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9743 11:41:20.028710 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9744 11:41:20.032342 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9745 11:41:20.038807 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9746 11:41:20.042065 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9747 11:41:20.045505 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9748 11:41:20.048698 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9749 11:41:20.051948 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9750 11:41:20.058848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9751 11:41:20.061984 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9752 11:41:20.065655 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9753 11:41:20.071987 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9754 11:41:20.075266 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9755 11:41:20.078556 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9756 11:41:20.082497 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9757 11:41:20.089223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9758 11:41:20.092393 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9759 11:41:20.099060 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9760 11:41:20.102342 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9761 11:41:20.105478 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9762 11:41:20.112516 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9763 11:41:20.115511 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9764 11:41:20.122312 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9765 11:41:20.125457 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9766 11:41:20.128640 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9767 11:41:20.135692 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9768 11:41:20.138471 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9769 11:41:20.145731 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9770 11:41:20.148941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9771 11:41:20.151988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9772 11:41:20.158861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9773 11:41:20.161994 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9774 11:41:20.168692 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9775 11:41:20.171713 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9776 11:41:20.175218 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9777 11:41:20.181748 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9778 11:41:20.185116 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9779 11:41:20.191732 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9780 11:41:20.195116 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9781 11:41:20.198341 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9782 11:41:20.205030 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9783 11:41:20.208437 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9784 11:41:20.215201 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9785 11:41:20.218799 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9786 11:41:20.224830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9787 11:41:20.228535 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9788 11:41:20.231644 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9789 11:41:20.238555 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9790 11:41:20.241899 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9791 11:41:20.248447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9792 11:41:20.251638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9793 11:41:20.254901 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9794 11:41:20.261501 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9795 11:41:20.265321 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9796 11:41:20.271615 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9797 11:41:20.274878 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9798 11:41:20.278055 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9799 11:41:20.284795 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9800 11:41:20.288097 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9801 11:41:20.294656 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9802 11:41:20.297960 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9803 11:41:20.301941 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9804 11:41:20.308677 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9805 11:41:20.312022 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9806 11:41:20.318480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9807 11:41:20.321775 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9808 11:41:20.325010 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9809 11:41:20.331842 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9810 11:41:20.334832 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9811 11:41:20.341567 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9812 11:41:20.344616 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9813 11:41:20.348337 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9814 11:41:20.354656 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9815 11:41:20.358197 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9816 11:41:20.364672 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9817 11:41:20.368399 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9818 11:41:20.374995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9819 11:41:20.378378 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9820 11:41:20.381585 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9821 11:41:20.388415 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9822 11:41:20.391881 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9823 11:41:20.395039 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9824 11:41:20.401766 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9825 11:41:20.405086 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9826 11:41:20.411660 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9827 11:41:20.415043 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9828 11:41:20.421706 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9829 11:41:20.424963 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9830 11:41:20.428373 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9831 11:41:20.435373 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9832 11:41:20.438422 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9833 11:41:20.445133 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9834 11:41:20.448427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9835 11:41:20.454683 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9836 11:41:20.457935 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9837 11:41:20.461705 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9838 11:41:20.467987 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9839 11:41:20.471164 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9840 11:41:20.478253 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9841 11:41:20.481315 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9842 11:41:20.488210 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9843 11:41:20.491358 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9844 11:41:20.494475 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9845 11:41:20.500981 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9846 11:41:20.505014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9847 11:41:20.511161 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9848 11:41:20.514900 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9849 11:41:20.520975 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9850 11:41:20.525043 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9851 11:41:20.528314 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9852 11:41:20.534880 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9853 11:41:20.537998 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9854 11:41:20.544329 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9855 11:41:20.547948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9856 11:41:20.554538 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9857 11:41:20.557542 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9858 11:41:20.560782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9859 11:41:20.567384 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9860 11:41:20.571251 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9861 11:41:20.577949 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9862 11:41:20.580696 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9863 11:41:20.587631 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9864 11:41:20.590785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9865 11:41:20.598002 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9866 11:41:20.601064 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9867 11:41:20.604167 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9868 11:41:20.610946 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9869 11:41:20.614227 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9870 11:41:20.620785 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9871 11:41:20.624151 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9872 11:41:20.630873 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9873 11:41:20.634179 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9874 11:41:20.637491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9875 11:41:20.644098 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9876 11:41:20.647715 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9877 11:41:20.654002 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9878 11:41:20.657840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9879 11:41:20.660968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9880 11:41:20.667954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9881 11:41:20.670875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9882 11:41:20.677901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9883 11:41:20.680824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9884 11:41:20.687338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9885 11:41:20.691377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9886 11:41:20.697859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9887 11:41:20.700736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9888 11:41:20.707397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9889 11:41:20.711175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9890 11:41:20.717797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9891 11:41:20.721055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9892 11:41:20.727667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9893 11:41:20.730973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9894 11:41:20.737536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9895 11:41:20.740440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9896 11:41:20.747187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9897 11:41:20.750213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9898 11:41:20.754005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9899 11:41:20.760783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9900 11:41:20.763890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9901 11:41:20.770550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9902 11:41:20.773764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9903 11:41:20.780506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9904 11:41:20.783567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9905 11:41:20.790523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9906 11:41:20.797045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9907 11:41:20.800316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9908 11:41:20.807252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9909 11:41:20.810671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9910 11:41:20.813402 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9911 11:41:20.817134 INFO: [APUAPC] vio 0
9912 11:41:20.820474 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9913 11:41:20.826699 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9914 11:41:20.830702 INFO: [APUAPC] D0_APC_0: 0x400510
9915 11:41:20.833261 INFO: [APUAPC] D0_APC_1: 0x0
9916 11:41:20.836658 INFO: [APUAPC] D0_APC_2: 0x1540
9917 11:41:20.836741 INFO: [APUAPC] D0_APC_3: 0x0
9918 11:41:20.840082 INFO: [APUAPC] D1_APC_0: 0xffffffff
9919 11:41:20.843545 INFO: [APUAPC] D1_APC_1: 0xffffffff
9920 11:41:20.846753 INFO: [APUAPC] D1_APC_2: 0x3fffff
9921 11:41:20.850122 INFO: [APUAPC] D1_APC_3: 0x0
9922 11:41:20.853335 INFO: [APUAPC] D2_APC_0: 0xffffffff
9923 11:41:20.856761 INFO: [APUAPC] D2_APC_1: 0xffffffff
9924 11:41:20.860545 INFO: [APUAPC] D2_APC_2: 0x3fffff
9925 11:41:20.863596 INFO: [APUAPC] D2_APC_3: 0x0
9926 11:41:20.866743 INFO: [APUAPC] D3_APC_0: 0xffffffff
9927 11:41:20.869985 INFO: [APUAPC] D3_APC_1: 0xffffffff
9928 11:41:20.873531 INFO: [APUAPC] D3_APC_2: 0x3fffff
9929 11:41:20.876549 INFO: [APUAPC] D3_APC_3: 0x0
9930 11:41:20.879806 INFO: [APUAPC] D4_APC_0: 0xffffffff
9931 11:41:20.883441 INFO: [APUAPC] D4_APC_1: 0xffffffff
9932 11:41:20.886544 INFO: [APUAPC] D4_APC_2: 0x3fffff
9933 11:41:20.890269 INFO: [APUAPC] D4_APC_3: 0x0
9934 11:41:20.893323 INFO: [APUAPC] D5_APC_0: 0xffffffff
9935 11:41:20.896515 INFO: [APUAPC] D5_APC_1: 0xffffffff
9936 11:41:20.900291 INFO: [APUAPC] D5_APC_2: 0x3fffff
9937 11:41:20.903622 INFO: [APUAPC] D5_APC_3: 0x0
9938 11:41:20.906323 INFO: [APUAPC] D6_APC_0: 0xffffffff
9939 11:41:20.910178 INFO: [APUAPC] D6_APC_1: 0xffffffff
9940 11:41:20.913367 INFO: [APUAPC] D6_APC_2: 0x3fffff
9941 11:41:20.916671 INFO: [APUAPC] D6_APC_3: 0x0
9942 11:41:20.919873 INFO: [APUAPC] D7_APC_0: 0xffffffff
9943 11:41:20.923212 INFO: [APUAPC] D7_APC_1: 0xffffffff
9944 11:41:20.926348 INFO: [APUAPC] D7_APC_2: 0x3fffff
9945 11:41:20.929959 INFO: [APUAPC] D7_APC_3: 0x0
9946 11:41:20.933364 INFO: [APUAPC] D8_APC_0: 0xffffffff
9947 11:41:20.936642 INFO: [APUAPC] D8_APC_1: 0xffffffff
9948 11:41:20.940075 INFO: [APUAPC] D8_APC_2: 0x3fffff
9949 11:41:20.943324 INFO: [APUAPC] D8_APC_3: 0x0
9950 11:41:20.946642 INFO: [APUAPC] D9_APC_0: 0xffffffff
9951 11:41:20.950050 INFO: [APUAPC] D9_APC_1: 0xffffffff
9952 11:41:20.953317 INFO: [APUAPC] D9_APC_2: 0x3fffff
9953 11:41:20.956681 INFO: [APUAPC] D9_APC_3: 0x0
9954 11:41:20.960068 INFO: [APUAPC] D10_APC_0: 0xffffffff
9955 11:41:20.963352 INFO: [APUAPC] D10_APC_1: 0xffffffff
9956 11:41:20.966470 INFO: [APUAPC] D10_APC_2: 0x3fffff
9957 11:41:20.969601 INFO: [APUAPC] D10_APC_3: 0x0
9958 11:41:20.972642 INFO: [APUAPC] D11_APC_0: 0xffffffff
9959 11:41:20.976355 INFO: [APUAPC] D11_APC_1: 0xffffffff
9960 11:41:20.979342 INFO: [APUAPC] D11_APC_2: 0x3fffff
9961 11:41:20.983051 INFO: [APUAPC] D11_APC_3: 0x0
9962 11:41:20.986292 INFO: [APUAPC] D12_APC_0: 0xffffffff
9963 11:41:20.989316 INFO: [APUAPC] D12_APC_1: 0xffffffff
9964 11:41:20.993191 INFO: [APUAPC] D12_APC_2: 0x3fffff
9965 11:41:20.996185 INFO: [APUAPC] D12_APC_3: 0x0
9966 11:41:20.999691 INFO: [APUAPC] D13_APC_0: 0xffffffff
9967 11:41:21.002821 INFO: [APUAPC] D13_APC_1: 0xffffffff
9968 11:41:21.006027 INFO: [APUAPC] D13_APC_2: 0x3fffff
9969 11:41:21.009845 INFO: [APUAPC] D13_APC_3: 0x0
9970 11:41:21.013141 INFO: [APUAPC] D14_APC_0: 0xffffffff
9971 11:41:21.016428 INFO: [APUAPC] D14_APC_1: 0xffffffff
9972 11:41:21.019543 INFO: [APUAPC] D14_APC_2: 0x3fffff
9973 11:41:21.022831 INFO: [APUAPC] D14_APC_3: 0x0
9974 11:41:21.026087 INFO: [APUAPC] D15_APC_0: 0xffffffff
9975 11:41:21.029340 INFO: [APUAPC] D15_APC_1: 0xffffffff
9976 11:41:21.032587 INFO: [APUAPC] D15_APC_2: 0x3fffff
9977 11:41:21.036117 INFO: [APUAPC] D15_APC_3: 0x0
9978 11:41:21.039281 INFO: [APUAPC] APC_CON: 0x4
9979 11:41:21.042516 INFO: [NOCDAPC] D0_APC_0: 0x0
9980 11:41:21.042599 INFO: [NOCDAPC] D0_APC_1: 0x0
9981 11:41:21.045826 INFO: [NOCDAPC] D1_APC_0: 0x0
9982 11:41:21.049148 INFO: [NOCDAPC] D1_APC_1: 0xfff
9983 11:41:21.052541 INFO: [NOCDAPC] D2_APC_0: 0x0
9984 11:41:21.055919 INFO: [NOCDAPC] D2_APC_1: 0xfff
9985 11:41:21.059255 INFO: [NOCDAPC] D3_APC_0: 0x0
9986 11:41:21.062522 INFO: [NOCDAPC] D3_APC_1: 0xfff
9987 11:41:21.066437 INFO: [NOCDAPC] D4_APC_0: 0x0
9988 11:41:21.069788 INFO: [NOCDAPC] D4_APC_1: 0xfff
9989 11:41:21.073031 INFO: [NOCDAPC] D5_APC_0: 0x0
9990 11:41:21.073113 INFO: [NOCDAPC] D5_APC_1: 0xfff
9991 11:41:21.076088 INFO: [NOCDAPC] D6_APC_0: 0x0
9992 11:41:21.079334 INFO: [NOCDAPC] D6_APC_1: 0xfff
9993 11:41:21.082563 INFO: [NOCDAPC] D7_APC_0: 0x0
9994 11:41:21.086152 INFO: [NOCDAPC] D7_APC_1: 0xfff
9995 11:41:21.089327 INFO: [NOCDAPC] D8_APC_0: 0x0
9996 11:41:21.092930 INFO: [NOCDAPC] D8_APC_1: 0xfff
9997 11:41:21.096501 INFO: [NOCDAPC] D9_APC_0: 0x0
9998 11:41:21.099713 INFO: [NOCDAPC] D9_APC_1: 0xfff
9999 11:41:21.102795 INFO: [NOCDAPC] D10_APC_0: 0x0
10000 11:41:21.105941 INFO: [NOCDAPC] D10_APC_1: 0xfff
10001 11:41:21.106030 INFO: [NOCDAPC] D11_APC_0: 0x0
10002 11:41:21.109304 INFO: [NOCDAPC] D11_APC_1: 0xfff
10003 11:41:21.113079 INFO: [NOCDAPC] D12_APC_0: 0x0
10004 11:41:21.116372 INFO: [NOCDAPC] D12_APC_1: 0xfff
10005 11:41:21.119702 INFO: [NOCDAPC] D13_APC_0: 0x0
10006 11:41:21.122786 INFO: [NOCDAPC] D13_APC_1: 0xfff
10007 11:41:21.125891 INFO: [NOCDAPC] D14_APC_0: 0x0
10008 11:41:21.129024 INFO: [NOCDAPC] D14_APC_1: 0xfff
10009 11:41:21.132380 INFO: [NOCDAPC] D15_APC_0: 0x0
10010 11:41:21.135616 INFO: [NOCDAPC] D15_APC_1: 0xfff
10011 11:41:21.139405 INFO: [NOCDAPC] APC_CON: 0x4
10012 11:41:21.142611 INFO: [APUAPC] set_apusys_apc done
10013 11:41:21.145682 INFO: [DEVAPC] devapc_init done
10014 11:41:21.149011 INFO: GICv3 without legacy support detected.
10015 11:41:21.152377 INFO: ARM GICv3 driver initialized in EL3
10016 11:41:21.155637 INFO: Maximum SPI INTID supported: 639
10017 11:41:21.162046 INFO: BL31: Initializing runtime services
10018 11:41:21.165596 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10019 11:41:21.168690 INFO: SPM: enable CPC mode
10020 11:41:21.175457 INFO: mcdi ready for mcusys-off-idle and system suspend
10021 11:41:21.179279 INFO: BL31: Preparing for EL3 exit to normal world
10022 11:41:21.182363 INFO: Entry point address = 0x80000000
10023 11:41:21.185544 INFO: SPSR = 0x8
10024 11:41:21.190648
10025 11:41:21.190730
10026 11:41:21.190796
10027 11:41:21.193751 Starting depthcharge on Spherion...
10028 11:41:21.193833
10029 11:41:21.193899 Wipe memory regions:
10030 11:41:21.193961
10031 11:41:21.194561 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10032 11:41:21.194663 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10033 11:41:21.194746 Setting prompt string to ['asurada:']
10034 11:41:21.194827 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10035 11:41:21.196929 [0x00000040000000, 0x00000054600000)
10036 11:41:21.319358
10037 11:41:21.319495 [0x00000054660000, 0x00000080000000)
10038 11:41:21.580418
10039 11:41:21.580557 [0x000000821a7280, 0x000000ffe64000)
10040 11:41:22.324718
10041 11:41:22.324924 [0x00000100000000, 0x00000240000000)
10042 11:41:24.214881
10043 11:41:24.218108 Initializing XHCI USB controller at 0x11200000.
10044 11:41:25.256531
10045 11:41:25.259603 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10046 11:41:25.259698
10047 11:41:25.259767
10048 11:41:25.259829
10049 11:41:25.260112 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10051 11:41:25.360564 asurada: tftpboot 192.168.201.1 10742228/tftp-deploy-t5m_fu4a/kernel/image.itb 10742228/tftp-deploy-t5m_fu4a/kernel/cmdline
10052 11:41:25.360703 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 11:41:25.360810 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10054 11:41:25.365313 tftpboot 192.168.201.1 10742228/tftp-deploy-t5m_fu4a/kernel/image.ittp-deploy-t5m_fu4a/kernel/cmdline
10055 11:41:25.365400
10056 11:41:25.365466 Waiting for link
10057 11:41:25.523737
10058 11:41:25.523896 R8152: Initializing
10059 11:41:25.523965
10060 11:41:25.526682 Version 9 (ocp_data = 6010)
10061 11:41:25.526766
10062 11:41:25.530064 R8152: Done initializing
10063 11:41:25.530147
10064 11:41:25.530213 Adding net device
10065 11:41:27.404664
10066 11:41:27.404823 done.
10067 11:41:27.404894
10068 11:41:27.404956 MAC: 00:e0:4c:78:7a:aa
10069 11:41:27.405016
10070 11:41:27.407938 Sending DHCP discover... done.
10071 11:41:27.408023
10072 11:41:27.411711 Waiting for reply... done.
10073 11:41:27.411794
10074 11:41:27.414708 Sending DHCP request... done.
10075 11:41:27.414845
10076 11:41:27.418763 Waiting for reply... done.
10077 11:41:27.418872
10078 11:41:27.418967 My ip is 192.168.201.12
10079 11:41:27.419039
10080 11:41:27.422406 The DHCP server ip is 192.168.201.1
10081 11:41:27.422490
10082 11:41:27.428583 TFTP server IP predefined by user: 192.168.201.1
10083 11:41:27.428692
10084 11:41:27.435546 Bootfile predefined by user: 10742228/tftp-deploy-t5m_fu4a/kernel/image.itb
10085 11:41:27.435630
10086 11:41:27.435697 Sending tftp read request... done.
10087 11:41:27.438554
10088 11:41:27.442295 Waiting for the transfer...
10089 11:41:27.442379
10090 11:41:27.726904 00000000 ################################################################
10091 11:41:27.727057
10092 11:41:27.984210 00080000 ################################################################
10093 11:41:27.984360
10094 11:41:28.245846 00100000 ################################################################
10095 11:41:28.246027
10096 11:41:28.505775 00180000 ################################################################
10097 11:41:28.505912
10098 11:41:28.758612 00200000 ################################################################
10099 11:41:28.758755
10100 11:41:29.023140 00280000 ################################################################
10101 11:41:29.023281
10102 11:41:29.284785 00300000 ################################################################
10103 11:41:29.284959
10104 11:41:29.544914 00380000 ################################################################
10105 11:41:29.545052
10106 11:41:29.809431 00400000 ################################################################
10107 11:41:29.809581
10108 11:41:30.074410 00480000 ################################################################
10109 11:41:30.074549
10110 11:41:30.336594 00500000 ################################################################
10111 11:41:30.336726
10112 11:41:30.595609 00580000 ################################################################
10113 11:41:30.595744
10114 11:41:30.861592 00600000 ################################################################
10115 11:41:30.861729
10116 11:41:31.119707 00680000 ################################################################
10117 11:41:31.119845
10118 11:41:31.372502 00700000 ################################################################
10119 11:41:31.372667
10120 11:41:31.626998 00780000 ################################################################
10121 11:41:31.627179
10122 11:41:31.884767 00800000 ################################################################
10123 11:41:31.884953
10124 11:41:32.148916 00880000 ################################################################
10125 11:41:32.149069
10126 11:41:32.404433 00900000 ################################################################
10127 11:41:32.404584
10128 11:41:32.658867 00980000 ################################################################
10129 11:41:32.659020
10130 11:41:32.913860 00a00000 ################################################################
10131 11:41:32.914015
10132 11:41:33.175483 00a80000 ################################################################
10133 11:41:33.175645
10134 11:41:33.433350 00b00000 ################################################################
10135 11:41:33.433502
10136 11:41:33.687588 00b80000 ################################################################
10137 11:41:33.687734
10138 11:41:33.939305 00c00000 ################################################################
10139 11:41:33.939454
10140 11:41:34.192636 00c80000 ################################################################
10141 11:41:34.192816
10142 11:41:34.447260 00d00000 ################################################################
10143 11:41:34.447441
10144 11:41:34.703900 00d80000 ################################################################
10145 11:41:34.704073
10146 11:41:34.959092 00e00000 ################################################################
10147 11:41:34.959267
10148 11:41:35.212845 00e80000 ################################################################
10149 11:41:35.213018
10150 11:41:35.466963 00f00000 ################################################################
10151 11:41:35.467131
10152 11:41:35.736671 00f80000 ################################################################
10153 11:41:35.736854
10154 11:41:36.004736 01000000 ################################################################
10155 11:41:36.004923
10156 11:41:36.281157 01080000 ################################################################
10157 11:41:36.281346
10158 11:41:36.565984 01100000 ################################################################
10159 11:41:36.566138
10160 11:41:36.832681 01180000 ################################################################
10161 11:41:36.832841
10162 11:41:37.091456 01200000 ################################################################
10163 11:41:37.091604
10164 11:41:37.370852 01280000 ################################################################
10165 11:41:37.371026
10166 11:41:37.641943 01300000 ################################################################
10167 11:41:37.642117
10168 11:41:37.906431 01380000 ################################################################
10169 11:41:37.906606
10170 11:41:38.160945 01400000 ################################################################
10171 11:41:38.161088
10172 11:41:38.415230 01480000 ################################################################
10173 11:41:38.415399
10174 11:41:38.676711 01500000 ################################################################
10175 11:41:38.676890
10176 11:41:38.963237 01580000 ################################################################
10177 11:41:38.963411
10178 11:41:39.217218 01600000 ################################################################
10179 11:41:39.217367
10180 11:41:39.472971 01680000 ################################################################
10181 11:41:39.473119
10182 11:41:39.727329 01700000 ################################################################
10183 11:41:39.727478
10184 11:41:39.979448 01780000 ################################################################
10185 11:41:39.979596
10186 11:41:40.234424 01800000 ################################################################
10187 11:41:40.234574
10188 11:41:40.488135 01880000 ################################################################
10189 11:41:40.488292
10190 11:41:40.745238 01900000 ################################################################
10191 11:41:40.745395
10192 11:41:41.017375 01980000 ################################################################
10193 11:41:41.017552
10194 11:41:41.270155 01a00000 ################################################################
10195 11:41:41.270303
10196 11:41:41.438473 01a80000 ########################################### done.
10197 11:41:41.438651
10198 11:41:41.441486 The bootfile was 28134230 bytes long.
10199 11:41:41.441564
10200 11:41:41.445483 Sending tftp read request... done.
10201 11:41:41.445589
10202 11:41:41.448581 Waiting for the transfer...
10203 11:41:41.448686
10204 11:41:41.448777 00000000 # done.
10205 11:41:41.448913
10206 11:41:41.458209 Command line loaded dynamically from TFTP file: 10742228/tftp-deploy-t5m_fu4a/kernel/cmdline
10207 11:41:41.458320
10208 11:41:41.474821 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742228/extract-nfsrootfs-kz1ohlq0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10209 11:41:41.474934
10210 11:41:41.475029 Loading FIT.
10211 11:41:41.475119
10212 11:41:41.477940 Image ramdisk-1 has 17641909 bytes.
10213 11:41:41.478015
10214 11:41:41.481656 Image fdt-1 has 46924 bytes.
10215 11:41:41.481748
10216 11:41:41.485040 Image kernel-1 has 10443363 bytes.
10217 11:41:41.485114
10218 11:41:41.491421 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10219 11:41:41.494753
10220 11:41:41.511671 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10221 11:41:41.511783
10222 11:41:41.514775 Choosing best match conf-1 for compat google,spherion-rev2.
10223 11:41:41.520330
10224 11:41:41.524581 Connected to device vid:did:rid of 1ae0:0028:00
10225 11:41:41.533109
10226 11:41:41.536186 tpm_get_response: command 0x17b, return code 0x0
10227 11:41:41.536288
10228 11:41:41.539357 ec_init: CrosEC protocol v3 supported (256, 248)
10229 11:41:41.543455
10230 11:41:41.546574 tpm_cleanup: add release locality here.
10231 11:41:41.546679
10232 11:41:41.546771 Shutting down all USB controllers.
10233 11:41:41.550498
10234 11:41:41.550605 Removing current net device
10235 11:41:41.550741
10236 11:41:41.557163 Exiting depthcharge with code 4 at timestamp: 49593096
10237 11:41:41.557271
10238 11:41:41.560051 LZMA decompressing kernel-1 to 0x821a6718
10239 11:41:41.560134
10240 11:41:41.563817 LZMA decompressing kernel-1 to 0x40000000
10241 11:41:42.874638
10242 11:41:42.874816 jumping to kernel
10243 11:41:42.875487 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10244 11:41:42.875617 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10245 11:41:42.875722 Setting prompt string to ['Linux version [0-9]']
10246 11:41:42.875820 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10247 11:41:42.875922 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10248 11:41:43.421015
10249 11:41:43.424211 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10250 11:41:43.427648 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10251 11:41:43.427763 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10252 11:41:43.427880 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10253 11:41:43.427975 Using line separator: #'\n'#
10254 11:41:43.428042 No login prompt set.
10255 11:41:43.428117 Parsing kernel messages
10256 11:41:43.428211 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10257 11:41:43.428398 [login-action] Waiting for messages, (timeout 00:04:03)
10258 11:41:43.447481 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10259 11:41:43.450569 [ 0.000000] random: crng init done
10260 11:41:43.454282 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10261 11:41:43.457423 [ 0.000000] efi: UEFI not found.
10262 11:41:43.467072 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10263 11:41:43.473569 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10264 11:41:43.483826 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10265 11:41:43.493483 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10266 11:41:43.496529 [ 0.000000] NUMA: No NUMA configuration found
10267 11:41:43.506643 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10268 11:41:43.510153 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10269 11:41:43.513440 [ 0.000000] Zone ranges:
10270 11:41:43.519924 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10271 11:41:43.523268 [ 0.000000] DMA32 empty
10272 11:41:43.529780 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10273 11:41:43.533119 [ 0.000000] Movable zone start for each node
10274 11:41:43.536127 [ 0.000000] Early memory node ranges
10275 11:41:43.543109 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10276 11:41:43.549713 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10277 11:41:43.556452 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10278 11:41:43.559232 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10279 11:41:43.566536 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10280 11:41:43.572940 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10281 11:41:43.579112 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10282 11:41:43.586142 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10283 11:41:43.592756 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10284 11:41:43.595834 [ 0.000000] psci: probing for conduit method from DT.
10285 11:41:43.602212 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10286 11:41:43.605882 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10287 11:41:43.612725 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10288 11:41:43.615577 [ 0.000000] psci: SMC Calling Convention v1.2
10289 11:41:43.622343 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10290 11:41:43.625499 [ 0.000000] Detected VIPT I-cache on CPU0
10291 11:41:43.632008 [ 0.000000] CPU features: detected: GIC system register CPU interface
10292 11:41:43.639170 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10293 11:41:43.645414 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10294 11:41:43.652100 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10295 11:41:43.658498 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10296 11:41:43.668626 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10297 11:41:43.672244 [ 0.000000] alternatives: applying boot alternatives
10298 11:41:43.674872 [ 0.000000] Fallback order for Node 0: 0
10299 11:41:43.682020 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10300 11:41:43.685156 [ 0.000000] Policy zone: Normal
10301 11:41:43.704940 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10742228/extract-nfsrootfs-kz1ohlq0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10302 11:41:43.714850 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10303 11:41:43.721773 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10304 11:41:43.728421 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10305 11:41:43.734727 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10306 11:41:43.741235 [ 0.000000] software IO TLB: area num 8.
10307 11:41:43.747734 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10308 11:41:43.761465 [ 0.000000] Memory: 7953928K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 398840K reserved, 32768K cma-reserved)
10309 11:41:43.768289 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10310 11:41:43.774601 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10311 11:41:43.777742 [ 0.000000] rcu: RCU event tracing is enabled.
10312 11:41:43.784796 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10313 11:41:43.791197 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10314 11:41:43.794352 [ 0.000000] Tracing variant of Tasks RCU enabled.
10315 11:41:43.801537 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10316 11:41:43.811031 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10317 11:41:43.814768 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10318 11:41:43.820977 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10319 11:41:43.824546 [ 0.000000] GICv3: 608 SPIs implemented
10320 11:41:43.827535 [ 0.000000] GICv3: 0 Extended SPIs implemented
10321 11:41:43.834280 [ 0.000000] Root IRQ handler: gic_handle_irq
10322 11:41:43.837825 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10323 11:41:43.844362 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10324 11:41:43.854249 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10325 11:41:43.867607 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10326 11:41:43.874043 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10327 11:41:43.880717 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10328 11:41:43.890355 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10329 11:41:43.900926 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10330 11:41:43.904129 [ 0.000930] Console: colour dummy device 80x25
10331 11:41:43.913654 [ 0.000984] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10332 11:41:43.917401 [ 0.000991] pid_max: default: 32768 minimum: 301
10333 11:41:43.924082 [ 0.001026] LSM: Security Framework initializing
10334 11:41:43.930384 [ 0.001092] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10335 11:41:43.940369 [ 0.001112] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10336 11:41:43.947123 [ 0.002252] cblist_init_generic: Setting adjustable number of callback queues.
10337 11:41:43.953640 [ 0.002262] cblist_init_generic: Setting shift to 3 and lim to 1.
10338 11:41:43.956697 [ 0.002304] cblist_init_generic: Setting shift to 3 and lim to 1.
10339 11:41:43.963955 [ 0.002409] rcu: Hierarchical SRCU implementation.
10340 11:41:43.966701 [ 0.002412] rcu: Max phase no-delay instances is 1000.
10341 11:41:43.973331 [ 0.004034] EFI services will not be available.
10342 11:41:43.977260 [ 0.004249] smp: Bringing up secondary CPUs ...
10343 11:41:43.980213 [ 0.004543] Detected VIPT I-cache on CPU1
10344 11:41:43.987030 [ 0.004616] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10345 11:41:43.994081 [ 0.004647] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10346 11:41:44.000170 [ 0.004991] Detected VIPT I-cache on CPU2
10347 11:41:44.006582 [ 0.005044] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10348 11:41:44.013559 [ 0.005061] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10349 11:41:44.017069 [ 0.005323] Detected VIPT I-cache on CPU3
10350 11:41:44.023492 [ 0.005370] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10351 11:41:44.030033 [ 0.005386] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10352 11:41:44.033520 [ 0.005695] CPU features: detected: Spectre-v4
10353 11:41:44.040012 [ 0.005703] CPU features: detected: Spectre-BHB
10354 11:41:44.043677 [ 0.005709] Detected PIPT I-cache on CPU4
10355 11:41:44.050101 [ 0.005768] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10356 11:41:44.056525 [ 0.005784] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10357 11:41:44.059731 [ 0.006081] Detected PIPT I-cache on CPU5
10358 11:41:44.066724 [ 0.006142] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10359 11:41:44.073192 [ 0.006158] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10360 11:41:44.076658 [ 0.006442] Detected PIPT I-cache on CPU6
10361 11:41:44.086052 [ 0.006506] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10362 11:41:44.092777 [ 0.006523] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10363 11:41:44.096421 [ 0.006823] Detected PIPT I-cache on CPU7
10364 11:41:44.103347 [ 0.006888] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10365 11:41:44.109668 [ 0.006904] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10366 11:41:44.112932 [ 0.006952] smp: Brought up 1 node, 8 CPUs
10367 11:41:44.119401 [ 0.006957] SMP: Total of 8 processors activated.
10368 11:41:44.122648 [ 0.006960] CPU features: detected: 32-bit EL0 Support
10369 11:41:44.132554 [ 0.006963] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10370 11:41:44.139410 [ 0.006966] CPU features: detected: Common not Private translations
10371 11:41:44.142713 [ 0.006968] CPU features: detected: CRC32 instructions
10372 11:41:44.149279 [ 0.006971] CPU features: detected: RCpc load-acquire (LDAPR)
10373 11:41:44.155922 [ 0.006972] CPU features: detected: LSE atomic instructions
10374 11:41:44.159013 [ 0.006974] CPU features: detected: Privileged Access Never
10375 11:41:44.165468 [ 0.006976] CPU features: detected: RAS Extension Support
10376 11:41:44.172517 [ 0.006979] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10377 11:41:44.175751 [ 0.007048] CPU: All CPU(s) started at EL2
10378 11:41:44.182033 [ 0.007050] alternatives: applying system-wide alternatives
10379 11:41:44.185620 [ 0.012005] devtmpfs: initialized
10380 11:41:44.195271 [ 0.017289] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10381 11:41:44.201916 [ 0.017304] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10382 11:41:44.208714 [ 0.017933] pinctrl core: initialized pinctrl subsystem
10383 11:41:44.211820 [ 0.019141] DMI not present or invalid.
10384 11:41:44.215098 [ 0.019480] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10385 11:41:44.224661 [ 0.020221] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10386 11:41:44.231924 [ 0.020444] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10387 11:41:44.238445 [ 0.020622] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10388 11:41:44.244726 [ 0.020648] audit: initializing netlink subsys (disabled)
10389 11:41:44.251194 [ 0.020720] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10390 11:41:44.257939 [ 0.021423] thermal_sys: Registered thermal governor 'step_wise'
10391 11:41:44.264507 [ 0.021427] thermal_sys: Registered thermal governor 'power_allocator'
10392 11:41:44.268060 [ 0.021455] cpuidle: using governor menu
10393 11:41:44.274957 [ 0.021517] NET: Registered PF_QIPCRTR protocol family
10394 11:41:44.281410 [ 0.021631] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10395 11:41:44.287816 [ 0.021721] ASID allocator initialised with 32768 entries
10396 11:41:44.291288 [ 0.022660] Serial: AMBA PL011 UART driver
10397 11:41:44.294372 [ 0.027130] Trying to register duplicate clock ID: 134
10398 11:41:44.298003 [ 0.079443] KASLR enabled
10399 11:41:44.304324 [ 0.084283] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10400 11:41:44.310910 [ 0.084287] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10401 11:41:44.317386 [ 0.084291] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10402 11:41:44.324350 [ 0.084294] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10403 11:41:44.330986 [ 0.084297] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10404 11:41:44.337531 [ 0.084299] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10405 11:41:44.343942 [ 0.084302] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10406 11:41:44.351054 [ 0.084304] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10407 11:41:44.354396 [ 0.085214] ACPI: Interpreter disabled.
10408 11:41:44.357334 [ 0.087523] iommu: Default domain type: Translated
10409 11:41:44.364214 [ 0.087527] iommu: DMA domain TLB invalidation policy: strict mode
10410 11:41:44.370654 [ 0.087703] SCSI subsystem initialized
10411 11:41:44.374215 [ 0.087889] usbcore: registered new interface driver usbfs
10412 11:41:44.380461 [ 0.087906] usbcore: registered new interface driver hub
10413 11:41:44.383850 [ 0.087919] usbcore: registered new device driver usb
10414 11:41:44.390863 [ 0.088726] pps_core: LinuxPPS API ver. 1 registered
10415 11:41:44.397553 [ 0.088728] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10416 11:41:44.404012 [ 0.088735] PTP clock support registered
10417 11:41:44.407512 [ 0.088817] EDAC MC: Ver: 3.0.0
10418 11:41:44.410254 [ 0.090598] FPGA manager framework
10419 11:41:44.413551 [ 0.090637] Advanced Linux Sound Architecture Driver Initialized.
10420 11:41:44.417222 [ 0.091075] vgaarb: loaded
10421 11:41:44.423831 [ 0.091282] clocksource: Switched to clocksource arch_sys_counter
10422 11:41:44.426872 [ 0.091400] VFS: Disk quotas dquot_6.6.0
10423 11:41:44.433946 [ 0.091427] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10424 11:41:44.436966 [ 0.091530] pnp: PnP ACPI: disabled
10425 11:41:44.443538 [ 0.094288] NET: Registered PF_INET protocol family
10426 11:41:44.450818 [ 0.094763] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10427 11:41:44.460126 [ 0.099287] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10428 11:41:44.467158 [ 0.099362] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10429 11:41:44.473604 [ 0.099375] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10430 11:41:44.483325 [ 0.099949] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10431 11:41:44.489826 [ 0.102055] TCP: Hash tables configured (established 65536 bind 65536)
10432 11:41:44.496427 [ 0.102165] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10433 11:41:44.503632 [ 0.102358] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10434 11:41:44.509707 [ 0.102622] NET: Registered PF_UNIX/PF_LOCAL protocol family
10435 11:41:44.513530 [ 0.102917] RPC: Registered named UNIX socket transport module.
10436 11:41:44.520402 [ 0.102921] RPC: Registered udp transport module.
10437 11:41:44.523359 [ 0.102923] RPC: Registered tcp transport module.
10438 11:41:44.529812 [ 0.102925] RPC: Registered tcp NFSv4.1 backchannel transport module.
10439 11:41:44.533555 [ 0.102937] PCI: CLS 0 bytes, default 64
10440 11:41:44.536283 [ 0.103171] Unpacking initramfs...
10441 11:41:44.546486 [ 0.111906] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10442 11:41:44.553047 [ 0.112132] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10443 11:41:44.559414 [ 0.112585] kvm [1]: IPA Size Limit: 40 bits
10444 11:41:44.563159 [ 0.112609] kvm [1]: GICv3: no GICV resource entry
10445 11:41:44.566532 [ 0.112613] kvm [1]: disabling GICv2 emulation
10446 11:41:44.572688 [ 0.112626] kvm [1]: GIC system register CPU interface enabled
10447 11:41:44.576174 [ 0.112714] kvm [1]: vgic interrupt IRQ18
10448 11:41:44.582546 [ 0.112812] kvm [1]: VHE mode initialized successfully
10449 11:41:44.586401 [ 0.113702] Initialise system trusted keyrings
10450 11:41:44.592744 [ 0.113786] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10451 11:41:44.599206 [ 0.117175] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10452 11:41:44.602511 [ 0.117490] NFS: Registering the id_resolver key type
10453 11:41:44.609401 [ 0.117507] Key type id_resolver registered
10454 11:41:44.612752 [ 0.117509] Key type id_legacy registered
10455 11:41:44.619347 [ 0.117551] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10456 11:41:44.625818 [ 0.117555] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10457 11:41:44.632782 [ 0.117655] 9p: Installing v9fs 9p2000 file system support
10458 11:41:44.635794 [ 0.149919] Key type asymmetric registered
10459 11:41:44.639779 [ 0.149924] Asymmetric key parser 'x509' registered
10460 11:41:44.649351 [ 0.149965] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10461 11:41:44.652533 [ 0.149969] io scheduler mq-deadline registered
10462 11:41:44.656214 [ 0.149974] io scheduler kyber registered
10463 11:41:44.659332 [ 0.162399] EINJ: ACPI disabled.
10464 11:41:44.669308 [ 0.184258] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10465 11:41:44.678934 [ 0.184413] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10466 11:41:44.685528 [ 0.194339] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10467 11:41:44.692131 [ 0.195718] printk: console [ttyS0] disabled
10468 11:41:44.698710 [ 0.215872] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10469 11:41:44.705936 [ 0.860999] Freeing initrd memory: 17224K
10470 11:41:44.709099 [ 0.864333] printk: console [ttyS0] enabled
10471 11:41:44.715436 [ 1.506428] SuperH (H)SCI(F) driver initialized
10472 11:41:44.718694 [ 1.511440] msm_serial: driver initialized
10473 11:41:44.731597 [ 1.520066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10474 11:41:44.737978 [ 1.528351] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10475 11:41:44.748247 [ 1.536633] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10476 11:41:44.757896 [ 1.545000] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10477 11:41:44.764601 [ 1.553445] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10478 11:41:44.774611 [ 1.561896] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10479 11:41:44.781194 [ 1.570176] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10480 11:41:44.790941 [ 1.578716] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10481 11:41:44.797507 [ 1.586998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10482 11:41:44.806261 [ 1.601948] loop: module loaded
10483 11:41:44.815713 [ 1.607494] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10484 11:41:44.838391 [ 1.630224] mtk-pmic-keys: Failed to locate of_node [id: -1]
10485 11:41:44.841348 [ 1.636555] megasas: 07.719.03.00-rc1
10486 11:41:44.853934 [ 1.645653] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10487 11:41:44.863711 [ 1.654679] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10488 11:41:44.869831 [ 1.656632] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10489 11:41:44.879572 [ 1.671463] tun: Universal TUN/TAP device driver, 1.6
10490 11:41:44.886665 [ 1.672463] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10491 11:41:44.891198 [ 1.677230] thunder_xcv, ver 1.0
10492 11:41:44.891286 [ 1.685920] thunder_bgx, ver 1.0
10493 11:41:44.899705 [ 1.689153] nicpf, ver 1.0
10494 11:41:44.904063 [ 1.692885] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10495 11:41:44.916734 [ 1.700101] hns3: Copyright (c) 2017 Huawei Corporation.
10496 11:41:44.917096 [ 1.705424] hclge is initializing
10497 11:41:44.921352 [ 1.708742] e1000: Intel(R) PRO/1000 Network Driver
10498 11:41:44.927681 [ 1.713612] e1000: Copyright (c) 1999-2006 Intel Corporation.
10499 11:41:44.932511 [ 1.719365] e1000e: Intel(R) PRO/1000 Network Driver
10500 11:41:44.938443 [ 1.724320] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10501 11:41:44.942282 [ 1.730247] igb: Intel(R) Gigabit Ethernet Network Driver
10502 11:41:44.945268 [ 1.735638] igb: Copyright (c) 2007-2014 Intel Corporation.
10503 11:41:44.955196 [ 1.737175] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10504 11:41:44.962290 [ 1.741213] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10505 11:41:44.968352 [ 1.758228] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10506 11:41:44.972214 [ 1.764443] sky2: driver version 1.30
10507 11:41:44.978420 [ 1.769160] VFIO - User Level meta-driver version: 0.3
10508 11:41:44.985161 [ 1.777061] usbcore: registered new interface driver usb-storage
10509 11:41:44.991441 [ 1.783244] usbcore: registered new device driver onboard-usb-hub
10510 11:41:45.000392 [ 1.792059] mt6397-rtc mt6359-rtc: registered as rtc0
10511 11:41:45.010251 [ 1.797283] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:41:29 UTC (1686829289)
10512 11:41:45.013452 [ 1.806587] i2c_dev: i2c /dev entries driver
10513 11:41:45.029422 [ 1.817935] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10514 11:41:45.035817 [ 1.827869] sdhci: Secure Digital Host Controller Interface driver
10515 11:41:45.042680 [ 1.834044] sdhci: Copyright(c) Pierre Ossman
10516 11:41:45.049155 [ 1.839204] Synopsys Designware Multimedia Card Interface Driver
10517 11:41:45.052370 [ 1.845658] mmc0: CQHCI version 5.10
10518 11:41:45.058981 [ 1.846094] sdhci-pltfm: SDHCI platform and OF driver helper
10519 11:41:45.065943 [ 1.856985] ledtrig-cpu: registered to indicate activity on CPUs
10520 11:41:45.072432 [ 1.864160] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10521 11:41:45.079183 [ 1.871307] usbcore: registered new interface driver usbhid
10522 11:41:45.082804 [ 1.876875] usbhid: USB HID core driver
10523 11:41:45.089505 [ 1.880874] spi_master spi0: will run message pump with realtime priority
10524 11:41:45.139040 [ 1.924586] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10525 11:41:45.155053 [ 1.939884] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10526 11:41:45.161518 [ 1.953277] mmc0: Command Queue Engine enabled
10527 11:41:45.165082 [ 1.955479] cros-ec-spi spi0.0: Chrome EC device registered
10528 11:41:45.171956 [ 1.957742] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10529 11:41:45.178914 [ 1.970471] mmcblk0: mmc0:0001 DA4128 116 GiB
10530 11:41:45.193135 [ 1.981503] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10531 11:41:45.199535 [ 1.987531] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10532 11:41:45.202679 [ 1.992778] NET: Registered PF_PACKET protocol family
10533 11:41:45.209278 [ 1.998550] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10534 11:41:45.212946 [ 2.001375] 9pnet: Installing 9P2000 support
10535 11:41:45.219405 [ 2.007156] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10536 11:41:45.222891 [ 2.010534] Key type dns_resolver registered
10537 11:41:45.229742 [ 2.016475] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10538 11:41:45.232836 [ 2.020277] registered taskstats version 1
10539 11:41:45.239034 [ 2.030121] Loading compiled-in X.509 certificates
10540 11:41:45.270840 [ 2.056483] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 11:41:45.281042 [ 2.066906] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10542 11:41:45.291297 [ 2.079027] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10543 11:41:45.302489 [ 2.094306] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10544 11:41:45.308838 [ 2.100903] xhci-mtk 11200000.usb: xHCI Host Controller
10545 11:41:45.315618 [ 2.106143] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10546 11:41:45.325711 [ 2.113746] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10547 11:41:45.332610 [ 2.122915] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10548 11:41:45.335298 [ 2.128747] xhci-mtk 11200000.usb: xHCI Host Controller
10549 11:41:45.345578 [ 2.133967] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10550 11:41:45.351908 [ 2.141360] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10551 11:41:45.355666 [ 2.148803] hub 1-0:1.0: USB hub found
10552 11:41:45.358868 [ 2.152580] hub 1-0:1.0: 1 port detected
10553 11:41:45.368430 [ 2.156659] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10554 11:41:45.372232 [ 2.165004] hub 2-0:1.0: USB hub found
10555 11:41:45.375152 [ 2.168771] hub 2-0:1.0: 1 port detected
10556 11:41:45.384162 [ 2.176018] mtk-msdc 11f70000.mmc: Got CD GPIO
10557 11:41:45.402175 [ 2.190470] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10558 11:41:45.408571 [ 2.198245] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10559 11:41:45.418853 [ 2.205963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10560 11:41:45.425031 [ 2.215375] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10561 11:41:45.435193 [ 2.223202] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10562 11:41:45.441877 [ 2.230964] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10563 11:41:45.448637 [ 2.238620] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10564 11:41:45.458227 [ 2.246180] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10565 11:41:45.465464 [ 2.253746] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10566 11:41:45.475576 [ 2.263942] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10567 11:41:45.481759 [ 2.272065] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10568 11:41:45.491790 [ 2.280149] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10569 11:41:45.498512 [ 2.288232] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10570 11:41:45.508388 [ 2.296314] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10571 11:41:45.515464 [ 2.304398] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10572 11:41:45.525101 [ 2.312481] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10573 11:41:45.532336 [ 2.320563] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10574 11:41:45.538632 [ 2.328647] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10575 11:41:45.548409 [ 2.336731] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10576 11:41:45.555581 [ 2.344814] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10577 11:41:45.565549 [ 2.352897] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10578 11:41:45.571982 [ 2.360981] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10579 11:41:45.578506 [ 2.369064] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10580 11:41:45.588371 [ 2.377146] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10581 11:41:45.595010 [ 2.385773] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10582 11:41:45.601933 [ 2.392967] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10583 11:41:45.608567 [ 2.399809] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10584 11:41:45.615472 [ 2.406702] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10585 11:41:45.621822 [ 2.413781] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10586 11:41:45.632138 [ 2.420456] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10587 11:41:45.641932 [ 2.429336] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10588 11:41:45.648628 [ 2.438210] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10589 11:41:45.658683 [ 2.447252] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10590 11:41:45.668451 [ 2.456466] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10591 11:41:45.678627 [ 2.465680] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10592 11:41:45.685533 [ 2.474546] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10593 11:41:45.695170 [ 2.483760] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10594 11:41:45.704914 [ 2.492625] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10595 11:41:45.714887 [ 2.501666] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10596 11:41:45.725347 [ 2.511571] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10597 11:41:45.735409 [ 2.522514] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10598 11:41:45.742093 [ 2.531947] Trying to probe devices needed for running init ...
10599 11:41:45.763457 [ 2.555750] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10600 11:41:45.793848 [ 2.585938] hub 2-1:1.0: USB hub found
10601 11:41:45.797042 [ 2.590088] hub 2-1:1.0: 3 ports detected
10602 11:41:45.915801 [ 2.707529] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10603 11:41:46.071754 [ 2.863874] hub 1-1:1.0: USB hub found
10604 11:41:46.074846 [ 2.867970] hub 1-1:1.0: 4 ports detected
10605 11:41:46.151836 [ 2.943674] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10606 11:41:46.394877 [ 3.183553] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10607 11:41:46.528096 [ 3.319561] hub 1-1.4:1.0: USB hub found
10608 11:41:46.531513 [ 3.323952] hub 1-1.4:1.0: 2 ports detected
10609 11:41:46.826876 [ 3.615556] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10610 11:41:47.018846 [ 3.807583] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10611 11:41:58.019890 [ 14.816001] ALSA device list:
10612 11:41:58.022799 [ 14.818969] No soundcards found.
10613 11:41:58.031930 [ 14.825074] Freeing unused kernel memory: 8384K
10614 11:41:58.035116 [ 14.829709] Run /init as init process
10615 11:41:58.043415 Loading, please wait...
10616 11:41:58.060256 Starting version 247.3-7+deb11u2
10617 11:41:58.360795 [ 15.151091] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10618 11:41:58.372051 [ 15.162366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 11:41:58.378982 [ 15.170244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10620 11:41:58.385329 [ 15.175498] remoteproc remoteproc0: scp is available
10621 11:41:58.392126 [ 15.178072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 11:41:58.401834 [ 15.183119] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10623 11:41:58.408106 [ 15.200445] remoteproc remoteproc0: powering up scp
10624 11:41:58.415330 [ 15.205394] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10625 11:41:58.421365 [ 15.214966] remoteproc remoteproc0: request_firmware failed: -2
10626 11:41:58.428530 [ 15.219008] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10627 11:41:58.437816 [ 15.228358] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10628 11:41:58.448104 [ 15.236849] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10629 11:41:58.454883 [ 15.238872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 11:41:58.461664 [ 15.249804] usbcore: registered new interface driver r8152
10631 11:41:58.468316 [ 15.253155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 11:41:58.474598 [ 15.254174] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10633 11:41:58.480997 [ 15.257755] mc: Linux media interface: v0.10
10634 11:41:58.488336 [ 15.263512] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10635 11:41:58.494843 [ 15.266479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 11:41:58.501182 [ 15.274024] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10637 11:41:58.507607 [ 15.274452] videodev: Linux video capture interface: v2.00
10638 11:41:58.514284 [ 15.278081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10639 11:41:58.521293 [ 15.278089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10640 11:41:58.530925 [ 15.278680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10641 11:41:58.538001 [ 15.329081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 11:41:58.547715 [ 15.336929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 11:41:58.554747 [ 15.337625] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10644 11:41:58.560759 [ 15.337625] Fallback method does not support PEC.
10645 11:41:58.567855 [ 15.343681] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10646 11:41:58.574334 [ 15.344755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10647 11:41:58.580824 [ 15.344815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10648 11:41:58.587735 [ 15.364692] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10649 11:41:58.598065 [ 15.364739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10650 11:41:58.601242 [ 15.372584] pci_bus 0000:00: root bus resource [bus 00-ff]
10651 11:41:58.611387 [ 15.380369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10652 11:41:58.617791 [ 15.380377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10653 11:41:58.624257 [ 15.380383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 11:41:58.630762 [ 15.387001] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10655 11:41:58.641244 [ 15.394825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10656 11:41:58.651584 [ 15.400316] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10657 11:41:58.657678 [ 15.448299] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10658 11:41:58.664184 [ 15.449047] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10659 11:41:58.675051 [ 15.449178] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10660 11:41:58.685046 [ 15.449530] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10661 11:41:58.691564 [ 15.450819] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10662 11:41:58.701559 [ 15.450828] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10663 11:41:58.708372 [ 15.454397] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10664 11:41:58.714730 [ 15.469708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10665 11:41:58.721611 [ 15.473255] pci 0000:00:00.0: supports D1 D2
10666 11:41:58.724743 [ 15.491178] usbcore: registered new interface driver cdc_ether
10667 11:41:58.731938 [ 15.498577] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10668 11:41:58.741377 [ 15.500260] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10669 11:41:58.744433 [ 15.506771] Bluetooth: Core ver 2.22
10670 11:41:58.750844 [ 15.514457] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10671 11:41:58.754510 [ 15.514610] usbcore: registered new interface driver r8153_ecm
10672 11:41:58.760924 [ 15.518679] NET: Registered PF_BLUETOOTH protocol family
10673 11:41:58.764674 [ 15.518722] r8152 2-1.3:1.0 eth0: v1.12.13
10674 11:41:58.771362 [ 15.524468] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10675 11:41:58.777844 [ 15.525645] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10676 11:41:58.784889 [ 15.526240] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10677 11:41:58.798700 [ 15.526714] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10678 11:41:58.801694 [ 15.526833] usbcore: registered new interface driver uvcvideo
10679 11:41:58.808319 [ 15.531064] Bluetooth: HCI device and connection manager initialized
10680 11:41:58.815173 [ 15.539064] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10681 11:41:58.821937 [ 15.542633] Bluetooth: HCI socket layer initialized
10682 11:41:58.828551 [ 15.548628] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10683 11:41:58.834642 [ 15.554454] Bluetooth: L2CAP socket layer initialized
10684 11:41:58.841345 [ 15.555017] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10685 11:41:58.845335 [ 15.559854] pci 0000:01:00.0: supports D1 D2
10686 11:41:58.848229 [ 15.563846] Bluetooth: SCO socket layer initialized
10687 11:41:58.855099 [ 15.571053] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10688 11:41:58.864631 [ 15.601545] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10689 11:41:58.871157 [ 15.619477] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10690 11:41:58.874867 [ 15.639008] usbcore: registered new interface driver btusb
10691 11:41:58.888193 [ 15.639575] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10692 11:41:58.891399 [ 15.639585] Bluetooth: hci0: Failed to load firmware file (-2)
10693 11:41:58.898389 [ 15.639589] Bluetooth: hci0: Failed to set up firmware (-2)
10694 11:41:58.907940 [ 15.639592] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10695 11:41:58.914876 [ 15.642783] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10696 11:41:58.924434 [ 15.714436] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10697 11:41:58.930844 [ 15.722180] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10698 11:41:58.937732 [ 15.729928] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10699 11:41:58.947506 [ 15.737679] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10700 11:41:58.950701 [ 15.745429] pci 0000:00:00.0: PCI bridge to [bus 01]
10701 11:41:58.960927 [ 15.750390] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10702 11:41:58.964059 [ 15.758242] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10703 11:41:58.971711 [ 15.765098] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10704 11:41:58.977994 [ 15.771149] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10705 11:41:58.994301 [ 15.784432] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10706 11:41:59.008515 [ 15.802338] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10707 11:41:59.018888 [ 15.808967] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10708 11:41:59.025570 [ 15.817606] cfg80211: failed to load regulatory.db
10709 11:41:59.048503 [ 15.838313] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10710 11:41:59.051510 [ 15.845537] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10711 11:41:59.078453 [ 15.871937] mt7921e 0000:01:00.0: ASIC revision: 79610010
10712 11:41:59.175196 [ 15.962352] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10713 11:41:59.187093 Begin: Loading essential drivers ... done.
10714 11:41:59.190103 Begin: Running /scripts/init-premount ... done.
10715 11:41:59.196959 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10716 11:41:59.207066 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10717 11:41:59.210174 Device /sys/class/net/enx00e04c787aaa found
10718 11:41:59.210289 done.
10719 11:41:59.274284 [ 16.061200] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10720 11:41:59.285144 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10721 11:41:59.374243 [ 16.161282] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10722 11:41:59.474180 [ 16.261268] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10723 11:41:59.574415 [ 16.361257] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10724 11:41:59.674376 [ 16.461238] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10725 11:41:59.774441 [ 16.561252] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10726 11:41:59.874205 [ 16.661211] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10727 11:41:59.974186 [ 16.761232] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10728 11:42:00.074104 [ 16.861198] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10729 11:42:00.165221 [ 16.959186] mt7921e 0000:01:00.0: hardware init failed
10730 11:42:00.367977 [ 17.161569] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10731 11:42:00.503708 IP-Config: no response after 2 secs - giving up
10732 11:42:00.541793 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10733 11:42:00.548689 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10734 11:42:00.555006 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10735 11:42:00.561631 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10736 11:42:00.567980 host : mt8192-asurada-spherion-r0-cbg-0
10737 11:42:00.574797 domain : lava-rack
10738 11:42:00.581288 rootserver: 192.168.201.1 rootpath:
10739 11:42:00.581467 filename :
10740 11:42:00.613344 done.
10741 11:42:00.620473 Begin: Running /scripts/nfs-bottom ... done.
10742 11:42:00.631449 Begin: Running /scripts/init-bottom ... done.
10743 11:42:01.702960 [ 18.497053] NET: Registered PF_INET6 protocol family
10744 11:42:01.706567 [ 18.503078] Segment Routing with IPv6
10745 11:42:01.712990 [ 18.506768] In-situ OAM (IOAM) with IPv6
10746 11:42:01.810177 [ 18.587509] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10747 11:42:01.817008 [ 18.610912] systemd[1]: Detected architecture arm64.
10748 11:42:01.834174
10749 11:42:01.837298 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10750 11:42:01.837401
10751 11:42:01.850917 [ 18.645105] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10752 11:42:02.289608 [ 19.080268] systemd[1]: Queued start job for default target Graphical Interface.
10753 11:42:02.314435 [ 19.108432] systemd[1]: Created slice system-getty.slice.
10754 11:42:02.320819 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10755 11:42:02.338180 [ 19.132065] systemd[1]: Created slice system-modprobe.slice.
10756 11:42:02.344450 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10757 11:42:02.362305 [ 19.155990] systemd[1]: Created slice system-serial\x2dgetty.slice.
10758 11:42:02.368725 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10759 11:42:02.386127 [ 19.179917] systemd[1]: Created slice User and Session Slice.
10760 11:42:02.392507 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10761 11:42:02.413056 [ 19.203790] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10762 11:42:02.419506 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10763 11:42:02.437136 [ 19.227626] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10764 11:42:02.443431 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10765 11:42:02.464260 [ 19.251586] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10766 11:42:02.470801 [ 19.263258] systemd[1]: Reached target Local Encrypted Volumes.
10767 11:42:02.477755 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10768 11:42:02.489438 [ 19.283569] systemd[1]: Reached target Paths.
10769 11:42:02.492687 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10770 11:42:02.509551 [ 19.303491] systemd[1]: Reached target Remote File Systems.
10771 11:42:02.515878 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10772 11:42:02.529817 [ 19.323512] systemd[1]: Reached target Slices.
10773 11:42:02.532856 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10774 11:42:02.549566 [ 19.343524] systemd[1]: Reached target Swap.
10775 11:42:02.552908 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10776 11:42:02.569613 [ 19.363699] systemd[1]: Listening on initctl Compatibility Named Pipe.
10777 11:42:02.579670 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10778 11:42:02.594434 [ 19.388599] systemd[1]: Listening on Journal Audit Socket.
10779 11:42:02.600931 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10780 11:42:02.618637 [ 19.412412] systemd[1]: Listening on Journal Socket (/dev/log).
10781 11:42:02.625235 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10782 11:42:02.641955 [ 19.435997] systemd[1]: Listening on Journal Socket.
10783 11:42:02.648754 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10784 11:42:02.662646 [ 19.456524] systemd[1]: Listening on Network Service Netlink Socket.
10785 11:42:02.672711 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10786 11:42:02.687985 [ 19.481714] systemd[1]: Listening on udev Control Socket.
10787 11:42:02.694691 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10788 11:42:02.709892 [ 19.503764] systemd[1]: Listening on udev Kernel Socket.
10789 11:42:02.716316 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10790 11:42:02.750231 [ 19.543678] systemd[1]: Mounting Huge Pages File System...
10791 11:42:02.756187 Mounting [0;1;39mHuge Pages File System[0m...
10792 11:42:02.771603 [ 19.565242] systemd[1]: Mounting POSIX Message Queue File System...
10793 11:42:02.778141 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10794 11:42:02.795572 [ 19.589271] systemd[1]: Mounting Kernel Debug File System...
10795 11:42:02.801803 Mounting [0;1;39mKernel Debug File System[0m...
10796 11:42:02.817017 [ 19.607770] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10797 11:42:02.837009 [ 19.627424] systemd[1]: Starting Create list of static device nodes for the current kernel...
10798 11:42:02.843710 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10799 11:42:02.859564 [ 19.653327] systemd[1]: Starting Load Kernel Module configfs...
10800 11:42:02.866230 Starting [0;1;39mLoad Kernel Module configfs[0m...
10801 11:42:02.883084 [ 19.677327] systemd[1]: Starting Load Kernel Module drm...
10802 11:42:02.890077 Starting [0;1;39mLoad Kernel Module drm[0m...
10803 11:42:02.903520 [ 19.697380] systemd[1]: Starting Load Kernel Module fuse...
10804 11:42:02.909875 Starting [0;1;39mLoad Kernel Module fuse[0m...
10805 11:42:02.935885 [ 19.730126] fuse: init (API version 7.37)
10806 11:42:02.942753 [ 19.730616] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10807 11:42:02.952699 [ 19.746635] systemd[1]: Starting Journal Service...
10808 11:42:02.955936 Starting [0;1;39mJournal Service[0m...
10809 11:42:02.983652 [ 19.777624] systemd[1]: Starting Load Kernel Modules...
10810 11:42:02.990027 Starting [0;1;39mLoad Kernel Modules[0m...
10811 11:42:03.010794 [ 19.801352] systemd[1]: Starting Remount Root and Kernel File Systems...
10812 11:42:03.013984 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10813 11:42:03.035705 [ 19.829319] systemd[1]: Starting Coldplug All udev Devices...
10814 11:42:03.042057 Starting [0;1;39mColdplug All udev Devices[0m...
10815 11:42:03.056475 [ 19.849936] systemd[1]: Mounted Huge Pages File System.
10816 11:42:03.062541 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10817 11:42:03.082099 [ 19.875691] systemd[1]: Mounted POSIX Message Queue File System.
10818 11:42:03.095912 [[0;32m OK [0m] Mounted [0;[ 19.884178] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10819 11:42:03.098924 1;39mPOSIX Message Queue File System[0m.
10820 11:42:03.113667 [ 19.907621] systemd[1]: Mounted Kernel Debug File System.
10821 11:42:03.127036 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0[ 19.918379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10822 11:42:03.127157 m.
10823 11:42:03.149235 [ 19.940177] systemd[1]: Finished Create list of static device nodes for the current kernel.
10824 11:42:03.156381 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10825 11:42:03.168742 [ 19.959382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10826 11:42:03.175120 [ 19.968934] systemd[1]: modprobe@configfs.service: Succeeded.
10827 11:42:03.182309 [ 19.975163] systemd[1]: Finished Load Kernel Module configfs.
10828 11:42:03.189201 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10829 11:42:03.201542 [ 19.992286] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10830 11:42:03.207962 [ 20.001687] systemd[1]: modprobe@drm.service: Succeeded.
10831 11:42:03.214925 [ 20.007628] systemd[1]: Finished Load Kernel Module drm.
10832 11:42:03.218594 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10833 11:42:03.234253 [ 20.024506] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10834 11:42:03.240693 [ 20.033852] systemd[1]: modprobe@fuse.service: Succeeded.
10835 11:42:03.247342 [ 20.040000] systemd[1]: Finished Load Kernel Module fuse.
10836 11:42:03.253726 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10837 11:42:03.270438 [ 20.064237] systemd[1]: Finished Load Kernel Modules.
10838 11:42:03.280269 [ 20.064862] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 11:42:03.283256 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10840 11:42:03.298757 [ 20.092291] systemd[1]: Finished Remount Root and Kernel File Systems.
10841 11:42:03.308662 [[0;32m OK [[ 20.098958] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 11:42:03.315078 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10843 11:42:03.340075 [ 20.130523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 11:42:03.356252 [ 20.149988] systemd[1]: Mounting FUSE Control File System...
10845 11:42:03.363159 Mounting [0;1;39mFUSE Control File System[0m...
10846 11:42:03.379269 [ 20.173336] systemd[1]: Mounting Kernel Configuration File System...
10847 11:42:03.386223 Mounting [0;1;39mKernel Configuration File System[0m...
10848 11:42:03.408335 [ 20.198571] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10849 11:42:03.418104 [ 20.207181] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10850 11:42:03.424303 [ 20.218359] systemd[1]: Starting Load/Save Random Seed...
10851 11:42:03.430647 Starting [0;1;39mLoad/Save Random Seed[0m...
10852 11:42:03.447515 [ 20.241353] systemd[1]: Starting Apply Kernel Variables...
10853 11:42:03.454065 Starting [0;1;39mApply Kernel Variables[0m...
10854 11:42:03.472213 [ 20.265881] systemd[1]: Starting Create System Users...
10855 11:42:03.478110 Starting [0;1;39mCreate System Users[0m...
10856 11:42:03.498500 [ 20.292622] systemd[1]: Started Journal Service.
10857 11:42:03.501625 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10858 11:42:03.518696 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10859 11:42:03.551128 [[0;32m OK [0m] Mounted [0;1;39mKernel Conf[ 20.334750] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10860 11:42:03.561486 iguration File S[ 20.351321] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10861 11:42:03.561630 ystem[0m.
10862 11:42:03.578588 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10863 11:42:03.598275 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10864 11:42:03.609799 See 'systemctl status systemd-udev-trigger.service' for details.
10865 11:42:03.625996 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10866 11:42:03.642207 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10867 11:42:03.693900 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10868 11:42:03.710837 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10869 11:42:03.731283 [ 20.522058] systemd-journald[303]: Received client request to flush runtime journal.
10870 11:42:04.798362 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10871 11:42:04.809420 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10872 11:42:04.825188 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10873 11:42:04.865278 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10874 11:42:05.089312 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10875 11:42:05.133912 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10876 11:42:05.169292 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10877 11:42:05.225262 Starting [0;1;39mNetwork Service[0m...
10878 11:42:05.460542 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10879 11:42:05.479432 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10880 11:42:05.524799 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10881 11:42:05.560281 [ 22.354659] power_supply_show_property: 5 callbacks suppressed
10882 11:42:05.569993 [ 22.354671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 11:42:05.610585 [ 22.401497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 11:42:05.620192 [ 22.402323] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10885 11:42:05.728169 [ 22.522875] remoteproc remoteproc0: powering up scp
10886 11:42:05.767901 [ 22.558716] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10887 11:42:05.774150 [ 22.568608] remoteproc remoteproc0: request_firmware failed: -2
10888 11:42:05.783894 [ 22.574808] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10889 11:42:05.831795 [ 22.623041] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 11:42:05.912484 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10891 11:42:05.925455 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10892 11:42:05.952675 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and [ 22.741287] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 11:42:05.952851 Directories[0m.
10894 11:42:05.982854 [ 22.774056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 11:42:06.000471 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10896 11:42:06.014434 [ 22.805460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 11:42:06.024338 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10898 11:42:06.043760 [ 22.834788] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 11:42:06.074604 [ 22.865365] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 11:42:06.081070 Starting [0;1;39mNetwork Name Resolution[0m...
10901 11:42:06.105574 Starting [0;1;39mNetwo[ 22.895150] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 11:42:06.108551 rk Time Synchronization[0m...
10903 11:42:06.123313 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10904 11:42:06.139552 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10905 11:42:06.255390 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10906 11:42:06.273218 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10907 11:42:06.327013 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10908 11:42:06.341453 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10909 11:42:06.360346 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10910 11:42:06.373321 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10911 11:42:06.389192 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10912 11:42:06.506227 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10913 11:42:06.537340 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10914 11:42:06.600140 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10915 11:42:06.636688 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10916 11:42:06.649472 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10917 11:42:06.669649 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10918 11:42:06.680787 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10919 11:42:06.697538 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10920 11:42:06.737348 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10921 11:42:06.796847 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10922 11:42:06.885328 Starting [0;1;39mUser Login Management[0m...
10923 11:42:06.901865 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10924 11:42:06.917699 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10925 11:42:06.936106 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10926 11:42:06.981179 Starting [0;1;39mPermit User Sessions[0m...
10927 11:42:07.090322 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10928 11:42:07.106258 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10929 11:42:07.165895 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10930 11:42:07.187217 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10931 11:42:07.205249 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10932 11:42:07.222781 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10933 11:42:07.237798 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10934 11:42:07.253400 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10935 11:42:07.300692 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10936 11:42:07.406901 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10937 11:42:07.528398
10938 11:42:07.528579
10939 11:42:07.531421 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10940 11:42:07.531511
10941 11:42:07.535024 debian-bullseye-arm64 login: root (automatic login)
10942 11:42:07.535137
10943 11:42:07.535205
10944 11:42:07.755676 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
10945 11:42:07.755821
10946 11:42:07.762582 The programs included with the Debian GNU/Linux system are free software;
10947 11:42:07.769142 the exact distribution terms for each program are described in the
10948 11:42:07.771931 individual files in /usr/share/doc/*/copyright.
10949 11:42:07.772015
10950 11:42:07.779134 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10951 11:42:07.782011 permitted by applicable law.
10952 11:42:07.866516 Matched prompt #10: / #
10954 11:42:07.866804 Setting prompt string to ['/ #']
10955 11:42:07.866900 end: 2.2.5.1 login-action (duration 00:00:24) [common]
10957 11:42:07.867147 end: 2.2.5 auto-login-action (duration 00:00:25) [common]
10958 11:42:07.867235 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
10959 11:42:07.867308 Setting prompt string to ['/ #']
10960 11:42:07.867370 Forcing a shell prompt, looking for ['/ #']
10962 11:42:07.917588 / #
10963 11:42:07.917711 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10964 11:42:07.917793 Waiting using forced prompt support (timeout 00:02:30)
10965 11:42:07.923078
10966 11:42:07.923352 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10967 11:42:07.923445 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
10969 11:42:08.023796 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742228/extract-nfsrootfs-kz1ohlq0'
10970 11:42:08.029472 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10742228/extract-nfsrootfs-kz1ohlq0'
10972 11:42:08.129970 / # export NFS_SERVER_IP='192.168.201.1'
10973 11:42:08.135091 export NFS_SERVER_IP='192.168.201.1'
10974 11:42:08.135384 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10975 11:42:08.135485 end: 2.2 depthcharge-retry (duration 00:01:22) [common]
10976 11:42:08.135571 end: 2 depthcharge-action (duration 00:01:22) [common]
10977 11:42:08.135659 start: 3 lava-test-retry (timeout 00:30:00) [common]
10978 11:42:08.135743 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10979 11:42:08.135818 Using namespace: common
10981 11:42:08.236164 / # #
10982 11:42:08.236345 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10983 11:42:08.241317 #
10984 11:42:08.241588 Using /lava-10742228
10986 11:42:08.341931 / # export SHELL=/bin/sh
10987 11:42:08.347269 export SHELL=/bin/sh
10989 11:42:08.447775 / # . /lava-10742228/environment
10990 11:42:08.453004 . /lava-10742228/environment
10992 11:42:08.557147 / # /lava-10742228/bin/lava-test-runner /lava-10742228/0
10993 11:42:08.557293 Test shell timeout: 10s (minimum of the action and connection timeout)
10994 11:42:08.562467 /lava-10742228/bin/lava-test-runner /lava-10742228/0
10995 11:42:08.724562 + export TESTRUN_ID=0_lc-compliance
10996 11:42:08.730699 + cd /lava-10742228/0/tests/0_lc-compliance
10997 11:42:08.730791 + cat uuid
10998 11:42:08.734387 + UUID=10742228_1.6.2.3.1
10999 11:42:08.734472 + set +x
11000 11:42:08.737385 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 10742228_1.6.2.3.1>
11001 11:42:08.737643 Received signal: <STARTRUN> 0_lc-compliance 10742228_1.6.2.3.1
11002 11:42:08.737718 Starting test lava.0_lc-compliance (10742228_1.6.2.3.1)
11003 11:42:08.737808 Skipping test definition patterns.
11004 11:42:08.741008 + /usr/bin/lc-compliance-parser.sh
11005 11:42:09.862824 [0:00:26.723556730] [411] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:298 [0mlibcamera v0.0.0+1-0ee93393
11006 11:42:09.865895 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11007 11:42:09.875639 [0:00:26.737414171] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11008 11:42:09.910688 [==========] Running 120 tests from 1 test suite.
11009 11:42:09.926665 [0:00:26.789017770] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11010 11:42:09.957212 [----------] Global test environment set-up.
11011 11:42:09.974778 [0:00:26.838969180] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11012 11:42:10.000113 [----------] 120 tests from CaptureTests/SingleStream
11013 11:42:10.023620 [0:00:26.888852077] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11014 11:42:10.048007 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11015 11:42:10.086152 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11016 11:42:10.086483 Received signal: <TESTSET> START CaptureTests/SingleStream
11017 11:42:10.086571 Starting test_set CaptureTests/SingleStream
11018 11:42:10.089247 Camera needs 4 requests, can't test only 1
11019 11:42:10.132753 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11020 11:42:10.172760
11021 11:42:10.217864 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (52 ms)
11022 11:42:10.269538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11023 11:42:10.269866 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11025 11:42:10.277640 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11026 11:42:10.307221 Camera needs 4 requests, can't test only 2
11027 11:42:10.350110 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11028 11:42:10.383165 [0:00:27.258271452] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11029 11:42:10.389298
11030 11:42:10.440074 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (50 ms)
11031 11:42:10.508449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11032 11:42:10.508785 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11034 11:42:10.520094 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11035 11:42:10.555553 Camera needs 4 requests, can't test only 3
11036 11:42:10.601265 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11037 11:42:10.643679
11038 11:42:10.691188 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (50 ms)
11039 11:42:10.744572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11040 11:42:10.744898 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11042 11:42:10.755181 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11043 11:42:10.788978 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (369 ms)
11044 11:42:10.842183 [0:00:27.728321722] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11045 11:42:10.845526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11046 11:42:10.845795 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11048 11:42:10.856713 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11049 11:42:10.889281 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (470 ms)
11050 11:42:10.947470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11051 11:42:10.947798 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11053 11:42:10.956697 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11054 11:42:11.556286 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (739 ms)
11055 11:42:11.565861 [0:00:28.466661539] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11056 11:42:11.620382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11057 11:42:11.620705 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11059 11:42:11.629802 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11060 11:42:12.447227 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (910 ms)
11061 11:42:12.457122 [0:00:29.376658821] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11062 11:42:12.499670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11063 11:42:12.499990 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11065 11:42:12.508713 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11066 11:42:13.837305 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1414 ms)
11067 11:42:13.847044 [0:00:30.791623548] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11068 11:42:13.891135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11069 11:42:13.891457 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11071 11:42:13.900648 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11072 11:42:15.959712 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2152 ms)
11073 11:42:15.969231 [0:00:32.943604202] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11074 11:42:16.024378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11075 11:42:16.024701 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11077 11:42:16.034412 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11078 11:42:19.151019 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3223 ms)
11079 11:42:19.160761 [0:00:36.166791592] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11080 11:42:19.207393 [0:00:36.215164415] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11081 11:42:19.216263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11082 11:42:19.217185 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11084 11:42:19.226707 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11085 11:42:19.255467 [0:00:36.263503658] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11086 11:42:19.266103 Camera needs 4 requests, can't test only 1
11087 11:42:19.303173 [0:00:36.311571491] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11088 11:42:19.317766 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11089 11:42:19.357080
11090 11:42:19.401225 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (49 ms)
11091 11:42:19.446476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11092 11:42:19.446772 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11094 11:42:19.454744 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11095 11:42:19.485843 Camera needs 4 requests, can't test only 2
11096 11:42:19.535051 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11097 11:42:19.587327
11098 11:42:19.640865 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (48 ms)
11099 11:42:19.661229 [0:00:36.672266019] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11100 11:42:19.692249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11101 11:42:19.692515 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11103 11:42:19.701242 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11104 11:42:19.732203 Camera needs 4 requests, can't test only 3
11105 11:42:19.774191 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11106 11:42:19.814230
11107 11:42:19.860113 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (49 ms)
11108 11:42:19.906786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11109 11:42:19.907104 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11111 11:42:19.915410 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11112 11:42:19.944776 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (361 ms)
11113 11:42:19.995058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11114 11:42:19.995353 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11116 11:42:20.004019 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11117 11:42:20.112478 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (462 ms)
11118 11:42:20.125743 [0:00:37.135258994] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11119 11:42:20.179132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11120 11:42:20.179420 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11122 11:42:20.189316 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11123 11:42:21.110226 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1004 ms)
11124 11:42:21.123572 [0:00:38.139606107] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11125 11:42:21.193678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11126 11:42:21.194435 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11128 11:42:21.206458 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11129 11:42:22.003728 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (898 ms)
11130 11:42:22.016098 [0:00:39.038233104] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11131 11:42:22.071960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11132 11:42:22.072781 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11134 11:42:22.082345 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11135 11:42:23.331136 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1335 ms)
11136 11:42:23.344210 [0:00:40.372265436] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11137 11:42:23.410268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11138 11:42:23.410986 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11140 11:42:23.421630 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11141 11:42:25.421682 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2098 ms)
11142 11:42:25.434761 [0:00:42.471139982] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11143 11:42:25.480792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11144 11:42:25.481116 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11146 11:42:25.490873 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11147 11:42:28.674821 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3263 ms)
11148 11:42:28.687554 [0:00:45.734094566] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11149 11:42:28.732279 [0:00:45.782707252] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11150 11:42:28.738398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11151 11:42:28.738682 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11153 11:42:28.748015 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11154 11:42:28.779805 [0:00:45.831036481] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11155 11:42:28.787873 Camera needs 4 requests, can't test only 1
11156 11:42:28.828533 [0:00:45.879795328] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11157 11:42:28.845554 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11158 11:42:28.898493
11159 11:42:28.956295 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (50 ms)
11160 11:42:28.982995 [ 45.783228] vpu: disabling
11161 11:42:28.986094 [ 45.786008] vproc2: disabling
11162 11:42:28.989254 [ 45.789019] vproc1: disabling
11163 11:42:28.993192 [ 45.792019] vaud18: disabling
11164 11:42:28.996129 [ 45.795166] vsram_others: disabling
11165 11:42:28.999268 [ 45.798770] va09: disabling
11166 11:42:29.002724 [ 45.801611] vsram_md: disabling
11167 11:42:29.006212 [ 45.804833] Vgpu: disabling
11168 11:42:29.019673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11169 11:42:29.019944 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11171 11:42:29.029831 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11172 11:42:29.060462 Camera needs 4 requests, can't test only 2
11173 11:42:29.100113 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11174 11:42:29.133082
11175 11:42:29.177086 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (48 ms)
11176 11:42:29.189998 [0:00:46.240540103] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11177 11:42:29.223537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11178 11:42:29.223831 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11180 11:42:29.232657 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11181 11:42:29.264005 Camera needs 4 requests, can't test only 3
11182 11:42:29.317055 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11183 11:42:29.354844
11184 11:42:29.401672 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (48 ms)
11185 11:42:29.452768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11186 11:42:29.453112 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11188 11:42:29.462889 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11189 11:42:29.497026 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (362 ms)
11190 11:42:29.550884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11191 11:42:29.551189 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11193 11:42:29.560433 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11194 11:42:29.640105 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (460 ms)
11195 11:42:29.653477 [0:00:46.700448684] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11196 11:42:29.697089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11197 11:42:29.697362 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11199 11:42:29.706771 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11200 11:42:30.361738 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (723 ms)
11201 11:42:30.374784 [0:00:47.423410837] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11202 11:42:30.413918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11203 11:42:30.414223 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11205 11:42:30.423809 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11206 11:42:31.253356 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (893 ms)
11207 11:42:31.266107 [0:00:48.316568806] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11208 11:42:31.306274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11209 11:42:31.306564 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11211 11:42:31.315808 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11212 11:42:32.580713 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1329 ms)
11213 11:42:32.593902 [0:00:49.645997284] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 11:42:32.637384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11215 11:42:32.637677 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11217 11:42:32.646856 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11218 11:42:34.703830 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2125 ms)
11219 11:42:34.716868 [0:00:51.771147768] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11220 11:42:34.773995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11221 11:42:34.774260 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11223 11:42:34.784996 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11224 11:42:37.894580 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3194 ms)
11225 11:42:37.907521 [0:00:54.966095308] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 11:42:37.951792 [0:00:55.014842840] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11227 11:42:37.958210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11228 11:42:37.958478 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11230 11:42:37.966620 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11231 11:42:37.999306 [0:00:55.062872754] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11232 11:42:38.003133 Camera needs 4 requests, can't test only 1
11233 11:42:38.040812 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11234 11:42:38.050487 [0:00:55.110850403] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 11:42:38.084858
11236 11:42:38.141871 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (50 ms)
11237 11:42:38.206608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11238 11:42:38.207409 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11240 11:42:38.217280 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11241 11:42:38.255261 Camera needs 4 requests, can't test only 2
11242 11:42:38.310244 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11243 11:42:38.359752
11244 11:42:38.406526 [0:00:55.469999824] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11245 11:42:38.409602 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (48 ms)
11246 11:42:38.467113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11247 11:42:38.467899 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11249 11:42:38.478422 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11250 11:42:38.523552 Camera needs 4 requests, can't test only 3
11251 11:42:38.584787 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11252 11:42:38.641574
11253 11:42:38.708156 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (48 ms)
11254 11:42:38.776394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11255 11:42:38.777219 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11257 11:42:38.788252 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11258 11:42:38.833404 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (358 ms)
11259 11:42:38.867869 [0:00:55.931636422] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11260 11:42:38.891512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11261 11:42:38.891820 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11263 11:42:38.902000 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11264 11:42:38.933495 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (462 ms)
11265 11:42:38.980645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11266 11:42:38.980983 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11268 11:42:38.990021 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11269 11:42:39.583267 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (724 ms)
11270 11:42:39.596441 [0:00:56.656255573] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11271 11:42:39.647287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11272 11:42:39.647570 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11274 11:42:39.658440 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11275 11:42:40.476763 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (895 ms)
11276 11:42:40.489607 [0:00:57.550580825] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11277 11:42:40.534299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11278 11:42:40.534611 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11280 11:42:40.543265 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11281 11:42:41.866737 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1391 ms)
11282 11:42:41.880055 [0:00:58.941376899] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11283 11:42:41.921595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11284 11:42:41.921917 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11286 11:42:41.931386 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11287 11:42:43.927451 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2062 ms)
11288 11:42:43.940656 [0:01:01.003482884] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11289 11:42:43.994513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11290 11:42:43.994786 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11292 11:42:44.005296 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11293 11:42:47.149969 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3224 ms)
11294 11:42:47.163478 [0:01:04.228037264] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11295 11:42:47.206928 [0:01:04.276244229] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11296 11:42:47.255253 [0:01:04.324482819] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11297 11:42:47.304452 [0:01:04.373563385] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 11:42:47.437596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11299 11:42:47.437987 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11301 11:42:47.451926 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11302 11:42:47.486139 Camera needs 4 requests, can't test only 1
11303 11:42:47.536543 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11304 11:42:47.588164
11305 11:42:47.645410 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (49 ms)
11306 11:42:47.725739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11307 11:42:47.726066 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11309 11:42:47.736679 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11310 11:42:47.771132 Camera needs 4 requests, can't test only 2
11311 11:42:47.825614 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11312 11:42:47.875376
11313 11:42:47.934906 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (49 ms)
11314 11:42:48.234236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11315 11:42:48.234613 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11317 11:42:48.247455 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11318 11:42:48.290278 Camera needs 4 requests, can't test only 3
11319 11:42:48.348200 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11320 11:42:48.377379 [0:01:05.446765638] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11321 11:42:48.396561
11322 11:42:48.440679 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (48 ms)
11323 11:42:48.551822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11324 11:42:48.552204 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11326 11:42:48.563155 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11327 11:42:48.602984 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1073 ms)
11328 11:42:48.734096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11329 11:42:48.734467 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11331 11:42:48.746340 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11332 11:42:49.742463 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1375 ms)
11333 11:42:49.755332 [0:01:06.820905649] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11334 11:42:49.804420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11335 11:42:49.804750 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11337 11:42:49.814437 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11338 11:42:51.779279 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2037 ms)
11339 11:42:51.792463 [0:01:08.859071402] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11340 11:42:51.833022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11341 11:42:51.833353 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11343 11:42:51.841180 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11344 11:42:54.451296 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2673 ms)
11345 11:42:54.464163 [0:01:11.532094894] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11346 11:42:54.502707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11347 11:42:54.503036 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11349 11:42:54.510813 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11350 11:42:58.523168 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4074 ms)
11351 11:42:58.536646 [0:01:15.605657158] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 11:42:58.579204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11353 11:42:58.579523 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11355 11:42:58.587811 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11356 11:43:04.881983 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6361 ms)
11357 11:43:04.895324 [0:01:21.967002241] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 11:43:04.974012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11359 11:43:04.974430 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11361 11:43:04.984634 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11362 11:43:14.609281 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9730 ms)
11363 11:43:14.622722 [0:01:31.696841115] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 11:43:14.658238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11365 11:43:14.658574 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11367 11:43:14.671863 [0:01:31.746561446] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11368 11:43:14.675086 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11369 11:43:14.694459 Camera needs 4 requests, can't test only 1
11370 11:43:14.716140 [0:01:31.794829749] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11371 11:43:14.734183 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11372 11:43:14.764337 [0:01:31.842652303] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 11:43:14.771205
11374 11:43:14.816265 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (50 ms)
11375 11:43:14.866865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11376 11:43:14.867251 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11378 11:43:14.873368 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11379 11:43:14.900865 Camera needs 4 requests, can't test only 2
11380 11:43:14.942602 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11381 11:43:14.980771
11382 11:43:15.029215 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (49 ms)
11383 11:43:15.084811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11384 11:43:15.085150 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11386 11:43:15.091483 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11387 11:43:15.121106 Camera needs 4 requests, can't test only 3
11388 11:43:15.162480 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11389 11:43:15.196494
11390 11:43:15.245156 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (48 ms)
11391 11:43:15.300866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11392 11:43:15.301299 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11394 11:43:15.307392 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11395 11:43:15.831139 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1071 ms)
11396 11:43:15.840783 [0:01:32.915048926] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11397 11:43:15.909830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11398 11:43:15.910178 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11400 11:43:15.916266 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11401 11:43:17.204851 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1374 ms)
11402 11:43:17.214745 [0:01:34.289338333] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11403 11:43:17.324223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11404 11:43:17.324713 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11406 11:43:17.330842 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11407 11:43:19.303666 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2100 ms)
11408 11:43:19.313456 [0:01:36.389035867] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11409 11:43:19.390194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11410 11:43:19.390524 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11412 11:43:19.400228 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11413 11:43:22.208835 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2905 ms)
11414 11:43:22.218719 [0:01:39.294032366] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11415 11:43:22.514400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11416 11:43:22.514962 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11418 11:43:22.522920 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11419 11:43:26.280402 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4073 ms)
11420 11:43:26.290283 [0:01:43.366823144] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11421 11:43:26.764386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11422 11:43:26.764980 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11424 11:43:26.770232 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11425 11:43:32.581052 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6302 ms)
11426 11:43:32.591064 [0:01:49.668549504] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11427 11:43:32.728036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11428 11:43:32.728402 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11430 11:43:32.734375 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11431 11:43:42.309656 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9730 ms)
11432 11:43:42.319275 [0:01:59.398222219] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11433 11:43:42.362628 [0:01:59.447139184] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11434 11:43:42.410707 [0:01:59.495375251] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11435 11:43:42.418028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11436 11:43:42.418332 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11438 11:43:42.424449 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11439 11:43:42.459671 [0:01:59.544046659] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11440 11:43:42.462724 Camera needs 4 requests, can't test only 1
11441 11:43:42.500014 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11442 11:43:42.541141
11443 11:43:42.589399 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (49 ms)
11444 11:43:43.555153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11445 11:43:43.555352 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11446 11:43:43.555458 Camera needs 4 requests, can't test only 2
11447 11:43:43.555553 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11448 11:43:43.555647 [0:02:00.618023017] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11449 11:43:43.555740
11450 11:43:43.556014 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11452 11:43:43.605369 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (49 ms)
11453 11:43:44.597297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11454 11:43:44.597635 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11456 11:43:44.605660 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11457 11:43:44.636994 Camera needs 4 requests, can't test only 3
11458 11:43:44.677896 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11459 11:43:44.717315
11460 11:43:44.764189 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (48 ms)
11461 11:43:44.906115 [0:02:01.990454335] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11462 11:43:45.225374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11463 11:43:45.225736 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11465 11:43:45.232148 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11466 11:43:45.265813 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1074 ms)
11467 11:43:45.406481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11468 11:43:45.406787 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11470 11:43:45.413635 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11471 11:43:45.450019 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1373 ms)
11472 11:43:45.589759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11473 11:43:45.590072 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11475 11:43:45.596102 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11476 11:43:46.997229 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2094 ms)
11477 11:43:47.007543 [0:02:04.086499172] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11478 11:43:47.370505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11479 11:43:47.370924 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11481 11:43:47.377245 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11482 11:43:49.669957 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2673 ms)
11483 11:43:49.679842 [0:02:06.758638011] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 11:43:49.723789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11485 11:43:49.724111 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11487 11:43:49.730781 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11488 11:43:53.741269 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4070 ms)
11489 11:43:53.751551 [0:02:10.828486380] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 11:43:53.809388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11491 11:43:53.809729 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11493 11:43:53.815327 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11494 11:44:00.068922 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6327 ms)
11495 11:44:00.079136 [0:02:17.155080233] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 11:44:00.906219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11497 11:44:00.906642 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11499 11:44:00.914090 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11500 11:44:09.765192 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9696 ms)
11501 11:44:09.775039 [0:02:26.850823223] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 11:44:09.818555 [0:02:26.899962230] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11503 11:44:09.867154 [0:02:26.948540931] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11504 11:44:09.915548 [0:02:26.996738686] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 11:44:10.647899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11506 11:44:10.648583 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11508 11:44:10.656655 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11509 11:44:10.696308 Camera needs 4 requests, can't test only 1
11510 11:44:10.746968 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11511 11:44:10.798796
11512 11:44:10.853593 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (49 ms)
11513 11:44:10.988407 [0:02:28.069513382] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 11:44:11.778591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11515 11:44:11.778771 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11516 11:44:11.779081 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11518 11:44:11.810751 Camera needs 4 requests, can't test only 2
11519 11:44:11.852585 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11520 11:44:11.892675
11521 11:44:11.942674 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (49 ms)
11522 11:44:12.361679 [0:02:29.443121143] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11523 11:44:12.624971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11524 11:44:12.625343 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11526 11:44:12.633518 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11527 11:44:12.667561 Camera needs 4 requests, can't test only 3
11528 11:44:12.717043 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11529 11:44:12.757675
11530 11:44:12.811849 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (48 ms)
11531 11:44:13.399100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11532 11:44:13.399501 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11534 11:44:13.406582 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11535 11:44:13.442672 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1073 ms)
11536 11:44:14.013012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11537 11:44:14.013399 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11539 11:44:14.019205 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11540 11:44:14.053601 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1373 ms)
11541 11:44:14.169216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11542 11:44:14.169555 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11544 11:44:14.176161 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11545 11:44:14.454930 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2098 ms)
11546 11:44:14.465129 [0:02:31.540507878] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11547 11:44:14.511349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11548 11:44:14.511672 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11550 11:44:14.517909 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11551 11:44:17.127491 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2672 ms)
11552 11:44:17.136935 [0:02:34.212678649] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11553 11:44:17.347645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11554 11:44:17.347957 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11556 11:44:17.354314 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11557 11:44:21.197713 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4071 ms)
11558 11:44:21.207999 [0:02:38.283543467] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11559 11:44:21.479920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11560 11:44:21.480276 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11562 11:44:21.487616 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11563 11:44:27.561607 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6363 ms)
11564 11:44:27.570878 [0:02:44.646985099] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11565 11:44:29.453043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11566 11:44:29.454092 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11567 11:44:29.455271 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11569 11:44:37.286523 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9726 ms)
11570 11:44:37.296221 [0:02:54.372331668] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11571 11:44:37.612454 [0:02:54.694495910] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11572 11:44:37.871399 [0:02:54.953640595] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11573 11:44:38.163688 [0:02:55.245538041] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11574 11:44:39.712459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11575 11:44:39.713397 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11577 11:44:39.714693 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11578 11:44:39.715153 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (322 ms)
11579 11:44:39.715741 [0:02:55.604061295] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11580 11:44:39.716288 [0:02:56.065097888] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11581 11:44:39.716859 [0:02:56.788680637] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 11:44:40.196685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11583 11:44:40.197046 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11585 11:44:40.207545 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11586 11:44:40.240013 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (259 ms)
11587 11:44:40.533343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11588 11:44:40.533558 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11589 11:44:40.533882 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11591 11:44:40.551995 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (292 ms)
11592 11:44:40.599350 [0:02:57.681684249] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11593 11:44:40.880085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11594 11:44:40.880436 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11596 11:44:41.043243 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11597 11:44:41.043927 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (358 ms)
11598 11:44:41.302982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11599 11:44:41.303844 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11601 11:44:41.314905 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11602 11:44:41.352648 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (461 ms)
11603 11:44:41.988676 [0:02:59.071403073] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11604 11:44:42.732699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11605 11:44:42.733897 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11607 11:44:42.747215 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11608 11:44:42.779474 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (724 ms)
11609 11:44:44.046939 [0:03:01.129520589] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11610 11:44:45.128674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11611 11:44:45.129060 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11613 11:44:45.140008 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11614 11:44:45.176298 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (893 ms)
11615 11:44:45.235250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11616 11:44:45.235597 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11618 11:44:45.246415 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11619 11:44:45.283248 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1390 ms)
11620 11:44:47.678865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11621 11:44:47.678996 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11622 11:44:47.679068 [0:03:04.385318704] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11623 11:44:47.679133 [0:03:04.709037386] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 11:44:47.679383 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11626 11:44:47.918124 [0:03:05.001152910] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11627 11:44:48.033279 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2058 ms)
11628 11:44:48.092990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11629 11:44:48.093314 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11631 11:44:48.102026 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11632 11:44:48.133166 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3255 ms)
11633 11:44:48.210540 [0:03:05.293477737] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11634 11:44:48.569098 [0:03:05.652152562] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11635 11:44:49.028563 [0:03:06.111251797] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 11:44:49.964551 [0:03:06.832122006] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11637 11:44:49.971009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11638 11:44:49.971368 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11640 11:44:49.981040 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11641 11:44:50.016445 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (324 ms)
11642 11:44:50.641491 [0:03:07.724200438] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11643 11:44:50.752634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11644 11:44:50.753567 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11646 11:44:50.760788 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11647 11:44:50.801698 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (292 ms)
11648 11:44:52.175208 [0:03:09.114390675] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11649 11:44:52.246106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11650 11:44:52.247779 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11652 11:44:52.261976 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11653 11:44:52.296422 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (293 ms)
11654 11:44:52.461460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11655 11:44:52.462327 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11657 11:44:52.468065 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11658 11:44:52.574002 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (359 ms)
11659 11:44:52.587040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11660 11:44:52.587479 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11662 11:44:52.593907 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11663 11:44:52.627402 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (459 ms)
11664 11:44:52.737743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11665 11:44:52.738798 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11667 11:44:52.747094 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11668 11:44:52.874782 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (720 ms)
11669 11:44:52.888238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11670 11:44:52.888592 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11672 11:44:52.894478 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11673 11:44:52.927952 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (892 ms)
11674 11:44:53.030592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11675 11:44:53.030958 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11677 11:44:53.037368 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11678 11:44:53.069856 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1389 ms)
11679 11:44:53.919024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11680 11:44:53.919788 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11681 11:44:53.920662 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11683 11:44:54.085018 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2058 ms)
11684 11:44:54.094395 [0:03:11.172314288] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11685 11:44:55.002135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11686 11:44:55.002785 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11688 11:44:55.010457 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11689 11:44:57.340785 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3256 ms)
11690 11:44:57.350689 [0:03:14.428214517] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11691 11:44:57.668511 [0:03:14.751916797] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11692 11:44:57.753364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11693 11:44:57.754136 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11695 11:44:57.762981 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11696 11:44:57.803944 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (323 ms)
11697 11:44:58.088404 [0:03:15.013465833] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11698 11:44:58.222874 [0:03:15.306129997] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11699 11:44:58.393175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11700 11:44:58.394291 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11702 11:44:58.402565 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11703 11:44:58.444135 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (261 ms)
11704 11:44:58.511530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11705 11:44:58.511952 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11707 11:44:58.518204 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11708 11:44:58.552944 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (292 ms)
11709 11:44:58.606912 [0:03:15.665484352] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11710 11:44:58.627977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11711 11:44:58.629128 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11713 11:44:58.635408 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11714 11:44:58.709508 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (359 ms)
11715 11:44:58.730947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11716 11:44:58.731281 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11718 11:44:58.737581 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11719 11:44:59.039963 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (459 ms)
11720 11:44:59.046741 [0:03:16.126123309] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11721 11:44:59.239222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11722 11:44:59.240420 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11724 11:44:59.247276 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11725 11:44:59.728722 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (691 ms)
11726 11:44:59.738582 [0:03:16.817704064] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11727 11:45:00.627269 [0:03:17.710759709] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11728 11:45:01.431669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11729 11:45:01.431867 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11730 11:45:01.431973 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (893 ms)
11731 11:45:01.432259 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11733 11:45:01.450713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11734 11:45:01.451039 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11736 11:45:01.457944 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11737 11:45:02.012386 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1391 ms)
11738 11:45:02.022281 [0:03:19.101130223] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11739 11:45:02.985228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11740 11:45:02.985389 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11741 11:45:02.985686 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11743 11:45:04.071572 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2060 ms)
11744 11:45:04.081661 [0:03:21.160964209] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11745 11:45:04.469633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11746 11:45:04.469959 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11748 11:45:04.476193 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11749 11:45:07.326166 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3254 ms)
11750 11:45:07.336086 [0:03:24.415869503] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11751 11:45:07.653947 [0:03:24.739024678] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11752 11:45:07.913450 [0:03:24.998364476] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11753 11:45:08.205974 [0:03:25.290814765] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11754 11:45:08.565175 [0:03:25.650077933] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11755 11:45:08.838691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11756 11:45:08.838904 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11757 11:45:08.839030 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (324 ms)
11758 11:45:08.839302 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11760 11:45:08.848465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11761 11:45:08.848854 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11763 11:45:08.857074 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11764 11:45:08.891988 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (259 ms)
11765 11:45:08.959148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11766 11:45:08.959929 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11768 11:45:08.970733 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11769 11:45:09.009901 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (292 ms)
11770 11:45:09.024786 [0:03:26.109813429] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11771 11:45:09.444867 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11773 11:45:09.447905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11774 11:45:09.454796 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11775 11:45:09.489559 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (360 ms)
11776 11:45:09.644144 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11778 11:45:09.647326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11779 11:45:09.653816 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11780 11:45:09.687859 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (459 ms)
11781 11:45:09.736098 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11783 11:45:09.739330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11784 11:45:09.749327 [0:03:26.831032033] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11785 11:45:09.756023 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11786 11:45:09.775753 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (722 ms)
11787 11:45:09.854785 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11789 11:45:09.857285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11790 11:45:09.865359 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11791 11:45:10.632105 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (891 ms)
11792 11:45:10.642080 [0:03:27.722789429] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11793 11:45:10.681853 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11795 11:45:10.684762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11796 11:45:10.691203 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11797 11:45:11.958742 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1327 ms)
11798 11:45:11.969208 [0:03:29.049704814] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11799 11:45:12.005127 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11801 11:45:12.008062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11802 11:45:12.014678 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11803 11:45:14.048304 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2090 ms)
11804 11:45:14.058347 [0:03:31.139402693] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1028 [0mconfiguring streams: (0) 1280x720-MJPEG
11805 11:45:15.350527 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11807 11:45:15.353610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11808 11:45:15.360908 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11809 11:45:17.325785 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3253 ms)
11810 11:45:18.836430 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11812 11:45:18.839618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11813 11:45:18.847728 [----------] 120 tests from CaptureTests/SingleStream (187655 ms total)
11814 11:45:18.889140
11815 11:45:18.936041 [----------] Global test environment tear-down
11816 11:45:18.979778 [==========] 120 tests from 1 test suite ran. (187655 ms total)
11817 11:45:19.019547 <LAVA_SIGNAL_TESTSET STOP>
11818 11:45:19.019881 Received signal: <TESTSET> STOP
11819 11:45:19.019987 Closing test_set CaptureTests/SingleStream
11820 11:45:19.057509 + set +x
11821 11:45:19.060729 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 10742228_1.6.2.3.1>
11822 11:45:19.061139 Received signal: <ENDRUN> 0_lc-compliance 10742228_1.6.2.3.1
11823 11:45:19.061370 Ending use of test pattern.
11824 11:45:19.061586 Ending test lava.0_lc-compliance (10742228_1.6.2.3.1), duration 190.32
11826 11:45:19.759159 <LAVA_TEST_RUNNER EXIT>
11827 11:45:19.760043 ok: lava_test_shell seems to have completed
11828 11:45:19.776450 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11829 11:45:19.777570 end: 3.1 lava-test-shell (duration 00:03:12) [common]
11830 11:45:19.778189 end: 3 lava-test-retry (duration 00:03:12) [common]
11831 11:45:19.778811 start: 4 finalize (timeout 00:10:00) [common]
11832 11:45:19.779435 start: 4.1 power-off (timeout 00:00:30) [common]
11833 11:45:19.780910 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11834 11:45:19.902760 >> Command sent successfully.
11835 11:45:19.913207 Returned 0 in 0 seconds
11836 11:45:20.014543 end: 4.1 power-off (duration 00:00:00) [common]
11838 11:45:20.015975 start: 4.2 read-feedback (timeout 00:10:00) [common]
11839 11:45:20.017325 Listened to connection for namespace 'common' for up to 1s
11840 11:45:21.016878 Finalising connection for namespace 'common'
11841 11:45:21.017140 Disconnecting from shell: Finalise
11842 11:45:21.017295 / #
11843 11:45:21.117723 end: 4.2 read-feedback (duration 00:00:01) [common]
11844 11:45:21.118062 end: 4 finalize (duration 00:00:01) [common]
11845 11:45:21.118337 Cleaning after the job
11846 11:45:21.118581 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/ramdisk
11847 11:45:21.119593 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/kernel
11848 11:45:21.126185 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/dtb
11849 11:45:21.126444 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/nfsrootfs
11850 11:45:21.139875 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742228/tftp-deploy-t5m_fu4a/modules
11851 11:45:21.145502 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742228
11852 11:45:21.591892 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742228
11853 11:45:21.592061 Job finished correctly