Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 33
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 27
- Errors: 3
1 11:46:02.971592 lava-dispatcher, installed at version: 2023.05.1
2 11:46:02.971824 start: 0 validate
3 11:46:02.971976 Start time: 2023-06-15 11:46:02.971968+00:00 (UTC)
4 11:46:02.972114 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:46:02.972260 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 11:46:03.235458 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:46:03.235686 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:46:03.493424 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:46:03.493621 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:46:03.742991 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:46:03.743174 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:46:04.009007 validate duration: 1.04
14 11:46:04.009314 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:46:04.009415 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:46:04.009504 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:46:04.009621 Not decompressing ramdisk as can be used compressed.
18 11:46:04.009710 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230609.0/arm64/rootfs.cpio.gz
19 11:46:04.009809 saving as /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/ramdisk/rootfs.cpio.gz
20 11:46:04.009875 total size: 84920281 (80MB)
21 11:46:04.010982 progress 0% (0MB)
22 11:46:04.034152 progress 5% (4MB)
23 11:46:04.058089 progress 10% (8MB)
24 11:46:04.080660 progress 15% (12MB)
25 11:46:04.103559 progress 20% (16MB)
26 11:46:04.126130 progress 25% (20MB)
27 11:46:04.149009 progress 30% (24MB)
28 11:46:04.172354 progress 35% (28MB)
29 11:46:04.195444 progress 40% (32MB)
30 11:46:04.219066 progress 45% (36MB)
31 11:46:04.243157 progress 50% (40MB)
32 11:46:04.267752 progress 55% (44MB)
33 11:46:04.291654 progress 60% (48MB)
34 11:46:04.314463 progress 65% (52MB)
35 11:46:04.337575 progress 70% (56MB)
36 11:46:04.360643 progress 75% (60MB)
37 11:46:04.384123 progress 80% (64MB)
38 11:46:04.407230 progress 85% (68MB)
39 11:46:04.430453 progress 90% (72MB)
40 11:46:04.453032 progress 95% (76MB)
41 11:46:04.477838 progress 100% (80MB)
42 11:46:04.478140 80MB downloaded in 0.47s (172.95MB/s)
43 11:46:04.478367 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:46:04.478801 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:46:04.478930 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:46:04.479058 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:46:04.479252 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:46:04.479358 saving as /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/kernel/Image
50 11:46:04.479468 total size: 47581696 (45MB)
51 11:46:04.479584 No compression specified
52 11:46:04.481337 progress 0% (0MB)
53 11:46:04.495256 progress 5% (2MB)
54 11:46:04.508800 progress 10% (4MB)
55 11:46:04.521799 progress 15% (6MB)
56 11:46:04.535050 progress 20% (9MB)
57 11:46:04.548283 progress 25% (11MB)
58 11:46:04.561063 progress 30% (13MB)
59 11:46:04.574553 progress 35% (15MB)
60 11:46:04.588067 progress 40% (18MB)
61 11:46:04.602340 progress 45% (20MB)
62 11:46:04.616493 progress 50% (22MB)
63 11:46:04.630426 progress 55% (24MB)
64 11:46:04.644640 progress 60% (27MB)
65 11:46:04.657660 progress 65% (29MB)
66 11:46:04.670858 progress 70% (31MB)
67 11:46:04.684370 progress 75% (34MB)
68 11:46:04.697534 progress 80% (36MB)
69 11:46:04.711370 progress 85% (38MB)
70 11:46:04.724462 progress 90% (40MB)
71 11:46:04.737743 progress 95% (43MB)
72 11:46:04.752048 progress 100% (45MB)
73 11:46:04.752256 45MB downloaded in 0.27s (166.35MB/s)
74 11:46:04.752475 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:46:04.752883 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:46:04.753021 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:46:04.753157 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:46:04.753342 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:46:04.753450 saving as /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/dtb/mt8192-asurada-spherion-r0.dtb
81 11:46:04.753555 total size: 46924 (0MB)
82 11:46:04.753661 No compression specified
83 11:46:04.755363 progress 69% (0MB)
84 11:46:04.755678 progress 100% (0MB)
85 11:46:04.755879 0MB downloaded in 0.00s (19.27MB/s)
86 11:46:04.756061 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:46:04.756455 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:46:04.756591 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:46:04.756718 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:46:04.756882 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:46:04.756996 saving as /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/modules/modules.tar
93 11:46:04.757099 total size: 8555256 (8MB)
94 11:46:04.757208 Using unxz to decompress xz
95 11:46:04.760971 progress 0% (0MB)
96 11:46:04.786643 progress 5% (0MB)
97 11:46:04.816196 progress 10% (0MB)
98 11:46:04.844582 progress 15% (1MB)
99 11:46:04.872875 progress 20% (1MB)
100 11:46:04.901107 progress 25% (2MB)
101 11:46:04.928531 progress 30% (2MB)
102 11:46:04.959574 progress 35% (2MB)
103 11:46:04.989267 progress 40% (3MB)
104 11:46:05.017777 progress 45% (3MB)
105 11:46:05.050760 progress 50% (4MB)
106 11:46:05.080620 progress 55% (4MB)
107 11:46:05.111577 progress 60% (4MB)
108 11:46:05.139851 progress 65% (5MB)
109 11:46:05.167716 progress 70% (5MB)
110 11:46:05.196494 progress 75% (6MB)
111 11:46:05.224545 progress 80% (6MB)
112 11:46:05.253635 progress 85% (6MB)
113 11:46:05.288675 progress 90% (7MB)
114 11:46:05.321568 progress 95% (7MB)
115 11:46:05.349750 progress 100% (8MB)
116 11:46:05.354527 8MB downloaded in 0.60s (13.66MB/s)
117 11:46:05.354858 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:46:05.355263 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:46:05.355391 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:46:05.355523 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:46:05.355638 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:46:05.355759 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:46:05.356021 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b
125 11:46:05.356189 makedir: /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin
126 11:46:05.356325 makedir: /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/tests
127 11:46:05.356455 makedir: /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/results
128 11:46:05.356606 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-add-keys
129 11:46:05.356788 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-add-sources
130 11:46:05.356953 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-background-process-start
131 11:46:05.357132 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-background-process-stop
132 11:46:05.357298 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-common-functions
133 11:46:05.357461 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-echo-ipv4
134 11:46:05.357626 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-install-packages
135 11:46:05.357787 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-installed-packages
136 11:46:05.357944 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-os-build
137 11:46:05.358111 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-probe-channel
138 11:46:05.358273 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-probe-ip
139 11:46:05.358428 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-target-ip
140 11:46:05.358589 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-target-mac
141 11:46:05.358745 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-target-storage
142 11:46:05.358907 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-test-case
143 11:46:05.359070 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-test-event
144 11:46:05.359228 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-test-feedback
145 11:46:05.359387 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-test-raise
146 11:46:05.359547 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-test-reference
147 11:46:05.359705 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-test-runner
148 11:46:05.359863 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-test-set
149 11:46:05.360022 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-test-shell
150 11:46:05.360183 Updating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-install-packages (oe)
151 11:46:05.360365 Updating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/bin/lava-installed-packages (oe)
152 11:46:05.360523 Creating /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/environment
153 11:46:05.360659 LAVA metadata
154 11:46:05.360766 - LAVA_JOB_ID=10742265
155 11:46:05.360870 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:46:05.361018 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:46:05.361117 skipped lava-vland-overlay
158 11:46:05.361228 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:46:05.361340 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:46:05.361436 skipped lava-multinode-overlay
161 11:46:05.361548 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:46:05.361666 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:46:05.361780 Loading test definitions
164 11:46:05.361915 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 11:46:05.362028 Using /lava-10742265 at stage 0
166 11:46:05.362184 Fetching tests from https://github.com/kernelci/kernelci-core
167 11:46:05.362309 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/0/tests/0_sleep'
168 11:46:06.079855 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/0/tests/0_sleep
169 11:46:06.081169 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 11:46:06.081701 uuid=10742265_1.5.2.3.1 testdef=None
171 11:46:06.081883 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 11:46:06.082272 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 11:46:06.083105 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 11:46:06.083491 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 11:46:06.084554 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 11:46:06.084956 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 11:46:06.086008 runner path: /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/0/tests/0_sleep test_uuid 10742265_1.5.2.3.1
181 11:46:06.086130 sleep_params='mem freeze'
182 11:46:06.086318 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 11:46:06.086681 Creating lava-test-runner.conf files
185 11:46:06.086787 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742265/lava-overlay-f5drdt4b/lava-10742265/0 for stage 0
186 11:46:06.086921 - 0_sleep
187 11:46:06.087065 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 11:46:06.087192 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 11:46:06.228713 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 11:46:06.228913 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 11:46:06.229046 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 11:46:06.229177 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 11:46:06.229282 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 11:46:08.733918 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 11:46:08.734309 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 11:46:08.734458 extracting modules file /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742265/extract-overlay-ramdisk-f9ofs8vm/ramdisk
197 11:46:09.038720 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 11:46:09.038949 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 11:46:09.039082 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742265/compress-overlay-ky6l2bcm/overlay-1.5.2.4.tar.gz to ramdisk
200 11:46:09.039191 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742265/compress-overlay-ky6l2bcm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742265/extract-overlay-ramdisk-f9ofs8vm/ramdisk
201 11:46:09.132708 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 11:46:09.132909 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 11:46:09.133174 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 11:46:09.133306 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 11:46:09.133427 Building ramdisk /var/lib/lava/dispatcher/tmp/10742265/extract-overlay-ramdisk-f9ofs8vm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742265/extract-overlay-ramdisk-f9ofs8vm/ramdisk
206 11:46:10.683475 >> 561605 blocks
207 11:46:21.235403 rename /var/lib/lava/dispatcher/tmp/10742265/extract-overlay-ramdisk-f9ofs8vm/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/ramdisk/ramdisk.cpio.gz
208 11:46:21.235931 end: 1.5.7 compress-ramdisk (duration 00:00:12) [common]
209 11:46:21.236114 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 11:46:21.236251 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 11:46:21.236380 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/kernel/Image'
212 11:46:35.221871 Returned 0 in 13 seconds
213 11:46:35.322523 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/kernel/image.itb
214 11:46:36.529660 output: FIT description: Kernel Image image with one or more FDT blobs
215 11:46:36.530054 output: Created: Thu Jun 15 12:46:36 2023
216 11:46:36.530140 output: Image 0 (kernel-1)
217 11:46:36.530209 output: Description:
218 11:46:36.530281 output: Created: Thu Jun 15 12:46:36 2023
219 11:46:36.530349 output: Type: Kernel Image
220 11:46:36.530413 output: Compression: lzma compressed
221 11:46:36.530478 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
222 11:46:36.530562 output: Architecture: AArch64
223 11:46:36.530626 output: OS: Linux
224 11:46:36.530687 output: Load Address: 0x00000000
225 11:46:36.530751 output: Entry Point: 0x00000000
226 11:46:36.530810 output: Hash algo: crc32
227 11:46:36.530867 output: Hash value: cd22d0e5
228 11:46:36.530923 output: Image 1 (fdt-1)
229 11:46:36.530979 output: Description: mt8192-asurada-spherion-r0
230 11:46:36.531035 output: Created: Thu Jun 15 12:46:36 2023
231 11:46:36.531091 output: Type: Flat Device Tree
232 11:46:36.531146 output: Compression: uncompressed
233 11:46:36.531202 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
234 11:46:36.531258 output: Architecture: AArch64
235 11:46:36.531313 output: Hash algo: crc32
236 11:46:36.531368 output: Hash value: 1df858fa
237 11:46:36.531424 output: Image 2 (ramdisk-1)
238 11:46:36.531479 output: Description: unavailable
239 11:46:36.531534 output: Created: Thu Jun 15 12:46:36 2023
240 11:46:36.531589 output: Type: RAMDisk Image
241 11:46:36.531645 output: Compression: Unknown Compression
242 11:46:36.531700 output: Data Size: 98158137 Bytes = 95857.56 KiB = 93.61 MiB
243 11:46:36.531756 output: Architecture: AArch64
244 11:46:36.531811 output: OS: Linux
245 11:46:36.531866 output: Load Address: unavailable
246 11:46:36.531921 output: Entry Point: unavailable
247 11:46:36.531984 output: Hash algo: crc32
248 11:46:36.532057 output: Hash value: 85b9e8cc
249 11:46:36.532115 output: Default Configuration: 'conf-1'
250 11:46:36.532170 output: Configuration 0 (conf-1)
251 11:46:36.532226 output: Description: mt8192-asurada-spherion-r0
252 11:46:36.532281 output: Kernel: kernel-1
253 11:46:36.532337 output: Init Ramdisk: ramdisk-1
254 11:46:36.532392 output: FDT: fdt-1
255 11:46:36.532447 output: Loadables: kernel-1
256 11:46:36.532503 output:
257 11:46:36.532698 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 11:46:36.532798 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 11:46:36.532910 end: 1.5 prepare-tftp-overlay (duration 00:00:31) [common]
260 11:46:36.533017 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 11:46:36.533103 No LXC device requested
262 11:46:36.533186 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 11:46:36.533274 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 11:46:36.533355 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 11:46:36.533424 Checking files for TFTP limit of 4294967296 bytes.
266 11:46:36.533929 end: 1 tftp-deploy (duration 00:00:33) [common]
267 11:46:36.534038 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 11:46:36.534133 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 11:46:36.534256 substitutions:
270 11:46:36.534327 - {DTB}: 10742265/tftp-deploy-boyaql5d/dtb/mt8192-asurada-spherion-r0.dtb
271 11:46:36.534392 - {INITRD}: 10742265/tftp-deploy-boyaql5d/ramdisk/ramdisk.cpio.gz
272 11:46:36.534454 - {KERNEL}: 10742265/tftp-deploy-boyaql5d/kernel/Image
273 11:46:36.534514 - {LAVA_MAC}: None
274 11:46:36.534574 - {PRESEED_CONFIG}: None
275 11:46:36.534633 - {PRESEED_LOCAL}: None
276 11:46:36.534690 - {RAMDISK}: 10742265/tftp-deploy-boyaql5d/ramdisk/ramdisk.cpio.gz
277 11:46:36.534748 - {ROOT_PART}: None
278 11:46:36.534804 - {ROOT}: None
279 11:46:36.534861 - {SERVER_IP}: 192.168.201.1
280 11:46:36.534918 - {TEE}: None
281 11:46:36.534975 Parsed boot commands:
282 11:46:36.535031 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 11:46:36.535205 Parsed boot commands: tftpboot 192.168.201.1 10742265/tftp-deploy-boyaql5d/kernel/image.itb 10742265/tftp-deploy-boyaql5d/kernel/cmdline
284 11:46:36.535297 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 11:46:36.535386 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 11:46:36.535480 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 11:46:36.535568 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 11:46:36.535643 Not connected, no need to disconnect.
289 11:46:36.535719 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 11:46:36.535801 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 11:46:36.535872 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
292 11:46:36.539003 Setting prompt string to ['lava-test: # ']
293 11:46:36.539348 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 11:46:36.539464 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 11:46:36.539569 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 11:46:36.539665 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 11:46:36.539871 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
298 11:46:41.682984 >> Command sent successfully.
299 11:46:41.685590 Returned 0 in 5 seconds
300 11:46:41.785996 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 11:46:41.786321 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 11:46:41.786427 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 11:46:41.786519 Setting prompt string to 'Starting depthcharge on Spherion...'
305 11:46:41.786592 Changing prompt to 'Starting depthcharge on Spherion...'
306 11:46:41.786666 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 11:46:41.786924 [Enter `^Ec?' for help]
308 11:46:41.958880
309 11:46:41.959063
310 11:46:41.959179 F0: 102B 0000
311 11:46:41.959288
312 11:46:41.961959 F3: 1001 0000 [0200]
313 11:46:41.962052
314 11:46:41.962122 F3: 1001 0000
315 11:46:41.962188
316 11:46:41.962251 F7: 102D 0000
317 11:46:41.962313
318 11:46:41.965267 F1: 0000 0000
319 11:46:41.965355
320 11:46:41.965424 V0: 0000 0000 [0001]
321 11:46:41.965490
322 11:46:41.968826 00: 0007 8000
323 11:46:41.968953
324 11:46:41.969048 01: 0000 0000
325 11:46:41.969116
326 11:46:41.971856 BP: 0C00 0209 [0000]
327 11:46:41.971961
328 11:46:41.972045 G0: 1182 0000
329 11:46:41.972108
330 11:46:41.975394 EC: 0000 0021 [4000]
331 11:46:41.975499
332 11:46:41.975594 S7: 0000 0000 [0000]
333 11:46:41.975685
334 11:46:41.979134 CC: 0000 0000 [0001]
335 11:46:41.979234
336 11:46:41.979326 T0: 0000 0040 [010F]
337 11:46:41.979418
338 11:46:41.979507 Jump to BL
339 11:46:41.979596
340 11:46:42.005985
341 11:46:42.006116
342 11:46:42.006224
343 11:46:42.015870 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 11:46:42.015991 ARM64: Exception handlers installed.
345 11:46:42.019569 ARM64: Testing exception
346 11:46:42.023373 ARM64: Done test exception
347 11:46:42.029903 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 11:46:42.039695 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 11:46:42.046628 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 11:46:42.056565 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 11:46:42.063490 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 11:46:42.073436 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 11:46:42.083807 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 11:46:42.090324 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 11:46:42.108594 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 11:46:42.111746 WDT: Last reset was cold boot
357 11:46:42.115001 SPI1(PAD0) initialized at 2873684 Hz
358 11:46:42.118215 SPI5(PAD0) initialized at 992727 Hz
359 11:46:42.121976 VBOOT: Loading verstage.
360 11:46:42.128331 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 11:46:42.131478 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 11:46:42.134905 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 11:46:42.138292 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 11:46:42.145900 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 11:46:42.152345 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 11:46:42.163643 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 11:46:42.163736
368 11:46:42.163806
369 11:46:42.173402 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 11:46:42.176859 ARM64: Exception handlers installed.
371 11:46:42.179939 ARM64: Testing exception
372 11:46:42.183514 ARM64: Done test exception
373 11:46:42.186704 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 11:46:42.190208 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 11:46:42.204619 Probing TPM: . done!
376 11:46:42.204702 TPM ready after 0 ms
377 11:46:42.211356 Connected to device vid:did:rid of 1ae0:0028:00
378 11:46:42.221130 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 11:46:42.276484 Initialized TPM device CR50 revision 0
380 11:46:42.287514 tlcl_send_startup: Startup return code is 0
381 11:46:42.287609 TPM: setup succeeded
382 11:46:42.298683 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 11:46:42.307810 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 11:46:42.317552 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 11:46:42.327234 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 11:46:42.330473 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 11:46:42.337756 in-header: 03 07 00 00 08 00 00 00
388 11:46:42.341375 in-data: aa e4 47 04 13 02 00 00
389 11:46:42.344570 Chrome EC: UHEPI supported
390 11:46:42.351562 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 11:46:42.355592 in-header: 03 ad 00 00 08 00 00 00
392 11:46:42.359072 in-data: 00 20 20 08 00 00 00 00
393 11:46:42.359158 Phase 1
394 11:46:42.363037 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 11:46:42.370313 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 11:46:42.377348 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 11:46:42.377435 Recovery requested (1009000e)
398 11:46:42.388208 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 11:46:42.394121 tlcl_extend: response is 0
400 11:46:42.404362 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 11:46:42.410776 tlcl_extend: response is 0
402 11:46:42.417752 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 11:46:42.437678 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 11:46:42.444253 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 11:46:42.444377
406 11:46:42.444486
407 11:46:42.454044 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 11:46:42.457828 ARM64: Exception handlers installed.
409 11:46:42.457946 ARM64: Testing exception
410 11:46:42.460933 ARM64: Done test exception
411 11:46:42.483093 pmic_efuse_setting: Set efuses in 11 msecs
412 11:46:42.486377 pmwrap_interface_init: Select PMIF_VLD_RDY
413 11:46:42.493120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 11:46:42.496422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 11:46:42.503113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 11:46:42.506415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 11:46:42.509713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 11:46:42.516822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 11:46:42.520454 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 11:46:42.524152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 11:46:42.532002 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 11:46:42.535885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 11:46:42.539590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 11:46:42.543285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 11:46:42.549816 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 11:46:42.556314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 11:46:42.559612 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 11:46:42.566504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 11:46:42.573493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 11:46:42.576783 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 11:46:42.584065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 11:46:42.590850 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 11:46:42.594098 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 11:46:42.600993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 11:46:42.604618 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 11:46:42.611176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 11:46:42.617801 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 11:46:42.620982 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 11:46:42.627659 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 11:46:42.630883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 11:46:42.637803 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 11:46:42.640905 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 11:46:42.647671 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 11:46:42.650987 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 11:46:42.657782 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 11:46:42.661001 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 11:46:42.667346 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 11:46:42.670827 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 11:46:42.677235 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 11:46:42.680794 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 11:46:42.687881 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 11:46:42.691218 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 11:46:42.694794 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 11:46:42.698198 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 11:46:42.704897 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 11:46:42.708205 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 11:46:42.711427 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 11:46:42.719033 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 11:46:42.722703 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 11:46:42.726384 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 11:46:42.730223 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 11:46:42.733680 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 11:46:42.737265 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 11:46:42.744776 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 11:46:42.756003 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 11:46:42.759846 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 11:46:42.767334 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 11:46:42.774475 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 11:46:42.780942 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 11:46:42.784693 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 11:46:42.787626 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 11:46:42.795546 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2
473 11:46:42.802153 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 11:46:42.805274 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 11:46:42.808951 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 11:46:42.820343 [RTC]rtc_get_frequency_meter,154: input=15, output=771
477 11:46:42.829540 [RTC]rtc_get_frequency_meter,154: input=23, output=957
478 11:46:42.839485 [RTC]rtc_get_frequency_meter,154: input=19, output=864
479 11:46:42.849009 [RTC]rtc_get_frequency_meter,154: input=17, output=818
480 11:46:42.858356 [RTC]rtc_get_frequency_meter,154: input=16, output=795
481 11:46:42.861630 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
482 11:46:42.864849 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
483 11:46:42.871601 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
484 11:46:42.874933 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
485 11:46:42.878200 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
486 11:46:42.881368 ADC[4]: Raw value=902507 ID=7
487 11:46:42.884804 ADC[3]: Raw value=213179 ID=1
488 11:46:42.884910 RAM Code: 0x71
489 11:46:42.891557 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
490 11:46:42.895053 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
491 11:46:42.904921 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
492 11:46:42.911655 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 11:46:42.914898 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
494 11:46:42.918187 in-header: 03 07 00 00 08 00 00 00
495 11:46:42.921556 in-data: aa e4 47 04 13 02 00 00
496 11:46:42.925043 Chrome EC: UHEPI supported
497 11:46:42.931525 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
498 11:46:42.934662 in-header: 03 ed 00 00 08 00 00 00
499 11:46:42.937849 in-data: 80 20 60 08 00 00 00 00
500 11:46:42.941202 MRC: failed to locate region type 0.
501 11:46:42.947908 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
502 11:46:42.951098 DRAM-K: Running full calibration
503 11:46:42.958087 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
504 11:46:42.958180 header.status = 0x0
505 11:46:42.961347 header.version = 0x6 (expected: 0x6)
506 11:46:42.964516 header.size = 0xd00 (expected: 0xd00)
507 11:46:42.967739 header.flags = 0x0
508 11:46:42.974153 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
509 11:46:42.990612 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
510 11:46:42.997201 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
511 11:46:43.000573 dram_init: ddr_geometry: 2
512 11:46:43.003849 [EMI] MDL number = 2
513 11:46:43.003963 [EMI] Get MDL freq = 0
514 11:46:43.007532 dram_init: ddr_type: 0
515 11:46:43.007640 is_discrete_lpddr4: 1
516 11:46:43.010715 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
517 11:46:43.010820
518 11:46:43.010915
519 11:46:43.013845 [Bian_co] ETT version 0.0.0.1
520 11:46:43.020476 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
521 11:46:43.020559
522 11:46:43.024043 dramc_set_vcore_voltage set vcore to 650000
523 11:46:43.027307 Read voltage for 800, 4
524 11:46:43.027382 Vio18 = 0
525 11:46:43.027479 Vcore = 650000
526 11:46:43.027570 Vdram = 0
527 11:46:43.030621 Vddq = 0
528 11:46:43.030706 Vmddr = 0
529 11:46:43.033804 dram_init: config_dvfs: 1
530 11:46:43.037404 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
531 11:46:43.043932 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
532 11:46:43.047151 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
533 11:46:43.050682 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
534 11:46:43.053798 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
535 11:46:43.057089 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
536 11:46:43.060683 MEM_TYPE=3, freq_sel=18
537 11:46:43.063706 sv_algorithm_assistance_LP4_1600
538 11:46:43.066962 ============ PULL DRAM RESETB DOWN ============
539 11:46:43.073600 ========== PULL DRAM RESETB DOWN end =========
540 11:46:43.077289 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
541 11:46:43.080537 ===================================
542 11:46:43.083740 LPDDR4 DRAM CONFIGURATION
543 11:46:43.086956 ===================================
544 11:46:43.087072 EX_ROW_EN[0] = 0x0
545 11:46:43.090280 EX_ROW_EN[1] = 0x0
546 11:46:43.090400 LP4Y_EN = 0x0
547 11:46:43.093623 WORK_FSP = 0x0
548 11:46:43.093729 WL = 0x2
549 11:46:43.096851 RL = 0x2
550 11:46:43.096964 BL = 0x2
551 11:46:43.100388 RPST = 0x0
552 11:46:43.100499 RD_PRE = 0x0
553 11:46:43.103545 WR_PRE = 0x1
554 11:46:43.103651 WR_PST = 0x0
555 11:46:43.107013 DBI_WR = 0x0
556 11:46:43.110455 DBI_RD = 0x0
557 11:46:43.110564 OTF = 0x1
558 11:46:43.113325 ===================================
559 11:46:43.117128 ===================================
560 11:46:43.117220 ANA top config
561 11:46:43.120526 ===================================
562 11:46:43.123614 DLL_ASYNC_EN = 0
563 11:46:43.126855 ALL_SLAVE_EN = 1
564 11:46:43.130122 NEW_RANK_MODE = 1
565 11:46:43.133788 DLL_IDLE_MODE = 1
566 11:46:43.133883 LP45_APHY_COMB_EN = 1
567 11:46:43.137091 TX_ODT_DIS = 1
568 11:46:43.140281 NEW_8X_MODE = 1
569 11:46:43.143608 ===================================
570 11:46:43.146908 ===================================
571 11:46:43.150100 data_rate = 1600
572 11:46:43.153615 CKR = 1
573 11:46:43.153730 DQ_P2S_RATIO = 8
574 11:46:43.156824 ===================================
575 11:46:43.160001 CA_P2S_RATIO = 8
576 11:46:43.163280 DQ_CA_OPEN = 0
577 11:46:43.166584 DQ_SEMI_OPEN = 0
578 11:46:43.169995 CA_SEMI_OPEN = 0
579 11:46:43.173275 CA_FULL_RATE = 0
580 11:46:43.173353 DQ_CKDIV4_EN = 1
581 11:46:43.176492 CA_CKDIV4_EN = 1
582 11:46:43.180206 CA_PREDIV_EN = 0
583 11:46:43.183399 PH8_DLY = 0
584 11:46:43.186793 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
585 11:46:43.190008 DQ_AAMCK_DIV = 4
586 11:46:43.190095 CA_AAMCK_DIV = 4
587 11:46:43.193301 CA_ADMCK_DIV = 4
588 11:46:43.196492 DQ_TRACK_CA_EN = 0
589 11:46:43.200104 CA_PICK = 800
590 11:46:43.203267 CA_MCKIO = 800
591 11:46:43.206529 MCKIO_SEMI = 0
592 11:46:43.209927 PLL_FREQ = 3068
593 11:46:43.210045 DQ_UI_PI_RATIO = 32
594 11:46:43.212967 CA_UI_PI_RATIO = 0
595 11:46:43.216447 ===================================
596 11:46:43.219835 ===================================
597 11:46:43.223074 memory_type:LPDDR4
598 11:46:43.226384 GP_NUM : 10
599 11:46:43.226493 SRAM_EN : 1
600 11:46:43.230218 MD32_EN : 0
601 11:46:43.234143 ===================================
602 11:46:43.234248 [ANA_INIT] >>>>>>>>>>>>>>
603 11:46:43.237633 <<<<<< [CONFIGURE PHASE]: ANA_TX
604 11:46:43.241406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
605 11:46:43.245045 ===================================
606 11:46:43.248738 data_rate = 1600,PCW = 0X7600
607 11:46:43.248851 ===================================
608 11:46:43.252859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
609 11:46:43.259750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
610 11:46:43.263524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
611 11:46:43.270522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
612 11:46:43.273848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
613 11:46:43.277252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
614 11:46:43.277346 [ANA_INIT] flow start
615 11:46:43.280491 [ANA_INIT] PLL >>>>>>>>
616 11:46:43.283729 [ANA_INIT] PLL <<<<<<<<
617 11:46:43.283828 [ANA_INIT] MIDPI >>>>>>>>
618 11:46:43.286966 [ANA_INIT] MIDPI <<<<<<<<
619 11:46:43.290453 [ANA_INIT] DLL >>>>>>>>
620 11:46:43.290535 [ANA_INIT] flow end
621 11:46:43.296854 ============ LP4 DIFF to SE enter ============
622 11:46:43.300599 ============ LP4 DIFF to SE exit ============
623 11:46:43.303817 [ANA_INIT] <<<<<<<<<<<<<
624 11:46:43.307083 [Flow] Enable top DCM control >>>>>
625 11:46:43.310749 [Flow] Enable top DCM control <<<<<
626 11:46:43.310858 Enable DLL master slave shuffle
627 11:46:43.317363 ==============================================================
628 11:46:43.321242 Gating Mode config
629 11:46:43.324797 ==============================================================
630 11:46:43.328226 Config description:
631 11:46:43.335369 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
632 11:46:43.342743 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
633 11:46:43.346357 SELPH_MODE 0: By rank 1: By Phase
634 11:46:43.354001 ==============================================================
635 11:46:43.357035 GAT_TRACK_EN = 1
636 11:46:43.360663 RX_GATING_MODE = 2
637 11:46:43.360774 RX_GATING_TRACK_MODE = 2
638 11:46:43.363917 SELPH_MODE = 1
639 11:46:43.367969 PICG_EARLY_EN = 1
640 11:46:43.371537 VALID_LAT_VALUE = 1
641 11:46:43.375157 ==============================================================
642 11:46:43.378855 Enter into Gating configuration >>>>
643 11:46:43.382637 Exit from Gating configuration <<<<
644 11:46:43.386289 Enter into DVFS_PRE_config >>>>>
645 11:46:43.397604 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
646 11:46:43.401336 Exit from DVFS_PRE_config <<<<<
647 11:46:43.404846 Enter into PICG configuration >>>>
648 11:46:43.408451 Exit from PICG configuration <<<<
649 11:46:43.408566 [RX_INPUT] configuration >>>>>
650 11:46:43.412183 [RX_INPUT] configuration <<<<<
651 11:46:43.419301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
652 11:46:43.423008 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
653 11:46:43.430460 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
654 11:46:43.434227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
655 11:46:43.441315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
656 11:46:43.448504 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
657 11:46:43.452065 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
658 11:46:43.455796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
659 11:46:43.459643 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
660 11:46:43.463339 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
661 11:46:43.466826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
662 11:46:43.474073 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
663 11:46:43.478264 ===================================
664 11:46:43.478375 LPDDR4 DRAM CONFIGURATION
665 11:46:43.481576 ===================================
666 11:46:43.485296 EX_ROW_EN[0] = 0x0
667 11:46:43.485374 EX_ROW_EN[1] = 0x0
668 11:46:43.489066 LP4Y_EN = 0x0
669 11:46:43.489145 WORK_FSP = 0x0
670 11:46:43.492465 WL = 0x2
671 11:46:43.492540 RL = 0x2
672 11:46:43.492603 BL = 0x2
673 11:46:43.496593 RPST = 0x0
674 11:46:43.496677 RD_PRE = 0x0
675 11:46:43.500327 WR_PRE = 0x1
676 11:46:43.500405 WR_PST = 0x0
677 11:46:43.503705 DBI_WR = 0x0
678 11:46:43.503779 DBI_RD = 0x0
679 11:46:43.507320 OTF = 0x1
680 11:46:43.511148 ===================================
681 11:46:43.514774 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
682 11:46:43.518521 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
683 11:46:43.521876 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
684 11:46:43.525673 ===================================
685 11:46:43.529464 LPDDR4 DRAM CONFIGURATION
686 11:46:43.529550 ===================================
687 11:46:43.533315 EX_ROW_EN[0] = 0x10
688 11:46:43.536852 EX_ROW_EN[1] = 0x0
689 11:46:43.536962 LP4Y_EN = 0x0
690 11:46:43.540768 WORK_FSP = 0x0
691 11:46:43.540880 WL = 0x2
692 11:46:43.541013 RL = 0x2
693 11:46:43.544472 BL = 0x2
694 11:46:43.544578 RPST = 0x0
695 11:46:43.548277 RD_PRE = 0x0
696 11:46:43.548382 WR_PRE = 0x1
697 11:46:43.551803 WR_PST = 0x0
698 11:46:43.551912 DBI_WR = 0x0
699 11:46:43.555450 DBI_RD = 0x0
700 11:46:43.555563 OTF = 0x1
701 11:46:43.559158 ===================================
702 11:46:43.566171 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
703 11:46:43.570332 nWR fixed to 40
704 11:46:43.570420 [ModeRegInit_LP4] CH0 RK0
705 11:46:43.573963 [ModeRegInit_LP4] CH0 RK1
706 11:46:43.577672 [ModeRegInit_LP4] CH1 RK0
707 11:46:43.577759 [ModeRegInit_LP4] CH1 RK1
708 11:46:43.580871 match AC timing 13
709 11:46:43.584767 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
710 11:46:43.588173 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
711 11:46:43.591838 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
712 11:46:43.599383 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
713 11:46:43.602692 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
714 11:46:43.602810 [EMI DOE] emi_dcm 0
715 11:46:43.609757 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
716 11:46:43.609842 ==
717 11:46:43.613486 Dram Type= 6, Freq= 0, CH_0, rank 0
718 11:46:43.617012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
719 11:46:43.617101 ==
720 11:46:43.620747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
721 11:46:43.627449 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
722 11:46:43.636749 [CA 0] Center 37 (7~68) winsize 62
723 11:46:43.640203 [CA 1] Center 38 (7~69) winsize 63
724 11:46:43.643264 [CA 2] Center 35 (5~66) winsize 62
725 11:46:43.646628 [CA 3] Center 35 (5~66) winsize 62
726 11:46:43.650112 [CA 4] Center 35 (4~66) winsize 63
727 11:46:43.653629 [CA 5] Center 34 (4~64) winsize 61
728 11:46:43.653724
729 11:46:43.656687 [CmdBusTrainingLP45] Vref(ca) range 1: 32
730 11:46:43.656804
731 11:46:43.659931 [CATrainingPosCal] consider 1 rank data
732 11:46:43.663174 u2DelayCellTimex100 = 270/100 ps
733 11:46:43.666533 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
734 11:46:43.670154 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
735 11:46:43.676874 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
736 11:46:43.680109 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
737 11:46:43.683366 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
738 11:46:43.686708 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
739 11:46:43.686815
740 11:46:43.690327 CA PerBit enable=1, Macro0, CA PI delay=34
741 11:46:43.690436
742 11:46:43.693716 [CBTSetCACLKResult] CA Dly = 34
743 11:46:43.693821 CS Dly: 5 (0~36)
744 11:46:43.693920 ==
745 11:46:43.696946 Dram Type= 6, Freq= 0, CH_0, rank 1
746 11:46:43.703613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
747 11:46:43.703725 ==
748 11:46:43.706853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
749 11:46:43.713338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
750 11:46:43.722887 [CA 0] Center 38 (7~69) winsize 63
751 11:46:43.726392 [CA 1] Center 38 (8~69) winsize 62
752 11:46:43.729380 [CA 2] Center 36 (6~67) winsize 62
753 11:46:43.732716 [CA 3] Center 35 (5~66) winsize 62
754 11:46:43.736295 [CA 4] Center 35 (4~66) winsize 63
755 11:46:43.739660 [CA 5] Center 34 (4~65) winsize 62
756 11:46:43.739764
757 11:46:43.742745 [CmdBusTrainingLP45] Vref(ca) range 1: 32
758 11:46:43.742849
759 11:46:43.746288 [CATrainingPosCal] consider 2 rank data
760 11:46:43.749629 u2DelayCellTimex100 = 270/100 ps
761 11:46:43.752864 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
762 11:46:43.759596 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
763 11:46:43.762641 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
764 11:46:43.766356 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
765 11:46:43.769187 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
766 11:46:43.772825 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
767 11:46:43.772935
768 11:46:43.776253 CA PerBit enable=1, Macro0, CA PI delay=34
769 11:46:43.776335
770 11:46:43.779522 [CBTSetCACLKResult] CA Dly = 34
771 11:46:43.779629 CS Dly: 6 (0~38)
772 11:46:43.782626
773 11:46:43.785896 ----->DramcWriteLeveling(PI) begin...
774 11:46:43.785976 ==
775 11:46:43.789160 Dram Type= 6, Freq= 0, CH_0, rank 0
776 11:46:43.792844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
777 11:46:43.792957 ==
778 11:46:43.796054 Write leveling (Byte 0): 31 => 31
779 11:46:43.799337 Write leveling (Byte 1): 31 => 31
780 11:46:43.802783 DramcWriteLeveling(PI) end<-----
781 11:46:43.802895
782 11:46:43.802992 ==
783 11:46:43.805949 Dram Type= 6, Freq= 0, CH_0, rank 0
784 11:46:43.809161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
785 11:46:43.809248 ==
786 11:46:43.812731 [Gating] SW mode calibration
787 11:46:43.819987 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
788 11:46:43.824018 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
789 11:46:43.827312 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
790 11:46:43.834251 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
791 11:46:43.837366 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
792 11:46:43.841103 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:46:43.848004 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:46:43.851337 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:46:43.854598 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:46:43.857944 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:46:43.864675 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:46:43.868143 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:46:43.871397 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:46:43.878187 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:46:43.881437 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:46:43.884712 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:46:43.891314 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:46:43.894499 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:46:43.897823 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
806 11:46:43.904748 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
807 11:46:43.907930 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
808 11:46:43.911203 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
809 11:46:43.917696 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:46:43.921380 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:46:43.924521 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:46:43.931214 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:46:43.934362 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:46:43.937785 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 11:46:43.944689 0 9 8 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
816 11:46:43.947928 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
817 11:46:43.951216 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:46:43.957811 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:46:43.961332 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 11:46:43.964289 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 11:46:43.971220 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 11:46:43.974887 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
823 11:46:43.977736 0 10 8 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
824 11:46:43.981212 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
825 11:46:43.988018 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:46:43.991015 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:46:43.994317 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:46:44.000938 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:46:44.004545 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:46:44.007813 0 11 4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
831 11:46:44.014299 0 11 8 | B1->B0 | 2f2f 4646 | 1 0 | (1 1) (0 0)
832 11:46:44.017376 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
833 11:46:44.021016 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:46:44.027801 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:46:44.030947 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 11:46:44.034185 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 11:46:44.040687 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 11:46:44.044138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
839 11:46:44.047396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
840 11:46:44.054332 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:46:44.057541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:46:44.060594 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:46:44.067526 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:46:44.070706 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:46:44.073974 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:46:44.080672 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:46:44.084179 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:46:44.087380 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:46:44.094105 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:46:44.097302 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:46:44.100915 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:46:44.104186 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 11:46:44.110879 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 11:46:44.113795 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
855 11:46:44.117654 Total UI for P1: 0, mck2ui 16
856 11:46:44.120878 best dqsien dly found for B0: ( 0, 14, 2)
857 11:46:44.124020 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
858 11:46:44.130389 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
859 11:46:44.133721 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 11:46:44.137306 Total UI for P1: 0, mck2ui 16
861 11:46:44.140500 best dqsien dly found for B1: ( 0, 14, 10)
862 11:46:44.143740 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
863 11:46:44.147033 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
864 11:46:44.147145
865 11:46:44.150283 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
866 11:46:44.157054 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
867 11:46:44.157168 [Gating] SW calibration Done
868 11:46:44.157283 ==
869 11:46:44.160310 Dram Type= 6, Freq= 0, CH_0, rank 0
870 11:46:44.167139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
871 11:46:44.167253 ==
872 11:46:44.167353 RX Vref Scan: 0
873 11:46:44.167451
874 11:46:44.170223 RX Vref 0 -> 0, step: 1
875 11:46:44.170329
876 11:46:44.173774 RX Delay -130 -> 252, step: 16
877 11:46:44.177307 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
878 11:46:44.180416 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
879 11:46:44.183613 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
880 11:46:44.187337 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
881 11:46:44.193927 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
882 11:46:44.197140 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
883 11:46:44.200758 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
884 11:46:44.203893 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
885 11:46:44.207007 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
886 11:46:44.213808 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
887 11:46:44.216948 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
888 11:46:44.220634 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
889 11:46:44.223789 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
890 11:46:44.230622 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
891 11:46:44.233934 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
892 11:46:44.237186 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
893 11:46:44.237272 ==
894 11:46:44.240474 Dram Type= 6, Freq= 0, CH_0, rank 0
895 11:46:44.243670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
896 11:46:44.243756 ==
897 11:46:44.246950 DQS Delay:
898 11:46:44.247035 DQS0 = 0, DQS1 = 0
899 11:46:44.250558 DQM Delay:
900 11:46:44.250648 DQM0 = 90, DQM1 = 76
901 11:46:44.250729 DQ Delay:
902 11:46:44.253620 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
903 11:46:44.256766 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
904 11:46:44.260564 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
905 11:46:44.263713 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
906 11:46:44.263798
907 11:46:44.263866
908 11:46:44.266895 ==
909 11:46:44.266980 Dram Type= 6, Freq= 0, CH_0, rank 0
910 11:46:44.273626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
911 11:46:44.273711 ==
912 11:46:44.273777
913 11:46:44.273838
914 11:46:44.277111 TX Vref Scan disable
915 11:46:44.277195 == TX Byte 0 ==
916 11:46:44.280418 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
917 11:46:44.286752 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
918 11:46:44.286917 == TX Byte 1 ==
919 11:46:44.290033 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
920 11:46:44.296966 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
921 11:46:44.297094 ==
922 11:46:44.300143 Dram Type= 6, Freq= 0, CH_0, rank 0
923 11:46:44.303329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 11:46:44.303415 ==
925 11:46:44.316745 TX Vref=22, minBit 6, minWin=27, winSum=440
926 11:46:44.319497 TX Vref=24, minBit 6, minWin=27, winSum=445
927 11:46:44.323153 TX Vref=26, minBit 6, minWin=27, winSum=446
928 11:46:44.326452 TX Vref=28, minBit 8, minWin=27, winSum=449
929 11:46:44.329667 TX Vref=30, minBit 5, minWin=28, winSum=458
930 11:46:44.336667 TX Vref=32, minBit 10, minWin=27, winSum=454
931 11:46:44.339968 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30
932 11:46:44.340047
933 11:46:44.343240 Final TX Range 1 Vref 30
934 11:46:44.343350
935 11:46:44.343451 ==
936 11:46:44.346412 Dram Type= 6, Freq= 0, CH_0, rank 0
937 11:46:44.349574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
938 11:46:44.349650 ==
939 11:46:44.353164
940 11:46:44.353245
941 11:46:44.353321 TX Vref Scan disable
942 11:46:44.356261 == TX Byte 0 ==
943 11:46:44.359913 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
944 11:46:44.366316 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
945 11:46:44.366395 == TX Byte 1 ==
946 11:46:44.369616 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
947 11:46:44.376328 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
948 11:46:44.376419
949 11:46:44.376498 [DATLAT]
950 11:46:44.376560 Freq=800, CH0 RK0
951 11:46:44.376628
952 11:46:44.379650 DATLAT Default: 0xa
953 11:46:44.379725 0, 0xFFFF, sum = 0
954 11:46:44.383127 1, 0xFFFF, sum = 0
955 11:46:44.383232 2, 0xFFFF, sum = 0
956 11:46:44.386543 3, 0xFFFF, sum = 0
957 11:46:44.389866 4, 0xFFFF, sum = 0
958 11:46:44.389978 5, 0xFFFF, sum = 0
959 11:46:44.393001 6, 0xFFFF, sum = 0
960 11:46:44.393084 7, 0xFFFF, sum = 0
961 11:46:44.396389 8, 0xFFFF, sum = 0
962 11:46:44.396474 9, 0x0, sum = 1
963 11:46:44.399670 10, 0x0, sum = 2
964 11:46:44.399757 11, 0x0, sum = 3
965 11:46:44.399825 12, 0x0, sum = 4
966 11:46:44.402965 best_step = 10
967 11:46:44.403046
968 11:46:44.403125 ==
969 11:46:44.406285 Dram Type= 6, Freq= 0, CH_0, rank 0
970 11:46:44.409640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 11:46:44.409781 ==
972 11:46:44.412867 RX Vref Scan: 1
973 11:46:44.412951
974 11:46:44.416111 Set Vref Range= 32 -> 127
975 11:46:44.416213
976 11:46:44.416317 RX Vref 32 -> 127, step: 1
977 11:46:44.416415
978 11:46:44.419403 RX Delay -95 -> 252, step: 8
979 11:46:44.419503
980 11:46:44.422657 Set Vref, RX VrefLevel [Byte0]: 32
981 11:46:44.426482 [Byte1]: 32
982 11:46:44.426558
983 11:46:44.429782 Set Vref, RX VrefLevel [Byte0]: 33
984 11:46:44.432910 [Byte1]: 33
985 11:46:44.436576
986 11:46:44.440252 Set Vref, RX VrefLevel [Byte0]: 34
987 11:46:44.443517 [Byte1]: 34
988 11:46:44.443594
989 11:46:44.446811 Set Vref, RX VrefLevel [Byte0]: 35
990 11:46:44.450008 [Byte1]: 35
991 11:46:44.450084
992 11:46:44.453209 Set Vref, RX VrefLevel [Byte0]: 36
993 11:46:44.456497 [Byte1]: 36
994 11:46:44.456616
995 11:46:44.460272 Set Vref, RX VrefLevel [Byte0]: 37
996 11:46:44.463491 [Byte1]: 37
997 11:46:44.467015
998 11:46:44.467090 Set Vref, RX VrefLevel [Byte0]: 38
999 11:46:44.470230 [Byte1]: 38
1000 11:46:44.474851
1001 11:46:44.474993 Set Vref, RX VrefLevel [Byte0]: 39
1002 11:46:44.477926 [Byte1]: 39
1003 11:46:44.482978
1004 11:46:44.483110 Set Vref, RX VrefLevel [Byte0]: 40
1005 11:46:44.486325 [Byte1]: 40
1006 11:46:44.489998
1007 11:46:44.490082 Set Vref, RX VrefLevel [Byte0]: 41
1008 11:46:44.493358 [Byte1]: 41
1009 11:46:44.497747
1010 11:46:44.497834 Set Vref, RX VrefLevel [Byte0]: 42
1011 11:46:44.500758 [Byte1]: 42
1012 11:46:44.505646
1013 11:46:44.505761 Set Vref, RX VrefLevel [Byte0]: 43
1014 11:46:44.508756 [Byte1]: 43
1015 11:46:44.513491
1016 11:46:44.513577 Set Vref, RX VrefLevel [Byte0]: 44
1017 11:46:44.516713 [Byte1]: 44
1018 11:46:44.520198
1019 11:46:44.520311 Set Vref, RX VrefLevel [Byte0]: 45
1020 11:46:44.523519 [Byte1]: 45
1021 11:46:44.527736
1022 11:46:44.527847 Set Vref, RX VrefLevel [Byte0]: 46
1023 11:46:44.530988 [Byte1]: 46
1024 11:46:44.535583
1025 11:46:44.538754 Set Vref, RX VrefLevel [Byte0]: 47
1026 11:46:44.542003 [Byte1]: 47
1027 11:46:44.542097
1028 11:46:44.545358 Set Vref, RX VrefLevel [Byte0]: 48
1029 11:46:44.548631 [Byte1]: 48
1030 11:46:44.548710
1031 11:46:44.551907 Set Vref, RX VrefLevel [Byte0]: 49
1032 11:46:44.555496 [Byte1]: 49
1033 11:46:44.555582
1034 11:46:44.558749 Set Vref, RX VrefLevel [Byte0]: 50
1035 11:46:44.562212 [Byte1]: 50
1036 11:46:44.565680
1037 11:46:44.565767 Set Vref, RX VrefLevel [Byte0]: 51
1038 11:46:44.569357 [Byte1]: 51
1039 11:46:44.573494
1040 11:46:44.573597 Set Vref, RX VrefLevel [Byte0]: 52
1041 11:46:44.576667 [Byte1]: 52
1042 11:46:44.581238
1043 11:46:44.581316 Set Vref, RX VrefLevel [Byte0]: 53
1044 11:46:44.584412 [Byte1]: 53
1045 11:46:44.588557
1046 11:46:44.588641 Set Vref, RX VrefLevel [Byte0]: 54
1047 11:46:44.591912 [Byte1]: 54
1048 11:46:44.596272
1049 11:46:44.596385 Set Vref, RX VrefLevel [Byte0]: 55
1050 11:46:44.599891 [Byte1]: 55
1051 11:46:44.603915
1052 11:46:44.604002 Set Vref, RX VrefLevel [Byte0]: 56
1053 11:46:44.607308 [Byte1]: 56
1054 11:46:44.611321
1055 11:46:44.611404 Set Vref, RX VrefLevel [Byte0]: 57
1056 11:46:44.614665 [Byte1]: 57
1057 11:46:44.618846
1058 11:46:44.618924 Set Vref, RX VrefLevel [Byte0]: 58
1059 11:46:44.622215 [Byte1]: 58
1060 11:46:44.626678
1061 11:46:44.626752 Set Vref, RX VrefLevel [Byte0]: 59
1062 11:46:44.630183 [Byte1]: 59
1063 11:46:44.634082
1064 11:46:44.634150 Set Vref, RX VrefLevel [Byte0]: 60
1065 11:46:44.637782 [Byte1]: 60
1066 11:46:44.641904
1067 11:46:44.641976 Set Vref, RX VrefLevel [Byte0]: 61
1068 11:46:44.645119 [Byte1]: 61
1069 11:46:44.649588
1070 11:46:44.649657 Set Vref, RX VrefLevel [Byte0]: 62
1071 11:46:44.652833 [Byte1]: 62
1072 11:46:44.656948
1073 11:46:44.657043 Set Vref, RX VrefLevel [Byte0]: 63
1074 11:46:44.660247 [Byte1]: 63
1075 11:46:44.664806
1076 11:46:44.664882 Set Vref, RX VrefLevel [Byte0]: 64
1077 11:46:44.667870 [Byte1]: 64
1078 11:46:44.672342
1079 11:46:44.672415 Set Vref, RX VrefLevel [Byte0]: 65
1080 11:46:44.675639 [Byte1]: 65
1081 11:46:44.679829
1082 11:46:44.679899 Set Vref, RX VrefLevel [Byte0]: 66
1083 11:46:44.683261 [Byte1]: 66
1084 11:46:44.687414
1085 11:46:44.687485 Set Vref, RX VrefLevel [Byte0]: 67
1086 11:46:44.690637 [Byte1]: 67
1087 11:46:44.695163
1088 11:46:44.695247 Set Vref, RX VrefLevel [Byte0]: 68
1089 11:46:44.698399 [Byte1]: 68
1090 11:46:44.702763
1091 11:46:44.702833 Set Vref, RX VrefLevel [Byte0]: 69
1092 11:46:44.705780 [Byte1]: 69
1093 11:46:44.710104
1094 11:46:44.710182 Set Vref, RX VrefLevel [Byte0]: 70
1095 11:46:44.713749 [Byte1]: 70
1096 11:46:44.717898
1097 11:46:44.717977 Set Vref, RX VrefLevel [Byte0]: 71
1098 11:46:44.720934 [Byte1]: 71
1099 11:46:44.725535
1100 11:46:44.725608 Set Vref, RX VrefLevel [Byte0]: 72
1101 11:46:44.728621 [Byte1]: 72
1102 11:46:44.732983
1103 11:46:44.733066 Set Vref, RX VrefLevel [Byte0]: 73
1104 11:46:44.736366 [Byte1]: 73
1105 11:46:44.740530
1106 11:46:44.740605 Set Vref, RX VrefLevel [Byte0]: 74
1107 11:46:44.743834 [Byte1]: 74
1108 11:46:44.748043
1109 11:46:44.748121 Set Vref, RX VrefLevel [Byte0]: 75
1110 11:46:44.751331 [Byte1]: 75
1111 11:46:44.756028
1112 11:46:44.756110 Set Vref, RX VrefLevel [Byte0]: 76
1113 11:46:44.759210 [Byte1]: 76
1114 11:46:44.763375
1115 11:46:44.763484 Final RX Vref Byte 0 = 61 to rank0
1116 11:46:44.766755 Final RX Vref Byte 1 = 59 to rank0
1117 11:46:44.769939 Final RX Vref Byte 0 = 61 to rank1
1118 11:46:44.773462 Final RX Vref Byte 1 = 59 to rank1==
1119 11:46:44.776637 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 11:46:44.783210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 11:46:44.783313 ==
1122 11:46:44.783408 DQS Delay:
1123 11:46:44.783505 DQS0 = 0, DQS1 = 0
1124 11:46:44.786504 DQM Delay:
1125 11:46:44.786601 DQM0 = 93, DQM1 = 82
1126 11:46:44.790067 DQ Delay:
1127 11:46:44.793358 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1128 11:46:44.796717 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1129 11:46:44.799861 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1130 11:46:44.803468 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1131 11:46:44.803571
1132 11:46:44.803663
1133 11:46:44.810121 [DQSOSCAuto] RK0, (LSB)MR18= 0x3833, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1134 11:46:44.813265 CH0 RK0: MR19=606, MR18=3833
1135 11:46:44.820093 CH0_RK0: MR19=0x606, MR18=0x3833, DQSOSC=395, MR23=63, INC=94, DEC=63
1136 11:46:44.820171
1137 11:46:44.823286 ----->DramcWriteLeveling(PI) begin...
1138 11:46:44.823364 ==
1139 11:46:44.826452 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 11:46:44.829903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 11:46:44.829981 ==
1142 11:46:44.833338 Write leveling (Byte 0): 34 => 34
1143 11:46:44.836551 Write leveling (Byte 1): 30 => 30
1144 11:46:44.839687 DramcWriteLeveling(PI) end<-----
1145 11:46:44.839793
1146 11:46:44.839891 ==
1147 11:46:44.843141 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 11:46:44.846465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 11:46:44.846545 ==
1150 11:46:44.849738 [Gating] SW mode calibration
1151 11:46:44.856325 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 11:46:44.862822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 11:46:44.866125 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 11:46:44.873079 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1155 11:46:44.876219 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:46:44.879388 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:46:44.926723 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:46:44.926821 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:46:44.927166 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:46:44.927439 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:46:44.927545 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:46:44.927639 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:46:44.927730 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:46:44.927830 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:46:44.928110 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:46:44.928203 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:46:44.928292 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:46:44.940450 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:46:44.940871 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1170 11:46:44.944082 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1171 11:46:44.947076 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1172 11:46:44.950396 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:46:44.953885 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:46:44.960428 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:46:44.963720 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:46:44.967184 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:46:44.973619 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:46:44.977219 0 9 4 | B1->B0 | 2323 2524 | 0 1 | (1 1) (1 1)
1179 11:46:44.980382 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1180 11:46:44.987321 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:46:44.990602 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:46:44.993871 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:46:44.997195 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:46:45.003643 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:46:45.007214 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:46:45.010535 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
1187 11:46:45.016868 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
1188 11:46:45.020237 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:46:45.023317 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:46:45.030195 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:46:45.033518 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:46:45.036745 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:46:45.043512 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:46:45.046613 0 11 4 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
1195 11:46:45.050150 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1196 11:46:45.056898 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:46:45.059911 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:46:45.063652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:46:45.070995 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:46:45.074332 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:46:45.077951 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:46:45.081291 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 11:46:45.087926 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:46:45.091650 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:46:45.095465 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:46:45.098483 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:46:45.105360 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:46:45.108692 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:46:45.111756 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:46:45.118758 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:46:45.122011 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:46:45.125309 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:46:45.132131 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:46:45.135251 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:46:45.138565 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:46:45.145247 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:46:45.148560 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:46:45.151830 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 11:46:45.158765 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 11:46:45.158874 Total UI for P1: 0, mck2ui 16
1221 11:46:45.161804 best dqsien dly found for B0: ( 0, 14, 4)
1222 11:46:45.168547 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 11:46:45.172187 Total UI for P1: 0, mck2ui 16
1224 11:46:45.175383 best dqsien dly found for B1: ( 0, 14, 6)
1225 11:46:45.178560 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1226 11:46:45.182239 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1227 11:46:45.182336
1228 11:46:45.185510 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1229 11:46:45.188640 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1230 11:46:45.192090 [Gating] SW calibration Done
1231 11:46:45.192193 ==
1232 11:46:45.195364 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 11:46:45.198594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 11:46:45.198674 ==
1235 11:46:45.201704 RX Vref Scan: 0
1236 11:46:45.201779
1237 11:46:45.201840 RX Vref 0 -> 0, step: 1
1238 11:46:45.201899
1239 11:46:45.204989 RX Delay -130 -> 252, step: 16
1240 11:46:45.212060 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1241 11:46:45.215330 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1242 11:46:45.218279 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1243 11:46:45.221620 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1244 11:46:45.225008 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1245 11:46:45.231539 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1246 11:46:45.234777 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1247 11:46:45.238163 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1248 11:46:45.241407 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1249 11:46:45.244861 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1250 11:46:45.251558 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1251 11:46:45.254628 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1252 11:46:45.257787 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1253 11:46:45.261215 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1254 11:46:45.267938 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1255 11:46:45.271355 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1256 11:46:45.271460 ==
1257 11:46:45.274572 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 11:46:45.277830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 11:46:45.277942 ==
1260 11:46:45.278042 DQS Delay:
1261 11:46:45.281168 DQS0 = 0, DQS1 = 0
1262 11:46:45.281262 DQM Delay:
1263 11:46:45.284729 DQM0 = 91, DQM1 = 82
1264 11:46:45.284828 DQ Delay:
1265 11:46:45.287973 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1266 11:46:45.291244 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1267 11:46:45.294319 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1268 11:46:45.297664 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =93
1269 11:46:45.297776
1270 11:46:45.297870
1271 11:46:45.298004 ==
1272 11:46:45.300860 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 11:46:45.304549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 11:46:45.307730 ==
1275 11:46:45.307849
1276 11:46:45.307971
1277 11:46:45.308073 TX Vref Scan disable
1278 11:46:45.310844 == TX Byte 0 ==
1279 11:46:45.314615 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1280 11:46:45.317893 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1281 11:46:45.321009 == TX Byte 1 ==
1282 11:46:45.324375 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1283 11:46:45.327731 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1284 11:46:45.330910 ==
1285 11:46:45.334163 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 11:46:45.337736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 11:46:45.337845 ==
1288 11:46:45.350399 TX Vref=22, minBit 1, minWin=27, winSum=441
1289 11:46:45.354096 TX Vref=24, minBit 1, minWin=27, winSum=448
1290 11:46:45.357109 TX Vref=26, minBit 8, minWin=27, winSum=450
1291 11:46:45.360295 TX Vref=28, minBit 8, minWin=27, winSum=454
1292 11:46:45.363601 TX Vref=30, minBit 14, minWin=27, winSum=456
1293 11:46:45.370562 TX Vref=32, minBit 8, minWin=27, winSum=456
1294 11:46:45.373829 [TxChooseVref] Worse bit 14, Min win 27, Win sum 456, Final Vref 30
1295 11:46:45.373958
1296 11:46:45.377116 Final TX Range 1 Vref 30
1297 11:46:45.377199
1298 11:46:45.377277 ==
1299 11:46:45.380211 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:46:45.383516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:46:45.387156 ==
1302 11:46:45.387237
1303 11:46:45.387300
1304 11:46:45.387359 TX Vref Scan disable
1305 11:46:45.390717 == TX Byte 0 ==
1306 11:46:45.393982 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1307 11:46:45.400488 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1308 11:46:45.400595 == TX Byte 1 ==
1309 11:46:45.403650 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1310 11:46:45.410553 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1311 11:46:45.410660
1312 11:46:45.410752 [DATLAT]
1313 11:46:45.410840 Freq=800, CH0 RK1
1314 11:46:45.410925
1315 11:46:45.413887 DATLAT Default: 0xa
1316 11:46:45.413968 0, 0xFFFF, sum = 0
1317 11:46:45.416989 1, 0xFFFF, sum = 0
1318 11:46:45.417103 2, 0xFFFF, sum = 0
1319 11:46:45.420221 3, 0xFFFF, sum = 0
1320 11:46:45.423898 4, 0xFFFF, sum = 0
1321 11:46:45.423980 5, 0xFFFF, sum = 0
1322 11:46:45.427220 6, 0xFFFF, sum = 0
1323 11:46:45.427302 7, 0xFFFF, sum = 0
1324 11:46:45.430384 8, 0xFFFF, sum = 0
1325 11:46:45.430467 9, 0x0, sum = 1
1326 11:46:45.433867 10, 0x0, sum = 2
1327 11:46:45.433949 11, 0x0, sum = 3
1328 11:46:45.434014 12, 0x0, sum = 4
1329 11:46:45.437467 best_step = 10
1330 11:46:45.437547
1331 11:46:45.437610 ==
1332 11:46:45.440392 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 11:46:45.444053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 11:46:45.444162 ==
1335 11:46:45.447519 RX Vref Scan: 0
1336 11:46:45.447601
1337 11:46:45.447665 RX Vref 0 -> 0, step: 1
1338 11:46:45.447724
1339 11:46:45.450302 RX Delay -79 -> 252, step: 8
1340 11:46:45.457014 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1341 11:46:45.460591 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1342 11:46:45.463675 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1343 11:46:45.467242 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1344 11:46:45.470428 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1345 11:46:45.477229 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1346 11:46:45.480407 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1347 11:46:45.483971 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1348 11:46:45.486941 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1349 11:46:45.490199 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1350 11:46:45.497239 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1351 11:46:45.500372 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1352 11:46:45.503722 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1353 11:46:45.506971 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1354 11:46:45.513840 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1355 11:46:45.517171 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1356 11:46:45.517253 ==
1357 11:46:45.520360 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 11:46:45.523577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 11:46:45.523677 ==
1360 11:46:45.523767 DQS Delay:
1361 11:46:45.526872 DQS0 = 0, DQS1 = 0
1362 11:46:45.526965 DQM Delay:
1363 11:46:45.530226 DQM0 = 90, DQM1 = 81
1364 11:46:45.530300 DQ Delay:
1365 11:46:45.533312 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1366 11:46:45.536834 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1367 11:46:45.539956 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1368 11:46:45.543678 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1369 11:46:45.543771
1370 11:46:45.543858
1371 11:46:45.553376 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
1372 11:46:45.553478 CH0 RK1: MR19=606, MR18=3D18
1373 11:46:45.560256 CH0_RK1: MR19=0x606, MR18=0x3D18, DQSOSC=394, MR23=63, INC=95, DEC=63
1374 11:46:45.563445 [RxdqsGatingPostProcess] freq 800
1375 11:46:45.570122 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 11:46:45.573336 Pre-setting of DQS Precalculation
1377 11:46:45.576962 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 11:46:45.577072 ==
1379 11:46:45.580327 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 11:46:45.586798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 11:46:45.586899 ==
1382 11:46:45.590248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 11:46:45.596488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 11:46:45.605920 [CA 0] Center 36 (6~67) winsize 62
1385 11:46:45.609363 [CA 1] Center 36 (6~67) winsize 62
1386 11:46:45.612537 [CA 2] Center 35 (5~65) winsize 61
1387 11:46:45.615635 [CA 3] Center 34 (3~65) winsize 63
1388 11:46:45.619547 [CA 4] Center 34 (4~65) winsize 62
1389 11:46:45.622255 [CA 5] Center 33 (3~64) winsize 62
1390 11:46:45.622350
1391 11:46:45.625387 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1392 11:46:45.625504
1393 11:46:45.629222 [CATrainingPosCal] consider 1 rank data
1394 11:46:45.632308 u2DelayCellTimex100 = 270/100 ps
1395 11:46:45.635574 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1396 11:46:45.642181 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1397 11:46:45.645899 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1398 11:46:45.649133 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1399 11:46:45.652210 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1400 11:46:45.655629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 11:46:45.655731
1402 11:46:45.658752 CA PerBit enable=1, Macro0, CA PI delay=33
1403 11:46:45.658850
1404 11:46:45.662018 [CBTSetCACLKResult] CA Dly = 33
1405 11:46:45.662114 CS Dly: 5 (0~36)
1406 11:46:45.665299 ==
1407 11:46:45.668805 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 11:46:45.672077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 11:46:45.672155 ==
1410 11:46:45.675231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 11:46:45.681741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 11:46:45.691990 [CA 0] Center 37 (6~68) winsize 63
1413 11:46:45.695115 [CA 1] Center 37 (6~68) winsize 63
1414 11:46:45.698627 [CA 2] Center 35 (5~66) winsize 62
1415 11:46:45.701953 [CA 3] Center 34 (4~65) winsize 62
1416 11:46:45.705108 [CA 4] Center 34 (4~65) winsize 62
1417 11:46:45.708844 [CA 5] Center 34 (4~64) winsize 61
1418 11:46:45.708943
1419 11:46:45.712001 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1420 11:46:45.712098
1421 11:46:45.715077 [CATrainingPosCal] consider 2 rank data
1422 11:46:45.718730 u2DelayCellTimex100 = 270/100 ps
1423 11:46:45.721714 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 11:46:45.724952 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 11:46:45.732457 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1426 11:46:45.735813 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 11:46:45.739674 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 11:46:45.743431 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 11:46:45.743532
1430 11:46:45.747016 CA PerBit enable=1, Macro0, CA PI delay=34
1431 11:46:45.747120
1432 11:46:45.747211 [CBTSetCACLKResult] CA Dly = 34
1433 11:46:45.750724 CS Dly: 6 (0~38)
1434 11:46:45.750795
1435 11:46:45.754402 ----->DramcWriteLeveling(PI) begin...
1436 11:46:45.754504 ==
1437 11:46:45.758132 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 11:46:45.761755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 11:46:45.761923 ==
1440 11:46:45.765521 Write leveling (Byte 0): 29 => 29
1441 11:46:45.768651 Write leveling (Byte 1): 30 => 30
1442 11:46:45.768727 DramcWriteLeveling(PI) end<-----
1443 11:46:45.772177
1444 11:46:45.772284 ==
1445 11:46:45.775410 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 11:46:45.778701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 11:46:45.778799 ==
1448 11:46:45.781987 [Gating] SW mode calibration
1449 11:46:45.788569 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 11:46:45.791845 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 11:46:45.798656 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1452 11:46:45.801777 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 11:46:45.805398 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:46:45.811795 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:46:45.815070 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:46:45.818527 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:46:45.825376 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:46:45.828639 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:46:45.831835 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:46:45.838547 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:46:45.841911 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:46:45.845071 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:46:45.851475 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:46:45.854854 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:46:45.858098 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:46:45.864803 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1467 11:46:45.868041 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 11:46:45.871341 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1469 11:46:45.878014 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1470 11:46:45.881292 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:46:45.884905 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:46:45.891468 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:46:45.894711 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:46:45.897954 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:46:45.904756 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:46:45.907847 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1477 11:46:45.911203 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 11:46:45.917754 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:46:45.921125 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:46:45.924674 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:46:45.931600 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:46:45.934372 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:46:45.938002 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:46:45.944341 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (1 0)
1485 11:46:45.947881 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:46:45.951061 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:46:45.954600 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:46:45.960917 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:46:45.964652 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:46:45.967737 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:46:45.974327 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:46:45.977423 0 11 4 | B1->B0 | 3030 3939 | 0 0 | (0 0) (1 1)
1493 11:46:45.980968 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1494 11:46:45.987778 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:46:45.990907 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:46:45.994046 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:46:46.000881 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:46:46.004152 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:46:46.007335 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:46:46.014047 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1501 11:46:46.017106 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:46:46.020718 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:46:46.027197 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:46:46.030466 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:46:46.034149 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:46:46.040753 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:46:46.044198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:46:46.047310 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:46:46.054126 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:46:46.057401 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:46:46.060698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:46:46.067173 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:46:46.070372 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:46:46.073864 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:46:46.080213 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1516 11:46:46.083487 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 11:46:46.086911 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 11:46:46.090153 Total UI for P1: 0, mck2ui 16
1519 11:46:46.093484 best dqsien dly found for B0: ( 0, 14, 2)
1520 11:46:46.097127 Total UI for P1: 0, mck2ui 16
1521 11:46:46.100498 best dqsien dly found for B1: ( 0, 14, 4)
1522 11:46:46.103753 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1523 11:46:46.107077 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1524 11:46:46.107178
1525 11:46:46.110255 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1526 11:46:46.116852 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1527 11:46:46.116955 [Gating] SW calibration Done
1528 11:46:46.117037 ==
1529 11:46:46.120083 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 11:46:46.127128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 11:46:46.127229 ==
1532 11:46:46.127331 RX Vref Scan: 0
1533 11:46:46.127422
1534 11:46:46.130070 RX Vref 0 -> 0, step: 1
1535 11:46:46.130183
1536 11:46:46.133446 RX Delay -130 -> 252, step: 16
1537 11:46:46.136786 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1538 11:46:46.140450 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1539 11:46:46.143250 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1540 11:46:46.150291 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1541 11:46:46.153570 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1542 11:46:46.156864 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1543 11:46:46.160131 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1544 11:46:46.163174 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1545 11:46:46.169858 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1546 11:46:46.173470 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1547 11:46:46.176625 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1548 11:46:46.179638 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1549 11:46:46.183314 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1550 11:46:46.189773 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1551 11:46:46.192920 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1552 11:46:46.196213 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1553 11:46:46.196310 ==
1554 11:46:46.199920 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 11:46:46.203221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 11:46:46.206443 ==
1557 11:46:46.206513 DQS Delay:
1558 11:46:46.206578 DQS0 = 0, DQS1 = 0
1559 11:46:46.209719 DQM Delay:
1560 11:46:46.209790 DQM0 = 90, DQM1 = 80
1561 11:46:46.212848 DQ Delay:
1562 11:46:46.212946 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1563 11:46:46.216416 DQ4 =93, DQ5 =93, DQ6 =101, DQ7 =85
1564 11:46:46.219780 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1565 11:46:46.223060 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 11:46:46.223147
1567 11:46:46.226604
1568 11:46:46.226689 ==
1569 11:46:46.229628 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 11:46:46.233119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 11:46:46.233204 ==
1572 11:46:46.233271
1573 11:46:46.233334
1574 11:46:46.236276 TX Vref Scan disable
1575 11:46:46.236361 == TX Byte 0 ==
1576 11:46:46.242997 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1577 11:46:46.246144 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1578 11:46:46.246239 == TX Byte 1 ==
1579 11:46:46.252673 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1580 11:46:46.255993 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1581 11:46:46.256069 ==
1582 11:46:46.259639 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 11:46:46.262424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 11:46:46.262503 ==
1585 11:46:46.275931 TX Vref=22, minBit 8, minWin=27, winSum=448
1586 11:46:46.279569 TX Vref=24, minBit 13, minWin=27, winSum=452
1587 11:46:46.282585 TX Vref=26, minBit 8, minWin=27, winSum=455
1588 11:46:46.286054 TX Vref=28, minBit 15, minWin=27, winSum=455
1589 11:46:46.289314 TX Vref=30, minBit 15, minWin=27, winSum=457
1590 11:46:46.295920 TX Vref=32, minBit 9, minWin=27, winSum=457
1591 11:46:46.299153 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 30
1592 11:46:46.299255
1593 11:46:46.302787 Final TX Range 1 Vref 30
1594 11:46:46.302858
1595 11:46:46.302921 ==
1596 11:46:46.305917 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:46:46.309749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:46:46.309829 ==
1599 11:46:46.312879
1600 11:46:46.313000
1601 11:46:46.313105 TX Vref Scan disable
1602 11:46:46.316588 == TX Byte 0 ==
1603 11:46:46.319831 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 11:46:46.326278 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 11:46:46.326350 == TX Byte 1 ==
1606 11:46:46.329576 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1607 11:46:46.336082 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1608 11:46:46.336185
1609 11:46:46.336279 [DATLAT]
1610 11:46:46.336367 Freq=800, CH1 RK0
1611 11:46:46.336453
1612 11:46:46.339647 DATLAT Default: 0xa
1613 11:46:46.339718 0, 0xFFFF, sum = 0
1614 11:46:46.342910 1, 0xFFFF, sum = 0
1615 11:46:46.342984 2, 0xFFFF, sum = 0
1616 11:46:46.346243 3, 0xFFFF, sum = 0
1617 11:46:46.349704 4, 0xFFFF, sum = 0
1618 11:46:46.349775 5, 0xFFFF, sum = 0
1619 11:46:46.353081 6, 0xFFFF, sum = 0
1620 11:46:46.353153 7, 0xFFFF, sum = 0
1621 11:46:46.356425 8, 0xFFFF, sum = 0
1622 11:46:46.356509 9, 0x0, sum = 1
1623 11:46:46.356575 10, 0x0, sum = 2
1624 11:46:46.359638 11, 0x0, sum = 3
1625 11:46:46.359722 12, 0x0, sum = 4
1626 11:46:46.362812 best_step = 10
1627 11:46:46.362894
1628 11:46:46.362958 ==
1629 11:46:46.366060 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 11:46:46.369319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 11:46:46.369402 ==
1632 11:46:46.372909 RX Vref Scan: 1
1633 11:46:46.373046
1634 11:46:46.376229 Set Vref Range= 32 -> 127
1635 11:46:46.376311
1636 11:46:46.376376 RX Vref 32 -> 127, step: 1
1637 11:46:46.376436
1638 11:46:46.379447 RX Delay -95 -> 252, step: 8
1639 11:46:46.379530
1640 11:46:46.382714 Set Vref, RX VrefLevel [Byte0]: 32
1641 11:46:46.386264 [Byte1]: 32
1642 11:46:46.386346
1643 11:46:46.389577 Set Vref, RX VrefLevel [Byte0]: 33
1644 11:46:46.392772 [Byte1]: 33
1645 11:46:46.396791
1646 11:46:46.396898 Set Vref, RX VrefLevel [Byte0]: 34
1647 11:46:46.399882 [Byte1]: 34
1648 11:46:46.404653
1649 11:46:46.404775 Set Vref, RX VrefLevel [Byte0]: 35
1650 11:46:46.407945 [Byte1]: 35
1651 11:46:46.412011
1652 11:46:46.412102 Set Vref, RX VrefLevel [Byte0]: 36
1653 11:46:46.415278 [Byte1]: 36
1654 11:46:46.419363
1655 11:46:46.419462 Set Vref, RX VrefLevel [Byte0]: 37
1656 11:46:46.422934 [Byte1]: 37
1657 11:46:46.427085
1658 11:46:46.427167 Set Vref, RX VrefLevel [Byte0]: 38
1659 11:46:46.430292 [Byte1]: 38
1660 11:46:46.434930
1661 11:46:46.435013 Set Vref, RX VrefLevel [Byte0]: 39
1662 11:46:46.437913 [Byte1]: 39
1663 11:46:46.442466
1664 11:46:46.442548 Set Vref, RX VrefLevel [Byte0]: 40
1665 11:46:46.445651 [Byte1]: 40
1666 11:46:46.449953
1667 11:46:46.450061 Set Vref, RX VrefLevel [Byte0]: 41
1668 11:46:46.453281 [Byte1]: 41
1669 11:46:46.457308
1670 11:46:46.457391 Set Vref, RX VrefLevel [Byte0]: 42
1671 11:46:46.460616 [Byte1]: 42
1672 11:46:46.465351
1673 11:46:46.465430 Set Vref, RX VrefLevel [Byte0]: 43
1674 11:46:46.468613 [Byte1]: 43
1675 11:46:46.472621
1676 11:46:46.472719 Set Vref, RX VrefLevel [Byte0]: 44
1677 11:46:46.476152 [Byte1]: 44
1678 11:46:46.480306
1679 11:46:46.480400 Set Vref, RX VrefLevel [Byte0]: 45
1680 11:46:46.483688 [Byte1]: 45
1681 11:46:46.487693
1682 11:46:46.487788 Set Vref, RX VrefLevel [Byte0]: 46
1683 11:46:46.491211 [Byte1]: 46
1684 11:46:46.495619
1685 11:46:46.495717 Set Vref, RX VrefLevel [Byte0]: 47
1686 11:46:46.498785 [Byte1]: 47
1687 11:46:46.503195
1688 11:46:46.503290 Set Vref, RX VrefLevel [Byte0]: 48
1689 11:46:46.506373 [Byte1]: 48
1690 11:46:46.510901
1691 11:46:46.510970 Set Vref, RX VrefLevel [Byte0]: 49
1692 11:46:46.513761 [Byte1]: 49
1693 11:46:46.518460
1694 11:46:46.518574 Set Vref, RX VrefLevel [Byte0]: 50
1695 11:46:46.521499 [Byte1]: 50
1696 11:46:46.525897
1697 11:46:46.525993 Set Vref, RX VrefLevel [Byte0]: 51
1698 11:46:46.529222 [Byte1]: 51
1699 11:46:46.533478
1700 11:46:46.533547 Set Vref, RX VrefLevel [Byte0]: 52
1701 11:46:46.536720 [Byte1]: 52
1702 11:46:46.541261
1703 11:46:46.541362 Set Vref, RX VrefLevel [Byte0]: 53
1704 11:46:46.544368 [Byte1]: 53
1705 11:46:46.548754
1706 11:46:46.548847 Set Vref, RX VrefLevel [Byte0]: 54
1707 11:46:46.551891 [Byte1]: 54
1708 11:46:46.556376
1709 11:46:46.556472 Set Vref, RX VrefLevel [Byte0]: 55
1710 11:46:46.559573 [Byte1]: 55
1711 11:46:46.563826
1712 11:46:46.567021 Set Vref, RX VrefLevel [Byte0]: 56
1713 11:46:46.567120 [Byte1]: 56
1714 11:46:46.571296
1715 11:46:46.571395 Set Vref, RX VrefLevel [Byte0]: 57
1716 11:46:46.574898 [Byte1]: 57
1717 11:46:46.579001
1718 11:46:46.579094 Set Vref, RX VrefLevel [Byte0]: 58
1719 11:46:46.582135 [Byte1]: 58
1720 11:46:46.586813
1721 11:46:46.586959 Set Vref, RX VrefLevel [Byte0]: 59
1722 11:46:46.589986 [Byte1]: 59
1723 11:46:46.594111
1724 11:46:46.594184 Set Vref, RX VrefLevel [Byte0]: 60
1725 11:46:46.597561 [Byte1]: 60
1726 11:46:46.602068
1727 11:46:46.602135 Set Vref, RX VrefLevel [Byte0]: 61
1728 11:46:46.605263 [Byte1]: 61
1729 11:46:46.609584
1730 11:46:46.609695 Set Vref, RX VrefLevel [Byte0]: 62
1731 11:46:46.612853 [Byte1]: 62
1732 11:46:46.616827
1733 11:46:46.616921 Set Vref, RX VrefLevel [Byte0]: 63
1734 11:46:46.620611 [Byte1]: 63
1735 11:46:46.624550
1736 11:46:46.624644 Set Vref, RX VrefLevel [Byte0]: 64
1737 11:46:46.627881 [Byte1]: 64
1738 11:46:46.632087
1739 11:46:46.632218 Set Vref, RX VrefLevel [Byte0]: 65
1740 11:46:46.635818 [Byte1]: 65
1741 11:46:46.639682
1742 11:46:46.639777 Set Vref, RX VrefLevel [Byte0]: 66
1743 11:46:46.643405 [Byte1]: 66
1744 11:46:46.647397
1745 11:46:46.647490 Set Vref, RX VrefLevel [Byte0]: 67
1746 11:46:46.650581 [Byte1]: 67
1747 11:46:46.654911
1748 11:46:46.654984 Set Vref, RX VrefLevel [Byte0]: 68
1749 11:46:46.658446 [Byte1]: 68
1750 11:46:46.662608
1751 11:46:46.662680 Set Vref, RX VrefLevel [Byte0]: 69
1752 11:46:46.665743 [Byte1]: 69
1753 11:46:46.670112
1754 11:46:46.670180 Set Vref, RX VrefLevel [Byte0]: 70
1755 11:46:46.673413 [Byte1]: 70
1756 11:46:46.677882
1757 11:46:46.678036 Set Vref, RX VrefLevel [Byte0]: 71
1758 11:46:46.681191 [Byte1]: 71
1759 11:46:46.685400
1760 11:46:46.685468 Set Vref, RX VrefLevel [Byte0]: 72
1761 11:46:46.688524 [Byte1]: 72
1762 11:46:46.693295
1763 11:46:46.693364 Set Vref, RX VrefLevel [Byte0]: 73
1764 11:46:46.699215 [Byte1]: 73
1765 11:46:46.699316
1766 11:46:46.702557 Set Vref, RX VrefLevel [Byte0]: 74
1767 11:46:46.705899 [Byte1]: 74
1768 11:46:46.705993
1769 11:46:46.708960 Set Vref, RX VrefLevel [Byte0]: 75
1770 11:46:46.712667 [Byte1]: 75
1771 11:46:46.715760
1772 11:46:46.715852 Set Vref, RX VrefLevel [Byte0]: 76
1773 11:46:46.719017 [Byte1]: 76
1774 11:46:46.723294
1775 11:46:46.723388 Set Vref, RX VrefLevel [Byte0]: 77
1776 11:46:46.726779 [Byte1]: 77
1777 11:46:46.730947
1778 11:46:46.731041 Set Vref, RX VrefLevel [Byte0]: 78
1779 11:46:46.734336 [Byte1]: 78
1780 11:46:46.738755
1781 11:46:46.738851 Set Vref, RX VrefLevel [Byte0]: 79
1782 11:46:46.741843 [Byte1]: 79
1783 11:46:46.746043
1784 11:46:46.746139 Set Vref, RX VrefLevel [Byte0]: 80
1785 11:46:46.749627 [Byte1]: 80
1786 11:46:46.753767
1787 11:46:46.753835 Final RX Vref Byte 0 = 51 to rank0
1788 11:46:46.756957 Final RX Vref Byte 1 = 66 to rank0
1789 11:46:46.760241 Final RX Vref Byte 0 = 51 to rank1
1790 11:46:46.763814 Final RX Vref Byte 1 = 66 to rank1==
1791 11:46:46.767066 Dram Type= 6, Freq= 0, CH_1, rank 0
1792 11:46:46.773737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 11:46:46.773813 ==
1794 11:46:46.773877 DQS Delay:
1795 11:46:46.773935 DQS0 = 0, DQS1 = 0
1796 11:46:46.776862 DQM Delay:
1797 11:46:46.776970 DQM0 = 92, DQM1 = 81
1798 11:46:46.780320 DQ Delay:
1799 11:46:46.783605 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1800 11:46:46.786992 DQ4 =92, DQ5 =100, DQ6 =100, DQ7 =88
1801 11:46:46.790348 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1802 11:46:46.793706 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1803 11:46:46.793806
1804 11:46:46.793905
1805 11:46:46.800247 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1806 11:46:46.803828 CH1 RK0: MR19=606, MR18=2B48
1807 11:46:46.810510 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1808 11:46:46.810582
1809 11:46:46.813629 ----->DramcWriteLeveling(PI) begin...
1810 11:46:46.813702 ==
1811 11:46:46.816992 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 11:46:46.820227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 11:46:46.820319 ==
1814 11:46:46.823614 Write leveling (Byte 0): 27 => 27
1815 11:46:46.826834 Write leveling (Byte 1): 29 => 29
1816 11:46:46.830061 DramcWriteLeveling(PI) end<-----
1817 11:46:46.830132
1818 11:46:46.830193 ==
1819 11:46:46.833643 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 11:46:46.836609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1821 11:46:46.836703 ==
1822 11:46:46.839935 [Gating] SW mode calibration
1823 11:46:46.846756 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1824 11:46:46.853247 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1825 11:46:46.856566 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1826 11:46:46.860109 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1827 11:46:46.867045 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:46:46.869952 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:46:46.873539 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:46:46.880254 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:46:46.883400 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:46:46.887027 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:46:46.893538 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:46:46.897271 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:46:46.900132 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:46:46.906587 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:46:46.910084 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:46:46.913222 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:46:46.920062 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:46:46.923176 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:46:46.926961 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:46:46.933312 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1843 11:46:46.936864 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:46:46.940197 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:46:46.946568 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:46:46.949882 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:46:46.953329 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:46:46.959724 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:46:46.963422 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:46:46.966679 0 9 4 | B1->B0 | 2323 2424 | 1 0 | (0 0) (0 0)
1851 11:46:46.973125 0 9 8 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1852 11:46:46.976578 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 11:46:46.979603 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 11:46:46.983397 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 11:46:46.989881 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 11:46:46.993135 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 11:46:46.996583 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 11:46:47.003218 0 10 4 | B1->B0 | 2d2d 2f2f | 1 0 | (1 1) (0 1)
1859 11:46:47.006487 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:46:47.010007 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:46:47.016682 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:46:47.019935 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:46:47.023040 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 11:46:47.029771 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:46:47.032889 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:46:47.036258 0 11 4 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 0)
1867 11:46:47.043218 0 11 8 | B1->B0 | 3f3f 4040 | 1 0 | (0 0) (0 0)
1868 11:46:47.046364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 11:46:47.049753 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 11:46:47.056047 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 11:46:47.059410 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 11:46:47.062950 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 11:46:47.069499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1874 11:46:47.072752 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1875 11:46:47.075953 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1876 11:46:47.082685 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:46:47.085967 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:46:47.089274 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 11:46:47.095992 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 11:46:47.099453 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 11:46:47.102495 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 11:46:47.109239 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 11:46:47.112602 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 11:46:47.115627 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 11:46:47.122273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 11:46:47.131877 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 11:46:47.132158 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 11:46:47.135828 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 11:46:47.138955 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 11:46:47.142279 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1891 11:46:47.148761 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 11:46:47.148852 Total UI for P1: 0, mck2ui 16
1893 11:46:47.152575 best dqsien dly found for B0: ( 0, 14, 4)
1894 11:46:47.155655 Total UI for P1: 0, mck2ui 16
1895 11:46:47.158795 best dqsien dly found for B1: ( 0, 14, 4)
1896 11:46:47.162085 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1897 11:46:47.168863 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1898 11:46:47.168973
1899 11:46:47.172275 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1900 11:46:47.175568 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1901 11:46:47.178855 [Gating] SW calibration Done
1902 11:46:47.178952 ==
1903 11:46:47.182066 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 11:46:47.185587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 11:46:47.185689 ==
1906 11:46:47.185780 RX Vref Scan: 0
1907 11:46:47.185868
1908 11:46:47.188729 RX Vref 0 -> 0, step: 1
1909 11:46:47.188794
1910 11:46:47.191859 RX Delay -130 -> 252, step: 16
1911 11:46:47.195570 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1912 11:46:47.198880 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1913 11:46:47.205288 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1914 11:46:47.208529 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1915 11:46:47.212251 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1916 11:46:47.215368 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1917 11:46:47.218555 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1918 11:46:47.225198 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1919 11:46:47.228621 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1920 11:46:47.231802 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1921 11:46:47.235191 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1922 11:46:47.238364 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1923 11:46:47.245344 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1924 11:46:47.248636 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1925 11:46:47.251890 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1926 11:46:47.255431 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1927 11:46:47.255531 ==
1928 11:46:47.258237 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 11:46:47.264948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 11:46:47.265076 ==
1931 11:46:47.265140 DQS Delay:
1932 11:46:47.268236 DQS0 = 0, DQS1 = 0
1933 11:46:47.268332 DQM Delay:
1934 11:46:47.268420 DQM0 = 89, DQM1 = 82
1935 11:46:47.271790 DQ Delay:
1936 11:46:47.275020 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1937 11:46:47.278378 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1938 11:46:47.281718 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1939 11:46:47.284920 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1940 11:46:47.285047
1941 11:46:47.285110
1942 11:46:47.285172 ==
1943 11:46:47.288615 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 11:46:47.291495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 11:46:47.291590 ==
1946 11:46:47.291676
1947 11:46:47.291761
1948 11:46:47.294738 TX Vref Scan disable
1949 11:46:47.298320 == TX Byte 0 ==
1950 11:46:47.301618 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1951 11:46:47.304800 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1952 11:46:47.308094 == TX Byte 1 ==
1953 11:46:47.311282 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1954 11:46:47.314537 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1955 11:46:47.314637 ==
1956 11:46:47.318085 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 11:46:47.321205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 11:46:47.321305 ==
1959 11:46:47.335773 TX Vref=22, minBit 15, minWin=27, winSum=452
1960 11:46:47.339089 TX Vref=24, minBit 13, minWin=27, winSum=456
1961 11:46:47.342269 TX Vref=26, minBit 15, minWin=27, winSum=454
1962 11:46:47.345718 TX Vref=28, minBit 8, minWin=28, winSum=458
1963 11:46:47.348889 TX Vref=30, minBit 8, minWin=28, winSum=462
1964 11:46:47.355833 TX Vref=32, minBit 9, minWin=27, winSum=457
1965 11:46:47.359088 [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 30
1966 11:46:47.359176
1967 11:46:47.362237 Final TX Range 1 Vref 30
1968 11:46:47.362334
1969 11:46:47.362422 ==
1970 11:46:47.365457 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 11:46:47.368752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 11:46:47.371978 ==
1973 11:46:47.372086
1974 11:46:47.372167
1975 11:46:47.372229 TX Vref Scan disable
1976 11:46:47.375906 == TX Byte 0 ==
1977 11:46:47.379241 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1978 11:46:47.386041 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1979 11:46:47.386143 == TX Byte 1 ==
1980 11:46:47.389212 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1981 11:46:47.395771 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1982 11:46:47.395881
1983 11:46:47.395975 [DATLAT]
1984 11:46:47.396059 Freq=800, CH1 RK1
1985 11:46:47.396124
1986 11:46:47.398935 DATLAT Default: 0xa
1987 11:46:47.399032 0, 0xFFFF, sum = 0
1988 11:46:47.402517 1, 0xFFFF, sum = 0
1989 11:46:47.402623 2, 0xFFFF, sum = 0
1990 11:46:47.405583 3, 0xFFFF, sum = 0
1991 11:46:47.409255 4, 0xFFFF, sum = 0
1992 11:46:47.409361 5, 0xFFFF, sum = 0
1993 11:46:47.412324 6, 0xFFFF, sum = 0
1994 11:46:47.412431 7, 0xFFFF, sum = 0
1995 11:46:47.415577 8, 0xFFFF, sum = 0
1996 11:46:47.415680 9, 0x0, sum = 1
1997 11:46:47.415772 10, 0x0, sum = 2
1998 11:46:47.418784 11, 0x0, sum = 3
1999 11:46:47.418882 12, 0x0, sum = 4
2000 11:46:47.422351 best_step = 10
2001 11:46:47.422446
2002 11:46:47.422545 ==
2003 11:46:47.425660 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 11:46:47.428847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 11:46:47.428945 ==
2006 11:46:47.432425 RX Vref Scan: 0
2007 11:46:47.432522
2008 11:46:47.432610 RX Vref 0 -> 0, step: 1
2009 11:46:47.435679
2010 11:46:47.435781 RX Delay -79 -> 252, step: 8
2011 11:46:47.442546 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2012 11:46:47.445570 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2013 11:46:47.449350 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2014 11:46:47.452212 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2015 11:46:47.455857 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2016 11:46:47.462431 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2017 11:46:47.465583 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2018 11:46:47.468881 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2019 11:46:47.472188 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2020 11:46:47.475395 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2021 11:46:47.481917 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2022 11:46:47.485173 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2023 11:46:47.488733 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2024 11:46:47.491921 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2025 11:46:47.498686 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2026 11:46:47.501731 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2027 11:46:47.501808 ==
2028 11:46:47.505323 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 11:46:47.508622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 11:46:47.508725 ==
2031 11:46:47.508817 DQS Delay:
2032 11:46:47.511776 DQS0 = 0, DQS1 = 0
2033 11:46:47.511871 DQM Delay:
2034 11:46:47.515132 DQM0 = 92, DQM1 = 83
2035 11:46:47.515229 DQ Delay:
2036 11:46:47.518773 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2037 11:46:47.521929 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2038 11:46:47.525358 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =80
2039 11:46:47.528627 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2040 11:46:47.528731
2041 11:46:47.528826
2042 11:46:47.538636 [DQSOSCAuto] RK1, (LSB)MR18= 0x350a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2043 11:46:47.538739 CH1 RK1: MR19=606, MR18=350A
2044 11:46:47.545344 CH1_RK1: MR19=0x606, MR18=0x350A, DQSOSC=396, MR23=63, INC=94, DEC=62
2045 11:46:47.548340 [RxdqsGatingPostProcess] freq 800
2046 11:46:47.555349 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2047 11:46:47.558521 Pre-setting of DQS Precalculation
2048 11:46:47.561656 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2049 11:46:47.568429 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2050 11:46:47.578607 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2051 11:46:47.578701
2052 11:46:47.578793
2053 11:46:47.581775 [Calibration Summary] 1600 Mbps
2054 11:46:47.581874 CH 0, Rank 0
2055 11:46:47.584951 SW Impedance : PASS
2056 11:46:47.585067 DUTY Scan : NO K
2057 11:46:47.588221 ZQ Calibration : PASS
2058 11:46:47.588289 Jitter Meter : NO K
2059 11:46:47.591907 CBT Training : PASS
2060 11:46:47.594793 Write leveling : PASS
2061 11:46:47.594936 RX DQS gating : PASS
2062 11:46:47.598071 RX DQ/DQS(RDDQC) : PASS
2063 11:46:47.601806 TX DQ/DQS : PASS
2064 11:46:47.601903 RX DATLAT : PASS
2065 11:46:47.604824 RX DQ/DQS(Engine): PASS
2066 11:46:47.608054 TX OE : NO K
2067 11:46:47.608137 All Pass.
2068 11:46:47.608198
2069 11:46:47.608256 CH 0, Rank 1
2070 11:46:47.611829 SW Impedance : PASS
2071 11:46:47.614999 DUTY Scan : NO K
2072 11:46:47.615097 ZQ Calibration : PASS
2073 11:46:47.618117 Jitter Meter : NO K
2074 11:46:47.621357 CBT Training : PASS
2075 11:46:47.621432 Write leveling : PASS
2076 11:46:47.624739 RX DQS gating : PASS
2077 11:46:47.628270 RX DQ/DQS(RDDQC) : PASS
2078 11:46:47.628365 TX DQ/DQS : PASS
2079 11:46:47.631494 RX DATLAT : PASS
2080 11:46:47.634705 RX DQ/DQS(Engine): PASS
2081 11:46:47.634800 TX OE : NO K
2082 11:46:47.634890 All Pass.
2083 11:46:47.634975
2084 11:46:47.637796 CH 1, Rank 0
2085 11:46:47.641041 SW Impedance : PASS
2086 11:46:47.641146 DUTY Scan : NO K
2087 11:46:47.644604 ZQ Calibration : PASS
2088 11:46:47.644702 Jitter Meter : NO K
2089 11:46:47.648092 CBT Training : PASS
2090 11:46:47.651093 Write leveling : PASS
2091 11:46:47.651198 RX DQS gating : PASS
2092 11:46:47.654718 RX DQ/DQS(RDDQC) : PASS
2093 11:46:47.657789 TX DQ/DQS : PASS
2094 11:46:47.657901 RX DATLAT : PASS
2095 11:46:47.661279 RX DQ/DQS(Engine): PASS
2096 11:46:47.664654 TX OE : NO K
2097 11:46:47.664763 All Pass.
2098 11:46:47.664857
2099 11:46:47.664948 CH 1, Rank 1
2100 11:46:47.668196 SW Impedance : PASS
2101 11:46:47.671454 DUTY Scan : NO K
2102 11:46:47.671567 ZQ Calibration : PASS
2103 11:46:47.674588 Jitter Meter : NO K
2104 11:46:47.677898 CBT Training : PASS
2105 11:46:47.677981 Write leveling : PASS
2106 11:46:47.681007 RX DQS gating : PASS
2107 11:46:47.684619 RX DQ/DQS(RDDQC) : PASS
2108 11:46:47.684719 TX DQ/DQS : PASS
2109 11:46:47.687932 RX DATLAT : PASS
2110 11:46:47.691162 RX DQ/DQS(Engine): PASS
2111 11:46:47.691263 TX OE : NO K
2112 11:46:47.691355 All Pass.
2113 11:46:47.691443
2114 11:46:47.694451 DramC Write-DBI off
2115 11:46:47.697867 PER_BANK_REFRESH: Hybrid Mode
2116 11:46:47.697966 TX_TRACKING: ON
2117 11:46:47.700970 [GetDramInforAfterCalByMRR] Vendor 6.
2118 11:46:47.704599 [GetDramInforAfterCalByMRR] Revision 606.
2119 11:46:47.710806 [GetDramInforAfterCalByMRR] Revision 2 0.
2120 11:46:47.710905 MR0 0x3b3b
2121 11:46:47.710996 MR8 0x5151
2122 11:46:47.714220 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 11:46:47.714318
2124 11:46:47.717419 MR0 0x3b3b
2125 11:46:47.717487 MR8 0x5151
2126 11:46:47.721216 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2127 11:46:47.721288
2128 11:46:47.730868 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2129 11:46:47.733934 [FAST_K] Save calibration result to emmc
2130 11:46:47.737689 [FAST_K] Save calibration result to emmc
2131 11:46:47.740811 dram_init: config_dvfs: 1
2132 11:46:47.744111 dramc_set_vcore_voltage set vcore to 662500
2133 11:46:47.747687 Read voltage for 1200, 2
2134 11:46:47.747784 Vio18 = 0
2135 11:46:47.747874 Vcore = 662500
2136 11:46:47.750662 Vdram = 0
2137 11:46:47.750757 Vddq = 0
2138 11:46:47.750844 Vmddr = 0
2139 11:46:47.757374 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2140 11:46:47.760859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2141 11:46:47.763950 MEM_TYPE=3, freq_sel=15
2142 11:46:47.767292 sv_algorithm_assistance_LP4_1600
2143 11:46:47.770994 ============ PULL DRAM RESETB DOWN ============
2144 11:46:47.773970 ========== PULL DRAM RESETB DOWN end =========
2145 11:46:47.780811 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2146 11:46:47.784074 ===================================
2147 11:46:47.784173 LPDDR4 DRAM CONFIGURATION
2148 11:46:47.787319 ===================================
2149 11:46:47.790479 EX_ROW_EN[0] = 0x0
2150 11:46:47.793948 EX_ROW_EN[1] = 0x0
2151 11:46:47.794047 LP4Y_EN = 0x0
2152 11:46:47.797289 WORK_FSP = 0x0
2153 11:46:47.797360 WL = 0x4
2154 11:46:47.800544 RL = 0x4
2155 11:46:47.800641 BL = 0x2
2156 11:46:47.804099 RPST = 0x0
2157 11:46:47.804184 RD_PRE = 0x0
2158 11:46:47.807480 WR_PRE = 0x1
2159 11:46:47.807562 WR_PST = 0x0
2160 11:46:47.810582 DBI_WR = 0x0
2161 11:46:47.810666 DBI_RD = 0x0
2162 11:46:47.813585 OTF = 0x1
2163 11:46:47.817299 ===================================
2164 11:46:47.820678 ===================================
2165 11:46:47.820761 ANA top config
2166 11:46:47.824150 ===================================
2167 11:46:47.827352 DLL_ASYNC_EN = 0
2168 11:46:47.830569 ALL_SLAVE_EN = 0
2169 11:46:47.830652 NEW_RANK_MODE = 1
2170 11:46:47.833666 DLL_IDLE_MODE = 1
2171 11:46:47.837300 LP45_APHY_COMB_EN = 1
2172 11:46:47.840419 TX_ODT_DIS = 1
2173 11:46:47.843679 NEW_8X_MODE = 1
2174 11:46:47.846934 ===================================
2175 11:46:47.850295 ===================================
2176 11:46:47.850378 data_rate = 2400
2177 11:46:47.853654 CKR = 1
2178 11:46:47.856869 DQ_P2S_RATIO = 8
2179 11:46:47.860226 ===================================
2180 11:46:47.863421 CA_P2S_RATIO = 8
2181 11:46:47.866868 DQ_CA_OPEN = 0
2182 11:46:47.870184 DQ_SEMI_OPEN = 0
2183 11:46:47.870294 CA_SEMI_OPEN = 0
2184 11:46:47.873586 CA_FULL_RATE = 0
2185 11:46:47.877047 DQ_CKDIV4_EN = 0
2186 11:46:47.880385 CA_CKDIV4_EN = 0
2187 11:46:47.883592 CA_PREDIV_EN = 0
2188 11:46:47.887147 PH8_DLY = 17
2189 11:46:47.887231 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2190 11:46:47.890276 DQ_AAMCK_DIV = 4
2191 11:46:47.893559 CA_AAMCK_DIV = 4
2192 11:46:47.896767 CA_ADMCK_DIV = 4
2193 11:46:47.900391 DQ_TRACK_CA_EN = 0
2194 11:46:47.903790 CA_PICK = 1200
2195 11:46:47.907123 CA_MCKIO = 1200
2196 11:46:47.907207 MCKIO_SEMI = 0
2197 11:46:47.910236 PLL_FREQ = 2366
2198 11:46:47.913566 DQ_UI_PI_RATIO = 32
2199 11:46:47.916911 CA_UI_PI_RATIO = 0
2200 11:46:47.920078 ===================================
2201 11:46:47.923373 ===================================
2202 11:46:47.926734 memory_type:LPDDR4
2203 11:46:47.926818 GP_NUM : 10
2204 11:46:47.929889 SRAM_EN : 1
2205 11:46:47.933193 MD32_EN : 0
2206 11:46:47.936831 ===================================
2207 11:46:47.936915 [ANA_INIT] >>>>>>>>>>>>>>
2208 11:46:47.939937 <<<<<< [CONFIGURE PHASE]: ANA_TX
2209 11:46:47.943637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2210 11:46:47.946763 ===================================
2211 11:46:47.950016 data_rate = 2400,PCW = 0X5b00
2212 11:46:47.953215 ===================================
2213 11:46:47.956625 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2214 11:46:47.963430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 11:46:47.966585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 11:46:47.973139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2217 11:46:47.976418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2218 11:46:47.979836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2219 11:46:47.979920 [ANA_INIT] flow start
2220 11:46:47.983237 [ANA_INIT] PLL >>>>>>>>
2221 11:46:47.986419 [ANA_INIT] PLL <<<<<<<<
2222 11:46:47.986503 [ANA_INIT] MIDPI >>>>>>>>
2223 11:46:47.989856 [ANA_INIT] MIDPI <<<<<<<<
2224 11:46:47.993140 [ANA_INIT] DLL >>>>>>>>
2225 11:46:47.996790 [ANA_INIT] DLL <<<<<<<<
2226 11:46:47.996874 [ANA_INIT] flow end
2227 11:46:47.999660 ============ LP4 DIFF to SE enter ============
2228 11:46:48.006379 ============ LP4 DIFF to SE exit ============
2229 11:46:48.006468 [ANA_INIT] <<<<<<<<<<<<<
2230 11:46:48.009647 [Flow] Enable top DCM control >>>>>
2231 11:46:48.013166 [Flow] Enable top DCM control <<<<<
2232 11:46:48.016205 Enable DLL master slave shuffle
2233 11:46:48.023019 ==============================================================
2234 11:46:48.023102 Gating Mode config
2235 11:46:48.029449 ==============================================================
2236 11:46:48.032605 Config description:
2237 11:46:48.042754 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2238 11:46:48.049784 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2239 11:46:48.052892 SELPH_MODE 0: By rank 1: By Phase
2240 11:46:48.059377 ==============================================================
2241 11:46:48.062842 GAT_TRACK_EN = 1
2242 11:46:48.062924 RX_GATING_MODE = 2
2243 11:46:48.066317 RX_GATING_TRACK_MODE = 2
2244 11:46:48.069554 SELPH_MODE = 1
2245 11:46:48.072712 PICG_EARLY_EN = 1
2246 11:46:48.076318 VALID_LAT_VALUE = 1
2247 11:46:48.082678 ==============================================================
2248 11:46:48.086093 Enter into Gating configuration >>>>
2249 11:46:48.089472 Exit from Gating configuration <<<<
2250 11:46:48.092797 Enter into DVFS_PRE_config >>>>>
2251 11:46:48.102739 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2252 11:46:48.105907 Exit from DVFS_PRE_config <<<<<
2253 11:46:48.109153 Enter into PICG configuration >>>>
2254 11:46:48.112736 Exit from PICG configuration <<<<
2255 11:46:48.115896 [RX_INPUT] configuration >>>>>
2256 11:46:48.119089 [RX_INPUT] configuration <<<<<
2257 11:46:48.122343 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2258 11:46:48.129327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2259 11:46:48.135794 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 11:46:48.139088 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 11:46:48.145781 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2262 11:46:48.152387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2263 11:46:48.155670 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2264 11:46:48.162218 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2265 11:46:48.165335 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2266 11:46:48.168833 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2267 11:46:48.172038 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2268 11:46:48.178874 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 11:46:48.182121 ===================================
2270 11:46:48.182198 LPDDR4 DRAM CONFIGURATION
2271 11:46:48.185707 ===================================
2272 11:46:48.189068 EX_ROW_EN[0] = 0x0
2273 11:46:48.192007 EX_ROW_EN[1] = 0x0
2274 11:46:48.192087 LP4Y_EN = 0x0
2275 11:46:48.195338 WORK_FSP = 0x0
2276 11:46:48.195416 WL = 0x4
2277 11:46:48.198720 RL = 0x4
2278 11:46:48.198793 BL = 0x2
2279 11:46:48.202031 RPST = 0x0
2280 11:46:48.202105 RD_PRE = 0x0
2281 11:46:48.205334 WR_PRE = 0x1
2282 11:46:48.205408 WR_PST = 0x0
2283 11:46:48.208656 DBI_WR = 0x0
2284 11:46:48.208754 DBI_RD = 0x0
2285 11:46:48.212474 OTF = 0x1
2286 11:46:48.215562 ===================================
2287 11:46:48.218807 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2288 11:46:48.222059 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2289 11:46:48.228642 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 11:46:48.232129 ===================================
2291 11:46:48.232212 LPDDR4 DRAM CONFIGURATION
2292 11:46:48.235380 ===================================
2293 11:46:48.238688 EX_ROW_EN[0] = 0x10
2294 11:46:48.241932 EX_ROW_EN[1] = 0x0
2295 11:46:48.242015 LP4Y_EN = 0x0
2296 11:46:48.245231 WORK_FSP = 0x0
2297 11:46:48.245313 WL = 0x4
2298 11:46:48.248404 RL = 0x4
2299 11:46:48.248527 BL = 0x2
2300 11:46:48.251815 RPST = 0x0
2301 11:46:48.251923 RD_PRE = 0x0
2302 11:46:48.254930 WR_PRE = 0x1
2303 11:46:48.255002 WR_PST = 0x0
2304 11:46:48.258221 DBI_WR = 0x0
2305 11:46:48.258302 DBI_RD = 0x0
2306 11:46:48.262013 OTF = 0x1
2307 11:46:48.265184 ===================================
2308 11:46:48.271854 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2309 11:46:48.271935 ==
2310 11:46:48.275034 Dram Type= 6, Freq= 0, CH_0, rank 0
2311 11:46:48.278110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2312 11:46:48.278191 ==
2313 11:46:48.281817 [Duty_Offset_Calibration]
2314 11:46:48.281968 B0:2 B1:0 CA:1
2315 11:46:48.282139
2316 11:46:48.284909 [DutyScan_Calibration_Flow] k_type=0
2317 11:46:48.294230
2318 11:46:48.294340 ==CLK 0==
2319 11:46:48.297386 Final CLK duty delay cell = -4
2320 11:46:48.300916 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2321 11:46:48.304132 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2322 11:46:48.307293 [-4] AVG Duty = 4953%(X100)
2323 11:46:48.307395
2324 11:46:48.310657 CH0 CLK Duty spec in!! Max-Min= 156%
2325 11:46:48.314340 [DutyScan_Calibration_Flow] ====Done====
2326 11:46:48.314420
2327 11:46:48.317428 [DutyScan_Calibration_Flow] k_type=1
2328 11:46:48.333353
2329 11:46:48.333433 ==DQS 0 ==
2330 11:46:48.336297 Final DQS duty delay cell = 0
2331 11:46:48.339993 [0] MAX Duty = 5187%(X100), DQS PI = 30
2332 11:46:48.343241 [0] MIN Duty = 4938%(X100), DQS PI = 0
2333 11:46:48.343321 [0] AVG Duty = 5062%(X100)
2334 11:46:48.346525
2335 11:46:48.346644 ==DQS 1 ==
2336 11:46:48.349731 Final DQS duty delay cell = -4
2337 11:46:48.352957 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2338 11:46:48.356563 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2339 11:46:48.359692 [-4] AVG Duty = 5031%(X100)
2340 11:46:48.359772
2341 11:46:48.362968 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2342 11:46:48.363050
2343 11:46:48.366175 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2344 11:46:48.369590 [DutyScan_Calibration_Flow] ====Done====
2345 11:46:48.369670
2346 11:46:48.372990 [DutyScan_Calibration_Flow] k_type=3
2347 11:46:48.389980
2348 11:46:48.390061 ==DQM 0 ==
2349 11:46:48.393141 Final DQM duty delay cell = 0
2350 11:46:48.396399 [0] MAX Duty = 5062%(X100), DQS PI = 24
2351 11:46:48.399906 [0] MIN Duty = 4875%(X100), DQS PI = 0
2352 11:46:48.400015 [0] AVG Duty = 4968%(X100)
2353 11:46:48.402948
2354 11:46:48.403049 ==DQM 1 ==
2355 11:46:48.406448 Final DQM duty delay cell = 0
2356 11:46:48.409552 [0] MAX Duty = 5218%(X100), DQS PI = 50
2357 11:46:48.412785 [0] MIN Duty = 5000%(X100), DQS PI = 22
2358 11:46:48.416358 [0] AVG Duty = 5109%(X100)
2359 11:46:48.416458
2360 11:46:48.419936 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2361 11:46:48.420009
2362 11:46:48.423092 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2363 11:46:48.426378 [DutyScan_Calibration_Flow] ====Done====
2364 11:46:48.426449
2365 11:46:48.429452 [DutyScan_Calibration_Flow] k_type=2
2366 11:46:48.446336
2367 11:46:48.446418 ==DQ 0 ==
2368 11:46:48.449593 Final DQ duty delay cell = -4
2369 11:46:48.452875 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2370 11:46:48.456139 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2371 11:46:48.459678 [-4] AVG Duty = 4953%(X100)
2372 11:46:48.459760
2373 11:46:48.459825 ==DQ 1 ==
2374 11:46:48.463162 Final DQ duty delay cell = 4
2375 11:46:48.466354 [4] MAX Duty = 5093%(X100), DQS PI = 6
2376 11:46:48.469627 [4] MIN Duty = 5031%(X100), DQS PI = 2
2377 11:46:48.469702 [4] AVG Duty = 5062%(X100)
2378 11:46:48.472868
2379 11:46:48.476220 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2380 11:46:48.476296
2381 11:46:48.479722 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2382 11:46:48.482887 [DutyScan_Calibration_Flow] ====Done====
2383 11:46:48.482993 ==
2384 11:46:48.486189 Dram Type= 6, Freq= 0, CH_1, rank 0
2385 11:46:48.489312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2386 11:46:48.489416 ==
2387 11:46:48.492904 [Duty_Offset_Calibration]
2388 11:46:48.493060 B0:0 B1:-1 CA:2
2389 11:46:48.493154
2390 11:46:48.496279 [DutyScan_Calibration_Flow] k_type=0
2391 11:46:48.506513
2392 11:46:48.506625 ==CLK 0==
2393 11:46:48.509914 Final CLK duty delay cell = 0
2394 11:46:48.512852 [0] MAX Duty = 5156%(X100), DQS PI = 16
2395 11:46:48.516246 [0] MIN Duty = 4969%(X100), DQS PI = 44
2396 11:46:48.519436 [0] AVG Duty = 5062%(X100)
2397 11:46:48.519539
2398 11:46:48.523091 CH1 CLK Duty spec in!! Max-Min= 187%
2399 11:46:48.526325 [DutyScan_Calibration_Flow] ====Done====
2400 11:46:48.526436
2401 11:46:48.529554 [DutyScan_Calibration_Flow] k_type=1
2402 11:46:48.545942
2403 11:46:48.546025 ==DQS 0 ==
2404 11:46:48.549243 Final DQS duty delay cell = 0
2405 11:46:48.552388 [0] MAX Duty = 5093%(X100), DQS PI = 22
2406 11:46:48.555692 [0] MIN Duty = 4969%(X100), DQS PI = 0
2407 11:46:48.559301 [0] AVG Duty = 5031%(X100)
2408 11:46:48.559398
2409 11:46:48.559487 ==DQS 1 ==
2410 11:46:48.562523 Final DQS duty delay cell = 0
2411 11:46:48.566096 [0] MAX Duty = 5156%(X100), DQS PI = 0
2412 11:46:48.569118 [0] MIN Duty = 4844%(X100), DQS PI = 36
2413 11:46:48.569191 [0] AVG Duty = 5000%(X100)
2414 11:46:48.569251
2415 11:46:48.576268 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2416 11:46:48.576367
2417 11:46:48.579552 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2418 11:46:48.582664 [DutyScan_Calibration_Flow] ====Done====
2419 11:46:48.582738
2420 11:46:48.585943 [DutyScan_Calibration_Flow] k_type=3
2421 11:46:48.602305
2422 11:46:48.602392 ==DQM 0 ==
2423 11:46:48.605561 Final DQM duty delay cell = 4
2424 11:46:48.608730 [4] MAX Duty = 5093%(X100), DQS PI = 6
2425 11:46:48.612445 [4] MIN Duty = 4938%(X100), DQS PI = 44
2426 11:46:48.612527 [4] AVG Duty = 5015%(X100)
2427 11:46:48.615564
2428 11:46:48.615645 ==DQM 1 ==
2429 11:46:48.618848 Final DQM duty delay cell = -4
2430 11:46:48.622212 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2431 11:46:48.625731 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2432 11:46:48.628749 [-4] AVG Duty = 4875%(X100)
2433 11:46:48.628852
2434 11:46:48.632057 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2435 11:46:48.632133
2436 11:46:48.635304 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2437 11:46:48.638567 [DutyScan_Calibration_Flow] ====Done====
2438 11:46:48.638648
2439 11:46:48.641862 [DutyScan_Calibration_Flow] k_type=2
2440 11:46:48.659031
2441 11:46:48.659119 ==DQ 0 ==
2442 11:46:48.662296 Final DQ duty delay cell = 0
2443 11:46:48.665493 [0] MAX Duty = 5062%(X100), DQS PI = 18
2444 11:46:48.669112 [0] MIN Duty = 4938%(X100), DQS PI = 0
2445 11:46:48.669190 [0] AVG Duty = 5000%(X100)
2446 11:46:48.672249
2447 11:46:48.672352 ==DQ 1 ==
2448 11:46:48.675500 Final DQ duty delay cell = 0
2449 11:46:48.679304 [0] MAX Duty = 5031%(X100), DQS PI = 2
2450 11:46:48.682408 [0] MIN Duty = 4813%(X100), DQS PI = 36
2451 11:46:48.682483 [0] AVG Duty = 4922%(X100)
2452 11:46:48.682547
2453 11:46:48.685737 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2454 11:46:48.688876
2455 11:46:48.692211 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2456 11:46:48.695277 [DutyScan_Calibration_Flow] ====Done====
2457 11:46:48.698854 nWR fixed to 30
2458 11:46:48.698934 [ModeRegInit_LP4] CH0 RK0
2459 11:46:48.702047 [ModeRegInit_LP4] CH0 RK1
2460 11:46:48.705200 [ModeRegInit_LP4] CH1 RK0
2461 11:46:48.708852 [ModeRegInit_LP4] CH1 RK1
2462 11:46:48.708925 match AC timing 7
2463 11:46:48.712025 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2464 11:46:48.718426 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2465 11:46:48.721995 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2466 11:46:48.728501 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2467 11:46:48.731870 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2468 11:46:48.731946 ==
2469 11:46:48.735203 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 11:46:48.738600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 11:46:48.738682 ==
2472 11:46:48.745118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 11:46:48.751393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2474 11:46:48.758685 [CA 0] Center 38 (7~69) winsize 63
2475 11:46:48.762504 [CA 1] Center 38 (8~69) winsize 62
2476 11:46:48.765661 [CA 2] Center 35 (5~66) winsize 62
2477 11:46:48.768901 [CA 3] Center 35 (4~66) winsize 63
2478 11:46:48.772335 [CA 4] Center 34 (4~65) winsize 62
2479 11:46:48.775420 [CA 5] Center 33 (3~63) winsize 61
2480 11:46:48.775495
2481 11:46:48.778970 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 11:46:48.779051
2483 11:46:48.782252 [CATrainingPosCal] consider 1 rank data
2484 11:46:48.785384 u2DelayCellTimex100 = 270/100 ps
2485 11:46:48.788965 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2486 11:46:48.792223 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2487 11:46:48.798750 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 11:46:48.802349 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2489 11:46:48.805547 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2490 11:46:48.808718 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2491 11:46:48.808872
2492 11:46:48.812349 CA PerBit enable=1, Macro0, CA PI delay=33
2493 11:46:48.812425
2494 11:46:48.815598 [CBTSetCACLKResult] CA Dly = 33
2495 11:46:48.815680 CS Dly: 6 (0~37)
2496 11:46:48.818869 ==
2497 11:46:48.818944 Dram Type= 6, Freq= 0, CH_0, rank 1
2498 11:46:48.825203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 11:46:48.825301 ==
2500 11:46:48.828850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 11:46:48.835417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2502 11:46:48.844675 [CA 0] Center 39 (8~70) winsize 63
2503 11:46:48.847565 [CA 1] Center 38 (8~69) winsize 62
2504 11:46:48.851231 [CA 2] Center 35 (5~66) winsize 62
2505 11:46:48.854386 [CA 3] Center 35 (5~66) winsize 62
2506 11:46:48.857502 [CA 4] Center 34 (4~65) winsize 62
2507 11:46:48.860800 [CA 5] Center 33 (3~64) winsize 62
2508 11:46:48.860875
2509 11:46:48.864469 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2510 11:46:48.864563
2511 11:46:48.867663 [CATrainingPosCal] consider 2 rank data
2512 11:46:48.870863 u2DelayCellTimex100 = 270/100 ps
2513 11:46:48.874459 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2514 11:46:48.880787 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2515 11:46:48.884025 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2516 11:46:48.887798 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2517 11:46:48.890892 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2518 11:46:48.894229 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2519 11:46:48.894304
2520 11:46:48.897350 CA PerBit enable=1, Macro0, CA PI delay=33
2521 11:46:48.897425
2522 11:46:48.900899 [CBTSetCACLKResult] CA Dly = 33
2523 11:46:48.901048 CS Dly: 7 (0~39)
2524 11:46:48.904472
2525 11:46:48.907661 ----->DramcWriteLeveling(PI) begin...
2526 11:46:48.907745 ==
2527 11:46:48.910957 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 11:46:48.914175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 11:46:48.914278 ==
2530 11:46:48.917385 Write leveling (Byte 0): 32 => 32
2531 11:46:48.920966 Write leveling (Byte 1): 31 => 31
2532 11:46:48.924336 DramcWriteLeveling(PI) end<-----
2533 11:46:48.924439
2534 11:46:48.924538 ==
2535 11:46:48.927693 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 11:46:48.930799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 11:46:48.930881 ==
2538 11:46:48.933996 [Gating] SW mode calibration
2539 11:46:48.941220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2540 11:46:48.947585 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2541 11:46:48.950812 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2542 11:46:48.954236 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
2543 11:46:48.960966 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 11:46:48.964279 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 11:46:48.967422 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 11:46:48.970762 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 11:46:48.977259 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2548 11:46:48.980862 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2549 11:46:48.984220 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2550 11:46:48.990724 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 11:46:48.994265 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 11:46:48.997478 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 11:46:49.004089 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 11:46:49.007635 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 11:46:49.010844 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2556 11:46:49.017330 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2557 11:46:49.020427 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
2558 11:46:49.023693 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 11:46:49.030556 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 11:46:49.033819 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 11:46:49.037584 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 11:46:49.043946 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 11:46:49.047022 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 11:46:49.050187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2565 11:46:49.056853 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2566 11:46:49.060626 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:46:49.063595 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:46:49.070120 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 11:46:49.073766 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 11:46:49.076907 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 11:46:49.083778 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 11:46:49.086801 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 11:46:49.090413 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 11:46:49.096755 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 11:46:49.100013 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 11:46:49.103687 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 11:46:49.110316 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 11:46:49.113438 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 11:46:49.116611 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 11:46:49.123572 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2581 11:46:49.126881 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2582 11:46:49.130034 Total UI for P1: 0, mck2ui 16
2583 11:46:49.133690 best dqsien dly found for B0: ( 1, 3, 26)
2584 11:46:49.136684 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 11:46:49.140306 Total UI for P1: 0, mck2ui 16
2586 11:46:49.143483 best dqsien dly found for B1: ( 1, 4, 0)
2587 11:46:49.146736 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2588 11:46:49.149890 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2589 11:46:49.149974
2590 11:46:49.153344 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2591 11:46:49.156533 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2592 11:46:49.160152 [Gating] SW calibration Done
2593 11:46:49.160233 ==
2594 11:46:49.163215 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 11:46:49.170191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 11:46:49.170273 ==
2597 11:46:49.170338 RX Vref Scan: 0
2598 11:46:49.170397
2599 11:46:49.173117 RX Vref 0 -> 0, step: 1
2600 11:46:49.173202
2601 11:46:49.176503 RX Delay -40 -> 252, step: 8
2602 11:46:49.179647 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2603 11:46:49.183269 iDelay=200, Bit 1, Center 127 (56 ~ 199) 144
2604 11:46:49.186618 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2605 11:46:49.189767 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2606 11:46:49.196350 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2607 11:46:49.199973 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2608 11:46:49.203248 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2609 11:46:49.206435 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2610 11:46:49.210029 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2611 11:46:49.216714 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2612 11:46:49.219877 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2613 11:46:49.223112 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2614 11:46:49.226307 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2615 11:46:49.229591 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2616 11:46:49.236195 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2617 11:46:49.239890 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2618 11:46:49.239972 ==
2619 11:46:49.243161 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 11:46:49.246387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 11:46:49.246471 ==
2622 11:46:49.249530 DQS Delay:
2623 11:46:49.249614 DQS0 = 0, DQS1 = 0
2624 11:46:49.249678 DQM Delay:
2625 11:46:49.252797 DQM0 = 123, DQM1 = 110
2626 11:46:49.252880 DQ Delay:
2627 11:46:49.256183 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2628 11:46:49.259783 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2629 11:46:49.262963 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2630 11:46:49.269504 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2631 11:46:49.269588
2632 11:46:49.269654
2633 11:46:49.269715 ==
2634 11:46:49.272795 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 11:46:49.276483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 11:46:49.276582 ==
2637 11:46:49.276681
2638 11:46:49.276759
2639 11:46:49.279323 TX Vref Scan disable
2640 11:46:49.279406 == TX Byte 0 ==
2641 11:46:49.286209 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2642 11:46:49.289400 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2643 11:46:49.289486 == TX Byte 1 ==
2644 11:46:49.296264 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2645 11:46:49.299869 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2646 11:46:49.299952 ==
2647 11:46:49.302993 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 11:46:49.306178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 11:46:49.306262 ==
2650 11:46:49.318883 TX Vref=22, minBit 1, minWin=24, winSum=409
2651 11:46:49.322416 TX Vref=24, minBit 0, minWin=25, winSum=415
2652 11:46:49.325306 TX Vref=26, minBit 0, minWin=25, winSum=416
2653 11:46:49.328902 TX Vref=28, minBit 0, minWin=26, winSum=426
2654 11:46:49.332052 TX Vref=30, minBit 7, minWin=25, winSum=425
2655 11:46:49.338760 TX Vref=32, minBit 1, minWin=25, winSum=422
2656 11:46:49.341979 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
2657 11:46:49.342063
2658 11:46:49.345321 Final TX Range 1 Vref 28
2659 11:46:49.345405
2660 11:46:49.345471 ==
2661 11:46:49.348877 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 11:46:49.352179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 11:46:49.352264 ==
2664 11:46:49.355439
2665 11:46:49.355522
2666 11:46:49.355588 TX Vref Scan disable
2667 11:46:49.358631 == TX Byte 0 ==
2668 11:46:49.361920 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2669 11:46:49.368732 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2670 11:46:49.368816 == TX Byte 1 ==
2671 11:46:49.371914 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2672 11:46:49.375106 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2673 11:46:49.378669
2674 11:46:49.378752 [DATLAT]
2675 11:46:49.378819 Freq=1200, CH0 RK0
2676 11:46:49.378902
2677 11:46:49.382086 DATLAT Default: 0xd
2678 11:46:49.382195 0, 0xFFFF, sum = 0
2679 11:46:49.385366 1, 0xFFFF, sum = 0
2680 11:46:49.385451 2, 0xFFFF, sum = 0
2681 11:46:49.388660 3, 0xFFFF, sum = 0
2682 11:46:49.392037 4, 0xFFFF, sum = 0
2683 11:46:49.392126 5, 0xFFFF, sum = 0
2684 11:46:49.395390 6, 0xFFFF, sum = 0
2685 11:46:49.395476 7, 0xFFFF, sum = 0
2686 11:46:49.398556 8, 0xFFFF, sum = 0
2687 11:46:49.398641 9, 0xFFFF, sum = 0
2688 11:46:49.401725 10, 0xFFFF, sum = 0
2689 11:46:49.401810 11, 0xFFFF, sum = 0
2690 11:46:49.405292 12, 0x0, sum = 1
2691 11:46:49.405377 13, 0x0, sum = 2
2692 11:46:49.408444 14, 0x0, sum = 3
2693 11:46:49.408529 15, 0x0, sum = 4
2694 11:46:49.408596 best_step = 13
2695 11:46:49.411610
2696 11:46:49.411693 ==
2697 11:46:49.415171 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 11:46:49.418354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 11:46:49.418438 ==
2700 11:46:49.418505 RX Vref Scan: 1
2701 11:46:49.418567
2702 11:46:49.421884 Set Vref Range= 32 -> 127
2703 11:46:49.421969
2704 11:46:49.424948 RX Vref 32 -> 127, step: 1
2705 11:46:49.425056
2706 11:46:49.428328 RX Delay -13 -> 252, step: 4
2707 11:46:49.428414
2708 11:46:49.431653 Set Vref, RX VrefLevel [Byte0]: 32
2709 11:46:49.434834 [Byte1]: 32
2710 11:46:49.434918
2711 11:46:49.438691 Set Vref, RX VrefLevel [Byte0]: 33
2712 11:46:49.441831 [Byte1]: 33
2713 11:46:49.445017
2714 11:46:49.445101 Set Vref, RX VrefLevel [Byte0]: 34
2715 11:46:49.448189 [Byte1]: 34
2716 11:46:49.452881
2717 11:46:49.452965 Set Vref, RX VrefLevel [Byte0]: 35
2718 11:46:49.456128 [Byte1]: 35
2719 11:46:49.460811
2720 11:46:49.460920 Set Vref, RX VrefLevel [Byte0]: 36
2721 11:46:49.464265 [Byte1]: 36
2722 11:46:49.468854
2723 11:46:49.468938 Set Vref, RX VrefLevel [Byte0]: 37
2724 11:46:49.471988 [Byte1]: 37
2725 11:46:49.476731
2726 11:46:49.479812 Set Vref, RX VrefLevel [Byte0]: 38
2727 11:46:49.479897 [Byte1]: 38
2728 11:46:49.484345
2729 11:46:49.484428 Set Vref, RX VrefLevel [Byte0]: 39
2730 11:46:49.487669 [Byte1]: 39
2731 11:46:49.492478
2732 11:46:49.492562 Set Vref, RX VrefLevel [Byte0]: 40
2733 11:46:49.495415 [Byte1]: 40
2734 11:46:49.500392
2735 11:46:49.500501 Set Vref, RX VrefLevel [Byte0]: 41
2736 11:46:49.503285 [Byte1]: 41
2737 11:46:49.508082
2738 11:46:49.508166 Set Vref, RX VrefLevel [Byte0]: 42
2739 11:46:49.511429 [Byte1]: 42
2740 11:46:49.515999
2741 11:46:49.516083 Set Vref, RX VrefLevel [Byte0]: 43
2742 11:46:49.519235 [Byte1]: 43
2743 11:46:49.523818
2744 11:46:49.523900 Set Vref, RX VrefLevel [Byte0]: 44
2745 11:46:49.527161 [Byte1]: 44
2746 11:46:49.531895
2747 11:46:49.531979 Set Vref, RX VrefLevel [Byte0]: 45
2748 11:46:49.535151 [Byte1]: 45
2749 11:46:49.539788
2750 11:46:49.539871 Set Vref, RX VrefLevel [Byte0]: 46
2751 11:46:49.543011 [Byte1]: 46
2752 11:46:49.547667
2753 11:46:49.547751 Set Vref, RX VrefLevel [Byte0]: 47
2754 11:46:49.550899 [Byte1]: 47
2755 11:46:49.555690
2756 11:46:49.555774 Set Vref, RX VrefLevel [Byte0]: 48
2757 11:46:49.558855 [Byte1]: 48
2758 11:46:49.563500
2759 11:46:49.563585 Set Vref, RX VrefLevel [Byte0]: 49
2760 11:46:49.566643 [Byte1]: 49
2761 11:46:49.571159
2762 11:46:49.571243 Set Vref, RX VrefLevel [Byte0]: 50
2763 11:46:49.574294 [Byte1]: 50
2764 11:46:49.579301
2765 11:46:49.579384 Set Vref, RX VrefLevel [Byte0]: 51
2766 11:46:49.582559 [Byte1]: 51
2767 11:46:49.586834
2768 11:46:49.586918 Set Vref, RX VrefLevel [Byte0]: 52
2769 11:46:49.590369 [Byte1]: 52
2770 11:46:49.594921
2771 11:46:49.595008 Set Vref, RX VrefLevel [Byte0]: 53
2772 11:46:49.598145 [Byte1]: 53
2773 11:46:49.602758
2774 11:46:49.602834 Set Vref, RX VrefLevel [Byte0]: 54
2775 11:46:49.606125 [Byte1]: 54
2776 11:46:49.610689
2777 11:46:49.610798 Set Vref, RX VrefLevel [Byte0]: 55
2778 11:46:49.614067 [Byte1]: 55
2779 11:46:49.618524
2780 11:46:49.618607 Set Vref, RX VrefLevel [Byte0]: 56
2781 11:46:49.621880 [Byte1]: 56
2782 11:46:49.626416
2783 11:46:49.626500 Set Vref, RX VrefLevel [Byte0]: 57
2784 11:46:49.629611 [Byte1]: 57
2785 11:46:49.634352
2786 11:46:49.634461 Set Vref, RX VrefLevel [Byte0]: 58
2787 11:46:49.637708 [Byte1]: 58
2788 11:46:49.642262
2789 11:46:49.642347 Set Vref, RX VrefLevel [Byte0]: 59
2790 11:46:49.645641 [Byte1]: 59
2791 11:46:49.650282
2792 11:46:49.650366 Set Vref, RX VrefLevel [Byte0]: 60
2793 11:46:49.653436 [Byte1]: 60
2794 11:46:49.657761
2795 11:46:49.657845 Set Vref, RX VrefLevel [Byte0]: 61
2796 11:46:49.661456 [Byte1]: 61
2797 11:46:49.665918
2798 11:46:49.666002 Set Vref, RX VrefLevel [Byte0]: 62
2799 11:46:49.669120 [Byte1]: 62
2800 11:46:49.673853
2801 11:46:49.673936 Set Vref, RX VrefLevel [Byte0]: 63
2802 11:46:49.677203 [Byte1]: 63
2803 11:46:49.681872
2804 11:46:49.681956 Set Vref, RX VrefLevel [Byte0]: 64
2805 11:46:49.684835 [Byte1]: 64
2806 11:46:49.689344
2807 11:46:49.689427 Set Vref, RX VrefLevel [Byte0]: 65
2808 11:46:49.692931 [Byte1]: 65
2809 11:46:49.697296
2810 11:46:49.697380 Set Vref, RX VrefLevel [Byte0]: 66
2811 11:46:49.700948 [Byte1]: 66
2812 11:46:49.705111
2813 11:46:49.705194 Set Vref, RX VrefLevel [Byte0]: 67
2814 11:46:49.708630 [Byte1]: 67
2815 11:46:49.713225
2816 11:46:49.713308 Set Vref, RX VrefLevel [Byte0]: 68
2817 11:46:49.716527 [Byte1]: 68
2818 11:46:49.721279
2819 11:46:49.721369 Set Vref, RX VrefLevel [Byte0]: 69
2820 11:46:49.724583 [Byte1]: 69
2821 11:46:49.729045
2822 11:46:49.729129 Set Vref, RX VrefLevel [Byte0]: 70
2823 11:46:49.732103 [Byte1]: 70
2824 11:46:49.736962
2825 11:46:49.737085 Final RX Vref Byte 0 = 58 to rank0
2826 11:46:49.740216 Final RX Vref Byte 1 = 48 to rank0
2827 11:46:49.743453 Final RX Vref Byte 0 = 58 to rank1
2828 11:46:49.746636 Final RX Vref Byte 1 = 48 to rank1==
2829 11:46:49.749871 Dram Type= 6, Freq= 0, CH_0, rank 0
2830 11:46:49.756871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 11:46:49.756957 ==
2832 11:46:49.757069 DQS Delay:
2833 11:46:49.757133 DQS0 = 0, DQS1 = 0
2834 11:46:49.760054 DQM Delay:
2835 11:46:49.760138 DQM0 = 122, DQM1 = 109
2836 11:46:49.763324 DQ Delay:
2837 11:46:49.766918 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2838 11:46:49.770147 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2839 11:46:49.773368 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2840 11:46:49.776488 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =118
2841 11:46:49.776573
2842 11:46:49.776639
2843 11:46:49.786624 [DQSOSCAuto] RK0, (LSB)MR18= 0x906, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2844 11:46:49.786710 CH0 RK0: MR19=404, MR18=906
2845 11:46:49.793540 CH0_RK0: MR19=0x404, MR18=0x906, DQSOSC=406, MR23=63, INC=39, DEC=26
2846 11:46:49.793696
2847 11:46:49.796660 ----->DramcWriteLeveling(PI) begin...
2848 11:46:49.796774 ==
2849 11:46:49.800150 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 11:46:49.803220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 11:46:49.806459 ==
2852 11:46:49.806543 Write leveling (Byte 0): 33 => 33
2853 11:46:49.810078 Write leveling (Byte 1): 31 => 31
2854 11:46:49.813350 DramcWriteLeveling(PI) end<-----
2855 11:46:49.813459
2856 11:46:49.813554 ==
2857 11:46:49.816616 Dram Type= 6, Freq= 0, CH_0, rank 1
2858 11:46:49.823305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 11:46:49.823390 ==
2860 11:46:49.823479 [Gating] SW mode calibration
2861 11:46:49.833125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2862 11:46:49.836372 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2863 11:46:49.842949 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2864 11:46:49.846427 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 11:46:49.849559 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 11:46:49.853247 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 11:46:49.859674 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 11:46:49.863130 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2869 11:46:49.866444 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2870 11:46:49.872926 0 15 28 | B1->B0 | 3131 2d2d | 1 1 | (1 0) (1 0)
2871 11:46:49.876124 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2872 11:46:49.879826 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 11:46:49.886461 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 11:46:49.889669 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 11:46:49.892802 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 11:46:49.899710 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2877 11:46:49.902821 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2878 11:46:49.906349 1 0 28 | B1->B0 | 3232 3c3c | 0 1 | (0 0) (1 1)
2879 11:46:49.913199 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 11:46:49.916356 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 11:46:49.919637 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 11:46:49.926219 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 11:46:49.929475 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 11:46:49.932697 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 11:46:49.939345 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2886 11:46:49.942717 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2887 11:46:49.946024 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:46:49.952840 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:46:49.956101 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:46:49.959242 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:46:49.966104 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 11:46:49.969323 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 11:46:49.972661 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 11:46:49.979161 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 11:46:49.982486 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 11:46:49.985841 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 11:46:49.992255 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 11:46:49.995909 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 11:46:49.999077 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 11:46:50.002691 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 11:46:50.009012 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 11:46:50.012314 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2903 11:46:50.015597 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2904 11:46:50.018900 Total UI for P1: 0, mck2ui 16
2905 11:46:50.022633 best dqsien dly found for B1: ( 1, 3, 28)
2906 11:46:50.029230 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 11:46:50.032269 Total UI for P1: 0, mck2ui 16
2908 11:46:50.035470 best dqsien dly found for B0: ( 1, 3, 30)
2909 11:46:50.038935 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2910 11:46:50.042613 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2911 11:46:50.042723
2912 11:46:50.045492 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2913 11:46:50.048764 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2914 11:46:50.052128 [Gating] SW calibration Done
2915 11:46:50.052213 ==
2916 11:46:50.055502 Dram Type= 6, Freq= 0, CH_0, rank 1
2917 11:46:50.058653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2918 11:46:50.058739 ==
2919 11:46:50.062294 RX Vref Scan: 0
2920 11:46:50.062392
2921 11:46:50.062461 RX Vref 0 -> 0, step: 1
2922 11:46:50.065676
2923 11:46:50.065761 RX Delay -40 -> 252, step: 8
2924 11:46:50.071847 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2925 11:46:50.075514 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2926 11:46:50.078748 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2927 11:46:50.081881 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2928 11:46:50.085176 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2929 11:46:50.091896 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2930 11:46:50.095198 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2931 11:46:50.098890 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2932 11:46:50.102061 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2933 11:46:50.105308 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2934 11:46:50.111976 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2935 11:46:50.115032 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2936 11:46:50.118282 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2937 11:46:50.121552 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2938 11:46:50.125234 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2939 11:46:50.131786 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2940 11:46:50.131866 ==
2941 11:46:50.134897 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 11:46:50.138112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 11:46:50.138201 ==
2944 11:46:50.138268 DQS Delay:
2945 11:46:50.141779 DQS0 = 0, DQS1 = 0
2946 11:46:50.141858 DQM Delay:
2947 11:46:50.144821 DQM0 = 120, DQM1 = 108
2948 11:46:50.144921 DQ Delay:
2949 11:46:50.148358 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2950 11:46:50.151827 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2951 11:46:50.155099 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2952 11:46:50.158077 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2953 11:46:50.158153
2954 11:46:50.158224
2955 11:46:50.161777 ==
2956 11:46:50.164610 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 11:46:50.168308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 11:46:50.168399 ==
2959 11:46:50.168468
2960 11:46:50.168530
2961 11:46:50.171572 TX Vref Scan disable
2962 11:46:50.171646 == TX Byte 0 ==
2963 11:46:50.174766 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2964 11:46:50.181246 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2965 11:46:50.181331 == TX Byte 1 ==
2966 11:46:50.185007 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2967 11:46:50.191489 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2968 11:46:50.191566 ==
2969 11:46:50.194593 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 11:46:50.197839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 11:46:50.197912 ==
2972 11:46:50.210309 TX Vref=22, minBit 1, minWin=24, winSum=411
2973 11:46:50.213493 TX Vref=24, minBit 0, minWin=25, winSum=417
2974 11:46:50.216673 TX Vref=26, minBit 2, minWin=24, winSum=418
2975 11:46:50.220156 TX Vref=28, minBit 1, minWin=25, winSum=419
2976 11:46:50.223433 TX Vref=30, minBit 7, minWin=25, winSum=423
2977 11:46:50.229969 TX Vref=32, minBit 2, minWin=25, winSum=420
2978 11:46:50.233613 [TxChooseVref] Worse bit 7, Min win 25, Win sum 423, Final Vref 30
2979 11:46:50.233714
2980 11:46:50.236763 Final TX Range 1 Vref 30
2981 11:46:50.236873
2982 11:46:50.236963 ==
2983 11:46:50.239943 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 11:46:50.243494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 11:46:50.243597 ==
2986 11:46:50.246652
2987 11:46:50.246755
2988 11:46:50.246854 TX Vref Scan disable
2989 11:46:50.249814 == TX Byte 0 ==
2990 11:46:50.253365 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2991 11:46:50.256486 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2992 11:46:50.259774 == TX Byte 1 ==
2993 11:46:50.263230 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2994 11:46:50.270057 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2995 11:46:50.270139
2996 11:46:50.270206 [DATLAT]
2997 11:46:50.270269 Freq=1200, CH0 RK1
2998 11:46:50.270348
2999 11:46:50.273277 DATLAT Default: 0xd
3000 11:46:50.273361 0, 0xFFFF, sum = 0
3001 11:46:50.276719 1, 0xFFFF, sum = 0
3002 11:46:50.276820 2, 0xFFFF, sum = 0
3003 11:46:50.279906 3, 0xFFFF, sum = 0
3004 11:46:50.283110 4, 0xFFFF, sum = 0
3005 11:46:50.283183 5, 0xFFFF, sum = 0
3006 11:46:50.286310 6, 0xFFFF, sum = 0
3007 11:46:50.286384 7, 0xFFFF, sum = 0
3008 11:46:50.289923 8, 0xFFFF, sum = 0
3009 11:46:50.289997 9, 0xFFFF, sum = 0
3010 11:46:50.293233 10, 0xFFFF, sum = 0
3011 11:46:50.293308 11, 0xFFFF, sum = 0
3012 11:46:50.296451 12, 0x0, sum = 1
3013 11:46:50.296529 13, 0x0, sum = 2
3014 11:46:50.299519 14, 0x0, sum = 3
3015 11:46:50.299601 15, 0x0, sum = 4
3016 11:46:50.303085 best_step = 13
3017 11:46:50.303171
3018 11:46:50.303255 ==
3019 11:46:50.306498 Dram Type= 6, Freq= 0, CH_0, rank 1
3020 11:46:50.309691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3021 11:46:50.309770 ==
3022 11:46:50.309863 RX Vref Scan: 0
3023 11:46:50.309943
3024 11:46:50.312925 RX Vref 0 -> 0, step: 1
3025 11:46:50.313035
3026 11:46:50.316076 RX Delay -21 -> 252, step: 4
3027 11:46:50.319658 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3028 11:46:50.326318 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3029 11:46:50.329682 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3030 11:46:50.332755 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3031 11:46:50.335943 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3032 11:46:50.339184 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3033 11:46:50.346359 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3034 11:46:50.349196 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3035 11:46:50.352886 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3036 11:46:50.356154 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3037 11:46:50.359467 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3038 11:46:50.366067 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3039 11:46:50.369576 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3040 11:46:50.372707 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3041 11:46:50.376106 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3042 11:46:50.379435 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3043 11:46:50.382756 ==
3044 11:46:50.386092 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 11:46:50.389192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 11:46:50.389278 ==
3047 11:46:50.389357 DQS Delay:
3048 11:46:50.392632 DQS0 = 0, DQS1 = 0
3049 11:46:50.392708 DQM Delay:
3050 11:46:50.395815 DQM0 = 119, DQM1 = 107
3051 11:46:50.395907 DQ Delay:
3052 11:46:50.399441 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3053 11:46:50.402489 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3054 11:46:50.406083 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =104
3055 11:46:50.409186 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3056 11:46:50.409263
3057 11:46:50.409337
3058 11:46:50.419083 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3059 11:46:50.419165 CH0 RK1: MR19=403, MR18=CF5
3060 11:46:50.425766 CH0_RK1: MR19=0x403, MR18=0xCF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3061 11:46:50.429297 [RxdqsGatingPostProcess] freq 1200
3062 11:46:50.435837 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3063 11:46:50.439125 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 11:46:50.442305 best DQS1 dly(2T, 0.5T) = (0, 12)
3065 11:46:50.445862 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 11:46:50.448948 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3067 11:46:50.452265 best DQS0 dly(2T, 0.5T) = (0, 11)
3068 11:46:50.452340 best DQS1 dly(2T, 0.5T) = (0, 11)
3069 11:46:50.455957 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3070 11:46:50.459137 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3071 11:46:50.462375 Pre-setting of DQS Precalculation
3072 11:46:50.468945 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3073 11:46:50.469039 ==
3074 11:46:50.472451 Dram Type= 6, Freq= 0, CH_1, rank 0
3075 11:46:50.475861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 11:46:50.475947 ==
3077 11:46:50.482195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 11:46:50.489021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3079 11:46:50.496207 [CA 0] Center 37 (7~68) winsize 62
3080 11:46:50.499520 [CA 1] Center 37 (7~68) winsize 62
3081 11:46:50.502868 [CA 2] Center 35 (5~65) winsize 61
3082 11:46:50.505904 [CA 3] Center 34 (4~65) winsize 62
3083 11:46:50.509486 [CA 4] Center 33 (3~64) winsize 62
3084 11:46:50.512747 [CA 5] Center 33 (3~64) winsize 62
3085 11:46:50.512859
3086 11:46:50.515958 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3087 11:46:50.516035
3088 11:46:50.519648 [CATrainingPosCal] consider 1 rank data
3089 11:46:50.522830 u2DelayCellTimex100 = 270/100 ps
3090 11:46:50.525854 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3091 11:46:50.529285 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 11:46:50.535704 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 11:46:50.539007 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3094 11:46:50.542106 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3095 11:46:50.545777 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3096 11:46:50.545868
3097 11:46:50.548918 CA PerBit enable=1, Macro0, CA PI delay=33
3098 11:46:50.549060
3099 11:46:50.552452 [CBTSetCACLKResult] CA Dly = 33
3100 11:46:50.552558 CS Dly: 5 (0~36)
3101 11:46:50.555417 ==
3102 11:46:50.558749 Dram Type= 6, Freq= 0, CH_1, rank 1
3103 11:46:50.562031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 11:46:50.562138 ==
3105 11:46:50.568555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 11:46:50.571629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 11:46:50.581424 [CA 0] Center 38 (8~68) winsize 61
3108 11:46:50.584827 [CA 1] Center 38 (8~68) winsize 61
3109 11:46:50.588507 [CA 2] Center 35 (5~66) winsize 62
3110 11:46:50.592318 [CA 3] Center 34 (4~65) winsize 62
3111 11:46:50.594903 [CA 4] Center 35 (5~65) winsize 61
3112 11:46:50.598460 [CA 5] Center 34 (4~65) winsize 62
3113 11:46:50.598565
3114 11:46:50.601490 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3115 11:46:50.601595
3116 11:46:50.605072 [CATrainingPosCal] consider 2 rank data
3117 11:46:50.608277 u2DelayCellTimex100 = 270/100 ps
3118 11:46:50.611492 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3119 11:46:50.615172 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3120 11:46:50.621616 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3121 11:46:50.624796 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3122 11:46:50.628177 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3123 11:46:50.631894 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3124 11:46:50.631993
3125 11:46:50.634818 CA PerBit enable=1, Macro0, CA PI delay=34
3126 11:46:50.634923
3127 11:46:50.638280 [CBTSetCACLKResult] CA Dly = 34
3128 11:46:50.638381 CS Dly: 6 (0~38)
3129 11:46:50.638478
3130 11:46:50.641381 ----->DramcWriteLeveling(PI) begin...
3131 11:46:50.644740 ==
3132 11:46:50.648286 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 11:46:50.651600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 11:46:50.651701 ==
3135 11:46:50.654762 Write leveling (Byte 0): 25 => 25
3136 11:46:50.658379 Write leveling (Byte 1): 28 => 28
3137 11:46:50.661336 DramcWriteLeveling(PI) end<-----
3138 11:46:50.661411
3139 11:46:50.661488 ==
3140 11:46:50.665129 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 11:46:50.667903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 11:46:50.668004 ==
3143 11:46:50.671282 [Gating] SW mode calibration
3144 11:46:50.677961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3145 11:46:50.684847 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3146 11:46:50.688014 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 11:46:50.691515 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 11:46:50.697874 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 11:46:50.701227 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 11:46:50.704594 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 11:46:50.711213 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3152 11:46:50.714303 0 15 24 | B1->B0 | 3131 2d2d | 0 0 | (0 1) (1 0)
3153 11:46:50.717933 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3154 11:46:50.721090 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 11:46:50.727685 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 11:46:50.730894 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 11:46:50.734172 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 11:46:50.740836 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 11:46:50.744518 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 11:46:50.747709 1 0 24 | B1->B0 | 3a3a 3f3f | 0 1 | (0 0) (0 0)
3161 11:46:50.754476 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 11:46:50.757826 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 11:46:50.760962 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 11:46:50.767365 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 11:46:50.770925 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 11:46:50.774200 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 11:46:50.780863 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3168 11:46:50.784269 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3169 11:46:50.787676 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3170 11:46:50.793965 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:46:50.797528 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:46:50.800730 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:46:50.807266 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 11:46:50.810618 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 11:46:50.813972 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 11:46:50.820625 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 11:46:50.823835 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 11:46:50.827513 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 11:46:50.834083 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 11:46:50.837229 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 11:46:50.840389 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 11:46:50.847220 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 11:46:50.850487 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3184 11:46:50.853729 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3185 11:46:50.860620 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3186 11:46:50.860705 Total UI for P1: 0, mck2ui 16
3187 11:46:50.863823 best dqsien dly found for B0: ( 1, 3, 22)
3188 11:46:50.870210 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 11:46:50.873500 Total UI for P1: 0, mck2ui 16
3190 11:46:50.876824 best dqsien dly found for B1: ( 1, 3, 26)
3191 11:46:50.880420 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3192 11:46:50.883919 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3193 11:46:50.884004
3194 11:46:50.886977 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3195 11:46:50.890244 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3196 11:46:50.893769 [Gating] SW calibration Done
3197 11:46:50.893868 ==
3198 11:46:50.896861 Dram Type= 6, Freq= 0, CH_1, rank 0
3199 11:46:50.900396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 11:46:50.900481 ==
3201 11:46:50.903593 RX Vref Scan: 0
3202 11:46:50.903677
3203 11:46:50.906767 RX Vref 0 -> 0, step: 1
3204 11:46:50.906851
3205 11:46:50.906917 RX Delay -40 -> 252, step: 8
3206 11:46:50.913658 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3207 11:46:50.916789 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3208 11:46:50.919773 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3209 11:46:50.923216 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3210 11:46:50.926897 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3211 11:46:50.933460 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3212 11:46:50.936637 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3213 11:46:50.939781 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3214 11:46:50.943827 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3215 11:46:50.946513 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3216 11:46:50.953195 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3217 11:46:50.956337 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3218 11:46:50.959685 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3219 11:46:50.963250 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3220 11:46:50.969573 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3221 11:46:50.972920 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3222 11:46:50.973036 ==
3223 11:46:50.976117 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 11:46:50.979762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 11:46:50.979841 ==
3226 11:46:50.979924 DQS Delay:
3227 11:46:50.982852 DQS0 = 0, DQS1 = 0
3228 11:46:50.982938 DQM Delay:
3229 11:46:50.986272 DQM0 = 120, DQM1 = 113
3230 11:46:50.986357 DQ Delay:
3231 11:46:50.989567 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3232 11:46:50.992929 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =123
3233 11:46:50.996133 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
3234 11:46:51.003221 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3235 11:46:51.003302
3236 11:46:51.003393
3237 11:46:51.003488 ==
3238 11:46:51.006245 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:46:51.009480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:46:51.009573 ==
3241 11:46:51.009659
3242 11:46:51.009749
3243 11:46:51.012743 TX Vref Scan disable
3244 11:46:51.012837 == TX Byte 0 ==
3245 11:46:51.019432 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3246 11:46:51.022773 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3247 11:46:51.022867 == TX Byte 1 ==
3248 11:46:51.029680 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3249 11:46:51.032633 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3250 11:46:51.032754 ==
3251 11:46:51.035872 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 11:46:51.039200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 11:46:51.039278 ==
3254 11:46:51.051688 TX Vref=22, minBit 1, minWin=24, winSum=403
3255 11:46:51.055317 TX Vref=24, minBit 3, minWin=25, winSum=409
3256 11:46:51.058544 TX Vref=26, minBit 1, minWin=25, winSum=415
3257 11:46:51.061695 TX Vref=28, minBit 10, minWin=25, winSum=418
3258 11:46:51.065102 TX Vref=30, minBit 10, minWin=25, winSum=424
3259 11:46:51.071626 TX Vref=32, minBit 1, minWin=26, winSum=423
3260 11:46:51.074871 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 32
3261 11:46:51.074967
3262 11:46:51.078563 Final TX Range 1 Vref 32
3263 11:46:51.078641
3264 11:46:51.078723 ==
3265 11:46:51.081889 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 11:46:51.085179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 11:46:51.088399 ==
3268 11:46:51.088480
3269 11:46:51.088564
3270 11:46:51.088664 TX Vref Scan disable
3271 11:46:51.091840 == TX Byte 0 ==
3272 11:46:51.094764 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3273 11:46:51.101667 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3274 11:46:51.101769 == TX Byte 1 ==
3275 11:46:51.105376 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3276 11:46:51.111536 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3277 11:46:51.111629
3278 11:46:51.111715 [DATLAT]
3279 11:46:51.111806 Freq=1200, CH1 RK0
3280 11:46:51.111884
3281 11:46:51.115078 DATLAT Default: 0xd
3282 11:46:51.115171 0, 0xFFFF, sum = 0
3283 11:46:51.118346 1, 0xFFFF, sum = 0
3284 11:46:51.121488 2, 0xFFFF, sum = 0
3285 11:46:51.121577 3, 0xFFFF, sum = 0
3286 11:46:51.124845 4, 0xFFFF, sum = 0
3287 11:46:51.124951 5, 0xFFFF, sum = 0
3288 11:46:51.128031 6, 0xFFFF, sum = 0
3289 11:46:51.128116 7, 0xFFFF, sum = 0
3290 11:46:51.131542 8, 0xFFFF, sum = 0
3291 11:46:51.131631 9, 0xFFFF, sum = 0
3292 11:46:51.134562 10, 0xFFFF, sum = 0
3293 11:46:51.134654 11, 0xFFFF, sum = 0
3294 11:46:51.138234 12, 0x0, sum = 1
3295 11:46:51.138312 13, 0x0, sum = 2
3296 11:46:51.141324 14, 0x0, sum = 3
3297 11:46:51.141419 15, 0x0, sum = 4
3298 11:46:51.144558 best_step = 13
3299 11:46:51.144683
3300 11:46:51.144778 ==
3301 11:46:51.147797 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 11:46:51.151477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 11:46:51.151575 ==
3304 11:46:51.151644 RX Vref Scan: 1
3305 11:46:51.154645
3306 11:46:51.154739 Set Vref Range= 32 -> 127
3307 11:46:51.154808
3308 11:46:51.157895 RX Vref 32 -> 127, step: 1
3309 11:46:51.157989
3310 11:46:51.161433 RX Delay -13 -> 252, step: 4
3311 11:46:51.161507
3312 11:46:51.164603 Set Vref, RX VrefLevel [Byte0]: 32
3313 11:46:51.167822 [Byte1]: 32
3314 11:46:51.167905
3315 11:46:51.171358 Set Vref, RX VrefLevel [Byte0]: 33
3316 11:46:51.174596 [Byte1]: 33
3317 11:46:51.178301
3318 11:46:51.178372 Set Vref, RX VrefLevel [Byte0]: 34
3319 11:46:51.181474 [Byte1]: 34
3320 11:46:51.185993
3321 11:46:51.186061 Set Vref, RX VrefLevel [Byte0]: 35
3322 11:46:51.189563 [Byte1]: 35
3323 11:46:51.193727
3324 11:46:51.193798 Set Vref, RX VrefLevel [Byte0]: 36
3325 11:46:51.197288 [Byte1]: 36
3326 11:46:51.201804
3327 11:46:51.201874 Set Vref, RX VrefLevel [Byte0]: 37
3328 11:46:51.205154 [Byte1]: 37
3329 11:46:51.209677
3330 11:46:51.209746 Set Vref, RX VrefLevel [Byte0]: 38
3331 11:46:51.213263 [Byte1]: 38
3332 11:46:51.217752
3333 11:46:51.217833 Set Vref, RX VrefLevel [Byte0]: 39
3334 11:46:51.221165 [Byte1]: 39
3335 11:46:51.225233
3336 11:46:51.225315 Set Vref, RX VrefLevel [Byte0]: 40
3337 11:46:51.228898 [Byte1]: 40
3338 11:46:51.233245
3339 11:46:51.233327 Set Vref, RX VrefLevel [Byte0]: 41
3340 11:46:51.236631 [Byte1]: 41
3341 11:46:51.241148
3342 11:46:51.241259 Set Vref, RX VrefLevel [Byte0]: 42
3343 11:46:51.244472 [Byte1]: 42
3344 11:46:51.249111
3345 11:46:51.249192 Set Vref, RX VrefLevel [Byte0]: 43
3346 11:46:51.252236 [Byte1]: 43
3347 11:46:51.256836
3348 11:46:51.256945 Set Vref, RX VrefLevel [Byte0]: 44
3349 11:46:51.260288 [Byte1]: 44
3350 11:46:51.264785
3351 11:46:51.267905 Set Vref, RX VrefLevel [Byte0]: 45
3352 11:46:51.271355 [Byte1]: 45
3353 11:46:51.271437
3354 11:46:51.274601 Set Vref, RX VrefLevel [Byte0]: 46
3355 11:46:51.277886 [Byte1]: 46
3356 11:46:51.277967
3357 11:46:51.281570 Set Vref, RX VrefLevel [Byte0]: 47
3358 11:46:51.284725 [Byte1]: 47
3359 11:46:51.288682
3360 11:46:51.288763 Set Vref, RX VrefLevel [Byte0]: 48
3361 11:46:51.291830 [Byte1]: 48
3362 11:46:51.296225
3363 11:46:51.296309 Set Vref, RX VrefLevel [Byte0]: 49
3364 11:46:51.299745 [Byte1]: 49
3365 11:46:51.304246
3366 11:46:51.304352 Set Vref, RX VrefLevel [Byte0]: 50
3367 11:46:51.307667 [Byte1]: 50
3368 11:46:51.312140
3369 11:46:51.312219 Set Vref, RX VrefLevel [Byte0]: 51
3370 11:46:51.315346 [Byte1]: 51
3371 11:46:51.320234
3372 11:46:51.320312 Set Vref, RX VrefLevel [Byte0]: 52
3373 11:46:51.323541 [Byte1]: 52
3374 11:46:51.328104
3375 11:46:51.328279 Set Vref, RX VrefLevel [Byte0]: 53
3376 11:46:51.334523 [Byte1]: 53
3377 11:46:51.334610
3378 11:46:51.337729 Set Vref, RX VrefLevel [Byte0]: 54
3379 11:46:51.340820 [Byte1]: 54
3380 11:46:51.340932
3381 11:46:51.344240 Set Vref, RX VrefLevel [Byte0]: 55
3382 11:46:51.347716 [Byte1]: 55
3383 11:46:51.351531
3384 11:46:51.351628 Set Vref, RX VrefLevel [Byte0]: 56
3385 11:46:51.354990 [Byte1]: 56
3386 11:46:51.359713
3387 11:46:51.359803 Set Vref, RX VrefLevel [Byte0]: 57
3388 11:46:51.362701 [Byte1]: 57
3389 11:46:51.367223
3390 11:46:51.367318 Set Vref, RX VrefLevel [Byte0]: 58
3391 11:46:51.370813 [Byte1]: 58
3392 11:46:51.375278
3393 11:46:51.375390 Set Vref, RX VrefLevel [Byte0]: 59
3394 11:46:51.378573 [Byte1]: 59
3395 11:46:51.383061
3396 11:46:51.383134 Set Vref, RX VrefLevel [Byte0]: 60
3397 11:46:51.386630 [Byte1]: 60
3398 11:46:51.391232
3399 11:46:51.391322 Set Vref, RX VrefLevel [Byte0]: 61
3400 11:46:51.394400 [Byte1]: 61
3401 11:46:51.399072
3402 11:46:51.399181 Set Vref, RX VrefLevel [Byte0]: 62
3403 11:46:51.402252 [Byte1]: 62
3404 11:46:51.406615
3405 11:46:51.406689 Set Vref, RX VrefLevel [Byte0]: 63
3406 11:46:51.410240 [Byte1]: 63
3407 11:46:51.414894
3408 11:46:51.414973 Set Vref, RX VrefLevel [Byte0]: 64
3409 11:46:51.417809 [Byte1]: 64
3410 11:46:51.422567
3411 11:46:51.422646 Set Vref, RX VrefLevel [Byte0]: 65
3412 11:46:51.425787 [Byte1]: 65
3413 11:46:51.430577
3414 11:46:51.430652 Set Vref, RX VrefLevel [Byte0]: 66
3415 11:46:51.433816 [Byte1]: 66
3416 11:46:51.438315
3417 11:46:51.438386 Final RX Vref Byte 0 = 53 to rank0
3418 11:46:51.442026 Final RX Vref Byte 1 = 53 to rank0
3419 11:46:51.444872 Final RX Vref Byte 0 = 53 to rank1
3420 11:46:51.448557 Final RX Vref Byte 1 = 53 to rank1==
3421 11:46:51.451636 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 11:46:51.458474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 11:46:51.458565 ==
3424 11:46:51.458642 DQS Delay:
3425 11:46:51.458709 DQS0 = 0, DQS1 = 0
3426 11:46:51.461481 DQM Delay:
3427 11:46:51.461564 DQM0 = 119, DQM1 = 112
3428 11:46:51.465168 DQ Delay:
3429 11:46:51.468476 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3430 11:46:51.471509 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3431 11:46:51.474909 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3432 11:46:51.478172 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =118
3433 11:46:51.478265
3434 11:46:51.478350
3435 11:46:51.488096 [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3436 11:46:51.488186 CH1 RK0: MR19=404, MR18=115
3437 11:46:51.494931 CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27
3438 11:46:51.495012
3439 11:46:51.498285 ----->DramcWriteLeveling(PI) begin...
3440 11:46:51.498364 ==
3441 11:46:51.501604 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 11:46:51.504699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 11:46:51.508235 ==
3444 11:46:51.508327 Write leveling (Byte 0): 25 => 25
3445 11:46:51.511751 Write leveling (Byte 1): 28 => 28
3446 11:46:51.514976 DramcWriteLeveling(PI) end<-----
3447 11:46:51.515091
3448 11:46:51.515180 ==
3449 11:46:51.518007 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 11:46:51.524835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 11:46:51.524964 ==
3452 11:46:51.525092 [Gating] SW mode calibration
3453 11:46:51.534979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 11:46:51.538201 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 11:46:51.544501 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 11:46:51.547895 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 11:46:51.551607 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 11:46:51.554805 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 11:46:51.561486 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 11:46:51.564865 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3461 11:46:51.567856 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 0)
3462 11:46:51.574558 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (0 0)
3463 11:46:51.577919 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 11:46:51.581519 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 11:46:51.588059 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 11:46:51.591315 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 11:46:51.594548 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 11:46:51.601347 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 11:46:51.604542 1 0 24 | B1->B0 | 3f3f 2e2e | 0 0 | (1 1) (0 0)
3470 11:46:51.607940 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3471 11:46:51.614572 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 11:46:51.617654 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 11:46:51.620932 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 11:46:51.627552 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 11:46:51.630947 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 11:46:51.634188 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 11:46:51.640632 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3478 11:46:51.643877 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3479 11:46:51.647130 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:46:51.653628 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:46:51.657328 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 11:46:51.660514 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 11:46:51.666946 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 11:46:51.670372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 11:46:51.673389 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 11:46:51.680214 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 11:46:51.683378 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 11:46:51.686551 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 11:46:51.693560 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 11:46:51.696811 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 11:46:51.700125 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 11:46:51.706832 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 11:46:51.709988 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3494 11:46:51.713180 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 11:46:51.716758 Total UI for P1: 0, mck2ui 16
3496 11:46:51.719746 best dqsien dly found for B0: ( 1, 3, 24)
3497 11:46:51.722992 Total UI for P1: 0, mck2ui 16
3498 11:46:51.726229 best dqsien dly found for B1: ( 1, 3, 24)
3499 11:46:51.729544 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3500 11:46:51.733083 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3501 11:46:51.736246
3502 11:46:51.739613 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3503 11:46:51.742848 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3504 11:46:51.746121 [Gating] SW calibration Done
3505 11:46:51.746204 ==
3506 11:46:51.749325 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 11:46:51.752912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3508 11:46:51.753034 ==
3509 11:46:51.753102 RX Vref Scan: 0
3510 11:46:51.753163
3511 11:46:51.756557 RX Vref 0 -> 0, step: 1
3512 11:46:51.756641
3513 11:46:51.759758 RX Delay -40 -> 252, step: 8
3514 11:46:51.762937 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3515 11:46:51.766066 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3516 11:46:51.772892 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3517 11:46:51.775945 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3518 11:46:51.779261 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3519 11:46:51.782838 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3520 11:46:51.785768 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3521 11:46:51.792653 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3522 11:46:51.795827 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3523 11:46:51.799080 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3524 11:46:51.802746 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3525 11:46:51.805880 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3526 11:46:51.812609 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3527 11:46:51.815568 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3528 11:46:51.818866 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3529 11:46:51.822421 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3530 11:46:51.822505 ==
3531 11:46:51.825473 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 11:46:51.832178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 11:46:51.832300 ==
3534 11:46:51.832398 DQS Delay:
3535 11:46:51.835756 DQS0 = 0, DQS1 = 0
3536 11:46:51.835840 DQM Delay:
3537 11:46:51.838993 DQM0 = 120, DQM1 = 113
3538 11:46:51.839077 DQ Delay:
3539 11:46:51.842159 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3540 11:46:51.845419 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3541 11:46:51.848713 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3542 11:46:51.851881 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3543 11:46:51.851965
3544 11:46:51.852030
3545 11:46:51.852092 ==
3546 11:46:51.855112 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 11:46:51.861899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 11:46:51.861983 ==
3549 11:46:51.862050
3550 11:46:51.862111
3551 11:46:51.862170 TX Vref Scan disable
3552 11:46:51.865471 == TX Byte 0 ==
3553 11:46:51.868639 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3554 11:46:51.875242 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3555 11:46:51.875326 == TX Byte 1 ==
3556 11:46:51.878170 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3557 11:46:51.884981 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3558 11:46:51.885081 ==
3559 11:46:51.888432 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 11:46:51.891498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 11:46:51.891627 ==
3562 11:46:51.903065 TX Vref=22, minBit 3, minWin=25, winSum=416
3563 11:46:51.906350 TX Vref=24, minBit 1, minWin=25, winSum=418
3564 11:46:51.909834 TX Vref=26, minBit 1, minWin=26, winSum=426
3565 11:46:51.913217 TX Vref=28, minBit 8, minWin=26, winSum=430
3566 11:46:51.916254 TX Vref=30, minBit 9, minWin=26, winSum=432
3567 11:46:51.923117 TX Vref=32, minBit 0, minWin=26, winSum=425
3568 11:46:51.926210 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3569 11:46:51.926294
3570 11:46:51.929355 Final TX Range 1 Vref 30
3571 11:46:51.929439
3572 11:46:51.929505 ==
3573 11:46:51.932945 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 11:46:51.936167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 11:46:51.939416 ==
3576 11:46:51.939500
3577 11:46:51.939567
3578 11:46:51.939627 TX Vref Scan disable
3579 11:46:51.942923 == TX Byte 0 ==
3580 11:46:51.946151 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3581 11:46:51.952564 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3582 11:46:51.952651 == TX Byte 1 ==
3583 11:46:51.956264 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3584 11:46:51.962639 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3585 11:46:51.962723
3586 11:46:51.962790 [DATLAT]
3587 11:46:51.962853 Freq=1200, CH1 RK1
3588 11:46:51.962913
3589 11:46:51.965889 DATLAT Default: 0xd
3590 11:46:51.965972 0, 0xFFFF, sum = 0
3591 11:46:51.969456 1, 0xFFFF, sum = 0
3592 11:46:51.972694 2, 0xFFFF, sum = 0
3593 11:46:51.972797 3, 0xFFFF, sum = 0
3594 11:46:51.975890 4, 0xFFFF, sum = 0
3595 11:46:51.975975 5, 0xFFFF, sum = 0
3596 11:46:51.979481 6, 0xFFFF, sum = 0
3597 11:46:51.979566 7, 0xFFFF, sum = 0
3598 11:46:51.982405 8, 0xFFFF, sum = 0
3599 11:46:51.982490 9, 0xFFFF, sum = 0
3600 11:46:51.985723 10, 0xFFFF, sum = 0
3601 11:46:51.985808 11, 0xFFFF, sum = 0
3602 11:46:51.989043 12, 0x0, sum = 1
3603 11:46:51.989128 13, 0x0, sum = 2
3604 11:46:51.992377 14, 0x0, sum = 3
3605 11:46:51.992583 15, 0x0, sum = 4
3606 11:46:51.995514 best_step = 13
3607 11:46:51.995646
3608 11:46:51.995769 ==
3609 11:46:51.999214 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 11:46:52.002401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 11:46:52.002485 ==
3612 11:46:52.002552 RX Vref Scan: 0
3613 11:46:52.005762
3614 11:46:52.005849 RX Vref 0 -> 0, step: 1
3615 11:46:52.005916
3616 11:46:52.008849 RX Delay -13 -> 252, step: 4
3617 11:46:52.015517 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3618 11:46:52.018727 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3619 11:46:52.021823 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3620 11:46:52.025408 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3621 11:46:52.028637 iDelay=191, Bit 4, Center 120 (59 ~ 182) 124
3622 11:46:52.035359 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3623 11:46:52.038704 iDelay=191, Bit 6, Center 124 (63 ~ 186) 124
3624 11:46:52.041620 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3625 11:46:52.045124 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3626 11:46:52.048278 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3627 11:46:52.055085 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3628 11:46:52.058310 iDelay=191, Bit 11, Center 108 (43 ~ 174) 132
3629 11:46:52.061720 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3630 11:46:52.064850 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3631 11:46:52.071199 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3632 11:46:52.074867 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3633 11:46:52.074970 ==
3634 11:46:52.077949 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 11:46:52.081204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 11:46:52.081276 ==
3637 11:46:52.084815 DQS Delay:
3638 11:46:52.084922 DQS0 = 0, DQS1 = 0
3639 11:46:52.085053 DQM Delay:
3640 11:46:52.087953 DQM0 = 118, DQM1 = 113
3641 11:46:52.088052 DQ Delay:
3642 11:46:52.090979 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3643 11:46:52.094340 DQ4 =120, DQ5 =128, DQ6 =124, DQ7 =116
3644 11:46:52.097801 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3645 11:46:52.104363 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3646 11:46:52.104453
3647 11:46:52.104524
3648 11:46:52.111062 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
3649 11:46:52.114241 CH1 RK1: MR19=403, MR18=4E9
3650 11:46:52.120909 CH1_RK1: MR19=0x403, MR18=0x4E9, DQSOSC=408, MR23=63, INC=39, DEC=26
3651 11:46:52.124136 [RxdqsGatingPostProcess] freq 1200
3652 11:46:52.127265 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3653 11:46:52.130435 best DQS0 dly(2T, 0.5T) = (0, 11)
3654 11:46:52.133632 best DQS1 dly(2T, 0.5T) = (0, 11)
3655 11:46:52.137207 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3656 11:46:52.140363 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3657 11:46:52.143665 best DQS0 dly(2T, 0.5T) = (0, 11)
3658 11:46:52.147354 best DQS1 dly(2T, 0.5T) = (0, 11)
3659 11:46:52.150427 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3660 11:46:52.153791 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3661 11:46:52.157129 Pre-setting of DQS Precalculation
3662 11:46:52.160281 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3663 11:46:52.170354 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3664 11:46:52.177232 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3665 11:46:52.177312
3666 11:46:52.177379
3667 11:46:52.180384 [Calibration Summary] 2400 Mbps
3668 11:46:52.180455 CH 0, Rank 0
3669 11:46:52.183588 SW Impedance : PASS
3670 11:46:52.183660 DUTY Scan : NO K
3671 11:46:52.186790 ZQ Calibration : PASS
3672 11:46:52.189941 Jitter Meter : NO K
3673 11:46:52.190014 CBT Training : PASS
3674 11:46:52.193216 Write leveling : PASS
3675 11:46:52.196802 RX DQS gating : PASS
3676 11:46:52.196902 RX DQ/DQS(RDDQC) : PASS
3677 11:46:52.200165 TX DQ/DQS : PASS
3678 11:46:52.203044 RX DATLAT : PASS
3679 11:46:52.203147 RX DQ/DQS(Engine): PASS
3680 11:46:52.206726 TX OE : NO K
3681 11:46:52.206825 All Pass.
3682 11:46:52.206925
3683 11:46:52.209605 CH 0, Rank 1
3684 11:46:52.209684 SW Impedance : PASS
3685 11:46:52.213254 DUTY Scan : NO K
3686 11:46:52.216577 ZQ Calibration : PASS
3687 11:46:52.216650 Jitter Meter : NO K
3688 11:46:52.219634 CBT Training : PASS
3689 11:46:52.222809 Write leveling : PASS
3690 11:46:52.222894 RX DQS gating : PASS
3691 11:46:52.226419 RX DQ/DQS(RDDQC) : PASS
3692 11:46:52.229694 TX DQ/DQS : PASS
3693 11:46:52.229810 RX DATLAT : PASS
3694 11:46:52.232835 RX DQ/DQS(Engine): PASS
3695 11:46:52.236162 TX OE : NO K
3696 11:46:52.236234 All Pass.
3697 11:46:52.236304
3698 11:46:52.236365 CH 1, Rank 0
3699 11:46:52.239808 SW Impedance : PASS
3700 11:46:52.242941 DUTY Scan : NO K
3701 11:46:52.243019 ZQ Calibration : PASS
3702 11:46:52.246239 Jitter Meter : NO K
3703 11:46:52.249501 CBT Training : PASS
3704 11:46:52.249576 Write leveling : PASS
3705 11:46:52.252768 RX DQS gating : PASS
3706 11:46:52.252867 RX DQ/DQS(RDDQC) : PASS
3707 11:46:52.256131 TX DQ/DQS : PASS
3708 11:46:52.259243 RX DATLAT : PASS
3709 11:46:52.259315 RX DQ/DQS(Engine): PASS
3710 11:46:52.262599 TX OE : NO K
3711 11:46:52.262678 All Pass.
3712 11:46:52.262741
3713 11:46:52.265829 CH 1, Rank 1
3714 11:46:52.265911 SW Impedance : PASS
3715 11:46:52.269301 DUTY Scan : NO K
3716 11:46:52.272420 ZQ Calibration : PASS
3717 11:46:52.272521 Jitter Meter : NO K
3718 11:46:52.275929 CBT Training : PASS
3719 11:46:52.278951 Write leveling : PASS
3720 11:46:52.279094 RX DQS gating : PASS
3721 11:46:52.282314 RX DQ/DQS(RDDQC) : PASS
3722 11:46:52.285655 TX DQ/DQS : PASS
3723 11:46:52.285731 RX DATLAT : PASS
3724 11:46:52.289249 RX DQ/DQS(Engine): PASS
3725 11:46:52.292476 TX OE : NO K
3726 11:46:52.292569 All Pass.
3727 11:46:52.292662
3728 11:46:52.292751 DramC Write-DBI off
3729 11:46:52.295647 PER_BANK_REFRESH: Hybrid Mode
3730 11:46:52.298977 TX_TRACKING: ON
3731 11:46:52.305856 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3732 11:46:52.312270 [FAST_K] Save calibration result to emmc
3733 11:46:52.315281 dramc_set_vcore_voltage set vcore to 650000
3734 11:46:52.315357 Read voltage for 600, 5
3735 11:46:52.318649 Vio18 = 0
3736 11:46:52.318768 Vcore = 650000
3737 11:46:52.318840 Vdram = 0
3738 11:46:52.322089 Vddq = 0
3739 11:46:52.322166 Vmddr = 0
3740 11:46:52.325080 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3741 11:46:52.331886 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3742 11:46:52.335177 MEM_TYPE=3, freq_sel=19
3743 11:46:52.338744 sv_algorithm_assistance_LP4_1600
3744 11:46:52.342015 ============ PULL DRAM RESETB DOWN ============
3745 11:46:52.344953 ========== PULL DRAM RESETB DOWN end =========
3746 11:46:52.351771 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3747 11:46:52.355040 ===================================
3748 11:46:52.355116 LPDDR4 DRAM CONFIGURATION
3749 11:46:52.358088 ===================================
3750 11:46:52.361628 EX_ROW_EN[0] = 0x0
3751 11:46:52.361733 EX_ROW_EN[1] = 0x0
3752 11:46:52.365124 LP4Y_EN = 0x0
3753 11:46:52.368329 WORK_FSP = 0x0
3754 11:46:52.368436 WL = 0x2
3755 11:46:52.371596 RL = 0x2
3756 11:46:52.371683 BL = 0x2
3757 11:46:52.374764 RPST = 0x0
3758 11:46:52.374853 RD_PRE = 0x0
3759 11:46:52.378309 WR_PRE = 0x1
3760 11:46:52.378417 WR_PST = 0x0
3761 11:46:52.381331 DBI_WR = 0x0
3762 11:46:52.381438 DBI_RD = 0x0
3763 11:46:52.384602 OTF = 0x1
3764 11:46:52.388308 ===================================
3765 11:46:52.391507 ===================================
3766 11:46:52.391584 ANA top config
3767 11:46:52.394736 ===================================
3768 11:46:52.398123 DLL_ASYNC_EN = 0
3769 11:46:52.401323 ALL_SLAVE_EN = 1
3770 11:46:52.401417 NEW_RANK_MODE = 1
3771 11:46:52.404629 DLL_IDLE_MODE = 1
3772 11:46:52.407803 LP45_APHY_COMB_EN = 1
3773 11:46:52.411168 TX_ODT_DIS = 1
3774 11:46:52.414368 NEW_8X_MODE = 1
3775 11:46:52.417857 ===================================
3776 11:46:52.420857 ===================================
3777 11:46:52.420961 data_rate = 1200
3778 11:46:52.424301 CKR = 1
3779 11:46:52.427656 DQ_P2S_RATIO = 8
3780 11:46:52.430998 ===================================
3781 11:46:52.434202 CA_P2S_RATIO = 8
3782 11:46:52.437852 DQ_CA_OPEN = 0
3783 11:46:52.440700 DQ_SEMI_OPEN = 0
3784 11:46:52.440800 CA_SEMI_OPEN = 0
3785 11:46:52.444353 CA_FULL_RATE = 0
3786 11:46:52.447584 DQ_CKDIV4_EN = 1
3787 11:46:52.450926 CA_CKDIV4_EN = 1
3788 11:46:52.454285 CA_PREDIV_EN = 0
3789 11:46:52.457410 PH8_DLY = 0
3790 11:46:52.460585 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3791 11:46:52.460660 DQ_AAMCK_DIV = 4
3792 11:46:52.464276 CA_AAMCK_DIV = 4
3793 11:46:52.467423 CA_ADMCK_DIV = 4
3794 11:46:52.470565 DQ_TRACK_CA_EN = 0
3795 11:46:52.474180 CA_PICK = 600
3796 11:46:52.476987 CA_MCKIO = 600
3797 11:46:52.477080 MCKIO_SEMI = 0
3798 11:46:52.480319 PLL_FREQ = 2288
3799 11:46:52.483974 DQ_UI_PI_RATIO = 32
3800 11:46:52.487003 CA_UI_PI_RATIO = 0
3801 11:46:52.490236 ===================================
3802 11:46:52.493541 ===================================
3803 11:46:52.496876 memory_type:LPDDR4
3804 11:46:52.496985 GP_NUM : 10
3805 11:46:52.500142 SRAM_EN : 1
3806 11:46:52.503885 MD32_EN : 0
3807 11:46:52.506743 ===================================
3808 11:46:52.506817 [ANA_INIT] >>>>>>>>>>>>>>
3809 11:46:52.509900 <<<<<< [CONFIGURE PHASE]: ANA_TX
3810 11:46:52.513492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3811 11:46:52.516905 ===================================
3812 11:46:52.520084 data_rate = 1200,PCW = 0X5800
3813 11:46:52.523186 ===================================
3814 11:46:52.526683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3815 11:46:52.533065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 11:46:52.536416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 11:46:52.542971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3818 11:46:52.546654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3819 11:46:52.549930 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3820 11:46:52.552888 [ANA_INIT] flow start
3821 11:46:52.553031 [ANA_INIT] PLL >>>>>>>>
3822 11:46:52.556260 [ANA_INIT] PLL <<<<<<<<
3823 11:46:52.559908 [ANA_INIT] MIDPI >>>>>>>>
3824 11:46:52.559991 [ANA_INIT] MIDPI <<<<<<<<
3825 11:46:52.563170 [ANA_INIT] DLL >>>>>>>>
3826 11:46:52.566343 [ANA_INIT] flow end
3827 11:46:52.569397 ============ LP4 DIFF to SE enter ============
3828 11:46:52.572965 ============ LP4 DIFF to SE exit ============
3829 11:46:52.576131 [ANA_INIT] <<<<<<<<<<<<<
3830 11:46:52.579815 [Flow] Enable top DCM control >>>>>
3831 11:46:52.582972 [Flow] Enable top DCM control <<<<<
3832 11:46:52.586246 Enable DLL master slave shuffle
3833 11:46:52.589358 ==============================================================
3834 11:46:52.592561 Gating Mode config
3835 11:46:52.599442 ==============================================================
3836 11:46:52.599526 Config description:
3837 11:46:52.609006 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3838 11:46:52.615881 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3839 11:46:52.622504 SELPH_MODE 0: By rank 1: By Phase
3840 11:46:52.625729 ==============================================================
3841 11:46:52.628839 GAT_TRACK_EN = 1
3842 11:46:52.632299 RX_GATING_MODE = 2
3843 11:46:52.635409 RX_GATING_TRACK_MODE = 2
3844 11:46:52.638807 SELPH_MODE = 1
3845 11:46:52.642073 PICG_EARLY_EN = 1
3846 11:46:52.645827 VALID_LAT_VALUE = 1
3847 11:46:52.648891 ==============================================================
3848 11:46:52.652155 Enter into Gating configuration >>>>
3849 11:46:52.655298 Exit from Gating configuration <<<<
3850 11:46:52.658966 Enter into DVFS_PRE_config >>>>>
3851 11:46:52.672273 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3852 11:46:52.675371 Exit from DVFS_PRE_config <<<<<
3853 11:46:52.678790 Enter into PICG configuration >>>>
3854 11:46:52.681980 Exit from PICG configuration <<<<
3855 11:46:52.682090 [RX_INPUT] configuration >>>>>
3856 11:46:52.685198 [RX_INPUT] configuration <<<<<
3857 11:46:52.691889 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3858 11:46:52.694981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3859 11:46:52.701810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3860 11:46:52.708206 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3861 11:46:52.714807 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 11:46:52.721406 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 11:46:52.724906 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3864 11:46:52.728133 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3865 11:46:52.734471 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3866 11:46:52.738116 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3867 11:46:52.741312 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3868 11:46:52.744858 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 11:46:52.747780 ===================================
3870 11:46:52.751274 LPDDR4 DRAM CONFIGURATION
3871 11:46:52.754437 ===================================
3872 11:46:52.757742 EX_ROW_EN[0] = 0x0
3873 11:46:52.757847 EX_ROW_EN[1] = 0x0
3874 11:46:52.761185 LP4Y_EN = 0x0
3875 11:46:52.761261 WORK_FSP = 0x0
3876 11:46:52.764454 WL = 0x2
3877 11:46:52.764556 RL = 0x2
3878 11:46:52.767607 BL = 0x2
3879 11:46:52.767712 RPST = 0x0
3880 11:46:52.770871 RD_PRE = 0x0
3881 11:46:52.774449 WR_PRE = 0x1
3882 11:46:52.774550 WR_PST = 0x0
3883 11:46:52.777858 DBI_WR = 0x0
3884 11:46:52.777957 DBI_RD = 0x0
3885 11:46:52.781121 OTF = 0x1
3886 11:46:52.784390 ===================================
3887 11:46:52.787685 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3888 11:46:52.790834 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3889 11:46:52.794093 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3890 11:46:52.797578 ===================================
3891 11:46:52.800800 LPDDR4 DRAM CONFIGURATION
3892 11:46:52.803946 ===================================
3893 11:46:52.807456 EX_ROW_EN[0] = 0x10
3894 11:46:52.807561 EX_ROW_EN[1] = 0x0
3895 11:46:52.810579 LP4Y_EN = 0x0
3896 11:46:52.810694 WORK_FSP = 0x0
3897 11:46:52.814238 WL = 0x2
3898 11:46:52.814335 RL = 0x2
3899 11:46:52.817548 BL = 0x2
3900 11:46:52.817631 RPST = 0x0
3901 11:46:52.820840 RD_PRE = 0x0
3902 11:46:52.824127 WR_PRE = 0x1
3903 11:46:52.824209 WR_PST = 0x0
3904 11:46:52.827182 DBI_WR = 0x0
3905 11:46:52.827266 DBI_RD = 0x0
3906 11:46:52.830727 OTF = 0x1
3907 11:46:52.833975 ===================================
3908 11:46:52.837108 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3909 11:46:52.842467 nWR fixed to 30
3910 11:46:52.845889 [ModeRegInit_LP4] CH0 RK0
3911 11:46:52.845973 [ModeRegInit_LP4] CH0 RK1
3912 11:46:52.848909 [ModeRegInit_LP4] CH1 RK0
3913 11:46:52.852311 [ModeRegInit_LP4] CH1 RK1
3914 11:46:52.852394 match AC timing 17
3915 11:46:52.858934 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3916 11:46:52.862234 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3917 11:46:52.865822 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3918 11:46:52.872318 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3919 11:46:52.875710 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3920 11:46:52.875794 ==
3921 11:46:52.878911 Dram Type= 6, Freq= 0, CH_0, rank 0
3922 11:46:52.882324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 11:46:52.882409 ==
3924 11:46:52.888539 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 11:46:52.895370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 11:46:52.898496 [CA 0] Center 35 (5~66) winsize 62
3927 11:46:52.902098 [CA 1] Center 36 (6~67) winsize 62
3928 11:46:52.905219 [CA 2] Center 34 (4~65) winsize 62
3929 11:46:52.908446 [CA 3] Center 34 (3~65) winsize 63
3930 11:46:52.911660 [CA 4] Center 33 (3~64) winsize 62
3931 11:46:52.915213 [CA 5] Center 33 (3~64) winsize 62
3932 11:46:52.915294
3933 11:46:52.918429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 11:46:52.918503
3935 11:46:52.921705 [CATrainingPosCal] consider 1 rank data
3936 11:46:52.924869 u2DelayCellTimex100 = 270/100 ps
3937 11:46:52.928394 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3938 11:46:52.931842 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3939 11:46:52.935031 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3940 11:46:52.938288 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3941 11:46:52.944785 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3942 11:46:52.948429 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3943 11:46:52.948504
3944 11:46:52.951758 CA PerBit enable=1, Macro0, CA PI delay=33
3945 11:46:52.951843
3946 11:46:52.954797 [CBTSetCACLKResult] CA Dly = 33
3947 11:46:52.954949 CS Dly: 5 (0~36)
3948 11:46:52.955059 ==
3949 11:46:52.958173 Dram Type= 6, Freq= 0, CH_0, rank 1
3950 11:46:52.964405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 11:46:52.964484 ==
3952 11:46:52.967915 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 11:46:52.974650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3954 11:46:52.977793 [CA 0] Center 36 (6~67) winsize 62
3955 11:46:52.981051 [CA 1] Center 37 (7~67) winsize 61
3956 11:46:52.984585 [CA 2] Center 35 (4~66) winsize 63
3957 11:46:52.987725 [CA 3] Center 34 (4~65) winsize 62
3958 11:46:52.990902 [CA 4] Center 34 (4~65) winsize 62
3959 11:46:52.994603 [CA 5] Center 33 (3~64) winsize 62
3960 11:46:52.994675
3961 11:46:52.997789 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3962 11:46:52.997861
3963 11:46:53.001206 [CATrainingPosCal] consider 2 rank data
3964 11:46:53.004230 u2DelayCellTimex100 = 270/100 ps
3965 11:46:53.007867 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3966 11:46:53.014380 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3967 11:46:53.017578 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3968 11:46:53.020770 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 11:46:53.024442 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3970 11:46:53.027577 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 11:46:53.027650
3972 11:46:53.030901 CA PerBit enable=1, Macro0, CA PI delay=33
3973 11:46:53.030979
3974 11:46:53.033971 [CBTSetCACLKResult] CA Dly = 33
3975 11:46:53.034042 CS Dly: 6 (0~38)
3976 11:46:53.037566
3977 11:46:53.040717 ----->DramcWriteLeveling(PI) begin...
3978 11:46:53.040789 ==
3979 11:46:53.044315 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 11:46:53.047499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 11:46:53.047576 ==
3982 11:46:53.050671 Write leveling (Byte 0): 35 => 35
3983 11:46:53.054171 Write leveling (Byte 1): 30 => 30
3984 11:46:53.057456 DramcWriteLeveling(PI) end<-----
3985 11:46:53.057529
3986 11:46:53.057591 ==
3987 11:46:53.060779 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 11:46:53.063846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 11:46:53.063920 ==
3990 11:46:53.067414 [Gating] SW mode calibration
3991 11:46:53.073990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3992 11:46:53.080155 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3993 11:46:53.083765 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 11:46:53.086883 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 11:46:53.093823 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3996 11:46:53.097137 0 9 12 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 1)
3997 11:46:53.100265 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3998 11:46:53.107189 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 11:46:53.110432 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 11:46:53.113767 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 11:46:53.120327 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 11:46:53.123655 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 11:46:53.126860 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 11:46:53.133326 0 10 12 | B1->B0 | 2b2b 3939 | 0 0 | (0 0) (1 1)
4005 11:46:53.137139 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4006 11:46:53.140050 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 11:46:53.146879 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 11:46:53.149942 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 11:46:53.153228 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 11:46:53.159895 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 11:46:53.163467 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 11:46:53.166497 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4013 11:46:53.172955 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4014 11:46:53.176289 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:46:53.179722 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:46:53.186303 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:46:53.189491 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:46:53.193043 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:46:53.199708 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 11:46:53.202952 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 11:46:53.206227 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 11:46:53.212617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 11:46:53.216080 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 11:46:53.219243 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 11:46:53.222592 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 11:46:53.229623 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 11:46:53.232762 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 11:46:53.235929 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4029 11:46:53.242839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4030 11:46:53.246052 Total UI for P1: 0, mck2ui 16
4031 11:46:53.249178 best dqsien dly found for B0: ( 0, 13, 12)
4032 11:46:53.252749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 11:46:53.255956 Total UI for P1: 0, mck2ui 16
4034 11:46:53.259079 best dqsien dly found for B1: ( 0, 13, 16)
4035 11:46:53.262328 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4036 11:46:53.265734 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4037 11:46:53.265825
4038 11:46:53.268807 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4039 11:46:53.275736 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4040 11:46:53.275856 [Gating] SW calibration Done
4041 11:46:53.275969 ==
4042 11:46:53.278994 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 11:46:53.285339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 11:46:53.285426 ==
4045 11:46:53.285510 RX Vref Scan: 0
4046 11:46:53.285597
4047 11:46:53.288793 RX Vref 0 -> 0, step: 1
4048 11:46:53.288868
4049 11:46:53.291948 RX Delay -230 -> 252, step: 16
4050 11:46:53.295186 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4051 11:46:53.298562 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4052 11:46:53.305033 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4053 11:46:53.308373 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4054 11:46:53.311782 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4055 11:46:53.315238 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4056 11:46:53.318334 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4057 11:46:53.325084 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4058 11:46:53.328362 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4059 11:46:53.331677 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4060 11:46:53.334833 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4061 11:46:53.341362 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4062 11:46:53.344661 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4063 11:46:53.347988 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4064 11:46:53.351182 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4065 11:46:53.358108 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4066 11:46:53.358186 ==
4067 11:46:53.361178 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 11:46:53.364299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 11:46:53.364376 ==
4070 11:46:53.364465 DQS Delay:
4071 11:46:53.368040 DQS0 = 0, DQS1 = 0
4072 11:46:53.368141 DQM Delay:
4073 11:46:53.371351 DQM0 = 48, DQM1 = 40
4074 11:46:53.371436 DQ Delay:
4075 11:46:53.374576 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4076 11:46:53.377593 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4077 11:46:53.381041 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4078 11:46:53.384367 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =41
4079 11:46:53.384451
4080 11:46:53.384516
4081 11:46:53.384577 ==
4082 11:46:53.387702 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 11:46:53.391136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 11:46:53.394116 ==
4085 11:46:53.394199
4086 11:46:53.394264
4087 11:46:53.394325 TX Vref Scan disable
4088 11:46:53.397566 == TX Byte 0 ==
4089 11:46:53.400732 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4090 11:46:53.407477 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4091 11:46:53.407559 == TX Byte 1 ==
4092 11:46:53.410727 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4093 11:46:53.417655 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4094 11:46:53.417738 ==
4095 11:46:53.420857 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 11:46:53.423948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 11:46:53.424032 ==
4098 11:46:53.424097
4099 11:46:53.424157
4100 11:46:53.427149 TX Vref Scan disable
4101 11:46:53.430705 == TX Byte 0 ==
4102 11:46:53.433827 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4103 11:46:53.437498 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4104 11:46:53.440778 == TX Byte 1 ==
4105 11:46:53.443951 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4106 11:46:53.447103 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4107 11:46:53.447187
4108 11:46:53.447253 [DATLAT]
4109 11:46:53.450688 Freq=600, CH0 RK0
4110 11:46:53.450771
4111 11:46:53.453734 DATLAT Default: 0x9
4112 11:46:53.453842 0, 0xFFFF, sum = 0
4113 11:46:53.457400 1, 0xFFFF, sum = 0
4114 11:46:53.457485 2, 0xFFFF, sum = 0
4115 11:46:53.460672 3, 0xFFFF, sum = 0
4116 11:46:53.460756 4, 0xFFFF, sum = 0
4117 11:46:53.463942 5, 0xFFFF, sum = 0
4118 11:46:53.464025 6, 0xFFFF, sum = 0
4119 11:46:53.467004 7, 0xFFFF, sum = 0
4120 11:46:53.467088 8, 0x0, sum = 1
4121 11:46:53.470569 9, 0x0, sum = 2
4122 11:46:53.470654 10, 0x0, sum = 3
4123 11:46:53.473679 11, 0x0, sum = 4
4124 11:46:53.473764 best_step = 9
4125 11:46:53.473829
4126 11:46:53.473891 ==
4127 11:46:53.476971 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 11:46:53.480497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 11:46:53.480581 ==
4130 11:46:53.483525 RX Vref Scan: 1
4131 11:46:53.483615
4132 11:46:53.486979 RX Vref 0 -> 0, step: 1
4133 11:46:53.487062
4134 11:46:53.487128 RX Delay -179 -> 252, step: 8
4135 11:46:53.487189
4136 11:46:53.489970 Set Vref, RX VrefLevel [Byte0]: 58
4137 11:46:53.493697 [Byte1]: 48
4138 11:46:53.498041
4139 11:46:53.498126 Final RX Vref Byte 0 = 58 to rank0
4140 11:46:53.501521 Final RX Vref Byte 1 = 48 to rank0
4141 11:46:53.504490 Final RX Vref Byte 0 = 58 to rank1
4142 11:46:53.508131 Final RX Vref Byte 1 = 48 to rank1==
4143 11:46:53.511272 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 11:46:53.518250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 11:46:53.518331 ==
4146 11:46:53.518397 DQS Delay:
4147 11:46:53.518459 DQS0 = 0, DQS1 = 0
4148 11:46:53.521504 DQM Delay:
4149 11:46:53.521588 DQM0 = 48, DQM1 = 39
4150 11:46:53.524660 DQ Delay:
4151 11:46:53.528129 DQ0 =44, DQ1 =44, DQ2 =44, DQ3 =44
4152 11:46:53.531404 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4153 11:46:53.534678 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4154 11:46:53.537886 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4155 11:46:53.537960
4156 11:46:53.538023
4157 11:46:53.544413 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f59, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
4158 11:46:53.547705 CH0 RK0: MR19=808, MR18=5F59
4159 11:46:53.554347 CH0_RK0: MR19=0x808, MR18=0x5F59, DQSOSC=391, MR23=63, INC=171, DEC=114
4160 11:46:53.554431
4161 11:46:53.557672 ----->DramcWriteLeveling(PI) begin...
4162 11:46:53.557756 ==
4163 11:46:53.560813 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 11:46:53.564087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 11:46:53.564171 ==
4166 11:46:53.567404 Write leveling (Byte 0): 35 => 35
4167 11:46:53.570849 Write leveling (Byte 1): 29 => 29
4168 11:46:53.574202 DramcWriteLeveling(PI) end<-----
4169 11:46:53.574299
4170 11:46:53.574370 ==
4171 11:46:53.577321 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 11:46:53.580559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 11:46:53.580632 ==
4174 11:46:53.583881 [Gating] SW mode calibration
4175 11:46:53.590488 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4176 11:46:53.596958 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4177 11:46:53.600733 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 11:46:53.607262 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 11:46:53.610293 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 11:46:53.613965 0 9 12 | B1->B0 | 3131 3131 | 1 1 | (1 0) (1 1)
4181 11:46:53.620561 0 9 16 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
4182 11:46:53.623773 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 11:46:53.627041 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 11:46:53.633668 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 11:46:53.636949 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 11:46:53.640639 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 11:46:53.647002 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 11:46:53.650267 0 10 12 | B1->B0 | 2c2c 2d2d | 0 0 | (0 0) (0 0)
4189 11:46:53.653598 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 11:46:53.660381 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 11:46:53.663654 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 11:46:53.666901 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 11:46:53.673360 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 11:46:53.676744 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 11:46:53.679914 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 11:46:53.686419 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4197 11:46:53.689733 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:46:53.693229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:46:53.699599 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:46:53.702982 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:46:53.706110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 11:46:53.712697 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 11:46:53.716057 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 11:46:53.719563 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 11:46:53.725970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 11:46:53.729216 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 11:46:53.732343 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 11:46:53.739083 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 11:46:53.742476 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 11:46:53.745619 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 11:46:53.752439 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4212 11:46:53.755643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 11:46:53.758846 Total UI for P1: 0, mck2ui 16
4214 11:46:53.761984 best dqsien dly found for B0: ( 0, 13, 8)
4215 11:46:53.765500 Total UI for P1: 0, mck2ui 16
4216 11:46:53.768615 best dqsien dly found for B1: ( 0, 13, 10)
4217 11:46:53.771902 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4218 11:46:53.775148 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4219 11:46:53.775221
4220 11:46:53.778928 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4221 11:46:53.782112 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4222 11:46:53.785350 [Gating] SW calibration Done
4223 11:46:53.785433 ==
4224 11:46:53.788542 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 11:46:53.791744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 11:46:53.795002 ==
4227 11:46:53.795082 RX Vref Scan: 0
4228 11:46:53.795147
4229 11:46:53.798717 RX Vref 0 -> 0, step: 1
4230 11:46:53.798801
4231 11:46:53.801850 RX Delay -230 -> 252, step: 16
4232 11:46:53.804832 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4233 11:46:53.808069 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4234 11:46:53.811411 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4235 11:46:53.818412 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4236 11:46:53.821843 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4237 11:46:53.824828 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4238 11:46:53.828323 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4239 11:46:53.831308 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4240 11:46:53.838215 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4241 11:46:53.841231 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4242 11:46:53.844662 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4243 11:46:53.847830 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4244 11:46:53.854553 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4245 11:46:53.857803 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4246 11:46:53.861097 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4247 11:46:53.867488 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4248 11:46:53.867595 ==
4249 11:46:53.870957 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 11:46:53.874222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 11:46:53.874327 ==
4252 11:46:53.874435 DQS Delay:
4253 11:46:53.877589 DQS0 = 0, DQS1 = 0
4254 11:46:53.877695 DQM Delay:
4255 11:46:53.880732 DQM0 = 46, DQM1 = 42
4256 11:46:53.880834 DQ Delay:
4257 11:46:53.884070 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4258 11:46:53.887240 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4259 11:46:53.890469 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4260 11:46:53.894095 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4261 11:46:53.894202
4262 11:46:53.894303
4263 11:46:53.894405 ==
4264 11:46:53.897341 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 11:46:53.900601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 11:46:53.900703 ==
4267 11:46:53.900802
4268 11:46:53.903922
4269 11:46:53.904028 TX Vref Scan disable
4270 11:46:53.906959 == TX Byte 0 ==
4271 11:46:53.910484 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4272 11:46:53.913999 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4273 11:46:53.917256 == TX Byte 1 ==
4274 11:46:53.920321 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4275 11:46:53.923738 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4276 11:46:53.923843 ==
4277 11:46:53.927072 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 11:46:53.933690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 11:46:53.933775 ==
4280 11:46:53.933859
4281 11:46:53.933938
4282 11:46:53.936881 TX Vref Scan disable
4283 11:46:53.936987 == TX Byte 0 ==
4284 11:46:53.943564 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4285 11:46:53.946844 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4286 11:46:53.946950 == TX Byte 1 ==
4287 11:46:53.953327 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4288 11:46:53.956656 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4289 11:46:53.956763
4290 11:46:53.956866 [DATLAT]
4291 11:46:53.959942 Freq=600, CH0 RK1
4292 11:46:53.960046
4293 11:46:53.960128 DATLAT Default: 0x9
4294 11:46:53.962968 0, 0xFFFF, sum = 0
4295 11:46:53.963075 1, 0xFFFF, sum = 0
4296 11:46:53.966362 2, 0xFFFF, sum = 0
4297 11:46:53.970171 3, 0xFFFF, sum = 0
4298 11:46:53.970257 4, 0xFFFF, sum = 0
4299 11:46:53.973139 5, 0xFFFF, sum = 0
4300 11:46:53.973249 6, 0xFFFF, sum = 0
4301 11:46:53.976614 7, 0xFFFF, sum = 0
4302 11:46:53.976724 8, 0x0, sum = 1
4303 11:46:53.976820 9, 0x0, sum = 2
4304 11:46:53.979923 10, 0x0, sum = 3
4305 11:46:53.980032 11, 0x0, sum = 4
4306 11:46:53.983078 best_step = 9
4307 11:46:53.983182
4308 11:46:53.983272 ==
4309 11:46:53.986616 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 11:46:53.989749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 11:46:53.989824 ==
4312 11:46:53.992873 RX Vref Scan: 0
4313 11:46:53.992971
4314 11:46:53.993049 RX Vref 0 -> 0, step: 1
4315 11:46:53.996286
4316 11:46:53.996384 RX Delay -179 -> 252, step: 8
4317 11:46:54.003593 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4318 11:46:54.006926 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4319 11:46:54.010248 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4320 11:46:54.013510 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4321 11:46:54.020466 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4322 11:46:54.023435 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4323 11:46:54.026697 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4324 11:46:54.030154 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4325 11:46:54.033414 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4326 11:46:54.040048 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4327 11:46:54.043343 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4328 11:46:54.046659 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4329 11:46:54.049722 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4330 11:46:54.056591 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4331 11:46:54.059816 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4332 11:46:54.062988 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4333 11:46:54.063089 ==
4334 11:46:54.066328 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 11:46:54.069910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 11:46:54.069991 ==
4337 11:46:54.072757 DQS Delay:
4338 11:46:54.072856 DQS0 = 0, DQS1 = 0
4339 11:46:54.076302 DQM Delay:
4340 11:46:54.076427 DQM0 = 47, DQM1 = 40
4341 11:46:54.076568 DQ Delay:
4342 11:46:54.079632 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =40
4343 11:46:54.082827 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4344 11:46:54.085962 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4345 11:46:54.089542 DQ12 =44, DQ13 =44, DQ14 =52, DQ15 =44
4346 11:46:54.089614
4347 11:46:54.092818
4348 11:46:54.099374 [DQSOSCAuto] RK1, (LSB)MR18= 0x6433, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4349 11:46:54.102667 CH0 RK1: MR19=808, MR18=6433
4350 11:46:54.108936 CH0_RK1: MR19=0x808, MR18=0x6433, DQSOSC=391, MR23=63, INC=171, DEC=114
4351 11:46:54.112261 [RxdqsGatingPostProcess] freq 600
4352 11:46:54.115886 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4353 11:46:54.119102 Pre-setting of DQS Precalculation
4354 11:46:54.125594 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4355 11:46:54.125678 ==
4356 11:46:54.128959 Dram Type= 6, Freq= 0, CH_1, rank 0
4357 11:46:54.132166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 11:46:54.132277 ==
4359 11:46:54.139002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 11:46:54.142117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4361 11:46:54.146442 [CA 0] Center 35 (5~66) winsize 62
4362 11:46:54.149641 [CA 1] Center 35 (5~66) winsize 62
4363 11:46:54.153112 [CA 2] Center 34 (4~65) winsize 62
4364 11:46:54.156713 [CA 3] Center 33 (3~64) winsize 62
4365 11:46:54.159865 [CA 4] Center 34 (3~65) winsize 63
4366 11:46:54.162828 [CA 5] Center 33 (3~64) winsize 62
4367 11:46:54.162912
4368 11:46:54.166399 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4369 11:46:54.166482
4370 11:46:54.169661 [CATrainingPosCal] consider 1 rank data
4371 11:46:54.172828 u2DelayCellTimex100 = 270/100 ps
4372 11:46:54.176028 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 11:46:54.182785 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 11:46:54.186246 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 11:46:54.189506 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 11:46:54.192859 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4377 11:46:54.196093 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 11:46:54.196199
4379 11:46:54.199212 CA PerBit enable=1, Macro0, CA PI delay=33
4380 11:46:54.199316
4381 11:46:54.202458 [CBTSetCACLKResult] CA Dly = 33
4382 11:46:54.206295 CS Dly: 5 (0~36)
4383 11:46:54.206382 ==
4384 11:46:54.209376 Dram Type= 6, Freq= 0, CH_1, rank 1
4385 11:46:54.212552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 11:46:54.212660 ==
4387 11:46:54.219139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 11:46:54.222332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4389 11:46:54.226479 [CA 0] Center 35 (5~66) winsize 62
4390 11:46:54.229986 [CA 1] Center 35 (5~66) winsize 62
4391 11:46:54.233065 [CA 2] Center 34 (4~65) winsize 62
4392 11:46:54.236333 [CA 3] Center 34 (4~65) winsize 62
4393 11:46:54.239640 [CA 4] Center 34 (4~65) winsize 62
4394 11:46:54.243138 [CA 5] Center 33 (3~64) winsize 62
4395 11:46:54.243221
4396 11:46:54.246431 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4397 11:46:54.246517
4398 11:46:54.249529 [CATrainingPosCal] consider 2 rank data
4399 11:46:54.252874 u2DelayCellTimex100 = 270/100 ps
4400 11:46:54.256407 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 11:46:54.262886 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 11:46:54.266090 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 11:46:54.269264 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4404 11:46:54.272932 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 11:46:54.276148 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 11:46:54.276231
4407 11:46:54.279394 CA PerBit enable=1, Macro0, CA PI delay=33
4408 11:46:54.279477
4409 11:46:54.282702 [CBTSetCACLKResult] CA Dly = 33
4410 11:46:54.285917 CS Dly: 5 (0~37)
4411 11:46:54.286000
4412 11:46:54.289225 ----->DramcWriteLeveling(PI) begin...
4413 11:46:54.289310 ==
4414 11:46:54.292403 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 11:46:54.295772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 11:46:54.295880 ==
4417 11:46:54.299148 Write leveling (Byte 0): 29 => 29
4418 11:46:54.302509 Write leveling (Byte 1): 31 => 31
4419 11:46:54.305670 DramcWriteLeveling(PI) end<-----
4420 11:46:54.305793
4421 11:46:54.305931 ==
4422 11:46:54.309210 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 11:46:54.312420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 11:46:54.312523 ==
4425 11:46:54.315707 [Gating] SW mode calibration
4426 11:46:54.322266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4427 11:46:54.328529 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4428 11:46:54.332111 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 11:46:54.335215 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4430 11:46:54.341951 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4431 11:46:54.345377 0 9 12 | B1->B0 | 2f2f 2c2c | 1 1 | (1 1) (1 1)
4432 11:46:54.348779 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 11:46:54.355154 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 11:46:54.358210 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 11:46:54.361702 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 11:46:54.368086 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 11:46:54.371839 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 11:46:54.374859 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4439 11:46:54.381539 0 10 12 | B1->B0 | 3838 3b3b | 0 0 | (0 0) (0 0)
4440 11:46:54.384738 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 11:46:54.387969 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 11:46:54.394549 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 11:46:54.397733 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 11:46:54.401334 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 11:46:54.407770 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 11:46:54.411093 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 11:46:54.414353 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4448 11:46:54.421258 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:46:54.424600 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:46:54.427709 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:46:54.434122 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:46:54.437693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:46:54.440790 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 11:46:54.447520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 11:46:54.450910 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 11:46:54.454211 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 11:46:54.460524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 11:46:54.463889 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 11:46:54.467170 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 11:46:54.474093 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 11:46:54.477268 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 11:46:54.480414 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4463 11:46:54.487182 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4464 11:46:54.490412 Total UI for P1: 0, mck2ui 16
4465 11:46:54.493615 best dqsien dly found for B0: ( 0, 13, 10)
4466 11:46:54.497063 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 11:46:54.500253 Total UI for P1: 0, mck2ui 16
4468 11:46:54.503401 best dqsien dly found for B1: ( 0, 13, 10)
4469 11:46:54.507037 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4470 11:46:54.510327 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4471 11:46:54.510406
4472 11:46:54.513633 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4473 11:46:54.516849 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4474 11:46:54.520154 [Gating] SW calibration Done
4475 11:46:54.520231 ==
4476 11:46:54.523430 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 11:46:54.529905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 11:46:54.529982 ==
4479 11:46:54.530062 RX Vref Scan: 0
4480 11:46:54.530137
4481 11:46:54.533135 RX Vref 0 -> 0, step: 1
4482 11:46:54.533209
4483 11:46:54.536435 RX Delay -230 -> 252, step: 16
4484 11:46:54.539556 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4485 11:46:54.543144 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4486 11:46:54.546239 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4487 11:46:54.553074 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4488 11:46:54.556437 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4489 11:46:54.559455 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4490 11:46:54.562911 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4491 11:46:54.569696 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4492 11:46:54.573174 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4493 11:46:54.576221 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4494 11:46:54.579548 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4495 11:46:54.586066 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4496 11:46:54.589678 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4497 11:46:54.592931 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4498 11:46:54.596276 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4499 11:46:54.602530 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4500 11:46:54.602631 ==
4501 11:46:54.605773 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 11:46:54.609197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 11:46:54.609306 ==
4504 11:46:54.609400 DQS Delay:
4505 11:46:54.612333 DQS0 = 0, DQS1 = 0
4506 11:46:54.612440 DQM Delay:
4507 11:46:54.616006 DQM0 = 50, DQM1 = 42
4508 11:46:54.616081 DQ Delay:
4509 11:46:54.619195 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4510 11:46:54.622359 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4511 11:46:54.625606 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4512 11:46:54.629252 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4513 11:46:54.629334
4514 11:46:54.629398
4515 11:46:54.629458 ==
4516 11:46:54.632432 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 11:46:54.635812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 11:46:54.635898 ==
4519 11:46:54.635963
4520 11:46:54.639071
4521 11:46:54.639153 TX Vref Scan disable
4522 11:46:54.642321 == TX Byte 0 ==
4523 11:46:54.645525 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4524 11:46:54.648757 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4525 11:46:54.652342 == TX Byte 1 ==
4526 11:46:54.655262 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4527 11:46:54.658781 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4528 11:46:54.662092 ==
4529 11:46:54.662174 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 11:46:54.668585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 11:46:54.668668 ==
4532 11:46:54.668733
4533 11:46:54.668794
4534 11:46:54.671665 TX Vref Scan disable
4535 11:46:54.671773 == TX Byte 0 ==
4536 11:46:54.678320 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4537 11:46:54.681664 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4538 11:46:54.681748 == TX Byte 1 ==
4539 11:46:54.688409 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4540 11:46:54.691730 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4541 11:46:54.691813
4542 11:46:54.691878 [DATLAT]
4543 11:46:54.694825 Freq=600, CH1 RK0
4544 11:46:54.694908
4545 11:46:54.695036 DATLAT Default: 0x9
4546 11:46:54.698104 0, 0xFFFF, sum = 0
4547 11:46:54.698190 1, 0xFFFF, sum = 0
4548 11:46:54.701422 2, 0xFFFF, sum = 0
4549 11:46:54.704805 3, 0xFFFF, sum = 0
4550 11:46:54.704890 4, 0xFFFF, sum = 0
4551 11:46:54.708022 5, 0xFFFF, sum = 0
4552 11:46:54.708107 6, 0xFFFF, sum = 0
4553 11:46:54.711303 7, 0xFFFF, sum = 0
4554 11:46:54.711388 8, 0x0, sum = 1
4555 11:46:54.714511 9, 0x0, sum = 2
4556 11:46:54.714596 10, 0x0, sum = 3
4557 11:46:54.717781 11, 0x0, sum = 4
4558 11:46:54.717872 best_step = 9
4559 11:46:54.717952
4560 11:46:54.718038 ==
4561 11:46:54.721051 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 11:46:54.724309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 11:46:54.724393 ==
4564 11:46:54.727505 RX Vref Scan: 1
4565 11:46:54.727588
4566 11:46:54.731128 RX Vref 0 -> 0, step: 1
4567 11:46:54.731211
4568 11:46:54.731277 RX Delay -179 -> 252, step: 8
4569 11:46:54.731339
4570 11:46:54.734462 Set Vref, RX VrefLevel [Byte0]: 53
4571 11:46:54.737348 [Byte1]: 53
4572 11:46:54.741902
4573 11:46:54.741986 Final RX Vref Byte 0 = 53 to rank0
4574 11:46:54.745518 Final RX Vref Byte 1 = 53 to rank0
4575 11:46:54.748827 Final RX Vref Byte 0 = 53 to rank1
4576 11:46:54.752019 Final RX Vref Byte 1 = 53 to rank1==
4577 11:46:54.755250 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 11:46:54.761935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 11:46:54.762020 ==
4580 11:46:54.762086 DQS Delay:
4581 11:46:54.765394 DQS0 = 0, DQS1 = 0
4582 11:46:54.765496 DQM Delay:
4583 11:46:54.765564 DQM0 = 48, DQM1 = 40
4584 11:46:54.768595 DQ Delay:
4585 11:46:54.771645 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4586 11:46:54.775014 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4587 11:46:54.778346 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32
4588 11:46:54.781495 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4589 11:46:54.781579
4590 11:46:54.781645
4591 11:46:54.788103 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4592 11:46:54.791818 CH1 RK0: MR19=808, MR18=4A70
4593 11:46:54.798335 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4594 11:46:54.798419
4595 11:46:54.801617 ----->DramcWriteLeveling(PI) begin...
4596 11:46:54.801702 ==
4597 11:46:54.804808 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 11:46:54.808103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 11:46:54.808188 ==
4600 11:46:54.811677 Write leveling (Byte 0): 29 => 29
4601 11:46:54.814872 Write leveling (Byte 1): 29 => 29
4602 11:46:54.817984 DramcWriteLeveling(PI) end<-----
4603 11:46:54.818067
4604 11:46:54.818134 ==
4605 11:46:54.821314 Dram Type= 6, Freq= 0, CH_1, rank 1
4606 11:46:54.824535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 11:46:54.827829 ==
4608 11:46:54.827912 [Gating] SW mode calibration
4609 11:46:54.837971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4610 11:46:54.841151 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4611 11:46:54.844484 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 11:46:54.850932 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4613 11:46:54.854214 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 11:46:54.857518 0 9 12 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 1)
4615 11:46:54.864274 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4616 11:46:54.867668 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 11:46:54.870774 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 11:46:54.877672 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 11:46:54.880699 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 11:46:54.884129 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 11:46:54.890592 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4622 11:46:54.893888 0 10 12 | B1->B0 | 3a3a 3232 | 0 0 | (0 0) (0 0)
4623 11:46:54.897148 0 10 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4624 11:46:54.903927 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 11:46:54.907200 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 11:46:54.910453 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 11:46:54.917185 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 11:46:54.920370 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 11:46:54.923581 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4630 11:46:54.930040 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4631 11:46:54.933312 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:46:54.936758 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:46:54.943311 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:46:54.946657 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 11:46:54.949809 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:46:54.956666 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 11:46:54.959898 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 11:46:54.963170 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 11:46:54.969842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 11:46:54.972900 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 11:46:54.976279 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 11:46:54.982953 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 11:46:54.986437 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 11:46:54.989352 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 11:46:54.996223 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4646 11:46:54.999536 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4647 11:46:55.002561 Total UI for P1: 0, mck2ui 16
4648 11:46:55.006193 best dqsien dly found for B0: ( 0, 13, 8)
4649 11:46:55.009413 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 11:46:55.012621 Total UI for P1: 0, mck2ui 16
4651 11:46:55.015819 best dqsien dly found for B1: ( 0, 13, 10)
4652 11:46:55.019244 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4653 11:46:55.022437 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4654 11:46:55.022513
4655 11:46:55.029251 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4656 11:46:55.032484 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4657 11:46:55.035747 [Gating] SW calibration Done
4658 11:46:55.035821 ==
4659 11:46:55.038890 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 11:46:55.042141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 11:46:55.042217 ==
4662 11:46:55.042298 RX Vref Scan: 0
4663 11:46:55.042373
4664 11:46:55.045443 RX Vref 0 -> 0, step: 1
4665 11:46:55.045516
4666 11:46:55.049205 RX Delay -230 -> 252, step: 16
4667 11:46:55.052308 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4668 11:46:55.055546 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4669 11:46:55.061930 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4670 11:46:55.065457 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4671 11:46:55.068860 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4672 11:46:55.072041 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4673 11:46:55.078791 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4674 11:46:55.081795 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4675 11:46:55.085466 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4676 11:46:55.088465 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4677 11:46:55.092010 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4678 11:46:55.098617 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4679 11:46:55.101688 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4680 11:46:55.104940 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4681 11:46:55.108313 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4682 11:46:55.115354 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4683 11:46:55.115432 ==
4684 11:46:55.118544 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 11:46:55.121701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 11:46:55.121801 ==
4687 11:46:55.121906 DQS Delay:
4688 11:46:55.124870 DQS0 = 0, DQS1 = 0
4689 11:46:55.124971 DQM Delay:
4690 11:46:55.128383 DQM0 = 51, DQM1 = 46
4691 11:46:55.128456 DQ Delay:
4692 11:46:55.131806 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4693 11:46:55.134722 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4694 11:46:55.138069 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4695 11:46:55.141713 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4696 11:46:55.141786
4697 11:46:55.141910
4698 11:46:55.141984 ==
4699 11:46:55.144899 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 11:46:55.151322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 11:46:55.151399 ==
4702 11:46:55.151481
4703 11:46:55.151556
4704 11:46:55.151630 TX Vref Scan disable
4705 11:46:55.154543 == TX Byte 0 ==
4706 11:46:55.158147 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 11:46:55.164458 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 11:46:55.164534 == TX Byte 1 ==
4709 11:46:55.168046 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4710 11:46:55.174331 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4711 11:46:55.174419 ==
4712 11:46:55.177695 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 11:46:55.181330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 11:46:55.181405 ==
4715 11:46:55.181485
4716 11:46:55.181577
4717 11:46:55.184449 TX Vref Scan disable
4718 11:46:55.187886 == TX Byte 0 ==
4719 11:46:55.190824 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4720 11:46:55.194132 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4721 11:46:55.197525 == TX Byte 1 ==
4722 11:46:55.200580 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4723 11:46:55.204202 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4724 11:46:55.204276
4725 11:46:55.204354 [DATLAT]
4726 11:46:55.207711 Freq=600, CH1 RK1
4727 11:46:55.207788
4728 11:46:55.210657 DATLAT Default: 0x9
4729 11:46:55.210731 0, 0xFFFF, sum = 0
4730 11:46:55.214199 1, 0xFFFF, sum = 0
4731 11:46:55.214283 2, 0xFFFF, sum = 0
4732 11:46:55.217449 3, 0xFFFF, sum = 0
4733 11:46:55.217523 4, 0xFFFF, sum = 0
4734 11:46:55.220767 5, 0xFFFF, sum = 0
4735 11:46:55.220870 6, 0xFFFF, sum = 0
4736 11:46:55.223857 7, 0xFFFF, sum = 0
4737 11:46:55.223935 8, 0x0, sum = 1
4738 11:46:55.227314 9, 0x0, sum = 2
4739 11:46:55.227389 10, 0x0, sum = 3
4740 11:46:55.230454 11, 0x0, sum = 4
4741 11:46:55.230528 best_step = 9
4742 11:46:55.230606
4743 11:46:55.230680 ==
4744 11:46:55.234074 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 11:46:55.237336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 11:46:55.237409 ==
4747 11:46:55.240604 RX Vref Scan: 0
4748 11:46:55.240675
4749 11:46:55.243818 RX Vref 0 -> 0, step: 1
4750 11:46:55.243890
4751 11:46:55.243967 RX Delay -163 -> 252, step: 8
4752 11:46:55.251451 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4753 11:46:55.254732 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4754 11:46:55.258368 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4755 11:46:55.261732 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4756 11:46:55.268264 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4757 11:46:55.271323 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4758 11:46:55.274526 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4759 11:46:55.278218 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4760 11:46:55.281166 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4761 11:46:55.287990 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4762 11:46:55.291396 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4763 11:46:55.294890 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4764 11:46:55.298145 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4765 11:46:55.301587 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4766 11:46:55.307914 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4767 11:46:55.311403 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4768 11:46:55.311506 ==
4769 11:46:55.314415 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 11:46:55.317818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 11:46:55.317921 ==
4772 11:46:55.321392 DQS Delay:
4773 11:46:55.321467 DQS0 = 0, DQS1 = 0
4774 11:46:55.321531 DQM Delay:
4775 11:46:55.324533 DQM0 = 49, DQM1 = 43
4776 11:46:55.324635 DQ Delay:
4777 11:46:55.327757 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4778 11:46:55.331232 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4779 11:46:55.334394 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =40
4780 11:46:55.337419 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4781 11:46:55.337495
4782 11:46:55.337569
4783 11:46:55.347493 [DQSOSCAuto] RK1, (LSB)MR18= 0x541a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
4784 11:46:55.350663 CH1 RK1: MR19=808, MR18=541A
4785 11:46:55.354404 CH1_RK1: MR19=0x808, MR18=0x541A, DQSOSC=393, MR23=63, INC=169, DEC=113
4786 11:46:55.357602 [RxdqsGatingPostProcess] freq 600
4787 11:46:55.364051 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4788 11:46:55.367306 Pre-setting of DQS Precalculation
4789 11:46:55.370885 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4790 11:46:55.380758 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4791 11:46:55.387302 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4792 11:46:55.387410
4793 11:46:55.387505
4794 11:46:55.390548 [Calibration Summary] 1200 Mbps
4795 11:46:55.390632 CH 0, Rank 0
4796 11:46:55.394113 SW Impedance : PASS
4797 11:46:55.394196 DUTY Scan : NO K
4798 11:46:55.397195 ZQ Calibration : PASS
4799 11:46:55.400513 Jitter Meter : NO K
4800 11:46:55.400597 CBT Training : PASS
4801 11:46:55.403775 Write leveling : PASS
4802 11:46:55.407018 RX DQS gating : PASS
4803 11:46:55.407126 RX DQ/DQS(RDDQC) : PASS
4804 11:46:55.410219 TX DQ/DQS : PASS
4805 11:46:55.413517 RX DATLAT : PASS
4806 11:46:55.413614 RX DQ/DQS(Engine): PASS
4807 11:46:55.416926 TX OE : NO K
4808 11:46:55.417047 All Pass.
4809 11:46:55.417108
4810 11:46:55.420440 CH 0, Rank 1
4811 11:46:55.420508 SW Impedance : PASS
4812 11:46:55.423400 DUTY Scan : NO K
4813 11:46:55.426877 ZQ Calibration : PASS
4814 11:46:55.426975 Jitter Meter : NO K
4815 11:46:55.430100 CBT Training : PASS
4816 11:46:55.430198 Write leveling : PASS
4817 11:46:55.433720 RX DQS gating : PASS
4818 11:46:55.436702 RX DQ/DQS(RDDQC) : PASS
4819 11:46:55.436769 TX DQ/DQS : PASS
4820 11:46:55.439948 RX DATLAT : PASS
4821 11:46:55.443791 RX DQ/DQS(Engine): PASS
4822 11:46:55.443883 TX OE : NO K
4823 11:46:55.446780 All Pass.
4824 11:46:55.446848
4825 11:46:55.446906 CH 1, Rank 0
4826 11:46:55.450191 SW Impedance : PASS
4827 11:46:55.450260 DUTY Scan : NO K
4828 11:46:55.453332 ZQ Calibration : PASS
4829 11:46:55.456501 Jitter Meter : NO K
4830 11:46:55.456596 CBT Training : PASS
4831 11:46:55.459687 Write leveling : PASS
4832 11:46:55.463296 RX DQS gating : PASS
4833 11:46:55.463388 RX DQ/DQS(RDDQC) : PASS
4834 11:46:55.466635 TX DQ/DQS : PASS
4835 11:46:55.469765 RX DATLAT : PASS
4836 11:46:55.469851 RX DQ/DQS(Engine): PASS
4837 11:46:55.472901 TX OE : NO K
4838 11:46:55.473038 All Pass.
4839 11:46:55.473125
4840 11:46:55.476629 CH 1, Rank 1
4841 11:46:55.476727 SW Impedance : PASS
4842 11:46:55.479840 DUTY Scan : NO K
4843 11:46:55.483027 ZQ Calibration : PASS
4844 11:46:55.483120 Jitter Meter : NO K
4845 11:46:55.486212 CBT Training : PASS
4846 11:46:55.489651 Write leveling : PASS
4847 11:46:55.489717 RX DQS gating : PASS
4848 11:46:55.492802 RX DQ/DQS(RDDQC) : PASS
4849 11:46:55.496421 TX DQ/DQS : PASS
4850 11:46:55.496513 RX DATLAT : PASS
4851 11:46:55.499649 RX DQ/DQS(Engine): PASS
4852 11:46:55.499721 TX OE : NO K
4853 11:46:55.503062 All Pass.
4854 11:46:55.503145
4855 11:46:55.503209 DramC Write-DBI off
4856 11:46:55.506561 PER_BANK_REFRESH: Hybrid Mode
4857 11:46:55.509479 TX_TRACKING: ON
4858 11:46:55.516309 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4859 11:46:55.519458 [FAST_K] Save calibration result to emmc
4860 11:46:55.522978 dramc_set_vcore_voltage set vcore to 662500
4861 11:46:55.526372 Read voltage for 933, 3
4862 11:46:55.526454 Vio18 = 0
4863 11:46:55.529323 Vcore = 662500
4864 11:46:55.529404 Vdram = 0
4865 11:46:55.529469 Vddq = 0
4866 11:46:55.533077 Vmddr = 0
4867 11:46:55.536206 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4868 11:46:55.542777 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4869 11:46:55.545996 MEM_TYPE=3, freq_sel=17
4870 11:46:55.546079 sv_algorithm_assistance_LP4_1600
4871 11:46:55.552452 ============ PULL DRAM RESETB DOWN ============
4872 11:46:55.555810 ========== PULL DRAM RESETB DOWN end =========
4873 11:46:55.559363 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4874 11:46:55.562575 ===================================
4875 11:46:55.565819 LPDDR4 DRAM CONFIGURATION
4876 11:46:55.568958 ===================================
4877 11:46:55.572152 EX_ROW_EN[0] = 0x0
4878 11:46:55.572236 EX_ROW_EN[1] = 0x0
4879 11:46:55.575789 LP4Y_EN = 0x0
4880 11:46:55.575871 WORK_FSP = 0x0
4881 11:46:55.579235 WL = 0x3
4882 11:46:55.579316 RL = 0x3
4883 11:46:55.582202 BL = 0x2
4884 11:46:55.582284 RPST = 0x0
4885 11:46:55.585535 RD_PRE = 0x0
4886 11:46:55.585616 WR_PRE = 0x1
4887 11:46:55.588710 WR_PST = 0x0
4888 11:46:55.588814 DBI_WR = 0x0
4889 11:46:55.591857 DBI_RD = 0x0
4890 11:46:55.595298 OTF = 0x1
4891 11:46:55.598653 ===================================
4892 11:46:55.601896 ===================================
4893 11:46:55.601979 ANA top config
4894 11:46:55.605147 ===================================
4895 11:46:55.608641 DLL_ASYNC_EN = 0
4896 11:46:55.612050 ALL_SLAVE_EN = 1
4897 11:46:55.612133 NEW_RANK_MODE = 1
4898 11:46:55.614958 DLL_IDLE_MODE = 1
4899 11:46:55.618302 LP45_APHY_COMB_EN = 1
4900 11:46:55.621533 TX_ODT_DIS = 1
4901 11:46:55.621616 NEW_8X_MODE = 1
4902 11:46:55.624983 ===================================
4903 11:46:55.628462 ===================================
4904 11:46:55.631541 data_rate = 1866
4905 11:46:55.634969 CKR = 1
4906 11:46:55.638348 DQ_P2S_RATIO = 8
4907 11:46:55.641870 ===================================
4908 11:46:55.644798 CA_P2S_RATIO = 8
4909 11:46:55.648064 DQ_CA_OPEN = 0
4910 11:46:55.651359 DQ_SEMI_OPEN = 0
4911 11:46:55.651442 CA_SEMI_OPEN = 0
4912 11:46:55.654629 CA_FULL_RATE = 0
4913 11:46:55.657973 DQ_CKDIV4_EN = 1
4914 11:46:55.661207 CA_CKDIV4_EN = 1
4915 11:46:55.664757 CA_PREDIV_EN = 0
4916 11:46:55.668008 PH8_DLY = 0
4917 11:46:55.668090 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4918 11:46:55.671105 DQ_AAMCK_DIV = 4
4919 11:46:55.674462 CA_AAMCK_DIV = 4
4920 11:46:55.677640 CA_ADMCK_DIV = 4
4921 11:46:55.681352 DQ_TRACK_CA_EN = 0
4922 11:46:55.684445 CA_PICK = 933
4923 11:46:55.684527 CA_MCKIO = 933
4924 11:46:55.687637 MCKIO_SEMI = 0
4925 11:46:55.690814 PLL_FREQ = 3732
4926 11:46:55.694246 DQ_UI_PI_RATIO = 32
4927 11:46:55.697735 CA_UI_PI_RATIO = 0
4928 11:46:55.700857 ===================================
4929 11:46:55.703990 ===================================
4930 11:46:55.707576 memory_type:LPDDR4
4931 11:46:55.707657 GP_NUM : 10
4932 11:46:55.710873 SRAM_EN : 1
4933 11:46:55.710956 MD32_EN : 0
4934 11:46:55.714116 ===================================
4935 11:46:55.717472 [ANA_INIT] >>>>>>>>>>>>>>
4936 11:46:55.720513 <<<<<< [CONFIGURE PHASE]: ANA_TX
4937 11:46:55.724047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4938 11:46:55.727198 ===================================
4939 11:46:55.730561 data_rate = 1866,PCW = 0X8f00
4940 11:46:55.733631 ===================================
4941 11:46:55.737088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4942 11:46:55.743511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 11:46:55.746888 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4944 11:46:55.753574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4945 11:46:55.756917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4946 11:46:55.759947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4947 11:46:55.763125 [ANA_INIT] flow start
4948 11:46:55.763208 [ANA_INIT] PLL >>>>>>>>
4949 11:46:55.766336 [ANA_INIT] PLL <<<<<<<<
4950 11:46:55.770056 [ANA_INIT] MIDPI >>>>>>>>
4951 11:46:55.770139 [ANA_INIT] MIDPI <<<<<<<<
4952 11:46:55.773241 [ANA_INIT] DLL >>>>>>>>
4953 11:46:55.776439 [ANA_INIT] flow end
4954 11:46:55.779583 ============ LP4 DIFF to SE enter ============
4955 11:46:55.783128 ============ LP4 DIFF to SE exit ============
4956 11:46:55.786288 [ANA_INIT] <<<<<<<<<<<<<
4957 11:46:55.789552 [Flow] Enable top DCM control >>>>>
4958 11:46:55.792767 [Flow] Enable top DCM control <<<<<
4959 11:46:55.796053 Enable DLL master slave shuffle
4960 11:46:55.799350 ==============================================================
4961 11:46:55.803010 Gating Mode config
4962 11:46:55.809232 ==============================================================
4963 11:46:55.809316 Config description:
4964 11:46:55.819251 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4965 11:46:55.825791 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4966 11:46:55.832683 SELPH_MODE 0: By rank 1: By Phase
4967 11:46:55.835710 ==============================================================
4968 11:46:55.839112 GAT_TRACK_EN = 1
4969 11:46:55.842324 RX_GATING_MODE = 2
4970 11:46:55.845748 RX_GATING_TRACK_MODE = 2
4971 11:46:55.849270 SELPH_MODE = 1
4972 11:46:55.852540 PICG_EARLY_EN = 1
4973 11:46:55.855763 VALID_LAT_VALUE = 1
4974 11:46:55.858826 ==============================================================
4975 11:46:55.862508 Enter into Gating configuration >>>>
4976 11:46:55.865594 Exit from Gating configuration <<<<
4977 11:46:55.868787 Enter into DVFS_PRE_config >>>>>
4978 11:46:55.882010 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4979 11:46:55.885204 Exit from DVFS_PRE_config <<<<<
4980 11:46:55.888799 Enter into PICG configuration >>>>
4981 11:46:55.888885 Exit from PICG configuration <<<<
4982 11:46:55.892078 [RX_INPUT] configuration >>>>>
4983 11:46:55.895315 [RX_INPUT] configuration <<<<<
4984 11:46:55.902038 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4985 11:46:55.905160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4986 11:46:55.911923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 11:46:55.918353 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 11:46:55.925380 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 11:46:55.931974 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 11:46:55.935442 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4991 11:46:55.938752 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4992 11:46:55.941652 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4993 11:46:55.948214 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4994 11:46:55.951735 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4995 11:46:55.955093 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 11:46:55.958166 ===================================
4997 11:46:55.961645 LPDDR4 DRAM CONFIGURATION
4998 11:46:55.964768 ===================================
4999 11:46:55.968074 EX_ROW_EN[0] = 0x0
5000 11:46:55.968187 EX_ROW_EN[1] = 0x0
5001 11:46:55.971231 LP4Y_EN = 0x0
5002 11:46:55.971335 WORK_FSP = 0x0
5003 11:46:55.974822 WL = 0x3
5004 11:46:55.974926 RL = 0x3
5005 11:46:55.978219 BL = 0x2
5006 11:46:55.978338 RPST = 0x0
5007 11:46:55.981501 RD_PRE = 0x0
5008 11:46:55.981584 WR_PRE = 0x1
5009 11:46:55.984630 WR_PST = 0x0
5010 11:46:55.987932 DBI_WR = 0x0
5011 11:46:55.988040 DBI_RD = 0x0
5012 11:46:55.991249 OTF = 0x1
5013 11:46:55.994527 ===================================
5014 11:46:55.997681 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5015 11:46:56.000867 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5016 11:46:56.004559 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5017 11:46:56.007702 ===================================
5018 11:46:56.010921 LPDDR4 DRAM CONFIGURATION
5019 11:46:56.014085 ===================================
5020 11:46:56.018175 EX_ROW_EN[0] = 0x10
5021 11:46:56.018692 EX_ROW_EN[1] = 0x0
5022 11:46:56.021211 LP4Y_EN = 0x0
5023 11:46:56.021661 WORK_FSP = 0x0
5024 11:46:56.024447 WL = 0x3
5025 11:46:56.025093 RL = 0x3
5026 11:46:56.028024 BL = 0x2
5027 11:46:56.028467 RPST = 0x0
5028 11:46:56.031106 RD_PRE = 0x0
5029 11:46:56.031584 WR_PRE = 0x1
5030 11:46:56.034709 WR_PST = 0x0
5031 11:46:56.037710 DBI_WR = 0x0
5032 11:46:56.038177 DBI_RD = 0x0
5033 11:46:56.041101 OTF = 0x1
5034 11:46:56.044504 ===================================
5035 11:46:56.047857 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5036 11:46:56.053050 nWR fixed to 30
5037 11:46:56.056334 [ModeRegInit_LP4] CH0 RK0
5038 11:46:56.056804 [ModeRegInit_LP4] CH0 RK1
5039 11:46:56.059431 [ModeRegInit_LP4] CH1 RK0
5040 11:46:56.062886 [ModeRegInit_LP4] CH1 RK1
5041 11:46:56.063377 match AC timing 9
5042 11:46:56.069735 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5043 11:46:56.073040 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5044 11:46:56.076378 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5045 11:46:56.082831 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5046 11:46:56.085873 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5047 11:46:56.086337 ==
5048 11:46:56.089564 Dram Type= 6, Freq= 0, CH_0, rank 0
5049 11:46:56.092776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 11:46:56.093296 ==
5051 11:46:56.099259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 11:46:56.106163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5053 11:46:56.109396 [CA 0] Center 38 (8~69) winsize 62
5054 11:46:56.112569 [CA 1] Center 38 (8~69) winsize 62
5055 11:46:56.115743 [CA 2] Center 35 (5~66) winsize 62
5056 11:46:56.119421 [CA 3] Center 35 (5~66) winsize 62
5057 11:46:56.122686 [CA 4] Center 34 (4~65) winsize 62
5058 11:46:56.125905 [CA 5] Center 33 (3~64) winsize 62
5059 11:46:56.126368
5060 11:46:56.129463 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5061 11:46:56.129926
5062 11:46:56.132749 [CATrainingPosCal] consider 1 rank data
5063 11:46:56.135982 u2DelayCellTimex100 = 270/100 ps
5064 11:46:56.139108 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5065 11:46:56.142488 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5066 11:46:56.145720 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5067 11:46:56.149046 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5068 11:46:56.155792 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5069 11:46:56.158735 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5070 11:46:56.159201
5071 11:46:56.162187 CA PerBit enable=1, Macro0, CA PI delay=33
5072 11:46:56.162652
5073 11:46:56.165312 [CBTSetCACLKResult] CA Dly = 33
5074 11:46:56.165396 CS Dly: 7 (0~38)
5075 11:46:56.165469 ==
5076 11:46:56.168835 Dram Type= 6, Freq= 0, CH_0, rank 1
5077 11:46:56.175153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 11:46:56.175621 ==
5079 11:46:56.178650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 11:46:56.185156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5081 11:46:56.188959 [CA 0] Center 38 (8~69) winsize 62
5082 11:46:56.192099 [CA 1] Center 38 (8~69) winsize 62
5083 11:46:56.195283 [CA 2] Center 36 (6~67) winsize 62
5084 11:46:56.198439 [CA 3] Center 35 (5~66) winsize 62
5085 11:46:56.201789 [CA 4] Center 34 (4~65) winsize 62
5086 11:46:56.205140 [CA 5] Center 34 (4~64) winsize 61
5087 11:46:56.205609
5088 11:46:56.208206 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5089 11:46:56.208677
5090 11:46:56.211495 [CATrainingPosCal] consider 2 rank data
5091 11:46:56.214675 u2DelayCellTimex100 = 270/100 ps
5092 11:46:56.217989 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5093 11:46:56.221253 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5094 11:46:56.227880 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5095 11:46:56.231682 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5096 11:46:56.234990 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5097 11:46:56.238226 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5098 11:46:56.238805
5099 11:46:56.241729 CA PerBit enable=1, Macro0, CA PI delay=34
5100 11:46:56.242203
5101 11:46:56.244906 [CBTSetCACLKResult] CA Dly = 34
5102 11:46:56.245427 CS Dly: 7 (0~39)
5103 11:46:56.248204
5104 11:46:56.251211 ----->DramcWriteLeveling(PI) begin...
5105 11:46:56.251698 ==
5106 11:46:56.254639 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 11:46:56.257637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 11:46:56.258112 ==
5109 11:46:56.260956 Write leveling (Byte 0): 35 => 35
5110 11:46:56.264691 Write leveling (Byte 1): 28 => 28
5111 11:46:56.267729 DramcWriteLeveling(PI) end<-----
5112 11:46:56.268216
5113 11:46:56.268589 ==
5114 11:46:56.271171 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 11:46:56.274435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 11:46:56.274917 ==
5117 11:46:56.277798 [Gating] SW mode calibration
5118 11:46:56.284486 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5119 11:46:56.290819 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5120 11:46:56.294509 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 11:46:56.297820 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 11:46:56.304301 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 11:46:56.307412 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 11:46:56.310907 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 11:46:56.317373 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 11:46:56.320622 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5127 11:46:56.323940 0 14 28 | B1->B0 | 3434 2323 | 0 0 | (1 0) (0 0)
5128 11:46:56.330867 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5129 11:46:56.334053 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 11:46:56.337180 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 11:46:56.344039 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 11:46:56.347228 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 11:46:56.350125 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 11:46:56.356819 0 15 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5135 11:46:56.360107 0 15 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
5136 11:46:56.363425 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5137 11:46:56.370098 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 11:46:56.373033 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 11:46:56.376654 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 11:46:56.383478 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 11:46:56.386667 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 11:46:56.389793 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5143 11:46:56.396423 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5144 11:46:56.399945 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5145 11:46:56.403273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:46:56.409949 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:46:56.413181 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:46:56.416581 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 11:46:56.423240 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 11:46:56.426405 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 11:46:56.429599 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 11:46:56.436358 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 11:46:56.439559 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 11:46:56.442763 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 11:46:56.449696 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 11:46:56.452965 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 11:46:56.456231 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 11:46:56.459589 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5159 11:46:56.466191 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5160 11:46:56.469571 Total UI for P1: 0, mck2ui 16
5161 11:46:56.472802 best dqsien dly found for B0: ( 1, 2, 24)
5162 11:46:56.475865 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5163 11:46:56.479209 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 11:46:56.482652 Total UI for P1: 0, mck2ui 16
5165 11:46:56.486154 best dqsien dly found for B1: ( 1, 2, 30)
5166 11:46:56.489044 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5167 11:46:56.495653 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5168 11:46:56.496073
5169 11:46:56.499078 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5170 11:46:56.502296 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5171 11:46:56.505535 [Gating] SW calibration Done
5172 11:46:56.505970 ==
5173 11:46:56.508759 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 11:46:56.512160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 11:46:56.512615 ==
5176 11:46:56.515832 RX Vref Scan: 0
5177 11:46:56.516251
5178 11:46:56.516581 RX Vref 0 -> 0, step: 1
5179 11:46:56.516929
5180 11:46:56.519203 RX Delay -80 -> 252, step: 8
5181 11:46:56.522333 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5182 11:46:56.529000 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5183 11:46:56.532172 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5184 11:46:56.535363 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5185 11:46:56.538915 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5186 11:46:56.542215 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5187 11:46:56.545414 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5188 11:46:56.551817 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5189 11:46:56.555531 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5190 11:46:56.558912 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5191 11:46:56.561722 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5192 11:46:56.565475 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5193 11:46:56.571907 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5194 11:46:56.574922 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5195 11:46:56.578447 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5196 11:46:56.581884 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5197 11:46:56.582373 ==
5198 11:46:56.584779 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 11:46:56.588117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 11:46:56.588905 ==
5201 11:46:56.591375 DQS Delay:
5202 11:46:56.591958 DQS0 = 0, DQS1 = 0
5203 11:46:56.594971 DQM Delay:
5204 11:46:56.595660 DQM0 = 106, DQM1 = 91
5205 11:46:56.596284 DQ Delay:
5206 11:46:56.601491 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5207 11:46:56.604960 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5208 11:46:56.608049 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5209 11:46:56.611362 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5210 11:46:56.611826
5211 11:46:56.612251
5212 11:46:56.612662 ==
5213 11:46:56.614460 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 11:46:56.617786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 11:46:56.618260 ==
5216 11:46:56.618632
5217 11:46:56.619039
5218 11:46:56.621438 TX Vref Scan disable
5219 11:46:56.621924 == TX Byte 0 ==
5220 11:46:56.627860 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5221 11:46:56.631089 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5222 11:46:56.631651 == TX Byte 1 ==
5223 11:46:56.637794 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5224 11:46:56.641133 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5225 11:46:56.641654 ==
5226 11:46:56.644464 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 11:46:56.647631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 11:46:56.648081 ==
5229 11:46:56.648472
5230 11:46:56.650787
5231 11:46:56.651300 TX Vref Scan disable
5232 11:46:56.654107 == TX Byte 0 ==
5233 11:46:56.657885 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5234 11:46:56.663957 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5235 11:46:56.664404 == TX Byte 1 ==
5236 11:46:56.667499 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5237 11:46:56.673949 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5238 11:46:56.674380
5239 11:46:56.674746 [DATLAT]
5240 11:46:56.675121 Freq=933, CH0 RK0
5241 11:46:56.675458
5242 11:46:56.677106 DATLAT Default: 0xd
5243 11:46:56.680655 0, 0xFFFF, sum = 0
5244 11:46:56.681153 1, 0xFFFF, sum = 0
5245 11:46:56.683901 2, 0xFFFF, sum = 0
5246 11:46:56.684329 3, 0xFFFF, sum = 0
5247 11:46:56.687350 4, 0xFFFF, sum = 0
5248 11:46:56.687865 5, 0xFFFF, sum = 0
5249 11:46:56.690355 6, 0xFFFF, sum = 0
5250 11:46:56.690905 7, 0xFFFF, sum = 0
5251 11:46:56.694039 8, 0xFFFF, sum = 0
5252 11:46:56.694475 9, 0xFFFF, sum = 0
5253 11:46:56.696901 10, 0x0, sum = 1
5254 11:46:56.697355 11, 0x0, sum = 2
5255 11:46:56.700584 12, 0x0, sum = 3
5256 11:46:56.701247 13, 0x0, sum = 4
5257 11:46:56.701772 best_step = 11
5258 11:46:56.703810
5259 11:46:56.704322 ==
5260 11:46:56.706727 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 11:46:56.710465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 11:46:56.711036 ==
5263 11:46:56.711542 RX Vref Scan: 1
5264 11:46:56.712023
5265 11:46:56.713532 RX Vref 0 -> 0, step: 1
5266 11:46:56.714052
5267 11:46:56.716768 RX Delay -53 -> 252, step: 4
5268 11:46:56.717328
5269 11:46:56.720500 Set Vref, RX VrefLevel [Byte0]: 58
5270 11:46:56.723605 [Byte1]: 48
5271 11:46:56.726775
5272 11:46:56.727348 Final RX Vref Byte 0 = 58 to rank0
5273 11:46:56.730113 Final RX Vref Byte 1 = 48 to rank0
5274 11:46:56.733422 Final RX Vref Byte 0 = 58 to rank1
5275 11:46:56.737069 Final RX Vref Byte 1 = 48 to rank1==
5276 11:46:56.740428 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 11:46:56.746747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 11:46:56.747171 ==
5279 11:46:56.747503 DQS Delay:
5280 11:46:56.747813 DQS0 = 0, DQS1 = 0
5281 11:46:56.749879 DQM Delay:
5282 11:46:56.750300 DQM0 = 107, DQM1 = 92
5283 11:46:56.753169 DQ Delay:
5284 11:46:56.756669 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5285 11:46:56.760043 DQ4 =106, DQ5 =98, DQ6 =116, DQ7 =114
5286 11:46:56.763027 DQ8 =84, DQ9 =78, DQ10 =90, DQ11 =90
5287 11:46:56.766881 DQ12 =96, DQ13 =96, DQ14 =104, DQ15 =98
5288 11:46:56.767303
5289 11:46:56.767639
5290 11:46:56.773628 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5291 11:46:56.777423 CH0 RK0: MR19=505, MR18=2723
5292 11:46:56.783608 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5293 11:46:56.784087
5294 11:46:56.786596 ----->DramcWriteLeveling(PI) begin...
5295 11:46:56.787145 ==
5296 11:46:56.790124 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 11:46:56.793474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 11:46:56.793948 ==
5299 11:46:56.796818 Write leveling (Byte 0): 31 => 31
5300 11:46:56.799935 Write leveling (Byte 1): 28 => 28
5301 11:46:56.802978 DramcWriteLeveling(PI) end<-----
5302 11:46:56.803538
5303 11:46:56.804002 ==
5304 11:46:56.806187 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 11:46:56.812844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 11:46:56.813315 ==
5307 11:46:56.813685 [Gating] SW mode calibration
5308 11:46:56.822670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 11:46:56.826007 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 11:46:56.832599 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5311 11:46:56.836272 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 11:46:56.839229 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 11:46:56.846074 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 11:46:56.849184 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 11:46:56.852553 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 11:46:56.859169 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5317 11:46:56.862335 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5318 11:46:56.865507 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5319 11:46:56.872479 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 11:46:56.875652 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 11:46:56.878620 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 11:46:56.882379 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 11:46:56.888716 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 11:46:56.891825 0 15 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
5325 11:46:56.895521 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
5326 11:46:56.902045 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 11:46:56.905225 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 11:46:56.908478 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 11:46:56.914901 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 11:46:56.918467 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 11:46:56.921801 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 11:46:56.928301 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 11:46:56.931907 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5334 11:46:56.935168 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:46:56.941668 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:46:56.945222 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 11:46:56.948616 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 11:46:56.955015 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 11:46:56.958541 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 11:46:56.961677 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 11:46:56.968295 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 11:46:56.971609 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 11:46:56.975023 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 11:46:56.981591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 11:46:56.984681 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 11:46:56.987771 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 11:46:56.994532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 11:46:56.997781 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 11:46:57.000933 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5350 11:46:57.004473 Total UI for P1: 0, mck2ui 16
5351 11:46:57.007561 best dqsien dly found for B0: ( 1, 2, 26)
5352 11:46:57.014068 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 11:46:57.014155 Total UI for P1: 0, mck2ui 16
5354 11:46:57.020915 best dqsien dly found for B1: ( 1, 2, 28)
5355 11:46:57.024407 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5356 11:46:57.027736 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5357 11:46:57.027822
5358 11:46:57.030850 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5359 11:46:57.034082 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5360 11:46:57.037324 [Gating] SW calibration Done
5361 11:46:57.037411 ==
5362 11:46:57.040884 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 11:46:57.044164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 11:46:57.044245 ==
5365 11:46:57.047419 RX Vref Scan: 0
5366 11:46:57.047504
5367 11:46:57.047607 RX Vref 0 -> 0, step: 1
5368 11:46:57.047707
5369 11:46:57.050668 RX Delay -80 -> 252, step: 8
5370 11:46:57.053870 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5371 11:46:57.060645 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5372 11:46:57.063890 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5373 11:46:57.067136 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5374 11:46:57.070512 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5375 11:46:57.073793 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5376 11:46:57.076921 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5377 11:46:57.083636 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5378 11:46:57.086901 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5379 11:46:57.090221 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5380 11:46:57.093603 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5381 11:46:57.096841 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5382 11:46:57.103605 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5383 11:46:57.106728 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5384 11:46:57.109852 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5385 11:46:57.113334 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5386 11:46:57.113420 ==
5387 11:46:57.116898 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 11:46:57.119859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 11:46:57.123217 ==
5390 11:46:57.123303 DQS Delay:
5391 11:46:57.123388 DQS0 = 0, DQS1 = 0
5392 11:46:57.126725 DQM Delay:
5393 11:46:57.126832 DQM0 = 104, DQM1 = 90
5394 11:46:57.130248 DQ Delay:
5395 11:46:57.132844 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5396 11:46:57.136461 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5397 11:46:57.139788 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5398 11:46:57.142831 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5399 11:46:57.142916
5400 11:46:57.142982
5401 11:46:57.143043 ==
5402 11:46:57.146204 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 11:46:57.149344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 11:46:57.149428 ==
5405 11:46:57.149495
5406 11:46:57.149557
5407 11:46:57.152874 TX Vref Scan disable
5408 11:46:57.152960 == TX Byte 0 ==
5409 11:46:57.159329 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5410 11:46:57.162576 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5411 11:46:57.165823 == TX Byte 1 ==
5412 11:46:57.169175 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5413 11:46:57.172814 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5414 11:46:57.172898 ==
5415 11:46:57.176234 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 11:46:57.179504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 11:46:57.179589 ==
5418 11:46:57.182729
5419 11:46:57.182812
5420 11:46:57.182879 TX Vref Scan disable
5421 11:46:57.186037 == TX Byte 0 ==
5422 11:46:57.189072 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5423 11:46:57.196021 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5424 11:46:57.196105 == TX Byte 1 ==
5425 11:46:57.199154 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5426 11:46:57.205404 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5427 11:46:57.205488
5428 11:46:57.205554 [DATLAT]
5429 11:46:57.205617 Freq=933, CH0 RK1
5430 11:46:57.205695
5431 11:46:57.209128 DATLAT Default: 0xb
5432 11:46:57.212271 0, 0xFFFF, sum = 0
5433 11:46:57.212357 1, 0xFFFF, sum = 0
5434 11:46:57.215572 2, 0xFFFF, sum = 0
5435 11:46:57.215657 3, 0xFFFF, sum = 0
5436 11:46:57.219020 4, 0xFFFF, sum = 0
5437 11:46:57.219105 5, 0xFFFF, sum = 0
5438 11:46:57.221900 6, 0xFFFF, sum = 0
5439 11:46:57.221985 7, 0xFFFF, sum = 0
5440 11:46:57.225337 8, 0xFFFF, sum = 0
5441 11:46:57.225422 9, 0xFFFF, sum = 0
5442 11:46:57.228493 10, 0x0, sum = 1
5443 11:46:57.228577 11, 0x0, sum = 2
5444 11:46:57.231964 12, 0x0, sum = 3
5445 11:46:57.232049 13, 0x0, sum = 4
5446 11:46:57.235237 best_step = 11
5447 11:46:57.235323
5448 11:46:57.235390 ==
5449 11:46:57.238669 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 11:46:57.241716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 11:46:57.241801 ==
5452 11:46:57.241868 RX Vref Scan: 0
5453 11:46:57.244900
5454 11:46:57.245034 RX Vref 0 -> 0, step: 1
5455 11:46:57.245105
5456 11:46:57.248257 RX Delay -53 -> 252, step: 4
5457 11:46:57.255193 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5458 11:46:57.258356 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5459 11:46:57.261651 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5460 11:46:57.264745 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5461 11:46:57.268421 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5462 11:46:57.274831 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5463 11:46:57.278197 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5464 11:46:57.281454 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5465 11:46:57.284643 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5466 11:46:57.288265 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5467 11:46:57.291496 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5468 11:46:57.298073 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5469 11:46:57.301346 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5470 11:46:57.304613 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5471 11:46:57.307907 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5472 11:46:57.314536 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5473 11:46:57.314620 ==
5474 11:46:57.317717 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 11:46:57.320893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 11:46:57.320986 ==
5477 11:46:57.321070 DQS Delay:
5478 11:46:57.324436 DQS0 = 0, DQS1 = 0
5479 11:46:57.324520 DQM Delay:
5480 11:46:57.327831 DQM0 = 104, DQM1 = 93
5481 11:46:57.327915 DQ Delay:
5482 11:46:57.330968 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5483 11:46:57.334212 DQ4 =104, DQ5 =98, DQ6 =110, DQ7 =110
5484 11:46:57.337521 DQ8 =86, DQ9 =80, DQ10 =92, DQ11 =92
5485 11:46:57.341028 DQ12 =98, DQ13 =94, DQ14 =104, DQ15 =100
5486 11:46:57.341111
5487 11:46:57.341178
5488 11:46:57.350892 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5489 11:46:57.350989 CH0 RK1: MR19=505, MR18=2A0B
5490 11:46:57.357136 CH0_RK1: MR19=0x505, MR18=0x2A0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5491 11:46:57.360509 [RxdqsGatingPostProcess] freq 933
5492 11:46:57.367348 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5493 11:46:57.370580 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 11:46:57.373861 best DQS1 dly(2T, 0.5T) = (0, 10)
5495 11:46:57.377302 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 11:46:57.380517 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5497 11:46:57.383689 best DQS0 dly(2T, 0.5T) = (0, 10)
5498 11:46:57.386850 best DQS1 dly(2T, 0.5T) = (0, 10)
5499 11:46:57.390150 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5500 11:46:57.393815 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5501 11:46:57.393897 Pre-setting of DQS Precalculation
5502 11:46:57.400285 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5503 11:46:57.400368 ==
5504 11:46:57.403479 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 11:46:57.406706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 11:46:57.406789 ==
5507 11:46:57.413497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 11:46:57.420115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5509 11:46:57.423316 [CA 0] Center 38 (8~68) winsize 61
5510 11:46:57.426483 [CA 1] Center 38 (8~68) winsize 61
5511 11:46:57.430191 [CA 2] Center 36 (6~66) winsize 61
5512 11:46:57.433232 [CA 3] Center 34 (4~65) winsize 62
5513 11:46:57.436589 [CA 4] Center 35 (4~66) winsize 63
5514 11:46:57.439968 [CA 5] Center 34 (4~65) winsize 62
5515 11:46:57.440050
5516 11:46:57.443102 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5517 11:46:57.443214
5518 11:46:57.446599 [CATrainingPosCal] consider 1 rank data
5519 11:46:57.449615 u2DelayCellTimex100 = 270/100 ps
5520 11:46:57.452943 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5521 11:46:57.456209 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5522 11:46:57.459888 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5523 11:46:57.463195 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5524 11:46:57.466445 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5525 11:46:57.472749 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5526 11:46:57.472829
5527 11:46:57.476449 CA PerBit enable=1, Macro0, CA PI delay=34
5528 11:46:57.476522
5529 11:46:57.479744 [CBTSetCACLKResult] CA Dly = 34
5530 11:46:57.479856 CS Dly: 6 (0~37)
5531 11:46:57.479964 ==
5532 11:46:57.482635 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 11:46:57.486307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 11:46:57.489480 ==
5535 11:46:57.492662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5536 11:46:57.499569 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5537 11:46:57.502399 [CA 0] Center 38 (8~68) winsize 61
5538 11:46:57.506150 [CA 1] Center 38 (7~69) winsize 63
5539 11:46:57.509378 [CA 2] Center 36 (5~67) winsize 63
5540 11:46:57.512557 [CA 3] Center 35 (5~65) winsize 61
5541 11:46:57.515827 [CA 4] Center 35 (5~66) winsize 62
5542 11:46:57.519161 [CA 5] Center 34 (4~65) winsize 62
5543 11:46:57.519270
5544 11:46:57.522337 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5545 11:46:57.522453
5546 11:46:57.525503 [CATrainingPosCal] consider 2 rank data
5547 11:46:57.528922 u2DelayCellTimex100 = 270/100 ps
5548 11:46:57.532236 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5549 11:46:57.535354 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5550 11:46:57.542080 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5551 11:46:57.545229 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5552 11:46:57.548679 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5553 11:46:57.552146 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5554 11:46:57.552228
5555 11:46:57.555285 CA PerBit enable=1, Macro0, CA PI delay=34
5556 11:46:57.555367
5557 11:46:57.558754 [CBTSetCACLKResult] CA Dly = 34
5558 11:46:57.558836 CS Dly: 7 (0~39)
5559 11:46:57.561834
5560 11:46:57.565348 ----->DramcWriteLeveling(PI) begin...
5561 11:46:57.565432 ==
5562 11:46:57.568674 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 11:46:57.571860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 11:46:57.571943 ==
5565 11:46:57.575559 Write leveling (Byte 0): 28 => 28
5566 11:46:57.578656 Write leveling (Byte 1): 30 => 30
5567 11:46:57.581841 DramcWriteLeveling(PI) end<-----
5568 11:46:57.581923
5569 11:46:57.581989 ==
5570 11:46:57.585175 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 11:46:57.588360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 11:46:57.588443 ==
5573 11:46:57.591628 [Gating] SW mode calibration
5574 11:46:57.598083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5575 11:46:57.604624 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5576 11:46:57.608352 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 11:46:57.611205 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 11:46:57.618207 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 11:46:57.621558 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 11:46:57.624767 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 11:46:57.631500 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5582 11:46:57.634743 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
5583 11:46:57.637913 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5584 11:46:57.644521 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 11:46:57.647602 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 11:46:57.651030 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 11:46:57.657799 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 11:46:57.660717 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 11:46:57.664165 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 11:46:57.671001 0 15 24 | B1->B0 | 2c2c 2c2b | 1 1 | (0 0) (0 0)
5591 11:46:57.674055 0 15 28 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
5592 11:46:57.677483 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 11:46:57.684336 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 11:46:57.687584 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 11:46:57.690807 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 11:46:57.697211 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 11:46:57.700455 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 11:46:57.704090 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5599 11:46:57.710432 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5600 11:46:57.714132 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:46:57.717461 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:46:57.723792 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:46:57.727468 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 11:46:57.730660 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 11:46:57.736967 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 11:46:57.740172 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 11:46:57.743842 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 11:46:57.750216 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 11:46:57.753615 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 11:46:57.757027 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 11:46:57.763533 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 11:46:57.766824 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 11:46:57.770144 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5614 11:46:57.776546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5615 11:46:57.780043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 11:46:57.783244 Total UI for P1: 0, mck2ui 16
5617 11:46:57.786885 best dqsien dly found for B0: ( 1, 2, 22)
5618 11:46:57.790073 Total UI for P1: 0, mck2ui 16
5619 11:46:57.793274 best dqsien dly found for B1: ( 1, 2, 26)
5620 11:46:57.796387 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5621 11:46:57.799635 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5622 11:46:57.799719
5623 11:46:57.803349 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5624 11:46:57.806637 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5625 11:46:57.809800 [Gating] SW calibration Done
5626 11:46:57.809884 ==
5627 11:46:57.813167 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 11:46:57.816332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 11:46:57.816416 ==
5630 11:46:57.819443 RX Vref Scan: 0
5631 11:46:57.819526
5632 11:46:57.822657 RX Vref 0 -> 0, step: 1
5633 11:46:57.822739
5634 11:46:57.822805 RX Delay -80 -> 252, step: 8
5635 11:46:57.829433 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5636 11:46:57.832772 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5637 11:46:57.836207 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5638 11:46:57.839543 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5639 11:46:57.842854 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5640 11:46:57.849669 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5641 11:46:57.852772 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5642 11:46:57.855952 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5643 11:46:57.859168 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5644 11:46:57.862682 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5645 11:46:57.865883 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5646 11:46:57.872333 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5647 11:46:57.875732 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5648 11:46:57.879267 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5649 11:46:57.882663 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5650 11:46:57.885689 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5651 11:46:57.889027 ==
5652 11:46:57.889110 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 11:46:57.895579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 11:46:57.895662 ==
5655 11:46:57.895728 DQS Delay:
5656 11:46:57.898775 DQS0 = 0, DQS1 = 0
5657 11:46:57.898859 DQM Delay:
5658 11:46:57.902464 DQM0 = 102, DQM1 = 95
5659 11:46:57.902547 DQ Delay:
5660 11:46:57.905692 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5661 11:46:57.908896 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5662 11:46:57.912116 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5663 11:46:57.915489 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5664 11:46:57.915572
5665 11:46:57.915638
5666 11:46:57.915697 ==
5667 11:46:57.918675 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 11:46:57.922324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 11:46:57.922407 ==
5670 11:46:57.925609
5671 11:46:57.925691
5672 11:46:57.925756 TX Vref Scan disable
5673 11:46:57.928690 == TX Byte 0 ==
5674 11:46:57.931994 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5675 11:46:57.935295 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5676 11:46:57.938418 == TX Byte 1 ==
5677 11:46:57.941985 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5678 11:46:57.945298 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5679 11:46:57.948444 ==
5680 11:46:57.948527 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 11:46:57.954859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 11:46:57.954942 ==
5683 11:46:57.955008
5684 11:46:57.955067
5685 11:46:57.958356 TX Vref Scan disable
5686 11:46:57.958440 == TX Byte 0 ==
5687 11:46:57.964992 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5688 11:46:57.967931 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5689 11:46:57.968013 == TX Byte 1 ==
5690 11:46:57.974907 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5691 11:46:57.977844 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5692 11:46:57.977931
5693 11:46:57.977997 [DATLAT]
5694 11:46:57.981350 Freq=933, CH1 RK0
5695 11:46:57.981432
5696 11:46:57.981498 DATLAT Default: 0xd
5697 11:46:57.984576 0, 0xFFFF, sum = 0
5698 11:46:57.984669 1, 0xFFFF, sum = 0
5699 11:46:57.988004 2, 0xFFFF, sum = 0
5700 11:46:57.988089 3, 0xFFFF, sum = 0
5701 11:46:57.991030 4, 0xFFFF, sum = 0
5702 11:46:57.991115 5, 0xFFFF, sum = 0
5703 11:46:57.994472 6, 0xFFFF, sum = 0
5704 11:46:57.997777 7, 0xFFFF, sum = 0
5705 11:46:57.997862 8, 0xFFFF, sum = 0
5706 11:46:58.000886 9, 0xFFFF, sum = 0
5707 11:46:58.000971 10, 0x0, sum = 1
5708 11:46:58.004637 11, 0x0, sum = 2
5709 11:46:58.004722 12, 0x0, sum = 3
5710 11:46:58.004789 13, 0x0, sum = 4
5711 11:46:58.007719 best_step = 11
5712 11:46:58.007801
5713 11:46:58.007867 ==
5714 11:46:58.011051 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 11:46:58.014236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 11:46:58.014321 ==
5717 11:46:58.017562 RX Vref Scan: 1
5718 11:46:58.017646
5719 11:46:58.017712 RX Vref 0 -> 0, step: 1
5720 11:46:58.020749
5721 11:46:58.020833 RX Delay -53 -> 252, step: 4
5722 11:46:58.020900
5723 11:46:58.024470 Set Vref, RX VrefLevel [Byte0]: 53
5724 11:46:58.027690 [Byte1]: 53
5725 11:46:58.032169
5726 11:46:58.032252 Final RX Vref Byte 0 = 53 to rank0
5727 11:46:58.035100 Final RX Vref Byte 1 = 53 to rank0
5728 11:46:58.038296 Final RX Vref Byte 0 = 53 to rank1
5729 11:46:58.041778 Final RX Vref Byte 1 = 53 to rank1==
5730 11:46:58.044894 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 11:46:58.051366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 11:46:58.051461 ==
5733 11:46:58.051545 DQS Delay:
5734 11:46:58.054785 DQS0 = 0, DQS1 = 0
5735 11:46:58.054864 DQM Delay:
5736 11:46:58.054946 DQM0 = 104, DQM1 = 96
5737 11:46:58.057979 DQ Delay:
5738 11:46:58.061611 DQ0 =110, DQ1 =98, DQ2 =96, DQ3 =102
5739 11:46:58.064748 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5740 11:46:58.068025 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =90
5741 11:46:58.071545 DQ12 =106, DQ13 =100, DQ14 =104, DQ15 =104
5742 11:46:58.071641
5743 11:46:58.071724
5744 11:46:58.081112 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5745 11:46:58.081216 CH1 RK0: MR19=505, MR18=1C35
5746 11:46:58.087674 CH1_RK0: MR19=0x505, MR18=0x1C35, DQSOSC=405, MR23=63, INC=66, DEC=44
5747 11:46:58.087756
5748 11:46:58.091176 ----->DramcWriteLeveling(PI) begin...
5749 11:46:58.091257 ==
5750 11:46:58.094519 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 11:46:58.100896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 11:46:58.101021 ==
5753 11:46:58.104263 Write leveling (Byte 0): 30 => 30
5754 11:46:58.107448 Write leveling (Byte 1): 28 => 28
5755 11:46:58.107529 DramcWriteLeveling(PI) end<-----
5756 11:46:58.107620
5757 11:46:58.110698 ==
5758 11:46:58.114278 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 11:46:58.117426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 11:46:58.117505 ==
5761 11:46:58.120756 [Gating] SW mode calibration
5762 11:46:58.127279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5763 11:46:58.130417 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5764 11:46:58.137445 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 11:46:58.140692 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 11:46:58.143781 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 11:46:58.150563 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 11:46:58.153758 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 11:46:58.157062 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5770 11:46:58.163319 0 14 24 | B1->B0 | 2f2f 3333 | 0 1 | (0 1) (1 0)
5771 11:46:58.166941 0 14 28 | B1->B0 | 2323 3030 | 0 0 | (1 0) (0 1)
5772 11:46:58.170146 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 11:46:58.176827 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 11:46:58.180147 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 11:46:58.183222 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 11:46:58.189753 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 11:46:58.193059 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 11:46:58.196401 0 15 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5779 11:46:58.202995 0 15 28 | B1->B0 | 4646 3737 | 0 1 | (0 0) (0 0)
5780 11:46:58.206511 1 0 0 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
5781 11:46:58.209364 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 11:46:58.216263 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 11:46:58.219623 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 11:46:58.222836 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 11:46:58.229759 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 11:46:58.232903 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5787 11:46:58.236150 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5788 11:46:58.242512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:46:58.246247 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:46:58.249555 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:46:58.256198 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 11:46:58.259423 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 11:46:58.262481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 11:46:58.269009 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 11:46:58.272623 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 11:46:58.275688 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 11:46:58.282684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 11:46:58.285604 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 11:46:58.289139 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 11:46:58.295653 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 11:46:58.298853 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 11:46:58.302379 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5803 11:46:58.308650 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5804 11:46:58.312123 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 11:46:58.315256 Total UI for P1: 0, mck2ui 16
5806 11:46:58.318635 best dqsien dly found for B0: ( 1, 2, 26)
5807 11:46:58.322402 Total UI for P1: 0, mck2ui 16
5808 11:46:58.325417 best dqsien dly found for B1: ( 1, 2, 26)
5809 11:46:58.328638 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5810 11:46:58.331906 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5811 11:46:58.331990
5812 11:46:58.335546 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 11:46:58.338772 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5814 11:46:58.341910 [Gating] SW calibration Done
5815 11:46:58.342027 ==
5816 11:46:58.345559 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 11:46:58.348756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 11:46:58.352201 ==
5819 11:46:58.352285 RX Vref Scan: 0
5820 11:46:58.352351
5821 11:46:58.355203 RX Vref 0 -> 0, step: 1
5822 11:46:58.355286
5823 11:46:58.358312 RX Delay -80 -> 252, step: 8
5824 11:46:58.361724 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5825 11:46:58.364886 iDelay=200, Bit 1, Center 103 (24 ~ 183) 160
5826 11:46:58.368544 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5827 11:46:58.371678 iDelay=200, Bit 3, Center 107 (24 ~ 191) 168
5828 11:46:58.378195 iDelay=200, Bit 4, Center 107 (24 ~ 191) 168
5829 11:46:58.381581 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5830 11:46:58.384733 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5831 11:46:58.388378 iDelay=200, Bit 7, Center 107 (24 ~ 191) 168
5832 11:46:58.391603 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5833 11:46:58.398125 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5834 11:46:58.401299 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5835 11:46:58.404596 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5836 11:46:58.407748 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5837 11:46:58.411233 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5838 11:46:58.417689 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5839 11:46:58.421146 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5840 11:46:58.421248 ==
5841 11:46:58.424548 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 11:46:58.427639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 11:46:58.427743 ==
5844 11:46:58.427836 DQS Delay:
5845 11:46:58.431298 DQS0 = 0, DQS1 = 0
5846 11:46:58.431396 DQM Delay:
5847 11:46:58.434491 DQM0 = 105, DQM1 = 95
5848 11:46:58.434593 DQ Delay:
5849 11:46:58.437822 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =107
5850 11:46:58.441045 DQ4 =107, DQ5 =111, DQ6 =111, DQ7 =107
5851 11:46:58.444191 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5852 11:46:58.447848 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5853 11:46:58.447948
5854 11:46:58.448038
5855 11:46:58.451006 ==
5856 11:46:58.454270 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 11:46:58.457568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 11:46:58.457643 ==
5859 11:46:58.457706
5860 11:46:58.457766
5861 11:46:58.460629 TX Vref Scan disable
5862 11:46:58.460793 == TX Byte 0 ==
5863 11:46:58.467532 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5864 11:46:58.470732 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5865 11:46:58.470810 == TX Byte 1 ==
5866 11:46:58.477286 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 11:46:58.480562 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 11:46:58.480668 ==
5869 11:46:58.483970 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 11:46:58.487215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 11:46:58.487289 ==
5872 11:46:58.487382
5873 11:46:58.487471
5874 11:46:58.490355 TX Vref Scan disable
5875 11:46:58.493755 == TX Byte 0 ==
5876 11:46:58.496812 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5877 11:46:58.500601 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5878 11:46:58.503668 == TX Byte 1 ==
5879 11:46:58.506969 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5880 11:46:58.510481 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5881 11:46:58.510587
5882 11:46:58.513631 [DATLAT]
5883 11:46:58.513739 Freq=933, CH1 RK1
5884 11:46:58.513834
5885 11:46:58.517066 DATLAT Default: 0xb
5886 11:46:58.517143 0, 0xFFFF, sum = 0
5887 11:46:58.520143 1, 0xFFFF, sum = 0
5888 11:46:58.520217 2, 0xFFFF, sum = 0
5889 11:46:58.523550 3, 0xFFFF, sum = 0
5890 11:46:58.523654 4, 0xFFFF, sum = 0
5891 11:46:58.526929 5, 0xFFFF, sum = 0
5892 11:46:58.527036 6, 0xFFFF, sum = 0
5893 11:46:58.530167 7, 0xFFFF, sum = 0
5894 11:46:58.530247 8, 0xFFFF, sum = 0
5895 11:46:58.533239 9, 0xFFFF, sum = 0
5896 11:46:58.533313 10, 0x0, sum = 1
5897 11:46:58.536540 11, 0x0, sum = 2
5898 11:46:58.536649 12, 0x0, sum = 3
5899 11:46:58.540173 13, 0x0, sum = 4
5900 11:46:58.540251 best_step = 11
5901 11:46:58.540324
5902 11:46:58.540419 ==
5903 11:46:58.543301 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 11:46:58.550038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 11:46:58.550142 ==
5906 11:46:58.550238 RX Vref Scan: 0
5907 11:46:58.550328
5908 11:46:58.553191 RX Vref 0 -> 0, step: 1
5909 11:46:58.553268
5910 11:46:58.556463 RX Delay -53 -> 252, step: 4
5911 11:46:58.559862 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5912 11:46:58.566316 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5913 11:46:58.569597 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5914 11:46:58.573261 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5915 11:46:58.576407 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5916 11:46:58.579268 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5917 11:46:58.586304 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5918 11:46:58.589512 iDelay=199, Bit 7, Center 100 (19 ~ 182) 164
5919 11:46:58.592580 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5920 11:46:58.595836 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5921 11:46:58.599052 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5922 11:46:58.605700 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5923 11:46:58.609252 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5924 11:46:58.612347 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5925 11:46:58.615952 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5926 11:46:58.619028 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5927 11:46:58.619110 ==
5928 11:46:58.622524 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 11:46:58.628938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 11:46:58.629068 ==
5931 11:46:58.629134 DQS Delay:
5932 11:46:58.632374 DQS0 = 0, DQS1 = 0
5933 11:46:58.632446 DQM Delay:
5934 11:46:58.635390 DQM0 = 104, DQM1 = 97
5935 11:46:58.635463 DQ Delay:
5936 11:46:58.638966 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5937 11:46:58.642572 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =100
5938 11:46:58.645776 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =90
5939 11:46:58.648900 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =106
5940 11:46:58.648970
5941 11:46:58.649069
5942 11:46:58.658620 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5943 11:46:58.658695 CH1 RK1: MR19=504, MR18=20FC
5944 11:46:58.665519 CH1_RK1: MR19=0x504, MR18=0x20FC, DQSOSC=411, MR23=63, INC=64, DEC=42
5945 11:46:58.668565 [RxdqsGatingPostProcess] freq 933
5946 11:46:58.675423 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5947 11:46:58.678695 best DQS0 dly(2T, 0.5T) = (0, 10)
5948 11:46:58.681962 best DQS1 dly(2T, 0.5T) = (0, 10)
5949 11:46:58.685119 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5950 11:46:58.688345 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5951 11:46:58.691702 best DQS0 dly(2T, 0.5T) = (0, 10)
5952 11:46:58.691806 best DQS1 dly(2T, 0.5T) = (0, 10)
5953 11:46:58.695338 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5954 11:46:58.698621 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5955 11:46:58.701808 Pre-setting of DQS Precalculation
5956 11:46:58.708198 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5957 11:46:58.714954 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5958 11:46:58.721436 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5959 11:46:58.721542
5960 11:46:58.721636
5961 11:46:58.724672 [Calibration Summary] 1866 Mbps
5962 11:46:58.728192 CH 0, Rank 0
5963 11:46:58.728278 SW Impedance : PASS
5964 11:46:58.731350 DUTY Scan : NO K
5965 11:46:58.734636 ZQ Calibration : PASS
5966 11:46:58.734719 Jitter Meter : NO K
5967 11:46:58.738018 CBT Training : PASS
5968 11:46:58.738100 Write leveling : PASS
5969 11:46:58.741366 RX DQS gating : PASS
5970 11:46:58.744824 RX DQ/DQS(RDDQC) : PASS
5971 11:46:58.744907 TX DQ/DQS : PASS
5972 11:46:58.748092 RX DATLAT : PASS
5973 11:46:58.751384 RX DQ/DQS(Engine): PASS
5974 11:46:58.751467 TX OE : NO K
5975 11:46:58.754631 All Pass.
5976 11:46:58.754714
5977 11:46:58.754779 CH 0, Rank 1
5978 11:46:58.757821 SW Impedance : PASS
5979 11:46:58.757930 DUTY Scan : NO K
5980 11:46:58.760889 ZQ Calibration : PASS
5981 11:46:58.764529 Jitter Meter : NO K
5982 11:46:58.764631 CBT Training : PASS
5983 11:46:58.767788 Write leveling : PASS
5984 11:46:58.770970 RX DQS gating : PASS
5985 11:46:58.771054 RX DQ/DQS(RDDQC) : PASS
5986 11:46:58.774379 TX DQ/DQS : PASS
5987 11:46:58.777644 RX DATLAT : PASS
5988 11:46:58.777726 RX DQ/DQS(Engine): PASS
5989 11:46:58.781341 TX OE : NO K
5990 11:46:58.781424 All Pass.
5991 11:46:58.781490
5992 11:46:58.784589 CH 1, Rank 0
5993 11:46:58.784671 SW Impedance : PASS
5994 11:46:58.787750 DUTY Scan : NO K
5995 11:46:58.790946 ZQ Calibration : PASS
5996 11:46:58.791055 Jitter Meter : NO K
5997 11:46:58.794201 CBT Training : PASS
5998 11:46:58.797259 Write leveling : PASS
5999 11:46:58.797361 RX DQS gating : PASS
6000 11:46:58.800945 RX DQ/DQS(RDDQC) : PASS
6001 11:46:58.801064 TX DQ/DQS : PASS
6002 11:46:58.804115 RX DATLAT : PASS
6003 11:46:58.807644 RX DQ/DQS(Engine): PASS
6004 11:46:58.807727 TX OE : NO K
6005 11:46:58.810846 All Pass.
6006 11:46:58.810929
6007 11:46:58.810994 CH 1, Rank 1
6008 11:46:58.814040 SW Impedance : PASS
6009 11:46:58.814122 DUTY Scan : NO K
6010 11:46:58.817771 ZQ Calibration : PASS
6011 11:46:58.820498 Jitter Meter : NO K
6012 11:46:58.820655 CBT Training : PASS
6013 11:46:58.823810 Write leveling : PASS
6014 11:46:58.827359 RX DQS gating : PASS
6015 11:46:58.827443 RX DQ/DQS(RDDQC) : PASS
6016 11:46:58.830771 TX DQ/DQS : PASS
6017 11:46:58.833822 RX DATLAT : PASS
6018 11:46:58.833905 RX DQ/DQS(Engine): PASS
6019 11:46:58.837250 TX OE : NO K
6020 11:46:58.837333 All Pass.
6021 11:46:58.837399
6022 11:46:58.840667 DramC Write-DBI off
6023 11:46:58.843958 PER_BANK_REFRESH: Hybrid Mode
6024 11:46:58.844041 TX_TRACKING: ON
6025 11:46:58.853866 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6026 11:46:58.856885 [FAST_K] Save calibration result to emmc
6027 11:46:58.860236 dramc_set_vcore_voltage set vcore to 650000
6028 11:46:58.863830 Read voltage for 400, 6
6029 11:46:58.863913 Vio18 = 0
6030 11:46:58.863979 Vcore = 650000
6031 11:46:58.867004 Vdram = 0
6032 11:46:58.867086 Vddq = 0
6033 11:46:58.867152 Vmddr = 0
6034 11:46:58.873872 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6035 11:46:58.876847 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6036 11:46:58.880059 MEM_TYPE=3, freq_sel=20
6037 11:46:58.883390 sv_algorithm_assistance_LP4_800
6038 11:46:58.886861 ============ PULL DRAM RESETB DOWN ============
6039 11:46:58.890084 ========== PULL DRAM RESETB DOWN end =========
6040 11:46:58.896918 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6041 11:46:58.900109 ===================================
6042 11:46:58.903158 LPDDR4 DRAM CONFIGURATION
6043 11:46:58.906447 ===================================
6044 11:46:58.906530 EX_ROW_EN[0] = 0x0
6045 11:46:58.909842 EX_ROW_EN[1] = 0x0
6046 11:46:58.909925 LP4Y_EN = 0x0
6047 11:46:58.912968 WORK_FSP = 0x0
6048 11:46:58.913073 WL = 0x2
6049 11:46:58.916664 RL = 0x2
6050 11:46:58.916774 BL = 0x2
6051 11:46:58.919866 RPST = 0x0
6052 11:46:58.919949 RD_PRE = 0x0
6053 11:46:58.923113 WR_PRE = 0x1
6054 11:46:58.923196 WR_PST = 0x0
6055 11:46:58.926285 DBI_WR = 0x0
6056 11:46:58.926367 DBI_RD = 0x0
6057 11:46:58.929614 OTF = 0x1
6058 11:46:58.932752 ===================================
6059 11:46:58.936203 ===================================
6060 11:46:58.936287 ANA top config
6061 11:46:58.939640 ===================================
6062 11:46:58.942811 DLL_ASYNC_EN = 0
6063 11:46:58.946132 ALL_SLAVE_EN = 1
6064 11:46:58.949623 NEW_RANK_MODE = 1
6065 11:46:58.952934 DLL_IDLE_MODE = 1
6066 11:46:58.953050 LP45_APHY_COMB_EN = 1
6067 11:46:58.955977 TX_ODT_DIS = 1
6068 11:46:58.959169 NEW_8X_MODE = 1
6069 11:46:58.962407 ===================================
6070 11:46:58.965601 ===================================
6071 11:46:58.969300 data_rate = 800
6072 11:46:58.972672 CKR = 1
6073 11:46:58.972756 DQ_P2S_RATIO = 4
6074 11:46:58.975827 ===================================
6075 11:46:58.979242 CA_P2S_RATIO = 4
6076 11:46:58.982316 DQ_CA_OPEN = 0
6077 11:46:58.985860 DQ_SEMI_OPEN = 1
6078 11:46:58.989092 CA_SEMI_OPEN = 1
6079 11:46:58.992449 CA_FULL_RATE = 0
6080 11:46:58.992532 DQ_CKDIV4_EN = 0
6081 11:46:58.995815 CA_CKDIV4_EN = 1
6082 11:46:58.998890 CA_PREDIV_EN = 0
6083 11:46:59.002182 PH8_DLY = 0
6084 11:46:59.005735 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6085 11:46:59.008999 DQ_AAMCK_DIV = 0
6086 11:46:59.009097 CA_AAMCK_DIV = 0
6087 11:46:59.012285 CA_ADMCK_DIV = 4
6088 11:46:59.015461 DQ_TRACK_CA_EN = 0
6089 11:46:59.018839 CA_PICK = 800
6090 11:46:59.021976 CA_MCKIO = 400
6091 11:46:59.025245 MCKIO_SEMI = 400
6092 11:46:59.028678 PLL_FREQ = 3016
6093 11:46:59.032107 DQ_UI_PI_RATIO = 32
6094 11:46:59.032230 CA_UI_PI_RATIO = 32
6095 11:46:59.035354 ===================================
6096 11:46:59.038470 ===================================
6097 11:46:59.042077 memory_type:LPDDR4
6098 11:46:59.045326 GP_NUM : 10
6099 11:46:59.045409 SRAM_EN : 1
6100 11:46:59.048497 MD32_EN : 0
6101 11:46:59.051945 ===================================
6102 11:46:59.054862 [ANA_INIT] >>>>>>>>>>>>>>
6103 11:46:59.058228 <<<<<< [CONFIGURE PHASE]: ANA_TX
6104 11:46:59.061682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6105 11:46:59.065172 ===================================
6106 11:46:59.065255 data_rate = 800,PCW = 0X7400
6107 11:46:59.068508 ===================================
6108 11:46:59.071710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6109 11:46:59.078224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 11:46:59.091282 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6111 11:46:59.094943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6112 11:46:59.097814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6113 11:46:59.101056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6114 11:46:59.104664 [ANA_INIT] flow start
6115 11:46:59.104755 [ANA_INIT] PLL >>>>>>>>
6116 11:46:59.107733 [ANA_INIT] PLL <<<<<<<<
6117 11:46:59.111216 [ANA_INIT] MIDPI >>>>>>>>
6118 11:46:59.114209 [ANA_INIT] MIDPI <<<<<<<<
6119 11:46:59.114287 [ANA_INIT] DLL >>>>>>>>
6120 11:46:59.117865 [ANA_INIT] flow end
6121 11:46:59.121167 ============ LP4 DIFF to SE enter ============
6122 11:46:59.124291 ============ LP4 DIFF to SE exit ============
6123 11:46:59.127639 [ANA_INIT] <<<<<<<<<<<<<
6124 11:46:59.130789 [Flow] Enable top DCM control >>>>>
6125 11:46:59.134476 [Flow] Enable top DCM control <<<<<
6126 11:46:59.137645 Enable DLL master slave shuffle
6127 11:46:59.144057 ==============================================================
6128 11:46:59.144141 Gating Mode config
6129 11:46:59.150725 ==============================================================
6130 11:46:59.150809 Config description:
6131 11:46:59.160930 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6132 11:46:59.167084 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6133 11:46:59.173985 SELPH_MODE 0: By rank 1: By Phase
6134 11:46:59.176935 ==============================================================
6135 11:46:59.180243 GAT_TRACK_EN = 0
6136 11:46:59.184166 RX_GATING_MODE = 2
6137 11:46:59.187220 RX_GATING_TRACK_MODE = 2
6138 11:46:59.190345 SELPH_MODE = 1
6139 11:46:59.193636 PICG_EARLY_EN = 1
6140 11:46:59.196876 VALID_LAT_VALUE = 1
6141 11:46:59.203840 ==============================================================
6142 11:46:59.207007 Enter into Gating configuration >>>>
6143 11:46:59.210171 Exit from Gating configuration <<<<
6144 11:46:59.213622 Enter into DVFS_PRE_config >>>>>
6145 11:46:59.223326 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6146 11:46:59.226935 Exit from DVFS_PRE_config <<<<<
6147 11:46:59.230208 Enter into PICG configuration >>>>
6148 11:46:59.233403 Exit from PICG configuration <<<<
6149 11:46:59.236754 [RX_INPUT] configuration >>>>>
6150 11:46:59.236863 [RX_INPUT] configuration <<<<<
6151 11:46:59.243100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6152 11:46:59.250025 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6153 11:46:59.253085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 11:46:59.259878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 11:46:59.266592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6156 11:46:59.273230 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6157 11:46:59.276562 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6158 11:46:59.279770 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6159 11:46:59.286337 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6160 11:46:59.289639 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6161 11:46:59.292730 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6162 11:46:59.299378 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 11:46:59.302608 ===================================
6164 11:46:59.302701 LPDDR4 DRAM CONFIGURATION
6165 11:46:59.306222 ===================================
6166 11:46:59.309595 EX_ROW_EN[0] = 0x0
6167 11:46:59.309671 EX_ROW_EN[1] = 0x0
6168 11:46:59.312385 LP4Y_EN = 0x0
6169 11:46:59.315984 WORK_FSP = 0x0
6170 11:46:59.316056 WL = 0x2
6171 11:46:59.319153 RL = 0x2
6172 11:46:59.319228 BL = 0x2
6173 11:46:59.322481 RPST = 0x0
6174 11:46:59.322562 RD_PRE = 0x0
6175 11:46:59.325738 WR_PRE = 0x1
6176 11:46:59.325811 WR_PST = 0x0
6177 11:46:59.328969 DBI_WR = 0x0
6178 11:46:59.329052 DBI_RD = 0x0
6179 11:46:59.332740 OTF = 0x1
6180 11:46:59.335932 ===================================
6181 11:46:59.339052 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6182 11:46:59.342600 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6183 11:46:59.349011 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 11:46:59.352288 ===================================
6185 11:46:59.352372 LPDDR4 DRAM CONFIGURATION
6186 11:46:59.355735 ===================================
6187 11:46:59.359256 EX_ROW_EN[0] = 0x10
6188 11:46:59.359340 EX_ROW_EN[1] = 0x0
6189 11:46:59.362099 LP4Y_EN = 0x0
6190 11:46:59.365684 WORK_FSP = 0x0
6191 11:46:59.365768 WL = 0x2
6192 11:46:59.368931 RL = 0x2
6193 11:46:59.369052 BL = 0x2
6194 11:46:59.372134 RPST = 0x0
6195 11:46:59.372218 RD_PRE = 0x0
6196 11:46:59.375489 WR_PRE = 0x1
6197 11:46:59.375639 WR_PST = 0x0
6198 11:46:59.378418 DBI_WR = 0x0
6199 11:46:59.378526 DBI_RD = 0x0
6200 11:46:59.381865 OTF = 0x1
6201 11:46:59.385236 ===================================
6202 11:46:59.392019 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6203 11:46:59.395520 nWR fixed to 30
6204 11:46:59.395625 [ModeRegInit_LP4] CH0 RK0
6205 11:46:59.398598 [ModeRegInit_LP4] CH0 RK1
6206 11:46:59.402161 [ModeRegInit_LP4] CH1 RK0
6207 11:46:59.405128 [ModeRegInit_LP4] CH1 RK1
6208 11:46:59.405199 match AC timing 19
6209 11:46:59.408826 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6210 11:46:59.415510 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6211 11:46:59.418612 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6212 11:46:59.421884 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6213 11:46:59.428379 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6214 11:46:59.428483 ==
6215 11:46:59.431603 Dram Type= 6, Freq= 0, CH_0, rank 0
6216 11:46:59.434835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6217 11:46:59.434938 ==
6218 11:46:59.441901 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6219 11:46:59.448276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6220 11:46:59.451920 [CA 0] Center 36 (8~64) winsize 57
6221 11:46:59.452000 [CA 1] Center 36 (8~64) winsize 57
6222 11:46:59.455100 [CA 2] Center 36 (8~64) winsize 57
6223 11:46:59.458215 [CA 3] Center 36 (8~64) winsize 57
6224 11:46:59.461657 [CA 4] Center 36 (8~64) winsize 57
6225 11:46:59.464810 [CA 5] Center 36 (8~64) winsize 57
6226 11:46:59.464911
6227 11:46:59.467945 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6228 11:46:59.468071
6229 11:46:59.471377 [CATrainingPosCal] consider 1 rank data
6230 11:46:59.474868 u2DelayCellTimex100 = 270/100 ps
6231 11:46:59.478066 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 11:46:59.484638 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 11:46:59.488144 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 11:46:59.491370 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 11:46:59.494374 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 11:46:59.497759 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 11:46:59.498113
6238 11:46:59.501445 CA PerBit enable=1, Macro0, CA PI delay=36
6239 11:46:59.501744
6240 11:46:59.504925 [CBTSetCACLKResult] CA Dly = 36
6241 11:46:59.508109 CS Dly: 1 (0~32)
6242 11:46:59.508468 ==
6243 11:46:59.511187 Dram Type= 6, Freq= 0, CH_0, rank 1
6244 11:46:59.514951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 11:46:59.515459 ==
6246 11:46:59.521385 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 11:46:59.524534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6248 11:46:59.527883 [CA 0] Center 36 (8~64) winsize 57
6249 11:46:59.531043 [CA 1] Center 36 (8~64) winsize 57
6250 11:46:59.534643 [CA 2] Center 36 (8~64) winsize 57
6251 11:46:59.537889 [CA 3] Center 36 (8~64) winsize 57
6252 11:46:59.541061 [CA 4] Center 36 (8~64) winsize 57
6253 11:46:59.544087 [CA 5] Center 36 (8~64) winsize 57
6254 11:46:59.544458
6255 11:46:59.547855 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6256 11:46:59.548358
6257 11:46:59.550994 [CATrainingPosCal] consider 2 rank data
6258 11:46:59.554300 u2DelayCellTimex100 = 270/100 ps
6259 11:46:59.557456 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 11:46:59.560666 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 11:46:59.567605 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 11:46:59.570960 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 11:46:59.574144 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 11:46:59.577571 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 11:46:59.578126
6266 11:46:59.580892 CA PerBit enable=1, Macro0, CA PI delay=36
6267 11:46:59.581540
6268 11:46:59.583724 [CBTSetCACLKResult] CA Dly = 36
6269 11:46:59.584240 CS Dly: 1 (0~32)
6270 11:46:59.584708
6271 11:46:59.587394 ----->DramcWriteLeveling(PI) begin...
6272 11:46:59.590634 ==
6273 11:46:59.593800 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 11:46:59.597275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 11:46:59.597705 ==
6276 11:46:59.600553 Write leveling (Byte 0): 40 => 8
6277 11:46:59.603825 Write leveling (Byte 1): 32 => 0
6278 11:46:59.607145 DramcWriteLeveling(PI) end<-----
6279 11:46:59.607642
6280 11:46:59.608013 ==
6281 11:46:59.610188 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 11:46:59.613333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 11:46:59.613843 ==
6284 11:46:59.616870 [Gating] SW mode calibration
6285 11:46:59.623585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6286 11:46:59.629988 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6287 11:46:59.633260 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 11:46:59.637050 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 11:46:59.643497 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 11:46:59.646897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 11:46:59.649939 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 11:46:59.657022 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 11:46:59.660133 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 11:46:59.663381 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 11:46:59.669823 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 11:46:59.670463 Total UI for P1: 0, mck2ui 16
6297 11:46:59.672956 best dqsien dly found for B0: ( 0, 14, 24)
6298 11:46:59.676419 Total UI for P1: 0, mck2ui 16
6299 11:46:59.679570 best dqsien dly found for B1: ( 0, 14, 24)
6300 11:46:59.686250 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6301 11:46:59.689683 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6302 11:46:59.690113
6303 11:46:59.692961 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 11:46:59.695838 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6305 11:46:59.699566 [Gating] SW calibration Done
6306 11:46:59.700136 ==
6307 11:46:59.702490 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 11:46:59.705870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 11:46:59.706268 ==
6310 11:46:59.708985 RX Vref Scan: 0
6311 11:46:59.709061
6312 11:46:59.709122 RX Vref 0 -> 0, step: 1
6313 11:46:59.709185
6314 11:46:59.712467 RX Delay -410 -> 252, step: 16
6315 11:46:59.719035 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6316 11:46:59.722030 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6317 11:46:59.725717 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6318 11:46:59.728632 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6319 11:46:59.735495 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6320 11:46:59.738754 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6321 11:46:59.742000 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6322 11:46:59.745242 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6323 11:46:59.752080 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6324 11:46:59.755299 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6325 11:46:59.758568 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6326 11:46:59.761872 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6327 11:46:59.768789 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6328 11:46:59.771893 iDelay=230, Bit 13, Center -35 (-266 ~ 197) 464
6329 11:46:59.775024 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6330 11:46:59.778288 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6331 11:46:59.781582 ==
6332 11:46:59.785278 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 11:46:59.788217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 11:46:59.788315 ==
6335 11:46:59.788403 DQS Delay:
6336 11:46:59.791483 DQS0 = 27, DQS1 = 43
6337 11:46:59.791577 DQM Delay:
6338 11:46:59.794987 DQM0 = 11, DQM1 = 11
6339 11:46:59.795085 DQ Delay:
6340 11:46:59.798305 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6341 11:46:59.801612 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6342 11:46:59.804758 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6343 11:46:59.808146 DQ12 =16, DQ13 =8, DQ14 =24, DQ15 =16
6344 11:46:59.808239
6345 11:46:59.808324
6346 11:46:59.808408 ==
6347 11:46:59.811663 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 11:46:59.814838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 11:46:59.814906 ==
6350 11:46:59.814963
6351 11:46:59.815018
6352 11:46:59.818232 TX Vref Scan disable
6353 11:46:59.818312 == TX Byte 0 ==
6354 11:46:59.824891 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 11:46:59.828229 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 11:46:59.828328 == TX Byte 1 ==
6357 11:46:59.834461 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6358 11:46:59.838149 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6359 11:46:59.838245 ==
6360 11:46:59.841200 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 11:46:59.844698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 11:46:59.844768 ==
6363 11:46:59.844829
6364 11:46:59.844887
6365 11:46:59.847899 TX Vref Scan disable
6366 11:46:59.851227 == TX Byte 0 ==
6367 11:46:59.854445 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 11:46:59.857725 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 11:46:59.857820 == TX Byte 1 ==
6370 11:46:59.864433 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6371 11:46:59.868010 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6372 11:46:59.868082
6373 11:46:59.868142 [DATLAT]
6374 11:46:59.871121 Freq=400, CH0 RK0
6375 11:46:59.871215
6376 11:46:59.871303 DATLAT Default: 0xf
6377 11:46:59.874308 0, 0xFFFF, sum = 0
6378 11:46:59.874377 1, 0xFFFF, sum = 0
6379 11:46:59.878001 2, 0xFFFF, sum = 0
6380 11:46:59.881167 3, 0xFFFF, sum = 0
6381 11:46:59.881240 4, 0xFFFF, sum = 0
6382 11:46:59.884488 5, 0xFFFF, sum = 0
6383 11:46:59.884584 6, 0xFFFF, sum = 0
6384 11:46:59.887688 7, 0xFFFF, sum = 0
6385 11:46:59.887788 8, 0xFFFF, sum = 0
6386 11:46:59.890975 9, 0xFFFF, sum = 0
6387 11:46:59.891074 10, 0xFFFF, sum = 0
6388 11:46:59.894145 11, 0xFFFF, sum = 0
6389 11:46:59.894259 12, 0xFFFF, sum = 0
6390 11:46:59.897695 13, 0x0, sum = 1
6391 11:46:59.897772 14, 0x0, sum = 2
6392 11:46:59.900836 15, 0x0, sum = 3
6393 11:46:59.900933 16, 0x0, sum = 4
6394 11:46:59.904189 best_step = 14
6395 11:46:59.904260
6396 11:46:59.904319 ==
6397 11:46:59.907478 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 11:46:59.910569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 11:46:59.910665 ==
6400 11:46:59.914046 RX Vref Scan: 1
6401 11:46:59.914262
6402 11:46:59.914394 RX Vref 0 -> 0, step: 1
6403 11:46:59.914516
6404 11:46:59.917138 RX Delay -327 -> 252, step: 8
6405 11:46:59.917234
6406 11:46:59.920573 Set Vref, RX VrefLevel [Byte0]: 58
6407 11:46:59.924071 [Byte1]: 48
6408 11:46:59.928036
6409 11:46:59.928119 Final RX Vref Byte 0 = 58 to rank0
6410 11:46:59.931429 Final RX Vref Byte 1 = 48 to rank0
6411 11:46:59.934907 Final RX Vref Byte 0 = 58 to rank1
6412 11:46:59.937904 Final RX Vref Byte 1 = 48 to rank1==
6413 11:46:59.941548 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 11:46:59.948286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 11:46:59.948371 ==
6416 11:46:59.948474 DQS Delay:
6417 11:46:59.951611 DQS0 = 24, DQS1 = 48
6418 11:46:59.951695 DQM Delay:
6419 11:46:59.951761 DQM0 = 8, DQM1 = 15
6420 11:46:59.954412 DQ Delay:
6421 11:46:59.958132 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6422 11:46:59.958215 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6423 11:46:59.961409 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6424 11:46:59.964607 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6425 11:46:59.964690
6426 11:46:59.967889
6427 11:46:59.974544 [DQSOSCAuto] RK0, (LSB)MR18= 0xaba3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6428 11:46:59.977741 CH0 RK0: MR19=C0C, MR18=ABA3
6429 11:46:59.984394 CH0_RK0: MR19=0xC0C, MR18=0xABA3, DQSOSC=388, MR23=63, INC=392, DEC=261
6430 11:46:59.984479 ==
6431 11:46:59.987599 Dram Type= 6, Freq= 0, CH_0, rank 1
6432 11:46:59.990803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 11:46:59.990887 ==
6434 11:46:59.994062 [Gating] SW mode calibration
6435 11:47:00.000639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6436 11:47:00.007303 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6437 11:47:00.010691 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 11:47:00.014154 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 11:47:00.020777 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 11:47:00.023660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 11:47:00.027226 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 11:47:00.033687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 11:47:00.037041 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 11:47:00.040189 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 11:47:00.046706 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 11:47:00.046815 Total UI for P1: 0, mck2ui 16
6447 11:47:00.053297 best dqsien dly found for B0: ( 0, 14, 24)
6448 11:47:00.053380 Total UI for P1: 0, mck2ui 16
6449 11:47:00.060290 best dqsien dly found for B1: ( 0, 14, 24)
6450 11:47:00.063350 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6451 11:47:00.066652 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6452 11:47:00.066755
6453 11:47:00.069800 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 11:47:00.073106 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6455 11:47:00.076301 [Gating] SW calibration Done
6456 11:47:00.076384 ==
6457 11:47:00.079969 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 11:47:00.083089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 11:47:00.083181 ==
6460 11:47:00.086450 RX Vref Scan: 0
6461 11:47:00.086533
6462 11:47:00.086607 RX Vref 0 -> 0, step: 1
6463 11:47:00.089701
6464 11:47:00.089777 RX Delay -410 -> 252, step: 16
6465 11:47:00.095953 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6466 11:47:00.099539 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6467 11:47:00.102776 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6468 11:47:00.109228 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6469 11:47:00.112367 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6470 11:47:00.116062 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6471 11:47:00.118889 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6472 11:47:00.125832 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6473 11:47:00.129203 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6474 11:47:00.132345 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6475 11:47:00.135816 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6476 11:47:00.142195 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6477 11:47:00.145801 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6478 11:47:00.149243 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6479 11:47:00.152266 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6480 11:47:00.159115 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6481 11:47:00.159223 ==
6482 11:47:00.162374 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 11:47:00.165191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 11:47:00.165366 ==
6485 11:47:00.165462 DQS Delay:
6486 11:47:00.168521 DQS0 = 27, DQS1 = 35
6487 11:47:00.168618 DQM Delay:
6488 11:47:00.172115 DQM0 = 11, DQM1 = 9
6489 11:47:00.172211 DQ Delay:
6490 11:47:00.175383 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6491 11:47:00.178799 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6492 11:47:00.182078 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6493 11:47:00.185311 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6494 11:47:00.185393
6495 11:47:00.185459
6496 11:47:00.185518 ==
6497 11:47:00.188429 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 11:47:00.192034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 11:47:00.192118 ==
6500 11:47:00.192184
6501 11:47:00.192244
6502 11:47:00.195179 TX Vref Scan disable
6503 11:47:00.195288 == TX Byte 0 ==
6504 11:47:00.201904 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6505 11:47:00.205105 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6506 11:47:00.205182 == TX Byte 1 ==
6507 11:47:00.211875 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6508 11:47:00.215084 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6509 11:47:00.215168 ==
6510 11:47:00.218329 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 11:47:00.221458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 11:47:00.221558 ==
6513 11:47:00.221633
6514 11:47:00.221694
6515 11:47:00.225073 TX Vref Scan disable
6516 11:47:00.225197 == TX Byte 0 ==
6517 11:47:00.231765 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6518 11:47:00.234932 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6519 11:47:00.235016 == TX Byte 1 ==
6520 11:47:00.241544 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6521 11:47:00.244797 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6522 11:47:00.244884
6523 11:47:00.244950 [DATLAT]
6524 11:47:00.248062 Freq=400, CH0 RK1
6525 11:47:00.248145
6526 11:47:00.248210 DATLAT Default: 0xe
6527 11:47:00.251461 0, 0xFFFF, sum = 0
6528 11:47:00.251575 1, 0xFFFF, sum = 0
6529 11:47:00.254501 2, 0xFFFF, sum = 0
6530 11:47:00.254614 3, 0xFFFF, sum = 0
6531 11:47:00.257849 4, 0xFFFF, sum = 0
6532 11:47:00.257962 5, 0xFFFF, sum = 0
6533 11:47:00.261290 6, 0xFFFF, sum = 0
6534 11:47:00.264347 7, 0xFFFF, sum = 0
6535 11:47:00.264544 8, 0xFFFF, sum = 0
6536 11:47:00.267924 9, 0xFFFF, sum = 0
6537 11:47:00.268008 10, 0xFFFF, sum = 0
6538 11:47:00.271031 11, 0xFFFF, sum = 0
6539 11:47:00.271115 12, 0xFFFF, sum = 0
6540 11:47:00.274291 13, 0x0, sum = 1
6541 11:47:00.274368 14, 0x0, sum = 2
6542 11:47:00.277671 15, 0x0, sum = 3
6543 11:47:00.277755 16, 0x0, sum = 4
6544 11:47:00.281099 best_step = 14
6545 11:47:00.281182
6546 11:47:00.281247 ==
6547 11:47:00.284274 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 11:47:00.287602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 11:47:00.287687 ==
6550 11:47:00.287753 RX Vref Scan: 0
6551 11:47:00.291101
6552 11:47:00.291209 RX Vref 0 -> 0, step: 1
6553 11:47:00.291309
6554 11:47:00.294135 RX Delay -311 -> 252, step: 8
6555 11:47:00.301590 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6556 11:47:00.304706 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6557 11:47:00.308314 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6558 11:47:00.314545 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6559 11:47:00.317761 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6560 11:47:00.321126 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6561 11:47:00.324421 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6562 11:47:00.331297 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6563 11:47:00.334583 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6564 11:47:00.338015 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6565 11:47:00.341180 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6566 11:47:00.347809 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6567 11:47:00.351149 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6568 11:47:00.354488 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6569 11:47:00.357703 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6570 11:47:00.364317 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6571 11:47:00.364405 ==
6572 11:47:00.367736 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 11:47:00.371194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 11:47:00.371306 ==
6575 11:47:00.371372 DQS Delay:
6576 11:47:00.374292 DQS0 = 28, DQS1 = 44
6577 11:47:00.374376 DQM Delay:
6578 11:47:00.377561 DQM0 = 9, DQM1 = 15
6579 11:47:00.377673 DQ Delay:
6580 11:47:00.380924 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6581 11:47:00.384149 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6582 11:47:00.387303 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6583 11:47:00.390586 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6584 11:47:00.390670
6585 11:47:00.390743
6586 11:47:00.397379 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6587 11:47:00.400542 CH0 RK1: MR19=C0C, MR18=BD71
6588 11:47:00.407114 CH0_RK1: MR19=0xC0C, MR18=0xBD71, DQSOSC=386, MR23=63, INC=396, DEC=264
6589 11:47:00.410336 [RxdqsGatingPostProcess] freq 400
6590 11:47:00.417102 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6591 11:47:00.420298 best DQS0 dly(2T, 0.5T) = (0, 10)
6592 11:47:00.423612 best DQS1 dly(2T, 0.5T) = (0, 10)
6593 11:47:00.427167 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6594 11:47:00.427251 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6595 11:47:00.430389 best DQS0 dly(2T, 0.5T) = (0, 10)
6596 11:47:00.433630 best DQS1 dly(2T, 0.5T) = (0, 10)
6597 11:47:00.437096 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6598 11:47:00.440461 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6599 11:47:00.443791 Pre-setting of DQS Precalculation
6600 11:47:00.450243 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6601 11:47:00.450325 ==
6602 11:47:00.453727 Dram Type= 6, Freq= 0, CH_1, rank 0
6603 11:47:00.456776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 11:47:00.456885 ==
6605 11:47:00.463408 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6606 11:47:00.470150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6607 11:47:00.470232 [CA 0] Center 36 (8~64) winsize 57
6608 11:47:00.473489 [CA 1] Center 36 (8~64) winsize 57
6609 11:47:00.476900 [CA 2] Center 36 (8~64) winsize 57
6610 11:47:00.479821 [CA 3] Center 36 (8~64) winsize 57
6611 11:47:00.483107 [CA 4] Center 36 (8~64) winsize 57
6612 11:47:00.486361 [CA 5] Center 36 (8~64) winsize 57
6613 11:47:00.486436
6614 11:47:00.490022 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6615 11:47:00.490136
6616 11:47:00.493410 [CATrainingPosCal] consider 1 rank data
6617 11:47:00.496585 u2DelayCellTimex100 = 270/100 ps
6618 11:47:00.499708 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 11:47:00.506530 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 11:47:00.509714 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 11:47:00.512815 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 11:47:00.515943 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 11:47:00.519174 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 11:47:00.519265
6625 11:47:00.522692 CA PerBit enable=1, Macro0, CA PI delay=36
6626 11:47:00.522777
6627 11:47:00.526000 [CBTSetCACLKResult] CA Dly = 36
6628 11:47:00.529107 CS Dly: 1 (0~32)
6629 11:47:00.529179 ==
6630 11:47:00.532752 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 11:47:00.535927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 11:47:00.536002 ==
6633 11:47:00.542685 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 11:47:00.545852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6635 11:47:00.549519 [CA 0] Center 36 (8~64) winsize 57
6636 11:47:00.552728 [CA 1] Center 36 (8~64) winsize 57
6637 11:47:00.556002 [CA 2] Center 36 (8~64) winsize 57
6638 11:47:00.559126 [CA 3] Center 36 (8~64) winsize 57
6639 11:47:00.562631 [CA 4] Center 36 (8~64) winsize 57
6640 11:47:00.565810 [CA 5] Center 36 (8~64) winsize 57
6641 11:47:00.565884
6642 11:47:00.569026 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6643 11:47:00.569098
6644 11:47:00.572658 [CATrainingPosCal] consider 2 rank data
6645 11:47:00.575702 u2DelayCellTimex100 = 270/100 ps
6646 11:47:00.578998 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 11:47:00.582249 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 11:47:00.588944 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 11:47:00.592236 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 11:47:00.595532 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 11:47:00.598813 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 11:47:00.598894
6653 11:47:00.602025 CA PerBit enable=1, Macro0, CA PI delay=36
6654 11:47:00.602106
6655 11:47:00.605439 [CBTSetCACLKResult] CA Dly = 36
6656 11:47:00.605525 CS Dly: 1 (0~32)
6657 11:47:00.605591
6658 11:47:00.608665 ----->DramcWriteLeveling(PI) begin...
6659 11:47:00.612312 ==
6660 11:47:00.612406 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 11:47:00.618663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 11:47:00.618748 ==
6663 11:47:00.622308 Write leveling (Byte 0): 40 => 8
6664 11:47:00.625266 Write leveling (Byte 1): 32 => 0
6665 11:47:00.625351 DramcWriteLeveling(PI) end<-----
6666 11:47:00.628576
6667 11:47:00.628660 ==
6668 11:47:00.632142 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 11:47:00.635332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 11:47:00.635422 ==
6671 11:47:00.638658 [Gating] SW mode calibration
6672 11:47:00.645306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6673 11:47:00.648646 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6674 11:47:00.654823 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 11:47:00.658527 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6676 11:47:00.661762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 11:47:00.668294 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 11:47:00.671674 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 11:47:00.675190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 11:47:00.681592 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 11:47:00.684889 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 11:47:00.688313 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 11:47:00.691698 Total UI for P1: 0, mck2ui 16
6684 11:47:00.694940 best dqsien dly found for B0: ( 0, 14, 24)
6685 11:47:00.698106 Total UI for P1: 0, mck2ui 16
6686 11:47:00.701826 best dqsien dly found for B1: ( 0, 14, 24)
6687 11:47:00.704956 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6688 11:47:00.711561 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6689 11:47:00.711667
6690 11:47:00.714769 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 11:47:00.717864 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 11:47:00.721443 [Gating] SW calibration Done
6693 11:47:00.721526 ==
6694 11:47:00.724604 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 11:47:00.727833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 11:47:00.727959 ==
6697 11:47:00.731399 RX Vref Scan: 0
6698 11:47:00.731481
6699 11:47:00.731546 RX Vref 0 -> 0, step: 1
6700 11:47:00.731607
6701 11:47:00.734567 RX Delay -410 -> 252, step: 16
6702 11:47:00.737766 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6703 11:47:00.744184 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6704 11:47:00.747725 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6705 11:47:00.750920 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6706 11:47:00.754069 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6707 11:47:00.760551 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6708 11:47:00.764006 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6709 11:47:00.767298 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6710 11:47:00.773853 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6711 11:47:00.777449 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6712 11:47:00.780692 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6713 11:47:00.783890 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6714 11:47:00.790455 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6715 11:47:00.793715 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6716 11:47:00.797014 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6717 11:47:00.800250 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6718 11:47:00.803639 ==
6719 11:47:00.803748 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 11:47:00.810109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 11:47:00.810193 ==
6722 11:47:00.810258 DQS Delay:
6723 11:47:00.813558 DQS0 = 19, DQS1 = 35
6724 11:47:00.813641 DQM Delay:
6725 11:47:00.816756 DQM0 = 2, DQM1 = 13
6726 11:47:00.816889 DQ Delay:
6727 11:47:00.820051 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6728 11:47:00.823269 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6729 11:47:00.823352 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6730 11:47:00.830157 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6731 11:47:00.830276
6732 11:47:00.830374
6733 11:47:00.830467 ==
6734 11:47:00.833357 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 11:47:00.836829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 11:47:00.836905 ==
6737 11:47:00.836980
6738 11:47:00.837074
6739 11:47:00.840085 TX Vref Scan disable
6740 11:47:00.840157 == TX Byte 0 ==
6741 11:47:00.843232 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 11:47:00.849937 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 11:47:00.850036 == TX Byte 1 ==
6744 11:47:00.853392 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6745 11:47:00.859745 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6746 11:47:00.859851 ==
6747 11:47:00.862978 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 11:47:00.866657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 11:47:00.866737 ==
6750 11:47:00.866822
6751 11:47:00.866921
6752 11:47:00.869930 TX Vref Scan disable
6753 11:47:00.870118 == TX Byte 0 ==
6754 11:47:00.876679 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 11:47:00.879812 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 11:47:00.879913 == TX Byte 1 ==
6757 11:47:00.886254 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6758 11:47:00.889579 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6759 11:47:00.889663
6760 11:47:00.889731 [DATLAT]
6761 11:47:00.892805 Freq=400, CH1 RK0
6762 11:47:00.892905
6763 11:47:00.893002 DATLAT Default: 0xf
6764 11:47:00.896403 0, 0xFFFF, sum = 0
6765 11:47:00.896476 1, 0xFFFF, sum = 0
6766 11:47:00.899712 2, 0xFFFF, sum = 0
6767 11:47:00.899815 3, 0xFFFF, sum = 0
6768 11:47:00.902776 4, 0xFFFF, sum = 0
6769 11:47:00.902850 5, 0xFFFF, sum = 0
6770 11:47:00.906244 6, 0xFFFF, sum = 0
6771 11:47:00.906350 7, 0xFFFF, sum = 0
6772 11:47:00.909391 8, 0xFFFF, sum = 0
6773 11:47:00.912901 9, 0xFFFF, sum = 0
6774 11:47:00.913020 10, 0xFFFF, sum = 0
6775 11:47:00.915984 11, 0xFFFF, sum = 0
6776 11:47:00.916092 12, 0xFFFF, sum = 0
6777 11:47:00.919577 13, 0x0, sum = 1
6778 11:47:00.919693 14, 0x0, sum = 2
6779 11:47:00.922786 15, 0x0, sum = 3
6780 11:47:00.922873 16, 0x0, sum = 4
6781 11:47:00.922941 best_step = 14
6782 11:47:00.926130
6783 11:47:00.926243 ==
6784 11:47:00.929325 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 11:47:00.932567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 11:47:00.932682 ==
6787 11:47:00.932788 RX Vref Scan: 1
6788 11:47:00.932883
6789 11:47:00.936133 RX Vref 0 -> 0, step: 1
6790 11:47:00.936239
6791 11:47:00.939204 RX Delay -311 -> 252, step: 8
6792 11:47:00.939308
6793 11:47:00.942383 Set Vref, RX VrefLevel [Byte0]: 53
6794 11:47:00.945958 [Byte1]: 53
6795 11:47:00.949684
6796 11:47:00.949798 Final RX Vref Byte 0 = 53 to rank0
6797 11:47:00.952913 Final RX Vref Byte 1 = 53 to rank0
6798 11:47:00.956464 Final RX Vref Byte 0 = 53 to rank1
6799 11:47:00.959741 Final RX Vref Byte 1 = 53 to rank1==
6800 11:47:00.963006 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 11:47:00.969430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 11:47:00.969517 ==
6803 11:47:00.969584 DQS Delay:
6804 11:47:00.973141 DQS0 = 28, DQS1 = 40
6805 11:47:00.973226 DQM Delay:
6806 11:47:00.973293 DQM0 = 7, DQM1 = 12
6807 11:47:00.976244 DQ Delay:
6808 11:47:00.979640 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6809 11:47:00.979725 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6810 11:47:00.983050 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6811 11:47:00.986412 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6812 11:47:00.986498
6813 11:47:00.986568
6814 11:47:00.995886 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6815 11:47:00.999302 CH1 RK0: MR19=C0C, MR18=8FC9
6816 11:47:01.006007 CH1_RK0: MR19=0xC0C, MR18=0x8FC9, DQSOSC=384, MR23=63, INC=400, DEC=267
6817 11:47:01.006092 ==
6818 11:47:01.009183 Dram Type= 6, Freq= 0, CH_1, rank 1
6819 11:47:01.012608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 11:47:01.012717 ==
6821 11:47:01.015955 [Gating] SW mode calibration
6822 11:47:01.022511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6823 11:47:01.029091 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6824 11:47:01.032432 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 11:47:01.035933 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6826 11:47:01.042317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 11:47:01.045763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 11:47:01.049139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 11:47:01.055525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 11:47:01.058613 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 11:47:01.062198 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 11:47:01.068510 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6833 11:47:01.068593 Total UI for P1: 0, mck2ui 16
6834 11:47:01.072151 best dqsien dly found for B0: ( 0, 14, 24)
6835 11:47:01.075310 Total UI for P1: 0, mck2ui 16
6836 11:47:01.078713 best dqsien dly found for B1: ( 0, 14, 24)
6837 11:47:01.084960 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6838 11:47:01.088446 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6839 11:47:01.088542
6840 11:47:01.091700 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 11:47:01.094954 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6842 11:47:01.098295 [Gating] SW calibration Done
6843 11:47:01.098404 ==
6844 11:47:01.101775 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 11:47:01.104859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 11:47:01.104970 ==
6847 11:47:01.108148 RX Vref Scan: 0
6848 11:47:01.108247
6849 11:47:01.108338 RX Vref 0 -> 0, step: 1
6850 11:47:01.108426
6851 11:47:01.111451 RX Delay -410 -> 252, step: 16
6852 11:47:01.118241 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6853 11:47:01.121530 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6854 11:47:01.124778 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6855 11:47:01.128047 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6856 11:47:01.134755 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6857 11:47:01.138009 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6858 11:47:01.141264 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6859 11:47:01.144627 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6860 11:47:01.151285 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6861 11:47:01.154169 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6862 11:47:01.157864 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6863 11:47:01.161105 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6864 11:47:01.167383 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6865 11:47:01.170712 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6866 11:47:01.174008 iDelay=230, Bit 14, Center -19 (-266 ~ 229) 496
6867 11:47:01.180944 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6868 11:47:01.181074 ==
6869 11:47:01.184283 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 11:47:01.187436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 11:47:01.187546 ==
6872 11:47:01.187643 DQS Delay:
6873 11:47:01.190691 DQS0 = 35, DQS1 = 43
6874 11:47:01.190799 DQM Delay:
6875 11:47:01.193931 DQM0 = 16, DQM1 = 20
6876 11:47:01.194028 DQ Delay:
6877 11:47:01.197210 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6878 11:47:01.200546 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6879 11:47:01.204146 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6880 11:47:01.207137 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6881 11:47:01.207233
6882 11:47:01.207320
6883 11:47:01.207406 ==
6884 11:47:01.210328 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 11:47:01.213575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 11:47:01.213645 ==
6887 11:47:01.213707
6888 11:47:01.217204
6889 11:47:01.217270 TX Vref Scan disable
6890 11:47:01.220498 == TX Byte 0 ==
6891 11:47:01.223681 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6892 11:47:01.226827 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6893 11:47:01.230184 == TX Byte 1 ==
6894 11:47:01.233554 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6895 11:47:01.236946 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6896 11:47:01.237058 ==
6897 11:47:01.240161 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 11:47:01.243817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 11:47:01.243890 ==
6900 11:47:01.246907
6901 11:47:01.246989
6902 11:47:01.247054 TX Vref Scan disable
6903 11:47:01.250132 == TX Byte 0 ==
6904 11:47:01.253665 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6905 11:47:01.256885 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6906 11:47:01.260242 == TX Byte 1 ==
6907 11:47:01.263404 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6908 11:47:01.266500 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6909 11:47:01.266614
6910 11:47:01.266705 [DATLAT]
6911 11:47:01.269893 Freq=400, CH1 RK1
6912 11:47:01.270006
6913 11:47:01.273084 DATLAT Default: 0xe
6914 11:47:01.273194 0, 0xFFFF, sum = 0
6915 11:47:01.276695 1, 0xFFFF, sum = 0
6916 11:47:01.276809 2, 0xFFFF, sum = 0
6917 11:47:01.280027 3, 0xFFFF, sum = 0
6918 11:47:01.280129 4, 0xFFFF, sum = 0
6919 11:47:01.283209 5, 0xFFFF, sum = 0
6920 11:47:01.283293 6, 0xFFFF, sum = 0
6921 11:47:01.286425 7, 0xFFFF, sum = 0
6922 11:47:01.286516 8, 0xFFFF, sum = 0
6923 11:47:01.289669 9, 0xFFFF, sum = 0
6924 11:47:01.289781 10, 0xFFFF, sum = 0
6925 11:47:01.293237 11, 0xFFFF, sum = 0
6926 11:47:01.293321 12, 0xFFFF, sum = 0
6927 11:47:01.296300 13, 0x0, sum = 1
6928 11:47:01.296384 14, 0x0, sum = 2
6929 11:47:01.299511 15, 0x0, sum = 3
6930 11:47:01.299595 16, 0x0, sum = 4
6931 11:47:01.303126 best_step = 14
6932 11:47:01.303208
6933 11:47:01.303273 ==
6934 11:47:01.306414 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 11:47:01.309526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 11:47:01.309601 ==
6937 11:47:01.312688 RX Vref Scan: 0
6938 11:47:01.312757
6939 11:47:01.312818 RX Vref 0 -> 0, step: 1
6940 11:47:01.312876
6941 11:47:01.315869 RX Delay -327 -> 252, step: 8
6942 11:47:01.324306 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6943 11:47:01.327608 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6944 11:47:01.330791 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6945 11:47:01.337203 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6946 11:47:01.340635 iDelay=217, Bit 4, Center -20 (-247 ~ 208) 456
6947 11:47:01.343957 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6948 11:47:01.347236 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6949 11:47:01.353665 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6950 11:47:01.357123 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6951 11:47:01.360266 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6952 11:47:01.363581 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6953 11:47:01.370261 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6954 11:47:01.373735 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6955 11:47:01.376888 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6956 11:47:01.380183 iDelay=217, Bit 14, Center -24 (-255 ~ 208) 464
6957 11:47:01.386911 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6958 11:47:01.387038 ==
6959 11:47:01.390188 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 11:47:01.393344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 11:47:01.393457 ==
6962 11:47:01.393569 DQS Delay:
6963 11:47:01.396905 DQS0 = 32, DQS1 = 36
6964 11:47:01.397029 DQM Delay:
6965 11:47:01.400120 DQM0 = 12, DQM1 = 10
6966 11:47:01.400226 DQ Delay:
6967 11:47:01.403574 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6968 11:47:01.406749 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6969 11:47:01.410042 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6970 11:47:01.413211 DQ12 =16, DQ13 =16, DQ14 =12, DQ15 =20
6971 11:47:01.413325
6972 11:47:01.413426
6973 11:47:01.419612 [DQSOSCAuto] RK1, (LSB)MR18= 0xa24b, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6974 11:47:01.423376 CH1 RK1: MR19=C0C, MR18=A24B
6975 11:47:01.429913 CH1_RK1: MR19=0xC0C, MR18=0xA24B, DQSOSC=389, MR23=63, INC=390, DEC=260
6976 11:47:01.433059 [RxdqsGatingPostProcess] freq 400
6977 11:47:01.439493 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6978 11:47:01.442950 best DQS0 dly(2T, 0.5T) = (0, 10)
6979 11:47:01.446097 best DQS1 dly(2T, 0.5T) = (0, 10)
6980 11:47:01.449504 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6981 11:47:01.452821 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6982 11:47:01.456172 best DQS0 dly(2T, 0.5T) = (0, 10)
6983 11:47:01.456281 best DQS1 dly(2T, 0.5T) = (0, 10)
6984 11:47:01.459149 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6985 11:47:01.462648 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6986 11:47:01.465856 Pre-setting of DQS Precalculation
6987 11:47:01.472575 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6988 11:47:01.479066 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6989 11:47:01.485598 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6990 11:47:01.485681
6991 11:47:01.485777
6992 11:47:01.489269 [Calibration Summary] 800 Mbps
6993 11:47:01.492424 CH 0, Rank 0
6994 11:47:01.492528 SW Impedance : PASS
6995 11:47:01.495472 DUTY Scan : NO K
6996 11:47:01.495578 ZQ Calibration : PASS
6997 11:47:01.499123 Jitter Meter : NO K
6998 11:47:01.502129 CBT Training : PASS
6999 11:47:01.502231 Write leveling : PASS
7000 11:47:01.505452 RX DQS gating : PASS
7001 11:47:01.508755 RX DQ/DQS(RDDQC) : PASS
7002 11:47:01.508866 TX DQ/DQS : PASS
7003 11:47:01.512113 RX DATLAT : PASS
7004 11:47:01.515254 RX DQ/DQS(Engine): PASS
7005 11:47:01.515366 TX OE : NO K
7006 11:47:01.518659 All Pass.
7007 11:47:01.518773
7008 11:47:01.518868 CH 0, Rank 1
7009 11:47:01.521946 SW Impedance : PASS
7010 11:47:01.522056 DUTY Scan : NO K
7011 11:47:01.524988 ZQ Calibration : PASS
7012 11:47:01.528348 Jitter Meter : NO K
7013 11:47:01.528458 CBT Training : PASS
7014 11:47:01.531917 Write leveling : NO K
7015 11:47:01.534768 RX DQS gating : PASS
7016 11:47:01.534887 RX DQ/DQS(RDDQC) : PASS
7017 11:47:01.538356 TX DQ/DQS : PASS
7018 11:47:01.541545 RX DATLAT : PASS
7019 11:47:01.541648 RX DQ/DQS(Engine): PASS
7020 11:47:01.544724 TX OE : NO K
7021 11:47:01.544828 All Pass.
7022 11:47:01.544920
7023 11:47:01.548342 CH 1, Rank 0
7024 11:47:01.548456 SW Impedance : PASS
7025 11:47:01.551320 DUTY Scan : NO K
7026 11:47:01.554789 ZQ Calibration : PASS
7027 11:47:01.554894 Jitter Meter : NO K
7028 11:47:01.558193 CBT Training : PASS
7029 11:47:01.561131 Write leveling : PASS
7030 11:47:01.561241 RX DQS gating : PASS
7031 11:47:01.564732 RX DQ/DQS(RDDQC) : PASS
7032 11:47:01.567825 TX DQ/DQS : PASS
7033 11:47:01.567936 RX DATLAT : PASS
7034 11:47:01.571208 RX DQ/DQS(Engine): PASS
7035 11:47:01.574412 TX OE : NO K
7036 11:47:01.574520 All Pass.
7037 11:47:01.574629
7038 11:47:01.574722 CH 1, Rank 1
7039 11:47:01.577632 SW Impedance : PASS
7040 11:47:01.581229 DUTY Scan : NO K
7041 11:47:01.581331 ZQ Calibration : PASS
7042 11:47:01.584715 Jitter Meter : NO K
7043 11:47:01.584836 CBT Training : PASS
7044 11:47:01.587900 Write leveling : NO K
7045 11:47:01.591071 RX DQS gating : PASS
7046 11:47:01.591154 RX DQ/DQS(RDDQC) : PASS
7047 11:47:01.594426 TX DQ/DQS : PASS
7048 11:47:01.597561 RX DATLAT : PASS
7049 11:47:01.597669 RX DQ/DQS(Engine): PASS
7050 11:47:01.601223 TX OE : NO K
7051 11:47:01.601310 All Pass.
7052 11:47:01.601408
7053 11:47:01.604461 DramC Write-DBI off
7054 11:47:01.607580 PER_BANK_REFRESH: Hybrid Mode
7055 11:47:01.607663 TX_TRACKING: ON
7056 11:47:01.617396 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7057 11:47:01.620653 [FAST_K] Save calibration result to emmc
7058 11:47:01.624217 dramc_set_vcore_voltage set vcore to 725000
7059 11:47:01.627418 Read voltage for 1600, 0
7060 11:47:01.627526 Vio18 = 0
7061 11:47:01.630692 Vcore = 725000
7062 11:47:01.630793 Vdram = 0
7063 11:47:01.630884 Vddq = 0
7064 11:47:01.630972 Vmddr = 0
7065 11:47:01.637625 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7066 11:47:01.640514 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7067 11:47:01.644189 MEM_TYPE=3, freq_sel=13
7068 11:47:01.647137 sv_algorithm_assistance_LP4_3733
7069 11:47:01.650769 ============ PULL DRAM RESETB DOWN ============
7070 11:47:01.657539 ========== PULL DRAM RESETB DOWN end =========
7071 11:47:01.660569 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7072 11:47:01.663881 ===================================
7073 11:47:01.667001 LPDDR4 DRAM CONFIGURATION
7074 11:47:01.670410 ===================================
7075 11:47:01.670494 EX_ROW_EN[0] = 0x0
7076 11:47:01.673725 EX_ROW_EN[1] = 0x0
7077 11:47:01.673809 LP4Y_EN = 0x0
7078 11:47:01.677148 WORK_FSP = 0x1
7079 11:47:01.677232 WL = 0x5
7080 11:47:01.680373 RL = 0x5
7081 11:47:01.683567 BL = 0x2
7082 11:47:01.683650 RPST = 0x0
7083 11:47:01.686577 RD_PRE = 0x0
7084 11:47:01.686734 WR_PRE = 0x1
7085 11:47:01.690234 WR_PST = 0x1
7086 11:47:01.690317 DBI_WR = 0x0
7087 11:47:01.693415 DBI_RD = 0x0
7088 11:47:01.693498 OTF = 0x1
7089 11:47:01.696552 ===================================
7090 11:47:01.700182 ===================================
7091 11:47:01.703388 ANA top config
7092 11:47:01.706569 ===================================
7093 11:47:01.706652 DLL_ASYNC_EN = 0
7094 11:47:01.710019 ALL_SLAVE_EN = 0
7095 11:47:01.713573 NEW_RANK_MODE = 1
7096 11:47:01.716795 DLL_IDLE_MODE = 1
7097 11:47:01.716879 LP45_APHY_COMB_EN = 1
7098 11:47:01.719951 TX_ODT_DIS = 0
7099 11:47:01.723138 NEW_8X_MODE = 1
7100 11:47:01.726811 ===================================
7101 11:47:01.729925 ===================================
7102 11:47:01.732967 data_rate = 3200
7103 11:47:01.736583 CKR = 1
7104 11:47:01.739725 DQ_P2S_RATIO = 8
7105 11:47:01.742976 ===================================
7106 11:47:01.743119 CA_P2S_RATIO = 8
7107 11:47:01.746271 DQ_CA_OPEN = 0
7108 11:47:01.749528 DQ_SEMI_OPEN = 0
7109 11:47:01.753168 CA_SEMI_OPEN = 0
7110 11:47:01.756457 CA_FULL_RATE = 0
7111 11:47:01.759473 DQ_CKDIV4_EN = 0
7112 11:47:01.759622 CA_CKDIV4_EN = 0
7113 11:47:01.762951 CA_PREDIV_EN = 0
7114 11:47:01.766015 PH8_DLY = 12
7115 11:47:01.769583 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7116 11:47:01.772904 DQ_AAMCK_DIV = 4
7117 11:47:01.775884 CA_AAMCK_DIV = 4
7118 11:47:01.776059 CA_ADMCK_DIV = 4
7119 11:47:01.779209 DQ_TRACK_CA_EN = 0
7120 11:47:01.782555 CA_PICK = 1600
7121 11:47:01.785820 CA_MCKIO = 1600
7122 11:47:01.789356 MCKIO_SEMI = 0
7123 11:47:01.792452 PLL_FREQ = 3068
7124 11:47:01.795620 DQ_UI_PI_RATIO = 32
7125 11:47:01.799275 CA_UI_PI_RATIO = 0
7126 11:47:01.802532 ===================================
7127 11:47:01.805616 ===================================
7128 11:47:01.805727 memory_type:LPDDR4
7129 11:47:01.808800 GP_NUM : 10
7130 11:47:01.811927 SRAM_EN : 1
7131 11:47:01.812041 MD32_EN : 0
7132 11:47:01.815373 ===================================
7133 11:47:01.818593 [ANA_INIT] >>>>>>>>>>>>>>
7134 11:47:01.822296 <<<<<< [CONFIGURE PHASE]: ANA_TX
7135 11:47:01.825220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7136 11:47:01.828728 ===================================
7137 11:47:01.831792 data_rate = 3200,PCW = 0X7600
7138 11:47:01.835353 ===================================
7139 11:47:01.838521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7140 11:47:01.841692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 11:47:01.848173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7142 11:47:01.851740 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7143 11:47:01.854857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7144 11:47:01.861730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7145 11:47:01.861854 [ANA_INIT] flow start
7146 11:47:01.864757 [ANA_INIT] PLL >>>>>>>>
7147 11:47:01.867996 [ANA_INIT] PLL <<<<<<<<
7148 11:47:01.868107 [ANA_INIT] MIDPI >>>>>>>>
7149 11:47:01.871416 [ANA_INIT] MIDPI <<<<<<<<
7150 11:47:01.874903 [ANA_INIT] DLL >>>>>>>>
7151 11:47:01.875015 [ANA_INIT] DLL <<<<<<<<
7152 11:47:01.878195 [ANA_INIT] flow end
7153 11:47:01.881560 ============ LP4 DIFF to SE enter ============
7154 11:47:01.884889 ============ LP4 DIFF to SE exit ============
7155 11:47:01.887881 [ANA_INIT] <<<<<<<<<<<<<
7156 11:47:01.891358 [Flow] Enable top DCM control >>>>>
7157 11:47:01.894394 [Flow] Enable top DCM control <<<<<
7158 11:47:01.897615 Enable DLL master slave shuffle
7159 11:47:01.904535 ==============================================================
7160 11:47:01.904651 Gating Mode config
7161 11:47:01.911139 ==============================================================
7162 11:47:01.911261 Config description:
7163 11:47:01.920754 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7164 11:47:01.927603 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7165 11:47:01.933993 SELPH_MODE 0: By rank 1: By Phase
7166 11:47:01.940654 ==============================================================
7167 11:47:01.940770 GAT_TRACK_EN = 1
7168 11:47:01.944281 RX_GATING_MODE = 2
7169 11:47:01.947442 RX_GATING_TRACK_MODE = 2
7170 11:47:01.950645 SELPH_MODE = 1
7171 11:47:01.954341 PICG_EARLY_EN = 1
7172 11:47:01.957728 VALID_LAT_VALUE = 1
7173 11:47:01.964261 ==============================================================
7174 11:47:01.967508 Enter into Gating configuration >>>>
7175 11:47:01.970484 Exit from Gating configuration <<<<
7176 11:47:01.973610 Enter into DVFS_PRE_config >>>>>
7177 11:47:01.983508 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7178 11:47:01.986960 Exit from DVFS_PRE_config <<<<<
7179 11:47:01.990246 Enter into PICG configuration >>>>
7180 11:47:01.993645 Exit from PICG configuration <<<<
7181 11:47:01.996678 [RX_INPUT] configuration >>>>>
7182 11:47:02.000066 [RX_INPUT] configuration <<<<<
7183 11:47:02.003474 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7184 11:47:02.009884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7185 11:47:02.016819 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 11:47:02.023273 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 11:47:02.026575 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7188 11:47:02.033097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7189 11:47:02.036672 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7190 11:47:02.042982 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7191 11:47:02.046198 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7192 11:47:02.049792 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7193 11:47:02.053041 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7194 11:47:02.059619 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 11:47:02.062820 ===================================
7196 11:47:02.062905 LPDDR4 DRAM CONFIGURATION
7197 11:47:02.066097 ===================================
7198 11:47:02.069701 EX_ROW_EN[0] = 0x0
7199 11:47:02.072813 EX_ROW_EN[1] = 0x0
7200 11:47:02.072916 LP4Y_EN = 0x0
7201 11:47:02.075913 WORK_FSP = 0x1
7202 11:47:02.075990 WL = 0x5
7203 11:47:02.079205 RL = 0x5
7204 11:47:02.079279 BL = 0x2
7205 11:47:02.082844 RPST = 0x0
7206 11:47:02.082934 RD_PRE = 0x0
7207 11:47:02.086100 WR_PRE = 0x1
7208 11:47:02.086197 WR_PST = 0x1
7209 11:47:02.089160 DBI_WR = 0x0
7210 11:47:02.089234 DBI_RD = 0x0
7211 11:47:02.092590 OTF = 0x1
7212 11:47:02.095734 ===================================
7213 11:47:02.099182 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7214 11:47:02.102349 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7215 11:47:02.109235 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 11:47:02.112288 ===================================
7217 11:47:02.112399 LPDDR4 DRAM CONFIGURATION
7218 11:47:02.115870 ===================================
7219 11:47:02.119106 EX_ROW_EN[0] = 0x10
7220 11:47:02.122134 EX_ROW_EN[1] = 0x0
7221 11:47:02.122243 LP4Y_EN = 0x0
7222 11:47:02.125680 WORK_FSP = 0x1
7223 11:47:02.125790 WL = 0x5
7224 11:47:02.128780 RL = 0x5
7225 11:47:02.128890 BL = 0x2
7226 11:47:02.134103 RPST = 0x0
7227 11:47:02.134202 RD_PRE = 0x0
7228 11:47:02.135307 WR_PRE = 0x1
7229 11:47:02.135384 WR_PST = 0x1
7230 11:47:02.138510 DBI_WR = 0x0
7231 11:47:02.138583 DBI_RD = 0x0
7232 11:47:02.141976 OTF = 0x1
7233 11:47:02.145588 ===================================
7234 11:47:02.152066 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7235 11:47:02.152146 ==
7236 11:47:02.155173 Dram Type= 6, Freq= 0, CH_0, rank 0
7237 11:47:02.158751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7238 11:47:02.158851 ==
7239 11:47:02.161656 [Duty_Offset_Calibration]
7240 11:47:02.161730 B0:2 B1:0 CA:1
7241 11:47:02.161793
7242 11:47:02.165229 [DutyScan_Calibration_Flow] k_type=0
7243 11:47:02.175403
7244 11:47:02.175529 ==CLK 0==
7245 11:47:02.178951 Final CLK duty delay cell = -4
7246 11:47:02.182208 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7247 11:47:02.185369 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7248 11:47:02.188965 [-4] AVG Duty = 4922%(X100)
7249 11:47:02.189057
7250 11:47:02.192269 CH0 CLK Duty spec in!! Max-Min= 218%
7251 11:47:02.195367 [DutyScan_Calibration_Flow] ====Done====
7252 11:47:02.195452
7253 11:47:02.198575 [DutyScan_Calibration_Flow] k_type=1
7254 11:47:02.215038
7255 11:47:02.215166 ==DQS 0 ==
7256 11:47:02.218215 Final DQS duty delay cell = 0
7257 11:47:02.221615 [0] MAX Duty = 5249%(X100), DQS PI = 32
7258 11:47:02.224688 [0] MIN Duty = 4969%(X100), DQS PI = 0
7259 11:47:02.228006 [0] AVG Duty = 5109%(X100)
7260 11:47:02.228084
7261 11:47:02.228159 ==DQS 1 ==
7262 11:47:02.231512 Final DQS duty delay cell = -4
7263 11:47:02.234741 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7264 11:47:02.237912 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7265 11:47:02.241187 [-4] AVG Duty = 5000%(X100)
7266 11:47:02.241273
7267 11:47:02.244789 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7268 11:47:02.244864
7269 11:47:02.247739 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7270 11:47:02.251292 [DutyScan_Calibration_Flow] ====Done====
7271 11:47:02.251387
7272 11:47:02.254394 [DutyScan_Calibration_Flow] k_type=3
7273 11:47:02.272249
7274 11:47:02.272331 ==DQM 0 ==
7275 11:47:02.275465 Final DQM duty delay cell = 0
7276 11:47:02.279109 [0] MAX Duty = 5093%(X100), DQS PI = 28
7277 11:47:02.282135 [0] MIN Duty = 4813%(X100), DQS PI = 50
7278 11:47:02.285371 [0] AVG Duty = 4953%(X100)
7279 11:47:02.285471
7280 11:47:02.285539 ==DQM 1 ==
7281 11:47:02.288683 Final DQM duty delay cell = 0
7282 11:47:02.292238 [0] MAX Duty = 5249%(X100), DQS PI = 46
7283 11:47:02.295686 [0] MIN Duty = 5031%(X100), DQS PI = 8
7284 11:47:02.299009 [0] AVG Duty = 5140%(X100)
7285 11:47:02.299096
7286 11:47:02.302490 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7287 11:47:02.302576
7288 11:47:02.305727 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7289 11:47:02.308615 [DutyScan_Calibration_Flow] ====Done====
7290 11:47:02.308700
7291 11:47:02.311997 [DutyScan_Calibration_Flow] k_type=2
7292 11:47:02.330458
7293 11:47:02.330547 ==DQ 0 ==
7294 11:47:02.333507 Final DQ duty delay cell = 0
7295 11:47:02.336758 [0] MAX Duty = 5124%(X100), DQS PI = 32
7296 11:47:02.340135 [0] MIN Duty = 5000%(X100), DQS PI = 16
7297 11:47:02.343601 [0] AVG Duty = 5062%(X100)
7298 11:47:02.343687
7299 11:47:02.343753 ==DQ 1 ==
7300 11:47:02.346761 Final DQ duty delay cell = 4
7301 11:47:02.349807 [4] MAX Duty = 5125%(X100), DQS PI = 2
7302 11:47:02.353502 [4] MIN Duty = 5062%(X100), DQS PI = 0
7303 11:47:02.353590 [4] AVG Duty = 5093%(X100)
7304 11:47:02.356748
7305 11:47:02.359979 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7306 11:47:02.360061
7307 11:47:02.363128 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7308 11:47:02.366457 [DutyScan_Calibration_Flow] ====Done====
7309 11:47:02.366540 ==
7310 11:47:02.369615 Dram Type= 6, Freq= 0, CH_1, rank 0
7311 11:47:02.373177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7312 11:47:02.373260 ==
7313 11:47:02.376499 [Duty_Offset_Calibration]
7314 11:47:02.376581 B0:0 B1:-1 CA:2
7315 11:47:02.376647
7316 11:47:02.379708 [DutyScan_Calibration_Flow] k_type=0
7317 11:47:02.390316
7318 11:47:02.390403 ==CLK 0==
7319 11:47:02.393889 Final CLK duty delay cell = 0
7320 11:47:02.396938 [0] MAX Duty = 5156%(X100), DQS PI = 10
7321 11:47:02.400231 [0] MIN Duty = 4906%(X100), DQS PI = 46
7322 11:47:02.403417 [0] AVG Duty = 5031%(X100)
7323 11:47:02.403501
7324 11:47:02.406847 CH1 CLK Duty spec in!! Max-Min= 250%
7325 11:47:02.410087 [DutyScan_Calibration_Flow] ====Done====
7326 11:47:02.410170
7327 11:47:02.413081 [DutyScan_Calibration_Flow] k_type=1
7328 11:47:02.429917
7329 11:47:02.430005 ==DQS 0 ==
7330 11:47:02.433343 Final DQS duty delay cell = 0
7331 11:47:02.436701 [0] MAX Duty = 5124%(X100), DQS PI = 26
7332 11:47:02.439610 [0] MIN Duty = 4969%(X100), DQS PI = 2
7333 11:47:02.443201 [0] AVG Duty = 5046%(X100)
7334 11:47:02.443284
7335 11:47:02.443350 ==DQS 1 ==
7336 11:47:02.446516 Final DQS duty delay cell = 0
7337 11:47:02.449752 [0] MAX Duty = 5187%(X100), DQS PI = 62
7338 11:47:02.452959 [0] MIN Duty = 4844%(X100), DQS PI = 32
7339 11:47:02.456153 [0] AVG Duty = 5015%(X100)
7340 11:47:02.456235
7341 11:47:02.459782 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7342 11:47:02.459867
7343 11:47:02.463016 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7344 11:47:02.466172 [DutyScan_Calibration_Flow] ====Done====
7345 11:47:02.466255
7346 11:47:02.469450 [DutyScan_Calibration_Flow] k_type=3
7347 11:47:02.487822
7348 11:47:02.487907 ==DQM 0 ==
7349 11:47:02.490793 Final DQM duty delay cell = 4
7350 11:47:02.494497 [4] MAX Duty = 5125%(X100), DQS PI = 22
7351 11:47:02.497737 [4] MIN Duty = 4969%(X100), DQS PI = 32
7352 11:47:02.500875 [4] AVG Duty = 5047%(X100)
7353 11:47:02.500973
7354 11:47:02.501074 ==DQM 1 ==
7355 11:47:02.504162 Final DQM duty delay cell = 0
7356 11:47:02.507385 [0] MAX Duty = 5281%(X100), DQS PI = 58
7357 11:47:02.510776 [0] MIN Duty = 4907%(X100), DQS PI = 34
7358 11:47:02.514071 [0] AVG Duty = 5094%(X100)
7359 11:47:02.514198
7360 11:47:02.517280 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7361 11:47:02.517363
7362 11:47:02.520510 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7363 11:47:02.523975 [DutyScan_Calibration_Flow] ====Done====
7364 11:47:02.524052
7365 11:47:02.527130 [DutyScan_Calibration_Flow] k_type=2
7366 11:47:02.544476
7367 11:47:02.544565 ==DQ 0 ==
7368 11:47:02.547853 Final DQ duty delay cell = 0
7369 11:47:02.551077 [0] MAX Duty = 5093%(X100), DQS PI = 22
7370 11:47:02.554769 [0] MIN Duty = 4969%(X100), DQS PI = 0
7371 11:47:02.554924 [0] AVG Duty = 5031%(X100)
7372 11:47:02.557898
7373 11:47:02.558010 ==DQ 1 ==
7374 11:47:02.561195 Final DQ duty delay cell = 0
7375 11:47:02.564413 [0] MAX Duty = 5062%(X100), DQS PI = 2
7376 11:47:02.567443 [0] MIN Duty = 4813%(X100), DQS PI = 34
7377 11:47:02.567523 [0] AVG Duty = 4937%(X100)
7378 11:47:02.571106
7379 11:47:02.574006 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7380 11:47:02.574120
7381 11:47:02.577784 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7382 11:47:02.580837 [DutyScan_Calibration_Flow] ====Done====
7383 11:47:02.584021 nWR fixed to 30
7384 11:47:02.584115 [ModeRegInit_LP4] CH0 RK0
7385 11:47:02.587152 [ModeRegInit_LP4] CH0 RK1
7386 11:47:02.590940 [ModeRegInit_LP4] CH1 RK0
7387 11:47:02.593985 [ModeRegInit_LP4] CH1 RK1
7388 11:47:02.594070 match AC timing 5
7389 11:47:02.600932 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7390 11:47:02.604167 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7391 11:47:02.607427 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7392 11:47:02.613844 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7393 11:47:02.617078 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7394 11:47:02.617160 [MiockJmeterHQA]
7395 11:47:02.617228
7396 11:47:02.620399 [DramcMiockJmeter] u1RxGatingPI = 0
7397 11:47:02.624139 0 : 4367, 4139
7398 11:47:02.624247 4 : 4252, 4027
7399 11:47:02.627263 8 : 4253, 4026
7400 11:47:02.627376 12 : 4253, 4029
7401 11:47:02.627476 16 : 4258, 4029
7402 11:47:02.630676 20 : 4363, 4138
7403 11:47:02.630802 24 : 4250, 4026
7404 11:47:02.633974 28 : 4252, 4027
7405 11:47:02.634051 32 : 4258, 4029
7406 11:47:02.637547 36 : 4257, 4029
7407 11:47:02.637621 40 : 4252, 4027
7408 11:47:02.640561 44 : 4255, 4029
7409 11:47:02.640675 48 : 4252, 4027
7410 11:47:02.640787 52 : 4255, 4029
7411 11:47:02.643543 56 : 4366, 4140
7412 11:47:02.643659 60 : 4249, 4027
7413 11:47:02.647075 64 : 4255, 4029
7414 11:47:02.647180 68 : 4250, 4027
7415 11:47:02.650334 72 : 4363, 4137
7416 11:47:02.650423 76 : 4250, 4027
7417 11:47:02.653836 80 : 4253, 4029
7418 11:47:02.653921 84 : 4252, 4029
7419 11:47:02.653990 88 : 4250, 3640
7420 11:47:02.656957 92 : 4250, 0
7421 11:47:02.657066 96 : 4250, 0
7422 11:47:02.660157 100 : 4360, 0
7423 11:47:02.660244 104 : 4363, 0
7424 11:47:02.660311 108 : 4253, 0
7425 11:47:02.663381 112 : 4253, 0
7426 11:47:02.663466 116 : 4250, 0
7427 11:47:02.666577 120 : 4252, 0
7428 11:47:02.666664 124 : 4252, 0
7429 11:47:02.666733 128 : 4250, 0
7430 11:47:02.670185 132 : 4250, 0
7431 11:47:02.670272 136 : 4253, 0
7432 11:47:02.673138 140 : 4361, 0
7433 11:47:02.673224 144 : 4360, 0
7434 11:47:02.673293 148 : 4253, 0
7435 11:47:02.676819 152 : 4252, 0
7436 11:47:02.676932 156 : 4250, 0
7437 11:47:02.677040 160 : 4252, 0
7438 11:47:02.680029 164 : 4252, 0
7439 11:47:02.680105 168 : 4250, 0
7440 11:47:02.683245 172 : 4252, 0
7441 11:47:02.683331 176 : 4252, 0
7442 11:47:02.683400 180 : 4250, 0
7443 11:47:02.686447 184 : 4250, 0
7444 11:47:02.686533 188 : 4253, 0
7445 11:47:02.689724 192 : 4361, 0
7446 11:47:02.689810 196 : 4360, 0
7447 11:47:02.689879 200 : 4252, 3
7448 11:47:02.693422 204 : 4252, 2241
7449 11:47:02.693509 208 : 4366, 4139
7450 11:47:02.696695 212 : 4249, 4027
7451 11:47:02.696782 216 : 4360, 4137
7452 11:47:02.699925 220 : 4255, 4029
7453 11:47:02.700012 224 : 4250, 4027
7454 11:47:02.703119 228 : 4363, 4137
7455 11:47:02.703206 232 : 4250, 4027
7456 11:47:02.706264 236 : 4363, 4137
7457 11:47:02.706355 240 : 4250, 4027
7458 11:47:02.709565 244 : 4249, 4027
7459 11:47:02.709677 248 : 4250, 4026
7460 11:47:02.709774 252 : 4250, 4027
7461 11:47:02.713229 256 : 4250, 4027
7462 11:47:02.713330 260 : 4360, 4138
7463 11:47:02.716450 264 : 4250, 4027
7464 11:47:02.716536 268 : 4250, 4026
7465 11:47:02.719451 272 : 4250, 4027
7466 11:47:02.719569 276 : 4250, 4027
7467 11:47:02.723211 280 : 4363, 4140
7468 11:47:02.723297 284 : 4250, 4026
7469 11:47:02.726483 288 : 4361, 4137
7470 11:47:02.726569 292 : 4250, 4027
7471 11:47:02.729720 296 : 4249, 4027
7472 11:47:02.729807 300 : 4250, 4026
7473 11:47:02.733085 304 : 4250, 4026
7474 11:47:02.733172 308 : 4255, 4029
7475 11:47:02.733241 312 : 4363, 4118
7476 11:47:02.736271 316 : 4250, 2201
7477 11:47:02.736357 320 : 4250, 17
7478 11:47:02.736425
7479 11:47:02.739663 MIOCK jitter meter ch=0
7480 11:47:02.739749
7481 11:47:02.742795 1T = (320-92) = 228 dly cells
7482 11:47:02.749611 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7483 11:47:02.749698 ==
7484 11:47:02.752601 Dram Type= 6, Freq= 0, CH_0, rank 0
7485 11:47:02.755916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 11:47:02.756028 ==
7487 11:47:02.762703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 11:47:02.766262 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 11:47:02.769293 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 11:47:02.775677 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 11:47:02.784754 [CA 0] Center 42 (12~73) winsize 62
7492 11:47:02.788040 [CA 1] Center 42 (12~72) winsize 61
7493 11:47:02.791755 [CA 2] Center 37 (7~67) winsize 61
7494 11:47:02.794957 [CA 3] Center 37 (7~67) winsize 61
7495 11:47:02.798253 [CA 4] Center 36 (6~66) winsize 61
7496 11:47:02.801390 [CA 5] Center 35 (5~65) winsize 61
7497 11:47:02.801476
7498 11:47:02.804470 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 11:47:02.804555
7500 11:47:02.808122 [CATrainingPosCal] consider 1 rank data
7501 11:47:02.811383 u2DelayCellTimex100 = 285/100 ps
7502 11:47:02.814645 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7503 11:47:02.821371 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7504 11:47:02.824439 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7505 11:47:02.827590 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7506 11:47:02.831258 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7507 11:47:02.834423 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7508 11:47:02.834512
7509 11:47:02.837519 CA PerBit enable=1, Macro0, CA PI delay=35
7510 11:47:02.837605
7511 11:47:02.840720 [CBTSetCACLKResult] CA Dly = 35
7512 11:47:02.844469 CS Dly: 9 (0~40)
7513 11:47:02.847766 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 11:47:02.850862 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 11:47:02.850954 ==
7516 11:47:02.854146 Dram Type= 6, Freq= 0, CH_0, rank 1
7517 11:47:02.860726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 11:47:02.860815 ==
7519 11:47:02.864135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 11:47:02.870673 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 11:47:02.873788 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 11:47:02.880136 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 11:47:02.887992 [CA 0] Center 43 (13~73) winsize 61
7524 11:47:02.891349 [CA 1] Center 43 (13~73) winsize 61
7525 11:47:02.894524 [CA 2] Center 38 (9~67) winsize 59
7526 11:47:02.898256 [CA 3] Center 38 (8~68) winsize 61
7527 11:47:02.901424 [CA 4] Center 37 (7~67) winsize 61
7528 11:47:02.904765 [CA 5] Center 36 (6~66) winsize 61
7529 11:47:02.904864
7530 11:47:02.907777 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 11:47:02.907861
7532 11:47:02.911179 [CATrainingPosCal] consider 2 rank data
7533 11:47:02.914791 u2DelayCellTimex100 = 285/100 ps
7534 11:47:02.917881 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7535 11:47:02.924368 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7536 11:47:02.927866 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7537 11:47:02.931131 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7538 11:47:02.934360 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7539 11:47:02.937436 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7540 11:47:02.937520
7541 11:47:02.940923 CA PerBit enable=1, Macro0, CA PI delay=35
7542 11:47:02.941045
7543 11:47:02.944288 [CBTSetCACLKResult] CA Dly = 35
7544 11:47:02.947415 CS Dly: 10 (0~43)
7545 11:47:02.950733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 11:47:02.953957 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 11:47:02.954040
7548 11:47:02.957627 ----->DramcWriteLeveling(PI) begin...
7549 11:47:02.957711 ==
7550 11:47:02.960658 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 11:47:02.967106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 11:47:02.967190 ==
7553 11:47:02.970573 Write leveling (Byte 0): 36 => 36
7554 11:47:02.973904 Write leveling (Byte 1): 31 => 31
7555 11:47:02.973987 DramcWriteLeveling(PI) end<-----
7556 11:47:02.977439
7557 11:47:02.977523 ==
7558 11:47:02.980589 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 11:47:02.983820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 11:47:02.983918 ==
7561 11:47:02.987045 [Gating] SW mode calibration
7562 11:47:02.993552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7563 11:47:02.996757 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7564 11:47:03.003799 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 11:47:03.006961 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:47:03.010102 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7567 11:47:03.016940 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7568 11:47:03.020205 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7569 11:47:03.023582 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7570 11:47:03.030188 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 11:47:03.033600 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 11:47:03.036805 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 11:47:03.043444 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 11:47:03.046454 1 5 8 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7575 11:47:03.049898 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7576 11:47:03.056713 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7577 11:47:03.059687 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7578 11:47:03.063343 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 11:47:03.069752 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 11:47:03.073162 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 11:47:03.076612 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7582 11:47:03.083190 1 6 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7583 11:47:03.086318 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7584 11:47:03.089577 1 6 16 | B1->B0 | 2c2b 4646 | 1 0 | (0 0) (0 0)
7585 11:47:03.096517 1 6 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
7586 11:47:03.099415 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 11:47:03.102757 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 11:47:03.109600 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 11:47:03.112727 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 11:47:03.116243 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7591 11:47:03.122486 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 11:47:03.125843 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7593 11:47:03.129069 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 11:47:03.135556 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7595 11:47:03.138936 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:47:03.142307 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 11:47:03.148932 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 11:47:03.152564 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 11:47:03.155702 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 11:47:03.162252 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 11:47:03.165565 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 11:47:03.168736 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 11:47:03.175324 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 11:47:03.178646 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 11:47:03.182005 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 11:47:03.188620 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7607 11:47:03.191903 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 11:47:03.195059 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7609 11:47:03.198361 Total UI for P1: 0, mck2ui 16
7610 11:47:03.201918 best dqsien dly found for B0: ( 1, 9, 10)
7611 11:47:03.208587 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7612 11:47:03.211806 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 11:47:03.215026 Total UI for P1: 0, mck2ui 16
7614 11:47:03.218356 best dqsien dly found for B1: ( 1, 9, 20)
7615 11:47:03.221521 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7616 11:47:03.224819 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7617 11:47:03.224921
7618 11:47:03.228551 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7619 11:47:03.231679 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7620 11:47:03.235311 [Gating] SW calibration Done
7621 11:47:03.235405 ==
7622 11:47:03.238722 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 11:47:03.241738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 11:47:03.245224 ==
7625 11:47:03.245327 RX Vref Scan: 0
7626 11:47:03.245396
7627 11:47:03.248416 RX Vref 0 -> 0, step: 1
7628 11:47:03.248511
7629 11:47:03.248576 RX Delay 0 -> 252, step: 8
7630 11:47:03.254760 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7631 11:47:03.258066 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7632 11:47:03.261337 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7633 11:47:03.264732 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7634 11:47:03.267885 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7635 11:47:03.274725 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7636 11:47:03.277833 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7637 11:47:03.281511 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7638 11:47:03.284791 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7639 11:47:03.287968 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7640 11:47:03.294495 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7641 11:47:03.297840 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7642 11:47:03.301053 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7643 11:47:03.304331 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7644 11:47:03.310782 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7645 11:47:03.314315 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7646 11:47:03.314400 ==
7647 11:47:03.317549 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 11:47:03.320837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 11:47:03.320950 ==
7650 11:47:03.323893 DQS Delay:
7651 11:47:03.323979 DQS0 = 0, DQS1 = 0
7652 11:47:03.324046 DQM Delay:
7653 11:47:03.327542 DQM0 = 137, DQM1 = 125
7654 11:47:03.327627 DQ Delay:
7655 11:47:03.330931 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7656 11:47:03.334105 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7657 11:47:03.337669 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7658 11:47:03.344235 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =131
7659 11:47:03.344320
7660 11:47:03.344387
7661 11:47:03.344450 ==
7662 11:47:03.347189 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 11:47:03.350508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 11:47:03.350602 ==
7665 11:47:03.350675
7666 11:47:03.350740
7667 11:47:03.353637 TX Vref Scan disable
7668 11:47:03.353712 == TX Byte 0 ==
7669 11:47:03.360253 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7670 11:47:03.363580 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7671 11:47:03.367314 == TX Byte 1 ==
7672 11:47:03.370578 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7673 11:47:03.373417 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7674 11:47:03.373503 ==
7675 11:47:03.377202 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 11:47:03.380386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 11:47:03.383483 ==
7678 11:47:03.394866
7679 11:47:03.398073 TX Vref early break, caculate TX vref
7680 11:47:03.401447 TX Vref=16, minBit 6, minWin=23, winSum=382
7681 11:47:03.404480 TX Vref=18, minBit 6, minWin=23, winSum=387
7682 11:47:03.407762 TX Vref=20, minBit 0, minWin=24, winSum=399
7683 11:47:03.411325 TX Vref=22, minBit 1, minWin=25, winSum=412
7684 11:47:03.414567 TX Vref=24, minBit 1, minWin=25, winSum=415
7685 11:47:03.421303 TX Vref=26, minBit 12, minWin=25, winSum=427
7686 11:47:03.424385 TX Vref=28, minBit 7, minWin=25, winSum=429
7687 11:47:03.427965 TX Vref=30, minBit 0, minWin=25, winSum=423
7688 11:47:03.431107 TX Vref=32, minBit 0, minWin=25, winSum=417
7689 11:47:03.434258 TX Vref=34, minBit 2, minWin=24, winSum=404
7690 11:47:03.440818 [TxChooseVref] Worse bit 7, Min win 25, Win sum 429, Final Vref 28
7691 11:47:03.440932
7692 11:47:03.444008 Final TX Range 0 Vref 28
7693 11:47:03.444080
7694 11:47:03.444157 ==
7695 11:47:03.447705 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 11:47:03.450841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 11:47:03.450917 ==
7698 11:47:03.450982
7699 11:47:03.451042
7700 11:47:03.454529 TX Vref Scan disable
7701 11:47:03.460812 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7702 11:47:03.460899 == TX Byte 0 ==
7703 11:47:03.464061 u2DelayCellOfst[0]=13 cells (4 PI)
7704 11:47:03.467388 u2DelayCellOfst[1]=17 cells (5 PI)
7705 11:47:03.470630 u2DelayCellOfst[2]=10 cells (3 PI)
7706 11:47:03.474328 u2DelayCellOfst[3]=13 cells (4 PI)
7707 11:47:03.477603 u2DelayCellOfst[4]=6 cells (2 PI)
7708 11:47:03.480786 u2DelayCellOfst[5]=0 cells (0 PI)
7709 11:47:03.483946 u2DelayCellOfst[6]=17 cells (5 PI)
7710 11:47:03.487244 u2DelayCellOfst[7]=13 cells (4 PI)
7711 11:47:03.490554 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7712 11:47:03.493794 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7713 11:47:03.496872 == TX Byte 1 ==
7714 11:47:03.500568 u2DelayCellOfst[8]=0 cells (0 PI)
7715 11:47:03.503556 u2DelayCellOfst[9]=0 cells (0 PI)
7716 11:47:03.506905 u2DelayCellOfst[10]=10 cells (3 PI)
7717 11:47:03.506990 u2DelayCellOfst[11]=3 cells (1 PI)
7718 11:47:03.510256 u2DelayCellOfst[12]=13 cells (4 PI)
7719 11:47:03.513517 u2DelayCellOfst[13]=13 cells (4 PI)
7720 11:47:03.516787 u2DelayCellOfst[14]=17 cells (5 PI)
7721 11:47:03.520546 u2DelayCellOfst[15]=13 cells (4 PI)
7722 11:47:03.526677 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7723 11:47:03.530217 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7724 11:47:03.530298 DramC Write-DBI on
7725 11:47:03.530389 ==
7726 11:47:03.533803 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 11:47:03.540111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 11:47:03.540193 ==
7729 11:47:03.540296
7730 11:47:03.540379
7731 11:47:03.540488 TX Vref Scan disable
7732 11:47:03.544234 == TX Byte 0 ==
7733 11:47:03.547442 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7734 11:47:03.551199 == TX Byte 1 ==
7735 11:47:03.554179 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7736 11:47:03.557789 DramC Write-DBI off
7737 11:47:03.557874
7738 11:47:03.557957 [DATLAT]
7739 11:47:03.558043 Freq=1600, CH0 RK0
7740 11:47:03.558121
7741 11:47:03.560817 DATLAT Default: 0xf
7742 11:47:03.560930 0, 0xFFFF, sum = 0
7743 11:47:03.564301 1, 0xFFFF, sum = 0
7744 11:47:03.567570 2, 0xFFFF, sum = 0
7745 11:47:03.567681 3, 0xFFFF, sum = 0
7746 11:47:03.570813 4, 0xFFFF, sum = 0
7747 11:47:03.570925 5, 0xFFFF, sum = 0
7748 11:47:03.574111 6, 0xFFFF, sum = 0
7749 11:47:03.574197 7, 0xFFFF, sum = 0
7750 11:47:03.577491 8, 0xFFFF, sum = 0
7751 11:47:03.577577 9, 0xFFFF, sum = 0
7752 11:47:03.580633 10, 0xFFFF, sum = 0
7753 11:47:03.580719 11, 0xFFFF, sum = 0
7754 11:47:03.583905 12, 0xFFFF, sum = 0
7755 11:47:03.584064 13, 0xFFFF, sum = 0
7756 11:47:03.587439 14, 0x0, sum = 1
7757 11:47:03.587531 15, 0x0, sum = 2
7758 11:47:03.590661 16, 0x0, sum = 3
7759 11:47:03.590739 17, 0x0, sum = 4
7760 11:47:03.593997 best_step = 15
7761 11:47:03.594081
7762 11:47:03.594147 ==
7763 11:47:03.597262 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 11:47:03.600405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 11:47:03.600520 ==
7766 11:47:03.603954 RX Vref Scan: 1
7767 11:47:03.604088
7768 11:47:03.604163 Set Vref Range= 24 -> 127
7769 11:47:03.604345
7770 11:47:03.607053 RX Vref 24 -> 127, step: 1
7771 11:47:03.607154
7772 11:47:03.610737 RX Delay 19 -> 252, step: 4
7773 11:47:03.610827
7774 11:47:03.613733 Set Vref, RX VrefLevel [Byte0]: 24
7775 11:47:03.617052 [Byte1]: 24
7776 11:47:03.617178
7777 11:47:03.620520 Set Vref, RX VrefLevel [Byte0]: 25
7778 11:47:03.623430 [Byte1]: 25
7779 11:47:03.626795
7780 11:47:03.626878 Set Vref, RX VrefLevel [Byte0]: 26
7781 11:47:03.630410 [Byte1]: 26
7782 11:47:03.634530
7783 11:47:03.634614 Set Vref, RX VrefLevel [Byte0]: 27
7784 11:47:03.637958 [Byte1]: 27
7785 11:47:03.642071
7786 11:47:03.642155 Set Vref, RX VrefLevel [Byte0]: 28
7787 11:47:03.645426 [Byte1]: 28
7788 11:47:03.649704
7789 11:47:03.649788 Set Vref, RX VrefLevel [Byte0]: 29
7790 11:47:03.653279 [Byte1]: 29
7791 11:47:03.657188
7792 11:47:03.657271 Set Vref, RX VrefLevel [Byte0]: 30
7793 11:47:03.660872 [Byte1]: 30
7794 11:47:03.665116
7795 11:47:03.665206 Set Vref, RX VrefLevel [Byte0]: 31
7796 11:47:03.668260 [Byte1]: 31
7797 11:47:03.672959
7798 11:47:03.673415 Set Vref, RX VrefLevel [Byte0]: 32
7799 11:47:03.676337 [Byte1]: 32
7800 11:47:03.680542
7801 11:47:03.681124 Set Vref, RX VrefLevel [Byte0]: 33
7802 11:47:03.683449 [Byte1]: 33
7803 11:47:03.687737
7804 11:47:03.688394 Set Vref, RX VrefLevel [Byte0]: 34
7805 11:47:03.690990 [Byte1]: 34
7806 11:47:03.695538
7807 11:47:03.695968 Set Vref, RX VrefLevel [Byte0]: 35
7808 11:47:03.698923 [Byte1]: 35
7809 11:47:03.703055
7810 11:47:03.703549 Set Vref, RX VrefLevel [Byte0]: 36
7811 11:47:03.706546 [Byte1]: 36
7812 11:47:03.710557
7813 11:47:03.711029 Set Vref, RX VrefLevel [Byte0]: 37
7814 11:47:03.713757 [Byte1]: 37
7815 11:47:03.717997
7816 11:47:03.718619 Set Vref, RX VrefLevel [Byte0]: 38
7817 11:47:03.721673 [Byte1]: 38
7818 11:47:03.725764
7819 11:47:03.726194 Set Vref, RX VrefLevel [Byte0]: 39
7820 11:47:03.729043 [Byte1]: 39
7821 11:47:03.733203
7822 11:47:03.733761 Set Vref, RX VrefLevel [Byte0]: 40
7823 11:47:03.736521 [Byte1]: 40
7824 11:47:03.740894
7825 11:47:03.741504 Set Vref, RX VrefLevel [Byte0]: 41
7826 11:47:03.744003 [Byte1]: 41
7827 11:47:03.748530
7828 11:47:03.749164 Set Vref, RX VrefLevel [Byte0]: 42
7829 11:47:03.751804 [Byte1]: 42
7830 11:47:03.755996
7831 11:47:03.759265 Set Vref, RX VrefLevel [Byte0]: 43
7832 11:47:03.762314 [Byte1]: 43
7833 11:47:03.762886
7834 11:47:03.765813 Set Vref, RX VrefLevel [Byte0]: 44
7835 11:47:03.768915 [Byte1]: 44
7836 11:47:03.769476
7837 11:47:03.772091 Set Vref, RX VrefLevel [Byte0]: 45
7838 11:47:03.775624 [Byte1]: 45
7839 11:47:03.776273
7840 11:47:03.778707 Set Vref, RX VrefLevel [Byte0]: 46
7841 11:47:03.782089 [Byte1]: 46
7842 11:47:03.786273
7843 11:47:03.786705 Set Vref, RX VrefLevel [Byte0]: 47
7844 11:47:03.789639 [Byte1]: 47
7845 11:47:03.793876
7846 11:47:03.794482 Set Vref, RX VrefLevel [Byte0]: 48
7847 11:47:03.797050 [Byte1]: 48
7848 11:47:03.801276
7849 11:47:03.801941 Set Vref, RX VrefLevel [Byte0]: 49
7850 11:47:03.804854 [Byte1]: 49
7851 11:47:03.808921
7852 11:47:03.809564 Set Vref, RX VrefLevel [Byte0]: 50
7853 11:47:03.812450 [Byte1]: 50
7854 11:47:03.816634
7855 11:47:03.817370 Set Vref, RX VrefLevel [Byte0]: 51
7856 11:47:03.819774 [Byte1]: 51
7857 11:47:03.824137
7858 11:47:03.824750 Set Vref, RX VrefLevel [Byte0]: 52
7859 11:47:03.827355 [Byte1]: 52
7860 11:47:03.831715
7861 11:47:03.832278 Set Vref, RX VrefLevel [Byte0]: 53
7862 11:47:03.834924 [Byte1]: 53
7863 11:47:03.839292
7864 11:47:03.839912 Set Vref, RX VrefLevel [Byte0]: 54
7865 11:47:03.842542 [Byte1]: 54
7866 11:47:03.846959
7867 11:47:03.847543 Set Vref, RX VrefLevel [Byte0]: 55
7868 11:47:03.850051 [Byte1]: 55
7869 11:47:03.854258
7870 11:47:03.854688 Set Vref, RX VrefLevel [Byte0]: 56
7871 11:47:03.857576 [Byte1]: 56
7872 11:47:03.861833
7873 11:47:03.862135 Set Vref, RX VrefLevel [Byte0]: 57
7874 11:47:03.865272 [Byte1]: 57
7875 11:47:03.869728
7876 11:47:03.870046 Set Vref, RX VrefLevel [Byte0]: 58
7877 11:47:03.872874 [Byte1]: 58
7878 11:47:03.877026
7879 11:47:03.877349 Set Vref, RX VrefLevel [Byte0]: 59
7880 11:47:03.880524 [Byte1]: 59
7881 11:47:03.884760
7882 11:47:03.885090 Set Vref, RX VrefLevel [Byte0]: 60
7883 11:47:03.891135 [Byte1]: 60
7884 11:47:03.891460
7885 11:47:03.894218 Set Vref, RX VrefLevel [Byte0]: 61
7886 11:47:03.897611 [Byte1]: 61
7887 11:47:03.897939
7888 11:47:03.901059 Set Vref, RX VrefLevel [Byte0]: 62
7889 11:47:03.904546 [Byte1]: 62
7890 11:47:03.904850
7891 11:47:03.907566 Set Vref, RX VrefLevel [Byte0]: 63
7892 11:47:03.910924 [Byte1]: 63
7893 11:47:03.914991
7894 11:47:03.915401 Set Vref, RX VrefLevel [Byte0]: 64
7895 11:47:03.917993 [Byte1]: 64
7896 11:47:03.922593
7897 11:47:03.923049 Set Vref, RX VrefLevel [Byte0]: 65
7898 11:47:03.925737 [Byte1]: 65
7899 11:47:03.930252
7900 11:47:03.930735 Set Vref, RX VrefLevel [Byte0]: 66
7901 11:47:03.933233 [Byte1]: 66
7902 11:47:03.937613
7903 11:47:03.938047 Set Vref, RX VrefLevel [Byte0]: 67
7904 11:47:03.940837 [Byte1]: 67
7905 11:47:03.945373
7906 11:47:03.945835 Set Vref, RX VrefLevel [Byte0]: 68
7907 11:47:03.948368 [Byte1]: 68
7908 11:47:03.952779
7909 11:47:03.953212 Set Vref, RX VrefLevel [Byte0]: 69
7910 11:47:03.956326 [Byte1]: 69
7911 11:47:03.960543
7912 11:47:03.960925 Set Vref, RX VrefLevel [Byte0]: 70
7913 11:47:03.963497 [Byte1]: 70
7914 11:47:03.967699
7915 11:47:03.968051 Set Vref, RX VrefLevel [Byte0]: 71
7916 11:47:03.971118 [Byte1]: 71
7917 11:47:03.975605
7918 11:47:03.975906 Set Vref, RX VrefLevel [Byte0]: 72
7919 11:47:03.978805 [Byte1]: 72
7920 11:47:03.983297
7921 11:47:03.983600 Set Vref, RX VrefLevel [Byte0]: 73
7922 11:47:03.986409 [Byte1]: 73
7923 11:47:03.990495
7924 11:47:03.990831 Set Vref, RX VrefLevel [Byte0]: 74
7925 11:47:03.994035 [Byte1]: 74
7926 11:47:03.998303
7927 11:47:03.998606 Set Vref, RX VrefLevel [Byte0]: 75
7928 11:47:04.001647 [Byte1]: 75
7929 11:47:04.005686
7930 11:47:04.005988 Set Vref, RX VrefLevel [Byte0]: 76
7931 11:47:04.008949 [Byte1]: 76
7932 11:47:04.013112
7933 11:47:04.013197 Set Vref, RX VrefLevel [Byte0]: 77
7934 11:47:04.016712 [Byte1]: 77
7935 11:47:04.020439
7936 11:47:04.020558 Set Vref, RX VrefLevel [Byte0]: 78
7937 11:47:04.024139 [Byte1]: 78
7938 11:47:04.028207
7939 11:47:04.028323 Set Vref, RX VrefLevel [Byte0]: 79
7940 11:47:04.031367 [Byte1]: 79
7941 11:47:04.035818
7942 11:47:04.035927 Set Vref, RX VrefLevel [Byte0]: 80
7943 11:47:04.039087 [Byte1]: 80
7944 11:47:04.043291
7945 11:47:04.043412 Set Vref, RX VrefLevel [Byte0]: 81
7946 11:47:04.046579 [Byte1]: 81
7947 11:47:04.051150
7948 11:47:04.051257 Set Vref, RX VrefLevel [Byte0]: 82
7949 11:47:04.054146 [Byte1]: 82
7950 11:47:04.058617
7951 11:47:04.058730 Final RX Vref Byte 0 = 61 to rank0
7952 11:47:04.061733 Final RX Vref Byte 1 = 62 to rank0
7953 11:47:04.065115 Final RX Vref Byte 0 = 61 to rank1
7954 11:47:04.068674 Final RX Vref Byte 1 = 62 to rank1==
7955 11:47:04.071778 Dram Type= 6, Freq= 0, CH_0, rank 0
7956 11:47:04.078519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 11:47:04.078635 ==
7958 11:47:04.078741 DQS Delay:
7959 11:47:04.081762 DQS0 = 0, DQS1 = 0
7960 11:47:04.081872 DQM Delay:
7961 11:47:04.081969 DQM0 = 136, DQM1 = 124
7962 11:47:04.084742 DQ Delay:
7963 11:47:04.088254 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7964 11:47:04.091492 DQ4 =140, DQ5 =126, DQ6 =142, DQ7 =144
7965 11:47:04.094787 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7966 11:47:04.098040 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7967 11:47:04.098114
7968 11:47:04.098177
7969 11:47:04.098237
7970 11:47:04.101281 [DramC_TX_OE_Calibration] TA2
7971 11:47:04.104868 Original DQ_B0 (3 6) =30, OEN = 27
7972 11:47:04.107973 Original DQ_B1 (3 6) =30, OEN = 27
7973 11:47:04.111205 24, 0x0, End_B0=24 End_B1=24
7974 11:47:04.114525 25, 0x0, End_B0=25 End_B1=25
7975 11:47:04.114640 26, 0x0, End_B0=26 End_B1=26
7976 11:47:04.117783 27, 0x0, End_B0=27 End_B1=27
7977 11:47:04.120932 28, 0x0, End_B0=28 End_B1=28
7978 11:47:04.124658 29, 0x0, End_B0=29 End_B1=29
7979 11:47:04.124771 30, 0x0, End_B0=30 End_B1=30
7980 11:47:04.127871 31, 0x4545, End_B0=30 End_B1=30
7981 11:47:04.131029 Byte0 end_step=30 best_step=27
7982 11:47:04.134635 Byte1 end_step=30 best_step=27
7983 11:47:04.137758 Byte0 TX OE(2T, 0.5T) = (3, 3)
7984 11:47:04.140951 Byte1 TX OE(2T, 0.5T) = (3, 3)
7985 11:47:04.141047
7986 11:47:04.141147
7987 11:47:04.147531 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7988 11:47:04.150725 CH0 RK0: MR19=303, MR18=1F1D
7989 11:47:04.157567 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
7990 11:47:04.157674
7991 11:47:04.160934 ----->DramcWriteLeveling(PI) begin...
7992 11:47:04.161066 ==
7993 11:47:04.164202 Dram Type= 6, Freq= 0, CH_0, rank 1
7994 11:47:04.167208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7995 11:47:04.167330 ==
7996 11:47:04.170897 Write leveling (Byte 0): 38 => 38
7997 11:47:04.174238 Write leveling (Byte 1): 30 => 30
7998 11:47:04.177368 DramcWriteLeveling(PI) end<-----
7999 11:47:04.177485
8000 11:47:04.177595 ==
8001 11:47:04.180503 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 11:47:04.184080 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 11:47:04.187257 ==
8004 11:47:04.187357 [Gating] SW mode calibration
8005 11:47:04.197372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8006 11:47:04.200556 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8007 11:47:04.203777 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 11:47:04.210130 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 11:47:04.213396 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8010 11:47:04.216961 1 4 12 | B1->B0 | 2626 3131 | 0 1 | (0 0) (1 1)
8011 11:47:04.223410 1 4 16 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8012 11:47:04.226532 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 11:47:04.230020 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 11:47:04.236786 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 11:47:04.239875 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 11:47:04.243113 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 11:47:04.249857 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 11:47:04.252959 1 5 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (0 1)
8019 11:47:04.256582 1 5 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8020 11:47:04.263244 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 11:47:04.266313 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 11:47:04.269864 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 11:47:04.276215 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 11:47:04.279690 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 11:47:04.282936 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
8026 11:47:04.289611 1 6 12 | B1->B0 | 2b2b 4141 | 0 0 | (0 0) (1 1)
8027 11:47:04.292781 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 11:47:04.296308 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 11:47:04.302589 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 11:47:04.305905 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 11:47:04.309609 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 11:47:04.316192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 11:47:04.319478 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8034 11:47:04.322629 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8035 11:47:04.329231 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8036 11:47:04.332323 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 11:47:04.335982 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 11:47:04.342191 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 11:47:04.345919 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 11:47:04.348989 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:47:04.355364 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:47:04.358619 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 11:47:04.361889 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 11:47:04.368688 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 11:47:04.372152 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 11:47:04.375460 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 11:47:04.382146 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:47:04.385250 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 11:47:04.388608 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8050 11:47:04.395140 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 11:47:04.395229 Total UI for P1: 0, mck2ui 16
8052 11:47:04.402171 best dqsien dly found for B0: ( 1, 9, 8)
8053 11:47:04.405300 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8054 11:47:04.408532 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 11:47:04.411726 Total UI for P1: 0, mck2ui 16
8056 11:47:04.415117 best dqsien dly found for B1: ( 1, 9, 14)
8057 11:47:04.418308 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8058 11:47:04.421674 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8059 11:47:04.421760
8060 11:47:04.428345 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8061 11:47:04.431608 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8062 11:47:04.431694 [Gating] SW calibration Done
8063 11:47:04.435118 ==
8064 11:47:04.438201 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 11:47:04.441631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 11:47:04.441716 ==
8067 11:47:04.441784 RX Vref Scan: 0
8068 11:47:04.441847
8069 11:47:04.444741 RX Vref 0 -> 0, step: 1
8070 11:47:04.444827
8071 11:47:04.448018 RX Delay 0 -> 252, step: 8
8072 11:47:04.451557 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8073 11:47:04.455044 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8074 11:47:04.458190 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8075 11:47:04.464666 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8076 11:47:04.467848 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8077 11:47:04.471537 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8078 11:47:04.474508 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8079 11:47:04.478010 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8080 11:47:04.484457 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8081 11:47:04.487627 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8082 11:47:04.491094 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8083 11:47:04.494425 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8084 11:47:04.501149 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8085 11:47:04.504334 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8086 11:47:04.507292 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8087 11:47:04.511020 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8088 11:47:04.511128 ==
8089 11:47:04.514281 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 11:47:04.520682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 11:47:04.520762 ==
8092 11:47:04.520865 DQS Delay:
8093 11:47:04.524071 DQS0 = 0, DQS1 = 0
8094 11:47:04.524147 DQM Delay:
8095 11:47:04.524226 DQM0 = 136, DQM1 = 125
8096 11:47:04.527328 DQ Delay:
8097 11:47:04.530621 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8098 11:47:04.533899 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8099 11:47:04.537027 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8100 11:47:04.540207 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8101 11:47:04.540287
8102 11:47:04.540369
8103 11:47:04.540448 ==
8104 11:47:04.543785 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 11:47:04.550471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 11:47:04.550573 ==
8107 11:47:04.550659
8108 11:47:04.550739
8109 11:47:04.550824 TX Vref Scan disable
8110 11:47:04.553681 == TX Byte 0 ==
8111 11:47:04.556920 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8112 11:47:04.563547 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8113 11:47:04.563633 == TX Byte 1 ==
8114 11:47:04.566735 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8115 11:47:04.573121 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8116 11:47:04.573208 ==
8117 11:47:04.576849 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 11:47:04.579919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 11:47:04.579998 ==
8120 11:47:04.594756
8121 11:47:04.598058 TX Vref early break, caculate TX vref
8122 11:47:04.601255 TX Vref=16, minBit 0, minWin=23, winSum=388
8123 11:47:04.604598 TX Vref=18, minBit 0, minWin=24, winSum=401
8124 11:47:04.607654 TX Vref=20, minBit 8, minWin=24, winSum=408
8125 11:47:04.611115 TX Vref=22, minBit 0, minWin=25, winSum=414
8126 11:47:04.614613 TX Vref=24, minBit 0, minWin=25, winSum=427
8127 11:47:04.620834 TX Vref=26, minBit 8, minWin=25, winSum=431
8128 11:47:04.624464 TX Vref=28, minBit 2, minWin=26, winSum=434
8129 11:47:04.627754 TX Vref=30, minBit 0, minWin=25, winSum=430
8130 11:47:04.630835 TX Vref=32, minBit 0, minWin=25, winSum=422
8131 11:47:04.634096 TX Vref=34, minBit 0, minWin=25, winSum=412
8132 11:47:04.640638 TX Vref=36, minBit 2, minWin=24, winSum=406
8133 11:47:04.643738 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 28
8134 11:47:04.643848
8135 11:47:04.647379 Final TX Range 0 Vref 28
8136 11:47:04.647521
8137 11:47:04.647619 ==
8138 11:47:04.650756 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 11:47:04.653920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 11:47:04.657212 ==
8141 11:47:04.657288
8142 11:47:04.657351
8143 11:47:04.657410 TX Vref Scan disable
8144 11:47:04.664227 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8145 11:47:04.664329 == TX Byte 0 ==
8146 11:47:04.667179 u2DelayCellOfst[0]=13 cells (4 PI)
8147 11:47:04.670765 u2DelayCellOfst[1]=20 cells (6 PI)
8148 11:47:04.673687 u2DelayCellOfst[2]=13 cells (4 PI)
8149 11:47:04.677387 u2DelayCellOfst[3]=13 cells (4 PI)
8150 11:47:04.680715 u2DelayCellOfst[4]=10 cells (3 PI)
8151 11:47:04.683864 u2DelayCellOfst[5]=0 cells (0 PI)
8152 11:47:04.686963 u2DelayCellOfst[6]=20 cells (6 PI)
8153 11:47:04.690224 u2DelayCellOfst[7]=20 cells (6 PI)
8154 11:47:04.693581 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8155 11:47:04.697120 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8156 11:47:04.700346 == TX Byte 1 ==
8157 11:47:04.703602 u2DelayCellOfst[8]=0 cells (0 PI)
8158 11:47:04.706781 u2DelayCellOfst[9]=0 cells (0 PI)
8159 11:47:04.710154 u2DelayCellOfst[10]=3 cells (1 PI)
8160 11:47:04.713370 u2DelayCellOfst[11]=3 cells (1 PI)
8161 11:47:04.716933 u2DelayCellOfst[12]=13 cells (4 PI)
8162 11:47:04.720277 u2DelayCellOfst[13]=10 cells (3 PI)
8163 11:47:04.720390 u2DelayCellOfst[14]=13 cells (4 PI)
8164 11:47:04.723229 u2DelayCellOfst[15]=10 cells (3 PI)
8165 11:47:04.730122 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8166 11:47:04.733105 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8167 11:47:04.736453 DramC Write-DBI on
8168 11:47:04.736602 ==
8169 11:47:04.740080 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 11:47:04.743349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 11:47:04.743524 ==
8172 11:47:04.743627
8173 11:47:04.743734
8174 11:47:04.746478 TX Vref Scan disable
8175 11:47:04.746590 == TX Byte 0 ==
8176 11:47:04.752864 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8177 11:47:04.752973 == TX Byte 1 ==
8178 11:47:04.756518 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8179 11:47:04.759645 DramC Write-DBI off
8180 11:47:04.759816
8181 11:47:04.759920 [DATLAT]
8182 11:47:04.762958 Freq=1600, CH0 RK1
8183 11:47:04.763060
8184 11:47:04.763153 DATLAT Default: 0xf
8185 11:47:04.766269 0, 0xFFFF, sum = 0
8186 11:47:04.769396 1, 0xFFFF, sum = 0
8187 11:47:04.769481 2, 0xFFFF, sum = 0
8188 11:47:04.772946 3, 0xFFFF, sum = 0
8189 11:47:04.773069 4, 0xFFFF, sum = 0
8190 11:47:04.776219 5, 0xFFFF, sum = 0
8191 11:47:04.776306 6, 0xFFFF, sum = 0
8192 11:47:04.779425 7, 0xFFFF, sum = 0
8193 11:47:04.779512 8, 0xFFFF, sum = 0
8194 11:47:04.782732 9, 0xFFFF, sum = 0
8195 11:47:04.782816 10, 0xFFFF, sum = 0
8196 11:47:04.786118 11, 0xFFFF, sum = 0
8197 11:47:04.786205 12, 0xFFFF, sum = 0
8198 11:47:04.789169 13, 0xFFFF, sum = 0
8199 11:47:04.789283 14, 0x0, sum = 1
8200 11:47:04.792724 15, 0x0, sum = 2
8201 11:47:04.792812 16, 0x0, sum = 3
8202 11:47:04.796074 17, 0x0, sum = 4
8203 11:47:04.796161 best_step = 15
8204 11:47:04.796229
8205 11:47:04.796292 ==
8206 11:47:04.799513 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 11:47:04.805879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 11:47:04.805965 ==
8209 11:47:04.806032 RX Vref Scan: 0
8210 11:47:04.806095
8211 11:47:04.808955 RX Vref 0 -> 0, step: 1
8212 11:47:04.809049
8213 11:47:04.812601 RX Delay 11 -> 252, step: 4
8214 11:47:04.815788 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8215 11:47:04.818981 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8216 11:47:04.822400 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8217 11:47:04.828756 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8218 11:47:04.832152 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8219 11:47:04.835389 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8220 11:47:04.838984 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8221 11:47:04.842273 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8222 11:47:04.848294 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8223 11:47:04.851764 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8224 11:47:04.855375 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8225 11:47:04.858565 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8226 11:47:04.865200 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8227 11:47:04.868304 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8228 11:47:04.871556 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8229 11:47:04.875252 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8230 11:47:04.875350 ==
8231 11:47:04.878173 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 11:47:04.884659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 11:47:04.884765 ==
8234 11:47:04.884858 DQS Delay:
8235 11:47:04.887804 DQS0 = 0, DQS1 = 0
8236 11:47:04.887913 DQM Delay:
8237 11:47:04.891085 DQM0 = 133, DQM1 = 123
8238 11:47:04.891193 DQ Delay:
8239 11:47:04.894604 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8240 11:47:04.897819 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8241 11:47:04.901126 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8242 11:47:04.904363 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8243 11:47:04.904450
8244 11:47:04.904514
8245 11:47:04.904654
8246 11:47:04.907837 [DramC_TX_OE_Calibration] TA2
8247 11:47:04.911135 Original DQ_B0 (3 6) =30, OEN = 27
8248 11:47:04.914294 Original DQ_B1 (3 6) =30, OEN = 27
8249 11:47:04.917453 24, 0x0, End_B0=24 End_B1=24
8250 11:47:04.921211 25, 0x0, End_B0=25 End_B1=25
8251 11:47:04.921312 26, 0x0, End_B0=26 End_B1=26
8252 11:47:04.924132 27, 0x0, End_B0=27 End_B1=27
8253 11:47:04.927638 28, 0x0, End_B0=28 End_B1=28
8254 11:47:04.930826 29, 0x0, End_B0=29 End_B1=29
8255 11:47:04.930917 30, 0x0, End_B0=30 End_B1=30
8256 11:47:04.933964 31, 0x4141, End_B0=30 End_B1=30
8257 11:47:04.937637 Byte0 end_step=30 best_step=27
8258 11:47:04.940807 Byte1 end_step=30 best_step=27
8259 11:47:04.944129 Byte0 TX OE(2T, 0.5T) = (3, 3)
8260 11:47:04.947475 Byte1 TX OE(2T, 0.5T) = (3, 3)
8261 11:47:04.947559
8262 11:47:04.947625
8263 11:47:04.953846 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8264 11:47:04.957160 CH0 RK1: MR19=303, MR18=1F0C
8265 11:47:04.963902 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8266 11:47:04.967021 [RxdqsGatingPostProcess] freq 1600
8267 11:47:04.974017 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8268 11:47:04.974104 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 11:47:04.977242 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 11:47:04.980174 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 11:47:04.983795 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 11:47:04.986931 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 11:47:04.990611 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 11:47:04.993674 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 11:47:04.996762 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 11:47:05.000227 Pre-setting of DQS Precalculation
8277 11:47:05.003565 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8278 11:47:05.003681 ==
8279 11:47:05.006800 Dram Type= 6, Freq= 0, CH_1, rank 0
8280 11:47:05.013160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 11:47:05.013248 ==
8282 11:47:05.016437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8283 11:47:05.023181 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8284 11:47:05.026405 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8285 11:47:05.033018 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8286 11:47:05.041262 [CA 0] Center 42 (12~72) winsize 61
8287 11:47:05.044254 [CA 1] Center 42 (13~72) winsize 60
8288 11:47:05.047521 [CA 2] Center 38 (9~68) winsize 60
8289 11:47:05.051173 [CA 3] Center 37 (8~67) winsize 60
8290 11:47:05.054519 [CA 4] Center 37 (8~67) winsize 60
8291 11:47:05.057823 [CA 5] Center 37 (7~67) winsize 61
8292 11:47:05.057908
8293 11:47:05.060981 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8294 11:47:05.061066
8295 11:47:05.064031 [CATrainingPosCal] consider 1 rank data
8296 11:47:05.067694 u2DelayCellTimex100 = 285/100 ps
8297 11:47:05.070908 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8298 11:47:05.077617 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8299 11:47:05.080789 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8300 11:47:05.084090 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8301 11:47:05.087569 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8302 11:47:05.090844 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8303 11:47:05.090933
8304 11:47:05.094259 CA PerBit enable=1, Macro0, CA PI delay=37
8305 11:47:05.094355
8306 11:47:05.097571 [CBTSetCACLKResult] CA Dly = 37
8307 11:47:05.100781 CS Dly: 9 (0~40)
8308 11:47:05.104011 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8309 11:47:05.107154 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8310 11:47:05.107302 ==
8311 11:47:05.110522 Dram Type= 6, Freq= 0, CH_1, rank 1
8312 11:47:05.113709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 11:47:05.117333 ==
8314 11:47:05.120691 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8315 11:47:05.123796 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8316 11:47:05.130619 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8317 11:47:05.136721 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8318 11:47:05.144155 [CA 0] Center 42 (13~72) winsize 60
8319 11:47:05.147320 [CA 1] Center 42 (12~72) winsize 61
8320 11:47:05.150907 [CA 2] Center 38 (9~68) winsize 60
8321 11:47:05.154113 [CA 3] Center 37 (8~67) winsize 60
8322 11:47:05.157305 [CA 4] Center 38 (9~68) winsize 60
8323 11:47:05.160526 [CA 5] Center 37 (8~67) winsize 60
8324 11:47:05.160612
8325 11:47:05.163750 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8326 11:47:05.163840
8327 11:47:05.170676 [CATrainingPosCal] consider 2 rank data
8328 11:47:05.170792 u2DelayCellTimex100 = 285/100 ps
8329 11:47:05.177025 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8330 11:47:05.180306 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8331 11:47:05.183848 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8332 11:47:05.186785 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8333 11:47:05.190322 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8334 11:47:05.193575 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8335 11:47:05.193659
8336 11:47:05.196809 CA PerBit enable=1, Macro0, CA PI delay=37
8337 11:47:05.196894
8338 11:47:05.200189 [CBTSetCACLKResult] CA Dly = 37
8339 11:47:05.203420 CS Dly: 10 (0~42)
8340 11:47:05.206645 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8341 11:47:05.209912 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8342 11:47:05.209994
8343 11:47:05.213200 ----->DramcWriteLeveling(PI) begin...
8344 11:47:05.213285 ==
8345 11:47:05.216449 Dram Type= 6, Freq= 0, CH_1, rank 0
8346 11:47:05.223307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 11:47:05.223390 ==
8348 11:47:05.226524 Write leveling (Byte 0): 24 => 24
8349 11:47:05.229647 Write leveling (Byte 1): 26 => 26
8350 11:47:05.229729 DramcWriteLeveling(PI) end<-----
8351 11:47:05.233316
8352 11:47:05.233398 ==
8353 11:47:05.236601 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 11:47:05.239646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 11:47:05.239731 ==
8356 11:47:05.242889 [Gating] SW mode calibration
8357 11:47:05.249596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8358 11:47:05.256194 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8359 11:47:05.259433 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:47:05.262829 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 11:47:05.265987 1 4 8 | B1->B0 | 2a2a 2c2c | 0 0 | (0 0) (1 1)
8362 11:47:05.272843 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 11:47:05.275990 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 11:47:05.279112 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 11:47:05.285547 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 11:47:05.289024 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 11:47:05.292362 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 11:47:05.299175 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8369 11:47:05.302560 1 5 8 | B1->B0 | 2d2d 2c2c | 0 0 | (1 0) (1 0)
8370 11:47:05.305825 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8371 11:47:05.312092 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 11:47:05.315624 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 11:47:05.318846 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 11:47:05.325835 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 11:47:05.329151 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 11:47:05.332191 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8377 11:47:05.339106 1 6 8 | B1->B0 | 3333 3f3f | 0 0 | (0 0) (0 0)
8378 11:47:05.342143 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 11:47:05.345644 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 11:47:05.352233 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 11:47:05.355586 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 11:47:05.358767 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 11:47:05.365395 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 11:47:05.368511 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8385 11:47:05.372107 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8386 11:47:05.378456 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8387 11:47:05.381837 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 11:47:05.385245 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 11:47:05.391931 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 11:47:05.395376 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 11:47:05.398663 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 11:47:05.405566 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:47:05.408685 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:47:05.411929 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:47:05.418018 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:47:05.421754 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:47:05.424904 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:47:05.431380 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:47:05.434973 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:47:05.438278 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 11:47:05.444953 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8402 11:47:05.448000 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8403 11:47:05.451353 Total UI for P1: 0, mck2ui 16
8404 11:47:05.454523 best dqsien dly found for B0: ( 1, 9, 6)
8405 11:47:05.457836 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 11:47:05.460794 Total UI for P1: 0, mck2ui 16
8407 11:47:05.464507 best dqsien dly found for B1: ( 1, 9, 8)
8408 11:47:05.467610 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8409 11:47:05.470891 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8410 11:47:05.470974
8411 11:47:05.477796 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8412 11:47:05.480792 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8413 11:47:05.484071 [Gating] SW calibration Done
8414 11:47:05.484153 ==
8415 11:47:05.487664 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 11:47:05.490868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 11:47:05.490991 ==
8418 11:47:05.491096 RX Vref Scan: 0
8419 11:47:05.491185
8420 11:47:05.494066 RX Vref 0 -> 0, step: 1
8421 11:47:05.494145
8422 11:47:05.497520 RX Delay 0 -> 252, step: 8
8423 11:47:05.500733 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8424 11:47:05.504509 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8425 11:47:05.507393 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8426 11:47:05.514032 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8427 11:47:05.517561 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8428 11:47:05.520645 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8429 11:47:05.523990 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8430 11:47:05.527121 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8431 11:47:05.533650 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8432 11:47:05.537255 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8433 11:47:05.540488 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8434 11:47:05.544072 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8435 11:47:05.547239 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8436 11:47:05.553639 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8437 11:47:05.557214 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8438 11:47:05.560492 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8439 11:47:05.560790 ==
8440 11:47:05.563663 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 11:47:05.570374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 11:47:05.570856 ==
8443 11:47:05.571198 DQS Delay:
8444 11:47:05.571512 DQS0 = 0, DQS1 = 0
8445 11:47:05.573580 DQM Delay:
8446 11:47:05.573997 DQM0 = 136, DQM1 = 130
8447 11:47:05.576891 DQ Delay:
8448 11:47:05.580091 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8449 11:47:05.583196 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8450 11:47:05.586872 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8451 11:47:05.590177 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8452 11:47:05.590597
8453 11:47:05.591034
8454 11:47:05.591356 ==
8455 11:47:05.593237 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 11:47:05.596639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 11:47:05.600423 ==
8458 11:47:05.600942
8459 11:47:05.601340
8460 11:47:05.601656 TX Vref Scan disable
8461 11:47:05.603379 == TX Byte 0 ==
8462 11:47:05.606899 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8463 11:47:05.610187 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8464 11:47:05.613237 == TX Byte 1 ==
8465 11:47:05.617091 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8466 11:47:05.620255 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8467 11:47:05.623065 ==
8468 11:47:05.623665 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 11:47:05.629456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 11:47:05.629882 ==
8471 11:47:05.641585
8472 11:47:05.644764 TX Vref early break, caculate TX vref
8473 11:47:05.648081 TX Vref=16, minBit 10, minWin=22, winSum=374
8474 11:47:05.651258 TX Vref=18, minBit 10, minWin=23, winSum=391
8475 11:47:05.654711 TX Vref=20, minBit 15, minWin=23, winSum=399
8476 11:47:05.658045 TX Vref=22, minBit 10, minWin=24, winSum=402
8477 11:47:05.664588 TX Vref=24, minBit 1, minWin=25, winSum=416
8478 11:47:05.667911 TX Vref=26, minBit 15, minWin=25, winSum=425
8479 11:47:05.671174 TX Vref=28, minBit 0, minWin=25, winSum=427
8480 11:47:05.674422 TX Vref=30, minBit 1, minWin=26, winSum=423
8481 11:47:05.677596 TX Vref=32, minBit 9, minWin=25, winSum=415
8482 11:47:05.684114 TX Vref=34, minBit 12, minWin=24, winSum=404
8483 11:47:05.687807 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 30
8484 11:47:05.688273
8485 11:47:05.691176 Final TX Range 0 Vref 30
8486 11:47:05.691639
8487 11:47:05.692008 ==
8488 11:47:05.694520 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 11:47:05.697565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 11:47:05.698293 ==
8491 11:47:05.700610
8492 11:47:05.701154
8493 11:47:05.701534 TX Vref Scan disable
8494 11:47:05.707071 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8495 11:47:05.707538 == TX Byte 0 ==
8496 11:47:05.710856 u2DelayCellOfst[0]=17 cells (5 PI)
8497 11:47:05.713987 u2DelayCellOfst[1]=10 cells (3 PI)
8498 11:47:05.717106 u2DelayCellOfst[2]=0 cells (0 PI)
8499 11:47:05.720376 u2DelayCellOfst[3]=6 cells (2 PI)
8500 11:47:05.723652 u2DelayCellOfst[4]=6 cells (2 PI)
8501 11:47:05.727182 u2DelayCellOfst[5]=17 cells (5 PI)
8502 11:47:05.730450 u2DelayCellOfst[6]=17 cells (5 PI)
8503 11:47:05.733999 u2DelayCellOfst[7]=6 cells (2 PI)
8504 11:47:05.737262 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8505 11:47:05.740428 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8506 11:47:05.744008 == TX Byte 1 ==
8507 11:47:05.747248 u2DelayCellOfst[8]=0 cells (0 PI)
8508 11:47:05.750433 u2DelayCellOfst[9]=6 cells (2 PI)
8509 11:47:05.753821 u2DelayCellOfst[10]=13 cells (4 PI)
8510 11:47:05.757355 u2DelayCellOfst[11]=6 cells (2 PI)
8511 11:47:05.760402 u2DelayCellOfst[12]=17 cells (5 PI)
8512 11:47:05.760966 u2DelayCellOfst[13]=20 cells (6 PI)
8513 11:47:05.763310 u2DelayCellOfst[14]=20 cells (6 PI)
8514 11:47:05.766949 u2DelayCellOfst[15]=20 cells (6 PI)
8515 11:47:05.773440 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8516 11:47:05.776545 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8517 11:47:05.777089 DramC Write-DBI on
8518 11:47:05.779869 ==
8519 11:47:05.783456 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 11:47:05.786801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 11:47:05.787326 ==
8522 11:47:05.787798
8523 11:47:05.788249
8524 11:47:05.789950 TX Vref Scan disable
8525 11:47:05.790452 == TX Byte 0 ==
8526 11:47:05.796198 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8527 11:47:05.796748 == TX Byte 1 ==
8528 11:47:05.800144 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8529 11:47:05.803173 DramC Write-DBI off
8530 11:47:05.803597
8531 11:47:05.803933 [DATLAT]
8532 11:47:05.806541 Freq=1600, CH1 RK0
8533 11:47:05.806976
8534 11:47:05.807315 DATLAT Default: 0xf
8535 11:47:05.809857 0, 0xFFFF, sum = 0
8536 11:47:05.810382 1, 0xFFFF, sum = 0
8537 11:47:05.813086 2, 0xFFFF, sum = 0
8538 11:47:05.813525 3, 0xFFFF, sum = 0
8539 11:47:05.816422 4, 0xFFFF, sum = 0
8540 11:47:05.819769 5, 0xFFFF, sum = 0
8541 11:47:05.820262 6, 0xFFFF, sum = 0
8542 11:47:05.823049 7, 0xFFFF, sum = 0
8543 11:47:05.823521 8, 0xFFFF, sum = 0
8544 11:47:05.826274 9, 0xFFFF, sum = 0
8545 11:47:05.826710 10, 0xFFFF, sum = 0
8546 11:47:05.829516 11, 0xFFFF, sum = 0
8547 11:47:05.830089 12, 0xFFFF, sum = 0
8548 11:47:05.832722 13, 0xFFFF, sum = 0
8549 11:47:05.833300 14, 0x0, sum = 1
8550 11:47:05.836198 15, 0x0, sum = 2
8551 11:47:05.836650 16, 0x0, sum = 3
8552 11:47:05.839241 17, 0x0, sum = 4
8553 11:47:05.839809 best_step = 15
8554 11:47:05.840278
8555 11:47:05.840641 ==
8556 11:47:05.842450 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 11:47:05.846033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 11:47:05.849402 ==
8559 11:47:05.849826 RX Vref Scan: 1
8560 11:47:05.850162
8561 11:47:05.852552 Set Vref Range= 24 -> 127
8562 11:47:05.853111
8563 11:47:05.855951 RX Vref 24 -> 127, step: 1
8564 11:47:05.856358
8565 11:47:05.856823 RX Delay 19 -> 252, step: 4
8566 11:47:05.857240
8567 11:47:05.859096 Set Vref, RX VrefLevel [Byte0]: 24
8568 11:47:05.862212 [Byte1]: 24
8569 11:47:05.866263
8570 11:47:05.866374 Set Vref, RX VrefLevel [Byte0]: 25
8571 11:47:05.869186 [Byte1]: 25
8572 11:47:05.873371
8573 11:47:05.873481 Set Vref, RX VrefLevel [Byte0]: 26
8574 11:47:05.876911 [Byte1]: 26
8575 11:47:05.881146
8576 11:47:05.881256 Set Vref, RX VrefLevel [Byte0]: 27
8577 11:47:05.884207 [Byte1]: 27
8578 11:47:05.889027
8579 11:47:05.889109 Set Vref, RX VrefLevel [Byte0]: 28
8580 11:47:05.892283 [Byte1]: 28
8581 11:47:05.896160
8582 11:47:05.896242 Set Vref, RX VrefLevel [Byte0]: 29
8583 11:47:05.899548 [Byte1]: 29
8584 11:47:05.903761
8585 11:47:05.903877 Set Vref, RX VrefLevel [Byte0]: 30
8586 11:47:05.907397 [Byte1]: 30
8587 11:47:05.911469
8588 11:47:05.911567 Set Vref, RX VrefLevel [Byte0]: 31
8589 11:47:05.914761 [Byte1]: 31
8590 11:47:05.919452
8591 11:47:05.919564 Set Vref, RX VrefLevel [Byte0]: 32
8592 11:47:05.922688 [Byte1]: 32
8593 11:47:05.927009
8594 11:47:05.927212 Set Vref, RX VrefLevel [Byte0]: 33
8595 11:47:05.930148 [Byte1]: 33
8596 11:47:05.934499
8597 11:47:05.935047 Set Vref, RX VrefLevel [Byte0]: 34
8598 11:47:05.938025 [Byte1]: 34
8599 11:47:05.942146
8600 11:47:05.942619 Set Vref, RX VrefLevel [Byte0]: 35
8601 11:47:05.945487 [Byte1]: 35
8602 11:47:05.949461
8603 11:47:05.950146 Set Vref, RX VrefLevel [Byte0]: 36
8604 11:47:05.953058 [Byte1]: 36
8605 11:47:05.957301
8606 11:47:05.957793 Set Vref, RX VrefLevel [Byte0]: 37
8607 11:47:05.960755 [Byte1]: 37
8608 11:47:05.965149
8609 11:47:05.965690 Set Vref, RX VrefLevel [Byte0]: 38
8610 11:47:05.968347 [Byte1]: 38
8611 11:47:05.972658
8612 11:47:05.972765 Set Vref, RX VrefLevel [Byte0]: 39
8613 11:47:05.975137 [Byte1]: 39
8614 11:47:05.979731
8615 11:47:05.979843 Set Vref, RX VrefLevel [Byte0]: 40
8616 11:47:05.983236 [Byte1]: 40
8617 11:47:05.987339
8618 11:47:05.987421 Set Vref, RX VrefLevel [Byte0]: 41
8619 11:47:05.990583 [Byte1]: 41
8620 11:47:05.994754
8621 11:47:05.994849 Set Vref, RX VrefLevel [Byte0]: 42
8622 11:47:05.998191 [Byte1]: 42
8623 11:47:06.002385
8624 11:47:06.002558 Set Vref, RX VrefLevel [Byte0]: 43
8625 11:47:06.005577 [Byte1]: 43
8626 11:47:06.010031
8627 11:47:06.010171 Set Vref, RX VrefLevel [Byte0]: 44
8628 11:47:06.012950 [Byte1]: 44
8629 11:47:06.017327
8630 11:47:06.017410 Set Vref, RX VrefLevel [Byte0]: 45
8631 11:47:06.020937 [Byte1]: 45
8632 11:47:06.024948
8633 11:47:06.025059 Set Vref, RX VrefLevel [Byte0]: 46
8634 11:47:06.028872 [Byte1]: 46
8635 11:47:06.033029
8636 11:47:06.033527 Set Vref, RX VrefLevel [Byte0]: 47
8637 11:47:06.036063 [Byte1]: 47
8638 11:47:06.040252
8639 11:47:06.040864 Set Vref, RX VrefLevel [Byte0]: 48
8640 11:47:06.043928 [Byte1]: 48
8641 11:47:06.048068
8642 11:47:06.048684 Set Vref, RX VrefLevel [Byte0]: 49
8643 11:47:06.051367 [Byte1]: 49
8644 11:47:06.055498
8645 11:47:06.055986 Set Vref, RX VrefLevel [Byte0]: 50
8646 11:47:06.058848 [Byte1]: 50
8647 11:47:06.062902
8648 11:47:06.063528 Set Vref, RX VrefLevel [Byte0]: 51
8649 11:47:06.066552 [Byte1]: 51
8650 11:47:06.070947
8651 11:47:06.071641 Set Vref, RX VrefLevel [Byte0]: 52
8652 11:47:06.074056 [Byte1]: 52
8653 11:47:06.078278
8654 11:47:06.078927 Set Vref, RX VrefLevel [Byte0]: 53
8655 11:47:06.081670 [Byte1]: 53
8656 11:47:06.086191
8657 11:47:06.086689 Set Vref, RX VrefLevel [Byte0]: 54
8658 11:47:06.089439 [Byte1]: 54
8659 11:47:06.093525
8660 11:47:06.093988 Set Vref, RX VrefLevel [Byte0]: 55
8661 11:47:06.097107 [Byte1]: 55
8662 11:47:06.101143
8663 11:47:06.101600 Set Vref, RX VrefLevel [Byte0]: 56
8664 11:47:06.104387 [Byte1]: 56
8665 11:47:06.108640
8666 11:47:06.109248 Set Vref, RX VrefLevel [Byte0]: 57
8667 11:47:06.112211 [Byte1]: 57
8668 11:47:06.116450
8669 11:47:06.116869 Set Vref, RX VrefLevel [Byte0]: 58
8670 11:47:06.119434 [Byte1]: 58
8671 11:47:06.123742
8672 11:47:06.124160 Set Vref, RX VrefLevel [Byte0]: 59
8673 11:47:06.127001 [Byte1]: 59
8674 11:47:06.131437
8675 11:47:06.131886 Set Vref, RX VrefLevel [Byte0]: 60
8676 11:47:06.137603 [Byte1]: 60
8677 11:47:06.138033
8678 11:47:06.141226 Set Vref, RX VrefLevel [Byte0]: 61
8679 11:47:06.144368 [Byte1]: 61
8680 11:47:06.144919
8681 11:47:06.147891 Set Vref, RX VrefLevel [Byte0]: 62
8682 11:47:06.151080 [Byte1]: 62
8683 11:47:06.151634
8684 11:47:06.154723 Set Vref, RX VrefLevel [Byte0]: 63
8685 11:47:06.157854 [Byte1]: 63
8686 11:47:06.161783
8687 11:47:06.162231 Set Vref, RX VrefLevel [Byte0]: 64
8688 11:47:06.164974 [Byte1]: 64
8689 11:47:06.169428
8690 11:47:06.169980 Set Vref, RX VrefLevel [Byte0]: 65
8691 11:47:06.172451 [Byte1]: 65
8692 11:47:06.176852
8693 11:47:06.177447 Set Vref, RX VrefLevel [Byte0]: 66
8694 11:47:06.179908 [Byte1]: 66
8695 11:47:06.184477
8696 11:47:06.185115 Set Vref, RX VrefLevel [Byte0]: 67
8697 11:47:06.187581 [Byte1]: 67
8698 11:47:06.191671
8699 11:47:06.192202 Set Vref, RX VrefLevel [Byte0]: 68
8700 11:47:06.195078 [Byte1]: 68
8701 11:47:06.199582
8702 11:47:06.200009 Set Vref, RX VrefLevel [Byte0]: 69
8703 11:47:06.202832 [Byte1]: 69
8704 11:47:06.207364
8705 11:47:06.207792 Set Vref, RX VrefLevel [Byte0]: 70
8706 11:47:06.210657 [Byte1]: 70
8707 11:47:06.214671
8708 11:47:06.215100 Set Vref, RX VrefLevel [Byte0]: 71
8709 11:47:06.217874 [Byte1]: 71
8710 11:47:06.222174
8711 11:47:06.222602 Set Vref, RX VrefLevel [Byte0]: 72
8712 11:47:06.225493 [Byte1]: 72
8713 11:47:06.229972
8714 11:47:06.230443 Set Vref, RX VrefLevel [Byte0]: 73
8715 11:47:06.236334 [Byte1]: 73
8716 11:47:06.236845
8717 11:47:06.239551 Set Vref, RX VrefLevel [Byte0]: 74
8718 11:47:06.243229 [Byte1]: 74
8719 11:47:06.243708
8720 11:47:06.246556 Final RX Vref Byte 0 = 58 to rank0
8721 11:47:06.249765 Final RX Vref Byte 1 = 63 to rank0
8722 11:47:06.253451 Final RX Vref Byte 0 = 58 to rank1
8723 11:47:06.256668 Final RX Vref Byte 1 = 63 to rank1==
8724 11:47:06.259851 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 11:47:06.263047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 11:47:06.263546 ==
8727 11:47:06.266086 DQS Delay:
8728 11:47:06.266560 DQS0 = 0, DQS1 = 0
8729 11:47:06.266939 DQM Delay:
8730 11:47:06.269694 DQM0 = 134, DQM1 = 130
8731 11:47:06.270170 DQ Delay:
8732 11:47:06.272499 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8733 11:47:06.275953 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8734 11:47:06.282625 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8735 11:47:06.285849 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =138
8736 11:47:06.286325
8737 11:47:06.286699
8738 11:47:06.287045
8739 11:47:06.289350 [DramC_TX_OE_Calibration] TA2
8740 11:47:06.292487 Original DQ_B0 (3 6) =30, OEN = 27
8741 11:47:06.295788 Original DQ_B1 (3 6) =30, OEN = 27
8742 11:47:06.296393 24, 0x0, End_B0=24 End_B1=24
8743 11:47:06.299174 25, 0x0, End_B0=25 End_B1=25
8744 11:47:06.302571 26, 0x0, End_B0=26 End_B1=26
8745 11:47:06.305722 27, 0x0, End_B0=27 End_B1=27
8746 11:47:06.306195 28, 0x0, End_B0=28 End_B1=28
8747 11:47:06.308867 29, 0x0, End_B0=29 End_B1=29
8748 11:47:06.312643 30, 0x0, End_B0=30 End_B1=30
8749 11:47:06.315743 31, 0x4141, End_B0=30 End_B1=30
8750 11:47:06.318992 Byte0 end_step=30 best_step=27
8751 11:47:06.322209 Byte1 end_step=30 best_step=27
8752 11:47:06.322691 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 11:47:06.325751 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 11:47:06.326223
8755 11:47:06.326603
8756 11:47:06.335256 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8757 11:47:06.338971 CH1 RK0: MR19=303, MR18=1725
8758 11:47:06.341928 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8759 11:47:06.345534
8760 11:47:06.348574 ----->DramcWriteLeveling(PI) begin...
8761 11:47:06.349095 ==
8762 11:47:06.351974 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 11:47:06.355499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 11:47:06.356118 ==
8765 11:47:06.358797 Write leveling (Byte 0): 23 => 23
8766 11:47:06.361999 Write leveling (Byte 1): 28 => 28
8767 11:47:06.365102 DramcWriteLeveling(PI) end<-----
8768 11:47:06.365571
8769 11:47:06.365942 ==
8770 11:47:06.368761 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 11:47:06.372001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 11:47:06.372479 ==
8773 11:47:06.375018 [Gating] SW mode calibration
8774 11:47:06.381774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 11:47:06.388560 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 11:47:06.391876 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 11:47:06.395199 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 11:47:06.401560 1 4 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8779 11:47:06.404778 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8780 11:47:06.408462 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 11:47:06.414898 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 11:47:06.418202 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 11:47:06.421307 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 11:47:06.428241 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 11:47:06.431297 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8786 11:47:06.434910 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8787 11:47:06.441282 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 0)
8788 11:47:06.444794 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 11:47:06.447918 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 11:47:06.454636 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 11:47:06.457702 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 11:47:06.461312 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 11:47:06.467128 1 6 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8794 11:47:06.470792 1 6 8 | B1->B0 | 4343 2323 | 0 0 | (0 0) (0 0)
8795 11:47:06.473889 1 6 12 | B1->B0 | 4646 2f2f | 0 0 | (0 0) (0 0)
8796 11:47:06.480613 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 11:47:06.483927 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 11:47:06.487347 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 11:47:06.493493 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 11:47:06.497009 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 11:47:06.500446 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 11:47:06.507106 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8803 11:47:06.510597 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8804 11:47:06.513811 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 11:47:06.516964 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:47:06.523678 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:47:06.527266 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 11:47:06.530492 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 11:47:06.537042 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 11:47:06.540541 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 11:47:06.543975 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 11:47:06.550338 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 11:47:06.553551 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 11:47:06.557056 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 11:47:06.563635 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 11:47:06.566777 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:47:06.570144 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 11:47:06.576889 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8819 11:47:06.580124 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8820 11:47:06.583406 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 11:47:06.587148 Total UI for P1: 0, mck2ui 16
8822 11:47:06.589952 best dqsien dly found for B0: ( 1, 9, 10)
8823 11:47:06.593745 Total UI for P1: 0, mck2ui 16
8824 11:47:06.597011 best dqsien dly found for B1: ( 1, 9, 10)
8825 11:47:06.599916 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8826 11:47:06.603137 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8827 11:47:06.606418
8828 11:47:06.609601 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8829 11:47:06.612964 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8830 11:47:06.616709 [Gating] SW calibration Done
8831 11:47:06.617303 ==
8832 11:47:06.619761 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 11:47:06.623454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 11:47:06.623882 ==
8835 11:47:06.626296 RX Vref Scan: 0
8836 11:47:06.626720
8837 11:47:06.627057 RX Vref 0 -> 0, step: 1
8838 11:47:06.627371
8839 11:47:06.629938 RX Delay 0 -> 252, step: 8
8840 11:47:06.633190 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8841 11:47:06.636300 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8842 11:47:06.643429 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8843 11:47:06.646116 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8844 11:47:06.649541 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8845 11:47:06.652883 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8846 11:47:06.655961 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8847 11:47:06.662582 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8848 11:47:06.665921 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8849 11:47:06.669606 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8850 11:47:06.672671 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 11:47:06.675940 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8852 11:47:06.682828 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8853 11:47:06.685945 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8854 11:47:06.688934 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8855 11:47:06.692628 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8856 11:47:06.693191 ==
8857 11:47:06.695661 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 11:47:06.702636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 11:47:06.703104 ==
8860 11:47:06.703473 DQS Delay:
8861 11:47:06.705695 DQS0 = 0, DQS1 = 0
8862 11:47:06.706169 DQM Delay:
8863 11:47:06.709283 DQM0 = 136, DQM1 = 132
8864 11:47:06.709744 DQ Delay:
8865 11:47:06.712347 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8866 11:47:06.715525 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8867 11:47:06.719105 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8868 11:47:06.722438 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8869 11:47:06.722859
8870 11:47:06.723187
8871 11:47:06.723497 ==
8872 11:47:06.725493 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 11:47:06.731934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 11:47:06.732374 ==
8875 11:47:06.732709
8876 11:47:06.733051
8877 11:47:06.733359 TX Vref Scan disable
8878 11:47:06.735562 == TX Byte 0 ==
8879 11:47:06.738966 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8880 11:47:06.745875 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8881 11:47:06.746298 == TX Byte 1 ==
8882 11:47:06.748923 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8883 11:47:06.755585 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8884 11:47:06.756007 ==
8885 11:47:06.758765 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 11:47:06.761742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 11:47:06.761826 ==
8888 11:47:06.775654
8889 11:47:06.778958 TX Vref early break, caculate TX vref
8890 11:47:06.782128 TX Vref=16, minBit 12, minWin=22, winSum=384
8891 11:47:06.785237 TX Vref=18, minBit 10, minWin=23, winSum=390
8892 11:47:06.788867 TX Vref=20, minBit 9, minWin=23, winSum=397
8893 11:47:06.792034 TX Vref=22, minBit 9, minWin=24, winSum=407
8894 11:47:06.798739 TX Vref=24, minBit 8, minWin=25, winSum=415
8895 11:47:06.801721 TX Vref=26, minBit 9, minWin=25, winSum=420
8896 11:47:06.805486 TX Vref=28, minBit 8, minWin=25, winSum=421
8897 11:47:06.808823 TX Vref=30, minBit 8, minWin=24, winSum=411
8898 11:47:06.811809 TX Vref=32, minBit 9, minWin=24, winSum=409
8899 11:47:06.815444 TX Vref=34, minBit 1, minWin=24, winSum=399
8900 11:47:06.821848 TX Vref=36, minBit 8, minWin=23, winSum=390
8901 11:47:06.825090 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
8902 11:47:06.825186
8903 11:47:06.828242 Final TX Range 0 Vref 28
8904 11:47:06.828337
8905 11:47:06.828412 ==
8906 11:47:06.831710 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 11:47:06.834693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 11:47:06.838393 ==
8909 11:47:06.838603
8910 11:47:06.838712
8911 11:47:06.838809 TX Vref Scan disable
8912 11:47:06.845134 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8913 11:47:06.845371 == TX Byte 0 ==
8914 11:47:06.848199 u2DelayCellOfst[0]=17 cells (5 PI)
8915 11:47:06.851839 u2DelayCellOfst[1]=10 cells (3 PI)
8916 11:47:06.855219 u2DelayCellOfst[2]=0 cells (0 PI)
8917 11:47:06.858395 u2DelayCellOfst[3]=3 cells (1 PI)
8918 11:47:06.862006 u2DelayCellOfst[4]=6 cells (2 PI)
8919 11:47:06.865102 u2DelayCellOfst[5]=17 cells (5 PI)
8920 11:47:06.868267 u2DelayCellOfst[6]=17 cells (5 PI)
8921 11:47:06.872020 u2DelayCellOfst[7]=6 cells (2 PI)
8922 11:47:06.874970 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8923 11:47:06.878836 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8924 11:47:06.881606 == TX Byte 1 ==
8925 11:47:06.885031 u2DelayCellOfst[8]=0 cells (0 PI)
8926 11:47:06.888127 u2DelayCellOfst[9]=3 cells (1 PI)
8927 11:47:06.891614 u2DelayCellOfst[10]=13 cells (4 PI)
8928 11:47:06.894675 u2DelayCellOfst[11]=3 cells (1 PI)
8929 11:47:06.897741 u2DelayCellOfst[12]=17 cells (5 PI)
8930 11:47:06.901369 u2DelayCellOfst[13]=17 cells (5 PI)
8931 11:47:06.904566 u2DelayCellOfst[14]=20 cells (6 PI)
8932 11:47:06.908026 u2DelayCellOfst[15]=17 cells (5 PI)
8933 11:47:06.911162 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 11:47:06.914164 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8935 11:47:06.917674 DramC Write-DBI on
8936 11:47:06.918296 ==
8937 11:47:06.920915 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 11:47:06.924096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 11:47:06.924567 ==
8940 11:47:06.924936
8941 11:47:06.925348
8942 11:47:06.927216 TX Vref Scan disable
8943 11:47:06.930572 == TX Byte 0 ==
8944 11:47:06.934233 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8945 11:47:06.934699 == TX Byte 1 ==
8946 11:47:06.940521 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8947 11:47:06.941130 DramC Write-DBI off
8948 11:47:06.941594
8949 11:47:06.941997 [DATLAT]
8950 11:47:06.943599 Freq=1600, CH1 RK1
8951 11:47:06.944213
8952 11:47:06.947170 DATLAT Default: 0xf
8953 11:47:06.947797 0, 0xFFFF, sum = 0
8954 11:47:06.950625 1, 0xFFFF, sum = 0
8955 11:47:06.951102 2, 0xFFFF, sum = 0
8956 11:47:06.953699 3, 0xFFFF, sum = 0
8957 11:47:06.954172 4, 0xFFFF, sum = 0
8958 11:47:06.956926 5, 0xFFFF, sum = 0
8959 11:47:06.957419 6, 0xFFFF, sum = 0
8960 11:47:06.960021 7, 0xFFFF, sum = 0
8961 11:47:06.960563 8, 0xFFFF, sum = 0
8962 11:47:06.963304 9, 0xFFFF, sum = 0
8963 11:47:06.963731 10, 0xFFFF, sum = 0
8964 11:47:06.966885 11, 0xFFFF, sum = 0
8965 11:47:06.967378 12, 0xFFFF, sum = 0
8966 11:47:06.970251 13, 0xFFFF, sum = 0
8967 11:47:06.970681 14, 0x0, sum = 1
8968 11:47:06.973225 15, 0x0, sum = 2
8969 11:47:06.973650 16, 0x0, sum = 3
8970 11:47:06.976601 17, 0x0, sum = 4
8971 11:47:06.977108 best_step = 15
8972 11:47:06.977447
8973 11:47:06.977762 ==
8974 11:47:06.979798 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 11:47:06.986528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 11:47:06.987023 ==
8977 11:47:06.987586 RX Vref Scan: 0
8978 11:47:06.988188
8979 11:47:06.989665 RX Vref 0 -> 0, step: 1
8980 11:47:06.990200
8981 11:47:06.993337 RX Delay 19 -> 252, step: 4
8982 11:47:06.996414 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8983 11:47:06.999626 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8984 11:47:07.006413 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8985 11:47:07.009222 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8986 11:47:07.012710 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8987 11:47:07.015944 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8988 11:47:07.019447 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8989 11:47:07.022542 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8990 11:47:07.029098 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8991 11:47:07.032853 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8992 11:47:07.036018 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8993 11:47:07.038955 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8994 11:47:07.045750 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8995 11:47:07.048795 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8996 11:47:07.052488 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8997 11:47:07.055629 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8998 11:47:07.056049 ==
8999 11:47:07.058931 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 11:47:07.065539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 11:47:07.065964 ==
9002 11:47:07.066298 DQS Delay:
9003 11:47:07.068719 DQS0 = 0, DQS1 = 0
9004 11:47:07.069165 DQM Delay:
9005 11:47:07.069503 DQM0 = 133, DQM1 = 129
9006 11:47:07.071875 DQ Delay:
9007 11:47:07.075336 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
9008 11:47:07.078612 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9009 11:47:07.081905 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9010 11:47:07.085226 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9011 11:47:07.085649
9012 11:47:07.085980
9013 11:47:07.086290
9014 11:47:07.088702 [DramC_TX_OE_Calibration] TA2
9015 11:47:07.091757 Original DQ_B0 (3 6) =30, OEN = 27
9016 11:47:07.095289 Original DQ_B1 (3 6) =30, OEN = 27
9017 11:47:07.098529 24, 0x0, End_B0=24 End_B1=24
9018 11:47:07.099157 25, 0x0, End_B0=25 End_B1=25
9019 11:47:07.101788 26, 0x0, End_B0=26 End_B1=26
9020 11:47:07.105052 27, 0x0, End_B0=27 End_B1=27
9021 11:47:07.108525 28, 0x0, End_B0=28 End_B1=28
9022 11:47:07.111687 29, 0x0, End_B0=29 End_B1=29
9023 11:47:07.112150 30, 0x0, End_B0=30 End_B1=30
9024 11:47:07.114921 31, 0x4545, End_B0=30 End_B1=30
9025 11:47:07.118520 Byte0 end_step=30 best_step=27
9026 11:47:07.121723 Byte1 end_step=30 best_step=27
9027 11:47:07.124718 Byte0 TX OE(2T, 0.5T) = (3, 3)
9028 11:47:07.128084 Byte1 TX OE(2T, 0.5T) = (3, 3)
9029 11:47:07.128659
9030 11:47:07.129073
9031 11:47:07.134870 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
9032 11:47:07.138181 CH1 RK1: MR19=303, MR18=1A05
9033 11:47:07.144596 CH1_RK1: MR19=0x303, MR18=0x1A05, DQSOSC=396, MR23=63, INC=23, DEC=15
9034 11:47:07.148198 [RxdqsGatingPostProcess] freq 1600
9035 11:47:07.154873 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9036 11:47:07.155407 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 11:47:07.157911 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 11:47:07.161089 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 11:47:07.164329 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 11:47:07.167542 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 11:47:07.171142 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 11:47:07.174533 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 11:47:07.177815 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 11:47:07.181331 Pre-setting of DQS Precalculation
9045 11:47:07.184407 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9046 11:47:07.194391 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9047 11:47:07.200816 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 11:47:07.201319
9049 11:47:07.201687
9050 11:47:07.204093 [Calibration Summary] 3200 Mbps
9051 11:47:07.204561 CH 0, Rank 0
9052 11:47:07.207424 SW Impedance : PASS
9053 11:47:07.208004 DUTY Scan : NO K
9054 11:47:07.211067 ZQ Calibration : PASS
9055 11:47:07.214262 Jitter Meter : NO K
9056 11:47:07.214824 CBT Training : PASS
9057 11:47:07.217097 Write leveling : PASS
9058 11:47:07.220665 RX DQS gating : PASS
9059 11:47:07.221302 RX DQ/DQS(RDDQC) : PASS
9060 11:47:07.224090 TX DQ/DQS : PASS
9061 11:47:07.227184 RX DATLAT : PASS
9062 11:47:07.227647 RX DQ/DQS(Engine): PASS
9063 11:47:07.230829 TX OE : PASS
9064 11:47:07.231296 All Pass.
9065 11:47:07.231668
9066 11:47:07.234046 CH 0, Rank 1
9067 11:47:07.234514 SW Impedance : PASS
9068 11:47:07.237093 DUTY Scan : NO K
9069 11:47:07.240187 ZQ Calibration : PASS
9070 11:47:07.240651 Jitter Meter : NO K
9071 11:47:07.244144 CBT Training : PASS
9072 11:47:07.246847 Write leveling : PASS
9073 11:47:07.247319 RX DQS gating : PASS
9074 11:47:07.250578 RX DQ/DQS(RDDQC) : PASS
9075 11:47:07.251073 TX DQ/DQS : PASS
9076 11:47:07.253602 RX DATLAT : PASS
9077 11:47:07.256863 RX DQ/DQS(Engine): PASS
9078 11:47:07.257412 TX OE : PASS
9079 11:47:07.260096 All Pass.
9080 11:47:07.260558
9081 11:47:07.260924 CH 1, Rank 0
9082 11:47:07.263740 SW Impedance : PASS
9083 11:47:07.264202 DUTY Scan : NO K
9084 11:47:07.266902 ZQ Calibration : PASS
9085 11:47:07.269998 Jitter Meter : NO K
9086 11:47:07.270479 CBT Training : PASS
9087 11:47:07.273279 Write leveling : PASS
9088 11:47:07.276944 RX DQS gating : PASS
9089 11:47:07.277439 RX DQ/DQS(RDDQC) : PASS
9090 11:47:07.280092 TX DQ/DQS : PASS
9091 11:47:07.283304 RX DATLAT : PASS
9092 11:47:07.283783 RX DQ/DQS(Engine): PASS
9093 11:47:07.286834 TX OE : PASS
9094 11:47:07.287301 All Pass.
9095 11:47:07.287672
9096 11:47:07.289891 CH 1, Rank 1
9097 11:47:07.290408 SW Impedance : PASS
9098 11:47:07.293202 DUTY Scan : NO K
9099 11:47:07.296582 ZQ Calibration : PASS
9100 11:47:07.297077 Jitter Meter : NO K
9101 11:47:07.299770 CBT Training : PASS
9102 11:47:07.303103 Write leveling : PASS
9103 11:47:07.303570 RX DQS gating : PASS
9104 11:47:07.306308 RX DQ/DQS(RDDQC) : PASS
9105 11:47:07.309613 TX DQ/DQS : PASS
9106 11:47:07.310054 RX DATLAT : PASS
9107 11:47:07.313103 RX DQ/DQS(Engine): PASS
9108 11:47:07.313524 TX OE : PASS
9109 11:47:07.316332 All Pass.
9110 11:47:07.316748
9111 11:47:07.317154 DramC Write-DBI on
9112 11:47:07.319675 PER_BANK_REFRESH: Hybrid Mode
9113 11:47:07.322781 TX_TRACKING: ON
9114 11:47:07.329571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9115 11:47:07.339269 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9116 11:47:07.346163 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 11:47:07.349283 [FAST_K] Save calibration result to emmc
9118 11:47:07.352720 sync common calibartion params.
9119 11:47:07.353293 sync cbt_mode0:1, 1:1
9120 11:47:07.356017 dram_init: ddr_geometry: 2
9121 11:47:07.359201 dram_init: ddr_geometry: 2
9122 11:47:07.362872 dram_init: ddr_geometry: 2
9123 11:47:07.363580 0:dram_rank_size:100000000
9124 11:47:07.366037 1:dram_rank_size:100000000
9125 11:47:07.372590 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9126 11:47:07.373070 DFS_SHUFFLE_HW_MODE: ON
9127 11:47:07.379103 dramc_set_vcore_voltage set vcore to 725000
9128 11:47:07.379522 Read voltage for 1600, 0
9129 11:47:07.382203 Vio18 = 0
9130 11:47:07.382815 Vcore = 725000
9131 11:47:07.383302 Vdram = 0
9132 11:47:07.385849 Vddq = 0
9133 11:47:07.386306 Vmddr = 0
9134 11:47:07.389028 switch to 3200 Mbps bootup
9135 11:47:07.389655 [DramcRunTimeConfig]
9136 11:47:07.390172 PHYPLL
9137 11:47:07.392431 DPM_CONTROL_AFTERK: ON
9138 11:47:07.395520 PER_BANK_REFRESH: ON
9139 11:47:07.395942 REFRESH_OVERHEAD_REDUCTION: ON
9140 11:47:07.398859 CMD_PICG_NEW_MODE: OFF
9141 11:47:07.402370 XRTWTW_NEW_MODE: ON
9142 11:47:07.402789 XRTRTR_NEW_MODE: ON
9143 11:47:07.405522 TX_TRACKING: ON
9144 11:47:07.406003 RDSEL_TRACKING: OFF
9145 11:47:07.408908 DQS Precalculation for DVFS: ON
9146 11:47:07.409399 RX_TRACKING: OFF
9147 11:47:07.412163 HW_GATING DBG: ON
9148 11:47:07.415677 ZQCS_ENABLE_LP4: ON
9149 11:47:07.416099 RX_PICG_NEW_MODE: ON
9150 11:47:07.418606 TX_PICG_NEW_MODE: ON
9151 11:47:07.419055 ENABLE_RX_DCM_DPHY: ON
9152 11:47:07.422060 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9153 11:47:07.425045 DUMMY_READ_FOR_TRACKING: OFF
9154 11:47:07.428375 !!! SPM_CONTROL_AFTERK: OFF
9155 11:47:07.432111 !!! SPM could not control APHY
9156 11:47:07.432661 IMPEDANCE_TRACKING: ON
9157 11:47:07.435508 TEMP_SENSOR: ON
9158 11:47:07.435929 HW_SAVE_FOR_SR: OFF
9159 11:47:07.438468 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9160 11:47:07.442014 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9161 11:47:07.445074 Read ODT Tracking: ON
9162 11:47:07.448439 Refresh Rate DeBounce: ON
9163 11:47:07.448649 DFS_NO_QUEUE_FLUSH: ON
9164 11:47:07.451412 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9165 11:47:07.454480 ENABLE_DFS_RUNTIME_MRW: OFF
9166 11:47:07.458186 DDR_RESERVE_NEW_MODE: ON
9167 11:47:07.458293 MR_CBT_SWITCH_FREQ: ON
9168 11:47:07.461450 =========================
9169 11:47:07.479801 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9170 11:47:07.482941 dram_init: ddr_geometry: 2
9171 11:47:07.501399 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9172 11:47:07.504609 dram_init: dram init end (result: 0)
9173 11:47:07.511201 DRAM-K: Full calibration passed in 24549 msecs
9174 11:47:07.514323 MRC: failed to locate region type 0.
9175 11:47:07.514546 DRAM rank0 size:0x100000000,
9176 11:47:07.517837 DRAM rank1 size=0x100000000
9177 11:47:07.527723 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9178 11:47:07.534617 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9179 11:47:07.540865 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9180 11:47:07.550951 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9181 11:47:07.551528 DRAM rank0 size:0x100000000,
9182 11:47:07.554286 DRAM rank1 size=0x100000000
9183 11:47:07.554843 CBMEM:
9184 11:47:07.557691 IMD: root @ 0xfffff000 254 entries.
9185 11:47:07.560793 IMD: root @ 0xffffec00 62 entries.
9186 11:47:07.563892 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9187 11:47:07.570798 WARNING: RO_VPD is uninitialized or empty.
9188 11:47:07.574007 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9189 11:47:07.581713 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9190 11:47:07.594524 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9191 11:47:07.605830 BS: romstage times (exec / console): total (unknown) / 24041 ms
9192 11:47:07.606473
9193 11:47:07.607020
9194 11:47:07.615560 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9195 11:47:07.619240 ARM64: Exception handlers installed.
9196 11:47:07.622282 ARM64: Testing exception
9197 11:47:07.625618 ARM64: Done test exception
9198 11:47:07.626084 Enumerating buses...
9199 11:47:07.628970 Show all devs... Before device enumeration.
9200 11:47:07.632092 Root Device: enabled 1
9201 11:47:07.635675 CPU_CLUSTER: 0: enabled 1
9202 11:47:07.636139 CPU: 00: enabled 1
9203 11:47:07.638602 Compare with tree...
9204 11:47:07.639068 Root Device: enabled 1
9205 11:47:07.641922 CPU_CLUSTER: 0: enabled 1
9206 11:47:07.645425 CPU: 00: enabled 1
9207 11:47:07.646114 Root Device scanning...
9208 11:47:07.648564 scan_static_bus for Root Device
9209 11:47:07.651902 CPU_CLUSTER: 0 enabled
9210 11:47:07.655219 scan_static_bus for Root Device done
9211 11:47:07.658514 scan_bus: bus Root Device finished in 8 msecs
9212 11:47:07.658934 done
9213 11:47:07.664766 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9214 11:47:07.668271 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9215 11:47:07.675016 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9216 11:47:07.681500 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9217 11:47:07.682015 Allocating resources...
9218 11:47:07.684706 Reading resources...
9219 11:47:07.688088 Root Device read_resources bus 0 link: 0
9220 11:47:07.691273 DRAM rank0 size:0x100000000,
9221 11:47:07.691825 DRAM rank1 size=0x100000000
9222 11:47:07.697968 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9223 11:47:07.698523 CPU: 00 missing read_resources
9224 11:47:07.704710 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9225 11:47:07.707854 Root Device read_resources bus 0 link: 0 done
9226 11:47:07.711315 Done reading resources.
9227 11:47:07.714573 Show resources in subtree (Root Device)...After reading.
9228 11:47:07.717748 Root Device child on link 0 CPU_CLUSTER: 0
9229 11:47:07.721199 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 11:47:07.730979 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 11:47:07.731640 CPU: 00
9232 11:47:07.737588 Root Device assign_resources, bus 0 link: 0
9233 11:47:07.740770 CPU_CLUSTER: 0 missing set_resources
9234 11:47:07.744241 Root Device assign_resources, bus 0 link: 0 done
9235 11:47:07.747471 Done setting resources.
9236 11:47:07.750841 Show resources in subtree (Root Device)...After assigning values.
9237 11:47:07.754163 Root Device child on link 0 CPU_CLUSTER: 0
9238 11:47:07.760657 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 11:47:07.767035 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 11:47:07.770168 CPU: 00
9241 11:47:07.770591 Done allocating resources.
9242 11:47:07.776698 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9243 11:47:07.777234 Enabling resources...
9244 11:47:07.780291 done.
9245 11:47:07.783520 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9246 11:47:07.786914 Initializing devices...
9247 11:47:07.787335 Root Device init
9248 11:47:07.790088 init hardware done!
9249 11:47:07.790510 0x00000018: ctrlr->caps
9250 11:47:07.793401 52.000 MHz: ctrlr->f_max
9251 11:47:07.796572 0.400 MHz: ctrlr->f_min
9252 11:47:07.799910 0x40ff8080: ctrlr->voltages
9253 11:47:07.800336 sclk: 390625
9254 11:47:07.800671 Bus Width = 1
9255 11:47:07.803068 sclk: 390625
9256 11:47:07.803507 Bus Width = 1
9257 11:47:07.806782 Early init status = 3
9258 11:47:07.809603 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9259 11:47:07.813096 in-header: 03 fc 00 00 01 00 00 00
9260 11:47:07.816393 in-data: 00
9261 11:47:07.819926 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9262 11:47:07.824630 in-header: 03 fd 00 00 00 00 00 00
9263 11:47:07.827929 in-data:
9264 11:47:07.831107 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9265 11:47:07.834858 in-header: 03 fc 00 00 01 00 00 00
9266 11:47:07.837912 in-data: 00
9267 11:47:07.841175 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9268 11:47:07.846417 in-header: 03 fd 00 00 00 00 00 00
9269 11:47:07.849603 in-data:
9270 11:47:07.853077 [SSUSB] Setting up USB HOST controller...
9271 11:47:07.856544 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9272 11:47:07.859472 [SSUSB] phy power-on done.
9273 11:47:07.862903 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9274 11:47:07.869617 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9275 11:47:07.872815 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9276 11:47:07.879413 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9277 11:47:07.886082 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9278 11:47:07.892574 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9279 11:47:07.899698 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9280 11:47:07.906201 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9281 11:47:07.909440 SPM: binary array size = 0x9dc
9282 11:47:07.912704 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9283 11:47:07.918981 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9284 11:47:07.926024 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9285 11:47:07.932564 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9286 11:47:07.935664 configure_display: Starting display init
9287 11:47:07.969601 anx7625_power_on_init: Init interface.
9288 11:47:07.973205 anx7625_disable_pd_protocol: Disabled PD feature.
9289 11:47:07.976463 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9290 11:47:08.004036 anx7625_start_dp_work: Secure OCM version=00
9291 11:47:08.007289 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9292 11:47:08.022095 sp_tx_get_edid_block: EDID Block = 1
9293 11:47:08.125110 Extracted contents:
9294 11:47:08.128057 header: 00 ff ff ff ff ff ff 00
9295 11:47:08.131402 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9296 11:47:08.134728 version: 01 04
9297 11:47:08.138117 basic params: 95 1f 11 78 0a
9298 11:47:08.141327 chroma info: 76 90 94 55 54 90 27 21 50 54
9299 11:47:08.144460 established: 00 00 00
9300 11:47:08.150995 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9301 11:47:08.154213 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9302 11:47:08.161226 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9303 11:47:08.167618 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9304 11:47:08.174527 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9305 11:47:08.177345 extensions: 00
9306 11:47:08.177755 checksum: fb
9307 11:47:08.178079
9308 11:47:08.180799 Manufacturer: IVO Model 57d Serial Number 0
9309 11:47:08.183891 Made week 0 of 2020
9310 11:47:08.187291 EDID version: 1.4
9311 11:47:08.187783 Digital display
9312 11:47:08.190876 6 bits per primary color channel
9313 11:47:08.191420 DisplayPort interface
9314 11:47:08.193911 Maximum image size: 31 cm x 17 cm
9315 11:47:08.197063 Gamma: 220%
9316 11:47:08.197509 Check DPMS levels
9317 11:47:08.203858 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9318 11:47:08.207071 First detailed timing is preferred timing
9319 11:47:08.207646 Established timings supported:
9320 11:47:08.210343 Standard timings supported:
9321 11:47:08.213965 Detailed timings
9322 11:47:08.217139 Hex of detail: 383680a07038204018303c0035ae10000019
9323 11:47:08.224032 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9324 11:47:08.227155 0780 0798 07c8 0820 hborder 0
9325 11:47:08.230131 0438 043b 0447 0458 vborder 0
9326 11:47:08.233660 -hsync -vsync
9327 11:47:08.234102 Did detailed timing
9328 11:47:08.239987 Hex of detail: 000000000000000000000000000000000000
9329 11:47:08.243701 Manufacturer-specified data, tag 0
9330 11:47:08.246629 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9331 11:47:08.250070 ASCII string: InfoVision
9332 11:47:08.253335 Hex of detail: 000000fe00523134304e574635205248200a
9333 11:47:08.256529 ASCII string: R140NWF5 RH
9334 11:47:08.257088 Checksum
9335 11:47:08.259863 Checksum: 0xfb (valid)
9336 11:47:08.263284 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9337 11:47:08.266309 DSI data_rate: 832800000 bps
9338 11:47:08.272908 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9339 11:47:08.276339 anx7625_parse_edid: pixelclock(138800).
9340 11:47:08.279612 hactive(1920), hsync(48), hfp(24), hbp(88)
9341 11:47:08.283071 vactive(1080), vsync(12), vfp(3), vbp(17)
9342 11:47:08.286422 anx7625_dsi_config: config dsi.
9343 11:47:08.292684 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9344 11:47:08.306215 anx7625_dsi_config: success to config DSI
9345 11:47:08.309446 anx7625_dp_start: MIPI phy setup OK.
9346 11:47:08.313287 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9347 11:47:08.316357 mtk_ddp_mode_set invalid vrefresh 60
9348 11:47:08.319595 main_disp_path_setup
9349 11:47:08.319676 ovl_layer_smi_id_en
9350 11:47:08.322867 ovl_layer_smi_id_en
9351 11:47:08.322947 ccorr_config
9352 11:47:08.323010 aal_config
9353 11:47:08.326074 gamma_config
9354 11:47:08.326153 postmask_config
9355 11:47:08.329320 dither_config
9356 11:47:08.332863 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9357 11:47:08.339301 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9358 11:47:08.342385 Root Device init finished in 552 msecs
9359 11:47:08.345996 CPU_CLUSTER: 0 init
9360 11:47:08.352780 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9361 11:47:08.359741 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9362 11:47:08.360213 APU_MBOX 0x190000b0 = 0x10001
9363 11:47:08.363114 APU_MBOX 0x190001b0 = 0x10001
9364 11:47:08.366301 APU_MBOX 0x190005b0 = 0x10001
9365 11:47:08.369550 APU_MBOX 0x190006b0 = 0x10001
9366 11:47:08.375583 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9367 11:47:08.385349 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9368 11:47:08.397934 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9369 11:47:08.404608 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9370 11:47:08.416709 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9371 11:47:08.425582 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9372 11:47:08.428894 CPU_CLUSTER: 0 init finished in 81 msecs
9373 11:47:08.432250 Devices initialized
9374 11:47:08.435849 Show all devs... After init.
9375 11:47:08.436419 Root Device: enabled 1
9376 11:47:08.438691 CPU_CLUSTER: 0: enabled 1
9377 11:47:08.442298 CPU: 00: enabled 1
9378 11:47:08.445297 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9379 11:47:08.449037 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9380 11:47:08.452261 ELOG: NV offset 0x57f000 size 0x1000
9381 11:47:08.458958 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9382 11:47:08.465205 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9383 11:47:08.468709 ELOG: Event(17) added with size 13 at 2023-06-15 11:47:03 UTC
9384 11:47:08.475339 out: cmd=0x121: 03 db 21 01 00 00 00 00
9385 11:47:08.478521 in-header: 03 00 00 00 2c 00 00 00
9386 11:47:08.488170 in-data: 5f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9387 11:47:08.495040 ELOG: Event(A1) added with size 10 at 2023-06-15 11:47:03 UTC
9388 11:47:08.501791 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9389 11:47:08.508273 ELOG: Event(A0) added with size 9 at 2023-06-15 11:47:03 UTC
9390 11:47:08.511607 elog_add_boot_reason: Logged dev mode boot
9391 11:47:08.518126 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9392 11:47:08.518801 Finalize devices...
9393 11:47:08.521463 Devices finalized
9394 11:47:08.524625 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9395 11:47:08.527847 Writing coreboot table at 0xffe64000
9396 11:47:08.531139 0. 000000000010a000-0000000000113fff: RAMSTAGE
9397 11:47:08.538030 1. 0000000040000000-00000000400fffff: RAM
9398 11:47:08.540896 2. 0000000040100000-000000004032afff: RAMSTAGE
9399 11:47:08.544217 3. 000000004032b000-00000000545fffff: RAM
9400 11:47:08.547599 4. 0000000054600000-000000005465ffff: BL31
9401 11:47:08.550830 5. 0000000054660000-00000000ffe63fff: RAM
9402 11:47:08.557510 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9403 11:47:08.560534 7. 0000000100000000-000000023fffffff: RAM
9404 11:47:08.564197 Passing 5 GPIOs to payload:
9405 11:47:08.567399 NAME | PORT | POLARITY | VALUE
9406 11:47:08.574150 EC in RW | 0x000000aa | low | undefined
9407 11:47:08.577618 EC interrupt | 0x00000005 | low | undefined
9408 11:47:08.580656 TPM interrupt | 0x000000ab | high | undefined
9409 11:47:08.587466 SD card detect | 0x00000011 | high | undefined
9410 11:47:08.590497 speaker enable | 0x00000093 | high | undefined
9411 11:47:08.594093 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9412 11:47:08.597052 in-header: 03 f9 00 00 02 00 00 00
9413 11:47:08.600532 in-data: 02 00
9414 11:47:08.603821 ADC[4]: Raw value=901770 ID=7
9415 11:47:08.604242 ADC[3]: Raw value=212810 ID=1
9416 11:47:08.607191 RAM Code: 0x71
9417 11:47:08.610502 ADC[6]: Raw value=74502 ID=0
9418 11:47:08.610982 ADC[5]: Raw value=212441 ID=1
9419 11:47:08.613631 SKU Code: 0x1
9420 11:47:08.620533 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9421 11:47:08.621165 coreboot table: 964 bytes.
9422 11:47:08.623854 IMD ROOT 0. 0xfffff000 0x00001000
9423 11:47:08.627132 IMD SMALL 1. 0xffffe000 0x00001000
9424 11:47:08.630371 RO MCACHE 2. 0xffffc000 0x00001104
9425 11:47:08.633710 CONSOLE 3. 0xfff7c000 0x00080000
9426 11:47:08.636766 FMAP 4. 0xfff7b000 0x00000452
9427 11:47:08.640056 TIME STAMP 5. 0xfff7a000 0x00000910
9428 11:47:08.643302 VBOOT WORK 6. 0xfff66000 0x00014000
9429 11:47:08.647086 RAMOOPS 7. 0xffe66000 0x00100000
9430 11:47:08.650189 COREBOOT 8. 0xffe64000 0x00002000
9431 11:47:08.653626 IMD small region:
9432 11:47:08.656910 IMD ROOT 0. 0xffffec00 0x00000400
9433 11:47:08.660008 VPD 1. 0xffffeba0 0x0000004c
9434 11:47:08.663462 MMC STATUS 2. 0xffffeb80 0x00000004
9435 11:47:08.666690 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9436 11:47:08.670072 Probing TPM: done!
9437 11:47:08.673332 Connected to device vid:did:rid of 1ae0:0028:00
9438 11:47:08.684256 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9439 11:47:08.688238 Initialized TPM device CR50 revision 0
9440 11:47:08.691353 Checking cr50 for pending updates
9441 11:47:08.695383 Reading cr50 TPM mode
9442 11:47:08.703969 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9443 11:47:08.710332 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9444 11:47:08.750743 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9445 11:47:08.754036 Checking segment from ROM address 0x40100000
9446 11:47:08.757516 Checking segment from ROM address 0x4010001c
9447 11:47:08.764126 Loading segment from ROM address 0x40100000
9448 11:47:08.764696 code (compression=0)
9449 11:47:08.771141 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9450 11:47:08.780799 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9451 11:47:08.781423 it's not compressed!
9452 11:47:08.787395 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9453 11:47:08.790659 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9454 11:47:08.810773 Loading segment from ROM address 0x4010001c
9455 11:47:08.810870 Entry Point 0x80000000
9456 11:47:08.813992 Loaded segments
9457 11:47:08.817258 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9458 11:47:08.824020 Jumping to boot code at 0x80000000(0xffe64000)
9459 11:47:08.830750 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9460 11:47:08.837110 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9461 11:47:08.844905 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9462 11:47:08.848189 Checking segment from ROM address 0x40100000
9463 11:47:08.851896 Checking segment from ROM address 0x4010001c
9464 11:47:08.858254 Loading segment from ROM address 0x40100000
9465 11:47:08.858390 code (compression=1)
9466 11:47:08.864814 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9467 11:47:08.874627 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9468 11:47:08.874838 using LZMA
9469 11:47:08.883221 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9470 11:47:08.890448 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9471 11:47:08.893663 Loading segment from ROM address 0x4010001c
9472 11:47:08.894376 Entry Point 0x54601000
9473 11:47:08.896868 Loaded segments
9474 11:47:08.899960 NOTICE: MT8192 bl31_setup
9475 11:47:08.907237 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9476 11:47:08.910416 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9477 11:47:08.914026 WARNING: region 0:
9478 11:47:08.917341 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 11:47:08.917979 WARNING: region 1:
9480 11:47:08.923845 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9481 11:47:08.927037 WARNING: region 2:
9482 11:47:08.930594 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9483 11:47:08.933771 WARNING: region 3:
9484 11:47:08.936877 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 11:47:08.940669 WARNING: region 4:
9486 11:47:08.947255 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 11:47:08.947827 WARNING: region 5:
9488 11:47:08.950533 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 11:47:08.953814 WARNING: region 6:
9490 11:47:08.956911 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 11:47:08.960418 WARNING: region 7:
9492 11:47:08.963883 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 11:47:08.970328 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9494 11:47:08.973963 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9495 11:47:08.976805 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9496 11:47:08.983588 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9497 11:47:08.986873 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9498 11:47:08.990164 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9499 11:47:08.996968 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9500 11:47:09.000133 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9501 11:47:09.006656 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9502 11:47:09.010275 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9503 11:47:09.013234 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9504 11:47:09.020190 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9505 11:47:09.023449 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9506 11:47:09.029953 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9507 11:47:09.033322 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9508 11:47:09.036799 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9509 11:47:09.043649 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9510 11:47:09.046682 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9511 11:47:09.049867 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9512 11:47:09.056253 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9513 11:47:09.060099 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9514 11:47:09.066431 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9515 11:47:09.069994 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9516 11:47:09.073182 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9517 11:47:09.079923 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9518 11:47:09.082827 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9519 11:47:09.089769 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9520 11:47:09.093333 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9521 11:47:09.096646 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9522 11:47:09.103248 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9523 11:47:09.106173 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9524 11:47:09.113074 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9525 11:47:09.116122 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9526 11:47:09.119673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9527 11:47:09.123015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9528 11:47:09.129435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9529 11:47:09.132617 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9530 11:47:09.136173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9531 11:47:09.139391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9532 11:47:09.146126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9533 11:47:09.148891 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9534 11:47:09.152576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9535 11:47:09.155801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9536 11:47:09.162480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9537 11:47:09.165641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9538 11:47:09.168886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9539 11:47:09.175693 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9540 11:47:09.178758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9541 11:47:09.182466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9542 11:47:09.188839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9543 11:47:09.192379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9544 11:47:09.195473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9545 11:47:09.201984 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9546 11:47:09.205242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9547 11:47:09.211684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9548 11:47:09.215346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9549 11:47:09.221954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9550 11:47:09.225169 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9551 11:47:09.232030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9552 11:47:09.235277 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9553 11:47:09.238681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9554 11:47:09.245508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9555 11:47:09.248593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9556 11:47:09.255318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9557 11:47:09.258542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9558 11:47:09.265246 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9559 11:47:09.268560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9560 11:47:09.272112 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9561 11:47:09.278561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9562 11:47:09.281722 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9563 11:47:09.288511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9564 11:47:09.291568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9565 11:47:09.298287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9566 11:47:09.301403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9567 11:47:09.308117 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9568 11:47:09.311804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9569 11:47:09.315001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9570 11:47:09.321511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9571 11:47:09.325050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9572 11:47:09.331390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9573 11:47:09.334599 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9574 11:47:09.341520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9575 11:47:09.344780 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9576 11:47:09.351252 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9577 11:47:09.354680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9578 11:47:09.358025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9579 11:47:09.364532 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9580 11:47:09.367755 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9581 11:47:09.374600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9582 11:47:09.377717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9583 11:47:09.384557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9584 11:47:09.387641 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9585 11:47:09.394739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9586 11:47:09.397834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9587 11:47:09.400922 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9588 11:47:09.407443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9589 11:47:09.411113 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9590 11:47:09.414315 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9591 11:47:09.420919 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9592 11:47:09.424085 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9593 11:47:09.427740 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9594 11:47:09.434395 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9595 11:47:09.437703 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9596 11:47:09.440872 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9597 11:47:09.447767 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9598 11:47:09.451044 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9599 11:47:09.454371 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9600 11:47:09.461116 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9601 11:47:09.464530 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9602 11:47:09.470856 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9603 11:47:09.474131 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9604 11:47:09.480876 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9605 11:47:09.484008 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9606 11:47:09.487154 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9607 11:47:09.494293 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9608 11:47:09.497642 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9609 11:47:09.500612 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9610 11:47:09.507116 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9611 11:47:09.510752 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9612 11:47:09.514144 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9613 11:47:09.520594 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9614 11:47:09.523747 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9615 11:47:09.527461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9616 11:47:09.530249 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9617 11:47:09.536954 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9618 11:47:09.540394 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9619 11:47:09.543711 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9620 11:47:09.549942 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9621 11:47:09.553457 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9622 11:47:09.559846 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9623 11:47:09.563381 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9624 11:47:09.566580 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9625 11:47:09.573389 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9626 11:47:09.576607 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9627 11:47:09.583163 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9628 11:47:09.586527 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9629 11:47:09.590027 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9630 11:47:09.596536 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9631 11:47:09.599746 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9632 11:47:09.606616 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9633 11:47:09.609733 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9634 11:47:09.613230 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9635 11:47:09.620261 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9636 11:47:09.623607 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9637 11:47:09.629754 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9638 11:47:09.633232 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9639 11:47:09.636777 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9640 11:47:09.643202 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9641 11:47:09.646677 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9642 11:47:09.653192 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9643 11:47:09.656733 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9644 11:47:09.660337 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9645 11:47:09.666631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9646 11:47:09.669892 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9647 11:47:09.673144 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9648 11:47:09.679587 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9649 11:47:09.683386 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9650 11:47:09.689913 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9651 11:47:09.692837 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9652 11:47:09.696298 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9653 11:47:09.703068 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9654 11:47:09.705903 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9655 11:47:09.712727 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9656 11:47:09.716261 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9657 11:47:09.719497 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9658 11:47:09.726035 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9659 11:47:09.729249 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9660 11:47:09.735927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9661 11:47:09.739259 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9662 11:47:09.742229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9663 11:47:09.748938 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9664 11:47:09.752364 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9665 11:47:09.758864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9666 11:47:09.762254 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9667 11:47:09.765505 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9668 11:47:09.772036 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9669 11:47:09.775283 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9670 11:47:09.781954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9671 11:47:09.785161 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9672 11:47:09.788675 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9673 11:47:09.795256 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9674 11:47:09.798233 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9675 11:47:09.805035 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9676 11:47:09.808272 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9677 11:47:09.811845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9678 11:47:09.818079 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9679 11:47:09.821297 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9680 11:47:09.827704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9681 11:47:09.831284 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9682 11:47:09.834677 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9683 11:47:09.841258 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9684 11:47:09.844496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9685 11:47:09.850769 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9686 11:47:09.854019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9687 11:47:09.860819 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9688 11:47:09.863905 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9689 11:47:09.867480 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9690 11:47:09.873773 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9691 11:47:09.877169 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9692 11:47:09.883663 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9693 11:47:09.886892 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9694 11:47:09.893740 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9695 11:47:09.897067 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9696 11:47:09.900240 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9697 11:47:09.906690 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9698 11:47:09.910064 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9699 11:47:09.916854 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9700 11:47:09.920276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9701 11:47:09.926529 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9702 11:47:09.929768 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9703 11:47:09.933418 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9704 11:47:09.940001 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9705 11:47:09.943181 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9706 11:47:09.949683 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9707 11:47:09.953313 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9708 11:47:09.959716 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9709 11:47:09.963192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9710 11:47:09.966381 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9711 11:47:09.973026 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9712 11:47:09.976201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9713 11:47:09.982839 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9714 11:47:09.986015 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9715 11:47:09.992855 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9716 11:47:09.995965 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9717 11:47:09.999619 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9718 11:47:10.006077 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9719 11:47:10.009050 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9720 11:47:10.015616 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9721 11:47:10.019088 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9722 11:47:10.022564 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9723 11:47:10.028918 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9724 11:47:10.032512 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9725 11:47:10.035677 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9726 11:47:10.038827 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9727 11:47:10.045703 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9728 11:47:10.049082 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9729 11:47:10.052325 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9730 11:47:10.058787 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9731 11:47:10.062198 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9732 11:47:10.065601 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9733 11:47:10.071944 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9734 11:47:10.075572 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9735 11:47:10.081817 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9736 11:47:10.085362 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9737 11:47:10.088565 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9738 11:47:10.095378 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9739 11:47:10.098576 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9740 11:47:10.105149 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9741 11:47:10.108369 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9742 11:47:10.111444 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9743 11:47:10.118384 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9744 11:47:10.121751 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9745 11:47:10.124905 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9746 11:47:10.131746 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9747 11:47:10.134611 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9748 11:47:10.138201 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9749 11:47:10.144743 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9750 11:47:10.148004 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9751 11:47:10.151204 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9752 11:47:10.157717 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9753 11:47:10.161297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9754 11:47:10.167799 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9755 11:47:10.171058 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9756 11:47:10.174232 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9757 11:47:10.180752 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9758 11:47:10.184494 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9759 11:47:10.190995 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9760 11:47:10.194202 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9761 11:47:10.197536 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9762 11:47:10.200636 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9763 11:47:10.207745 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9764 11:47:10.210866 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9765 11:47:10.214143 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9766 11:47:10.217179 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9767 11:47:10.223807 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9768 11:47:10.227250 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9769 11:47:10.230661 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9770 11:47:10.233618 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9771 11:47:10.240422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9772 11:47:10.243562 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9773 11:47:10.247223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9774 11:47:10.250431 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9775 11:47:10.256849 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9776 11:47:10.260411 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9777 11:47:10.267110 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9778 11:47:10.269987 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9779 11:47:10.276828 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9780 11:47:10.280072 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9781 11:47:10.286492 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9782 11:47:10.289765 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9783 11:47:10.293261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9784 11:47:10.299890 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9785 11:47:10.302879 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9786 11:47:10.309719 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9787 11:47:10.313056 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9788 11:47:10.316186 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9789 11:47:10.322583 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9790 11:47:10.326192 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9791 11:47:10.332460 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9792 11:47:10.335785 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9793 11:47:10.342669 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9794 11:47:10.346076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9795 11:47:10.349198 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9796 11:47:10.355703 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9797 11:47:10.359399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9798 11:47:10.365866 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9799 11:47:10.369294 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9800 11:47:10.372628 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9801 11:47:10.378983 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9802 11:47:10.382278 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9803 11:47:10.388869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9804 11:47:10.392254 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9805 11:47:10.398844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9806 11:47:10.402244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9807 11:47:10.405500 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9808 11:47:10.411908 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9809 11:47:10.415493 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9810 11:47:10.422166 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9811 11:47:10.425252 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9812 11:47:10.432095 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9813 11:47:10.435252 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9814 11:47:10.438652 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9815 11:47:10.445375 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9816 11:47:10.448741 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9817 11:47:10.455158 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9818 11:47:10.458364 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9819 11:47:10.461637 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9820 11:47:10.468201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9821 11:47:10.471388 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9822 11:47:10.477858 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9823 11:47:10.481377 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9824 11:47:10.484646 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9825 11:47:10.491331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9826 11:47:10.494556 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9827 11:47:10.500961 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9828 11:47:10.504260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9829 11:47:10.510920 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9830 11:47:10.514298 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9831 11:47:10.517348 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9832 11:47:10.524122 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9833 11:47:10.527525 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9834 11:47:10.534030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9835 11:47:10.537326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9836 11:47:10.544375 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9837 11:47:10.547680 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9838 11:47:10.550585 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9839 11:47:10.557212 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9840 11:47:10.560856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9841 11:47:10.567158 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9842 11:47:10.570396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9843 11:47:10.574082 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9844 11:47:10.580594 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9845 11:47:10.583607 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9846 11:47:10.590230 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9847 11:47:10.593741 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9848 11:47:10.599989 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9849 11:47:10.603648 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9850 11:47:10.606651 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9851 11:47:10.613465 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9852 11:47:10.616698 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9853 11:47:10.623124 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9854 11:47:10.626626 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9855 11:47:10.632892 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9856 11:47:10.636663 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9857 11:47:10.643190 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9858 11:47:10.646256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9859 11:47:10.649400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9860 11:47:10.656151 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9861 11:47:10.659465 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9862 11:47:10.665977 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9863 11:47:10.669415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9864 11:47:10.675831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9865 11:47:10.679070 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9866 11:47:10.685865 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9867 11:47:10.688958 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9868 11:47:10.695826 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9869 11:47:10.698956 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9870 11:47:10.702529 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9871 11:47:10.708751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9872 11:47:10.712271 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9873 11:47:10.718980 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9874 11:47:10.721856 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9875 11:47:10.728417 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9876 11:47:10.731798 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9877 11:47:10.735294 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9878 11:47:10.741907 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9879 11:47:10.745269 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9880 11:47:10.751857 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9881 11:47:10.754988 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9882 11:47:10.761837 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9883 11:47:10.765010 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9884 11:47:10.771400 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9885 11:47:10.774856 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9886 11:47:10.778074 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9887 11:47:10.784809 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9888 11:47:10.788378 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9889 11:47:10.794848 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9890 11:47:10.798299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9891 11:47:10.804856 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9892 11:47:10.808026 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9893 11:47:10.814843 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9894 11:47:10.818153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9895 11:47:10.821339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9896 11:47:10.827728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9897 11:47:10.831429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9898 11:47:10.837780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9899 11:47:10.841145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9900 11:47:10.847670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9901 11:47:10.850787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9902 11:47:10.857787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9903 11:47:10.861020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9904 11:47:10.867488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9905 11:47:10.870791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9906 11:47:10.874165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9907 11:47:10.880678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9908 11:47:10.884122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9909 11:47:10.890391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9910 11:47:10.893853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9911 11:47:10.900008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9912 11:47:10.903199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9913 11:47:10.910259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9914 11:47:10.913519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9915 11:47:10.919801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9916 11:47:10.923099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9917 11:47:10.929733 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9918 11:47:10.932921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9919 11:47:10.939722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9920 11:47:10.943082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9921 11:47:10.949609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9922 11:47:10.952868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9923 11:47:10.959712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9924 11:47:10.966278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9925 11:47:10.969577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9926 11:47:10.976120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9927 11:47:10.979242 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9928 11:47:10.979321 INFO: [APUAPC] vio 0
9929 11:47:10.986691 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9930 11:47:10.989881 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9931 11:47:10.993580 INFO: [APUAPC] D0_APC_0: 0x400510
9932 11:47:10.996609 INFO: [APUAPC] D0_APC_1: 0x0
9933 11:47:10.999780 INFO: [APUAPC] D0_APC_2: 0x1540
9934 11:47:11.003132 INFO: [APUAPC] D0_APC_3: 0x0
9935 11:47:11.006384 INFO: [APUAPC] D1_APC_0: 0xffffffff
9936 11:47:11.009558 INFO: [APUAPC] D1_APC_1: 0xffffffff
9937 11:47:11.013246 INFO: [APUAPC] D1_APC_2: 0x3fffff
9938 11:47:11.016504 INFO: [APUAPC] D1_APC_3: 0x0
9939 11:47:11.019349 INFO: [APUAPC] D2_APC_0: 0xffffffff
9940 11:47:11.022937 INFO: [APUAPC] D2_APC_1: 0xffffffff
9941 11:47:11.026003 INFO: [APUAPC] D2_APC_2: 0x3fffff
9942 11:47:11.029350 INFO: [APUAPC] D2_APC_3: 0x0
9943 11:47:11.032676 INFO: [APUAPC] D3_APC_0: 0xffffffff
9944 11:47:11.036039 INFO: [APUAPC] D3_APC_1: 0xffffffff
9945 11:47:11.039363 INFO: [APUAPC] D3_APC_2: 0x3fffff
9946 11:47:11.042684 INFO: [APUAPC] D3_APC_3: 0x0
9947 11:47:11.045951 INFO: [APUAPC] D4_APC_0: 0xffffffff
9948 11:47:11.049181 INFO: [APUAPC] D4_APC_1: 0xffffffff
9949 11:47:11.052523 INFO: [APUAPC] D4_APC_2: 0x3fffff
9950 11:47:11.055882 INFO: [APUAPC] D4_APC_3: 0x0
9951 11:47:11.059127 INFO: [APUAPC] D5_APC_0: 0xffffffff
9952 11:47:11.062537 INFO: [APUAPC] D5_APC_1: 0xffffffff
9953 11:47:11.065820 INFO: [APUAPC] D5_APC_2: 0x3fffff
9954 11:47:11.068982 INFO: [APUAPC] D5_APC_3: 0x0
9955 11:47:11.072706 INFO: [APUAPC] D6_APC_0: 0xffffffff
9956 11:47:11.075840 INFO: [APUAPC] D6_APC_1: 0xffffffff
9957 11:47:11.078999 INFO: [APUAPC] D6_APC_2: 0x3fffff
9958 11:47:11.079097 INFO: [APUAPC] D6_APC_3: 0x0
9959 11:47:11.082534 INFO: [APUAPC] D7_APC_0: 0xffffffff
9960 11:47:11.088870 INFO: [APUAPC] D7_APC_1: 0xffffffff
9961 11:47:11.092468 INFO: [APUAPC] D7_APC_2: 0x3fffff
9962 11:47:11.092580 INFO: [APUAPC] D7_APC_3: 0x0
9963 11:47:11.095652 INFO: [APUAPC] D8_APC_0: 0xffffffff
9964 11:47:11.098802 INFO: [APUAPC] D8_APC_1: 0xffffffff
9965 11:47:11.102041 INFO: [APUAPC] D8_APC_2: 0x3fffff
9966 11:47:11.105864 INFO: [APUAPC] D8_APC_3: 0x0
9967 11:47:11.109063 INFO: [APUAPC] D9_APC_0: 0xffffffff
9968 11:47:11.112340 INFO: [APUAPC] D9_APC_1: 0xffffffff
9969 11:47:11.115597 INFO: [APUAPC] D9_APC_2: 0x3fffff
9970 11:47:11.118599 INFO: [APUAPC] D9_APC_3: 0x0
9971 11:47:11.121944 INFO: [APUAPC] D10_APC_0: 0xffffffff
9972 11:47:11.125098 INFO: [APUAPC] D10_APC_1: 0xffffffff
9973 11:47:11.128732 INFO: [APUAPC] D10_APC_2: 0x3fffff
9974 11:47:11.131844 INFO: [APUAPC] D10_APC_3: 0x0
9975 11:47:11.135216 INFO: [APUAPC] D11_APC_0: 0xffffffff
9976 11:47:11.138597 INFO: [APUAPC] D11_APC_1: 0xffffffff
9977 11:47:11.141774 INFO: [APUAPC] D11_APC_2: 0x3fffff
9978 11:47:11.145013 INFO: [APUAPC] D11_APC_3: 0x0
9979 11:47:11.148346 INFO: [APUAPC] D12_APC_0: 0xffffffff
9980 11:47:11.152058 INFO: [APUAPC] D12_APC_1: 0xffffffff
9981 11:47:11.155256 INFO: [APUAPC] D12_APC_2: 0x3fffff
9982 11:47:11.158496 INFO: [APUAPC] D12_APC_3: 0x0
9983 11:47:11.161733 INFO: [APUAPC] D13_APC_0: 0xffffffff
9984 11:47:11.168479 INFO: [APUAPC] D13_APC_1: 0xffffffff
9985 11:47:11.171819 INFO: [APUAPC] D13_APC_2: 0x3fffff
9986 11:47:11.171936 INFO: [APUAPC] D13_APC_3: 0x0
9987 11:47:11.175281 INFO: [APUAPC] D14_APC_0: 0xffffffff
9988 11:47:11.181670 INFO: [APUAPC] D14_APC_1: 0xffffffff
9989 11:47:11.185136 INFO: [APUAPC] D14_APC_2: 0x3fffff
9990 11:47:11.185248 INFO: [APUAPC] D14_APC_3: 0x0
9991 11:47:11.192050 INFO: [APUAPC] D15_APC_0: 0xffffffff
9992 11:47:11.194977 INFO: [APUAPC] D15_APC_1: 0xffffffff
9993 11:47:11.198336 INFO: [APUAPC] D15_APC_2: 0x3fffff
9994 11:47:11.201635 INFO: [APUAPC] D15_APC_3: 0x0
9995 11:47:11.201811 INFO: [APUAPC] APC_CON: 0x4
9996 11:47:11.205157 INFO: [NOCDAPC] D0_APC_0: 0x0
9997 11:47:11.208398 INFO: [NOCDAPC] D0_APC_1: 0x0
9998 11:47:11.211656 INFO: [NOCDAPC] D1_APC_0: 0x0
9999 11:47:11.214856 INFO: [NOCDAPC] D1_APC_1: 0xfff
10000 11:47:11.218067 INFO: [NOCDAPC] D2_APC_0: 0x0
10001 11:47:11.221630 INFO: [NOCDAPC] D2_APC_1: 0xfff
10002 11:47:11.225256 INFO: [NOCDAPC] D3_APC_0: 0x0
10003 11:47:11.228359 INFO: [NOCDAPC] D3_APC_1: 0xfff
10004 11:47:11.229036 INFO: [NOCDAPC] D4_APC_0: 0x0
10005 11:47:11.231840 INFO: [NOCDAPC] D4_APC_1: 0xfff
10006 11:47:11.234866 INFO: [NOCDAPC] D5_APC_0: 0x0
10007 11:47:11.238524 INFO: [NOCDAPC] D5_APC_1: 0xfff
10008 11:47:11.241533 INFO: [NOCDAPC] D6_APC_0: 0x0
10009 11:47:11.244880 INFO: [NOCDAPC] D6_APC_1: 0xfff
10010 11:47:11.248116 INFO: [NOCDAPC] D7_APC_0: 0x0
10011 11:47:11.251454 INFO: [NOCDAPC] D7_APC_1: 0xfff
10012 11:47:11.254692 INFO: [NOCDAPC] D8_APC_0: 0x0
10013 11:47:11.258088 INFO: [NOCDAPC] D8_APC_1: 0xfff
10014 11:47:11.261306 INFO: [NOCDAPC] D9_APC_0: 0x0
10015 11:47:11.264609 INFO: [NOCDAPC] D9_APC_1: 0xfff
10016 11:47:11.265422 INFO: [NOCDAPC] D10_APC_0: 0x0
10017 11:47:11.267810 INFO: [NOCDAPC] D10_APC_1: 0xfff
10018 11:47:11.270965 INFO: [NOCDAPC] D11_APC_0: 0x0
10019 11:47:11.274282 INFO: [NOCDAPC] D11_APC_1: 0xfff
10020 11:47:11.277848 INFO: [NOCDAPC] D12_APC_0: 0x0
10021 11:47:11.281130 INFO: [NOCDAPC] D12_APC_1: 0xfff
10022 11:47:11.284236 INFO: [NOCDAPC] D13_APC_0: 0x0
10023 11:47:11.287664 INFO: [NOCDAPC] D13_APC_1: 0xfff
10024 11:47:11.290779 INFO: [NOCDAPC] D14_APC_0: 0x0
10025 11:47:11.294169 INFO: [NOCDAPC] D14_APC_1: 0xfff
10026 11:47:11.297480 INFO: [NOCDAPC] D15_APC_0: 0x0
10027 11:47:11.300712 INFO: [NOCDAPC] D15_APC_1: 0xfff
10028 11:47:11.304111 INFO: [NOCDAPC] APC_CON: 0x4
10029 11:47:11.307331 INFO: [APUAPC] set_apusys_apc done
10030 11:47:11.310411 INFO: [DEVAPC] devapc_init done
10031 11:47:11.313706 INFO: GICv3 without legacy support detected.
10032 11:47:11.316849 INFO: ARM GICv3 driver initialized in EL3
10033 11:47:11.320618 INFO: Maximum SPI INTID supported: 639
10034 11:47:11.323588 INFO: BL31: Initializing runtime services
10035 11:47:11.330269 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10036 11:47:11.333639 INFO: SPM: enable CPC mode
10037 11:47:11.340156 INFO: mcdi ready for mcusys-off-idle and system suspend
10038 11:47:11.343297 INFO: BL31: Preparing for EL3 exit to normal world
10039 11:47:11.346484 INFO: Entry point address = 0x80000000
10040 11:47:11.349658 INFO: SPSR = 0x8
10041 11:47:11.354849
10042 11:47:11.355017
10043 11:47:11.355175
10044 11:47:11.358335 Starting depthcharge on Spherion...
10045 11:47:11.358550
10046 11:47:11.358707 Wipe memory regions:
10047 11:47:11.358864
10048 11:47:11.360111 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10049 11:47:11.360363 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10050 11:47:11.360614 Setting prompt string to ['asurada:']
10051 11:47:11.360817 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10052 11:47:11.361482 [0x00000040000000, 0x00000054600000)
10053 11:47:11.484175
10054 11:47:11.484798 [0x00000054660000, 0x00000080000000)
10055 11:47:11.744733
10056 11:47:11.745443 [0x000000821a7280, 0x000000ffe64000)
10057 11:47:12.489556
10058 11:47:12.490123 [0x00000100000000, 0x00000240000000)
10059 11:47:14.379780
10060 11:47:14.382922 Initializing XHCI USB controller at 0x11200000.
10061 11:47:15.420895
10062 11:47:15.424069 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10063 11:47:15.424503
10064 11:47:15.424835
10065 11:47:15.425254
10066 11:47:15.426159 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 11:47:15.527539 asurada: tftpboot 192.168.201.1 10742265/tftp-deploy-boyaql5d/kernel/image.itb 10742265/tftp-deploy-boyaql5d/kernel/cmdline
10069 11:47:15.528105 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 11:47:15.528494 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10071 11:47:15.532855 tftpboot 192.168.201.1 10742265/tftp-deploy-boyaql5d/kernel/image.itp-deploy-boyaql5d/kernel/cmdline
10072 11:47:15.533493
10073 11:47:15.533847 Waiting for link
10074 11:47:15.693039
10075 11:47:15.693551 R8152: Initializing
10076 11:47:15.693900
10077 11:47:15.696147 Version 9 (ocp_data = 6010)
10078 11:47:15.696609
10079 11:47:15.699627 R8152: Done initializing
10080 11:47:15.700241
10081 11:47:15.700674 Adding net device
10082 11:47:17.568915
10083 11:47:17.569521 done.
10084 11:47:17.569899
10085 11:47:17.570250 MAC: 00:e0:4c:72:2d:d6
10086 11:47:17.570588
10087 11:47:17.572159 Sending DHCP discover... done.
10088 11:47:17.572631
10089 11:47:28.018419 Waiting for reply... R8152: Bulk read error 0xffffffbf
10090 11:47:28.018953
10091 11:47:28.021637 Receive failed.
10092 11:47:28.022057
10093 11:47:28.022389 done.
10094 11:47:28.022700
10095 11:47:28.024779 Sending DHCP request... done.
10096 11:47:28.025227
10097 11:47:28.032601 Waiting for reply... done.
10098 11:47:28.033086
10099 11:47:28.033455 My ip is 192.168.201.21
10100 11:47:28.033793
10101 11:47:28.035851 The DHCP server ip is 192.168.201.1
10102 11:47:28.036317
10103 11:47:28.042338 TFTP server IP predefined by user: 192.168.201.1
10104 11:47:28.042777
10105 11:47:28.048570 Bootfile predefined by user: 10742265/tftp-deploy-boyaql5d/kernel/image.itb
10106 11:47:28.049158
10107 11:47:28.052090 Sending tftp read request... done.
10108 11:47:28.052560
10109 11:47:28.056828 Waiting for the transfer...
10110 11:47:28.057311
10111 11:47:28.410499 00000000 ################################################################
10112 11:47:28.410652
10113 11:47:28.698460 00080000 ################################################################
10114 11:47:28.698663
10115 11:47:28.974513 00100000 ################################################################
10116 11:47:28.974698
10117 11:47:29.245766 00180000 ################################################################
10118 11:47:29.245946
10119 11:47:29.510453 00200000 ################################################################
10120 11:47:29.510634
10121 11:47:29.795894 00280000 ################################################################
10122 11:47:29.796040
10123 11:47:30.071781 00300000 ################################################################
10124 11:47:30.071924
10125 11:47:30.352113 00380000 ################################################################
10126 11:47:30.352285
10127 11:47:30.606543 00400000 ################################################################
10128 11:47:30.606694
10129 11:47:30.871405 00480000 ################################################################
10130 11:47:30.871561
10131 11:47:31.121979 00500000 ################################################################
10132 11:47:31.122116
10133 11:47:31.375726 00580000 ################################################################
10134 11:47:31.375871
10135 11:47:31.627794 00600000 ################################################################
10136 11:47:31.627936
10137 11:47:31.878609 00680000 ################################################################
10138 11:47:31.878789
10139 11:47:32.129391 00700000 ################################################################
10140 11:47:32.129559
10141 11:47:32.379507 00780000 ################################################################
10142 11:47:32.379679
10143 11:47:32.629275 00800000 ################################################################
10144 11:47:32.629433
10145 11:47:32.875138 00880000 ################################################################
10146 11:47:32.875319
10147 11:47:33.130229 00900000 ################################################################
10148 11:47:33.130370
10149 11:47:33.376821 00980000 ################################################################
10150 11:47:33.377006
10151 11:47:33.624425 00a00000 ################################################################
10152 11:47:33.624573
10153 11:47:33.870215 00a80000 ################################################################
10154 11:47:33.870368
10155 11:47:34.115774 00b00000 ################################################################
10156 11:47:34.115928
10157 11:47:34.360587 00b80000 ################################################################
10158 11:47:34.360747
10159 11:47:34.612393 00c00000 ################################################################
10160 11:47:34.612560
10161 11:47:34.858581 00c80000 ################################################################
10162 11:47:34.858735
10163 11:47:35.103927 00d00000 ################################################################
10164 11:47:35.104084
10165 11:47:35.353879 00d80000 ################################################################
10166 11:47:35.354020
10167 11:47:35.605067 00e00000 ################################################################
10168 11:47:35.605243
10169 11:47:35.852993 00e80000 ################################################################
10170 11:47:35.853170
10171 11:47:36.100423 00f00000 ################################################################
10172 11:47:36.100602
10173 11:47:36.344536 00f80000 ################################################################
10174 11:47:36.344719
10175 11:47:36.591614 01000000 ################################################################
10176 11:47:36.591774
10177 11:47:36.860854 01080000 ################################################################
10178 11:47:36.861046
10179 11:47:37.121387 01100000 ################################################################
10180 11:47:37.121524
10181 11:47:37.375907 01180000 ################################################################
10182 11:47:37.376042
10183 11:47:37.625812 01200000 ################################################################
10184 11:47:37.625957
10185 11:47:37.875284 01280000 ################################################################
10186 11:47:37.875427
10187 11:47:38.144813 01300000 ################################################################
10188 11:47:38.144950
10189 11:47:38.392459 01380000 ################################################################
10190 11:47:38.392648
10191 11:47:38.639669 01400000 ################################################################
10192 11:47:38.639863
10193 11:47:38.887532 01480000 ################################################################
10194 11:47:38.887680
10195 11:47:39.138537 01500000 ################################################################
10196 11:47:39.138669
10197 11:47:39.388459 01580000 ################################################################
10198 11:47:39.388600
10199 11:47:39.637672 01600000 ################################################################
10200 11:47:39.637818
10201 11:47:39.899406 01680000 ################################################################
10202 11:47:39.899555
10203 11:47:40.149493 01700000 ################################################################
10204 11:47:40.149656
10205 11:47:40.398867 01780000 ################################################################
10206 11:47:40.399020
10207 11:47:40.648274 01800000 ################################################################
10208 11:47:40.648417
10209 11:47:40.898611 01880000 ################################################################
10210 11:47:40.898757
10211 11:47:41.149191 01900000 ################################################################
10212 11:47:41.149329
10213 11:47:41.398824 01980000 ################################################################
10214 11:47:41.398985
10215 11:47:41.660881 01a00000 ################################################################
10216 11:47:41.661057
10217 11:47:41.911956 01a80000 ################################################################
10218 11:47:41.912111
10219 11:47:42.162757 01b00000 ################################################################
10220 11:47:42.162901
10221 11:47:42.412908 01b80000 ################################################################
10222 11:47:42.413098
10223 11:47:42.660716 01c00000 ################################################################
10224 11:47:42.660860
10225 11:47:42.910950 01c80000 ################################################################
10226 11:47:42.911103
10227 11:47:43.164678 01d00000 ################################################################
10228 11:47:43.164816
10229 11:47:43.414462 01d80000 ################################################################
10230 11:47:43.414615
10231 11:47:43.664726 01e00000 ################################################################
10232 11:47:43.664881
10233 11:47:43.923512 01e80000 ################################################################
10234 11:47:43.923655
10235 11:47:44.172789 01f00000 ################################################################
10236 11:47:44.172925
10237 11:47:44.423947 01f80000 ################################################################
10238 11:47:44.424080
10239 11:47:44.673147 02000000 ################################################################
10240 11:47:44.673306
10241 11:47:44.924506 02080000 ################################################################
10242 11:47:44.924657
10243 11:47:45.177047 02100000 ################################################################
10244 11:47:45.177197
10245 11:47:45.426613 02180000 ################################################################
10246 11:47:45.426780
10247 11:47:45.698608 02200000 ################################################################
10248 11:47:45.698744
10249 11:47:45.948716 02280000 ################################################################
10250 11:47:45.948891
10251 11:47:46.223221 02300000 ################################################################
10252 11:47:46.223416
10253 11:47:46.546532 02380000 ################################################################
10254 11:47:46.546713
10255 11:47:46.891346 02400000 ################################################################
10256 11:47:46.891537
10257 11:47:47.213494 02480000 ################################################################
10258 11:47:47.213653
10259 11:47:47.485963 02500000 ################################################################
10260 11:47:47.486118
10261 11:47:47.735141 02580000 ################################################################
10262 11:47:47.735295
10263 11:47:47.979097 02600000 ################################################################
10264 11:47:47.979281
10265 11:47:48.226622 02680000 ################################################################
10266 11:47:48.226795
10267 11:47:48.482351 02700000 ################################################################
10268 11:47:48.482506
10269 11:47:48.734815 02780000 ################################################################
10270 11:47:48.734969
10271 11:47:48.986519 02800000 ################################################################
10272 11:47:48.986672
10273 11:47:49.235966 02880000 ################################################################
10274 11:47:49.236126
10275 11:47:49.486960 02900000 ################################################################
10276 11:47:49.487113
10277 11:47:49.741577 02980000 ################################################################
10278 11:47:49.741753
10279 11:47:49.991616 02a00000 ################################################################
10280 11:47:49.991796
10281 11:47:50.241250 02a80000 ################################################################
10282 11:47:50.241427
10283 11:47:50.492195 02b00000 ################################################################
10284 11:47:50.492337
10285 11:47:50.742137 02b80000 ################################################################
10286 11:47:50.742328
10287 11:47:50.993159 02c00000 ################################################################
10288 11:47:50.993301
10289 11:47:51.243699 02c80000 ################################################################
10290 11:47:51.243848
10291 11:47:51.498716 02d00000 ################################################################
10292 11:47:51.498856
10293 11:47:51.751304 02d80000 ################################################################
10294 11:47:51.751444
10295 11:47:52.004192 02e00000 ################################################################
10296 11:47:52.004344
10297 11:47:52.248798 02e80000 ################################################################
10298 11:47:52.248970
10299 11:47:52.487758 02f00000 ################################################################
10300 11:47:52.487905
10301 11:47:52.730570 02f80000 ################################################################
10302 11:47:52.730729
10303 11:47:52.969624 03000000 ################################################################
10304 11:47:52.969776
10305 11:47:53.216790 03080000 ################################################################
10306 11:47:53.216971
10307 11:47:53.462495 03100000 ################################################################
10308 11:47:53.462662
10309 11:47:53.707544 03180000 ################################################################
10310 11:47:53.707702
10311 11:47:53.954067 03200000 ################################################################
10312 11:47:53.954255
10313 11:47:54.201682 03280000 ################################################################
10314 11:47:54.201833
10315 11:47:54.462583 03300000 ################################################################
10316 11:47:54.462736
10317 11:47:54.713374 03380000 ################################################################
10318 11:47:54.713537
10319 11:47:54.964307 03400000 ################################################################
10320 11:47:54.964456
10321 11:47:55.217410 03480000 ################################################################
10322 11:47:55.217558
10323 11:47:55.468241 03500000 ################################################################
10324 11:47:55.468416
10325 11:47:55.717398 03580000 ################################################################
10326 11:47:55.717588
10327 11:47:55.972533 03600000 ################################################################
10328 11:47:55.972679
10329 11:47:56.251247 03680000 ################################################################
10330 11:47:56.251400
10331 11:47:56.517700 03700000 ################################################################
10332 11:47:56.517877
10333 11:47:56.766731 03780000 ################################################################
10334 11:47:56.766907
10335 11:47:57.014438 03800000 ################################################################
10336 11:47:57.014593
10337 11:47:57.281690 03880000 ################################################################
10338 11:47:57.281844
10339 11:47:57.548323 03900000 ################################################################
10340 11:47:57.548472
10341 11:47:57.835595 03980000 ################################################################
10342 11:47:57.835755
10343 11:47:58.103894 03a00000 ################################################################
10344 11:47:58.104063
10345 11:47:58.363429 03a80000 ################################################################
10346 11:47:58.363589
10347 11:47:58.617671 03b00000 ################################################################
10348 11:47:58.617827
10349 11:47:58.892714 03b80000 ################################################################
10350 11:47:58.892886
10351 11:47:59.146025 03c00000 ################################################################
10352 11:47:59.146175
10353 11:47:59.397509 03c80000 ################################################################
10354 11:47:59.397658
10355 11:47:59.673547 03d00000 ################################################################
10356 11:47:59.673692
10357 11:47:59.930603 03d80000 ################################################################
10358 11:47:59.930763
10359 11:48:00.177152 03e00000 ################################################################
10360 11:48:00.177390
10361 11:48:00.428136 03e80000 ################################################################
10362 11:48:00.428320
10363 11:48:00.696558 03f00000 ################################################################
10364 11:48:00.696740
10365 11:48:00.979477 03f80000 ################################################################
10366 11:48:00.979646
10367 11:48:01.271736 04000000 ################################################################
10368 11:48:01.271886
10369 11:48:01.529462 04080000 ################################################################
10370 11:48:01.529610
10371 11:48:01.794039 04100000 ################################################################
10372 11:48:01.794202
10373 11:48:02.053889 04180000 ################################################################
10374 11:48:02.054035
10375 11:48:02.316312 04200000 ################################################################
10376 11:48:02.316459
10377 11:48:02.567238 04280000 ################################################################
10378 11:48:02.567377
10379 11:48:02.816585 04300000 ################################################################
10380 11:48:02.816751
10381 11:48:03.065829 04380000 ################################################################
10382 11:48:03.065992
10383 11:48:03.315166 04400000 ################################################################
10384 11:48:03.315343
10385 11:48:03.578910 04480000 ################################################################
10386 11:48:03.579046
10387 11:48:03.829686 04500000 ################################################################
10388 11:48:03.829824
10389 11:48:04.080370 04580000 ################################################################
10390 11:48:04.080540
10391 11:48:04.338180 04600000 ################################################################
10392 11:48:04.338329
10393 11:48:04.591931 04680000 ################################################################
10394 11:48:04.592104
10395 11:48:04.841952 04700000 ################################################################
10396 11:48:04.842119
10397 11:48:05.091764 04780000 ################################################################
10398 11:48:05.091909
10399 11:48:05.340007 04800000 ################################################################
10400 11:48:05.340154
10401 11:48:05.592970 04880000 ################################################################
10402 11:48:05.593158
10403 11:48:05.849663 04900000 ################################################################
10404 11:48:05.849808
10405 11:48:06.128711 04980000 ################################################################
10406 11:48:06.128866
10407 11:48:06.395503 04a00000 ################################################################
10408 11:48:06.395658
10409 11:48:06.646883 04a80000 ################################################################
10410 11:48:06.647033
10411 11:48:06.894925 04b00000 ################################################################
10412 11:48:06.895083
10413 11:48:07.138958 04b80000 ################################################################
10414 11:48:07.139112
10415 11:48:07.397476 04c00000 ################################################################
10416 11:48:07.397628
10417 11:48:07.670132 04c80000 ################################################################
10418 11:48:07.670285
10419 11:48:07.924928 04d00000 ################################################################
10420 11:48:07.925103
10421 11:48:08.176226 04d80000 ################################################################
10422 11:48:08.176402
10423 11:48:08.434103 04e00000 ################################################################
10424 11:48:08.434256
10425 11:48:08.688510 04e80000 ################################################################
10426 11:48:08.688651
10427 11:48:08.949464 04f00000 ################################################################
10428 11:48:08.949610
10429 11:48:09.207732 04f80000 ################################################################
10430 11:48:09.207870
10431 11:48:09.463939 05000000 ################################################################
10432 11:48:09.464085
10433 11:48:09.719167 05080000 ################################################################
10434 11:48:09.719355
10435 11:48:09.980181 05100000 ################################################################
10436 11:48:09.980323
10437 11:48:10.242254 05180000 ################################################################
10438 11:48:10.242446
10439 11:48:10.498982 05200000 ################################################################
10440 11:48:10.499172
10441 11:48:10.753101 05280000 ################################################################
10442 11:48:10.753242
10443 11:48:11.011828 05300000 ################################################################
10444 11:48:11.012015
10445 11:48:11.270268 05380000 ################################################################
10446 11:48:11.270431
10447 11:48:11.526135 05400000 ################################################################
10448 11:48:11.526295
10449 11:48:11.780193 05480000 ################################################################
10450 11:48:11.780356
10451 11:48:12.026858 05500000 ################################################################
10452 11:48:12.027071
10453 11:48:12.276596 05580000 ################################################################
10454 11:48:12.276803
10455 11:48:12.527967 05600000 ################################################################
10456 11:48:12.528124
10457 11:48:12.778754 05680000 ################################################################
10458 11:48:12.778934
10459 11:48:13.029759 05700000 ################################################################
10460 11:48:13.029924
10461 11:48:13.280377 05780000 ################################################################
10462 11:48:13.280560
10463 11:48:13.530065 05800000 ################################################################
10464 11:48:13.530261
10465 11:48:13.785470 05880000 ################################################################
10466 11:48:13.785626
10467 11:48:14.043957 05900000 ################################################################
10468 11:48:14.044130
10469 11:48:14.292525 05980000 ################################################################
10470 11:48:14.292727
10471 11:48:14.536879 05a00000 ################################################################
10472 11:48:14.537065
10473 11:48:14.786287 05a80000 ################################################################
10474 11:48:14.786444
10475 11:48:15.039102 05b00000 ################################################################
10476 11:48:15.039257
10477 11:48:15.288760 05b80000 ################################################################
10478 11:48:15.288935
10479 11:48:15.538531 05c00000 ################################################################
10480 11:48:15.538688
10481 11:48:15.801490 05c80000 ################################################################
10482 11:48:15.801650
10483 11:48:16.054097 05d00000 ################################################################
10484 11:48:16.054249
10485 11:48:16.303646 05d80000 ################################################################
10486 11:48:16.303810
10487 11:48:16.556255 05e00000 ################################################################
10488 11:48:16.556438
10489 11:48:16.806147 05e80000 ################################################################
10490 11:48:16.806333
10491 11:48:17.055641 05f00000 ################################################################
10492 11:48:17.055875
10493 11:48:17.306465 05f80000 ################################################################
10494 11:48:17.306645
10495 11:48:17.571638 06000000 ################################################################
10496 11:48:17.571837
10497 11:48:17.824743 06080000 ################################################################
10498 11:48:17.824897
10499 11:48:18.074021 06100000 ################################################################
10500 11:48:18.074182
10501 11:48:18.330988 06180000 ################################################################
10502 11:48:18.331144
10503 11:48:18.580562 06200000 ################################################################
10504 11:48:18.580718
10505 11:48:18.830476 06280000 ################################################################
10506 11:48:18.830631
10507 11:48:19.079375 06300000 ################################################################
10508 11:48:19.079582
10509 11:48:19.326419 06380000 ################################################################
10510 11:48:19.326592
10511 11:48:19.571899 06400000 ################################################################
10512 11:48:19.572089
10513 11:48:19.818390 06480000 ################################################################
10514 11:48:19.818549
10515 11:48:20.068585 06500000 ################################################################
10516 11:48:20.068738
10517 11:48:20.321009 06580000 ################################################################
10518 11:48:20.321180
10519 11:48:20.582411 06600000 ################################################################
10520 11:48:20.582566
10521 11:48:20.834169 06680000 ################################################################
10522 11:48:20.834338
10523 11:48:21.104605 06700000 ################################################################
10524 11:48:21.104754
10525 11:48:21.164043 06780000 ############### done.
10526 11:48:21.164194
10527 11:48:21.167497 The bootfile was 108650458 bytes long.
10528 11:48:21.167593
10529 11:48:21.170714 Sending tftp read request... done.
10530 11:48:21.170798
10531 11:48:21.170863 Waiting for the transfer...
10532 11:48:21.170925
10533 11:48:21.174271 00000000 # done.
10534 11:48:21.174367
10535 11:48:21.180866 Command line loaded dynamically from TFTP file: 10742265/tftp-deploy-boyaql5d/kernel/cmdline
10536 11:48:21.180961
10537 11:48:21.194140 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10538 11:48:21.194228
10539 11:48:21.194293 Loading FIT.
10540 11:48:21.194353
10541 11:48:21.197332 Image ramdisk-1 has 98158137 bytes.
10542 11:48:21.197415
10543 11:48:21.200585 Image fdt-1 has 46924 bytes.
10544 11:48:21.200667
10545 11:48:21.204088 Image kernel-1 has 10443363 bytes.
10546 11:48:21.204171
10547 11:48:21.210604 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10548 11:48:21.213660
10549 11:48:21.230560 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10550 11:48:21.230652
10551 11:48:21.233655 Choosing best match conf-1 for compat google,spherion-rev2.
10552 11:48:21.238990
10553 11:48:21.243369 Connected to device vid:did:rid of 1ae0:0028:00
10554 11:48:21.250702
10555 11:48:21.254100 tpm_get_response: command 0x17b, return code 0x0
10556 11:48:21.254186
10557 11:48:21.257434 ec_init: CrosEC protocol v3 supported (256, 248)
10558 11:48:21.261064
10559 11:48:21.264604 tpm_cleanup: add release locality here.
10560 11:48:21.264691
10561 11:48:21.264758 Shutting down all USB controllers.
10562 11:48:21.267764
10563 11:48:21.267848 Removing current net device
10564 11:48:21.267914
10565 11:48:21.274313 Exiting depthcharge with code 4 at timestamp: 99265236
10566 11:48:21.274399
10567 11:48:21.277943 LZMA decompressing kernel-1 to 0x821a6718
10568 11:48:21.278028
10569 11:48:21.281319 LZMA decompressing kernel-1 to 0x40000000
10570 11:48:22.592145
10571 11:48:22.592297 jumping to kernel
10572 11:48:22.592768 end: 2.2.4 bootloader-commands (duration 00:01:11) [common]
10573 11:48:22.592870 start: 2.2.5 auto-login-action (timeout 00:03:14) [common]
10574 11:48:22.592946 Setting prompt string to ['Linux version [0-9]']
10575 11:48:22.593053 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10576 11:48:22.593122 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10577 11:48:22.673682
10578 11:48:22.676925 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10579 11:48:22.680362 start: 2.2.5.1 login-action (timeout 00:03:14) [common]
10580 11:48:22.680456 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10581 11:48:22.680542 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10582 11:48:22.680619 Using line separator: #'\n'#
10583 11:48:22.680680 No login prompt set.
10584 11:48:22.680781 Parsing kernel messages
10585 11:48:22.680836 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10586 11:48:22.680956 [login-action] Waiting for messages, (timeout 00:03:14)
10587 11:48:22.699996 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10588 11:48:22.703581 [ 0.000000] random: crng init done
10589 11:48:22.710227 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10590 11:48:22.710311 [ 0.000000] efi: UEFI not found.
10591 11:48:22.720108 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10592 11:48:22.726727 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10593 11:48:22.736588 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10594 11:48:22.746290 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10595 11:48:22.752869 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10596 11:48:22.759439 [ 0.000000] printk: bootconsole [mtk8250] enabled
10597 11:48:22.766246 [ 0.000000] NUMA: No NUMA configuration found
10598 11:48:22.772688 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10599 11:48:22.775771 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10600 11:48:22.779519 [ 0.000000] Zone ranges:
10601 11:48:22.786092 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10602 11:48:22.789172 [ 0.000000] DMA32 empty
10603 11:48:22.795669 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10604 11:48:22.799151 [ 0.000000] Movable zone start for each node
10605 11:48:22.802275 [ 0.000000] Early memory node ranges
10606 11:48:22.809148 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10607 11:48:22.815353 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10608 11:48:22.822227 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10609 11:48:22.828889 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10610 11:48:22.835618 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10611 11:48:22.842143 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10612 11:48:22.897959 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10613 11:48:22.904457 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10614 11:48:22.911167 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10615 11:48:22.914170 [ 0.000000] psci: probing for conduit method from DT.
10616 11:48:22.921117 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10617 11:48:22.924280 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10618 11:48:22.930849 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10619 11:48:22.933956 [ 0.000000] psci: SMC Calling Convention v1.2
10620 11:48:22.940826 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10621 11:48:22.943883 [ 0.000000] Detected VIPT I-cache on CPU0
10622 11:48:22.950356 [ 0.000000] CPU features: detected: GIC system register CPU interface
10623 11:48:22.957065 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10624 11:48:22.963520 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10625 11:48:22.970204 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10626 11:48:22.980105 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10627 11:48:22.986545 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10628 11:48:22.989984 [ 0.000000] alternatives: applying boot alternatives
10629 11:48:22.996770 [ 0.000000] Fallback order for Node 0: 0
10630 11:48:23.003478 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10631 11:48:23.006870 [ 0.000000] Policy zone: Normal
10632 11:48:23.016521 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10633 11:48:23.030034 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10634 11:48:23.039718 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10635 11:48:23.049778 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10636 11:48:23.056237 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10637 11:48:23.059737 <6>[ 0.000000] software IO TLB: area num 8.
10638 11:48:23.116588 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10639 11:48:23.265744 <6>[ 0.000000] Memory: 7875296K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 477472K reserved, 32768K cma-reserved)
10640 11:48:23.271989 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10641 11:48:23.278780 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10642 11:48:23.282327 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10643 11:48:23.288793 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10644 11:48:23.295199 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10645 11:48:23.298625 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10646 11:48:23.308595 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10647 11:48:23.314849 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10648 11:48:23.321464 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10649 11:48:23.328385 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10650 11:48:23.331517 <6>[ 0.000000] GICv3: 608 SPIs implemented
10651 11:48:23.334939 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10652 11:48:23.341739 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10653 11:48:23.344806 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10654 11:48:23.351586 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10655 11:48:23.364449 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10656 11:48:23.377717 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10657 11:48:23.384369 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10658 11:48:23.392294 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10659 11:48:23.405409 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10660 11:48:23.412067 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10661 11:48:23.418606 <6>[ 0.009225] Console: colour dummy device 80x25
10662 11:48:23.428398 <6>[ 0.013951] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10663 11:48:23.435226 <6>[ 0.024395] pid_max: default: 32768 minimum: 301
10664 11:48:23.438304 <6>[ 0.029297] LSM: Security Framework initializing
10665 11:48:23.444882 <6>[ 0.034237] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10666 11:48:23.455179 <6>[ 0.042099] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10667 11:48:23.465077 <6>[ 0.051380] cblist_init_generic: Setting adjustable number of callback queues.
10668 11:48:23.471161 <6>[ 0.058832] cblist_init_generic: Setting shift to 3 and lim to 1.
10669 11:48:23.474583 <6>[ 0.065210] cblist_init_generic: Setting shift to 3 and lim to 1.
10670 11:48:23.480957 <6>[ 0.071620] rcu: Hierarchical SRCU implementation.
10671 11:48:23.487458 <6>[ 0.076638] rcu: Max phase no-delay instances is 1000.
10672 11:48:23.493959 <6>[ 0.083658] EFI services will not be available.
10673 11:48:23.497470 <6>[ 0.088653] smp: Bringing up secondary CPUs ...
10674 11:48:23.505731 <6>[ 0.093702] Detected VIPT I-cache on CPU1
10675 11:48:23.512486 <6>[ 0.093776] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10676 11:48:23.518907 <6>[ 0.093807] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10677 11:48:23.521947 <6>[ 0.094147] Detected VIPT I-cache on CPU2
10678 11:48:23.532005 <6>[ 0.094200] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10679 11:48:23.538561 <6>[ 0.094219] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10680 11:48:23.541737 <6>[ 0.094479] Detected VIPT I-cache on CPU3
10681 11:48:23.548197 <6>[ 0.094526] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10682 11:48:23.554898 <6>[ 0.094541] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10683 11:48:23.558593 <6>[ 0.094848] CPU features: detected: Spectre-v4
10684 11:48:23.564616 <6>[ 0.094855] CPU features: detected: Spectre-BHB
10685 11:48:23.568238 <6>[ 0.094860] Detected PIPT I-cache on CPU4
10686 11:48:23.574318 <6>[ 0.094918] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10687 11:48:23.580751 <6>[ 0.094934] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10688 11:48:23.587479 <6>[ 0.095228] Detected PIPT I-cache on CPU5
10689 11:48:23.594173 <6>[ 0.095293] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10690 11:48:23.600801 <6>[ 0.095309] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10691 11:48:23.603871 <6>[ 0.095594] Detected PIPT I-cache on CPU6
10692 11:48:23.610665 <6>[ 0.095660] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10693 11:48:23.617345 <6>[ 0.095676] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10694 11:48:23.623630 <6>[ 0.095971] Detected PIPT I-cache on CPU7
10695 11:48:23.630455 <6>[ 0.096036] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10696 11:48:23.636865 <6>[ 0.096053] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10697 11:48:23.640280 <6>[ 0.096100] smp: Brought up 1 node, 8 CPUs
10698 11:48:23.646833 <6>[ 0.237341] SMP: Total of 8 processors activated.
10699 11:48:23.650129 <6>[ 0.242261] CPU features: detected: 32-bit EL0 Support
10700 11:48:23.660073 <6>[ 0.247624] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10701 11:48:23.666724 <6>[ 0.256425] CPU features: detected: Common not Private translations
10702 11:48:23.673245 <6>[ 0.262900] CPU features: detected: CRC32 instructions
10703 11:48:23.679808 <6>[ 0.268251] CPU features: detected: RCpc load-acquire (LDAPR)
10704 11:48:23.682892 <6>[ 0.274211] CPU features: detected: LSE atomic instructions
10705 11:48:23.689625 <6>[ 0.280028] CPU features: detected: Privileged Access Never
10706 11:48:23.695900 <6>[ 0.285807] CPU features: detected: RAS Extension Support
10707 11:48:23.702615 <6>[ 0.291450] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10708 11:48:23.706013 <6>[ 0.298670] CPU: All CPU(s) started at EL2
10709 11:48:23.712611 <6>[ 0.303013] alternatives: applying system-wide alternatives
10710 11:48:23.722491 <6>[ 0.313722] devtmpfs: initialized
10711 11:48:23.738053 <6>[ 0.322491] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10712 11:48:23.744443 <6>[ 0.332457] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10713 11:48:23.751115 <6>[ 0.340665] pinctrl core: initialized pinctrl subsystem
10714 11:48:23.754292 <6>[ 0.347323] DMI not present or invalid.
10715 11:48:23.761212 <6>[ 0.351728] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10716 11:48:23.771061 <6>[ 0.358603] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10717 11:48:23.777780 <6>[ 0.366182] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10718 11:48:23.787674 <6>[ 0.374406] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10719 11:48:23.791034 <6>[ 0.382647] audit: initializing netlink subsys (disabled)
10720 11:48:23.800985 <5>[ 0.388339] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10721 11:48:23.807783 <6>[ 0.389036] thermal_sys: Registered thermal governor 'step_wise'
10722 11:48:23.813915 <6>[ 0.396304] thermal_sys: Registered thermal governor 'power_allocator'
10723 11:48:23.817742 <6>[ 0.402557] cpuidle: using governor menu
10724 11:48:23.824480 <6>[ 0.413515] NET: Registered PF_QIPCRTR protocol family
10725 11:48:23.831163 <6>[ 0.418986] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10726 11:48:23.837267 <6>[ 0.426090] ASID allocator initialised with 32768 entries
10727 11:48:23.840730 <6>[ 0.432670] Serial: AMBA PL011 UART driver
10728 11:48:23.850569 <4>[ 0.441383] Trying to register duplicate clock ID: 134
10729 11:48:23.904512 <6>[ 0.498737] KASLR enabled
10730 11:48:23.919255 <6>[ 0.506438] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10731 11:48:23.925686 <6>[ 0.513449] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10732 11:48:23.932348 <6>[ 0.519937] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10733 11:48:23.938549 <6>[ 0.526942] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10734 11:48:23.945424 <6>[ 0.533427] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10735 11:48:23.952104 <6>[ 0.540431] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10736 11:48:23.958948 <6>[ 0.546916] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10737 11:48:23.965063 <6>[ 0.553919] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10738 11:48:23.968195 <6>[ 0.561398] ACPI: Interpreter disabled.
10739 11:48:23.977249 <6>[ 0.567819] iommu: Default domain type: Translated
10740 11:48:23.983856 <6>[ 0.572934] iommu: DMA domain TLB invalidation policy: strict mode
10741 11:48:23.987019 <5>[ 0.579598] SCSI subsystem initialized
10742 11:48:23.993754 <6>[ 0.583832] usbcore: registered new interface driver usbfs
10743 11:48:24.000179 <6>[ 0.589560] usbcore: registered new interface driver hub
10744 11:48:24.003330 <6>[ 0.595113] usbcore: registered new device driver usb
10745 11:48:24.010761 <6>[ 0.601208] pps_core: LinuxPPS API ver. 1 registered
10746 11:48:24.020719 <6>[ 0.606402] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10747 11:48:24.023920 <6>[ 0.615741] PTP clock support registered
10748 11:48:24.027195 <6>[ 0.619979] EDAC MC: Ver: 3.0.0
10749 11:48:24.034606 <6>[ 0.625154] FPGA manager framework
10750 11:48:24.040950 <6>[ 0.628833] Advanced Linux Sound Architecture Driver Initialized.
10751 11:48:24.044528 <6>[ 0.635596] vgaarb: loaded
10752 11:48:24.051027 <6>[ 0.638746] clocksource: Switched to clocksource arch_sys_counter
10753 11:48:24.054618 <5>[ 0.645193] VFS: Disk quotas dquot_6.6.0
10754 11:48:24.060716 <6>[ 0.649377] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10755 11:48:24.064219 <6>[ 0.656567] pnp: PnP ACPI: disabled
10756 11:48:24.072409 <6>[ 0.663226] NET: Registered PF_INET protocol family
10757 11:48:24.082436 <6>[ 0.668820] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10758 11:48:24.093995 <6>[ 0.681137] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10759 11:48:24.103812 <6>[ 0.689952] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10760 11:48:24.110428 <6>[ 0.697923] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10761 11:48:24.120109 <6>[ 0.706623] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10762 11:48:24.126781 <6>[ 0.716373] TCP: Hash tables configured (established 65536 bind 65536)
10763 11:48:24.133497 <6>[ 0.723234] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10764 11:48:24.143204 <6>[ 0.730432] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10765 11:48:24.149846 <6>[ 0.738130] NET: Registered PF_UNIX/PF_LOCAL protocol family
10766 11:48:24.153325 <6>[ 0.744271] RPC: Registered named UNIX socket transport module.
10767 11:48:24.159666 <6>[ 0.750426] RPC: Registered udp transport module.
10768 11:48:24.163342 <6>[ 0.755357] RPC: Registered tcp transport module.
10769 11:48:24.172785 <6>[ 0.760287] RPC: Registered tcp NFSv4.1 backchannel transport module.
10770 11:48:24.176047 <6>[ 0.766952] PCI: CLS 0 bytes, default 64
10771 11:48:24.179507 <6>[ 0.771212] Unpacking initramfs...
10772 11:48:24.195977 <6>[ 0.783278] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10773 11:48:24.205646 <6>[ 0.791932] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10774 11:48:24.208936 <6>[ 0.800767] kvm [1]: IPA Size Limit: 40 bits
10775 11:48:24.215964 <6>[ 0.805295] kvm [1]: GICv3: no GICV resource entry
10776 11:48:24.218995 <6>[ 0.810316] kvm [1]: disabling GICv2 emulation
10777 11:48:24.225602 <6>[ 0.814999] kvm [1]: GIC system register CPU interface enabled
10778 11:48:24.228922 <6>[ 0.821154] kvm [1]: vgic interrupt IRQ18
10779 11:48:24.236408 <6>[ 0.826797] kvm [1]: VHE mode initialized successfully
10780 11:48:24.242943 <5>[ 0.833190] Initialise system trusted keyrings
10781 11:48:24.249122 <6>[ 0.837976] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10782 11:48:24.257569 <6>[ 0.848031] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10783 11:48:24.264248 <5>[ 0.854425] NFS: Registering the id_resolver key type
10784 11:48:24.267544 <5>[ 0.859731] Key type id_resolver registered
10785 11:48:24.273811 <5>[ 0.864145] Key type id_legacy registered
10786 11:48:24.280341 <6>[ 0.868436] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10787 11:48:24.286988 <6>[ 0.875357] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10788 11:48:24.293526 <6>[ 0.883118] 9p: Installing v9fs 9p2000 file system support
10789 11:48:24.330331 <5>[ 0.920682] Key type asymmetric registered
10790 11:48:24.333694 <5>[ 0.925013] Asymmetric key parser 'x509' registered
10791 11:48:24.343138 <6>[ 0.930165] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10792 11:48:24.346179 <6>[ 0.937779] io scheduler mq-deadline registered
10793 11:48:24.349825 <6>[ 0.942540] io scheduler kyber registered
10794 11:48:24.368274 <6>[ 0.959332] EINJ: ACPI disabled.
10795 11:48:24.400439 <4>[ 0.984985] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10796 11:48:24.410215 <4>[ 0.995758] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10797 11:48:24.425581 <6>[ 1.016686] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10798 11:48:24.433359 <6>[ 1.024660] printk: console [ttyS0] disabled
10799 11:48:24.461480 <6>[ 1.049305] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10800 11:48:24.467997 <6>[ 1.058787] printk: console [ttyS0] enabled
10801 11:48:24.471562 <6>[ 1.058787] printk: console [ttyS0] enabled
10802 11:48:24.478001 <6>[ 1.067684] printk: bootconsole [mtk8250] disabled
10803 11:48:24.481219 <6>[ 1.067684] printk: bootconsole [mtk8250] disabled
10804 11:48:24.487673 <6>[ 1.078954] SuperH (H)SCI(F) driver initialized
10805 11:48:24.491286 <6>[ 1.084222] msm_serial: driver initialized
10806 11:48:24.505296 <6>[ 1.093123] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10807 11:48:24.515244 <6>[ 1.101670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10808 11:48:24.522098 <6>[ 1.110211] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10809 11:48:24.532047 <6>[ 1.118840] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10810 11:48:24.538546 <6>[ 1.127552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10811 11:48:24.548493 <6>[ 1.136267] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10812 11:48:24.558301 <6>[ 1.144807] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10813 11:48:24.564884 <6>[ 1.153616] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10814 11:48:24.574574 <6>[ 1.162161] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10815 11:48:24.586570 <6>[ 1.177831] loop: module loaded
10816 11:48:24.593191 <6>[ 1.183833] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10817 11:48:24.615707 <4>[ 1.206914] mtk-pmic-keys: Failed to locate of_node [id: -1]
10818 11:48:24.622488 <6>[ 1.213790] megasas: 07.719.03.00-rc1
10819 11:48:24.632024 <6>[ 1.223310] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10820 11:48:24.639455 <6>[ 1.230154] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10821 11:48:24.655329 <6>[ 1.246086] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10822 11:48:24.715244 <6>[ 1.299424] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10823 11:48:28.146568 <6>[ 4.738100] Freeing initrd memory: 95852K
10824 11:48:28.156998 <6>[ 4.748432] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10825 11:48:28.168059 <6>[ 4.759217] tun: Universal TUN/TAP device driver, 1.6
10826 11:48:28.171308 <6>[ 4.765264] thunder_xcv, ver 1.0
10827 11:48:28.174496 <6>[ 4.768769] thunder_bgx, ver 1.0
10828 11:48:28.177777 <6>[ 4.772263] nicpf, ver 1.0
10829 11:48:28.188234 <6>[ 4.776259] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10830 11:48:28.191620 <6>[ 4.783734] hns3: Copyright (c) 2017 Huawei Corporation.
10831 11:48:28.195230 <6>[ 4.789319] hclge is initializing
10832 11:48:28.201239 <6>[ 4.792892] e1000: Intel(R) PRO/1000 Network Driver
10833 11:48:28.207991 <6>[ 4.798022] e1000: Copyright (c) 1999-2006 Intel Corporation.
10834 11:48:28.211148 <6>[ 4.804051] e1000e: Intel(R) PRO/1000 Network Driver
10835 11:48:28.218010 <6>[ 4.809267] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10836 11:48:28.224482 <6>[ 4.815454] igb: Intel(R) Gigabit Ethernet Network Driver
10837 11:48:28.231211 <6>[ 4.821104] igb: Copyright (c) 2007-2014 Intel Corporation.
10838 11:48:28.237468 <6>[ 4.826939] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10839 11:48:28.243960 <6>[ 4.833458] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10840 11:48:28.247555 <6>[ 4.839912] sky2: driver version 1.30
10841 11:48:28.254262 <6>[ 4.844879] VFIO - User Level meta-driver version: 0.3
10842 11:48:28.261800 <6>[ 4.853051] usbcore: registered new interface driver usb-storage
10843 11:48:28.268292 <6>[ 4.859491] usbcore: registered new device driver onboard-usb-hub
10844 11:48:28.276956 <6>[ 4.868548] mt6397-rtc mt6359-rtc: registered as rtc0
10845 11:48:28.286820 <6>[ 4.874016] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:48:23 UTC (1686829703)
10846 11:48:28.289930 <6>[ 4.883579] i2c_dev: i2c /dev entries driver
10847 11:48:28.307342 <6>[ 4.895183] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10848 11:48:28.314387 <6>[ 4.905371] sdhci: Secure Digital Host Controller Interface driver
10849 11:48:28.321057 <6>[ 4.911811] sdhci: Copyright(c) Pierre Ossman
10850 11:48:28.327381 <6>[ 4.917201] Synopsys Designware Multimedia Card Interface Driver
10851 11:48:28.330880 <6>[ 4.923817] mmc0: CQHCI version 5.10
10852 11:48:28.337009 <6>[ 4.924343] sdhci-pltfm: SDHCI platform and OF driver helper
10853 11:48:28.344239 <6>[ 4.935664] ledtrig-cpu: registered to indicate activity on CPUs
10854 11:48:28.355101 <6>[ 4.943017] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10855 11:48:28.358460 <6>[ 4.950409] usbcore: registered new interface driver usbhid
10856 11:48:28.365040 <6>[ 4.956241] usbhid: USB HID core driver
10857 11:48:28.371455 <6>[ 4.960484] spi_master spi0: will run message pump with realtime priority
10858 11:48:28.421992 <6>[ 5.006591] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10859 11:48:28.441349 <6>[ 5.021839] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10860 11:48:28.444602 <6>[ 5.035465] mmc0: Command Queue Engine enabled
10861 11:48:28.451435 <6>[ 5.037392] cros-ec-spi spi0.0: Chrome EC device registered
10862 11:48:28.455099 <6>[ 5.040217] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10863 11:48:28.462504 <6>[ 5.053600] mmcblk0: mmc0:0001 DA4128 116 GiB
10864 11:48:28.472289 <6>[ 5.063419] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10865 11:48:28.482491 <6>[ 5.065445] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10866 11:48:28.488443 <6>[ 5.070690] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10867 11:48:28.492051 <6>[ 5.080759] NET: Registered PF_PACKET protocol family
10868 11:48:28.498525 <6>[ 5.084535] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10869 11:48:28.501880 <6>[ 5.089302] 9pnet: Installing 9P2000 support
10870 11:48:28.508521 <6>[ 5.095061] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10871 11:48:28.515104 <5>[ 5.098992] Key type dns_resolver registered
10872 11:48:28.518287 <6>[ 5.110516] registered taskstats version 1
10873 11:48:28.525017 <5>[ 5.114916] Loading compiled-in X.509 certificates
10874 11:48:28.557809 <4>[ 5.142084] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10875 11:48:28.567462 <4>[ 5.152784] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10876 11:48:28.577475 <3>[ 5.165509] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10877 11:48:28.589896 <6>[ 5.181118] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10878 11:48:28.596632 <6>[ 5.187881] xhci-mtk 11200000.usb: xHCI Host Controller
10879 11:48:28.603387 <6>[ 5.193387] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10880 11:48:28.613334 <6>[ 5.201233] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10881 11:48:28.619661 <6>[ 5.210669] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10882 11:48:28.626646 <6>[ 5.216874] xhci-mtk 11200000.usb: xHCI Host Controller
10883 11:48:28.633014 <6>[ 5.222370] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10884 11:48:28.639439 <6>[ 5.230033] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10885 11:48:28.646177 <6>[ 5.237935] hub 1-0:1.0: USB hub found
10886 11:48:28.649809 <6>[ 5.241970] hub 1-0:1.0: 1 port detected
10887 11:48:28.659839 <6>[ 5.246315] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10888 11:48:28.663009 <6>[ 5.255109] hub 2-0:1.0: USB hub found
10889 11:48:28.666093 <6>[ 5.259147] hub 2-0:1.0: 1 port detected
10890 11:48:28.674517 <6>[ 5.266362] mtk-msdc 11f70000.mmc: Got CD GPIO
10891 11:48:28.692574 <6>[ 5.280734] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10892 11:48:28.698976 <6>[ 5.288793] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10893 11:48:28.708761 <4>[ 5.296757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10894 11:48:28.718763 <6>[ 5.306415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10895 11:48:28.725386 <6>[ 5.314498] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10896 11:48:28.735375 <6>[ 5.322520] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10897 11:48:28.742170 <6>[ 5.330433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10898 11:48:28.748426 <6>[ 5.338255] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10899 11:48:28.758406 <6>[ 5.346077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10900 11:48:28.768525 <6>[ 5.356770] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10901 11:48:28.778136 <6>[ 5.365158] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10902 11:48:28.784714 <6>[ 5.373510] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10903 11:48:28.794686 <6>[ 5.381854] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10904 11:48:28.801572 <6>[ 5.390197] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10905 11:48:28.811500 <6>[ 5.398540] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10906 11:48:28.818057 <6>[ 5.406884] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10907 11:48:28.827713 <6>[ 5.415227] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10908 11:48:28.834548 <6>[ 5.423571] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10909 11:48:28.844539 <6>[ 5.431914] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10910 11:48:28.850805 <6>[ 5.440258] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10911 11:48:28.861116 <6>[ 5.448602] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10912 11:48:28.867627 <6>[ 5.456944] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10913 11:48:28.877165 <6>[ 5.465288] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10914 11:48:28.883911 <6>[ 5.473642] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10915 11:48:28.890780 <6>[ 5.482522] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10916 11:48:28.898295 <6>[ 5.489974] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10917 11:48:28.905485 <6>[ 5.497050] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10918 11:48:28.915619 <6>[ 5.504197] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10919 11:48:28.922382 <6>[ 5.511518] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10920 11:48:28.932258 <6>[ 5.518450] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10921 11:48:28.938807 <6>[ 5.527590] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10922 11:48:28.948867 <6>[ 5.536716] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10923 11:48:28.958532 <6>[ 5.546018] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10924 11:48:28.968878 <6>[ 5.555492] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10925 11:48:28.978699 <6>[ 5.564966] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10926 11:48:28.988482 <6>[ 5.574094] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10927 11:48:28.995315 <6>[ 5.583570] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10928 11:48:29.005162 <6>[ 5.592697] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10929 11:48:29.014730 <6>[ 5.601999] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10930 11:48:29.024431 <6>[ 5.612165] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10931 11:48:29.035615 <6>[ 5.624113] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10932 11:48:29.074713 <6>[ 5.663021] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10933 11:48:29.228474 <6>[ 5.820281] hub 1-1:1.0: USB hub found
10934 11:48:29.231974 <6>[ 5.824732] hub 1-1:1.0: 4 ports detected
10935 11:48:29.355398 <6>[ 5.943230] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10936 11:48:29.379981 <6>[ 5.971651] hub 2-1:1.0: USB hub found
10937 11:48:29.383573 <6>[ 5.976046] hub 2-1:1.0: 3 ports detected
10938 11:48:29.554843 <6>[ 6.143018] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10939 11:48:29.687330 <6>[ 6.279082] hub 1-1.4:1.0: USB hub found
10940 11:48:29.690588 <6>[ 6.283755] hub 1-1.4:1.0: 2 ports detected
10941 11:48:29.766844 <6>[ 6.355263] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10942 11:48:29.986728 <6>[ 6.575020] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10943 11:48:30.178853 <6>[ 6.767021] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10944 11:48:41.335300 <6>[ 17.931610] ALSA device list:
10945 11:48:41.341469 <6>[ 17.934859] No soundcards found.
10946 11:48:41.354380 <6>[ 17.947289] Freeing unused kernel memory: 8384K
10947 11:48:41.357462 <6>[ 17.952207] Run /init as init process
10948 11:48:41.388129 <6>[ 17.981144] NET: Registered PF_INET6 protocol family
10949 11:48:41.394806 <6>[ 17.987731] Segment Routing with IPv6
10950 11:48:41.397915 <6>[ 17.991692] In-situ OAM (IOAM) with IPv6
10951 11:48:41.432514 <30>[ 18.006075] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10952 11:48:41.435996 <30>[ 18.029899] systemd[1]: Detected architecture arm64.
10953 11:48:41.436085
10954 11:48:41.442604 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10955 11:48:41.442689
10956 11:48:41.462182 <30>[ 18.055130] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10957 11:48:41.587257 <30>[ 18.177109] systemd[1]: Queued start job for default target Graphical Interface.
10958 11:48:41.635354 <30>[ 18.228303] systemd[1]: Created slice system-getty.slice.
10959 11:48:41.641794 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10960 11:48:41.658394 <30>[ 18.251598] systemd[1]: Created slice system-modprobe.slice.
10961 11:48:41.664979 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10962 11:48:41.682175 <30>[ 18.275497] systemd[1]: Created slice system-serial\x2dgetty.slice.
10963 11:48:41.692637 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10964 11:48:41.707106 <30>[ 18.300053] systemd[1]: Created slice User and Session Slice.
10965 11:48:41.713312 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10966 11:48:41.733770 <30>[ 18.323558] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10967 11:48:41.743590 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10968 11:48:41.761766 <30>[ 18.351542] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10969 11:48:41.768168 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10970 11:48:41.788575 <30>[ 18.375106] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10971 11:48:41.795397 <30>[ 18.387135] systemd[1]: Reached target Local Encrypted Volumes.
10972 11:48:41.801727 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10973 11:48:41.818293 <30>[ 18.411377] systemd[1]: Reached target Paths.
10974 11:48:41.821403 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10975 11:48:41.837955 <30>[ 18.431052] systemd[1]: Reached target Remote File Systems.
10976 11:48:41.844384 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10977 11:48:41.857797 <30>[ 18.451077] systemd[1]: Reached target Slices.
10978 11:48:41.861290 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10979 11:48:41.878031 <30>[ 18.471069] systemd[1]: Reached target Swap.
10980 11:48:41.881162 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10981 11:48:41.901382 <30>[ 18.491364] systemd[1]: Listening on initctl Compatibility Named Pipe.
10982 11:48:41.908158 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10983 11:48:41.914912 <30>[ 18.506077] systemd[1]: Listening on Journal Audit Socket.
10984 11:48:41.921213 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10985 11:48:41.933951 <30>[ 18.527315] systemd[1]: Listening on Journal Socket (/dev/log).
10986 11:48:41.941009 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10987 11:48:41.958321 <30>[ 18.551337] systemd[1]: Listening on Journal Socket.
10988 11:48:41.964830 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10989 11:48:41.978315 <30>[ 18.571323] systemd[1]: Listening on udev Control Socket.
10990 11:48:41.985071 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10991 11:48:42.002659 <30>[ 18.595694] systemd[1]: Listening on udev Kernel Socket.
10992 11:48:42.008947 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10993 11:48:42.042070 <30>[ 18.635270] systemd[1]: Mounting Huge Pages File System...
10994 11:48:42.048895 Mounting [0;1;39mHuge Pages File System[0m...
10995 11:48:42.064068 <30>[ 18.657170] systemd[1]: Mounting POSIX Message Queue File System...
10996 11:48:42.070765 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10997 11:48:42.088160 <30>[ 18.681127] systemd[1]: Mounting Kernel Debug File System...
10998 11:48:42.094664 Mounting [0;1;39mKernel Debug File System[0m...
10999 11:48:42.113648 <30>[ 18.703356] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11000 11:48:42.145834 <30>[ 18.735555] systemd[1]: Starting Create list of static device nodes for the current kernel...
11001 11:48:42.152436 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11002 11:48:42.172213 <30>[ 18.765504] systemd[1]: Starting Load Kernel Module configfs...
11003 11:48:42.178720 Starting [0;1;39mLoad Kernel Module configfs[0m...
11004 11:48:42.196271 <30>[ 18.789369] systemd[1]: Starting Load Kernel Module drm...
11005 11:48:42.202784 Starting [0;1;39mLoad Kernel Module drm[0m...
11006 11:48:42.221480 <30>[ 18.811315] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11007 11:48:42.258643 <30>[ 18.851621] systemd[1]: Starting Journal Service...
11008 11:48:42.261793 Starting [0;1;39mJournal Service[0m...
11009 11:48:42.280744 <30>[ 18.873679] systemd[1]: Starting Load Kernel Modules...
11010 11:48:42.286849 Starting [0;1;39mLoad Kernel Modules[0m...
11011 11:48:42.338127 <30>[ 18.927890] systemd[1]: Starting Remount Root and Kernel File Systems...
11012 11:48:42.344487 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11013 11:48:42.360548 <30>[ 18.953660] systemd[1]: Starting Coldplug All udev Devices...
11014 11:48:42.367133 Starting [0;1;39mColdplug All udev Devices[0m...
11015 11:48:42.384179 <30>[ 18.977414] systemd[1]: Started Journal Service.
11016 11:48:42.390790 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11017 11:48:42.407761 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11018 11:48:42.422618 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11019 11:48:42.439010 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11020 11:48:42.458311 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11021 11:48:42.475492 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11022 11:48:42.495738 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11023 11:48:42.514794 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11024 11:48:42.539042 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11025 11:48:42.557773 See 'systemctl status systemd-remount-fs.service' for details.
11026 11:48:42.598518 Mounting [0;1;39mKernel Configuration File System[0m...
11027 11:48:42.620619 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11028 11:48:42.637321 <46>[ 19.227546] systemd-journald[179]: Received client request to flush runtime journal.
11029 11:48:42.646258 Starting [0;1;39mLoad/Save Random Seed[0m...
11030 11:48:42.669146 Starting [0;1;39mApply Kernel Variables[0m...
11031 11:48:42.685946 Starting [0;1;39mCreate System Users[0m...
11032 11:48:42.709256 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11033 11:48:42.734001 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11034 11:48:42.747161 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11035 11:48:42.763240 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11036 11:48:42.778702 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11037 11:48:42.794946 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11038 11:48:42.826683 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11039 11:48:42.850524 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11040 11:48:42.866241 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11041 11:48:42.886068 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11042 11:48:42.918495 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11043 11:48:42.941640 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11044 11:48:42.962705 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11045 11:48:42.983277 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11046 11:48:43.031055 Starting [0;1;39mNetwork Time Synchronization[0m...
11047 11:48:43.052595 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11048 11:48:43.097509 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11049 11:48:43.136061 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11050 11:48:43.149355 <6>[ 19.739518] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11051 11:48:43.159542 <6>[ 19.752846] remoteproc remoteproc0: scp is available
11052 11:48:43.169378 <4>[ 19.758532] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11053 11:48:43.176058 <6>[ 19.768443] remoteproc remoteproc0: powering up scp
11054 11:48:43.186155 <4>[ 19.773658] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11055 11:48:43.192441 <3>[ 19.783584] remoteproc remoteproc0: request_firmware failed: -2
11056 11:48:43.202408 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11057 11:48:43.209106 <6>[ 19.799432] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11058 11:48:43.215552 <3>[ 19.803968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11059 11:48:43.225879 <6>[ 19.807773] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11060 11:48:43.232496 <3>[ 19.815590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11061 11:48:43.242160 <6>[ 19.824165] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11062 11:48:43.251855 <3>[ 19.832167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11063 11:48:43.258411 <3>[ 19.849048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11064 11:48:43.268757 <3>[ 19.857198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11065 11:48:43.275557 [[0;32m OK [<3>[ 19.865695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11066 11:48:43.285256 0m] Started [0;<3>[ 19.874800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11067 11:48:43.295186 1;39mNetwork Tim<3>[ 19.884307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11068 11:48:43.301648 e Synchronizatio<6>[ 19.885000] mc: Linux media interface: v0.10
11069 11:48:43.301733 n[0m.
11070 11:48:43.311856 <3>[ 19.900252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11071 11:48:43.318083 <3>[ 19.908906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11072 11:48:43.328023 <3>[ 19.917369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11073 11:48:43.334703 <4>[ 19.920312] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11074 11:48:43.341328 <6>[ 19.922858] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11075 11:48:43.347792 <6>[ 19.923698] usbcore: registered new interface driver r8152
11076 11:48:43.354332 <3>[ 19.925572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11077 11:48:43.364507 <4>[ 19.936184] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11078 11:48:43.368110 <6>[ 19.945546] videodev: Linux video capture interface: v2.00
11079 11:48:43.378082 <3>[ 19.946168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11080 11:48:43.384586 <3>[ 19.946188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11081 11:48:43.394429 <3>[ 19.946196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11082 11:48:43.400964 <3>[ 19.946205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11083 11:48:43.411563 <3>[ 19.946212] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11084 11:48:43.418102 <3>[ 19.950393] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11085 11:48:43.424777 <4>[ 19.952968] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11086 11:48:43.431470 <4>[ 19.952968] Fallback method does not support PEC.
11087 11:48:43.441210 <3>[ 19.968551] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11088 11:48:43.448001 <6>[ 19.987402] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11089 11:48:43.454491 <3>[ 20.008346] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11090 11:48:43.461432 <6>[ 20.016802] pci_bus 0000:00: root bus resource [bus 00-ff]
11091 11:48:43.471473 <3>[ 20.030481] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11092 11:48:43.482180 <6>[ 20.037612] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11093 11:48:43.488507 <6>[ 20.038505] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11094 11:48:43.498255 <6>[ 20.038531] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11095 11:48:43.504934 <6>[ 20.038644] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11096 11:48:43.511595 <6>[ 20.038686] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11097 11:48:43.515081 <6>[ 20.038841] pci 0000:00:00.0: supports D1 D2
11098 11:48:43.521869 <6>[ 20.043465] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11099 11:48:43.531925 <6>[ 20.046123] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11100 11:48:43.538541 <6>[ 20.056212] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11101 11:48:43.545323 <3>[ 20.060661] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11102 11:48:43.555445 <4>[ 20.074399] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11103 11:48:43.561865 <6>[ 20.084635] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11104 11:48:43.571636 <3>[ 20.086443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11105 11:48:43.581809 <4>[ 20.086565] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11106 11:48:43.584802 <6>[ 20.096655] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11107 11:48:43.594663 <3>[ 20.124655] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11108 11:48:43.601370 <6>[ 20.130813] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11109 11:48:43.608074 <3>[ 20.184586] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11110 11:48:43.614715 <6>[ 20.193435] r8152 2-1.3:1.0 eth0: v1.12.13
11111 11:48:43.621577 <6>[ 20.193441] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11112 11:48:43.628520 <6>[ 20.193464] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11113 11:48:43.632138 <6>[ 20.193599] pci 0000:01:00.0: supports D1 D2
11114 11:48:43.638707 <6>[ 20.193603] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11115 11:48:43.645360 <6>[ 20.206942] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11116 11:48:43.655588 <3>[ 20.225298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11117 11:48:43.662566 <6>[ 20.226545] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11118 11:48:43.672537 <3>[ 20.253430] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11119 11:48:43.678932 <6>[ 20.253538] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11120 11:48:43.689236 <6>[ 20.278390] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11121 11:48:43.695892 <6>[ 20.278406] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11122 11:48:43.705720 <6>[ 20.294392] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11123 11:48:43.711985 [[0;32m OK [<6>[ 20.302399] pci 0000:00:00.0: PCI bridge to [bus 01]
11124 11:48:43.718612 0m] Finished [0<6>[ 20.309005] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11125 11:48:43.729027 ;1;39mLoad/Save <3>[ 20.309073] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
11126 11:48:43.735637 Screen …s of l<6>[ 20.318582] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11127 11:48:43.742080 eds:white:kbd_ba<3>[ 20.334043] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
11128 11:48:43.745759 cklight[0m.
11129 11:48:43.751915 <6>[ 20.334978] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11130 11:48:43.759122 <3>[ 20.335823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11131 11:48:43.769134 <6>[ 20.342253] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11132 11:48:43.775539 <6>[ 20.349784] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11133 11:48:43.782155 <3>[ 20.358276] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11134 11:48:43.792436 [[0;32m OK [0m] Found device<6>[ 20.384144] usbcore: registered new interface driver cdc_ether
11135 11:48:43.802635 [0;1;39m/dev/t<5>[ 20.386070] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11136 11:48:43.802750 tyS0[0m.
11137 11:48:43.809103 <6>[ 20.402451] usbcore: registered new interface driver r8153_ecm
11138 11:48:43.815779 <6>[ 20.402488] Bluetooth: Core ver 2.22
11139 11:48:43.818971 <6>[ 20.412860] NET: Registered PF_BLUETOOTH protocol family
11140 11:48:43.825633 <6>[ 20.414556] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11141 11:48:43.835458 <5>[ 20.414916] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11142 11:48:43.842417 <4>[ 20.415004] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11143 11:48:43.849044 <6>[ 20.415013] cfg80211: failed to load regulatory.db
11144 11:48:43.855362 <6>[ 20.418463] Bluetooth: HCI device and connection manager initialized
11145 11:48:43.859312 <6>[ 20.418483] Bluetooth: HCI socket layer initialized
11146 11:48:43.866152 <6>[ 20.425400] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
11147 11:48:43.876584 <6>[ 20.426920] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11148 11:48:43.883407 <6>[ 20.432775] Bluetooth: L2CAP socket layer initialized
11149 11:48:43.890013 <6>[ 20.433352] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11150 11:48:43.896828 <6>[ 20.437949] remoteproc remoteproc0: powering up scp
11151 11:48:43.903955 <4>[ 20.437993] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11152 11:48:43.910715 <3>[ 20.438002] remoteproc remoteproc0: request_firmware failed: -2
11153 11:48:43.920498 <3>[ 20.438006] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11154 11:48:43.923631 <6>[ 20.441609] usbcore: registered new interface driver uvcvideo
11155 11:48:43.931036 <6>[ 20.446427] Bluetooth: SCO socket layer initialized
11156 11:48:43.937600 <3>[ 20.471029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11157 11:48:43.946039 <6>[ 20.539246] usbcore: registered new interface driver btusb
11158 11:48:43.956016 <4>[ 20.540064] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11159 11:48:43.962301 <3>[ 20.555603] Bluetooth: hci0: Failed to load firmware file (-2)
11160 11:48:43.969264 <3>[ 20.561792] Bluetooth: hci0: Failed to set up firmware (-2)
11161 11:48:43.978861 <4>[ 20.567787] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11162 11:48:43.985508 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11163 11:48:43.992280 <6>[ 20.583844] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11164 11:48:43.998864 <6>[ 20.591513] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11165 11:48:44.005245 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11166 11:48:44.025253 [[0;32m OK [0m] Started [0;1;39mDaily Clean<6>[ 20.618279] mt7921e 0000:01:00.0: ASIC revision: 79610010
11167 11:48:44.028398 up of Temporary Directories[0m.
11168 11:48:44.045559 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11169 11:48:44.061808 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11170 11:48:44.081671 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11171 11:48:44.094080 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11172 11:48:44.113745 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11173 11:48:44.132641 <4>[ 20.719289] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11174 11:48:44.135855 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11175 11:48:44.153912 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11176 11:48:44.173578 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11177 11:48:44.206176 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11178 11:48:44.236400 Starting [0;1;39mUser Login Management[0m...
11179 11:48:44.252444 <4>[ 20.839359] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11180 11:48:44.263744 Starting [0;1;39mPermit User Sessions[0m...
11181 11:48:44.281793 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11182 11:48:44.298739 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11183 11:48:44.315412 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11184 11:48:44.374723 <4>[ 20.961479] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11185 11:48:44.381235 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11186 11:48:44.399049 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11187 11:48:44.405192 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11188 11:48:44.423131 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11189 11:48:44.430334 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11190 11:48:44.446358 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11191 11:48:44.494885 <4>[ 21.081623] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11192 11:48:44.519457 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11193 11:48:44.546334 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11194 11:48:44.616469 <4>[ 21.203396] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11195 11:48:44.616633
11196 11:48:44.616740
11197 11:48:44.623193 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11198 11:48:44.623309
11199 11:48:44.626297 debian-bullseye-arm64 login: root (automatic login)
11200 11:48:44.626383
11201 11:48:44.626450
11202 11:48:44.649623 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
11203 11:48:44.649737
11204 11:48:44.656221 The programs included with the Debian GNU/Linux system are free software;
11205 11:48:44.662775 the exact distribution terms for each program are described in the
11206 11:48:44.665802 individual files in /usr/share/doc/*/copyright.
11207 11:48:44.665887
11208 11:48:44.672688 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11209 11:48:44.675850 permitted by applicable law.
11210 11:48:44.676214 Matched prompt #10: / #
11212 11:48:44.676429 Setting prompt string to ['/ #']
11213 11:48:44.676524 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11215 11:48:44.676722 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11216 11:48:44.676809 start: 2.2.6 expect-shell-connection (timeout 00:02:52) [common]
11217 11:48:44.676880 Setting prompt string to ['/ #']
11218 11:48:44.676942 Forcing a shell prompt, looking for ['/ #']
11220 11:48:44.727147 / #
11221 11:48:44.727303 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11222 11:48:44.727422 Waiting using forced prompt support (timeout 00:02:30)
11223 11:48:44.738337 <4>[ 21.325270] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11224 11:48:44.738448
11225 11:48:44.742124 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11226 11:48:44.742230 start: 2.2.7 export-device-env (timeout 00:02:52) [common]
11227 11:48:44.742328 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11228 11:48:44.742445 end: 2.2 depthcharge-retry (duration 00:02:08) [common]
11229 11:48:44.742535 end: 2 depthcharge-action (duration 00:02:08) [common]
11230 11:48:44.742621 start: 3 lava-test-retry (timeout 00:05:00) [common]
11231 11:48:44.742707 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11232 11:48:44.742782 Using namespace: common
11234 11:48:44.843090 / # #
11235 11:48:44.843303 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11236 11:48:44.848137 #
11237 11:48:44.857956 <4>[ 21.445453] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11238 11:48:44.858270 Using /lava-10742265
11240 11:48:44.958636 / # export SHELL=/bin/sh
11241 11:48:44.964486 export SHELL=/bin/sh
11243 11:48:45.068127 / # <4>[ 21.565986] mt7. /lava-10742265/environment
11244 11:48:45.068324 921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11245 11:48:45.073239 . /lava-10742265/environment
11247 11:48:45.173745 / # /lava-10742265/bin/lava-test-runner /lava-10742265/0
11248 11:48:45.173906 Test shell timeout: 10s (minimum of the action and connection timeout)
11249 11:48:45.174231 <4>[ 21.685334] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11250 11:48:45.178709 /lava-10742265/bin/lava-test-runner /lava-10742265/0
11251 11:48:45.221178 + export TESTRUN_ID=0_sleep
11252 11:48:45.221280 + cd /lava-10742265/0/tests/0_sleep
11253 11:48:45.221349 + cat uuid
11254 11:48:45.221414 + UUID=10742265_1.5.2.3.1
11255 11:48:45.221475 + set +x
11256 11:48:45.221535 <LAVA_SIGNAL_<4>[ 21.806864] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11257 11:48:45.222114 STARTRUN 0_sleep 10742265_1.5.2.3.1>
11258 11:48:45.222374 Received signal: <<4>[> 21.806864] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
STARTRUN 0_sleep 10742265_1.5.2.3.1
11259 11:48:45.228720 + ./config/lava/sleep/sleep.sh mem freeze
11260 11:48:45.232324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11261 11:48:45.232578 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11262 11:48:45.232655 Unknown test uuid. The STARTRUN signal for this test action was not received correctly.
11264 11:48:45.232820 end: 3.1 lava-test-shell (duration 00:00:00) [common]
11266 11:48:45.233334 lava-test-retry failed: 1 of 1 attempts. 'Invalid TESTCASE signal'
11268 11:48:45.233566 end: 3 lava-test-retry (duration 00:00:00) [common]
11270 11:48:45.233900 Cleaning after the job
11271 11:48:45.234022 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/ramdisk
11272 11:48:45.243362 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/kernel
11273 11:48:45.249165 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/dtb
11274 11:48:45.249360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742265/tftp-deploy-boyaql5d/modules
11275 11:48:45.254321 start: 4.1 power-off (timeout 00:00:30) [common]
11276 11:48:45.254616 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11277 11:48:45.329856 >> Command sent successfully.
11278 11:48:45.332252 Returned 0 in 0 seconds
11279 11:48:45.432633 end: 4.1 power-off (duration 00:00:00) [common]
11281 11:48:45.433057 start: 4.2 read-feedback (timeout 00:10:00) [common]
11282 11:48:45.433328 Listened to connection for namespace 'common' for up to 1s
11294 11:48:45.434792 Listened to connection for namespace 'common' for up to 1s
11295 11:48:46.434242 Finalising connection for namespace 'common'
11296 11:48:46.434455 Disconnecting from shell: Finalise
11297 11:48:46.534834 end: 4.2 read-feedback (duration 00:00:01) [common]
11298 11:48:46.534987 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742265
11299 11:48:46.688846 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742265
11300 11:48:46.689346 TestError: A test failed to run, look at the error message.