Boot log: mt8192-asurada-spherion-r0
- Kernel Errors: 34
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 63
- Errors: 1
1 11:43:22.873153 lava-dispatcher, installed at version: 2023.05.1
2 11:43:22.873377 start: 0 validate
3 11:43:22.873546 Start time: 2023-06-15 11:43:22.873539+00:00 (UTC)
4 11:43:22.873676 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:43:22.873808 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230609.0%2Farm64%2Frootfs.cpio.gz exists
6 11:43:23.146020 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:43:23.146322 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:43:23.405004 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:43:23.405418 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:43:23.664274 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:43:23.664700 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.31-53-g486caac40d06%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:43:23.935121 validate duration: 1.06
14 11:43:23.935884 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:43:23.936161 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:43:23.936393 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:43:23.936732 Not decompressing ramdisk as can be used compressed.
18 11:43:23.936961 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230609.0/arm64/rootfs.cpio.gz
19 11:43:23.937180 saving as /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/ramdisk/rootfs.cpio.gz
20 11:43:23.937353 total size: 27153005 (25MB)
21 11:43:23.939973 progress 0% (0MB)
22 11:43:23.956950 progress 5% (1MB)
23 11:43:23.967633 progress 10% (2MB)
24 11:43:23.997874 progress 15% (3MB)
25 11:43:24.032362 progress 20% (5MB)
26 11:43:24.048967 progress 25% (6MB)
27 11:43:24.093577 progress 30% (7MB)
28 11:43:24.118601 progress 35% (9MB)
29 11:43:24.143215 progress 40% (10MB)
30 11:43:24.179482 progress 45% (11MB)
31 11:43:24.202030 progress 50% (12MB)
32 11:43:24.212855 progress 55% (14MB)
33 11:43:24.257589 progress 60% (15MB)
34 11:43:24.264562 progress 65% (16MB)
35 11:43:24.329111 progress 70% (18MB)
36 11:43:24.342286 progress 75% (19MB)
37 11:43:24.386282 progress 80% (20MB)
38 11:43:24.415130 progress 85% (22MB)
39 11:43:24.454515 progress 90% (23MB)
40 11:43:24.482133 progress 95% (24MB)
41 11:43:24.494263 progress 100% (25MB)
42 11:43:24.494556 25MB downloaded in 0.56s (46.47MB/s)
43 11:43:24.494767 end: 1.1.1 http-download (duration 00:00:01) [common]
45 11:43:24.495106 end: 1.1 download-retry (duration 00:00:01) [common]
46 11:43:24.495239 start: 1.2 download-retry (timeout 00:09:59) [common]
47 11:43:24.495361 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 11:43:24.495528 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:43:24.495633 saving as /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/kernel/Image
50 11:43:24.495721 total size: 47581696 (45MB)
51 11:43:24.495806 No compression specified
52 11:43:24.497396 progress 0% (0MB)
53 11:43:24.560934 progress 5% (2MB)
54 11:43:24.617510 progress 10% (4MB)
55 11:43:24.671775 progress 15% (6MB)
56 11:43:24.734679 progress 20% (9MB)
57 11:43:24.768031 progress 25% (11MB)
58 11:43:24.836193 progress 30% (13MB)
59 11:43:24.889341 progress 35% (15MB)
60 11:43:24.952342 progress 40% (18MB)
61 11:43:25.002315 progress 45% (20MB)
62 11:43:25.059830 progress 50% (22MB)
63 11:43:25.102103 progress 55% (24MB)
64 11:43:25.135992 progress 60% (27MB)
65 11:43:25.202214 progress 65% (29MB)
66 11:43:25.254072 progress 70% (31MB)
67 11:43:25.279665 progress 75% (34MB)
68 11:43:25.328480 progress 80% (36MB)
69 11:43:25.374460 progress 85% (38MB)
70 11:43:25.432421 progress 90% (40MB)
71 11:43:25.478124 progress 95% (43MB)
72 11:43:25.534042 progress 100% (45MB)
73 11:43:25.534279 45MB downloaded in 1.04s (43.69MB/s)
74 11:43:25.534510 end: 1.2.1 http-download (duration 00:00:01) [common]
76 11:43:25.534798 end: 1.2 download-retry (duration 00:00:01) [common]
77 11:43:25.534907 start: 1.3 download-retry (timeout 00:09:58) [common]
78 11:43:25.535016 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 11:43:25.535168 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:43:25.535261 saving as /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/dtb/mt8192-asurada-spherion-r0.dtb
81 11:43:25.535338 total size: 46924 (0MB)
82 11:43:25.535413 No compression specified
83 11:43:25.536732 progress 69% (0MB)
84 11:43:25.537081 progress 100% (0MB)
85 11:43:25.537272 0MB downloaded in 0.00s (23.17MB/s)
86 11:43:25.537424 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:43:25.537701 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:43:25.537809 start: 1.4 download-retry (timeout 00:09:58) [common]
90 11:43:25.537913 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 11:43:25.538053 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.31-53-g486caac40d06/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:43:25.538139 saving as /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/modules/modules.tar
93 11:43:25.538216 total size: 8555256 (8MB)
94 11:43:25.538291 Using unxz to decompress xz
95 11:43:25.542217 progress 0% (0MB)
96 11:43:25.569164 progress 5% (0MB)
97 11:43:25.640292 progress 10% (0MB)
98 11:43:25.667405 progress 15% (1MB)
99 11:43:25.692838 progress 20% (1MB)
100 11:43:25.740524 progress 25% (2MB)
101 11:43:25.789672 progress 30% (2MB)
102 11:43:25.845454 progress 35% (2MB)
103 11:43:25.870717 progress 40% (3MB)
104 11:43:25.920841 progress 45% (3MB)
105 11:43:25.969682 progress 50% (4MB)
106 11:43:26.033039 progress 55% (4MB)
107 11:43:26.100896 progress 60% (4MB)
108 11:43:26.136714 progress 65% (5MB)
109 11:43:26.184851 progress 70% (5MB)
110 11:43:26.208856 progress 75% (6MB)
111 11:43:26.261517 progress 80% (6MB)
112 11:43:26.285680 progress 85% (6MB)
113 11:43:26.380925 progress 90% (7MB)
114 11:43:26.465687 progress 95% (7MB)
115 11:43:26.490944 progress 100% (8MB)
116 11:43:26.495199 8MB downloaded in 0.96s (8.53MB/s)
117 11:43:26.495513 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:43:26.495824 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:43:26.495919 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 11:43:26.496019 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 11:43:26.496103 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:43:26.496190 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 11:43:26.496405 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu
125 11:43:26.496537 makedir: /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin
126 11:43:26.496638 makedir: /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/tests
127 11:43:26.496735 makedir: /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/results
128 11:43:26.496848 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-add-keys
129 11:43:26.497019 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-add-sources
130 11:43:26.497171 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-background-process-start
131 11:43:26.497315 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-background-process-stop
132 11:43:26.497475 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-common-functions
133 11:43:26.497668 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-echo-ipv4
134 11:43:26.497827 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-install-packages
135 11:43:26.497981 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-installed-packages
136 11:43:26.498152 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-os-build
137 11:43:26.498318 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-probe-channel
138 11:43:26.498472 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-probe-ip
139 11:43:26.498624 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-target-ip
140 11:43:26.498776 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-target-mac
141 11:43:26.498927 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-target-storage
142 11:43:26.499084 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-test-case
143 11:43:26.499238 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-test-event
144 11:43:26.499389 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-test-feedback
145 11:43:26.499542 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-test-raise
146 11:43:26.499695 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-test-reference
147 11:43:26.499872 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-test-runner
148 11:43:26.500024 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-test-set
149 11:43:26.500227 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-test-shell
150 11:43:26.500410 Updating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-install-packages (oe)
151 11:43:26.578015 Updating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/bin/lava-installed-packages (oe)
152 11:43:26.578413 Creating /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/environment
153 11:43:26.578648 LAVA metadata
154 11:43:26.578812 - LAVA_JOB_ID=10742243
155 11:43:26.578956 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:43:26.579201 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:57) [common]
157 11:43:26.579346 skipped lava-vland-overlay
158 11:43:26.579509 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:43:26.579690 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:57) [common]
160 11:43:26.579828 skipped lava-multinode-overlay
161 11:43:26.579991 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:43:26.580205 start: 1.5.2.3 test-definition (timeout 00:09:57) [common]
163 11:43:26.580388 Loading test definitions
164 11:43:26.580616 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:57) [common]
165 11:43:26.580890 Using /lava-10742243 at stage 0
166 11:43:26.581871 uuid=10742243_1.5.2.3.1 testdef=None
167 11:43:26.582065 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:43:26.582259 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
169 11:43:26.583295 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:43:26.583754 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
172 11:43:26.585005 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:43:26.585497 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
175 11:43:27.808411 runner path: /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10742243_1.5.2.3.1
176 11:43:27.808839 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:01) [common]
178 11:43:27.809309 Creating lava-test-runner.conf files
179 11:43:27.809436 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10742243/lava-overlay-3_joadlu/lava-10742243/0 for stage 0
180 11:43:27.809612 - 0_v4l2-compliance-mtk-vcodec-enc
181 11:43:27.809803 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
182 11:43:27.809970 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 11:43:27.821360 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:43:27.821553 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 11:43:27.821705 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:43:27.821849 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
187 11:43:27.822008 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 11:43:31.408804 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:04) [common]
189 11:43:31.409202 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
190 11:43:31.409342 extracting modules file /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10742243/extract-overlay-ramdisk-wxfmhuj2/ramdisk
191 11:43:32.362762 end: 1.5.4 extract-modules (duration 00:00:01) [common]
192 11:43:32.363050 start: 1.5.5 apply-overlay-tftp (timeout 00:09:52) [common]
193 11:43:32.363225 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742243/compress-overlay-gmqi1ue3/overlay-1.5.2.4.tar.gz to ramdisk
194 11:43:32.363375 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10742243/compress-overlay-gmqi1ue3/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10742243/extract-overlay-ramdisk-wxfmhuj2/ramdisk
195 11:43:32.373906 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:43:32.374072 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
197 11:43:32.374199 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:43:32.374326 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
199 11:43:32.374446 Building ramdisk /var/lib/lava/dispatcher/tmp/10742243/extract-overlay-ramdisk-wxfmhuj2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10742243/extract-overlay-ramdisk-wxfmhuj2/ramdisk
200 11:43:37.915966 >> 230342 blocks
201 11:43:41.861260 rename /var/lib/lava/dispatcher/tmp/10742243/extract-overlay-ramdisk-wxfmhuj2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/ramdisk/ramdisk.cpio.gz
202 11:43:41.861694 end: 1.5.7 compress-ramdisk (duration 00:00:09) [common]
203 11:43:41.861812 start: 1.5.8 prepare-kernel (timeout 00:09:42) [common]
204 11:43:41.861912 start: 1.5.8.1 prepare-fit (timeout 00:09:42) [common]
205 11:43:41.862015 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/kernel/Image'
206 11:43:59.170530 Returned 0 in 17 seconds
207 11:43:59.271463 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/kernel/image.itb
208 11:44:00.369301 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:44:00.369687 output: Created: Thu Jun 15 12:44:00 2023
210 11:44:00.369773 output: Image 0 (kernel-1)
211 11:44:00.369842 output: Description:
212 11:44:00.369908 output: Created: Thu Jun 15 12:44:00 2023
213 11:44:00.369973 output: Type: Kernel Image
214 11:44:00.370034 output: Compression: lzma compressed
215 11:44:00.370096 output: Data Size: 10443363 Bytes = 10198.60 KiB = 9.96 MiB
216 11:44:00.370157 output: Architecture: AArch64
217 11:44:00.370215 output: OS: Linux
218 11:44:00.370274 output: Load Address: 0x00000000
219 11:44:00.370332 output: Entry Point: 0x00000000
220 11:44:00.370389 output: Hash algo: crc32
221 11:44:00.370443 output: Hash value: cd22d0e5
222 11:44:00.370496 output: Image 1 (fdt-1)
223 11:44:00.370551 output: Description: mt8192-asurada-spherion-r0
224 11:44:00.370605 output: Created: Thu Jun 15 12:44:00 2023
225 11:44:00.370660 output: Type: Flat Device Tree
226 11:44:00.370714 output: Compression: uncompressed
227 11:44:00.370768 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:44:00.370822 output: Architecture: AArch64
229 11:44:00.370876 output: Hash algo: crc32
230 11:44:00.370929 output: Hash value: 1df858fa
231 11:44:00.370983 output: Image 2 (ramdisk-1)
232 11:44:00.371037 output: Description: unavailable
233 11:44:00.371092 output: Created: Thu Jun 15 12:44:00 2023
234 11:44:00.371146 output: Type: RAMDisk Image
235 11:44:00.371199 output: Compression: Unknown Compression
236 11:44:00.371252 output: Data Size: 40137926 Bytes = 39197.19 KiB = 38.28 MiB
237 11:44:00.371306 output: Architecture: AArch64
238 11:44:00.371359 output: OS: Linux
239 11:44:00.371412 output: Load Address: unavailable
240 11:44:00.371466 output: Entry Point: unavailable
241 11:44:00.371520 output: Hash algo: crc32
242 11:44:00.371573 output: Hash value: 8b85e188
243 11:44:00.371626 output: Default Configuration: 'conf-1'
244 11:44:00.371679 output: Configuration 0 (conf-1)
245 11:44:00.371732 output: Description: mt8192-asurada-spherion-r0
246 11:44:00.371786 output: Kernel: kernel-1
247 11:44:00.371839 output: Init Ramdisk: ramdisk-1
248 11:44:00.371892 output: FDT: fdt-1
249 11:44:00.371945 output: Loadables: kernel-1
250 11:44:00.371998 output:
251 11:44:00.372186 end: 1.5.8.1 prepare-fit (duration 00:00:19) [common]
252 11:44:00.372287 end: 1.5.8 prepare-kernel (duration 00:00:19) [common]
253 11:44:00.372398 end: 1.5 prepare-tftp-overlay (duration 00:00:34) [common]
254 11:44:00.372495 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:24) [common]
255 11:44:00.372573 No LXC device requested
256 11:44:00.372654 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:44:00.372745 start: 1.7 deploy-device-env (timeout 00:09:24) [common]
258 11:44:00.372835 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:44:00.372965 Checking files for TFTP limit of 4294967296 bytes.
260 11:44:00.373513 end: 1 tftp-deploy (duration 00:00:36) [common]
261 11:44:00.373623 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:44:00.373715 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:44:00.373835 substitutions:
264 11:44:00.373904 - {DTB}: 10742243/tftp-deploy-me9zrnxy/dtb/mt8192-asurada-spherion-r0.dtb
265 11:44:00.373970 - {INITRD}: 10742243/tftp-deploy-me9zrnxy/ramdisk/ramdisk.cpio.gz
266 11:44:00.374028 - {KERNEL}: 10742243/tftp-deploy-me9zrnxy/kernel/Image
267 11:44:00.374087 - {LAVA_MAC}: None
268 11:44:00.374146 - {PRESEED_CONFIG}: None
269 11:44:00.374203 - {PRESEED_LOCAL}: None
270 11:44:00.374257 - {RAMDISK}: 10742243/tftp-deploy-me9zrnxy/ramdisk/ramdisk.cpio.gz
271 11:44:00.374312 - {ROOT_PART}: None
272 11:44:00.374367 - {ROOT}: None
273 11:44:00.374422 - {SERVER_IP}: 192.168.201.1
274 11:44:00.374476 - {TEE}: None
275 11:44:00.374530 Parsed boot commands:
276 11:44:00.374585 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:44:00.374758 Parsed boot commands: tftpboot 192.168.201.1 10742243/tftp-deploy-me9zrnxy/kernel/image.itb 10742243/tftp-deploy-me9zrnxy/kernel/cmdline
278 11:44:00.374848 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:44:00.374934 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:44:00.375029 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:44:00.375117 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:44:00.375189 Not connected, no need to disconnect.
283 11:44:00.375264 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:44:00.375342 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:44:00.375409 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
286 11:44:00.378400 Setting prompt string to ['lava-test: # ']
287 11:44:00.378767 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:44:00.378877 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:44:00.378974 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:44:00.379069 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:44:00.379269 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 11:44:05.511131 >> Command sent successfully.
293 11:44:05.513407 Returned 0 in 5 seconds
294 11:44:05.613799 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:44:05.614631 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:44:05.614788 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:44:05.614923 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:44:05.615029 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:44:05.615165 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:44:05.615551 [Enter `^Ec?' for help]
302 11:44:05.787138
303 11:44:05.787287
304 11:44:05.787358 F0: 102B 0000
305 11:44:05.787423
306 11:44:05.787485 F3: 1001 0000 [0200]
307 11:44:05.787545
308 11:44:05.791015 F3: 1001 0000
309 11:44:05.791103
310 11:44:05.791170 F7: 102D 0000
311 11:44:05.791234
312 11:44:05.791294 F1: 0000 0000
313 11:44:05.794405
314 11:44:05.794491 V0: 0000 0000 [0001]
315 11:44:05.794558
316 11:44:05.794619 00: 0007 8000
317 11:44:05.794682
318 11:44:05.797947 01: 0000 0000
319 11:44:05.798034
320 11:44:05.798102 BP: 0C00 0209 [0000]
321 11:44:05.798166
322 11:44:05.801554 G0: 1182 0000
323 11:44:05.801646
324 11:44:05.801715 EC: 0000 0021 [4000]
325 11:44:05.801805
326 11:44:05.805301 S7: 0000 0000 [0000]
327 11:44:05.805394
328 11:44:05.805463 CC: 0000 0000 [0001]
329 11:44:05.805524
330 11:44:05.808803 T0: 0000 0040 [010F]
331 11:44:05.808896
332 11:44:05.808967 Jump to BL
333 11:44:05.809067
334 11:44:05.833412
335 11:44:05.833555
336 11:44:05.833624
337 11:44:05.840421 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:44:05.843936 ARM64: Exception handlers installed.
339 11:44:05.847979 ARM64: Testing exception
340 11:44:05.851396 ARM64: Done test exception
341 11:44:05.858458 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:44:05.869192 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:44:05.876199 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:44:05.885875 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:44:05.892881 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:44:05.899245 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:44:05.910980 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:44:05.917720 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:44:05.936751 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:44:05.939897 WDT: Last reset was cold boot
351 11:44:05.943225 SPI1(PAD0) initialized at 2873684 Hz
352 11:44:05.946618 SPI5(PAD0) initialized at 992727 Hz
353 11:44:05.949975 VBOOT: Loading verstage.
354 11:44:05.956687 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:44:05.960028 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:44:05.963215 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:44:05.966743 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:44:05.974147 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:44:05.980495 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:44:05.991564 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 11:44:05.991660
362 11:44:05.991727
363 11:44:06.001521 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:44:06.005076 ARM64: Exception handlers installed.
365 11:44:06.008274 ARM64: Testing exception
366 11:44:06.008350 ARM64: Done test exception
367 11:44:06.014876 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:44:06.018094 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:44:06.032691 Probing TPM: . done!
370 11:44:06.032820 TPM ready after 0 ms
371 11:44:06.039392 Connected to device vid:did:rid of 1ae0:0028:00
372 11:44:06.046476 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 11:44:06.049751 Initialized TPM device CR50 revision 0
374 11:44:06.116565 tlcl_send_startup: Startup return code is 0
375 11:44:06.116706 TPM: setup succeeded
376 11:44:06.127969 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:44:06.136597 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:44:06.147244 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:44:06.156154 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:44:06.159843 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:44:06.166762 in-header: 03 07 00 00 08 00 00 00
382 11:44:06.170408 in-data: aa e4 47 04 13 02 00 00
383 11:44:06.174140 Chrome EC: UHEPI supported
384 11:44:06.180863 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:44:06.184652 in-header: 03 ad 00 00 08 00 00 00
386 11:44:06.188248 in-data: 00 20 20 08 00 00 00 00
387 11:44:06.188408 Phase 1
388 11:44:06.191885 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:44:06.199064 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:44:06.202714 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:44:06.206702 Recovery requested (1009000e)
392 11:44:06.216618 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:44:06.222963 tlcl_extend: response is 0
394 11:44:06.232501 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:44:06.238520 tlcl_extend: response is 0
396 11:44:06.245871 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:44:06.266217 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:44:06.272851 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:44:06.273013
400 11:44:06.273105
401 11:44:06.283071 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:44:06.286413 ARM64: Exception handlers installed.
403 11:44:06.286500 ARM64: Testing exception
404 11:44:06.289972 ARM64: Done test exception
405 11:44:06.311463 pmic_efuse_setting: Set efuses in 11 msecs
406 11:44:06.314773 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:44:06.321911 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:44:06.325014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:44:06.331572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:44:06.334980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:44:06.338339 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:44:06.345322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:44:06.348996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:44:06.356366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:44:06.360195 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:44:06.363487 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:44:06.367505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:44:06.374098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:44:06.377190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:44:06.384264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:44:06.390553 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:44:06.394256 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:44:06.401933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:44:06.405234 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:44:06.412189 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:44:06.418882 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:44:06.422314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:44:06.428637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:44:06.435540 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:44:06.438462 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:44:06.445201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:44:06.451915 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:44:06.455127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:44:06.461913 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:44:06.465021 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:44:06.468535 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:44:06.475284 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:44:06.478442 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:44:06.485499 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:44:06.488758 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:44:06.495709 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:44:06.498977 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:44:06.505425 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:44:06.508457 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:44:06.515253 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:44:06.518849 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:44:06.522077 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:44:06.528783 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:44:06.532184 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:44:06.535960 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:44:06.539471 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:44:06.546357 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:44:06.549446 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:44:06.552933 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:44:06.559388 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:44:06.562897 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:44:06.566138 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:44:06.572783 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:44:06.582918 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:44:06.586087 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:44:06.596047 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:44:06.602282 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:44:06.609414 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:44:06.612462 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:44:06.616254 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:44:06.624189 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2
467 11:44:06.631084 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:44:06.634209 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:44:06.640315 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:44:06.648402 [RTC]rtc_get_frequency_meter,154: input=15, output=771
471 11:44:06.658449 [RTC]rtc_get_frequency_meter,154: input=23, output=958
472 11:44:06.667816 [RTC]rtc_get_frequency_meter,154: input=19, output=863
473 11:44:06.677153 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 11:44:06.686450 [RTC]rtc_get_frequency_meter,154: input=16, output=794
475 11:44:06.689734 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 11:44:06.696616 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 11:44:06.699966 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 11:44:06.703621 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 11:44:06.706935 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 11:44:06.709988 ADC[4]: Raw value=902507 ID=7
481 11:44:06.713665 ADC[3]: Raw value=213179 ID=1
482 11:44:06.713817 RAM Code: 0x71
483 11:44:06.720528 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 11:44:06.724159 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 11:44:06.731790 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 11:44:06.738955 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 11:44:06.742576 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 11:44:06.746485 in-header: 03 07 00 00 08 00 00 00
489 11:44:06.750117 in-data: aa e4 47 04 13 02 00 00
490 11:44:06.753754 Chrome EC: UHEPI supported
491 11:44:06.757326 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 11:44:06.761344 in-header: 03 ed 00 00 08 00 00 00
493 11:44:06.765403 in-data: 80 20 60 08 00 00 00 00
494 11:44:06.768329 MRC: failed to locate region type 0.
495 11:44:06.775148 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 11:44:06.778159 DRAM-K: Running full calibration
497 11:44:06.784570 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 11:44:06.788152 header.status = 0x0
499 11:44:06.788347 header.version = 0x6 (expected: 0x6)
500 11:44:06.791634 header.size = 0xd00 (expected: 0xd00)
501 11:44:06.794835 header.flags = 0x0
502 11:44:06.801580 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 11:44:06.818931 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
504 11:44:06.825613 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 11:44:06.829210 dram_init: ddr_geometry: 2
506 11:44:06.829329 [EMI] MDL number = 2
507 11:44:06.833041 [EMI] Get MDL freq = 0
508 11:44:06.833164 dram_init: ddr_type: 0
509 11:44:06.836722 is_discrete_lpddr4: 1
510 11:44:06.839962 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 11:44:06.840114
512 11:44:06.840253
513 11:44:06.843777 [Bian_co] ETT version 0.0.0.1
514 11:44:06.847198 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 11:44:06.847945
516 11:44:06.850712 dramc_set_vcore_voltage set vcore to 650000
517 11:44:06.854050 Read voltage for 800, 4
518 11:44:06.854486 Vio18 = 0
519 11:44:06.857048 Vcore = 650000
520 11:44:06.857472 Vdram = 0
521 11:44:06.857811 Vddq = 0
522 11:44:06.858155 Vmddr = 0
523 11:44:06.860609 dram_init: config_dvfs: 1
524 11:44:06.867225 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 11:44:06.870838 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 11:44:06.873960 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
527 11:44:06.880661 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
528 11:44:06.883719 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 11:44:06.886837 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 11:44:06.887050 MEM_TYPE=3, freq_sel=18
531 11:44:06.890308 sv_algorithm_assistance_LP4_1600
532 11:44:06.897157 ============ PULL DRAM RESETB DOWN ============
533 11:44:06.900719 ========== PULL DRAM RESETB DOWN end =========
534 11:44:06.903679 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 11:44:06.907461 ===================================
536 11:44:06.910601 LPDDR4 DRAM CONFIGURATION
537 11:44:06.913736 ===================================
538 11:44:06.917301 EX_ROW_EN[0] = 0x0
539 11:44:06.917437 EX_ROW_EN[1] = 0x0
540 11:44:06.920351 LP4Y_EN = 0x0
541 11:44:06.920488 WORK_FSP = 0x0
542 11:44:06.924227 WL = 0x2
543 11:44:06.924364 RL = 0x2
544 11:44:06.927030 BL = 0x2
545 11:44:06.927164 RPST = 0x0
546 11:44:06.930515 RD_PRE = 0x0
547 11:44:06.930649 WR_PRE = 0x1
548 11:44:06.933574 WR_PST = 0x0
549 11:44:06.933708 DBI_WR = 0x0
550 11:44:06.937143 DBI_RD = 0x0
551 11:44:06.937279 OTF = 0x1
552 11:44:06.940071 ===================================
553 11:44:06.943535 ===================================
554 11:44:06.946790 ANA top config
555 11:44:06.950071 ===================================
556 11:44:06.953799 DLL_ASYNC_EN = 0
557 11:44:06.953935 ALL_SLAVE_EN = 1
558 11:44:06.956821 NEW_RANK_MODE = 1
559 11:44:06.960135 DLL_IDLE_MODE = 1
560 11:44:06.963331 LP45_APHY_COMB_EN = 1
561 11:44:06.963470 TX_ODT_DIS = 1
562 11:44:06.966800 NEW_8X_MODE = 1
563 11:44:06.970227 ===================================
564 11:44:06.973464 ===================================
565 11:44:06.977202 data_rate = 1600
566 11:44:06.980411 CKR = 1
567 11:44:06.983971 DQ_P2S_RATIO = 8
568 11:44:06.987311 ===================================
569 11:44:06.990533 CA_P2S_RATIO = 8
570 11:44:06.990976 DQ_CA_OPEN = 0
571 11:44:06.993677 DQ_SEMI_OPEN = 0
572 11:44:06.997068 CA_SEMI_OPEN = 0
573 11:44:07.000294 CA_FULL_RATE = 0
574 11:44:07.003465 DQ_CKDIV4_EN = 1
575 11:44:07.007032 CA_CKDIV4_EN = 1
576 11:44:07.007267 CA_PREDIV_EN = 0
577 11:44:07.010156 PH8_DLY = 0
578 11:44:07.013728 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 11:44:07.016867 DQ_AAMCK_DIV = 4
580 11:44:07.020037 CA_AAMCK_DIV = 4
581 11:44:07.020195 CA_ADMCK_DIV = 4
582 11:44:07.023232 DQ_TRACK_CA_EN = 0
583 11:44:07.026843 CA_PICK = 800
584 11:44:07.029897 CA_MCKIO = 800
585 11:44:07.033363 MCKIO_SEMI = 0
586 11:44:07.036469 PLL_FREQ = 3068
587 11:44:07.039990 DQ_UI_PI_RATIO = 32
588 11:44:07.042985 CA_UI_PI_RATIO = 0
589 11:44:07.046527 ===================================
590 11:44:07.046688 ===================================
591 11:44:07.049872 memory_type:LPDDR4
592 11:44:07.053513 GP_NUM : 10
593 11:44:07.053675 SRAM_EN : 1
594 11:44:07.056635 MD32_EN : 0
595 11:44:07.060283 ===================================
596 11:44:07.063640 [ANA_INIT] >>>>>>>>>>>>>>
597 11:44:07.066890 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 11:44:07.070482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:44:07.070650 ===================================
600 11:44:07.074224 data_rate = 1600,PCW = 0X7600
601 11:44:07.077240 ===================================
602 11:44:07.081007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 11:44:07.088015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 11:44:07.091926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 11:44:07.095531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 11:44:07.102113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 11:44:07.105290 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 11:44:07.105437 [ANA_INIT] flow start
609 11:44:07.108846 [ANA_INIT] PLL >>>>>>>>
610 11:44:07.111961 [ANA_INIT] PLL <<<<<<<<
611 11:44:07.112104 [ANA_INIT] MIDPI >>>>>>>>
612 11:44:07.115635 [ANA_INIT] MIDPI <<<<<<<<
613 11:44:07.118577 [ANA_INIT] DLL >>>>>>>>
614 11:44:07.118708 [ANA_INIT] flow end
615 11:44:07.121920 ============ LP4 DIFF to SE enter ============
616 11:44:07.128648 ============ LP4 DIFF to SE exit ============
617 11:44:07.128774 [ANA_INIT] <<<<<<<<<<<<<
618 11:44:07.132276 [Flow] Enable top DCM control >>>>>
619 11:44:07.135298 [Flow] Enable top DCM control <<<<<
620 11:44:07.138300 Enable DLL master slave shuffle
621 11:44:07.144910 ==============================================================
622 11:44:07.148277 Gating Mode config
623 11:44:07.152000 ==============================================================
624 11:44:07.155609 Config description:
625 11:44:07.166307 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 11:44:07.169305 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 11:44:07.176592 SELPH_MODE 0: By rank 1: By Phase
628 11:44:07.180392 ==============================================================
629 11:44:07.183495 GAT_TRACK_EN = 1
630 11:44:07.187111 RX_GATING_MODE = 2
631 11:44:07.190651 RX_GATING_TRACK_MODE = 2
632 11:44:07.194316 SELPH_MODE = 1
633 11:44:07.197840 PICG_EARLY_EN = 1
634 11:44:07.197974 VALID_LAT_VALUE = 1
635 11:44:07.204784 ==============================================================
636 11:44:07.208432 Enter into Gating configuration >>>>
637 11:44:07.212001 Exit from Gating configuration <<<<
638 11:44:07.215264 Enter into DVFS_PRE_config >>>>>
639 11:44:07.226036 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 11:44:07.229806 Exit from DVFS_PRE_config <<<<<
641 11:44:07.233598 Enter into PICG configuration >>>>
642 11:44:07.233806 Exit from PICG configuration <<<<
643 11:44:07.236647 [RX_INPUT] configuration >>>>>
644 11:44:07.240665 [RX_INPUT] configuration <<<<<
645 11:44:07.244211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 11:44:07.251414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 11:44:07.258696 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 11:44:07.262747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 11:44:07.269633 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 11:44:07.276892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 11:44:07.280597 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 11:44:07.284312 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 11:44:07.288015 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 11:44:07.291777 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 11:44:07.295464 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 11:44:07.299137 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 11:44:07.302904 ===================================
658 11:44:07.306586 LPDDR4 DRAM CONFIGURATION
659 11:44:07.310552 ===================================
660 11:44:07.310646 EX_ROW_EN[0] = 0x0
661 11:44:07.314207 EX_ROW_EN[1] = 0x0
662 11:44:07.314300 LP4Y_EN = 0x0
663 11:44:07.317769 WORK_FSP = 0x0
664 11:44:07.317859 WL = 0x2
665 11:44:07.321211 RL = 0x2
666 11:44:07.321312 BL = 0x2
667 11:44:07.324897 RPST = 0x0
668 11:44:07.325044 RD_PRE = 0x0
669 11:44:07.328963 WR_PRE = 0x1
670 11:44:07.329154 WR_PST = 0x0
671 11:44:07.332351 DBI_WR = 0x0
672 11:44:07.332433 DBI_RD = 0x0
673 11:44:07.332500 OTF = 0x1
674 11:44:07.335665 ===================================
675 11:44:07.343050 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 11:44:07.346594 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 11:44:07.350374 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 11:44:07.354394 ===================================
679 11:44:07.354501 LPDDR4 DRAM CONFIGURATION
680 11:44:07.357848 ===================================
681 11:44:07.361351 EX_ROW_EN[0] = 0x10
682 11:44:07.361434 EX_ROW_EN[1] = 0x0
683 11:44:07.365366 LP4Y_EN = 0x0
684 11:44:07.365477 WORK_FSP = 0x0
685 11:44:07.369150 WL = 0x2
686 11:44:07.369235 RL = 0x2
687 11:44:07.372745 BL = 0x2
688 11:44:07.372868 RPST = 0x0
689 11:44:07.376291 RD_PRE = 0x0
690 11:44:07.376382 WR_PRE = 0x1
691 11:44:07.380139 WR_PST = 0x0
692 11:44:07.380283 DBI_WR = 0x0
693 11:44:07.383315 DBI_RD = 0x0
694 11:44:07.383401 OTF = 0x1
695 11:44:07.387209 ===================================
696 11:44:07.394467 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 11:44:07.398305 nWR fixed to 40
698 11:44:07.398403 [ModeRegInit_LP4] CH0 RK0
699 11:44:07.401580 [ModeRegInit_LP4] CH0 RK1
700 11:44:07.404946 [ModeRegInit_LP4] CH1 RK0
701 11:44:07.405057 [ModeRegInit_LP4] CH1 RK1
702 11:44:07.408632 match AC timing 13
703 11:44:07.412344 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 11:44:07.415814 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 11:44:07.419917 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 11:44:07.426721 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 11:44:07.430263 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 11:44:07.430435 [EMI DOE] emi_dcm 0
709 11:44:07.438016 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 11:44:07.438107 ==
711 11:44:07.441517 Dram Type= 6, Freq= 0, CH_0, rank 0
712 11:44:07.445210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 11:44:07.445357 ==
714 11:44:07.448748 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 11:44:07.455977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 11:44:07.464497 [CA 0] Center 37 (7~68) winsize 62
717 11:44:07.467882 [CA 1] Center 38 (7~69) winsize 63
718 11:44:07.471581 [CA 2] Center 35 (5~66) winsize 62
719 11:44:07.474901 [CA 3] Center 35 (4~66) winsize 63
720 11:44:07.477940 [CA 4] Center 34 (4~65) winsize 62
721 11:44:07.481444 [CA 5] Center 33 (3~64) winsize 62
722 11:44:07.481533
723 11:44:07.484893 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 11:44:07.484990
725 11:44:07.488044 [CATrainingPosCal] consider 1 rank data
726 11:44:07.491451 u2DelayCellTimex100 = 270/100 ps
727 11:44:07.494687 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
728 11:44:07.497885 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 11:44:07.501519 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 11:44:07.507837 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
731 11:44:07.511053 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 11:44:07.514448 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 11:44:07.514532
734 11:44:07.517801 CA PerBit enable=1, Macro0, CA PI delay=33
735 11:44:07.517877
736 11:44:07.521081 [CBTSetCACLKResult] CA Dly = 33
737 11:44:07.521156 CS Dly: 6 (0~37)
738 11:44:07.521218 ==
739 11:44:07.524660 Dram Type= 6, Freq= 0, CH_0, rank 1
740 11:44:07.531459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 11:44:07.531541 ==
742 11:44:07.534649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 11:44:07.541359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 11:44:07.550658 [CA 0] Center 38 (7~69) winsize 63
745 11:44:07.554266 [CA 1] Center 38 (7~69) winsize 63
746 11:44:07.557343 [CA 2] Center 36 (6~67) winsize 62
747 11:44:07.560904 [CA 3] Center 35 (5~66) winsize 62
748 11:44:07.564000 [CA 4] Center 35 (4~66) winsize 63
749 11:44:07.567554 [CA 5] Center 34 (4~65) winsize 62
750 11:44:07.567629
751 11:44:07.571014 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 11:44:07.571122
753 11:44:07.574099 [CATrainingPosCal] consider 2 rank data
754 11:44:07.577530 u2DelayCellTimex100 = 270/100 ps
755 11:44:07.580612 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
756 11:44:07.587092 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 11:44:07.590769 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 11:44:07.593843 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 11:44:07.597189 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 11:44:07.600491 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 11:44:07.600576
762 11:44:07.603990 CA PerBit enable=1, Macro0, CA PI delay=34
763 11:44:07.604080
764 11:44:07.607255 [CBTSetCACLKResult] CA Dly = 34
765 11:44:07.610425 CS Dly: 6 (0~38)
766 11:44:07.610514
767 11:44:07.613601 ----->DramcWriteLeveling(PI) begin...
768 11:44:07.613688 ==
769 11:44:07.616783 Dram Type= 6, Freq= 0, CH_0, rank 0
770 11:44:07.620192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 11:44:07.620279 ==
772 11:44:07.623627 Write leveling (Byte 0): 32 => 32
773 11:44:07.626826 Write leveling (Byte 1): 30 => 30
774 11:44:07.630497 DramcWriteLeveling(PI) end<-----
775 11:44:07.630605
776 11:44:07.630689 ==
777 11:44:07.633683 Dram Type= 6, Freq= 0, CH_0, rank 0
778 11:44:07.636848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 11:44:07.636936 ==
780 11:44:07.640309 [Gating] SW mode calibration
781 11:44:07.647319 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 11:44:07.651092 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 11:44:07.658101 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
784 11:44:07.661464 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 11:44:07.664558 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 11:44:07.671799 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:44:07.675488 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:44:07.678701 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:44:07.681957 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:44:07.688415 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:44:07.692255 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:44:07.695157 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:44:07.702038 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:44:07.705270 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:44:07.708535 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:44:07.715253 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:44:07.718572 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:44:07.721734 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:44:07.728561 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 11:44:07.731681 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
801 11:44:07.735194 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:44:07.741893 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:44:07.744967 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:44:07.748560 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:44:07.751805 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:44:07.758557 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:44:07.761607 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:44:07.764701 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
809 11:44:07.771446 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 11:44:07.774929 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
811 11:44:07.778100 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:44:07.784804 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:44:07.788267 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 11:44:07.791389 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:44:07.798353 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 11:44:07.801473 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
817 11:44:07.805159 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
818 11:44:07.811905 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:44:07.815184 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:44:07.818268 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:44:07.824860 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:44:07.828323 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:44:07.831608 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:44:07.838356 0 11 4 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
825 11:44:07.841551 0 11 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
826 11:44:07.844951 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
827 11:44:07.851858 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:44:07.855019 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:44:07.858287 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 11:44:07.861668 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:44:07.868149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
832 11:44:07.871449 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 11:44:07.874932 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 11:44:07.881506 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:44:07.884732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:44:07.888174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:44:07.894786 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:44:07.898092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:44:07.901482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:44:07.907910 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:44:07.911493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:44:07.914532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:44:07.921698 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:44:07.924869 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:44:07.928021 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:44:07.934624 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:44:07.938062 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:44:07.941177 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 11:44:07.944937 Total UI for P1: 0, mck2ui 16
850 11:44:07.948132 best dqsien dly found for B0: ( 0, 14, 2)
851 11:44:07.954924 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 11:44:07.955025 Total UI for P1: 0, mck2ui 16
853 11:44:07.957990 best dqsien dly found for B1: ( 0, 14, 4)
854 11:44:07.964533 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
855 11:44:07.967580 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
856 11:44:07.967708
857 11:44:07.971226 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
858 11:44:07.974291 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 11:44:07.977946 [Gating] SW calibration Done
860 11:44:07.978036 ==
861 11:44:07.980959 Dram Type= 6, Freq= 0, CH_0, rank 0
862 11:44:07.984409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 11:44:07.984495 ==
864 11:44:07.987842 RX Vref Scan: 0
865 11:44:07.987926
866 11:44:07.987993 RX Vref 0 -> 0, step: 1
867 11:44:07.988055
868 11:44:07.990898 RX Delay -130 -> 252, step: 16
869 11:44:07.994592 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
870 11:44:08.000912 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 11:44:08.004277 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 11:44:08.007778 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 11:44:08.010829 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
874 11:44:08.014443 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 11:44:08.021167 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 11:44:08.024246 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 11:44:08.027465 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 11:44:08.031014 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 11:44:08.034123 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 11:44:08.040935 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 11:44:08.044481 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
882 11:44:08.047700 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 11:44:08.050917 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 11:44:08.054602 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
885 11:44:08.057701 ==
886 11:44:08.060820 Dram Type= 6, Freq= 0, CH_0, rank 0
887 11:44:08.064019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 11:44:08.064106 ==
889 11:44:08.064175 DQS Delay:
890 11:44:08.067491 DQS0 = 0, DQS1 = 0
891 11:44:08.067583 DQM Delay:
892 11:44:08.070995 DQM0 = 91, DQM1 = 80
893 11:44:08.071082 DQ Delay:
894 11:44:08.073969 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
895 11:44:08.077874 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
896 11:44:08.080974 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 11:44:08.084134 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
898 11:44:08.084222
899 11:44:08.084290
900 11:44:08.084354 ==
901 11:44:08.087586 Dram Type= 6, Freq= 0, CH_0, rank 0
902 11:44:08.090951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 11:44:08.091039 ==
904 11:44:08.091107
905 11:44:08.091171
906 11:44:08.094326 TX Vref Scan disable
907 11:44:08.097450 == TX Byte 0 ==
908 11:44:08.100957 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
909 11:44:08.104217 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
910 11:44:08.107286 == TX Byte 1 ==
911 11:44:08.110583 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
912 11:44:08.114242 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
913 11:44:08.114331 ==
914 11:44:08.117378 Dram Type= 6, Freq= 0, CH_0, rank 0
915 11:44:08.124008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 11:44:08.124101 ==
917 11:44:08.135581 TX Vref=22, minBit 6, minWin=27, winSum=438
918 11:44:08.138751 TX Vref=24, minBit 10, minWin=27, winSum=444
919 11:44:08.142157 TX Vref=26, minBit 11, minWin=26, winSum=446
920 11:44:08.145655 TX Vref=28, minBit 8, minWin=27, winSum=449
921 11:44:08.148882 TX Vref=30, minBit 5, minWin=28, winSum=454
922 11:44:08.155603 TX Vref=32, minBit 5, minWin=28, winSum=457
923 11:44:08.159151 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 32
924 11:44:08.159242
925 11:44:08.162209 Final TX Range 1 Vref 32
926 11:44:08.162295
927 11:44:08.162363 ==
928 11:44:08.165354 Dram Type= 6, Freq= 0, CH_0, rank 0
929 11:44:08.169034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 11:44:08.172123 ==
931 11:44:08.172212
932 11:44:08.172278
933 11:44:08.172360 TX Vref Scan disable
934 11:44:08.175769 == TX Byte 0 ==
935 11:44:08.178951 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
936 11:44:08.185540 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
937 11:44:08.185628 == TX Byte 1 ==
938 11:44:08.189235 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
939 11:44:08.195451 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
940 11:44:08.195537
941 11:44:08.195604 [DATLAT]
942 11:44:08.195685 Freq=800, CH0 RK0
943 11:44:08.195749
944 11:44:08.198827 DATLAT Default: 0xa
945 11:44:08.198914 0, 0xFFFF, sum = 0
946 11:44:08.202155 1, 0xFFFF, sum = 0
947 11:44:08.202231 2, 0xFFFF, sum = 0
948 11:44:08.205355 3, 0xFFFF, sum = 0
949 11:44:08.208849 4, 0xFFFF, sum = 0
950 11:44:08.208924 5, 0xFFFF, sum = 0
951 11:44:08.212367 6, 0xFFFF, sum = 0
952 11:44:08.212441 7, 0xFFFF, sum = 0
953 11:44:08.215359 8, 0xFFFF, sum = 0
954 11:44:08.215433 9, 0x0, sum = 1
955 11:44:08.215495 10, 0x0, sum = 2
956 11:44:08.218965 11, 0x0, sum = 3
957 11:44:08.219043 12, 0x0, sum = 4
958 11:44:08.221958 best_step = 10
959 11:44:08.222032
960 11:44:08.222093 ==
961 11:44:08.225473 Dram Type= 6, Freq= 0, CH_0, rank 0
962 11:44:08.228645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 11:44:08.228721 ==
964 11:44:08.232250 RX Vref Scan: 1
965 11:44:08.232322
966 11:44:08.235380 Set Vref Range= 32 -> 127
967 11:44:08.235453
968 11:44:08.235515 RX Vref 32 -> 127, step: 1
969 11:44:08.235593
970 11:44:08.238658 RX Delay -95 -> 252, step: 8
971 11:44:08.238730
972 11:44:08.242233 Set Vref, RX VrefLevel [Byte0]: 32
973 11:44:08.245488 [Byte1]: 32
974 11:44:08.245561
975 11:44:08.248848 Set Vref, RX VrefLevel [Byte0]: 33
976 11:44:08.251900 [Byte1]: 33
977 11:44:08.255994
978 11:44:08.256092 Set Vref, RX VrefLevel [Byte0]: 34
979 11:44:08.259263 [Byte1]: 34
980 11:44:08.263829
981 11:44:08.263905 Set Vref, RX VrefLevel [Byte0]: 35
982 11:44:08.266945 [Byte1]: 35
983 11:44:08.271059
984 11:44:08.271162 Set Vref, RX VrefLevel [Byte0]: 36
985 11:44:08.274671 [Byte1]: 36
986 11:44:08.278691
987 11:44:08.278767 Set Vref, RX VrefLevel [Byte0]: 37
988 11:44:08.282335 [Byte1]: 37
989 11:44:08.286685
990 11:44:08.286763 Set Vref, RX VrefLevel [Byte0]: 38
991 11:44:08.290275 [Byte1]: 38
992 11:44:08.293979
993 11:44:08.294060 Set Vref, RX VrefLevel [Byte0]: 39
994 11:44:08.297293 [Byte1]: 39
995 11:44:08.301499
996 11:44:08.301577 Set Vref, RX VrefLevel [Byte0]: 40
997 11:44:08.304781 [Byte1]: 40
998 11:44:08.309042
999 11:44:08.312190 Set Vref, RX VrefLevel [Byte0]: 41
1000 11:44:08.312297 [Byte1]: 41
1001 11:44:08.317132
1002 11:44:08.317212 Set Vref, RX VrefLevel [Byte0]: 42
1003 11:44:08.320132 [Byte1]: 42
1004 11:44:08.324767
1005 11:44:08.324847 Set Vref, RX VrefLevel [Byte0]: 43
1006 11:44:08.327885 [Byte1]: 43
1007 11:44:08.332180
1008 11:44:08.332262 Set Vref, RX VrefLevel [Byte0]: 44
1009 11:44:08.335353 [Byte1]: 44
1010 11:44:08.340270
1011 11:44:08.340357 Set Vref, RX VrefLevel [Byte0]: 45
1012 11:44:08.343398 [Byte1]: 45
1013 11:44:08.347457
1014 11:44:08.347574 Set Vref, RX VrefLevel [Byte0]: 46
1015 11:44:08.350472 [Byte1]: 46
1016 11:44:08.354790
1017 11:44:08.354893 Set Vref, RX VrefLevel [Byte0]: 47
1018 11:44:08.358195 [Byte1]: 47
1019 11:44:08.362268
1020 11:44:08.362367 Set Vref, RX VrefLevel [Byte0]: 48
1021 11:44:08.365477 [Byte1]: 48
1022 11:44:08.369990
1023 11:44:08.370092 Set Vref, RX VrefLevel [Byte0]: 49
1024 11:44:08.373492 [Byte1]: 49
1025 11:44:08.377456
1026 11:44:08.377547 Set Vref, RX VrefLevel [Byte0]: 50
1027 11:44:08.380650 [Byte1]: 50
1028 11:44:08.385080
1029 11:44:08.385181 Set Vref, RX VrefLevel [Byte0]: 51
1030 11:44:08.388537 [Byte1]: 51
1031 11:44:08.392419
1032 11:44:08.392510 Set Vref, RX VrefLevel [Byte0]: 52
1033 11:44:08.396123 [Byte1]: 52
1034 11:44:08.400168
1035 11:44:08.400267 Set Vref, RX VrefLevel [Byte0]: 53
1036 11:44:08.403529 [Byte1]: 53
1037 11:44:08.407632
1038 11:44:08.407706 Set Vref, RX VrefLevel [Byte0]: 54
1039 11:44:08.411095 [Byte1]: 54
1040 11:44:08.415649
1041 11:44:08.415743 Set Vref, RX VrefLevel [Byte0]: 55
1042 11:44:08.418853 [Byte1]: 55
1043 11:44:08.423074
1044 11:44:08.426629 Set Vref, RX VrefLevel [Byte0]: 56
1045 11:44:08.426705 [Byte1]: 56
1046 11:44:08.430695
1047 11:44:08.430813 Set Vref, RX VrefLevel [Byte0]: 57
1048 11:44:08.434147 [Byte1]: 57
1049 11:44:08.438559
1050 11:44:08.438643 Set Vref, RX VrefLevel [Byte0]: 58
1051 11:44:08.441649 [Byte1]: 58
1052 11:44:08.445678
1053 11:44:08.445761 Set Vref, RX VrefLevel [Byte0]: 59
1054 11:44:08.449397 [Byte1]: 59
1055 11:44:08.453758
1056 11:44:08.453886 Set Vref, RX VrefLevel [Byte0]: 60
1057 11:44:08.456959 [Byte1]: 60
1058 11:44:08.461336
1059 11:44:08.461425 Set Vref, RX VrefLevel [Byte0]: 61
1060 11:44:08.464441 [Byte1]: 61
1061 11:44:08.468560
1062 11:44:08.468643 Set Vref, RX VrefLevel [Byte0]: 62
1063 11:44:08.472215 [Byte1]: 62
1064 11:44:08.476169
1065 11:44:08.476252 Set Vref, RX VrefLevel [Byte0]: 63
1066 11:44:08.479817 [Byte1]: 63
1067 11:44:08.484107
1068 11:44:08.484189 Set Vref, RX VrefLevel [Byte0]: 64
1069 11:44:08.486974 [Byte1]: 64
1070 11:44:08.491823
1071 11:44:08.492243 Set Vref, RX VrefLevel [Byte0]: 65
1072 11:44:08.495296 [Byte1]: 65
1073 11:44:08.499269
1074 11:44:08.502513 Set Vref, RX VrefLevel [Byte0]: 66
1075 11:44:08.502934 [Byte1]: 66
1076 11:44:08.506903
1077 11:44:08.507322 Set Vref, RX VrefLevel [Byte0]: 67
1078 11:44:08.510140 [Byte1]: 67
1079 11:44:08.514718
1080 11:44:08.515143 Set Vref, RX VrefLevel [Byte0]: 68
1081 11:44:08.517869 [Byte1]: 68
1082 11:44:08.522344
1083 11:44:08.522765 Set Vref, RX VrefLevel [Byte0]: 69
1084 11:44:08.525467 [Byte1]: 69
1085 11:44:08.529814
1086 11:44:08.530271 Set Vref, RX VrefLevel [Byte0]: 70
1087 11:44:08.533258 [Byte1]: 70
1088 11:44:08.537635
1089 11:44:08.538093 Set Vref, RX VrefLevel [Byte0]: 71
1090 11:44:08.540793 [Byte1]: 71
1091 11:44:08.544829
1092 11:44:08.545282 Set Vref, RX VrefLevel [Byte0]: 72
1093 11:44:08.548414 [Byte1]: 72
1094 11:44:08.552392
1095 11:44:08.552806 Set Vref, RX VrefLevel [Byte0]: 73
1096 11:44:08.556053 [Byte1]: 73
1097 11:44:08.560278
1098 11:44:08.560692 Set Vref, RX VrefLevel [Byte0]: 74
1099 11:44:08.563679 [Byte1]: 74
1100 11:44:08.567632
1101 11:44:08.568049 Set Vref, RX VrefLevel [Byte0]: 75
1102 11:44:08.571219 [Byte1]: 75
1103 11:44:08.575200
1104 11:44:08.575661 Set Vref, RX VrefLevel [Byte0]: 76
1105 11:44:08.578672 [Byte1]: 76
1106 11:44:08.582611
1107 11:44:08.582910 Final RX Vref Byte 0 = 62 to rank0
1108 11:44:08.586254 Final RX Vref Byte 1 = 57 to rank0
1109 11:44:08.589366 Final RX Vref Byte 0 = 62 to rank1
1110 11:44:08.592720 Final RX Vref Byte 1 = 57 to rank1==
1111 11:44:08.595800 Dram Type= 6, Freq= 0, CH_0, rank 0
1112 11:44:08.602431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1113 11:44:08.602561 ==
1114 11:44:08.602693 DQS Delay:
1115 11:44:08.602822 DQS0 = 0, DQS1 = 0
1116 11:44:08.605987 DQM Delay:
1117 11:44:08.606128 DQM0 = 93, DQM1 = 82
1118 11:44:08.609119 DQ Delay:
1119 11:44:08.612493 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1120 11:44:08.616018 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1121 11:44:08.619550 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1122 11:44:08.622777 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1123 11:44:08.623217
1124 11:44:08.623663
1125 11:44:08.629483 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1126 11:44:08.633012 CH0 RK0: MR19=606, MR18=3B36
1127 11:44:08.639797 CH0_RK0: MR19=0x606, MR18=0x3B36, DQSOSC=394, MR23=63, INC=95, DEC=63
1128 11:44:08.640223
1129 11:44:08.643156 ----->DramcWriteLeveling(PI) begin...
1130 11:44:08.643587 ==
1131 11:44:08.646148 Dram Type= 6, Freq= 0, CH_0, rank 1
1132 11:44:08.649757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 11:44:08.650189 ==
1134 11:44:08.652937 Write leveling (Byte 0): 33 => 33
1135 11:44:08.656207 Write leveling (Byte 1): 28 => 28
1136 11:44:08.659584 DramcWriteLeveling(PI) end<-----
1137 11:44:08.660011
1138 11:44:08.660348 ==
1139 11:44:08.663065 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 11:44:08.666270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 11:44:08.666504 ==
1142 11:44:08.669577 [Gating] SW mode calibration
1143 11:44:08.675995 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1144 11:44:08.682526 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1145 11:44:08.685986 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1146 11:44:08.689248 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1147 11:44:08.696062 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 11:44:08.699185 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:44:08.702275 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:44:08.709148 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:44:08.712377 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:44:08.756536 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:44:08.756857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:44:08.756937 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:44:08.757036 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:44:08.757109 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:44:08.757170 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:44:08.757412 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:44:08.757474 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:44:08.757530 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:44:08.757597 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1162 11:44:08.769639 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1163 11:44:08.769906 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1164 11:44:08.772834 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:44:08.772948 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:44:08.779440 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:44:08.783192 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:44:08.786353 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:44:08.792734 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:44:08.796297 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (1 0)
1171 11:44:08.799483 0 9 8 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
1172 11:44:08.806127 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 11:44:08.809397 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 11:44:08.812917 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 11:44:08.819391 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 11:44:08.822930 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 11:44:08.826260 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 11:44:08.832677 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
1179 11:44:08.835890 0 10 8 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
1180 11:44:08.839334 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:44:08.845876 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:44:08.849240 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:44:08.852375 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:44:08.859146 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:44:08.862319 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:44:08.865935 0 11 4 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
1187 11:44:08.872207 0 11 8 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
1188 11:44:08.875697 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 11:44:08.879001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 11:44:08.882492 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 11:44:08.888897 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 11:44:08.892956 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 11:44:08.896203 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 11:44:08.899912 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1195 11:44:08.907233 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:44:08.910463 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:44:08.914057 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:44:08.920852 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:44:08.923813 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:44:08.927256 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:44:08.930629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:44:08.937605 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:44:08.940962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:44:08.944262 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:44:08.950658 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:44:08.954091 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:44:08.957679 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:44:08.964032 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:44:08.967160 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:44:08.970793 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1211 11:44:08.977058 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 11:44:08.980557 Total UI for P1: 0, mck2ui 16
1213 11:44:08.983926 best dqsien dly found for B0: ( 0, 14, 4)
1214 11:44:08.984013 Total UI for P1: 0, mck2ui 16
1215 11:44:08.990391 best dqsien dly found for B1: ( 0, 14, 4)
1216 11:44:08.993912 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1217 11:44:08.996904 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1218 11:44:08.997047
1219 11:44:09.000655 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1220 11:44:09.003914 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1221 11:44:09.007115 [Gating] SW calibration Done
1222 11:44:09.007200 ==
1223 11:44:09.010690 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 11:44:09.013761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 11:44:09.013842 ==
1226 11:44:09.016828 RX Vref Scan: 0
1227 11:44:09.016928
1228 11:44:09.017058 RX Vref 0 -> 0, step: 1
1229 11:44:09.017136
1230 11:44:09.020395 RX Delay -130 -> 252, step: 16
1231 11:44:09.023506 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1232 11:44:09.030607 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1233 11:44:09.033568 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1234 11:44:09.037073 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1235 11:44:09.040329 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1236 11:44:09.043449 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1237 11:44:09.050026 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1238 11:44:09.054003 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1239 11:44:09.056902 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1240 11:44:09.060324 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1241 11:44:09.063473 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1242 11:44:09.070423 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1243 11:44:09.073449 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
1244 11:44:09.076689 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1245 11:44:09.080246 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1246 11:44:09.086797 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1247 11:44:09.086891 ==
1248 11:44:09.090086 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 11:44:09.093363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1250 11:44:09.093473 ==
1251 11:44:09.093573 DQS Delay:
1252 11:44:09.096624 DQS0 = 0, DQS1 = 0
1253 11:44:09.096730 DQM Delay:
1254 11:44:09.099925 DQM0 = 89, DQM1 = 81
1255 11:44:09.100037 DQ Delay:
1256 11:44:09.103613 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1257 11:44:09.106848 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
1258 11:44:09.110092 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1259 11:44:09.113659 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1260 11:44:09.113745
1261 11:44:09.113832
1262 11:44:09.113912 ==
1263 11:44:09.116440 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 11:44:09.120001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 11:44:09.120106 ==
1266 11:44:09.120198
1267 11:44:09.120286
1268 11:44:09.123154 TX Vref Scan disable
1269 11:44:09.126534 == TX Byte 0 ==
1270 11:44:09.129749 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1271 11:44:09.133409 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1272 11:44:09.136404 == TX Byte 1 ==
1273 11:44:09.139882 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1274 11:44:09.142875 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1275 11:44:09.142989 ==
1276 11:44:09.146573 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 11:44:09.153033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 11:44:09.153123 ==
1279 11:44:09.165489 TX Vref=22, minBit 1, minWin=27, winSum=443
1280 11:44:09.169009 TX Vref=24, minBit 1, minWin=27, winSum=446
1281 11:44:09.172080 TX Vref=26, minBit 8, minWin=27, winSum=451
1282 11:44:09.175742 TX Vref=28, minBit 8, minWin=27, winSum=453
1283 11:44:09.178828 TX Vref=30, minBit 8, minWin=27, winSum=453
1284 11:44:09.182177 TX Vref=32, minBit 4, minWin=28, winSum=454
1285 11:44:09.188830 [TxChooseVref] Worse bit 4, Min win 28, Win sum 454, Final Vref 32
1286 11:44:09.188937
1287 11:44:09.192106 Final TX Range 1 Vref 32
1288 11:44:09.192204
1289 11:44:09.192295 ==
1290 11:44:09.195476 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 11:44:09.198961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 11:44:09.199064 ==
1293 11:44:09.199154
1294 11:44:09.201933
1295 11:44:09.202032 TX Vref Scan disable
1296 11:44:09.205542 == TX Byte 0 ==
1297 11:44:09.208674 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1298 11:44:09.212379 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1299 11:44:09.215662 == TX Byte 1 ==
1300 11:44:09.218908 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1301 11:44:09.225599 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1302 11:44:09.225709
1303 11:44:09.225805 [DATLAT]
1304 11:44:09.225902 Freq=800, CH0 RK1
1305 11:44:09.225991
1306 11:44:09.228739 DATLAT Default: 0xa
1307 11:44:09.228839 0, 0xFFFF, sum = 0
1308 11:44:09.232379 1, 0xFFFF, sum = 0
1309 11:44:09.232465 2, 0xFFFF, sum = 0
1310 11:44:09.235454 3, 0xFFFF, sum = 0
1311 11:44:09.238599 4, 0xFFFF, sum = 0
1312 11:44:09.238683 5, 0xFFFF, sum = 0
1313 11:44:09.241897 6, 0xFFFF, sum = 0
1314 11:44:09.241982 7, 0xFFFF, sum = 0
1315 11:44:09.245346 8, 0xFFFF, sum = 0
1316 11:44:09.245430 9, 0x0, sum = 1
1317 11:44:09.248742 10, 0x0, sum = 2
1318 11:44:09.248825 11, 0x0, sum = 3
1319 11:44:09.248890 12, 0x0, sum = 4
1320 11:44:09.252013 best_step = 10
1321 11:44:09.252096
1322 11:44:09.252160 ==
1323 11:44:09.255308 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 11:44:09.258719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 11:44:09.258802 ==
1326 11:44:09.262178 RX Vref Scan: 0
1327 11:44:09.262260
1328 11:44:09.262323 RX Vref 0 -> 0, step: 1
1329 11:44:09.262383
1330 11:44:09.265206 RX Delay -95 -> 252, step: 8
1331 11:44:09.272214 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1332 11:44:09.275717 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1333 11:44:09.279032 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1334 11:44:09.282004 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1335 11:44:09.285214 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1336 11:44:09.292073 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1337 11:44:09.295512 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1338 11:44:09.298941 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1339 11:44:09.302146 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1340 11:44:09.305352 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1341 11:44:09.312129 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1342 11:44:09.315302 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1343 11:44:09.318459 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1344 11:44:09.322221 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1345 11:44:09.328701 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1346 11:44:09.331786 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1347 11:44:09.331868 ==
1348 11:44:09.334966 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 11:44:09.338373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 11:44:09.338454 ==
1351 11:44:09.338519 DQS Delay:
1352 11:44:09.341865 DQS0 = 0, DQS1 = 0
1353 11:44:09.341937 DQM Delay:
1354 11:44:09.345403 DQM0 = 91, DQM1 = 81
1355 11:44:09.345484 DQ Delay:
1356 11:44:09.348443 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1357 11:44:09.351792 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1358 11:44:09.355160 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =80
1359 11:44:09.358444 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1360 11:44:09.358526
1361 11:44:09.358590
1362 11:44:09.368420 [DQSOSCAuto] RK1, (LSB)MR18= 0x411b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1363 11:44:09.368504 CH0 RK1: MR19=606, MR18=411B
1364 11:44:09.375174 CH0_RK1: MR19=0x606, MR18=0x411B, DQSOSC=393, MR23=63, INC=95, DEC=63
1365 11:44:09.378316 [RxdqsGatingPostProcess] freq 800
1366 11:44:09.385096 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1367 11:44:09.388273 Pre-setting of DQS Precalculation
1368 11:44:09.391807 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1369 11:44:09.391892 ==
1370 11:44:09.394925 Dram Type= 6, Freq= 0, CH_1, rank 0
1371 11:44:09.401745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 11:44:09.401836 ==
1373 11:44:09.404941 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1374 11:44:09.411571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1375 11:44:09.420515 [CA 0] Center 36 (6~67) winsize 62
1376 11:44:09.424116 [CA 1] Center 36 (6~67) winsize 62
1377 11:44:09.427234 [CA 2] Center 34 (4~65) winsize 62
1378 11:44:09.430400 [CA 3] Center 34 (4~65) winsize 62
1379 11:44:09.433786 [CA 4] Center 34 (4~65) winsize 62
1380 11:44:09.437557 [CA 5] Center 34 (3~65) winsize 63
1381 11:44:09.437633
1382 11:44:09.440606 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1383 11:44:09.440680
1384 11:44:09.443794 [CATrainingPosCal] consider 1 rank data
1385 11:44:09.447174 u2DelayCellTimex100 = 270/100 ps
1386 11:44:09.450598 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1387 11:44:09.453625 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1388 11:44:09.460332 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1389 11:44:09.464092 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1390 11:44:09.467031 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1391 11:44:09.470411 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1392 11:44:09.470491
1393 11:44:09.473589 CA PerBit enable=1, Macro0, CA PI delay=34
1394 11:44:09.473668
1395 11:44:09.477012 [CBTSetCACLKResult] CA Dly = 34
1396 11:44:09.477105 CS Dly: 4 (0~35)
1397 11:44:09.480783 ==
1398 11:44:09.480855 Dram Type= 6, Freq= 0, CH_1, rank 1
1399 11:44:09.486969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 11:44:09.487047 ==
1401 11:44:09.490138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 11:44:09.496998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 11:44:09.506955 [CA 0] Center 37 (7~67) winsize 61
1404 11:44:09.509841 [CA 1] Center 37 (6~68) winsize 63
1405 11:44:09.513450 [CA 2] Center 35 (4~66) winsize 63
1406 11:44:09.516784 [CA 3] Center 34 (4~65) winsize 62
1407 11:44:09.519957 [CA 4] Center 34 (4~65) winsize 62
1408 11:44:09.523085 [CA 5] Center 33 (3~64) winsize 62
1409 11:44:09.523202
1410 11:44:09.526718 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1411 11:44:09.526801
1412 11:44:09.529856 [CATrainingPosCal] consider 2 rank data
1413 11:44:09.533320 u2DelayCellTimex100 = 270/100 ps
1414 11:44:09.536931 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
1415 11:44:09.543070 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1416 11:44:09.546591 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 11:44:09.550045 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1418 11:44:09.553250 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1419 11:44:09.556769 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1420 11:44:09.556854
1421 11:44:09.559820 CA PerBit enable=1, Macro0, CA PI delay=33
1422 11:44:09.559905
1423 11:44:09.563605 [CBTSetCACLKResult] CA Dly = 33
1424 11:44:09.563692 CS Dly: 5 (0~38)
1425 11:44:09.563758
1426 11:44:09.567263 ----->DramcWriteLeveling(PI) begin...
1427 11:44:09.567348 ==
1428 11:44:09.570735 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 11:44:09.574782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 11:44:09.578192 ==
1431 11:44:09.578277 Write leveling (Byte 0): 26 => 26
1432 11:44:09.582146 Write leveling (Byte 1): 29 => 29
1433 11:44:09.585615 DramcWriteLeveling(PI) end<-----
1434 11:44:09.585700
1435 11:44:09.585766 ==
1436 11:44:09.589157 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 11:44:09.592855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 11:44:09.592967 ==
1439 11:44:09.596931 [Gating] SW mode calibration
1440 11:44:09.603575 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1441 11:44:09.606749 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1442 11:44:09.613560 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1443 11:44:09.616624 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1444 11:44:09.619894 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 11:44:09.626684 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:44:09.629894 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 11:44:09.632943 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:44:09.639973 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:44:09.643383 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:44:09.646553 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:44:09.653151 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:44:09.656263 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:44:09.659649 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:44:09.666268 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:44:09.669851 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:44:09.672996 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:44:09.679979 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:44:09.683113 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1459 11:44:09.686264 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1460 11:44:09.693004 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:44:09.696216 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:44:09.699903 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:44:09.706390 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:44:09.709569 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:44:09.712877 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:44:09.719902 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:44:09.722998 0 9 4 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
1468 11:44:09.726181 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1469 11:44:09.732514 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 11:44:09.736035 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 11:44:09.739309 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 11:44:09.742870 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 11:44:09.749210 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 11:44:09.752665 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1475 11:44:09.755707 0 10 4 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
1476 11:44:09.762592 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:44:09.765628 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:44:09.768965 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:44:09.775681 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:44:09.779123 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:44:09.782490 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:44:09.789112 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1483 11:44:09.792190 0 11 4 | B1->B0 | 2d2d 3b3b | 0 0 | (1 1) (1 1)
1484 11:44:09.795403 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 11:44:09.802264 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 11:44:09.805368 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 11:44:09.808761 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 11:44:09.815418 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 11:44:09.818660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 11:44:09.822355 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 11:44:09.828578 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1492 11:44:09.832163 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1493 11:44:09.835718 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:44:09.841887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:44:09.845447 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:44:09.848671 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:44:09.855351 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:44:09.858630 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:44:09.862279 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:44:09.868809 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:44:09.872229 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:44:09.875493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:44:09.881897 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:44:09.885317 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:44:09.888479 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:44:09.895499 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1507 11:44:09.898792 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1508 11:44:09.901970 Total UI for P1: 0, mck2ui 16
1509 11:44:09.905362 best dqsien dly found for B0: ( 0, 14, 0)
1510 11:44:09.908560 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1511 11:44:09.911989 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 11:44:09.915577 Total UI for P1: 0, mck2ui 16
1513 11:44:09.918618 best dqsien dly found for B1: ( 0, 14, 6)
1514 11:44:09.922082 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1515 11:44:09.928467 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1516 11:44:09.928554
1517 11:44:09.931748 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1518 11:44:09.935363 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1519 11:44:09.938473 [Gating] SW calibration Done
1520 11:44:09.938559 ==
1521 11:44:09.941604 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 11:44:09.945235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 11:44:09.945321 ==
1524 11:44:09.945407 RX Vref Scan: 0
1525 11:44:09.948355
1526 11:44:09.948440 RX Vref 0 -> 0, step: 1
1527 11:44:09.948524
1528 11:44:09.951575 RX Delay -130 -> 252, step: 16
1529 11:44:09.955204 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1530 11:44:09.958201 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1531 11:44:09.964888 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1532 11:44:09.968519 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1533 11:44:09.971884 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1534 11:44:09.975190 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1535 11:44:09.978459 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1536 11:44:09.984969 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1537 11:44:09.988282 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1538 11:44:09.991831 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1539 11:44:09.994899 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1540 11:44:09.997961 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1541 11:44:10.004938 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1542 11:44:10.008193 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1543 11:44:10.011512 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1544 11:44:10.014734 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1545 11:44:10.014825 ==
1546 11:44:10.017952 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 11:44:10.024991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 11:44:10.025107 ==
1549 11:44:10.025194 DQS Delay:
1550 11:44:10.028030 DQS0 = 0, DQS1 = 0
1551 11:44:10.028115 DQM Delay:
1552 11:44:10.028200 DQM0 = 93, DQM1 = 80
1553 11:44:10.031672 DQ Delay:
1554 11:44:10.034814 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1555 11:44:10.038066 DQ4 =93, DQ5 =101, DQ6 =109, DQ7 =85
1556 11:44:10.041238 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1557 11:44:10.044888 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1558 11:44:10.045036
1559 11:44:10.045126
1560 11:44:10.045208 ==
1561 11:44:10.048014 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 11:44:10.051335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 11:44:10.051421 ==
1564 11:44:10.051507
1565 11:44:10.051586
1566 11:44:10.054877 TX Vref Scan disable
1567 11:44:10.057877 == TX Byte 0 ==
1568 11:44:10.061537 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1569 11:44:10.064555 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1570 11:44:10.068233 == TX Byte 1 ==
1571 11:44:10.071405 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1572 11:44:10.074812 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1573 11:44:10.074915 ==
1574 11:44:10.078173 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 11:44:10.081540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 11:44:10.081640 ==
1577 11:44:10.095837 TX Vref=22, minBit 8, minWin=27, winSum=447
1578 11:44:10.099033 TX Vref=24, minBit 8, minWin=27, winSum=452
1579 11:44:10.102128 TX Vref=26, minBit 13, minWin=27, winSum=453
1580 11:44:10.105898 TX Vref=28, minBit 15, minWin=27, winSum=457
1581 11:44:10.109034 TX Vref=30, minBit 15, minWin=27, winSum=459
1582 11:44:10.115910 TX Vref=32, minBit 9, minWin=27, winSum=458
1583 11:44:10.119014 [TxChooseVref] Worse bit 15, Min win 27, Win sum 459, Final Vref 30
1584 11:44:10.119114
1585 11:44:10.122282 Final TX Range 1 Vref 30
1586 11:44:10.122382
1587 11:44:10.122472 ==
1588 11:44:10.125443 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 11:44:10.128967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 11:44:10.132055 ==
1591 11:44:10.132173
1592 11:44:10.132246
1593 11:44:10.132308 TX Vref Scan disable
1594 11:44:10.136091 == TX Byte 0 ==
1595 11:44:10.139120 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1596 11:44:10.142951 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1597 11:44:10.146600 == TX Byte 1 ==
1598 11:44:10.149952 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1599 11:44:10.153350 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1600 11:44:10.153451
1601 11:44:10.156544 [DATLAT]
1602 11:44:10.156630 Freq=800, CH1 RK0
1603 11:44:10.156697
1604 11:44:10.160089 DATLAT Default: 0xa
1605 11:44:10.160174 0, 0xFFFF, sum = 0
1606 11:44:10.163193 1, 0xFFFF, sum = 0
1607 11:44:10.163279 2, 0xFFFF, sum = 0
1608 11:44:10.166779 3, 0xFFFF, sum = 0
1609 11:44:10.166865 4, 0xFFFF, sum = 0
1610 11:44:10.170039 5, 0xFFFF, sum = 0
1611 11:44:10.170124 6, 0xFFFF, sum = 0
1612 11:44:10.173200 7, 0xFFFF, sum = 0
1613 11:44:10.173285 8, 0xFFFF, sum = 0
1614 11:44:10.176755 9, 0x0, sum = 1
1615 11:44:10.176840 10, 0x0, sum = 2
1616 11:44:10.179890 11, 0x0, sum = 3
1617 11:44:10.179975 12, 0x0, sum = 4
1618 11:44:10.183309 best_step = 10
1619 11:44:10.183392
1620 11:44:10.183458 ==
1621 11:44:10.186758 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 11:44:10.190045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 11:44:10.190131 ==
1624 11:44:10.193115 RX Vref Scan: 1
1625 11:44:10.193199
1626 11:44:10.193266 Set Vref Range= 32 -> 127
1627 11:44:10.193328
1628 11:44:10.196396 RX Vref 32 -> 127, step: 1
1629 11:44:10.196481
1630 11:44:10.199660 RX Delay -95 -> 252, step: 8
1631 11:44:10.199745
1632 11:44:10.203495 Set Vref, RX VrefLevel [Byte0]: 32
1633 11:44:10.206640 [Byte1]: 32
1634 11:44:10.206725
1635 11:44:10.209726 Set Vref, RX VrefLevel [Byte0]: 33
1636 11:44:10.213457 [Byte1]: 33
1637 11:44:10.216381
1638 11:44:10.216464 Set Vref, RX VrefLevel [Byte0]: 34
1639 11:44:10.219731 [Byte1]: 34
1640 11:44:10.223834
1641 11:44:10.223918 Set Vref, RX VrefLevel [Byte0]: 35
1642 11:44:10.227452 [Byte1]: 35
1643 11:44:10.231411
1644 11:44:10.231495 Set Vref, RX VrefLevel [Byte0]: 36
1645 11:44:10.234911 [Byte1]: 36
1646 11:44:10.238932
1647 11:44:10.239015 Set Vref, RX VrefLevel [Byte0]: 37
1648 11:44:10.242424 [Byte1]: 37
1649 11:44:10.246947
1650 11:44:10.247032 Set Vref, RX VrefLevel [Byte0]: 38
1651 11:44:10.249951 [Byte1]: 38
1652 11:44:10.254453
1653 11:44:10.254538 Set Vref, RX VrefLevel [Byte0]: 39
1654 11:44:10.257722 [Byte1]: 39
1655 11:44:10.261855
1656 11:44:10.261990 Set Vref, RX VrefLevel [Byte0]: 40
1657 11:44:10.265278 [Byte1]: 40
1658 11:44:10.269483
1659 11:44:10.269616 Set Vref, RX VrefLevel [Byte0]: 41
1660 11:44:10.272644 [Byte1]: 41
1661 11:44:10.277179
1662 11:44:10.277310 Set Vref, RX VrefLevel [Byte0]: 42
1663 11:44:10.280400 [Byte1]: 42
1664 11:44:10.284970
1665 11:44:10.285138 Set Vref, RX VrefLevel [Byte0]: 43
1666 11:44:10.288038 [Byte1]: 43
1667 11:44:10.292165
1668 11:44:10.292296 Set Vref, RX VrefLevel [Byte0]: 44
1669 11:44:10.295699 [Byte1]: 44
1670 11:44:10.299757
1671 11:44:10.299894 Set Vref, RX VrefLevel [Byte0]: 45
1672 11:44:10.302962 [Byte1]: 45
1673 11:44:10.307502
1674 11:44:10.307640 Set Vref, RX VrefLevel [Byte0]: 46
1675 11:44:10.310646 [Byte1]: 46
1676 11:44:10.315010
1677 11:44:10.315145 Set Vref, RX VrefLevel [Byte0]: 47
1678 11:44:10.318571 [Byte1]: 47
1679 11:44:10.322517
1680 11:44:10.322649 Set Vref, RX VrefLevel [Byte0]: 48
1681 11:44:10.326253 [Byte1]: 48
1682 11:44:10.330114
1683 11:44:10.330244 Set Vref, RX VrefLevel [Byte0]: 49
1684 11:44:10.333393 [Byte1]: 49
1685 11:44:10.337752
1686 11:44:10.337886 Set Vref, RX VrefLevel [Byte0]: 50
1687 11:44:10.341225 [Byte1]: 50
1688 11:44:10.345646
1689 11:44:10.345779 Set Vref, RX VrefLevel [Byte0]: 51
1690 11:44:10.348955 [Byte1]: 51
1691 11:44:10.352901
1692 11:44:10.353018 Set Vref, RX VrefLevel [Byte0]: 52
1693 11:44:10.356294 [Byte1]: 52
1694 11:44:10.360653
1695 11:44:10.360752 Set Vref, RX VrefLevel [Byte0]: 53
1696 11:44:10.364245 [Byte1]: 53
1697 11:44:10.368382
1698 11:44:10.368504 Set Vref, RX VrefLevel [Byte0]: 54
1699 11:44:10.371419 [Byte1]: 54
1700 11:44:10.375960
1701 11:44:10.376106 Set Vref, RX VrefLevel [Byte0]: 55
1702 11:44:10.379027 [Byte1]: 55
1703 11:44:10.383522
1704 11:44:10.383652 Set Vref, RX VrefLevel [Byte0]: 56
1705 11:44:10.386606 [Byte1]: 56
1706 11:44:10.391219
1707 11:44:10.391343 Set Vref, RX VrefLevel [Byte0]: 57
1708 11:44:10.394397 [Byte1]: 57
1709 11:44:10.398464
1710 11:44:10.398637 Set Vref, RX VrefLevel [Byte0]: 58
1711 11:44:10.401910 [Byte1]: 58
1712 11:44:10.406384
1713 11:44:10.406576 Set Vref, RX VrefLevel [Byte0]: 59
1714 11:44:10.409714 [Byte1]: 59
1715 11:44:10.413837
1716 11:44:10.413997 Set Vref, RX VrefLevel [Byte0]: 60
1717 11:44:10.416909 [Byte1]: 60
1718 11:44:10.421194
1719 11:44:10.421336 Set Vref, RX VrefLevel [Byte0]: 61
1720 11:44:10.424867 [Byte1]: 61
1721 11:44:10.428818
1722 11:44:10.428955 Set Vref, RX VrefLevel [Byte0]: 62
1723 11:44:10.432283 [Byte1]: 62
1724 11:44:10.436556
1725 11:44:10.436789 Set Vref, RX VrefLevel [Byte0]: 63
1726 11:44:10.440141 [Byte1]: 63
1727 11:44:10.444249
1728 11:44:10.444385 Set Vref, RX VrefLevel [Byte0]: 64
1729 11:44:10.447407 [Byte1]: 64
1730 11:44:10.451860
1731 11:44:10.452016 Set Vref, RX VrefLevel [Byte0]: 65
1732 11:44:10.455112 [Byte1]: 65
1733 11:44:10.459616
1734 11:44:10.459798 Set Vref, RX VrefLevel [Byte0]: 66
1735 11:44:10.462776 [Byte1]: 66
1736 11:44:10.467131
1737 11:44:10.467291 Set Vref, RX VrefLevel [Byte0]: 67
1738 11:44:10.470152 [Byte1]: 67
1739 11:44:10.474527
1740 11:44:10.474659 Set Vref, RX VrefLevel [Byte0]: 68
1741 11:44:10.477852 [Byte1]: 68
1742 11:44:10.482212
1743 11:44:10.482344 Set Vref, RX VrefLevel [Byte0]: 69
1744 11:44:10.485529 [Byte1]: 69
1745 11:44:10.489633
1746 11:44:10.489767 Set Vref, RX VrefLevel [Byte0]: 70
1747 11:44:10.492952 [Byte1]: 70
1748 11:44:10.497439
1749 11:44:10.497574 Set Vref, RX VrefLevel [Byte0]: 71
1750 11:44:10.500954 [Byte1]: 71
1751 11:44:10.505109
1752 11:44:10.505246 Set Vref, RX VrefLevel [Byte0]: 72
1753 11:44:10.508442 [Byte1]: 72
1754 11:44:10.512496
1755 11:44:10.512631 Set Vref, RX VrefLevel [Byte0]: 73
1756 11:44:10.515971 [Byte1]: 73
1757 11:44:10.520318
1758 11:44:10.520451 Set Vref, RX VrefLevel [Byte0]: 74
1759 11:44:10.523526 [Byte1]: 74
1760 11:44:10.527885
1761 11:44:10.528021 Set Vref, RX VrefLevel [Byte0]: 75
1762 11:44:10.531443 [Byte1]: 75
1763 11:44:10.535286
1764 11:44:10.535419 Set Vref, RX VrefLevel [Byte0]: 76
1765 11:44:10.538945 [Byte1]: 76
1766 11:44:10.542896
1767 11:44:10.543027 Set Vref, RX VrefLevel [Byte0]: 77
1768 11:44:10.546242 [Byte1]: 77
1769 11:44:10.550704
1770 11:44:10.550841 Final RX Vref Byte 0 = 51 to rank0
1771 11:44:10.553903 Final RX Vref Byte 1 = 63 to rank0
1772 11:44:10.557212 Final RX Vref Byte 0 = 51 to rank1
1773 11:44:10.560630 Final RX Vref Byte 1 = 63 to rank1==
1774 11:44:10.563905 Dram Type= 6, Freq= 0, CH_1, rank 0
1775 11:44:10.570404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1776 11:44:10.570605 ==
1777 11:44:10.570740 DQS Delay:
1778 11:44:10.570859 DQS0 = 0, DQS1 = 0
1779 11:44:10.573942 DQM Delay:
1780 11:44:10.574087 DQM0 = 93, DQM1 = 82
1781 11:44:10.577005 DQ Delay:
1782 11:44:10.580641 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1783 11:44:10.583866 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1784 11:44:10.587107 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1785 11:44:10.590629 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1786 11:44:10.590763
1787 11:44:10.590885
1788 11:44:10.596900 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1789 11:44:10.600249 CH1 RK0: MR19=606, MR18=2C49
1790 11:44:10.606930 CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64
1791 11:44:10.607051
1792 11:44:10.610256 ----->DramcWriteLeveling(PI) begin...
1793 11:44:10.610340 ==
1794 11:44:10.613847 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 11:44:10.616854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 11:44:10.616954 ==
1797 11:44:10.619863 Write leveling (Byte 0): 25 => 25
1798 11:44:10.623724 Write leveling (Byte 1): 31 => 31
1799 11:44:10.626663 DramcWriteLeveling(PI) end<-----
1800 11:44:10.626748
1801 11:44:10.626813 ==
1802 11:44:10.630248 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 11:44:10.633216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 11:44:10.633338 ==
1805 11:44:10.636815 [Gating] SW mode calibration
1806 11:44:10.643230 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1807 11:44:10.649782 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1808 11:44:10.653289 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1809 11:44:10.659961 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1810 11:44:10.663436 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:44:10.666484 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:44:10.673181 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:44:10.676404 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:44:10.679487 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:44:10.686234 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:44:10.689447 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:44:10.693051 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:44:10.699433 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:44:10.702715 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:44:10.706286 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:44:10.709363 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:44:10.716067 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:44:10.719545 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:44:10.722557 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:44:10.729544 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1826 11:44:10.732881 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1827 11:44:10.736077 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:44:10.742712 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:44:10.746192 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:44:10.749339 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:44:10.755991 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:44:10.759334 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:44:10.762795 0 9 4 | B1->B0 | 2424 2323 | 1 1 | (1 1) (1 1)
1834 11:44:10.769629 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1835 11:44:10.772836 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 11:44:10.775827 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 11:44:10.782607 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 11:44:10.786076 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 11:44:10.789269 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:44:10.796027 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:44:10.799174 0 10 4 | B1->B0 | 2e2e 3333 | 1 1 | (0 0) (1 0)
1842 11:44:10.802701 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:44:10.808968 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:44:10.812625 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:44:10.815676 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:44:10.822487 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:44:10.825801 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:44:10.828970 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:44:10.835644 0 11 4 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 0)
1850 11:44:10.839313 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 11:44:10.842379 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 11:44:10.849190 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 11:44:10.852289 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 11:44:10.855817 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 11:44:10.858901 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:44:10.865681 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:44:10.868855 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1858 11:44:10.872379 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:44:10.879011 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:44:10.882153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:44:10.885354 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:44:10.891911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:44:10.895540 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:44:10.898576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:44:10.905554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:44:10.908827 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:44:10.912127 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:44:10.918833 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:44:10.922003 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:44:10.925494 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:44:10.932156 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:44:10.935271 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:44:10.938574 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1874 11:44:10.941713 Total UI for P1: 0, mck2ui 16
1875 11:44:10.945229 best dqsien dly found for B1: ( 0, 14, 2)
1876 11:44:10.952005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1877 11:44:10.955312 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 11:44:10.958882 Total UI for P1: 0, mck2ui 16
1879 11:44:10.961857 best dqsien dly found for B0: ( 0, 14, 6)
1880 11:44:10.965702 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1881 11:44:10.968682 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1882 11:44:10.968767
1883 11:44:10.971899 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 11:44:10.975359 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1885 11:44:10.978598 [Gating] SW calibration Done
1886 11:44:10.978684 ==
1887 11:44:10.981669 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 11:44:10.985255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 11:44:10.985339 ==
1890 11:44:10.988806 RX Vref Scan: 0
1891 11:44:10.988892
1892 11:44:10.991888 RX Vref 0 -> 0, step: 1
1893 11:44:10.991971
1894 11:44:10.992036 RX Delay -130 -> 252, step: 16
1895 11:44:10.998485 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1896 11:44:11.001685 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1897 11:44:11.005381 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1898 11:44:11.008280 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1899 11:44:11.011933 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1900 11:44:11.018459 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1901 11:44:11.021612 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1902 11:44:11.024871 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1903 11:44:11.028460 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1904 11:44:11.031631 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1905 11:44:11.038221 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1906 11:44:11.041542 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1907 11:44:11.044629 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1908 11:44:11.048160 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1909 11:44:11.054672 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1910 11:44:11.058398 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1911 11:44:11.058486 ==
1912 11:44:11.061387 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 11:44:11.064921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 11:44:11.065048 ==
1915 11:44:11.067925 DQS Delay:
1916 11:44:11.068008 DQS0 = 0, DQS1 = 0
1917 11:44:11.068074 DQM Delay:
1918 11:44:11.071335 DQM0 = 89, DQM1 = 80
1919 11:44:11.071418 DQ Delay:
1920 11:44:11.075037 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1921 11:44:11.078263 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1922 11:44:11.081233 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1923 11:44:11.084711 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1924 11:44:11.084794
1925 11:44:11.084859
1926 11:44:11.084933 ==
1927 11:44:11.087882 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 11:44:11.094529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 11:44:11.094618 ==
1930 11:44:11.094684
1931 11:44:11.094744
1932 11:44:11.094803 TX Vref Scan disable
1933 11:44:11.098071 == TX Byte 0 ==
1934 11:44:11.101188 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1935 11:44:11.108058 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1936 11:44:11.108155 == TX Byte 1 ==
1937 11:44:11.111382 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1938 11:44:11.114941 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1939 11:44:11.118004 ==
1940 11:44:11.121236 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 11:44:11.124327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 11:44:11.124419 ==
1943 11:44:11.137679 TX Vref=22, minBit 8, minWin=27, winSum=447
1944 11:44:11.140773 TX Vref=24, minBit 8, minWin=27, winSum=449
1945 11:44:11.144341 TX Vref=26, minBit 13, minWin=27, winSum=454
1946 11:44:11.147763 TX Vref=28, minBit 1, minWin=28, winSum=457
1947 11:44:11.150745 TX Vref=30, minBit 8, minWin=28, winSum=460
1948 11:44:11.157567 TX Vref=32, minBit 9, minWin=27, winSum=456
1949 11:44:11.160792 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1950 11:44:11.160970
1951 11:44:11.164098 Final TX Range 1 Vref 30
1952 11:44:11.164179
1953 11:44:11.164243 ==
1954 11:44:11.167309 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 11:44:11.170590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 11:44:11.170673 ==
1957 11:44:11.173859
1958 11:44:11.173942
1959 11:44:11.174005 TX Vref Scan disable
1960 11:44:11.177509 == TX Byte 0 ==
1961 11:44:11.181167 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1962 11:44:11.184323 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1963 11:44:11.187347 == TX Byte 1 ==
1964 11:44:11.191071 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1965 11:44:11.194267 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1966 11:44:11.197684
1967 11:44:11.197761 [DATLAT]
1968 11:44:11.197826 Freq=800, CH1 RK1
1969 11:44:11.197886
1970 11:44:11.200914 DATLAT Default: 0xa
1971 11:44:11.201048 0, 0xFFFF, sum = 0
1972 11:44:11.204055 1, 0xFFFF, sum = 0
1973 11:44:11.204149 2, 0xFFFF, sum = 0
1974 11:44:11.207815 3, 0xFFFF, sum = 0
1975 11:44:11.207918 4, 0xFFFF, sum = 0
1976 11:44:11.210956 5, 0xFFFF, sum = 0
1977 11:44:11.214259 6, 0xFFFF, sum = 0
1978 11:44:11.214344 7, 0xFFFF, sum = 0
1979 11:44:11.217556 8, 0xFFFF, sum = 0
1980 11:44:11.217642 9, 0x0, sum = 1
1981 11:44:11.217719 10, 0x0, sum = 2
1982 11:44:11.220777 11, 0x0, sum = 3
1983 11:44:11.220888 12, 0x0, sum = 4
1984 11:44:11.224248 best_step = 10
1985 11:44:11.224328
1986 11:44:11.224392 ==
1987 11:44:11.227389 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 11:44:11.230668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 11:44:11.230754 ==
1990 11:44:11.234290 RX Vref Scan: 0
1991 11:44:11.234373
1992 11:44:11.234438 RX Vref 0 -> 0, step: 1
1993 11:44:11.234500
1994 11:44:11.237341 RX Delay -95 -> 252, step: 8
1995 11:44:11.244163 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
1996 11:44:11.247660 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1997 11:44:11.251087 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1998 11:44:11.254137 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1999 11:44:11.257505 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2000 11:44:11.264135 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2001 11:44:11.267390 iDelay=209, Bit 6, Center 100 (1 ~ 200) 200
2002 11:44:11.270754 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2003 11:44:11.273827 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2004 11:44:11.277283 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2005 11:44:11.284271 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2006 11:44:11.287445 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2007 11:44:11.290646 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2008 11:44:11.293885 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2009 11:44:11.297499 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2010 11:44:11.304143 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2011 11:44:11.304267 ==
2012 11:44:11.307293 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 11:44:11.310845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 11:44:11.310958 ==
2015 11:44:11.311053 DQS Delay:
2016 11:44:11.313929 DQS0 = 0, DQS1 = 0
2017 11:44:11.314018 DQM Delay:
2018 11:44:11.317147 DQM0 = 92, DQM1 = 84
2019 11:44:11.317242 DQ Delay:
2020 11:44:11.320334 DQ0 =92, DQ1 =88, DQ2 =80, DQ3 =88
2021 11:44:11.323522 DQ4 =96, DQ5 =104, DQ6 =100, DQ7 =88
2022 11:44:11.327014 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2023 11:44:11.330505 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92
2024 11:44:11.330610
2025 11:44:11.330702
2026 11:44:11.340408 [DQSOSCAuto] RK1, (LSB)MR18= 0x350a, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2027 11:44:11.340520 CH1 RK1: MR19=606, MR18=350A
2028 11:44:11.346973 CH1_RK1: MR19=0x606, MR18=0x350A, DQSOSC=396, MR23=63, INC=94, DEC=62
2029 11:44:11.350233 [RxdqsGatingPostProcess] freq 800
2030 11:44:11.356701 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 11:44:11.360329 Pre-setting of DQS Precalculation
2032 11:44:11.363394 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 11:44:11.369966 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 11:44:11.380463 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 11:44:11.380566
2036 11:44:11.380636
2037 11:44:11.380701 [Calibration Summary] 1600 Mbps
2038 11:44:11.383848 CH 0, Rank 0
2039 11:44:11.386517 SW Impedance : PASS
2040 11:44:11.386603 DUTY Scan : NO K
2041 11:44:11.390031 ZQ Calibration : PASS
2042 11:44:11.393227 Jitter Meter : NO K
2043 11:44:11.393369 CBT Training : PASS
2044 11:44:11.396642 Write leveling : PASS
2045 11:44:11.396718 RX DQS gating : PASS
2046 11:44:11.399883 RX DQ/DQS(RDDQC) : PASS
2047 11:44:11.403375 TX DQ/DQS : PASS
2048 11:44:11.403456 RX DATLAT : PASS
2049 11:44:11.406553 RX DQ/DQS(Engine): PASS
2050 11:44:11.409862 TX OE : NO K
2051 11:44:11.409937 All Pass.
2052 11:44:11.409998
2053 11:44:11.410057 CH 0, Rank 1
2054 11:44:11.413417 SW Impedance : PASS
2055 11:44:11.416453 DUTY Scan : NO K
2056 11:44:11.416521 ZQ Calibration : PASS
2057 11:44:11.419970 Jitter Meter : NO K
2058 11:44:11.423161 CBT Training : PASS
2059 11:44:11.423239 Write leveling : PASS
2060 11:44:11.426452 RX DQS gating : PASS
2061 11:44:11.429871 RX DQ/DQS(RDDQC) : PASS
2062 11:44:11.429974 TX DQ/DQS : PASS
2063 11:44:11.433109 RX DATLAT : PASS
2064 11:44:11.436755 RX DQ/DQS(Engine): PASS
2065 11:44:11.436837 TX OE : NO K
2066 11:44:11.436949 All Pass.
2067 11:44:11.439901
2068 11:44:11.439975 CH 1, Rank 0
2069 11:44:11.443060 SW Impedance : PASS
2070 11:44:11.443151 DUTY Scan : NO K
2071 11:44:11.446311 ZQ Calibration : PASS
2072 11:44:11.446387 Jitter Meter : NO K
2073 11:44:11.449916 CBT Training : PASS
2074 11:44:11.452706 Write leveling : PASS
2075 11:44:11.452781 RX DQS gating : PASS
2076 11:44:11.455864 RX DQ/DQS(RDDQC) : PASS
2077 11:44:11.459455 TX DQ/DQS : PASS
2078 11:44:11.459533 RX DATLAT : PASS
2079 11:44:11.462852 RX DQ/DQS(Engine): PASS
2080 11:44:11.466332 TX OE : NO K
2081 11:44:11.466428 All Pass.
2082 11:44:11.466520
2083 11:44:11.466607 CH 1, Rank 1
2084 11:44:11.469591 SW Impedance : PASS
2085 11:44:11.472942 DUTY Scan : NO K
2086 11:44:11.473071 ZQ Calibration : PASS
2087 11:44:11.476023 Jitter Meter : NO K
2088 11:44:11.479241 CBT Training : PASS
2089 11:44:11.479356 Write leveling : PASS
2090 11:44:11.482808 RX DQS gating : PASS
2091 11:44:11.486080 RX DQ/DQS(RDDQC) : PASS
2092 11:44:11.486204 TX DQ/DQS : PASS
2093 11:44:11.489180 RX DATLAT : PASS
2094 11:44:11.492627 RX DQ/DQS(Engine): PASS
2095 11:44:11.492710 TX OE : NO K
2096 11:44:11.496091 All Pass.
2097 11:44:11.496181
2098 11:44:11.496248 DramC Write-DBI off
2099 11:44:11.499151 PER_BANK_REFRESH: Hybrid Mode
2100 11:44:11.499239 TX_TRACKING: ON
2101 11:44:11.503051 [GetDramInforAfterCalByMRR] Vendor 6.
2102 11:44:11.506173 [GetDramInforAfterCalByMRR] Revision 606.
2103 11:44:11.513254 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 11:44:11.513719 MR0 0x3b3b
2105 11:44:11.514057 MR8 0x5151
2106 11:44:11.516324 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 11:44:11.516768
2108 11:44:11.519828 MR0 0x3b3b
2109 11:44:11.520265 MR8 0x5151
2110 11:44:11.523068 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 11:44:11.523538
2112 11:44:11.532967 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 11:44:11.536157 [FAST_K] Save calibration result to emmc
2114 11:44:11.539516 [FAST_K] Save calibration result to emmc
2115 11:44:11.542567 dram_init: config_dvfs: 1
2116 11:44:11.546173 dramc_set_vcore_voltage set vcore to 662500
2117 11:44:11.549307 Read voltage for 1200, 2
2118 11:44:11.549549 Vio18 = 0
2119 11:44:11.549782 Vcore = 662500
2120 11:44:11.552599 Vdram = 0
2121 11:44:11.552855 Vddq = 0
2122 11:44:11.553092 Vmddr = 0
2123 11:44:11.559292 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 11:44:11.562847 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 11:44:11.565983 MEM_TYPE=3, freq_sel=15
2126 11:44:11.569158 sv_algorithm_assistance_LP4_1600
2127 11:44:11.572593 ============ PULL DRAM RESETB DOWN ============
2128 11:44:11.575838 ========== PULL DRAM RESETB DOWN end =========
2129 11:44:11.582373 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 11:44:11.585659 ===================================
2131 11:44:11.585818 LPDDR4 DRAM CONFIGURATION
2132 11:44:11.589380 ===================================
2133 11:44:11.592942 EX_ROW_EN[0] = 0x0
2134 11:44:11.593413 EX_ROW_EN[1] = 0x0
2135 11:44:11.596088 LP4Y_EN = 0x0
2136 11:44:11.599584 WORK_FSP = 0x0
2137 11:44:11.600314 WL = 0x4
2138 11:44:11.603078 RL = 0x4
2139 11:44:11.603507 BL = 0x2
2140 11:44:11.606095 RPST = 0x0
2141 11:44:11.606473 RD_PRE = 0x0
2142 11:44:11.609468 WR_PRE = 0x1
2143 11:44:11.609872 WR_PST = 0x0
2144 11:44:11.612565 DBI_WR = 0x0
2145 11:44:11.612845 DBI_RD = 0x0
2146 11:44:11.616117 OTF = 0x1
2147 11:44:11.619218 ===================================
2148 11:44:11.622511 ===================================
2149 11:44:11.622676 ANA top config
2150 11:44:11.626103 ===================================
2151 11:44:11.629206 DLL_ASYNC_EN = 0
2152 11:44:11.632803 ALL_SLAVE_EN = 0
2153 11:44:11.632990 NEW_RANK_MODE = 1
2154 11:44:11.636003 DLL_IDLE_MODE = 1
2155 11:44:11.639569 LP45_APHY_COMB_EN = 1
2156 11:44:11.642630 TX_ODT_DIS = 1
2157 11:44:11.642773 NEW_8X_MODE = 1
2158 11:44:11.645759 ===================================
2159 11:44:11.649385 ===================================
2160 11:44:11.652837 data_rate = 2400
2161 11:44:11.655786 CKR = 1
2162 11:44:11.659413 DQ_P2S_RATIO = 8
2163 11:44:11.662472 ===================================
2164 11:44:11.666098 CA_P2S_RATIO = 8
2165 11:44:11.669266 DQ_CA_OPEN = 0
2166 11:44:11.669408 DQ_SEMI_OPEN = 0
2167 11:44:11.672593 CA_SEMI_OPEN = 0
2168 11:44:11.676222 CA_FULL_RATE = 0
2169 11:44:11.679043 DQ_CKDIV4_EN = 0
2170 11:44:11.682475 CA_CKDIV4_EN = 0
2171 11:44:11.685707 CA_PREDIV_EN = 0
2172 11:44:11.685865 PH8_DLY = 17
2173 11:44:11.689303 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 11:44:11.692616 DQ_AAMCK_DIV = 4
2175 11:44:11.695978 CA_AAMCK_DIV = 4
2176 11:44:11.699128 CA_ADMCK_DIV = 4
2177 11:44:11.702370 DQ_TRACK_CA_EN = 0
2178 11:44:11.706004 CA_PICK = 1200
2179 11:44:11.706158 CA_MCKIO = 1200
2180 11:44:11.709188 MCKIO_SEMI = 0
2181 11:44:11.712633 PLL_FREQ = 2366
2182 11:44:11.715765 DQ_UI_PI_RATIO = 32
2183 11:44:11.719489 CA_UI_PI_RATIO = 0
2184 11:44:11.722520 ===================================
2185 11:44:11.725620 ===================================
2186 11:44:11.729265 memory_type:LPDDR4
2187 11:44:11.729568 GP_NUM : 10
2188 11:44:11.732379 SRAM_EN : 1
2189 11:44:11.732554 MD32_EN : 0
2190 11:44:11.735957 ===================================
2191 11:44:11.739002 [ANA_INIT] >>>>>>>>>>>>>>
2192 11:44:11.742538 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 11:44:11.745813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 11:44:11.748961 ===================================
2195 11:44:11.752099 data_rate = 2400,PCW = 0X5b00
2196 11:44:11.755864 ===================================
2197 11:44:11.759070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 11:44:11.762218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 11:44:11.769246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 11:44:11.775900 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 11:44:11.779065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 11:44:11.782143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 11:44:11.782278 [ANA_INIT] flow start
2204 11:44:11.785633 [ANA_INIT] PLL >>>>>>>>
2205 11:44:11.788904 [ANA_INIT] PLL <<<<<<<<
2206 11:44:11.789073 [ANA_INIT] MIDPI >>>>>>>>
2207 11:44:11.792233 [ANA_INIT] MIDPI <<<<<<<<
2208 11:44:11.795426 [ANA_INIT] DLL >>>>>>>>
2209 11:44:11.795559 [ANA_INIT] DLL <<<<<<<<
2210 11:44:11.798963 [ANA_INIT] flow end
2211 11:44:11.802071 ============ LP4 DIFF to SE enter ============
2212 11:44:11.805147 ============ LP4 DIFF to SE exit ============
2213 11:44:11.808854 [ANA_INIT] <<<<<<<<<<<<<
2214 11:44:11.812032 [Flow] Enable top DCM control >>>>>
2215 11:44:11.815190 [Flow] Enable top DCM control <<<<<
2216 11:44:11.818932 Enable DLL master slave shuffle
2217 11:44:11.825112 ==============================================================
2218 11:44:11.825252 Gating Mode config
2219 11:44:11.832022 ==============================================================
2220 11:44:11.832162 Config description:
2221 11:44:11.841989 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 11:44:11.848863 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 11:44:11.855207 SELPH_MODE 0: By rank 1: By Phase
2224 11:44:11.858769 ==============================================================
2225 11:44:11.861920 GAT_TRACK_EN = 1
2226 11:44:11.865494 RX_GATING_MODE = 2
2227 11:44:11.868619 RX_GATING_TRACK_MODE = 2
2228 11:44:11.871773 SELPH_MODE = 1
2229 11:44:11.875268 PICG_EARLY_EN = 1
2230 11:44:11.878622 VALID_LAT_VALUE = 1
2231 11:44:11.884895 ==============================================================
2232 11:44:11.888612 Enter into Gating configuration >>>>
2233 11:44:11.891910 Exit from Gating configuration <<<<
2234 11:44:11.895385 Enter into DVFS_PRE_config >>>>>
2235 11:44:11.905255 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 11:44:11.908693 Exit from DVFS_PRE_config <<<<<
2237 11:44:11.911774 Enter into PICG configuration >>>>
2238 11:44:11.915348 Exit from PICG configuration <<<<
2239 11:44:11.918697 [RX_INPUT] configuration >>>>>
2240 11:44:11.918959 [RX_INPUT] configuration <<<<<
2241 11:44:11.925062 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 11:44:11.931650 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 11:44:11.934789 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 11:44:11.941522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 11:44:11.947933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 11:44:11.955087 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 11:44:11.958206 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 11:44:11.961434 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 11:44:11.968228 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 11:44:11.971377 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 11:44:11.975043 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 11:44:11.978226 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 11:44:11.981337 ===================================
2254 11:44:11.984872 LPDDR4 DRAM CONFIGURATION
2255 11:44:11.988128 ===================================
2256 11:44:11.991270 EX_ROW_EN[0] = 0x0
2257 11:44:11.991357 EX_ROW_EN[1] = 0x0
2258 11:44:11.994766 LP4Y_EN = 0x0
2259 11:44:11.994853 WORK_FSP = 0x0
2260 11:44:11.997951 WL = 0x4
2261 11:44:11.998037 RL = 0x4
2262 11:44:12.001151 BL = 0x2
2263 11:44:12.004798 RPST = 0x0
2264 11:44:12.004909 RD_PRE = 0x0
2265 11:44:12.007951 WR_PRE = 0x1
2266 11:44:12.008037 WR_PST = 0x0
2267 11:44:12.011060 DBI_WR = 0x0
2268 11:44:12.011162 DBI_RD = 0x0
2269 11:44:12.014650 OTF = 0x1
2270 11:44:12.017877 ===================================
2271 11:44:12.021125 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 11:44:12.024668 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 11:44:12.027677 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 11:44:12.030956 ===================================
2275 11:44:12.034702 LPDDR4 DRAM CONFIGURATION
2276 11:44:12.037952 ===================================
2277 11:44:12.041102 EX_ROW_EN[0] = 0x10
2278 11:44:12.041209 EX_ROW_EN[1] = 0x0
2279 11:44:12.044329 LP4Y_EN = 0x0
2280 11:44:12.044420 WORK_FSP = 0x0
2281 11:44:12.047740 WL = 0x4
2282 11:44:12.047823 RL = 0x4
2283 11:44:12.050854 BL = 0x2
2284 11:44:12.050937 RPST = 0x0
2285 11:44:12.054474 RD_PRE = 0x0
2286 11:44:12.054556 WR_PRE = 0x1
2287 11:44:12.057697 WR_PST = 0x0
2288 11:44:12.060703 DBI_WR = 0x0
2289 11:44:12.060798 DBI_RD = 0x0
2290 11:44:12.064337 OTF = 0x1
2291 11:44:12.067551 ===================================
2292 11:44:12.070737 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 11:44:12.074368 ==
2294 11:44:12.074488 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 11:44:12.080623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 11:44:12.080753 ==
2297 11:44:12.084260 [Duty_Offset_Calibration]
2298 11:44:12.084345 B0:2 B1:0 CA:1
2299 11:44:12.084429
2300 11:44:12.087486 [DutyScan_Calibration_Flow] k_type=0
2301 11:44:12.095781
2302 11:44:12.095872 ==CLK 0==
2303 11:44:12.099469 Final CLK duty delay cell = -4
2304 11:44:12.102715 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2305 11:44:12.105786 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2306 11:44:12.109131 [-4] AVG Duty = 4953%(X100)
2307 11:44:12.109245
2308 11:44:12.112586 CH0 CLK Duty spec in!! Max-Min= 156%
2309 11:44:12.115886 [DutyScan_Calibration_Flow] ====Done====
2310 11:44:12.115976
2311 11:44:12.118978 [DutyScan_Calibration_Flow] k_type=1
2312 11:44:12.134942
2313 11:44:12.135065 ==DQS 0 ==
2314 11:44:12.138127 Final DQS duty delay cell = 0
2315 11:44:12.141654 [0] MAX Duty = 5187%(X100), DQS PI = 30
2316 11:44:12.144737 [0] MIN Duty = 4938%(X100), DQS PI = 0
2317 11:44:12.144813 [0] AVG Duty = 5062%(X100)
2318 11:44:12.148171
2319 11:44:12.148248 ==DQS 1 ==
2320 11:44:12.151418 Final DQS duty delay cell = -4
2321 11:44:12.155076 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2322 11:44:12.158343 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2323 11:44:12.161351 [-4] AVG Duty = 5031%(X100)
2324 11:44:12.161423
2325 11:44:12.164923 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2326 11:44:12.165037
2327 11:44:12.168390 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2328 11:44:12.171525 [DutyScan_Calibration_Flow] ====Done====
2329 11:44:12.171596
2330 11:44:12.174637 [DutyScan_Calibration_Flow] k_type=3
2331 11:44:12.240964
2332 11:44:12.241143 ==DQM 0 ==
2333 11:44:12.241218 Final DQM duty delay cell = 0
2334 11:44:12.241281 [0] MAX Duty = 5062%(X100), DQS PI = 24
2335 11:44:12.241342 [0] MIN Duty = 4875%(X100), DQS PI = 0
2336 11:44:12.241401 [0] AVG Duty = 4968%(X100)
2337 11:44:12.241458
2338 11:44:12.241532 ==DQM 1 ==
2339 11:44:12.241590 Final DQM duty delay cell = -4
2340 11:44:12.241647 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2341 11:44:12.241702 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2342 11:44:12.241757 [-4] AVG Duty = 4906%(X100)
2343 11:44:12.241811
2344 11:44:12.241865 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2345 11:44:12.241919
2346 11:44:12.241973 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2347 11:44:12.242042 [DutyScan_Calibration_Flow] ====Done====
2348 11:44:12.242099
2349 11:44:12.242153 [DutyScan_Calibration_Flow] k_type=2
2350 11:44:12.247858
2351 11:44:12.247942 ==DQ 0 ==
2352 11:44:12.250937 Final DQ duty delay cell = -4
2353 11:44:12.253993 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2354 11:44:12.257532 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2355 11:44:12.260910 [-4] AVG Duty = 4953%(X100)
2356 11:44:12.261052
2357 11:44:12.261140 ==DQ 1 ==
2358 11:44:12.264405 Final DQ duty delay cell = 4
2359 11:44:12.267618 [4] MAX Duty = 5093%(X100), DQS PI = 4
2360 11:44:12.270905 [4] MIN Duty = 5031%(X100), DQS PI = 0
2361 11:44:12.270988 [4] AVG Duty = 5062%(X100)
2362 11:44:12.274132
2363 11:44:12.277654 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2364 11:44:12.277763
2365 11:44:12.281075 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2366 11:44:12.284297 [DutyScan_Calibration_Flow] ====Done====
2367 11:44:12.284379 ==
2368 11:44:12.287456 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 11:44:12.291058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 11:44:12.291167 ==
2371 11:44:12.294326 [Duty_Offset_Calibration]
2372 11:44:12.294408 B0:0 B1:-1 CA:2
2373 11:44:12.294473
2374 11:44:12.297393 [DutyScan_Calibration_Flow] k_type=0
2375 11:44:12.307862
2376 11:44:12.307944 ==CLK 0==
2377 11:44:12.311457 Final CLK duty delay cell = 0
2378 11:44:12.314448 [0] MAX Duty = 5156%(X100), DQS PI = 16
2379 11:44:12.317660 [0] MIN Duty = 4938%(X100), DQS PI = 44
2380 11:44:12.317743 [0] AVG Duty = 5047%(X100)
2381 11:44:12.321239
2382 11:44:12.324380 CH1 CLK Duty spec in!! Max-Min= 218%
2383 11:44:12.327830 [DutyScan_Calibration_Flow] ====Done====
2384 11:44:12.327912
2385 11:44:12.331035 [DutyScan_Calibration_Flow] k_type=1
2386 11:44:12.347328
2387 11:44:12.347411 ==DQS 0 ==
2388 11:44:12.350555 Final DQS duty delay cell = 0
2389 11:44:12.353863 [0] MAX Duty = 5093%(X100), DQS PI = 22
2390 11:44:12.357041 [0] MIN Duty = 4969%(X100), DQS PI = 0
2391 11:44:12.360682 [0] AVG Duty = 5031%(X100)
2392 11:44:12.360769
2393 11:44:12.360871 ==DQS 1 ==
2394 11:44:12.364063 Final DQS duty delay cell = 0
2395 11:44:12.367010 [0] MAX Duty = 5156%(X100), DQS PI = 0
2396 11:44:12.370607 [0] MIN Duty = 4813%(X100), DQS PI = 36
2397 11:44:12.373930 [0] AVG Duty = 4984%(X100)
2398 11:44:12.374016
2399 11:44:12.377008 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2400 11:44:12.377125
2401 11:44:12.380642 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2402 11:44:12.383876 [DutyScan_Calibration_Flow] ====Done====
2403 11:44:12.383978
2404 11:44:12.386854 [DutyScan_Calibration_Flow] k_type=3
2405 11:44:12.403656
2406 11:44:12.403739 ==DQM 0 ==
2407 11:44:12.407282 Final DQM duty delay cell = 4
2408 11:44:12.410272 [4] MAX Duty = 5093%(X100), DQS PI = 4
2409 11:44:12.413841 [4] MIN Duty = 4938%(X100), DQS PI = 48
2410 11:44:12.413925 [4] AVG Duty = 5015%(X100)
2411 11:44:12.417074
2412 11:44:12.417157 ==DQM 1 ==
2413 11:44:12.420545 Final DQM duty delay cell = -4
2414 11:44:12.423480 [-4] MAX Duty = 5031%(X100), DQS PI = 62
2415 11:44:12.427139 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2416 11:44:12.430299 [-4] AVG Duty = 4891%(X100)
2417 11:44:12.430382
2418 11:44:12.433950 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2419 11:44:12.434033
2420 11:44:12.437128 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2421 11:44:12.440526 [DutyScan_Calibration_Flow] ====Done====
2422 11:44:12.440609
2423 11:44:12.443491 [DutyScan_Calibration_Flow] k_type=2
2424 11:44:12.460664
2425 11:44:12.460749 ==DQ 0 ==
2426 11:44:12.463785 Final DQ duty delay cell = 0
2427 11:44:12.467192 [0] MAX Duty = 5062%(X100), DQS PI = 20
2428 11:44:12.470483 [0] MIN Duty = 4938%(X100), DQS PI = 0
2429 11:44:12.470560 [0] AVG Duty = 5000%(X100)
2430 11:44:12.473681
2431 11:44:12.473762 ==DQ 1 ==
2432 11:44:12.477251 Final DQ duty delay cell = 0
2433 11:44:12.480442 [0] MAX Duty = 5031%(X100), DQS PI = 2
2434 11:44:12.484014 [0] MIN Duty = 4813%(X100), DQS PI = 34
2435 11:44:12.484087 [0] AVG Duty = 4922%(X100)
2436 11:44:12.484149
2437 11:44:12.487179 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2438 11:44:12.490386
2439 11:44:12.493958 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2440 11:44:12.496868 [DutyScan_Calibration_Flow] ====Done====
2441 11:44:12.500557 nWR fixed to 30
2442 11:44:12.500632 [ModeRegInit_LP4] CH0 RK0
2443 11:44:12.504095 [ModeRegInit_LP4] CH0 RK1
2444 11:44:12.507150 [ModeRegInit_LP4] CH1 RK0
2445 11:44:12.507233 [ModeRegInit_LP4] CH1 RK1
2446 11:44:12.510418 match AC timing 7
2447 11:44:12.513868 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 11:44:12.517076 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 11:44:12.523629 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 11:44:12.527162 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 11:44:12.533726 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 11:44:12.533809 ==
2453 11:44:12.537272 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 11:44:12.540440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 11:44:12.540523 ==
2456 11:44:12.547001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 11:44:12.550425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2458 11:44:12.560414 [CA 0] Center 38 (7~69) winsize 63
2459 11:44:12.563782 [CA 1] Center 38 (7~69) winsize 63
2460 11:44:12.566777 [CA 2] Center 34 (4~65) winsize 62
2461 11:44:12.570498 [CA 3] Center 34 (4~65) winsize 62
2462 11:44:12.573496 [CA 4] Center 34 (4~64) winsize 61
2463 11:44:12.576693 [CA 5] Center 32 (2~63) winsize 62
2464 11:44:12.576818
2465 11:44:12.580520 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2466 11:44:12.580641
2467 11:44:12.583579 [CATrainingPosCal] consider 1 rank data
2468 11:44:12.586725 u2DelayCellTimex100 = 270/100 ps
2469 11:44:12.590182 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2470 11:44:12.597042 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2471 11:44:12.600313 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2472 11:44:12.603317 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2473 11:44:12.606714 CA4 delay=34 (4~64),Diff = 2 PI (9 cell)
2474 11:44:12.609920 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2475 11:44:12.610035
2476 11:44:12.613491 CA PerBit enable=1, Macro0, CA PI delay=32
2477 11:44:12.613583
2478 11:44:12.616768 [CBTSetCACLKResult] CA Dly = 32
2479 11:44:12.616873 CS Dly: 6 (0~37)
2480 11:44:12.619971 ==
2481 11:44:12.623517 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 11:44:12.626649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 11:44:12.626764 ==
2484 11:44:12.630026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 11:44:12.636509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2486 11:44:12.646080 [CA 0] Center 38 (8~69) winsize 62
2487 11:44:12.649163 [CA 1] Center 38 (8~69) winsize 62
2488 11:44:12.652719 [CA 2] Center 35 (5~66) winsize 62
2489 11:44:12.655916 [CA 3] Center 35 (5~66) winsize 62
2490 11:44:12.659383 [CA 4] Center 34 (3~65) winsize 63
2491 11:44:12.662494 [CA 5] Center 33 (3~64) winsize 62
2492 11:44:12.662602
2493 11:44:12.666148 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2494 11:44:12.666238
2495 11:44:12.669219 [CATrainingPosCal] consider 2 rank data
2496 11:44:12.672526 u2DelayCellTimex100 = 270/100 ps
2497 11:44:12.675687 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2498 11:44:12.679088 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2499 11:44:12.685691 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2500 11:44:12.689176 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2501 11:44:12.692780 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2502 11:44:12.695891 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2503 11:44:12.696045
2504 11:44:12.699418 CA PerBit enable=1, Macro0, CA PI delay=33
2505 11:44:12.699511
2506 11:44:12.702535 [CBTSetCACLKResult] CA Dly = 33
2507 11:44:12.702625 CS Dly: 7 (0~39)
2508 11:44:12.702695
2509 11:44:12.705726 ----->DramcWriteLeveling(PI) begin...
2510 11:44:12.709177 ==
2511 11:44:12.712277 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 11:44:12.715903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 11:44:12.715988 ==
2514 11:44:12.718982 Write leveling (Byte 0): 35 => 35
2515 11:44:12.722375 Write leveling (Byte 1): 30 => 30
2516 11:44:12.725837 DramcWriteLeveling(PI) end<-----
2517 11:44:12.725925
2518 11:44:12.725991 ==
2519 11:44:12.728942 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 11:44:12.732102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 11:44:12.732187 ==
2522 11:44:12.735524 [Gating] SW mode calibration
2523 11:44:12.742048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 11:44:12.749018 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 11:44:12.751984 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2526 11:44:12.755392 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
2527 11:44:12.762049 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 11:44:12.765737 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 11:44:12.768800 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 11:44:12.775505 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:44:12.778619 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
2532 11:44:12.782028 0 15 28 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
2533 11:44:12.785392 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
2534 11:44:12.791834 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 11:44:12.795174 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 11:44:12.798836 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 11:44:12.805443 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 11:44:12.808611 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:44:12.811907 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2540 11:44:12.818533 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2541 11:44:12.821620 1 1 0 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2542 11:44:12.824926 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 11:44:12.831678 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 11:44:12.834924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 11:44:12.838433 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 11:44:12.844773 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:44:12.848011 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:44:12.851423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 11:44:12.857932 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 11:44:12.861471 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:44:12.864715 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:44:12.871409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:44:12.874602 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:44:12.878007 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:44:12.884631 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:44:12.887909 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:44:12.891130 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:44:12.898136 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:44:12.901128 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:44:12.904159 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:44:12.910912 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:44:12.914229 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:44:12.917882 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2564 11:44:12.924251 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 11:44:12.924343 Total UI for P1: 0, mck2ui 16
2566 11:44:12.931059 best dqsien dly found for B0: ( 1, 3, 24)
2567 11:44:12.934432 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2568 11:44:12.937540 Total UI for P1: 0, mck2ui 16
2569 11:44:12.940736 best dqsien dly found for B1: ( 1, 3, 28)
2570 11:44:12.944160 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2571 11:44:12.947405 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2572 11:44:12.947488
2573 11:44:12.950655 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2574 11:44:12.954304 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2575 11:44:12.957421 [Gating] SW calibration Done
2576 11:44:12.957521 ==
2577 11:44:12.960734 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 11:44:12.964210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2579 11:44:12.967314 ==
2580 11:44:12.967396 RX Vref Scan: 0
2581 11:44:12.967459
2582 11:44:12.970979 RX Vref 0 -> 0, step: 1
2583 11:44:12.971050
2584 11:44:12.974144 RX Delay -40 -> 252, step: 8
2585 11:44:12.977672 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2586 11:44:12.980834 iDelay=200, Bit 1, Center 127 (56 ~ 199) 144
2587 11:44:12.983877 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2588 11:44:12.987490 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2589 11:44:12.993928 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2590 11:44:12.997491 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2591 11:44:13.000724 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2592 11:44:13.003993 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2593 11:44:13.006969 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2594 11:44:13.010635 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2595 11:44:13.016909 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2596 11:44:13.020124 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2597 11:44:13.023883 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2598 11:44:13.026911 iDelay=200, Bit 13, Center 111 (48 ~ 175) 128
2599 11:44:13.033685 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2600 11:44:13.037111 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2601 11:44:13.037192 ==
2602 11:44:13.040127 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 11:44:13.043740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 11:44:13.043818 ==
2605 11:44:13.046893 DQS Delay:
2606 11:44:13.046971 DQS0 = 0, DQS1 = 0
2607 11:44:13.047033 DQM Delay:
2608 11:44:13.050232 DQM0 = 123, DQM1 = 109
2609 11:44:13.050325 DQ Delay:
2610 11:44:13.053433 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2611 11:44:13.056625 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2612 11:44:13.060248 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2613 11:44:13.066844 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2614 11:44:13.066942
2615 11:44:13.067007
2616 11:44:13.067067 ==
2617 11:44:13.069884 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 11:44:13.073536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 11:44:13.073607 ==
2620 11:44:13.073668
2621 11:44:13.073725
2622 11:44:13.076647 TX Vref Scan disable
2623 11:44:13.076741 == TX Byte 0 ==
2624 11:44:13.083447 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2625 11:44:13.086964 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2626 11:44:13.087054 == TX Byte 1 ==
2627 11:44:13.093491 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2628 11:44:13.096563 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2629 11:44:13.096644 ==
2630 11:44:13.100291 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 11:44:13.103346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 11:44:13.103425 ==
2633 11:44:13.116421 TX Vref=22, minBit 0, minWin=23, winSum=396
2634 11:44:13.119651 TX Vref=24, minBit 7, minWin=22, winSum=403
2635 11:44:13.122797 TX Vref=26, minBit 1, minWin=24, winSum=412
2636 11:44:13.126347 TX Vref=28, minBit 0, minWin=25, winSum=416
2637 11:44:13.129558 TX Vref=30, minBit 5, minWin=24, winSum=419
2638 11:44:13.136288 TX Vref=32, minBit 0, minWin=24, winSum=413
2639 11:44:13.139358 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
2640 11:44:13.139464
2641 11:44:13.142713 Final TX Range 1 Vref 28
2642 11:44:13.142794
2643 11:44:13.142866 ==
2644 11:44:13.145925 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 11:44:13.149392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 11:44:13.152623 ==
2647 11:44:13.152697
2648 11:44:13.152759
2649 11:44:13.152817 TX Vref Scan disable
2650 11:44:13.155964 == TX Byte 0 ==
2651 11:44:13.159754 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2652 11:44:13.166026 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2653 11:44:13.166111 == TX Byte 1 ==
2654 11:44:13.169404 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2655 11:44:13.175732 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2656 11:44:13.175816
2657 11:44:13.175880 [DATLAT]
2658 11:44:13.175940 Freq=1200, CH0 RK0
2659 11:44:13.175999
2660 11:44:13.179303 DATLAT Default: 0xd
2661 11:44:13.179387 0, 0xFFFF, sum = 0
2662 11:44:13.182547 1, 0xFFFF, sum = 0
2663 11:44:13.186061 2, 0xFFFF, sum = 0
2664 11:44:13.186150 3, 0xFFFF, sum = 0
2665 11:44:13.189231 4, 0xFFFF, sum = 0
2666 11:44:13.189319 5, 0xFFFF, sum = 0
2667 11:44:13.192462 6, 0xFFFF, sum = 0
2668 11:44:13.192546 7, 0xFFFF, sum = 0
2669 11:44:13.195896 8, 0xFFFF, sum = 0
2670 11:44:13.195981 9, 0xFFFF, sum = 0
2671 11:44:13.199187 10, 0xFFFF, sum = 0
2672 11:44:13.199280 11, 0xFFFF, sum = 0
2673 11:44:13.202574 12, 0x0, sum = 1
2674 11:44:13.202652 13, 0x0, sum = 2
2675 11:44:13.205941 14, 0x0, sum = 3
2676 11:44:13.206023 15, 0x0, sum = 4
2677 11:44:13.209000 best_step = 13
2678 11:44:13.209094
2679 11:44:13.209161 ==
2680 11:44:13.212236 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 11:44:13.215389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 11:44:13.215488 ==
2683 11:44:13.215569 RX Vref Scan: 1
2684 11:44:13.218958
2685 11:44:13.219030 Set Vref Range= 32 -> 127
2686 11:44:13.219091
2687 11:44:13.222050 RX Vref 32 -> 127, step: 1
2688 11:44:13.222129
2689 11:44:13.225771 RX Delay -13 -> 252, step: 4
2690 11:44:13.225859
2691 11:44:13.229105 Set Vref, RX VrefLevel [Byte0]: 32
2692 11:44:13.232057 [Byte1]: 32
2693 11:44:13.232165
2694 11:44:13.235717 Set Vref, RX VrefLevel [Byte0]: 33
2695 11:44:13.238904 [Byte1]: 33
2696 11:44:13.242479
2697 11:44:13.242563 Set Vref, RX VrefLevel [Byte0]: 34
2698 11:44:13.245754 [Byte1]: 34
2699 11:44:13.250105
2700 11:44:13.250212 Set Vref, RX VrefLevel [Byte0]: 35
2701 11:44:13.253821 [Byte1]: 35
2702 11:44:13.258075
2703 11:44:13.258166 Set Vref, RX VrefLevel [Byte0]: 36
2704 11:44:13.261495 [Byte1]: 36
2705 11:44:13.266068
2706 11:44:13.266154 Set Vref, RX VrefLevel [Byte0]: 37
2707 11:44:13.269334 [Byte1]: 37
2708 11:44:13.274121
2709 11:44:13.274243 Set Vref, RX VrefLevel [Byte0]: 38
2710 11:44:13.277171 [Byte1]: 38
2711 11:44:13.282018
2712 11:44:13.282099 Set Vref, RX VrefLevel [Byte0]: 39
2713 11:44:13.285435 [Byte1]: 39
2714 11:44:13.289720
2715 11:44:13.289800 Set Vref, RX VrefLevel [Byte0]: 40
2716 11:44:13.292862 [Byte1]: 40
2717 11:44:13.297549
2718 11:44:13.297637 Set Vref, RX VrefLevel [Byte0]: 41
2719 11:44:13.300921 [Byte1]: 41
2720 11:44:13.305444
2721 11:44:13.305528 Set Vref, RX VrefLevel [Byte0]: 42
2722 11:44:13.308679 [Byte1]: 42
2723 11:44:13.313333
2724 11:44:13.313411 Set Vref, RX VrefLevel [Byte0]: 43
2725 11:44:13.316650 [Byte1]: 43
2726 11:44:13.321187
2727 11:44:13.321273 Set Vref, RX VrefLevel [Byte0]: 44
2728 11:44:13.324867 [Byte1]: 44
2729 11:44:13.329104
2730 11:44:13.329182 Set Vref, RX VrefLevel [Byte0]: 45
2731 11:44:13.332667 [Byte1]: 45
2732 11:44:13.337237
2733 11:44:13.337314 Set Vref, RX VrefLevel [Byte0]: 46
2734 11:44:13.340516 [Byte1]: 46
2735 11:44:13.345138
2736 11:44:13.345219 Set Vref, RX VrefLevel [Byte0]: 47
2737 11:44:13.348109 [Byte1]: 47
2738 11:44:13.352961
2739 11:44:13.353045 Set Vref, RX VrefLevel [Byte0]: 48
2740 11:44:13.356227 [Byte1]: 48
2741 11:44:13.360654
2742 11:44:13.360738 Set Vref, RX VrefLevel [Byte0]: 49
2743 11:44:13.364076 [Byte1]: 49
2744 11:44:13.368644
2745 11:44:13.368725 Set Vref, RX VrefLevel [Byte0]: 50
2746 11:44:13.371935 [Byte1]: 50
2747 11:44:13.376447
2748 11:44:13.376537 Set Vref, RX VrefLevel [Byte0]: 51
2749 11:44:13.379777 [Byte1]: 51
2750 11:44:13.384486
2751 11:44:13.384574 Set Vref, RX VrefLevel [Byte0]: 52
2752 11:44:13.387728 [Byte1]: 52
2753 11:44:13.392223
2754 11:44:13.392355 Set Vref, RX VrefLevel [Byte0]: 53
2755 11:44:13.395716 [Byte1]: 53
2756 11:44:13.400282
2757 11:44:13.400403 Set Vref, RX VrefLevel [Byte0]: 54
2758 11:44:13.403346 [Byte1]: 54
2759 11:44:13.408067
2760 11:44:13.408147 Set Vref, RX VrefLevel [Byte0]: 55
2761 11:44:13.411403 [Byte1]: 55
2762 11:44:13.416041
2763 11:44:13.416127 Set Vref, RX VrefLevel [Byte0]: 56
2764 11:44:13.419441 [Byte1]: 56
2765 11:44:13.424069
2766 11:44:13.424155 Set Vref, RX VrefLevel [Byte0]: 57
2767 11:44:13.427127 [Byte1]: 57
2768 11:44:13.431708
2769 11:44:13.431786 Set Vref, RX VrefLevel [Byte0]: 58
2770 11:44:13.435259 [Byte1]: 58
2771 11:44:13.439539
2772 11:44:13.439627 Set Vref, RX VrefLevel [Byte0]: 59
2773 11:44:13.443288 [Byte1]: 59
2774 11:44:13.447698
2775 11:44:13.447778 Set Vref, RX VrefLevel [Byte0]: 60
2776 11:44:13.450656 [Byte1]: 60
2777 11:44:13.455507
2778 11:44:13.455614 Set Vref, RX VrefLevel [Byte0]: 61
2779 11:44:13.458577 [Byte1]: 61
2780 11:44:13.463444
2781 11:44:13.463526 Set Vref, RX VrefLevel [Byte0]: 62
2782 11:44:13.466494 [Byte1]: 62
2783 11:44:13.471099
2784 11:44:13.471183 Set Vref, RX VrefLevel [Byte0]: 63
2785 11:44:13.474655 [Byte1]: 63
2786 11:44:13.479061
2787 11:44:13.479165 Set Vref, RX VrefLevel [Byte0]: 64
2788 11:44:13.482537 [Byte1]: 64
2789 11:44:13.487233
2790 11:44:13.487313 Set Vref, RX VrefLevel [Byte0]: 65
2791 11:44:13.490420 [Byte1]: 65
2792 11:44:13.494987
2793 11:44:13.495131 Set Vref, RX VrefLevel [Byte0]: 66
2794 11:44:13.498058 [Byte1]: 66
2795 11:44:13.523797
2796 11:44:13.523996 Set Vref, RX VrefLevel [Byte0]: 67
2797 11:44:13.524082 [Byte1]: 67
2798 11:44:13.524143
2799 11:44:13.524201 Set Vref, RX VrefLevel [Byte0]: 68
2800 11:44:13.524304 [Byte1]: 68
2801 11:44:13.524360
2802 11:44:13.524415 Set Vref, RX VrefLevel [Byte0]: 69
2803 11:44:13.524471 [Byte1]: 69
2804 11:44:13.526606
2805 11:44:13.526673 Final RX Vref Byte 0 = 60 to rank0
2806 11:44:13.529847 Final RX Vref Byte 1 = 52 to rank0
2807 11:44:13.533493 Final RX Vref Byte 0 = 60 to rank1
2808 11:44:13.536290 Final RX Vref Byte 1 = 52 to rank1==
2809 11:44:13.539434 Dram Type= 6, Freq= 0, CH_0, rank 0
2810 11:44:13.546457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2811 11:44:13.546530 ==
2812 11:44:13.546592 DQS Delay:
2813 11:44:13.549565 DQS0 = 0, DQS1 = 0
2814 11:44:13.549640 DQM Delay:
2815 11:44:13.549699 DQM0 = 123, DQM1 = 110
2816 11:44:13.553129 DQ Delay:
2817 11:44:13.556342 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2818 11:44:13.559608 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2819 11:44:13.562798 DQ8 =102, DQ9 =96, DQ10 =110, DQ11 =108
2820 11:44:13.566249 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2821 11:44:13.566320
2822 11:44:13.566380
2823 11:44:13.576205 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2824 11:44:13.576278 CH0 RK0: MR19=404, MR18=804
2825 11:44:13.582625 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2826 11:44:13.582759
2827 11:44:13.586061 ----->DramcWriteLeveling(PI) begin...
2828 11:44:13.586198 ==
2829 11:44:13.589313 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 11:44:13.592893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 11:44:13.596018 ==
2832 11:44:13.599312 Write leveling (Byte 0): 34 => 34
2833 11:44:13.599408 Write leveling (Byte 1): 29 => 29
2834 11:44:13.602909 DramcWriteLeveling(PI) end<-----
2835 11:44:13.603003
2836 11:44:13.603067 ==
2837 11:44:13.605825 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 11:44:13.612671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 11:44:13.612749 ==
2840 11:44:13.615767 [Gating] SW mode calibration
2841 11:44:13.622490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2842 11:44:13.625838 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2843 11:44:13.632559 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2844 11:44:13.635710 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 11:44:13.639344 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 11:44:13.646037 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 11:44:13.649172 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 11:44:13.652337 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 11:44:13.659204 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 11:44:13.662654 0 15 28 | B1->B0 | 2d2d 2c2c | 0 0 | (0 1) (1 0)
2851 11:44:13.665850 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 11:44:13.668918 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 11:44:13.675804 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 11:44:13.679028 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 11:44:13.682521 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 11:44:13.688974 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 11:44:13.692050 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2858 11:44:13.695504 1 0 28 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
2859 11:44:13.702241 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 11:44:13.705332 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 11:44:13.708768 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 11:44:13.715723 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 11:44:13.718516 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 11:44:13.721907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 11:44:13.728793 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 11:44:13.731869 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2867 11:44:13.735066 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:44:13.741787 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:44:13.745352 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:44:13.748440 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:44:13.755375 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:44:13.758642 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:44:13.761689 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:44:13.768668 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:44:13.771838 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:44:13.774946 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:44:13.781894 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:44:13.785393 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:44:13.788464 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:44:13.795263 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:44:13.798369 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2882 11:44:13.801984 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2883 11:44:13.808209 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 11:44:13.808300 Total UI for P1: 0, mck2ui 16
2885 11:44:13.814806 best dqsien dly found for B0: ( 1, 3, 26)
2886 11:44:13.814897 Total UI for P1: 0, mck2ui 16
2887 11:44:13.818264 best dqsien dly found for B1: ( 1, 3, 28)
2888 11:44:13.824873 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2889 11:44:13.828058 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2890 11:44:13.828151
2891 11:44:13.831633 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2892 11:44:13.834681 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2893 11:44:13.838300 [Gating] SW calibration Done
2894 11:44:13.838385 ==
2895 11:44:13.841700 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 11:44:13.844706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 11:44:13.844830 ==
2898 11:44:13.848142 RX Vref Scan: 0
2899 11:44:13.848229
2900 11:44:13.848345 RX Vref 0 -> 0, step: 1
2901 11:44:13.848426
2902 11:44:13.851295 RX Delay -40 -> 252, step: 8
2903 11:44:13.854814 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2904 11:44:13.861615 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2905 11:44:13.864664 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2906 11:44:13.867867 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2907 11:44:13.871443 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2908 11:44:13.874410 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2909 11:44:13.881284 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2910 11:44:13.884612 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2911 11:44:13.887570 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2912 11:44:13.891243 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2913 11:44:13.894471 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2914 11:44:13.901084 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2915 11:44:13.904302 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2916 11:44:13.907756 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2917 11:44:13.910894 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2918 11:44:13.914122 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2919 11:44:13.917657 ==
2920 11:44:13.917796 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 11:44:13.924358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 11:44:13.924446 ==
2923 11:44:13.924511 DQS Delay:
2924 11:44:13.927817 DQS0 = 0, DQS1 = 0
2925 11:44:13.927900 DQM Delay:
2926 11:44:13.930976 DQM0 = 120, DQM1 = 108
2927 11:44:13.931078 DQ Delay:
2928 11:44:13.934030 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2929 11:44:13.937572 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2930 11:44:13.940619 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =103
2931 11:44:13.944156 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2932 11:44:13.944265
2933 11:44:13.944358
2934 11:44:13.944446 ==
2935 11:44:13.947650 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 11:44:13.954300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 11:44:13.954409 ==
2938 11:44:13.954528
2939 11:44:13.954632
2940 11:44:13.954718 TX Vref Scan disable
2941 11:44:13.957373 == TX Byte 0 ==
2942 11:44:13.960556 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2943 11:44:13.967440 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2944 11:44:13.967579 == TX Byte 1 ==
2945 11:44:13.970542 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2946 11:44:13.977195 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2947 11:44:13.977344 ==
2948 11:44:13.980889 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 11:44:13.984029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 11:44:13.984128 ==
2951 11:44:13.995819 TX Vref=22, minBit 5, minWin=23, winSum=402
2952 11:44:13.998969 TX Vref=24, minBit 0, minWin=24, winSum=409
2953 11:44:14.002287 TX Vref=26, minBit 4, minWin=24, winSum=413
2954 11:44:14.005809 TX Vref=28, minBit 7, minWin=24, winSum=416
2955 11:44:14.008941 TX Vref=30, minBit 4, minWin=24, winSum=421
2956 11:44:14.012626 TX Vref=32, minBit 1, minWin=25, winSum=416
2957 11:44:14.019015 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 32
2958 11:44:14.019092
2959 11:44:14.022650 Final TX Range 1 Vref 32
2960 11:44:14.022725
2961 11:44:14.022824 ==
2962 11:44:14.025817 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 11:44:14.029332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 11:44:14.029405 ==
2965 11:44:14.029474
2966 11:44:14.029532
2967 11:44:14.032343 TX Vref Scan disable
2968 11:44:14.035886 == TX Byte 0 ==
2969 11:44:14.038906 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2970 11:44:14.042454 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2971 11:44:14.045935 == TX Byte 1 ==
2972 11:44:14.048918 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2973 11:44:14.052158 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2974 11:44:14.052241
2975 11:44:14.055614 [DATLAT]
2976 11:44:14.055684 Freq=1200, CH0 RK1
2977 11:44:14.055744
2978 11:44:14.059053 DATLAT Default: 0xd
2979 11:44:14.059129 0, 0xFFFF, sum = 0
2980 11:44:14.062209 1, 0xFFFF, sum = 0
2981 11:44:14.062302 2, 0xFFFF, sum = 0
2982 11:44:14.065517 3, 0xFFFF, sum = 0
2983 11:44:14.065590 4, 0xFFFF, sum = 0
2984 11:44:14.069025 5, 0xFFFF, sum = 0
2985 11:44:14.069104 6, 0xFFFF, sum = 0
2986 11:44:14.072291 7, 0xFFFF, sum = 0
2987 11:44:14.075518 8, 0xFFFF, sum = 0
2988 11:44:14.075591 9, 0xFFFF, sum = 0
2989 11:44:14.079068 10, 0xFFFF, sum = 0
2990 11:44:14.079144 11, 0xFFFF, sum = 0
2991 11:44:14.082087 12, 0x0, sum = 1
2992 11:44:14.082164 13, 0x0, sum = 2
2993 11:44:14.085633 14, 0x0, sum = 3
2994 11:44:14.085748 15, 0x0, sum = 4
2995 11:44:14.085894 best_step = 13
2996 11:44:14.086021
2997 11:44:14.088886 ==
2998 11:44:14.092225 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 11:44:14.095576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 11:44:14.095662 ==
3001 11:44:14.095729 RX Vref Scan: 0
3002 11:44:14.095791
3003 11:44:14.098720 RX Vref 0 -> 0, step: 1
3004 11:44:14.098804
3005 11:44:14.101873 RX Delay -13 -> 252, step: 4
3006 11:44:14.105416 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3007 11:44:14.112030 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3008 11:44:14.115123 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3009 11:44:14.118386 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3010 11:44:14.121961 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3011 11:44:14.124915 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3012 11:44:14.131719 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3013 11:44:14.134830 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3014 11:44:14.138483 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3015 11:44:14.141681 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3016 11:44:14.145132 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3017 11:44:14.151944 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3018 11:44:14.154966 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3019 11:44:14.158459 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3020 11:44:14.161770 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3021 11:44:14.164946 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3022 11:44:14.168075 ==
3023 11:44:14.171375 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 11:44:14.174912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 11:44:14.175002 ==
3026 11:44:14.175094 DQS Delay:
3027 11:44:14.178227 DQS0 = 0, DQS1 = 0
3028 11:44:14.178331 DQM Delay:
3029 11:44:14.181243 DQM0 = 120, DQM1 = 107
3030 11:44:14.181327 DQ Delay:
3031 11:44:14.184640 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =114
3032 11:44:14.188348 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3033 11:44:14.191370 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3034 11:44:14.194969 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3035 11:44:14.195056
3036 11:44:14.195121
3037 11:44:14.204518 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3038 11:44:14.204626 CH0 RK1: MR19=403, MR18=EF5
3039 11:44:14.210991 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3040 11:44:14.214681 [RxdqsGatingPostProcess] freq 1200
3041 11:44:14.220958 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3042 11:44:14.224712 best DQS0 dly(2T, 0.5T) = (0, 11)
3043 11:44:14.227851 best DQS1 dly(2T, 0.5T) = (0, 11)
3044 11:44:14.230969 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3045 11:44:14.234388 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3046 11:44:14.237960 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 11:44:14.240911 best DQS1 dly(2T, 0.5T) = (0, 11)
3048 11:44:14.244665 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 11:44:14.247853 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3050 11:44:14.247950 Pre-setting of DQS Precalculation
3051 11:44:14.254197 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3052 11:44:14.254287 ==
3053 11:44:14.257867 Dram Type= 6, Freq= 0, CH_1, rank 0
3054 11:44:14.260851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 11:44:14.261017 ==
3056 11:44:14.267851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3057 11:44:14.274469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3058 11:44:14.281592 [CA 0] Center 37 (7~67) winsize 61
3059 11:44:14.284612 [CA 1] Center 37 (7~68) winsize 62
3060 11:44:14.287934 [CA 2] Center 34 (4~65) winsize 62
3061 11:44:14.291310 [CA 3] Center 33 (3~64) winsize 62
3062 11:44:14.294713 [CA 4] Center 33 (3~64) winsize 62
3063 11:44:14.298303 [CA 5] Center 33 (3~63) winsize 61
3064 11:44:14.298392
3065 11:44:14.301231 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3066 11:44:14.301317
3067 11:44:14.304648 [CATrainingPosCal] consider 1 rank data
3068 11:44:14.307965 u2DelayCellTimex100 = 270/100 ps
3069 11:44:14.311480 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3070 11:44:14.318149 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3071 11:44:14.321377 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3072 11:44:14.324422 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3073 11:44:14.327877 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3074 11:44:14.331445 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3075 11:44:14.331518
3076 11:44:14.334404 CA PerBit enable=1, Macro0, CA PI delay=33
3077 11:44:14.334482
3078 11:44:14.338014 [CBTSetCACLKResult] CA Dly = 33
3079 11:44:14.338090 CS Dly: 5 (0~36)
3080 11:44:14.341107 ==
3081 11:44:14.344549 Dram Type= 6, Freq= 0, CH_1, rank 1
3082 11:44:14.347847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:44:14.347936 ==
3084 11:44:14.354365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3085 11:44:14.357830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3086 11:44:14.366963 [CA 0] Center 38 (8~68) winsize 61
3087 11:44:14.370511 [CA 1] Center 37 (7~68) winsize 62
3088 11:44:14.373614 [CA 2] Center 35 (4~66) winsize 63
3089 11:44:14.376854 [CA 3] Center 34 (4~65) winsize 62
3090 11:44:14.380477 [CA 4] Center 34 (4~64) winsize 61
3091 11:44:14.383710 [CA 5] Center 33 (3~64) winsize 62
3092 11:44:14.383818
3093 11:44:14.387067 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3094 11:44:14.387155
3095 11:44:14.390248 [CATrainingPosCal] consider 2 rank data
3096 11:44:14.393657 u2DelayCellTimex100 = 270/100 ps
3097 11:44:14.396721 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3098 11:44:14.403434 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3099 11:44:14.407244 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3100 11:44:14.410306 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3101 11:44:14.413862 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3102 11:44:14.416893 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3103 11:44:14.417015
3104 11:44:14.420144 CA PerBit enable=1, Macro0, CA PI delay=33
3105 11:44:14.420228
3106 11:44:14.423732 [CBTSetCACLKResult] CA Dly = 33
3107 11:44:14.423828 CS Dly: 6 (0~38)
3108 11:44:14.423925
3109 11:44:14.426778 ----->DramcWriteLeveling(PI) begin...
3110 11:44:14.430397 ==
3111 11:44:14.433703 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 11:44:14.436757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 11:44:14.436875 ==
3114 11:44:14.440424 Write leveling (Byte 0): 24 => 24
3115 11:44:14.443511 Write leveling (Byte 1): 29 => 29
3116 11:44:14.446650 DramcWriteLeveling(PI) end<-----
3117 11:44:14.446769
3118 11:44:14.446893 ==
3119 11:44:14.450143 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 11:44:14.453635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 11:44:14.453739 ==
3122 11:44:14.456616 [Gating] SW mode calibration
3123 11:44:14.463329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3124 11:44:14.469972 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3125 11:44:14.473112 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 11:44:14.476692 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 11:44:14.483641 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 11:44:14.486761 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 11:44:14.489948 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 11:44:14.496674 0 15 20 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
3131 11:44:14.500042 0 15 24 | B1->B0 | 2525 2323 | 1 0 | (1 0) (1 0)
3132 11:44:14.503159 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3133 11:44:14.506762 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 11:44:14.513219 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 11:44:14.516858 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 11:44:14.520108 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 11:44:14.526457 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 11:44:14.529680 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3139 11:44:14.533208 1 0 24 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
3140 11:44:14.539644 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:44:14.543142 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 11:44:14.546200 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 11:44:14.553070 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 11:44:14.556078 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 11:44:14.559637 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 11:44:14.565968 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 11:44:14.569428 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3148 11:44:14.572946 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3149 11:44:14.579297 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:44:14.582967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:44:14.586081 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:44:14.592743 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:44:14.595902 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:44:14.599240 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:44:14.605945 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:44:14.609612 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:44:14.612555 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:44:14.619286 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:44:14.622386 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:44:14.625927 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:44:14.632532 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:44:14.635831 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3163 11:44:14.639017 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 11:44:14.645810 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3165 11:44:14.645909 Total UI for P1: 0, mck2ui 16
3166 11:44:14.652425 best dqsien dly found for B0: ( 1, 3, 22)
3167 11:44:14.655883 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 11:44:14.658932 Total UI for P1: 0, mck2ui 16
3169 11:44:14.662177 best dqsien dly found for B1: ( 1, 3, 26)
3170 11:44:14.665669 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3171 11:44:14.669030 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3172 11:44:14.669106
3173 11:44:14.671975 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3174 11:44:14.675397 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3175 11:44:14.678843 [Gating] SW calibration Done
3176 11:44:14.678915 ==
3177 11:44:14.682177 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 11:44:14.685229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 11:44:14.688858 ==
3180 11:44:14.688981 RX Vref Scan: 0
3181 11:44:14.689062
3182 11:44:14.691847 RX Vref 0 -> 0, step: 1
3183 11:44:14.691946
3184 11:44:14.692037 RX Delay -40 -> 252, step: 8
3185 11:44:14.698829 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3186 11:44:14.702290 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3187 11:44:14.705688 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3188 11:44:14.708825 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3189 11:44:14.712043 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3190 11:44:14.718707 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3191 11:44:14.722076 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3192 11:44:14.725182 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3193 11:44:14.728685 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3194 11:44:14.732127 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3195 11:44:14.738844 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3196 11:44:14.741976 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3197 11:44:14.745162 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3198 11:44:14.748760 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3199 11:44:14.751842 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3200 11:44:14.758381 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3201 11:44:14.758460 ==
3202 11:44:14.761969 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 11:44:14.765078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 11:44:14.765158 ==
3205 11:44:14.765221 DQS Delay:
3206 11:44:14.768561 DQS0 = 0, DQS1 = 0
3207 11:44:14.768659 DQM Delay:
3208 11:44:14.771636 DQM0 = 119, DQM1 = 113
3209 11:44:14.771729 DQ Delay:
3210 11:44:14.775295 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3211 11:44:14.778307 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3212 11:44:14.781960 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3213 11:44:14.785325 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3214 11:44:14.785415
3215 11:44:14.788379
3216 11:44:14.788489 ==
3217 11:44:14.792035 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 11:44:14.795258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 11:44:14.795369 ==
3220 11:44:14.795468
3221 11:44:14.795559
3222 11:44:14.798356 TX Vref Scan disable
3223 11:44:14.798456 == TX Byte 0 ==
3224 11:44:14.805234 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3225 11:44:14.808277 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3226 11:44:14.808373 == TX Byte 1 ==
3227 11:44:14.814984 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3228 11:44:14.818146 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3229 11:44:14.818230 ==
3230 11:44:14.821670 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 11:44:14.824735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 11:44:14.824837 ==
3233 11:44:14.837283 TX Vref=22, minBit 1, minWin=24, winSum=396
3234 11:44:14.840332 TX Vref=24, minBit 1, minWin=24, winSum=403
3235 11:44:14.844045 TX Vref=26, minBit 1, minWin=24, winSum=411
3236 11:44:14.847218 TX Vref=28, minBit 9, minWin=25, winSum=416
3237 11:44:14.850379 TX Vref=30, minBit 10, minWin=25, winSum=419
3238 11:44:14.857360 TX Vref=32, minBit 11, minWin=24, winSum=418
3239 11:44:14.860525 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 30
3240 11:44:14.860641
3241 11:44:14.863931 Final TX Range 1 Vref 30
3242 11:44:14.864061
3243 11:44:14.864162 ==
3244 11:44:14.867391 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 11:44:14.870345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 11:44:14.873470 ==
3247 11:44:14.873556
3248 11:44:14.873622
3249 11:44:14.873685 TX Vref Scan disable
3250 11:44:14.877398 == TX Byte 0 ==
3251 11:44:14.880464 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3252 11:44:14.887309 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3253 11:44:14.887391 == TX Byte 1 ==
3254 11:44:14.890577 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3255 11:44:14.897452 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3256 11:44:14.897534
3257 11:44:14.897599 [DATLAT]
3258 11:44:14.897662 Freq=1200, CH1 RK0
3259 11:44:14.897723
3260 11:44:14.900746 DATLAT Default: 0xd
3261 11:44:14.900821 0, 0xFFFF, sum = 0
3262 11:44:14.903925 1, 0xFFFF, sum = 0
3263 11:44:14.904002 2, 0xFFFF, sum = 0
3264 11:44:14.907147 3, 0xFFFF, sum = 0
3265 11:44:14.910490 4, 0xFFFF, sum = 0
3266 11:44:14.910578 5, 0xFFFF, sum = 0
3267 11:44:14.914403 6, 0xFFFF, sum = 0
3268 11:44:14.914491 7, 0xFFFF, sum = 0
3269 11:44:14.917129 8, 0xFFFF, sum = 0
3270 11:44:14.917217 9, 0xFFFF, sum = 0
3271 11:44:14.920870 10, 0xFFFF, sum = 0
3272 11:44:14.920959 11, 0xFFFF, sum = 0
3273 11:44:14.923818 12, 0x0, sum = 1
3274 11:44:14.923904 13, 0x0, sum = 2
3275 11:44:14.927393 14, 0x0, sum = 3
3276 11:44:14.927484 15, 0x0, sum = 4
3277 11:44:14.927562 best_step = 13
3278 11:44:14.930544
3279 11:44:14.930628 ==
3280 11:44:14.933691 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 11:44:14.937323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 11:44:14.937409 ==
3283 11:44:14.937494 RX Vref Scan: 1
3284 11:44:14.937560
3285 11:44:14.940375 Set Vref Range= 32 -> 127
3286 11:44:14.940460
3287 11:44:14.943676 RX Vref 32 -> 127, step: 1
3288 11:44:14.943791
3289 11:44:14.946947 RX Delay -13 -> 252, step: 4
3290 11:44:14.947034
3291 11:44:14.950626 Set Vref, RX VrefLevel [Byte0]: 32
3292 11:44:14.953674 [Byte1]: 32
3293 11:44:14.953757
3294 11:44:14.957245 Set Vref, RX VrefLevel [Byte0]: 33
3295 11:44:14.960438 [Byte1]: 33
3296 11:44:14.963911
3297 11:44:14.964021 Set Vref, RX VrefLevel [Byte0]: 34
3298 11:44:14.967358 [Byte1]: 34
3299 11:44:14.971658
3300 11:44:14.971761 Set Vref, RX VrefLevel [Byte0]: 35
3301 11:44:14.974852 [Byte1]: 35
3302 11:44:14.979476
3303 11:44:14.979559 Set Vref, RX VrefLevel [Byte0]: 36
3304 11:44:14.982683 [Byte1]: 36
3305 11:44:14.987542
3306 11:44:14.987623 Set Vref, RX VrefLevel [Byte0]: 37
3307 11:44:14.990522 [Byte1]: 37
3308 11:44:14.995085
3309 11:44:14.995193 Set Vref, RX VrefLevel [Byte0]: 38
3310 11:44:14.998638 [Byte1]: 38
3311 11:44:15.003053
3312 11:44:15.003134 Set Vref, RX VrefLevel [Byte0]: 39
3313 11:44:15.006274 [Byte1]: 39
3314 11:44:15.010912
3315 11:44:15.010993 Set Vref, RX VrefLevel [Byte0]: 40
3316 11:44:15.014665 [Byte1]: 40
3317 11:44:15.018863
3318 11:44:15.018944 Set Vref, RX VrefLevel [Byte0]: 41
3319 11:44:15.021954 [Byte1]: 41
3320 11:44:15.026881
3321 11:44:15.030014 Set Vref, RX VrefLevel [Byte0]: 42
3322 11:44:15.030100 [Byte1]: 42
3323 11:44:15.034440
3324 11:44:15.034521 Set Vref, RX VrefLevel [Byte0]: 43
3325 11:44:15.037709 [Byte1]: 43
3326 11:44:15.042653
3327 11:44:15.042735 Set Vref, RX VrefLevel [Byte0]: 44
3328 11:44:15.045669 [Byte1]: 44
3329 11:44:15.050400
3330 11:44:15.050482 Set Vref, RX VrefLevel [Byte0]: 45
3331 11:44:15.053550 [Byte1]: 45
3332 11:44:15.058176
3333 11:44:15.058257 Set Vref, RX VrefLevel [Byte0]: 46
3334 11:44:15.061643 [Byte1]: 46
3335 11:44:15.065979
3336 11:44:15.066061 Set Vref, RX VrefLevel [Byte0]: 47
3337 11:44:15.069532 [Byte1]: 47
3338 11:44:15.074326
3339 11:44:15.074421 Set Vref, RX VrefLevel [Byte0]: 48
3340 11:44:15.077467 [Byte1]: 48
3341 11:44:15.081859
3342 11:44:15.081967 Set Vref, RX VrefLevel [Byte0]: 49
3343 11:44:15.085382 [Byte1]: 49
3344 11:44:15.089867
3345 11:44:15.089948 Set Vref, RX VrefLevel [Byte0]: 50
3346 11:44:15.096258 [Byte1]: 50
3347 11:44:15.096339
3348 11:44:15.099541 Set Vref, RX VrefLevel [Byte0]: 51
3349 11:44:15.103084 [Byte1]: 51
3350 11:44:15.103165
3351 11:44:15.106302 Set Vref, RX VrefLevel [Byte0]: 52
3352 11:44:15.109458 [Byte1]: 52
3353 11:44:15.113640
3354 11:44:15.113721 Set Vref, RX VrefLevel [Byte0]: 53
3355 11:44:15.116817 [Byte1]: 53
3356 11:44:15.121466
3357 11:44:15.121547 Set Vref, RX VrefLevel [Byte0]: 54
3358 11:44:15.124588 [Byte1]: 54
3359 11:44:15.129165
3360 11:44:15.129250 Set Vref, RX VrefLevel [Byte0]: 55
3361 11:44:15.132689 [Byte1]: 55
3362 11:44:15.136914
3363 11:44:15.137035 Set Vref, RX VrefLevel [Byte0]: 56
3364 11:44:15.140544 [Byte1]: 56
3365 11:44:15.145242
3366 11:44:15.145324 Set Vref, RX VrefLevel [Byte0]: 57
3367 11:44:15.148368 [Byte1]: 57
3368 11:44:15.152906
3369 11:44:15.153047 Set Vref, RX VrefLevel [Byte0]: 58
3370 11:44:15.156101 [Byte1]: 58
3371 11:44:15.160738
3372 11:44:15.160821 Set Vref, RX VrefLevel [Byte0]: 59
3373 11:44:15.164217 [Byte1]: 59
3374 11:44:15.168645
3375 11:44:15.168728 Set Vref, RX VrefLevel [Byte0]: 60
3376 11:44:15.172273 [Byte1]: 60
3377 11:44:15.176573
3378 11:44:15.176657 Set Vref, RX VrefLevel [Byte0]: 61
3379 11:44:15.179951 [Byte1]: 61
3380 11:44:15.184457
3381 11:44:15.184550 Set Vref, RX VrefLevel [Byte0]: 62
3382 11:44:15.187862 [Byte1]: 62
3383 11:44:15.192665
3384 11:44:15.192748 Set Vref, RX VrefLevel [Byte0]: 63
3385 11:44:15.195752 [Byte1]: 63
3386 11:44:15.200318
3387 11:44:15.200401 Set Vref, RX VrefLevel [Byte0]: 64
3388 11:44:15.203603 [Byte1]: 64
3389 11:44:15.208397
3390 11:44:15.208481 Set Vref, RX VrefLevel [Byte0]: 65
3391 11:44:15.211568 [Byte1]: 65
3392 11:44:15.216006
3393 11:44:15.216089 Set Vref, RX VrefLevel [Byte0]: 66
3394 11:44:15.219323 [Byte1]: 66
3395 11:44:15.224128
3396 11:44:15.224211 Set Vref, RX VrefLevel [Byte0]: 67
3397 11:44:15.227095 [Byte1]: 67
3398 11:44:15.231875
3399 11:44:15.231958 Final RX Vref Byte 0 = 52 to rank0
3400 11:44:15.235189 Final RX Vref Byte 1 = 48 to rank0
3401 11:44:15.238707 Final RX Vref Byte 0 = 52 to rank1
3402 11:44:15.241832 Final RX Vref Byte 1 = 48 to rank1==
3403 11:44:15.245084 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 11:44:15.251850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 11:44:15.251934 ==
3406 11:44:15.252001 DQS Delay:
3407 11:44:15.252061 DQS0 = 0, DQS1 = 0
3408 11:44:15.255196 DQM Delay:
3409 11:44:15.255268 DQM0 = 119, DQM1 = 111
3410 11:44:15.258191 DQ Delay:
3411 11:44:15.261562 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3412 11:44:15.265318 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3413 11:44:15.268383 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =104
3414 11:44:15.271752 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =116
3415 11:44:15.271831
3416 11:44:15.271898
3417 11:44:15.278351 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3418 11:44:15.281705 CH1 RK0: MR19=404, MR18=215
3419 11:44:15.288425 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3420 11:44:15.288503
3421 11:44:15.291422 ----->DramcWriteLeveling(PI) begin...
3422 11:44:15.291518 ==
3423 11:44:15.294850 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 11:44:15.298285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 11:44:15.301437 ==
3426 11:44:15.301507 Write leveling (Byte 0): 26 => 26
3427 11:44:15.304790 Write leveling (Byte 1): 30 => 30
3428 11:44:15.308120 DramcWriteLeveling(PI) end<-----
3429 11:44:15.308189
3430 11:44:15.308251 ==
3431 11:44:15.311588 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 11:44:15.318026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 11:44:15.318101 ==
3434 11:44:15.318163 [Gating] SW mode calibration
3435 11:44:15.327755 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 11:44:15.331289 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 11:44:15.337756 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 11:44:15.340964 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 11:44:15.344204 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 11:44:15.350978 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 11:44:15.354584 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 11:44:15.357496 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 11:44:15.364311 0 15 24 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 1)
3444 11:44:15.367802 0 15 28 | B1->B0 | 2323 2d2d | 0 1 | (1 0) (1 0)
3445 11:44:15.370939 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 11:44:15.377560 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 11:44:15.380807 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 11:44:15.384253 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 11:44:15.390711 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 11:44:15.394176 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 11:44:15.397680 1 0 24 | B1->B0 | 3635 2828 | 1 0 | (0 0) (0 0)
3452 11:44:15.404005 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 11:44:15.407520 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 11:44:15.410803 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 11:44:15.414042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 11:44:15.420904 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 11:44:15.424051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 11:44:15.427276 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 11:44:15.433903 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3460 11:44:15.437479 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:44:15.440548 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:44:15.447297 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:44:15.450587 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:44:15.453651 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:44:15.460414 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:44:15.463489 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:44:15.467119 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:44:15.473410 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:44:15.477021 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:44:15.480038 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:44:15.486856 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:44:15.489751 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:44:15.493249 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:44:15.499635 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:44:15.502959 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 11:44:15.506222 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3477 11:44:15.509784 Total UI for P1: 0, mck2ui 16
3478 11:44:15.513212 best dqsien dly found for B1: ( 1, 3, 24)
3479 11:44:15.519645 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 11:44:15.519730 Total UI for P1: 0, mck2ui 16
3481 11:44:15.526386 best dqsien dly found for B0: ( 1, 3, 26)
3482 11:44:15.529549 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3483 11:44:15.532702 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3484 11:44:15.532786
3485 11:44:15.536221 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 11:44:15.539217 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3487 11:44:15.542754 [Gating] SW calibration Done
3488 11:44:15.542837 ==
3489 11:44:15.545902 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 11:44:15.549160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 11:44:15.549244 ==
3492 11:44:15.552660 RX Vref Scan: 0
3493 11:44:15.552743
3494 11:44:15.555864 RX Vref 0 -> 0, step: 1
3495 11:44:15.555947
3496 11:44:15.556012 RX Delay -40 -> 252, step: 8
3497 11:44:15.562772 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3498 11:44:15.565768 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3499 11:44:15.569305 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3500 11:44:15.572641 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3501 11:44:15.576155 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3502 11:44:15.582570 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3503 11:44:15.586007 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3504 11:44:15.588957 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3505 11:44:15.592657 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3506 11:44:15.595652 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3507 11:44:15.602423 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
3508 11:44:15.605709 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3509 11:44:15.608925 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3510 11:44:15.612068 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3511 11:44:15.618835 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3512 11:44:15.622229 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3513 11:44:15.622319 ==
3514 11:44:15.625400 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 11:44:15.628489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 11:44:15.628574 ==
3517 11:44:15.628640 DQS Delay:
3518 11:44:15.632097 DQS0 = 0, DQS1 = 0
3519 11:44:15.632193 DQM Delay:
3520 11:44:15.635411 DQM0 = 120, DQM1 = 112
3521 11:44:15.635498 DQ Delay:
3522 11:44:15.638660 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3523 11:44:15.641849 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3524 11:44:15.645097 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3525 11:44:15.651444 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3526 11:44:15.651527
3527 11:44:15.651593
3528 11:44:15.651653 ==
3529 11:44:15.654827 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 11:44:15.658068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 11:44:15.658151 ==
3532 11:44:15.658217
3533 11:44:15.658278
3534 11:44:15.661216 TX Vref Scan disable
3535 11:44:15.661299 == TX Byte 0 ==
3536 11:44:15.667820 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3537 11:44:15.671220 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3538 11:44:15.674376 == TX Byte 1 ==
3539 11:44:15.678020 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3540 11:44:15.681366 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3541 11:44:15.681450 ==
3542 11:44:15.684422 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 11:44:15.687905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 11:44:15.690856 ==
3545 11:44:15.701207 TX Vref=22, minBit 0, minWin=25, winSum=411
3546 11:44:15.704240 TX Vref=24, minBit 1, minWin=25, winSum=416
3547 11:44:15.707784 TX Vref=26, minBit 1, minWin=25, winSum=425
3548 11:44:15.710767 TX Vref=28, minBit 3, minWin=25, winSum=423
3549 11:44:15.713933 TX Vref=30, minBit 3, minWin=25, winSum=428
3550 11:44:15.720649 TX Vref=32, minBit 9, minWin=25, winSum=426
3551 11:44:15.723964 [TxChooseVref] Worse bit 3, Min win 25, Win sum 428, Final Vref 30
3552 11:44:15.724048
3553 11:44:15.727232 Final TX Range 1 Vref 30
3554 11:44:15.727316
3555 11:44:15.727381 ==
3556 11:44:15.730592 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 11:44:15.733970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 11:44:15.737041 ==
3559 11:44:15.737135
3560 11:44:15.737201
3561 11:44:15.737261 TX Vref Scan disable
3562 11:44:15.740786 == TX Byte 0 ==
3563 11:44:15.743829 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 11:44:15.750949 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 11:44:15.751032 == TX Byte 1 ==
3566 11:44:15.754095 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3567 11:44:15.760476 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3568 11:44:15.760560
3569 11:44:15.760625 [DATLAT]
3570 11:44:15.760685 Freq=1200, CH1 RK1
3571 11:44:15.760790
3572 11:44:15.763938 DATLAT Default: 0xd
3573 11:44:15.764043 0, 0xFFFF, sum = 0
3574 11:44:15.767141 1, 0xFFFF, sum = 0
3575 11:44:15.770377 2, 0xFFFF, sum = 0
3576 11:44:15.770461 3, 0xFFFF, sum = 0
3577 11:44:15.773923 4, 0xFFFF, sum = 0
3578 11:44:15.774008 5, 0xFFFF, sum = 0
3579 11:44:15.776907 6, 0xFFFF, sum = 0
3580 11:44:15.777049 7, 0xFFFF, sum = 0
3581 11:44:15.780502 8, 0xFFFF, sum = 0
3582 11:44:15.780587 9, 0xFFFF, sum = 0
3583 11:44:15.783830 10, 0xFFFF, sum = 0
3584 11:44:15.783916 11, 0xFFFF, sum = 0
3585 11:44:15.786989 12, 0x0, sum = 1
3586 11:44:15.787073 13, 0x0, sum = 2
3587 11:44:15.790193 14, 0x0, sum = 3
3588 11:44:15.790279 15, 0x0, sum = 4
3589 11:44:15.793650 best_step = 13
3590 11:44:15.793733
3591 11:44:15.793799 ==
3592 11:44:15.796782 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 11:44:15.800106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 11:44:15.800187 ==
3595 11:44:15.803419 RX Vref Scan: 0
3596 11:44:15.803495
3597 11:44:15.803558 RX Vref 0 -> 0, step: 1
3598 11:44:15.803618
3599 11:44:15.806553 RX Delay -13 -> 252, step: 4
3600 11:44:15.813086 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3601 11:44:15.816469 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3602 11:44:15.820103 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3603 11:44:15.823260 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3604 11:44:15.826712 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3605 11:44:15.832850 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3606 11:44:15.836258 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3607 11:44:15.839968 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3608 11:44:15.842727 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3609 11:44:15.846272 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3610 11:44:15.852912 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3611 11:44:15.855891 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3612 11:44:15.859419 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3613 11:44:15.862600 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3614 11:44:15.869406 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3615 11:44:15.872775 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3616 11:44:15.872858 ==
3617 11:44:15.875854 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 11:44:15.879297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 11:44:15.879378 ==
3620 11:44:15.879443 DQS Delay:
3621 11:44:15.882335 DQS0 = 0, DQS1 = 0
3622 11:44:15.882423 DQM Delay:
3623 11:44:15.885933 DQM0 = 119, DQM1 = 112
3624 11:44:15.886007 DQ Delay:
3625 11:44:15.889206 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3626 11:44:15.892323 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3627 11:44:15.895899 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3628 11:44:15.902748 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =120
3629 11:44:15.902832
3630 11:44:15.902896
3631 11:44:15.908947 [DQSOSCAuto] RK1, (LSB)MR18= 0x9ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3632 11:44:15.912255 CH1 RK1: MR19=403, MR18=9EE
3633 11:44:15.918652 CH1_RK1: MR19=0x403, MR18=0x9EE, DQSOSC=406, MR23=63, INC=39, DEC=26
3634 11:44:15.922357 [RxdqsGatingPostProcess] freq 1200
3635 11:44:15.925490 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 11:44:15.928597 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 11:44:15.931991 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 11:44:15.935426 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 11:44:15.938610 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 11:44:15.942240 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 11:44:15.945431 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 11:44:15.948447 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 11:44:15.952106 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 11:44:15.955141 Pre-setting of DQS Precalculation
3645 11:44:15.958662 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 11:44:15.968545 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 11:44:15.975143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 11:44:15.975222
3649 11:44:15.975286
3650 11:44:15.978455 [Calibration Summary] 2400 Mbps
3651 11:44:15.978530 CH 0, Rank 0
3652 11:44:15.981518 SW Impedance : PASS
3653 11:44:15.981591 DUTY Scan : NO K
3654 11:44:15.984828 ZQ Calibration : PASS
3655 11:44:15.988465 Jitter Meter : NO K
3656 11:44:15.988540 CBT Training : PASS
3657 11:44:15.991678 Write leveling : PASS
3658 11:44:15.994671 RX DQS gating : PASS
3659 11:44:15.994757 RX DQ/DQS(RDDQC) : PASS
3660 11:44:15.997892 TX DQ/DQS : PASS
3661 11:44:16.001510 RX DATLAT : PASS
3662 11:44:16.001592 RX DQ/DQS(Engine): PASS
3663 11:44:16.004632 TX OE : NO K
3664 11:44:16.004714 All Pass.
3665 11:44:16.004778
3666 11:44:16.007794 CH 0, Rank 1
3667 11:44:16.007865 SW Impedance : PASS
3668 11:44:16.011213 DUTY Scan : NO K
3669 11:44:16.014442 ZQ Calibration : PASS
3670 11:44:16.014523 Jitter Meter : NO K
3671 11:44:16.017632 CBT Training : PASS
3672 11:44:16.020952 Write leveling : PASS
3673 11:44:16.021068 RX DQS gating : PASS
3674 11:44:16.024285 RX DQ/DQS(RDDQC) : PASS
3675 11:44:16.027489 TX DQ/DQS : PASS
3676 11:44:16.027570 RX DATLAT : PASS
3677 11:44:16.030758 RX DQ/DQS(Engine): PASS
3678 11:44:16.030829 TX OE : NO K
3679 11:44:16.034471 All Pass.
3680 11:44:16.034553
3681 11:44:16.034625 CH 1, Rank 0
3682 11:44:16.037313 SW Impedance : PASS
3683 11:44:16.037395 DUTY Scan : NO K
3684 11:44:16.040713 ZQ Calibration : PASS
3685 11:44:16.044255 Jitter Meter : NO K
3686 11:44:16.044337 CBT Training : PASS
3687 11:44:16.047558 Write leveling : PASS
3688 11:44:16.050652 RX DQS gating : PASS
3689 11:44:16.050722 RX DQ/DQS(RDDQC) : PASS
3690 11:44:16.053861 TX DQ/DQS : PASS
3691 11:44:16.057275 RX DATLAT : PASS
3692 11:44:16.057361 RX DQ/DQS(Engine): PASS
3693 11:44:16.060590 TX OE : NO K
3694 11:44:16.060680 All Pass.
3695 11:44:16.060744
3696 11:44:16.064083 CH 1, Rank 1
3697 11:44:16.064173 SW Impedance : PASS
3698 11:44:16.067293 DUTY Scan : NO K
3699 11:44:16.070548 ZQ Calibration : PASS
3700 11:44:16.070630 Jitter Meter : NO K
3701 11:44:16.073868 CBT Training : PASS
3702 11:44:16.076877 Write leveling : PASS
3703 11:44:16.076986 RX DQS gating : PASS
3704 11:44:16.080453 RX DQ/DQS(RDDQC) : PASS
3705 11:44:16.083664 TX DQ/DQS : PASS
3706 11:44:16.083742 RX DATLAT : PASS
3707 11:44:16.086980 RX DQ/DQS(Engine): PASS
3708 11:44:16.090501 TX OE : NO K
3709 11:44:16.090585 All Pass.
3710 11:44:16.090652
3711 11:44:16.090712 DramC Write-DBI off
3712 11:44:16.093695 PER_BANK_REFRESH: Hybrid Mode
3713 11:44:16.096932 TX_TRACKING: ON
3714 11:44:16.103645 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 11:44:16.107206 [FAST_K] Save calibration result to emmc
3716 11:44:16.113662 dramc_set_vcore_voltage set vcore to 650000
3717 11:44:16.113752 Read voltage for 600, 5
3718 11:44:16.117123 Vio18 = 0
3719 11:44:16.117201 Vcore = 650000
3720 11:44:16.117272 Vdram = 0
3721 11:44:16.117340 Vddq = 0
3722 11:44:16.120224 Vmddr = 0
3723 11:44:16.123335 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 11:44:16.130143 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 11:44:16.133235 MEM_TYPE=3, freq_sel=19
3726 11:44:16.136867 sv_algorithm_assistance_LP4_1600
3727 11:44:16.139918 ============ PULL DRAM RESETB DOWN ============
3728 11:44:16.143033 ========== PULL DRAM RESETB DOWN end =========
3729 11:44:16.146742 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 11:44:16.149952 ===================================
3731 11:44:16.152940 LPDDR4 DRAM CONFIGURATION
3732 11:44:16.156350 ===================================
3733 11:44:16.159578 EX_ROW_EN[0] = 0x0
3734 11:44:16.159653 EX_ROW_EN[1] = 0x0
3735 11:44:16.162767 LP4Y_EN = 0x0
3736 11:44:16.162859 WORK_FSP = 0x0
3737 11:44:16.166203 WL = 0x2
3738 11:44:16.166289 RL = 0x2
3739 11:44:16.169405 BL = 0x2
3740 11:44:16.172574 RPST = 0x0
3741 11:44:16.172646 RD_PRE = 0x0
3742 11:44:16.176231 WR_PRE = 0x1
3743 11:44:16.176306 WR_PST = 0x0
3744 11:44:16.179245 DBI_WR = 0x0
3745 11:44:16.179322 DBI_RD = 0x0
3746 11:44:16.182508 OTF = 0x1
3747 11:44:16.186181 ===================================
3748 11:44:16.189126 ===================================
3749 11:44:16.189220 ANA top config
3750 11:44:16.192702 ===================================
3751 11:44:16.195763 DLL_ASYNC_EN = 0
3752 11:44:16.199266 ALL_SLAVE_EN = 1
3753 11:44:16.199353 NEW_RANK_MODE = 1
3754 11:44:16.202400 DLL_IDLE_MODE = 1
3755 11:44:16.205825 LP45_APHY_COMB_EN = 1
3756 11:44:16.208923 TX_ODT_DIS = 1
3757 11:44:16.212386 NEW_8X_MODE = 1
3758 11:44:16.212545 ===================================
3759 11:44:16.215708 ===================================
3760 11:44:16.219120 data_rate = 1200
3761 11:44:16.222262 CKR = 1
3762 11:44:16.225968 DQ_P2S_RATIO = 8
3763 11:44:16.229122 ===================================
3764 11:44:16.232074 CA_P2S_RATIO = 8
3765 11:44:16.235660 DQ_CA_OPEN = 0
3766 11:44:16.238951 DQ_SEMI_OPEN = 0
3767 11:44:16.239061 CA_SEMI_OPEN = 0
3768 11:44:16.242439 CA_FULL_RATE = 0
3769 11:44:16.245567 DQ_CKDIV4_EN = 1
3770 11:44:16.248907 CA_CKDIV4_EN = 1
3771 11:44:16.252565 CA_PREDIV_EN = 0
3772 11:44:16.255642 PH8_DLY = 0
3773 11:44:16.255729 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 11:44:16.258842 DQ_AAMCK_DIV = 4
3775 11:44:16.262051 CA_AAMCK_DIV = 4
3776 11:44:16.265145 CA_ADMCK_DIV = 4
3777 11:44:16.268838 DQ_TRACK_CA_EN = 0
3778 11:44:16.271875 CA_PICK = 600
3779 11:44:16.275026 CA_MCKIO = 600
3780 11:44:16.275110 MCKIO_SEMI = 0
3781 11:44:16.278357 PLL_FREQ = 2288
3782 11:44:16.281860 DQ_UI_PI_RATIO = 32
3783 11:44:16.285226 CA_UI_PI_RATIO = 0
3784 11:44:16.288417 ===================================
3785 11:44:16.291867 ===================================
3786 11:44:16.294843 memory_type:LPDDR4
3787 11:44:16.294959 GP_NUM : 10
3788 11:44:16.298522 SRAM_EN : 1
3789 11:44:16.301814 MD32_EN : 0
3790 11:44:16.304943 ===================================
3791 11:44:16.305047 [ANA_INIT] >>>>>>>>>>>>>>
3792 11:44:16.308188 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 11:44:16.311854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 11:44:16.314999 ===================================
3795 11:44:16.318353 data_rate = 1200,PCW = 0X5800
3796 11:44:16.321516 ===================================
3797 11:44:16.324596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 11:44:16.331550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 11:44:16.334599 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 11:44:16.341115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 11:44:16.344623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 11:44:16.347940 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 11:44:16.348101 [ANA_INIT] flow start
3804 11:44:16.350918 [ANA_INIT] PLL >>>>>>>>
3805 11:44:16.354442 [ANA_INIT] PLL <<<<<<<<
3806 11:44:16.357760 [ANA_INIT] MIDPI >>>>>>>>
3807 11:44:16.357844 [ANA_INIT] MIDPI <<<<<<<<
3808 11:44:16.360897 [ANA_INIT] DLL >>>>>>>>
3809 11:44:16.364015 [ANA_INIT] flow end
3810 11:44:16.367675 ============ LP4 DIFF to SE enter ============
3811 11:44:16.370904 ============ LP4 DIFF to SE exit ============
3812 11:44:16.373931 [ANA_INIT] <<<<<<<<<<<<<
3813 11:44:16.377694 [Flow] Enable top DCM control >>>>>
3814 11:44:16.381016 [Flow] Enable top DCM control <<<<<
3815 11:44:16.384084 Enable DLL master slave shuffle
3816 11:44:16.387336 ==============================================================
3817 11:44:16.390503 Gating Mode config
3818 11:44:16.397209 ==============================================================
3819 11:44:16.397295 Config description:
3820 11:44:16.407106 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 11:44:16.413649 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 11:44:16.417143 SELPH_MODE 0: By rank 1: By Phase
3823 11:44:16.423694 ==============================================================
3824 11:44:16.427165 GAT_TRACK_EN = 1
3825 11:44:16.430335 RX_GATING_MODE = 2
3826 11:44:16.433576 RX_GATING_TRACK_MODE = 2
3827 11:44:16.437076 SELPH_MODE = 1
3828 11:44:16.440223 PICG_EARLY_EN = 1
3829 11:44:16.443440 VALID_LAT_VALUE = 1
3830 11:44:16.446768 ==============================================================
3831 11:44:16.450359 Enter into Gating configuration >>>>
3832 11:44:16.453382 Exit from Gating configuration <<<<
3833 11:44:16.456887 Enter into DVFS_PRE_config >>>>>
3834 11:44:16.470207 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 11:44:16.473423 Exit from DVFS_PRE_config <<<<<
3836 11:44:16.476617 Enter into PICG configuration >>>>
3837 11:44:16.476707 Exit from PICG configuration <<<<
3838 11:44:16.479771 [RX_INPUT] configuration >>>>>
3839 11:44:16.483381 [RX_INPUT] configuration <<<<<
3840 11:44:16.489964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 11:44:16.492868 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 11:44:16.499861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 11:44:16.506450 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 11:44:16.512831 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 11:44:16.519518 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 11:44:16.522605 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 11:44:16.525830 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 11:44:16.532515 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 11:44:16.535714 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 11:44:16.539202 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 11:44:16.542632 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 11:44:16.545852 ===================================
3853 11:44:16.549096 LPDDR4 DRAM CONFIGURATION
3854 11:44:16.552409 ===================================
3855 11:44:16.555450 EX_ROW_EN[0] = 0x0
3856 11:44:16.555533 EX_ROW_EN[1] = 0x0
3857 11:44:16.558942 LP4Y_EN = 0x0
3858 11:44:16.559031 WORK_FSP = 0x0
3859 11:44:16.562128 WL = 0x2
3860 11:44:16.562240 RL = 0x2
3861 11:44:16.565383 BL = 0x2
3862 11:44:16.565467 RPST = 0x0
3863 11:44:16.568614 RD_PRE = 0x0
3864 11:44:16.572255 WR_PRE = 0x1
3865 11:44:16.572380 WR_PST = 0x0
3866 11:44:16.575514 DBI_WR = 0x0
3867 11:44:16.575604 DBI_RD = 0x0
3868 11:44:16.578747 OTF = 0x1
3869 11:44:16.582177 ===================================
3870 11:44:16.585196 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 11:44:16.588853 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 11:44:16.592030 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 11:44:16.595216 ===================================
3874 11:44:16.598887 LPDDR4 DRAM CONFIGURATION
3875 11:44:16.602163 ===================================
3876 11:44:16.605330 EX_ROW_EN[0] = 0x10
3877 11:44:16.605427 EX_ROW_EN[1] = 0x0
3878 11:44:16.608388 LP4Y_EN = 0x0
3879 11:44:16.608471 WORK_FSP = 0x0
3880 11:44:16.612000 WL = 0x2
3881 11:44:16.612104 RL = 0x2
3882 11:44:16.615259 BL = 0x2
3883 11:44:16.615343 RPST = 0x0
3884 11:44:16.618533 RD_PRE = 0x0
3885 11:44:16.621880 WR_PRE = 0x1
3886 11:44:16.621962 WR_PST = 0x0
3887 11:44:16.625128 DBI_WR = 0x0
3888 11:44:16.625261 DBI_RD = 0x0
3889 11:44:16.628188 OTF = 0x1
3890 11:44:16.631935 ===================================
3891 11:44:16.634869 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 11:44:16.640218 nWR fixed to 30
3893 11:44:16.643422 [ModeRegInit_LP4] CH0 RK0
3894 11:44:16.643527 [ModeRegInit_LP4] CH0 RK1
3895 11:44:16.646830 [ModeRegInit_LP4] CH1 RK0
3896 11:44:16.649962 [ModeRegInit_LP4] CH1 RK1
3897 11:44:16.650062 match AC timing 17
3898 11:44:16.656949 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 11:44:16.659925 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 11:44:16.663457 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 11:44:16.670310 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 11:44:16.673431 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 11:44:16.673509 ==
3904 11:44:16.676787 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 11:44:16.680031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 11:44:16.680104 ==
3907 11:44:16.686889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 11:44:16.693197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3909 11:44:16.696828 [CA 0] Center 35 (5~66) winsize 62
3910 11:44:16.700081 [CA 1] Center 36 (6~67) winsize 62
3911 11:44:16.703279 [CA 2] Center 34 (4~65) winsize 62
3912 11:44:16.706466 [CA 3] Center 34 (3~65) winsize 63
3913 11:44:16.709796 [CA 4] Center 33 (3~64) winsize 62
3914 11:44:16.713305 [CA 5] Center 33 (2~64) winsize 63
3915 11:44:16.713390
3916 11:44:16.716383 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3917 11:44:16.716485
3918 11:44:16.719652 [CATrainingPosCal] consider 1 rank data
3919 11:44:16.722891 u2DelayCellTimex100 = 270/100 ps
3920 11:44:16.726581 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3921 11:44:16.729748 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3922 11:44:16.732874 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3923 11:44:16.736144 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3924 11:44:16.742967 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3925 11:44:16.746044 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3926 11:44:16.746156
3927 11:44:16.749165 CA PerBit enable=1, Macro0, CA PI delay=33
3928 11:44:16.749243
3929 11:44:16.752622 [CBTSetCACLKResult] CA Dly = 33
3930 11:44:16.752732 CS Dly: 5 (0~36)
3931 11:44:16.752826 ==
3932 11:44:16.755905 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 11:44:16.762876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 11:44:16.762984 ==
3935 11:44:16.765970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 11:44:16.772749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 11:44:16.775899 [CA 0] Center 36 (6~67) winsize 62
3938 11:44:16.779120 [CA 1] Center 36 (6~67) winsize 62
3939 11:44:16.782296 [CA 2] Center 34 (4~65) winsize 62
3940 11:44:16.785582 [CA 3] Center 34 (4~65) winsize 62
3941 11:44:16.789205 [CA 4] Center 34 (3~65) winsize 63
3942 11:44:16.792641 [CA 5] Center 33 (3~64) winsize 62
3943 11:44:16.792755
3944 11:44:16.795835 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 11:44:16.795919
3946 11:44:16.799026 [CATrainingPosCal] consider 2 rank data
3947 11:44:16.802228 u2DelayCellTimex100 = 270/100 ps
3948 11:44:16.805807 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 11:44:16.809096 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3950 11:44:16.815447 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 11:44:16.818868 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 11:44:16.821916 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 11:44:16.825491 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 11:44:16.825575
3955 11:44:16.828839 CA PerBit enable=1, Macro0, CA PI delay=33
3956 11:44:16.828923
3957 11:44:16.832084 [CBTSetCACLKResult] CA Dly = 33
3958 11:44:16.832167 CS Dly: 5 (0~37)
3959 11:44:16.835534
3960 11:44:16.838766 ----->DramcWriteLeveling(PI) begin...
3961 11:44:16.838850 ==
3962 11:44:16.841976 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 11:44:16.845068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 11:44:16.845150 ==
3965 11:44:16.848566 Write leveling (Byte 0): 34 => 34
3966 11:44:16.851753 Write leveling (Byte 1): 30 => 30
3967 11:44:16.855358 DramcWriteLeveling(PI) end<-----
3968 11:44:16.855438
3969 11:44:16.855523 ==
3970 11:44:16.858448 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 11:44:16.861730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 11:44:16.861837 ==
3973 11:44:16.864995 [Gating] SW mode calibration
3974 11:44:16.871684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 11:44:16.878191 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 11:44:16.881462 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 11:44:16.885155 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 11:44:16.891682 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 11:44:16.894908 0 9 12 | B1->B0 | 3333 2828 | 1 0 | (1 0) (1 0)
3980 11:44:16.898322 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
3981 11:44:16.905250 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 11:44:16.908488 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 11:44:16.911751 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 11:44:16.918079 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 11:44:16.921634 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 11:44:16.924802 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3987 11:44:16.931227 0 10 12 | B1->B0 | 2929 3c3c | 0 0 | (0 0) (0 0)
3988 11:44:16.934900 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3989 11:44:16.938102 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 11:44:16.944468 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 11:44:16.948026 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:44:16.951172 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 11:44:16.954850 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 11:44:16.960958 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 11:44:16.964608 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3996 11:44:16.971079 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3997 11:44:16.974108 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:44:16.977587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:44:16.984348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:44:16.987660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:44:16.990930 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:44:16.997231 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:44:17.000406 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:44:17.003910 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:44:17.010352 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:44:17.014038 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:44:17.017752 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:44:17.020512 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:44:17.027295 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:44:17.030622 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:44:17.033793 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4012 11:44:17.036883 Total UI for P1: 0, mck2ui 16
4013 11:44:17.040463 best dqsien dly found for B0: ( 0, 13, 10)
4014 11:44:17.046854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 11:44:17.049980 Total UI for P1: 0, mck2ui 16
4016 11:44:17.053439 best dqsien dly found for B1: ( 0, 13, 12)
4017 11:44:17.056873 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4018 11:44:17.060079 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4019 11:44:17.060163
4020 11:44:17.063351 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4021 11:44:17.066662 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4022 11:44:17.069844 [Gating] SW calibration Done
4023 11:44:17.069922 ==
4024 11:44:17.072972 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 11:44:17.076580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 11:44:17.079594 ==
4027 11:44:17.079682 RX Vref Scan: 0
4028 11:44:17.079764
4029 11:44:17.083057 RX Vref 0 -> 0, step: 1
4030 11:44:17.083190
4031 11:44:17.086267 RX Delay -230 -> 252, step: 16
4032 11:44:17.089864 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4033 11:44:17.093114 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4034 11:44:17.096407 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 11:44:17.102708 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4036 11:44:17.106225 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4037 11:44:17.109380 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 11:44:17.112541 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4039 11:44:17.115864 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4040 11:44:17.122624 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4041 11:44:17.125905 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4042 11:44:17.129391 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 11:44:17.132431 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4044 11:44:17.138970 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4045 11:44:17.142203 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4046 11:44:17.145825 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4047 11:44:17.149067 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4048 11:44:17.149152 ==
4049 11:44:17.152263 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 11:44:17.159024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 11:44:17.159138 ==
4052 11:44:17.159207 DQS Delay:
4053 11:44:17.162450 DQS0 = 0, DQS1 = 0
4054 11:44:17.162536 DQM Delay:
4055 11:44:17.162603 DQM0 = 53, DQM1 = 40
4056 11:44:17.165553 DQ Delay:
4057 11:44:17.169116 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4058 11:44:17.172161 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4059 11:44:17.175366 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4060 11:44:17.179166 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4061 11:44:17.179245
4062 11:44:17.179309
4063 11:44:17.179368 ==
4064 11:44:17.182115 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 11:44:17.185694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 11:44:17.185773 ==
4067 11:44:17.185837
4068 11:44:17.185896
4069 11:44:17.188737 TX Vref Scan disable
4070 11:44:17.192391 == TX Byte 0 ==
4071 11:44:17.195616 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4072 11:44:17.198893 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4073 11:44:17.202048 == TX Byte 1 ==
4074 11:44:17.205173 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4075 11:44:17.208365 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4076 11:44:17.208471 ==
4077 11:44:17.211874 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 11:44:17.214997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 11:44:17.218315 ==
4080 11:44:17.218416
4081 11:44:17.218507
4082 11:44:17.218578 TX Vref Scan disable
4083 11:44:17.222426 == TX Byte 0 ==
4084 11:44:17.225637 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4085 11:44:17.232534 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4086 11:44:17.232635 == TX Byte 1 ==
4087 11:44:17.235650 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4088 11:44:17.242195 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4089 11:44:17.242297
4090 11:44:17.242365 [DATLAT]
4091 11:44:17.242426 Freq=600, CH0 RK0
4092 11:44:17.242484
4093 11:44:17.245927 DATLAT Default: 0x9
4094 11:44:17.245995 0, 0xFFFF, sum = 0
4095 11:44:17.248717 1, 0xFFFF, sum = 0
4096 11:44:17.252159 2, 0xFFFF, sum = 0
4097 11:44:17.252262 3, 0xFFFF, sum = 0
4098 11:44:17.255411 4, 0xFFFF, sum = 0
4099 11:44:17.255531 5, 0xFFFF, sum = 0
4100 11:44:17.258765 6, 0xFFFF, sum = 0
4101 11:44:17.258872 7, 0xFFFF, sum = 0
4102 11:44:17.262426 8, 0x0, sum = 1
4103 11:44:17.262501 9, 0x0, sum = 2
4104 11:44:17.262565 10, 0x0, sum = 3
4105 11:44:17.265431 11, 0x0, sum = 4
4106 11:44:17.265539 best_step = 9
4107 11:44:17.265629
4108 11:44:17.265719 ==
4109 11:44:17.268964 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 11:44:17.275201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 11:44:17.275288 ==
4112 11:44:17.275356 RX Vref Scan: 1
4113 11:44:17.275417
4114 11:44:17.278828 RX Vref 0 -> 0, step: 1
4115 11:44:17.278947
4116 11:44:17.282199 RX Delay -163 -> 252, step: 8
4117 11:44:17.282303
4118 11:44:17.285360 Set Vref, RX VrefLevel [Byte0]: 60
4119 11:44:17.288847 [Byte1]: 52
4120 11:44:17.288950
4121 11:44:17.291925 Final RX Vref Byte 0 = 60 to rank0
4122 11:44:17.295161 Final RX Vref Byte 1 = 52 to rank0
4123 11:44:17.298435 Final RX Vref Byte 0 = 60 to rank1
4124 11:44:17.302047 Final RX Vref Byte 1 = 52 to rank1==
4125 11:44:17.305358 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 11:44:17.308568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 11:44:17.308708 ==
4128 11:44:17.311842 DQS Delay:
4129 11:44:17.311925 DQS0 = 0, DQS1 = 0
4130 11:44:17.315004 DQM Delay:
4131 11:44:17.315086 DQM0 = 49, DQM1 = 38
4132 11:44:17.315169 DQ Delay:
4133 11:44:17.318416 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =48
4134 11:44:17.321723 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4135 11:44:17.324865 DQ8 =32, DQ9 =24, DQ10 =40, DQ11 =32
4136 11:44:17.328462 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =48
4137 11:44:17.328590
4138 11:44:17.328689
4139 11:44:17.338295 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e58, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4140 11:44:17.341501 CH0 RK0: MR19=808, MR18=5E58
4141 11:44:17.347980 CH0_RK0: MR19=0x808, MR18=0x5E58, DQSOSC=392, MR23=63, INC=170, DEC=113
4142 11:44:17.348146
4143 11:44:17.351643 ----->DramcWriteLeveling(PI) begin...
4144 11:44:17.351788 ==
4145 11:44:17.354681 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 11:44:17.357806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 11:44:17.357905 ==
4148 11:44:17.361466 Write leveling (Byte 0): 33 => 33
4149 11:44:17.364555 Write leveling (Byte 1): 30 => 30
4150 11:44:17.368036 DramcWriteLeveling(PI) end<-----
4151 11:44:17.368130
4152 11:44:17.368197 ==
4153 11:44:17.371121 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 11:44:17.374373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 11:44:17.374457 ==
4156 11:44:17.377853 [Gating] SW mode calibration
4157 11:44:17.384283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 11:44:17.390965 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 11:44:17.394452 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 11:44:17.397910 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 11:44:17.404296 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 11:44:17.407483 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
4163 11:44:17.411018 0 9 16 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
4164 11:44:17.417363 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 11:44:17.420935 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 11:44:17.424295 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 11:44:17.431018 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 11:44:17.434223 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 11:44:17.437390 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 11:44:17.444091 0 10 12 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
4171 11:44:17.447378 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4172 11:44:17.450475 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 11:44:17.457286 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 11:44:17.460435 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:44:17.463854 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 11:44:17.470712 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 11:44:17.473756 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 11:44:17.476903 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4179 11:44:17.483802 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4180 11:44:17.486901 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:44:17.490145 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:44:17.496881 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:44:17.500269 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:44:17.503664 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:44:17.509841 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:44:17.513127 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:44:17.516272 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:44:17.523086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:44:17.526284 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:44:17.529849 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:44:17.536594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:44:17.539744 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:44:17.542994 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4194 11:44:17.549730 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4195 11:44:17.549833 Total UI for P1: 0, mck2ui 16
4196 11:44:17.556215 best dqsien dly found for B0: ( 0, 13, 10)
4197 11:44:17.559534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 11:44:17.562719 Total UI for P1: 0, mck2ui 16
4199 11:44:17.566290 best dqsien dly found for B1: ( 0, 13, 10)
4200 11:44:17.569654 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4201 11:44:17.572907 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4202 11:44:17.573015
4203 11:44:17.576111 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4204 11:44:17.579366 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4205 11:44:17.582603 [Gating] SW calibration Done
4206 11:44:17.582678 ==
4207 11:44:17.586058 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 11:44:17.592451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 11:44:17.592529 ==
4210 11:44:17.592628 RX Vref Scan: 0
4211 11:44:17.592701
4212 11:44:17.595704 RX Vref 0 -> 0, step: 1
4213 11:44:17.595773
4214 11:44:17.598940 RX Delay -230 -> 252, step: 16
4215 11:44:17.602367 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4216 11:44:17.605556 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4217 11:44:17.609148 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4218 11:44:17.615354 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4219 11:44:17.618654 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4220 11:44:17.622497 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4221 11:44:17.625621 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4222 11:44:17.632330 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4223 11:44:17.635555 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4224 11:44:17.638870 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4225 11:44:17.642122 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4226 11:44:17.648426 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4227 11:44:17.651610 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4228 11:44:17.654899 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4229 11:44:17.658630 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4230 11:44:17.664824 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4231 11:44:17.664950 ==
4232 11:44:17.668438 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 11:44:17.671722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 11:44:17.671807 ==
4235 11:44:17.671873 DQS Delay:
4236 11:44:17.674750 DQS0 = 0, DQS1 = 0
4237 11:44:17.674859 DQM Delay:
4238 11:44:17.677865 DQM0 = 50, DQM1 = 42
4239 11:44:17.677944 DQ Delay:
4240 11:44:17.681362 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4241 11:44:17.684647 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4242 11:44:17.688139 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4243 11:44:17.691285 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4244 11:44:17.691422
4245 11:44:17.691515
4246 11:44:17.691607 ==
4247 11:44:17.694774 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 11:44:17.697889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 11:44:17.698004 ==
4250 11:44:17.701474
4251 11:44:17.701558
4252 11:44:17.701731 TX Vref Scan disable
4253 11:44:17.704538 == TX Byte 0 ==
4254 11:44:17.707968 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4255 11:44:17.711167 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4256 11:44:17.714495 == TX Byte 1 ==
4257 11:44:17.717602 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4258 11:44:17.720877 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4259 11:44:17.724195 ==
4260 11:44:17.727515 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 11:44:17.731016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 11:44:17.731093 ==
4263 11:44:17.731228
4264 11:44:17.731295
4265 11:44:17.733956 TX Vref Scan disable
4266 11:44:17.734031 == TX Byte 0 ==
4267 11:44:17.740604 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4268 11:44:17.743855 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4269 11:44:17.747478 == TX Byte 1 ==
4270 11:44:17.750777 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4271 11:44:17.753856 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4272 11:44:17.753960
4273 11:44:17.754079 [DATLAT]
4274 11:44:17.757089 Freq=600, CH0 RK1
4275 11:44:17.757159
4276 11:44:17.760382 DATLAT Default: 0x9
4277 11:44:17.760503 0, 0xFFFF, sum = 0
4278 11:44:17.764025 1, 0xFFFF, sum = 0
4279 11:44:17.764109 2, 0xFFFF, sum = 0
4280 11:44:17.767252 3, 0xFFFF, sum = 0
4281 11:44:17.767349 4, 0xFFFF, sum = 0
4282 11:44:17.770362 5, 0xFFFF, sum = 0
4283 11:44:17.770434 6, 0xFFFF, sum = 0
4284 11:44:17.773695 7, 0xFFFF, sum = 0
4285 11:44:17.773784 8, 0x0, sum = 1
4286 11:44:17.776796 9, 0x0, sum = 2
4287 11:44:17.776871 10, 0x0, sum = 3
4288 11:44:17.780377 11, 0x0, sum = 4
4289 11:44:17.780481 best_step = 9
4290 11:44:17.780571
4291 11:44:17.780656 ==
4292 11:44:17.783571 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 11:44:17.786943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 11:44:17.787021 ==
4295 11:44:17.790075 RX Vref Scan: 0
4296 11:44:17.790151
4297 11:44:17.793816 RX Vref 0 -> 0, step: 1
4298 11:44:17.793887
4299 11:44:17.793947 RX Delay -179 -> 252, step: 8
4300 11:44:17.801518 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4301 11:44:17.804854 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4302 11:44:17.807914 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4303 11:44:17.811095 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4304 11:44:17.814621 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4305 11:44:17.821396 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4306 11:44:17.824447 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4307 11:44:17.827679 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4308 11:44:17.831016 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4309 11:44:17.837922 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4310 11:44:17.841076 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4311 11:44:17.844208 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4312 11:44:17.847386 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4313 11:44:17.854325 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4314 11:44:17.857464 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4315 11:44:17.860528 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4316 11:44:17.860611 ==
4317 11:44:17.864156 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 11:44:17.867397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 11:44:17.867475 ==
4320 11:44:17.870701 DQS Delay:
4321 11:44:17.870777 DQS0 = 0, DQS1 = 0
4322 11:44:17.873840 DQM Delay:
4323 11:44:17.873927 DQM0 = 48, DQM1 = 40
4324 11:44:17.873990 DQ Delay:
4325 11:44:17.877201 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4326 11:44:17.880543 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4327 11:44:17.883721 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4328 11:44:17.887181 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =52
4329 11:44:17.887263
4330 11:44:17.887335
4331 11:44:17.897065 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4332 11:44:17.900646 CH0 RK1: MR19=808, MR18=5F2D
4333 11:44:17.907034 CH0_RK1: MR19=0x808, MR18=0x5F2D, DQSOSC=391, MR23=63, INC=171, DEC=114
4334 11:44:17.907112 [RxdqsGatingPostProcess] freq 600
4335 11:44:17.913665 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4336 11:44:17.916970 Pre-setting of DQS Precalculation
4337 11:44:17.920356 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4338 11:44:17.923624 ==
4339 11:44:17.923700 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 11:44:17.930667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 11:44:17.930795 ==
4342 11:44:17.933346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4343 11:44:17.940168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4344 11:44:17.943911 [CA 0] Center 35 (5~65) winsize 61
4345 11:44:17.947110 [CA 1] Center 35 (5~66) winsize 62
4346 11:44:17.950417 [CA 2] Center 34 (4~65) winsize 62
4347 11:44:17.953699 [CA 3] Center 33 (3~64) winsize 62
4348 11:44:17.957332 [CA 4] Center 33 (3~64) winsize 62
4349 11:44:17.960554 [CA 5] Center 33 (3~64) winsize 62
4350 11:44:17.960638
4351 11:44:17.963679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4352 11:44:17.963788
4353 11:44:17.967361 [CATrainingPosCal] consider 1 rank data
4354 11:44:17.970588 u2DelayCellTimex100 = 270/100 ps
4355 11:44:17.973931 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4356 11:44:17.980379 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4357 11:44:17.983720 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 11:44:17.986875 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4359 11:44:17.990006 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4360 11:44:17.993699 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 11:44:17.993808
4362 11:44:17.996762 CA PerBit enable=1, Macro0, CA PI delay=33
4363 11:44:17.996866
4364 11:44:18.000365 [CBTSetCACLKResult] CA Dly = 33
4365 11:44:18.003344 CS Dly: 5 (0~36)
4366 11:44:18.003420 ==
4367 11:44:18.006540 Dram Type= 6, Freq= 0, CH_1, rank 1
4368 11:44:18.010147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 11:44:18.010228 ==
4370 11:44:18.016720 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 11:44:18.019704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4372 11:44:18.023903 [CA 0] Center 35 (5~66) winsize 62
4373 11:44:18.027121 [CA 1] Center 35 (5~66) winsize 62
4374 11:44:18.030392 [CA 2] Center 34 (4~65) winsize 62
4375 11:44:18.033831 [CA 3] Center 34 (4~65) winsize 62
4376 11:44:18.036953 [CA 4] Center 34 (4~65) winsize 62
4377 11:44:18.040608 [CA 5] Center 34 (3~65) winsize 63
4378 11:44:18.040688
4379 11:44:18.043877 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4380 11:44:18.043962
4381 11:44:18.046985 [CATrainingPosCal] consider 2 rank data
4382 11:44:18.050378 u2DelayCellTimex100 = 270/100 ps
4383 11:44:18.053479 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4384 11:44:18.060131 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 11:44:18.063687 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 11:44:18.066718 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4387 11:44:18.070216 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4388 11:44:18.073683 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 11:44:18.073760
4390 11:44:18.076867 CA PerBit enable=1, Macro0, CA PI delay=33
4391 11:44:18.076973
4392 11:44:18.080132 [CBTSetCACLKResult] CA Dly = 33
4393 11:44:18.083360 CS Dly: 5 (0~37)
4394 11:44:18.083435
4395 11:44:18.086600 ----->DramcWriteLeveling(PI) begin...
4396 11:44:18.086683 ==
4397 11:44:18.089889 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 11:44:18.093172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 11:44:18.093260 ==
4400 11:44:18.096446 Write leveling (Byte 0): 30 => 30
4401 11:44:18.099672 Write leveling (Byte 1): 30 => 30
4402 11:44:18.103013 DramcWriteLeveling(PI) end<-----
4403 11:44:18.103091
4404 11:44:18.103171 ==
4405 11:44:18.106654 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 11:44:18.109942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 11:44:18.110025 ==
4408 11:44:18.113013 [Gating] SW mode calibration
4409 11:44:18.120155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4410 11:44:18.126444 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4411 11:44:18.129972 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 11:44:18.132956 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 11:44:18.139748 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4414 11:44:18.142875 0 9 12 | B1->B0 | 2f2f 2c2c | 0 0 | (1 1) (1 1)
4415 11:44:18.146069 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 11:44:18.152748 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 11:44:18.156252 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 11:44:18.159439 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:44:18.165889 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 11:44:18.169613 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 11:44:18.172608 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4422 11:44:18.179339 0 10 12 | B1->B0 | 3838 4242 | 0 0 | (0 0) (0 0)
4423 11:44:18.182782 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 11:44:18.186002 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:44:18.192405 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:44:18.195705 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:44:18.198930 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:44:18.205666 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 11:44:18.209135 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 11:44:18.212334 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4431 11:44:18.218808 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:44:18.222142 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:44:18.225669 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:44:18.232038 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:44:18.235594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:44:18.238834 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:44:18.245309 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:44:18.248883 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:44:18.252094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:44:18.258789 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:44:18.261786 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:44:18.265008 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:44:18.271956 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:44:18.275062 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:44:18.278262 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4446 11:44:18.284775 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 11:44:18.284892 Total UI for P1: 0, mck2ui 16
4448 11:44:18.291753 best dqsien dly found for B0: ( 0, 13, 8)
4449 11:44:18.291837 Total UI for P1: 0, mck2ui 16
4450 11:44:18.298339 best dqsien dly found for B1: ( 0, 13, 10)
4451 11:44:18.301529 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4452 11:44:18.304734 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4453 11:44:18.304817
4454 11:44:18.308418 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4455 11:44:18.311395 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4456 11:44:18.314958 [Gating] SW calibration Done
4457 11:44:18.315041 ==
4458 11:44:18.318054 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 11:44:18.321511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 11:44:18.321586 ==
4461 11:44:18.324609 RX Vref Scan: 0
4462 11:44:18.324707
4463 11:44:18.324799 RX Vref 0 -> 0, step: 1
4464 11:44:18.324886
4465 11:44:18.327975 RX Delay -230 -> 252, step: 16
4466 11:44:18.334679 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4467 11:44:18.337527 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4468 11:44:18.340807 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4469 11:44:18.344366 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4470 11:44:18.347518 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4471 11:44:18.354181 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4472 11:44:18.357314 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4473 11:44:18.360616 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4474 11:44:18.364135 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4475 11:44:18.370587 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4476 11:44:18.373822 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4477 11:44:18.377349 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4478 11:44:18.380395 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4479 11:44:18.387261 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4480 11:44:18.390412 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4481 11:44:18.393706 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4482 11:44:18.393789 ==
4483 11:44:18.396940 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 11:44:18.400435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 11:44:18.403773 ==
4486 11:44:18.403857 DQS Delay:
4487 11:44:18.403943 DQS0 = 0, DQS1 = 0
4488 11:44:18.407036 DQM Delay:
4489 11:44:18.407119 DQM0 = 51, DQM1 = 44
4490 11:44:18.410385 DQ Delay:
4491 11:44:18.410468 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4492 11:44:18.413490 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4493 11:44:18.417097 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4494 11:44:18.420291 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4495 11:44:18.420374
4496 11:44:18.423608
4497 11:44:18.423691 ==
4498 11:44:18.426968 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 11:44:18.430111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 11:44:18.430194 ==
4501 11:44:18.430260
4502 11:44:18.430321
4503 11:44:18.433266 TX Vref Scan disable
4504 11:44:18.433350 == TX Byte 0 ==
4505 11:44:18.440020 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4506 11:44:18.443564 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4507 11:44:18.443672 == TX Byte 1 ==
4508 11:44:18.450190 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4509 11:44:18.453323 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4510 11:44:18.453442 ==
4511 11:44:18.456456 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 11:44:18.459800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 11:44:18.459886 ==
4514 11:44:18.459952
4515 11:44:18.460039
4516 11:44:18.462941 TX Vref Scan disable
4517 11:44:18.466429 == TX Byte 0 ==
4518 11:44:18.469437 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 11:44:18.472873 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 11:44:18.476053 == TX Byte 1 ==
4521 11:44:18.479356 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4522 11:44:18.486273 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4523 11:44:18.486350
4524 11:44:18.486414 [DATLAT]
4525 11:44:18.486476 Freq=600, CH1 RK0
4526 11:44:18.486534
4527 11:44:18.489401 DATLAT Default: 0x9
4528 11:44:18.489468 0, 0xFFFF, sum = 0
4529 11:44:18.755610 1, 0xFFFF, sum = 0
4530 11:44:18.755994 2, 0xFFFF, sum = 0
4531 11:44:18.756105 3, 0xFFFF, sum = 0
4532 11:44:18.756170 4, 0xFFFF, sum = 0
4533 11:44:18.756233 5, 0xFFFF, sum = 0
4534 11:44:18.756293 6, 0xFFFF, sum = 0
4535 11:44:18.756351 7, 0xFFFF, sum = 0
4536 11:44:18.756409 8, 0x0, sum = 1
4537 11:44:18.756466 9, 0x0, sum = 2
4538 11:44:18.756522 10, 0x0, sum = 3
4539 11:44:18.756610 11, 0x0, sum = 4
4540 11:44:18.756666 best_step = 9
4541 11:44:18.756721
4542 11:44:18.756775 ==
4543 11:44:18.756830 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 11:44:18.756884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 11:44:18.756940 ==
4546 11:44:18.757022 RX Vref Scan: 1
4547 11:44:18.757112
4548 11:44:18.757180 RX Vref 0 -> 0, step: 1
4549 11:44:18.757234
4550 11:44:18.757288 RX Delay -163 -> 252, step: 8
4551 11:44:18.757341
4552 11:44:18.757395 Set Vref, RX VrefLevel [Byte0]: 52
4553 11:44:18.757449 [Byte1]: 48
4554 11:44:18.757503
4555 11:44:18.757556 Final RX Vref Byte 0 = 52 to rank0
4556 11:44:18.757610 Final RX Vref Byte 1 = 48 to rank0
4557 11:44:18.757700 Final RX Vref Byte 0 = 52 to rank1
4558 11:44:18.757754 Final RX Vref Byte 1 = 48 to rank1==
4559 11:44:18.757808 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 11:44:18.757862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 11:44:18.757916 ==
4562 11:44:18.757970 DQS Delay:
4563 11:44:18.758024 DQS0 = 0, DQS1 = 0
4564 11:44:18.758077 DQM Delay:
4565 11:44:18.758130 DQM0 = 49, DQM1 = 41
4566 11:44:18.758183 DQ Delay:
4567 11:44:18.758237 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4568 11:44:18.758290 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4569 11:44:18.758343 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =36
4570 11:44:18.758396 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4571 11:44:18.758450
4572 11:44:18.758503
4573 11:44:18.758557 [DQSOSCAuto] RK0, (LSB)MR18= 0x4870, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 396 ps
4574 11:44:18.758612 CH1 RK0: MR19=808, MR18=4870
4575 11:44:18.758666 CH1_RK0: MR19=0x808, MR18=0x4870, DQSOSC=388, MR23=63, INC=174, DEC=116
4576 11:44:18.758720
4577 11:44:18.758773 ----->DramcWriteLeveling(PI) begin...
4578 11:44:18.758828 ==
4579 11:44:18.758882 Dram Type= 6, Freq= 0, CH_1, rank 1
4580 11:44:18.758936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 11:44:18.758990 ==
4582 11:44:18.759043 Write leveling (Byte 0): 29 => 29
4583 11:44:18.759097 Write leveling (Byte 1): 30 => 30
4584 11:44:18.759151 DramcWriteLeveling(PI) end<-----
4585 11:44:18.759204
4586 11:44:18.759257 ==
4587 11:44:18.759310 Dram Type= 6, Freq= 0, CH_1, rank 1
4588 11:44:18.759363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:44:18.759417 ==
4590 11:44:18.759470 [Gating] SW mode calibration
4591 11:44:18.759524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4592 11:44:18.759578 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4593 11:44:18.759633 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 11:44:18.759686 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 11:44:18.759847 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 11:44:18.759961 0 9 12 | B1->B0 | 2626 3030 | 1 1 | (1 0) (0 1)
4597 11:44:18.760095 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4598 11:44:18.760213 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 11:44:18.760340 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 11:44:18.760479 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 11:44:18.760572 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 11:44:18.760660 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 11:44:18.760746 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4604 11:44:18.760831 0 10 12 | B1->B0 | 3e3e 2b2b | 0 0 | (0 0) (0 0)
4605 11:44:18.760937 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 11:44:18.761030 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 11:44:18.761087 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 11:44:18.761142 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 11:44:18.761197 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 11:44:18.761252 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 11:44:18.761306 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4612 11:44:18.761360 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 11:44:18.761439 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 11:44:18.761507 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:44:18.761561 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:44:18.761615 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:44:18.761669 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:44:18.761722 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:44:18.761776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:44:18.761844 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:44:18.763064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:44:18.765885 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:44:18.769338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:44:18.775754 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:44:18.779221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:44:18.782743 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:44:18.789309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:44:18.792557 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 11:44:18.795735 Total UI for P1: 0, mck2ui 16
4630 11:44:18.798876 best dqsien dly found for B0: ( 0, 13, 10)
4631 11:44:18.802249 Total UI for P1: 0, mck2ui 16
4632 11:44:18.805489 best dqsien dly found for B1: ( 0, 13, 10)
4633 11:44:18.809188 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4634 11:44:18.812352 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4635 11:44:18.812435
4636 11:44:18.815521 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4637 11:44:18.819051 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4638 11:44:18.822142 [Gating] SW calibration Done
4639 11:44:18.822225 ==
4640 11:44:18.825350 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 11:44:18.829005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:44:18.832093 ==
4643 11:44:18.832176 RX Vref Scan: 0
4644 11:44:18.832242
4645 11:44:18.835594 RX Vref 0 -> 0, step: 1
4646 11:44:18.835677
4647 11:44:18.838829 RX Delay -230 -> 252, step: 16
4648 11:44:18.841966 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4649 11:44:18.845245 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4650 11:44:18.848626 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4651 11:44:18.855293 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4652 11:44:18.858441 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4653 11:44:18.861719 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4654 11:44:18.865269 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4655 11:44:18.868936 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4656 11:44:18.875216 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4657 11:44:18.878357 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4658 11:44:18.881787 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4659 11:44:18.885288 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 11:44:18.891679 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4661 11:44:18.894802 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4662 11:44:18.897980 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4663 11:44:18.901440 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4664 11:44:18.901524 ==
4665 11:44:18.905085 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 11:44:18.911541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 11:44:18.911625 ==
4668 11:44:18.911691 DQS Delay:
4669 11:44:18.914813 DQS0 = 0, DQS1 = 0
4670 11:44:18.914897 DQM Delay:
4671 11:44:18.914963 DQM0 = 52, DQM1 = 46
4672 11:44:18.918003 DQ Delay:
4673 11:44:18.921699 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4674 11:44:18.924746 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4675 11:44:18.927963 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4676 11:44:18.931150 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4677 11:44:18.931233
4678 11:44:18.931298
4679 11:44:18.931359 ==
4680 11:44:18.934835 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 11:44:18.937739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 11:44:18.937823 ==
4683 11:44:18.937889
4684 11:44:18.937950
4685 11:44:18.941268 TX Vref Scan disable
4686 11:44:18.944960 == TX Byte 0 ==
4687 11:44:18.947955 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4688 11:44:18.951490 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4689 11:44:18.954411 == TX Byte 1 ==
4690 11:44:18.958014 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 11:44:18.961156 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 11:44:18.961312 ==
4693 11:44:18.964293 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 11:44:18.967802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 11:44:18.970825 ==
4696 11:44:18.971003
4697 11:44:18.971122
4698 11:44:18.971239 TX Vref Scan disable
4699 11:44:18.974886 == TX Byte 0 ==
4700 11:44:18.977884 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4701 11:44:18.984580 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4702 11:44:18.984667 == TX Byte 1 ==
4703 11:44:18.987979 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 11:44:18.994753 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 11:44:18.994865
4706 11:44:18.994963 [DATLAT]
4707 11:44:18.995053 Freq=600, CH1 RK1
4708 11:44:18.995142
4709 11:44:18.997732 DATLAT Default: 0x9
4710 11:44:19.000893 0, 0xFFFF, sum = 0
4711 11:44:19.000999 1, 0xFFFF, sum = 0
4712 11:44:19.004618 2, 0xFFFF, sum = 0
4713 11:44:19.004731 3, 0xFFFF, sum = 0
4714 11:44:19.007633 4, 0xFFFF, sum = 0
4715 11:44:19.007744 5, 0xFFFF, sum = 0
4716 11:44:19.010949 6, 0xFFFF, sum = 0
4717 11:44:19.011034 7, 0xFFFF, sum = 0
4718 11:44:19.014314 8, 0x0, sum = 1
4719 11:44:19.014398 9, 0x0, sum = 2
4720 11:44:19.017486 10, 0x0, sum = 3
4721 11:44:19.017570 11, 0x0, sum = 4
4722 11:44:19.017636 best_step = 9
4723 11:44:19.017698
4724 11:44:19.020785 ==
4725 11:44:19.024384 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 11:44:19.027550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 11:44:19.027634 ==
4728 11:44:19.027700 RX Vref Scan: 0
4729 11:44:19.027762
4730 11:44:19.030842 RX Vref 0 -> 0, step: 1
4731 11:44:19.030925
4732 11:44:19.034103 RX Delay -163 -> 252, step: 8
4733 11:44:19.040757 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4734 11:44:19.043947 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4735 11:44:19.047139 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4736 11:44:19.050415 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4737 11:44:19.053902 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4738 11:44:19.060347 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4739 11:44:19.063940 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4740 11:44:19.067028 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4741 11:44:19.070247 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4742 11:44:19.073793 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4743 11:44:19.080181 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4744 11:44:19.083627 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4745 11:44:19.086809 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4746 11:44:19.090275 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4747 11:44:19.096530 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4748 11:44:19.100109 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4749 11:44:19.100213 ==
4750 11:44:19.103354 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 11:44:19.106579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 11:44:19.106652 ==
4753 11:44:19.110035 DQS Delay:
4754 11:44:19.110132 DQS0 = 0, DQS1 = 0
4755 11:44:19.110221 DQM Delay:
4756 11:44:19.113123 DQM0 = 49, DQM1 = 43
4757 11:44:19.113196 DQ Delay:
4758 11:44:19.116396 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4759 11:44:19.119683 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4760 11:44:19.123398 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4761 11:44:19.126714 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =52
4762 11:44:19.126810
4763 11:44:19.126899
4764 11:44:19.136225 [DQSOSCAuto] RK1, (LSB)MR18= 0x591f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4765 11:44:19.136328 CH1 RK1: MR19=808, MR18=591F
4766 11:44:19.143109 CH1_RK1: MR19=0x808, MR18=0x591F, DQSOSC=393, MR23=63, INC=169, DEC=113
4767 11:44:19.146547 [RxdqsGatingPostProcess] freq 600
4768 11:44:19.152896 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 11:44:19.156151 Pre-setting of DQS Precalculation
4770 11:44:19.159634 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 11:44:19.166060 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 11:44:19.175901 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 11:44:19.176010
4774 11:44:19.176081
4775 11:44:19.179394 [Calibration Summary] 1200 Mbps
4776 11:44:19.179493 CH 0, Rank 0
4777 11:44:19.182460 SW Impedance : PASS
4778 11:44:19.182559 DUTY Scan : NO K
4779 11:44:19.185854 ZQ Calibration : PASS
4780 11:44:19.189056 Jitter Meter : NO K
4781 11:44:19.189159 CBT Training : PASS
4782 11:44:19.192472 Write leveling : PASS
4783 11:44:19.195646 RX DQS gating : PASS
4784 11:44:19.195750 RX DQ/DQS(RDDQC) : PASS
4785 11:44:19.199180 TX DQ/DQS : PASS
4786 11:44:19.202379 RX DATLAT : PASS
4787 11:44:19.202480 RX DQ/DQS(Engine): PASS
4788 11:44:19.205620 TX OE : NO K
4789 11:44:19.205718 All Pass.
4790 11:44:19.205787
4791 11:44:19.208840 CH 0, Rank 1
4792 11:44:19.208944 SW Impedance : PASS
4793 11:44:19.212039 DUTY Scan : NO K
4794 11:44:19.215429 ZQ Calibration : PASS
4795 11:44:19.215530 Jitter Meter : NO K
4796 11:44:19.218881 CBT Training : PASS
4797 11:44:19.218980 Write leveling : PASS
4798 11:44:19.222310 RX DQS gating : PASS
4799 11:44:19.225635 RX DQ/DQS(RDDQC) : PASS
4800 11:44:19.225715 TX DQ/DQS : PASS
4801 11:44:19.228788 RX DATLAT : PASS
4802 11:44:19.231938 RX DQ/DQS(Engine): PASS
4803 11:44:19.232010 TX OE : NO K
4804 11:44:19.235166 All Pass.
4805 11:44:19.235270
4806 11:44:19.235359 CH 1, Rank 0
4807 11:44:19.238853 SW Impedance : PASS
4808 11:44:19.238952 DUTY Scan : NO K
4809 11:44:19.241636 ZQ Calibration : PASS
4810 11:44:19.245318 Jitter Meter : NO K
4811 11:44:19.245394 CBT Training : PASS
4812 11:44:19.248385 Write leveling : PASS
4813 11:44:19.251562 RX DQS gating : PASS
4814 11:44:19.251684 RX DQ/DQS(RDDQC) : PASS
4815 11:44:19.254952 TX DQ/DQS : PASS
4816 11:44:19.258118 RX DATLAT : PASS
4817 11:44:19.258225 RX DQ/DQS(Engine): PASS
4818 11:44:19.261782 TX OE : NO K
4819 11:44:19.261856 All Pass.
4820 11:44:19.261920
4821 11:44:19.264925 CH 1, Rank 1
4822 11:44:19.265019 SW Impedance : PASS
4823 11:44:19.268184 DUTY Scan : NO K
4824 11:44:19.271493 ZQ Calibration : PASS
4825 11:44:19.271567 Jitter Meter : NO K
4826 11:44:19.274676 CBT Training : PASS
4827 11:44:19.277913 Write leveling : PASS
4828 11:44:19.277994 RX DQS gating : PASS
4829 11:44:19.281099 RX DQ/DQS(RDDQC) : PASS
4830 11:44:19.284701 TX DQ/DQS : PASS
4831 11:44:19.284784 RX DATLAT : PASS
4832 11:44:19.287921 RX DQ/DQS(Engine): PASS
4833 11:44:19.290996 TX OE : NO K
4834 11:44:19.291079 All Pass.
4835 11:44:19.291142
4836 11:44:19.291233 DramC Write-DBI off
4837 11:44:19.294735 PER_BANK_REFRESH: Hybrid Mode
4838 11:44:19.297661 TX_TRACKING: ON
4839 11:44:19.304447 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 11:44:19.308073 [FAST_K] Save calibration result to emmc
4841 11:44:19.314270 dramc_set_vcore_voltage set vcore to 662500
4842 11:44:19.314380 Read voltage for 933, 3
4843 11:44:19.317495 Vio18 = 0
4844 11:44:19.317568 Vcore = 662500
4845 11:44:19.317632 Vdram = 0
4846 11:44:19.317690 Vddq = 0
4847 11:44:19.321127 Vmddr = 0
4848 11:44:19.324345 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 11:44:19.330926 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 11:44:19.334233 MEM_TYPE=3, freq_sel=17
4851 11:44:19.337534 sv_algorithm_assistance_LP4_1600
4852 11:44:19.340798 ============ PULL DRAM RESETB DOWN ============
4853 11:44:19.344061 ========== PULL DRAM RESETB DOWN end =========
4854 11:44:19.347250 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 11:44:19.350879 ===================================
4856 11:44:19.354107 LPDDR4 DRAM CONFIGURATION
4857 11:44:19.357438 ===================================
4858 11:44:19.360686 EX_ROW_EN[0] = 0x0
4859 11:44:19.360781 EX_ROW_EN[1] = 0x0
4860 11:44:19.363855 LP4Y_EN = 0x0
4861 11:44:19.363925 WORK_FSP = 0x0
4862 11:44:19.367403 WL = 0x3
4863 11:44:19.367506 RL = 0x3
4864 11:44:19.370738 BL = 0x2
4865 11:44:19.370826 RPST = 0x0
4866 11:44:19.373869 RD_PRE = 0x0
4867 11:44:19.374007 WR_PRE = 0x1
4868 11:44:19.376918 WR_PST = 0x0
4869 11:44:19.380658 DBI_WR = 0x0
4870 11:44:19.380764 DBI_RD = 0x0
4871 11:44:19.383888 OTF = 0x1
4872 11:44:19.387151 ===================================
4873 11:44:19.390216 ===================================
4874 11:44:19.390293 ANA top config
4875 11:44:19.393658 ===================================
4876 11:44:19.397044 DLL_ASYNC_EN = 0
4877 11:44:19.400321 ALL_SLAVE_EN = 1
4878 11:44:19.400394 NEW_RANK_MODE = 1
4879 11:44:19.403797 DLL_IDLE_MODE = 1
4880 11:44:19.406931 LP45_APHY_COMB_EN = 1
4881 11:44:19.410058 TX_ODT_DIS = 1
4882 11:44:19.410134 NEW_8X_MODE = 1
4883 11:44:19.413692 ===================================
4884 11:44:19.416878 ===================================
4885 11:44:19.420155 data_rate = 1866
4886 11:44:19.423549 CKR = 1
4887 11:44:19.426826 DQ_P2S_RATIO = 8
4888 11:44:19.429918 ===================================
4889 11:44:19.433618 CA_P2S_RATIO = 8
4890 11:44:19.436831 DQ_CA_OPEN = 0
4891 11:44:19.436903 DQ_SEMI_OPEN = 0
4892 11:44:19.440004 CA_SEMI_OPEN = 0
4893 11:44:19.443095 CA_FULL_RATE = 0
4894 11:44:19.446732 DQ_CKDIV4_EN = 1
4895 11:44:19.449858 CA_CKDIV4_EN = 1
4896 11:44:19.453090 CA_PREDIV_EN = 0
4897 11:44:19.456593 PH8_DLY = 0
4898 11:44:19.456662 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 11:44:19.459567 DQ_AAMCK_DIV = 4
4900 11:44:19.463231 CA_AAMCK_DIV = 4
4901 11:44:19.466371 CA_ADMCK_DIV = 4
4902 11:44:19.469588 DQ_TRACK_CA_EN = 0
4903 11:44:19.472673 CA_PICK = 933
4904 11:44:19.475908 CA_MCKIO = 933
4905 11:44:19.475980 MCKIO_SEMI = 0
4906 11:44:19.479448 PLL_FREQ = 3732
4907 11:44:19.482652 DQ_UI_PI_RATIO = 32
4908 11:44:19.485948 CA_UI_PI_RATIO = 0
4909 11:44:19.489269 ===================================
4910 11:44:19.492626 ===================================
4911 11:44:19.495978 memory_type:LPDDR4
4912 11:44:19.496052 GP_NUM : 10
4913 11:44:19.499352 SRAM_EN : 1
4914 11:44:19.499423 MD32_EN : 0
4915 11:44:19.502533 ===================================
4916 11:44:19.505936 [ANA_INIT] >>>>>>>>>>>>>>
4917 11:44:19.508959 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 11:44:19.512597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 11:44:19.515725 ===================================
4920 11:44:19.519270 data_rate = 1866,PCW = 0X8f00
4921 11:44:19.522609 ===================================
4922 11:44:19.525890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 11:44:19.532505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 11:44:19.535703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 11:44:19.542165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 11:44:19.545419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 11:44:19.548755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 11:44:19.548827 [ANA_INIT] flow start
4929 11:44:19.552344 [ANA_INIT] PLL >>>>>>>>
4930 11:44:19.555737 [ANA_INIT] PLL <<<<<<<<
4931 11:44:19.558872 [ANA_INIT] MIDPI >>>>>>>>
4932 11:44:19.558951 [ANA_INIT] MIDPI <<<<<<<<
4933 11:44:19.561930 [ANA_INIT] DLL >>>>>>>>
4934 11:44:19.562017 [ANA_INIT] flow end
4935 11:44:19.568673 ============ LP4 DIFF to SE enter ============
4936 11:44:19.571978 ============ LP4 DIFF to SE exit ============
4937 11:44:19.575456 [ANA_INIT] <<<<<<<<<<<<<
4938 11:44:19.578710 [Flow] Enable top DCM control >>>>>
4939 11:44:19.581934 [Flow] Enable top DCM control <<<<<
4940 11:44:19.584942 Enable DLL master slave shuffle
4941 11:44:19.588228 ==============================================================
4942 11:44:19.591926 Gating Mode config
4943 11:44:19.594986 ==============================================================
4944 11:44:19.598487 Config description:
4945 11:44:19.608119 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 11:44:19.615104 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 11:44:19.618198 SELPH_MODE 0: By rank 1: By Phase
4948 11:44:19.624923 ==============================================================
4949 11:44:19.628194 GAT_TRACK_EN = 1
4950 11:44:19.631217 RX_GATING_MODE = 2
4951 11:44:19.634498 RX_GATING_TRACK_MODE = 2
4952 11:44:19.638218 SELPH_MODE = 1
4953 11:44:19.641375 PICG_EARLY_EN = 1
4954 11:44:19.644614 VALID_LAT_VALUE = 1
4955 11:44:19.647768 ==============================================================
4956 11:44:19.651441 Enter into Gating configuration >>>>
4957 11:44:19.654324 Exit from Gating configuration <<<<
4958 11:44:19.658150 Enter into DVFS_PRE_config >>>>>
4959 11:44:19.671001 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 11:44:19.671094 Exit from DVFS_PRE_config <<<<<
4961 11:44:19.674162 Enter into PICG configuration >>>>
4962 11:44:19.677542 Exit from PICG configuration <<<<
4963 11:44:19.681000 [RX_INPUT] configuration >>>>>
4964 11:44:19.684267 [RX_INPUT] configuration <<<<<
4965 11:44:19.691010 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 11:44:19.694137 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 11:44:19.700866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 11:44:19.707728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 11:44:19.713850 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 11:44:19.720784 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 11:44:19.723913 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 11:44:19.727451 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 11:44:19.730646 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 11:44:19.737468 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 11:44:19.740877 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 11:44:19.744184 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 11:44:19.747364 ===================================
4978 11:44:19.750643 LPDDR4 DRAM CONFIGURATION
4979 11:44:19.753890 ===================================
4980 11:44:19.753965 EX_ROW_EN[0] = 0x0
4981 11:44:19.757048 EX_ROW_EN[1] = 0x0
4982 11:44:19.760312 LP4Y_EN = 0x0
4983 11:44:19.760383 WORK_FSP = 0x0
4984 11:44:19.764049 WL = 0x3
4985 11:44:19.764127 RL = 0x3
4986 11:44:19.767391 BL = 0x2
4987 11:44:19.767479 RPST = 0x0
4988 11:44:19.770521 RD_PRE = 0x0
4989 11:44:19.770600 WR_PRE = 0x1
4990 11:44:19.773542 WR_PST = 0x0
4991 11:44:19.773614 DBI_WR = 0x0
4992 11:44:19.777263 DBI_RD = 0x0
4993 11:44:19.777339 OTF = 0x1
4994 11:44:19.780363 ===================================
4995 11:44:19.786776 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 11:44:19.790447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 11:44:19.793845 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 11:44:19.797184 ===================================
4999 11:44:19.800210 LPDDR4 DRAM CONFIGURATION
5000 11:44:19.803341 ===================================
5001 11:44:19.803451 EX_ROW_EN[0] = 0x10
5002 11:44:19.806924 EX_ROW_EN[1] = 0x0
5003 11:44:19.810242 LP4Y_EN = 0x0
5004 11:44:19.810314 WORK_FSP = 0x0
5005 11:44:19.813381 WL = 0x3
5006 11:44:19.813460 RL = 0x3
5007 11:44:19.816766 BL = 0x2
5008 11:44:19.816837 RPST = 0x0
5009 11:44:19.820233 RD_PRE = 0x0
5010 11:44:19.820312 WR_PRE = 0x1
5011 11:44:19.823749 WR_PST = 0x0
5012 11:44:19.823822 DBI_WR = 0x0
5013 11:44:19.826833 DBI_RD = 0x0
5014 11:44:19.826903 OTF = 0x1
5015 11:44:19.830179 ===================================
5016 11:44:19.836655 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 11:44:19.840923 nWR fixed to 30
5018 11:44:19.844477 [ModeRegInit_LP4] CH0 RK0
5019 11:44:19.844560 [ModeRegInit_LP4] CH0 RK1
5020 11:44:19.847795 [ModeRegInit_LP4] CH1 RK0
5021 11:44:19.851060 [ModeRegInit_LP4] CH1 RK1
5022 11:44:19.851143 match AC timing 9
5023 11:44:19.857952 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 11:44:19.860890 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 11:44:19.864626 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 11:44:19.870984 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 11:44:19.874338 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 11:44:19.874422 ==
5029 11:44:19.877372 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 11:44:19.880989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 11:44:19.881103 ==
5032 11:44:19.887377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 11:44:19.894287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5034 11:44:19.897360 [CA 0] Center 37 (7~68) winsize 62
5035 11:44:19.900618 [CA 1] Center 38 (8~68) winsize 61
5036 11:44:19.903753 [CA 2] Center 35 (5~65) winsize 61
5037 11:44:19.907423 [CA 3] Center 34 (4~65) winsize 62
5038 11:44:19.910774 [CA 4] Center 34 (4~64) winsize 61
5039 11:44:19.914191 [CA 5] Center 33 (3~64) winsize 62
5040 11:44:19.914289
5041 11:44:19.917275 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5042 11:44:19.917359
5043 11:44:19.920394 [CATrainingPosCal] consider 1 rank data
5044 11:44:19.923822 u2DelayCellTimex100 = 270/100 ps
5045 11:44:19.927012 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5046 11:44:19.930568 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5047 11:44:19.933773 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5048 11:44:19.936960 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5049 11:44:19.940541 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5050 11:44:19.947074 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5051 11:44:19.947157
5052 11:44:19.950204 CA PerBit enable=1, Macro0, CA PI delay=33
5053 11:44:19.950349
5054 11:44:19.953401 [CBTSetCACLKResult] CA Dly = 33
5055 11:44:19.953477 CS Dly: 6 (0~37)
5056 11:44:19.953540 ==
5057 11:44:19.956638 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 11:44:19.963147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 11:44:19.963226 ==
5060 11:44:19.966780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 11:44:19.973248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 11:44:19.976452 [CA 0] Center 38 (7~69) winsize 63
5063 11:44:19.979688 [CA 1] Center 38 (8~68) winsize 61
5064 11:44:19.983186 [CA 2] Center 36 (6~66) winsize 61
5065 11:44:19.986342 [CA 3] Center 35 (5~66) winsize 62
5066 11:44:19.989490 [CA 4] Center 34 (4~65) winsize 62
5067 11:44:19.993063 [CA 5] Center 33 (3~64) winsize 62
5068 11:44:19.993135
5069 11:44:19.996165 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 11:44:19.996241
5071 11:44:19.999790 [CATrainingPosCal] consider 2 rank data
5072 11:44:20.003012 u2DelayCellTimex100 = 270/100 ps
5073 11:44:20.006413 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5074 11:44:20.009663 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5075 11:44:20.016162 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5076 11:44:20.019597 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5077 11:44:20.022595 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5078 11:44:20.026284 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5079 11:44:20.026373
5080 11:44:20.029243 CA PerBit enable=1, Macro0, CA PI delay=33
5081 11:44:20.029313
5082 11:44:20.032800 [CBTSetCACLKResult] CA Dly = 33
5083 11:44:20.035902 CS Dly: 7 (0~39)
5084 11:44:20.035987
5085 11:44:20.039070 ----->DramcWriteLeveling(PI) begin...
5086 11:44:20.039142 ==
5087 11:44:20.042857 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 11:44:20.046052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:44:20.046124 ==
5090 11:44:20.049013 Write leveling (Byte 0): 35 => 35
5091 11:44:20.052136 Write leveling (Byte 1): 28 => 28
5092 11:44:20.055472 DramcWriteLeveling(PI) end<-----
5093 11:44:20.055543
5094 11:44:20.055603 ==
5095 11:44:20.058820 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 11:44:20.062411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 11:44:20.062501 ==
5098 11:44:20.065562 [Gating] SW mode calibration
5099 11:44:20.072107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 11:44:20.078585 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 11:44:20.081707 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5102 11:44:20.085048 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 11:44:20.091749 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 11:44:20.095014 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 11:44:20.098436 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 11:44:20.104772 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 11:44:20.108344 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5108 11:44:20.111547 0 14 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5109 11:44:20.117883 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5110 11:44:20.121276 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 11:44:20.124456 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 11:44:20.131319 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 11:44:20.134791 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 11:44:20.137847 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 11:44:20.144602 0 15 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5116 11:44:20.147852 0 15 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
5117 11:44:20.151387 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5118 11:44:20.157748 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 11:44:20.160843 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:44:20.164584 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:44:20.170835 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 11:44:20.174056 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 11:44:20.177701 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 11:44:20.184228 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5125 11:44:20.187502 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:44:20.190943 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5127 11:44:20.197290 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:44:20.200784 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:44:20.204043 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:44:20.210451 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:44:20.213807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:44:20.216868 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:44:20.223413 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:44:20.226876 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:44:20.230437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:44:20.236730 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:44:20.240043 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:44:20.243492 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:44:20.249927 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:44:20.253593 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 11:44:20.256675 Total UI for P1: 0, mck2ui 16
5142 11:44:20.260166 best dqsien dly found for B0: ( 1, 2, 26)
5143 11:44:20.263407 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 11:44:20.269816 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 11:44:20.269898 Total UI for P1: 0, mck2ui 16
5146 11:44:20.276564 best dqsien dly found for B1: ( 1, 2, 30)
5147 11:44:20.279731 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5148 11:44:20.283058 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5149 11:44:20.283140
5150 11:44:20.286236 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5151 11:44:20.289610 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5152 11:44:20.293190 [Gating] SW calibration Done
5153 11:44:20.293272 ==
5154 11:44:20.296237 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 11:44:20.299408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 11:44:20.299507 ==
5157 11:44:20.302621 RX Vref Scan: 0
5158 11:44:20.302702
5159 11:44:20.306235 RX Vref 0 -> 0, step: 1
5160 11:44:20.306317
5161 11:44:20.306381 RX Delay -80 -> 252, step: 8
5162 11:44:20.312637 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5163 11:44:20.315786 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5164 11:44:20.319449 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5165 11:44:20.322588 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5166 11:44:20.325707 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5167 11:44:20.332519 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5168 11:44:20.335639 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5169 11:44:20.338835 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5170 11:44:20.342380 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5171 11:44:20.345749 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5172 11:44:20.348952 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5173 11:44:20.355426 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5174 11:44:20.358937 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5175 11:44:20.361926 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5176 11:44:20.365191 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5177 11:44:20.368451 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5178 11:44:20.371640 ==
5179 11:44:20.371735 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 11:44:20.378578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 11:44:20.378660 ==
5182 11:44:20.378723 DQS Delay:
5183 11:44:20.381895 DQS0 = 0, DQS1 = 0
5184 11:44:20.381976 DQM Delay:
5185 11:44:20.384847 DQM0 = 105, DQM1 = 89
5186 11:44:20.384928 DQ Delay:
5187 11:44:20.388465 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5188 11:44:20.391695 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5189 11:44:20.395009 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5190 11:44:20.398076 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5191 11:44:20.398158
5192 11:44:20.398224
5193 11:44:20.398285 ==
5194 11:44:20.401195 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 11:44:20.404901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 11:44:20.405031 ==
5197 11:44:20.408218
5198 11:44:20.408316
5199 11:44:20.408394 TX Vref Scan disable
5200 11:44:20.411369 == TX Byte 0 ==
5201 11:44:20.414493 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5202 11:44:20.418042 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5203 11:44:20.421372 == TX Byte 1 ==
5204 11:44:20.424798 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5205 11:44:20.427855 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5206 11:44:20.430988 ==
5207 11:44:20.431071 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 11:44:20.437713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 11:44:20.437800 ==
5210 11:44:20.437866
5211 11:44:20.437926
5212 11:44:20.441161 TX Vref Scan disable
5213 11:44:20.441246 == TX Byte 0 ==
5214 11:44:20.447587 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5215 11:44:20.451097 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5216 11:44:20.451179 == TX Byte 1 ==
5217 11:44:20.457613 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5218 11:44:20.460783 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5219 11:44:20.460865
5220 11:44:20.460953 [DATLAT]
5221 11:44:20.464234 Freq=933, CH0 RK0
5222 11:44:20.464316
5223 11:44:20.464381 DATLAT Default: 0xd
5224 11:44:20.467379 0, 0xFFFF, sum = 0
5225 11:44:20.467464 1, 0xFFFF, sum = 0
5226 11:44:20.471049 2, 0xFFFF, sum = 0
5227 11:44:20.471159 3, 0xFFFF, sum = 0
5228 11:44:20.474277 4, 0xFFFF, sum = 0
5229 11:44:20.474361 5, 0xFFFF, sum = 0
5230 11:44:20.477410 6, 0xFFFF, sum = 0
5231 11:44:20.477494 7, 0xFFFF, sum = 0
5232 11:44:20.480730 8, 0xFFFF, sum = 0
5233 11:44:20.483973 9, 0xFFFF, sum = 0
5234 11:44:20.484083 10, 0x0, sum = 1
5235 11:44:20.484179 11, 0x0, sum = 2
5236 11:44:20.487662 12, 0x0, sum = 3
5237 11:44:20.487745 13, 0x0, sum = 4
5238 11:44:20.490786 best_step = 11
5239 11:44:20.490868
5240 11:44:20.490936 ==
5241 11:44:20.493905 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 11:44:20.497578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 11:44:20.497660 ==
5244 11:44:20.500685 RX Vref Scan: 1
5245 11:44:20.500766
5246 11:44:20.500831 RX Vref 0 -> 0, step: 1
5247 11:44:20.500892
5248 11:44:20.503711 RX Delay -53 -> 252, step: 4
5249 11:44:20.503792
5250 11:44:20.506969 Set Vref, RX VrefLevel [Byte0]: 60
5251 11:44:20.510587 [Byte1]: 52
5252 11:44:20.514956
5253 11:44:20.515039 Final RX Vref Byte 0 = 60 to rank0
5254 11:44:20.518049 Final RX Vref Byte 1 = 52 to rank0
5255 11:44:20.521251 Final RX Vref Byte 0 = 60 to rank1
5256 11:44:20.524768 Final RX Vref Byte 1 = 52 to rank1==
5257 11:44:20.527915 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:44:20.534554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:44:20.534660 ==
5260 11:44:20.534724 DQS Delay:
5261 11:44:20.538121 DQS0 = 0, DQS1 = 0
5262 11:44:20.538191 DQM Delay:
5263 11:44:20.538251 DQM0 = 108, DQM1 = 93
5264 11:44:20.541242 DQ Delay:
5265 11:44:20.544232 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5266 11:44:20.547415 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =116
5267 11:44:20.550791 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5268 11:44:20.554250 DQ12 =100, DQ13 =96, DQ14 =102, DQ15 =100
5269 11:44:20.554321
5270 11:44:20.554384
5271 11:44:20.564166 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5272 11:44:20.564254 CH0 RK0: MR19=505, MR18=2723
5273 11:44:20.570992 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5274 11:44:20.571138
5275 11:44:20.574243 ----->DramcWriteLeveling(PI) begin...
5276 11:44:20.574327 ==
5277 11:44:20.577432 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 11:44:20.583854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 11:44:20.583971 ==
5280 11:44:20.587059 Write leveling (Byte 0): 33 => 33
5281 11:44:20.590687 Write leveling (Byte 1): 32 => 32
5282 11:44:20.590759 DramcWriteLeveling(PI) end<-----
5283 11:44:20.590821
5284 11:44:20.593966 ==
5285 11:44:20.597274 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 11:44:20.600441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:44:20.600547 ==
5288 11:44:20.603651 [Gating] SW mode calibration
5289 11:44:20.610172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 11:44:20.613346 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 11:44:20.619997 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 11:44:20.623216 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 11:44:20.626824 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 11:44:20.633130 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 11:44:20.636662 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 11:44:20.639684 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 11:44:20.646268 0 14 24 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
5298 11:44:20.649847 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5299 11:44:20.652992 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 11:44:20.659630 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 11:44:20.663271 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 11:44:20.666454 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 11:44:20.672889 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 11:44:20.676486 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 11:44:20.679719 0 15 24 | B1->B0 | 2525 3030 | 0 1 | (1 1) (0 0)
5306 11:44:20.686374 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5307 11:44:20.689618 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 11:44:20.692962 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 11:44:20.699322 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 11:44:20.702499 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 11:44:20.705693 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 11:44:20.712481 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 11:44:20.715764 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5314 11:44:20.718831 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 11:44:20.725340 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 11:44:20.728881 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 11:44:20.732235 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 11:44:20.738673 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:44:20.742263 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:44:20.745224 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:44:20.752072 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:44:20.755314 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:44:20.758661 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:44:20.765232 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:44:20.768322 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:44:20.771543 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:44:20.778494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:44:20.781475 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:44:20.785030 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:44:20.791684 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5331 11:44:20.795036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 11:44:20.798263 Total UI for P1: 0, mck2ui 16
5333 11:44:20.801465 best dqsien dly found for B0: ( 1, 2, 28)
5334 11:44:20.805173 Total UI for P1: 0, mck2ui 16
5335 11:44:20.808420 best dqsien dly found for B1: ( 1, 2, 28)
5336 11:44:20.811678 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5337 11:44:20.814741 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5338 11:44:20.814821
5339 11:44:20.817991 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 11:44:20.821170 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5341 11:44:20.824946 [Gating] SW calibration Done
5342 11:44:20.825048 ==
5343 11:44:20.828145 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 11:44:20.834786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 11:44:20.834867 ==
5346 11:44:20.834930 RX Vref Scan: 0
5347 11:44:20.834988
5348 11:44:20.837978 RX Vref 0 -> 0, step: 1
5349 11:44:20.838057
5350 11:44:20.841207 RX Delay -80 -> 252, step: 8
5351 11:44:20.844483 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5352 11:44:20.847848 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5353 11:44:20.851226 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5354 11:44:20.854225 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5355 11:44:20.860858 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5356 11:44:20.864662 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5357 11:44:20.867580 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5358 11:44:20.871078 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5359 11:44:20.874239 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5360 11:44:20.877503 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5361 11:44:20.884203 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5362 11:44:20.887307 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5363 11:44:20.890741 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5364 11:44:20.893830 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5365 11:44:20.897513 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5366 11:44:20.903533 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5367 11:44:20.903611 ==
5368 11:44:20.907148 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 11:44:20.910584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 11:44:20.910656 ==
5371 11:44:20.910717 DQS Delay:
5372 11:44:20.914062 DQS0 = 0, DQS1 = 0
5373 11:44:20.914130 DQM Delay:
5374 11:44:20.917203 DQM0 = 105, DQM1 = 90
5375 11:44:20.917270 DQ Delay:
5376 11:44:20.920475 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5377 11:44:20.923926 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115
5378 11:44:20.927131 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5379 11:44:20.930288 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5380 11:44:20.930361
5381 11:44:20.930420
5382 11:44:20.930477 ==
5383 11:44:20.933799 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 11:44:20.936881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 11:44:20.940113 ==
5386 11:44:20.940193
5387 11:44:20.940257
5388 11:44:20.940315 TX Vref Scan disable
5389 11:44:20.943370 == TX Byte 0 ==
5390 11:44:20.946633 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5391 11:44:20.950297 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5392 11:44:20.953276 == TX Byte 1 ==
5393 11:44:20.956645 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5394 11:44:20.960131 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5395 11:44:20.963219 ==
5396 11:44:20.966612 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 11:44:20.969746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 11:44:20.969828 ==
5399 11:44:20.969892
5400 11:44:20.969952
5401 11:44:20.973296 TX Vref Scan disable
5402 11:44:20.973378 == TX Byte 0 ==
5403 11:44:20.979590 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5404 11:44:20.983135 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5405 11:44:20.983237 == TX Byte 1 ==
5406 11:44:20.989933 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5407 11:44:20.992858 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5408 11:44:20.992959
5409 11:44:20.993065 [DATLAT]
5410 11:44:20.996111 Freq=933, CH0 RK1
5411 11:44:20.996188
5412 11:44:20.996248 DATLAT Default: 0xb
5413 11:44:20.999874 0, 0xFFFF, sum = 0
5414 11:44:20.999971 1, 0xFFFF, sum = 0
5415 11:44:21.002991 2, 0xFFFF, sum = 0
5416 11:44:21.003063 3, 0xFFFF, sum = 0
5417 11:44:21.006172 4, 0xFFFF, sum = 0
5418 11:44:21.009383 5, 0xFFFF, sum = 0
5419 11:44:21.009479 6, 0xFFFF, sum = 0
5420 11:44:21.012618 7, 0xFFFF, sum = 0
5421 11:44:21.012716 8, 0xFFFF, sum = 0
5422 11:44:21.016169 9, 0xFFFF, sum = 0
5423 11:44:21.016284 10, 0x0, sum = 1
5424 11:44:21.019503 11, 0x0, sum = 2
5425 11:44:21.019616 12, 0x0, sum = 3
5426 11:44:21.019719 13, 0x0, sum = 4
5427 11:44:21.022456 best_step = 11
5428 11:44:21.022563
5429 11:44:21.022656 ==
5430 11:44:21.026273 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 11:44:21.029443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 11:44:21.029548 ==
5433 11:44:21.032335 RX Vref Scan: 0
5434 11:44:21.032432
5435 11:44:21.035927 RX Vref 0 -> 0, step: 1
5436 11:44:21.036024
5437 11:44:21.036116 RX Delay -53 -> 252, step: 4
5438 11:44:21.043325 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5439 11:44:21.046885 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5440 11:44:21.050257 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5441 11:44:21.053603 iDelay=203, Bit 3, Center 100 (15 ~ 186) 172
5442 11:44:21.060011 iDelay=203, Bit 4, Center 106 (19 ~ 194) 176
5443 11:44:21.063542 iDelay=203, Bit 5, Center 98 (15 ~ 182) 168
5444 11:44:21.066830 iDelay=203, Bit 6, Center 116 (31 ~ 202) 172
5445 11:44:21.069855 iDelay=203, Bit 7, Center 110 (23 ~ 198) 176
5446 11:44:21.073431 iDelay=203, Bit 8, Center 86 (3 ~ 170) 168
5447 11:44:21.076503 iDelay=203, Bit 9, Center 84 (3 ~ 166) 164
5448 11:44:21.083183 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5449 11:44:21.086693 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5450 11:44:21.089778 iDelay=203, Bit 12, Center 100 (15 ~ 186) 172
5451 11:44:21.092914 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5452 11:44:21.096521 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5453 11:44:21.102926 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5454 11:44:21.103013 ==
5455 11:44:21.106229 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:44:21.109981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:44:21.110065 ==
5458 11:44:21.110131 DQS Delay:
5459 11:44:21.113270 DQS0 = 0, DQS1 = 0
5460 11:44:21.113342 DQM Delay:
5461 11:44:21.116412 DQM0 = 105, DQM1 = 93
5462 11:44:21.116483 DQ Delay:
5463 11:44:21.119721 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5464 11:44:21.122999 DQ4 =106, DQ5 =98, DQ6 =116, DQ7 =110
5465 11:44:21.126100 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =92
5466 11:44:21.129406 DQ12 =100, DQ13 =94, DQ14 =100, DQ15 =98
5467 11:44:21.129483
5468 11:44:21.129545
5469 11:44:21.139253 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5470 11:44:21.142403 CH0 RK1: MR19=505, MR18=2A0B
5471 11:44:21.145621 CH0_RK1: MR19=0x505, MR18=0x2A0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5472 11:44:21.149139 [RxdqsGatingPostProcess] freq 933
5473 11:44:21.155466 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 11:44:21.159090 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 11:44:21.162072 best DQS1 dly(2T, 0.5T) = (0, 10)
5476 11:44:21.165614 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 11:44:21.168901 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5478 11:44:21.172056 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 11:44:21.175064 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 11:44:21.178642 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 11:44:21.181786 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 11:44:21.185194 Pre-setting of DQS Precalculation
5483 11:44:21.188314 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 11:44:21.188389 ==
5485 11:44:21.191645 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 11:44:21.197989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:44:21.198063 ==
5488 11:44:21.201638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 11:44:21.208023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5490 11:44:21.211305 [CA 0] Center 37 (7~67) winsize 61
5491 11:44:21.214919 [CA 1] Center 37 (7~68) winsize 62
5492 11:44:21.218121 [CA 2] Center 35 (5~65) winsize 61
5493 11:44:21.221359 [CA 3] Center 34 (5~64) winsize 60
5494 11:44:21.224851 [CA 4] Center 35 (5~65) winsize 61
5495 11:44:21.227957 [CA 5] Center 34 (5~64) winsize 60
5496 11:44:21.228039
5497 11:44:21.231409 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5498 11:44:21.231491
5499 11:44:21.234395 [CATrainingPosCal] consider 1 rank data
5500 11:44:21.237748 u2DelayCellTimex100 = 270/100 ps
5501 11:44:21.240933 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5502 11:44:21.244535 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5503 11:44:21.250973 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5504 11:44:21.254346 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5505 11:44:21.257885 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5506 11:44:21.261109 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5507 11:44:21.261191
5508 11:44:21.264191 CA PerBit enable=1, Macro0, CA PI delay=34
5509 11:44:21.264274
5510 11:44:21.267664 [CBTSetCACLKResult] CA Dly = 34
5511 11:44:21.267745 CS Dly: 6 (0~37)
5512 11:44:21.270680 ==
5513 11:44:21.270763 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 11:44:21.277268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:44:21.277350 ==
5516 11:44:21.280854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 11:44:21.287366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5518 11:44:21.290944 [CA 0] Center 37 (7~68) winsize 62
5519 11:44:21.294054 [CA 1] Center 38 (7~69) winsize 63
5520 11:44:21.297343 [CA 2] Center 35 (5~66) winsize 62
5521 11:44:21.300905 [CA 3] Center 35 (5~65) winsize 61
5522 11:44:21.304049 [CA 4] Center 35 (5~65) winsize 61
5523 11:44:21.307299 [CA 5] Center 34 (4~64) winsize 61
5524 11:44:21.307382
5525 11:44:21.310968 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5526 11:44:21.311051
5527 11:44:21.314190 [CATrainingPosCal] consider 2 rank data
5528 11:44:21.317414 u2DelayCellTimex100 = 270/100 ps
5529 11:44:21.320472 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5530 11:44:21.327434 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5531 11:44:21.330973 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5532 11:44:21.334054 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5533 11:44:21.337119 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5534 11:44:21.340656 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5535 11:44:21.340738
5536 11:44:21.343908 CA PerBit enable=1, Macro0, CA PI delay=34
5537 11:44:21.344007
5538 11:44:21.347131 [CBTSetCACLKResult] CA Dly = 34
5539 11:44:21.347213 CS Dly: 7 (0~39)
5540 11:44:21.350914
5541 11:44:21.353935 ----->DramcWriteLeveling(PI) begin...
5542 11:44:21.354028 ==
5543 11:44:21.357380 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 11:44:21.360586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 11:44:21.360669 ==
5546 11:44:21.363792 Write leveling (Byte 0): 25 => 25
5547 11:44:21.367030 Write leveling (Byte 1): 28 => 28
5548 11:44:21.370344 DramcWriteLeveling(PI) end<-----
5549 11:44:21.370427
5550 11:44:21.370492 ==
5551 11:44:21.373930 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 11:44:21.376915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 11:44:21.377022 ==
5554 11:44:21.380431 [Gating] SW mode calibration
5555 11:44:21.387021 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 11:44:21.393670 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 11:44:21.396883 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 11:44:21.399900 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 11:44:21.406830 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 11:44:21.410087 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 11:44:21.413300 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 11:44:21.419900 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5563 11:44:21.423132 0 14 24 | B1->B0 | 3333 3232 | 0 0 | (0 1) (0 1)
5564 11:44:21.426447 0 14 28 | B1->B0 | 2626 2727 | 0 0 | (1 0) (1 1)
5565 11:44:21.432927 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 11:44:21.436687 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 11:44:21.439882 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 11:44:21.446376 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 11:44:21.449575 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 11:44:21.453181 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 11:44:21.459579 0 15 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5572 11:44:21.463190 0 15 28 | B1->B0 | 3d3d 3f3f | 0 1 | (0 0) (0 0)
5573 11:44:21.466404 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 11:44:21.472779 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 11:44:21.476316 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 11:44:21.479386 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 11:44:21.485873 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:44:21.489392 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:44:21.492787 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5580 11:44:21.499616 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5581 11:44:21.502851 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:44:21.506092 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:44:21.512443 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:44:21.515794 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:44:21.519122 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:44:21.525931 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:44:21.529193 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:44:21.532392 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:44:21.539143 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:44:21.542398 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:44:21.545848 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:44:21.548892 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:44:21.555979 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:44:21.559134 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:44:21.562160 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5596 11:44:21.565819 Total UI for P1: 0, mck2ui 16
5597 11:44:21.568892 best dqsien dly found for B0: ( 1, 2, 22)
5598 11:44:21.575252 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5599 11:44:21.578931 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 11:44:21.581966 Total UI for P1: 0, mck2ui 16
5601 11:44:21.585348 best dqsien dly found for B1: ( 1, 2, 26)
5602 11:44:21.588405 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5603 11:44:21.591970 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5604 11:44:21.592063
5605 11:44:21.595143 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5606 11:44:21.601580 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5607 11:44:21.601693 [Gating] SW calibration Done
5608 11:44:21.601791 ==
5609 11:44:21.605234 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 11:44:21.611509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 11:44:21.611594 ==
5612 11:44:21.611660 RX Vref Scan: 0
5613 11:44:21.611722
5614 11:44:21.614972 RX Vref 0 -> 0, step: 1
5615 11:44:21.615055
5616 11:44:21.618332 RX Delay -80 -> 252, step: 8
5617 11:44:21.621682 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5618 11:44:21.624857 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5619 11:44:21.628170 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5620 11:44:21.634628 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5621 11:44:21.637934 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5622 11:44:21.641167 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5623 11:44:21.644379 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5624 11:44:21.648004 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5625 11:44:21.651050 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5626 11:44:21.657827 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5627 11:44:21.661101 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5628 11:44:21.664390 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5629 11:44:21.667446 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5630 11:44:21.671008 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5631 11:44:21.677672 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5632 11:44:21.680768 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5633 11:44:21.680878 ==
5634 11:44:21.683976 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:44:21.687684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:44:21.687768 ==
5637 11:44:21.687834 DQS Delay:
5638 11:44:21.690689 DQS0 = 0, DQS1 = 0
5639 11:44:21.690772 DQM Delay:
5640 11:44:21.694253 DQM0 = 101, DQM1 = 95
5641 11:44:21.694336 DQ Delay:
5642 11:44:21.697377 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5643 11:44:21.700684 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5644 11:44:21.703820 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5645 11:44:21.707111 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5646 11:44:21.707194
5647 11:44:21.707259
5648 11:44:21.707319 ==
5649 11:44:21.710728 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 11:44:21.717081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 11:44:21.717164 ==
5652 11:44:21.717230
5653 11:44:21.717291
5654 11:44:21.717350 TX Vref Scan disable
5655 11:44:21.720728 == TX Byte 0 ==
5656 11:44:21.724395 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5657 11:44:21.730748 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5658 11:44:21.730831 == TX Byte 1 ==
5659 11:44:21.734023 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5660 11:44:21.740959 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5661 11:44:21.741078 ==
5662 11:44:21.744128 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 11:44:21.747309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 11:44:21.747393 ==
5665 11:44:21.747458
5666 11:44:21.747519
5667 11:44:21.750420 TX Vref Scan disable
5668 11:44:21.750503 == TX Byte 0 ==
5669 11:44:21.757260 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5670 11:44:21.760758 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5671 11:44:21.760842 == TX Byte 1 ==
5672 11:44:21.767360 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5673 11:44:21.770784 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5674 11:44:21.770872
5675 11:44:21.770937 [DATLAT]
5676 11:44:21.774027 Freq=933, CH1 RK0
5677 11:44:21.774111
5678 11:44:21.774176 DATLAT Default: 0xd
5679 11:44:21.777286 0, 0xFFFF, sum = 0
5680 11:44:21.777371 1, 0xFFFF, sum = 0
5681 11:44:21.780561 2, 0xFFFF, sum = 0
5682 11:44:21.780648 3, 0xFFFF, sum = 0
5683 11:44:21.783548 4, 0xFFFF, sum = 0
5684 11:44:21.787020 5, 0xFFFF, sum = 0
5685 11:44:21.787104 6, 0xFFFF, sum = 0
5686 11:44:21.790651 7, 0xFFFF, sum = 0
5687 11:44:21.790740 8, 0xFFFF, sum = 0
5688 11:44:21.793659 9, 0xFFFF, sum = 0
5689 11:44:21.793743 10, 0x0, sum = 1
5690 11:44:21.797050 11, 0x0, sum = 2
5691 11:44:21.797134 12, 0x0, sum = 3
5692 11:44:21.797201 13, 0x0, sum = 4
5693 11:44:21.800238 best_step = 11
5694 11:44:21.800321
5695 11:44:21.800388 ==
5696 11:44:21.803626 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:44:21.807093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:44:21.807177 ==
5699 11:44:21.810292 RX Vref Scan: 1
5700 11:44:21.810375
5701 11:44:21.813441 RX Vref 0 -> 0, step: 1
5702 11:44:21.813523
5703 11:44:21.813588 RX Delay -53 -> 252, step: 4
5704 11:44:21.813648
5705 11:44:21.816590 Set Vref, RX VrefLevel [Byte0]: 52
5706 11:44:21.819821 [Byte1]: 48
5707 11:44:21.824761
5708 11:44:21.824845 Final RX Vref Byte 0 = 52 to rank0
5709 11:44:21.827962 Final RX Vref Byte 1 = 48 to rank0
5710 11:44:21.831319 Final RX Vref Byte 0 = 52 to rank1
5711 11:44:21.834519 Final RX Vref Byte 1 = 48 to rank1==
5712 11:44:21.837905 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 11:44:21.844750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 11:44:21.844837 ==
5715 11:44:21.844903 DQS Delay:
5716 11:44:21.847979 DQS0 = 0, DQS1 = 0
5717 11:44:21.848067 DQM Delay:
5718 11:44:21.848134 DQM0 = 104, DQM1 = 97
5719 11:44:21.851144 DQ Delay:
5720 11:44:21.854505 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5721 11:44:21.857977 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =100
5722 11:44:21.860878 DQ8 =86, DQ9 =84, DQ10 =102, DQ11 =90
5723 11:44:21.864160 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =100
5724 11:44:21.864252
5725 11:44:21.864321
5726 11:44:21.874420 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5727 11:44:21.874518 CH1 RK0: MR19=505, MR18=1C34
5728 11:44:21.881090 CH1_RK0: MR19=0x505, MR18=0x1C34, DQSOSC=405, MR23=63, INC=66, DEC=44
5729 11:44:21.881177
5730 11:44:21.884218 ----->DramcWriteLeveling(PI) begin...
5731 11:44:21.884333 ==
5732 11:44:21.887359 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 11:44:21.894193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 11:44:21.894289 ==
5735 11:44:21.897163 Write leveling (Byte 0): 24 => 24
5736 11:44:21.897246 Write leveling (Byte 1): 27 => 27
5737 11:44:21.900580 DramcWriteLeveling(PI) end<-----
5738 11:44:21.900663
5739 11:44:21.903680 ==
5740 11:44:21.907206 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 11:44:21.910321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 11:44:21.910421 ==
5743 11:44:21.913924 [Gating] SW mode calibration
5744 11:44:21.920427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5745 11:44:21.923751 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5746 11:44:21.930531 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5747 11:44:21.933700 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 11:44:21.936948 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 11:44:21.943491 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 11:44:21.946817 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 11:44:21.950367 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 11:44:21.956929 0 14 24 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
5753 11:44:21.960131 0 14 28 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (0 0)
5754 11:44:21.963313 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5755 11:44:21.969915 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 11:44:21.973531 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 11:44:21.976731 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 11:44:21.983356 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 11:44:21.986494 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 11:44:21.989757 0 15 24 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5761 11:44:21.996765 0 15 28 | B1->B0 | 4646 3d3d | 0 1 | (0 0) (0 0)
5762 11:44:21.999727 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5763 11:44:22.002986 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 11:44:22.009519 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 11:44:22.013028 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 11:44:22.016479 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 11:44:22.022868 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 11:44:22.026127 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5769 11:44:22.029545 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5770 11:44:22.036277 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 11:44:22.039544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:44:22.042815 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:44:22.049395 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:44:22.052802 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:44:22.055879 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:44:22.062346 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:44:22.065621 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:44:22.069176 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:44:22.075797 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:44:22.079031 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:44:22.082378 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:44:22.088920 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:44:22.092267 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:44:22.095562 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5785 11:44:22.101873 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 11:44:22.101961 Total UI for P1: 0, mck2ui 16
5787 11:44:22.108558 best dqsien dly found for B0: ( 1, 2, 24)
5788 11:44:22.108644 Total UI for P1: 0, mck2ui 16
5789 11:44:22.115398 best dqsien dly found for B1: ( 1, 2, 24)
5790 11:44:22.118506 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5791 11:44:22.121698 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5792 11:44:22.121784
5793 11:44:22.124875 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 11:44:22.128187 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5795 11:44:22.131341 [Gating] SW calibration Done
5796 11:44:22.131425 ==
5797 11:44:22.134992 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 11:44:22.138156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 11:44:22.138241 ==
5800 11:44:22.141495 RX Vref Scan: 0
5801 11:44:22.141580
5802 11:44:22.141646 RX Vref 0 -> 0, step: 1
5803 11:44:22.141707
5804 11:44:22.144751 RX Delay -80 -> 252, step: 8
5805 11:44:22.151457 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5806 11:44:22.154679 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5807 11:44:22.157855 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5808 11:44:22.161450 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5809 11:44:22.164275 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5810 11:44:22.168004 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5811 11:44:22.174220 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5812 11:44:22.177956 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5813 11:44:22.180823 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5814 11:44:22.184165 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5815 11:44:22.187708 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5816 11:44:22.194045 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5817 11:44:22.197196 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5818 11:44:22.200363 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5819 11:44:22.203834 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5820 11:44:22.207348 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5821 11:44:22.207445 ==
5822 11:44:22.210624 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:44:22.216974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:44:22.217082 ==
5825 11:44:22.217148 DQS Delay:
5826 11:44:22.220498 DQS0 = 0, DQS1 = 0
5827 11:44:22.220592 DQM Delay:
5828 11:44:22.223655 DQM0 = 102, DQM1 = 95
5829 11:44:22.223763 DQ Delay:
5830 11:44:22.226709 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5831 11:44:22.229953 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5832 11:44:22.233331 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5833 11:44:22.236935 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =107
5834 11:44:22.237058
5835 11:44:22.237124
5836 11:44:22.237184 ==
5837 11:44:22.240052 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 11:44:22.243670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 11:44:22.246940 ==
5840 11:44:22.247025
5841 11:44:22.247091
5842 11:44:22.247152 TX Vref Scan disable
5843 11:44:22.250079 == TX Byte 0 ==
5844 11:44:22.253310 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5845 11:44:22.256721 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5846 11:44:22.259783 == TX Byte 1 ==
5847 11:44:22.262993 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5848 11:44:22.266237 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5849 11:44:22.269462 ==
5850 11:44:22.272969 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 11:44:22.276158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 11:44:22.276237 ==
5853 11:44:22.276304
5854 11:44:22.276365
5855 11:44:22.279738 TX Vref Scan disable
5856 11:44:22.279813 == TX Byte 0 ==
5857 11:44:22.285957 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5858 11:44:22.289808 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5859 11:44:22.289885 == TX Byte 1 ==
5860 11:44:22.295993 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5861 11:44:22.299601 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5862 11:44:22.299678
5863 11:44:22.299746 [DATLAT]
5864 11:44:22.302739 Freq=933, CH1 RK1
5865 11:44:22.302816
5866 11:44:22.302879 DATLAT Default: 0xb
5867 11:44:22.305912 0, 0xFFFF, sum = 0
5868 11:44:22.305990 1, 0xFFFF, sum = 0
5869 11:44:22.309380 2, 0xFFFF, sum = 0
5870 11:44:22.309464 3, 0xFFFF, sum = 0
5871 11:44:22.312653 4, 0xFFFF, sum = 0
5872 11:44:22.312734 5, 0xFFFF, sum = 0
5873 11:44:22.315881 6, 0xFFFF, sum = 0
5874 11:44:22.319378 7, 0xFFFF, sum = 0
5875 11:44:22.319452 8, 0xFFFF, sum = 0
5876 11:44:22.322554 9, 0xFFFF, sum = 0
5877 11:44:22.322625 10, 0x0, sum = 1
5878 11:44:22.322686 11, 0x0, sum = 2
5879 11:44:22.326061 12, 0x0, sum = 3
5880 11:44:22.326134 13, 0x0, sum = 4
5881 11:44:22.329202 best_step = 11
5882 11:44:22.329272
5883 11:44:22.329332 ==
5884 11:44:22.332825 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 11:44:22.335681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 11:44:22.335754 ==
5887 11:44:22.339075 RX Vref Scan: 0
5888 11:44:22.339145
5889 11:44:22.339205 RX Vref 0 -> 0, step: 1
5890 11:44:22.342512
5891 11:44:22.342589 RX Delay -53 -> 252, step: 4
5892 11:44:22.349702 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5893 11:44:22.353254 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5894 11:44:22.356494 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5895 11:44:22.359793 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5896 11:44:22.366305 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5897 11:44:22.369457 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5898 11:44:22.372840 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5899 11:44:22.376360 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5900 11:44:22.379601 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5901 11:44:22.382624 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5902 11:44:22.389413 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5903 11:44:22.392727 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5904 11:44:22.396000 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5905 11:44:22.399158 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5906 11:44:22.402746 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5907 11:44:22.409217 iDelay=199, Bit 15, Center 104 (19 ~ 190) 172
5908 11:44:22.409295 ==
5909 11:44:22.412776 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:44:22.415749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:44:22.415827 ==
5912 11:44:22.415891 DQS Delay:
5913 11:44:22.418938 DQS0 = 0, DQS1 = 0
5914 11:44:22.419014 DQM Delay:
5915 11:44:22.422570 DQM0 = 105, DQM1 = 97
5916 11:44:22.422644 DQ Delay:
5917 11:44:22.425655 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =104
5918 11:44:22.428788 DQ4 =108, DQ5 =114, DQ6 =112, DQ7 =104
5919 11:44:22.432279 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5920 11:44:22.435459 DQ12 =104, DQ13 =102, DQ14 =106, DQ15 =104
5921 11:44:22.435537
5922 11:44:22.435600
5923 11:44:22.445531 [DQSOSCAuto] RK1, (LSB)MR18= 0x21fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5924 11:44:22.448742 CH1 RK1: MR19=504, MR18=21FE
5925 11:44:22.452404 CH1_RK1: MR19=0x504, MR18=0x21FE, DQSOSC=411, MR23=63, INC=64, DEC=42
5926 11:44:22.455612 [RxdqsGatingPostProcess] freq 933
5927 11:44:22.462088 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5928 11:44:22.465556 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 11:44:22.468744 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 11:44:22.471960 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 11:44:22.475200 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 11:44:22.478619 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 11:44:22.481845 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 11:44:22.484917 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 11:44:22.488634 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 11:44:22.491626 Pre-setting of DQS Precalculation
5937 11:44:22.494979 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5938 11:44:22.501641 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5939 11:44:22.511278 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5940 11:44:22.511370
5941 11:44:22.511438
5942 11:44:22.514419 [Calibration Summary] 1866 Mbps
5943 11:44:22.514503 CH 0, Rank 0
5944 11:44:22.517772 SW Impedance : PASS
5945 11:44:22.517856 DUTY Scan : NO K
5946 11:44:22.520996 ZQ Calibration : PASS
5947 11:44:22.524606 Jitter Meter : NO K
5948 11:44:22.524690 CBT Training : PASS
5949 11:44:22.527614 Write leveling : PASS
5950 11:44:22.527699 RX DQS gating : PASS
5951 11:44:22.531160 RX DQ/DQS(RDDQC) : PASS
5952 11:44:22.534406 TX DQ/DQS : PASS
5953 11:44:22.534492 RX DATLAT : PASS
5954 11:44:22.537731 RX DQ/DQS(Engine): PASS
5955 11:44:22.540852 TX OE : NO K
5956 11:44:22.540963 All Pass.
5957 11:44:22.541076
5958 11:44:22.541139 CH 0, Rank 1
5959 11:44:22.544199 SW Impedance : PASS
5960 11:44:22.547534 DUTY Scan : NO K
5961 11:44:22.547618 ZQ Calibration : PASS
5962 11:44:22.551018 Jitter Meter : NO K
5963 11:44:22.554081 CBT Training : PASS
5964 11:44:22.554171 Write leveling : PASS
5965 11:44:22.557331 RX DQS gating : PASS
5966 11:44:22.560948 RX DQ/DQS(RDDQC) : PASS
5967 11:44:22.561097 TX DQ/DQS : PASS
5968 11:44:22.564285 RX DATLAT : PASS
5969 11:44:22.567555 RX DQ/DQS(Engine): PASS
5970 11:44:22.567667 TX OE : NO K
5971 11:44:22.570852 All Pass.
5972 11:44:22.570975
5973 11:44:22.571074 CH 1, Rank 0
5974 11:44:22.574042 SW Impedance : PASS
5975 11:44:22.574166 DUTY Scan : NO K
5976 11:44:22.577559 ZQ Calibration : PASS
5977 11:44:22.580724 Jitter Meter : NO K
5978 11:44:22.580877 CBT Training : PASS
5979 11:44:22.584023 Write leveling : PASS
5980 11:44:22.587347 RX DQS gating : PASS
5981 11:44:22.587523 RX DQ/DQS(RDDQC) : PASS
5982 11:44:22.590423 TX DQ/DQS : PASS
5983 11:44:22.593956 RX DATLAT : PASS
5984 11:44:22.594162 RX DQ/DQS(Engine): PASS
5985 11:44:22.597192 TX OE : NO K
5986 11:44:22.597436 All Pass.
5987 11:44:22.597629
5988 11:44:22.600751 CH 1, Rank 1
5989 11:44:22.601082 SW Impedance : PASS
5990 11:44:22.604095 DUTY Scan : NO K
5991 11:44:22.604431 ZQ Calibration : PASS
5992 11:44:22.607141 Jitter Meter : NO K
5993 11:44:22.610615 CBT Training : PASS
5994 11:44:22.611109 Write leveling : PASS
5995 11:44:22.613923 RX DQS gating : PASS
5996 11:44:22.617086 RX DQ/DQS(RDDQC) : PASS
5997 11:44:22.617559 TX DQ/DQS : PASS
5998 11:44:22.620638 RX DATLAT : PASS
5999 11:44:22.623595 RX DQ/DQS(Engine): PASS
6000 11:44:22.624067 TX OE : NO K
6001 11:44:22.626960 All Pass.
6002 11:44:22.627429
6003 11:44:22.627800 DramC Write-DBI off
6004 11:44:22.630340 PER_BANK_REFRESH: Hybrid Mode
6005 11:44:22.633789 TX_TRACKING: ON
6006 11:44:22.640546 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6007 11:44:22.643596 [FAST_K] Save calibration result to emmc
6008 11:44:22.646884 dramc_set_vcore_voltage set vcore to 650000
6009 11:44:22.650118 Read voltage for 400, 6
6010 11:44:22.650605 Vio18 = 0
6011 11:44:22.653456 Vcore = 650000
6012 11:44:22.653929 Vdram = 0
6013 11:44:22.654303 Vddq = 0
6014 11:44:22.656668 Vmddr = 0
6015 11:44:22.660236 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6016 11:44:22.666898 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6017 11:44:22.667370 MEM_TYPE=3, freq_sel=20
6018 11:44:22.670037 sv_algorithm_assistance_LP4_800
6019 11:44:22.676504 ============ PULL DRAM RESETB DOWN ============
6020 11:44:22.680300 ========== PULL DRAM RESETB DOWN end =========
6021 11:44:22.683185 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 11:44:22.686752 ===================================
6023 11:44:22.689804 LPDDR4 DRAM CONFIGURATION
6024 11:44:22.693159 ===================================
6025 11:44:22.696635 EX_ROW_EN[0] = 0x0
6026 11:44:22.697295 EX_ROW_EN[1] = 0x0
6027 11:44:22.699680 LP4Y_EN = 0x0
6028 11:44:22.700143 WORK_FSP = 0x0
6029 11:44:22.702844 WL = 0x2
6030 11:44:22.703337 RL = 0x2
6031 11:44:22.706616 BL = 0x2
6032 11:44:22.707082 RPST = 0x0
6033 11:44:22.709681 RD_PRE = 0x0
6034 11:44:22.710218 WR_PRE = 0x1
6035 11:44:22.712923 WR_PST = 0x0
6036 11:44:22.713462 DBI_WR = 0x0
6037 11:44:22.716545 DBI_RD = 0x0
6038 11:44:22.717078 OTF = 0x1
6039 11:44:22.719804 ===================================
6040 11:44:22.722978 ===================================
6041 11:44:22.726081 ANA top config
6042 11:44:22.729510 ===================================
6043 11:44:22.732731 DLL_ASYNC_EN = 0
6044 11:44:22.733249 ALL_SLAVE_EN = 1
6045 11:44:22.736104 NEW_RANK_MODE = 1
6046 11:44:22.739561 DLL_IDLE_MODE = 1
6047 11:44:22.742831 LP45_APHY_COMB_EN = 1
6048 11:44:22.746325 TX_ODT_DIS = 1
6049 11:44:22.746908 NEW_8X_MODE = 1
6050 11:44:22.749241 ===================================
6051 11:44:22.752631 ===================================
6052 11:44:22.755875 data_rate = 800
6053 11:44:22.759073 CKR = 1
6054 11:44:22.762691 DQ_P2S_RATIO = 4
6055 11:44:22.765871 ===================================
6056 11:44:22.769075 CA_P2S_RATIO = 4
6057 11:44:22.772343 DQ_CA_OPEN = 0
6058 11:44:22.772877 DQ_SEMI_OPEN = 1
6059 11:44:22.775584 CA_SEMI_OPEN = 1
6060 11:44:22.778895 CA_FULL_RATE = 0
6061 11:44:22.782030 DQ_CKDIV4_EN = 0
6062 11:44:22.785329 CA_CKDIV4_EN = 1
6063 11:44:22.788679 CA_PREDIV_EN = 0
6064 11:44:22.789230 PH8_DLY = 0
6065 11:44:22.791907 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6066 11:44:22.795599 DQ_AAMCK_DIV = 0
6067 11:44:22.798783 CA_AAMCK_DIV = 0
6068 11:44:22.802368 CA_ADMCK_DIV = 4
6069 11:44:22.805341 DQ_TRACK_CA_EN = 0
6070 11:44:22.805846 CA_PICK = 800
6071 11:44:22.808671 CA_MCKIO = 400
6072 11:44:22.812320 MCKIO_SEMI = 400
6073 11:44:22.815424 PLL_FREQ = 3016
6074 11:44:22.818528 DQ_UI_PI_RATIO = 32
6075 11:44:22.821816 CA_UI_PI_RATIO = 32
6076 11:44:22.825065 ===================================
6077 11:44:22.828720 ===================================
6078 11:44:22.831855 memory_type:LPDDR4
6079 11:44:22.832316 GP_NUM : 10
6080 11:44:22.835390 SRAM_EN : 1
6081 11:44:22.835849 MD32_EN : 0
6082 11:44:22.838511 ===================================
6083 11:44:22.841696 [ANA_INIT] >>>>>>>>>>>>>>
6084 11:44:22.844927 <<<<<< [CONFIGURE PHASE]: ANA_TX
6085 11:44:22.848324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6086 11:44:22.851621 ===================================
6087 11:44:22.855145 data_rate = 800,PCW = 0X7400
6088 11:44:22.858157 ===================================
6089 11:44:22.861302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6090 11:44:22.868298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 11:44:22.877900 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 11:44:22.881453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6093 11:44:22.884801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6094 11:44:22.891217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6095 11:44:22.891723 [ANA_INIT] flow start
6096 11:44:22.894558 [ANA_INIT] PLL >>>>>>>>
6097 11:44:22.897911 [ANA_INIT] PLL <<<<<<<<
6098 11:44:22.898382 [ANA_INIT] MIDPI >>>>>>>>
6099 11:44:22.901119 [ANA_INIT] MIDPI <<<<<<<<
6100 11:44:22.904154 [ANA_INIT] DLL >>>>>>>>
6101 11:44:22.904622 [ANA_INIT] flow end
6102 11:44:22.907833 ============ LP4 DIFF to SE enter ============
6103 11:44:22.914543 ============ LP4 DIFF to SE exit ============
6104 11:44:22.915021 [ANA_INIT] <<<<<<<<<<<<<
6105 11:44:22.917683 [Flow] Enable top DCM control >>>>>
6106 11:44:22.920677 [Flow] Enable top DCM control <<<<<
6107 11:44:22.924210 Enable DLL master slave shuffle
6108 11:44:22.930684 ==============================================================
6109 11:44:22.934322 Gating Mode config
6110 11:44:22.937497 ==============================================================
6111 11:44:22.941113 Config description:
6112 11:44:22.950719 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6113 11:44:22.957257 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6114 11:44:22.960797 SELPH_MODE 0: By rank 1: By Phase
6115 11:44:22.967213 ==============================================================
6116 11:44:22.970595 GAT_TRACK_EN = 0
6117 11:44:22.974009 RX_GATING_MODE = 2
6118 11:44:22.974631 RX_GATING_TRACK_MODE = 2
6119 11:44:22.977411 SELPH_MODE = 1
6120 11:44:22.980502 PICG_EARLY_EN = 1
6121 11:44:22.983748 VALID_LAT_VALUE = 1
6122 11:44:22.990616 ==============================================================
6123 11:44:22.993734 Enter into Gating configuration >>>>
6124 11:44:22.997254 Exit from Gating configuration <<<<
6125 11:44:23.000563 Enter into DVFS_PRE_config >>>>>
6126 11:44:23.010310 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6127 11:44:23.013548 Exit from DVFS_PRE_config <<<<<
6128 11:44:23.016701 Enter into PICG configuration >>>>
6129 11:44:23.019956 Exit from PICG configuration <<<<
6130 11:44:23.023608 [RX_INPUT] configuration >>>>>
6131 11:44:23.026624 [RX_INPUT] configuration <<<<<
6132 11:44:23.029700 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6133 11:44:23.036715 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6134 11:44:23.043061 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 11:44:23.049767 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 11:44:23.056054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 11:44:23.059562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 11:44:23.066335 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6139 11:44:23.069512 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6140 11:44:23.072501 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6141 11:44:23.076251 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6142 11:44:23.082509 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6143 11:44:23.085984 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 11:44:23.089299 ===================================
6145 11:44:23.092632 LPDDR4 DRAM CONFIGURATION
6146 11:44:23.095901 ===================================
6147 11:44:23.096060 EX_ROW_EN[0] = 0x0
6148 11:44:23.099288 EX_ROW_EN[1] = 0x0
6149 11:44:23.099410 LP4Y_EN = 0x0
6150 11:44:23.102783 WORK_FSP = 0x0
6151 11:44:23.103161 WL = 0x2
6152 11:44:23.105891 RL = 0x2
6153 11:44:23.106392 BL = 0x2
6154 11:44:23.109081 RPST = 0x0
6155 11:44:23.112328 RD_PRE = 0x0
6156 11:44:23.112756 WR_PRE = 0x1
6157 11:44:23.115899 WR_PST = 0x0
6158 11:44:23.116358 DBI_WR = 0x0
6159 11:44:23.119671 DBI_RD = 0x0
6160 11:44:23.120166 OTF = 0x1
6161 11:44:23.122863 ===================================
6162 11:44:23.126132 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6163 11:44:23.132389 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6164 11:44:23.135952 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 11:44:23.139134 ===================================
6166 11:44:23.142232 LPDDR4 DRAM CONFIGURATION
6167 11:44:23.145783 ===================================
6168 11:44:23.146419 EX_ROW_EN[0] = 0x10
6169 11:44:23.149368 EX_ROW_EN[1] = 0x0
6170 11:44:23.149951 LP4Y_EN = 0x0
6171 11:44:23.152537 WORK_FSP = 0x0
6172 11:44:23.153145 WL = 0x2
6173 11:44:23.155541 RL = 0x2
6174 11:44:23.156050 BL = 0x2
6175 11:44:23.159126 RPST = 0x0
6176 11:44:23.162069 RD_PRE = 0x0
6177 11:44:23.162772 WR_PRE = 0x1
6178 11:44:23.165685 WR_PST = 0x0
6179 11:44:23.166331 DBI_WR = 0x0
6180 11:44:23.168864 DBI_RD = 0x0
6181 11:44:23.169506 OTF = 0x1
6182 11:44:23.172153 ===================================
6183 11:44:23.178495 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6184 11:44:23.182544 nWR fixed to 30
6185 11:44:23.185875 [ModeRegInit_LP4] CH0 RK0
6186 11:44:23.186345 [ModeRegInit_LP4] CH0 RK1
6187 11:44:23.189059 [ModeRegInit_LP4] CH1 RK0
6188 11:44:23.192328 [ModeRegInit_LP4] CH1 RK1
6189 11:44:23.192790 match AC timing 19
6190 11:44:23.198894 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6191 11:44:23.202628 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6192 11:44:23.205716 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6193 11:44:23.212094 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6194 11:44:23.215353 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6195 11:44:23.215828 ==
6196 11:44:23.219026 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 11:44:23.222071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6198 11:44:23.222545 ==
6199 11:44:23.228493 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6200 11:44:23.235246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6201 11:44:23.238491 [CA 0] Center 36 (8~64) winsize 57
6202 11:44:23.241989 [CA 1] Center 36 (8~64) winsize 57
6203 11:44:23.245267 [CA 2] Center 36 (8~64) winsize 57
6204 11:44:23.248308 [CA 3] Center 36 (8~64) winsize 57
6205 11:44:23.251859 [CA 4] Center 36 (8~64) winsize 57
6206 11:44:23.255014 [CA 5] Center 36 (8~64) winsize 57
6207 11:44:23.255527
6208 11:44:23.258166 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6209 11:44:23.258782
6210 11:44:23.261882 [CATrainingPosCal] consider 1 rank data
6211 11:44:23.265078 u2DelayCellTimex100 = 270/100 ps
6212 11:44:23.267939 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 11:44:23.271472 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 11:44:23.274641 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:44:23.277804 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 11:44:23.280991 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 11:44:23.284554 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:44:23.284750
6219 11:44:23.290961 CA PerBit enable=1, Macro0, CA PI delay=36
6220 11:44:23.291148
6221 11:44:23.291291 [CBTSetCACLKResult] CA Dly = 36
6222 11:44:23.294292 CS Dly: 1 (0~32)
6223 11:44:23.294429 ==
6224 11:44:23.297390 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 11:44:23.301020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 11:44:23.301130 ==
6227 11:44:23.307602 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 11:44:23.314067 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6229 11:44:23.317776 [CA 0] Center 36 (8~64) winsize 57
6230 11:44:23.321047 [CA 1] Center 36 (8~64) winsize 57
6231 11:44:23.324367 [CA 2] Center 36 (8~64) winsize 57
6232 11:44:23.324926 [CA 3] Center 36 (8~64) winsize 57
6233 11:44:23.327972 [CA 4] Center 36 (8~64) winsize 57
6234 11:44:23.331239 [CA 5] Center 36 (8~64) winsize 57
6235 11:44:23.331720
6236 11:44:23.337325 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6237 11:44:23.337754
6238 11:44:23.341127 [CATrainingPosCal] consider 2 rank data
6239 11:44:23.344101 u2DelayCellTimex100 = 270/100 ps
6240 11:44:23.347737 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 11:44:23.350925 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:44:23.354049 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:44:23.357409 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:44:23.360555 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:44:23.364044 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:44:23.364595
6247 11:44:23.367169 CA PerBit enable=1, Macro0, CA PI delay=36
6248 11:44:23.367615
6249 11:44:23.370713 [CBTSetCACLKResult] CA Dly = 36
6250 11:44:23.374094 CS Dly: 1 (0~32)
6251 11:44:23.374520
6252 11:44:23.377265 ----->DramcWriteLeveling(PI) begin...
6253 11:44:23.377697 ==
6254 11:44:23.380453 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 11:44:23.383663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 11:44:23.384093 ==
6257 11:44:23.387371 Write leveling (Byte 0): 40 => 8
6258 11:44:23.390574 Write leveling (Byte 1): 32 => 0
6259 11:44:23.393804 DramcWriteLeveling(PI) end<-----
6260 11:44:23.394272
6261 11:44:23.394607 ==
6262 11:44:23.397263 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 11:44:23.400414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 11:44:23.400845 ==
6265 11:44:23.404067 [Gating] SW mode calibration
6266 11:44:23.410704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6267 11:44:23.417170 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6268 11:44:23.420267 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 11:44:23.423428 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 11:44:23.429863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 11:44:23.433493 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 11:44:23.436666 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 11:44:23.443119 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 11:44:23.446641 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 11:44:23.449667 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 11:44:23.456430 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 11:44:23.459437 Total UI for P1: 0, mck2ui 16
6278 11:44:23.463226 best dqsien dly found for B0: ( 0, 14, 24)
6279 11:44:23.466227 Total UI for P1: 0, mck2ui 16
6280 11:44:23.469691 best dqsien dly found for B1: ( 0, 14, 24)
6281 11:44:23.472908 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6282 11:44:23.475899 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6283 11:44:23.476008
6284 11:44:23.479502 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 11:44:23.482786 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 11:44:23.485903 [Gating] SW calibration Done
6287 11:44:23.485987 ==
6288 11:44:23.489106 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 11:44:23.492503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 11:44:23.492589 ==
6291 11:44:23.495718 RX Vref Scan: 0
6292 11:44:23.495801
6293 11:44:23.499360 RX Vref 0 -> 0, step: 1
6294 11:44:23.499442
6295 11:44:23.499506 RX Delay -410 -> 252, step: 16
6296 11:44:23.506000 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6297 11:44:23.509672 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6298 11:44:23.512896 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6299 11:44:23.516057 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6300 11:44:23.522476 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6301 11:44:23.525852 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6302 11:44:23.529579 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6303 11:44:23.532514 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6304 11:44:23.539151 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6305 11:44:23.542306 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6306 11:44:23.546059 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6307 11:44:23.552454 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6308 11:44:23.555581 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6309 11:44:23.558830 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6310 11:44:23.562515 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6311 11:44:23.569246 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6312 11:44:23.569447 ==
6313 11:44:23.572280 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 11:44:23.575530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:44:23.575832 ==
6316 11:44:23.576068 DQS Delay:
6317 11:44:23.578997 DQS0 = 19, DQS1 = 43
6318 11:44:23.579294 DQM Delay:
6319 11:44:23.582589 DQM0 = 5, DQM1 = 14
6320 11:44:23.582970 DQ Delay:
6321 11:44:23.585805 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6322 11:44:23.589139 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6323 11:44:23.592116 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6324 11:44:23.596024 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6325 11:44:23.596673
6326 11:44:23.597235
6327 11:44:23.597595 ==
6328 11:44:23.599038 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 11:44:23.602336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 11:44:23.602823 ==
6331 11:44:23.603204
6332 11:44:23.603753
6333 11:44:23.605464 TX Vref Scan disable
6334 11:44:23.606089 == TX Byte 0 ==
6335 11:44:23.612535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 11:44:23.615679 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 11:44:23.616302 == TX Byte 1 ==
6338 11:44:23.622513 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6339 11:44:23.625646 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6340 11:44:23.626128 ==
6341 11:44:23.628915 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 11:44:23.632238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 11:44:23.632731 ==
6344 11:44:23.633140
6345 11:44:23.635354
6346 11:44:23.635837 TX Vref Scan disable
6347 11:44:23.638597 == TX Byte 0 ==
6348 11:44:23.641930 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 11:44:23.645481 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 11:44:23.648577 == TX Byte 1 ==
6351 11:44:23.651908 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6352 11:44:23.655634 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6353 11:44:23.656273
6354 11:44:23.656656 [DATLAT]
6355 11:44:23.658644 Freq=400, CH0 RK0
6356 11:44:23.659204
6357 11:44:23.661856 DATLAT Default: 0xf
6358 11:44:23.662321 0, 0xFFFF, sum = 0
6359 11:44:23.665226 1, 0xFFFF, sum = 0
6360 11:44:23.665795 2, 0xFFFF, sum = 0
6361 11:44:23.668729 3, 0xFFFF, sum = 0
6362 11:44:23.669272 4, 0xFFFF, sum = 0
6363 11:44:23.671557 5, 0xFFFF, sum = 0
6364 11:44:23.671916 6, 0xFFFF, sum = 0
6365 11:44:23.675117 7, 0xFFFF, sum = 0
6366 11:44:23.675445 8, 0xFFFF, sum = 0
6367 11:44:23.678454 9, 0xFFFF, sum = 0
6368 11:44:23.678739 10, 0xFFFF, sum = 0
6369 11:44:23.681614 11, 0xFFFF, sum = 0
6370 11:44:23.681836 12, 0xFFFF, sum = 0
6371 11:44:23.684722 13, 0x0, sum = 1
6372 11:44:23.684918 14, 0x0, sum = 2
6373 11:44:23.688141 15, 0x0, sum = 3
6374 11:44:23.688302 16, 0x0, sum = 4
6375 11:44:23.691231 best_step = 14
6376 11:44:23.691367
6377 11:44:23.691474 ==
6378 11:44:23.694886 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 11:44:23.698051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 11:44:23.698178 ==
6381 11:44:23.701104 RX Vref Scan: 1
6382 11:44:23.701211
6383 11:44:23.701295 RX Vref 0 -> 0, step: 1
6384 11:44:23.701373
6385 11:44:23.704892 RX Delay -327 -> 252, step: 8
6386 11:44:23.705051
6387 11:44:23.707953 Set Vref, RX VrefLevel [Byte0]: 60
6388 11:44:23.711015 [Byte1]: 52
6389 11:44:23.715647
6390 11:44:23.715774 Final RX Vref Byte 0 = 60 to rank0
6391 11:44:23.718935 Final RX Vref Byte 1 = 52 to rank0
6392 11:44:23.722212 Final RX Vref Byte 0 = 60 to rank1
6393 11:44:23.725796 Final RX Vref Byte 1 = 52 to rank1==
6394 11:44:23.728835 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 11:44:23.735609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 11:44:23.735723 ==
6397 11:44:23.735823 DQS Delay:
6398 11:44:23.739023 DQS0 = 24, DQS1 = 44
6399 11:44:23.739135 DQM Delay:
6400 11:44:23.739233 DQM0 = 9, DQM1 = 11
6401 11:44:23.742246 DQ Delay:
6402 11:44:23.745388 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =4
6403 11:44:23.745477 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6404 11:44:23.748852 DQ8 =4, DQ9 =0, DQ10 =8, DQ11 =4
6405 11:44:23.752091 DQ12 =16, DQ13 =12, DQ14 =24, DQ15 =20
6406 11:44:23.752177
6407 11:44:23.752242
6408 11:44:23.762005 [DQSOSCAuto] RK0, (LSB)MR18= 0xa59c, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6409 11:44:23.765214 CH0 RK0: MR19=C0C, MR18=A59C
6410 11:44:23.772053 CH0_RK0: MR19=0xC0C, MR18=0xA59C, DQSOSC=389, MR23=63, INC=390, DEC=260
6411 11:44:23.772201 ==
6412 11:44:23.775210 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 11:44:23.778468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 11:44:23.778580 ==
6415 11:44:23.782151 [Gating] SW mode calibration
6416 11:44:23.788810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6417 11:44:23.795409 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6418 11:44:23.798673 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 11:44:23.801948 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 11:44:23.808564 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 11:44:23.811893 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 11:44:23.815173 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 11:44:23.821643 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 11:44:23.825189 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:44:23.828436 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:44:23.834988 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 11:44:23.835458 Total UI for P1: 0, mck2ui 16
6428 11:44:23.838289 best dqsien dly found for B0: ( 0, 14, 24)
6429 11:44:23.841419 Total UI for P1: 0, mck2ui 16
6430 11:44:23.845027 best dqsien dly found for B1: ( 0, 14, 24)
6431 11:44:23.851083 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6432 11:44:23.854537 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6433 11:44:23.855137
6434 11:44:23.857809 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 11:44:23.861105 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 11:44:23.864658 [Gating] SW calibration Done
6437 11:44:23.865324 ==
6438 11:44:23.868036 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 11:44:23.871118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 11:44:23.871590 ==
6441 11:44:23.874205 RX Vref Scan: 0
6442 11:44:23.874844
6443 11:44:23.875383 RX Vref 0 -> 0, step: 1
6444 11:44:23.875920
6445 11:44:23.877813 RX Delay -410 -> 252, step: 16
6446 11:44:23.884038 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6447 11:44:23.887570 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6448 11:44:23.890649 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6449 11:44:23.894034 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6450 11:44:23.900664 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6451 11:44:23.903940 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6452 11:44:23.907188 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6453 11:44:23.910312 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6454 11:44:23.917030 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6455 11:44:23.920243 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6456 11:44:23.923517 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6457 11:44:23.929959 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6458 11:44:23.933620 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6459 11:44:23.936846 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6460 11:44:23.940051 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6461 11:44:23.946911 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6462 11:44:23.947596 ==
6463 11:44:23.950086 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 11:44:23.953098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 11:44:23.953475 ==
6466 11:44:23.953892 DQS Delay:
6467 11:44:23.956121 DQS0 = 27, DQS1 = 43
6468 11:44:23.956461 DQM Delay:
6469 11:44:23.959733 DQM0 = 10, DQM1 = 15
6470 11:44:23.960061 DQ Delay:
6471 11:44:23.963032 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6472 11:44:23.966022 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6473 11:44:23.969466 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6474 11:44:23.972868 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6475 11:44:23.973018
6476 11:44:23.973131
6477 11:44:23.973239 ==
6478 11:44:23.976066 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 11:44:23.979276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 11:44:23.979452 ==
6481 11:44:23.979595
6482 11:44:23.979729
6483 11:44:23.982366 TX Vref Scan disable
6484 11:44:23.985659 == TX Byte 0 ==
6485 11:44:23.988953 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6486 11:44:23.992530 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6487 11:44:23.995676 == TX Byte 1 ==
6488 11:44:23.999065 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6489 11:44:24.002517 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6490 11:44:24.002613 ==
6491 11:44:24.005496 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 11:44:24.009028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 11:44:24.009110 ==
6494 11:44:24.012402
6495 11:44:24.012482
6496 11:44:24.012548 TX Vref Scan disable
6497 11:44:24.015479 == TX Byte 0 ==
6498 11:44:24.018755 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6499 11:44:24.021970 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6500 11:44:24.025627 == TX Byte 1 ==
6501 11:44:24.028842 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6502 11:44:24.032133 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6503 11:44:24.032216
6504 11:44:24.032281 [DATLAT]
6505 11:44:24.035340 Freq=400, CH0 RK1
6506 11:44:24.035419
6507 11:44:24.038513 DATLAT Default: 0xe
6508 11:44:24.038593 0, 0xFFFF, sum = 0
6509 11:44:24.041740 1, 0xFFFF, sum = 0
6510 11:44:24.041820 2, 0xFFFF, sum = 0
6511 11:44:24.045127 3, 0xFFFF, sum = 0
6512 11:44:24.045221 4, 0xFFFF, sum = 0
6513 11:44:24.048368 5, 0xFFFF, sum = 0
6514 11:44:24.048449 6, 0xFFFF, sum = 0
6515 11:44:24.051979 7, 0xFFFF, sum = 0
6516 11:44:24.052059 8, 0xFFFF, sum = 0
6517 11:44:24.055291 9, 0xFFFF, sum = 0
6518 11:44:24.055375 10, 0xFFFF, sum = 0
6519 11:44:24.058561 11, 0xFFFF, sum = 0
6520 11:44:24.058642 12, 0xFFFF, sum = 0
6521 11:44:24.061821 13, 0x0, sum = 1
6522 11:44:24.061908 14, 0x0, sum = 2
6523 11:44:24.064919 15, 0x0, sum = 3
6524 11:44:24.065013 16, 0x0, sum = 4
6525 11:44:24.068718 best_step = 14
6526 11:44:24.068803
6527 11:44:24.068869 ==
6528 11:44:24.071896 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 11:44:24.075014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 11:44:24.075101 ==
6531 11:44:24.078302 RX Vref Scan: 0
6532 11:44:24.078387
6533 11:44:24.078454 RX Vref 0 -> 0, step: 1
6534 11:44:24.078517
6535 11:44:24.081540 RX Delay -327 -> 252, step: 8
6536 11:44:24.089304 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6537 11:44:24.093209 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6538 11:44:24.096342 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6539 11:44:24.102949 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6540 11:44:24.106345 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6541 11:44:24.109404 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6542 11:44:24.112865 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6543 11:44:24.119517 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6544 11:44:24.122639 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6545 11:44:24.126213 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6546 11:44:24.129543 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6547 11:44:24.136047 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6548 11:44:24.139410 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6549 11:44:24.142704 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6550 11:44:24.145712 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6551 11:44:24.152394 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6552 11:44:24.152857 ==
6553 11:44:24.155607 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:44:24.158714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:44:24.159192 ==
6556 11:44:24.159567 DQS Delay:
6557 11:44:24.162359 DQS0 = 28, DQS1 = 40
6558 11:44:24.162873 DQM Delay:
6559 11:44:24.165615 DQM0 = 9, DQM1 = 12
6560 11:44:24.166178 DQ Delay:
6561 11:44:24.168844 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6562 11:44:24.172135 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6563 11:44:24.175314 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6564 11:44:24.178947 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6565 11:44:24.179607
6566 11:44:24.180068
6567 11:44:24.185377 [DQSOSCAuto] RK1, (LSB)MR18= 0xb46a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6568 11:44:24.188934 CH0 RK1: MR19=C0C, MR18=B46A
6569 11:44:24.195577 CH0_RK1: MR19=0xC0C, MR18=0xB46A, DQSOSC=387, MR23=63, INC=394, DEC=262
6570 11:44:24.198721 [RxdqsGatingPostProcess] freq 400
6571 11:44:24.205235 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6572 11:44:24.208626 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 11:44:24.212195 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 11:44:24.215326 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 11:44:24.215988 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 11:44:24.218701 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 11:44:24.221983 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 11:44:24.225482 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 11:44:24.228598 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 11:44:24.231856 Pre-setting of DQS Precalculation
6581 11:44:24.238616 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6582 11:44:24.239092 ==
6583 11:44:24.241937 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 11:44:24.245286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 11:44:24.245780 ==
6586 11:44:24.251533 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6587 11:44:24.258051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6588 11:44:24.261916 [CA 0] Center 36 (8~64) winsize 57
6589 11:44:24.262564 [CA 1] Center 36 (8~64) winsize 57
6590 11:44:24.264834 [CA 2] Center 36 (8~64) winsize 57
6591 11:44:24.268126 [CA 3] Center 36 (8~64) winsize 57
6592 11:44:24.271513 [CA 4] Center 36 (8~64) winsize 57
6593 11:44:24.274524 [CA 5] Center 36 (8~64) winsize 57
6594 11:44:24.275157
6595 11:44:24.278271 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6596 11:44:24.278934
6597 11:44:24.284474 [CATrainingPosCal] consider 1 rank data
6598 11:44:24.285071 u2DelayCellTimex100 = 270/100 ps
6599 11:44:24.287744 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 11:44:24.294477 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 11:44:24.298118 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:44:24.301370 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 11:44:24.304391 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 11:44:24.307719 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:44:24.308190
6606 11:44:24.311122 CA PerBit enable=1, Macro0, CA PI delay=36
6607 11:44:24.311678
6608 11:44:24.314358 [CBTSetCACLKResult] CA Dly = 36
6609 11:44:24.317619 CS Dly: 1 (0~32)
6610 11:44:24.318186 ==
6611 11:44:24.320791 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 11:44:24.324141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 11:44:24.324927 ==
6614 11:44:24.330825 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 11:44:24.334084 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6616 11:44:24.337251 [CA 0] Center 36 (8~64) winsize 57
6617 11:44:24.340631 [CA 1] Center 36 (8~64) winsize 57
6618 11:44:24.344420 [CA 2] Center 36 (8~64) winsize 57
6619 11:44:24.347526 [CA 3] Center 36 (8~64) winsize 57
6620 11:44:24.350658 [CA 4] Center 36 (8~64) winsize 57
6621 11:44:24.353828 [CA 5] Center 36 (8~64) winsize 57
6622 11:44:24.354054
6623 11:44:24.356834 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6624 11:44:24.357035
6625 11:44:24.360577 [CATrainingPosCal] consider 2 rank data
6626 11:44:24.363672 u2DelayCellTimex100 = 270/100 ps
6627 11:44:24.366930 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 11:44:24.370277 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:44:24.373418 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:44:24.380143 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:44:24.383783 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:44:24.386910 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:44:24.387002
6634 11:44:24.390189 CA PerBit enable=1, Macro0, CA PI delay=36
6635 11:44:24.390288
6636 11:44:24.393297 [CBTSetCACLKResult] CA Dly = 36
6637 11:44:24.393389 CS Dly: 1 (0~32)
6638 11:44:24.393462
6639 11:44:24.396504 ----->DramcWriteLeveling(PI) begin...
6640 11:44:24.400208 ==
6641 11:44:24.403100 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 11:44:24.406655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:44:24.406748 ==
6644 11:44:24.409837 Write leveling (Byte 0): 40 => 8
6645 11:44:24.413237 Write leveling (Byte 1): 32 => 0
6646 11:44:24.416379 DramcWriteLeveling(PI) end<-----
6647 11:44:24.416479
6648 11:44:24.416561 ==
6649 11:44:24.419984 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 11:44:24.423037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 11:44:24.423136 ==
6652 11:44:24.426250 [Gating] SW mode calibration
6653 11:44:24.432721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 11:44:24.439645 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6655 11:44:24.442974 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 11:44:24.446329 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 11:44:24.453109 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 11:44:24.456322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 11:44:24.459583 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 11:44:24.466003 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 11:44:24.469200 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 11:44:24.472753 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 11:44:24.479042 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 11:44:24.479456 Total UI for P1: 0, mck2ui 16
6665 11:44:24.485783 best dqsien dly found for B0: ( 0, 14, 24)
6666 11:44:24.486218 Total UI for P1: 0, mck2ui 16
6667 11:44:24.492272 best dqsien dly found for B1: ( 0, 14, 24)
6668 11:44:24.495429 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6669 11:44:24.498785 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6670 11:44:24.499229
6671 11:44:24.502704 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 11:44:24.505520 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 11:44:24.508805 [Gating] SW calibration Done
6674 11:44:24.509289 ==
6675 11:44:24.512197 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 11:44:24.515214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 11:44:24.515642 ==
6678 11:44:24.518720 RX Vref Scan: 0
6679 11:44:24.519162
6680 11:44:24.519515 RX Vref 0 -> 0, step: 1
6681 11:44:24.521941
6682 11:44:24.522381 RX Delay -410 -> 252, step: 16
6683 11:44:24.528364 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6684 11:44:24.532025 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6685 11:44:24.534673 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6686 11:44:24.541292 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6687 11:44:24.544618 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6688 11:44:24.548246 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6689 11:44:24.551516 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6690 11:44:24.557802 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6691 11:44:24.561082 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6692 11:44:24.564349 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6693 11:44:24.567684 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6694 11:44:24.574654 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6695 11:44:24.577959 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6696 11:44:24.581064 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6697 11:44:24.584257 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6698 11:44:24.591063 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6699 11:44:24.591517 ==
6700 11:44:24.594118 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 11:44:24.597558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:44:24.597997 ==
6703 11:44:24.598336 DQS Delay:
6704 11:44:24.600713 DQS0 = 19, DQS1 = 43
6705 11:44:24.601179 DQM Delay:
6706 11:44:24.604026 DQM0 = 3, DQM1 = 20
6707 11:44:24.604560 DQ Delay:
6708 11:44:24.607394 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6709 11:44:24.610560 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6710 11:44:24.614029 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6711 11:44:24.617296 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6712 11:44:24.617727
6713 11:44:24.618082
6714 11:44:24.618392 ==
6715 11:44:24.620598 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 11:44:24.623757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 11:44:24.624208 ==
6718 11:44:24.624565
6719 11:44:24.627417
6720 11:44:24.627932 TX Vref Scan disable
6721 11:44:24.630373 == TX Byte 0 ==
6722 11:44:24.633696 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 11:44:24.637098 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 11:44:24.640557 == TX Byte 1 ==
6725 11:44:24.643630 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6726 11:44:24.647253 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6727 11:44:24.647690 ==
6728 11:44:24.650486 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 11:44:24.653555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 11:44:24.656861 ==
6731 11:44:24.657329
6732 11:44:24.657682
6733 11:44:24.658002 TX Vref Scan disable
6734 11:44:24.660080 == TX Byte 0 ==
6735 11:44:24.663233 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 11:44:24.666980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 11:44:24.670311 == TX Byte 1 ==
6738 11:44:24.673331 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6739 11:44:24.676548 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6740 11:44:24.676973
6741 11:44:24.679787 [DATLAT]
6742 11:44:24.680206 Freq=400, CH1 RK0
6743 11:44:24.680754
6744 11:44:24.683342 DATLAT Default: 0xf
6745 11:44:24.683762 0, 0xFFFF, sum = 0
6746 11:44:24.686572 1, 0xFFFF, sum = 0
6747 11:44:24.686997 2, 0xFFFF, sum = 0
6748 11:44:24.689605 3, 0xFFFF, sum = 0
6749 11:44:24.690035 4, 0xFFFF, sum = 0
6750 11:44:24.693287 5, 0xFFFF, sum = 0
6751 11:44:24.693715 6, 0xFFFF, sum = 0
6752 11:44:24.696519 7, 0xFFFF, sum = 0
6753 11:44:24.696947 8, 0xFFFF, sum = 0
6754 11:44:24.699762 9, 0xFFFF, sum = 0
6755 11:44:24.703097 10, 0xFFFF, sum = 0
6756 11:44:24.703524 11, 0xFFFF, sum = 0
6757 11:44:24.706224 12, 0xFFFF, sum = 0
6758 11:44:24.706648 13, 0x0, sum = 1
6759 11:44:24.709447 14, 0x0, sum = 2
6760 11:44:24.709909 15, 0x0, sum = 3
6761 11:44:24.713081 16, 0x0, sum = 4
6762 11:44:24.713599 best_step = 14
6763 11:44:24.713948
6764 11:44:24.714261 ==
6765 11:44:24.716060 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 11:44:24.719589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 11:44:24.720018 ==
6768 11:44:24.722840 RX Vref Scan: 1
6769 11:44:24.723267
6770 11:44:24.725862 RX Vref 0 -> 0, step: 1
6771 11:44:24.726292
6772 11:44:24.726628 RX Delay -327 -> 252, step: 8
6773 11:44:24.726945
6774 11:44:24.729595 Set Vref, RX VrefLevel [Byte0]: 52
6775 11:44:24.732513 [Byte1]: 48
6776 11:44:24.738274
6777 11:44:24.738695 Final RX Vref Byte 0 = 52 to rank0
6778 11:44:24.741495 Final RX Vref Byte 1 = 48 to rank0
6779 11:44:24.744838 Final RX Vref Byte 0 = 52 to rank1
6780 11:44:24.747886 Final RX Vref Byte 1 = 48 to rank1==
6781 11:44:24.751321 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 11:44:24.758163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 11:44:24.758589 ==
6784 11:44:24.758944 DQS Delay:
6785 11:44:24.761307 DQS0 = 32, DQS1 = 40
6786 11:44:24.761730 DQM Delay:
6787 11:44:24.762087 DQM0 = 12, DQM1 = 13
6788 11:44:24.764714 DQ Delay:
6789 11:44:24.767956 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6790 11:44:24.768380 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6791 11:44:24.771131 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6792 11:44:24.774292 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6793 11:44:24.774717
6794 11:44:24.777469
6795 11:44:24.784361 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6796 11:44:24.787574 CH1 RK0: MR19=C0C, MR18=8FC9
6797 11:44:24.794256 CH1_RK0: MR19=0xC0C, MR18=0x8FC9, DQSOSC=384, MR23=63, INC=400, DEC=267
6798 11:44:24.794686 ==
6799 11:44:24.797751 Dram Type= 6, Freq= 0, CH_1, rank 1
6800 11:44:24.801047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 11:44:24.801516 ==
6802 11:44:24.804315 [Gating] SW mode calibration
6803 11:44:24.810837 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6804 11:44:24.817425 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6805 11:44:24.820697 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 11:44:24.824057 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 11:44:24.830610 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 11:44:24.833778 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 11:44:24.837390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 11:44:24.844081 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 11:44:24.847535 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 11:44:24.850648 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 11:44:24.856994 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 11:44:24.857502 Total UI for P1: 0, mck2ui 16
6815 11:44:24.863793 best dqsien dly found for B0: ( 0, 14, 24)
6816 11:44:24.864329 Total UI for P1: 0, mck2ui 16
6817 11:44:24.866884 best dqsien dly found for B1: ( 0, 14, 24)
6818 11:44:24.873813 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6819 11:44:24.877105 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6820 11:44:24.877667
6821 11:44:24.880279 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 11:44:24.883521 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 11:44:24.886714 [Gating] SW calibration Done
6824 11:44:24.887258 ==
6825 11:44:24.889917 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 11:44:24.893522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 11:44:24.894071 ==
6828 11:44:24.896677 RX Vref Scan: 0
6829 11:44:24.897286
6830 11:44:24.897778 RX Vref 0 -> 0, step: 1
6831 11:44:24.898258
6832 11:44:24.899826 RX Delay -410 -> 252, step: 16
6833 11:44:24.906647 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6834 11:44:24.910027 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6835 11:44:24.913305 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6836 11:44:24.916420 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6837 11:44:24.923393 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6838 11:44:24.926401 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6839 11:44:24.929933 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6840 11:44:24.932943 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6841 11:44:24.939819 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6842 11:44:24.942896 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6843 11:44:24.946071 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6844 11:44:24.949619 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6845 11:44:24.956274 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6846 11:44:24.959532 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6847 11:44:24.962916 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6848 11:44:24.969376 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6849 11:44:24.969805 ==
6850 11:44:24.972974 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 11:44:24.976193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 11:44:24.976624 ==
6853 11:44:24.976961 DQS Delay:
6854 11:44:24.979294 DQS0 = 35, DQS1 = 35
6855 11:44:24.979717 DQM Delay:
6856 11:44:24.982391 DQM0 = 16, DQM1 = 11
6857 11:44:24.982873 DQ Delay:
6858 11:44:24.985976 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6859 11:44:24.989242 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6860 11:44:24.992598 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6861 11:44:24.995884 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6862 11:44:24.996256
6863 11:44:24.996590
6864 11:44:24.996886 ==
6865 11:44:24.999093 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 11:44:25.001982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 11:44:25.002066 ==
6868 11:44:25.002130
6869 11:44:25.002189
6870 11:44:25.005415 TX Vref Scan disable
6871 11:44:25.005497 == TX Byte 0 ==
6872 11:44:25.011941 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6873 11:44:25.015650 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6874 11:44:25.015732 == TX Byte 1 ==
6875 11:44:25.022364 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6876 11:44:25.025378 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6877 11:44:25.025484 ==
6878 11:44:25.028659 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 11:44:25.031786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 11:44:25.031869 ==
6881 11:44:25.031934
6882 11:44:25.031993
6883 11:44:25.035551 TX Vref Scan disable
6884 11:44:25.038452 == TX Byte 0 ==
6885 11:44:25.041730 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6886 11:44:25.045388 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6887 11:44:25.045496 == TX Byte 1 ==
6888 11:44:25.051962 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6889 11:44:25.055151 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6890 11:44:25.055234
6891 11:44:25.055298 [DATLAT]
6892 11:44:25.058354 Freq=400, CH1 RK1
6893 11:44:25.058436
6894 11:44:25.058499 DATLAT Default: 0xe
6895 11:44:25.061452 0, 0xFFFF, sum = 0
6896 11:44:25.061538 1, 0xFFFF, sum = 0
6897 11:44:25.065106 2, 0xFFFF, sum = 0
6898 11:44:25.067954 3, 0xFFFF, sum = 0
6899 11:44:25.068037 4, 0xFFFF, sum = 0
6900 11:44:25.071271 5, 0xFFFF, sum = 0
6901 11:44:25.071354 6, 0xFFFF, sum = 0
6902 11:44:25.074539 7, 0xFFFF, sum = 0
6903 11:44:25.074622 8, 0xFFFF, sum = 0
6904 11:44:25.078134 9, 0xFFFF, sum = 0
6905 11:44:25.078216 10, 0xFFFF, sum = 0
6906 11:44:25.081407 11, 0xFFFF, sum = 0
6907 11:44:25.081489 12, 0xFFFF, sum = 0
6908 11:44:25.084696 13, 0x0, sum = 1
6909 11:44:25.084780 14, 0x0, sum = 2
6910 11:44:25.087951 15, 0x0, sum = 3
6911 11:44:25.088038 16, 0x0, sum = 4
6912 11:44:25.091150 best_step = 14
6913 11:44:25.091231
6914 11:44:25.091294 ==
6915 11:44:25.094325 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 11:44:25.097890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 11:44:25.097972 ==
6918 11:44:25.100913 RX Vref Scan: 0
6919 11:44:25.101051
6920 11:44:25.101116 RX Vref 0 -> 0, step: 1
6921 11:44:25.101175
6922 11:44:25.104187 RX Delay -311 -> 252, step: 8
6923 11:44:25.111800 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6924 11:44:25.115357 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6925 11:44:25.118240 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6926 11:44:25.125058 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6927 11:44:25.128570 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6928 11:44:25.131981 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6929 11:44:25.134953 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6930 11:44:25.141535 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6931 11:44:25.144739 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6932 11:44:25.148184 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6933 11:44:25.151649 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6934 11:44:25.158057 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6935 11:44:25.161476 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6936 11:44:25.164486 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6937 11:44:25.167773 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6938 11:44:25.174575 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6939 11:44:25.174657 ==
6940 11:44:25.177844 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:44:25.180876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:44:25.181007 ==
6943 11:44:25.181118 DQS Delay:
6944 11:44:25.184568 DQS0 = 32, DQS1 = 36
6945 11:44:25.184650 DQM Delay:
6946 11:44:25.187652 DQM0 = 13, DQM1 = 11
6947 11:44:25.187734 DQ Delay:
6948 11:44:25.190847 DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =8
6949 11:44:25.194088 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6950 11:44:25.197306 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6951 11:44:25.201052 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
6952 11:44:25.201141
6953 11:44:25.201205
6954 11:44:25.210628 [DQSOSCAuto] RK1, (LSB)MR18= 0xa851, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6955 11:44:25.210710 CH1 RK1: MR19=C0C, MR18=A851
6956 11:44:25.217489 CH1_RK1: MR19=0xC0C, MR18=0xA851, DQSOSC=388, MR23=63, INC=392, DEC=261
6957 11:44:25.220661 [RxdqsGatingPostProcess] freq 400
6958 11:44:25.227232 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6959 11:44:25.230699 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 11:44:25.234172 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 11:44:25.237331 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 11:44:25.240374 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 11:44:25.243792 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 11:44:25.243904 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 11:44:25.246925 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 11:44:25.250272 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 11:44:25.253427 Pre-setting of DQS Precalculation
6968 11:44:25.260321 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6969 11:44:25.266929 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6970 11:44:25.273341 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6971 11:44:25.273419
6972 11:44:25.273483
6973 11:44:25.276556 [Calibration Summary] 800 Mbps
6974 11:44:25.280027 CH 0, Rank 0
6975 11:44:25.280126 SW Impedance : PASS
6976 11:44:25.283281 DUTY Scan : NO K
6977 11:44:25.286474 ZQ Calibration : PASS
6978 11:44:25.286564 Jitter Meter : NO K
6979 11:44:25.289766 CBT Training : PASS
6980 11:44:25.289842 Write leveling : PASS
6981 11:44:25.293384 RX DQS gating : PASS
6982 11:44:25.296781 RX DQ/DQS(RDDQC) : PASS
6983 11:44:25.296863 TX DQ/DQS : PASS
6984 11:44:25.299924 RX DATLAT : PASS
6985 11:44:25.303210 RX DQ/DQS(Engine): PASS
6986 11:44:25.303319 TX OE : NO K
6987 11:44:25.306654 All Pass.
6988 11:44:25.306757
6989 11:44:25.306854 CH 0, Rank 1
6990 11:44:25.309474 SW Impedance : PASS
6991 11:44:25.309584 DUTY Scan : NO K
6992 11:44:25.312770 ZQ Calibration : PASS
6993 11:44:25.316281 Jitter Meter : NO K
6994 11:44:25.316356 CBT Training : PASS
6995 11:44:25.319559 Write leveling : NO K
6996 11:44:25.323135 RX DQS gating : PASS
6997 11:44:25.323238 RX DQ/DQS(RDDQC) : PASS
6998 11:44:25.326038 TX DQ/DQS : PASS
6999 11:44:25.329568 RX DATLAT : PASS
7000 11:44:25.329649 RX DQ/DQS(Engine): PASS
7001 11:44:25.332835 TX OE : NO K
7002 11:44:25.332940 All Pass.
7003 11:44:25.333069
7004 11:44:25.336110 CH 1, Rank 0
7005 11:44:25.336212 SW Impedance : PASS
7006 11:44:25.339335 DUTY Scan : NO K
7007 11:44:25.342589 ZQ Calibration : PASS
7008 11:44:25.342664 Jitter Meter : NO K
7009 11:44:25.346017 CBT Training : PASS
7010 11:44:25.349313 Write leveling : PASS
7011 11:44:25.349417 RX DQS gating : PASS
7012 11:44:25.352554 RX DQ/DQS(RDDQC) : PASS
7013 11:44:25.355817 TX DQ/DQS : PASS
7014 11:44:25.355928 RX DATLAT : PASS
7015 11:44:25.359246 RX DQ/DQS(Engine): PASS
7016 11:44:25.359350 TX OE : NO K
7017 11:44:25.362445 All Pass.
7018 11:44:25.362549
7019 11:44:25.362644 CH 1, Rank 1
7020 11:44:25.365538 SW Impedance : PASS
7021 11:44:25.365646 DUTY Scan : NO K
7022 11:44:25.369093 ZQ Calibration : PASS
7023 11:44:25.372313 Jitter Meter : NO K
7024 11:44:25.372413 CBT Training : PASS
7025 11:44:25.375646 Write leveling : NO K
7026 11:44:25.378864 RX DQS gating : PASS
7027 11:44:25.378946 RX DQ/DQS(RDDQC) : PASS
7028 11:44:25.382458 TX DQ/DQS : PASS
7029 11:44:25.385752 RX DATLAT : PASS
7030 11:44:25.385868 RX DQ/DQS(Engine): PASS
7031 11:44:25.388874 TX OE : NO K
7032 11:44:25.388974 All Pass.
7033 11:44:25.389077
7034 11:44:25.392114 DramC Write-DBI off
7035 11:44:25.395440 PER_BANK_REFRESH: Hybrid Mode
7036 11:44:25.395522 TX_TRACKING: ON
7037 11:44:25.405276 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7038 11:44:25.408397 [FAST_K] Save calibration result to emmc
7039 11:44:25.411762 dramc_set_vcore_voltage set vcore to 725000
7040 11:44:25.415634 Read voltage for 1600, 0
7041 11:44:25.415716 Vio18 = 0
7042 11:44:25.415780 Vcore = 725000
7043 11:44:25.418834 Vdram = 0
7044 11:44:25.418943 Vddq = 0
7045 11:44:25.419040 Vmddr = 0
7046 11:44:25.425584 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7047 11:44:25.428797 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7048 11:44:25.432038 MEM_TYPE=3, freq_sel=13
7049 11:44:25.435257 sv_algorithm_assistance_LP4_3733
7050 11:44:25.438474 ============ PULL DRAM RESETB DOWN ============
7051 11:44:25.444926 ========== PULL DRAM RESETB DOWN end =========
7052 11:44:25.448087 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7053 11:44:25.451602 ===================================
7054 11:44:25.455063 LPDDR4 DRAM CONFIGURATION
7055 11:44:25.458096 ===================================
7056 11:44:25.458183 EX_ROW_EN[0] = 0x0
7057 11:44:25.461444 EX_ROW_EN[1] = 0x0
7058 11:44:25.461532 LP4Y_EN = 0x0
7059 11:44:25.464809 WORK_FSP = 0x1
7060 11:44:25.464891 WL = 0x5
7061 11:44:25.468204 RL = 0x5
7062 11:44:25.468286 BL = 0x2
7063 11:44:25.471286 RPST = 0x0
7064 11:44:25.471393 RD_PRE = 0x0
7065 11:44:25.474874 WR_PRE = 0x1
7066 11:44:25.478053 WR_PST = 0x1
7067 11:44:25.478134 DBI_WR = 0x0
7068 11:44:25.481253 DBI_RD = 0x0
7069 11:44:25.481393 OTF = 0x1
7070 11:44:25.484899 ===================================
7071 11:44:25.488254 ===================================
7072 11:44:25.488336 ANA top config
7073 11:44:25.491316 ===================================
7074 11:44:25.494846 DLL_ASYNC_EN = 0
7075 11:44:25.498086 ALL_SLAVE_EN = 0
7076 11:44:25.501398 NEW_RANK_MODE = 1
7077 11:44:25.504365 DLL_IDLE_MODE = 1
7078 11:44:25.504457 LP45_APHY_COMB_EN = 1
7079 11:44:25.507605 TX_ODT_DIS = 0
7080 11:44:25.510991 NEW_8X_MODE = 1
7081 11:44:25.514265 ===================================
7082 11:44:25.517577 ===================================
7083 11:44:25.520988 data_rate = 3200
7084 11:44:25.524139 CKR = 1
7085 11:44:25.527710 DQ_P2S_RATIO = 8
7086 11:44:25.530856 ===================================
7087 11:44:25.530943 CA_P2S_RATIO = 8
7088 11:44:25.534089 DQ_CA_OPEN = 0
7089 11:44:25.537294 DQ_SEMI_OPEN = 0
7090 11:44:25.540594 CA_SEMI_OPEN = 0
7091 11:44:25.544039 CA_FULL_RATE = 0
7092 11:44:25.547490 DQ_CKDIV4_EN = 0
7093 11:44:25.547604 CA_CKDIV4_EN = 0
7094 11:44:25.550626 CA_PREDIV_EN = 0
7095 11:44:25.553863 PH8_DLY = 12
7096 11:44:25.557083 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7097 11:44:25.560506 DQ_AAMCK_DIV = 4
7098 11:44:25.564048 CA_AAMCK_DIV = 4
7099 11:44:25.564130 CA_ADMCK_DIV = 4
7100 11:44:25.567381 DQ_TRACK_CA_EN = 0
7101 11:44:25.570476 CA_PICK = 1600
7102 11:44:25.573715 CA_MCKIO = 1600
7103 11:44:25.577051 MCKIO_SEMI = 0
7104 11:44:25.580244 PLL_FREQ = 3068
7105 11:44:25.583562 DQ_UI_PI_RATIO = 32
7106 11:44:25.586724 CA_UI_PI_RATIO = 0
7107 11:44:25.590148 ===================================
7108 11:44:25.593380 ===================================
7109 11:44:25.593464 memory_type:LPDDR4
7110 11:44:25.596638 GP_NUM : 10
7111 11:44:25.599899 SRAM_EN : 1
7112 11:44:25.599982 MD32_EN : 0
7113 11:44:25.603331 ===================================
7114 11:44:25.606409 [ANA_INIT] >>>>>>>>>>>>>>
7115 11:44:25.609617 <<<<<< [CONFIGURE PHASE]: ANA_TX
7116 11:44:25.613044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7117 11:44:25.616622 ===================================
7118 11:44:25.619854 data_rate = 3200,PCW = 0X7600
7119 11:44:25.623175 ===================================
7120 11:44:25.626442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7121 11:44:25.629996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 11:44:25.636235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 11:44:25.639476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7124 11:44:25.642762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7125 11:44:25.646440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7126 11:44:25.649218 [ANA_INIT] flow start
7127 11:44:25.652903 [ANA_INIT] PLL >>>>>>>>
7128 11:44:25.653014 [ANA_INIT] PLL <<<<<<<<
7129 11:44:25.655983 [ANA_INIT] MIDPI >>>>>>>>
7130 11:44:25.659538 [ANA_INIT] MIDPI <<<<<<<<
7131 11:44:25.662654 [ANA_INIT] DLL >>>>>>>>
7132 11:44:25.662741 [ANA_INIT] DLL <<<<<<<<
7133 11:44:25.666065 [ANA_INIT] flow end
7134 11:44:25.669255 ============ LP4 DIFF to SE enter ============
7135 11:44:25.672452 ============ LP4 DIFF to SE exit ============
7136 11:44:25.675661 [ANA_INIT] <<<<<<<<<<<<<
7137 11:44:25.679133 [Flow] Enable top DCM control >>>>>
7138 11:44:25.682562 [Flow] Enable top DCM control <<<<<
7139 11:44:25.685705 Enable DLL master slave shuffle
7140 11:44:25.692036 ==============================================================
7141 11:44:25.692121 Gating Mode config
7142 11:44:25.698947 ==============================================================
7143 11:44:25.699031 Config description:
7144 11:44:25.708824 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7145 11:44:25.715311 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7146 11:44:25.722310 SELPH_MODE 0: By rank 1: By Phase
7147 11:44:25.728604 ==============================================================
7148 11:44:25.728722 GAT_TRACK_EN = 1
7149 11:44:25.731799 RX_GATING_MODE = 2
7150 11:44:25.734910 RX_GATING_TRACK_MODE = 2
7151 11:44:25.738611 SELPH_MODE = 1
7152 11:44:25.742087 PICG_EARLY_EN = 1
7153 11:44:25.745253 VALID_LAT_VALUE = 1
7154 11:44:25.751838 ==============================================================
7155 11:44:25.755188 Enter into Gating configuration >>>>
7156 11:44:25.758396 Exit from Gating configuration <<<<
7157 11:44:25.761429 Enter into DVFS_PRE_config >>>>>
7158 11:44:25.771911 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7159 11:44:25.775032 Exit from DVFS_PRE_config <<<<<
7160 11:44:25.778331 Enter into PICG configuration >>>>
7161 11:44:25.781711 Exit from PICG configuration <<<<
7162 11:44:25.784863 [RX_INPUT] configuration >>>>>
7163 11:44:25.788343 [RX_INPUT] configuration <<<<<
7164 11:44:25.791347 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7165 11:44:25.798013 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7166 11:44:25.804389 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 11:44:25.807574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 11:44:25.814388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 11:44:25.820794 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 11:44:25.824187 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7171 11:44:25.830705 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7172 11:44:25.834451 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7173 11:44:25.837779 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7174 11:44:25.840961 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7175 11:44:25.847693 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7176 11:44:25.851027 ===================================
7177 11:44:25.851661 LPDDR4 DRAM CONFIGURATION
7178 11:44:25.854343 ===================================
7179 11:44:25.858024 EX_ROW_EN[0] = 0x0
7180 11:44:25.861131 EX_ROW_EN[1] = 0x0
7181 11:44:25.861603 LP4Y_EN = 0x0
7182 11:44:25.864280 WORK_FSP = 0x1
7183 11:44:25.864837 WL = 0x5
7184 11:44:25.867853 RL = 0x5
7185 11:44:25.868336 BL = 0x2
7186 11:44:25.870936 RPST = 0x0
7187 11:44:25.871419 RD_PRE = 0x0
7188 11:44:25.874348 WR_PRE = 0x1
7189 11:44:25.874817 WR_PST = 0x1
7190 11:44:25.877649 DBI_WR = 0x0
7191 11:44:25.878128 DBI_RD = 0x0
7192 11:44:25.880753 OTF = 0x1
7193 11:44:25.884398 ===================================
7194 11:44:25.887456 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7195 11:44:25.890640 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7196 11:44:25.897375 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 11:44:25.900450 ===================================
7198 11:44:25.900885 LPDDR4 DRAM CONFIGURATION
7199 11:44:25.903876 ===================================
7200 11:44:25.907135 EX_ROW_EN[0] = 0x10
7201 11:44:25.910476 EX_ROW_EN[1] = 0x0
7202 11:44:25.910980 LP4Y_EN = 0x0
7203 11:44:25.914108 WORK_FSP = 0x1
7204 11:44:25.914706 WL = 0x5
7205 11:44:25.917371 RL = 0x5
7206 11:44:25.917850 BL = 0x2
7207 11:44:25.920385 RPST = 0x0
7208 11:44:25.920851 RD_PRE = 0x0
7209 11:44:25.923736 WR_PRE = 0x1
7210 11:44:25.924201 WR_PST = 0x1
7211 11:44:25.927026 DBI_WR = 0x0
7212 11:44:25.927489 DBI_RD = 0x0
7213 11:44:25.930235 OTF = 0x1
7214 11:44:25.933605 ===================================
7215 11:44:25.939894 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7216 11:44:25.939977 ==
7217 11:44:25.943432 Dram Type= 6, Freq= 0, CH_0, rank 0
7218 11:44:25.946540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7219 11:44:25.946650 ==
7220 11:44:25.949798 [Duty_Offset_Calibration]
7221 11:44:25.949881 B0:2 B1:0 CA:1
7222 11:44:25.949946
7223 11:44:25.953355 [DutyScan_Calibration_Flow] k_type=0
7224 11:44:25.963282
7225 11:44:25.963365 ==CLK 0==
7226 11:44:25.966455 Final CLK duty delay cell = -4
7227 11:44:25.969636 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7228 11:44:25.973113 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7229 11:44:25.976057 [-4] AVG Duty = 4922%(X100)
7230 11:44:25.976141
7231 11:44:25.979547 CH0 CLK Duty spec in!! Max-Min= 218%
7232 11:44:25.982650 [DutyScan_Calibration_Flow] ====Done====
7233 11:44:25.982733
7234 11:44:25.986279 [DutyScan_Calibration_Flow] k_type=1
7235 11:44:26.002563
7236 11:44:26.002694 ==DQS 0 ==
7237 11:44:26.005895 Final DQS duty delay cell = 0
7238 11:44:26.009345 [0] MAX Duty = 5249%(X100), DQS PI = 32
7239 11:44:26.012679 [0] MIN Duty = 4969%(X100), DQS PI = 2
7240 11:44:26.015751 [0] AVG Duty = 5109%(X100)
7241 11:44:26.015850
7242 11:44:26.015941 ==DQS 1 ==
7243 11:44:26.019076 Final DQS duty delay cell = -4
7244 11:44:26.022677 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7245 11:44:26.025875 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7246 11:44:26.029106 [-4] AVG Duty = 4984%(X100)
7247 11:44:26.029186
7248 11:44:26.032374 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7249 11:44:26.032446
7250 11:44:26.035664 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7251 11:44:26.038948 [DutyScan_Calibration_Flow] ====Done====
7252 11:44:26.039047
7253 11:44:26.042039 [DutyScan_Calibration_Flow] k_type=3
7254 11:44:26.060266
7255 11:44:26.060372 ==DQM 0 ==
7256 11:44:26.063492 Final DQM duty delay cell = 0
7257 11:44:26.067092 [0] MAX Duty = 5093%(X100), DQS PI = 28
7258 11:44:26.070356 [0] MIN Duty = 4813%(X100), DQS PI = 50
7259 11:44:26.070464 [0] AVG Duty = 4953%(X100)
7260 11:44:26.073528
7261 11:44:26.073623 ==DQM 1 ==
7262 11:44:26.076828 Final DQM duty delay cell = 0
7263 11:44:26.080258 [0] MAX Duty = 5249%(X100), DQS PI = 44
7264 11:44:26.083320 [0] MIN Duty = 5031%(X100), DQS PI = 6
7265 11:44:26.086722 [0] AVG Duty = 5140%(X100)
7266 11:44:26.086883
7267 11:44:26.090110 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7268 11:44:26.090249
7269 11:44:26.093134 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7270 11:44:26.096683 [DutyScan_Calibration_Flow] ====Done====
7271 11:44:26.096947
7272 11:44:26.099765 [DutyScan_Calibration_Flow] k_type=2
7273 11:44:26.117839
7274 11:44:26.118350 ==DQ 0 ==
7275 11:44:26.120910 Final DQ duty delay cell = 0
7276 11:44:26.124249 [0] MAX Duty = 5124%(X100), DQS PI = 34
7277 11:44:26.127592 [0] MIN Duty = 5000%(X100), DQS PI = 0
7278 11:44:26.128132 [0] AVG Duty = 5062%(X100)
7279 11:44:26.130828
7280 11:44:26.131369 ==DQ 1 ==
7281 11:44:26.133980 Final DQ duty delay cell = 0
7282 11:44:26.137749 [0] MAX Duty = 4969%(X100), DQS PI = 28
7283 11:44:26.140679 [0] MIN Duty = 4875%(X100), DQS PI = 10
7284 11:44:26.141306 [0] AVG Duty = 4922%(X100)
7285 11:44:26.144059
7286 11:44:26.147285 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7287 11:44:26.147765
7288 11:44:26.150580 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7289 11:44:26.154090 [DutyScan_Calibration_Flow] ====Done====
7290 11:44:26.154559 ==
7291 11:44:26.157103 Dram Type= 6, Freq= 0, CH_1, rank 0
7292 11:44:26.160763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7293 11:44:26.161273 ==
7294 11:44:26.163630 [Duty_Offset_Calibration]
7295 11:44:26.164084 B0:0 B1:-1 CA:2
7296 11:44:26.164444
7297 11:44:26.166950 [DutyScan_Calibration_Flow] k_type=0
7298 11:44:26.177871
7299 11:44:26.178280 ==CLK 0==
7300 11:44:26.180814 Final CLK duty delay cell = 0
7301 11:44:26.184295 [0] MAX Duty = 5156%(X100), DQS PI = 40
7302 11:44:26.187554 [0] MIN Duty = 4906%(X100), DQS PI = 14
7303 11:44:26.188023 [0] AVG Duty = 5031%(X100)
7304 11:44:26.190757
7305 11:44:26.194185 CH1 CLK Duty spec in!! Max-Min= 250%
7306 11:44:26.197325 [DutyScan_Calibration_Flow] ====Done====
7307 11:44:26.197651
7308 11:44:26.200648 [DutyScan_Calibration_Flow] k_type=1
7309 11:44:26.217266
7310 11:44:26.217588 ==DQS 0 ==
7311 11:44:26.220572 Final DQS duty delay cell = 0
7312 11:44:26.224167 [0] MAX Duty = 5062%(X100), DQS PI = 8
7313 11:44:26.227198 [0] MIN Duty = 5000%(X100), DQS PI = 0
7314 11:44:26.230288 [0] AVG Duty = 5031%(X100)
7315 11:44:26.230677
7316 11:44:26.231061 ==DQS 1 ==
7317 11:44:26.233929 Final DQS duty delay cell = 0
7318 11:44:26.237117 [0] MAX Duty = 5218%(X100), DQS PI = 30
7319 11:44:26.240280 [0] MIN Duty = 4813%(X100), DQS PI = 4
7320 11:44:26.243649 [0] AVG Duty = 5015%(X100)
7321 11:44:26.244063
7322 11:44:26.247095 CH1 DQS 0 Duty spec in!! Max-Min= 62%
7323 11:44:26.247743
7324 11:44:26.250678 CH1 DQS 1 Duty spec in!! Max-Min= 405%
7325 11:44:26.253905 [DutyScan_Calibration_Flow] ====Done====
7326 11:44:26.254510
7327 11:44:26.257107 [DutyScan_Calibration_Flow] k_type=3
7328 11:44:26.274269
7329 11:44:26.274844 ==DQM 0 ==
7330 11:44:26.277519 Final DQM duty delay cell = 4
7331 11:44:26.280818 [4] MAX Duty = 5156%(X100), DQS PI = 24
7332 11:44:26.283830 [4] MIN Duty = 4969%(X100), DQS PI = 0
7333 11:44:26.284308 [4] AVG Duty = 5062%(X100)
7334 11:44:26.287477
7335 11:44:26.287888 ==DQM 1 ==
7336 11:44:26.290728 Final DQM duty delay cell = -4
7337 11:44:26.294031 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7338 11:44:26.297075 [-4] MIN Duty = 4719%(X100), DQS PI = 0
7339 11:44:26.300252 [-4] AVG Duty = 4844%(X100)
7340 11:44:26.300828
7341 11:44:26.303755 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7342 11:44:26.304177
7343 11:44:26.307125 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7344 11:44:26.310168 [DutyScan_Calibration_Flow] ====Done====
7345 11:44:26.310582
7346 11:44:26.313595 [DutyScan_Calibration_Flow] k_type=2
7347 11:44:26.331304
7348 11:44:26.331716 ==DQ 0 ==
7349 11:44:26.334670 Final DQ duty delay cell = 0
7350 11:44:26.337734 [0] MAX Duty = 5093%(X100), DQS PI = 22
7351 11:44:26.340966 [0] MIN Duty = 4938%(X100), DQS PI = 0
7352 11:44:26.341431 [0] AVG Duty = 5015%(X100)
7353 11:44:26.344248
7354 11:44:26.344737 ==DQ 1 ==
7355 11:44:26.347442 Final DQ duty delay cell = 0
7356 11:44:26.351027 [0] MAX Duty = 5094%(X100), DQS PI = 34
7357 11:44:26.354322 [0] MIN Duty = 4813%(X100), DQS PI = 0
7358 11:44:26.354850 [0] AVG Duty = 4953%(X100)
7359 11:44:26.355190
7360 11:44:26.360804 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7361 11:44:26.361268
7362 11:44:26.363996 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7363 11:44:26.367322 [DutyScan_Calibration_Flow] ====Done====
7364 11:44:26.370682 nWR fixed to 30
7365 11:44:26.371143 [ModeRegInit_LP4] CH0 RK0
7366 11:44:26.373770 [ModeRegInit_LP4] CH0 RK1
7367 11:44:26.377149 [ModeRegInit_LP4] CH1 RK0
7368 11:44:26.380399 [ModeRegInit_LP4] CH1 RK1
7369 11:44:26.380842 match AC timing 5
7370 11:44:26.387289 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7371 11:44:26.390488 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7372 11:44:26.393785 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7373 11:44:26.400243 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7374 11:44:26.403689 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7375 11:44:26.404128 [MiockJmeterHQA]
7376 11:44:26.404456
7377 11:44:26.406852 [DramcMiockJmeter] u1RxGatingPI = 0
7378 11:44:26.410137 0 : 4252, 4027
7379 11:44:26.410779 4 : 4252, 4027
7380 11:44:26.413591 8 : 4254, 4029
7381 11:44:26.414008 12 : 4252, 4027
7382 11:44:26.414358 16 : 4252, 4027
7383 11:44:26.416901 20 : 4363, 4137
7384 11:44:26.417359 24 : 4253, 4027
7385 11:44:26.420475 28 : 4253, 4026
7386 11:44:26.420890 32 : 4252, 4027
7387 11:44:26.423472 36 : 4253, 4027
7388 11:44:26.423886 40 : 4252, 4027
7389 11:44:26.426909 44 : 4252, 4027
7390 11:44:26.427328 48 : 4365, 4139
7391 11:44:26.427660 52 : 4253, 4026
7392 11:44:26.430342 56 : 4255, 4029
7393 11:44:26.430768 60 : 4250, 4027
7394 11:44:26.433814 64 : 4363, 4138
7395 11:44:26.434235 68 : 4252, 4030
7396 11:44:26.437002 72 : 4252, 4026
7397 11:44:26.437426 76 : 4252, 4029
7398 11:44:26.440445 80 : 4250, 4026
7399 11:44:26.440867 84 : 4252, 4029
7400 11:44:26.441411 88 : 4249, 3757
7401 11:44:26.443638 92 : 4250, 2
7402 11:44:26.444063 96 : 4250, 0
7403 11:44:26.446898 100 : 4250, 0
7404 11:44:26.447319 104 : 4253, 0
7405 11:44:26.447812 108 : 4250, 0
7406 11:44:26.450270 112 : 4250, 0
7407 11:44:26.450716 116 : 4250, 0
7408 11:44:26.451246 120 : 4363, 0
7409 11:44:26.453378 124 : 4250, 0
7410 11:44:26.453802 128 : 4360, 0
7411 11:44:26.456648 132 : 4254, 0
7412 11:44:26.457106 136 : 4250, 0
7413 11:44:26.457475 140 : 4250, 0
7414 11:44:26.460189 144 : 4254, 0
7415 11:44:26.460767 148 : 4360, 0
7416 11:44:26.463568 152 : 4250, 0
7417 11:44:26.463989 156 : 4250, 0
7418 11:44:26.464326 160 : 4250, 0
7419 11:44:26.466968 164 : 4363, 0
7420 11:44:26.467504 168 : 4250, 0
7421 11:44:26.470072 172 : 4361, 0
7422 11:44:26.470493 176 : 4361, 0
7423 11:44:26.470831 180 : 4248, 0
7424 11:44:26.473280 184 : 4250, 0
7425 11:44:26.473703 188 : 4250, 0
7426 11:44:26.476371 192 : 4250, 0
7427 11:44:26.476796 196 : 4360, 0
7428 11:44:26.477177 200 : 4250, 1
7429 11:44:26.479749 204 : 4255, 2040
7430 11:44:26.480182 208 : 4250, 4027
7431 11:44:26.482870 212 : 4363, 4138
7432 11:44:26.483303 216 : 4250, 4026
7433 11:44:26.486134 220 : 4249, 4027
7434 11:44:26.486603 224 : 4250, 4026
7435 11:44:26.489710 228 : 4250, 4027
7436 11:44:26.490175 232 : 4360, 4138
7437 11:44:26.492670 236 : 4252, 4030
7438 11:44:26.493241 240 : 4360, 4137
7439 11:44:26.495928 244 : 4250, 4027
7440 11:44:26.496451 248 : 4250, 4027
7441 11:44:26.497030 252 : 4250, 4027
7442 11:44:26.499670 256 : 4250, 4027
7443 11:44:26.500258 260 : 4255, 4029
7444 11:44:26.502901 264 : 4361, 4138
7445 11:44:26.503359 268 : 4250, 4027
7446 11:44:26.506201 272 : 4250, 4027
7447 11:44:26.506760 276 : 4250, 4027
7448 11:44:26.509276 280 : 4250, 4026
7449 11:44:26.509687 284 : 4363, 4138
7450 11:44:26.513006 288 : 4249, 4027
7451 11:44:26.513428 292 : 4363, 4137
7452 11:44:26.516069 296 : 4250, 4026
7453 11:44:26.516557 300 : 4250, 4027
7454 11:44:26.519441 304 : 4250, 4027
7455 11:44:26.519991 308 : 4250, 4027
7456 11:44:26.520513 312 : 4250, 3989
7457 11:44:26.522733 316 : 4361, 2322
7458 11:44:26.523140 320 : 4250, 3
7459 11:44:26.523468
7460 11:44:26.526111 MIOCK jitter meter ch=0
7461 11:44:26.526477
7462 11:44:26.529427 1T = (320-92) = 228 dly cells
7463 11:44:26.536214 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7464 11:44:26.536789 ==
7465 11:44:26.539454 Dram Type= 6, Freq= 0, CH_0, rank 0
7466 11:44:26.542428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7467 11:44:26.542862 ==
7468 11:44:26.549387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7469 11:44:26.552510 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7470 11:44:26.555742 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7471 11:44:26.562109 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7472 11:44:26.571176 [CA 0] Center 42 (13~72) winsize 60
7473 11:44:26.574314 [CA 1] Center 42 (12~72) winsize 61
7474 11:44:26.577976 [CA 2] Center 37 (7~67) winsize 61
7475 11:44:26.581428 [CA 3] Center 37 (7~67) winsize 61
7476 11:44:26.584542 [CA 4] Center 36 (6~66) winsize 61
7477 11:44:26.587663 [CA 5] Center 35 (5~65) winsize 61
7478 11:44:26.588147
7479 11:44:26.591027 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7480 11:44:26.591527
7481 11:44:26.594396 [CATrainingPosCal] consider 1 rank data
7482 11:44:26.597522 u2DelayCellTimex100 = 285/100 ps
7483 11:44:26.604158 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7484 11:44:26.607536 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7485 11:44:26.610843 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7486 11:44:26.614285 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7487 11:44:26.617418 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7488 11:44:26.620652 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7489 11:44:26.621113
7490 11:44:26.624152 CA PerBit enable=1, Macro0, CA PI delay=35
7491 11:44:26.624722
7492 11:44:26.627129 [CBTSetCACLKResult] CA Dly = 35
7493 11:44:26.630326 CS Dly: 9 (0~40)
7494 11:44:26.633673 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7495 11:44:26.637000 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7496 11:44:26.637430 ==
7497 11:44:26.640334 Dram Type= 6, Freq= 0, CH_0, rank 1
7498 11:44:26.647013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 11:44:26.647445 ==
7500 11:44:26.650112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 11:44:26.656617 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 11:44:26.660175 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 11:44:26.666494 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 11:44:26.674432 [CA 0] Center 43 (13~74) winsize 62
7505 11:44:26.677404 [CA 1] Center 43 (13~73) winsize 61
7506 11:44:26.680719 [CA 2] Center 38 (9~68) winsize 60
7507 11:44:26.684080 [CA 3] Center 38 (9~68) winsize 60
7508 11:44:26.687311 [CA 4] Center 37 (7~67) winsize 61
7509 11:44:26.690706 [CA 5] Center 36 (6~66) winsize 61
7510 11:44:26.691174
7511 11:44:26.694309 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7512 11:44:26.694735
7513 11:44:26.697494 [CATrainingPosCal] consider 2 rank data
7514 11:44:26.700835 u2DelayCellTimex100 = 285/100 ps
7515 11:44:26.707296 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7516 11:44:26.710577 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7517 11:44:26.713869 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7518 11:44:26.717451 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7519 11:44:26.720710 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7520 11:44:26.723923 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7521 11:44:26.724349
7522 11:44:26.727132 CA PerBit enable=1, Macro0, CA PI delay=35
7523 11:44:26.727558
7524 11:44:26.730477 [CBTSetCACLKResult] CA Dly = 35
7525 11:44:26.734052 CS Dly: 10 (0~43)
7526 11:44:26.736933 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 11:44:26.740570 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 11:44:26.741158
7529 11:44:26.743829 ----->DramcWriteLeveling(PI) begin...
7530 11:44:26.744353 ==
7531 11:44:26.747183 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 11:44:26.753573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 11:44:26.754011 ==
7534 11:44:26.756872 Write leveling (Byte 0): 36 => 36
7535 11:44:26.760243 Write leveling (Byte 1): 30 => 30
7536 11:44:26.760677 DramcWriteLeveling(PI) end<-----
7537 11:44:26.761045
7538 11:44:26.763577 ==
7539 11:44:26.766810 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 11:44:26.770023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 11:44:26.770482 ==
7542 11:44:26.773548 [Gating] SW mode calibration
7543 11:44:26.780160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7544 11:44:26.783700 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7545 11:44:26.790139 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7546 11:44:26.793410 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 11:44:26.796820 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7548 11:44:26.803376 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7549 11:44:26.806726 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7550 11:44:26.809981 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7551 11:44:26.816420 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 11:44:26.819680 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 11:44:26.823502 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 11:44:26.829948 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 11:44:26.833085 1 5 8 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7556 11:44:26.836543 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7557 11:44:26.843059 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7558 11:44:26.846216 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7559 11:44:26.849356 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 11:44:26.856260 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 11:44:26.859744 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 11:44:26.862764 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7563 11:44:26.869432 1 6 8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7564 11:44:26.872613 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7565 11:44:26.875881 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7566 11:44:26.882936 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (1 1) (0 0)
7567 11:44:26.885971 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 11:44:26.889169 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 11:44:26.895963 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 11:44:26.899116 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 11:44:26.902419 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 11:44:26.909055 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7573 11:44:26.912337 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7574 11:44:26.915823 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7575 11:44:26.922099 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 11:44:26.925257 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 11:44:26.928963 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 11:44:26.935667 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 11:44:26.939058 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 11:44:26.942225 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:44:26.948855 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 11:44:26.952219 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:44:26.955082 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:44:26.961792 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:44:26.965181 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:44:26.968274 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:44:26.975089 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7588 11:44:26.978463 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 11:44:26.981761 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7590 11:44:26.984927 Total UI for P1: 0, mck2ui 16
7591 11:44:26.988129 best dqsien dly found for B0: ( 1, 9, 10)
7592 11:44:26.995028 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7593 11:44:26.998246 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7594 11:44:27.001315 Total UI for P1: 0, mck2ui 16
7595 11:44:27.005032 best dqsien dly found for B1: ( 1, 9, 18)
7596 11:44:27.008278 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7597 11:44:27.011676 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7598 11:44:27.012237
7599 11:44:27.014940 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7600 11:44:27.018720 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7601 11:44:27.021769 [Gating] SW calibration Done
7602 11:44:27.022322 ==
7603 11:44:27.025019 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 11:44:27.028189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 11:44:27.031524 ==
7606 11:44:27.031943 RX Vref Scan: 0
7607 11:44:27.032274
7608 11:44:27.035016 RX Vref 0 -> 0, step: 1
7609 11:44:27.035436
7610 11:44:27.035769 RX Delay 0 -> 252, step: 8
7611 11:44:27.041486 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7612 11:44:27.044784 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7613 11:44:27.047916 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7614 11:44:27.051534 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7615 11:44:27.054447 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7616 11:44:27.061400 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7617 11:44:27.064469 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7618 11:44:27.067857 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7619 11:44:27.071147 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7620 11:44:27.074327 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7621 11:44:27.081008 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7622 11:44:27.084136 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7623 11:44:27.087509 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7624 11:44:27.091124 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7625 11:44:27.097915 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7626 11:44:27.101198 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7627 11:44:27.101666 ==
7628 11:44:27.104272 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 11:44:27.107689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 11:44:27.108174 ==
7631 11:44:27.108551 DQS Delay:
7632 11:44:27.111221 DQS0 = 0, DQS1 = 0
7633 11:44:27.111784 DQM Delay:
7634 11:44:27.114082 DQM0 = 138, DQM1 = 126
7635 11:44:27.114553 DQ Delay:
7636 11:44:27.117738 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7637 11:44:27.120905 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7638 11:44:27.124197 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7639 11:44:27.130796 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7640 11:44:27.131335
7641 11:44:27.131705
7642 11:44:27.132050 ==
7643 11:44:27.133860 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 11:44:27.137119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 11:44:27.137596 ==
7646 11:44:27.137972
7647 11:44:27.138318
7648 11:44:27.140819 TX Vref Scan disable
7649 11:44:27.141332 == TX Byte 0 ==
7650 11:44:27.147395 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7651 11:44:27.150556 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7652 11:44:27.150892 == TX Byte 1 ==
7653 11:44:27.157049 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7654 11:44:27.160119 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7655 11:44:27.160366 ==
7656 11:44:27.163417 Dram Type= 6, Freq= 0, CH_0, rank 0
7657 11:44:27.166749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7658 11:44:27.166913 ==
7659 11:44:27.181475
7660 11:44:27.184721 TX Vref early break, caculate TX vref
7661 11:44:27.187697 TX Vref=16, minBit 12, minWin=22, winSum=380
7662 11:44:27.191029 TX Vref=18, minBit 1, minWin=23, winSum=385
7663 11:44:27.194425 TX Vref=20, minBit 7, minWin=23, winSum=398
7664 11:44:27.197382 TX Vref=22, minBit 2, minWin=25, winSum=413
7665 11:44:27.200957 TX Vref=24, minBit 2, minWin=25, winSum=419
7666 11:44:27.207447 TX Vref=26, minBit 4, minWin=25, winSum=425
7667 11:44:27.210699 TX Vref=28, minBit 0, minWin=25, winSum=428
7668 11:44:27.214023 TX Vref=30, minBit 0, minWin=25, winSum=416
7669 11:44:27.217851 TX Vref=32, minBit 0, minWin=25, winSum=409
7670 11:44:27.221006 TX Vref=34, minBit 2, minWin=24, winSum=399
7671 11:44:27.227393 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
7672 11:44:27.227945
7673 11:44:27.230532 Final TX Range 0 Vref 28
7674 11:44:27.231003
7675 11:44:27.231373 ==
7676 11:44:27.233734 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 11:44:27.237495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 11:44:27.238029 ==
7679 11:44:27.238405
7680 11:44:27.238750
7681 11:44:27.240257 TX Vref Scan disable
7682 11:44:27.247059 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7683 11:44:27.247605 == TX Byte 0 ==
7684 11:44:27.250592 u2DelayCellOfst[0]=10 cells (3 PI)
7685 11:44:27.253983 u2DelayCellOfst[1]=17 cells (5 PI)
7686 11:44:27.257166 u2DelayCellOfst[2]=10 cells (3 PI)
7687 11:44:27.260384 u2DelayCellOfst[3]=10 cells (3 PI)
7688 11:44:27.263542 u2DelayCellOfst[4]=6 cells (2 PI)
7689 11:44:27.266767 u2DelayCellOfst[5]=0 cells (0 PI)
7690 11:44:27.269940 u2DelayCellOfst[6]=17 cells (5 PI)
7691 11:44:27.273227 u2DelayCellOfst[7]=13 cells (4 PI)
7692 11:44:27.276573 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7693 11:44:27.280146 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7694 11:44:27.283285 == TX Byte 1 ==
7695 11:44:27.286760 u2DelayCellOfst[8]=0 cells (0 PI)
7696 11:44:27.289834 u2DelayCellOfst[9]=0 cells (0 PI)
7697 11:44:27.293232 u2DelayCellOfst[10]=6 cells (2 PI)
7698 11:44:27.293731 u2DelayCellOfst[11]=3 cells (1 PI)
7699 11:44:27.296625 u2DelayCellOfst[12]=10 cells (3 PI)
7700 11:44:27.299956 u2DelayCellOfst[13]=10 cells (3 PI)
7701 11:44:27.303317 u2DelayCellOfst[14]=13 cells (4 PI)
7702 11:44:27.306643 u2DelayCellOfst[15]=10 cells (3 PI)
7703 11:44:27.312929 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7704 11:44:27.316338 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7705 11:44:27.316808 DramC Write-DBI on
7706 11:44:27.319737 ==
7707 11:44:27.322903 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 11:44:27.326182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 11:44:27.326747 ==
7710 11:44:27.327241
7711 11:44:27.327600
7712 11:44:27.329272 TX Vref Scan disable
7713 11:44:27.329894 == TX Byte 0 ==
7714 11:44:27.336179 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7715 11:44:27.336648 == TX Byte 1 ==
7716 11:44:27.339369 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7717 11:44:27.342682 DramC Write-DBI off
7718 11:44:27.343220
7719 11:44:27.343651 [DATLAT]
7720 11:44:27.346225 Freq=1600, CH0 RK0
7721 11:44:27.346699
7722 11:44:27.347071 DATLAT Default: 0xf
7723 11:44:27.349199 0, 0xFFFF, sum = 0
7724 11:44:27.349695 1, 0xFFFF, sum = 0
7725 11:44:27.352870 2, 0xFFFF, sum = 0
7726 11:44:27.353386 3, 0xFFFF, sum = 0
7727 11:44:27.356396 4, 0xFFFF, sum = 0
7728 11:44:27.357019 5, 0xFFFF, sum = 0
7729 11:44:27.359719 6, 0xFFFF, sum = 0
7730 11:44:27.360301 7, 0xFFFF, sum = 0
7731 11:44:27.362845 8, 0xFFFF, sum = 0
7732 11:44:27.366024 9, 0xFFFF, sum = 0
7733 11:44:27.366496 10, 0xFFFF, sum = 0
7734 11:44:27.369189 11, 0xFFFF, sum = 0
7735 11:44:27.369664 12, 0xFFFF, sum = 0
7736 11:44:27.373025 13, 0xFFFF, sum = 0
7737 11:44:27.373598 14, 0x0, sum = 1
7738 11:44:27.375791 15, 0x0, sum = 2
7739 11:44:27.376259 16, 0x0, sum = 3
7740 11:44:27.379090 17, 0x0, sum = 4
7741 11:44:27.379564 best_step = 15
7742 11:44:27.379932
7743 11:44:27.380396 ==
7744 11:44:27.382493 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 11:44:27.385984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 11:44:27.386553 ==
7747 11:44:27.389071 RX Vref Scan: 1
7748 11:44:27.389541
7749 11:44:27.392226 Set Vref Range= 24 -> 127
7750 11:44:27.392715
7751 11:44:27.393308 RX Vref 24 -> 127, step: 1
7752 11:44:27.395530
7753 11:44:27.396160 RX Delay 19 -> 252, step: 4
7754 11:44:27.396633
7755 11:44:27.399136 Set Vref, RX VrefLevel [Byte0]: 24
7756 11:44:27.402041 [Byte1]: 24
7757 11:44:27.405881
7758 11:44:27.406492 Set Vref, RX VrefLevel [Byte0]: 25
7759 11:44:27.409081 [Byte1]: 25
7760 11:44:27.413584
7761 11:44:27.414161 Set Vref, RX VrefLevel [Byte0]: 26
7762 11:44:27.416843 [Byte1]: 26
7763 11:44:27.420856
7764 11:44:27.424174 Set Vref, RX VrefLevel [Byte0]: 27
7765 11:44:27.427491 [Byte1]: 27
7766 11:44:27.428042
7767 11:44:27.431038 Set Vref, RX VrefLevel [Byte0]: 28
7768 11:44:27.433870 [Byte1]: 28
7769 11:44:27.434329
7770 11:44:27.437556 Set Vref, RX VrefLevel [Byte0]: 29
7771 11:44:27.440734 [Byte1]: 29
7772 11:44:27.441320
7773 11:44:27.444083 Set Vref, RX VrefLevel [Byte0]: 30
7774 11:44:27.447198 [Byte1]: 30
7775 11:44:27.451472
7776 11:44:27.452105 Set Vref, RX VrefLevel [Byte0]: 31
7777 11:44:27.454599 [Byte1]: 31
7778 11:44:27.459263
7779 11:44:27.459839 Set Vref, RX VrefLevel [Byte0]: 32
7780 11:44:27.462121 [Byte1]: 32
7781 11:44:27.466641
7782 11:44:27.467106 Set Vref, RX VrefLevel [Byte0]: 33
7783 11:44:27.469812 [Byte1]: 33
7784 11:44:27.474232
7785 11:44:27.474770 Set Vref, RX VrefLevel [Byte0]: 34
7786 11:44:27.477373 [Byte1]: 34
7787 11:44:27.481646
7788 11:44:27.482195 Set Vref, RX VrefLevel [Byte0]: 35
7789 11:44:27.484810 [Byte1]: 35
7790 11:44:27.489027
7791 11:44:27.489511 Set Vref, RX VrefLevel [Byte0]: 36
7792 11:44:27.492534 [Byte1]: 36
7793 11:44:27.496969
7794 11:44:27.497473 Set Vref, RX VrefLevel [Byte0]: 37
7795 11:44:27.500284 [Byte1]: 37
7796 11:44:27.504294
7797 11:44:27.504761 Set Vref, RX VrefLevel [Byte0]: 38
7798 11:44:27.507757 [Byte1]: 38
7799 11:44:27.511869
7800 11:44:27.512386 Set Vref, RX VrefLevel [Byte0]: 39
7801 11:44:27.515014 [Byte1]: 39
7802 11:44:27.519544
7803 11:44:27.520021 Set Vref, RX VrefLevel [Byte0]: 40
7804 11:44:27.522756 [Byte1]: 40
7805 11:44:27.527142
7806 11:44:27.527606 Set Vref, RX VrefLevel [Byte0]: 41
7807 11:44:27.530579 [Byte1]: 41
7808 11:44:27.534812
7809 11:44:27.535276 Set Vref, RX VrefLevel [Byte0]: 42
7810 11:44:27.538095 [Byte1]: 42
7811 11:44:27.542281
7812 11:44:27.542847 Set Vref, RX VrefLevel [Byte0]: 43
7813 11:44:27.545420 [Byte1]: 43
7814 11:44:27.549885
7815 11:44:27.550354 Set Vref, RX VrefLevel [Byte0]: 44
7816 11:44:27.553095 [Byte1]: 44
7817 11:44:27.557262
7818 11:44:27.557788 Set Vref, RX VrefLevel [Byte0]: 45
7819 11:44:27.560677 [Byte1]: 45
7820 11:44:27.564927
7821 11:44:27.565421 Set Vref, RX VrefLevel [Byte0]: 46
7822 11:44:27.568260 [Byte1]: 46
7823 11:44:27.572639
7824 11:44:27.573152 Set Vref, RX VrefLevel [Byte0]: 47
7825 11:44:27.575812 [Byte1]: 47
7826 11:44:27.580060
7827 11:44:27.580612 Set Vref, RX VrefLevel [Byte0]: 48
7828 11:44:27.583278 [Byte1]: 48
7829 11:44:27.587599
7830 11:44:27.588066 Set Vref, RX VrefLevel [Byte0]: 49
7831 11:44:27.590746 [Byte1]: 49
7832 11:44:27.595109
7833 11:44:27.595572 Set Vref, RX VrefLevel [Byte0]: 50
7834 11:44:27.598560 [Byte1]: 50
7835 11:44:27.602620
7836 11:44:27.603123 Set Vref, RX VrefLevel [Byte0]: 51
7837 11:44:27.605861 [Byte1]: 51
7838 11:44:27.610297
7839 11:44:27.610761 Set Vref, RX VrefLevel [Byte0]: 52
7840 11:44:27.613489 [Byte1]: 52
7841 11:44:27.618182
7842 11:44:27.618647 Set Vref, RX VrefLevel [Byte0]: 53
7843 11:44:27.621118 [Byte1]: 53
7844 11:44:27.625401
7845 11:44:27.625861 Set Vref, RX VrefLevel [Byte0]: 54
7846 11:44:27.628959 [Byte1]: 54
7847 11:44:27.633130
7848 11:44:27.633594 Set Vref, RX VrefLevel [Byte0]: 55
7849 11:44:27.636376 [Byte1]: 55
7850 11:44:27.640730
7851 11:44:27.641309 Set Vref, RX VrefLevel [Byte0]: 56
7852 11:44:27.643942 [Byte1]: 56
7853 11:44:27.648311
7854 11:44:27.648886 Set Vref, RX VrefLevel [Byte0]: 57
7855 11:44:27.651379 [Byte1]: 57
7856 11:44:27.656193
7857 11:44:27.656757 Set Vref, RX VrefLevel [Byte0]: 58
7858 11:44:27.659249 [Byte1]: 58
7859 11:44:27.663304
7860 11:44:27.663775 Set Vref, RX VrefLevel [Byte0]: 59
7861 11:44:27.666592 [Byte1]: 59
7862 11:44:27.671110
7863 11:44:27.671572 Set Vref, RX VrefLevel [Byte0]: 60
7864 11:44:27.674211 [Byte1]: 60
7865 11:44:27.678662
7866 11:44:27.679217 Set Vref, RX VrefLevel [Byte0]: 61
7867 11:44:27.682262 [Byte1]: 61
7868 11:44:27.686259
7869 11:44:27.686726 Set Vref, RX VrefLevel [Byte0]: 62
7870 11:44:27.689479 [Byte1]: 62
7871 11:44:27.693512
7872 11:44:27.694014 Set Vref, RX VrefLevel [Byte0]: 63
7873 11:44:27.696761 [Byte1]: 63
7874 11:44:27.701125
7875 11:44:27.701589 Set Vref, RX VrefLevel [Byte0]: 64
7876 11:44:27.704366 [Byte1]: 64
7877 11:44:27.709060
7878 11:44:27.709580 Set Vref, RX VrefLevel [Byte0]: 65
7879 11:44:27.712071 [Byte1]: 65
7880 11:44:27.716567
7881 11:44:27.717083 Set Vref, RX VrefLevel [Byte0]: 66
7882 11:44:27.719948 [Byte1]: 66
7883 11:44:27.723986
7884 11:44:27.724450 Set Vref, RX VrefLevel [Byte0]: 67
7885 11:44:27.727195 [Byte1]: 67
7886 11:44:27.731518
7887 11:44:27.731990 Set Vref, RX VrefLevel [Byte0]: 68
7888 11:44:27.734801 [Byte1]: 68
7889 11:44:27.739331
7890 11:44:27.739800 Set Vref, RX VrefLevel [Byte0]: 69
7891 11:44:27.742211 [Byte1]: 69
7892 11:44:27.746854
7893 11:44:27.747438 Set Vref, RX VrefLevel [Byte0]: 70
7894 11:44:27.749804 [Byte1]: 70
7895 11:44:27.754447
7896 11:44:27.754910 Set Vref, RX VrefLevel [Byte0]: 71
7897 11:44:27.757774 [Byte1]: 71
7898 11:44:27.761964
7899 11:44:27.762512 Set Vref, RX VrefLevel [Byte0]: 72
7900 11:44:27.765164 [Byte1]: 72
7901 11:44:27.769290
7902 11:44:27.769754 Set Vref, RX VrefLevel [Byte0]: 73
7903 11:44:27.772846 [Byte1]: 73
7904 11:44:27.777219
7905 11:44:27.777686 Set Vref, RX VrefLevel [Byte0]: 74
7906 11:44:27.780274 [Byte1]: 74
7907 11:44:27.784465
7908 11:44:27.785049 Set Vref, RX VrefLevel [Byte0]: 75
7909 11:44:27.787990 [Byte1]: 75
7910 11:44:27.792337
7911 11:44:27.792803 Set Vref, RX VrefLevel [Byte0]: 76
7912 11:44:27.795505 [Byte1]: 76
7913 11:44:27.799676
7914 11:44:27.800144 Set Vref, RX VrefLevel [Byte0]: 77
7915 11:44:27.802760 [Byte1]: 77
7916 11:44:27.807185
7917 11:44:27.807646 Set Vref, RX VrefLevel [Byte0]: 78
7918 11:44:27.810315 [Byte1]: 78
7919 11:44:27.815140
7920 11:44:27.815699 Set Vref, RX VrefLevel [Byte0]: 79
7921 11:44:27.818141 [Byte1]: 79
7922 11:44:27.822535
7923 11:44:27.822997 Set Vref, RX VrefLevel [Byte0]: 80
7924 11:44:27.825654 [Byte1]: 80
7925 11:44:27.829995
7926 11:44:27.830552 Final RX Vref Byte 0 = 60 to rank0
7927 11:44:27.833065 Final RX Vref Byte 1 = 62 to rank0
7928 11:44:27.837007 Final RX Vref Byte 0 = 60 to rank1
7929 11:44:27.840016 Final RX Vref Byte 1 = 62 to rank1==
7930 11:44:27.843502 Dram Type= 6, Freq= 0, CH_0, rank 0
7931 11:44:27.849432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7932 11:44:27.849901 ==
7933 11:44:27.850320 DQS Delay:
7934 11:44:27.852849 DQS0 = 0, DQS1 = 0
7935 11:44:27.853369 DQM Delay:
7936 11:44:27.853744 DQM0 = 135, DQM1 = 124
7937 11:44:27.856559 DQ Delay:
7938 11:44:27.859496 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7939 11:44:27.862844 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7940 11:44:27.866094 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
7941 11:44:27.869468 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7942 11:44:27.869934
7943 11:44:27.870297
7944 11:44:27.870636
7945 11:44:27.872622 [DramC_TX_OE_Calibration] TA2
7946 11:44:27.876363 Original DQ_B0 (3 6) =30, OEN = 27
7947 11:44:27.879736 Original DQ_B1 (3 6) =30, OEN = 27
7948 11:44:27.882928 24, 0x0, End_B0=24 End_B1=24
7949 11:44:27.886015 25, 0x0, End_B0=25 End_B1=25
7950 11:44:27.886509 26, 0x0, End_B0=26 End_B1=26
7951 11:44:27.889302 27, 0x0, End_B0=27 End_B1=27
7952 11:44:27.892490 28, 0x0, End_B0=28 End_B1=28
7953 11:44:27.895684 29, 0x0, End_B0=29 End_B1=29
7954 11:44:27.896160 30, 0x0, End_B0=30 End_B1=30
7955 11:44:27.899258 31, 0x5151, End_B0=30 End_B1=30
7956 11:44:27.902576 Byte0 end_step=30 best_step=27
7957 11:44:27.905747 Byte1 end_step=30 best_step=27
7958 11:44:27.909053 Byte0 TX OE(2T, 0.5T) = (3, 3)
7959 11:44:27.912453 Byte1 TX OE(2T, 0.5T) = (3, 3)
7960 11:44:27.912938
7961 11:44:27.913397
7962 11:44:27.919029 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7963 11:44:27.922441 CH0 RK0: MR19=303, MR18=1D1B
7964 11:44:27.929062 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7965 11:44:27.929590
7966 11:44:27.932220 ----->DramcWriteLeveling(PI) begin...
7967 11:44:27.932723 ==
7968 11:44:27.935382 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 11:44:27.938931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 11:44:27.939622 ==
7971 11:44:27.941837 Write leveling (Byte 0): 38 => 38
7972 11:44:27.945484 Write leveling (Byte 1): 29 => 29
7973 11:44:27.948638 DramcWriteLeveling(PI) end<-----
7974 11:44:27.949143
7975 11:44:27.949514 ==
7976 11:44:27.952057 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 11:44:27.955455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 11:44:27.958436 ==
7979 11:44:27.958952 [Gating] SW mode calibration
7980 11:44:27.968336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7981 11:44:27.972092 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7982 11:44:27.975336 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 11:44:27.981812 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 11:44:27.985002 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7985 11:44:27.988149 1 4 12 | B1->B0 | 2727 3232 | 1 1 | (1 1) (1 1)
7986 11:44:27.994677 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 11:44:27.997942 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 11:44:28.001300 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 11:44:28.008202 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 11:44:28.011511 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 11:44:28.014396 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 11:44:28.021277 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7993 11:44:28.024506 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
7994 11:44:28.028310 1 5 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7995 11:44:28.034644 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 11:44:28.038210 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 11:44:28.041487 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 11:44:28.047866 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 11:44:28.051046 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 11:44:28.054580 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8001 11:44:28.060940 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8002 11:44:28.064579 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8003 11:44:28.067655 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 11:44:28.074135 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 11:44:28.077473 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 11:44:28.081039 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 11:44:28.087530 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 11:44:28.090954 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 11:44:28.093979 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8010 11:44:28.100632 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8011 11:44:28.103691 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:44:28.107514 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:44:28.113960 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 11:44:28.117096 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 11:44:28.120664 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 11:44:28.127091 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 11:44:28.130258 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 11:44:28.133488 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 11:44:28.140280 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 11:44:28.143834 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 11:44:28.146955 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 11:44:28.153415 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 11:44:28.156766 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 11:44:28.160055 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8025 11:44:28.166651 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8026 11:44:28.169928 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8027 11:44:28.173490 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 11:44:28.176492 Total UI for P1: 0, mck2ui 16
8029 11:44:28.179824 best dqsien dly found for B0: ( 1, 9, 12)
8030 11:44:28.183328 Total UI for P1: 0, mck2ui 16
8031 11:44:28.186707 best dqsien dly found for B1: ( 1, 9, 14)
8032 11:44:28.190324 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8033 11:44:28.193217 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8034 11:44:28.193681
8035 11:44:28.199580 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8036 11:44:28.203105 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8037 11:44:28.203578 [Gating] SW calibration Done
8038 11:44:28.206378 ==
8039 11:44:28.209737 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 11:44:28.212883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 11:44:28.213435 ==
8042 11:44:28.213813 RX Vref Scan: 0
8043 11:44:28.214163
8044 11:44:28.216325 RX Vref 0 -> 0, step: 1
8045 11:44:28.216957
8046 11:44:28.219750 RX Delay 0 -> 252, step: 8
8047 11:44:28.223193 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8048 11:44:28.226193 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8049 11:44:28.229448 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8050 11:44:28.236463 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8051 11:44:28.239570 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8052 11:44:28.243093 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8053 11:44:28.246332 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8054 11:44:28.249440 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8055 11:44:28.256017 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8056 11:44:28.259150 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8057 11:44:28.262793 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8058 11:44:28.265830 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8059 11:44:28.272868 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8060 11:44:28.276059 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8061 11:44:28.279209 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8062 11:44:28.282460 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8063 11:44:28.282957 ==
8064 11:44:28.285565 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 11:44:28.292458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 11:44:28.292971 ==
8067 11:44:28.293422 DQS Delay:
8068 11:44:28.293772 DQS0 = 0, DQS1 = 0
8069 11:44:28.296130 DQM Delay:
8070 11:44:28.296815 DQM0 = 136, DQM1 = 124
8071 11:44:28.299211 DQ Delay:
8072 11:44:28.302209 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8073 11:44:28.305640 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8074 11:44:28.308788 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8075 11:44:28.312109 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8076 11:44:28.312720
8077 11:44:28.313349
8078 11:44:28.313713 ==
8079 11:44:28.315384 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 11:44:28.318636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 11:44:28.322022 ==
8082 11:44:28.322591
8083 11:44:28.323168
8084 11:44:28.323526 TX Vref Scan disable
8085 11:44:28.325260 == TX Byte 0 ==
8086 11:44:28.328427 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8087 11:44:28.331984 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8088 11:44:28.335350 == TX Byte 1 ==
8089 11:44:28.338408 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8090 11:44:28.345066 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8091 11:44:28.345629 ==
8092 11:44:28.348387 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 11:44:28.351588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 11:44:28.352088 ==
8095 11:44:28.365249
8096 11:44:28.368063 TX Vref early break, caculate TX vref
8097 11:44:28.371677 TX Vref=16, minBit 0, minWin=23, winSum=392
8098 11:44:28.374698 TX Vref=18, minBit 0, minWin=23, winSum=395
8099 11:44:28.378324 TX Vref=20, minBit 8, minWin=24, winSum=410
8100 11:44:28.381480 TX Vref=22, minBit 0, minWin=25, winSum=418
8101 11:44:28.384815 TX Vref=24, minBit 0, minWin=25, winSum=423
8102 11:44:28.391351 TX Vref=26, minBit 0, minWin=26, winSum=430
8103 11:44:28.394947 TX Vref=28, minBit 0, minWin=25, winSum=427
8104 11:44:28.397995 TX Vref=30, minBit 0, minWin=25, winSum=422
8105 11:44:28.401377 TX Vref=32, minBit 0, minWin=25, winSum=411
8106 11:44:28.404691 TX Vref=34, minBit 3, minWin=24, winSum=401
8107 11:44:28.411298 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
8108 11:44:28.411832
8109 11:44:28.414743 Final TX Range 0 Vref 26
8110 11:44:28.415220
8111 11:44:28.415590 ==
8112 11:44:28.417896 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 11:44:28.421099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 11:44:28.421577 ==
8115 11:44:28.421948
8116 11:44:28.422290
8117 11:44:28.424312 TX Vref Scan disable
8118 11:44:28.430884 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8119 11:44:28.431414 == TX Byte 0 ==
8120 11:44:28.434359 u2DelayCellOfst[0]=13 cells (4 PI)
8121 11:44:28.437689 u2DelayCellOfst[1]=20 cells (6 PI)
8122 11:44:28.441009 u2DelayCellOfst[2]=13 cells (4 PI)
8123 11:44:28.443984 u2DelayCellOfst[3]=13 cells (4 PI)
8124 11:44:28.447484 u2DelayCellOfst[4]=10 cells (3 PI)
8125 11:44:28.450920 u2DelayCellOfst[5]=0 cells (0 PI)
8126 11:44:28.454073 u2DelayCellOfst[6]=20 cells (6 PI)
8127 11:44:28.457795 u2DelayCellOfst[7]=20 cells (6 PI)
8128 11:44:28.460917 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8129 11:44:28.464051 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8130 11:44:28.467858 == TX Byte 1 ==
8131 11:44:28.470961 u2DelayCellOfst[8]=3 cells (1 PI)
8132 11:44:28.473783 u2DelayCellOfst[9]=0 cells (0 PI)
8133 11:44:28.474368 u2DelayCellOfst[10]=6 cells (2 PI)
8134 11:44:28.477397 u2DelayCellOfst[11]=3 cells (1 PI)
8135 11:44:28.480716 u2DelayCellOfst[12]=13 cells (4 PI)
8136 11:44:28.484053 u2DelayCellOfst[13]=13 cells (4 PI)
8137 11:44:28.487364 u2DelayCellOfst[14]=17 cells (5 PI)
8138 11:44:28.490941 u2DelayCellOfst[15]=10 cells (3 PI)
8139 11:44:28.497084 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8140 11:44:28.500384 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8141 11:44:28.500857 DramC Write-DBI on
8142 11:44:28.501304 ==
8143 11:44:28.503948 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 11:44:28.510451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 11:44:28.511171 ==
8146 11:44:28.511563
8147 11:44:28.511908
8148 11:44:28.512242 TX Vref Scan disable
8149 11:44:28.514723 == TX Byte 0 ==
8150 11:44:28.517725 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8151 11:44:28.521079 == TX Byte 1 ==
8152 11:44:28.524267 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8153 11:44:28.528075 DramC Write-DBI off
8154 11:44:28.528543
8155 11:44:28.528930 [DATLAT]
8156 11:44:28.529433 Freq=1600, CH0 RK1
8157 11:44:28.529886
8158 11:44:28.531259 DATLAT Default: 0xf
8159 11:44:28.534459 0, 0xFFFF, sum = 0
8160 11:44:28.534948 1, 0xFFFF, sum = 0
8161 11:44:28.537438 2, 0xFFFF, sum = 0
8162 11:44:28.537884 3, 0xFFFF, sum = 0
8163 11:44:28.540961 4, 0xFFFF, sum = 0
8164 11:44:28.541431 5, 0xFFFF, sum = 0
8165 11:44:28.544287 6, 0xFFFF, sum = 0
8166 11:44:28.544721 7, 0xFFFF, sum = 0
8167 11:44:28.547620 8, 0xFFFF, sum = 0
8168 11:44:28.548052 9, 0xFFFF, sum = 0
8169 11:44:28.550560 10, 0xFFFF, sum = 0
8170 11:44:28.550994 11, 0xFFFF, sum = 0
8171 11:44:28.554262 12, 0xFFFF, sum = 0
8172 11:44:28.554694 13, 0xFFFF, sum = 0
8173 11:44:28.557668 14, 0x0, sum = 1
8174 11:44:28.558100 15, 0x0, sum = 2
8175 11:44:28.560689 16, 0x0, sum = 3
8176 11:44:28.561150 17, 0x0, sum = 4
8177 11:44:28.564108 best_step = 15
8178 11:44:28.564534
8179 11:44:28.564869 ==
8180 11:44:28.567406 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 11:44:28.570641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 11:44:28.571073 ==
8183 11:44:28.574019 RX Vref Scan: 0
8184 11:44:28.574521
8185 11:44:28.574859 RX Vref 0 -> 0, step: 1
8186 11:44:28.575173
8187 11:44:28.577194 RX Delay 11 -> 252, step: 4
8188 11:44:28.583510 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8189 11:44:28.586916 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8190 11:44:28.590133 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8191 11:44:28.593342 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8192 11:44:28.597044 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8193 11:44:28.603372 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8194 11:44:28.606629 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8195 11:44:28.609967 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8196 11:44:28.613149 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8197 11:44:28.616337 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8198 11:44:28.622856 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8199 11:44:28.626495 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8200 11:44:28.629636 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8201 11:44:28.632769 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8202 11:44:28.639502 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8203 11:44:28.642586 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8204 11:44:28.643139 ==
8205 11:44:28.646071 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 11:44:28.649213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 11:44:28.649771 ==
8208 11:44:28.652497 DQS Delay:
8209 11:44:28.653065 DQS0 = 0, DQS1 = 0
8210 11:44:28.653547 DQM Delay:
8211 11:44:28.655889 DQM0 = 133, DQM1 = 123
8212 11:44:28.656435 DQ Delay:
8213 11:44:28.659082 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8214 11:44:28.662897 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8215 11:44:28.669352 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8216 11:44:28.672487 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8217 11:44:28.672908
8218 11:44:28.673289
8219 11:44:28.673601
8220 11:44:28.675575 [DramC_TX_OE_Calibration] TA2
8221 11:44:28.678868 Original DQ_B0 (3 6) =30, OEN = 27
8222 11:44:28.682287 Original DQ_B1 (3 6) =30, OEN = 27
8223 11:44:28.682721 24, 0x0, End_B0=24 End_B1=24
8224 11:44:28.685352 25, 0x0, End_B0=25 End_B1=25
8225 11:44:28.688544 26, 0x0, End_B0=26 End_B1=26
8226 11:44:28.691918 27, 0x0, End_B0=27 End_B1=27
8227 11:44:28.695473 28, 0x0, End_B0=28 End_B1=28
8228 11:44:28.695920 29, 0x0, End_B0=29 End_B1=29
8229 11:44:28.698699 30, 0x0, End_B0=30 End_B1=30
8230 11:44:28.701963 31, 0x4141, End_B0=30 End_B1=30
8231 11:44:28.705043 Byte0 end_step=30 best_step=27
8232 11:44:28.708698 Byte1 end_step=30 best_step=27
8233 11:44:28.709298 Byte0 TX OE(2T, 0.5T) = (3, 3)
8234 11:44:28.712070 Byte1 TX OE(2T, 0.5T) = (3, 3)
8235 11:44:28.712608
8236 11:44:28.712948
8237 11:44:28.721993 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8238 11:44:28.724970 CH0 RK1: MR19=303, MR18=220F
8239 11:44:28.731524 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8240 11:44:28.732123 [RxdqsGatingPostProcess] freq 1600
8241 11:44:28.738574 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8242 11:44:28.790211 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 11:44:28.790654 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 11:44:28.791002 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 11:44:28.791362 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 11:44:28.791707 best DQS0 dly(2T, 0.5T) = (1, 1)
8247 11:44:28.792109 best DQS1 dly(2T, 0.5T) = (1, 1)
8248 11:44:28.792557 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8249 11:44:28.792868 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8250 11:44:28.793231 Pre-setting of DQS Precalculation
8251 11:44:28.793529 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8252 11:44:28.793819 ==
8253 11:44:28.794102 Dram Type= 6, Freq= 0, CH_1, rank 0
8254 11:44:28.794388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 11:44:28.794675 ==
8256 11:44:28.794956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8257 11:44:28.795235 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8258 11:44:28.795818 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8259 11:44:28.798017 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8260 11:44:28.807632 [CA 0] Center 40 (11~70) winsize 60
8261 11:44:28.810963 [CA 1] Center 41 (11~71) winsize 61
8262 11:44:28.814189 [CA 2] Center 37 (8~67) winsize 60
8263 11:44:28.817178 [CA 3] Center 36 (7~66) winsize 60
8264 11:44:28.820336 [CA 4] Center 36 (7~66) winsize 60
8265 11:44:28.824142 [CA 5] Center 35 (5~66) winsize 62
8266 11:44:28.824372
8267 11:44:28.827150 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8268 11:44:28.827336
8269 11:44:28.830314 [CATrainingPosCal] consider 1 rank data
8270 11:44:28.833785 u2DelayCellTimex100 = 285/100 ps
8271 11:44:28.840580 CA0 delay=40 (11~70),Diff = 5 PI (17 cell)
8272 11:44:28.843864 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8273 11:44:28.847176 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
8274 11:44:28.850695 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8275 11:44:28.853686 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8276 11:44:28.857479 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
8277 11:44:28.857905
8278 11:44:28.860838 CA PerBit enable=1, Macro0, CA PI delay=35
8279 11:44:28.861409
8280 11:44:28.863836 [CBTSetCACLKResult] CA Dly = 35
8281 11:44:28.866997 CS Dly: 8 (0~39)
8282 11:44:28.870542 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8283 11:44:28.873799 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8284 11:44:28.874410 ==
8285 11:44:28.876931 Dram Type= 6, Freq= 0, CH_1, rank 1
8286 11:44:28.880642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 11:44:28.883662 ==
8288 11:44:28.887182 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 11:44:28.890210 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 11:44:28.897012 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 11:44:28.903237 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 11:44:28.910613 [CA 0] Center 42 (13~72) winsize 60
8293 11:44:28.913992 [CA 1] Center 41 (11~71) winsize 61
8294 11:44:28.917104 [CA 2] Center 37 (8~67) winsize 60
8295 11:44:28.920480 [CA 3] Center 37 (8~66) winsize 59
8296 11:44:28.923797 [CA 4] Center 37 (8~67) winsize 60
8297 11:44:28.927006 [CA 5] Center 36 (7~66) winsize 60
8298 11:44:28.927452
8299 11:44:28.930483 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8300 11:44:28.930950
8301 11:44:28.933718 [CATrainingPosCal] consider 2 rank data
8302 11:44:28.936966 u2DelayCellTimex100 = 285/100 ps
8303 11:44:28.943205 CA0 delay=41 (13~70),Diff = 5 PI (17 cell)
8304 11:44:28.946606 CA1 delay=41 (11~71),Diff = 5 PI (17 cell)
8305 11:44:28.949846 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8306 11:44:28.953329 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8307 11:44:28.956717 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8308 11:44:28.959767 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 11:44:28.960132
8310 11:44:28.963326 CA PerBit enable=1, Macro0, CA PI delay=36
8311 11:44:28.963649
8312 11:44:28.966687 [CBTSetCACLKResult] CA Dly = 36
8313 11:44:28.969993 CS Dly: 10 (0~43)
8314 11:44:28.973141 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 11:44:28.976122 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 11:44:28.976462
8317 11:44:28.979587 ----->DramcWriteLeveling(PI) begin...
8318 11:44:28.979915 ==
8319 11:44:28.982854 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 11:44:28.989668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 11:44:28.990020 ==
8322 11:44:28.992802 Write leveling (Byte 0): 23 => 23
8323 11:44:28.995917 Write leveling (Byte 1): 27 => 27
8324 11:44:28.999254 DramcWriteLeveling(PI) end<-----
8325 11:44:28.999666
8326 11:44:28.999988 ==
8327 11:44:29.002817 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 11:44:29.005935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 11:44:29.006504 ==
8330 11:44:29.009570 [Gating] SW mode calibration
8331 11:44:29.015979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8332 11:44:29.019730 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8333 11:44:29.026164 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 11:44:29.029632 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 11:44:29.032552 1 4 8 | B1->B0 | 2626 2e2e | 1 1 | (0 0) (0 0)
8336 11:44:29.039319 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 11:44:29.042412 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 11:44:29.045697 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 11:44:29.052088 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 11:44:29.055682 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 11:44:29.058959 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 11:44:29.065578 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8343 11:44:29.069055 1 5 8 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 1)
8344 11:44:29.072261 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8345 11:44:29.079218 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 11:44:29.082205 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 11:44:29.085457 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 11:44:29.092366 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 11:44:29.095704 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 11:44:29.099132 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 11:44:29.105472 1 6 8 | B1->B0 | 3434 3e3e | 1 0 | (0 0) (0 0)
8352 11:44:29.108720 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 11:44:29.112172 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 11:44:29.119025 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 11:44:29.122095 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 11:44:29.125216 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 11:44:29.132084 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 11:44:29.135316 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8359 11:44:29.138568 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 11:44:29.144940 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8361 11:44:29.148403 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8362 11:44:29.151880 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:44:29.158803 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 11:44:29.161954 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 11:44:29.165231 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 11:44:29.171466 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 11:44:29.174652 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 11:44:29.178070 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 11:44:29.184873 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 11:44:29.188192 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 11:44:29.191451 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 11:44:29.198079 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:44:29.201684 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:44:29.204814 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8375 11:44:29.211434 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8376 11:44:29.214932 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 11:44:29.218324 Total UI for P1: 0, mck2ui 16
8378 11:44:29.221346 best dqsien dly found for B0: ( 1, 9, 6)
8379 11:44:29.224602 Total UI for P1: 0, mck2ui 16
8380 11:44:29.227769 best dqsien dly found for B1: ( 1, 9, 8)
8381 11:44:29.231061 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8382 11:44:29.234407 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8383 11:44:29.234926
8384 11:44:29.238053 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8385 11:44:29.241368 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8386 11:44:29.244540 [Gating] SW calibration Done
8387 11:44:29.245130 ==
8388 11:44:29.247771 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 11:44:29.251117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 11:44:29.251644 ==
8391 11:44:29.254345 RX Vref Scan: 0
8392 11:44:29.254809
8393 11:44:29.257900 RX Vref 0 -> 0, step: 1
8394 11:44:29.258362
8395 11:44:29.258755 RX Delay 0 -> 252, step: 8
8396 11:44:29.264286 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8397 11:44:29.267461 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8398 11:44:29.270932 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8399 11:44:29.274168 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8400 11:44:29.277260 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8401 11:44:29.284046 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8402 11:44:29.287474 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8403 11:44:29.290692 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8404 11:44:29.294386 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8405 11:44:29.297427 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8406 11:44:29.303864 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8407 11:44:29.307079 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8408 11:44:29.310503 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8409 11:44:29.313714 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8410 11:44:29.317221 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8411 11:44:29.323762 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8412 11:44:29.324265 ==
8413 11:44:29.327038 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 11:44:29.330550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 11:44:29.330981 ==
8416 11:44:29.331321 DQS Delay:
8417 11:44:29.333829 DQS0 = 0, DQS1 = 0
8418 11:44:29.334255 DQM Delay:
8419 11:44:29.337165 DQM0 = 137, DQM1 = 130
8420 11:44:29.337613 DQ Delay:
8421 11:44:29.340405 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8422 11:44:29.343398 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8423 11:44:29.346713 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8424 11:44:29.349914 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8425 11:44:29.353242
8426 11:44:29.353763
8427 11:44:29.354232 ==
8428 11:44:29.356400 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 11:44:29.359800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 11:44:29.360239 ==
8431 11:44:29.360575
8432 11:44:29.360888
8433 11:44:29.363349 TX Vref Scan disable
8434 11:44:29.363771 == TX Byte 0 ==
8435 11:44:29.370275 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8436 11:44:29.373077 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8437 11:44:29.373505 == TX Byte 1 ==
8438 11:44:29.380066 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8439 11:44:29.383486 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8440 11:44:29.383913 ==
8441 11:44:29.386647 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 11:44:29.389923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 11:44:29.390514 ==
8444 11:44:29.403188
8445 11:44:29.406773 TX Vref early break, caculate TX vref
8446 11:44:29.410062 TX Vref=16, minBit 10, minWin=22, winSum=374
8447 11:44:29.412935 TX Vref=18, minBit 10, minWin=22, winSum=387
8448 11:44:29.416482 TX Vref=20, minBit 10, minWin=23, winSum=392
8449 11:44:29.419819 TX Vref=22, minBit 15, minWin=23, winSum=405
8450 11:44:29.426198 TX Vref=24, minBit 10, minWin=25, winSum=417
8451 11:44:29.429458 TX Vref=26, minBit 10, minWin=25, winSum=422
8452 11:44:29.433049 TX Vref=28, minBit 12, minWin=25, winSum=420
8453 11:44:29.435993 TX Vref=30, minBit 13, minWin=24, winSum=413
8454 11:44:29.439653 TX Vref=32, minBit 9, minWin=24, winSum=404
8455 11:44:29.446219 TX Vref=34, minBit 12, minWin=23, winSum=394
8456 11:44:29.449520 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 26
8457 11:44:29.450017
8458 11:44:29.452520 Final TX Range 0 Vref 26
8459 11:44:29.452942
8460 11:44:29.453340 ==
8461 11:44:29.455833 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 11:44:29.462428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 11:44:29.462919 ==
8464 11:44:29.463255
8465 11:44:29.463566
8466 11:44:29.463864 TX Vref Scan disable
8467 11:44:29.469393 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8468 11:44:29.469817 == TX Byte 0 ==
8469 11:44:29.472510 u2DelayCellOfst[0]=13 cells (4 PI)
8470 11:44:29.476368 u2DelayCellOfst[1]=6 cells (2 PI)
8471 11:44:29.479251 u2DelayCellOfst[2]=0 cells (0 PI)
8472 11:44:29.482817 u2DelayCellOfst[3]=3 cells (1 PI)
8473 11:44:29.485936 u2DelayCellOfst[4]=6 cells (2 PI)
8474 11:44:29.489309 u2DelayCellOfst[5]=17 cells (5 PI)
8475 11:44:29.492457 u2DelayCellOfst[6]=17 cells (5 PI)
8476 11:44:29.495907 u2DelayCellOfst[7]=3 cells (1 PI)
8477 11:44:29.499161 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8478 11:44:29.502271 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8479 11:44:29.505673 == TX Byte 1 ==
8480 11:44:29.508623 u2DelayCellOfst[8]=0 cells (0 PI)
8481 11:44:29.512176 u2DelayCellOfst[9]=3 cells (1 PI)
8482 11:44:29.515187 u2DelayCellOfst[10]=10 cells (3 PI)
8483 11:44:29.518543 u2DelayCellOfst[11]=3 cells (1 PI)
8484 11:44:29.521900 u2DelayCellOfst[12]=13 cells (4 PI)
8485 11:44:29.525037 u2DelayCellOfst[13]=17 cells (5 PI)
8486 11:44:29.528507 u2DelayCellOfst[14]=17 cells (5 PI)
8487 11:44:29.531836 u2DelayCellOfst[15]=17 cells (5 PI)
8488 11:44:29.535145 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8489 11:44:29.538379 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8490 11:44:29.541560 DramC Write-DBI on
8491 11:44:29.542112 ==
8492 11:44:29.544747 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 11:44:29.548402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 11:44:29.549102 ==
8495 11:44:29.549677
8496 11:44:29.550135
8497 11:44:29.551425 TX Vref Scan disable
8498 11:44:29.551992 == TX Byte 0 ==
8499 11:44:29.558019 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8500 11:44:29.558554 == TX Byte 1 ==
8501 11:44:29.564819 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8502 11:44:29.565425 DramC Write-DBI off
8503 11:44:29.565769
8504 11:44:29.566077 [DATLAT]
8505 11:44:29.568098 Freq=1600, CH1 RK0
8506 11:44:29.568687
8507 11:44:29.569241 DATLAT Default: 0xf
8508 11:44:29.571292 0, 0xFFFF, sum = 0
8509 11:44:29.574751 1, 0xFFFF, sum = 0
8510 11:44:29.575345 2, 0xFFFF, sum = 0
8511 11:44:29.577966 3, 0xFFFF, sum = 0
8512 11:44:29.578535 4, 0xFFFF, sum = 0
8513 11:44:29.581159 5, 0xFFFF, sum = 0
8514 11:44:29.581667 6, 0xFFFF, sum = 0
8515 11:44:29.584595 7, 0xFFFF, sum = 0
8516 11:44:29.585163 8, 0xFFFF, sum = 0
8517 11:44:29.588352 9, 0xFFFF, sum = 0
8518 11:44:29.588908 10, 0xFFFF, sum = 0
8519 11:44:29.591288 11, 0xFFFF, sum = 0
8520 11:44:29.591722 12, 0xFFFF, sum = 0
8521 11:44:29.594553 13, 0xFFFF, sum = 0
8522 11:44:29.594986 14, 0x0, sum = 1
8523 11:44:29.598069 15, 0x0, sum = 2
8524 11:44:29.598535 16, 0x0, sum = 3
8525 11:44:29.601174 17, 0x0, sum = 4
8526 11:44:29.601658 best_step = 15
8527 11:44:29.602005
8528 11:44:29.602427 ==
8529 11:44:29.604431 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 11:44:29.610970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 11:44:29.611445 ==
8532 11:44:29.611822 RX Vref Scan: 1
8533 11:44:29.612183
8534 11:44:29.614684 Set Vref Range= 24 -> 127
8535 11:44:29.615300
8536 11:44:29.617879 RX Vref 24 -> 127, step: 1
8537 11:44:29.618348
8538 11:44:29.618882 RX Delay 19 -> 252, step: 4
8539 11:44:29.619269
8540 11:44:29.620852 Set Vref, RX VrefLevel [Byte0]: 24
8541 11:44:29.624185 [Byte1]: 24
8542 11:44:29.628100
8543 11:44:29.628668 Set Vref, RX VrefLevel [Byte0]: 25
8544 11:44:29.631749 [Byte1]: 25
8545 11:44:29.635809
8546 11:44:29.636113 Set Vref, RX VrefLevel [Byte0]: 26
8547 11:44:29.638979 [Byte1]: 26
8548 11:44:29.643233
8549 11:44:29.643420 Set Vref, RX VrefLevel [Byte0]: 27
8550 11:44:29.646259 [Byte1]: 27
8551 11:44:29.650883
8552 11:44:29.651008 Set Vref, RX VrefLevel [Byte0]: 28
8553 11:44:29.654203 [Byte1]: 28
8554 11:44:29.658448
8555 11:44:29.658536 Set Vref, RX VrefLevel [Byte0]: 29
8556 11:44:29.661797 [Byte1]: 29
8557 11:44:29.665965
8558 11:44:29.666048 Set Vref, RX VrefLevel [Byte0]: 30
8559 11:44:29.669370 [Byte1]: 30
8560 11:44:29.673371
8561 11:44:29.673454 Set Vref, RX VrefLevel [Byte0]: 31
8562 11:44:29.676874 [Byte1]: 31
8563 11:44:29.681176
8564 11:44:29.681678 Set Vref, RX VrefLevel [Byte0]: 32
8565 11:44:29.684622 [Byte1]: 32
8566 11:44:29.688661
8567 11:44:29.689214 Set Vref, RX VrefLevel [Byte0]: 33
8568 11:44:29.692200 [Byte1]: 33
8569 11:44:29.696714
8570 11:44:29.697273 Set Vref, RX VrefLevel [Byte0]: 34
8571 11:44:29.699573 [Byte1]: 34
8572 11:44:29.704021
8573 11:44:29.704644 Set Vref, RX VrefLevel [Byte0]: 35
8574 11:44:29.707291 [Byte1]: 35
8575 11:44:29.711760
8576 11:44:29.712207 Set Vref, RX VrefLevel [Byte0]: 36
8577 11:44:29.715211 [Byte1]: 36
8578 11:44:29.719190
8579 11:44:29.719613 Set Vref, RX VrefLevel [Byte0]: 37
8580 11:44:29.722467 [Byte1]: 37
8581 11:44:29.726655
8582 11:44:29.727134 Set Vref, RX VrefLevel [Byte0]: 38
8583 11:44:29.730057 [Byte1]: 38
8584 11:44:29.734296
8585 11:44:29.734794 Set Vref, RX VrefLevel [Byte0]: 39
8586 11:44:29.737686 [Byte1]: 39
8587 11:44:29.741924
8588 11:44:29.742344 Set Vref, RX VrefLevel [Byte0]: 40
8589 11:44:29.745238 [Byte1]: 40
8590 11:44:29.749496
8591 11:44:29.749943 Set Vref, RX VrefLevel [Byte0]: 41
8592 11:44:29.752675 [Byte1]: 41
8593 11:44:29.757354
8594 11:44:29.757899 Set Vref, RX VrefLevel [Byte0]: 42
8595 11:44:29.760686 [Byte1]: 42
8596 11:44:29.764523
8597 11:44:29.765100 Set Vref, RX VrefLevel [Byte0]: 43
8598 11:44:29.767795 [Byte1]: 43
8599 11:44:29.772495
8600 11:44:29.772920 Set Vref, RX VrefLevel [Byte0]: 44
8601 11:44:29.775719 [Byte1]: 44
8602 11:44:29.779742
8603 11:44:29.780169 Set Vref, RX VrefLevel [Byte0]: 45
8604 11:44:29.782960 [Byte1]: 45
8605 11:44:29.787542
8606 11:44:29.787972 Set Vref, RX VrefLevel [Byte0]: 46
8607 11:44:29.790770 [Byte1]: 46
8608 11:44:29.795005
8609 11:44:29.795430 Set Vref, RX VrefLevel [Byte0]: 47
8610 11:44:29.798549 [Byte1]: 47
8611 11:44:29.802595
8612 11:44:29.803152 Set Vref, RX VrefLevel [Byte0]: 48
8613 11:44:29.805762 [Byte1]: 48
8614 11:44:29.810080
8615 11:44:29.810501 Set Vref, RX VrefLevel [Byte0]: 49
8616 11:44:29.813236 [Byte1]: 49
8617 11:44:29.818119
8618 11:44:29.818577 Set Vref, RX VrefLevel [Byte0]: 50
8619 11:44:29.821024 [Byte1]: 50
8620 11:44:29.825081
8621 11:44:29.825518 Set Vref, RX VrefLevel [Byte0]: 51
8622 11:44:29.828496 [Byte1]: 51
8623 11:44:29.832636
8624 11:44:29.835953 Set Vref, RX VrefLevel [Byte0]: 52
8625 11:44:29.836382 [Byte1]: 52
8626 11:44:29.840417
8627 11:44:29.840878 Set Vref, RX VrefLevel [Byte0]: 53
8628 11:44:29.844010 [Byte1]: 53
8629 11:44:29.848099
8630 11:44:29.848535 Set Vref, RX VrefLevel [Byte0]: 54
8631 11:44:29.851321 [Byte1]: 54
8632 11:44:29.855272
8633 11:44:29.855708 Set Vref, RX VrefLevel [Byte0]: 55
8634 11:44:29.858651 [Byte1]: 55
8635 11:44:29.863101
8636 11:44:29.863673 Set Vref, RX VrefLevel [Byte0]: 56
8637 11:44:29.866701 [Byte1]: 56
8638 11:44:29.870732
8639 11:44:29.871242 Set Vref, RX VrefLevel [Byte0]: 57
8640 11:44:29.873986 [Byte1]: 57
8641 11:44:29.878282
8642 11:44:29.878829 Set Vref, RX VrefLevel [Byte0]: 58
8643 11:44:29.881470 [Byte1]: 58
8644 11:44:29.885644
8645 11:44:29.886070 Set Vref, RX VrefLevel [Byte0]: 59
8646 11:44:29.889125 [Byte1]: 59
8647 11:44:29.893354
8648 11:44:29.893778 Set Vref, RX VrefLevel [Byte0]: 60
8649 11:44:29.896626 [Byte1]: 60
8650 11:44:29.900905
8651 11:44:29.901420 Set Vref, RX VrefLevel [Byte0]: 61
8652 11:44:29.904175 [Byte1]: 61
8653 11:44:29.908348
8654 11:44:29.908775 Set Vref, RX VrefLevel [Byte0]: 62
8655 11:44:29.911830 [Byte1]: 62
8656 11:44:29.916167
8657 11:44:29.916618 Set Vref, RX VrefLevel [Byte0]: 63
8658 11:44:29.919356 [Byte1]: 63
8659 11:44:29.923748
8660 11:44:29.924323 Set Vref, RX VrefLevel [Byte0]: 64
8661 11:44:29.926856 [Byte1]: 64
8662 11:44:29.931444
8663 11:44:29.932020 Set Vref, RX VrefLevel [Byte0]: 65
8664 11:44:29.934308 [Byte1]: 65
8665 11:44:29.938616
8666 11:44:29.939065 Set Vref, RX VrefLevel [Byte0]: 66
8667 11:44:29.942203 [Byte1]: 66
8668 11:44:29.945968
8669 11:44:29.946291 Set Vref, RX VrefLevel [Byte0]: 67
8670 11:44:29.949547 [Byte1]: 67
8671 11:44:29.953805
8672 11:44:29.953978 Set Vref, RX VrefLevel [Byte0]: 68
8673 11:44:29.956828 [Byte1]: 68
8674 11:44:29.961368
8675 11:44:29.961506 Set Vref, RX VrefLevel [Byte0]: 69
8676 11:44:29.964771 [Byte1]: 69
8677 11:44:29.968816
8678 11:44:29.968961 Set Vref, RX VrefLevel [Byte0]: 70
8679 11:44:29.972080 [Byte1]: 70
8680 11:44:29.976239
8681 11:44:29.976346 Set Vref, RX VrefLevel [Byte0]: 71
8682 11:44:29.979468 [Byte1]: 71
8683 11:44:29.983923
8684 11:44:29.984032 Set Vref, RX VrefLevel [Byte0]: 72
8685 11:44:29.987257 [Byte1]: 72
8686 11:44:29.991414
8687 11:44:29.991516 Set Vref, RX VrefLevel [Byte0]: 73
8688 11:44:29.994944 [Byte1]: 73
8689 11:44:29.999374
8690 11:44:29.999796 Set Vref, RX VrefLevel [Byte0]: 74
8691 11:44:30.002695 [Byte1]: 74
8692 11:44:30.007098
8693 11:44:30.007750 Set Vref, RX VrefLevel [Byte0]: 75
8694 11:44:30.010343 [Byte1]: 75
8695 11:44:30.014468
8696 11:44:30.014921 Final RX Vref Byte 0 = 59 to rank0
8697 11:44:30.017564 Final RX Vref Byte 1 = 62 to rank0
8698 11:44:30.020937 Final RX Vref Byte 0 = 59 to rank1
8699 11:44:30.024202 Final RX Vref Byte 1 = 62 to rank1==
8700 11:44:30.027776 Dram Type= 6, Freq= 0, CH_1, rank 0
8701 11:44:30.034233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 11:44:30.034685 ==
8703 11:44:30.035027 DQS Delay:
8704 11:44:30.037850 DQS0 = 0, DQS1 = 0
8705 11:44:30.038293 DQM Delay:
8706 11:44:30.038709 DQM0 = 134, DQM1 = 130
8707 11:44:30.041033 DQ Delay:
8708 11:44:30.044229 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8709 11:44:30.047495 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8710 11:44:30.050855 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8711 11:44:30.054067 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =138
8712 11:44:30.054606
8713 11:44:30.055125
8714 11:44:30.055620
8715 11:44:30.057279 [DramC_TX_OE_Calibration] TA2
8716 11:44:30.060884 Original DQ_B0 (3 6) =30, OEN = 27
8717 11:44:30.064133 Original DQ_B1 (3 6) =30, OEN = 27
8718 11:44:30.067466 24, 0x0, End_B0=24 End_B1=24
8719 11:44:30.067920 25, 0x0, End_B0=25 End_B1=25
8720 11:44:30.070761 26, 0x0, End_B0=26 End_B1=26
8721 11:44:30.073961 27, 0x0, End_B0=27 End_B1=27
8722 11:44:30.077370 28, 0x0, End_B0=28 End_B1=28
8723 11:44:30.080709 29, 0x0, End_B0=29 End_B1=29
8724 11:44:30.081193 30, 0x0, End_B0=30 End_B1=30
8725 11:44:30.083719 31, 0x4141, End_B0=30 End_B1=30
8726 11:44:30.087051 Byte0 end_step=30 best_step=27
8727 11:44:30.090457 Byte1 end_step=30 best_step=27
8728 11:44:30.094257 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 11:44:30.097248 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 11:44:30.097678
8731 11:44:30.098191
8732 11:44:30.103965 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8733 11:44:30.107259 CH1 RK0: MR19=303, MR18=1927
8734 11:44:30.113950 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8735 11:44:30.114418
8736 11:44:30.117305 ----->DramcWriteLeveling(PI) begin...
8737 11:44:30.117771 ==
8738 11:44:30.120361 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 11:44:30.123926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 11:44:30.124525 ==
8741 11:44:30.127298 Write leveling (Byte 0): 23 => 23
8742 11:44:30.130047 Write leveling (Byte 1): 29 => 29
8743 11:44:30.133578 DramcWriteLeveling(PI) end<-----
8744 11:44:30.134061
8745 11:44:30.134541 ==
8746 11:44:30.136816 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 11:44:30.140014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 11:44:30.143257 ==
8749 11:44:30.143733 [Gating] SW mode calibration
8750 11:44:30.153404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8751 11:44:30.156484 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8752 11:44:30.159898 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 11:44:30.166252 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 11:44:30.169907 1 4 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8755 11:44:30.172799 1 4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 1)
8756 11:44:30.179473 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 11:44:30.182753 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 11:44:30.186241 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 11:44:30.192577 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 11:44:30.195778 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 11:44:30.199274 1 5 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8762 11:44:30.205633 1 5 8 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 0)
8763 11:44:30.209382 1 5 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 0)
8764 11:44:30.219202 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 11:44:30.220266 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 11:44:30.222265 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 11:44:30.225952 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 11:44:30.231951 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 11:44:30.235158 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8770 11:44:30.238711 1 6 8 | B1->B0 | 4545 2424 | 0 0 | (0 0) (0 0)
8771 11:44:30.245059 1 6 12 | B1->B0 | 4646 3939 | 0 0 | (0 0) (0 0)
8772 11:44:30.248156 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 11:44:30.251792 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 11:44:30.258380 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 11:44:30.261571 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 11:44:30.264610 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 11:44:30.271268 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 11:44:30.274541 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8779 11:44:30.277918 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8780 11:44:30.284367 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 11:44:30.287662 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:44:30.291251 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:44:30.297642 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:44:30.300962 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:44:30.304582 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:44:30.310865 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:44:30.314211 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:44:30.317383 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:44:30.324526 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:44:30.327422 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:44:30.330871 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:44:30.337513 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 11:44:30.340607 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 11:44:30.343899 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8795 11:44:30.350627 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8796 11:44:30.354065 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 11:44:30.357241 Total UI for P1: 0, mck2ui 16
8798 11:44:30.360382 best dqsien dly found for B0: ( 1, 9, 10)
8799 11:44:30.363760 Total UI for P1: 0, mck2ui 16
8800 11:44:30.367017 best dqsien dly found for B1: ( 1, 9, 10)
8801 11:44:30.370328 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8802 11:44:30.373685 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8803 11:44:30.373813
8804 11:44:30.376863 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8805 11:44:30.383491 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8806 11:44:30.383618 [Gating] SW calibration Done
8807 11:44:30.383715 ==
8808 11:44:30.386822 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 11:44:30.393377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 11:44:30.393464 ==
8811 11:44:30.393538 RX Vref Scan: 0
8812 11:44:30.393598
8813 11:44:30.396649 RX Vref 0 -> 0, step: 1
8814 11:44:30.396751
8815 11:44:30.399821 RX Delay 0 -> 252, step: 8
8816 11:44:30.403658 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8817 11:44:30.406549 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8818 11:44:30.409927 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8819 11:44:30.413349 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8820 11:44:30.419740 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8821 11:44:30.423052 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8822 11:44:30.426259 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8823 11:44:30.429783 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8824 11:44:30.432894 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8825 11:44:30.439803 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8826 11:44:30.442783 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8827 11:44:30.446467 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8828 11:44:30.449526 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8829 11:44:30.455905 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8830 11:44:30.459264 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8831 11:44:30.462521 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8832 11:44:30.462621 ==
8833 11:44:30.465782 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 11:44:30.469068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 11:44:30.472647 ==
8836 11:44:30.472744 DQS Delay:
8837 11:44:30.472833 DQS0 = 0, DQS1 = 0
8838 11:44:30.475861 DQM Delay:
8839 11:44:30.475965 DQM0 = 136, DQM1 = 131
8840 11:44:30.479073 DQ Delay:
8841 11:44:30.482652 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8842 11:44:30.485685 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8843 11:44:30.488953 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8844 11:44:30.492725 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8845 11:44:30.492808
8846 11:44:30.492873
8847 11:44:30.492934 ==
8848 11:44:30.495780 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 11:44:30.499033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 11:44:30.499154 ==
8851 11:44:30.499246
8852 11:44:30.502254
8853 11:44:30.502325 TX Vref Scan disable
8854 11:44:30.505562 == TX Byte 0 ==
8855 11:44:30.509133 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8856 11:44:30.512395 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8857 11:44:30.515405 == TX Byte 1 ==
8858 11:44:30.518871 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8859 11:44:30.522102 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8860 11:44:30.522185 ==
8861 11:44:30.525262 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 11:44:30.532082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 11:44:30.532200 ==
8864 11:44:30.544315
8865 11:44:30.547499 TX Vref early break, caculate TX vref
8866 11:44:30.550694 TX Vref=16, minBit 9, minWin=22, winSum=383
8867 11:44:30.553892 TX Vref=18, minBit 8, minWin=22, winSum=385
8868 11:44:30.557135 TX Vref=20, minBit 11, minWin=23, winSum=400
8869 11:44:30.560730 TX Vref=22, minBit 11, minWin=23, winSum=404
8870 11:44:30.567193 TX Vref=24, minBit 10, minWin=24, winSum=415
8871 11:44:30.570452 TX Vref=26, minBit 13, minWin=24, winSum=415
8872 11:44:30.573664 TX Vref=28, minBit 15, minWin=24, winSum=413
8873 11:44:30.577285 TX Vref=30, minBit 8, minWin=24, winSum=410
8874 11:44:30.580485 TX Vref=32, minBit 10, minWin=23, winSum=401
8875 11:44:30.583639 TX Vref=34, minBit 8, minWin=23, winSum=391
8876 11:44:30.590494 [TxChooseVref] Worse bit 10, Min win 24, Win sum 415, Final Vref 24
8877 11:44:30.590577
8878 11:44:30.593953 Final TX Range 0 Vref 24
8879 11:44:30.594033
8880 11:44:30.594097 ==
8881 11:44:30.597179 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 11:44:30.600492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 11:44:30.600594 ==
8884 11:44:30.600702
8885 11:44:30.603747
8886 11:44:30.603828 TX Vref Scan disable
8887 11:44:30.610030 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8888 11:44:30.610115 == TX Byte 0 ==
8889 11:44:30.613313 u2DelayCellOfst[0]=13 cells (4 PI)
8890 11:44:30.616856 u2DelayCellOfst[1]=10 cells (3 PI)
8891 11:44:30.619970 u2DelayCellOfst[2]=0 cells (0 PI)
8892 11:44:30.623388 u2DelayCellOfst[3]=3 cells (1 PI)
8893 11:44:30.626819 u2DelayCellOfst[4]=6 cells (2 PI)
8894 11:44:30.630221 u2DelayCellOfst[5]=17 cells (5 PI)
8895 11:44:30.633349 u2DelayCellOfst[6]=17 cells (5 PI)
8896 11:44:30.636869 u2DelayCellOfst[7]=3 cells (1 PI)
8897 11:44:30.639776 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8898 11:44:30.642969 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8899 11:44:30.646533 == TX Byte 1 ==
8900 11:44:30.649921 u2DelayCellOfst[8]=0 cells (0 PI)
8901 11:44:30.653026 u2DelayCellOfst[9]=3 cells (1 PI)
8902 11:44:30.656559 u2DelayCellOfst[10]=6 cells (2 PI)
8903 11:44:30.659681 u2DelayCellOfst[11]=3 cells (1 PI)
8904 11:44:30.659788 u2DelayCellOfst[12]=13 cells (4 PI)
8905 11:44:30.662826 u2DelayCellOfst[13]=13 cells (4 PI)
8906 11:44:30.666056 u2DelayCellOfst[14]=17 cells (5 PI)
8907 11:44:30.669743 u2DelayCellOfst[15]=17 cells (5 PI)
8908 11:44:30.676342 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8909 11:44:30.679497 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8910 11:44:30.679587 DramC Write-DBI on
8911 11:44:30.682713 ==
8912 11:44:30.686201 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 11:44:30.689558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 11:44:30.689641 ==
8915 11:44:30.689713
8916 11:44:30.689776
8917 11:44:30.692562 TX Vref Scan disable
8918 11:44:30.692644 == TX Byte 0 ==
8919 11:44:30.699189 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8920 11:44:30.699270 == TX Byte 1 ==
8921 11:44:30.702477 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8922 11:44:30.705866 DramC Write-DBI off
8923 11:44:30.705939
8924 11:44:30.706002 [DATLAT]
8925 11:44:30.709346 Freq=1600, CH1 RK1
8926 11:44:30.709424
8927 11:44:30.709495 DATLAT Default: 0xf
8928 11:44:30.712378 0, 0xFFFF, sum = 0
8929 11:44:30.712465 1, 0xFFFF, sum = 0
8930 11:44:30.715588 2, 0xFFFF, sum = 0
8931 11:44:30.715661 3, 0xFFFF, sum = 0
8932 11:44:30.719119 4, 0xFFFF, sum = 0
8933 11:44:30.719217 5, 0xFFFF, sum = 0
8934 11:44:30.722319 6, 0xFFFF, sum = 0
8935 11:44:30.725910 7, 0xFFFF, sum = 0
8936 11:44:30.725981 8, 0xFFFF, sum = 0
8937 11:44:30.728862 9, 0xFFFF, sum = 0
8938 11:44:30.728993 10, 0xFFFF, sum = 0
8939 11:44:30.732196 11, 0xFFFF, sum = 0
8940 11:44:30.732271 12, 0xFFFF, sum = 0
8941 11:44:30.735855 13, 0xFFFF, sum = 0
8942 11:44:30.735972 14, 0x0, sum = 1
8943 11:44:30.738985 15, 0x0, sum = 2
8944 11:44:30.739071 16, 0x0, sum = 3
8945 11:44:30.742100 17, 0x0, sum = 4
8946 11:44:30.742211 best_step = 15
8947 11:44:30.742292
8948 11:44:30.742366 ==
8949 11:44:30.745509 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 11:44:30.748983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 11:44:30.752163 ==
8952 11:44:30.752281 RX Vref Scan: 0
8953 11:44:30.752373
8954 11:44:30.755615 RX Vref 0 -> 0, step: 1
8955 11:44:30.755725
8956 11:44:30.755816 RX Delay 19 -> 252, step: 4
8957 11:44:30.762607 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8958 11:44:30.766075 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8959 11:44:30.769467 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8960 11:44:30.772625 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8961 11:44:30.775798 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8962 11:44:30.782742 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8963 11:44:30.785895 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8964 11:44:30.788935 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8965 11:44:30.792552 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8966 11:44:30.795691 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8967 11:44:30.802524 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8968 11:44:30.805727 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8969 11:44:30.808809 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8970 11:44:30.811988 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8971 11:44:30.815547 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8972 11:44:30.822082 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8973 11:44:30.822164 ==
8974 11:44:30.825728 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 11:44:30.828742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 11:44:30.828852 ==
8977 11:44:30.828945 DQS Delay:
8978 11:44:30.832183 DQS0 = 0, DQS1 = 0
8979 11:44:30.832257 DQM Delay:
8980 11:44:30.835522 DQM0 = 133, DQM1 = 129
8981 11:44:30.835621 DQ Delay:
8982 11:44:30.838716 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8983 11:44:30.841751 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8984 11:44:30.845361 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8985 11:44:30.851987 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
8986 11:44:30.852085
8987 11:44:30.852203
8988 11:44:30.852301
8989 11:44:30.852390 [DramC_TX_OE_Calibration] TA2
8990 11:44:30.855195 Original DQ_B0 (3 6) =30, OEN = 27
8991 11:44:30.858711 Original DQ_B1 (3 6) =30, OEN = 27
8992 11:44:30.861934 24, 0x0, End_B0=24 End_B1=24
8993 11:44:30.865114 25, 0x0, End_B0=25 End_B1=25
8994 11:44:30.868584 26, 0x0, End_B0=26 End_B1=26
8995 11:44:30.868670 27, 0x0, End_B0=27 End_B1=27
8996 11:44:30.871888 28, 0x0, End_B0=28 End_B1=28
8997 11:44:30.874812 29, 0x0, End_B0=29 End_B1=29
8998 11:44:30.878326 30, 0x0, End_B0=30 End_B1=30
8999 11:44:30.881502 31, 0x4545, End_B0=30 End_B1=30
9000 11:44:30.884742 Byte0 end_step=30 best_step=27
9001 11:44:30.884838 Byte1 end_step=30 best_step=27
9002 11:44:30.888379 Byte0 TX OE(2T, 0.5T) = (3, 3)
9003 11:44:30.891536 Byte1 TX OE(2T, 0.5T) = (3, 3)
9004 11:44:30.891610
9005 11:44:30.891680
9006 11:44:30.901360 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9007 11:44:30.901445 CH1 RK1: MR19=303, MR18=1D07
9008 11:44:30.907702 CH1_RK1: MR19=0x303, MR18=0x1D07, DQSOSC=395, MR23=63, INC=23, DEC=15
9009 11:44:30.911464 [RxdqsGatingPostProcess] freq 1600
9010 11:44:30.918073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9011 11:44:30.921334 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 11:44:30.924522 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 11:44:30.927769 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 11:44:30.930804 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 11:44:30.934374 best DQS0 dly(2T, 0.5T) = (1, 1)
9016 11:44:30.934457 best DQS1 dly(2T, 0.5T) = (1, 1)
9017 11:44:30.937702 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9018 11:44:30.940859 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9019 11:44:30.943982 Pre-setting of DQS Precalculation
9020 11:44:30.950818 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9021 11:44:30.957554 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9022 11:44:30.963934 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9023 11:44:30.964018
9024 11:44:30.964083
9025 11:44:30.967176 [Calibration Summary] 3200 Mbps
9026 11:44:30.971119 CH 0, Rank 0
9027 11:44:30.971201 SW Impedance : PASS
9028 11:44:30.973802 DUTY Scan : NO K
9029 11:44:30.973885 ZQ Calibration : PASS
9030 11:44:30.977105 Jitter Meter : NO K
9031 11:44:30.980800 CBT Training : PASS
9032 11:44:30.980882 Write leveling : PASS
9033 11:44:30.983720 RX DQS gating : PASS
9034 11:44:30.987158 RX DQ/DQS(RDDQC) : PASS
9035 11:44:30.987241 TX DQ/DQS : PASS
9036 11:44:30.990403 RX DATLAT : PASS
9037 11:44:30.993910 RX DQ/DQS(Engine): PASS
9038 11:44:30.994017 TX OE : PASS
9039 11:44:30.997013 All Pass.
9040 11:44:30.997109
9041 11:44:30.997175 CH 0, Rank 1
9042 11:44:31.000615 SW Impedance : PASS
9043 11:44:31.000697 DUTY Scan : NO K
9044 11:44:31.003928 ZQ Calibration : PASS
9045 11:44:31.007036 Jitter Meter : NO K
9046 11:44:31.007119 CBT Training : PASS
9047 11:44:31.010602 Write leveling : PASS
9048 11:44:31.013850 RX DQS gating : PASS
9049 11:44:31.013977 RX DQ/DQS(RDDQC) : PASS
9050 11:44:31.017168 TX DQ/DQS : PASS
9051 11:44:31.020344 RX DATLAT : PASS
9052 11:44:31.020453 RX DQ/DQS(Engine): PASS
9053 11:44:31.023543 TX OE : PASS
9054 11:44:31.023645 All Pass.
9055 11:44:31.023735
9056 11:44:31.026793 CH 1, Rank 0
9057 11:44:31.026887 SW Impedance : PASS
9058 11:44:31.030198 DUTY Scan : NO K
9059 11:44:31.033310 ZQ Calibration : PASS
9060 11:44:31.033393 Jitter Meter : NO K
9061 11:44:31.036554 CBT Training : PASS
9062 11:44:31.036636 Write leveling : PASS
9063 11:44:31.040048 RX DQS gating : PASS
9064 11:44:31.043092 RX DQ/DQS(RDDQC) : PASS
9065 11:44:31.043191 TX DQ/DQS : PASS
9066 11:44:31.046746 RX DATLAT : PASS
9067 11:44:31.050046 RX DQ/DQS(Engine): PASS
9068 11:44:31.050130 TX OE : PASS
9069 11:44:31.053314 All Pass.
9070 11:44:31.053399
9071 11:44:31.053465 CH 1, Rank 1
9072 11:44:31.056469 SW Impedance : PASS
9073 11:44:31.056553 DUTY Scan : NO K
9074 11:44:31.059630 ZQ Calibration : PASS
9075 11:44:31.063015 Jitter Meter : NO K
9076 11:44:31.063098 CBT Training : PASS
9077 11:44:31.066576 Write leveling : PASS
9078 11:44:31.069782 RX DQS gating : PASS
9079 11:44:31.069865 RX DQ/DQS(RDDQC) : PASS
9080 11:44:31.072859 TX DQ/DQS : PASS
9081 11:44:31.076317 RX DATLAT : PASS
9082 11:44:31.076400 RX DQ/DQS(Engine): PASS
9083 11:44:31.079452 TX OE : PASS
9084 11:44:31.079536 All Pass.
9085 11:44:31.079602
9086 11:44:31.082860 DramC Write-DBI on
9087 11:44:31.086017 PER_BANK_REFRESH: Hybrid Mode
9088 11:44:31.086106 TX_TRACKING: ON
9089 11:44:31.096096 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9090 11:44:31.102793 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9091 11:44:31.109497 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9092 11:44:31.112618 [FAST_K] Save calibration result to emmc
9093 11:44:31.115849 sync common calibartion params.
9094 11:44:31.119212 sync cbt_mode0:1, 1:1
9095 11:44:31.122318 dram_init: ddr_geometry: 2
9096 11:44:31.122450 dram_init: ddr_geometry: 2
9097 11:44:31.125620 dram_init: ddr_geometry: 2
9098 11:44:31.128869 0:dram_rank_size:100000000
9099 11:44:31.132139 1:dram_rank_size:100000000
9100 11:44:31.135910 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9101 11:44:31.139120 DFS_SHUFFLE_HW_MODE: ON
9102 11:44:31.142250 dramc_set_vcore_voltage set vcore to 725000
9103 11:44:31.145738 Read voltage for 1600, 0
9104 11:44:31.145835 Vio18 = 0
9105 11:44:31.145932 Vcore = 725000
9106 11:44:31.149290 Vdram = 0
9107 11:44:31.149397 Vddq = 0
9108 11:44:31.149502 Vmddr = 0
9109 11:44:31.152237 switch to 3200 Mbps bootup
9110 11:44:31.155333 [DramcRunTimeConfig]
9111 11:44:31.155416 PHYPLL
9112 11:44:31.155499 DPM_CONTROL_AFTERK: ON
9113 11:44:31.159074 PER_BANK_REFRESH: ON
9114 11:44:31.162084 REFRESH_OVERHEAD_REDUCTION: ON
9115 11:44:31.165353 CMD_PICG_NEW_MODE: OFF
9116 11:44:31.165448 XRTWTW_NEW_MODE: ON
9117 11:44:31.168832 XRTRTR_NEW_MODE: ON
9118 11:44:31.168935 TX_TRACKING: ON
9119 11:44:31.171979 RDSEL_TRACKING: OFF
9120 11:44:31.172093 DQS Precalculation for DVFS: ON
9121 11:44:31.175649 RX_TRACKING: OFF
9122 11:44:31.175762 HW_GATING DBG: ON
9123 11:44:31.178745 ZQCS_ENABLE_LP4: ON
9124 11:44:31.182081 RX_PICG_NEW_MODE: ON
9125 11:44:31.182170 TX_PICG_NEW_MODE: ON
9126 11:44:31.185249 ENABLE_RX_DCM_DPHY: ON
9127 11:44:31.188527 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9128 11:44:31.188624 DUMMY_READ_FOR_TRACKING: OFF
9129 11:44:31.191771 !!! SPM_CONTROL_AFTERK: OFF
9130 11:44:31.195130 !!! SPM could not control APHY
9131 11:44:31.198381 IMPEDANCE_TRACKING: ON
9132 11:44:31.198494 TEMP_SENSOR: ON
9133 11:44:31.202011 HW_SAVE_FOR_SR: OFF
9134 11:44:31.204963 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9135 11:44:31.208097 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9136 11:44:31.208235 Read ODT Tracking: ON
9137 11:44:31.211701 Refresh Rate DeBounce: ON
9138 11:44:31.214814 DFS_NO_QUEUE_FLUSH: ON
9139 11:44:31.218588 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9140 11:44:31.218764 ENABLE_DFS_RUNTIME_MRW: OFF
9141 11:44:31.221681 DDR_RESERVE_NEW_MODE: ON
9142 11:44:31.224896 MR_CBT_SWITCH_FREQ: ON
9143 11:44:31.225140 =========================
9144 11:44:31.245284 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9145 11:44:31.248493 dram_init: ddr_geometry: 2
9146 11:44:31.266616 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9147 11:44:31.269995 dram_init: dram init end (result: 0)
9148 11:44:31.276557 DRAM-K: Full calibration passed in 24486 msecs
9149 11:44:31.279612 MRC: failed to locate region type 0.
9150 11:44:31.280174 DRAM rank0 size:0x100000000,
9151 11:44:31.283205 DRAM rank1 size=0x100000000
9152 11:44:31.293212 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9153 11:44:31.299657 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9154 11:44:31.306123 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9155 11:44:31.316052 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9156 11:44:31.316469 DRAM rank0 size:0x100000000,
9157 11:44:31.319240 DRAM rank1 size=0x100000000
9158 11:44:31.319666 CBMEM:
9159 11:44:31.322490 IMD: root @ 0xfffff000 254 entries.
9160 11:44:31.325990 IMD: root @ 0xffffec00 62 entries.
9161 11:44:31.329269 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9162 11:44:31.335906 WARNING: RO_VPD is uninitialized or empty.
9163 11:44:31.339076 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9164 11:44:31.347050 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9165 11:44:31.359500 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9166 11:44:31.370748 BS: romstage times (exec / console): total (unknown) / 23986 ms
9167 11:44:31.371337
9168 11:44:31.371902
9169 11:44:31.380641 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9170 11:44:31.384234 ARM64: Exception handlers installed.
9171 11:44:31.387447 ARM64: Testing exception
9172 11:44:31.390898 ARM64: Done test exception
9173 11:44:31.391335 Enumerating buses...
9174 11:44:31.394071 Show all devs... Before device enumeration.
9175 11:44:31.397374 Root Device: enabled 1
9176 11:44:31.400643 CPU_CLUSTER: 0: enabled 1
9177 11:44:31.401113 CPU: 00: enabled 1
9178 11:44:31.403909 Compare with tree...
9179 11:44:31.404400 Root Device: enabled 1
9180 11:44:31.407289 CPU_CLUSTER: 0: enabled 1
9181 11:44:31.410493 CPU: 00: enabled 1
9182 11:44:31.410943 Root Device scanning...
9183 11:44:31.413693 scan_static_bus for Root Device
9184 11:44:31.417276 CPU_CLUSTER: 0 enabled
9185 11:44:31.420350 scan_static_bus for Root Device done
9186 11:44:31.423910 scan_bus: bus Root Device finished in 8 msecs
9187 11:44:31.424348 done
9188 11:44:31.430691 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9189 11:44:31.433522 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9190 11:44:31.440347 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9191 11:44:31.443599 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9192 11:44:31.447127 Allocating resources...
9193 11:44:31.450420 Reading resources...
9194 11:44:31.453622 Root Device read_resources bus 0 link: 0
9195 11:44:31.454106 DRAM rank0 size:0x100000000,
9196 11:44:31.457275 DRAM rank1 size=0x100000000
9197 11:44:31.460326 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9198 11:44:31.463409 CPU: 00 missing read_resources
9199 11:44:31.470375 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9200 11:44:31.473471 Root Device read_resources bus 0 link: 0 done
9201 11:44:31.473909 Done reading resources.
9202 11:44:31.480058 Show resources in subtree (Root Device)...After reading.
9203 11:44:31.483730 Root Device child on link 0 CPU_CLUSTER: 0
9204 11:44:31.486402 CPU_CLUSTER: 0 child on link 0 CPU: 00
9205 11:44:31.496451 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9206 11:44:31.497050 CPU: 00
9207 11:44:31.499691 Root Device assign_resources, bus 0 link: 0
9208 11:44:31.503459 CPU_CLUSTER: 0 missing set_resources
9209 11:44:31.509587 Root Device assign_resources, bus 0 link: 0 done
9210 11:44:31.510275 Done setting resources.
9211 11:44:31.516486 Show resources in subtree (Root Device)...After assigning values.
9212 11:44:31.519622 Root Device child on link 0 CPU_CLUSTER: 0
9213 11:44:31.523349 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 11:44:31.532636 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 11:44:31.533167 CPU: 00
9216 11:44:31.536314 Done allocating resources.
9217 11:44:31.542748 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9218 11:44:31.543324 Enabling resources...
9219 11:44:31.543701 done.
9220 11:44:31.549385 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9221 11:44:31.552785 Initializing devices...
9222 11:44:31.553382 Root Device init
9223 11:44:31.555916 init hardware done!
9224 11:44:31.556479 0x00000018: ctrlr->caps
9225 11:44:31.559445 52.000 MHz: ctrlr->f_max
9226 11:44:31.562193 0.400 MHz: ctrlr->f_min
9227 11:44:31.562672 0x40ff8080: ctrlr->voltages
9228 11:44:31.565404 sclk: 390625
9229 11:44:31.565870 Bus Width = 1
9230 11:44:31.568816 sclk: 390625
9231 11:44:31.569310 Bus Width = 1
9232 11:44:31.571921 Early init status = 3
9233 11:44:31.575630 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9234 11:44:31.579438 in-header: 03 fc 00 00 01 00 00 00
9235 11:44:31.582575 in-data: 00
9236 11:44:31.585655 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9237 11:44:31.591429 in-header: 03 fd 00 00 00 00 00 00
9238 11:44:31.595197 in-data:
9239 11:44:31.598071 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9240 11:44:31.602433 in-header: 03 fc 00 00 01 00 00 00
9241 11:44:31.605726 in-data: 00
9242 11:44:31.608717 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9243 11:44:31.614553 in-header: 03 fd 00 00 00 00 00 00
9244 11:44:31.618142 in-data:
9245 11:44:31.621356 [SSUSB] Setting up USB HOST controller...
9246 11:44:31.624923 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9247 11:44:31.628609 [SSUSB] phy power-on done.
9248 11:44:31.631605 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9249 11:44:31.638266 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9250 11:44:31.641381 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9251 11:44:31.648049 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9252 11:44:31.654696 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9253 11:44:31.661127 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9254 11:44:31.667735 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9255 11:44:31.674259 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9256 11:44:31.677602 SPM: binary array size = 0x9dc
9257 11:44:31.680475 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9258 11:44:31.687393 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9259 11:44:31.693749 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9260 11:44:31.700654 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9261 11:44:31.703918 configure_display: Starting display init
9262 11:44:31.737907 anx7625_power_on_init: Init interface.
9263 11:44:31.741397 anx7625_disable_pd_protocol: Disabled PD feature.
9264 11:44:31.745102 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9265 11:44:31.772482 anx7625_start_dp_work: Secure OCM version=00
9266 11:44:31.775560 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9267 11:44:31.790273 sp_tx_get_edid_block: EDID Block = 1
9268 11:44:31.893517 Extracted contents:
9269 11:44:31.896704 header: 00 ff ff ff ff ff ff 00
9270 11:44:31.899823 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9271 11:44:31.903291 version: 01 04
9272 11:44:31.906353 basic params: 95 1f 11 78 0a
9273 11:44:31.909516 chroma info: 76 90 94 55 54 90 27 21 50 54
9274 11:44:31.912820 established: 00 00 00
9275 11:44:31.919625 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9276 11:44:31.922888 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9277 11:44:31.929516 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9278 11:44:31.936175 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9279 11:44:31.942374 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9280 11:44:31.945761 extensions: 00
9281 11:44:31.946223 checksum: fb
9282 11:44:31.946618
9283 11:44:31.948871 Manufacturer: IVO Model 57d Serial Number 0
9284 11:44:31.952372 Made week 0 of 2020
9285 11:44:31.955518 EDID version: 1.4
9286 11:44:31.955980 Digital display
9287 11:44:31.959248 6 bits per primary color channel
9288 11:44:31.959718 DisplayPort interface
9289 11:44:31.962445 Maximum image size: 31 cm x 17 cm
9290 11:44:31.965922 Gamma: 220%
9291 11:44:31.966480 Check DPMS levels
9292 11:44:31.968943 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9293 11:44:31.975773 First detailed timing is preferred timing
9294 11:44:31.976230 Established timings supported:
9295 11:44:31.979033 Standard timings supported:
9296 11:44:31.982401 Detailed timings
9297 11:44:31.985596 Hex of detail: 383680a07038204018303c0035ae10000019
9298 11:44:31.992363 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9299 11:44:31.995473 0780 0798 07c8 0820 hborder 0
9300 11:44:31.998615 0438 043b 0447 0458 vborder 0
9301 11:44:32.002087 -hsync -vsync
9302 11:44:32.002473 Did detailed timing
9303 11:44:32.008530 Hex of detail: 000000000000000000000000000000000000
9304 11:44:32.011924 Manufacturer-specified data, tag 0
9305 11:44:32.015235 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9306 11:44:32.018280 ASCII string: InfoVision
9307 11:44:32.021510 Hex of detail: 000000fe00523134304e574635205248200a
9308 11:44:32.025138 ASCII string: R140NWF5 RH
9309 11:44:32.025426 Checksum
9310 11:44:32.028330 Checksum: 0xfb (valid)
9311 11:44:32.031539 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9312 11:44:32.035089 DSI data_rate: 832800000 bps
9313 11:44:32.041670 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9314 11:44:32.045495 anx7625_parse_edid: pixelclock(138800).
9315 11:44:32.048373 hactive(1920), hsync(48), hfp(24), hbp(88)
9316 11:44:32.052002 vactive(1080), vsync(12), vfp(3), vbp(17)
9317 11:44:32.055010 anx7625_dsi_config: config dsi.
9318 11:44:32.061660 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9319 11:44:32.075161 anx7625_dsi_config: success to config DSI
9320 11:44:32.078168 anx7625_dp_start: MIPI phy setup OK.
9321 11:44:32.081506 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9322 11:44:32.084819 mtk_ddp_mode_set invalid vrefresh 60
9323 11:44:32.088135 main_disp_path_setup
9324 11:44:32.088586 ovl_layer_smi_id_en
9325 11:44:32.091701 ovl_layer_smi_id_en
9326 11:44:32.092155 ccorr_config
9327 11:44:32.092513 aal_config
9328 11:44:32.094940 gamma_config
9329 11:44:32.095394 postmask_config
9330 11:44:32.098083 dither_config
9331 11:44:32.101402 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9332 11:44:32.107966 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9333 11:44:32.111093 Root Device init finished in 555 msecs
9334 11:44:32.114563 CPU_CLUSTER: 0 init
9335 11:44:32.121384 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9336 11:44:32.128045 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9337 11:44:32.128497 APU_MBOX 0x190000b0 = 0x10001
9338 11:44:32.131246 APU_MBOX 0x190001b0 = 0x10001
9339 11:44:32.134584 APU_MBOX 0x190005b0 = 0x10001
9340 11:44:32.138543 APU_MBOX 0x190006b0 = 0x10001
9341 11:44:32.144806 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9342 11:44:32.154203 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9343 11:44:32.166900 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9344 11:44:32.173032 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9345 11:44:32.184710 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9346 11:44:32.194116 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9347 11:44:32.197303 CPU_CLUSTER: 0 init finished in 81 msecs
9348 11:44:32.200455 Devices initialized
9349 11:44:32.203879 Show all devs... After init.
9350 11:44:32.204330 Root Device: enabled 1
9351 11:44:32.207059 CPU_CLUSTER: 0: enabled 1
9352 11:44:32.210249 CPU: 00: enabled 1
9353 11:44:32.213506 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9354 11:44:32.216641 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9355 11:44:32.220876 ELOG: NV offset 0x57f000 size 0x1000
9356 11:44:32.227405 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9357 11:44:32.233748 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9358 11:44:32.237079 ELOG: Event(17) added with size 13 at 2023-06-15 11:44:27 UTC
9359 11:44:32.243783 out: cmd=0x121: 03 db 21 01 00 00 00 00
9360 11:44:32.246841 in-header: 03 3c 00 00 2c 00 00 00
9361 11:44:32.257049 in-data: 23 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9362 11:44:32.263344 ELOG: Event(A1) added with size 10 at 2023-06-15 11:44:27 UTC
9363 11:44:32.269898 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9364 11:44:32.276738 ELOG: Event(A0) added with size 9 at 2023-06-15 11:44:27 UTC
9365 11:44:32.279903 elog_add_boot_reason: Logged dev mode boot
9366 11:44:32.286532 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9367 11:44:32.287085 Finalize devices...
9368 11:44:32.289691 Devices finalized
9369 11:44:32.293420 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9370 11:44:32.296381 Writing coreboot table at 0xffe64000
9371 11:44:32.300121 0. 000000000010a000-0000000000113fff: RAMSTAGE
9372 11:44:32.303414 1. 0000000040000000-00000000400fffff: RAM
9373 11:44:32.309673 2. 0000000040100000-000000004032afff: RAMSTAGE
9374 11:44:32.312659 3. 000000004032b000-00000000545fffff: RAM
9375 11:44:32.316158 4. 0000000054600000-000000005465ffff: BL31
9376 11:44:32.319264 5. 0000000054660000-00000000ffe63fff: RAM
9377 11:44:32.326378 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9378 11:44:32.329500 7. 0000000100000000-000000023fffffff: RAM
9379 11:44:32.332734 Passing 5 GPIOs to payload:
9380 11:44:32.335982 NAME | PORT | POLARITY | VALUE
9381 11:44:32.343055 EC in RW | 0x000000aa | low | undefined
9382 11:44:32.346221 EC interrupt | 0x00000005 | low | undefined
9383 11:44:32.349278 TPM interrupt | 0x000000ab | high | undefined
9384 11:44:32.356392 SD card detect | 0x00000011 | high | undefined
9385 11:44:32.359344 speaker enable | 0x00000093 | high | undefined
9386 11:44:32.362350 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9387 11:44:32.366078 in-header: 03 f9 00 00 02 00 00 00
9388 11:44:32.369153 in-data: 02 00
9389 11:44:32.372583 ADC[4]: Raw value=901401 ID=7
9390 11:44:32.373347 ADC[3]: Raw value=213179 ID=1
9391 11:44:32.375514 RAM Code: 0x71
9392 11:44:32.378524 ADC[6]: Raw value=74502 ID=0
9393 11:44:32.378637 ADC[5]: Raw value=212072 ID=1
9394 11:44:32.382149 SKU Code: 0x1
9395 11:44:32.385388 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bb3
9396 11:44:32.388774 coreboot table: 964 bytes.
9397 11:44:32.391881 IMD ROOT 0. 0xfffff000 0x00001000
9398 11:44:32.395256 IMD SMALL 1. 0xffffe000 0x00001000
9399 11:44:32.398556 RO MCACHE 2. 0xffffc000 0x00001104
9400 11:44:32.401863 CONSOLE 3. 0xfff7c000 0x00080000
9401 11:44:32.404959 FMAP 4. 0xfff7b000 0x00000452
9402 11:44:32.408211 TIME STAMP 5. 0xfff7a000 0x00000910
9403 11:44:32.411748 VBOOT WORK 6. 0xfff66000 0x00014000
9404 11:44:32.414958 RAMOOPS 7. 0xffe66000 0x00100000
9405 11:44:32.418631 COREBOOT 8. 0xffe64000 0x00002000
9406 11:44:32.421869 IMD small region:
9407 11:44:32.424947 IMD ROOT 0. 0xffffec00 0x00000400
9408 11:44:32.428241 VPD 1. 0xffffeba0 0x0000004c
9409 11:44:32.431737 MMC STATUS 2. 0xffffeb80 0x00000004
9410 11:44:32.434828 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9411 11:44:32.438344 Probing TPM: done!
9412 11:44:32.441507 Connected to device vid:did:rid of 1ae0:0028:00
9413 11:44:32.452651 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9414 11:44:32.455883 Initialized TPM device CR50 revision 0
9415 11:44:32.459629 Checking cr50 for pending updates
9416 11:44:32.463253 Reading cr50 TPM mode
9417 11:44:32.472083 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9418 11:44:32.478503 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9419 11:44:32.518515 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9420 11:44:32.522124 Checking segment from ROM address 0x40100000
9421 11:44:32.525243 Checking segment from ROM address 0x4010001c
9422 11:44:32.532202 Loading segment from ROM address 0x40100000
9423 11:44:32.532793 code (compression=0)
9424 11:44:32.538633 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9425 11:44:32.548376 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9426 11:44:32.548936 it's not compressed!
9427 11:44:32.555279 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9428 11:44:32.561933 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9429 11:44:32.579018 Loading segment from ROM address 0x4010001c
9430 11:44:32.579447 Entry Point 0x80000000
9431 11:44:32.582246 Loaded segments
9432 11:44:32.585356 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9433 11:44:32.592140 Jumping to boot code at 0x80000000(0xffe64000)
9434 11:44:32.598833 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9435 11:44:32.605568 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9436 11:44:32.613428 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9437 11:44:32.616820 Checking segment from ROM address 0x40100000
9438 11:44:32.620371 Checking segment from ROM address 0x4010001c
9439 11:44:32.626620 Loading segment from ROM address 0x40100000
9440 11:44:32.627048 code (compression=1)
9441 11:44:32.633273 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9442 11:44:32.643369 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9443 11:44:32.643928 using LZMA
9444 11:44:32.651777 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9445 11:44:32.658624 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9446 11:44:32.661729 Loading segment from ROM address 0x4010001c
9447 11:44:32.662158 Entry Point 0x54601000
9448 11:44:32.665372 Loaded segments
9449 11:44:32.668668 NOTICE: MT8192 bl31_setup
9450 11:44:32.675530 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9451 11:44:32.679091 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9452 11:44:32.682361 WARNING: region 0:
9453 11:44:32.685407 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 11:44:32.685968 WARNING: region 1:
9455 11:44:32.692131 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9456 11:44:32.695602 WARNING: region 2:
9457 11:44:32.698748 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9458 11:44:32.702057 WARNING: region 3:
9459 11:44:32.705575 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 11:44:32.708863 WARNING: region 4:
9461 11:44:32.715301 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 11:44:32.715750 WARNING: region 5:
9463 11:44:32.718624 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 11:44:32.721872 WARNING: region 6:
9465 11:44:32.725622 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 11:44:32.728827 WARNING: region 7:
9467 11:44:32.731815 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 11:44:32.738701 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9469 11:44:32.741994 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9470 11:44:32.745483 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9471 11:44:32.752446 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9472 11:44:32.755363 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9473 11:44:32.758938 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9474 11:44:32.765588 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9475 11:44:32.768728 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9476 11:44:32.775763 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9477 11:44:32.778842 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9478 11:44:32.781949 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9479 11:44:32.789116 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9480 11:44:32.792267 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9481 11:44:32.795800 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9482 11:44:32.802371 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9483 11:44:32.805576 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9484 11:44:32.812257 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9485 11:44:32.815160 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9486 11:44:32.818656 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9487 11:44:32.825689 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9488 11:44:32.828800 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9489 11:44:32.832120 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9490 11:44:32.839004 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9491 11:44:32.842208 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9492 11:44:32.848918 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9493 11:44:32.851779 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9494 11:44:32.858578 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9495 11:44:32.861908 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9496 11:44:32.864941 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9497 11:44:32.871794 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9498 11:44:32.874897 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9499 11:44:32.878405 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9500 11:44:32.884942 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9501 11:44:32.888174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9502 11:44:32.891586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9503 11:44:32.894971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9504 11:44:32.901477 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9505 11:44:32.904755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9506 11:44:32.907903 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9507 11:44:32.911444 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9508 11:44:32.918216 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9509 11:44:32.921498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9510 11:44:32.924607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9511 11:44:32.931759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9512 11:44:32.934762 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9513 11:44:32.937929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9514 11:44:32.941610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9515 11:44:32.948093 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9516 11:44:32.951603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9517 11:44:32.955002 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9518 11:44:32.961278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9519 11:44:32.964951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9520 11:44:32.971649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9521 11:44:32.974699 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9522 11:44:32.981560 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9523 11:44:32.984678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9524 11:44:32.987912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9525 11:44:32.994553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9526 11:44:32.998090 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9527 11:44:33.004825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9528 11:44:33.007643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9529 11:44:33.014415 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9530 11:44:33.017584 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9531 11:44:33.024475 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9532 11:44:33.027868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9533 11:44:33.031043 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9534 11:44:33.038071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9535 11:44:33.041124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9536 11:44:33.047969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9537 11:44:33.051181 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9538 11:44:33.057695 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9539 11:44:33.061135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9540 11:44:33.064720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9541 11:44:33.071269 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9542 11:44:33.074323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9543 11:44:33.080702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9544 11:44:33.084265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9545 11:44:33.091107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9546 11:44:33.094631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9547 11:44:33.101132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9548 11:44:33.104437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9549 11:44:33.107419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9550 11:44:33.114008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9551 11:44:33.117734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9552 11:44:33.124558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9553 11:44:33.127718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9554 11:44:33.134107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9555 11:44:33.137327 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9556 11:44:33.140630 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9557 11:44:33.147470 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9558 11:44:33.151004 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9559 11:44:33.157655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9560 11:44:33.160824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9561 11:44:33.167194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9562 11:44:33.170469 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9563 11:44:33.177305 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9564 11:44:33.180408 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9565 11:44:33.183851 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9566 11:44:33.187377 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9567 11:44:33.193833 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9568 11:44:33.197441 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9569 11:44:33.200584 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9570 11:44:33.206934 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9571 11:44:33.210513 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9572 11:44:33.216727 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9573 11:44:33.219892 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9574 11:44:33.223339 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9575 11:44:33.230090 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9576 11:44:33.233364 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9577 11:44:33.239652 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9578 11:44:33.243309 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9579 11:44:33.247094 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9580 11:44:33.253645 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9581 11:44:33.256973 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9582 11:44:33.263265 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9583 11:44:33.266736 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9584 11:44:33.269935 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9585 11:44:33.273096 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9586 11:44:33.279838 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9587 11:44:33.283702 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9588 11:44:33.286972 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9589 11:44:33.289991 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9590 11:44:33.296683 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9591 11:44:33.300238 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9592 11:44:33.303418 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9593 11:44:33.309840 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9594 11:44:33.313499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9595 11:44:33.319623 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9596 11:44:33.323231 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9597 11:44:33.326121 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9598 11:44:33.333051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9599 11:44:33.336375 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9600 11:44:33.343043 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9601 11:44:33.346475 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9602 11:44:33.349444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9603 11:44:33.356146 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9604 11:44:33.359551 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9605 11:44:33.363141 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9606 11:44:33.369394 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9607 11:44:33.373190 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9608 11:44:33.379567 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9609 11:44:33.382612 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9610 11:44:33.386451 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9611 11:44:33.392973 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9612 11:44:33.396048 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9613 11:44:33.402597 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9614 11:44:33.405678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9615 11:44:33.409382 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9616 11:44:33.415829 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9617 11:44:33.419248 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9618 11:44:33.426005 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9619 11:44:33.429271 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9620 11:44:33.432521 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9621 11:44:33.439226 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9622 11:44:33.442588 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9623 11:44:33.449367 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9624 11:44:33.452454 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9625 11:44:33.455915 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9626 11:44:33.462631 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9627 11:44:33.465558 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9628 11:44:33.469268 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9629 11:44:33.475584 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9630 11:44:33.478976 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9631 11:44:33.485288 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9632 11:44:33.489029 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9633 11:44:33.492105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9634 11:44:33.499192 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9635 11:44:33.502333 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9636 11:44:33.508539 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9637 11:44:33.512098 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9638 11:44:33.518331 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9639 11:44:33.521948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9640 11:44:33.525116 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9641 11:44:33.531870 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9642 11:44:33.535131 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9643 11:44:33.538318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9644 11:44:33.545209 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9645 11:44:33.548544 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9646 11:44:33.555317 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9647 11:44:33.558249 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9648 11:44:33.561295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9649 11:44:33.567808 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9650 11:44:33.571403 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9651 11:44:33.577737 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9652 11:44:33.581400 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9653 11:44:33.584702 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9654 11:44:33.591271 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9655 11:44:33.594539 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9656 11:44:33.601190 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9657 11:44:33.604757 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9658 11:44:33.611306 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9659 11:44:33.614251 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9660 11:44:33.617871 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9661 11:44:33.624479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9662 11:44:33.627461 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9663 11:44:33.634434 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9664 11:44:33.637421 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9665 11:44:33.641158 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9666 11:44:33.647680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9667 11:44:33.651245 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9668 11:44:33.657314 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9669 11:44:33.660486 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9670 11:44:33.667346 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9671 11:44:33.670462 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9672 11:44:33.674009 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9673 11:44:33.680763 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9674 11:44:33.684129 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9675 11:44:33.690563 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9676 11:44:33.693777 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9677 11:44:33.700747 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9678 11:44:33.703833 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9679 11:44:33.707206 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9680 11:44:33.713717 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9681 11:44:33.716853 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9682 11:44:33.723567 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9683 11:44:33.726780 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9684 11:44:33.729913 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9685 11:44:33.736658 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9686 11:44:33.740413 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9687 11:44:33.746724 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9688 11:44:33.749649 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9689 11:44:33.756484 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9690 11:44:33.759821 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9691 11:44:33.763036 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9692 11:44:33.769938 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9693 11:44:33.773211 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9694 11:44:33.779467 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9695 11:44:33.782846 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9696 11:44:33.789445 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9697 11:44:33.792611 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9698 11:44:33.796214 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9699 11:44:33.799502 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9700 11:44:33.805826 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9701 11:44:33.809026 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9702 11:44:33.812501 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9703 11:44:33.819306 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9704 11:44:33.822304 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9705 11:44:33.825431 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9706 11:44:33.832421 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9707 11:44:33.835617 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9708 11:44:33.839047 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9709 11:44:33.845685 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9710 11:44:33.849124 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9711 11:44:33.852282 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9712 11:44:33.858699 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9713 11:44:33.861650 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9714 11:44:33.868675 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9715 11:44:33.872113 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9716 11:44:33.875032 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9717 11:44:33.881597 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9718 11:44:33.885423 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9719 11:44:33.891763 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9720 11:44:33.895248 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9721 11:44:33.898641 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9722 11:44:33.904810 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9723 11:44:33.908431 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9724 11:44:33.912006 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9725 11:44:33.918008 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9726 11:44:33.921227 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9727 11:44:33.924851 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9728 11:44:33.931556 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9729 11:44:33.935208 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9730 11:44:33.941337 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9731 11:44:33.944560 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9732 11:44:33.948437 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9733 11:44:33.954814 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9734 11:44:33.957942 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9735 11:44:33.964402 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9736 11:44:33.967973 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9737 11:44:33.971331 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9738 11:44:33.974465 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9739 11:44:33.977814 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9740 11:44:33.984514 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9741 11:44:33.987604 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9742 11:44:33.990897 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9743 11:44:33.994118 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9744 11:44:34.001194 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9745 11:44:34.004173 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9746 11:44:34.007649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9747 11:44:34.010559 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9748 11:44:34.017546 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9749 11:44:34.020721 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9750 11:44:34.023882 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9751 11:44:34.030709 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9752 11:44:34.034026 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9753 11:44:34.041131 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9754 11:44:34.044254 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9755 11:44:34.050733 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9756 11:44:34.054053 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9757 11:44:34.057418 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9758 11:44:34.064317 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9759 11:44:34.067345 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9760 11:44:34.073656 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9761 11:44:34.076852 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9762 11:44:34.080810 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9763 11:44:34.086983 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9764 11:44:34.089876 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9765 11:44:34.096826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9766 11:44:34.100223 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9767 11:44:34.103570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9768 11:44:34.110269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9769 11:44:34.113398 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9770 11:44:34.119789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9771 11:44:34.123219 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9772 11:44:34.129642 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9773 11:44:34.133155 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9774 11:44:34.136432 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9775 11:44:34.142709 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9776 11:44:34.145899 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9777 11:44:34.152623 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9778 11:44:34.156127 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9779 11:44:34.162772 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9780 11:44:34.165887 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9781 11:44:34.169004 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9782 11:44:34.175977 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9783 11:44:34.179132 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9784 11:44:34.185677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9785 11:44:34.189426 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9786 11:44:34.192719 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9787 11:44:34.199630 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9788 11:44:34.202764 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9789 11:44:34.209156 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9790 11:44:34.212826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9791 11:44:34.216045 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9792 11:44:34.222257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9793 11:44:34.225759 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9794 11:44:34.232088 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9795 11:44:34.235862 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9796 11:44:34.242148 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9797 11:44:34.245314 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9798 11:44:34.248415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9799 11:44:34.254918 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9800 11:44:34.258340 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9801 11:44:34.265461 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9802 11:44:34.268482 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9803 11:44:34.275465 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9804 11:44:34.278545 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9805 11:44:34.281578 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9806 11:44:34.288381 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9807 11:44:34.291518 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9808 11:44:34.298171 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9809 11:44:34.301122 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9810 11:44:34.304919 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9811 11:44:34.311839 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9812 11:44:34.314906 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9813 11:44:34.321345 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9814 11:44:34.324426 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9815 11:44:34.327670 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9816 11:44:34.334293 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9817 11:44:34.337424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9818 11:44:34.344161 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9819 11:44:34.347371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9820 11:44:34.354464 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9821 11:44:34.357513 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9822 11:44:34.360783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9823 11:44:34.367377 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9824 11:44:34.371067 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9825 11:44:34.377321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9826 11:44:34.380784 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9827 11:44:34.387255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9828 11:44:34.390517 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9829 11:44:34.393993 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9830 11:44:34.400594 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9831 11:44:34.403994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9832 11:44:34.410660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9833 11:44:34.414104 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9834 11:44:34.420289 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9835 11:44:34.423603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9836 11:44:34.430456 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9837 11:44:34.434058 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9838 11:44:34.437139 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9839 11:44:34.443947 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9840 11:44:34.447035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9841 11:44:34.453716 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9842 11:44:34.456915 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9843 11:44:34.464000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9844 11:44:34.466804 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9845 11:44:34.470613 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9846 11:44:34.476741 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9847 11:44:34.480024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9848 11:44:34.487108 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9849 11:44:34.490156 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9850 11:44:34.496328 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9851 11:44:34.499725 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9852 11:44:34.506645 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9853 11:44:34.509864 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9854 11:44:34.513357 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9855 11:44:34.519606 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9856 11:44:34.522823 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9857 11:44:34.529456 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9858 11:44:34.533050 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9859 11:44:34.539601 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9860 11:44:34.542994 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9861 11:44:34.549197 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9862 11:44:34.552627 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9863 11:44:34.556089 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9864 11:44:34.562538 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9865 11:44:34.565815 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9866 11:44:34.572514 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9867 11:44:34.575614 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9868 11:44:34.582080 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9869 11:44:34.585428 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9870 11:44:34.588593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9871 11:44:34.595377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9872 11:44:34.598885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9873 11:44:34.605312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9874 11:44:34.608567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9875 11:44:34.615257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9876 11:44:34.618450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9877 11:44:34.625253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9878 11:44:34.628536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9879 11:44:34.635087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9880 11:44:34.638533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9881 11:44:34.644784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9882 11:44:34.647994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9883 11:44:34.654971 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9884 11:44:34.658102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9885 11:44:34.664600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9886 11:44:34.667862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9887 11:44:34.674383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9888 11:44:34.677957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9889 11:44:34.684248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9890 11:44:34.687602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9891 11:44:34.694120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9892 11:44:34.697430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9893 11:44:34.704341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9894 11:44:34.707546 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9895 11:44:34.714246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9896 11:44:34.717319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9897 11:44:34.723822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9898 11:44:34.727524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9899 11:44:34.733776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9900 11:44:34.737174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9901 11:44:34.744167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9902 11:44:34.747062 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9903 11:44:34.750683 INFO: [APUAPC] vio 0
9904 11:44:34.754173 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9905 11:44:34.760520 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9906 11:44:34.763841 INFO: [APUAPC] D0_APC_0: 0x400510
9907 11:44:34.764416 INFO: [APUAPC] D0_APC_1: 0x0
9908 11:44:34.767221 INFO: [APUAPC] D0_APC_2: 0x1540
9909 11:44:34.770840 INFO: [APUAPC] D0_APC_3: 0x0
9910 11:44:34.773770 INFO: [APUAPC] D1_APC_0: 0xffffffff
9911 11:44:34.777041 INFO: [APUAPC] D1_APC_1: 0xffffffff
9912 11:44:34.780177 INFO: [APUAPC] D1_APC_2: 0x3fffff
9913 11:44:34.783592 INFO: [APUAPC] D1_APC_3: 0x0
9914 11:44:34.786654 INFO: [APUAPC] D2_APC_0: 0xffffffff
9915 11:44:34.789949 INFO: [APUAPC] D2_APC_1: 0xffffffff
9916 11:44:34.793068 INFO: [APUAPC] D2_APC_2: 0x3fffff
9917 11:44:34.796441 INFO: [APUAPC] D2_APC_3: 0x0
9918 11:44:34.799888 INFO: [APUAPC] D3_APC_0: 0xffffffff
9919 11:44:34.803201 INFO: [APUAPC] D3_APC_1: 0xffffffff
9920 11:44:34.806372 INFO: [APUAPC] D3_APC_2: 0x3fffff
9921 11:44:34.809557 INFO: [APUAPC] D3_APC_3: 0x0
9922 11:44:34.813358 INFO: [APUAPC] D4_APC_0: 0xffffffff
9923 11:44:34.816321 INFO: [APUAPC] D4_APC_1: 0xffffffff
9924 11:44:34.819606 INFO: [APUAPC] D4_APC_2: 0x3fffff
9925 11:44:34.822953 INFO: [APUAPC] D4_APC_3: 0x0
9926 11:44:34.826076 INFO: [APUAPC] D5_APC_0: 0xffffffff
9927 11:44:34.829303 INFO: [APUAPC] D5_APC_1: 0xffffffff
9928 11:44:34.832885 INFO: [APUAPC] D5_APC_2: 0x3fffff
9929 11:44:34.836195 INFO: [APUAPC] D5_APC_3: 0x0
9930 11:44:34.839368 INFO: [APUAPC] D6_APC_0: 0xffffffff
9931 11:44:34.842966 INFO: [APUAPC] D6_APC_1: 0xffffffff
9932 11:44:34.845822 INFO: [APUAPC] D6_APC_2: 0x3fffff
9933 11:44:34.849029 INFO: [APUAPC] D6_APC_3: 0x0
9934 11:44:34.852470 INFO: [APUAPC] D7_APC_0: 0xffffffff
9935 11:44:34.855979 INFO: [APUAPC] D7_APC_1: 0xffffffff
9936 11:44:34.858983 INFO: [APUAPC] D7_APC_2: 0x3fffff
9937 11:44:34.862788 INFO: [APUAPC] D7_APC_3: 0x0
9938 11:44:34.865776 INFO: [APUAPC] D8_APC_0: 0xffffffff
9939 11:44:34.868925 INFO: [APUAPC] D8_APC_1: 0xffffffff
9940 11:44:34.872822 INFO: [APUAPC] D8_APC_2: 0x3fffff
9941 11:44:34.875754 INFO: [APUAPC] D8_APC_3: 0x0
9942 11:44:34.879087 INFO: [APUAPC] D9_APC_0: 0xffffffff
9943 11:44:34.882520 INFO: [APUAPC] D9_APC_1: 0xffffffff
9944 11:44:34.885605 INFO: [APUAPC] D9_APC_2: 0x3fffff
9945 11:44:34.889201 INFO: [APUAPC] D9_APC_3: 0x0
9946 11:44:34.892620 INFO: [APUAPC] D10_APC_0: 0xffffffff
9947 11:44:34.895545 INFO: [APUAPC] D10_APC_1: 0xffffffff
9948 11:44:34.899058 INFO: [APUAPC] D10_APC_2: 0x3fffff
9949 11:44:34.902284 INFO: [APUAPC] D10_APC_3: 0x0
9950 11:44:34.905501 INFO: [APUAPC] D11_APC_0: 0xffffffff
9951 11:44:34.908710 INFO: [APUAPC] D11_APC_1: 0xffffffff
9952 11:44:34.911741 INFO: [APUAPC] D11_APC_2: 0x3fffff
9953 11:44:34.915151 INFO: [APUAPC] D11_APC_3: 0x0
9954 11:44:34.918749 INFO: [APUAPC] D12_APC_0: 0xffffffff
9955 11:44:34.922025 INFO: [APUAPC] D12_APC_1: 0xffffffff
9956 11:44:34.925040 INFO: [APUAPC] D12_APC_2: 0x3fffff
9957 11:44:34.928629 INFO: [APUAPC] D12_APC_3: 0x0
9958 11:44:34.931751 INFO: [APUAPC] D13_APC_0: 0xffffffff
9959 11:44:34.934994 INFO: [APUAPC] D13_APC_1: 0xffffffff
9960 11:44:34.938531 INFO: [APUAPC] D13_APC_2: 0x3fffff
9961 11:44:34.941623 INFO: [APUAPC] D13_APC_3: 0x0
9962 11:44:34.945054 INFO: [APUAPC] D14_APC_0: 0xffffffff
9963 11:44:34.948255 INFO: [APUAPC] D14_APC_1: 0xffffffff
9964 11:44:34.951468 INFO: [APUAPC] D14_APC_2: 0x3fffff
9965 11:44:34.954983 INFO: [APUAPC] D14_APC_3: 0x0
9966 11:44:34.958171 INFO: [APUAPC] D15_APC_0: 0xffffffff
9967 11:44:34.961391 INFO: [APUAPC] D15_APC_1: 0xffffffff
9968 11:44:34.964713 INFO: [APUAPC] D15_APC_2: 0x3fffff
9969 11:44:34.967909 INFO: [APUAPC] D15_APC_3: 0x0
9970 11:44:34.971496 INFO: [APUAPC] APC_CON: 0x4
9971 11:44:34.974654 INFO: [NOCDAPC] D0_APC_0: 0x0
9972 11:44:34.977762 INFO: [NOCDAPC] D0_APC_1: 0x0
9973 11:44:34.981152 INFO: [NOCDAPC] D1_APC_0: 0x0
9974 11:44:34.984276 INFO: [NOCDAPC] D1_APC_1: 0xfff
9975 11:44:34.987706 INFO: [NOCDAPC] D2_APC_0: 0x0
9976 11:44:34.988226 INFO: [NOCDAPC] D2_APC_1: 0xfff
9977 11:44:34.991117 INFO: [NOCDAPC] D3_APC_0: 0x0
9978 11:44:34.994194 INFO: [NOCDAPC] D3_APC_1: 0xfff
9979 11:44:34.997612 INFO: [NOCDAPC] D4_APC_0: 0x0
9980 11:44:35.000972 INFO: [NOCDAPC] D4_APC_1: 0xfff
9981 11:44:35.004354 INFO: [NOCDAPC] D5_APC_0: 0x0
9982 11:44:35.007390 INFO: [NOCDAPC] D5_APC_1: 0xfff
9983 11:44:35.010423 INFO: [NOCDAPC] D6_APC_0: 0x0
9984 11:44:35.014191 INFO: [NOCDAPC] D6_APC_1: 0xfff
9985 11:44:35.017388 INFO: [NOCDAPC] D7_APC_0: 0x0
9986 11:44:35.020576 INFO: [NOCDAPC] D7_APC_1: 0xfff
9987 11:44:35.023668 INFO: [NOCDAPC] D8_APC_0: 0x0
9988 11:44:35.024129 INFO: [NOCDAPC] D8_APC_1: 0xfff
9989 11:44:35.027387 INFO: [NOCDAPC] D9_APC_0: 0x0
9990 11:44:35.030218 INFO: [NOCDAPC] D9_APC_1: 0xfff
9991 11:44:35.033573 INFO: [NOCDAPC] D10_APC_0: 0x0
9992 11:44:35.037222 INFO: [NOCDAPC] D10_APC_1: 0xfff
9993 11:44:35.040331 INFO: [NOCDAPC] D11_APC_0: 0x0
9994 11:44:35.043533 INFO: [NOCDAPC] D11_APC_1: 0xfff
9995 11:44:35.046981 INFO: [NOCDAPC] D12_APC_0: 0x0
9996 11:44:35.050478 INFO: [NOCDAPC] D12_APC_1: 0xfff
9997 11:44:35.053375 INFO: [NOCDAPC] D13_APC_0: 0x0
9998 11:44:35.056587 INFO: [NOCDAPC] D13_APC_1: 0xfff
9999 11:44:35.059790 INFO: [NOCDAPC] D14_APC_0: 0x0
10000 11:44:35.062918 INFO: [NOCDAPC] D14_APC_1: 0xfff
10001 11:44:35.066419 INFO: [NOCDAPC] D15_APC_0: 0x0
10002 11:44:35.069637 INFO: [NOCDAPC] D15_APC_1: 0xfff
10003 11:44:35.073203 INFO: [NOCDAPC] APC_CON: 0x4
10004 11:44:35.076532 INFO: [APUAPC] set_apusys_apc done
10005 11:44:35.076965 INFO: [DEVAPC] devapc_init done
10006 11:44:35.083001 INFO: GICv3 without legacy support detected.
10007 11:44:35.086184 INFO: ARM GICv3 driver initialized in EL3
10008 11:44:35.089699 INFO: Maximum SPI INTID supported: 639
10009 11:44:35.092834 INFO: BL31: Initializing runtime services
10010 11:44:35.099547 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10011 11:44:35.102464 INFO: SPM: enable CPC mode
10012 11:44:35.105710 INFO: mcdi ready for mcusys-off-idle and system suspend
10013 11:44:35.112726 INFO: BL31: Preparing for EL3 exit to normal world
10014 11:44:35.115847 INFO: Entry point address = 0x80000000
10015 11:44:35.119040 INFO: SPSR = 0x8
10016 11:44:35.123698
10017 11:44:35.124117
10018 11:44:35.124451
10019 11:44:35.126843 Starting depthcharge on Spherion...
10020 11:44:35.127267
10021 11:44:35.127603 Wipe memory regions:
10022 11:44:35.127919
10023 11:44:35.130116 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10024 11:44:35.130607 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10025 11:44:35.131007 Setting prompt string to ['asurada:']
10026 11:44:35.131418 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10027 11:44:35.132063 [0x00000040000000, 0x00000054600000)
10028 11:44:35.252578
10029 11:44:35.253200 [0x00000054660000, 0x00000080000000)
10030 11:44:35.512936
10031 11:44:35.513535 [0x000000821a7280, 0x000000ffe64000)
10032 11:44:36.257729
10033 11:44:36.257878 [0x00000100000000, 0x00000240000000)
10034 11:44:38.148085
10035 11:44:38.151269 Initializing XHCI USB controller at 0x11200000.
10036 11:44:39.189233
10037 11:44:39.192410 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10038 11:44:39.192504
10039 11:44:39.192570
10040 11:44:39.192633
10041 11:44:39.192911 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 11:44:39.293275 asurada: tftpboot 192.168.201.1 10742243/tftp-deploy-me9zrnxy/kernel/image.itb 10742243/tftp-deploy-me9zrnxy/kernel/cmdline
10044 11:44:39.293400 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 11:44:39.293490 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10046 11:44:39.297201 tftpboot 192.168.201.1 10742243/tftp-deploy-me9zrnxy/kernel/image.itp-deploy-me9zrnxy/kernel/cmdline
10047 11:44:39.297289
10048 11:44:39.297356 Waiting for link
10049 11:44:39.457781
10050 11:44:39.457898 R8152: Initializing
10051 11:44:39.457968
10052 11:44:39.461115 Version 9 (ocp_data = 6010)
10053 11:44:39.461199
10054 11:44:39.464230 R8152: Done initializing
10055 11:44:39.464314
10056 11:44:39.464380 Adding net device
10057 11:44:41.410900
10058 11:44:41.411465 done.
10059 11:44:41.411847
10060 11:44:41.412200 MAC: 00:e0:4c:72:2d:d6
10061 11:44:41.412539
10062 11:44:41.414246 Sending DHCP discover... done.
10063 11:44:41.414718
10064 11:44:41.417211 Waiting for reply... done.
10065 11:44:41.417828
10066 11:44:41.420682 Sending DHCP request... done.
10067 11:44:41.421215
10068 11:44:44.524951 Waiting for reply... done.
10069 11:44:44.525185
10070 11:44:44.525310 My ip is 192.168.201.21
10071 11:44:44.525425
10072 11:44:44.528529 The DHCP server ip is 192.168.201.1
10073 11:44:44.528661
10074 11:44:44.535004 TFTP server IP predefined by user: 192.168.201.1
10075 11:44:44.535120
10076 11:44:44.541592 Bootfile predefined by user: 10742243/tftp-deploy-me9zrnxy/kernel/image.itb
10077 11:44:44.541746
10078 11:44:44.544666 Sending tftp read request... done.
10079 11:44:44.544830
10080 11:44:44.548302 Waiting for the transfer...
10081 11:44:44.548455
10082 11:44:44.839123 00000000 ################################################################
10083 11:44:44.839290
10084 11:44:45.087891 00080000 ################################################################
10085 11:44:45.088051
10086 11:44:45.343673 00100000 ################################################################
10087 11:44:45.343815
10088 11:44:45.590157 00180000 ################################################################
10089 11:44:45.590295
10090 11:44:45.850430 00200000 ################################################################
10091 11:44:45.850550
10092 11:44:46.121982 00280000 ################################################################
10093 11:44:46.122114
10094 11:44:46.383273 00300000 ################################################################
10095 11:44:46.383401
10096 11:44:46.653902 00380000 ################################################################
10097 11:44:46.654026
10098 11:44:46.920577 00400000 ################################################################
10099 11:44:46.920712
10100 11:44:47.214064 00480000 ################################################################
10101 11:44:47.214193
10102 11:44:47.509255 00500000 ################################################################
10103 11:44:47.509377
10104 11:44:47.788214 00580000 ################################################################
10105 11:44:47.788361
10106 11:44:48.050464 00600000 ################################################################
10107 11:44:48.050600
10108 11:44:48.329758 00680000 ################################################################
10109 11:44:48.329893
10110 11:44:48.578471 00700000 ################################################################
10111 11:44:48.578611
10112 11:44:48.837849 00780000 ################################################################
10113 11:44:48.837986
10114 11:44:49.088767 00800000 ################################################################
10115 11:44:49.088888
10116 11:44:49.493271 00880000 ################################################################
10117 11:44:49.493452
10118 11:44:49.600192 00900000 ################################################################
10119 11:44:49.600333
10120 11:44:49.850701 00980000 ################################################################
10121 11:44:49.850833
10122 11:44:50.102677 00a00000 ################################################################
10123 11:44:50.102807
10124 11:44:50.352973 00a80000 ################################################################
10125 11:44:50.353111
10126 11:44:50.604712 00b00000 ################################################################
10127 11:44:50.604851
10128 11:44:50.863662 00b80000 ################################################################
10129 11:44:50.863812
10130 11:44:51.135929 00c00000 ################################################################
10131 11:44:51.136474
10132 11:44:51.447032 00c80000 ################################################################
10133 11:44:51.447576
10134 11:44:51.759056 00d00000 ################################################################
10135 11:44:51.759198
10136 11:44:52.019430 00d80000 ################################################################
10137 11:44:52.019584
10138 11:44:52.301280 00e00000 ################################################################
10139 11:44:52.301430
10140 11:44:52.588294 00e80000 ################################################################
10141 11:44:52.588446
10142 11:44:52.877170 00f00000 ################################################################
10143 11:44:52.877320
10144 11:44:53.173185 00f80000 ################################################################
10145 11:44:53.173317
10146 11:44:53.469013 01000000 ################################################################
10147 11:44:53.469182
10148 11:44:53.765763 01080000 ################################################################
10149 11:44:53.765907
10150 11:44:54.058477 01100000 ################################################################
10151 11:44:54.058602
10152 11:44:54.354688 01180000 ################################################################
10153 11:44:54.354812
10154 11:44:54.650136 01200000 ################################################################
10155 11:44:54.650275
10156 11:44:54.911959 01280000 ################################################################
10157 11:44:54.912110
10158 11:44:55.164065 01300000 ################################################################
10159 11:44:55.164189
10160 11:44:55.419095 01380000 ################################################################
10161 11:44:55.419217
10162 11:44:55.668182 01400000 ################################################################
10163 11:44:55.668301
10164 11:44:55.920094 01480000 ################################################################
10165 11:44:55.920222
10166 11:44:56.187115 01500000 ################################################################
10167 11:44:56.187256
10168 11:44:56.439043 01580000 ################################################################
10169 11:44:56.439181
10170 11:44:56.695551 01600000 ################################################################
10171 11:44:56.695709
10172 11:44:56.959596 01680000 ################################################################
10173 11:44:56.959758
10174 11:44:57.248372 01700000 ################################################################
10175 11:44:57.248497
10176 11:44:57.506521 01780000 ################################################################
10177 11:44:57.506649
10178 11:44:57.763582 01800000 ################################################################
10179 11:44:57.763706
10180 11:44:58.020538 01880000 ################################################################
10181 11:44:58.020671
10182 11:44:58.278361 01900000 ################################################################
10183 11:44:58.278497
10184 11:44:58.533595 01980000 ################################################################
10185 11:44:58.533737
10186 11:44:58.828823 01a00000 ################################################################
10187 11:44:58.829005
10188 11:44:59.111173 01a80000 ################################################################
10189 11:44:59.111303
10190 11:44:59.378643 01b00000 ################################################################
10191 11:44:59.378775
10192 11:44:59.641100 01b80000 ################################################################
10193 11:44:59.641221
10194 11:44:59.892352 01c00000 ################################################################
10195 11:44:59.892496
10196 11:45:00.141302 01c80000 ################################################################
10197 11:45:00.141435
10198 11:45:00.393905 01d00000 ################################################################
10199 11:45:00.394042
10200 11:45:00.668825 01d80000 ################################################################
10201 11:45:00.669013
10202 11:45:00.943812 01e00000 ################################################################
10203 11:45:00.943966
10204 11:45:01.187295 01e80000 ################################################################
10205 11:45:01.187447
10206 11:45:01.460473 01f00000 ################################################################
10207 11:45:01.460619
10208 11:45:01.738008 01f80000 ################################################################
10209 11:45:01.738162
10210 11:45:02.005655 02000000 ################################################################
10211 11:45:02.005832
10212 11:45:02.285535 02080000 ################################################################
10213 11:45:02.285689
10214 11:45:02.545372 02100000 ################################################################
10215 11:45:02.545524
10216 11:45:02.829457 02180000 ################################################################
10217 11:45:02.829614
10218 11:45:03.107360 02200000 ################################################################
10219 11:45:03.107505
10220 11:45:03.371422 02280000 ################################################################
10221 11:45:03.371579
10222 11:45:03.634124 02300000 ################################################################
10223 11:45:03.634283
10224 11:45:03.915510 02380000 ################################################################
10225 11:45:03.915668
10226 11:45:04.963941 02400000 ################################################################
10227 11:45:04.964127
10228 11:45:04.964228 02480000 ################################################################
10229 11:45:04.964323
10230 11:45:04.964420 02500000 ################################################################
10231 11:45:04.964513
10232 11:45:04.964601 02580000 ################################################################
10233 11:45:04.964692
10234 11:45:05.198460 02600000 ################################################################
10235 11:45:05.198617
10236 11:45:05.450653 02680000 ################################################################
10237 11:45:05.450806
10238 11:45:05.701563 02700000 ################################################################
10239 11:45:05.701709
10240 11:45:05.956356 02780000 ################################################################
10241 11:45:05.956516
10242 11:45:06.823428 02800000 ################################################################
10243 11:45:06.824183
10244 11:45:06.824802 02880000 ################################################################
10245 11:45:06.825413
10246 11:45:06.826001 02900000 ################################################################
10247 11:45:06.826601
10248 11:45:06.994777 02980000 ################################################################
10249 11:45:06.994927
10250 11:45:07.286942 02a00000 ################################################################
10251 11:45:07.287093
10252 11:45:07.577432 02a80000 ################################################################
10253 11:45:07.577556
10254 11:45:07.833320 02b00000 ################################################################
10255 11:45:07.833455
10256 11:45:08.097597 02b80000 ################################################################
10257 11:45:08.097745
10258 11:45:08.379381 02c00000 ################################################################
10259 11:45:08.379505
10260 11:45:08.657577 02c80000 ################################################################
10261 11:45:08.657708
10262 11:45:08.953987 02d00000 ################################################################
10263 11:45:08.954115
10264 11:45:09.249533 02d80000 ################################################################
10265 11:45:09.249659
10266 11:45:09.541988 02e00000 ################################################################
10267 11:45:09.542115
10268 11:45:09.814227 02e80000 ################################################################
10269 11:45:09.814359
10270 11:45:10.081935 02f00000 ################################################################
10271 11:45:10.082059
10272 11:45:10.351970 02f80000 ################################################################
10273 11:45:10.352102
10274 11:45:10.501847 03000000 ##################################### done.
10275 11:45:10.501963
10276 11:45:10.505337 The bootfile was 50630246 bytes long.
10277 11:45:10.505427
10278 11:45:10.508426 Sending tftp read request... done.
10279 11:45:10.508522
10280 11:45:10.511615 Waiting for the transfer...
10281 11:45:10.511712
10282 11:45:10.511788 00000000 # done.
10283 11:45:10.511863
10284 11:45:10.522022 Command line loaded dynamically from TFTP file: 10742243/tftp-deploy-me9zrnxy/kernel/cmdline
10285 11:45:10.522230
10286 11:45:10.531880 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10287 11:45:10.532062
10288 11:45:10.535705 Loading FIT.
10289 11:45:10.535936
10290 11:45:10.536071 Image ramdisk-1 has 40137926 bytes.
10291 11:45:10.538253
10292 11:45:10.538435 Image fdt-1 has 46924 bytes.
10293 11:45:10.538578
10294 11:45:10.541887 Image kernel-1 has 10443363 bytes.
10295 11:45:10.542166
10296 11:45:10.551531 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10297 11:45:10.551796
10298 11:45:10.568396 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10299 11:45:10.568888
10300 11:45:10.575271 Choosing best match conf-1 for compat google,spherion-rev2.
10301 11:45:10.579010
10302 11:45:10.582796 Connected to device vid:did:rid of 1ae0:0028:00
10303 11:45:10.590218
10304 11:45:10.593634 tpm_get_response: command 0x17b, return code 0x0
10305 11:45:10.594109
10306 11:45:10.596529 ec_init: CrosEC protocol v3 supported (256, 248)
10307 11:45:10.601041
10308 11:45:10.604113 tpm_cleanup: add release locality here.
10309 11:45:10.604576
10310 11:45:10.604943 Shutting down all USB controllers.
10311 11:45:10.607550
10312 11:45:10.608009 Removing current net device
10313 11:45:10.608377
10314 11:45:10.613748 Exiting depthcharge with code 4 at timestamp: 64776369
10315 11:45:10.614298
10316 11:45:10.616821 LZMA decompressing kernel-1 to 0x821a6718
10317 11:45:10.616930
10318 11:45:10.619957 LZMA decompressing kernel-1 to 0x40000000
10319 11:45:12.524087
10320 11:45:12.524778 jumping to kernel
10321 11:45:12.525296
10322 11:45:12.525662 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10323 11:45:12.526020 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j40550-arm64-gcc-10-defconfig-arm64-chromebook-kp2kc) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023
10324 11:45:12.526418 [ 0.000000] random: crng init done
10325 11:45:12.526968 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10326 11:45:12.527510 [ 0.000000] efi: UEFI not found.
10327 11:45:12.528053 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10328 11:45:12.528527 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10329 11:45:12.529121 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10330 11:45:12.529289 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10331 11:45:12.529377 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10332 11:45:12.529440 [ 0.000000] printk: bootconsole [mtk8250] enabled
10333 11:45:12.529500 [ 0.000000] NUMA: No NUMA configuration found
10334 11:45:12.529557 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10335 11:45:12.529615 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10336 11:45:12.529671 [ 0.000000] Zone ranges:
10337 11:45:12.529729 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10338 11:45:12.529785 [ 0.000000] DMA32 empty
10339 11:45:12.529842 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10340 11:45:12.529897 [ 0.000000] Movable zone start for each node
10341 11:45:12.529954 [ 0.000000] Early memory node ranges
10342 11:45:12.530010 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10343 11:45:12.530066 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10344 11:45:12.530120 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10345 11:45:12.530176 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10346 11:45:12.530231 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10347 11:45:12.530287 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10348 11:45:12.530343 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10349 11:45:12.530398 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10350 11:45:12.530454 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10351 11:45:12.530510 [ 0.000000] psci: probing for conduit method from DT.
10352 11:45:12.530565 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10353 11:45:12.530628 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10354 11:45:12.530701 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10355 11:45:12.530758 [ 0.000000] psci: SMC Calling Convention v1.2
10356 11:45:12.530817 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10357 11:45:12.530895 [ 0.000000] Detected VIPT I-cache on CPU0
10358 11:45:12.530972 [ 0.000000] CPU features: detected: GIC system register CPU interface
10359 11:45:12.531048 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10360 11:45:12.531155 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10361 11:45:12.531297 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10362 11:45:12.531385 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10363 11:45:12.531472 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10364 11:45:12.531557 [ 0.000000] alternatives: applying boot alternatives
10365 11:45:12.531642 [ 0.000000] Fallback order for Node 0: 0
10366 11:45:12.531728 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10367 11:45:12.531812 [ 0.000000] Policy zone: Normal
10368 11:45:12.531914 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10369 11:45:12.532003 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10370 11:45:12.532092 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10371 11:45:12.532180 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10372 11:45:12.532281 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10373 11:45:12.532366 <6>[ 0.000000] software IO TLB: area num 8.
10374 11:45:12.532451 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10375 11:45:12.533138 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10376 11:45:12.533256 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10377 11:45:12.533334 Setting prompt string to ['Linux version [0-9]']
10378 11:45:12.533404 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10379 11:45:12.533475 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10380 11:45:12.533767 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10381 11:45:12.533850 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10382 11:45:12.533933 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10383 11:45:12.534008 Using line separator: #'\n'#
10384 11:45:12.534069 No login prompt set.
10385 11:45:12.534131 Parsing kernel messages
10386 11:45:12.534206 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10387 11:45:12.534387 [login-action] Waiting for messages, (timeout 00:03:48)
10388 11:45:12.604519 <6>[ 0.000000] Memory: 7931960K/8385536K available (17984K kernel code, 4098K rwdata, 15868K rodata, 8384K init, 615K bss, 420808K reserved, 32768K cma-reserved)
10389 11:45:12.611180 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10390 11:45:12.617865 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10391 11:45:12.620949 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10392 11:45:12.627676 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10393 11:45:12.634220 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10394 11:45:12.637363 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10395 11:45:12.647518 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10396 11:45:12.654237 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10397 11:45:12.660561 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10398 11:45:12.667121 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10399 11:45:12.670606 <6>[ 0.000000] GICv3: 608 SPIs implemented
10400 11:45:12.673589 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10401 11:45:12.680831 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10402 11:45:12.684051 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10403 11:45:12.690712 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10404 11:45:12.703511 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10405 11:45:12.717121 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10406 11:45:12.723626 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10407 11:45:12.731205 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10408 11:45:12.744511 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10409 11:45:12.750835 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10410 11:45:12.757378 <6>[ 0.009177] Console: colour dummy device 80x25
10411 11:45:12.767787 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10412 11:45:12.773967 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10413 11:45:12.777149 <6>[ 0.029218] LSM: Security Framework initializing
10414 11:45:12.783704 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 11:45:12.793818 <6>[ 0.041985] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10416 11:45:12.803673 <6>[ 0.051412] cblist_init_generic: Setting adjustable number of callback queues.
10417 11:45:12.806933 <6>[ 0.058863] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 11:45:12.813815 <6>[ 0.065242] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 11:45:12.820389 <6>[ 0.071648] rcu: Hierarchical SRCU implementation.
10420 11:45:12.827112 <6>[ 0.076692] rcu: Max phase no-delay instances is 1000.
10421 11:45:12.830417 <6>[ 0.083711] EFI services will not be available.
10422 11:45:12.837323 <6>[ 0.088680] smp: Bringing up secondary CPUs ...
10423 11:45:12.844374 <6>[ 0.093731] Detected VIPT I-cache on CPU1
10424 11:45:12.850970 <6>[ 0.093806] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10425 11:45:12.857674 <6>[ 0.093836] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10426 11:45:12.861419 <6>[ 0.094175] Detected VIPT I-cache on CPU2
10427 11:45:12.867457 <6>[ 0.094229] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10428 11:45:12.877416 <6>[ 0.094245] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10429 11:45:12.880962 <6>[ 0.094510] Detected VIPT I-cache on CPU3
10430 11:45:12.887380 <6>[ 0.094560] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10431 11:45:12.893744 <6>[ 0.094575] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10432 11:45:12.897499 <6>[ 0.094882] CPU features: detected: Spectre-v4
10433 11:45:12.903587 <6>[ 0.094889] CPU features: detected: Spectre-BHB
10434 11:45:12.907311 <6>[ 0.094895] Detected PIPT I-cache on CPU4
10435 11:45:12.913635 <6>[ 0.094945] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10436 11:45:12.920224 <6>[ 0.094961] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10437 11:45:12.927238 <6>[ 0.095242] Detected PIPT I-cache on CPU5
10438 11:45:12.933567 <6>[ 0.095299] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10439 11:45:12.940279 <6>[ 0.095315] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10440 11:45:12.943709 <6>[ 0.095592] Detected PIPT I-cache on CPU6
10441 11:45:12.950013 <6>[ 0.095658] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10442 11:45:12.956702 <6>[ 0.095674] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10443 11:45:12.963155 <6>[ 0.095970] Detected PIPT I-cache on CPU7
10444 11:45:12.969941 <6>[ 0.096034] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10445 11:45:12.976677 <6>[ 0.096050] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10446 11:45:12.979728 <6>[ 0.096097] smp: Brought up 1 node, 8 CPUs
10447 11:45:12.986371 <6>[ 0.237274] SMP: Total of 8 processors activated.
10448 11:45:12.990014 <6>[ 0.242196] CPU features: detected: 32-bit EL0 Support
10449 11:45:12.999691 <6>[ 0.247558] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10450 11:45:13.005984 <6>[ 0.256358] CPU features: detected: Common not Private translations
10451 11:45:13.012784 <6>[ 0.262873] CPU features: detected: CRC32 instructions
10452 11:45:13.015944 <6>[ 0.268225] CPU features: detected: RCpc load-acquire (LDAPR)
10453 11:45:13.022627 <6>[ 0.274184] CPU features: detected: LSE atomic instructions
10454 11:45:13.029137 <6>[ 0.279965] CPU features: detected: Privileged Access Never
10455 11:45:13.036099 <6>[ 0.285745] CPU features: detected: RAS Extension Support
10456 11:45:13.042808 <6>[ 0.291354] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10457 11:45:13.045747 <6>[ 0.298575] CPU: All CPU(s) started at EL2
10458 11:45:13.052291 <6>[ 0.302891] alternatives: applying system-wide alternatives
10459 11:45:13.062142 <6>[ 0.313600] devtmpfs: initialized
10460 11:45:13.077461 <6>[ 0.322373] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10461 11:45:13.083809 <6>[ 0.332335] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10462 11:45:13.090398 <6>[ 0.340512] pinctrl core: initialized pinctrl subsystem
10463 11:45:13.093569 <6>[ 0.347185] DMI not present or invalid.
10464 11:45:13.100444 <6>[ 0.351588] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10465 11:45:13.110372 <6>[ 0.358446] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10466 11:45:13.117118 <6>[ 0.366024] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10467 11:45:13.127084 <6>[ 0.374239] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10468 11:45:13.130109 <6>[ 0.382480] audit: initializing netlink subsys (disabled)
10469 11:45:13.140326 <5>[ 0.388170] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10470 11:45:13.146511 <6>[ 0.388880] thermal_sys: Registered thermal governor 'step_wise'
10471 11:45:13.153324 <6>[ 0.396137] thermal_sys: Registered thermal governor 'power_allocator'
10472 11:45:13.156386 <6>[ 0.402390] cpuidle: using governor menu
10473 11:45:13.163353 <6>[ 0.413348] NET: Registered PF_QIPCRTR protocol family
10474 11:45:13.169485 <6>[ 0.418821] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10475 11:45:13.176350 <6>[ 0.425922] ASID allocator initialised with 32768 entries
10476 11:45:13.179356 <6>[ 0.432480] Serial: AMBA PL011 UART driver
10477 11:45:13.189424 <4>[ 0.441145] Trying to register duplicate clock ID: 134
10478 11:45:13.243522 <6>[ 0.498350] KASLR enabled
10479 11:45:13.257901 <6>[ 0.506110] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10480 11:45:13.264409 <6>[ 0.513122] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10481 11:45:13.271265 <6>[ 0.519610] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10482 11:45:13.277886 <6>[ 0.526614] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10483 11:45:13.284317 <6>[ 0.533099] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10484 11:45:13.291018 <6>[ 0.540102] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10485 11:45:13.297630 <6>[ 0.546587] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10486 11:45:13.303846 <6>[ 0.553592] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10487 11:45:13.306924 <6>[ 0.561098] ACPI: Interpreter disabled.
10488 11:45:13.315713 <6>[ 0.567473] iommu: Default domain type: Translated
10489 11:45:13.321958 <6>[ 0.572583] iommu: DMA domain TLB invalidation policy: strict mode
10490 11:45:13.325622 <5>[ 0.579237] SCSI subsystem initialized
10491 11:45:13.332213 <6>[ 0.583403] usbcore: registered new interface driver usbfs
10492 11:45:13.338462 <6>[ 0.589136] usbcore: registered new interface driver hub
10493 11:45:13.341853 <6>[ 0.594686] usbcore: registered new device driver usb
10494 11:45:13.349151 <6>[ 0.600767] pps_core: LinuxPPS API ver. 1 registered
10495 11:45:13.359135 <6>[ 0.605960] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10496 11:45:13.362266 <6>[ 0.615309] PTP clock support registered
10497 11:45:13.365406 <6>[ 0.619549] EDAC MC: Ver: 3.0.0
10498 11:45:13.372957 <6>[ 0.624686] FPGA manager framework
10499 11:45:13.376215 <6>[ 0.628365] Advanced Linux Sound Architecture Driver Initialized.
10500 11:45:13.380185 <6>[ 0.635129] vgaarb: loaded
10501 11:45:13.386327 <6>[ 0.638290] clocksource: Switched to clocksource arch_sys_counter
10502 11:45:13.393090 <5>[ 0.644725] VFS: Disk quotas dquot_6.6.0
10503 11:45:13.399825 <6>[ 0.648908] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10504 11:45:13.402673 <6>[ 0.656095] pnp: PnP ACPI: disabled
10505 11:45:13.410934 <6>[ 0.662750] NET: Registered PF_INET protocol family
10506 11:45:13.420424 <6>[ 0.668332] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10507 11:45:13.432242 <6>[ 0.680632] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10508 11:45:13.442136 <6>[ 0.689448] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10509 11:45:13.448552 <6>[ 0.697417] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10510 11:45:13.458255 <6>[ 0.706115] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10511 11:45:13.465042 <6>[ 0.715834] TCP: Hash tables configured (established 65536 bind 65536)
10512 11:45:13.471844 <6>[ 0.722680] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 11:45:13.481851 <6>[ 0.729878] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 11:45:13.488289 <6>[ 0.737571] NET: Registered PF_UNIX/PF_LOCAL protocol family
10515 11:45:13.491546 <6>[ 0.743715] RPC: Registered named UNIX socket transport module.
10516 11:45:13.497794 <6>[ 0.749869] RPC: Registered udp transport module.
10517 11:45:13.501495 <6>[ 0.754801] RPC: Registered tcp transport module.
10518 11:45:13.507961 <6>[ 0.759733] RPC: Registered tcp NFSv4.1 backchannel transport module.
10519 11:45:13.514383 <6>[ 0.766401] PCI: CLS 0 bytes, default 64
10520 11:45:13.517694 <6>[ 0.770706] Unpacking initramfs...
10521 11:45:13.534110 <6>[ 0.782860] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10522 11:45:13.543957 <6>[ 0.791502] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10523 11:45:13.547617 <6>[ 0.800328] kvm [1]: IPA Size Limit: 40 bits
10524 11:45:13.554119 <6>[ 0.804856] kvm [1]: GICv3: no GICV resource entry
10525 11:45:13.557367 <6>[ 0.809877] kvm [1]: disabling GICv2 emulation
10526 11:45:13.564023 <6>[ 0.814561] kvm [1]: GIC system register CPU interface enabled
10527 11:45:13.567126 <6>[ 0.820718] kvm [1]: vgic interrupt IRQ18
10528 11:45:13.574388 <6>[ 0.826376] kvm [1]: VHE mode initialized successfully
10529 11:45:13.581186 <5>[ 0.832666] Initialise system trusted keyrings
10530 11:45:13.587595 <6>[ 0.837487] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10531 11:45:13.595613 <6>[ 0.847441] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10532 11:45:13.601861 <5>[ 0.853822] NFS: Registering the id_resolver key type
10533 11:45:13.605623 <5>[ 0.859136] Key type id_resolver registered
10534 11:45:13.611913 <5>[ 0.863549] Key type id_legacy registered
10535 11:45:13.618224 <6>[ 0.867827] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10536 11:45:13.624918 <6>[ 0.874752] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10537 11:45:13.631216 <6>[ 0.882494] 9p: Installing v9fs 9p2000 file system support
10538 11:45:13.668051 <5>[ 0.920138] Key type asymmetric registered
10539 11:45:13.671119 <5>[ 0.924468] Asymmetric key parser 'x509' registered
10540 11:45:13.681396 <6>[ 0.929634] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10541 11:45:13.684473 <6>[ 0.937253] io scheduler mq-deadline registered
10542 11:45:13.687581 <6>[ 0.942012] io scheduler kyber registered
10543 11:45:13.706672 <6>[ 0.958673] EINJ: ACPI disabled.
10544 11:45:13.738277 <4>[ 0.983589] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 11:45:13.747923 <4>[ 0.994205] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 11:45:13.762381 <6>[ 1.014667] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10547 11:45:13.770079 <6>[ 1.022546] printk: console [ttyS0] disabled
10548 11:45:13.798321 <6>[ 1.047190] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10549 11:45:13.805025 <6>[ 1.056663] printk: console [ttyS0] enabled
10550 11:45:13.808353 <6>[ 1.056663] printk: console [ttyS0] enabled
10551 11:45:13.814909 <6>[ 1.065556] printk: bootconsole [mtk8250] disabled
10552 11:45:13.818458 <6>[ 1.065556] printk: bootconsole [mtk8250] disabled
10553 11:45:13.824970 <6>[ 1.076554] SuperH (H)SCI(F) driver initialized
10554 11:45:13.828235 <6>[ 1.081815] msm_serial: driver initialized
10555 11:45:13.841736 <6>[ 1.090604] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10556 11:45:13.852039 <6>[ 1.099146] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10557 11:45:13.858498 <6>[ 1.107688] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10558 11:45:13.868644 <6>[ 1.116315] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10559 11:45:13.878624 <6>[ 1.125020] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10560 11:45:13.885245 <6>[ 1.133738] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10561 11:45:13.895136 <6>[ 1.142282] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10562 11:45:13.901427 <6>[ 1.151066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10563 11:45:13.910949 <6>[ 1.159607] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10564 11:45:13.922822 <6>[ 1.174946] loop: module loaded
10565 11:45:13.929674 <6>[ 1.180875] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10566 11:45:13.951925 <4>[ 1.204089] mtk-pmic-keys: Failed to locate of_node [id: -1]
10567 11:45:13.961858 <6>[ 1.210754] megasas: 07.719.03.00-rc1
10568 11:45:13.968550 <6>[ 1.220163] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10569 11:45:14.004109 <6>[ 1.233661] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10570 11:45:14.005256 <6>[ 1.249463] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10571 11:45:14.056866 <6>[ 1.302463] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10572 11:45:15.124006 <6>[ 2.375735] Freeing initrd memory: 39192K
10573 11:45:15.133855 <6>[ 2.385983] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10574 11:45:15.144860 <6>[ 2.396854] tun: Universal TUN/TAP device driver, 1.6
10575 11:45:15.148057 <6>[ 2.402909] thunder_xcv, ver 1.0
10576 11:45:15.151577 <6>[ 2.406410] thunder_bgx, ver 1.0
10577 11:45:15.155088 <6>[ 2.409898] nicpf, ver 1.0
10578 11:45:15.164935 <6>[ 2.413900] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10579 11:45:15.168777 <6>[ 2.421376] hns3: Copyright (c) 2017 Huawei Corporation.
10580 11:45:15.175036 <6>[ 2.426961] hclge is initializing
10581 11:45:15.178262 <6>[ 2.430540] e1000: Intel(R) PRO/1000 Network Driver
10582 11:45:15.184771 <6>[ 2.435669] e1000: Copyright (c) 1999-2006 Intel Corporation.
10583 11:45:15.187867 <6>[ 2.441681] e1000e: Intel(R) PRO/1000 Network Driver
10584 11:45:15.194603 <6>[ 2.446896] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10585 11:45:15.201149 <6>[ 2.453083] igb: Intel(R) Gigabit Ethernet Network Driver
10586 11:45:15.207695 <6>[ 2.458733] igb: Copyright (c) 2007-2014 Intel Corporation.
10587 11:45:15.214428 <6>[ 2.464569] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10588 11:45:15.220911 <6>[ 2.471087] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10589 11:45:15.224612 <6>[ 2.477544] sky2: driver version 1.30
10590 11:45:15.230925 <6>[ 2.482523] VFIO - User Level meta-driver version: 0.3
10591 11:45:15.238400 <6>[ 2.490722] usbcore: registered new interface driver usb-storage
10592 11:45:15.245035 <6>[ 2.497161] usbcore: registered new device driver onboard-usb-hub
10593 11:45:15.253738 <6>[ 2.506209] mt6397-rtc mt6359-rtc: registered as rtc0
10594 11:45:15.263891 <6>[ 2.511676] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-15T11:45:10 UTC (1686829510)
10595 11:45:15.267571 <6>[ 2.521230] i2c_dev: i2c /dev entries driver
10596 11:45:15.283844 <6>[ 2.532781] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10597 11:45:15.290875 <6>[ 2.542772] sdhci: Secure Digital Host Controller Interface driver
10598 11:45:15.297619 <6>[ 2.549210] sdhci: Copyright(c) Pierre Ossman
10599 11:45:15.304080 <6>[ 2.554604] Synopsys Designware Multimedia Card Interface Driver
10600 11:45:15.307311 <6>[ 2.561195] mmc0: CQHCI version 5.10
10601 11:45:15.313731 <6>[ 2.561754] sdhci-pltfm: SDHCI platform and OF driver helper
10602 11:45:15.320728 <6>[ 2.573031] ledtrig-cpu: registered to indicate activity on CPUs
10603 11:45:15.331669 <6>[ 2.580324] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10604 11:45:15.335285 <6>[ 2.587713] usbcore: registered new interface driver usbhid
10605 11:45:15.341386 <6>[ 2.593545] usbhid: USB HID core driver
10606 11:45:15.348084 <6>[ 2.597788] spi_master spi0: will run message pump with realtime priority
10607 11:45:15.392945 <6>[ 2.638266] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10608 11:45:15.412797 <6>[ 2.654090] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10609 11:45:15.415880 <6>[ 2.667659] mmc0: Command Queue Engine enabled
10610 11:45:15.422911 <6>[ 2.669235] cros-ec-spi spi0.0: Chrome EC device registered
10611 11:45:15.426077 <6>[ 2.672409] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10612 11:45:15.433341 <6>[ 2.685425] mmcblk0: mmc0:0001 DA4128 116 GiB
10613 11:45:15.446342 <6>[ 2.694955] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10614 11:45:15.452727 <6>[ 2.696773] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10615 11:45:15.459610 <6>[ 2.706464] NET: Registered PF_PACKET protocol family
10616 11:45:15.463031 <6>[ 2.711550] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10617 11:45:15.469336 <6>[ 2.715607] 9pnet: Installing 9P2000 support
10618 11:45:15.473043 <6>[ 2.721314] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10619 11:45:15.479567 <5>[ 2.725282] Key type dns_resolver registered
10620 11:45:15.486015 <6>[ 2.731089] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10621 11:45:15.489283 <6>[ 2.735599] registered taskstats version 1
10622 11:45:15.492477 <5>[ 2.745890] Loading compiled-in X.509 certificates
10623 11:45:15.528724 <4>[ 2.773727] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10624 11:45:15.538588 <4>[ 2.784425] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 11:45:15.548564 <3>[ 2.797240] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10626 11:45:15.560867 <6>[ 2.812762] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10627 11:45:15.567570 <6>[ 2.819515] xhci-mtk 11200000.usb: xHCI Host Controller
10628 11:45:15.573950 <6>[ 2.825023] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10629 11:45:15.584118 <6>[ 2.832893] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10630 11:45:15.590724 <6>[ 2.842342] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10631 11:45:15.597423 <6>[ 2.848572] xhci-mtk 11200000.usb: xHCI Host Controller
10632 11:45:15.604421 <6>[ 2.854068] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10633 11:45:15.610929 <6>[ 2.861728] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10634 11:45:15.617645 <6>[ 2.869629] hub 1-0:1.0: USB hub found
10635 11:45:15.620769 <6>[ 2.873668] hub 1-0:1.0: 1 port detected
10636 11:45:15.630902 <6>[ 2.878016] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10637 11:45:15.634257 <6>[ 2.886835] hub 2-0:1.0: USB hub found
10638 11:45:15.637352 <6>[ 2.890907] hub 2-0:1.0: 1 port detected
10639 11:45:15.646261 <6>[ 2.897995] mtk-msdc 11f70000.mmc: Got CD GPIO
10640 11:45:15.663163 <6>[ 2.911880] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10641 11:45:15.669739 <6>[ 2.919933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10642 11:45:15.679712 <4>[ 2.927905] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10643 11:45:15.689638 <6>[ 2.937560] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10644 11:45:15.696029 <6>[ 2.945641] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10645 11:45:15.705985 <6>[ 2.953681] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10646 11:45:15.712333 <6>[ 2.961597] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10647 11:45:15.718831 <6>[ 2.969419] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10648 11:45:15.728812 <6>[ 2.977250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10649 11:45:15.739146 <6>[ 2.987994] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10650 11:45:15.749422 <6>[ 2.996362] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10651 11:45:15.755858 <6>[ 3.004716] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10652 11:45:15.765856 <6>[ 3.013063] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10653 11:45:15.772663 <6>[ 3.021406] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10654 11:45:15.782535 <6>[ 3.029749] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10655 11:45:15.788887 <6>[ 3.038091] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10656 11:45:15.798798 <6>[ 3.046435] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10657 11:45:15.805599 <6>[ 3.054778] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10658 11:45:15.815547 <6>[ 3.063121] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10659 11:45:15.821831 <6>[ 3.071465] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10660 11:45:15.832039 <6>[ 3.079807] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10661 11:45:15.838976 <6>[ 3.088150] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10662 11:45:15.848266 <6>[ 3.096493] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10663 11:45:15.855093 <6>[ 3.104839] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10664 11:45:15.861950 <6>[ 3.113728] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10665 11:45:15.869134 <6>[ 3.121181] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10666 11:45:15.876373 <6>[ 3.128266] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10667 11:45:15.886596 <6>[ 3.135405] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10668 11:45:15.893156 <6>[ 3.142729] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10669 11:45:15.903293 <6>[ 3.149638] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10670 11:45:15.909970 <6>[ 3.158779] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10671 11:45:15.919747 <6>[ 3.167905] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10672 11:45:15.929769 <6>[ 3.177207] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10673 11:45:15.939841 <6>[ 3.186682] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10674 11:45:15.949297 <6>[ 3.196156] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10675 11:45:15.956103 <6>[ 3.205292] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10676 11:45:15.966141 <6>[ 3.214767] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10677 11:45:15.976122 <6>[ 3.223894] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10678 11:45:15.985806 <6>[ 3.233208] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10679 11:45:15.996140 <6>[ 3.243376] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10680 11:45:16.006263 <6>[ 3.254791] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10681 11:45:16.045815 <6>[ 3.294567] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10682 11:45:16.199945 <6>[ 3.451895] hub 1-1:1.0: USB hub found
10683 11:45:16.203232 <6>[ 3.456373] hub 1-1:1.0: 4 ports detected
10684 11:45:16.325494 <6>[ 3.574693] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10685 11:45:16.350966 <6>[ 3.602898] hub 2-1:1.0: USB hub found
10686 11:45:16.354191 <6>[ 3.607293] hub 2-1:1.0: 3 ports detected
10687 11:45:16.525619 <6>[ 3.774566] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10688 11:45:16.658654 <6>[ 3.910766] hub 1-1.4:1.0: USB hub found
10689 11:45:16.661721 <6>[ 3.915445] hub 1-1.4:1.0: 2 ports detected
10690 11:45:16.737770 <6>[ 3.986814] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10691 11:45:16.957822 <6>[ 4.206571] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10692 11:45:17.149501 <6>[ 4.398569] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10693 11:45:28.306618 <6>[ 15.563112] ALSA device list:
10694 11:45:28.312773 <6>[ 15.566369] No soundcards found.
10695 11:45:28.325174 <6>[ 15.578813] Freeing unused kernel memory: 8384K
10696 11:45:28.328650 <6>[ 15.583733] Run /init as init process
10697 11:45:28.358838 <6>[ 15.612557] NET: Registered PF_INET6 protocol family
10698 11:45:28.365333 <6>[ 15.619022] Segment Routing with IPv6
10699 11:45:28.368310 <6>[ 15.622983] In-situ OAM (IOAM) with IPv6
10700 11:45:28.403016 <30>[ 15.637321] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10701 11:45:28.406538 <30>[ 15.661190] systemd[1]: Detected architecture arm64.
10702 11:45:28.406734
10703 11:45:28.413243 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10704 11:45:28.413362
10705 11:45:28.429116 <30>[ 15.682693] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10706 11:45:28.580685 <30>[ 15.831245] systemd[1]: Queued start job for default target Graphical Interface.
10707 11:45:28.619082 <30>[ 15.871966] systemd[1]: Created slice system-getty.slice.
10708 11:45:28.624833 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10709 11:45:28.641868 <30>[ 15.895155] systemd[1]: Created slice system-modprobe.slice.
10710 11:45:28.648560 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10711 11:45:28.666468 <30>[ 15.919699] systemd[1]: Created slice system-serial\x2dgetty.slice.
10712 11:45:28.676212 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10713 11:45:28.689773 <30>[ 15.943074] systemd[1]: Created slice User and Session Slice.
10714 11:45:28.696281 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10715 11:45:28.717201 <30>[ 15.967121] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10716 11:45:28.726400 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10717 11:45:28.744911 <30>[ 15.994736] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10718 11:45:28.751327 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10719 11:45:28.772061 <30>[ 16.018676] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10720 11:45:28.778260 <30>[ 16.030725] systemd[1]: Reached target Local Encrypted Volumes.
10721 11:45:28.784787 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10722 11:45:28.801611 <30>[ 16.054944] systemd[1]: Reached target Paths.
10723 11:45:28.805159 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10724 11:45:28.821447 <30>[ 16.074613] systemd[1]: Reached target Remote File Systems.
10725 11:45:28.827767 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10726 11:45:28.845631 <30>[ 16.098831] systemd[1]: Reached target Slices.
10727 11:45:28.852255 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10728 11:45:28.865147 <30>[ 16.118620] systemd[1]: Reached target Swap.
10729 11:45:28.868448 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10730 11:45:28.888627 <30>[ 16.138936] systemd[1]: Listening on initctl Compatibility Named Pipe.
10731 11:45:28.895212 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10732 11:45:28.901556 <30>[ 16.153744] systemd[1]: Listening on Journal Audit Socket.
10733 11:45:28.908114 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10734 11:45:28.921336 <30>[ 16.174896] systemd[1]: Listening on Journal Socket (/dev/log).
10735 11:45:28.927871 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10736 11:45:28.946281 <30>[ 16.199358] systemd[1]: Listening on Journal Socket.
10737 11:45:28.952222 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10738 11:45:28.968840 <30>[ 16.218999] systemd[1]: Listening on Network Service Netlink Socket.
10739 11:45:28.975749 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10740 11:45:28.989925 <30>[ 16.243345] systemd[1]: Listening on udev Control Socket.
10741 11:45:28.996436 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10742 11:45:29.013911 <30>[ 16.267273] systemd[1]: Listening on udev Kernel Socket.
10743 11:45:29.020607 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10744 11:45:29.057635 <30>[ 16.310861] systemd[1]: Mounting Huge Pages File System...
10745 11:45:29.064031 Mounting [0;1;39mHuge Pages File System[0m...
10746 11:45:29.079294 <30>[ 16.332547] systemd[1]: Mounting POSIX Message Queue File System...
10747 11:45:29.085705 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10748 11:45:29.103195 <30>[ 16.356533] systemd[1]: Mounting Kernel Debug File System...
10749 11:45:29.109382 Mounting [0;1;39mKernel Debug File System[0m...
10750 11:45:29.129131 <30>[ 16.378839] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10751 11:45:29.139927 <30>[ 16.389878] systemd[1]: Starting Create list of static device nodes for the current kernel...
10752 11:45:29.146258 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10753 11:45:29.163895 <30>[ 16.417022] systemd[1]: Starting Load Kernel Module configfs...
10754 11:45:29.169900 Starting [0;1;39mLoad Kernel Module configfs[0m...
10755 11:45:29.187420 <30>[ 16.440889] systemd[1]: Starting Load Kernel Module drm...
10756 11:45:29.193907 Starting [0;1;39mLoad Kernel Module drm[0m...
10757 11:45:29.212826 <30>[ 16.462887] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10758 11:45:29.223278 <30>[ 16.476586] systemd[1]: Starting Journal Service...
10759 11:45:29.226447 Starting [0;1;39mJournal Service[0m...
10760 11:45:29.244064 <30>[ 16.497445] systemd[1]: Starting Load Kernel Modules...
10761 11:45:29.250702 Starting [0;1;39mLoad Kernel Modules[0m...
10762 11:45:29.270726 <30>[ 16.521182] systemd[1]: Starting Remount Root and Kernel File Systems...
10763 11:45:29.277216 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10764 11:45:29.291811 <30>[ 16.545120] systemd[1]: Starting Coldplug All udev Devices...
10765 11:45:29.298062 Starting [0;1;39mColdplug All udev Devices[0m...
10766 11:45:29.316085 <30>[ 16.569438] systemd[1]: Mounted Huge Pages File System.
10767 11:45:29.322339 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10768 11:45:29.337385 <30>[ 16.591066] systemd[1]: Started Journal Service.
10769 11:45:29.344198 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10770 11:45:29.358905 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10771 11:45:29.373937 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10772 11:45:29.393533 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10773 11:45:29.410791 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10774 11:45:29.426669 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10775 11:45:29.442175 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10776 11:45:29.465980 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10777 11:45:29.485105 See 'systemctl status systemd-remount-fs.service' for details.
10778 11:45:29.557893 Mounting [0;1;39mKernel Configuration File System[0m...
10779 11:45:29.579867 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10780 11:45:29.597433 <46>[ 16.847396] systemd-journald[177]: Received client request to flush runtime journal.
10781 11:45:29.605845 Starting [0;1;39mLoad/Save Random Seed[0m...
10782 11:45:29.627791 Starting [0;1;39mApply Kernel Variables[0m...
10783 11:45:29.644669 Starting [0;1;39mCreate System Users[0m...
10784 11:45:29.666861 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10785 11:45:29.685452 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10786 11:45:29.701857 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10787 11:45:29.718190 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10788 11:45:29.734444 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10789 11:45:29.749664 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10790 11:45:29.801393 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10791 11:45:29.825901 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10792 11:45:29.837733 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10793 11:45:29.852918 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10794 11:45:29.909561 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10795 11:45:29.933253 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10796 11:45:29.953756 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10797 11:45:29.973744 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10798 11:45:30.031348 Starting [0;1;39mNetwork Service[0m...
10799 11:45:30.051883 Starting [0;1;39mNetwork Time Synchronization[0m...
10800 11:45:30.072171 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10801 11:45:30.109210 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10802 11:45:30.129914 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10803 11:45:30.169983 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10804 11:45:30.196113 <6>[ 17.446140] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10805 11:45:30.204945 <6>[ 17.458537] remoteproc remoteproc0: scp is available
10806 11:45:30.211979 <6>[ 17.465010] remoteproc remoteproc0: powering up scp
10807 11:45:30.221724 <6>[ 17.470211] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10808 11:45:30.228574 <3>[ 17.472363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 11:45:30.234761 <6>[ 17.478832] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10810 11:45:30.241668 <3>[ 17.486978] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 11:45:30.247676 <6>[ 17.491369] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10812 11:45:30.257887 <6>[ 17.491413] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10813 11:45:30.267732 <6>[ 17.491426] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10814 11:45:30.274400 <3>[ 17.525460] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 11:45:30.281040 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10816 11:45:30.298309 <3>[ 17.548580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 11:45:30.304838 <3>[ 17.556714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 11:45:30.315307 <3>[ 17.564810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 11:45:30.321641 <3>[ 17.572902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 11:45:30.331701 <3>[ 17.580990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 11:45:30.344626 <3>[ 17.594684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10822 11:45:30.351065 <6>[ 17.604880] mc: Linux media interface: v0.10
10823 11:45:30.357886 <4>[ 17.605001] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10824 11:45:30.367749 <3>[ 17.612704] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10825 11:45:30.374468 <6>[ 17.617956] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10826 11:45:30.381101 <6>[ 17.617961] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10827 11:45:30.387512 <4>[ 17.621015] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10828 11:45:30.397578 <3>[ 17.625102] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 11:45:30.404336 <6>[ 17.632252] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10830 11:45:30.410669 <6>[ 17.632261] pci_bus 0000:00: root bus resource [bus 00-ff]
10831 11:45:30.417689 <6>[ 17.632268] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10832 11:45:30.427403 <6>[ 17.632279] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10833 11:45:30.434086 <6>[ 17.632317] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10834 11:45:30.440624 <6>[ 17.632338] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10835 11:45:30.447549 <6>[ 17.632420] pci 0000:00:00.0: supports D1 D2
10836 11:45:30.454051 <6>[ 17.632424] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10837 11:45:30.460770 <6>[ 17.633617] remoteproc remoteproc0: remote processor scp is now up
10838 11:45:30.467408 <6>[ 17.634037] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10839 11:45:30.473883 <6>[ 17.634189] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10840 11:45:30.480604 <6>[ 17.634223] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10841 11:45:30.486734 <6>[ 17.634246] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10842 11:45:30.497056 <6>[ 17.634264] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10843 11:45:30.500151 <6>[ 17.634428] pci 0000:01:00.0: supports D1 D2
10844 11:45:30.506650 <6>[ 17.634433] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10845 11:45:30.516781 <3>[ 17.640584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 11:45:30.523417 <6>[ 17.642474] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10847 11:45:30.529882 <6>[ 17.657589] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10848 11:45:30.536361 <3>[ 17.664711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 11:45:30.543127 <6>[ 17.668248] usbcore: registered new interface driver r8152
10850 11:45:30.553118 <6>[ 17.668661] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10851 11:45:30.556528 <6>[ 17.674611] videodev: Linux video capture interface: v2.00
10852 11:45:30.566292 <3>[ 17.675839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 11:45:30.573467 <6>[ 17.685983] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10854 11:45:30.583359 <3>[ 17.692548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 11:45:30.590102 <6>[ 17.699729] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10856 11:45:30.596498 <3>[ 17.704216] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10857 11:45:30.606457 <6>[ 17.711007] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10858 11:45:30.616419 <6>[ 17.711134] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10859 11:45:30.625926 <6>[ 17.713532] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10860 11:45:30.633117 <3>[ 17.717597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 11:45:30.642673 <6>[ 17.725914] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10862 11:45:30.646271 <3>[ 17.726566] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10863 11:45:30.655772 <3>[ 17.732895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 11:45:30.662608 <6>[ 17.739608] pci 0000:00:00.0: PCI bridge to [bus 01]
10865 11:45:30.669347 <6>[ 17.766655] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10866 11:45:30.675457 <6>[ 17.774060] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10867 11:45:30.685568 <6>[ 17.774189] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10868 11:45:30.692346 <6>[ 17.777553] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10869 11:45:30.702412 <4>[ 17.801684] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10870 11:45:30.708939 <6>[ 17.802859] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10871 11:45:30.716388 <4>[ 17.809153] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10872 11:45:30.722723 <4>[ 17.809153] Fallback method does not support PEC.
10873 11:45:30.729467 <4>[ 17.810475] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10874 11:45:30.736178 <6>[ 17.817172] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10875 11:45:30.742431 <3>[ 17.826617] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10876 11:45:30.749316 <6>[ 17.832899] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10877 11:45:30.752524 <6>[ 17.883698] r8152 2-1.3:1.0 eth0: v1.12.13
10878 11:45:30.762534 <3>[ 17.926717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 11:45:30.766363 <3>[ 17.942549] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10880 11:45:30.776311 <3>[ 17.981174] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 11:45:30.782556 <3>[ 17.994426] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10882 11:45:30.792850 <3>[ 18.001174] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10883 11:45:30.799269 <6>[ 18.006919] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10884 11:45:30.809301 <3>[ 18.024627] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 11:45:30.816155 <6>[ 18.064804] usbcore: registered new interface driver cdc_ether
10886 11:45:30.822664 <5>[ 18.072858] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10887 11:45:30.829343 <6>[ 18.076227] Bluetooth: Core ver 2.22
10888 11:45:30.832350 <6>[ 18.083064] usbcore: registered new interface driver r8153_ecm
10889 11:45:30.839255 <6>[ 18.086452] NET: Registered PF_BLUETOOTH protocol family
10890 11:45:30.845550 <6>[ 18.087495] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10891 11:45:30.858725 <6>[ 18.088883] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10892 11:45:30.865469 <6>[ 18.089123] usbcore: registered new interface driver uvcvideo
10893 11:45:30.871992 <5>[ 18.098974] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10894 11:45:30.878658 <6>[ 18.105329] Bluetooth: HCI device and connection manager initialized
10895 11:45:30.885464 <6>[ 18.107476] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10896 11:45:30.891743 <6>[ 18.126084] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10897 11:45:30.895018 <6>[ 18.130684] Bluetooth: HCI socket layer initialized
10898 11:45:30.901814 <6>[ 18.155092] Bluetooth: L2CAP socket layer initialized
10899 11:45:30.908683 <6>[ 18.160537] Bluetooth: SCO socket layer initialized
10900 11:45:30.918498 Startin<4>[ 18.161868] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10901 11:45:30.924577 g [0;1;39mNetwo<6>[ 18.175950] cfg80211: failed to load regulatory.db
10902 11:45:30.925082 rk Name Resolution[0m...
10903 11:45:30.935899 <6>[ 18.189559] usbcore: registered new interface driver btusb
10904 11:45:30.949341 <4>[ 18.196213] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10905 11:45:30.952704 <3>[ 18.206834] Bluetooth: hci0: Failed to load firmware file (-2)
10906 11:45:30.959152 <3>[ 18.212956] Bluetooth: hci0: Failed to set up firmware (-2)
10907 11:45:30.969313 <4>[ 18.212966] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10908 11:45:30.979797 <6>[ 18.216579] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10909 11:45:30.986393 [[0;32m OK [<6>[ 18.237072] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10910 11:45:30.996779 0m] Started [0;1;39mNetwork Tim<3>[ 18.246443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10911 11:45:31.006785 e Synchronizatio<3>[ 18.247232] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 11:45:31.016793 <3>[ 18.251849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 11:45:31.020433 <6>[ 18.262482] mt7921e 0000:01:00.0: ASIC revision: 79610010
10914 11:45:31.023773 n[0m.
10915 11:45:31.034014 <3>[ 18.283839] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:45:31.040412 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10917 11:45:31.062177 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10918 11:45:31.068924 <3>[ 18.319782] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 11:45:31.079360 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10920 11:45:31.101701 <3>[ 18.352409] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:45:31.128501 <4>[ 18.375099] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10922 11:45:31.245855 <4>[ 18.492701] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10923 11:45:31.274089 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10924 11:45:31.289160 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10925 11:45:31.308208 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10926 11:45:31.321374 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10927 11:45:31.344439 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10928 11:45:31.367377 [[0;32m OK [0m] Reached targ<4>[ 18.612802] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10929 11:45:31.370551 et [0;1;39mSystem Time Set[0m.
10930 11:45:31.376744 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10931 11:45:31.396469 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10932 11:45:31.408923 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10933 11:45:31.428800 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10934 11:45:31.441396 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10935 11:45:31.457346 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10936 11:45:31.487909 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch S<4>[ 18.733096] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10937 11:45:31.488510 tatus /dev/rfkill Watch[0m.
10938 11:45:31.533666 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10939 11:45:31.560186 Starting [0;1;39mUser Login Management[0m...
10940 11:45:31.575444 Starting [0;1;39mPermit User Sessions[0m...
10941 11:45:31.611881 Starting [0;1;39mLoad/<4>[ 18.857601] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10942 11:45:31.615051 Save RF Kill Switch Status[0m...
10943 11:45:31.621672 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10944 11:45:31.639117 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10945 11:45:31.697710 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10946 11:45:31.720815 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10947 11:45:31.734182 [[0;32m OK [<4>[ 18.982374] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10948 11:45:31.740826 0m] Reached target [0;1;39mLogin Prompts[0m.
10949 11:45:31.758226 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10950 11:45:31.777974 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10951 11:45:31.793202 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10952 11:45:31.857600 <4>[ 19.104696] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10953 11:45:31.864536 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10954 11:45:31.893283 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10955 11:45:31.925561
10956 11:45:31.926123
10957 11:45:31.928654 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10958 11:45:31.929166
10959 11:45:31.931963 debian-bullseye-arm64 login: root (automatic login)
10960 11:45:31.932433
10961 11:45:31.932799
10962 11:45:31.949121 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Thu Jun 15 11:29:51 UTC 2023 aarch64
10963 11:45:31.949701
10964 11:45:31.955620 The programs included with the Debian GNU/Linux system are free software;
10965 11:45:31.962387 the exact distribution terms for each program are described in the
10966 11:45:31.965642 individual files in /usr/share/doc/*/copyright.
10967 11:45:31.966207
10968 11:45:31.978571 Debian GNU/Linux com<4>[ 19.225260] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 11:45:31.981864 es with ABSOLUTELY NO WARRANTY, to the extent
10970 11:45:31.985505 permitted by applicable law.
10971 11:45:31.986812 Matched prompt #10: / #
10973 11:45:31.987929 Setting prompt string to ['/ #']
10974 11:45:31.988414 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10976 11:45:31.989540 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10977 11:45:31.990043 start: 2.2.6 expect-shell-connection (timeout 00:03:28) [common]
10978 11:45:31.990454 Setting prompt string to ['/ #']
10979 11:45:31.990800 Forcing a shell prompt, looking for ['/ #']
10981 11:45:32.041679 / #
10982 11:45:32.042354 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10983 11:45:32.042837 Waiting using forced prompt support (timeout 00:02:30)
10984 11:45:32.047798
10985 11:45:32.048737 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10986 11:45:32.049333 start: 2.2.7 export-device-env (timeout 00:03:28) [common]
10987 11:45:32.049856 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10988 11:45:32.050408 end: 2.2 depthcharge-retry (duration 00:01:32) [common]
10989 11:45:32.050904 end: 2 depthcharge-action (duration 00:01:32) [common]
10990 11:45:32.051395 start: 3 lava-test-retry (timeout 00:07:52) [common]
10991 11:45:32.051865 start: 3.1 lava-test-shell (timeout 00:07:52) [common]
10992 11:45:32.052269 Using namespace: common
10994 11:45:32.153451 / # #
10995 11:45:32.154159 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10996 11:45:32.154821 <4>[ 19.344383] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10997 11:45:32.159664 #
10998 11:45:32.160543 Using /lava-10742243
11000 11:45:32.261906 / # export SHELL=/bin/sh
11001 11:45:32.262711 <4>[ 19.464173] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11002 11:45:32.264011 export SHELL=/bin/sh<6>[ 19.514545] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11003 11:45:32.305527 <6>[ 19.522472] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11004 11:45:32.306101
11006 11:45:32.407603 / # . /lava-10742243/environment
11007 11:45:32.408384 <3>[ 19.578547] mt7921e 0000:01:00.0: hardware init failed
11008 11:45:32.414360 . /lava-10742243/environment
11010 11:45:32.516392 / # /lava-10742243/bin/lava-test-runner /lava-10742243/0
11011 11:45:32.517100 Test shell timeout: 10s (minimum of the action and connection timeout)
11012 11:45:32.522551 /lava-10742243/bin/lava-test-runner /lava-10742243/0
11013 11:45:32.544943 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11014 11:45:32.551285 + cd /lava-10742243/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11015 11:45:32.551858 + cat uuid
11016 11:45:32.554869 + UUID=10742243_1.5.2.3.1
11017 11:45:32.555435 + set +x
11018 11:45:32.561136 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10742243_1.5.2.3.1>
11019 11:45:32.562000 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10742243_1.5.2.3.1
11020 11:45:32.562412 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10742243_1.5.2.3.1)
11021 11:45:32.562868 Skipping test definition patterns.
11022 11:45:32.564369 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11023 11:45:32.571321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11024 11:45:32.572149 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11026 11:45:32.577579 d<4>[ 19.828573] use of bytesused == 0 is deprecated and will be removed in the future,
11027 11:45:32.584119 evice: /dev/vide<4>[ 19.837088] use the actual size instead.
11028 11:45:32.584686 o2
11029 11:45:32.590541 <4>[ 19.844085] ------------[ cut here ]------------
11030 11:45:32.597319 <4>[ 19.849037] get_vaddr_frames() cannot follow VM_IO mapping
11031 11:45:32.607189 <4>[ 19.849244] WARNING: CPU: 0 PID: 311 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11032 11:45:32.657127 <4>[ 19.867370] Modules linked in: btusb btintel mt7921e btmtk mt7921_common btrtl mt76_connac_lib btbcm mt76 mac80211 libarc4 mtk_vcodec_enc mtk_vcodec_common mtk_vpu uvcvideo v4l2_mem2mem r8153_ecm videobuf2_dma_contig videobuf2_vmalloc videobuf2_memops bluetooth cdc_ether cfg80211 ecdh_generic videobuf2_v4l2 videobuf2_common usbnet ecc cros_ec_rpmsg videodev rfkill r8152 crct10dif_ce mc elants_i2c sbs_battery elan_i2c hid_google_hammer cros_ec_typec cros_ec_chardev pcie_mediatek_gen3 hid_vivaldi_common mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11033 11:45:32.663772 <4>[ 19.916754] CPU: 0 PID: 311 Comm: v4l2-compliance Not tainted 6.1.31 #1
11034 11:45:32.669667 <4>[ 19.923619] Hardware name: Google Spherion (rev0 - 3) (DT)
11035 11:45:32.676857 <4>[ 19.929353] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11036 11:45:32.683350 <4>[ 19.936564] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11037 11:45:32.689675 <4>[ 19.942655] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11038 11:45:32.693030 <4>[ 19.948745] sp : ffff80000914b850
11039 11:45:32.699685 <4>[ 19.952309] x29: ffff80000914b850 x28: ffffa23edee7a000 x27: ffffa23edee76238
11040 11:45:32.709712 <4>[ 19.959697] x26: 0000000000000000 x25: ffffa23f46a9d1f8 x24: ffff21764ead1298
11041 11:45:32.716420 <4>[ 19.967084] x23: ffff2176408cb400 x22: ffff217640d48010 x21: 0000000000000000
11042 11:45:32.722887 <4>[ 19.974470] x20: 00000000fffffff2 x19: ffff21764e37a680 x18: fffffffffffe96b8
11043 11:45:32.729452 <4>[ 19.981857] x17: 0000000000000000 x16: ffffa23f44a8bb60 x15: 0000000000000038
11044 11:45:32.739383 <4>[ 19.989244] x14: ffffa23f473834a8 x13: 0000000000000648 x12: 0000000000000218
11045 11:45:32.746040 <4>[ 19.996630] x11: fffffffffffe96b8 x10: fffffffffffe9680 x9 : 00000000fffff218
11046 11:45:32.752917 <4>[ 20.004017] x8 : ffffa23f473834a8 x7 : ffffa23f473db4a8 x6 : 0000000000001920
11047 11:45:32.759437 <4>[ 20.011404] x5 : ffff21777ef14a18 x4 : 00000000fffff218 x3 : ffff7f3838251000
11048 11:45:32.766031 <4>[ 20.018791] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff2176497f0ec0
11049 11:45:32.769398 <4>[ 20.026178] Call trace:
11050 11:45:32.775801 <4>[ 20.028875] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11051 11:45:32.782264 <4>[ 20.034618] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11052 11:45:32.788939 <4>[ 20.040619] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11053 11:45:32.795335 <4>[ 20.046970] __prepare_userptr+0x280/0x410 [videobuf2_common]
11054 11:45:32.798784 <4>[ 20.052973] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11055 11:45:32.805125 <4>[ 20.058630] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11056 11:45:32.811741 <4>[ 20.064808] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11057 11:45:32.818826 <4>[ 20.070310] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11058 11:45:32.821675 <4>[ 20.076106] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11059 11:45:32.828560 <4>[ 20.082371] v4l_prepare_buf+0x48/0x60 [videodev]
11060 11:45:32.835247 <4>[ 20.087424] __video_do_ioctl+0x184/0x3d0 [videodev]
11061 11:45:32.838733 <4>[ 20.092669] video_usercopy+0x358/0x680 [videodev]
11062 11:45:32.845497 <4>[ 20.097739] video_ioctl2+0x18/0x30 [videodev]
11063 11:45:32.848537 <4>[ 20.102463] v4l2_ioctl+0x40/0x60 [videodev]
11064 11:45:32.851702 <4>[ 20.107013] __arm64_sys_ioctl+0xa8/0xf0
11065 11:45:32.855248 <4>[ 20.111194] invoke_syscall+0x48/0x114
11066 11:45:32.861943 <4>[ 20.115199] el0_svc_common.constprop.0+0x44/0xec
11067 11:45:32.865186 <4>[ 20.120155] do_el0_svc+0x2c/0xd0
11068 11:45:32.868439 <4>[ 20.123720] el0_svc+0x2c/0x84
11069 11:45:32.871631 <4>[ 20.127031] el0t_64_sync_handler+0xb8/0xc0
11070 11:45:32.874918 <4>[ 20.131464] el0t_64_sync+0x18c/0x190
11071 11:45:32.881181 <4>[ 20.135377] ---[ end trace 0000000000000000 ]---
11072 11:45:32.894814 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11073 11:45:32.905139 v4l2-compliance SHA: 57b6b2492f4a 2023-06-07 12:27:03
11074 11:45:32.911080
11075 11:45:32.924007 Compliance test for mtk-vcodec-enc device /dev/video2:
11076 11:45:32.930706
11077 11:45:32.941131 Driver Info:
11078 11:45:32.951244 Driver name : mtk-vcodec-enc
11079 11:45:32.964729 Card type : MT8192 video encoder
11080 11:45:32.975074 Bus info : platform:17020000.vcodec
11081 11:45:32.980800 Driver version : 6.1.31
11082 11:45:32.991074 Capabilities : 0x84204000
11083 11:45:33.000723 Video Memory-to-Memory Multiplanar
11084 11:45:33.009686 Streaming
11085 11:45:33.019657 Extended Pix Format
11086 11:45:33.030812 Device Capabilities
11087 11:45:33.040633 Device Caps : 0x04204000
11088 11:45:33.051818 Video Memory-to-Memory Multiplanar
11089 11:45:33.061460 Streaming
11090 11:45:33.072217 Extended Pix Format
11091 11:45:33.082061 Detected Stateful Encoder
11092 11:45:33.091930
11093 11:45:33.102178 Required ioctls:
11094 11:45:33.116670 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11095 11:45:33.117233 test VIDIOC_QUERYCAP: OK
11096 11:45:33.117887 Received signal: <TESTSET> START Required-ioctls
11097 11:45:33.118253 Starting test_set Required-ioctls
11098 11:45:33.140011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11099 11:45:33.140794 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11101 11:45:33.143463 test invalid ioctls: OK
11102 11:45:33.163189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11103 11:45:33.163749
11104 11:45:33.164376 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11106 11:45:33.172513 Allow for multiple opens:
11107 11:45:33.179549 <LAVA_SIGNAL_TESTSET STOP>
11108 11:45:33.180223 Received signal: <TESTSET> STOP
11109 11:45:33.180623 Closing test_set Required-ioctls
11110 11:45:33.189167 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11111 11:45:33.189840 Received signal: <TESTSET> START Allow-for-multiple-opens
11112 11:45:33.190195 Starting test_set Allow-for-multiple-opens
11113 11:45:33.192345 test second /dev/video2 open: OK
11114 11:45:33.214085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11115 11:45:33.214766 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11117 11:45:33.217208 test VIDIOC_QUERYCAP: OK
11118 11:45:33.238147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11119 11:45:33.238826 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11121 11:45:33.241195 test VIDIOC_G/S_PRIORITY: OK
11122 11:45:33.262261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11123 11:45:33.262938 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11125 11:45:33.265635 test for unlimited opens: OK
11126 11:45:33.286583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11127 11:45:33.287273
11128 11:45:33.288092 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11130 11:45:33.296284 Debug ioctls:
11131 11:45:33.303075 <LAVA_SIGNAL_TESTSET STOP>
11132 11:45:33.303941 Received signal: <TESTSET> STOP
11133 11:45:33.304539 Closing test_set Allow-for-multiple-opens
11134 11:45:33.312046 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11135 11:45:33.312943 Received signal: <TESTSET> START Debug-ioctls
11136 11:45:33.313401 Starting test_set Debug-ioctls
11137 11:45:33.315288 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11138 11:45:33.335326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11139 11:45:33.336268 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11141 11:45:33.341840 test VIDIOC_LOG_STATUS: OK (Not Supported)
11142 11:45:33.359135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11143 11:45:33.359619
11144 11:45:33.360303 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11146 11:45:33.368048 Input ioctls:
11147 11:45:33.375288 <LAVA_SIGNAL_TESTSET STOP>
11148 11:45:33.376089 Received signal: <TESTSET> STOP
11149 11:45:33.376731 Closing test_set Debug-ioctls
11150 11:45:33.384258 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11151 11:45:33.385009 Received signal: <TESTSET> START Input-ioctls
11152 11:45:33.385428 Starting test_set Input-ioctls
11153 11:45:33.387367 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11154 11:45:33.411552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11155 11:45:33.412252 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11157 11:45:33.415079 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11158 11:45:33.431776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11159 11:45:33.432435 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11161 11:45:33.438166 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11162 11:45:33.455624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11163 11:45:33.456359 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11165 11:45:33.462292 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11166 11:45:33.478982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11167 11:45:33.479846 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11169 11:45:33.482334 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11170 11:45:33.502820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11171 11:45:33.503485 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11173 11:45:33.506006 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11174 11:45:33.526488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11175 11:45:33.527383 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11177 11:45:33.529519 Inputs: 0 Audio Inputs: 0 Tuners: 0
11178 11:45:33.536274
11179 11:45:33.553118 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11180 11:45:33.574082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11181 11:45:33.574988 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11183 11:45:33.580551 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11184 11:45:33.602631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11185 11:45:33.603296 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11187 11:45:33.608959 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11188 11:45:33.626086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11189 11:45:33.626900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11191 11:45:33.632628 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11192 11:45:33.648344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11193 11:45:33.649076 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11195 11:45:33.654549 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11196 11:45:33.670904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11197 11:45:33.671328
11198 11:45:33.671924 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11200 11:45:33.686440 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11201 11:45:33.706664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11202 11:45:33.707345 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11204 11:45:33.712932 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11205 11:45:33.734860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11206 11:45:33.735683 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11208 11:45:33.737945 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11209 11:45:33.755349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11210 11:45:33.756110 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11212 11:45:33.758535 test VIDIOC_G/S_EDID: OK (Not Supported)
11213 11:45:33.778941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11214 11:45:33.779497
11215 11:45:33.780234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11217 11:45:33.788398 Control ioctls:
11218 11:45:33.795934 <LAVA_SIGNAL_TESTSET STOP>
11219 11:45:33.796750 Received signal: <TESTSET> STOP
11220 11:45:33.797289 Closing test_set Input-ioctls
11221 11:45:33.804573 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11222 11:45:33.805380 Received signal: <TESTSET> START Control-ioctls
11223 11:45:33.805876 Starting test_set Control-ioctls
11224 11:45:33.808098 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11225 11:45:33.832428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11226 11:45:33.833008 test VIDIOC_QUERYCTRL: OK
11227 11:45:33.833604 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11229 11:45:33.854149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11230 11:45:33.854881 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11232 11:45:33.857322 test VIDIOC_G/S_CTRL: OK
11233 11:45:33.878310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11234 11:45:33.879021 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11236 11:45:33.881670 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11237 11:45:33.901987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11238 11:45:33.902637 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11240 11:45:33.912249 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11241 11:45:33.915389 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11242 11:45:33.937579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11243 11:45:33.938255 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11245 11:45:33.941049 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11246 11:45:33.958194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11247 11:45:33.958869 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11249 11:45:33.961494 Standard Controls: 16 Private Controls: 0
11250 11:45:33.967923
11251 11:45:33.978237 Format ioctls:
11252 11:45:33.983867 <LAVA_SIGNAL_TESTSET STOP>
11253 11:45:33.984147 Received signal: <TESTSET> STOP
11254 11:45:33.984244 Closing test_set Control-ioctls
11255 11:45:33.992800 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11256 11:45:33.993093 Received signal: <TESTSET> START Format-ioctls
11257 11:45:33.993191 Starting test_set Format-ioctls
11258 11:45:33.995803 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11259 11:45:34.020958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11260 11:45:34.021254 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11262 11:45:34.024149 test VIDIOC_G/S_PARM: OK
11263 11:45:34.041325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11264 11:45:34.041575 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11266 11:45:34.044439 test VIDIOC_G_FBUF: OK (Not Supported)
11267 11:45:34.065207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11268 11:45:34.065456 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11270 11:45:34.068497 test VIDIOC_G_FMT: OK
11271 11:45:34.089178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11272 11:45:34.089431 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11274 11:45:34.092585 test VIDIOC_TRY_FMT: OK
11275 11:45:34.113437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11276 11:45:34.113787 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11278 11:45:34.123783 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11279 11:45:34.123986 test VIDIOC_S_FMT: FAIL
11280 11:45:34.147272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11281 11:45:34.147770 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11283 11:45:34.150128 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11284 11:45:34.170941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11285 11:45:34.171767 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11287 11:45:34.174102 test Cropping: OK
11288 11:45:34.195020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11289 11:45:34.195852 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11291 11:45:34.197925 test Composing: OK (Not Supported)
11292 11:45:34.218176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11293 11:45:34.218981 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11295 11:45:34.221416 test Scaling: OK (Not Supported)
11296 11:45:34.241641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11297 11:45:34.242203
11298 11:45:34.242830 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11300 11:45:34.251587 Codec ioctls:
11301 11:45:34.258085 <LAVA_SIGNAL_TESTSET STOP>
11302 11:45:34.258914 Received signal: <TESTSET> STOP
11303 11:45:34.259295 Closing test_set Format-ioctls
11304 11:45:34.267242 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11305 11:45:34.268066 Received signal: <TESTSET> START Codec-ioctls
11306 11:45:34.268454 Starting test_set Codec-ioctls
11307 11:45:34.270301 test VIDIOC_(TRY_)ENCODER_CMD: OK
11308 11:45:34.291720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11309 11:45:34.292554 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11311 11:45:34.298007 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11312 11:45:34.314519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11313 11:45:34.315324 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11315 11:45:34.320969 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11316 11:45:34.340094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11317 11:45:34.340668
11318 11:45:34.341352 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11320 11:45:34.348706 Buffer ioctls:
11321 11:45:34.355421 <LAVA_SIGNAL_TESTSET STOP>
11322 11:45:34.356248 Received signal: <TESTSET> STOP
11323 11:45:34.356654 Closing test_set Codec-ioctls
11324 11:45:34.364105 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11325 11:45:34.364938 Received signal: <TESTSET> START Buffer-ioctls
11326 11:45:34.365362 Starting test_set Buffer-ioctls
11327 11:45:34.367184 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11328 11:45:34.391978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11329 11:45:34.392547 test VIDIOC_EXPBUF: OK
11330 11:45:34.393385 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11332 11:45:34.410979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11333 11:45:34.411790 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11335 11:45:34.414173 test Requests: OK (Not Supported)
11336 11:45:34.433724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11337 11:45:34.434278
11338 11:45:34.434899 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11340 11:45:34.444355 Test input 0:
11341 11:45:34.454098
11342 11:45:34.464169 Streaming ioctls:
11343 11:45:34.471009 <LAVA_SIGNAL_TESTSET STOP>
11344 11:45:34.471769 Received signal: <TESTSET> STOP
11345 11:45:34.472168 Closing test_set Buffer-ioctls
11346 11:45:34.480454 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11347 11:45:34.481372 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11348 11:45:34.481770 Starting test_set Streaming-ioctls_Test-input-0
11349 11:45:34.483899 test read/write: OK (Not Supported)
11350 11:45:34.503390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11351 11:45:34.504123 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11353 11:45:34.510086 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11354 11:45:34.520030 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11355 11:45:34.523166 test blocking wait: FAIL
11356 11:45:34.550371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11357 11:45:34.550630 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11359 11:45:34.559809 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11360 11:45:34.559892 test MMAP (select): FAIL
11361 11:45:34.586405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11362 11:45:34.586660 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11364 11:45:34.592766 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11365 11:45:34.596328 test MMAP (epoll): FAIL
11366 11:45:34.619349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11367 11:45:34.619608 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11369 11:45:34.629474 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11370 11:45:34.636003 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11371 11:45:34.640602 test USERPTR (select): FAIL
11372 11:45:34.670203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11373 11:45:34.671015 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11375 11:45:34.677238 test DMABUF: Cannot test, specify --expbuf-device
11376 11:45:34.677804
11377 11:45:34.696006 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11378 11:45:34.699095 <LAVA_TEST_RUNNER EXIT>
11379 11:45:34.699917 ok: lava_test_shell seems to have completed
11380 11:45:34.700335 Marking unfinished test run as failed
11382 11:45:34.705318 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11383 11:45:34.705958 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11384 11:45:34.706441 end: 3 lava-test-retry (duration 00:00:03) [common]
11385 11:45:34.706921 start: 4 finalize (timeout 00:07:49) [common]
11386 11:45:34.707403 start: 4.1 power-off (timeout 00:00:30) [common]
11387 11:45:34.708237 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11388 11:45:34.828109 >> Command sent successfully.
11389 11:45:34.832042 Returned 0 in 0 seconds
11390 11:45:34.933084 end: 4.1 power-off (duration 00:00:00) [common]
11392 11:45:34.934682 start: 4.2 read-feedback (timeout 00:07:49) [common]
11393 11:45:34.935960 Listened to connection for namespace 'common' for up to 1s
11394 11:45:35.936596 Finalising connection for namespace 'common'
11395 11:45:35.937245 Disconnecting from shell: Finalise
11396 11:45:35.937642 / #
11397 11:45:36.038297 end: 4.2 read-feedback (duration 00:00:01) [common]
11398 11:45:36.038447 end: 4 finalize (duration 00:00:01) [common]
11399 11:45:36.038558 Cleaning after the job
11400 11:45:36.038657 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/ramdisk
11401 11:45:36.042617 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/kernel
11402 11:45:36.048154 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/dtb
11403 11:45:36.048305 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10742243/tftp-deploy-me9zrnxy/modules
11404 11:45:36.053151 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10742243
11405 11:45:36.105237 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10742243
11406 11:45:36.105420 Job finished correctly